From 1e324d9eef6a0d4c471fdfb9354df9d484e6eae2 Mon Sep 17 00:00:00 2001 From: Fabien Poussin Date: Wed, 29 Mar 2017 17:51:59 +0200 Subject: [PATCH 01/74] Deleting old ChibiOS folders --- .gitmodules | 2 +- firmware/ChibiOS_16/community/.gitignore | 5 - firmware/ChibiOS_16/community/AUTHORS.txt | 21 - firmware/ChibiOS_16/community/README.md | 24 - firmware/ChibiOS_16/community/os/.keep | 0 firmware/ChibiOS_16/community/os/hal/hal.mk | 24 - .../community/os/hal/include/hal_community.h | 127 - .../community/os/hal/include/hal_crc.h | 158 - .../community/os/hal/include/hal_ee24xx.h | 64 - .../community/os/hal/include/hal_ee25xx.h | 63 - .../community/os/hal/include/hal_eeprom.h | 143 - .../community/os/hal/include/hal_eicu.h | 191 - .../community/os/hal/include/hal_nand.h | 138 - .../community/os/hal/include/hal_onewire.h | 367 - .../community/os/hal/include/hal_qei.h | 159 - .../community/os/hal/include/hal_rng.h | 136 - .../community/os/hal/include/hal_timcap.h | 206 - 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firmware/ChibiOS_16/os/hal/include/i2s.h | 167 - firmware/ChibiOS_16/os/hal/include/icu.h | 238 - firmware/ChibiOS_16/os/hal/include/mac.h | 202 - firmware/ChibiOS_16/os/hal/include/mii.h | 175 - firmware/ChibiOS_16/os/hal/include/mmc_spi.h | 195 - firmware/ChibiOS_16/os/hal/include/pal.h | 642 -- firmware/ChibiOS_16/os/hal/include/pwm.h | 308 - firmware/ChibiOS_16/os/hal/include/rtc.h | 144 - firmware/ChibiOS_16/os/hal/include/sdc.h | 195 - firmware/ChibiOS_16/os/hal/include/serial.h | 286 - .../ChibiOS_16/os/hal/include/serial_usb.h | 195 - firmware/ChibiOS_16/os/hal/include/spi.h | 291 - firmware/ChibiOS_16/os/hal/include/st.h | 97 - firmware/ChibiOS_16/os/hal/include/uart.h | 342 - firmware/ChibiOS_16/os/hal/include/usb.h | 634 -- firmware/ChibiOS_16/os/hal/include/usb_cdc.h | 136 - firmware/ChibiOS_16/os/hal/include/wdg.h | 89 - .../ChibiOS_16/os/hal/lib/streams/chprintf.c | 370 - .../ChibiOS_16/os/hal/lib/streams/chprintf.h | 49 - .../os/hal/lib/streams/memstreams.c | 113 - .../os/hal/lib/streams/memstreams.h | 95 - .../os/hal/lib/streams/nullstreams.c | 92 - .../os/hal/lib/streams/nullstreams.h | 86 - firmware/ChibiOS_16/os/hal/osal/nil/osal.c | 115 - firmware/ChibiOS_16/os/hal/osal/nil/osal.h | 920 -- firmware/ChibiOS_16/os/hal/osal/nil/osal.mk | 5 - .../os/hal/osal/os-less/ARMCMx/osal.c | 580 -- .../os/hal/osal/os-less/ARMCMx/osal.h | 769 -- .../os/hal/osal/os-less/ARMCMx/osal.mk | 5 - firmware/ChibiOS_16/os/hal/osal/rt/osal.c | 51 - firmware/ChibiOS_16/os/hal/osal/rt/osal.h | 941 -- firmware/ChibiOS_16/os/hal/osal/rt/osal.mk | 5 - .../os/hal/ports/STM32/LLD/ADCv1/adc_lld.c | 336 - .../os/hal/ports/STM32/LLD/ADCv1/adc_lld.h | 441 - .../os/hal/ports/STM32/LLD/ADCv1/notes.txt | 16 - .../os/hal/ports/STM32/LLD/ADCv2/adc_lld.c | 428 - .../os/hal/ports/STM32/LLD/ADCv2/adc_lld.h | 570 - .../os/hal/ports/STM32/LLD/ADCv2/notes.txt | 13 - .../os/hal/ports/STM32/LLD/ADCv3/adc_lld.c | 959 -- .../os/hal/ports/STM32/LLD/ADCv3/adc_lld.h | 890 -- .../os/hal/ports/STM32/LLD/ADCv3/notes.txt | 19 - .../os/hal/ports/STM32/LLD/CANv1/can_lld.c | 848 -- .../os/hal/ports/STM32/LLD/CANv1/can_lld.h | 379 - .../os/hal/ports/STM32/LLD/DACv1/dac_lld.c | 536 - .../os/hal/ports/STM32/LLD/DACv1/dac_lld.h | 469 - .../os/hal/ports/STM32/LLD/DMAv1/notes.txt | 25 - .../os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c | 557 - .../os/hal/ports/STM32/LLD/DMAv1/stm32_dma.h | 480 - .../os/hal/ports/STM32/LLD/DMAv2/notes.txt | 20 - .../os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c | 522 - .../os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h | 676 -- .../os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c | 239 - .../os/hal/ports/STM32/LLD/EXTIv1/ext_lld.h | 155 - .../os/hal/ports/STM32/LLD/EXTIv1/notes.txt | 23 - .../os/hal/ports/STM32/LLD/GPIOv1/pal_lld.c | 183 - .../os/hal/ports/STM32/LLD/GPIOv1/pal_lld.h | 376 - .../os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c | 212 - .../os/hal/ports/STM32/LLD/GPIOv2/pal_lld.h | 559 - .../os/hal/ports/STM32/LLD/GPIOv3/pal_lld.c | 199 - .../os/hal/ports/STM32/LLD/GPIOv3/pal_lld.h | 571 - .../os/hal/ports/STM32/LLD/I2Cv1/i2c_lld.c | 855 -- .../os/hal/ports/STM32/LLD/I2Cv1/i2c_lld.h | 513 - .../os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.c | 1156 --- .../os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.h | 502 - .../os/hal/ports/STM32/LLD/MACv1/mac_lld.c | 757 -- .../os/hal/ports/STM32/LLD/MACv1/mac_lld.h | 359 - .../os/hal/ports/STM32/LLD/OTGv1/stm32_otg.h | 933 -- .../os/hal/ports/STM32/LLD/OTGv1/usb_lld.c | 1356 --- .../os/hal/ports/STM32/LLD/OTGv1/usb_lld.h | 595 -- .../os/hal/ports/STM32/LLD/RTCv1/rtc_lld.c | 443 - .../os/hal/ports/STM32/LLD/RTCv1/rtc_lld.h | 198 - .../os/hal/ports/STM32/LLD/RTCv2/rtc_lld.c | 555 - .../os/hal/ports/STM32/LLD/RTCv2/rtc_lld.h | 237 - .../os/hal/ports/STM32/LLD/SDIOv1/sdc_lld.c | 872 -- .../os/hal/ports/STM32/LLD/SDIOv1/sdc_lld.h | 350 - .../os/hal/ports/STM32/LLD/SDMMCv1/sdc_lld.c | 884 -- .../os/hal/ports/STM32/LLD/SDMMCv1/sdc_lld.h | 275 - .../os/hal/ports/STM32/LLD/SPIv1/i2s_lld.c | 577 -- .../os/hal/ports/STM32/LLD/SPIv1/i2s_lld.h | 432 - .../os/hal/ports/STM32/LLD/SPIv1/spi_lld.c | 635 -- .../os/hal/ports/STM32/LLD/SPIv1/spi_lld.h | 543 - .../os/hal/ports/STM32/LLD/SPIv2/i2s_lld.c | 577 -- .../os/hal/ports/STM32/LLD/SPIv2/i2s_lld.h | 432 - .../os/hal/ports/STM32/LLD/SPIv2/spi_lld.c | 652 -- .../os/hal/ports/STM32/LLD/SPIv2/spi_lld.h | 547 - .../os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c | 892 -- .../os/hal/ports/STM32/LLD/TIMv1/gpt_lld.h | 641 -- .../os/hal/ports/STM32/LLD/TIMv1/icu_lld.c | 805 -- .../os/hal/ports/STM32/LLD/TIMv1/icu_lld.h | 487 - .../os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c | 858 -- .../os/hal/ports/STM32/LLD/TIMv1/pwm_lld.h | 550 - .../os/hal/ports/STM32/LLD/TIMv1/st_lld.c | 308 - .../os/hal/ports/STM32/LLD/TIMv1/st_lld.h | 210 - .../os/hal/ports/STM32/LLD/TIMv1/stm32_tim.h | 450 - .../ports/STM32/LLD/TIMv1/tim_irq_mapping.txt | 14 - .../hal/ports/STM32/LLD/USARTv1/serial_lld.c | 631 -- .../hal/ports/STM32/LLD/USARTv1/serial_lld.h | 360 - .../os/hal/ports/STM32/LLD/USARTv1/uart_lld.c | 811 -- .../os/hal/ports/STM32/LLD/USARTv1/uart_lld.h | 623 -- .../hal/ports/STM32/LLD/USARTv2/serial_lld.c | 764 -- .../hal/ports/STM32/LLD/USARTv2/serial_lld.h | 399 - .../os/hal/ports/STM32/LLD/USARTv2/uart_lld.c | 931 -- .../os/hal/ports/STM32/LLD/USARTv2/uart_lld.h | 734 -- .../os/hal/ports/STM32/LLD/USBv1/stm32_usb.h | 266 - .../os/hal/ports/STM32/LLD/USBv1/usb_lld.c | 863 -- .../os/hal/ports/STM32/LLD/USBv1/usb_lld.h | 486 - .../os/hal/ports/STM32/LLD/xWDGv1/wdg_lld.c | 140 - .../os/hal/ports/STM32/LLD/xWDGv1/wdg_lld.h | 183 - .../hal/ports/STM32/STM32F4xx/ext_lld_isr.c | 407 - .../hal/ports/STM32/STM32F4xx/ext_lld_isr.h | 170 - .../os/hal/ports/STM32/STM32F4xx/hal_lld.c | 278 - .../os/hal/ports/STM32/STM32F4xx/hal_lld.h | 1552 --- .../os/hal/ports/STM32/STM32F4xx/platform.mk | 107 - .../os/hal/ports/STM32/STM32F4xx/stm32_isr.h | 205 - .../os/hal/ports/STM32/STM32F4xx/stm32_rcc.h | 1614 --- .../ports/STM32/STM32F4xx/stm32_registry.h | 1686 --- .../os/hal/ports/common/ARMCMx/mpu.h | 208 - .../os/hal/ports/common/ARMCMx/nvic.c | 114 - .../os/hal/ports/common/ARMCMx/nvic.h | 88 - .../os/hal/ports/simulator/console.c | 134 - .../os/hal/ports/simulator/console.h | 62 - .../os/hal/ports/simulator/pal_lld.c | 94 - .../os/hal/ports/simulator/pal_lld.h | 206 - .../os/hal/ports/simulator/st_lld.c | 67 - .../os/hal/ports/simulator/st_lld.h | 141 - .../os/hal/ports/simulator/win32/hal_lld.c | 110 - .../os/hal/ports/simulator/win32/hal_lld.h | 67 - .../os/hal/ports/simulator/win32/platform.mk | 10 - .../os/hal/ports/simulator/win32/serial_lld.c | 282 - .../os/hal/ports/simulator/win32/serial_lld.h | 143 - firmware/ChibiOS_16/os/hal/src/adc.c | 321 - firmware/ChibiOS_16/os/hal/src/can.c | 361 - firmware/ChibiOS_16/os/hal/src/dac.c | 349 - firmware/ChibiOS_16/os/hal/src/ext.c | 202 - firmware/ChibiOS_16/os/hal/src/gpt.c | 262 - firmware/ChibiOS_16/os/hal/src/hal.c | 144 - firmware/ChibiOS_16/os/hal/src/hal_buffers.c | 867 -- firmware/ChibiOS_16/os/hal/src/hal_mmcsd.c | 331 - firmware/ChibiOS_16/os/hal/src/hal_queues.c | 417 - firmware/ChibiOS_16/os/hal/src/i2c.c | 283 - firmware/ChibiOS_16/os/hal/src/i2s.c | 155 - firmware/ChibiOS_16/os/hal/src/icu.c | 225 - firmware/ChibiOS_16/os/hal/src/mac.c | 268 - firmware/ChibiOS_16/os/hal/src/mmc_spi.c | 918 -- firmware/ChibiOS_16/os/hal/src/pal.c | 122 - firmware/ChibiOS_16/os/hal/src/pwm.c | 309 - firmware/ChibiOS_16/os/hal/src/rtc.c | 321 - firmware/ChibiOS_16/os/hal/src/sdc.c | 1005 -- firmware/ChibiOS_16/os/hal/src/serial.c | 289 - firmware/ChibiOS_16/os/hal/src/serial_usb.c | 501 - firmware/ChibiOS_16/os/hal/src/spi.c | 416 - firmware/ChibiOS_16/os/hal/src/st.c | 130 - firmware/ChibiOS_16/os/hal/src/uart.c | 515 - firmware/ChibiOS_16/os/hal/src/usb.c | 966 -- firmware/ChibiOS_16/os/hal/src/wdg.c | 120 - .../ChibiOS_16/os/hal/templates/adc_lld.c | 141 - .../ChibiOS_16/os/hal/templates/adc_lld.h | 211 - .../ChibiOS_16/os/hal/templates/can_lld.c | 242 - .../ChibiOS_16/os/hal/templates/can_lld.h | 228 - .../ChibiOS_16/os/hal/templates/dac_lld.c | 170 - .../ChibiOS_16/os/hal/templates/dac_lld.h | 211 - .../ChibiOS_16/os/hal/templates/ext_lld.c | 147 - .../ChibiOS_16/os/hal/templates/ext_lld.h | 150 - .../ChibiOS_16/os/hal/templates/gpt_lld.c | 163 - .../ChibiOS_16/os/hal/templates/gpt_lld.h | 154 - .../ChibiOS_16/os/hal/templates/hal_lld.c | 60 - .../ChibiOS_16/os/hal/templates/hal_lld.h | 82 - .../ChibiOS_16/os/hal/templates/halconf.h | 429 - .../ChibiOS_16/os/hal/templates/i2c_lld.c | 187 - .../ChibiOS_16/os/hal/templates/i2c_lld.h | 152 - .../ChibiOS_16/os/hal/templates/i2s_lld.c | 136 - .../ChibiOS_16/os/hal/templates/i2s_lld.h | 143 - .../ChibiOS_16/os/hal/templates/icu_lld.c | 185 - .../ChibiOS_16/os/hal/templates/icu_lld.h | 193 - .../ChibiOS_16/os/hal/templates/mac_lld.c | 313 - .../ChibiOS_16/os/hal/templates/mac_lld.h | 181 - .../ChibiOS_16/os/hal/templates/mcuconf.h | 30 - .../ChibiOS_16/os/hal/templates/osal/osal.c | 411 - .../ChibiOS_16/os/hal/templates/osal/osal.h | 648 -- .../ChibiOS_16/os/hal/templates/osal/osal.mk | 5 - .../ChibiOS_16/os/hal/templates/pal_lld.c | 90 - .../ChibiOS_16/os/hal/templates/pal_lld.h | 422 - .../ChibiOS_16/os/hal/templates/platform.mk | 20 - .../ChibiOS_16/os/hal/templates/pwm_lld.c | 220 - .../ChibiOS_16/os/hal/templates/pwm_lld.h | 215 - .../ChibiOS_16/os/hal/templates/rtc_lld.c | 149 - .../ChibiOS_16/os/hal/templates/rtc_lld.h | 182 - .../ChibiOS_16/os/hal/templates/sdc_lld.c | 328 - .../ChibiOS_16/os/hal/templates/sdc_lld.h | 184 - .../ChibiOS_16/os/hal/templates/serial_lld.c | 127 - .../ChibiOS_16/os/hal/templates/serial_lld.h | 119 - .../ChibiOS_16/os/hal/templates/spi_lld.c | 247 - .../ChibiOS_16/os/hal/templates/spi_lld.h | 152 - firmware/ChibiOS_16/os/hal/templates/st_lld.c | 67 - firmware/ChibiOS_16/os/hal/templates/st_lld.h | 141 - .../ChibiOS_16/os/hal/templates/uart_lld.c | 191 - .../ChibiOS_16/os/hal/templates/uart_lld.h | 202 - .../ChibiOS_16/os/hal/templates/usb_lld.c | 390 - .../ChibiOS_16/os/hal/templates/usb_lld.h | 376 - .../ChibiOS_16/os/hal/templates/wdg_lld.c | 101 - .../ChibiOS_16/os/hal/templates/wdg_lld.h | 113 - firmware/ChibiOS_16/os/nil/dox/nil.dox | 50 - firmware/ChibiOS_16/os/nil/include/nil.h | 1003 -- firmware/ChibiOS_16/os/nil/nil.mk | 5 - .../ports/ARMCMx/compilers/GCC/mk/port_v6m.mk | 8 - .../ports/ARMCMx/compilers/GCC/mk/port_v7m.mk | 8 - .../ARMCMx/compilers/GCC/nilcoreasm_v6m.s | 124 - .../ARMCMx/compilers/GCC/nilcoreasm_v7m.s | 130 - .../nil/ports/ARMCMx/compilers/GCC/niltypes.h | 96 - .../ChibiOS_16/os/nil/ports/ARMCMx/nilcore.c | 54 - .../ChibiOS_16/os/nil/ports/ARMCMx/nilcore.h | 204 - .../os/nil/ports/ARMCMx/nilcore_timer.h | 124 - .../os/nil/ports/ARMCMx/nilcore_v6m.c | 147 - .../os/nil/ports/ARMCMx/nilcore_v6m.h | 406 - .../os/nil/ports/ARMCMx/nilcore_v7m.c | 165 - .../os/nil/ports/ARMCMx/nilcore_v7m.h | 576 -- .../os/nil/ports/AVR/compilers/GCC/mk/port.mk | 7 - .../os/nil/ports/AVR/compilers/GCC/niltypes.h | 96 - .../ChibiOS_16/os/nil/ports/AVR/nilcore.c | 137 - .../ChibiOS_16/os/nil/ports/AVR/nilcore.h | 418 - .../os/nil/ports/AVR/nilcore_timer.h | 124 - .../os/nil/ports/e200/compilers/GCC/ivor.s | 234 - .../e200/compilers/GCC/mk/port_spc560bcxx.mk | 14 - .../e200/compilers/GCC/mk/port_spc560bxx.mk | 14 - .../e200/compilers/GCC/mk/port_spc560dxx.mk | 14 - .../e200/compilers/GCC/mk/port_spc560pxx.mk | 14 - .../e200/compilers/GCC/mk/port_spc563mxx.mk | 14 - .../e200/compilers/GCC/mk/port_spc564axx.mk | 14 - .../e200/compilers/GCC/mk/port_spc56ecxx.mk | 14 - .../e200/compilers/GCC/mk/port_spc56elxx.mk | 14 - .../e200/compilers/GCC/mk/port_spc57emxx.mk | 14 - .../nil/ports/e200/compilers/GCC/niltypes.h | 96 - .../ChibiOS_16/os/nil/ports/e200/nilcore.c | 107 - .../ChibiOS_16/os/nil/ports/e200/nilcore.h | 555 - firmware/ChibiOS_16/os/nil/src/nil.c | 832 -- .../ChibiOS_16/os/nil/templates/nilconf.h | 179 - .../ChibiOS_16/os/nil/templates/nilcore.c | 54 - .../ChibiOS_16/os/nil/templates/nilcore.h | 379 - .../os/nil/templates/nilcore_timer.h | 120 - .../ChibiOS_16/os/nil/templates/niltypes.h | 96 - firmware/ChibiOS_16/os/readme.txt | 29 - firmware/ChibiOS_16/os/rt/dox/rt.dox | 175 - firmware/ChibiOS_16/os/rt/include/ch.h | 101 - firmware/ChibiOS_16/os/rt/include/chbsem.h | 311 - firmware/ChibiOS_16/os/rt/include/chcond.h | 116 - .../ChibiOS_16/os/rt/include/chcustomer.h | 71 - firmware/ChibiOS_16/os/rt/include/chdebug.h | 239 - firmware/ChibiOS_16/os/rt/include/chdynamic.h | 96 - firmware/ChibiOS_16/os/rt/include/chevents.h | 263 - firmware/ChibiOS_16/os/rt/include/chheap.h | 118 - firmware/ChibiOS_16/os/rt/include/chlicense.h | 245 - firmware/ChibiOS_16/os/rt/include/chmboxes.h | 207 - firmware/ChibiOS_16/os/rt/include/chmemcore.h | 111 - .../ChibiOS_16/os/rt/include/chmempools.h | 168 - firmware/ChibiOS_16/os/rt/include/chmsg.h | 122 - firmware/ChibiOS_16/os/rt/include/chmtx.h | 152 - firmware/ChibiOS_16/os/rt/include/chqueues.h | 437 - .../ChibiOS_16/os/rt/include/chregistry.h | 184 - firmware/ChibiOS_16/os/rt/include/chschd.h | 781 -- firmware/ChibiOS_16/os/rt/include/chsem.h | 160 - firmware/ChibiOS_16/os/rt/include/chstats.h | 105 - firmware/ChibiOS_16/os/rt/include/chstreams.h | 146 - firmware/ChibiOS_16/os/rt/include/chsys.h | 462 - .../ChibiOS_16/os/rt/include/chsystypes.h | 136 - firmware/ChibiOS_16/os/rt/include/chthreads.h | 326 - firmware/ChibiOS_16/os/rt/include/chtm.h | 109 - firmware/ChibiOS_16/os/rt/include/chvt.h | 591 -- firmware/ChibiOS_16/os/rt/ports/ARM/chcore.c | 54 - firmware/ChibiOS_16/os/rt/ports/ARM/chcore.h | 531 - .../ChibiOS_16/os/rt/ports/ARM/chcore_timer.h | 124 - .../os/rt/ports/ARM/compilers/GCC/chcoreasm.s | 278 - .../os/rt/ports/ARM/compilers/GCC/chtypes.h | 98 - .../ARM/compilers/GCC/mk/port_generic.mk | 7 - .../ChibiOS_16/os/rt/ports/ARMCMx/chcore.c | 54 - .../ChibiOS_16/os/rt/ports/ARMCMx/chcore.h | 214 - .../os/rt/ports/ARMCMx/chcore_timer.h | 124 - .../os/rt/ports/ARMCMx/chcore_v6m.c | 147 - .../os/rt/ports/ARMCMx/chcore_v6m.h | 407 - .../os/rt/ports/ARMCMx/chcore_v7m.c | 168 - .../os/rt/ports/ARMCMx/chcore_v7m.h | 577 -- .../os/rt/ports/ARMCMx/cmsis_os/cmsis_os.c | 554 - .../os/rt/ports/ARMCMx/cmsis_os/cmsis_os.h | 520 - .../os/rt/ports/ARMCMx/cmsis_os/cmsis_os.mk | 4 - .../ARMCMx/compilers/GCC/chcoreasm_v6m.s | 142 - .../ARMCMx/compilers/GCC/chcoreasm_v7m.s | 148 - .../rt/ports/ARMCMx/compilers/GCC/chtypes.h | 98 - .../ports/ARMCMx/compilers/GCC/mk/port_v6m.mk | 8 - .../ports/ARMCMx/compilers/GCC/mk/port_v7m.mk | 8 - .../ARMCMx/compilers/IAR/chcoreasm_v6m.s | 142 - .../ARMCMx/compilers/IAR/chcoreasm_v7m.s | 150 - .../rt/ports/ARMCMx/compilers/IAR/chtypes.h | 98 - .../ARMCMx/compilers/RVCT/chcoreasm_v6m.s | 139 - .../ARMCMx/compilers/RVCT/chcoreasm_v7m.s | 148 - .../rt/ports/ARMCMx/compilers/RVCT/chtypes.h | 98 - firmware/ChibiOS_16/os/rt/ports/AVR/chcore.c | 132 - firmware/ChibiOS_16/os/rt/ports/AVR/chcore.h | 390 - .../ChibiOS_16/os/rt/ports/AVR/chcore_timer.h | 124 - .../os/rt/ports/AVR/compilers/GCC/chtypes.h | 91 - .../os/rt/ports/AVR/compilers/GCC/mk/port.mk | 7 - .../ChibiOS_16/os/rt/ports/SIMIA32/chcore.c | 119 - .../ChibiOS_16/os/rt/ports/SIMIA32/chcore.h | 381 - .../rt/ports/SIMIA32/compilers/GCC/chtypes.h | 110 - .../os/rt/ports/SIMIA32/compilers/GCC/port.mk | 7 - firmware/ChibiOS_16/os/rt/ports/e200/chcore.c | 54 - firmware/ChibiOS_16/os/rt/ports/e200/chcore.h | 599 -- .../os/rt/ports/e200/compilers/CW/chcoreasm.s | 105 - .../os/rt/ports/e200/compilers/CW/chtypes.h | 93 - .../os/rt/ports/e200/compilers/CW/ivor.s | 204 - .../rt/ports/e200/compilers/GCC/chcoreasm.s | 97 - .../os/rt/ports/e200/compilers/GCC/chtypes.h | 93 - .../os/rt/ports/e200/compilers/GCC/ivor.s | 258 - .../os/rt/ports/e200/compilers/GCC/mk/port.mk | 8 - firmware/ChibiOS_16/os/rt/rt.mk | 76 - firmware/ChibiOS_16/os/rt/src/chcond.c | 323 - firmware/ChibiOS_16/os/rt/src/chdebug.c | 290 - firmware/ChibiOS_16/os/rt/src/chdynamic.c | 240 - firmware/ChibiOS_16/os/rt/src/chevents.c | 587 -- firmware/ChibiOS_16/os/rt/src/chheap.c | 294 - firmware/ChibiOS_16/os/rt/src/chmboxes.c | 434 - firmware/ChibiOS_16/os/rt/src/chmemcore.c | 163 - firmware/ChibiOS_16/os/rt/src/chmempools.c | 202 - firmware/ChibiOS_16/os/rt/src/chmsg.c | 154 - firmware/ChibiOS_16/os/rt/src/chmtx.c | 518 - firmware/ChibiOS_16/os/rt/src/chqueues.c | 446 - firmware/ChibiOS_16/os/rt/src/chregistry.c | 181 - firmware/ChibiOS_16/os/rt/src/chschd.c | 542 - firmware/ChibiOS_16/os/rt/src/chsem.c | 411 - firmware/ChibiOS_16/os/rt/src/chstats.c | 126 - firmware/ChibiOS_16/os/rt/src/chsys.c | 426 - firmware/ChibiOS_16/os/rt/src/chthreads.c | 685 -- firmware/ChibiOS_16/os/rt/src/chtm.c | 156 - firmware/ChibiOS_16/os/rt/src/chvt.c | 270 - firmware/ChibiOS_16/os/rt/templates/chconf.h | 498 - firmware/ChibiOS_16/os/rt/templates/chcore.c | 79 - firmware/ChibiOS_16/os/rt/templates/chcore.h | 411 - firmware/ChibiOS_16/os/rt/templates/chtypes.h | 102 - .../ChibiOS_16/os/rt/templates/meta/module.c | 80 - .../ChibiOS_16/os/rt/templates/meta/module.h | 76 - .../ChibiOS_16/os/various/cpp_wrappers/ch.cpp | 704 -- .../ChibiOS_16/os/various/cpp_wrappers/ch.hpp | 2466 ----- .../os/various/cpp_wrappers/chcpp.mk | 5 - .../os/various/cpp_wrappers/syscalls_cpp.cpp | 41 - .../os/various/cpp_wrappers/syscalls_cpp.hpp | 13 - .../os/various/devices_lib/accel/lis302dl.c | 118 - .../os/various/devices_lib/accel/lis302dl.dox | 26 - .../os/various/devices_lib/accel/lis302dl.h | 93 - .../os/various/devices_lib/lcd/lcd3310.c | 310 - .../os/various/devices_lib/lcd/lcd3310.h | 94 - firmware/ChibiOS_16/os/various/evtimer.c | 85 - firmware/ChibiOS_16/os/various/evtimer.h | 94 - .../os/various/fatfs_bindings/fatfs.mk | 7 - .../os/various/fatfs_bindings/fatfs_diskio.c | 254 - .../os/various/fatfs_bindings/fatfs_syscall.c | 84 - .../os/various/fatfs_bindings/readme.txt | 6 - .../os/various/lwip_bindings/arch/cc.h | 77 - .../os/various/lwip_bindings/arch/perf.h | 57 - .../os/various/lwip_bindings/arch/sys_arch.c | 257 - .../os/various/lwip_bindings/arch/sys_arch.h | 68 - .../os/various/lwip_bindings/lwip.mk | 54 - .../os/various/lwip_bindings/lwipthread.c | 340 - .../os/various/lwip_bindings/lwipthread.h | 161 - .../os/various/lwip_bindings/readme.txt | 6 - firmware/ChibiOS_16/os/various/shell.c | 303 - firmware/ChibiOS_16/os/various/shell.h | 86 - firmware/ChibiOS_16/os/various/syscalls.c | 179 - firmware/ChibiOS_16/os/various/various.dox | 81 - firmware/ChibiOS_16/readme.txt | 489 - .../chibios/boards/OLIMEX_STM32_E407/board.c | 108 - .../chibios/boards/OLIMEX_STM32_E407/board.h | 1300 --- .../chibios/boards/OLIMEX_STM32_E407/board.mk | 5 - .../boards/OLIMEX_STM32_E407/cfg/board.chcfg | 341 - .../chibios/boards/ST_NUCLEO_F103RB/board.c | 50 - .../chibios/boards/ST_NUCLEO_F103RB/board.h | 202 - .../chibios/boards/ST_NUCLEO_F103RB/board.mk | 5 - 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firmware/chibios/os/hal/include/io_block.h | 276 - firmware/chibios/os/hal/include/io_channel.h | 301 - firmware/chibios/os/hal/include/mac.h | 221 - firmware/chibios/os/hal/include/mii.h | 169 - firmware/chibios/os/hal/include/mmc_spi.h | 206 - firmware/chibios/os/hal/include/mmcsd.h | 286 - firmware/chibios/os/hal/include/pal.h | 562 - firmware/chibios/os/hal/include/pwm.h | 259 - firmware/chibios/os/hal/include/rtc.h | 178 - firmware/chibios/os/hal/include/sdc.h | 189 - firmware/chibios/os/hal/include/serial.h | 323 - firmware/chibios/os/hal/include/serial_usb.h | 241 - firmware/chibios/os/hal/include/spi.h | 331 - firmware/chibios/os/hal/include/tm.h | 125 - firmware/chibios/os/hal/include/uart.h | 129 - firmware/chibios/os/hal/include/usb.h | 585 -- .../chibios/os/hal/platforms/Posix/console.c | 128 - .../chibios/os/hal/platforms/Posix/console.h | 62 - .../chibios/os/hal/platforms/Posix/hal_lld.c | 104 - .../chibios/os/hal/platforms/Posix/hal_lld.h | 80 - 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.../os/hal/platforms/STM32F0xx/hal_lld.c | 216 - .../os/hal/platforms/STM32F0xx/hal_lld.h | 796 -- .../os/hal/platforms/STM32F0xx/platform.dox | 292 - .../os/hal/platforms/STM32F0xx/platform.mk | 25 - .../os/hal/platforms/STM32F0xx/stm32_dma.c | 315 - .../os/hal/platforms/STM32F0xx/stm32_dma.h | 406 - .../os/hal/platforms/STM32F0xx/stm32_isr.h | 91 - .../os/hal/platforms/STM32F0xx/stm32_rcc.h | 596 -- .../hal/platforms/STM32F0xx/stm32_registry.h | 417 - .../os/hal/platforms/STM32F0xx/stm32f0xx.h | 3295 ------ .../os/hal/platforms/STM32F1xx/adc_lld.c | 234 - .../os/hal/platforms/STM32F1xx/adc_lld.h | 393 - .../os/hal/platforms/STM32F1xx/ext_lld_isr.c | 338 - .../os/hal/platforms/STM32F1xx/ext_lld_isr.h | 149 - .../os/hal/platforms/STM32F1xx/hal_lld.c | 310 - .../os/hal/platforms/STM32F1xx/hal_lld.h | 255 - .../os/hal/platforms/STM32F1xx/hal_lld_f100.h | 950 -- .../os/hal/platforms/STM32F1xx/hal_lld_f103.h | 1308 --- .../platforms/STM32F1xx/hal_lld_f105_f107.h | 1050 -- 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.../os/hal/platforms/STM32F4xx/stm32f2xx.h | 6881 ------------- .../os/hal/platforms/STM32F4xx/stm32f4xx.h | 9158 ----------------- .../chibios/os/hal/platforms/Win32/console.c | 128 - .../chibios/os/hal/platforms/Win32/console.h | 62 - .../chibios/os/hal/platforms/Win32/hal_lld.c | 110 - .../chibios/os/hal/platforms/Win32/hal_lld.h | 72 - .../chibios/os/hal/platforms/Win32/pal_lld.c | 95 - .../chibios/os/hal/platforms/Win32/pal_lld.h | 206 - .../os/hal/platforms/Win32/platform.mk | 7 - .../os/hal/platforms/Win32/serial_lld.c | 278 - .../os/hal/platforms/Win32/serial_lld.h | 143 - firmware/chibios/os/hal/src/adc.c | 350 - firmware/chibios/os/hal/src/can.c | 292 - firmware/chibios/os/hal/src/ext.c | 214 - firmware/chibios/os/hal/src/gpt.c | 275 - firmware/chibios/os/hal/src/hal.c | 201 - firmware/chibios/os/hal/src/i2c.c | 310 - firmware/chibios/os/hal/src/icu.c | 166 - firmware/chibios/os/hal/src/mac.c | 279 - firmware/chibios/os/hal/src/mmc_spi.c | 886 -- firmware/chibios/os/hal/src/mmcsd.c | 121 - firmware/chibios/os/hal/src/pal.c | 137 - firmware/chibios/os/hal/src/pwm.c | 214 - firmware/chibios/os/hal/src/rtc.c | 197 - firmware/chibios/os/hal/src/sdc.c | 587 -- firmware/chibios/os/hal/src/serial.c | 253 - firmware/chibios/os/hal/src/serial_usb.c | 421 - firmware/chibios/os/hal/src/spi.c | 447 - firmware/chibios/os/hal/src/tm.c | 135 - firmware/chibios/os/hal/src/uart.c | 360 - firmware/chibios/os/hal/src/usb.c | 810 -- firmware/chibios/os/kernel/include/ch.h | 150 - firmware/chibios/os/kernel/include/chbsem.h | 258 - firmware/chibios/os/kernel/include/chcond.h | 98 - firmware/chibios/os/kernel/include/chdebug.h | 265 - .../chibios/os/kernel/include/chdynamic.h | 75 - firmware/chibios/os/kernel/include/chevents.h | 212 - firmware/chibios/os/kernel/include/chfiles.h | 172 - firmware/chibios/os/kernel/include/chheap.h | 100 - firmware/chibios/os/kernel/include/chinline.h | 94 - firmware/chibios/os/kernel/include/chlists.h | 134 - firmware/chibios/os/kernel/include/chmboxes.h | 170 - .../chibios/os/kernel/include/chmemcore.h | 93 - .../chibios/os/kernel/include/chmempools.h | 141 - firmware/chibios/os/kernel/include/chmsg.h | 92 - firmware/chibios/os/kernel/include/chmtx.h | 103 - firmware/chibios/os/kernel/include/chqueues.h | 376 - .../chibios/os/kernel/include/chregistry.h | 137 - firmware/chibios/os/kernel/include/chschd.h | 244 - firmware/chibios/os/kernel/include/chsem.h | 125 - .../chibios/os/kernel/include/chstreams.h | 154 - firmware/chibios/os/kernel/include/chsys.h | 254 - .../chibios/os/kernel/include/chthreads.h | 387 - firmware/chibios/os/kernel/include/chvt.h | 264 - firmware/chibios/os/kernel/kernel.mk | 23 - firmware/chibios/os/kernel/src/chcond.c | 292 - firmware/chibios/os/kernel/src/chdebug.c | 282 - firmware/chibios/os/kernel/src/chdynamic.c | 211 - firmware/chibios/os/kernel/src/chevents.c | 555 - firmware/chibios/os/kernel/src/chheap.c | 325 - firmware/chibios/os/kernel/src/chlists.c | 163 - firmware/chibios/os/kernel/src/chmboxes.c | 383 - firmware/chibios/os/kernel/src/chmemcore.c | 138 - firmware/chibios/os/kernel/src/chmempools.c | 180 - firmware/chibios/os/kernel/src/chmsg.c | 139 - firmware/chibios/os/kernel/src/chmtx.c | 400 - firmware/chibios/os/kernel/src/chqueues.c | 438 - firmware/chibios/os/kernel/src/chregistry.c | 163 - firmware/chibios/os/kernel/src/chschd.c | 385 - firmware/chibios/os/kernel/src/chsem.c | 400 - firmware/chibios/os/kernel/src/chsys.c | 156 - firmware/chibios/os/kernel/src/chthreads.c | 443 - firmware/chibios/os/kernel/src/chvt.c | 121 - .../os/ports/GCC/ARMCMx/STM32F0xx/cmparams.h | 69 - .../os/ports/GCC/ARMCMx/STM32F0xx/port.mk | 15 - .../os/ports/GCC/ARMCMx/STM32F0xx/vectors.c | 205 - .../os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h | 69 - .../os/ports/GCC/ARMCMx/STM32F1xx/port.mk | 15 - .../os/ports/GCC/ARMCMx/STM32F1xx/vectors.c | 337 - .../os/ports/GCC/ARMCMx/STM32F4xx/cmparams.h | 69 - .../os/ports/GCC/ARMCMx/STM32F4xx/port.mk | 15 - .../os/ports/GCC/ARMCMx/STM32F4xx/vectors.c | 338 - firmware/chibios/os/ports/GCC/ARMCMx/chcore.c | 53 - firmware/chibios/os/ports/GCC/ARMCMx/chcore.h | 195 - .../chibios/os/ports/GCC/ARMCMx/chcore_v6m.c | 206 - .../chibios/os/ports/GCC/ARMCMx/chcore_v6m.h | 385 - .../chibios/os/ports/GCC/ARMCMx/chcore_v7m.c | 260 - .../chibios/os/ports/GCC/ARMCMx/chcore_v7m.h | 543 - .../chibios/os/ports/GCC/ARMCMx/chtypes.h | 92 - firmware/chibios/os/ports/GCC/ARMCMx/crt0.c | 361 - firmware/chibios/os/ports/GCC/ARMCMx/rules.mk | 253 - .../chibios/os/ports/GCC/SIMIA32/chcore.c | 93 - .../chibios/os/ports/GCC/SIMIA32/chcore.h | 250 - .../chibios/os/ports/GCC/SIMIA32/chtypes.h | 77 - firmware/chibios/os/ports/GCC/SIMIA32/port.mk | 6 - .../os/ports/IAR/ARMCMx/STM32F0xx/cmparams.h | 69 - .../os/ports/IAR/ARMCMx/STM32F0xx/vectors.s | 317 - .../os/ports/IAR/ARMCMx/STM32F4xx/cmparams.h | 69 - .../os/ports/IAR/ARMCMx/STM32F4xx/vectors.s | 344 - firmware/chibios/os/ports/IAR/ARMCMx/chcore.c | 53 - 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.../chibios/os/ports/common/ARMCMx/nvic.c | 81 - .../chibios/os/ports/common/ARMCMx/nvic.h | 300 - firmware/chibios/os/various/chprintf.c | 286 - firmware/chibios/os/various/chprintf.h | 80 - firmware/chibios/os/various/chrtclib.c | 376 - firmware/chibios/os/various/chrtclib.h | 59 - .../chibios/os/various/cpp_wrappers/ch.cpp | 866 -- .../chibios/os/various/cpp_wrappers/ch.hpp | 2282 ---- .../chibios/os/various/cpp_wrappers/kernel.mk | 4 - .../os/various/devices_lib/accel/lis302dl.c | 119 - .../os/various/devices_lib/accel/lis302dl.h | 93 - .../os/various/fatfs_bindings/fatfs.mk | 7 - .../os/various/fatfs_bindings/fatfs_diskio.c | 255 - .../os/various/fatfs_bindings/fatfs_syscall.c | 84 - firmware/chibios/os/various/memstreams.c | 113 - firmware/chibios/os/various/memstreams.h | 95 - firmware/chibios/os/various/syscalls.c | 177 - firmware/chibios/readme.txt | 5 - firmware/chibios/rusefi_chibios.patch | 111 - 956 files changed, 1 insertion(+), 332563 deletions(-) delete mode 100644 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100644 firmware/chibios/os/various/cpp_wrappers/kernel.mk delete mode 100644 firmware/chibios/os/various/devices_lib/accel/lis302dl.c delete mode 100644 firmware/chibios/os/various/devices_lib/accel/lis302dl.h delete mode 100644 firmware/chibios/os/various/fatfs_bindings/fatfs.mk delete mode 100644 firmware/chibios/os/various/fatfs_bindings/fatfs_diskio.c delete mode 100644 firmware/chibios/os/various/fatfs_bindings/fatfs_syscall.c delete mode 100644 firmware/chibios/os/various/memstreams.c delete mode 100644 firmware/chibios/os/various/memstreams.h delete mode 100644 firmware/chibios/os/various/syscalls.c delete mode 100644 firmware/chibios/readme.txt delete mode 100644 firmware/chibios/rusefi_chibios.patch diff --git a/.gitmodules b/.gitmodules index 44f6da237c..de894b04fc 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,3 @@ -[submodule "firmware/ChibiOS-Contrib"] +[submodule "firmware/ChibiOS-Contrib"] path = firmware/ChibiOS-Contrib url = https://github.com/ChibiOS/ChibiOS-Contrib.git diff --git a/firmware/ChibiOS_16/community/.gitignore b/firmware/ChibiOS_16/community/.gitignore deleted file mode 100644 index 7cc5e99324..0000000000 --- a/firmware/ChibiOS_16/community/.gitignore +++ /dev/null @@ -1,5 +0,0 @@ -*.origin -*.swp -*~ -.dep -build diff --git a/firmware/ChibiOS_16/community/AUTHORS.txt b/firmware/ChibiOS_16/community/AUTHORS.txt deleted file mode 100644 index 6712859c07..0000000000 --- a/firmware/ChibiOS_16/community/AUTHORS.txt +++ /dev/null @@ -1,21 +0,0 @@ -Joel Bodenmann aka Tectu -https://github.com/Tectu -Git repository maintainer - -Uladzimir Pylinsky aka barthess -https://github.com/barthess -Git repository maintainer - -Marco Veeneman aka Marco -https://github.com/marcoveeneman -Maintainer of the ChibiOS port for the Texas Instruments -Tiva C Series Microcontrollers - -Fabien Poussin aka fpoussin -https://github.com/fpoussin - -Matthias Blaicher aka mabl -https://github.com/mabl - -Andrea Zoppi aka TexZK -https://github.com/TexZK diff --git a/firmware/ChibiOS_16/community/README.md b/firmware/ChibiOS_16/community/README.md deleted file mode 100644 index 913b1e741f..0000000000 --- a/firmware/ChibiOS_16/community/README.md +++ /dev/null @@ -1,24 +0,0 @@ -ChibiOS-Contrib -=============== -Code under this directory is not part of the core ChibiOS project -and the copyright is retained by the original authors. See copyright -notes in file headers. - -Code is maintained via Github https://github.com/ChibiOS/ChibiOS-Contrib -Feel free to send pull request there. - -#### Using - -```bash -# git clone git@github.com:Chibios/ChibiOS.git ChibiOS-RT -# git clone git@github.com:ChibiOS/ChibiOS-Contrib.git ChibiOS-Contrib -``` -Note: this repos cloned in the same directory side by side (not inside). - -#### Useful links - -https://help.github.com/ - -http://git-scm.com/ - -http://chibios.org/dokuwiki/doku.php?id=chibios:guides:style_guide diff --git a/firmware/ChibiOS_16/community/os/.keep b/firmware/ChibiOS_16/community/os/.keep deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/firmware/ChibiOS_16/community/os/hal/hal.mk b/firmware/ChibiOS_16/community/os/hal/hal.mk deleted file mode 100644 index 05164ae652..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/hal.mk +++ /dev/null @@ -1,24 +0,0 @@ -include ${CHIBIOS}/os/hal/hal.mk - -HALSRC += ${CHIBIOS_CONTRIB}/os/hal/src/hal_community.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/hal_nand.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/hal_onewire.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/hal_eicu.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/hal_crc.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/hal_rng.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/hal_usbh.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_debug.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_desciter.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_hub.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_msd.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_ftdi.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_uvc.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/hal_ee24xx.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/hal_ee25xx.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/hal_eeprom.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/hal_timcap.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/hal_qei.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/hal_usb_hid.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/hal_usb_msd.c - -HALINC += ${CHIBIOS_CONTRIB}/os/hal/include diff --git a/firmware/ChibiOS_16/community/os/hal/include/hal_community.h b/firmware/ChibiOS_16/community/os/hal/include/hal_community.h deleted file mode 100644 index e660f20ddb..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/include/hal_community.h +++ /dev/null @@ -1,127 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_community.h - * @brief HAL subsystem header (community part). - * - * @addtogroup HAL_COMMUNITY - * @{ - */ - -#ifndef HAL_COMMUNITY_H -#define HAL_COMMUNITY_H - - -/* Error checks on the configuration header file.*/ -#if !defined(HAL_USE_CRC) -#define HAL_USE_CRC FALSE -#endif - -#if !defined(HAL_USE_EEPROM) -#define HAL_USE_EEPROM FALSE -#endif - -#if !defined(HAL_USE_EICU) -#define HAL_USE_EICU FALSE -#endif - -#if !defined(HAL_USE_NAND) -#define HAL_USE_NAND FALSE -#endif - -#if !defined(HAL_USE_ONEWIRE) -#define HAL_USE_ONEWIRE FALSE -#endif - -#if !defined(HAL_USE_QEI) -#define HAL_USE_QEI FALSE -#endif - -#if !defined(HAL_USE_RNG) -#define HAL_USE_RNG FALSE -#endif - -#if !defined(HAL_USE_TIMCAP) -#define HAL_USE_TIMCAP FALSE -#endif - -#if !defined(HAL_USE_USBH) -#define HAL_USE_USBH FALSE -#endif - -#if !defined(HAL_USE_USB_HID) -#define HAL_USE_USB_HID FALSE -#endif - -#if !defined(HAL_USE_USB_MSD) -#define HAL_USE_USB_MSD FALSE -#endif - -/* Abstract interfaces.*/ - -/* Shared headers.*/ - -/* Normal drivers.*/ -#include "hal_nand.h" -#include "hal_eicu.h" -#include "hal_rng.h" -#include "hal_usbh.h" -#include "hal_timcap.h" -#include "hal_qei.h" - -/* Complex drivers.*/ -#include "hal_onewire.h" -#include "hal_crc.h" -#include "hal_eeprom.h" -#include "hal_usb_hid.h" -#include "hal_usb_msd.h" - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void halCommunityInit(void); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_COMMUNITY_H */ - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/hal/include/hal_crc.h b/firmware/ChibiOS_16/community/os/hal/include/hal_crc.h deleted file mode 100644 index d7ef10f2d4..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/include/hal_crc.h +++ /dev/null @@ -1,158 +0,0 @@ -/* - ChibiOS - Copyright (C) 2015 Michael D. Spradling - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef HAL_CRC_H_ -#define HAL_CRC_H_ - -#if (HAL_USE_CRC == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ - -/** - * @brief Enable DMA CRC - * @note Enables DMA when doing CRC calculations. This may be less - * efficient with smaller CRC calculations. - */ -#if !defined(CRC_USE_DMA) || defined(__DOXYGEN__) -#define CRC_USE_DMA FALSE -#endif - -/** - * @brief Enables the @p crcAcquireBus() and @p crcReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(CRC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define CRC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_CRC_USE_CRC1 != TRUE && CRCSW_USE_CRC1 != TRUE -#error "CRC requires at least one LLD driver." -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - CRC_UNINIT, /* Not initialized. */ - CRC_STOP, /* Stopped. */ - CRC_READY, /* Ready. */ - CRC_ACTIVE, /* Calculating CRC. */ - CRC_COMPLETE /* Asynchronous operation complete. */ -} crcstate_t; - -#include "hal_crc_lld.h" -#include "crcsw.h" /* Include software LL driver */ - - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Low level driver helper macros - * @{ - */ - -/** - * @brief Wakes up the waiting thread. - * - * @param[in] crcp pointer to the @p CRCDriver object - * - * @notapi - */ -#define _crc_wakeup_isr(crcp) { \ - osalSysLockFromISR(); \ - osalThreadResumeI(&(crcp)->thread, MSG_OK); \ - osalSysUnlockFromISR(); \ -} - -/** - * @brief Common ISR code. - * @details This code handles the portable part of the ISR code: - * - Callback invocation. - * - Waiting thread wakeup, if any. - * - Driver state transitions. - * . - * @note This macro is meant to be used in the low level drivers - * implementation only. - * - * @param[in] crcp pointer to the @p CRCDriver object - * - * @notapi - */ -#define _crc_isr_code(crcp, crc) { \ - if ((crcp)->config->end_cb) { \ - (crcp)->state = CRC_COMPLETE; \ - (crcp)->config->end_cb(crcp, crc); \ - if ((crcp)->state == CRC_COMPLETE) \ - (crcp)->state = CRC_READY; \ - } \ - else \ - (crcp)->state = CRC_READY; \ - _crc_wakeup_isr(crcp); \ -} - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void crcInit(void); - void crcObjectInit(CRCDriver *crcp); - void crcStart(CRCDriver *crcp, const CRCConfig *config); - void crcStop(CRCDriver *crcp); - void crcReset(CRCDriver *crcp); - void crcResetI(CRCDriver *crcp); - uint32_t crcCalc(CRCDriver *crcp, size_t n, const void *buf); - uint32_t crcCalcI(CRCDriver *crcp, size_t n, const void *buf); -#if CRC_USE_DMA == TRUE - void crcStartCalc(CRCDriver *crcp, size_t n, const void *buf); - void crcStartCalcI(CRCDriver *crcp, size_t n, const void *buf); -#endif -#if CRC_USE_MUTUAL_EXCLUSION == TRUE - void crcAcquireUnit(CRCDriver *crcp); - void crcReleaseUnit(CRCDriver *crcp); -#endif -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_CRC */ - -#endif /* HAL_CRC_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/hal/include/hal_ee24xx.h b/firmware/ChibiOS_16/community/os/hal/include/hal_ee24xx.h deleted file mode 100644 index 00cdc95f2c..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/include/hal_ee24xx.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - Copyright 2012 Uladzimir Pylinski aka barthess. - You may use this work without restrictions, as long as this notice is included. - The work is provided "as is" without warranty of any kind, neither express nor implied. -*/ - -#ifndef HAL_EE24XX_H -#define HAL_EE24XX_H - -#include "hal.h" - -#if defined(HAL_USE_EEPROM) && HAL_USE_EEPROM && EEPROM_USE_EE24XX - -#define EEPROM_DEV_24XX 24 - -/** - * @extends EepromFileConfig - */ -typedef struct { - _eeprom_file_config_data - /** - * Driver connected to IC. - */ - I2CDriver *i2cp; - /** - * Address of IC on I2C bus. - */ - i2caddr_t addr; - /** - * Pointer to write buffer. The safest size is (pagesize + 2) - */ - uint8_t *write_buf; -} I2CEepromFileConfig; - -/** - * @brief @p I2CEepromFileStream specific data. - */ -#define _eeprom_file_stream_data_i2c \ - _eeprom_file_stream_data - -/** - * @extends EepromFileStream - * - * @brief EEPROM file stream driver class for I2C device. - */ -typedef struct { - const struct EepromFileStreamVMT *vmt; - _eeprom_file_stream_data_i2c - /* Overwritten parent data member. */ - const I2CEepromFileConfig *cfg; -} I2CEepromFileStream; - - -/** - * Open I2C EEPROM IC as file and return pointer to the file stream object - * @note Fucntion allways successfully open file. All checking makes - * in read/write functions. - */ -#define I2CEepromFileOpen(efs, eepcfg, eepdev) \ - EepromFileOpen((EepromFileStream *)efs, (EepromFileConfig *)eepcfg, eepdev); - -#endif /* #if defined(EEPROM_USE_EE24XX) && EEPROM_USE_EE24XX */ - -#endif // HAL_EE24XX_H diff --git a/firmware/ChibiOS_16/community/os/hal/include/hal_ee25xx.h b/firmware/ChibiOS_16/community/os/hal/include/hal_ee25xx.h deleted file mode 100644 index e520bd64ac..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/include/hal_ee25xx.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - Copyright 2012 Uladzimir Pylinski aka barthess. - You may use this work without restrictions, as long as this notice is included. - The work is provided "as is" without warranty of any kind, neither express nor implied. -*/ - -#ifndef HAL_EE25XX_H -#define HAL_EE25XX_H - -#include "hal.h" - -#if defined(HAL_USE_EEPROM) && HAL_USE_EEPROM && EEPROM_USE_EE25XX - -#define EEPROM_DEV_25XX 25 - -/** - * @extends EepromFileConfig - */ -typedef struct { - _eeprom_file_config_data - /** - * Driver connected to IC. - */ - SPIDriver *spip; - /** - * Config associated with SPI driver. - */ - const SPIConfig *spicfg; -} SPIEepromFileConfig; - -/** - * @brief @p SPIEepromFileStream specific data. - */ -#define _eeprom_file_stream_data_spi \ - _eeprom_file_stream_data - -/** - * @extends EepromFileStream - * - * @brief EEPROM file stream driver class for SPI device. - */ -typedef struct { - const struct EepromFileStreamVMT *vmt; - _eeprom_file_stream_data_spi - /* Overwritten parent data member. */ - const SPIEepromFileConfig *cfg; -} SPIEepromFileStream; - -/** - * Open SPI EEPROM IC as file and return pointer to the file stream object - * @note Fucntion allways successfully open file. All checking makes - * in read/write functions. - */ -EepromFileStream *SPIEepromFileOpen(SPIEepromFileStream *efs, - const SPIEepromFileConfig *eepcfg, - const EepromDevice *eepdev); - -#define SPIEepromFileOpen(efs, eepcfg, eepdev) \ - EepromFileOpen((EepromFileStream *)efs, (EepromFileConfig *)eepcfg, eepdev); - -#endif /* #if defined(EEPROM_USE_EE25XX) && EEPROM_USE_EE25XX */ - -#endif // HAL_EE25XX_H diff --git a/firmware/ChibiOS_16/community/os/hal/include/hal_eeprom.h b/firmware/ChibiOS_16/community/os/hal/include/hal_eeprom.h deleted file mode 100644 index 6f53fb9c3b..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/include/hal_eeprom.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - Copyright (c) 2013 Timon Wong - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to deal - in the Software without restriction, including without limitation the rights - to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included in all - copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - THE SOFTWARE. -*/ - -/* - Copyright 2012 Uladzimir Pylinski aka barthess. - You may use this work without restrictions, as long as this notice is included. - The work is provided "as is" without warranty of any kind, neither express nor implied. -*/ - -#ifndef HAL_EEPROM_H_ -#define HAL_EEPROM_H_ - -#include "ch.h" -#include "hal.h" - -#ifndef EEPROM_USE_EE25XX -#define EEPROM_USE_EE25XX FALSE -#endif - -#ifndef EEPROM_USE_EE24XX -#define EEPROM_USE_EE24XX FALSE -#endif - -#if (HAL_USE_EEPROM == TRUE) || defined(__DOXYGEN__) - -#if EEPROM_USE_EE25XX && EEPROM_USE_EE24XX -#define EEPROM_TABLE_SIZE 2 -#elif EEPROM_USE_EE25XX || EEPROM_USE_EE24XX -#define EEPROM_TABLE_SIZE 1 -#else -#error "No EEPROM device selected!" -#endif - -#if EEPROM_USE_EE25XX && !HAL_USE_SPI -#error "25xx enabled but SPI driver is disabled!" -#endif - -#if EEPROM_USE_EE24XX && !HAL_USE_I2C -#error "24xx enabled but I2C driver is disabled!" -#endif - -#define _eeprom_file_config_data \ - /* Lower barrier of file in EEPROM memory array. */ \ - uint32_t barrier_low; \ - /* Higher barrier of file in EEPROM memory array. */ \ - uint32_t barrier_hi; \ - /* Size of memory array in bytes. */ \ - uint32_t size; \ - /* Size of single page in bytes. */ \ - uint16_t pagesize; \ - /* Time needed by IC for single byte/page writing. */ \ - systime_t write_time; - -typedef uint32_t fileoffset_t; - -typedef struct { - _eeprom_file_config_data -} EepromFileConfig; - -/** - * @brief @p EepromFileStream specific data. - */ -#define _eeprom_file_stream_data \ - _base_sequential_stream_data \ - uint32_t errors; \ - uint32_t position; \ - -/** - * @extends BaseFileStreamVMT - * - * @brief @p EepromFileStream virtual methods table. - */ -struct EepromFileStreamVMT { - _file_stream_methods -}; - -/** - * @extends BaseFileStream - * - * @brief EEPROM file stream driver class. - * @details This class extends @p BaseFileStream by adding some fields. - */ -typedef struct { - /** @brief Virtual Methods Table.*/ - const struct EepromFileStreamVMT *vmt; - _eeprom_file_stream_data - /** pointer to config object, must be overwritten by all derived classes.*/ - const EepromFileConfig *cfg; -} EepromFileStream; - -/** - * @brief Low level device descriptor. - */ -typedef struct { - const uint8_t id; - const struct EepromFileStreamVMT *efsvmt; -} EepromDevice; - -const EepromDevice *EepromFindDevice(uint8_t id); - -EepromFileStream *EepromFileOpen(EepromFileStream *efs, - const EepromFileConfig *eepcfg, - const EepromDevice *eepdev); - -uint8_t EepromReadByte(EepromFileStream *efs); -uint16_t EepromReadHalfword(EepromFileStream *efs); -uint32_t EepromReadWord(EepromFileStream *efs); -size_t EepromWriteByte(EepromFileStream *efs, uint8_t data); -size_t EepromWriteHalfword(EepromFileStream *efs, uint16_t data); -size_t EepromWriteWord(EepromFileStream *efs, uint32_t data); - -msg_t eepfs_getsize(void *ip); -msg_t eepfs_getposition(void *ip); -msg_t eepfs_lseek(void *ip, fileoffset_t offset); -msg_t eepfs_close(void *ip); -msg_t eepfs_geterror(void *ip); -msg_t eepfs_put(void *ip, uint8_t b); -msg_t eepfs_get(void *ip); - -#include "hal_ee24xx.h" -#include "hal_ee25xx.h" - -#endif /* #if defined(HAL_USE_EEPROM) && HAL_USE_EEPROM */ -#endif /* HAL_EEPROM_H_ */ diff --git a/firmware/ChibiOS_16/community/os/hal/include/hal_eicu.h b/firmware/ChibiOS_16/community/os/hal/include/hal_eicu.h deleted file mode 100644 index 8b4b07dfa2..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/include/hal_eicu.h +++ /dev/null @@ -1,191 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Rewritten by Emil Fresk (1/5 - 2014) for extended input capture - functionality. And fix for spurious callbacks in the interrupt handler. -*/ -/* - Improved by Uladzimir Pylinsky aka barthess (1/3 - 2015) for support of - 32-bit timers and timers with single capture/compare channels. -*/ - -#ifndef HAL_EICU_H_ -#define HAL_EICU_H_ - -#if (HAL_USE_EICU == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - EICU_UNINIT, /* Not initialized. */ - EICU_STOP, /* Stopped. */ - EICU_READY, /* Ready. */ - EICU_WAITING, /* Waiting for first edge. */ - EICU_ACTIVE, /* Active cycle phase. */ - EICU_IDLE /* Idle cycle phase. */ -} eicustate_t; - -/** - * @brief Channel state machine possible states. - */ -typedef enum { - EICU_CH_IDLE, /* Idle cycle phase. */ - EICU_CH_ACTIVE /* Active cycle phase. */ -} eicuchannelstate_t; - -/** - * @brief EICU channel selection definition - */ -typedef enum { - EICU_CHANNEL_1, - EICU_CHANNEL_2, - EICU_CHANNEL_3, - EICU_CHANNEL_4, - EICU_CHANNEL_ENUM_END -} eicuchannel_t; - -/** - * @brief Type of a structure representing an EICU driver. - */ -typedef struct EICUDriver EICUDriver; - -/** - * @brief EICU notification callback type. - * - * @param[in] eicup Pointer to a EICUDriver object - * @param[in] channel EICU channel that fired the interrupt - * @param[in] width Pulse width - * @param[in] period Pulse period - */ -typedef void (*eicucallback_t)(EICUDriver *eicup, eicuchannel_t channel, - uint32_t width, uint32_t period); - -#include "hal_eicu_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Enables the extended input capture. - * - * @param[in] eicup Pointer to the @p EICUDriver object - * - * @iclass - */ -#define eicuEnableI(eicup) eicu_lld_enable(eicup) - -/** - * @brief Disables the extended input capture. - * - * @param[in] eicup Pointer to the @p EICUDriver object - * - * @iclass - */ -#define eicuDisableI(eicup) eicu_lld_disable(eicup) -/** @} */ - -/** - * @name Low Level driver helper macros - * @{ - */ -/** - * @brief Common ISR code, EICU PWM width event. - * - * @param[in] eicup Pointer to the @p EICUDriver object - * @param[in] channel The timer channel that fired the interrupt. - * - * @notapi - */ -static inline void _eicu_isr_invoke_pwm_width_cb(EICUDriver *eicup, - eicuchannel_t channel) { - if (eicup->state != EICU_WAITING) { - eicup->state = EICU_IDLE; - eicup->config->iccfgp[channel]->capture_cb(eicup, channel, 0, 0); - } -} - -/** - * @brief Common ISR code, EICU PWM period event. - * - * @param[in] eicup Pointer to the @p EICUDriver object - * @param[in] channel The timer channel that fired the interrupt. - * - * @notapi - */ -static inline void _eicu_isr_invoke_pwm_period_cb(EICUDriver *eicup, - eicuchannel_t channel) { - eicustate_t previous_state = eicup->state; - eicup->state = EICU_ACTIVE; - if (previous_state != EICU_WAITING) - eicup->channel[channel].config->capture_cb(eicup, channel, 0, 0); -} - -/** - * @brief Common ISR code, EICU timer overflow event. - * - * @param[in] eicup Pointer to the @p EICUDriver object - * - * @notapi - */ -#define _eicu_isr_invoke_overflow_cb(icup) do { \ - (eicup)->config->overflow_cb(eicup, 0, 0, 0); \ -} while (0) -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void eicuInit(void); - void eicuObjectInit(EICUDriver *eicup); - void eicuStart(EICUDriver *eicup, const EICUConfig *config); - void eicuStop(EICUDriver *eicup); - void eicuEnable(EICUDriver *eicup); - void eicuDisable(EICUDriver *eicup); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_EICU */ - -#endif /* HAL_EICU_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/hal/include/hal_nand.h b/firmware/ChibiOS_16/community/os/hal/include/hal_nand.h deleted file mode 100644 index f90715244f..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/include/hal_nand.h +++ /dev/null @@ -1,138 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_nand.h - * @brief NAND Driver macros and structures. - * - * @addtogroup NAND - * @{ - */ - -#ifndef HAL_NAND_H_ -#define HAL_NAND_H_ - -#if (HAL_USE_NAND == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/* - * Standard NAND flash commands - */ -#define NAND_CMD_READ0 0x00 -#define NAND_CMD_RNDOUT 0x05 -#define NAND_CMD_PAGEPROG 0x10 -#define NAND_CMD_READ0_CONFIRM 0x30 -#define NAND_CMD_READOOB 0x50 -#define NAND_CMD_ERASE 0x60 -#define NAND_CMD_STATUS 0x70 -#define NAND_CMD_STATUS_MULTI 0x71 -#define NAND_CMD_WRITE 0x80 -#define NAND_CMD_RNDIN 0x85 -#define NAND_CMD_READID 0x90 -#define NAND_CMD_ERASE_CONFIRM 0xD0 -#define NAND_CMD_RESET 0xFF - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ -/** - * @brief Enables the mutual exclusion APIs on the NAND. - */ -#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define NAND_USE_MUTUAL_EXCLUSION FALSE -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ -#if NAND_USE_MUTUAL_EXCLUSION && !CH_CFG_USE_MUTEXES && !CH_CFG_USE_SEMAPHORES -#error "NAND_USE_MUTUAL_EXCLUSION requires CH_CFG_USE_MUTEXES and/or CH_CFG_USE_SEMAPHORES" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - NAND_UNINIT = 0, /**< Not initialized. */ - NAND_STOP = 1, /**< Stopped. */ - NAND_READY = 2, /**< Ready. */ - NAND_PROGRAM = 3, /**< Programming in progress. */ - NAND_ERASE = 4, /**< Erasing in progress. */ - NAND_WRITE = 5, /**< Writing to NAND buffer. */ - NAND_READ = 6, /**< Reading from NAND. */ - NAND_DMA_TX = 7, /**< DMA transmitting. */ - NAND_DMA_RX = 8, /**< DMA receiving. */ - NAND_RESET = 9, /**< Software reset in progress. */ -} nandstate_t; - -/** - * @brief Type of a structure representing a NAND driver. - */ -typedef struct NANDDriver NANDDriver; - -#include "hal_nand_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void nandInit(void); - void nandObjectInit(NANDDriver *nandp); - void nandStart(NANDDriver *nandp, const NANDConfig *config, bitmap_t *bb_map); - void nandStop(NANDDriver *nandp); - uint8_t nandErase(NANDDriver *nandp, uint32_t block); - void nandReadPageWhole(NANDDriver *nandp, uint32_t block, uint32_t page, - void *data, size_t datalen); - void nandReadPageData(NANDDriver *nandp, uint32_t block, uint32_t page, - void *data, size_t datalen, uint32_t *ecc); - void nandReadPageSpare(NANDDriver *nandp, uint32_t block, uint32_t page, - void *spare, size_t sparelen); - uint8_t nandWritePageWhole(NANDDriver *nandp, uint32_t block, uint32_t page, - const void *data, size_t datalen); - uint8_t nandWritePageData(NANDDriver *nandp, uint32_t block, uint32_t page, - const void *data, size_t datalen, uint32_t *ecc); - uint8_t nandWritePageSpare(NANDDriver *nandp, uint32_t block, uint32_t page, - const void *spare, size_t sparelen); - uint16_t nandReadBadMark(NANDDriver *nandp, uint32_t block, uint32_t page); - void nandMarkBad(NANDDriver *nandp, uint32_t block); - bool nandIsBad(NANDDriver *nandp, uint32_t block); -#if NAND_USE_MUTUAL_EXCLUSION - void nandAcquireBus(NANDDriver *nandp); - void nandReleaseBus(NANDDriver *nandp); -#endif /* NAND_USE_MUTUAL_EXCLUSION */ -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_NAND */ - -#endif /* _NAND_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/hal/include/hal_onewire.h b/firmware/ChibiOS_16/community/os/hal/include/hal_onewire.h deleted file mode 100644 index bbaf77b732..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/include/hal_onewire.h +++ /dev/null @@ -1,367 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_onewire.h - * @brief 1-wire Driver macros and structures. - * - * @addtogroup onewire - * @{ - */ - -#ifndef HAL_ONEWIRE_H_ -#define HAL_ONEWIRE_H_ - -#if (HAL_USE_ONEWIRE == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ -/** - * @brief Enable synthetic test for 'search ROM' procedure. - * @note Only for debugging/testing! - */ -#define ONEWIRE_SYNTH_SEARCH_TEST FALSE - -/** - * @brief Aliases for 1-wire protocol. - */ -#define ONEWIRE_CMD_READ_ROM 0x33 -#define ONEWIRE_CMD_SEARCH_ROM 0xF0 -#define ONEWIRE_CMD_MATCH_ROM 0x55 -#define ONEWIRE_CMD_SKIP_ROM 0xCC -#define ONEWIRE_CMD_CONVERT_TEMP 0x44 -#define ONEWIRE_CMD_READ_SCRATCHPAD 0xBE - -/** - * @brief How many bits will be used for transaction length storage. - */ -#define ONEWIRE_REG_BYTES_WIDTH 16U - -/** - * @brief Precalculated maximum transaction length. - */ -#define ONEWIRE_MAX_TRANSACTION_LEN ((1U << ONEWIRE_REG_BYTES_WIDTH) - 1U) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ -#if ONEWIRE_SYNTH_SEARCH_TEST && !ONEWIRE_USE_SEARCH_ROM -#error "Synthetic search rom test needs ONEWIRE_USE_SEARCH_ROM" -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ -#if !HAL_USE_PWM -#error "1-wire Driver requires HAL_USE_PWM" -#endif - -#if !HAL_USE_PAL -#error "1-wire Driver requires HAL_USE_PAL" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ -#if ONEWIRE_USE_STRONG_PULLUP -/** - * @brief 1-wire strong pull up assert callback type. - */ -typedef void (*onewire_pullup_assert_t)(void); - -/** - * @brief 1-wire strong pull up release callback type. - */ -typedef void (*onewire_pullup_release_t)(void); -#endif /* ONEWIRE_USE_STRONG_PULLUP */ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - ONEWIRE_UNINIT = 0, /**< Not initialized. */ - ONEWIRE_STOP = 1, /**< Stopped. */ - ONEWIRE_READY = 2, /**< Ready. */ -#if ONEWIRE_USE_STRONG_PULLUP - ONEWIRE_PULL_UP /**< Pull up asserted. */ -#endif -} onewire_state_t; - -#if ONEWIRE_USE_SEARCH_ROM -/** - * @brief Search ROM procedure possible state. - */ -typedef enum { - ONEWIRE_SEARCH_ROM_SUCCESS = 0, /**< ROM successfully discovered. */ - ONEWIRE_SEARCH_ROM_LAST = 1, /**< Last ROM successfully discovered. */ - ONEWIRE_SEARCH_ROM_ERROR = 2 /**< Error happened during search. */ -} search_rom_result_t; - -/** - * @brief Search ROM procedure iteration enum. - */ -typedef enum { - ONEWIRE_SEARCH_ROM_FIRST = 0, /**< First search run. */ - ONEWIRE_SEARCH_ROM_NEXT = 1 /**< Next search run. */ -} search_iteration_t; -#endif /* ONEWIRE_USE_SEARCH_ROM */ - -/** - * @brief Driver configuration structure. - */ -typedef struct { - /** - * @brief Pointer to @p PWM driver used for communication. - */ - PWMDriver *pwmd; - /** - * @brief Pointer to configuration structure for underlying PWM driver. - * @note It is NOT constant because 1-wire driver needs to change them - * during normal functioning. - */ - PWMConfig *pwmcfg; - /** - * @brief Active logic level for master channel. - * @details Just set it to @p PWM_OUTPUT_ACTIVE_LOW when 1-wire bus - * connected to direct (not complementary) output of the timer. - * In opposite case you need to check documentation to choose - * correct value. - */ - pwmmode_t pwmmode; - /** - * @brief Number of PWM channel used as master pulse generator. - */ - size_t master_channel; - /** - * @brief Number of PWM channel used as sample interrupt generator. - */ - size_t sample_channel; - /** - * @brief Port Identifier. - * @details This type can be a scalar or some kind of pointer, do not make - * any assumption about it, use the provided macros when populating - * variables of this type. - */ - ioportid_t port; - /** - * @brief Digital I/O port pad. - */ - ioportmask_t pad; -#if defined(STM32F1XX) - /** - * @brief Digital I/O mode for idle bus. - * @details This is a kind of workaround against F1x realization of alternate - * function. Alternate function mode will be activated only - * when you starts appropriate peripheral. - */ - iomode_t pad_mode_idle; -#endif - /** - * @brief Digital I/O mode for active bus. - */ - iomode_t pad_mode_active; -#if ONEWIRE_USE_STRONG_PULLUP - /** - * @brief Pointer to function asserting of strong pull up. - */ - onewire_pullup_assert_t pullup_assert; - /** - * @brief Pointer to function releasing of strong pull up. - */ - onewire_pullup_release_t pullup_release; -#endif -} onewireConfig; - -#if ONEWIRE_USE_SEARCH_ROM -/** - * @brief Search ROM registry. Contains small variables used - * in 'search ROM' procedure. - */ -typedef struct { - /** - * @brief Bool flag. True when bus has single slave device. - */ - uint32_t single_device: 1; - /** - * @brief Search iteration (@p search_iteration_t enum). - */ - uint32_t search_iter: 1; - /** - * @brief Result of discovery procedure (@p search_rom_result_t enum). - */ - uint32_t result: 2; - /** - * @brief One of 3 steps of bit discovery. - * @details 0 - direct, 1 - complemented, 2 - generated by master. - */ - uint32_t bit_step: 2; - /** - * @brief Values acquired during bit discovery. - */ - uint32_t bit_buf: 2; - /** - * @brief Currently processing ROM bit. - * @note Must be big enough to store number 64. - */ - uint32_t rombit: 7; - /** - * @brief Total device count discovered on bus. - * @note Maximum 256. - */ - uint32_t devices_found: 8; -} search_rom_reg_t; - -/** - * @brief Helper structure for 'search ROM' procedure - */ -typedef struct { - /** - * @brief Search ROM registry. - */ - search_rom_reg_t reg; - /** - * @brief Pointer to buffer with currently discovering ROM - */ - uint8_t *retbuf; - /** - * @brief Previously discovered ROM. - */ - uint8_t prev_path[8]; - /** - * @brief Last zero turn branch. - * @note Negative values use to point out of device tree's root. - */ - int8_t last_zero_branch; - /** - * @brief Previous zero turn branch. - * @note Negative values use to point out of device tree's root. - */ - int8_t prev_zero_branch; -} onewire_search_rom_t; -#endif /* ONEWIRE_USE_SEARCH_ROM */ - -/** - * @brief Onewire registry. Some small variables combined - * in single machine word to save RAM. - */ -typedef struct { -#if ONEWIRE_USE_STRONG_PULLUP - /** - * @brief This flag will be asserted by driver to signalizes - * ISR part when strong pull up needed. - */ - uint32_t need_pullup: 1; -#endif - /** - * @brief Bool flag. If @p true than at least one device presence on bus. - */ - uint32_t slave_present: 1; - /** - * @brief Driver internal state (@p onewire_state_t enum). - */ - uint32_t state: 2; - /** - * @brief Bit number in currently receiving/sending byte. - * @note Must be big enough to store 8. - */ - uint32_t bit: 4; - /** - * @brief Bool flag for premature timer stop prevention. - */ - uint32_t final_timeslot: 1; - /** - * @brief Bytes number to be processing in current transaction. - */ - uint32_t bytes: ONEWIRE_REG_BYTES_WIDTH; -} onewire_reg_t; - -/** - * @brief Structure representing an 1-wire driver. - */ -typedef struct { - /** - * @brief Onewire registry. - */ - onewire_reg_t reg; - /** - * @brief Onewire config. - */ - const onewireConfig *config; - /** - * @brief Pointer to I/O data buffer. - */ - uint8_t *buf; -#if ONEWIRE_USE_SEARCH_ROM - /** - * @brief Search ROM helper structure. - */ - onewire_search_rom_t search_rom; -#endif /* ONEWIRE_USE_SEARCH_ROM */ - /** - * @brief Thread waiting for I/O completion. - */ - thread_reference_t thread; -} onewireDriver; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -extern onewireDriver OWD1; - -#ifdef __cplusplus -extern "C" { -#endif - void onewireObjectInit(onewireDriver *owp); - void onewireStart(onewireDriver *owp, const onewireConfig *config); - void onewireStop(onewireDriver *owp); - bool onewireReset(onewireDriver *owp); - void onewireRead(onewireDriver *owp, uint8_t *rxbuf, size_t rxbytes); - uint8_t onewireCRC(const uint8_t *buf, size_t len); - void onewireWrite(onewireDriver *owp, uint8_t *txbuf, - size_t txbytes, systime_t pullup_time); -#if ONEWIRE_USE_SEARCH_ROM - size_t onewireSearchRom(onewireDriver *owp, - uint8_t *result, size_t max_rom_cnt); -#endif /* ONEWIRE_USE_SEARCH_ROM */ -#if ONEWIRE_SYNTH_SEARCH_TEST - void _synth_ow_write_bit(onewireDriver *owp, ioline_t bit); - ioline_t _synth_ow_read_bit(void); - void synthSearchRomTest(onewireDriver *owp); -#endif /* ONEWIRE_SYNTH_SEARCH_TEST */ -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_ONEWIRE */ - -#endif /* HAL_ONEWIRE_H_ */ - -/** @} */ - - - - - - - - - diff --git a/firmware/ChibiOS_16/community/os/hal/include/hal_qei.h b/firmware/ChibiOS_16/community/os/hal/include/hal_qei.h deleted file mode 100644 index d2de6933f0..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/include/hal_qei.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Martino Migliavacca - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_qei.h - * @brief QEI Driver macros and structures. - * - * @addtogroup QEI - * @{ - */ - -#ifndef HAL_QEI_H -#define HAL_QEI_H - -#if (HAL_USE_QEI == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - QEI_UNINIT = 0, /**< Not initialized. */ - QEI_STOP = 1, /**< Stopped. */ - QEI_READY = 2, /**< Ready. */ - QEI_ACTIVE = 3, /**< Active. */ -} qeistate_t; - -/** - * @brief Type of a structure representing an QEI driver. - */ -typedef struct QEIDriver QEIDriver; - -/** - * @brief QEI notification callback type. - * - * @param[in] qeip pointer to a @p QEIDriver object - */ -typedef void (*qeicallback_t)(QEIDriver *qeip); - -/** - * @brief Driver possible handling of counter overflow/underflow. - * - * @details When counter is going to overflow, the new value is - * computed according to this mode in such a way that - * the counter will either wrap around, stay unchange - * or reach min/max - * - * @note All driver implementation should support the - * QEI_OVERFLOW_WRAP mode. - * - * @note Mode QEI_OVERFLOW_DISCARD and QEI_OVERFLOW_MINMAX are included - * if QEI_USE_OVERFLOW_DISCARD and QEI_USE_OVERFLOW_MINMAX are - * set to TRUE in halconf_community.h and are not necessary supported - * by all drivers - */ -typedef enum { - QEI_OVERFLOW_WRAP = 0, /**< Counter value will wrap around. */ -#if QEI_USE_OVERFLOW_DISCARD == TRUE - QEI_OVERFLOW_DISCARD = 1, /**< Counter doesn't change. */ -#endif -#if QEI_USE_OVERFLOW_MINMAX == TRUE - QEI_OVERFLOW_MINMAX = 2, /**< Counter will be updated upto min or max.*/ -#endif -} qeioverflow_t; - - -#include "hal_qei_lld.h" - - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Enables the input capture. - * - * @param[in] qeip pointer to the @p QEIDriver object - * - * @iclass - */ -#define qeiEnableI(qeip) qei_lld_enable(qeip) - -/** - * @brief Disables the input capture. - * - * @param[in] qeip pointer to the @p QEIDriver object - * - * @iclass - */ -#define qeiDisableI(qeip) qei_lld_disable(qeip) - -/** - * @brief Returns the counter value. - * - * @param[in] qeip pointer to the @p QEIDriver object - * @return The current counter value. - * - * @iclass - */ -#define qeiGetCountI(qeip) qei_lld_get_count(qeip) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void qeiInit(void); - void qeiObjectInit(QEIDriver *qeip); - void qeiStart(QEIDriver *qeip, const QEIConfig *config); - void qeiStop(QEIDriver *qeip); - void qeiEnable(QEIDriver *qeip); - void qeiDisable(QEIDriver *qeip); - qeicnt_t qeiGetCount(QEIDriver *qeip); - qeidelta_t qeiUpdate(QEIDriver *qeip); - qeidelta_t qeiUpdateI(QEIDriver *qeip); - qeidelta_t qeiAdjustI(QEIDriver *qeip, qeidelta_t delta); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_QEI == TRUE */ - -#endif /* HAL_QEI_H */ - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/hal/include/hal_rng.h b/firmware/ChibiOS_16/community/os/hal/include/hal_rng.h deleted file mode 100644 index dc146c7253..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/include/hal_rng.h +++ /dev/null @@ -1,136 +0,0 @@ -/* - RNG for ChibiOS - Copyright (C) 2016 Stephane D'Alu - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef HAL_RNG_H_ -#define HAL_RNG_H_ - -#if (HAL_USE_RNG == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ - -/** - * @brief Enables the @p rngAcquireBus() and @p rngReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(RNG_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define RNG_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - RNG_UNINIT, /* Not initialized. */ - RNG_STOP, /* Stopped. */ - RNG_READY, /* Ready. */ -} rngstate_t; - -#include "hal_rng_lld.h" - - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Low level driver helper macros - * @{ - */ - -/** - * @brief Wakes up the waiting thread. - * - * @param[in] rngp pointer to the @p RNGDriver object - * - * @notapi - */ -#define _rng_wakeup_isr(rngp) { \ - osalSysLockFromISR(); \ - osalThreadResumeI(&(rngp)->thread, MSG_OK); \ - osalSysUnlockFromISR(); \ -} - -/** - * @brief Common ISR code. - * @details This code handles the portable part of the ISR code: - * - Callback invocation. - * - Waiting thread wakeup, if any. - * - Driver state transitions. - * . - * @note This macro is meant to be used in the low level drivers - * implementation only. - * - * @param[in] rngp pointer to the @p RNGDriver object - * - * @notapi - */ -#define _rng_isr_code(rngp, rng) { \ - if ((rngp)->config->end_cb) { \ - (rngp)->state = RNG_COMPLETE; \ - (rngp)->config->end_cb(rngp, rng); \ - if ((rngp)->state == RNG_COMPLETE) \ - (rngp)->state = RNG_READY; \ - } \ - else \ - (rngp)->state = RNG_READY; \ - _rng_wakeup_isr(rngp); \ -} - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void rngInit(void); - void rngObjectInit(RNGDriver *rngp); - void rngStart(RNGDriver *rngp, const RNGConfig *config); - void rngStop(RNGDriver *rngp); - msg_t rngWriteI(RNGDriver *rngp, uint8_t *buf, size_t n, systime_t timeout); - msg_t rngWrite(RNGDriver *rngp, uint8_t *buf, size_t n, systime_t timeout); -#if RNG_USE_MUTUAL_EXCLUSION == TRUE - void rngAcquireUnit(RNGDriver *rngp); - void rngReleaseUnit(RNGDriver *rngp); -#endif -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_RNG */ - -#endif /* HAL_RNG_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/hal/include/hal_timcap.h b/firmware/ChibiOS_16/community/os/hal/include/hal_timcap.h deleted file mode 100644 index 61c7fc5dfc..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/include/hal_timcap.h +++ /dev/null @@ -1,206 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file hal_timcap.h - * @brief TIMCAP Driver macros and structures. - * - * @addtogroup TIMCAP - * @{ - */ - -#ifndef HAL_TIMCAP_H_ -#define HAL_TIMCAP_H_ - -#include "ch.h" -#include "hal.h" - -#if (HAL_USE_TIMCAP == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - TIMCAP_UNINIT = 0, /**< Not initialized. */ - TIMCAP_STOP = 1, /**< Stopped. */ - TIMCAP_READY = 2, /**< Ready. */ - TIMCAP_WAITING = 3, /**< Waiting first edge. */ - TIMCAP_ACTIVE = 4, /**< Active cycle phase. */ - TIMCAP_IDLE = 5, /**< Idle cycle phase. */ -} timcapstate_t; - -/** - * @brief Type of a structure representing an TIMCAP driver. - */ -typedef struct TIMCAPDriver TIMCAPDriver; - - -/** - * @brief TIMCAP notification callback type. - * - * @param[in] timcapp pointer to a @p TIMCAPDriver object - */ -typedef void (*timcapcallback_t)(TIMCAPDriver *timcapp); - -#include "hal_timcap_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Enables the input capture. - * - * @param[in] timcapp pointer to the @p TIMCAPDriver object - * - * @iclass - */ -#define timcapEnableI(timcapp) timcap_lld_enable(timcapp) - -/** - * @brief Disables the input capture. - * - * @param[in] timcapp pointer to the @p TIMCAPDriver object - * - * @iclass - */ -#define timcapDisableI(timcapp) timcap_lld_disable(timcapp) - - - - -/** @} */ - -/** - * @name Low Level driver helper macros - * @{ - */ - - -/** - * @brief Common ISR code, TIMCAP channel 1 event. - * - * @param[in] timcapp pointer to the @p TIMCAPDriver object - * - * @notapi - */ -#define _timcap_isr_invoke_channel1_cb(timcapp) { \ - timcapstate_t previous_state = (timcapp)->state; \ - (timcapp)->state = TIMCAP_ACTIVE; \ - if (previous_state != TIMCAP_WAITING) \ - (timcapp)->config->capture_cb_array[0](timcapp); \ -} - -/** - * @brief Common ISR code, TIMCAP channel 2 event. - * - * @param[in] timcapp pointer to the @p TIMCAPDriver object - * - * @notapi - */ -#define _timcap_isr_invoke_channel2_cb(timcapp) { \ - timcapstate_t previous_state = (timcapp)->state; \ - (timcapp)->state = TIMCAP_ACTIVE; \ - if (previous_state != TIMCAP_WAITING) \ - (timcapp)->config->capture_cb_array[1](timcapp); \ -} - -/** - * @brief Common ISR code, TIMCAP channel 3 event. - * - * @param[in] timcapp pointer to the @p TIMCAPDriver object - * - * @notapi - */ -#define _timcap_isr_invoke_channel3_cb(timcapp) { \ - timcapstate_t previous_state = (timcapp)->state; \ - (timcapp)->state = TIMCAP_ACTIVE; \ - if (previous_state != TIMCAP_WAITING) \ - (timcapp)->config->capture_cb_array[2](timcapp); \ -} - -/** - * @brief Common ISR code, TIMCAP channel 4 event. - * - * @param[in] timcapp pointer to the @p TIMCAPDriver object - * - * @notapi - */ -#define _timcap_isr_invoke_channel4_cb(timcapp) { \ - timcapstate_t previous_state = (timcapp)->state; \ - (timcapp)->state = TIMCAP_ACTIVE; \ - if (previous_state != TIMCAP_WAITING) \ - (timcapp)->config->capture_cb_array[3](timcapp); \ -} - -/** - * @brief Common ISR code, TIMCAP timer overflow event. - * - * @param[in] timcapp pointer to the @p TIMCAPDriver object - * - * @notapi - */ -#define _timcap_isr_invoke_overflow_cb(timcapp) { \ - (timcapp)->config->overflow_cb(timcapp); \ -} -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void timcapInit(void); - void timcapObjectInit(TIMCAPDriver *timcapp); - void timcapStart(TIMCAPDriver *timcapp, const TIMCAPConfig *config); - void timcapStop(TIMCAPDriver *timcapp); - void timcapEnable(TIMCAPDriver *timcapp); - void timcapDisable(TIMCAPDriver *timcapp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_TIMCAP */ - -#endif /* HAL_TIMCAP_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/hal/include/hal_usb_hid.h b/firmware/ChibiOS_16/community/os/hal/include/hal_usb_hid.h deleted file mode 100644 index 7698a083e9..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/include/hal_usb_hid.h +++ /dev/null @@ -1,571 +0,0 @@ -/* - ChibiOS - Copyright (C) 2016 Jonathan Struebel - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_usb_hid.h - * @brief USB HID macros and structures. - * - * @addtogroup USB_HID - * @{ - */ - -#ifndef HAL_USB_HID_H -#define HAL_USB_HID_H - -#if (HAL_USE_USB_HID == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name HID specific messages. - * @{ - */ -#define HID_GET_REPORT 0x01U -#define HID_GET_IDLE 0x02U -#define HID_GET_PROTOCOL 0x03U -#define HID_SET_REPORT 0x09U -#define HID_SET_IDLE 0x0AU -#define HID_SET_PROTOCOL 0x0BU -/** @} */ - -/** - * @name HID classes - * @{ - */ -#define HID_INTERFACE_CLASS 0x03U -/** @} */ - -/** - * @name HID subclasses - * @{ - */ -#define HID_BOOT_INTERFACE 0x01U -/** @} */ - -/** - * @name HID descriptors - * @{ - */ -#define USB_DESCRIPTOR_HID 0x21U -#define HID_REPORT 0x22U -#define HID_PHYSICAL 0x23U -/** @} */ - -/** - * @name HID Report items - * @{ - */ -#define HID_REPORT_INPUT 0x80 -#define HID_REPORT_OUTPUT 0x90 -#define HID_REPORT_COLLECTION 0xA0 -#define HID_REPORT_FEATURE 0xB0 -#define HID_REPORT_END_COLLECTION 0xC0 - -#define HID_REPORT_USAGE_PAGE 0x04 -#define HID_REPORT_LOGICAL_MINIMUM 0x14 -#define HID_REPORT_LOGICAL_MAXIMUM 0x24 -#define HID_REPORT_PHYSICAL_MINIMUM 0x34 -#define HID_REPORT_PHYSICAL_MAXIMUM 0x44 -#define HID_REPORT_UNIT_EXPONENT 0x54 -#define HID_REPORT_UNIT 0x64 -#define HID_REPORT_REPORT_SIZE 0x74 -#define HID_REPORT_REPORT_ID 0x84 -#define HID_REPORT_REPORT_COUNT 0x94 -#define HID_REPORT_REPORT_PUSH 0xA4 -#define HID_REPORT_REPORT_POP 0xB4 - -#define HID_REPORT_USAGE 0x08 -#define HID_REPORT_USAGE_MINIMUM 0x18 -#define HID_REPORT_USAGE_MAXIMUM 0x28 -#define HID_REPORT_DESIGNATOR_INDEX 0x38 -#define HID_REPORT_DESIGNATOR_MINUMUM 0x48 -#define HID_REPORT_DESIGNATOR_MAXIMUM 0x58 -#define HID_REPORT_STRING_INDEX 0x78 -#define HID_REPORT_STRING_MINUMUM 0x88 -#define HID_REPORT_STRING_MAXIMUM 0x98 -#define HID_REPORT_DELIMITER 0xA8 -/** @} */ - -/** - * @name HID Collection item definitions - * @{ - */ -#define HID_COLLECTION_PHYSICAL 0x00 -#define HID_COLLECTION_APPLICATION 0x01 -#define HID_COLLECTION_LOGICAL 0x02 -#define HID_COLLECTION_REPORT 0x03 -#define HID_COLLECTION_NAMED_ARRAY 0x04 -#define HID_COLLECTION_USAGE_SWITCH 0x05 -#define HID_COLLECTION_USAGE_MODIFIER 0x06 -/** @} */ - -/** - * @name HID Usage Page item definitions - * @{ - */ -#define HID_USAGE_PAGE_GENERIC_DESKTOP 0x01 -#define HID_USAGE_PAGE_SIMULATION 0x02 -#define HID_USAGE_PAGE_VR 0x03 -#define HID_USAGE_PAGE_SPORT 0x04 -#define HID_USAGE_PAGE_GAME 0x05 -#define HID_USAGE_PAGE_GENERIC_DEVICE 0x06 -#define HID_USAGE_PAGE_KEYBOARD_KEYPAD 0x07 -#define HID_USAGE_PAGE_LEDS 0x08 -#define HID_USAGE_PAGE_BUTTON 0x09 -#define HID_USAGE_PAGE_ORDINAL 0x0A -#define HID_USAGE_PAGE_TELEPHONY 0x0B -#define HID_USAGE_PAGE_CONSUMER 0x0C -#define HID_USAGE_PAGE_DIGITIZER 0x0D -#define HID_USAGE_PAGE_PID 0x0F -#define HID_USAGE_PAGE_UNICODE 0x10 -#define HID_USAGE_PAGE_VENDOR 0xFF00 -/** @} */ - -/** - * @name HID Usage item definitions - * @{ - */ -#define HID_USAGE_ALPHANUMERIC_DISPLAY 0x14 -#define HID_USAGE_MEDICAL_INSTRUMENTS 0x40 -#define HID_USAGE_MONITOR_PAGE1 0x80 -#define HID_USAGE_MONITOR_PAGE2 0x81 -#define HID_USAGE_MONITOR_PAGE3 0x82 -#define HID_USAGE_MONITOR_PAGE4 0x83 -#define HID_USAGE_POWER_PAGE1 0x84 -#define HID_USAGE_POWER_PAGE2 0x85 -#define HID_USAGE_POWER_PAGE3 0x86 -#define HID_USAGE_POWER_PAGE4 0x87 -#define HID_USAGE_BAR_CODE_SCANNER_PAGE 0x8C -#define HID_USAGE_SCALE_PAGE 0x8D -#define HID_USAGE_MSR_PAGE 0x8E -#define HID_USAGE_CAMERA_PAGE 0x90 -#define HID_USAGE_ARCADE_PAGE 0x91 - -#define HID_USAGE_POINTER 0x01 -#define HID_USAGE_MOUSE 0x02 -#define HID_USAGE_JOYSTICK 0x04 -#define HID_USAGE_GAMEPAD 0x05 -#define HID_USAGE_KEYBOARD 0x06 -#define HID_USAGE_KEYPAD 0x07 -#define HID_USAGE_MULTIAXIS_CONTROLLER 0x08 - -#define HID_USAGE_BUTTON1 0x01 -#define HID_USAGE_BUTTON2 0x02 -#define HID_USAGE_BUTTON3 0x03 -#define HID_USAGE_BUTTON4 0x04 -#define HID_USAGE_BUTTON5 0x05 -#define HID_USAGE_BUTTON6 0x06 -#define HID_USAGE_BUTTON7 0x07 -#define HID_USAGE_BUTTON8 0x08 - -#define HID_USAGE_X 0x30 -#define HID_USAGE_Y 0x31 -#define HID_USAGE_Z 0x32 -#define HID_USAGE_RX 0x33 -#define HID_USAGE_RY 0x34 -#define HID_USAGE_RZ 0x35 -#define HID_USAGE_VX 0x40 -#define HID_USAGE_VY 0x41 -#define HID_USAGE_VZ 0x42 -#define HID_USAGE_VBRX 0x43 -#define HID_USAGE_VBRY 0x44 -#define HID_USAGE_VBRZ 0x45 -#define HID_USAGE_VNO 0x46 -/** @} */ - -/** - * @name HID item types definitions - * @{ - */ -#define HID_ITEM_DATA 0x00 -#define HID_ITEM_CNST 0x01 -#define HID_ITEM_ARR 0x00 -#define HID_ITEM_VAR 0x02 -#define HID_ITEM_ABS 0x00 -#define HID_ITEM_REL 0x04 -#define HID_ITEM_NWRP 0x00 -#define HID_ITEM_WRP 0x08 -#define HID_ITEM_LIN 0x00 -#define HID_ITEM_NLIN 0x10 -#define HID_ITEM_PRF 0x00 -#define HID_ITEM_NPRF 0x20 -#define HID_ITEM_NNUL 0x00 -#define HID_ITEM_NUL 0x40 -#define HID_ITEM_NVOL 0x00 -#define HID_ITEM_VOL 0x80 - -#define HID_ITEM_DATA_VAR_ABS (HID_ITEM_DATA | \ - HID_ITEM_VAR | \ - HID_ITEM_ABS) -#define HID_ITEM_CNST_VAR_ABS (HID_ITEM_CNST | \ - HID_ITEM_VAR | \ - HID_ITEM_ABS) -#define HID_ITEM_DATA_VAR_REL (HID_ITEM_DATA | \ - HID_ITEM_VAR | \ - HID_ITEM_REL) -/** @} */ - -/** - * @name Helper macros for USB HID descriptors - * @{ - */ -/* - * @define HID Descriptor size. - */ -#define USB_DESC_HID_SIZE 9U - -/** - * @brief HID Descriptor helper macro. - * @note This macro can only be used with a single HID report descriptor - */ -#define USB_DESC_HID(bcdHID, bCountryCode, bNumDescriptors, \ - bDescriptorType, wDescriptorLength) \ - USB_DESC_BYTE(USB_DESC_HID_SIZE), \ - USB_DESC_BYTE(USB_DESCRIPTOR_HID), \ - USB_DESC_BCD(bcdHID), \ - USB_DESC_BYTE(bCountryCode), \ - USB_DESC_BYTE(bNumDescriptors), \ - USB_DESC_BYTE(bDescriptorType), \ - USB_DESC_WORD(wDescriptorLength) - -/** - * @brief HID Report item helper macro (Single byte). - */ -#define HID_ITEM_B(id, value) \ - USB_DESC_BYTE(id | 0x01), \ - USB_DESC_BYTE(value) - -/** - * @brief HID Report item helper macro (Double byte). - */ -#define HID_ITEM_W(id, value) \ - USB_DESC_BYTE(id | 0x02), \ - USB_DESC_WORD(value) - -/** - * @brief HID Report Usage Page item helper macro (Single byte). - */ -#define HID_USAGE_PAGE_B(up) \ - HID_ITEM_B(HID_REPORT_USAGE_PAGE, up) - -/** - * @brief HID Report Usage Page item helper macro (Double byte). - */ -#define HID_USAGE_PAGE_W(up) \ - HID_ITEM_W(HID_REPORT_USAGE_PAGE, up) - -/** - * @brief HID Report Usage item helper macro (Single byte). - */ -#define HID_USAGE_B(u) \ - HID_ITEM_B(HID_REPORT_USAGE, u) - -/** - * @brief HID Report Usage item helper macro (Double byte). - */ -#define HID_USAGE_W(u) \ - HID_ITEM_W(HID_REPORT_USAGE, u) - -/** - * @brief HID Report Collection item helper macro (Single Byte). - */ -#define HID_COLLECTION_B(c) \ - HID_ITEM_B(HID_REPORT_COLLECTION, c) - -/** - * @brief HID Report Collection item helper macro (Double Byte). - */ -#define HID_COLLECTION_W(c) \ - HID_ITEM_W(HID_REPORT_COLLECTION, c) - -/** - * @brief HID Report End Collection item helper macro. - */ -#define HID_END_COLLECTION \ - USB_DESC_BYTE(HID_REPORT_END_COLLECTION) - -/** - * @brief HID Report Usage Minimum item helper macro (Single byte). - */ -#define HID_USAGE_MINIMUM_B(x) \ - HID_ITEM_B(HID_REPORT_USAGE_MINIMUM, x) - -/** - * @brief HID Report Usage Minimum item helper macro (Double byte). - */ -#define HID_USAGE_MINIMUM_W(x) \ - HID_ITEM_W(HID_REPORT_USAGE_MINIMUM, x) - -/** - * @brief HID Report Usage Maximum item helper macro (Single byte). - */ -#define HID_USAGE_MAXIMUM_B(x) \ - HID_ITEM_B(HID_REPORT_USAGE_MAXIMUM, x) - -/** - * @brief HID Report Usage Maximum item helper macro (Double byte). - */ -#define HID_USAGE_MAXIMUM_W(x) \ - HID_ITEM_W(HID_REPORT_USAGE_MAXIMUM, x) - -/** - * @brief HID Report Logical Minimum item helper macro (Single byte). - */ -#define HID_LOGICAL_MINIMUM_B(x) \ - HID_ITEM_B(HID_REPORT_LOGICAL_MINIMUM, x) - -/** - * @brief HID Report Logical Minimum item helper macro (Double byte). - */ -#define HID_LOGICAL_MINIMUM_W(x) \ - HID_ITEM_W(HID_REPORT_LOGICAL_MINIMUM, x) - -/** - * @brief HID Report Logical Maximum item helper macro (Single byte). - */ -#define HID_LOGICAL_MAXIMUM_B(x) \ - HID_ITEM_B(HID_REPORT_LOGICAL_MAXIMUM, x) - -/** - * @brief HID Report Logical Maximum item helper macro (Double byte). - */ -#define HID_LOGICAL_MAXIMUM_W(x) \ - HID_ITEM_W(HID_REPORT_LOGICAL_MAXIMUM, x) - -/** - * @brief HID Report ID item helper macro (Single byte). - */ -#define HID_REPORT_ID_B(x) \ - HID_ITEM_B(HID_REPORT_REPORT_ID, x) - -/** - * @brief HID Report ID item helper macro (Double byte). - */ -#define HID_REPORT_ID_W(x) \ - HID_ITEM_W(HID_REPORT_REPORT_ID, x) - -/** - * @brief HID Report Count item helper macro (Single byte). - */ -#define HID_REPORT_COUNT_B(x) \ - HID_ITEM_B(HID_REPORT_REPORT_COUNT, x) - -/** - * @brief HID Report Count item helper macro (Double byte). - */ -#define HID_REPORT_COUNT_W(x) \ - HID_ITEM_W(HID_REPORT_REPORT_COUNT, x) - -/** - * @brief HID Report Size item helper macro (Single byte). - */ -#define HID_REPORT_SIZE_B(x) \ - HID_ITEM_B(HID_REPORT_REPORT_SIZE, x) - -/** - * @brief HID Report Size item helper macro (Double byte). - */ -#define HID_REPORT_SIZE_W(x) \ - HID_ITEM_W(HID_REPORT_REPORT_SIZE, x) - -/** - * @brief HID Report Input item helper macro (Single byte). - */ -#define HID_INPUT_B(x) \ - HID_ITEM_B(HID_REPORT_INPUT, x) - -/** - * @brief HID Report Input item helper macro (Double byte). - */ -#define HID_INPUT_W(x) \ - HID_ITEM_W(HID_REPORT_INPUT, x) -/** @} */ - -/** - * @brief HID Report Output item helper macro (Single byte). - */ -#define HID_OUTPUT_B(x) \ - HID_ITEM_B(HID_REPORT_OUTPUT, x) - -/** - * @brief HID Report Output item helper macro (Double byte). - */ -#define HID_OUTPUT_W(x) \ - HID_ITEM_W(HID_REPORT_OUTPUT, x) -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name USB HID configuration options - * @{ - */ -/** - * @brief USB HID buffers size. - * @details Configuration parameter, the buffer size must be a multiple of - * the USB data endpoint maximum packet size. - * @note The default is 256 bytes for both the transmission and receive - * buffers. - */ -#if !defined(USB_HID_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define USB_HID_BUFFERS_SIZE 256 -#endif - -/** - * @brief USB HID number of buffers. - * @note The default is 2 buffers. - */ -#if !defined(USB_HID_BUFFERS_NUMBER) || defined(__DOXYGEN__) -#define USB_HID_BUFFERS_NUMBER 2 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if HAL_USE_USB == FALSE -#error "USB HID Driver requires HAL_USE_USB" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - HID_UNINIT = 0, /**< Not initialized. */ - HID_STOP = 1, /**< Stopped. */ - HID_READY = 2 /**< Ready. */ -} hidstate_t; - -/** - * @brief Structure representing a USB HID driver. - */ -typedef struct USBHIDDriver USBHIDDriver; - -/** - * @brief USB HID Driver configuration structure. - * @details An instance of this structure must be passed to @p hidStart() - * in order to configure and start the driver operations. - */ -typedef struct { - /** - * @brief USB driver to use. - */ - USBDriver *usbp; - /** - * @brief Interrupt IN endpoint used for outgoing data transfer. - */ - usbep_t int_in; - /** - * @brief Interrupt OUT endpoint used for incoming data transfer. - */ - usbep_t int_out; -} USBHIDConfig; - -/** - * @brief @p USBHIDDriver specific data. - */ -#define _usb_hid_driver_data \ - _base_asynchronous_channel_data \ - /* Driver state.*/ \ - hidstate_t state; \ - /* Input buffers queue.*/ \ - input_buffers_queue_t ibqueue; \ - /* Output queue.*/ \ - output_buffers_queue_t obqueue; \ - /* Input buffer.*/ \ - uint8_t ib[BQ_BUFFER_SIZE(USB_HID_BUFFERS_NUMBER, \ - USB_HID_BUFFERS_SIZE)]; \ - /* Output buffer.*/ \ - uint8_t ob[BQ_BUFFER_SIZE(USB_HID_BUFFERS_NUMBER, \ - USB_HID_BUFFERS_SIZE)]; \ - /* End of the mandatory fields.*/ \ - /* Current configuration data.*/ \ - const USBHIDConfig *config; - -/** - * @brief @p USBHIDDriver specific methods. - */ -#define _usb_hid_driver_methods \ - _base_asynchronous_channel_methods \ - /* Buffer flush method.*/ \ - void (*flush)(void *instance); - -/** - * @extends BaseAsynchronousChannelVMT - * - * @brief @p USBHIDDriver virtual methods table. - */ -struct USBHIDDriverVMT { - _usb_hid_driver_methods -}; - -/** - * @extends BaseAsynchronousChannel - * - * @brief Full duplex USB HID driver class. - * @details This class extends @p BaseAsynchronousChannel by adding physical - * I/O queues. - */ -struct USBHIDDriver { - /** @brief Virtual Methods Table.*/ - const struct USBHIDDriverVMT *vmt; - _usb_hid_driver_data -}; - -#define USB_DRIVER_EXT_FIELDS \ - USBHIDDriver hid - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ -#ifdef __cplusplus -extern "C" { -#endif - void hidInit(void); - void hidObjectInit(USBHIDDriver *uhdp); - void hidStart(USBHIDDriver *uhdp, const USBHIDConfig *config); - void hidStop(USBHIDDriver *uhdp); - void hidDisconnectI(USBHIDDriver *uhdp); - void hidConfigureHookI(USBHIDDriver *uhdp); - bool hidRequestsHook(USBDriver *usbp); - void hidDataTransmitted(USBDriver *usbp, usbep_t ep); - void hidDataReceived(USBDriver *usbp, usbep_t ep); - size_t hidWriteReport(USBHIDDriver *uhdp, uint8_t *bp, size_t n); - size_t hidWriteReportt(USBHIDDriver *uhdp, uint8_t *bp, size_t n, systime_t timeout); - size_t hidReadReport(USBHIDDriver *uhdp, uint8_t *bp, size_t n); - size_t hidReadReportt(USBHIDDriver *uhdp, uint8_t *bp, size_t n, systime_t timeout); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_USB_HID */ - -#endif /* HAL_USB_HID_H */ - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/hal/include/hal_usb_msd.h b/firmware/ChibiOS_16/community/os/hal/include/hal_usb_msd.h deleted file mode 100644 index fcc2cf2897..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/include/hal_usb_msd.h +++ /dev/null @@ -1,195 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2016 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_usb_msd.h - * @brief USM mass storage device driver macros and structures. - * - * @addtogroup usb_msd - * @{ - */ - -#ifndef HAL_USB_MSD_H -#define HAL_USB_MSD_H - -#if (HAL_USE_USB_MSD == TRUE) || defined(__DOXYGEN__) - -#include "lib_scsi.h" - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#define USB_MSD_DATA_EP 0x01 - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !HAL_USE_USB -#error "Mass storage Driver requires HAL_USE_USB" -#endif - -#if !USB_USE_WAIT -#error "Mass storage Driver requires USB_USE_WAIT" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a structure representing an USB mass storage driver. - */ -typedef struct USBMassStorageDriver USBMassStorageDriver; - -/** - * @brief Type of a driver state machine possible states. - */ -typedef enum { - USB_MSD_UNINIT = 0, - USB_MSD_STOP, - USB_MSD_READY, -} usbmsdstate_t; - -/** - * @brief Represents command block wrapper structure. - * @details See USB Mass Storage Class Specification. - */ -typedef struct PACKED_VAR { - uint32_t signature; - uint32_t tag; - uint32_t data_len; - uint8_t flags; - uint8_t lun; - uint8_t cmd_len; - uint8_t cmd_data[16]; -} msd_cbw_t; - -/** - * @brief Represents command status wrapper structure. - * @details See USB Mass Storage Class Specification. - */ -typedef struct PACKED_VAR { - uint32_t signature; - uint32_t tag; - uint32_t data_residue; - uint8_t status; -} msd_csw_t; - -/** - * @brief Transport handler passed to SCSI layer. - */ -typedef struct { - /** - * @brief Pointer to the @p USBDriver object. - */ - USBDriver *usbp; - /** - * @brief USB endpoint number. - */ - usbep_t ep; -} usb_scsi_transport_handler_t; - - -/** - * @brief Structure representing an USB mass storage driver. - */ -struct USBMassStorageDriver { - /** - * @brief Pointer to the @p USBDriver object. - */ - USBDriver *usbp; - /** - * @brief Driver state. - */ - usbmsdstate_t state; - /** - * @brief CBW structure. - */ - msd_cbw_t cbw; - /** - * @brief CSW structure. - */ - msd_csw_t csw; - /** - * @brief Thread working area. - */ - THD_WORKING_AREA( waMSDWorker, 512); - /** - * @brief Worker thread handler. - */ - thread_reference_t worker; - /** - * @brief SCSI target driver structure. - */ - SCSITarget scsi_target; - /** - * @brief SCSI target configuration structure. - */ - SCSITargetConfig scsi_config; - /** - * @brief SCSI transport structure. - */ - SCSITransport scsi_transport; - /** - * @brief SCSI over USB transport handler structure. - */ - usb_scsi_transport_handler_t usb_scsi_transport_handler; -}; - - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -extern USBMassStorageDriver USBMSD1; - -#ifdef __cplusplus -extern "C" { -#endif - void msdObjectInit(USBMassStorageDriver *msdp); - void msdStart(USBMassStorageDriver *msdp, USBDriver *usbp, - BaseBlockDevice *blkdev, uint8_t *blkbuf, - const scsi_inquiry_response_t *scsi_inquiry_response); - void msdStop(USBMassStorageDriver *msdp); - bool msd_request_hook(USBDriver *usbp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_USB_MSD */ - -#endif /* HAL_USB_MSD_H */ - -/** @} */ - - - - - - - - - diff --git a/firmware/ChibiOS_16/community/os/hal/include/hal_usbh.h b/firmware/ChibiOS_16/community/os/hal/include/hal_usbh.h deleted file mode 100644 index 63be93e71b..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/include/hal_usbh.h +++ /dev/null @@ -1,436 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail) - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef HAL_USBH_H_ -#define HAL_USBH_H_ - -#include "hal.h" - - -#ifndef HAL_USBH_USE_FTDI -#define HAL_USBH_USE_FTDI FALSE -#endif - -#ifndef HAL_USBH_USE_HUB -#define HAL_USBH_USE_HUB FALSE -#endif - -#ifndef HAL_USBH_USE_MSD -#define HAL_USBH_USE_MSD FALSE -#endif - -#ifndef HAL_USBH_USE_UVC -#define HAL_USBH_USE_UVC FALSE -#endif - -#if (HAL_USE_USBH == TRUE) || defined(__DOXYGEN__) - -#include "osal.h" -#include "usbh/list.h" -#include "usbh/defs.h" - -/* TODO: - * - * - Integrate VBUS power switching functionality to the API. - * - */ - - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !HAL_USBH_USE_HUB -#define USBH_MAX_ADDRESSES 1 -#else -#define USBH_MAX_ADDRESSES (HAL_USBHHUB_MAX_PORTS + 1) -#endif - -enum usbh_status { - USBH_STATUS_STOPPED = 0, - USBH_STATUS_STARTED, - USBH_STATUS_SUSPENDED, -}; - -enum usbh_devstatus { - USBH_DEVSTATUS_DISCONNECTED = 0, - USBH_DEVSTATUS_ATTACHED, - USBH_DEVSTATUS_CONNECTED, - USBH_DEVSTATUS_DEFAULT, - USBH_DEVSTATUS_ADDRESS, - USBH_DEVSTATUS_CONFIGURED, -}; - -enum usbh_devspeed { - USBH_DEVSPEED_LOW = 0, - USBH_DEVSPEED_FULL, - USBH_DEVSPEED_HIGH, -}; - -enum usbh_epdir { - USBH_EPDIR_IN = 0x80, - USBH_EPDIR_OUT = 0 -}; - -enum usbh_eptype { - USBH_EPTYPE_CTRL = 0, - USBH_EPTYPE_ISO = 1, - USBH_EPTYPE_BULK = 2, - USBH_EPTYPE_INT = 3, -}; - -enum usbh_epstatus { - USBH_EPSTATUS_UNINITIALIZED = 0, - USBH_EPSTATUS_CLOSED, - USBH_EPSTATUS_OPEN, - USBH_EPSTATUS_HALTED, -}; - -enum usbh_urbstatus { - USBH_URBSTATUS_UNINITIALIZED = 0, - USBH_URBSTATUS_INITIALIZED, - USBH_URBSTATUS_PENDING, -// USBH_URBSTATUS_QUEUED, - USBH_URBSTATUS_ERROR, - USBH_URBSTATUS_TIMEOUT, - USBH_URBSTATUS_CANCELLED, - USBH_URBSTATUS_STALL, - USBH_URBSTATUS_DISCONNECTED, -// USBH_URBSTATUS_EPCLOSED, - USBH_URBSTATUS_OK, -}; - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/* forward declarations */ -typedef struct USBHDriver USBHDriver; -typedef struct usbh_port usbh_port_t; -typedef struct usbh_device usbh_device_t; -typedef struct usbh_ep usbh_ep_t; -typedef struct usbh_urb usbh_urb_t; -typedef struct usbh_baseclassdriver usbh_baseclassdriver_t; -typedef struct usbh_classdriverinfo usbh_classdriverinfo_t; -#if HAL_USBH_USE_HUB -typedef struct USBHHubDriver USBHHubDriver; -#endif - -/* typedefs */ -typedef enum usbh_status usbh_status_t; -typedef enum usbh_devspeed usbh_devspeed_t; -typedef enum usbh_devstatus usbh_devstatus_t; -typedef enum usbh_epdir usbh_epdir_t; -typedef enum usbh_eptype usbh_eptype_t; -typedef enum usbh_epstatus usbh_epstatus_t; -typedef enum usbh_urbstatus usbh_urbstatus_t; -typedef uint16_t usbh_portstatus_t; -typedef uint16_t usbh_portcstatus_t; -typedef void (*usbh_completion_cb)(usbh_urb_t *); - -/* include the low level driver; the required definitions are above */ -#include "hal_usbh_lld.h" - -#define USBH_DEFINE_BUFFER(type, name) USBH_LLD_DEFINE_BUFFER(type, name) - -struct usbh_urb { - usbh_ep_t *ep; - - void *userData; - usbh_completion_cb callback; - - const void *setup_buff; - void *buff; - uint32_t requestedLength; - uint32_t actualLength; - - usbh_urbstatus_t status; - - thread_reference_t waitingThread; - thread_reference_t abortingThread; - - /* Low level part */ - _usbh_urb_ll_data -}; - -struct usbh_ep { - usbh_device_t *device; - usbh_ep_t *next; - - usbh_epstatus_t status; - uint8_t address; - bool in; - usbh_eptype_t type; - uint16_t wMaxPacketSize; - uint8_t bInterval; - - /* debug */ - const char *name; - - /* Low-level part */ - _usbh_ep_ll_data -}; - -struct usbh_device { - USBHDriver *host; /* shortcut to host */ - - usbh_ep_t ctrl; - usbh_ep_t *endpoints; - - usbh_baseclassdriver_t *drivers; - - uint16_t langID0; - - usbh_devstatus_t status; - usbh_devspeed_t speed; - - USBH_DEFINE_BUFFER(usbh_device_descriptor_t, devDesc); - unsigned char align_bytes[2]; - USBH_DEFINE_BUFFER(usbh_config_descriptor_t, basicConfigDesc); - - uint8_t *fullConfigurationDescriptor; - uint8_t keepFullCfgDesc; - - uint8_t address; - uint8_t bConfiguration; - - /* Low level part */ - _usbh_device_ll_data -}; - - -struct usbh_port { -#if HAL_USBH_USE_HUB - USBHHubDriver *hub; -#endif - - usbh_portstatus_t status; - usbh_portcstatus_t c_status; - - usbh_port_t *next; - - uint8_t number; - - usbh_device_t device; - - /* Low level part */ - _usbh_port_ll_data -}; - -struct USBHDriver { - usbh_status_t status; - uint8_t address_bitmap[(USBH_MAX_ADDRESSES + 7) / 8]; - - usbh_port_t rootport; - -#if HAL_USBH_USE_HUB - struct list_head hubs; -#endif - - /* Low level part */ - _usbhdriver_ll_data - -#if USBH_DEBUG_ENABLE - /* debug */ - uint8_t dbg_buff[USBH_DEBUG_BUFFER]; - THD_WORKING_AREA(waDebug, 512); - input_queue_t iq; -#endif -}; - - - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_USBH_USE_OTG1 -extern USBHDriver USBHD1; -#endif - -#if STM32_USBH_USE_OTG2 -extern USBHDriver USBHD2; -#endif - - -/*===========================================================================*/ -/* Main driver API. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - - /* Main functions */ - void usbhObjectInit(USBHDriver *usbh); - void usbhInit(void); - void usbhStart(USBHDriver *usbh); - void usbhStop(USBHDriver *usbh); - void usbhSuspend(USBHDriver *usbh); - void usbhResume(USBHDriver *usbh); - - /* Device-related */ -#if USBH_DEBUG_ENABLE && USBH_DEBUG_ENABLE_INFO - void usbhDevicePrintInfo(usbh_device_t *dev); - void usbhDevicePrintConfiguration(const uint8_t *descriptor, uint16_t rem); -#else -# define usbhDevicePrintInfo(dev) do {} while(0) -# define usbhDevicePrintConfiguration(descriptor, rem) do {} while(0) -#endif - bool usbhDeviceReadString(usbh_device_t *dev, char *dest, uint8_t size, - uint8_t index, uint16_t langID); - static inline usbh_port_t *usbhDeviceGetPort(usbh_device_t *dev) { - return container_of(dev, usbh_port_t, device); - } - - /* Synchronous API */ - usbh_urbstatus_t usbhBulkTransfer(usbh_ep_t *ep, - void *data, - uint32_t len, - uint32_t *actual_len, - systime_t timeout); - usbh_urbstatus_t usbhControlRequest(usbh_device_t *dev, - uint8_t bmRequestType, - uint8_t bRequest, - uint16_t wValue, - uint16_t wIndex, - uint16_t wLength, - uint8_t *buff); - usbh_urbstatus_t usbhControlRequestExtended(usbh_device_t *dev, - const usbh_control_request_t *req, - uint8_t *buff, - uint32_t *actual_len, - systime_t timeout); - - /* Standard request helpers */ - bool usbhStdReqGetDeviceDescriptor(usbh_device_t *dev, - uint16_t wLength, - uint8_t *buf); - bool usbhStdReqGetConfigurationDescriptor(usbh_device_t *dev, - uint8_t index, - uint16_t wLength, - uint8_t *buf); - bool usbhStdReqGetStringDescriptor(usbh_device_t *dev, - uint8_t index, - uint16_t langID, - uint16_t wLength, - uint8_t *buf); - bool usbhStdReqSetInterface(usbh_device_t *dev, - uint8_t bInterfaceNumber, - uint8_t bAlternateSetting); - bool usbhStdReqGetInterface(usbh_device_t *dev, - uint8_t bInterfaceNumber, - uint8_t *bAlternateSetting); - - /* Endpoint/pipe management */ - void usbhEPObjectInit(usbh_ep_t *ep, usbh_device_t *dev, const usbh_endpoint_descriptor_t *desc); - static inline void usbhEPOpen(usbh_ep_t *ep) { - osalDbgCheck(ep != 0); - osalSysLock(); - osalDbgAssert(ep->status == USBH_EPSTATUS_CLOSED, "invalid state"); - usbh_lld_ep_open(ep); - ep->next = ep->device->endpoints; - ep->device->endpoints = ep; - osalSysUnlock(); - } - static inline void usbhEPCloseS(usbh_ep_t *ep) { - osalDbgCheck(ep != 0); - osalDbgCheckClassS(); - osalDbgAssert(ep->status != USBH_EPSTATUS_UNINITIALIZED, "invalid state"); - if (ep->status == USBH_EPSTATUS_CLOSED) { - osalOsRescheduleS(); - return; - } - usbh_lld_ep_close(ep); - } - static inline void usbhEPClose(usbh_ep_t *ep) { - osalSysLock(); - usbhEPCloseS(ep); - osalSysUnlock(); - } - static inline void usbhEPResetI(usbh_ep_t *ep) { - osalDbgCheckClassI(); - osalDbgCheck(ep != NULL); - usbh_lld_epreset(ep); - } - static inline bool usbhEPIsPeriodic(usbh_ep_t *ep) { - osalDbgCheck(ep != NULL); - return (ep->type & 1) != 0; - } - static inline bool usbhURBIsBusy(usbh_urb_t *urb) { - osalDbgCheck(urb != NULL); - return (urb->status == USBH_URBSTATUS_PENDING); - } - static inline void usbhEPSetName(usbh_ep_t *ep, const char *name) { - ep->name = name; - } - - /* URB management */ - void usbhURBObjectInit(usbh_urb_t *urb, usbh_ep_t *ep, usbh_completion_cb callback, - void *user, void *buff, uint32_t len); - void usbhURBObjectResetI(usbh_urb_t *urb); - void usbhURBSubmitI(usbh_urb_t *urb); - bool usbhURBCancelI(usbh_urb_t *urb); - msg_t usbhURBSubmitAndWaitS(usbh_urb_t *urb, systime_t timeout); - void usbhURBCancelAndWaitS(usbh_urb_t *urb); - msg_t usbhURBWaitTimeoutS(usbh_urb_t *urb, systime_t timeout); - - /* Main loop */ - void usbhMainLoop(USBHDriver *usbh); - -#ifdef __cplusplus -} -#endif - - -/*===========================================================================*/ -/* Class driver definitions and API. */ -/*===========================================================================*/ - -typedef struct usbh_classdriver_vmt usbh_classdriver_vmt_t; -struct usbh_classdriver_vmt { - usbh_baseclassdriver_t *(*load)(usbh_device_t *dev, const uint8_t *descriptor, uint16_t rem); - void (*unload)(usbh_baseclassdriver_t *drv); -}; - -struct usbh_classdriverinfo { - int16_t class; - int16_t subclass; - int16_t protocol; - const char *name; - const usbh_classdriver_vmt_t *vmt; -}; - -#define _usbh_base_classdriver_data \ - const usbh_classdriverinfo_t *info; \ - usbh_device_t *dev; \ - usbh_baseclassdriver_t *next; - -struct usbh_baseclassdriver { - _usbh_base_classdriver_data -}; - - -/*===========================================================================*/ -/* Helper functions. */ -/*===========================================================================*/ -#include /* descriptor iterators */ -#include /* debug */ - -#endif - -#endif /* HAL_USBH_H_ */ diff --git a/firmware/ChibiOS_16/community/os/hal/include/usbh/debug.h b/firmware/ChibiOS_16/community/os/hal/include/usbh/debug.h deleted file mode 100644 index a3c73550e3..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/include/usbh/debug.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail) - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - - -#ifndef USBH_DEBUG_H_ -#define USBH_DEBUG_H_ - -#include "hal_usbh.h" - -#if HAL_USE_USBH - -//TODO: Debug is only for USBHD1, make it generic. - -#if USBH_DEBUG_ENABLE - void usbDbgPrintf(const char *fmt, ...); - void usbDbgPuts(const char *s); - void usbDbgInit(USBHDriver *host); - void usbDbgReset(void); - void usbDbgSystemHalted(void); -#else -#define usbDbgPrintf(fmt, ...) do {} while(0) -#define usbDbgPuts(s) do {} while(0) -#define usbDbgInit(host) do {} while(0) -#define usbDbgReset() do {} while(0) -#define usbDbgSystemHalted() do {} while(0) -#endif - -#endif - -#endif /* USBH_DEBUG_H_ */ diff --git a/firmware/ChibiOS_16/community/os/hal/include/usbh/defs.h b/firmware/ChibiOS_16/community/os/hal/include/usbh/defs.h deleted file mode 100644 index 51463138bf..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/include/usbh/defs.h +++ /dev/null @@ -1,160 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail) - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef USBH_DEFS_H_ -#define USBH_DEFS_H_ - -#include "hal.h" - -#if HAL_USE_USBH - -#include "osal.h" - -#ifdef __IAR_SYSTEMS_ICC__ -#define PACKED_STRUCT typedef PACKED_VAR struct -#else -#define PACKED_STRUCT typedef struct PACKED_VAR -#endif - -PACKED_STRUCT { - uint8_t bLength; - uint8_t bDescriptorType; - uint16_t bcdUSB; - uint8_t bDeviceClass; - uint8_t bDeviceSubClass; - uint8_t bDeviceProtocol; - uint8_t bMaxPacketSize0; - uint16_t idVendor; - uint16_t idProduct; - uint16_t bcdDevice; - uint8_t iManufacturer; - uint8_t iProduct; - uint8_t iSerialNumber; - uint8_t bNumConfigurations; -} usbh_device_descriptor_t; -#define USBH_DT_DEVICE 0x01 -#define USBH_DT_DEVICE_SIZE 18 - -PACKED_STRUCT { - uint8_t bLength; - uint8_t bDescriptorType; - uint16_t wTotalLength; - uint8_t bNumInterfaces; - uint8_t bConfigurationValue; - uint8_t iConfiguration; - uint8_t bmAttributes; - uint8_t bMaxPower; -} usbh_config_descriptor_t; -#define USBH_DT_CONFIG 0x02 -#define USBH_DT_CONFIG_SIZE 9 - -PACKED_STRUCT { - uint8_t bLength; - uint8_t bDescriptorType; - uint16_t wData[1]; -} usbh_string_descriptor_t; -#define USBH_DT_STRING 0x03 -#define USBH_DT_STRING_SIZE 2 - -PACKED_STRUCT { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bInterfaceNumber; - uint8_t bAlternateSetting; - uint8_t bNumEndpoints; - uint8_t bInterfaceClass; - uint8_t bInterfaceSubClass; - uint8_t bInterfaceProtocol; - uint8_t iInterface; -} usbh_interface_descriptor_t; -#define USBH_DT_INTERFACE 0x04 -#define USBH_DT_INTERFACE_SIZE 9 - -PACKED_STRUCT { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bEndpointAddress; - uint8_t bmAttributes; - uint16_t wMaxPacketSize; - uint8_t bInterval; -} usbh_endpoint_descriptor_t; -#define USBH_DT_ENDPOINT 0x05 -#define USBH_DT_ENDPOINT_SIZE 7 - -PACKED_STRUCT { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bFirstInterface; - uint8_t bInterfaceCount; - uint8_t bFunctionClass; - uint8_t bFunctionSubClass; - uint8_t bFunctionProtocol; - uint8_t iFunction; -} usbh_ia_descriptor_t; -#define USBH_DT_INTERFACE_ASSOCIATION 0x0b -#define USBH_DT_INTERFACE_ASSOCIATION_SIZE 8 - -PACKED_STRUCT { - uint8_t bDescLength; - uint8_t bDescriptorType; - uint8_t bNbrPorts; - uint16_t wHubCharacteristics; - uint8_t bPwrOn2PwrGood; - uint8_t bHubContrCurrent; - uint32_t DeviceRemovable; -} usbh_hub_descriptor_t; -#define USBH_DT_HUB 0x29 -#define USBH_DT_HUB_SIZE (7 + 4) - -PACKED_STRUCT { - uint8_t bmRequestType; - uint8_t bRequest; - uint16_t wValue; - uint16_t wIndex; - uint16_t wLength; -} usbh_control_request_t; - - -#define USBH_REQ_GET_STATUS 0x00 -#define USBH_REQ_CLEAR_FEATURE 0x01 -#define USBH_REQ_SET_FEATURE 0x03 -#define USBH_REQ_SET_ADDRESS 0x05 -#define USBH_REQ_GET_DESCRIPTOR 0x06 -#define USBH_REQ_SET_DESCRIPTOR 0x07 -#define USBH_REQ_GET_CONFIGURATION 0x08 -#define USBH_REQ_SET_CONFIGURATION 0x09 -#define USBH_REQ_GET_INTERFACE 0x0A -#define USBH_REQ_SET_INTERFACE 0x0B -#define USBH_REQ_SYNCH_FRAME 0x0C - - -#define USBH_REQTYPE_IN 0x80 -#define USBH_REQTYPE_OUT 0x00 - -#define USBH_REQTYPE_STANDARD 0x00 -#define USBH_REQTYPE_CLASS 0x20 -#define USBH_REQTYPE_VENDOR 0x40 - -#define USBH_REQTYPE_DEVICE 0x00 -#define USBH_REQTYPE_INTERFACE 0x01 -#define USBH_REQTYPE_ENDPOINT 0x02 -#define USBH_REQTYPE_OTHER 0x03 - -#endif - - -#endif /* USBH_DEFS_H_ */ diff --git a/firmware/ChibiOS_16/community/os/hal/include/usbh/desciter.h b/firmware/ChibiOS_16/community/os/hal/include/usbh/desciter.h deleted file mode 100644 index 570393b73c..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/include/usbh/desciter.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail) - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - - -#ifndef USBH_DESCITER_H_ -#define USBH_DESCITER_H_ - -#include "hal.h" - -#if HAL_USE_USBH - -#include "usbh/defs.h" - - -/* DESCRIPTOR PARSING */ -#define _generic_iterator_fields \ - const uint8_t *curr; \ - uint16_t rem; \ - bool valid; - -typedef struct { - _generic_iterator_fields -} generic_iterator_t; - -typedef struct { - _generic_iterator_fields - const usbh_ia_descriptor_t *iad; -} if_iterator_t; - -void cfg_iter_init(generic_iterator_t *icfg, const uint8_t *buff, uint16_t rem); -void if_iter_init(if_iterator_t *iif, const generic_iterator_t *icfg); -void ep_iter_init(generic_iterator_t *iep, const if_iterator_t *iif); -void cs_iter_init(generic_iterator_t *ics, const generic_iterator_t *iter); -void if_iter_next(if_iterator_t *iif); -void ep_iter_next(generic_iterator_t *iep); -void cs_iter_next(generic_iterator_t *ics); -static inline const usbh_config_descriptor_t *cfg_get(generic_iterator_t *icfg) { - return (const usbh_config_descriptor_t *)icfg->curr; -} -static inline const usbh_interface_descriptor_t *if_get(if_iterator_t *iif) { - return (const usbh_interface_descriptor_t *)iif->curr; -} -static inline const usbh_endpoint_descriptor_t *ep_get(generic_iterator_t *iep) { - return (const usbh_endpoint_descriptor_t *)iep->curr; -} - -#endif - -#endif /* USBH_DESCITER_H_ */ diff --git a/firmware/ChibiOS_16/community/os/hal/include/usbh/dev/ftdi.h b/firmware/ChibiOS_16/community/os/hal/include/usbh/dev/ftdi.h deleted file mode 100644 index 70295daa46..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/include/usbh/dev/ftdi.h +++ /dev/null @@ -1,154 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail) - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef USBH_FTDI_H_ -#define USBH_FTDI_H_ - -#include "hal_usbh.h" - -#if HAL_USE_USBH && HAL_USBH_USE_FTDI - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ -#define USBHFTDI_FRAMING_DATABITS_7 (0x7 << 0) -#define USBHFTDI_FRAMING_DATABITS_8 (0x8 << 0) -#define USBHFTDI_FRAMING_PARITY_NONE (0x0 << 8) -#define USBHFTDI_FRAMING_PARITY_NONE (0x0 << 8) -#define USBHFTDI_FRAMING_PARITY_ODD (0x1 << 8) -#define USBHFTDI_FRAMING_PARITY_EVEN (0x2 << 8) -#define USBHFTDI_FRAMING_PARITY_MARK (0x3 << 8) -#define USBHFTDI_FRAMING_PARITY_SPACE (0x4 << 8) -#define USBHFTDI_FRAMING_STOP_BITS_1 (0x0 << 11) -#define USBHFTDI_FRAMING_STOP_BITS_15 (0x1 << 11) -#define USBHFTDI_FRAMING_STOP_BITS_2 (0x2 << 11) - -#define USBHFTDI_HANDSHAKE_NONE (0x0) -#define USBHFTDI_HANDSHAKE_RTS_CTS (0x1) -#define USBHFTDI_HANDSHAKE_DTR_DSR (0x2) -#define USBHFTDI_HANDSHAKE_XON_XOFF (0x4) - - - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ -typedef struct { - uint32_t speed; - uint16_t framing; - uint8_t handshake; - uint8_t xon_character; - uint8_t xoff_character; -} USBHFTDIPortConfig; - -typedef enum { - USBHFTDI_TYPE_A, - USBHFTDI_TYPE_B, - USBHFTDI_TYPE_H, -} usbhftdi_type_t; - -typedef enum { - USBHFTDIP_STATE_UNINIT = 0, - USBHFTDIP_STATE_STOP = 1, - USBHFTDIP_STATE_ACTIVE = 2, - USBHFTDIP_STATE_READY = 3 -} usbhftdip_state_t; - - -#define _ftdi_port_driver_methods \ - _base_asynchronous_channel_methods - -struct FTDIPortDriverVMT { - _ftdi_port_driver_methods -}; - -typedef struct USBHFTDIPortDriver USBHFTDIPortDriver; -typedef struct USBHFTDIDriver USBHFTDIDriver; - -struct USBHFTDIPortDriver { - /* inherited from abstract asyncrhonous channel driver */ - const struct FTDIPortDriverVMT *vmt; - _base_asynchronous_channel_data - - USBHFTDIDriver *ftdip; - - usbhftdip_state_t state; - - usbh_ep_t epin; - usbh_urb_t iq_urb; - threads_queue_t iq_waiting; - uint32_t iq_counter; - USBH_DEFINE_BUFFER(uint8_t, iq_buff[64]); - uint8_t *iq_ptr; - - - usbh_ep_t epout; - usbh_urb_t oq_urb; - threads_queue_t oq_waiting; - uint32_t oq_counter; - USBH_DEFINE_BUFFER(uint8_t, oq_buff[64]); - uint8_t *oq_ptr; - - virtual_timer_t vt; - uint8_t ifnum; - - USBHFTDIPortDriver *next; -}; - -typedef struct USBHFTDIDriver { - /* inherited from abstract class driver */ - _usbh_base_classdriver_data - - usbhftdi_type_t type; - USBHFTDIPortDriver *ports; - - mutex_t mtx; -} USBHFTDIDriver; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ -extern USBHFTDIDriver USBHFTDID[HAL_USBHFTDI_MAX_INSTANCES]; -extern USBHFTDIPortDriver FTDIPD[HAL_USBHFTDI_MAX_PORTS]; - -#ifdef __cplusplus -extern "C" { -#endif - /* FTDI device driver */ - void usbhftdiObjectInit(USBHFTDIDriver *ftdip); - - /* FTDI port driver */ - void usbhftdipObjectInit(USBHFTDIPortDriver *ftdipp); - void usbhftdipStart(USBHFTDIPortDriver *ftdipp, const USBHFTDIPortConfig *config); - void usbhftdipStop(USBHFTDIPortDriver *ftdipp); -#ifdef __cplusplus -} -#endif - - -#endif - -#endif /* USBH_FTDI_H_ */ diff --git a/firmware/ChibiOS_16/community/os/hal/include/usbh/dev/hub.h b/firmware/ChibiOS_16/community/os/hal/include/usbh/dev/hub.h deleted file mode 100644 index 1993142c05..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/include/usbh/dev/hub.h +++ /dev/null @@ -1,138 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail) - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef USBH_HUB_H_ -#define USBH_HUB_H_ - -#include "hal_usbh.h" - -#if HAL_USE_USBH -#if HAL_USBH_USE_HUB - -typedef struct USBHHubDriver { - /* inherited from abstract class driver */ - _usbh_base_classdriver_data - - struct list_head node; - - usbh_ep_t epint; - usbh_urb_t urb; - - USBH_DEFINE_BUFFER(uint8_t, scbuff[4]); - volatile uint32_t statuschange; - uint16_t status; - uint16_t c_status; - - usbh_port_t *ports; - - USBH_DEFINE_BUFFER(usbh_hub_descriptor_t, hubDesc); - - /* Low level part */ - _usbh_hub_ll_data - -} USBHHubDriver; - -extern USBHHubDriver USBHHUBD[HAL_USBHHUB_MAX_INSTANCES]; - - -usbh_urbstatus_t usbhhubControlRequest(USBHDriver *host, USBHHubDriver *hub, - uint8_t bmRequestType, - uint8_t bRequest, - uint16_t wValue, - uint16_t wIndex, - uint16_t wLength, - uint8_t *buf); - - -static inline usbh_urbstatus_t usbhhubClearFeaturePort(usbh_port_t *port, uint8_t feature) { - return usbhhubControlRequest(port->device.host, port->hub, - USBH_REQTYPE_OUT | USBH_REQTYPE_CLASS | USBH_REQTYPE_OTHER, - USBH_REQ_CLEAR_FEATURE, - feature, - port->number, - 0, - 0); -} - -static inline usbh_urbstatus_t usbhhubClearFeatureHub(USBHDriver *host, USBHHubDriver *hub, uint8_t feature) { - return usbhhubControlRequest(host, hub, - USBH_REQTYPE_OUT | USBH_REQTYPE_CLASS | USBH_REQTYPE_DEVICE, - USBH_REQ_CLEAR_FEATURE, - feature, - 0, - 0, - 0); -} - -static inline usbh_urbstatus_t usbhhubSetFeaturePort(usbh_port_t *port, uint8_t feature) { - return usbhhubControlRequest(port->device.host, port->hub, - USBH_REQTYPE_OUT | USBH_REQTYPE_CLASS | USBH_REQTYPE_OTHER, - USBH_REQ_SET_FEATURE, - feature, - port->number, - 0, - 0); -} - -void usbhhubObjectInit(USBHHubDriver *hubdp); -#else - -static inline usbh_urbstatus_t usbhhubControlRequest(USBHDriver *host, - uint8_t bmRequestType, - uint8_t bRequest, - uint16_t wValue, - uint16_t wIndex, - uint16_t wLength, - uint8_t *buf) { - return usbh_lld_root_hub_request(host, bmRequestType, bRequest, wValue, wIndex, wLength, buf); -} - -static inline usbh_urbstatus_t usbhhubClearFeaturePort(usbh_port_t *port, uint8_t feature) { - return usbhhubControlRequest(port->device.host, - USBH_REQTYPE_OUT | USBH_REQTYPE_CLASS | USBH_REQTYPE_OTHER, - USBH_REQ_CLEAR_FEATURE, - feature, - port->number, - 0, - 0); -} - -static inline usbh_urbstatus_t usbhhubClearFeatureHub(USBHDriver *host, uint8_t feature) { - return usbhhubControlRequest(host, - USBH_REQTYPE_OUT | USBH_REQTYPE_CLASS | USBH_REQTYPE_DEVICE, - USBH_REQ_CLEAR_FEATURE, - feature, - 0, - 0, - 0); -} - -static inline usbh_urbstatus_t usbhhubSetFeaturePort(usbh_port_t *port, uint8_t feature) { - return usbhhubControlRequest(port->device.host, - USBH_REQTYPE_OUT | USBH_REQTYPE_CLASS | USBH_REQTYPE_OTHER, - USBH_REQ_SET_FEATURE, - feature, - port->number, - 0, - 0); -} - -#endif - -#endif - -#endif /* USBH_HUB_H_ */ diff --git a/firmware/ChibiOS_16/community/os/hal/include/usbh/dev/msd.h b/firmware/ChibiOS_16/community/os/hal/include/usbh/dev/msd.h deleted file mode 100644 index d40e3ee5ad..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/include/usbh/dev/msd.h +++ /dev/null @@ -1,125 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail) - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef USBH_MSD_H_ -#define USBH_MSD_H_ - -#include "hal_usbh.h" - -#if HAL_USE_USBH && HAL_USBH_USE_MSD - -/* TODO: - * - * - Implement of conditional compilation of multiple-luns per instance. - * - Implement error checking and recovery when commands fail. - * - */ - - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -#define _usbhmsd_driver_methods \ - _base_block_device_methods - -struct USBHMassStorageDriverVMT { - _usbhmsd_driver_methods -}; - -typedef struct USBHMassStorageLUNDriver USBHMassStorageLUNDriver; -typedef struct USBHMassStorageDriver USBHMassStorageDriver; - -struct USBHMassStorageLUNDriver { - /* inherited from abstract block driver */ - const struct USBHMassStorageDriverVMT *vmt; - _base_block_device_data - - BlockDeviceInfo info; - USBHMassStorageDriver *msdp; - - USBHMassStorageLUNDriver *next; -}; - -typedef struct USBHMassStorageDriver { - /* inherited from abstract class driver */ - _usbh_base_classdriver_data - - /* for LUN request serialization, can be removed - * if the driver is configured to support only one LUN - * per USBHMassStorageDriver instance */ - mutex_t mtx; - - usbh_ep_t epin; - usbh_ep_t epout; - uint8_t ifnum; - uint8_t max_lun; - uint32_t tag; - - USBHMassStorageLUNDriver *luns; -} USBHMassStorageDriver; - - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -extern USBHMassStorageLUNDriver MSBLKD[HAL_USBHMSD_MAX_LUNS]; -extern USBHMassStorageDriver USBHMSD[HAL_USBHMSD_MAX_INSTANCES]; - -#ifdef __cplusplus -extern "C" { -#endif - /* Mass Storage Driver */ - void usbhmsdObjectInit(USBHMassStorageDriver *msdp); - - /* Mass Storage LUN Driver (block driver) */ - void usbhmsdLUNObjectInit(USBHMassStorageLUNDriver *lunp); - void usbhmsdLUNStart(USBHMassStorageLUNDriver *lunp); - void usbhmsdLUNStop(USBHMassStorageLUNDriver *lunp); - bool usbhmsdLUNConnect(USBHMassStorageLUNDriver *lunp); - bool usbhmsdLUNDisconnect(USBHMassStorageLUNDriver *lunp); - bool usbhmsdLUNRead(USBHMassStorageLUNDriver *lunp, uint32_t startblk, - uint8_t *buffer, uint32_t n); - bool usbhmsdLUNWrite(USBHMassStorageLUNDriver *lunp, uint32_t startblk, - const uint8_t *buffer, uint32_t n); - bool usbhmsdLUNSync(USBHMassStorageLUNDriver *lunp); - bool usbhmsdLUNGetInfo(USBHMassStorageLUNDriver *lunp, BlockDeviceInfo *bdip); - bool usbhmsdLUNIsInserted(USBHMassStorageLUNDriver *lunp); - bool usbhmsdLUNIsProtected(USBHMassStorageLUNDriver *lunp); -#ifdef __cplusplus -} -#endif - -#endif - -#endif /* USBH_MSD_H_ */ diff --git a/firmware/ChibiOS_16/community/os/hal/include/usbh/internal.h b/firmware/ChibiOS_16/community/os/hal/include/usbh/internal.h deleted file mode 100644 index d19d87c732..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/include/usbh/internal.h +++ /dev/null @@ -1,148 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail) - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef USBH_INTERNAL_H_ -#define USBH_INTERNAL_H_ - -#include "hal_usbh.h" - -#if HAL_USE_USBH - -/*===========================================================================*/ -/* These declarations are not part of the public API. */ -/*===========================================================================*/ - -#if HAL_USBH_USE_FTDI -extern const usbh_classdriverinfo_t usbhftdiClassDriverInfo; -#endif -#if HAL_USBH_USE_MSD -extern const usbh_classdriverinfo_t usbhmsdClassDriverInfo; -#endif -#if HAL_USBH_USE_UVC -extern const usbh_classdriverinfo_t usbhuvcClassDriverInfo; -#endif -#if HAL_USBH_USE_HUB -extern const usbh_classdriverinfo_t usbhhubClassDriverInfo; -void _usbhub_port_object_init(usbh_port_t *port, USBHDriver *usbh, - USBHHubDriver *hub, uint8_t number); -#else -void _usbhub_port_object_init(usbh_port_t *port, USBHDriver *usbh, uint8_t number); -#endif - -void _usbh_port_disconnected(usbh_port_t *port); -void _usbh_urb_completeI(usbh_urb_t *urb, usbh_urbstatus_t status); -bool _usbh_urb_abortI(usbh_urb_t *urb, usbh_urbstatus_t status); -void _usbh_urb_abort_and_waitS(usbh_urb_t *urb, usbh_urbstatus_t status); - - -#define USBH_CLASSIN(type, req, value, index) \ - (USBH_REQTYPE_IN | type | USBH_REQTYPE_CLASS), \ - req, \ - value, \ - index - -#define USBH_CLASSOUT(type, req, value, index) \ - (USBH_REQTYPE_OUT | type | USBH_REQTYPE_CLASS), \ - req, \ - value, \ - index - -#define USBH_STANDARDIN(type, req, value, index) \ - (USBH_REQTYPE_IN | type | USBH_REQTYPE_STANDARD), \ - req, \ - value, \ - index - -#define USBH_STANDARDOUT(type, req, value, index) \ - (USBH_REQTYPE_OUT | type | USBH_REQTYPE_STANDARD), \ - req, \ - value, \ - index - - -#define USBH_PID_DATA0 0 -#define USBH_PID_DATA2 1 -#define USBH_PID_DATA1 2 -#define USBH_PID_MDATA 3 -#define USBH_PID_SETUP 3 - - -/* GetBusState and SetHubDescriptor are optional, omitted */ -#define ClearHubFeature (((USBH_REQTYPE_OUT | USBH_REQTYPE_CLASS | USBH_REQTYPE_DEVICE) << 8) \ - | USBH_REQ_CLEAR_FEATURE) -#define SetHubFeature (((USBH_REQTYPE_OUT | USBH_REQTYPE_CLASS | USBH_REQTYPE_DEVICE) << 8) \ - | USBH_REQ_SET_FEATURE) -#define ClearPortFeature (((USBH_REQTYPE_OUT | USBH_REQTYPE_CLASS | USBH_REQTYPE_OTHER) << 8) \ - | USBH_REQ_CLEAR_FEATURE) -#define SetPortFeature (((USBH_REQTYPE_OUT | USBH_REQTYPE_CLASS | USBH_REQTYPE_OTHER) << 8) \ - | USBH_REQ_SET_FEATURE) -#define GetHubDescriptor (((USBH_REQTYPE_IN | USBH_REQTYPE_CLASS | USBH_REQTYPE_DEVICE) << 8) \ - | USBH_REQ_GET_DESCRIPTOR) -#define GetHubStatus (((USBH_REQTYPE_IN | USBH_REQTYPE_CLASS | USBH_REQTYPE_DEVICE) << 8) \ - | USBH_REQ_GET_STATUS) -#define GetPortStatus (((USBH_REQTYPE_IN | USBH_REQTYPE_CLASS | USBH_REQTYPE_OTHER) << 8) \ - | USBH_REQ_GET_STATUS) - - -#define USBH_PORTSTATUS_CONNECTION 0x0001 -#define USBH_PORTSTATUS_ENABLE 0x0002 -#define USBH_PORTSTATUS_SUSPEND 0x0004 -#define USBH_PORTSTATUS_OVERCURRENT 0x0008 -#define USBH_PORTSTATUS_RESET 0x0010 -/* bits 5 to 7 are reserved */ -#define USBH_PORTSTATUS_POWER 0x0100 -#define USBH_PORTSTATUS_LOW_SPEED 0x0200 -#define USBH_PORTSTATUS_HIGH_SPEED 0x0400 -#define USBH_PORTSTATUS_TEST 0x0800 -#define USBH_PORTSTATUS_INDICATOR 0x1000 -/* bits 13 to 15 are reserved */ - -#define USBH_PORTSTATUS_C_CONNECTION 0x0001 -#define USBH_PORTSTATUS_C_ENABLE 0x0002 -#define USBH_PORTSTATUS_C_SUSPEND 0x0004 -#define USBH_PORTSTATUS_C_OVERCURRENT 0x0008 -#define USBH_PORTSTATUS_C_RESET 0x0010 - -#define USBH_HUBSTATUS_C_HUB_LOCAL_POWER 0x0001 -#define USBH_HUBSTATUS_C_HUB_OVER_CURRENT 0x0002 - -/* - * Port feature numbers - * See USB 2.0 spec Table 11-17 - */ -#define USBH_HUB_FEAT_C_HUB_LOCAL_POWER 0 -#define USBH_HUB_FEAT_C_HUB_OVER_CURRENT 1 -#define USBH_PORT_FEAT_CONNECTION 0 -#define USBH_PORT_FEAT_ENABLE 1 -#define USBH_PORT_FEAT_SUSPEND 2 -#define USBH_PORT_FEAT_OVERCURRENT 3 -#define USBH_PORT_FEAT_RESET 4 -#define USBH_PORT_FEAT_POWER 8 -#define USBH_PORT_FEAT_LOWSPEED 9 -#define USBH_PORT_FEAT_C_CONNECTION 16 -#define USBH_PORT_FEAT_C_ENABLE 17 -#define USBH_PORT_FEAT_C_SUSPEND 18 -#define USBH_PORT_FEAT_C_OVERCURRENT 19 -#define USBH_PORT_FEAT_C_RESET 20 -#define USBH_PORT_FEAT_TEST 21 -#define USBH_PORT_FEAT_INDICATOR 22 - -#define sizeof_array(x) (sizeof(x)/sizeof(*(x))) - -#endif - -#endif /* USBH_INTERNAL_H_ */ diff --git a/firmware/ChibiOS_16/community/os/hal/include/usbh/list.h b/firmware/ChibiOS_16/community/os/hal/include/usbh/list.h deleted file mode 100644 index 089406a2c4..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/include/usbh/list.h +++ /dev/null @@ -1,598 +0,0 @@ -#ifndef USBH_LIST_H_ -#define USBH_LIST_H_ - -/* TODO: re-write this file; stolen from linux */ - -#ifndef offsetof -#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) -#endif - -#define container_of(ptr, type, member) ((type *)(void *)((char *)(ptr) - offsetof(type, member))) -#ifndef container_of -#define container_of(ptr, type, member) ({ \ - const typeof(((type *)0)->member) * __mptr = (ptr); \ - (type *)((char *)__mptr - offsetof(type, member)); }) -#endif - -/* - * Simple doubly linked list implementation. - * - * Some of the internal functions ("__xxx") are useful when - * manipulating whole lists rather than single entries, as - * sometimes we already know the next/prev entries and we can - * generate better code by using them directly rather than - * using the generic single-entry routines. - */ -struct list_head { - struct list_head *next, *prev; -}; - -#define LIST_HEAD_INIT(name) { &(name), &(name) } - -#define LIST_HEAD(name) \ - struct list_head name = LIST_HEAD_INIT(name) - -static inline void INIT_LIST_HEAD(struct list_head *list) -{ - list->next = list; - list->prev = list; -} - -/* - * Insert a new entry between two known consecutive entries. - * - * This is only for internal list manipulation where we know - * the prev/next entries already! - */ -#ifndef CONFIG_DEBUG_LIST -static inline void __list_add(struct list_head *new, - struct list_head *prev, - struct list_head *next) -{ - next->prev = new; - new->next = next; - new->prev = prev; - prev->next = new; -} -#else -extern void __list_add(struct list_head *new, - struct list_head *prev, - struct list_head *next); -#endif - -/** - * list_add - add a new entry - * @new: new entry to be added - * @head: list head to add it after - * - * Insert a new entry after the specified head. - * This is good for implementing stacks. - */ -static inline void list_add(struct list_head *new, struct list_head *head) -{ - __list_add(new, head, head->next); -} - - -/** - * list_add_tail - add a new entry - * @new: new entry to be added - * @head: list head to add it before - * - * Insert a new entry before the specified head. - * This is useful for implementing queues. - */ -static inline void list_add_tail(struct list_head *new, struct list_head *head) -{ - __list_add(new, head->prev, head); -} - -/* - * Delete a list entry by making the prev/next entries - * point to each other. - * - * This is only for internal list manipulation where we know - * the prev/next entries already! - */ -static inline void __list_del(struct list_head * prev, struct list_head * next) -{ - next->prev = prev; - prev->next = next; -} - -/** - * list_del - deletes entry from list. - * @entry: the element to delete from the list. - * Note: list_empty() on entry does not return true after this, the entry is - * in an undefined state. - */ -#ifndef CONFIG_DEBUG_LIST -static inline void __list_del_entry(struct list_head *entry) -{ - __list_del(entry->prev, entry->next); -} - -static inline void list_del(struct list_head *entry) -{ - __list_del(entry->prev, entry->next); - // entry->next = LIST_POISON1; - // entry->prev = LIST_POISON2; -} -#else -extern void __list_del_entry(struct list_head *entry); -extern void list_del(struct list_head *entry); -#endif - -/** - * list_replace - replace old entry by new one - * @old : the element to be replaced - * @new : the new element to insert - * - * If @old was empty, it will be overwritten. - */ -static inline void list_replace(struct list_head *old, - struct list_head *new) -{ - new->next = old->next; - new->next->prev = new; - new->prev = old->prev; - new->prev->next = new; -} - -static inline void list_replace_init(struct list_head *old, - struct list_head *new) -{ - list_replace(old, new); - INIT_LIST_HEAD(old); -} - -/** - * list_del_init - deletes entry from list and reinitialize it. - * @entry: the element to delete from the list. - */ -static inline void list_del_init(struct list_head *entry) -{ - __list_del_entry(entry); - INIT_LIST_HEAD(entry); -} - -/** - * list_move - delete from one list and add as another's head - * @list: the entry to move - * @head: the head that will precede our entry - */ -static inline void list_move(struct list_head *list, struct list_head *head) -{ - __list_del_entry(list); - list_add(list, head); -} - -/** - * list_move_tail - delete from one list and add as another's tail - * @list: the entry to move - * @head: the head that will follow our entry - */ -static inline void list_move_tail(struct list_head *list, - struct list_head *head) -{ - __list_del_entry(list); - list_add_tail(list, head); -} - -/** - * list_is_last - tests whether @list is the last entry in list @head - * @list: the entry to test - * @head: the head of the list - */ -static inline int list_is_last(const struct list_head *list, - const struct list_head *head) -{ - return list->next == head; -} - -/** - * list_empty - tests whether a list is empty - * @head: the list to test. - */ -static inline int list_empty(const struct list_head *head) -{ - return head->next == head; -} - -/** - * list_empty_careful - tests whether a list is empty and not being modified - * @head: the list to test - * - * Description: - * tests whether a list is empty _and_ checks that no other CPU might be - * in the process of modifying either member (next or prev) - * - * NOTE: using list_empty_careful() without synchronization - * can only be safe if the only activity that can happen - * to the list entry is list_del_init(). Eg. it cannot be used - * if another CPU could re-list_add() it. - */ -static inline int list_empty_careful(const struct list_head *head) -{ - struct list_head *next = head->next; - return (next == head) && (next == head->prev); -} - -/** - * list_rotate_left - rotate the list to the left - * @head: the head of the list - */ -static inline void list_rotate_left(struct list_head *head) -{ - struct list_head *first; - - if (!list_empty(head)) { - first = head->next; - list_move_tail(first, head); - } -} - -/** - * list_is_singular - tests whether a list has just one entry. - * @head: the list to test. - */ -static inline int list_is_singular(const struct list_head *head) -{ - return !list_empty(head) && (head->next == head->prev); -} - -static inline void __list_cut_position(struct list_head *list, - struct list_head *head, struct list_head *entry) -{ - struct list_head *new_first = entry->next; - list->next = head->next; - list->next->prev = list; - list->prev = entry; - entry->next = list; - head->next = new_first; - new_first->prev = head; -} - -/** - * list_cut_position - cut a list into two - * @list: a new list to add all removed entries - * @head: a list with entries - * @entry: an entry within head, could be the head itself - * and if so we won't cut the list - * - * This helper moves the initial part of @head, up to and - * including @entry, from @head to @list. You should - * pass on @entry an element you know is on @head. @list - * should be an empty list or a list you do not care about - * losing its data. - * - */ -static inline void list_cut_position(struct list_head *list, - struct list_head *head, struct list_head *entry) -{ - if (list_empty(head)) - return; - if (list_is_singular(head) && - (head->next != entry && head != entry)) - return; - if (entry == head) - INIT_LIST_HEAD(list); - else - __list_cut_position(list, head, entry); -} - -static inline void __list_splice(const struct list_head *list, - struct list_head *prev, - struct list_head *next) -{ - struct list_head *first = list->next; - struct list_head *last = list->prev; - - first->prev = prev; - prev->next = first; - - last->next = next; - next->prev = last; -} - -/** - * list_splice - join two lists, this is designed for stacks - * @list: the new list to add. - * @head: the place to add it in the first list. - */ -static inline void list_splice(const struct list_head *list, - struct list_head *head) -{ - if (!list_empty(list)) - __list_splice(list, head, head->next); -} - -/** - * list_splice_tail - join two lists, each list being a queue - * @list: the new list to add. - * @head: the place to add it in the first list. - */ -static inline void list_splice_tail(struct list_head *list, - struct list_head *head) -{ - if (!list_empty(list)) - __list_splice(list, head->prev, head); -} - -/** - * list_splice_init - join two lists and reinitialise the emptied list. - * @list: the new list to add. - * @head: the place to add it in the first list. - * - * The list at @list is reinitialised - */ -static inline void list_splice_init(struct list_head *list, - struct list_head *head) -{ - if (!list_empty(list)) { - __list_splice(list, head, head->next); - INIT_LIST_HEAD(list); - } -} - -/** - * list_splice_tail_init - join two lists and reinitialise the emptied list - * @list: the new list to add. - * @head: the place to add it in the first list. - * - * Each of the lists is a queue. - * The list at @list is reinitialised - */ -static inline void list_splice_tail_init(struct list_head *list, - struct list_head *head) -{ - if (!list_empty(list)) { - __list_splice(list, head->prev, head); - INIT_LIST_HEAD(list); - } -} - -/** - * list_entry - get the struct for this entry - * @ptr: the &struct list_head pointer. - * @type: the type of the struct this is embedded in. - * @member: the name of the list_head within the struct. - */ -#define list_entry(ptr, type, member) \ - container_of(ptr, type, member) - -/** - * list_first_entry - get the first element from a list - * @ptr: the list head to take the element from. - * @type: the type of the struct this is embedded in. - * @member: the name of the list_head within the struct. - * - * Note, that list is expected to be not empty. - */ -#define list_first_entry(ptr, type, member) \ - list_entry((ptr)->next, type, member) - -/** - * list_last_entry - get the last element from a list - * @ptr: the list head to take the element from. - * @type: the type of the struct this is embedded in. - * @member: the name of the list_head within the struct. - * - * Note, that list is expected to be not empty. - */ -#define list_last_entry(ptr, type, member) \ - list_entry((ptr)->prev, type, member) - -/** - * list_first_entry_or_null - get the first element from a list - * @ptr: the list head to take the element from. - * @type: the type of the struct this is embedded in. - * @member: the name of the list_head within the struct. - * - * Note that if the list is empty, it returns NULL. - */ -#define list_first_entry_or_null(ptr, type, member) \ - (!list_empty(ptr) ? list_first_entry(ptr, type, member) : NULL) - -/** - * list_next_entry - get the next element in list - * @pos: the type * to cursor - * @member: the name of the list_head within the struct. - */ -#define list_next_entry(pos, type, member) \ - list_entry((pos)->member.next, type, member) - -/** - * list_prev_entry - get the prev element in list - * @pos: the type * to cursor - * @member: the name of the list_head within the struct. - */ -#define list_prev_entry(pos, type, member) \ - list_entry((pos)->member.prev, type, member) - -/** - * list_for_each - iterate over a list - * @pos: the &struct list_head to use as a loop cursor. - * @head: the head for your list. - */ -#define list_for_each(pos, head) \ - for (pos = (head)->next; pos != (head); pos = pos->next) - -/** - * list_for_each_prev - iterate over a list backwards - * @pos: the &struct list_head to use as a loop cursor. - * @head: the head for your list. - */ -#define list_for_each_prev(pos, head) \ - for (pos = (head)->prev; pos != (head); pos = pos->prev) - -/** - * list_for_each_safe - iterate over a list safe against removal of list entry - * @pos: the &struct list_head to use as a loop cursor. - * @n: another &struct list_head to use as temporary storage - * @head: the head for your list. - */ -#define list_for_each_safe(pos, n, head) \ - for (pos = (head)->next, n = pos->next; pos != (head); \ - pos = n, n = pos->next) - -/** - * list_for_each_prev_safe - iterate over a list backwards safe against removal of list entry - * @pos: the &struct list_head to use as a loop cursor. - * @n: another &struct list_head to use as temporary storage - * @head: the head for your list. - */ -#define list_for_each_prev_safe(pos, n, head) \ - for (pos = (head)->prev, n = pos->prev; \ - pos != (head); \ - pos = n, n = pos->prev) - -/** - * list_for_each_entry - iterate over list of given type - * @pos: the type * to use as a loop cursor. - * @head: the head for your list. - * @member: the name of the list_head within the struct. - */ -#define list_for_each_entry(pos, type, head, member) \ - for (pos = list_first_entry(head, type, member); \ - &pos->member != (head); \ - pos = list_next_entry(pos, type, member)) - -/** - * list_for_each_entry_reverse - iterate backwards over list of given type. - * @pos: the type * to use as a loop cursor. - * @head: the head for your list. - * @member: the name of the list_head within the struct. - */ -#define list_for_each_entry_reverse(pos, type, head, member) \ - for (pos = list_last_entry(head, type, member); \ - &pos->member != (head); \ - pos = list_prev_entry(pos, type, member)) - -/** - * list_prepare_entry - prepare a pos entry for use in list_for_each_entry_continue() - * @pos: the type * to use as a start point - * @head: the head of the list - * @member: the name of the list_head within the struct. - * - * Prepares a pos entry for use as a start point in list_for_each_entry_continue(). - */ -#define list_prepare_entry(pos, type, head, member) \ - ((pos) ? : list_entry(head, type, member)) - -/** - * list_for_each_entry_continue - continue iteration over list of given type - * @pos: the type * to use as a loop cursor. - * @head: the head for your list. - * @member: the name of the list_head within the struct. - * - * Continue to iterate over list of given type, continuing after - * the current position. - */ -#define list_for_each_entry_continue(pos, type, head, member) \ - for (pos = list_next_entry(pos, type, member); \ - &pos->member != (head); \ - pos = list_next_entry(pos, type, member)) - -/** - * list_for_each_entry_continue_reverse - iterate backwards from the given point - * @pos: the type * to use as a loop cursor. - * @head: the head for your list. - * @member: the name of the list_head within the struct. - * - * Start to iterate over list of given type backwards, continuing after - * the current position. - */ -#define list_for_each_entry_continue_reverse(pos, type, head, member) \ - for (pos = list_prev_entry(pos, type, member); \ - &pos->member != (head); \ - pos = list_prev_entry(pos, type, member)) - -/** - * list_for_each_entry_from - iterate over list of given type from the current point - * @pos: the type * to use as a loop cursor. - * @head: the head for your list. - * @member: the name of the list_head within the struct. - * - * Iterate over list of given type, continuing from current position. - */ -#define list_for_each_entry_from(pos, type, head, member) \ - for (; &pos->member != (head); \ - pos = list_next_entry(pos, type, member)) - -/** - * list_for_each_entry_safe - iterate over list of given type safe against removal of list entry - * @pos: the type * to use as a loop cursor. - * @n: another type * to use as temporary storage - * @head: the head for your list. - * @member: the name of the list_head within the struct. - */ -#define list_for_each_entry_safe(pos, type, n, head, member) \ - for (pos = list_first_entry(head, type, member), \ - n = list_next_entry(pos, type, member); \ - &pos->member != (head); \ - pos = n, n = list_next_entry(n, type, member)) - -/** - * list_for_each_entry_safe_continue - continue list iteration safe against removal - * @pos: the type * to use as a loop cursor. - * @n: another type * to use as temporary storage - * @head: the head for your list. - * @member: the name of the list_head within the struct. - * - * Iterate over list of given type, continuing after current point, - * safe against removal of list entry. - */ -#define list_for_each_entry_safe_continue(pos, type, n, head, member) \ - for (pos = list_next_entry(pos, type, member), \ - n = list_next_entry(pos, type, member); \ - &pos->member != (head); \ - pos = n, n = list_next_entry(n, type, member)) - -/** - * list_for_each_entry_safe_from - iterate over list from current point safe against removal - * @pos: the type * to use as a loop cursor. - * @n: another type * to use as temporary storage - * @head: the head for your list. - * @member: the name of the list_head within the struct. - * - * Iterate over list of given type from current point, safe against - * removal of list entry. - */ -#define list_for_each_entry_safe_from(pos, type, n, head, member) \ - for (n = list_next_entry(pos, type, member); \ - &pos->member != (head); \ - pos = n, n = list_next_entry(n, type, member)) - -/** - * list_for_each_entry_safe_reverse - iterate backwards over list safe against removal - * @pos: the type * to use as a loop cursor. - * @n: another type * to use as temporary storage - * @head: the head for your list. - * @member: the name of the list_head within the struct. - * - * Iterate backwards over list of given type, safe against removal - * of list entry. - */ -#define list_for_each_entry_safe_reverse(pos, type, n, head, member) \ - for (pos = list_last_entry(head, type, member), \ - n = list_prev_entry(pos, type, member); \ - &pos->member != (head); \ - pos = n, n = list_prev_entry(n, type, member)) - -/** - * list_safe_reset_next - reset a stale list_for_each_entry_safe loop - * @pos: the loop cursor used in the list_for_each_entry_safe loop - * @n: temporary storage used in list_for_each_entry_safe - * @member: the name of the list_head within the struct. - * - * list_safe_reset_next is not safe to use in general if the list may be - * modified concurrently (eg. the lock is dropped in the loop body). An - * exception to this is if the cursor element (pos) is pinned in the list, - * and list_safe_reset_next is called after re-taking the lock and before - * completing the current iteration of the loop body. - */ -#define list_safe_reset_next(pos, type, n, member) \ - n = list_next_entry(pos, type, member) - -#endif /* USBH_LIST_H_ */ diff --git a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c b/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c deleted file mode 100644 index a2cf0269c3..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c +++ /dev/null @@ -1,328 +0,0 @@ -/* - ChibiOS - Copyright (C) 2015 Michael D. Spradling - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/CRCv1/hal_crc_lld.c - * @brief STM32 CRC subsystem low level driver source. - * - * @addtogroup CRC - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_CRC == TRUE) || defined(__DOXYGEN__) - -/** - * Allow CRC Software override for ST drivers. Some ST CRC implimentations - * have limited capabilities. - */ -#if CRCSW_USE_CRC1 != TRUE - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/** - * @brief CRC default configuration. - */ -static const CRCConfig default_config = { - .poly_size = 32, - .poly = 0x04C11DB7, - .initial_val = 0xFFFFFFFF, - .final_val = 0xFFFFFFFF, - .reflect_data = 1, - .reflect_remainder = 1 -}; - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief CRC1 driver identifier.*/ -#if STM32_CRC_USE_CRC1 || defined(__DOXYGEN__) -CRCDriver CRCD1; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -void _crc_lld_calc_byte(CRCDriver *crcp, uint8_t data) { - __IO uint8_t *crc8 = (__IO uint8_t*)&(crcp->crc->DR); - *crc8 = data; -} - -/* - * @brief Returns calculated CRC from last reset - * - * @param[in] crcp pointer to the @p CRCDriver object - * @param[in] data data to be added to crc - * - * @notapi - */ -void _crc_lld_calc_halfword(CRCDriver *crcp, uint16_t data) { - __IO uint16_t *crc16 = (__IO uint16_t*)&(crcp->crc->DR); - *crc16 = data; -} - -/* - * @brief Returns calculated CRC from last reset - * - * @param[in] crcp pointer to the @p CRCDriver object - * @param[in] data data to be added to crc - * - * @notapi - */ -void _crc_lld_calc_word(CRCDriver *crcp, uint32_t data) { - crcp->crc->DR = data; -} - - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief Shared end-of-rx service routine. - * - * @param[in] crcp pointer to the @p CRCDriver object - * @param[in] flags pre-shifted content of the ISR register - */ -#if CRC_USE_DMA == TRUE -static void crc_lld_serve_interrupt(CRCDriver *crcp, uint32_t flags) { - - /* DMA errors handling.*/ -#if defined(STM32_CRC_DMA_ERROR_HOOK) - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - STM32_CRC_DMA_ERROR_HOOK(crcp); - } -#else - (void)flags; -#endif - - /* Stop everything.*/ - dmaStreamDisable(crcp->dma); - - /* Portable CRC ISR code defined in the high level driver, note, it is - a macro.*/ - _crc_isr_code(crcp, crcp->crc->DR ^ crcp->config->final_val); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level CRC driver initialization. - * - * @notapi - */ -void crc_lld_init(void) { - crcObjectInit(&CRCD1); - CRCD1.crc = CRC; -#if CRC_USE_DMA == TRUE - CRCD1.dma = STM32_CRC_CRC1_DMA_STREAM; -#endif -} - -/** - * @brief Configures and activates the CRC peripheral. - * - * @param[in] crcp pointer to the @p CRCDriver object - * - * @notapi - */ -void crc_lld_start(CRCDriver *crcp) { - if (crcp->config == NULL) - crcp->config = &default_config; - - rccEnableCRC(FALSE); - -#if STM32_CRC_PROGRAMMABLE == TRUE - crcp->crc->INIT = crcp->config->initial_val; - crcp->crc->POL = crcp->config->poly; - - crcp->crc->CR = 0; - switch(crcp->config->poly_size) { - case 32: - break; - case 16: - crcp->crc->CR |= CRC_CR_POLYSIZE_0; - break; - case 8: - crcp->crc->CR |= CRC_CR_POLYSIZE_1; - break; - case 7: - crcp->crc->CR |= CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0; - break; - default: - osalDbgAssert(false, "hardware doesn't support polynomial size"); - break; - }; - if (crcp->config->reflect_data) { - crcp->crc->CR |= CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0; - } - if (crcp->config->reflect_remainder) { - crcp->crc->CR |= CRC_CR_REV_OUT; - } -#else - osalDbgAssert(crcp->config->initial_val == default_config.initial_val, - "hardware doesn't support programmable initial value"); - osalDbgAssert(crcp->config->poly_size == default_config.poly_size, - "hardware doesn't support programmable polynomial size"); - osalDbgAssert(crcp->config->poly == default_config.poly, - "hardware doesn't support programmable polynomial"); - osalDbgAssert(crcp->config->reflect_data == default_config.reflect_data, - "hardware doesn't support reflect of input data"); - osalDbgAssert(crcp->config->reflect_remainder == default_config.reflect_remainder, - "hardware doesn't support reflect of output remainder"); -#endif - -#if CRC_USE_DMA == TRUE -#if STM32_CRC_PROGRAMMABLE == TRUE - crcp->dmamode = STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_PINC | - STM32_DMA_CR_MSIZE_BYTE | STM32_DMA_CR_PSIZE_BYTE | - STM32_DMA_CR_TEIE | STM32_DMA_CR_TCIE | - STM32_DMA_CR_PL(STM32_CRC_CRC1_DMA_PRIORITY); -#else - crcp->dmamode = STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_PINC | - STM32_DMA_CR_MSIZE_WORD | STM32_DMA_CR_PSIZE_WORD | - STM32_DMA_CR_TEIE | STM32_DMA_CR_TCIE | - STM32_DMA_CR_PL(STM32_CRC_CRC1_DMA_PRIORITY); -#endif - { - bool b; - b = dmaStreamAllocate(crcp->dma, - STM32_CRC_CRC1_DMA_IRQ_PRIORITY, - (stm32_dmaisr_t)crc_lld_serve_interrupt, - (void *)crcp); - osalDbgAssert(!b, "stream already allocated"); - } -#endif -} - - -/** - * @brief Deactivates the CRC peripheral. - * - * @param[in] crcp pointer to the @p CRCDriver object - * - * @notapi - */ -void crc_lld_stop(CRCDriver *crcp) { -#if CRC_USE_DMA == TRUE - dmaStreamRelease(crcp->dma); -#else - (void)crcp; -#endif - rccDisableCRC(FALSE); -} - -/** - * @brief Resets current CRC calculation. - * - * @param[in] crcp pointer to the @p CRCDriver object - * - * @notapi - */ -void crc_lld_reset(CRCDriver *crcp) { - crcp->crc->CR |= CRC_CR_RESET; -} - -/** - * @brief Returns calculated CRC from last reset - * - * @param[in] crcp pointer to the @p CRCDriver object - * @param[in] n size of buf in bytes - * @param[in] buf @p buffer location - * - * @notapi - */ -uint32_t crc_lld_calc(CRCDriver *crcp, size_t n, const void *buf) { -#if CRC_USE_DMA == TRUE - crc_lld_start_calc(crcp, n, buf); - (void) osalThreadSuspendS(&crcp->thread); -#else - /** - * BUG: Only peform byte writes to DR reg if reflect_data is disabled. - * The STM32 hardware unit seems to incorrectly calculate CRCs when all - * of the following is true: reflect_data(rev_in) is 0, dma is disable, and - * you are writing more than a byte into the DR register. - */ - if (crcp->config->reflect_data != 0) { - while(n > 3) { - _crc_lld_calc_word(crcp, *(uint32_t*)buf); - buf+=4; - n-=4; - } - } - -#if STM32_CRC_PROGRAMMABLE == TRUE - /* Programmable CRC units allow variable register width accesses.*/ - - /** - * BUG: Only peform byte writes to DR reg if reflect_data is disabled. - * The STM32 hardware unit seems to incorrectly calculate CRCs when all - * of the following is true: reflect_data(rev_in) is 0, dma is disable, and - * you are writing more than a byte into the DR register. - */ - if (crcp->config->reflect_data != 0) { - while(n > 1) { - _crc_lld_calc_halfword(crcp, *(uint16_t*)buf); - buf+=2; - n-=2; - } - } - - while(n > 0) { - _crc_lld_calc_byte(crcp, *(uint8_t*)buf); - buf++; - n--; - } -#else - osalDbgAssert(n == 0, "STM32 CRC Unit only supports WORD accesses"); -#endif - -#endif - return crcp->crc->DR ^ crcp->config->final_val; -} - -#if CRC_USE_DMA == TRUE -void crc_lld_start_calc(CRCDriver *crcp, size_t n, const void *buf) { - dmaStreamSetPeripheral(crcp->dma, buf); - dmaStreamSetMemory0(crcp->dma, &crcp->crc->DR); -#if STM32_CRC_PROGRAMMABLE == TRUE - dmaStreamSetTransactionSize(crcp->dma, n); -#else - dmaStreamSetTransactionSize(crcp->dma, (n / 4)); -#endif - dmaStreamSetMode(crcp->dma, crcp->dmamode); - - dmaStreamEnable(crcp->dma); -} -#endif - -#endif /* CRCSW_USE_CRC1 */ - -#endif /* HAL_USE_CRC */ - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.h b/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.h deleted file mode 100644 index 213d34629c..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.h +++ /dev/null @@ -1,249 +0,0 @@ -/* - ChibiOS - Copyright (C) 2015 Michael D. Spradling - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/CRCv1/hal_crc_lld.h - * @brief STM32 CRC subsystem low level driver header. - * - * @addtogroup CRC - * @{ - */ - -#ifndef HAL_CRC_LLD_H_ -#define HAL_CRC_LLD_H_ - -#if (HAL_USE_CRC == TRUE) || defined(__DOXYGEN__) - -/* - * This error check must occur outsite of CRCSW_USE_CRC1 to check if - * two LLD drivers are enabled at the same time - */ -#if STM32_CRC_USE_CRC1 == TRUE && \ - CRCSW_USE_CRC1 == TRUE -#error "Software CRC can't be enable with STM32_CRC_USE_CRC1" -#endif - -/** - * Allow CRC Software override for ST drivers. Some ST CRC implimentations - * have limited capabilities. - */ -#if CRCSW_USE_CRC1 != TRUE - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief CRC1 driver enable switch. - * @details If set to @p TRUE the support for CRC1 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_CRC_USE_CRC1) || defined(__DOXYGEN__) -#define STM32_CRC_USE_CRC1 FALSE -#endif - -/** - * @brief CRC1 DMA priority (0..3|lowest..highest). - * @note The priority level is for CRC DMA stream. - */ -#if !defined(STM32_CRC_CRC1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_CRC_CRC1_DMA_PRIORITY 2 -#endif - -/** - * @brief CRC1 DMA interrupt priority level setting. - */ -#if !defined(STM32_CRC_CRC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_CRC_CRC1_DMA_IRQ_PRIORITY 1 -#endif - -/** - * @brief CRC1 DMA STREAM to use when performing CRC calculation. - */ -#if !defined(STM32_CRC_CRC1_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_CRC_CRC1_DMA_STREAM STM32_DMA1_STREAM2 -#endif - -/** - * @brief CRC DMA error hook. - */ -#if !defined(STM32_CRC_DMA_ERROR_HOOK) || defined(__DOXYGEN__) -#define STM32_CRC_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_CRC_USE_CRC1 && !STM32_HAS_CRC -#error "Hardware CRC not present in the selected device" -#error "Use CRCSW_USE_CRC1 for software implementation" -#endif - -#if CRC_USE_DMA -#if STM32_CRC_USE_CRC1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_CRC_CRC1_DMA_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to CRC1" -#endif - -#if STM32_CRC_USE_CRC1 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_CRC_CRC1_DMA_PRIORITY) -#error "Invalid DMA priority assigned to CRC1" -#endif - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a structure representing an CRC driver. - */ -typedef struct CRCDriver CRCDriver; - -/** - * @brief CRC notification callback type - * - * @param[in] crcp pointer to the @ CRCDriver object triggering the - * callback - */ -typedef void (*crccallback_t)(CRCDriver *crcp, uint32_t crc); - -/** - * @brief Driver configuration structure. - */ -typedef struct { - /** - * @brief The size of polynomial to be used for CRC. - */ - uint32_t poly_size; - /** - * @brief The coefficients of the polynomial to be used for CRC. - */ - uint32_t poly; - /** - * @brief The inital value - */ - uint32_t initial_val; - /** - * @brief The final XOR value - */ - uint32_t final_val; - /** - * @brief Reflect bit order data going into CRC - */ - bool reflect_data; - /** - * @brief Reflect bit order of final remainder - */ - bool reflect_remainder; - /* End of the mandatory fields.*/ - /** - * @brief Operation complete callback or @p NULL - */ - crccallback_t end_cb; -} CRCConfig; - - -/** - * @brief Structure representing an CRC driver. - */ -struct CRCDriver { - /** - * @brief Driver state. - */ - crcstate_t state; - /** - * @brief Current configuration data. - */ - const CRCConfig *config; -#if CRC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the peripheral. - */ - mutex_t mutex; -#endif /* CRC_USE_MUTUAL_EXCLUSION */ -#if defined(CRC_DRIVER_EXT_FIELDS) - CRC_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the CRCx registers block. - */ - CRC_TypeDef *crc; - -#if CRC_USE_DMA == TRUE - /** - * @brief Waiting thread. - */ - thread_reference_t thread; - /** - * @brief CRC DMA stream - */ - const stm32_dma_stream_t *dma; - /** - * @brief DMA mode bit mask. - */ - uint32_t dmamode; -#endif -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_CRC_USE_CRC1 && !defined(__DOXYGEN__) -extern CRCDriver CRCD1; -#endif /* STM32_CRC_USE_CRC1 */ - -#ifdef __cplusplus -extern "C" { -#endif - void crc_lld_init(void); - void crc_lld_start(CRCDriver *crcp); - void crc_lld_stop(CRCDriver *crcp); - void crc_lld_reset(CRCDriver *crcp); - uint32_t crc_lld_calc(CRCDriver *crcp, size_t n, const void *buf); -#if CRC_USE_DMA - void crc_lld_start_calc(CRCDriver *crcp, size_t n, const void *buf); -#endif -#ifdef __cplusplus -} -#endif - -#endif /* CRCSW_USE_CRC1 */ - -#endif /* HAL_USE_CRC */ - -#endif /* HAL_CRC_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.c b/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.c deleted file mode 100644 index 675120236f..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.c +++ /dev/null @@ -1,3130 +0,0 @@ -/* - Copyright (C) 2013-2015 Andrea Zoppi - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_stm32_dma2d.c - * @brief DMA2D/Chrom-ART driver. - */ - -#include "ch.h" -#include "hal.h" - -#include "hal_stm32_dma2d.h" - -#if STM32_DMA2D_USE_DMA2D || defined(__DOXYGEN__) - -/* Ignore annoying warning messages for actually safe code.*/ -#if defined(__GNUC__) && !defined(__DOXYGEN__) -#pragma GCC diagnostic ignored "-Wtype-limits" -#endif - -/** - * @addtogroup dma2d - * @{ - */ - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief DMA2DD1 driver identifier.*/ -DMA2DDriver DMA2DD1; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief Bits per pixel lookup table. - */ -static const uint8_t dma2d_bpp[DMA2D_MAX_PIXFMT_ID + 1] = { - 32, /* DMA2D_FMT_ARGB8888 */ - 24, /* DMA2D_FMT_RGB888 */ - 16, /* DMA2D_FMT_RGB565 */ - 16, /* DMA2D_FMT_ARGB1555 */ - 16, /* DMA2D_FMT_ARGB4444 */ - 8, /* DMA2D_FMT_L8 */ - 8, /* DMA2D_FMT_AL44 */ - 16, /* DMA2D_FMT_AL88 */ - 4, /* DMA2D_FMT_L4 */ - 8, /* DMA2D_FMT_A8 */ - 4 /* DMA2D_FMT_A4 */ -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @name DMA2D interrupt handlers - * @{ - */ - -/** - * @brief DMA2D global interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_DMA2D_HANDLER) { - - DMA2DDriver *const dma2dp = &DMA2DD1; - bool job_done = false; - thread_t *tp = NULL; - - OSAL_IRQ_PROLOGUE(); - - /* Handle Configuration Error ISR.*/ - if ((DMA2D->ISR & DMA2D_ISR_CEIF) && (DMA2D->CR & DMA2D_CR_CEIE)) { - if (dma2dp->config->cfgerr_isr != NULL) - dma2dp->config->cfgerr_isr(dma2dp); - job_done = true; - DMA2D->IFCR |= DMA2D_IFSR_CCEIF; - } - - /* Handle CLUT (Palette) Transfer Complete ISR.*/ - if ((DMA2D->ISR & DMA2D_ISR_CTCIF) && (DMA2D->CR & DMA2D_CR_CTCIE)) { - if (dma2dp->config->paltrfdone_isr != NULL) - dma2dp->config->paltrfdone_isr(dma2dp); - job_done = true; - DMA2D->IFCR |= DMA2D_IFSR_CCTCIF; - } - - /* Handle CLUT (Palette) Access Error ISR.*/ - if ((DMA2D->ISR & DMA2D_ISR_CAEIF) && (DMA2D->CR & DMA2D_CR_CAEIE)) { - if (dma2dp->config->palacserr_isr != NULL) - dma2dp->config->palacserr_isr(dma2dp); - job_done = true; - DMA2D->IFCR |= DMA2D_IFSR_CCAEIF; - } - - /* Handle Transfer Watermark ISR.*/ - if ((DMA2D->ISR & DMA2D_ISR_TWIF) && (DMA2D->CR & DMA2D_CR_TWIE)) { - if (dma2dp->config->trfwmark_isr != NULL) - dma2dp->config->trfwmark_isr(dma2dp); - DMA2D->IFCR |= DMA2D_IFSR_CTWIF; - } - - /* Handle Transfer Complete ISR.*/ - if ((DMA2D->ISR & DMA2D_ISR_TCIF) && (DMA2D->CR & DMA2D_CR_TCIE)) { - if (dma2dp->config->trfdone_isr != NULL) - dma2dp->config->trfdone_isr(dma2dp); - job_done = true; - DMA2D->IFCR |= DMA2D_IFSR_CTCIF; - } - - /* Handle Transfer Error ISR.*/ - if ((DMA2D->ISR & DMA2D_ISR_TEIF) && (DMA2D->CR & DMA2D_CR_TEIE)) { - if (dma2dp->config->trferr_isr != NULL) - dma2dp->config->trferr_isr(dma2dp); - job_done = true; - DMA2D->IFCR |= DMA2D_IFSR_CTEIF; - } - - if (job_done) { - osalSysLockFromISR(); - osalDbgAssert(dma2dp->state == DMA2D_ACTIVE, "invalid state"); - - #if DMA2D_USE_WAIT - /* Wake the waiting thread up.*/ - if (dma2dp->thread != NULL) { - tp = dma2dp->thread; - dma2dp->thread = NULL; - tp->u.rdymsg = MSG_OK; - chSchReadyI(tp); - } - #endif /* DMA2D_USE_WAIT */ - - dma2dp->state = DMA2D_READY; - osalSysUnlockFromISR(); - } - - OSAL_IRQ_EPILOGUE(); -} - -/** @} */ - -/** - * @name DMA2D driver-specific methods - * @{ - */ - -/** - * @brief DMA2D Driver initialization. - * @details Initializes the DMA2D subsystem and chosen drivers. Should be - * called at board initialization. - * - * @init - */ -void dma2dInit(void) { - - /* Reset the DMA2D hardware module.*/ - rccResetDMA2D(); - - /* Enable the DMA2D clock.*/ - rccEnableDMA2D(false); - - /* Driver struct initialization.*/ - dma2dObjectInit(&DMA2DD1); - DMA2DD1.state = DMA2D_STOP; -} - -/** - * @brief Initializes the standard part of a @p DMA2DDriver structure. - * - * @param[out] dma2dp pointer to the @p DMA2DDriver object - * - * @init - */ -void dma2dObjectInit(DMA2DDriver *dma2dp) { - - osalDbgCheck(dma2dp == &DMA2DD1); - - dma2dp->state = DMA2D_UNINIT; - dma2dp->config = NULL; -#if DMA2D_USE_WAIT - dma2dp->thread = NULL; -#endif /* DMA2D_USE_WAIT */ -#if (TRUE == DMA2D_USE_MUTUAL_EXCLUSION) -#if (TRUE == CH_CFG_USE_MUTEXES) - chMtxObjectInit(&dma2dp->lock); -#else - chSemObjectInit(&dma2dp->lock, 1); -#endif -#endif /* (TRUE == DMA2D_USE_MUTUAL_EXCLUSION) */ -} - -/** - * @brief Get the driver state. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @retun driver state - * - * @iclass - */ -dma2d_state_t dma2dGetStateI(DMA2DDriver *dma2dp) { - - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgCheckClassI(); - - return dma2dp->state; -} - -/** - * @brief Get the driver state. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @retun driver state - * - * @api - */ -dma2d_state_t dma2dGetState(DMA2DDriver *dma2dp) { - - dma2d_state_t state; - chSysLock(); - state = dma2dGetStateI(dma2dp); - chSysUnlock(); - return state; -} - -/** - * @brief Configures and activates the DMA2D peripheral. - * @pre DMA2D is stopped. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] configp pointer to the @p DMA2DConfig object - * - * @api - */ -void dma2dStart(DMA2DDriver *dma2dp, const DMA2DConfig *configp) { - - chSysLock(); - - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgCheck(configp != NULL); - osalDbgAssert(dma2dp->state == DMA2D_STOP, "invalid state"); - - dma2dp->config = configp; - - /* Turn off the controller and its interrupts.*/ - DMA2D->CR = 0; - - /* Enable interrupts, except Line Watermark.*/ - nvicEnableVector(STM32_DMA2D_NUMBER, STM32_DMA2D_IRQ_PRIORITY); - - DMA2D->CR = (DMA2D_CR_CEIE | DMA2D_CR_CTCIE | DMA2D_CR_CAEIE | - DMA2D_CR_TCIE | DMA2D_CR_TEIE); - - dma2dp->state = DMA2D_READY; - chSysUnlock(); -} - -/** - * @brief Deactivates the DMA2D peripheral. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @api - */ -void dma2dStop(DMA2DDriver *dma2dp) { - - chSysLock(); - - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "invalid state"); -#if DMA2D_USE_WAIT - osalDbgAssert(dma2dp->thread == NULL, "still waiting"); -#endif /* DMA2D_USE_WAIT */ - - dma2dp->state = DMA2D_STOP; - chSysUnlock(); -} - -#if DMA2D_USE_MUTUAL_EXCLUSION - -/** - * @brief Gains exclusive access to the DMA2D module. - * @details This function tries to gain ownership to the DMA2D module, if the - * module is already being used then the invoking thread is queued. - * @pre In order to use this function the option - * @p DMA2D_USE_MUTUAL_EXCLUSION must be enabled. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @sclass - */ -void dma2dAcquireBusS(DMA2DDriver *dma2dp) { - - osalDbgCheckClassS(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - -#if (TRUE == CH_CFG_USE_MUTEXES) - chMtxLockS(&dma2dp->lock); -#else - chSemWaitS(&dma2dp->lock); -#endif -} - -/** - * @brief Gains exclusive access to the DMA2D module. - * @details This function tries to gain ownership to the DMA2D module, if the - * module is already being used then the invoking thread is queued. - * @pre In order to use this function the option - * @p DMA2D_USE_MUTUAL_EXCLUSION must be enabled. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @api - */ -void dma2dAcquireBus(DMA2DDriver *dma2dp) { - - chSysLock(); - dma2dAcquireBusS(dma2dp); - chSysUnlock(); -} - -/** - * @brief Releases exclusive access to the DMA2D module. - * @pre In order to use this function the option - * @p DMA2D_USE_MUTUAL_EXCLUSION must be enabled. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @sclass - */ -void dma2dReleaseBusS(DMA2DDriver *dma2dp) { - - osalDbgCheckClassS(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - -#if (TRUE == CH_CFG_USE_MUTEXES) - chMtxUnlockS(&dma2dp->lock); -#else - chSemSignalI(&dma2dp->lock); -#endif -} - -/** - * @brief Releases exclusive access to the DMA2D module. - * @pre In order to use this function the option - * @p DMA2D_USE_MUTUAL_EXCLUSION must be enabled. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @api - */ -void dma2dReleaseBus(DMA2DDriver *dma2dp) { - - chSysLock(); - dma2dReleaseBusS(dma2dp); - chSysUnlock(); -} - -#endif /* DMA2D_USE_MUTUAL_EXCLUSION */ - -/** @} */ - -/** - * @name DMA2D global methods - * @{ - */ - -/** - * @brief Get watermark position. - * @details Gets the watermark line position. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return watermark line position - * - * @iclass - */ -uint16_t dma2dGetWatermarkPosI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (uint16_t)(DMA2D->LWR & DMA2D_LWR_LW); -} - -/** - * @brief Get watermark position. - * @details Gets the watermark line position. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return watermark line position - * - * @api - */ -uint16_t dma2dGetWatermarkPos(DMA2DDriver *dma2dp) { - - uint16_t line; - chSysLock(); - line = dma2dGetWatermarkPosI(dma2dp); - chSysUnlock(); - return line; -} - -/** - * @brief Set watermark position. - * @details Sets the watermark line position. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] line watermark line position - * - * @iclass - */ -void dma2dSetWatermarkPosI(DMA2DDriver *dma2dp, uint16_t line) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - (void)dma2dp; - - DMA2D->LWR = ((DMA2D->LWR & ~DMA2D_LWR_LW) | - ((uint32_t)line & DMA2D_LWR_LW)); -} - -/** - * @brief Set watermark position. - * @details Sets the watermark line position. - * @note The interrupt is invoked after the last pixel of the watermark line - * is written. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] line watermark line position - * - * @iclass - */ -void dma2dSetWatermarkPos(DMA2DDriver *dma2dp, uint16_t line) { - - chSysLock(); - dma2dSetWatermarkPosI(dma2dp, line); - chSysUnlock(); -} - -/** - * @brief Watermark interrupt enabled. - * @details Tells whether the watermark interrupt is enabled. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return enabled - * - * @iclass - */ -bool dma2dIsWatermarkEnabledI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (DMA2D->CR & DMA2D_CR_TWIE) != 0; -} - -/** - * @brief Watermark interrupt enabled. - * @details Tells whether the watermark interrupt is enabled. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return enabled - * - * @api - */ -bool dma2dIsWatermarkEnabled(DMA2DDriver *dma2dp) { - - bool enabled; - chSysLock(); - enabled = dma2dIsWatermarkEnabledI(dma2dp); - chSysUnlock(); - return enabled; -} - -/** - * @brief Enable watermark interrupt. - * @details Enables the watermark interrupt. The interrupt is invoked after the - * last pixel of the watermark line is written to the output layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @iclass - */ -void dma2dEnableWatermarkI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - DMA2D->CR |= DMA2D_CR_TWIE; -} - -/** - * @brief Enable watermark interrupt. - * @details Enables the watermark interrupt. The interrupt is invoked after the - * last pixel of the watermark line is written to the output layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @api - */ -void dma2dEnableWatermark(DMA2DDriver *dma2dp) { - - chSysLock(); - dma2dEnableWatermarkI(dma2dp); - chSysUnlock(); -} - -/** - * @brief Disable watermark interrupt. - * @details Disables the watermark interrupt. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @iclass - */ -void dma2dDisableWatermarkI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - DMA2D->CR &= ~DMA2D_CR_TWIE; -} - -/** - * @brief Disable watermark interrupt. - * @details Disables the watermark interrupt. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @api - */ -void dma2dDisableWatermark(DMA2DDriver *dma2dp) { - - chSysLock(); - dma2dDisableWatermarkI(dma2dp); - chSysUnlock(); -} - -/** - * @brief Get dead time cycles. - * @details Gets the minimum dead time DMA2D clock cycles between DMA2D - * transactions. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return dead time, in DMA2D clock cycles - * - * @iclass - */ -uint32_t dma2dGetDeadTimeI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (DMA2D->AMTCR & DMA2D_AMTCR_DT) >> 8; -} - -/** - * @brief Get dead time cycles. - * @details Gets the minimum dead time DMA2D clock cycles between DMA2D - * transactions. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return dead time, in DMA2D clock cycles - * - * @api - */ -uint32_t dma2dGetDeadTime(DMA2DDriver *dma2dp) { - - uint32_t cycles; - chSysLock(); - cycles = dma2dGetDeadTimeI(dma2dp); - chSysUnlock(); - return cycles; -} - -/** - * @brief Set dead time cycles. - * @details Sets the minimum dead time DMA2D clock cycles between DMA2D - * transactions. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] cycles dead time, in DMA2D clock cycles - * - * @iclass - */ -void dma2dSetDeadTimeI(DMA2DDriver *dma2dp, uint32_t cycles) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(cycles <= DMA2D_MAX_DEADTIME_CYCLES, "bounds"); - (void)dma2dp; - - DMA2D->AMTCR = ((DMA2D->AMTCR & ~DMA2D_AMTCR_DT) | - ((cycles << 8) & DMA2D_AMTCR_DT)); -} - -/** - * @brief Set dead time cycles. - * @details Sets the minimum dead time DMA2D clock cycles between DMA2D - * transactions. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] cycles dead time, in DMA2D clock cycles - * - * @api - */ -void dma2dSetDeadTime(DMA2DDriver *dma2dp, uint32_t cycles) { - - chSysLock(); - dma2dSetDeadTimeI(dma2dp, cycles); - chSysUnlock(); -} - -/** - * @brief Dead time enabled. - * @details Tells whether the dead time between DMA2D transactions is enabled. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return enabled - * - * @iclass - */ -bool dma2dIsDeadTimeEnabledI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (DMA2D->AMTCR & DMA2D_AMTCR_EN) != 0; -} - -/** - * @brief Dead time enabled. - * @details Tells whether the dead time between DMA2D transactions is enabled. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return enabled - * - * @api - */ -bool dma2dIsDeadTimeEnabled(DMA2DDriver *dma2dp) { - - bool enabled; - chSysLock(); - enabled = dma2dIsDeadTimeEnabledI(dma2dp); - chSysUnlock(); - return enabled; -} - -/** - * @brief Enable dead time. - * @details Enables the dead time between DMA2D transactions. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @iclass - */ -void dma2dEnableDeadTimeI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - DMA2D->AMTCR |= DMA2D_AMTCR_EN; -} - -/** - * @brief Enable dead time. - * @details Enables the dead time between DMA2D transactions. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @api - */ -void dma2dEnableDeadTime(DMA2DDriver *dma2dp) { - - chSysLock(); - dma2dEnableDeadTimeI(dma2dp); - chSysUnlock(); -} - -/** - * @brief Disable dead time. - * @details Disables the dead time between DMA2D transactions. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @iclass - */ -void dma2dDisableDeadTimeI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - DMA2D->AMTCR &= ~DMA2D_AMTCR_EN; -} - -/** - * @brief Disable dead time. - * @details Disables the dead time between DMA2D transactions. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @api - */ -void dma2dDisableDeadTime(DMA2DDriver *dma2dp) { - - chSysLock(); - dma2dDisableDeadTimeI(dma2dp); - chSysUnlock(); -} - -/** @} */ - -/** - * @name DMA2D job (transaction) methods - * @{ - */ - -/** - * @brief Get job mode. - * @details Gets the job mode. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return job mode - * - * @iclass - */ -dma2d_jobmode_t dma2dJobGetModeI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (dma2d_jobmode_t)(DMA2D->CR & DMA2D_CR_MODE); -} - -/** - * @brief Get job mode. - * @details Gets the job mode. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return job mode - * - * @api - */ -dma2d_jobmode_t dma2dJobGetMode(DMA2DDriver *dma2dp) { - - dma2d_jobmode_t mode; - chSysLock(); - mode = dma2dJobGetModeI(dma2dp); - chSysUnlock(); - return mode; -} - -/** - * @brief Set job mode. - * @details Sets the job mode. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] mode job mode - * - * @iclass - */ -void dma2dJobSetModeI(DMA2DDriver *dma2dp, dma2d_jobmode_t mode) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - osalDbgAssert((mode & ~DMA2D_CR_MODE) == 0, "bounds"); - (void)dma2dp; - - DMA2D->CR = ((DMA2D->CR & ~DMA2D_CR_MODE) | - ((uint32_t)mode & DMA2D_CR_MODE)); -} - -/** - * @brief Set job mode. - * @details Sets the job mode. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] mode job mode - * - * @api - */ -void dma2dJobSetMode(DMA2DDriver *dma2dp, dma2d_jobmode_t mode) { - - chSysLock(); - dma2dJobSetModeI(dma2dp, mode); - chSysUnlock(); -} - -/** - * @brief Get job size. - * @details Gets the job size. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[out] widthp pointer to the job width, in pixels - * @param[out] heightp pointer to the job height, in pixels - * - * @iclass - */ -void dma2dJobGetSizeI(DMA2DDriver *dma2dp, - uint16_t *widthp, uint16_t *heightp) { - - uint32_t r; - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgCheck(widthp != NULL); - osalDbgCheck(heightp != NULL); - (void)dma2dp; - - r = DMA2D->NLR; - *widthp = (uint16_t)((r & DMA2D_NLR_PL) >> 16); - *heightp = (uint16_t)((r & DMA2D_NLR_NL) >> 0); -} - -/** - * @brief Get job size. - * @details Gets the job size. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[out] widthp pointer to the job width, in pixels - * @param[out] heightp pointer to the job height, in pixels - * - * @api - */ -void dma2dJobGetSize(DMA2DDriver *dma2dp, - uint16_t *widthp, uint16_t *heightp) { - - chSysLock(); - dma2dJobGetSizeI(dma2dp, widthp, heightp); - chSysUnlock(); -} - -/** - * @brief Set job size. - * @details Sets the job size. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] widthp job width, in pixels - * @param[in] heightp job height, in pixels - * - * @iclass - */ -void dma2dJobSetSizeI(DMA2DDriver *dma2dp, uint16_t width, uint16_t height) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - osalDbgAssert(width <= DMA2D_MAX_WIDTH, "bounds"); - osalDbgAssert(height <= DMA2D_MAX_HEIGHT, "bounds"); - (void)dma2dp; - - DMA2D->NLR = ((((uint32_t)width << 16) & DMA2D_NLR_PL) | - (((uint32_t)height << 0) & DMA2D_NLR_NL)); -} - -/** - * @brief Set job size. - * @details Sets the job size. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] widthp job width, in pixels - * @param[in] heightp job height, in pixels - * - * @api - */ -void dma2dJobSetSize(DMA2DDriver *dma2dp, uint16_t width, uint16_t height) { - - chSysLock(); - dma2dJobSetSizeI(dma2dp, width, height); - chSysUnlock(); -} - -/** - * @brief Job executing. - * @details Tells whether a job (transaction) is active or paused. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return executing - * - * @iclass - */ -bool dma2dJobIsExecutingI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - - return dma2dp->state > DMA2D_READY; -} - -/** - * @brief Job executing. - * @details Tells whether a job (transaction) is active or paused. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return executing - * - * @api - */ -bool dma2dJobIsExecuting(DMA2DDriver *dma2dp) { - - bool executing; - chSysLock(); - executing = dma2dJobIsExecutingI(dma2dp); - chSysUnlock(); - return executing; -} - -/** - * @brief Start job. - * @details The job is started, and the DMA2D is set to active. - * @note Should there be invalid parameters, the appropriate interrupt - * handler will be invoked, and the DMA2D set back to ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @iclass - */ -void dma2dJobStartI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - - dma2dp->state = DMA2D_ACTIVE; - DMA2D->CR |= DMA2D_CR_START; -} - -/** - * @brief Start job. - * @details The job is started, and the DMA2D is set to active. - * @note Should there be invalid parameters, the appropriate interrupt - * handler will be invoked, and the DMA2D set back to ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @api - */ -void dma2dJobStart(DMA2DDriver *dma2dp) { - - chSysLock(); - dma2dJobStartI(dma2dp); - chSysUnlock(); -} - -/** - * @brief Execute job. - * @details Starts the job and waits for its completion, synchronously. - * @note Should there be invalid parameters, the appropriate interrupt - * handler will be invoked, and the DMA2D set back to ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @sclass - */ -void dma2dJobExecuteS(DMA2DDriver *dma2dp) { - - osalDbgCheckClassS(); - osalDbgCheck(dma2dp == &DMA2DD1); - - dma2dJobStartI(dma2dp); -#if DMA2D_USE_WAIT - dma2dp->thread = chThdGetSelfX(); - chSchGoSleepS(CH_STATE_SUSPENDED); -#else - while (DMA2D->CR & DMA2D_CR_START) - chSchDoYieldS(); -#endif -} - -/** - * @brief Execute job. - * @details Starts the job and waits for its completion, synchronously. - * @note Should there be invalid parameters, the appropriate interrupt - * handler will be invoked, and the DMA2D set back to ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @api - */ -void dma2dJobExecute(DMA2DDriver *dma2dp) { - - chSysLock(); - dma2dJobExecuteS(dma2dp); - chSysUnlock(); -} - -/** - * @brief Suspend current job. - * @details Suspends the current job. The driver is set to a paused state. - * @pre There is an active job. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @iclass - */ -void dma2dJobSuspendI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgCheck((DMA2D->CR & DMA2D_CR_SUSP) == 0); - osalDbgAssert(dma2dp->state == DMA2D_ACTIVE, "invalid state"); - - dma2dp->state = DMA2D_PAUSED; - DMA2D->CR |= DMA2D_CR_SUSP; -} - -/** - * @brief Suspend current job. - * @details Suspends the current job. The driver is set to a paused state. - * @pre There is an active job. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @api - */ -void dma2dJobSuspend(DMA2DDriver *dma2dp) { - - chSysLock(); - dma2dJobSuspendI(dma2dp); - chSysUnlock(); -} - -/** - * @brief Resume current job. - * @details Resumes the current job. - * @pre There is a paused job. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @iclass - */ -void dma2dJobResumeI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgCheck((DMA2D->CR & DMA2D_CR_SUSP) != 0); - osalDbgAssert(dma2dp->state == DMA2D_PAUSED, "invalid state"); - - dma2dp->state = DMA2D_ACTIVE; - DMA2D->CR &= ~DMA2D_CR_SUSP; -} - -/** - * @brief Resume current job. - * @details Resumes the current job. - * @pre There is a paused job. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @api - */ -void dma2dJobResume(DMA2DDriver *dma2dp) { - - chSysLock(); - dma2dJobResumeI(dma2dp); - chSysUnlock(); -} - -/** - * @brief Abort current job. - * @details Abots the current job (if any), and the driver becomes ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @iclass - */ -void dma2dJobAbortI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgCheck((DMA2D->CR & DMA2D_CR_SUSP) == 0); - osalDbgAssert(dma2dp->state >= DMA2D_READY, "invalid state"); - - dma2dp->state = DMA2D_READY; - DMA2D->CR |= DMA2D_CR_ABORT; -} - -/** - * @brief Abort current job. - * @details Abots the current job (if any), and the driver becomes ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @api - */ -void dma2dJobAbort(DMA2DDriver *dma2dp) { - - chSysLock(); - dma2dJobAbortI(dma2dp); - chSysUnlock(); -} - -/** @} */ - -/** - * @name DMA2D background layer methods - * @{ - */ - -/** - * @brief Get background layer buffer address. - * @details Gets the buffer address of the background layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return buffer address - * - * @iclass - */ -void *dma2dBgGetAddressI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (void *)DMA2D->BGMAR; -} - -/** - * @brief Get background layer buffer address. - * @details Gets the buffer address of the background layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return buffer address - * - * @api - */ -void *dma2dBgGetAddress(DMA2DDriver *dma2dp) { - - void *bufferp; - chSysLock(); - bufferp = dma2dBgGetAddressI(dma2dp); - chSysUnlock(); - return bufferp; -} - -/** - * @brief Set background layer buffer address. - * @details Sets the buffer address of the background layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] bufferp buffer address - * - * @iclass - */ -void dma2dBgSetAddressI(DMA2DDriver *dma2dp, void *bufferp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - osalDbgCheck(dma2dIsAligned(bufferp, dma2dBgGetPixelFormatI(dma2dp))); - (void)dma2dp; - - DMA2D->BGMAR = (uint32_t)bufferp; -} - -/** - * @brief Set background layer buffer address. - * @details Sets the buffer address of the background layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] bufferp buffer address - * - * @api - */ -void dma2dBgSetAddress(DMA2DDriver *dma2dp, void *bufferp) { - - chSysLock(); - dma2dBgSetAddressI(dma2dp, bufferp); - chSysUnlock(); -} - -/** - * @brief Get background layer wrap offset. - * @details Gets the buffer line wrap offset of the background layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return wrap offset, in pixels - * - * @iclass - */ -size_t dma2dBgGetWrapOffsetI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (size_t)(DMA2D->BGOR & DMA2D_BGOR_LO); -} - -/** - * @brief Get background layer wrap offset. - * @details Gets the buffer line wrap offset of the background layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return wrap offset, in pixels - * - * @api - */ -size_t dma2dBgGetWrapOffset(DMA2DDriver *dma2dp) { - - size_t offset; - chSysLock(); - offset = dma2dBgGetWrapOffsetI(dma2dp); - chSysUnlock(); - return offset; -} - -/** - * @brief Set background layer wrap offset. - * @details Sets the buffer line wrap offset of the background layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] offset wrap offset, in pixels - * - * @iclass - */ -void dma2dBgSetWrapOffsetI(DMA2DDriver *dma2dp, size_t offset) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - osalDbgAssert(offset <= DMA2D_MAX_OFFSET, "bounds"); - (void)dma2dp; - - DMA2D->BGOR = ((DMA2D->BGOR & ~DMA2D_BGOR_LO) | - ((uint32_t)offset & DMA2D_BGOR_LO)); -} - -/** - * @brief Set background layer wrap offset. - * @details Sets the buffer line wrap offset of the background layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] offset wrap offset, in pixels - * - * @api - */ -void dma2dBgSetWrapOffset(DMA2DDriver *dma2dp, size_t offset) { - - chSysLock(); - dma2dBgSetWrapOffsetI(dma2dp, offset); - chSysUnlock(); -} - -/** - * @brief Get background layer constant alpha. - * @details Gets the constant alpha component of the background layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return constant alpha component, A-8 - * - * @iclass - */ -uint8_t dma2dBgGetConstantAlphaI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (uint8_t)((DMA2D->BGPFCCR & DMA2D_BGPFCCR_ALPHA) >> 24); -} - -/** - * @brief Get background layer constant alpha. - * @details Gets the constant alpha component of the background layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return constant alpha component, A-8 - * - * @api - */ -uint8_t dma2dBgGetConstantAlpha(DMA2DDriver *dma2dp) { - - uint8_t a; - chSysLock(); - a = dma2dBgGetConstantAlphaI(dma2dp); - chSysUnlock(); - return a; -} - -/** - * @brief Set background layer constant alpha. - * @details Sets the constant alpha component of the background layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] a constant alpha component, A-8 - * - * @iclass - */ -void dma2dBgSetConstantAlphaI(DMA2DDriver *dma2dp, uint8_t a) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - (void)dma2dp; - - DMA2D->BGPFCCR = ((DMA2D->BGPFCCR & ~DMA2D_BGPFCCR_ALPHA) | - (((uint32_t)a << 24) & DMA2D_BGPFCCR_ALPHA)); -} - -/** - * @brief Set background layer constant alpha. - * @details Sets the constant alpha component of the background layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] a constant alpha component, A-8 - * - * @api - */ -void dma2dBgSetConstantAlpha(DMA2DDriver *dma2dp, uint8_t a) { - - chSysLock(); - dma2dBgSetConstantAlphaI(dma2dp, a); - chSysUnlock(); -} - -/** - * @brief Get background layer alpha mode. - * @details Gets the alpha mode of the background layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return alpha mode - * - * @iclass - */ -dma2d_amode_t dma2dBgGetAlphaModeI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (dma2d_amode_t)(DMA2D->BGPFCCR & DMA2D_BGPFCCR_AM); -} - -/** - * @brief Get background layer alpha mode. - * @details Gets the alpha mode of the background layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return alpha mode - * - * @api - */ -dma2d_amode_t dma2dBgGetAlphaMode(DMA2DDriver *dma2dp) { - - dma2d_amode_t mode; - chSysLock(); - mode = dma2dBgGetAlphaModeI(dma2dp); - chSysUnlock(); - return mode; -} - -/** - * @brief Set background layer alpha mode. - * @details Sets the alpha mode of the background layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] mode alpha mode - * - * @iclass - */ -void dma2dBgSetAlphaModeI(DMA2DDriver *dma2dp, dma2d_amode_t mode) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - osalDbgAssert((mode & ~DMA2D_BGPFCCR_AM) == 0, "bounds"); - osalDbgAssert((mode & DMA2D_BGPFCCR_AM) != DMA2D_BGPFCCR_AM, "bounds"); - (void)dma2dp; - - DMA2D->BGPFCCR = ((DMA2D->BGPFCCR & ~DMA2D_BGPFCCR_AM) | - ((uint32_t)mode & DMA2D_BGPFCCR_AM)); -} - -/** - * @brief Set background layer alpha mode. - * @details Sets the alpha mode of the background layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] mode alpha mode - * - * @api - */ -void dma2dBgSetAlphaMode(DMA2DDriver *dma2dp, dma2d_amode_t mode) { - - chSysLock(); - dma2dBgSetAlphaModeI(dma2dp, mode); - chSysUnlock(); -} - -/** - * @brief Get background layer pixel format. - * @details Gets the pixel format of the background layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return pixel format - * - * @iclass - */ -dma2d_pixfmt_t dma2dBgGetPixelFormatI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (dma2d_pixfmt_t)(DMA2D->BGPFCCR & DMA2D_BGPFCCR_CM); -} - -/** - * @brief Get background layer pixel format. - * @details Gets the pixel format of the background layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return pixel format - * - * @api - */ -dma2d_pixfmt_t dma2dBgGetPixelFormat(DMA2DDriver *dma2dp) { - - dma2d_pixfmt_t fmt; - chSysLock(); - fmt = dma2dBgGetPixelFormatI(dma2dp); - chSysUnlock(); - return fmt; -} - -/** - * @brief Set background layer pixel format. - * @details Sets the pixel format of the background layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] fmt pixel format - * - * @iclass - */ -void dma2dBgSetPixelFormatI(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - osalDbgAssert(fmt <= DMA2D_MAX_PIXFMT_ID, "bounds"); - (void)dma2dp; - - DMA2D->BGPFCCR = ((DMA2D->BGPFCCR & ~DMA2D_BGPFCCR_CM) | - ((uint32_t)fmt & DMA2D_BGPFCCR_CM)); -} - -/** - * @brief Set background layer pixel format. - * @details Sets the pixel format of the background layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] fmt pixel format - * - * @api - */ -void dma2dBgSetPixelFormat(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt) { - - chSysLock(); - dma2dBgSetPixelFormatI(dma2dp, fmt); - chSysUnlock(); -} - -/** - * @brief Get background layer default color. - * @details Gets the default color of the background layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return default color, RGB-888 - * - * @iclass - */ -dma2d_color_t dma2dBgGetDefaultColorI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (dma2d_color_t)(DMA2D->BGCOLR & 0x00FFFFFF); -} - -/** - * @brief Get background layer default color. - * @details Gets the default color of the background layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return default color, RGB-888 - * - * @api - */ -dma2d_color_t dma2dBgGetDefaultColor(DMA2DDriver *dma2dp) { - - dma2d_color_t c; - chSysLock(); - c = dma2dBgGetDefaultColorI(dma2dp); - chSysUnlock(); - return c; -} - -/** - * @brief Set background layer default color. - * @details Sets the default color of the background layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] c default color, RGB-888 - * - * @iclass - */ -void dma2dBgSetDefaultColorI(DMA2DDriver *dma2dp, dma2d_color_t c) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - (void)dma2dp; - - DMA2D->BGCOLR = (uint32_t)c & 0x00FFFFFF; -} - -/** - * @brief Set background layer default color. - * @details Sets the default color of the background layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] c default color, RGB-888 - * - * @api - */ -void dma2dBgSetDefaultColor(DMA2DDriver *dma2dp, dma2d_color_t c) { - - chSysLock(); - dma2dBgSetDefaultColorI(dma2dp, c); - chSysUnlock(); -} - -/** - * @brief Get background layer palette specifications. - * @details Gets the palette specifications of the background layer. - * @note The palette colors pointer is actually addressed to a @p volatile - * memory zone. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[out] palettep pointer to the palette specifications - * - * @iclass - */ -void dma2dBgGetPaletteI(DMA2DDriver *dma2dp, dma2d_palcfg_t *palettep) { - - uint32_t r; - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgCheck(palettep != NULL); - (void)dma2dp; - - r = DMA2D->BGPFCCR; - palettep->colorsp = (const void *)DMA2D->BGCLUT; - palettep->length = (uint16_t)((r & DMA2D_BGPFCCR_CS) >> 8) + 1; - palettep->fmt = (dma2d_pixfmt_t)((r & DMA2D_BGPFCCR_CCM) >> 4); -} - -/** - * @brief Get background layer palette specifications. - * @details Gets the palette specifications of the background layer. - * @note The palette colors pointer is actually addressed to a @p volatile - * memory zone. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[out] palettep pointer to the palette specifications - * - * @api - */ -void dma2dBgGetPalette(DMA2DDriver *dma2dp, dma2d_palcfg_t *palettep) { - - chSysLock(); - dma2dBgGetPaletteI(dma2dp, palettep); - chSysUnlock(); -} - -/** - * @brief Set background layer palette specifications. - * @details Sets the palette specifications of the background layer. - * @note This function should not be called while the DMA2D is already - * executing a job, otherwise the appropriate error interrupt might be - * invoked. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] palettep pointer to the palette specifications - * - * @sclass - */ -void dma2dBgSetPaletteS(DMA2DDriver *dma2dp, const dma2d_palcfg_t *palettep) { - - osalDbgCheckClassS(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - osalDbgCheck(palettep != NULL); - osalDbgCheck(palettep->colorsp != NULL); - osalDbgAssert(palettep->length > 0, "bounds"); - osalDbgAssert(palettep->length <= DMA2D_MAX_PALETTE_LENGTH, "bounds"); - osalDbgAssert(((palettep->fmt == DMA2D_FMT_ARGB8888) || - (palettep->fmt == DMA2D_FMT_RGB888)), "invalid format"); - - DMA2D->BGCMAR = (uint32_t)palettep->colorsp; - DMA2D->BGPFCCR = ( - (DMA2D->BGPFCCR & ~(DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM)) | - ((((uint32_t)palettep->length - 1) << 8) & DMA2D_BGPFCCR_CS) | - ((uint32_t)palettep->fmt << 4) - ); - - dma2dp->state = DMA2D_ACTIVE; - DMA2D->BGPFCCR |= DMA2D_BGPFCCR_START; - -#if DMA2D_USE_WAIT - dma2dp->thread = chThdGetSelfX(); - chSchGoSleepS(CH_STATE_SUSPENDED); -#else - while (DMA2D->BGPFCCR & DMA2D_BGPFCCR_START) - chSchDoYieldS(); -#endif /* DMA2D_USE_WAIT */ -} - -/** - * @brief Set background layer palette specifications. - * @details Sets the palette specifications of the background layer. - * @note This function should not be called while the DMA2D is already - * executing a job, otherwise the appropriate error interrupt might be - * invoked. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] palettep pointer to the palette specifications - * - * @api - */ -void dma2dBgSetPalette(DMA2DDriver *dma2dp, const dma2d_palcfg_t *palettep) { - - chSysLock(); - dma2dBgSetPaletteS(dma2dp, palettep); - chSysUnlock(); -} - -/** - * @brief Get background layer specifications. - * @details Gets the background layer specifications at once. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[out] cfgp pointer to the layer specifications - * - * @iclass - */ -void dma2dBgGetLayerI(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgCheck(cfgp != NULL); - - cfgp->bufferp = dma2dBgGetAddressI(dma2dp); - cfgp->wrap_offset = dma2dBgGetWrapOffsetI(dma2dp); - cfgp->fmt = dma2dBgGetPixelFormatI(dma2dp); - cfgp->def_color = dma2dBgGetDefaultColorI(dma2dp); - cfgp->const_alpha = dma2dBgGetConstantAlphaI(dma2dp); - if (cfgp->palettep != NULL) - dma2dBgGetPaletteI(dma2dp, (dma2d_palcfg_t *)cfgp->palettep); -} - -/** - * @brief Get background layer specifications. - * @details Gets the background layer specifications at once. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[out] cfgp pointer to the layer specifications - * - * @api - */ -void dma2dBgGetLayer(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp) { - - chSysLock(); - dma2dBgGetLayerI(dma2dp, cfgp); - chSysUnlock(); -} - -/** - * @brief Set background layer specifications. - * @details Sets the background layer specifications at once. - * @note If the palette is unspecified, the layer palette is unmodified. - * @note This function should not be called while the DMA2D is already - * executing a job, otherwise the appropriate error interrupt might be - * invoked. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] cfgp pointer to the layer specifications - * - * @sclass - */ -void dma2dBgSetConfigS(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp) { - - osalDbgCheckClassS(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - osalDbgCheck(cfgp != NULL); - - dma2dBgSetAddressI(dma2dp, cfgp->bufferp); - dma2dBgSetWrapOffsetI(dma2dp, cfgp->wrap_offset); - dma2dBgSetPixelFormatI(dma2dp, cfgp->fmt); - dma2dBgSetDefaultColorI(dma2dp, cfgp->def_color); - dma2dBgSetConstantAlphaI(dma2dp, cfgp->const_alpha); - if (cfgp->palettep != NULL) - dma2dBgSetPaletteS(dma2dp, cfgp->palettep); -} - -/** - * @brief Set background layer specifications. - * @details Sets the background layer specifications at once. - * @note If the palette is unspecified, the layer palette is unmodified. - * @note This function should not be called while the DMA2D is already - * executing a job, otherwise the appropriate error interrupt might be - * invoked. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] cfgp pointer to the layer specifications - * - * @api - */ -void dma2dBgSetConfig(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp) { - - chSysLock(); - dma2dBgSetConfigS(dma2dp, cfgp); - chSysUnlock(); -} - -/** @} */ - -/** - * @name DMA2D foreground layer methods - * @{ - */ - -/** - * @brief Get foreground layer buffer address. - * @details Gets the buffer address of the foreground layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return buffer address - * - * @iclass - */ -void *dma2dFgGetAddressI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (void *)DMA2D->FGMAR; -} - -/** - * @brief Get foreground layer buffer address. - * @details Gets the buffer address of the foreground layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return buffer address - * - * @api - */ -void *dma2dFgGetAddress(DMA2DDriver *dma2dp) { - - void *bufferp; - chSysLock(); - bufferp = dma2dFgGetAddressI(dma2dp); - chSysUnlock(); - return bufferp; -} - -/** - * @brief Set foreground layer buffer address. - * @details Sets the buffer address of the foreground layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] bufferp buffer address - * - * @iclass - */ -void dma2dFgSetAddressI(DMA2DDriver *dma2dp, void *bufferp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - osalDbgCheck(dma2dIsAligned(bufferp, dma2dFgGetPixelFormatI(dma2dp))); - (void)dma2dp; - - DMA2D->FGMAR = (uint32_t)bufferp; -} - -/** - * @brief Set foreground layer buffer address. - * @details Sets the buffer address of the foreground layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] bufferp buffer address - * - * @api - */ -void dma2dFgSetAddress(DMA2DDriver *dma2dp, void *bufferp) { - - chSysLock(); - dma2dFgSetAddressI(dma2dp, bufferp); - chSysUnlock(); -} - -/** - * @brief Get foreground layer wrap offset. - * @details Gets the buffer line wrap offset of the foreground layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return wrap offset, in pixels - * - * @iclass - */ -size_t dma2dFgGetWrapOffsetI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (size_t)(DMA2D->FGOR & DMA2D_FGOR_LO); -} - -/** - * @brief Get foreground layer wrap offset. - * @details Gets the buffer line wrap offset of the foreground layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return wrap offset, in pixels - * - * @api - */ -size_t dma2dFgGetWrapOffset(DMA2DDriver *dma2dp) { - - size_t offset; - chSysLock(); - offset = dma2dFgGetWrapOffsetI(dma2dp); - chSysUnlock(); - return offset; -} - -/** - * @brief Set foreground layer wrap offset. - * @details Sets the buffer line wrap offset of the foreground layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] offset wrap offset, in pixels - * - * @iclass - */ -void dma2dFgSetWrapOffsetI(DMA2DDriver *dma2dp, size_t offset) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - osalDbgAssert(offset <= DMA2D_MAX_OFFSET, "bounds"); - (void)dma2dp; - - DMA2D->FGOR = ((DMA2D->FGOR & ~DMA2D_FGOR_LO) | - ((uint32_t)offset & DMA2D_FGOR_LO)); -} - -/** - * @brief Set foreground layer wrap offset. - * @details Sets the buffer line wrap offset of the foreground layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] offset wrap offset, in pixels - * - * @api - */ -void dma2dFgSetWrapOffset(DMA2DDriver *dma2dp, size_t offset) { - - chSysLock(); - dma2dFgSetWrapOffsetI(dma2dp, offset); - chSysUnlock(); -} - -/** - * @brief Get foreground layer constant alpha. - * @details Gets the constant alpha component of the foreground layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return constant alpha component, A-8 - * - * @iclass - */ -uint8_t dma2dFgGetConstantAlphaI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (uint8_t)((DMA2D->FGPFCCR & DMA2D_FGPFCCR_ALPHA) >> 24); -} - -/** - * @brief Get foreground layer constant alpha. - * @details Gets the constant alpha component of the foreground layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return constant alpha component, A-8 - * - * @api - */ -uint8_t dma2dFgGetConstantAlpha(DMA2DDriver *dma2dp) { - - uint8_t a; - chSysLock(); - a = dma2dFgGetConstantAlphaI(dma2dp); - chSysUnlock(); - return a; -} - -/** - * @brief Set foreground layer constant alpha. - * @details Sets the constant alpha component of the foreground layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] a constant alpha component, A-8 - * - * @iclass - */ -void dma2dFgSetConstantAlphaI(DMA2DDriver *dma2dp, uint8_t a) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - (void)dma2dp; - - DMA2D->FGPFCCR = ((DMA2D->FGPFCCR & ~DMA2D_FGPFCCR_ALPHA) | - (((uint32_t)a << 24) & DMA2D_FGPFCCR_ALPHA)); -} - -/** - * @brief Set foreground layer constant alpha. - * @details Sets the constant alpha component of the foreground layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] a constant alpha component, A-8 - * - * @api - */ -void dma2dFgSetConstantAlpha(DMA2DDriver *dma2dp, uint8_t a) { - - chSysLock(); - dma2dFgSetConstantAlphaI(dma2dp, a); - chSysUnlock(); -} - -/** - * @brief Get foreground layer alpha mode. - * @details Gets the alpha mode of the foreground layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return alpha mode - * - * @iclass - */ -dma2d_amode_t dma2dFgGetAlphaModeI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (dma2d_amode_t)(DMA2D->FGPFCCR & DMA2D_FGPFCCR_AM); -} - -/** - * @brief Get foreground layer alpha mode. - * @details Gets the alpha mode of the foreground layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return alpha mode - * - * @api - */ -dma2d_amode_t dma2dFgGetAlphaMode(DMA2DDriver *dma2dp) { - - dma2d_amode_t mode; - chSysLock(); - mode = dma2dFgGetAlphaModeI(dma2dp); - chSysUnlock(); - return mode; -} - -/** - * @brief Set foreground layer alpha mode. - * @details Sets the alpha mode of the foreground layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] mode alpha mode - * - * @iclass - */ -void dma2dFgSetAlphaModeI(DMA2DDriver *dma2dp, dma2d_amode_t mode) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - osalDbgAssert((mode & ~DMA2D_FGPFCCR_AM) == 0, "bounds"); - osalDbgAssert((mode & DMA2D_FGPFCCR_AM) != DMA2D_FGPFCCR_AM, "bounds"); - (void)dma2dp; - - DMA2D->FGPFCCR = ((DMA2D->FGPFCCR & ~DMA2D_FGPFCCR_AM) | - ((uint32_t)mode & DMA2D_FGPFCCR_AM)); -} - -/** - * @brief Set foreground layer alpha mode. - * @details Sets the alpha mode of the foreground layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] mode alpha mode - * - * @api - */ -void dma2dFgSetAlphaMode(DMA2DDriver *dma2dp, dma2d_amode_t mode) { - - chSysLock(); - dma2dFgSetAlphaModeI(dma2dp, mode); - chSysUnlock(); -} - -/** - * @brief Get foreground layer pixel format. - * @details Gets the pixel format of the foreground layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return pixel format - * - * @iclass - */ -dma2d_pixfmt_t dma2dFgGetPixelFormatI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (dma2d_pixfmt_t)(DMA2D->FGPFCCR & DMA2D_FGPFCCR_CM); -} - -/** - * @brief Get foreground layer pixel format. - * @details Gets the pixel format of the foreground layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return pixel format - * - * @api - */ -dma2d_pixfmt_t dma2dFgGetPixelFormat(DMA2DDriver *dma2dp) { - - dma2d_pixfmt_t fmt; - chSysLock(); - fmt = dma2dFgGetPixelFormatI(dma2dp); - chSysUnlock(); - return fmt; -} - -/** - * @brief Set foreground layer pixel format. - * @details Sets the pixel format of the foreground layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] fmt pixel format - * - * @iclass - */ -void dma2dFgSetPixelFormatI(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - osalDbgAssert(fmt <= DMA2D_MAX_PIXFMT_ID, "bounds"); - (void)dma2dp; - - DMA2D->FGPFCCR = ((DMA2D->FGPFCCR & ~DMA2D_FGPFCCR_CM) | - ((uint32_t)fmt & DMA2D_FGPFCCR_CM)); -} - -/** - * @brief Set foreground layer pixel format. - * @details Sets the pixel format of the foreground layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] fmt pixel format - * - * @api - */ -void dma2dFgSetPixelFormat(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt) { - - chSysLock(); - dma2dFgSetPixelFormatI(dma2dp, fmt); - chSysUnlock(); -} - -/** - * @brief Get foreground layer default color. - * @details Gets the default color of the foreground layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return default color, RGB-888 - * - * @iclass - */ -dma2d_color_t dma2dFgGetDefaultColorI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (dma2d_color_t)(DMA2D->FGCOLR & 0x00FFFFFF); -} - -/** - * @brief Get foreground layer default color. - * @details Gets the default color of the foreground layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return default color, RGB-888 - * - * @api - */ -dma2d_color_t dma2dFgGetDefaultColor(DMA2DDriver *dma2dp) { - - dma2d_color_t c; - chSysLock(); - c = dma2dFgGetDefaultColorI(dma2dp); - chSysUnlock(); - return c; -} - -/** - * @brief Set foreground layer default color. - * @details Sets the default color of the foreground layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] c default color, RGB-888 - * - * @iclass - */ -void dma2dFgSetDefaultColorI(DMA2DDriver *dma2dp, dma2d_color_t c) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - (void)dma2dp; - - DMA2D->FGCOLR = (uint32_t)c & 0x00FFFFFF; -} - -/** - * @brief Set foreground layer default color. - * @details Sets the default color of the foreground layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] c default color, RGB-888 - * - * @api - */ -void dma2dFgSetDefaultColor(DMA2DDriver *dma2dp, dma2d_color_t c) { - - chSysLock(); - dma2dFgSetDefaultColorI(dma2dp, c); - chSysUnlock(); -} - -/** - * @brief Get foreground layer palette specifications. - * @details Gets the palette specifications of the foreground layer. - * @note The palette colors pointer is actually addressed to a @p volatile - * memory zone. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[out] palettep pointer to the palette specifications - * - * @iclass - */ -void dma2dFgGetPaletteI(DMA2DDriver *dma2dp, dma2d_palcfg_t *palettep) { - - uint32_t r; - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgCheck(palettep != NULL); - (void)dma2dp; - - r = DMA2D->FGPFCCR; - palettep->colorsp = (const void *)DMA2D->FGCLUT; - palettep->length = (uint16_t)((r & DMA2D_FGPFCCR_CS) >> 8) + 1; - palettep->fmt = (dma2d_pixfmt_t)((r & DMA2D_FGPFCCR_CCM) >> 4); -} - -/** - * @brief Get foreground layer palette specifications. - * @details Gets the palette specifications of the foreground layer. - * @note The palette colors pointer is actually addressed to a @p volatile - * memory zone. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[out] palettep pointer to the palette specifications - * - * @api - */ -void dma2dFgGetPalette(DMA2DDriver *dma2dp, dma2d_palcfg_t *palettep) { - - chSysLock(); - dma2dFgGetPaletteI(dma2dp, palettep); - chSysUnlock(); -} - -/** - * @brief Set foreground layer palette specifications. - * @details Sets the palette specifications of the foreground layer. - * @note This function should not be called while the DMA2D is already - * executing a job, otherwise the appropriate error interrupt might be - * invoked. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] palettep pointer to the palette specifications - * - * @sclass - */ -void dma2dFgSetPaletteS(DMA2DDriver *dma2dp, const dma2d_palcfg_t *palettep) { - - osalDbgCheckClassS(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - osalDbgCheck(palettep != NULL); - osalDbgCheck(palettep->colorsp != NULL); - osalDbgAssert(palettep->length > 0, "bounds"); - osalDbgAssert(palettep->length <= DMA2D_MAX_PALETTE_LENGTH, "bounds"); - osalDbgAssert(((palettep->fmt == DMA2D_FMT_ARGB8888) || - (palettep->fmt == DMA2D_FMT_RGB888)), "invalid format"); - - DMA2D->FGCMAR = (uint32_t)palettep->colorsp; - DMA2D->FGPFCCR = ( - (DMA2D->FGPFCCR & ~(DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM)) | - ((((uint32_t)palettep->length - 1) << 8) & DMA2D_FGPFCCR_CS) | - ((uint32_t)palettep->fmt << 4) - ); - - dma2dp->state = DMA2D_ACTIVE; - DMA2D->FGPFCCR |= DMA2D_FGPFCCR_START; - -#if DMA2D_USE_WAIT - dma2dp->thread = chThdGetSelfX(); - chSchGoSleepS(CH_STATE_SUSPENDED); -#else - while (DMA2D->FGPFCCR & DMA2D_FGPFCCR_START) - chSchDoYieldS(); -#endif /* DMA2D_USE_WAIT */ -} - -/** - * @brief Set foreground layer palette specifications. - * @details Sets the palette specifications of the foreground layer. - * @note This function should not be called while the DMA2D is already - * executing a job, otherwise the appropriate error interrupt might be - * invoked. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] palettep pointer to the palette specifications - * - * @api - */ -void dma2dFgSetPalette(DMA2DDriver *dma2dp, const dma2d_palcfg_t *palettep) { - - chSysLock(); - dma2dFgSetPaletteS(dma2dp, palettep); - chSysUnlock(); -} - -/** - * @brief Get foreground layer specifications. - * @details Gets the foreground layer specifications at once. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[out] cfgp pointer to the layer specifications - * - * @iclass - */ -void dma2dFgGetLayerI(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgCheck(cfgp != NULL); - - cfgp->bufferp = dma2dFgGetAddressI(dma2dp); - cfgp->wrap_offset = dma2dFgGetWrapOffsetI(dma2dp); - cfgp->fmt = dma2dFgGetPixelFormatI(dma2dp); - cfgp->def_color = dma2dFgGetDefaultColorI(dma2dp); - cfgp->const_alpha = dma2dFgGetConstantAlphaI(dma2dp); - if (cfgp->palettep != NULL) - dma2dFgGetPaletteI(dma2dp, (dma2d_palcfg_t *)cfgp->palettep); -} - -/** - * @brief Get foreground layer specifications. - * @details Gets the foreground layer specifications at once. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[out] cfgp pointer to the layer specifications - * - * @api - */ -void dma2dFgGetLayer(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp) { - - chSysLock(); - dma2dFgGetLayerI(dma2dp, cfgp); - chSysUnlock(); -} - -/** - * @brief Set foreground layer specifications. - * @details Sets the foreground layer specifications at once. - * @note If the palette is unspecified, the layer palette is unmodified. - * @note This function should not be called while the DMA2D is already - * executing a job, otherwise the appropriate error interrupt might be - * invoked. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] cfgp pointer to the layer specifications - * - * @sclass - */ -void dma2dFgSetConfigS(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp) { - - osalDbgCheckClassS(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - osalDbgCheck(cfgp != NULL); - - dma2dFgSetAddressI(dma2dp, cfgp->bufferp); - dma2dFgSetWrapOffsetI(dma2dp, cfgp->wrap_offset); - dma2dFgSetPixelFormatI(dma2dp, cfgp->fmt); - dma2dFgSetDefaultColorI(dma2dp, cfgp->def_color); - dma2dFgSetConstantAlphaI(dma2dp, cfgp->const_alpha); - if (cfgp->palettep != NULL) - dma2dFgSetPaletteS(dma2dp, cfgp->palettep); -} - -/** - * @brief Set foreground layer specifications. - * @details Sets the foreground layer specifications at once. - * @note If the palette is unspecified, the layer palette is unmodified. - * @note This function should not be called while the DMA2D is already - * executing a job, otherwise the appropriate error interrupt might be - * invoked. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] cfgp pointer to the layer specifications - * - * @api - */ -void dma2dFgSetConfig(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp) { - - chSysLock(); - dma2dFgSetConfigS(dma2dp, cfgp); - chSysUnlock(); -} - -/** @} */ - -/** - * @name DMA2D output layer methods - * @{ - */ - -/** - * @brief Get output layer buffer address. - * @details Gets the buffer address of the output layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return buffer address - * - * @iclass - */ -void *dma2dOutGetAddressI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (void *)DMA2D->OMAR; -} - -/** - * @brief Get output layer buffer address. - * @details Gets the buffer address of the output layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return buffer address - * - * @api - */ -void *dma2dOutGetAddress(DMA2DDriver *dma2dp) { - - void *bufferp; - chSysLock(); - bufferp = dma2dOutGetAddressI(dma2dp); - chSysUnlock(); - return bufferp; -} - -/** - * @brief Set output layer buffer address. - * @details Sets the buffer address of the output layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] bufferp buffer address - * - * @iclass - */ -void dma2dOutSetAddressI(DMA2DDriver *dma2dp, void *bufferp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - osalDbgCheck(dma2dIsAligned(bufferp, dma2dOutGetPixelFormatI(dma2dp))); - (void)dma2dp; - - DMA2D->OMAR = (uint32_t)bufferp; -} - -/** - * @brief Set output layer buffer address. - * @details Sets the buffer address of the output layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] bufferp buffer address - * - * @api - */ -void dma2dOutSetAddress(DMA2DDriver *dma2dp, void *bufferp) { - - chSysLock(); - dma2dOutSetAddressI(dma2dp, bufferp); - chSysUnlock(); -} - -/** - * @brief Get output layer wrap offset. - * @details Gets the buffer line wrap offset of the output layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return wrap offset, in pixels - * - * @iclass - */ -size_t dma2dOutGetWrapOffsetI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (size_t)(DMA2D->OOR & DMA2D_OOR_LO); -} - -/** - * @brief Get output layer wrap offset. - * @details Gets the buffer line wrap offset of the output layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return wrap offset, in pixels - * - * @api - */ -size_t dma2dOutGetWrapOffset(DMA2DDriver *dma2dp) { - - size_t offset; - chSysLock(); - offset = dma2dOutGetWrapOffsetI(dma2dp); - chSysUnlock(); - return offset; -} - -/** - * @brief Set output layer wrap offset. - * @details Sets the buffer line wrap offset of the output layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] offset wrap offset, in pixels - * - * @iclass - */ -void dma2dOutSetWrapOffsetI(DMA2DDriver *dma2dp, size_t offset) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - osalDbgAssert(offset <= DMA2D_MAX_OFFSET, "bounds"); - (void)dma2dp; - - DMA2D->OOR = ((DMA2D->OOR & ~DMA2D_OOR_LO) | - ((uint32_t)offset & DMA2D_OOR_LO)); -} - -/** - * @brief Set output layer wrap offset. - * @details Sets the buffer line wrap offset of the output layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] offset wrap offset, in pixels - * - * @api - */ -void dma2dOutSetWrapOffset(DMA2DDriver *dma2dp, size_t offset) { - - chSysLock(); - dma2dOutSetWrapOffsetI(dma2dp, offset); - chSysUnlock(); -} - -/** - * @brief Get output layer pixel format. - * @details Gets the pixel format of the output layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return pixel format - * - * @iclass - */ -dma2d_pixfmt_t dma2dOutGetPixelFormatI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (dma2d_pixfmt_t)(DMA2D->OPFCCR & DMA2D_OPFCCR_CM); -} - -/** - * @brief Get output layer pixel format. - * @details Gets the pixel format of the output layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return pixel format - * - * @api - */ -dma2d_pixfmt_t dma2dOutGetPixelFormat(DMA2DDriver *dma2dp) { - - dma2d_pixfmt_t fmt; - chSysLock(); - fmt = dma2dOutGetPixelFormatI(dma2dp); - chSysUnlock(); - return fmt; -} - -/** - * @brief Set output layer pixel format. - * @details Sets the pixel format of the output layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] fmt pixel format - * - * @iclass - */ -void dma2dOutSetPixelFormatI(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - osalDbgAssert(fmt <= DMA2D_MAX_OUTPIXFMT_ID, "bounds"); - (void)dma2dp; - - DMA2D->OPFCCR = ((DMA2D->OPFCCR & ~DMA2D_OPFCCR_CM) | - ((uint32_t)fmt & DMA2D_OPFCCR_CM)); -} - -/** - * @brief Set output layer pixel format. - * @details Sets the pixel format of the output layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] fmt pixel format - * - * @api - */ -void dma2dOutSetPixelFormat(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt) { - - chSysLock(); - dma2dOutSetPixelFormatI(dma2dp, fmt); - chSysUnlock(); -} - -/** - * @brief Get output layer default color. - * @details Gets the default color of the output layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return default color, chosen output format - * - * @iclass - */ -dma2d_color_t dma2dOutGetDefaultColorI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (dma2d_color_t)(DMA2D->OCOLR & 0x00FFFFFF); -} - -/** - * @brief Get output layer default color. - * @details Gets the default color of the output layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return default color, chosen output format - * - * @api - */ -dma2d_color_t dma2dOutGetDefaultColor(DMA2DDriver *dma2dp) { - - dma2d_color_t c; - chSysLock(); - c = dma2dOutGetDefaultColorI(dma2dp); - chSysUnlock(); - return c; -} - -/** - * @brief Set output layer default color. - * @details Sets the default color of the output layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] c default color, chosen output format - * - * @iclass - */ -void dma2dOutSetDefaultColorI(DMA2DDriver *dma2dp, dma2d_color_t c) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - (void)dma2dp; - - DMA2D->OCOLR = (uint32_t)c & 0x00FFFFFF; -} - -/** - * @brief Set output layer default color. - * @details Sets the default color of the output layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] c default color, chosen output format - * - * @api - */ -void dma2dOutSetDefaultColor(DMA2DDriver *dma2dp, dma2d_color_t c) { - - chSysLock(); - dma2dOutSetDefaultColorI(dma2dp, c); - chSysUnlock(); -} - -/** - * @brief Get output layer specifications. - * @details Gets the output layer specifications at once. - * @note Constant alpha and palette specifications are ignored. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[out] cfgp pointer to the layer specifications - * - * @iclass - */ -void dma2dOutGetLayerI(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgCheck(cfgp != NULL); - - cfgp->bufferp = dma2dOutGetAddressI(dma2dp); - cfgp->wrap_offset = dma2dOutGetWrapOffsetI(dma2dp); - cfgp->fmt = dma2dOutGetPixelFormatI(dma2dp); - cfgp->def_color = dma2dOutGetDefaultColorI(dma2dp); -} - -/** - * @brief Get output layer specifications. - * @details Gets the output layer specifications at once. - * @note Constant alpha and palette specifications are ignored. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[out] cfgp pointer to the layer specifications - * - * @api - */ -void dma2dOutGetLayer(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp) { - - chSysLock(); - dma2dOutGetLayerI(dma2dp, cfgp); - chSysUnlock(); -} - -/** - * @brief Set output layer specifications. - * @details Sets the output layer specifications at once. - * @note Constant alpha and palette specifications are ignored. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] cfgp pointer to the layer specifications - * - * @iclass - */ -void dma2dOutSetConfigI(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - osalDbgCheck(cfgp != NULL); - - dma2dOutSetAddressI(dma2dp, cfgp->bufferp); - dma2dOutSetWrapOffsetI(dma2dp, cfgp->wrap_offset); - dma2dOutSetPixelFormatI(dma2dp, cfgp->fmt); - dma2dOutSetDefaultColorI(dma2dp, cfgp->def_color); -} - -/** - * @brief Set output layer specifications. - * @details Sets the output layer specifications at once. - * @note Constant alpha and palette specifications are ignored. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] cfgp pointer to the layer specifications - * - * @api - */ -void dma2dOutSetConfig(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp) { - - chSysLock(); - dma2dOutSetConfigI(dma2dp, cfgp); - chSysUnlock(); -} - -/** @} */ - -/** - * @name DMA2D helper functions - * @{ - */ - -/** - * @brief Compute pixel address. - * @details Computes the buffer address of a pixel, given the buffer - * specifications. - * - * @param[in] originp buffer origin address - * @param[in] pitch buffer pitch, in bytes - * @param[in] fmt buffer pixel format - * @param[in] x horizontal pixel coordinate - * @param[in] y vertical pixel coordinate - * - * @return pixel address, constant data - * - * @api - */ -const void *dma2dComputeAddressConst(const void *originp, size_t pitch, - dma2d_pixfmt_t fmt, - uint16_t x, uint16_t y) { - - osalDbgCheck(pitch > 0); - - switch (fmt) { - case DMA2D_FMT_ARGB8888: - return (const void *)((uintptr_t)originp + - (uintptr_t)y * pitch + (uintptr_t)x * 4); - case DMA2D_FMT_RGB888: - return (const void *)((uintptr_t)originp + - (uintptr_t)y * pitch + (uintptr_t)x * 3); - case DMA2D_FMT_RGB565: - case DMA2D_FMT_ARGB1555: - case DMA2D_FMT_ARGB4444: - case DMA2D_FMT_AL88: - return (const void *)((uintptr_t)originp + - (uintptr_t)y * pitch + (uintptr_t)x * 2); - case DMA2D_FMT_L8: - case DMA2D_FMT_AL44: - case DMA2D_FMT_A8: - return (const void *)((uintptr_t)originp + - (uintptr_t)y * pitch + (uintptr_t)x); - case DMA2D_FMT_L4: - case DMA2D_FMT_A4: - osalDbgAssert((x & 1) == 0, "not aligned"); - return (const void *)((uintptr_t)originp + - (uintptr_t)y * pitch + (uintptr_t)x / 2); - default: - osalDbgAssert(false, "invalid format"); - return NULL; - } -} - -/** - * @brief Address is aligned. - * @details Tells whether the address is aligned with the provided pixel format. - * - * @param[in] bufferp address - * @param[in] fmt pixel format - * - * @return address is aligned - * - * @api - */ -bool dma2dIsAligned(const void *bufferp, dma2d_pixfmt_t fmt) { - - switch (fmt) { - case DMA2D_FMT_ARGB8888: - case DMA2D_FMT_RGB888: - return ((uintptr_t)bufferp & 3) == 0; /* 32-bit alignment.*/ - case DMA2D_FMT_RGB565: - case DMA2D_FMT_ARGB1555: - case DMA2D_FMT_ARGB4444: - case DMA2D_FMT_AL88: - return ((uintptr_t)bufferp & 1) == 0; /* 16-bit alignment.*/ - case DMA2D_FMT_L8: - case DMA2D_FMT_AL44: - case DMA2D_FMT_L4: - case DMA2D_FMT_A8: - case DMA2D_FMT_A4: - return true; /* 8-bit alignment.*/ - default: - osalDbgAssert(false, "invalid format"); - return false; - } -} - -/** - * @brief Compute bits per pixel. - * @details Computes the bits per pixel for the specified pixel format. - * - * @param[in] fmt pixel format - * - * @retuen bits per pixel - * - * @api - */ -size_t dma2dBitsPerPixel(dma2d_pixfmt_t fmt) { - - osalDbgAssert(fmt < DMA2D_MAX_PIXFMT_ID, "invalid format"); - - return (size_t)dma2d_bpp[(unsigned)fmt]; -} - -#if DMA2D_USE_SOFTWARE_CONVERSIONS || defined(__DOXYGEN__) - -/** - * @brief Convert from ARGB-8888. - * @details Converts an ARGB-8888 color to the specified pixel format. - * - * @param[in] c color, ARGB-8888 - * @param[in] fmt target pixel format - * - * @return raw color value for the target pixel format, left - * padded with zeros. - * - * @api - */ -dma2d_color_t dma2dFromARGB8888(dma2d_color_t c, dma2d_pixfmt_t fmt) { - - switch (fmt) { - case DMA2D_FMT_ARGB8888: { - return c; - } - case DMA2D_FMT_RGB888: { - return (c & 0x00FFFFFF); - } - case DMA2D_FMT_RGB565: { - return (((c & 0x000000F8) >> ( 8 - 5)) | - ((c & 0x0000FC00) >> (16 - 11)) | - ((c & 0x00F80000) >> (24 - 16))); - } - case DMA2D_FMT_ARGB1555: { - return (((c & 0x000000F8) >> ( 8 - 5)) | - ((c & 0x0000F800) >> (16 - 10)) | - ((c & 0x00F80000) >> (24 - 15)) | - ((c & 0x80000000) >> (32 - 16))); - } - case DMA2D_FMT_ARGB4444: { - return (((c & 0x000000F0) >> ( 8 - 4)) | - ((c & 0x0000F000) >> (16 - 8)) | - ((c & 0x00F00000) >> (24 - 12)) | - ((c & 0xF0000000) >> (32 - 16))); - } - case DMA2D_FMT_L8: { - return (c & 0x000000FF); - } - case DMA2D_FMT_AL44: { - return (((c & 0x000000F0) >> ( 8 - 4)) | - ((c & 0xF0000000) >> (32 - 8))); - } - case DMA2D_FMT_AL88: { - return (((c & 0x000000FF) >> ( 8 - 8)) | - ((c & 0xFF000000) >> (32 - 16))); - } - case DMA2D_FMT_L4: { - return (c & 0x0000000F); - } - case DMA2D_FMT_A8: { - return ((c & 0xFF000000) >> (32 - 8)); - } - case DMA2D_FMT_A4: { - return ((c & 0xF0000000) >> (32 - 4)); - } - default: - osalDbgAssert(false, "invalid format"); - return 0; - } -} - -/** - * @brief Convert to ARGB-8888. - * @details Converts color of the specified pixel format to an ARGB-8888 color. - * - * @param[in] c color for the source pixel format, left padded with - * zeros. - * @param[in] fmt source pixel format - * - * @return color in ARGB-8888 format - * - * @api - */ -dma2d_color_t dma2dToARGB8888(dma2d_color_t c, dma2d_pixfmt_t fmt) { - - switch (fmt) { - case DMA2D_FMT_ARGB8888: { - return c; - } - case DMA2D_FMT_RGB888: { - return ((c & 0x00FFFFFF) | 0xFF000000); - } - case DMA2D_FMT_RGB565: { - register dma2d_color_t output = 0xFF000000; - if (c & 0x001F) output |= (((c & 0x001F) << ( 8 - 5)) | 0x00000007); - if (c & 0x07E0) output |= (((c & 0x07E0) << (16 - 11)) | 0x00000300); - if (c & 0xF800) output |= (((c & 0xF800) << (24 - 16)) | 0x00070000); - return output; - } - case DMA2D_FMT_ARGB1555: { - register dma2d_color_t output = 0x00000000; - if (c & 0x001F) output |= (((c & 0x001F) << ( 8 - 5)) | 0x00000007); - if (c & 0x03E0) output |= (((c & 0x03E0) << (16 - 10)) | 0x00000700); - if (c & 0x7C00) output |= (((c & 0x7C00) << (24 - 15)) | 0x00070000); - if (c & 0x8000) output |= 0xFF000000; - return output; - } - case DMA2D_FMT_ARGB4444: { - register dma2d_color_t output = 0x00000000; - if (c & 0x000F) output |= (((c & 0x000F) << ( 8 - 4)) | 0x0000000F); - if (c & 0x00F0) output |= (((c & 0x00F0) << (16 - 8)) | 0x00000F00); - if (c & 0x0F00) output |= (((c & 0x0F00) << (24 - 12)) | 0x000F0000); - if (c & 0xF000) output |= (((c & 0xF000) << (32 - 16)) | 0x0F000000); - return output; - } - case DMA2D_FMT_L8: { - return (c & 0xFF) | 0xFF000000; - } - case DMA2D_FMT_AL44: { - register dma2d_color_t output = 0x00000000; - if (c & 0x0F) output |= (((c & 0x0F) << ( 8 - 4)) | 0x0000000F); - if (c & 0xF0) output |= (((c & 0xF0) << (32 - 8)) | 0x0F000000); - return output; - } - case DMA2D_FMT_AL88: { - return (((c & 0x00FF) << ( 8 - 8)) | - ((c & 0xFF00) << (32 - 16))); - } - case DMA2D_FMT_L4: { - return ((c & 0x0F) | 0xFF000000); - } - case DMA2D_FMT_A8: { - return ((c & 0xFF) << (32 - 8)); - } - case DMA2D_FMT_A4: { - return ((c & 0x0F) << (32 - 4)); - } - default: - osalDbgAssert(false, "invalid format"); - return 0; - } -} - -#endif /* DMA2D_NEED_CONVERSIONS */ - -/** @} */ - -/** @} */ - -#endif /* STM32_DMA2D_USE_DMA2D */ diff --git a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.h b/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.h deleted file mode 100644 index c06ab625b8..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.h +++ /dev/null @@ -1,664 +0,0 @@ -/* - Copyright (C) 2013-2015 Andrea Zoppi - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_stm32_dma2d.h - * @brief DMA2D/Chrom-ART driver. - * - * @addtogroup dma2d - * @{ - */ - -#ifndef HAL_STM32_DMA2D_H_ -#define HAL_STM32_DMA2D_H_ - -/** - * @brief Using the DMA2D driver. - */ -#if !defined(STM32_DMA2D_USE_DMA2D) || defined(__DOXYGEN__) -#define STM32_DMA2D_USE_DMA2D (FALSE) -#endif - -#if (TRUE == STM32_DMA2D_USE_DMA2D) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name DMA2D job modes - * @{ - */ -#define DMA2D_JOB_COPY (0 << 16) /**< Copy, replace(FG only).*/ -#define DMA2D_JOB_CONVERT (1 << 16) /**< Copy, convert (FG + PFC).*/ -#define DMA2D_JOB_BLEND (2 << 16) /**< Copy, blend (FG + BG + PFC).*/ -#define DMA2D_JOB_CONST (3 << 16) /**< Default color only (FG REG).*/ -/** @} */ - -/** - * @name DMA2D enable flag - * @{ - */ -#define DMA2D_EF_ENABLE (1 << 0) /**< DMA2D enabled.*/ -#define DMA2D_EF_DITHER (1 << 16) /**< Dithering enabled.*/ -#define DMA2D_EF_PIXCLK_INVERT (1 << 28) /**< Inverted pixel clock.*/ -#define DMA2D_EF_DATAEN_HIGH (1 << 29) /**< Active-high data enable.*/ -#define DMA2D_EF_VSYNC_HIGH (1 << 30) /**< Active-high vsync.*/ -#define DMA2D_EF_HSYNC_HIGH (1 << 31) /**< Active-high hsync.*/ - -/** Enable flags mask. */ -#define DMA2D_EF_MASK \ - (DMA2D_EF_ENABLE | DMA2D_EF_DITHER | DMA2D_EF_PIXCLK_INVERT | \ - DMA2D_EF_DATAEN_HIGH | DMA2D_EF_VSYNC_HIGH | DMA2D_EF_HSYNC_HIGH) -/** @} */ - -/** - * @name DMA2D layer enable flags - * @{ - */ -#define DMA2D_LEF_ENABLE (1 << 0) /**< Layer enabled*/ -#define DMA2D_LEF_KEYING (1 << 1) /**< Color keying enabled.*/ -#define DMA2D_LEF_PALETTE (1 << 4) /**< Palette enabled.*/ - -/** Layer enable flag masks. */ -#define DMA2D_LEF_MASK \ - (DMA2D_LEF_ENABLE | DMA2D_LEF_KEYING | DMA2D_LEF_PALETTE) -/** @} */ - -/** - * @name DMA2D pixel formats - * @{ - */ -#define DMA2D_FMT_ARGB8888 (0) /**< ARGB-8888 format.*/ -#define DMA2D_FMT_RGB888 (1) /**< RGB-888 format.*/ -#define DMA2D_FMT_RGB565 (2) /**< RGB-565 format.*/ -#define DMA2D_FMT_ARGB1555 (3) /**< ARGB-1555 format.*/ -#define DMA2D_FMT_ARGB4444 (4) /**< ARGB-4444 format.*/ -#define DMA2D_FMT_L8 (5) /**< L-8 format.*/ -#define DMA2D_FMT_AL44 (6) /**< AL-44 format.*/ -#define DMA2D_FMT_AL88 (7) /**< AL-88 format.*/ -#define DMA2D_FMT_L4 (8) /**< L-4 format.*/ -#define DMA2D_FMT_A8 (9) /**< A-8 format.*/ -#define DMA2D_FMT_A4 (10) /**< A-4 format.*/ -/** @} */ - -/** - * @name DMA2D pixel format aliased raw masks - * @{ - */ -#define DMA2D_XMASK_ARGB8888 (0xFFFFFFFF) /**< ARGB-8888 aliased mask.*/ -#define DMA2D_XMASK_RGB888 (0x00FFFFFF) /**< RGB-888 aliased mask.*/ -#define DMA2D_XMASK_RGB565 (0x00F8FCF8) /**< RGB-565 aliased mask.*/ -#define DMA2D_XMASK_ARGB1555 (0x80F8F8F8) /**< ARGB-1555 aliased mask.*/ -#define DMA2D_XMASK_ARGB4444 (0xF0F0F0F0) /**< ARGB-4444 aliased mask.*/ -#define DMA2D_XMASK_L8 (0x000000FF) /**< L-8 aliased mask.*/ -#define DMA2D_XMASK_AL44 (0xF00000F0) /**< AL-44 aliased mask.*/ -#define DMA2D_XMASK_AL88 (0xFF0000FF) /**< AL-88 aliased mask.*/ -#define DMA2D_XMASK_L4 (0x0000000F) /**< L-4 aliased mask.*/ -#define DMA2D_XMASK_A8 (0xFF000000) /**< A-8 aliased mask.*/ -#define DMA2D_XMASK_A4 (0xF0000000) /**< A-4 aliased mask.*/ -/** @} */ - -/** - * @name DMA2D alpha modes - * @{ - */ -#define DMA2D_ALPHA_KEEP (0x00000000) /**< Original alpha channel.*/ -#define DMA2D_ALPHA_REPLACE (0x00010000) /**< Replace with constant.*/ -#define DMA2D_ALPHA_MODULATE (0x00020000) /**< Modulate with constant.*/ -/** @} */ - -/** - * @name DMA2D parameter bounds - * @{ - */ - -#define DMA2D_MIN_PIXFMT_ID (0) /**< Minimum pixel format ID.*/ -#define DMA2D_MAX_PIXFMT_ID (11) /**< Maximum pixel format ID.*/ -#define DMA2D_MIN_OUTPIXFMT_ID (0) /**< Minimum output pixel format ID.*/ -#define DMA2D_MAX_OUTPIXFMT_ID (4) /**< Maximum output pixel format ID.*/ - -#define DMA2D_MAX_OFFSET ((1 << 14) - 1) - -#define DMA2D_MAX_PALETTE_LENGTH (256) /***/ - -#define DMA2D_MAX_WIDTH ((1 << 14) - 1) -#define DMA2D_MAX_HEIGHT ((1 << 16) - 1) - -#define DMA2D_MAX_WATERMARK_POS ((1 << 16) - 1) - -#define DMA2D_MAX_DEADTIME_CYCLES ((1 << 8) - 1) - -/** @} */ - -/** - * @name DMA2D basic ARGB-8888 colors. - * @{ - */ -/* Microsoft Windows default 16-color palette.*/ -#define DMA2D_COLOR_BLACK (0xFF000000) -#define DMA2D_COLOR_MAROON (0xFF800000) -#define DMA2D_COLOR_GREEN (0xFF008000) -#define DMA2D_COLOR_OLIVE (0xFF808000) -#define DMA2D_COLOR_NAVY (0xFF000080) -#define DMA2D_COLOR_PURPLE (0xFF800080) -#define DMA2D_COLOR_TEAL (0xFF008080) -#define DMA2D_COLOR_SILVER (0xFFC0C0C0) -#define DMA2D_COLOR_GRAY (0xFF808080) -#define DMA2D_COLOR_RED (0xFFFF0000) -#define DMA2D_COLOR_LIME (0xFF00FF00) -#define DMA2D_COLOR_YELLOW (0xFFFFFF00) -#define DMA2D_COLOR_BLUE (0xFF0000FF) -#define DMA2D_COLOR_FUCHSIA (0xFFFF00FF) -#define DMA2D_COLOR_AQUA (0xFF00FFFF) -#define DMA2D_COLOR_WHITE (0xFFFFFFFF) -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name DMA2D configuration options - * @{ - */ - -/** - * @brief DMA2D event interrupt priority level setting. - */ -#if !defined(STM32_DMA2D_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_DMA2D_IRQ_PRIORITY (11) -#endif - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DMA2D_USE_WAIT) || defined(__DOXYGEN__) -#define DMA2D_USE_WAIT (TRUE) -#endif - -/** - * @brief Enables the @p dma2dAcquireBus() and @p dma2dReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DMA2D_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define DMA2D_USE_MUTUAL_EXCLUSION (TRUE) -#endif - -/** - * @brief Provides software color conversion functions. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DMA2D_USE_SOFTWARE_CONVERSIONS) || defined(__DOXYGEN__) -#define DMA2D_USE_SOFTWARE_CONVERSIONS (TRUE) -#endif - -/** - * @brief Enables checks for DMA2D functions. - * @note Disabling this option saves both code and data space. - * @note Disabling checks by ChibiOS will automatically disable DMA2D checks. - */ -#if !defined(DMA2D_USE_CHECKS) || defined(__DOXYGEN__) -#define DMA2D_USE_CHECKS (TRUE) -#endif - -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if (TRUE != STM32_HAS_DMA2D) -#error "DMA2D must be present when using the DMA2D subsystem" -#endif - -#if (TRUE != STM32_DMA2D_USE_DMA2D) && (TRUE != STM32_HAS_DMA2D) -#error "DMA2D not present in the selected device" -#endif - -#if (TRUE == DMA2D_USE_MUTUAL_EXCLUSION) -#if (TRUE != CH_CFG_USE_MUTEXES) && (TRUE != CH_CFG_USE_SEMAPHORES) -#error "DMA2D_USE_MUTUAL_EXCLUSION requires CH_CFG_USE_MUTEXES and/or CH_CFG_USE_SEMAPHORES" -#endif -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/* Complex types forwarding.*/ -typedef union dma2d_coloralias_t dma2d_coloralias_t; -typedef struct dma2d_palcfg_t dma2d_palcfg_t; -typedef struct dma2d_laycfg_t dma2d_layercfg_t; -typedef struct DMA2DConfig DMA2DConfig; -typedef enum dma2d_state_t dma2d_state_t; -typedef struct DMA2DDriver DMA2DDriver; - -/** - * @name DMA2D Data types - * @{ - */ - -/** - * @brief DMA2D generic color. - */ -typedef uint32_t dma2d_color_t; - -/** - * @brief DMA2D color aliases. - * @detail Mapped with ARGB-8888, except for luminance (L mapped onto B). - * Padding fields are prefixed with 'x', and should be clear - * (all 0) before compression and set (all 1) after expansion. - */ -typedef union dma2d_coloralias_t { - struct { - unsigned b : 8; - unsigned g : 8; - unsigned r : 8; - unsigned a : 8; - } argb8888; /**< Mapped ARGB-8888 bits.*/ - struct { - unsigned b : 8; - unsigned g : 8; - unsigned r : 8; - unsigned xa : 8; - } rgb888; /**< Mapped RGB-888 bits.*/ - struct { - unsigned xb : 3; - unsigned b : 5; - unsigned xg : 2; - unsigned g : 6; - unsigned xr : 3; - unsigned r : 5; - unsigned xa : 8; - } rgb565; /**< Mapped RGB-565 bits.*/ - struct { - unsigned xb : 3; - unsigned b : 5; - unsigned xg : 3; - unsigned g : 5; - unsigned xr : 3; - unsigned r : 5; - unsigned xa : 7; - unsigned a : 1; - } argb1555; /**< Mapped ARGB-1555 values.*/ - struct { - unsigned xb : 4; - unsigned b : 4; - unsigned xg : 4; - unsigned g : 4; - unsigned xr : 4; - unsigned r : 4; - unsigned xa : 4; - unsigned a : 4; - } argb4444; /**< Mapped ARGB-4444 values.*/ - struct { - unsigned l : 8; - unsigned x : 16; - unsigned xa : 8; - } l8; /**< Mapped L-8 bits.*/ - struct { - unsigned xl : 4; - unsigned l : 4; - unsigned x : 16; - unsigned xa : 4; - unsigned a : 4; - } al44; /**< Mapped AL-44 bits.*/ - struct { - unsigned l : 8; - unsigned x : 16; - unsigned a : 8; - } al88; /**< Mapped AL-88 bits.*/ - struct { - unsigned l : 4; - unsigned xl : 4; - unsigned x : 16; - unsigned xa : 8; - } l4; /**< Mapped L-4 bits.*/ - struct { - unsigned x : 24; - unsigned a : 8; - } a8; /**< Mapped A-8 bits.*/ - struct { - unsigned x : 24; - unsigned xa : 4; - unsigned a : 4; - } a4; /**< Mapped A-4 bits.*/ - dma2d_color_t aliased; /**< Aliased raw bits.*/ -} dma2d_coloralias_t; - -/** - * @brief DMA2D job (transfer) mode. - */ -typedef uint32_t dma2d_jobmode_t; - -/** - * @brief DMA2D pixel format. - */ -typedef uint32_t dma2d_pixfmt_t; - -/** - * @brief DMA2D alpha mode. - */ -typedef uint32_t dma2d_amode_t; - -/** - * @brief DMA2D ISR callback. - */ -typedef void (*dma2d_isrcb_t)(DMA2DDriver *dma2dp); - -/** - * @brief DMA2D palette specifications. - */ -typedef struct dma2d_palcfg_t { - const void *colorsp; /**< Pointer to color entries.*/ - uint16_t length; /**< Number of color entries.*/ - dma2d_pixfmt_t fmt; /**< Format, RGB-888 or ARGB-8888.*/ -} dma2d_palcfg_t; - -/** - * @brief DMA2D layer specifications. - */ -typedef struct dma2d_layercfg_t { - void *bufferp; /**< Frame buffer address.*/ - size_t wrap_offset; /**< Offset between lines, in pixels.*/ - dma2d_pixfmt_t fmt; /**< Pixel format.*/ - dma2d_color_t def_color; /**< Default color, RGB-888.*/ - uint8_t const_alpha; /**< Constant alpha factor.*/ - const dma2d_palcfg_t *palettep; /**< Palette specs, or @p NULL.*/ -} dma2d_laycfg_t; - -/** - * @brief DMA2D driver configuration. - */ -typedef struct DMA2DConfig { - /* ISR callbacks.*/ - dma2d_isrcb_t cfgerr_isr; /**< Configuration error, or @p NULL.*/ - dma2d_isrcb_t paltrfdone_isr; /**< Palette transfer done, or @p NULL.*/ - dma2d_isrcb_t palacserr_isr; /**< Palette access error, or @p NULL.*/ - dma2d_isrcb_t trfwmark_isr; /**< Transfer watermark, or @p NULL.*/ - dma2d_isrcb_t trfdone_isr; /**< Transfer complete, or @p NULL.*/ - dma2d_isrcb_t trferr_isr; /**< Transfer error, or @p NULL.*/ -} DMA2DConfig; - -/** - * @brief DMA2D driver state. - */ -typedef enum dma2d_state_t { - DMA2D_UNINIT = (0), /**< Not initialized.*/ - DMA2D_STOP = (1), /**< Stopped.*/ - DMA2D_READY = (2), /**< Ready.*/ - DMA2D_ACTIVE = (3), /**< Executing commands.*/ - DMA2D_PAUSED = (4), /**< Transfer suspended.*/ -} dma2d_state_t; - -/** - * @brief DMA2D driver. - */ -typedef struct DMA2DDriver { - dma2d_state_t state; /**< Driver state.*/ - const DMA2DConfig *config; /**< Driver configuration.*/ - - /* Multithreading stuff.*/ -#if (TRUE == DMA2D_USE_WAIT) || defined(__DOXYGEN__) - thread_t *thread; /**< Waiting thread.*/ -#endif /* DMA2D_USE_WAIT */ -#if (TRUE == DMA2D_USE_MUTUAL_EXCLUSION) -#if (TRUE == CH_CFG_USE_MUTEXES) - mutex_t lock; /**< Multithreading lock.*/ -#elif (TRUE == CH_CFG_USE_SEMAPHORES) - semaphore_t lock; /**< Multithreading lock.*/ -#endif -#endif /* DMA2D_USE_MUTUAL_EXCLUSION */ -} DMA2DDriver; - -/** @} */ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Makes an ARGB-8888 value from byte components. - * - * @param[in] a alpha byte component - * @param[in] r red byte component - * @param[in] g green byte component - * @param[in] b blue byte component - * - * @return color in ARGB-8888 format - * - * @api - */ -#define dma2dMakeARGB8888(a, r, g, b) \ - ((((dma2d_color_t)(a) & 0xFF) << 24) | \ - (((dma2d_color_t)(r) & 0xFF) << 16) | \ - (((dma2d_color_t)(g) & 0xFF) << 8) | \ - (((dma2d_color_t)(b) & 0xFF) << 0)) - -/** - * @brief Compute bytes per pixel. - * @details Computes the bytes per pixel for the specified pixel format. - * Rounds to the ceiling. - * - * @param[in] fmt pixel format - * - * @return bytes per pixel - * - * @api - */ -#define dma2dBytesPerPixel(fmt) \ - ((dma2dBitsPerPixel(fmt) + 7) >> 3) - -/** - * @brief Compute pixel address. - * @details Computes the buffer address of a pixel, given the buffer - * specifications. - * - * @param[in] originp buffer origin address - * @param[in] pitch buffer pitch, in bytes - * @param[in] fmt buffer pixel format - * @param[in] x horizontal pixel coordinate - * @param[in] y vertical pixel coordinate - * - * @return pixel address - * - * @api - */ -#define dma2dComputeAddress(originp, pitch, fmt, x, y) \ - ((void *)dma2dComputeAddressConst(originp, pitch, fmt, x, y)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -extern DMA2DDriver DMA2DD1; - -#ifdef __cplusplus -extern "C" { -#endif - - /* Driver methods.*/ - void dma2dInit(void); - void dma2dObjectInit(DMA2DDriver *dma2dp); - dma2d_state_t dma2dGetStateI(DMA2DDriver *dma2dp); - dma2d_state_t dma2dGetState(DMA2DDriver *dma2dp); - void dma2dStart(DMA2DDriver *dma2dp, const DMA2DConfig *configp); - void dma2dStop(DMA2DDriver *dma2dp); -#if (TRUE == DMA2D_USE_MUTUAL_EXCLUSION) - void dma2dAcquireBusS(DMA2DDriver *dma2dp); - void dma2dAcquireBus(DMA2DDriver *dma2dp); - void dma2dReleaseBusS(DMA2DDriver *dma2dp); - void dma2dReleaseBus(DMA2DDriver *dma2dp); -#endif /* DMA2D_USE_MUTUAL_EXCLUSION */ - - /* Global methods.*/ - uint16_t dma2dGetWatermarkPosI(DMA2DDriver *dma2dp); - uint16_t dma2dGetWatermarkPos(DMA2DDriver *dma2dp); - void dma2dSetWatermarkPosI(DMA2DDriver *dma2dp, uint16_t line); - void dma2dSetWatermarkPos(DMA2DDriver *dma2dp, uint16_t line); - bool dma2dIsWatermarkEnabledI(DMA2DDriver *dma2dp); - bool dma2dIsWatermarkEnabled(DMA2DDriver *dma2dp); - void dma2dEnableWatermarkI(DMA2DDriver *dma2dp); - void dma2dEnableWatermark(DMA2DDriver *dma2dp); - void dma2dDisableWatermarkI(DMA2DDriver *dma2dp); - void dma2dDisableWatermark(DMA2DDriver *dma2dp); - uint32_t dma2dGetDeadTimeI(DMA2DDriver *dma2dp); - uint32_t dma2dGetDeadTime(DMA2DDriver *dma2dp); - void dma2dSetDeadTimeI(DMA2DDriver *dma2dp, uint32_t cycles); - void dma2dSetDeadTime(DMA2DDriver *dma2dp, uint32_t cycles); - bool dma2dIsDeadTimeEnabledI(DMA2DDriver *dma2dp); - bool dma2dIsDeadTimeEnabled(DMA2DDriver *dma2dp); - void dma2dEnableDeadTimeI(DMA2DDriver *dma2dp); - void dma2dEnableDeadTime(DMA2DDriver *dma2dp); - void dma2dDisableDeadTimeI(DMA2DDriver *dma2dp); - void dma2dDisableDeadTime(DMA2DDriver *dma2dp); - - /* Job methods.*/ - dma2d_jobmode_t dma2dJobGetModeI(DMA2DDriver *dma2dp); - dma2d_jobmode_t dma2dJobGetMode(DMA2DDriver *dma2dp); - void dma2dJobSetModeI(DMA2DDriver *dma2dp, dma2d_jobmode_t mode); - void dma2dJobSetMode(DMA2DDriver *dma2dp, dma2d_jobmode_t mode); - void dma2dJobGetSizeI(DMA2DDriver *dma2dp, - uint16_t *widthp, uint16_t *heightp); - void dma2dJobGetSize(DMA2DDriver *dma2dp, - uint16_t *widthp, uint16_t *heightp); - void dma2dJobSetSizeI(DMA2DDriver *dma2dp, uint16_t width, uint16_t height); - void dma2dJobSetSize(DMA2DDriver *dma2dp, uint16_t width, uint16_t height); - bool dma2dJobIsExecutingI(DMA2DDriver *dma2dp); - bool dma2dJobIsExecuting(DMA2DDriver *dma2dp); - void dma2dJobStartI(DMA2DDriver *dma2dp); - void dma2dJobStart(DMA2DDriver *dma2dp); - void dma2dJobExecuteS(DMA2DDriver *dma2dp); - void dma2dJobExecute(DMA2DDriver *dma2dp); - void dma2dJobSuspendI(DMA2DDriver *dma2dp); - void dma2dJobSuspend(DMA2DDriver *dma2dp); - void dma2dJobResumeI(DMA2DDriver *dma2dp); - void dma2dJobResume(DMA2DDriver *dma2dp); - void dma2dJobAbortI(DMA2DDriver *dma2dp); - void dma2dJobAbort(DMA2DDriver *dma2dp); - - /* Background layer methods.*/ - void *dma2dBgGetAddressI(DMA2DDriver *dma2dp); - void *dma2dBgGetAddress(DMA2DDriver *dma2dp); - void dma2dBgSetAddressI(DMA2DDriver *dma2dp, void *bufferp); - void dma2dBgSetAddress(DMA2DDriver *dma2dp, void *bufferp); - size_t dma2dBgGetWrapOffsetI(DMA2DDriver *dma2dp); - size_t dma2dBgGetWrapOffset(DMA2DDriver *dma2dp); - void dma2dBgSetWrapOffsetI(DMA2DDriver *dma2dp, size_t offset); - void dma2dBgSetWrapOffset(DMA2DDriver *dma2dp, size_t offset); - uint8_t dma2dBgGetConstantAlphaI(DMA2DDriver *dma2dp); - uint8_t dma2dBgGetConstantAlpha(DMA2DDriver *dma2dp); - void dma2dBgSetConstantAlphaI(DMA2DDriver *dma2dp, uint8_t a); - void dma2dBgSetConstantAlpha(DMA2DDriver *dma2dp, uint8_t a); - dma2d_amode_t dma2dBgGetAlphaModeI(DMA2DDriver *dma2dp); - dma2d_amode_t dma2dBgGetAlphaMode(DMA2DDriver *dma2dp); - void dma2dBgSetAlphaModeI(DMA2DDriver *dma2dp, dma2d_amode_t mode); - void dma2dBgSetAlphaMode(DMA2DDriver *dma2dp, dma2d_amode_t mode); - dma2d_pixfmt_t dma2dBgGetPixelFormatI(DMA2DDriver *dma2dp); - dma2d_pixfmt_t dma2dBgGetPixelFormat(DMA2DDriver *dma2dp); - void dma2dBgSetPixelFormatI(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt); - void dma2dBgSetPixelFormat(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt); - dma2d_color_t dma2dBgGetDefaultColorI(DMA2DDriver *dma2dp); - dma2d_color_t dma2dBgGetDefaultColor(DMA2DDriver *dma2dp); - void dma2dBgSetDefaultColorI(DMA2DDriver *dma2dp, dma2d_color_t c); - void dma2dBgSetDefaultColor(DMA2DDriver *dma2dp, dma2d_color_t c); - void dma2dBgGetPaletteI(DMA2DDriver *dma2dp, dma2d_palcfg_t *palettep); - void dma2dBgGetPalette(DMA2DDriver *dma2dp, dma2d_palcfg_t *palettep); - void dma2dBgSetPaletteS(DMA2DDriver *dma2dp, const dma2d_palcfg_t *palettep); - void dma2dBgSetPalette(DMA2DDriver *dma2dp, const dma2d_palcfg_t *palettep); - void dma2dBgGetLayerI(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp); - void dma2dBgGetLayer(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp); - void dma2dBgSetConfigS(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp); - void dma2dBgSetConfig(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp); - - /* Foreground layer methods.*/ - void *dma2dFgGetAddressI(DMA2DDriver *dma2dp); - void *dma2dFgGetAddress(DMA2DDriver *dma2dp); - void dma2dFgSetAddressI(DMA2DDriver *dma2dp, void *bufferp); - void dma2dFgSetAddress(DMA2DDriver *dma2dp, void *bufferp); - size_t dma2dFgGetWrapOffsetI(DMA2DDriver *dma2dp); - size_t dma2dFgGetWrapOffset(DMA2DDriver *dma2dp); - void dma2dFgSetWrapOffsetI(DMA2DDriver *dma2dp, size_t offset); - void dma2dFgSetWrapOffset(DMA2DDriver *dma2dp, size_t offset); - uint8_t dma2dFgGetConstantAlphaI(DMA2DDriver *dma2dp); - uint8_t dma2dFgGetConstantAlpha(DMA2DDriver *dma2dp); - void dma2dFgSetConstantAlphaI(DMA2DDriver *dma2dp, uint8_t a); - void dma2dFgSetConstantAlpha(DMA2DDriver *dma2dp, uint8_t a); - dma2d_amode_t dma2dFgGetAlphaModeI(DMA2DDriver *dma2dp); - dma2d_amode_t dma2dFgGetAlphaMode(DMA2DDriver *dma2dp); - void dma2dFgSetAlphaModeI(DMA2DDriver *dma2dp, dma2d_amode_t mode); - void dma2dFgSetAlphaMode(DMA2DDriver *dma2dp, dma2d_amode_t mode); - dma2d_pixfmt_t dma2dFgGetPixelFormatI(DMA2DDriver *dma2dp); - dma2d_pixfmt_t dma2dFgGetPixelFormat(DMA2DDriver *dma2dp); - void dma2dFgSetPixelFormatI(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt); - void dma2dFgSetPixelFormat(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt); - dma2d_color_t dma2dFgGetDefaultColorI(DMA2DDriver *dma2dp); - dma2d_color_t dma2dFgGetDefaultColor(DMA2DDriver *dma2dp); - void dma2dFgSetDefaultColorI(DMA2DDriver *dma2dp, dma2d_color_t c); - void dma2dFgSetDefaultColor(DMA2DDriver *dma2dp, dma2d_color_t c); - void dma2dFgGetPaletteI(DMA2DDriver *dma2dp, dma2d_palcfg_t *palettep); - void dma2dFgGetPalette(DMA2DDriver *dma2dp, dma2d_palcfg_t *palettep); - void dma2dFgSetPaletteS(DMA2DDriver *dma2dp, const dma2d_palcfg_t *palettep); - void dma2dFgSetPalette(DMA2DDriver *dma2dp, const dma2d_palcfg_t *palettep); - void dma2dFgGetLayerI(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp); - void dma2dFgGetLayer(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp); - void dma2dFgSetConfigS(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp); - void dma2dFgSetConfig(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp); - - /* Output layer methods.*/ - void *dma2dOutGetAddressI(DMA2DDriver *dma2dp); - void *dma2dOutGetAddress(DMA2DDriver *dma2dp); - void dma2dOutSetAddressI(DMA2DDriver *dma2dp, void *bufferp); - void dma2dOutSetAddress(DMA2DDriver *dma2dp, void *bufferp); - size_t dma2dOutGetWrapOffsetI(DMA2DDriver *dma2dp); - size_t dma2dOutGetWrapOffset(DMA2DDriver *dma2dp); - void dma2dOutSetWrapOffsetI(DMA2DDriver *dma2dp, size_t offset); - void dma2dOutSetWrapOffset(DMA2DDriver *dma2dp, size_t offset); - dma2d_pixfmt_t dma2dOutGetPixelFormatI(DMA2DDriver *dma2dp); - dma2d_pixfmt_t dma2dOutGetPixelFormat(DMA2DDriver *dma2dp); - void dma2dOutSetPixelFormatI(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt); - void dma2dOutSetPixelFormat(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt); - dma2d_color_t dma2dOutGetDefaultColorI(DMA2DDriver *dma2dp); - dma2d_color_t dma2dOutGetDefaultColor(DMA2DDriver *dma2dp); - void dma2dOutSetDefaultColorI(DMA2DDriver *dma2dp, dma2d_color_t c); - void dma2dOutSetDefaultColor(DMA2DDriver *dma2dp, dma2d_color_t c); - void dma2dOutGetLayerI(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp); - void dma2dOutGetLayer(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp); - void dma2dOutSetConfigI(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp); - void dma2dOutSetConfig(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp); - - /* Helper functions.*/ - const void *dma2dComputeAddressConst(const void *originp, size_t pitch, - dma2d_pixfmt_t fmt, - uint16_t x, uint16_t y); - bool dma2dIsAligned(const void *bufferp, dma2d_pixfmt_t fmt); - size_t dma2dBitsPerPixel(dma2d_pixfmt_t fmt); -#if (TRUE == DMA2D_USE_SOFTWARE_CONVERSIONS) || defined(__DOXYGEN__) - dma2d_color_t dma2dFromARGB8888(dma2d_color_t c, dma2d_pixfmt_t fmt); - dma2d_color_t dma2dToARGB8888(dma2d_color_t c, dma2d_pixfmt_t fmt); -#endif /* DMA2D_USE_SOFTWARE_CONVERSIONS */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32_DMA2D_USE_DMA2D */ - -#endif /* HAL_STM32_DMA2D_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c b/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c deleted file mode 100644 index b4c29386b3..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c +++ /dev/null @@ -1,190 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_fsmc.c - * @brief FSMC Driver subsystem low level driver source template. - * - * @addtogroup FSMC - * @{ - */ -#include "hal.h" -#include "hal_fsmc.h" - -#if (HAL_USE_FSMC == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief FSMC1 driver identifier. - */ -#if STM32_FSMC_USE_FSMC1 || defined(__DOXYGEN__) -FSMCDriver FSMCD1; -#endif - -/*===========================================================================*/ -/* Driver local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level FSMC driver initialization. - * - * @notapi - */ -void fsmc_init(void) { - - if (FSMCD1.state == FSMC_UNINIT) { - FSMCD1.state = FSMC_STOP; - -#if STM32_SRAM_USE_FSMC_SRAM1 - FSMCD1.sram1 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE); -#endif - -#if STM32_SRAM_USE_FSMC_SRAM2 - FSMCD1.sram2 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8); -#endif - -#if STM32_SRAM_USE_FSMC_SRAM3 - FSMCD1.sram3 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8 * 2); -#endif - -#if STM32_SRAM_USE_FSMC_SRAM4 - FSMCD1.sram4 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8 * 3); -#endif - -#if STM32_NAND_USE_FSMC_NAND1 - FSMCD1.nand1 = (FSMC_NAND_TypeDef *)FSMC_Bank2_R_BASE; -#endif - -#if STM32_NAND_USE_FSMC_NAND2 - FSMCD1.nand2 = (FSMC_NAND_TypeDef *)FSMC_Bank3_R_BASE; -#endif - -#if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F7)) - #if STM32_USE_FSMC_SDRAM - FSMCD1.sdram = (FSMC_SDRAM_TypeDef *)FSMC_Bank5_6_R_BASE; - #endif -#endif - } -} - -/** - * @brief Configures and activates the FSMC peripheral. - * - * @param[in] fsmcp pointer to the @p FSMCDriver object - * - * @notapi - */ -void fsmc_start(FSMCDriver *fsmcp) { - - osalDbgAssert((fsmcp->state == FSMC_STOP) || (fsmcp->state == FSMC_READY), - "invalid state"); - - if (fsmcp->state == FSMC_STOP) { - /* Enables the peripheral.*/ -#if STM32_FSMC_USE_FSMC1 - if (&FSMCD1 == fsmcp) { -#ifdef rccResetFSMC - rccResetFSMC(); -#endif - rccEnableFSMC(FALSE); -#if HAL_USE_NAND - nvicEnableVector(STM32_FSMC_NUMBER, STM32_FSMC_FSMC1_IRQ_PRIORITY); -#endif - } -#endif /* STM32_FSMC_USE_FSMC1 */ - - fsmcp->state = FSMC_READY; - } -} - -/** - * @brief Deactivates the FSMC peripheral. - * - * @param[in] emcp pointer to the @p FSMCDriver object - * - * @notapi - */ -void fsmc_stop(FSMCDriver *fsmcp) { - - if (fsmcp->state == FSMC_READY) { - /* Resets the peripheral.*/ -#ifdef rccResetFSMC - rccResetFSMC(); -#endif - - /* Disables the peripheral.*/ -#if STM32_FSMC_USE_FSMC1 - if (&FSMCD1 == fsmcp) { -#if HAL_USE_NAND - nvicDisableVector(STM32_FSMC_NUMBER); -#endif - rccDisableFSMC(FALSE); - } -#endif /* STM32_FSMC_USE_FSMC1 */ - - fsmcp->state = FSMC_STOP; - } -} - -/** - * @brief FSMC shared interrupt handler. - * - * @notapi - */ -CH_IRQ_HANDLER(STM32_FSMC_HANDLER) { - - CH_IRQ_PROLOGUE(); -#if STM32_NAND_USE_FSMC_NAND1 - if (FSMCD1.nand1->SR & FSMC_SR_ISR_MASK) { - NANDD1.isr_handler(&NANDD1); - } -#endif -#if STM32_NAND_USE_FSMC_NAND2 - if (FSMCD1.nand2->SR & FSMC_SR_ISR_MASK) { - NANDD2.isr_handler(&NANDD2); - } -#endif - CH_IRQ_EPILOGUE(); -} - -#endif /* HAL_USE_FSMC */ - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h b/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h deleted file mode 100644 index 51b9428e6b..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h +++ /dev/null @@ -1,348 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_fsmc.h - * @brief FSMC Driver subsystem low level driver header. - * - * @addtogroup FSMC - * @{ - */ - -#ifndef HAL_FSMC_H_ -#define HAL_FSMC_H_ - -#if (HAL_USE_FSMC == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/* - * (Re)define if needed base address constants supplied in ST's CMSIS - */ -#if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F7)) - #if !defined(FSMC_Bank1_R_BASE) - #define FSMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) - #endif - #if !defined(FSMC_Bank1E_R_BASE) - #define FSMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) - #endif - #if !defined(FSMC_Bank2_R_BASE) - #define FSMC_Bank2_R_BASE (FMC_R_BASE + 0x0060) - #endif - #if !defined(FSMC_Bank3_R_BASE) - #define FSMC_Bank3_R_BASE (FMC_R_BASE + 0x0080) - #endif - #if !defined(FSMC_Bank4_R_BASE) - #define FSMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0) - #endif - #if !defined(FSMC_Bank5_R_BASE) - #define FSMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140) - #endif -#else - #if !defined(FSMC_Bank1_R_BASE) - #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) - #endif - #if !defined(FSMC_Bank1E_R_BASE) - #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) - #endif - #if !defined(FSMC_Bank2_R_BASE) - #define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) - #endif - #if !defined(FSMC_Bank3_R_BASE) - #define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) - #endif - #if !defined(FSMC_Bank4_R_BASE) - #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) - #endif -#endif - -/* - * Base bank mappings - */ -#define FSMC_Bank1_MAP_BASE ((uint32_t) 0x60000000) -#define FSMC_Bank2_MAP_BASE ((uint32_t) 0x70000000) -#define FSMC_Bank3_MAP_BASE ((uint32_t) 0x80000000) -#define FSMC_Bank4_MAP_BASE ((uint32_t) 0x90000000) -#if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F7)) - #define FSMC_Bank5_MAP_BASE ((uint32_t) 0xC0000000) - #define FSMC_Bank6_MAP_BASE ((uint32_t) 0xD0000000) -#endif - -/* - * Subbunks of bank1 - */ -#define FSMC_SUBBUNK_OFFSET (1024 * 1024 * 64) -#define FSMC_Bank1_1_MAP (FSMC_Bank1_MAP_BASE) -#define FSMC_Bank1_2_MAP (FSMC_Bank1_1_MAP + FSMC_SUBBUNK_OFFSET) -#define FSMC_Bank1_3_MAP (FSMC_Bank1_2_MAP + FSMC_SUBBUNK_OFFSET) -#define FSMC_Bank1_4_MAP (FSMC_Bank1_3_MAP + FSMC_SUBBUNK_OFFSET) - -/* - * Bank 2 (NAND) - */ -#define FSMC_Bank2_MAP_COMMON (FSMC_Bank2_MAP_BASE + 0) -#define FSMC_Bank2_MAP_ATTR (FSMC_Bank2_MAP_BASE + 0x8000000) - -#define FSMC_Bank2_MAP_COMMON_DATA (FSMC_Bank2_MAP_COMMON + 0) -#define FSMC_Bank2_MAP_COMMON_CMD (FSMC_Bank2_MAP_COMMON + 0x10000) -#define FSMC_Bank2_MAP_COMMON_ADDR (FSMC_Bank2_MAP_COMMON + 0x20000) - -#define FSMC_Bank2_MAP_ATTR_DATA (FSMC_Bank2_MAP_ATTR + 0) -#define FSMC_Bank2_MAP_ATTR_CMD (FSMC_Bank2_MAP_ATTR + 0x10000) -#define FSMC_Bank2_MAP_ATTR_ADDR (FSMC_Bank2_MAP_ATTR + 0x20000) - -/* - * Bank 3 (NAND) - */ -#define FSMC_Bank3_MAP_COMMON (FSMC_Bank3_MAP_BASE + 0) -#define FSMC_Bank3_MAP_ATTR (FSMC_Bank3_MAP_BASE + 0x8000000) - -#define FSMC_Bank3_MAP_COMMON_DATA (FSMC_Bank3_MAP_COMMON + 0) -#define FSMC_Bank3_MAP_COMMON_CMD (FSMC_Bank3_MAP_COMMON + 0x10000) -#define FSMC_Bank3_MAP_COMMON_ADDR (FSMC_Bank3_MAP_COMMON + 0x20000) - -#define FSMC_Bank3_MAP_ATTR_DATA (FSMC_Bank3_MAP_ATTR + 0) -#define FSMC_Bank3_MAP_ATTR_CMD (FSMC_Bank3_MAP_ATTR + 0x10000) -#define FSMC_Bank3_MAP_ATTR_ADDR (FSMC_Bank3_MAP_ATTR + 0x20000) - -/* - * Bank 4 (PC card) - */ -#define FSMC_Bank4_MAP_COMMON (FSMC_Bank4_MAP_BASE + 0) -#define FSMC_Bank4_MAP_ATTR (FSMC_Bank4_MAP_BASE + 0x8000000) -#define FSMC_Bank4_MAP_IO (FSMC_Bank4_MAP_BASE + 0xC000000) - -/* - * More convenient typedefs than CMSIS has - */ -typedef struct { - __IO uint32_t PCR; /**< NAND Flash control */ - __IO uint32_t SR; /**< NAND Flash FIFO status and interrupt */ - __IO uint32_t PMEM; /**< NAND Flash Common memory space timing */ - __IO uint32_t PATT; /**< NAND Flash Attribute memory space timing */ - uint32_t RESERVED0; /**< Reserved, 0x70 */ - __IO uint32_t ECCR; /**< NAND Flash ECC result registers */ -} FSMC_NAND_TypeDef; - -typedef struct { - __IO uint32_t PCR; /**< PC Card control */ - __IO uint32_t SR; /**< PC Card FIFO status and interrupt */ - __IO uint32_t PMEM; /**< PC Card Common memory space timing */ - __IO uint32_t PATT; /**< PC Card Attribute memory space timing */ - __IO uint32_t PIO; /**< PC Card I/O space timing */ -} FSMC_PCCard_TypeDef; - -typedef struct { - __IO uint32_t BCR; /**< SRAM/NOR chip-select control registers */ - __IO uint32_t BTR; /**< SRAM/NOR chip-select timing registers */ - uint32_t RESERVED[63]; /**< Reserved */ - __IO uint32_t BWTR; /**< SRAM/NOR write timing registers */ -} FSMC_SRAM_NOR_TypeDef; - -#if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F7)) - -typedef struct { - __IO uint32_t SDCR1; /**< SDRAM control register (bank 1) */ - __IO uint32_t SDCR2; /**< SDRAM control register (bank 2) */ - __IO uint32_t SDTR1; /**< SDRAM timing register (bank 1) */ - __IO uint32_t SDTR2; /**< SDRAM timing register (bank 2) */ - __IO uint32_t SDCMR; /**< SDRAM comand mode register */ - __IO uint32_t SDRTR; /**< SDRAM refresh timer register */ - __IO uint32_t SDSR; /**< SDRAM status register */ -} FSMC_SDRAM_TypeDef; - -#endif - -/** - * @brief PCR register - */ -#define FSMC_PCR_PWAITEN ((uint32_t)1 << 1) -#define FSMC_PCR_PBKEN ((uint32_t)1 << 2) -#define FSMC_PCR_PTYP ((uint32_t)1 << 3) -#define FSMC_PCR_PWID_8 ((uint32_t)0 << 4) -#define FSMC_PCR_PWID_16 ((uint32_t)1 << 4) -#define FSMC_PCR_PWID_RESERVED1 ((uint32_t)2 << 4) -#define FSMC_PCR_PWID_RESERVED2 ((uint32_t)3 << 4) -#define FSMC_PCR_PWID_MASK ((uint32_t)3 << 4) -#define FSMC_PCR_ECCEN ((uint32_t)1 << 6) -#define FSMC_PCR_PTYP_PCCARD 0 -#define FSMC_PCR_PTYP_NAND FSMC_PCR_PTYP - -/** - * @brief SR register - */ -#define FSMC_SR_IRS ((uint8_t)0x01) -#define FSMC_SR_ILS ((uint8_t)0x02) -#define FSMC_SR_IFS ((uint8_t)0x04) -#define FSMC_SR_IREN ((uint8_t)0x08) -#define FSMC_SR_ILEN ((uint8_t)0x10) -#define FSMC_SR_IFEN ((uint8_t)0x20) -#define FSMC_SR_FEMPT ((uint8_t)0x40) -#define FSMC_SR_ISR_MASK (FSMC_SR_IRS | FSMC_SR_ILS | FSMC_SR_IFS) - -/** - * @brief BCR register - */ -#define FSMC_BCR_MBKEN ((uint32_t)1 << 0) -#define FSMC_BCR_MUXEN ((uint32_t)1 << 1) -#define FSMC_BCR_MTYP_SRAM ((uint32_t)0 << 2) -#define FSMC_BCR_MTYP_PSRAM ((uint32_t)1 << 2) -#define FSMC_BCR_MTYP_NOR_NAND ((uint32_t)2 << 2) -#define FSMC_BCR_MTYP_RESERVED ((uint32_t)3 << 2) -#define FSMC_BCR_MWID_8 ((uint32_t)0 << 4) -#define FSMC_BCR_MWID_16 ((uint32_t)1 << 4) -#if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F7)) -#define FSMC_BCR_MWID_32 ((uint32_t)2 << 4) -#else -#define FSMC_BCR_MWID_RESERVED1 ((uint32_t)2 << 4) -#endif -#define FSMC_BCR_MWID_RESERVED2 ((uint32_t)3 << 4) -#define FSMC_BCR_FACCEN ((uint32_t)1 << 6) -#define FSMC_BCR_BURSTEN ((uint32_t)1 << 8) -#define FSMC_BCR_WAITPOL ((uint32_t)1 << 9) -#define FSMC_BCR_WRAPMOD ((uint32_t)1 << 10) -#define FSMC_BCR_WAITCFG ((uint32_t)1 << 11) -#define FSMC_BCR_WREN ((uint32_t)1 << 12) -#define FSMC_BCR_WAITEN ((uint32_t)1 << 13) -#define FSMC_BCR_EXTMOD ((uint32_t)1 << 14) -#define FSMC_BCR_ASYNCWAIT ((uint32_t)1 << 15) -#define FSMC_BCR_CBURSTRW ((uint32_t)1 << 19) -#if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F7)) -#define FSMC_BCR_CCLKEN ((uint32_t)1 << 20) -#endif -#if (defined(STM32F7)) -#define FSMC_BCR_WFDIS ((uint32_t)1 << 21) -#endif - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief FSMC driver enable switch. - * @details If set to @p TRUE the support for FSMC is included. - */ -#if !defined(STM32_FSMC_USE_FSMC1) || defined(__DOXYGEN__) -#define STM32_FSMC_USE_FSMC1 FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ -#if !STM32_FSMC_USE_FSMC1 -#error "FSMC driver activated but no FSMC peripheral assigned" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a structure representing an FSMC driver. - */ -typedef struct FSMCDriver FSMCDriver; - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - FSMC_UNINIT = 0, /**< Not initialized. */ - FSMC_STOP = 1, /**< Stopped. */ - FSMC_READY = 2, /**< Ready. */ -} fsmcstate_t; - -/** - * @brief Structure representing an FSMC driver. - */ -struct FSMCDriver { - /** - * @brief Driver state. - */ - fsmcstate_t state; - /* End of the mandatory fields.*/ - -#if STM32_SRAM_USE_FSMC_SRAM1 - FSMC_SRAM_NOR_TypeDef *sram1; -#endif -#if STM32_SRAM_USE_FSMC_SRAM2 - FSMC_SRAM_NOR_TypeDef *sram2; -#endif -#if STM32_SRAM_USE_FSMC_SRAM3 - FSMC_SRAM_NOR_TypeDef *sram3; -#endif -#if STM32_SRAM_USE_FSMC_SRAM4 - FSMC_SRAM_NOR_TypeDef *sram4; -#endif -#if STM32_NAND_USE_FSMC_NAND1 - FSMC_NAND_TypeDef *nand1; -#endif -#if STM32_NAND_USE_FSMC_NAND2 - FSMC_NAND_TypeDef *nand2; -#endif -#if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F7)) - #if STM32_USE_FSMC_SDRAM - FSMC_SDRAM_TypeDef *sdram; - #endif -#endif -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_FSMC_USE_FSMC1 && !defined(__DOXYGEN__) -extern FSMCDriver FSMCD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void fsmc_init(void); - void fsmc_start(FSMCDriver *fsmcp); - void fsmc_stop(FSMCDriver *fsmcp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_FSMC */ - -#endif /* HAL_FSMC_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c b/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c deleted file mode 100644 index ac83477d03..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c +++ /dev/null @@ -1,211 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - SDRAM routines added by Nick Klimov aka progfin. - */ - -/** - * @file hal_fsmc_sdram.c - * @brief SDRAM Driver subsystem low level driver source. - * - * @addtogroup SDRAM - * @{ - */ - -#include "hal.h" - -#if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx)) - -#if (STM32_USE_FSMC_SDRAM == TRUE) || defined(__DOXYGEN__) - -#include "hal_fsmc_sdram.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/** - * FMC_Command_Mode - */ -#define FMCCM_NORMAL ((uint32_t)0x00000000) -#define FMCCM_CLK_ENABLED ((uint32_t)0x00000001) -#define FMCCM_PALL ((uint32_t)0x00000002) -#define FMCCM_AUTO_REFRESH ((uint32_t)0x00000003) -#define FMCCM_LOAD_MODE ((uint32_t)0x00000004) -#define FMCCM_SELFREFRESH ((uint32_t)0x00000005) -#define FMCCM_POWER_DOWN ((uint32_t)0x00000006) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ -/** - * @brief SDRAM driver identifier. - */ -SDRAMDriver SDRAMD; - -/*===========================================================================*/ -/* Driver local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Wait until the SDRAM controller is ready. - * - * @notapi - */ -static void _sdram_wait_ready(void) { - /* Wait until the SDRAM controller is ready */ - while (SDRAMD.sdram->SDSR & FMC_SDSR_BUSY); -} - -/** - * @brief Executes the SDRAM memory initialization sequence. - * - * @param[in] cfgp pointer to the @p SDRAMConfig object - * - * @notapi - */ -static void _sdram_init_sequence(const SDRAMConfig *cfgp) { - - uint32_t command_target = 0; - -#if STM32_SDRAM_USE_FSMC_SDRAM1 - command_target |= FMC_SDCMR_CTB1; -#endif -#if STM32_SDRAM_USE_FSMC_SDRAM2 - command_target |= FMC_SDCMR_CTB2; -#endif - - /* Step 3: Configure a clock configuration enable command.*/ - _sdram_wait_ready(); - SDRAMD.sdram->SDCMR = FMCCM_CLK_ENABLED | command_target; - - /* Step 4: Insert delay (tipically 100uS).*/ - osalThreadSleepMilliseconds(1); - - /* Step 5: Configure a PALL (precharge all) command.*/ - _sdram_wait_ready(); - SDRAMD.sdram->SDCMR = FMCCM_PALL | command_target; - - /* Step 6.1: Configure a Auto-Refresh command: send the first command.*/ - _sdram_wait_ready(); - SDRAMD.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target | - (cfgp->sdcmr & FMC_SDCMR_NRFS); - - /* Step 6.2: Send the second command.*/ - _sdram_wait_ready(); - SDRAMD.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target | - (cfgp->sdcmr & FMC_SDCMR_NRFS); - - /* Step 7: Program the external memory mode register.*/ - _sdram_wait_ready(); - SDRAMD.sdram->SDCMR = FMCCM_LOAD_MODE | command_target | - (cfgp->sdcmr & FMC_SDCMR_MRD); - - /* Step 8: Set clock.*/ - _sdram_wait_ready(); - SDRAMD.sdram->SDRTR = cfgp->sdrtr & FMC_SDRTR_COUNT; - - _sdram_wait_ready(); -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level SDRAM driver initialization. - */ -void fsmcSdramInit(void) { - - fsmc_init(); - - SDRAMD.sdram = FSMCD1.sdram; - SDRAMD.state = SDRAM_STOP; -} - -/** - * @brief Configures and activates the SDRAM peripheral. - * - * @param[in] sdramp pointer to the @p SDRAMDriver object - * @param[in] cfgp pointer to the @p SDRAMConfig object - */ -void fsmcSdramStart(SDRAMDriver *sdramp, const SDRAMConfig *cfgp) { - - if (FSMCD1.state == FSMC_STOP) - fsmc_start(&FSMCD1); - - osalDbgAssert((sdramp->state == SDRAM_STOP) || (sdramp->state == SDRAM_READY), - "SDRAM. Invalid state."); - - if (sdramp->state == SDRAM_STOP) { - - /* Even if you need only bank2 you must properly set up SDCR and SDTR - regitsters for bank1 too. Both banks will be tuned equally assuming - connected memory ICs are equal.*/ - sdramp->sdram->SDCR1 = cfgp->sdcr; - sdramp->sdram->SDTR1 = cfgp->sdtr; - sdramp->sdram->SDCR2 = cfgp->sdcr; - sdramp->sdram->SDTR2 = cfgp->sdtr; - - _sdram_init_sequence(cfgp); - - sdramp->state = SDRAM_READY; - } -} - -/** - * @brief Deactivates the SDRAM peripheral. - * - * @param[in] sdramp pointer to the @p SDRAMDriver object - * - * @notapi - */ -void fsmcSdramStop(SDRAMDriver *sdramp) { - - uint32_t command_target = 0; - -#if STM32_SDRAM_USE_FSMC_SDRAM1 - command_target |= FMC_SDCMR_CTB1; -#endif -#if STM32_SDRAM_USE_FSMC_SDRAM2 - command_target |= FMC_SDCMR_CTB2; -#endif - - if (sdramp->state == SDRAM_READY) { - SDRAMD.sdram->SDCMR = FMCCM_POWER_DOWN | command_target; - sdramp->state = SDRAM_STOP; - } -} - -#endif /* STM32_USE_FSMC_SDRAM */ - -#endif /* STM32F427xx / STM32F429xx / STM32F437xx / STM32F439xx */ - -/** @} */ - diff --git a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h b/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h deleted file mode 100644 index b419168b01..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h +++ /dev/null @@ -1,171 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - SDRAM routines added by Nick Klimov aka progfin. - */ - -/** - * @file hal_fsmc_sdram.h - * @brief SDRAM Driver subsystem low level driver header. - * - * @addtogroup SDRAM - * @{ - */ - -#ifndef HAL_FMC_SDRAM_H_ -#define HAL_FMC_SDRAM_H_ - -#if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx)) - -#include "hal_fsmc.h" - -#if (STM32_USE_FSMC_SDRAM == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ -/** - * @name Configuration options - * @{ - */ - -/** - * @brief SDRAM driver enable switch. - * @details If set to @p TRUE the support for SDRAM1 is included. - */ -#if !defined(STM32_SDRAM_USE_FSMC_SDRAM1) || defined(__DOXYGEN__) -#define STM32_SDRAM_USE_FSMC_SDRAM1 FALSE -#else -#define STM32_SDRAM1_MAP_BASE FSMC_Bank5_MAP_BASE -#endif - -/** - * @brief SDRAM driver enable switch. - * @details If set to @p TRUE the support for SDRAM2 is included. - */ -#if !defined(STM32_SDRAM_USE_FSMC_SDRAM2) || defined(__DOXYGEN__) -#define STM32_SDRAM_USE_FSMC_SDRAM2 FALSE -#else -#define STM32_SDRAM2_MAP_BASE FSMC_Bank6_MAP_BASE -#endif - -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !STM32_SDRAM_USE_FSMC_SDRAM1 && !STM32_SDRAM_USE_FSMC_SDRAM2 -#error "SDRAM driver activated but no SDRAM peripheral assigned" -#endif - -#if (STM32_SDRAM_USE_FSMC_SDRAM1 || STM32_SDRAM_USE_FSMC_SDRAM2) && !STM32_HAS_FSMC -#error "FMC not present in the selected device" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ -/** - * @brief Driver state machine possible states. - */ -typedef enum { - SDRAM_UNINIT = 0, /**< Not initialized. */ - SDRAM_STOP = 1, /**< Stopped. */ - SDRAM_READY = 2, /**< Ready. */ -} sdramstate_t; - -/** - * @brief Type of a structure representing an SDRAM driver. - */ -typedef struct SDRAMDriver SDRAMDriver; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief SDRAM control register. - * @note Its value will be used for both banks. - */ - uint32_t sdcr; - - /** - * @brief SDRAM timing register. - * @note Its value will be used for both banks. - */ - uint32_t sdtr; - - /** - * @brief SDRAM command mode register. - * @note Only its MRD and NRFS bits will be used. - */ - uint32_t sdcmr; - - /** - * @brief SDRAM refresh timer register. - * @note Only its COUNT bits will be used. - */ - uint32_t sdrtr; -} SDRAMConfig; - -/** - * @brief Structure representing an SDRAM driver. - */ -struct SDRAMDriver { - /** - * @brief Driver state. - */ - sdramstate_t state; - /** - * @brief Pointer to the FMC SDRAM registers block. - */ - FSMC_SDRAM_TypeDef *sdram; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -extern SDRAMDriver SDRAMD; - -#ifdef __cplusplus -extern "C" { -#endif - void fsmcSdramInit(void); - void fsmcSdramStart(SDRAMDriver *sdramp, const SDRAMConfig *cfgp); - void fsmcSdramStop(SDRAMDriver *sdramp); -#ifdef __cplusplus -} -#endif - -#endif /* STM32_USE_FSMC_SDRAM */ - -#endif /* STM32F427xx / STM32F429xx / STM32F437xx / STM32F439xx */ - -#endif /* HAL_FMC_SDRAM_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c b/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c deleted file mode 100644 index fbd6f56ae0..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c +++ /dev/null @@ -1,162 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_fsmc_sram.c - * @brief SRAM Driver subsystem low level driver source. - * - * @addtogroup SRAM - * @{ - */ -#include "hal.h" -#include "hal_fsmc_sram.h" - -#if (STM32_USE_FSMC_SRAM == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ -/** - * @brief SRAM1 driver identifier. - */ -#if STM32_SRAM_USE_FSMC_SRAM1 || defined(__DOXYGEN__) -SRAMDriver SRAMD1; -#endif - -/** - * @brief SRAM2 driver identifier. - */ -#if STM32_SRAM_USE_FSMC_SRAM2 || defined(__DOXYGEN__) -SRAMDriver SRAMD2; -#endif - -/** - * @brief SRAM3 driver identifier. - */ -#if STM32_SRAM_USE_FSMC_SRAM3 || defined(__DOXYGEN__) -SRAMDriver SRAMD3; -#endif - -/** - * @brief SRAM4 driver identifier. - */ -#if STM32_SRAM_USE_FSMC_SRAM4 || defined(__DOXYGEN__) -SRAMDriver SRAMD4; -#endif - -/*===========================================================================*/ -/* Driver local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level SRAM driver initialization. - * - * @notapi - */ -void fsmcSramInit(void) { - - fsmc_init(); - -#if STM32_SRAM_USE_FSMC_SRAM1 - SRAMD1.sram = FSMCD1.sram1; - SRAMD1.state = SRAM_STOP; -#endif /* STM32_SRAM_USE_FSMC_SRAM1 */ - -#if STM32_SRAM_USE_FSMC_SRAM2 - SRAMD2.sram = FSMCD1.sram2; - SRAMD2.state = SRAM_STOP; -#endif /* STM32_SRAM_USE_FSMC_SRAM2 */ - -#if STM32_SRAM_USE_FSMC_SRAM3 - SRAMD3.sram = FSMCD1.sram3; - SRAMD3.state = SRAM_STOP; -#endif /* STM32_SRAM_USE_FSMC_SRAM3 */ - -#if STM32_SRAM_USE_FSMC_SRAM4 - SRAMD4.sram = FSMCD1.sram4; - SRAMD4.state = SRAM_STOP; -#endif /* STM32_SRAM_USE_FSMC_SRAM4 */ -} - -/** - * @brief Configures and activates the SRAM peripheral. - * - * @param[in] sramp pointer to the @p SRAMDriver object - * @param[in] cfgp pointer to the @p SRAMConfig object - * - * @notapi - */ -void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp) { - - if (FSMCD1.state == FSMC_STOP) - fsmc_start(&FSMCD1); - - osalDbgAssert((sramp->state == SRAM_STOP) || (sramp->state == SRAM_READY), - "invalid state"); - - if (sramp->state == SRAM_STOP) { - sramp->sram->BTR = cfgp->btr; - sramp->sram->BWTR = cfgp->bwtr; - sramp->sram->BCR = cfgp->bcr | FSMC_BCR_MBKEN; - sramp->state = SRAM_READY; - } -} - -/** - * @brief Deactivates the SRAM peripheral. - * - * @param[in] sramp pointer to the @p SRAMDriver object - * - * @notapi - */ -void fsmcSramStop(SRAMDriver *sramp) { - - if (sramp->state == SRAM_READY) { - uint32_t mask = FSMC_BCR_MBKEN; -#if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F7)) - mask |= FSMC_BCR_CCLKEN; -#endif - sramp->sram->BCR &= ~mask; - sramp->state = SRAM_STOP; - } -} - -#endif /* STM32_USE_FSMC_SRAM */ - -/** @} */ - diff --git a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.h b/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.h deleted file mode 100644 index 5e749a8fd9..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.h +++ /dev/null @@ -1,172 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_fsmc_sram.h - * @brief SRAM Driver subsystem low level driver header. - * - * @addtogroup SRAM - * @{ - */ - -#ifndef HAL_FSMC_SRAM_H_ -#define HAL_FSMC_SRAM_H_ - -#include "hal_fsmc.h" - -#if (STM32_USE_FSMC_SRAM == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ -/** - * @name Configuration options - * @{ - */ - -/** - * @brief SRAM driver enable switch. - * @details If set to @p TRUE the support for SRAM1 is included. - */ -#if !defined(STM32_SRAM_USE_FSMC_SRAM1) || defined(__DOXYGEN__) -#define STM32_SRAM_USE_FSMC_SRAM1 FALSE -#endif - -/** - * @brief SRAM driver enable switch. - * @details If set to @p TRUE the support for SRAM2 is included. - */ -#if !defined(STM32_SRAM_USE_FSMC_SRAM2) || defined(__DOXYGEN__) -#define STM32_SRAM_USE_FSMC_SRAM2 FALSE -#endif - -/** - * @brief SRAM driver enable switch. - * @details If set to @p TRUE the support for SRAM3 is included. - */ -#if !defined(STM32_SRAM_USE_FSMC_SRAM3) || defined(__DOXYGEN__) -#define STM32_SRAM_USE_FSMC_SRAM3 FALSE -#endif - -/** - * @brief SRAM driver enable switch. - * @details If set to @p TRUE the support for SRAM4 is included. - */ -#if !defined(STM32_SRAM_USE_FSMC_SRAM4) || defined(__DOXYGEN__) -#define STM32_SRAM_USE_FSMC_SRAM4 FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !STM32_SRAM_USE_FSMC_SRAM1 && !STM32_SRAM_USE_FSMC_SRAM2 && \ - !STM32_SRAM_USE_FSMC_SRAM3 && !STM32_SRAM_USE_FSMC_SRAM4 -#error "SRAM driver activated but no SRAM peripheral assigned" -#endif - -#if (STM32_SRAM_USE_FSMC_SRAM1 || STM32_SRAM_USE_FSMC_SRAM2 || \ - STM32_SRAM_USE_FSMC_SRAM3 || STM32_SRAM_USE_FSMC_SRAM4) && !STM32_HAS_FSMC -#error "FSMC not present in the selected device" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ -/** - * @brief Driver state machine possible states. - */ -typedef enum { - SRAM_UNINIT = 0, /**< Not initialized. */ - SRAM_STOP = 1, /**< Stopped. */ - SRAM_READY = 2, /**< Ready. */ -} sramstate_t; - -/** - * @brief Type of a structure representing an NAND driver. - */ -typedef struct SRAMDriver SRAMDriver; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - * @note Some bits in BCR register will be forced by driver. - */ -typedef struct { - uint32_t bcr; - uint32_t btr; - uint32_t bwtr; -} SRAMConfig; - -/** - * @brief Structure representing an NAND driver. - */ -struct SRAMDriver { - /** - * @brief Driver state. - */ - sramstate_t state; - /** - * @brief Pointer to the FSMC SRAM registers block. - */ - FSMC_SRAM_NOR_TypeDef *sram; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_SRAM_USE_FSMC_SRAM1 && !defined(__DOXYGEN__) -extern SRAMDriver SRAMD1; -#endif - -#if STM32_SRAM_USE_FSMC_SRAM2 && !defined(__DOXYGEN__) -extern SRAMDriver SRAMD2; -#endif - -#if STM32_SRAM_USE_FSMC_SRAM3 && !defined(__DOXYGEN__) -extern SRAMDriver SRAMD3; -#endif - -#if STM32_SRAM_USE_FSMC_SRAM4 && !defined(__DOXYGEN__) -extern SRAMDriver SRAMD4; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void fsmcSramInit(void); - void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp); - void fsmcSramStop(SRAMDriver *sramp); -#ifdef __cplusplus -} -#endif - -#endif /* STM32_USE_FSMC_SRAM */ - -#endif /* HAL_FSMC_SRAM_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c b/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c deleted file mode 100644 index 5729f92e3e..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c +++ /dev/null @@ -1,590 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_nand_lld.c - * @brief NAND Driver subsystem low level driver source. - * - * @addtogroup NAND - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_NAND == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ -#define NAND_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_NAND_DMA_STREAM, \ - STM32_FSMC_DMA_CHN) - -/** - * @brief Bus width of NAND IC. - * @details Must be 8 or 16 - */ -#if ! defined(STM32_NAND_BUS_WIDTH) || defined(__DOXYGEN__) -#define STM32_NAND_BUS_WIDTH 8 -#endif - -/** - * @brief DMA transaction width on AHB bus in bytes - */ -#define AHB_TRANSACTION_WIDTH 2 - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief NAND1 driver identifier. - */ -#if STM32_NAND_USE_FSMC_NAND1 || defined(__DOXYGEN__) -NANDDriver NANDD1; -#endif - -/** - * @brief NAND2 driver identifier. - */ -#if STM32_NAND_USE_FSMC_NAND2 || defined(__DOXYGEN__) -NANDDriver NANDD2; -#endif - -/*===========================================================================*/ -/* Driver local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Helper function. - * - * @notapi - */ -static void align_check(const void *ptr, uint32_t len) { - osalDbgCheck((((uint32_t)ptr % AHB_TRANSACTION_WIDTH) == 0) && - ((len % AHB_TRANSACTION_WIDTH) == 0) && - (len >= AHB_TRANSACTION_WIDTH)); - (void)ptr; - (void)len; -} - -/** - * @brief Work around errata in STM32's FSMC core. - * @details Constant output clock (if enabled) disappears when CLKDIV value - * sets to 1 (FMC_CLK period = 2 × HCLK periods) AND 8-bit async - * transaction generated on AHB. This workaround eliminates 8-bit - * transactions on bus when you use 8-bit memory. It suitable only - * for 8-bit memory (i.e. PWID bits in PCR register must be set - * to 8-bit mode). - * - * @notapi - */ -static void set_16bit_bus(NANDDriver *nandp) { -#if STM32_NAND_BUS_WIDTH - nandp->nand->PCR |= FSMC_PCR_PWID_16; -#else - (void)nandp; -#endif -} - -static void set_8bit_bus(NANDDriver *nandp) { -#if STM32_NAND_BUS_WIDTH - nandp->nand->PCR &= ~FSMC_PCR_PWID_16; -#else - (void)nandp; -#endif -} - -/** - * @brief Wakes up the waiting thread. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] msg wakeup message - * - * @notapi - */ -static void wakeup_isr(NANDDriver *nandp) { - - osalDbgCheck(nandp->thread != NULL); - osalThreadResumeI(&nandp->thread, MSG_OK); -} - -/** - * @brief Put calling thread in suspend and switch driver state - * - * @param[in] nandp pointer to the @p NANDDriver object - */ -static void nand_lld_suspend_thread(NANDDriver *nandp) { - - osalThreadSuspendS(&nandp->thread); -} - -/** - * @brief Caclulate ECCPS register value - * - * @param[in] nandp pointer to the @p NANDDriver object - */ -static uint32_t calc_eccps(NANDDriver *nandp) { - - uint32_t i = 0; - uint32_t eccps = nandp->config->page_data_size; - - eccps = eccps >> 9; - while (eccps > 0){ - i++; - eccps >>= 1; - } - - return i << 17; -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief Enable interrupts from NAND - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @notapi - */ -static void nand_ready_isr_enable(NANDDriver *nandp) { - - nandp->nand->SR &= ~(FSMC_SR_IRS | FSMC_SR_ILS | FSMC_SR_IFS | - FSMC_SR_ILEN | FSMC_SR_IFEN); - nandp->nand->SR |= FSMC_SR_IREN; -} - -/** - * @brief Disable interrupts from NAND - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @notapi - */ -static void nand_ready_isr_disable(NANDDriver *nandp) { - - nandp->nand->SR &= ~FSMC_SR_IREN; -} - -/** - * @brief Ready interrupt handler - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @notapi - */ -static void nand_isr_handler(NANDDriver *nandp) { - - osalSysLockFromISR(); - - osalDbgCheck(nandp->nand->SR & FSMC_SR_IRS); /* spurious interrupt happened */ - nandp->nand->SR &= ~FSMC_SR_IRS; - - switch (nandp->state){ - case NAND_READ: - nandp->state = NAND_DMA_RX; - dmaStartMemCopy(nandp->dma, nandp->dmamode, nandp->map_data, nandp->rxdata, - nandp->datalen/AHB_TRANSACTION_WIDTH); - /* thread will be waked up from DMA ISR */ - break; - - case NAND_ERASE: /* NAND reports about erase finish */ - case NAND_PROGRAM: /* NAND reports about page programming finish */ - case NAND_RESET: /* NAND reports about finished reset recover */ - nandp->state = NAND_READY; - wakeup_isr(nandp); - break; - - default: - osalSysHalt("Unhandled case"); - break; - } - osalSysUnlockFromISR(); -} - -/** - * @brief DMA RX end IRQ handler. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] flags pre-shifted content of the ISR register - * - * @notapi - */ -static void nand_lld_serve_transfer_end_irq(NANDDriver *nandp, uint32_t flags) { - /* DMA errors handling.*/ -#if defined(STM32_NAND_DMA_ERROR_HOOK) - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - STM32_NAND_DMA_ERROR_HOOK(nandp); - } -#else - (void)flags; -#endif - - osalSysLockFromISR(); - - dmaStreamDisable(nandp->dma); - - switch (nandp->state){ - case NAND_DMA_TX: - nandp->state = NAND_PROGRAM; - nandp->map_cmd[0] = NAND_CMD_PAGEPROG; - /* thread will be woken up from ready_isr() */ - break; - - case NAND_DMA_RX: - nandp->state = NAND_READY; - nandp->rxdata = NULL; - nandp->datalen = 0; - wakeup_isr(nandp); - break; - - default: - osalSysHalt("Unhandled case"); - break; - } - - osalSysUnlockFromISR(); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level NAND driver initialization. - * - * @notapi - */ -void nand_lld_init(void) { - - fsmc_init(); - -#if STM32_NAND_USE_FSMC_NAND1 - /* Driver initialization.*/ - nandObjectInit(&NANDD1); - NANDD1.rxdata = NULL; - NANDD1.datalen = 0; - NANDD1.thread = NULL; - NANDD1.dma = STM32_DMA_STREAM(STM32_NAND_DMA_STREAM); - NANDD1.nand = FSMCD1.nand1; - NANDD1.map_data = (void *)FSMC_Bank2_MAP_COMMON_DATA; - NANDD1.map_cmd = (uint16_t *)FSMC_Bank2_MAP_COMMON_CMD; - NANDD1.map_addr = (uint16_t *)FSMC_Bank2_MAP_COMMON_ADDR; - NANDD1.bb_map = NULL; -#endif /* STM32_NAND_USE_FSMC_NAND1 */ - -#if STM32_NAND_USE_FSMC_NAND2 - /* Driver initialization.*/ - nandObjectInit(&NANDD2); - NANDD2.rxdata = NULL; - NANDD2.datalen = 0; - NANDD2.thread = NULL; - NANDD2.dma = STM32_DMA_STREAM(STM32_NAND_DMA_STREAM); - NANDD2.nand = FSMCD1.nand2; - NANDD2.map_data = (void *)FSMC_Bank3_MAP_COMMON_DATA; - NANDD2.map_cmd = (uint16_t *)FSMC_Bank3_MAP_COMMON_CMD; - NANDD2.map_addr = (uint16_t *)FSMC_Bank3_MAP_COMMON_ADDR; - NANDD2.bb_map = NULL; -#endif /* STM32_NAND_USE_FSMC_NAND2 */ -} - -/** - * @brief Configures and activates the NAND peripheral. - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @notapi - */ -void nand_lld_start(NANDDriver *nandp) { - - bool b; - uint32_t dmasize; - uint32_t pcr_bus_width; - - if (FSMCD1.state == FSMC_STOP) - fsmc_start(&FSMCD1); - - if (nandp->state == NAND_STOP) { - b = dmaStreamAllocate(nandp->dma, - STM32_EMC_FSMC1_IRQ_PRIORITY, - (stm32_dmaisr_t)nand_lld_serve_transfer_end_irq, - (void *)nandp); - osalDbgAssert(!b, "stream already allocated"); - -#if AHB_TRANSACTION_WIDTH == 4 - dmasize = STM32_DMA_CR_PSIZE_WORD | STM32_DMA_CR_MSIZE_WORD; -#elif AHB_TRANSACTION_WIDTH == 2 - dmasize = STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; -#elif AHB_TRANSACTION_WIDTH == 1 - dmasize = STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE; -#else -#error "Incorrect AHB_TRANSACTION_WIDTH" -#endif - - nandp->dmamode = STM32_DMA_CR_CHSEL(NAND_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_NAND_NAND1_DMA_PRIORITY) | - dmasize | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE | - STM32_DMA_CR_TCIE; - -#if STM32_NAND_BUS_WIDTH == 8 - pcr_bus_width = FSMC_PCR_PWID_8; -#elif STM32_NAND_BUS_WIDTH == 16 - pcr_bus_width = FSMC_PCR_PWID_16; -#else -#error "Bus width must be 8 or 16 bits" -#endif - nandp->nand->PCR = pcr_bus_width | calc_eccps(nandp) | - FSMC_PCR_PTYP_NAND | FSMC_PCR_PBKEN; - nandp->nand->PMEM = nandp->config->pmem; - nandp->nand->PATT = nandp->config->pmem; - nandp->isr_handler = nand_isr_handler; - nand_ready_isr_enable(nandp); - } -} - -/** - * @brief Deactivates the NAND peripheral. - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @notapi - */ -void nand_lld_stop(NANDDriver *nandp) { - - if (nandp->state == NAND_READY) { - dmaStreamRelease(nandp->dma); - nandp->nand->PCR &= ~FSMC_PCR_PBKEN; - nand_ready_isr_disable(nandp); - nandp->isr_handler = NULL; - } -} - -/** - * @brief Read data from NAND. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[out] data pointer to data buffer - * @param[in] datalen size of data buffer in bytes - * @param[in] addr pointer to address buffer - * @param[in] addrlen length of address - * @param[out] ecc pointer to store computed ECC. Ignored when NULL. - * - * @notapi - */ -void nand_lld_read_data(NANDDriver *nandp, uint16_t *data, size_t datalen, - uint8_t *addr, size_t addrlen, uint32_t *ecc){ - - align_check(data, datalen); - - nandp->state = NAND_READ; - nandp->rxdata = data; - nandp->datalen = datalen; - - set_16bit_bus(nandp); - nand_lld_write_cmd(nandp, NAND_CMD_READ0); - nand_lld_write_addr(nandp, addr, addrlen); - osalSysLock(); - nand_lld_write_cmd(nandp, NAND_CMD_READ0_CONFIRM); - set_8bit_bus(nandp); - - /* Here NAND asserts busy signal and starts transferring from memory - array to page buffer. After the end of transmission ready_isr functions - starts DMA transfer from page buffer to MCU's RAM.*/ - osalDbgAssert((nandp->nand->PCR & FSMC_PCR_ECCEN) == 0, - "State machine broken. ECCEN must be previously disabled."); - - if (NULL != ecc){ - nandp->nand->PCR |= FSMC_PCR_ECCEN; - } - - nand_lld_suspend_thread(nandp); - osalSysUnlock(); - - /* thread was woken up from DMA ISR */ - if (NULL != ecc){ - while (! (nandp->nand->SR & FSMC_SR_FEMPT)) - ; - *ecc = nandp->nand->ECCR; - nandp->nand->PCR &= ~FSMC_PCR_ECCEN; - } -} - -/** - * @brief Write data to NAND. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] data buffer with data to be written - * @param[in] datalen size of data buffer in bytes - * @param[in] addr pointer to address buffer - * @param[in] addrlen length of address - * @param[out] ecc pointer to store computed ECC. Ignored when NULL. - * - * @return The operation status reported by NAND IC (0x70 command). - * - * @notapi - */ -uint8_t nand_lld_write_data(NANDDriver *nandp, const uint16_t *data, - size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc) { - - align_check(data, datalen); - - nandp->state = NAND_WRITE; - - set_16bit_bus(nandp); - nand_lld_write_cmd(nandp, NAND_CMD_WRITE); - osalSysLock(); - nand_lld_write_addr(nandp, addr, addrlen); - set_8bit_bus(nandp); - - /* Now start DMA transfer to NAND buffer and put thread in sleep state. - Tread will be woken up from ready ISR. */ - nandp->state = NAND_DMA_TX; - osalDbgAssert((nandp->nand->PCR & FSMC_PCR_ECCEN) == 0, - "State machine broken. ECCEN must be previously disabled."); - - if (NULL != ecc){ - nandp->nand->PCR |= FSMC_PCR_ECCEN; - } - - dmaStartMemCopy(nandp->dma, nandp->dmamode, data, nandp->map_data, - datalen/AHB_TRANSACTION_WIDTH); - - nand_lld_suspend_thread(nandp); - osalSysUnlock(); - - if (NULL != ecc){ - while (! (nandp->nand->SR & FSMC_SR_FEMPT)) - ; - *ecc = nandp->nand->ECCR; - nandp->nand->PCR &= ~FSMC_PCR_ECCEN; - } - - return nand_lld_read_status(nandp); -} - -/** - * @brief Soft reset NAND device. - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @notapi - */ -void nand_lld_reset(NANDDriver *nandp) { - - nandp->state = NAND_RESET; - - set_16bit_bus(nandp); - nand_lld_write_cmd(nandp, NAND_CMD_RESET); - set_8bit_bus(nandp); - - osalSysLock(); - nand_lld_suspend_thread(nandp); - osalSysUnlock(); -} - -/** - * @brief Erase block. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] addr pointer to address buffer - * @param[in] addrlen length of address - * - * @return The operation status reported by NAND IC (0x70 command). - * - * @notapi - */ -uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr, size_t addrlen) { - - nandp->state = NAND_ERASE; - - set_16bit_bus(nandp); - nand_lld_write_cmd(nandp, NAND_CMD_ERASE); - nand_lld_write_addr(nandp, addr, addrlen); - osalSysLock(); - nand_lld_write_cmd(nandp, NAND_CMD_ERASE_CONFIRM); - set_8bit_bus(nandp); - - nand_lld_suspend_thread(nandp); - osalSysUnlock(); - - return nand_lld_read_status(nandp); -} - -/** - * @brief Send addres to NAND. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] len length of address array - * @param[in] addr pointer to address array - * - * @notapi - */ -void nand_lld_write_addr(NANDDriver *nandp, const uint8_t *addr, size_t len) { - size_t i = 0; - - for (i=0; imap_addr[i] = addr[i]; -} - -/** - * @brief Send command to NAND. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] cmd command value - * - * @notapi - */ -void nand_lld_write_cmd(NANDDriver *nandp, uint8_t cmd) { - nandp->map_cmd[0] = cmd; -} - -/** - * @brief Read status byte from NAND. - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @return Status byte. - * - * @notapi - */ -uint8_t nand_lld_read_status(NANDDriver *nandp) { - - uint16_t status; - - set_16bit_bus(nandp); - nand_lld_write_cmd(nandp, NAND_CMD_STATUS); - set_8bit_bus(nandp); - status = nandp->map_data[0]; - - return status & 0xFF; -} - -#endif /* HAL_USE_NAND */ - -/** @} */ - diff --git a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h b/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h deleted file mode 100644 index 5266138635..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h +++ /dev/null @@ -1,294 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_nand_lld.h - * @brief NAND Driver subsystem low level driver header. - * - * @addtogroup NAND - * @{ - */ - -#ifndef HAL_NAND_LLD_H_ -#define HAL_NAND_LLD_H_ - -#include "hal_fsmc.h" -#include "bitmap.h" - -#if (HAL_USE_NAND == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ -#define NAND_MIN_PAGE_SIZE 256 -#define NAND_MAX_PAGE_SIZE 8192 - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief FSMC1 interrupt priority level setting. - */ -#if !defined(STM32_EMC_FSMC1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EMC_FSMC1_IRQ_PRIORITY 10 -#endif - -/** - * @brief NAND driver enable switch. - * @details If set to @p TRUE the support for NAND1 is included. - */ -#if !defined(STM32_NAND_USE_NAND1) || defined(__DOXYGEN__) -#define STM32_NAND_USE_NAND1 FALSE -#endif - -/** - * @brief NAND driver enable switch. - * @details If set to @p TRUE the support for NAND2 is included. - */ -#if !defined(STM32_NAND_USE_NAND2) || defined(__DOXYGEN__) -#define STM32_NAND_USE_NAND2 FALSE -#endif - -/** - * @brief NAND DMA error hook. - * @note The default action for DMA errors is a system halt because DMA - * error can only happen because programming errors. - */ -#if !defined(STM32_NAND_DMA_ERROR_HOOK) || defined(__DOXYGEN__) -#define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure") -#endif - -/** - * @brief NAND interrupt enable switch. - * @details If set to @p TRUE the support for internal FSMC interrupt included. - */ -#if !defined(STM32_NAND_USE_INT) || defined(__DOXYGEN__) -#define STM32_NAND_USE_INT FALSE -#endif - -/** -* @brief NAND1 DMA priority (0..3|lowest..highest). -*/ -#if !defined(STM32_NAND_NAND1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_NAND_NAND1_DMA_PRIORITY 0 -#endif - -/** -* @brief NAND2 DMA priority (0..3|lowest..highest). -*/ -#if !defined(STM32_NAND_NAND2_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_NAND_NAND2_DMA_PRIORITY 0 -#endif - -/** - * @brief DMA stream used for NAND operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_NAND_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) -#endif - -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !STM32_NAND_USE_FSMC_NAND1 && !STM32_NAND_USE_FSMC_NAND2 -#error "NAND driver activated but no NAND peripheral assigned" -#endif - -#if (STM32_NAND_USE_FSMC_NAND2 || STM32_NAND_USE_FSMC_NAND1) && !STM32_HAS_FSMC -#error "FSMC not present in the selected device" -#endif - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a structure representing an NAND driver. - */ -typedef struct NANDDriver NANDDriver; - -/** - * @brief Type of interrupt handler function. - */ -typedef void (*nandisrhandler_t)(NANDDriver *nandp); - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief Number of erase blocks in NAND device. - */ - uint32_t blocks; - /** - * @brief Number of data bytes in page. - */ - uint32_t page_data_size; - /** - * @brief Number of spare bytes in page. - */ - uint32_t page_spare_size; - /** - * @brief Number of pages in block. - */ - uint32_t pages_per_block; - /** - * @brief Number of write cycles for row addressing. - */ - uint8_t rowcycles; - /** - * @brief Number of write cycles for column addressing. - */ - uint8_t colcycles; - - /* End of the mandatory fields.*/ - /** - * @brief Number of wait cycles. This value will be used both for - * PMEM and PATTR registers - * - * @note For proper calculation procedure please look at AN2784 document - * from STMicroelectronics. - */ - uint32_t pmem; -} NANDConfig; - -/** - * @brief Structure representing an NAND driver. - */ -struct NANDDriver { - /** - * @brief Driver state. - */ - nandstate_t state; - /** - * @brief Current configuration data. - */ - const NANDConfig *config; - /** - * @brief Array to store bad block map. - */ -#if NAND_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) -#if CH_CFG_USE_MUTEXES || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the bus. - */ - mutex_t mutex; -#elif CH_CFG_USE_SEMAPHORES - semaphore_t semaphore; -#endif -#endif /* NAND_USE_MUTUAL_EXCLUSION */ - /* End of the mandatory fields.*/ - /** - * @brief Function enabling interrupts from FSMC. - */ - nandisrhandler_t isr_handler; - /** - * @brief Pointer to current transaction buffer. - */ - void *rxdata; - /** - * @brief Current transaction length in bytes. - */ - size_t datalen; - /** - * @brief DMA mode bit mask. - */ - uint32_t dmamode; - /** - * @brief DMA channel. - */ - const stm32_dma_stream_t *dma; - /** - * @brief Thread waiting for I/O completion. - */ - thread_t *thread; - /** - * @brief Pointer to the FSMC NAND registers block. - */ - FSMC_NAND_TypeDef *nand; - /** - * @brief Memory mapping for data. - */ - uint16_t *map_data; - /** - * @brief Memory mapping for commands. - */ - uint16_t *map_cmd; - /** - * @brief Memory mapping for addresses. - */ - uint16_t *map_addr; - /** - * @brief Pointer to bad block map. - * @details One bit per block. All memory allocation is user's responsibility. - */ - bitmap_t *bb_map; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_NAND_USE_FSMC_NAND1 && !defined(__DOXYGEN__) -extern NANDDriver NANDD1; -#endif - -#if STM32_NAND_USE_FSMC_NAND2 && !defined(__DOXYGEN__) -extern NANDDriver NANDD2; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void nand_lld_init(void); - void nand_lld_start(NANDDriver *nandp); - void nand_lld_stop(NANDDriver *nandp); - uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr, size_t addrlen); - void nand_lld_read_data(NANDDriver *nandp, uint16_t *data, - size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc); - void nand_lld_write_addr(NANDDriver *nandp, const uint8_t *addr, size_t len); - void nand_lld_write_cmd(NANDDriver *nandp, uint8_t cmd); - uint8_t nand_lld_write_data(NANDDriver *nandp, const uint16_t *data, - size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc); - uint8_t nand_lld_read_status(NANDDriver *nandp); - void nand_lld_reset(NANDDriver *nandp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_NAND */ - -#endif /* HAL_NAND_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.c b/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.c deleted file mode 100644 index f0fd289e2b..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.c +++ /dev/null @@ -1,3792 +0,0 @@ -/* - Copyright (C) 2013-2015 Andrea Zoppi - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_stm32_ltdc.c - * @brief LCD-TFT Controller Driver. - */ - -#include "ch.h" -#include "hal.h" - -#include "hal_stm32_ltdc.h" - -#if (TRUE == STM32_LTDC_USE_LTDC) || defined(__DOXYGEN__) - -/* TODO: Check preconditions (e.g., LTDC is ready).*/ - -/* Ignore annoying warning messages for actually safe code.*/ -#if defined(__GNUC__) && !defined(__DOXYGEN__) -#pragma GCC diagnostic ignored "-Wtype-limits" -#endif - -/** - * @addtogroup ltdc - * @{ - */ - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#if !defined(LTDC_LxBFCR_BF) && !defined(__DOXYGEN__) -#define LTDC_LxBFCR_BF (LTDC_LxBFCR_BF1 | LTDC_LxBFCR_BF2) -#endif - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief LTDC1 driver identifier. - */ -LTDCDriver LTDCD1; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief Bits per pixel lookup table. - */ -static const uint8_t ltdc_bpp[LTDC_MAX_PIXFMT_ID + 1] = { - 32, /* LTDC_FMT_ARGB8888 */ - 24, /* LTDC_FMT_RGB888 */ - 16, /* LTDC_FMT_RGB565 */ - 16, /* LTDC_FMT_ARGB1555 */ - 16, /* LTDC_FMT_ARGB4444 */ - 8, /* LTDC_FMT_L8 */ - 8, /* LTDC_FMT_AL44 */ - 16 /* LTDC_FMT_AL88 */ -}; - -/** - * @brief Invalid frame. - */ -static const ltdc_frame_t ltdc_invalid_frame = { - NULL, - 1, - 1, - 1, - LTDC_FMT_L8 -}; - -/** - * @brief Invalid window. - * @details Pixel size, located at the origin of the screen. - */ -static const ltdc_window_t ltdc_invalid_window = { - 0, - 1, - 0, - 1 -}; - -/** - * @brief Default layer specifications. - */ -static const ltdc_laycfg_t ltdc_default_laycfg = { - <dc_invalid_frame, - <dc_invalid_window, - LTDC_COLOR_BLACK, - 0x00, - LTDC_COLOR_BLACK, - NULL, - 0, - LTDC_BLEND_FIX1_FIX2, - 0 -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Forces LTDC register reload. - * @details Blocking function. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @sclass - * @notapi - */ -static void ltdc_force_reload_s(LTDCDriver *ltdcp) { - - osalDbgCheckClassS(); - osalDbgCheck(ltdcp == <DCD1); - - LTDC->SRCR |= LTDC_SRCR_IMR; - while (LTDC->SRCR & (LTDC_SRCR_IMR | LTDC_SRCR_VBR)) - chSchDoYieldS(); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @name LTDC interrupt handlers - * @{ - */ - -/** - * @brief LTDC event interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_LTDC_EV_HANDLER) { - - LTDCDriver *const ltdcp = <DCD1; - thread_t *tp = NULL; - - OSAL_IRQ_PROLOGUE(); - - /* Handle Line Interrupt ISR.*/ - if ((LTDC->ISR & LTDC_ISR_LIF) && (LTDC->IER & LTDC_IER_LIE)) { - osalDbgAssert(ltdcp->config->line_isr != NULL, "invalid state"); - ltdcp->config->line_isr(ltdcp); - LTDC->ICR |= LTDC_ICR_CLIF; - } - - /* Handle Register Reload ISR.*/ - if ((LTDC->ISR & LTDC_ISR_RRIF) && (LTDC->IER & LTDC_IER_RRIE)) { - if (ltdcp->config->rr_isr != NULL) - ltdcp->config->rr_isr(ltdcp); - - osalSysLockFromISR(); - osalDbgAssert(ltdcp->state == LTDC_ACTIVE, "invalid state"); -#if (TRUE == LTDC_USE_WAIT) - /* Wake the waiting thread up.*/ - if (ltdcp->thread != NULL) { - tp = ltdcp->thread; - ltdcp->thread = NULL; - tp->u.rdymsg = MSG_OK; - chSchReadyI(tp); - } -#endif /* LTDC_USE_WAIT */ - ltdcp->state = LTDC_READY; - osalSysUnlockFromISR(); - - LTDC->ICR |= LTDC_ICR_CRRIF; - } - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief LTDC error interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_LTDC_ER_HANDLER) { - - static LTDCDriver *const ltdcp = <DCD1; - - OSAL_IRQ_PROLOGUE(); - - /* Handle FIFO Underrun ISR.*/ - if ((LTDC->ISR & LTDC_ISR_FUIF) && (LTDC->IER & LTDC_IER_FUIE)) { - osalDbgAssert(ltdcp->config->fuerr_isr != NULL, "invalid state"); - ltdcp->config->fuerr_isr(ltdcp); - LTDC->ICR |= LTDC_ICR_CFUIF; - } - - /* Handle Transfer Error ISR.*/ - if ((LTDC->ISR & LTDC_ISR_TERRIF) && (LTDC->IER & LTDC_IER_TERRIE)) { - osalDbgAssert(ltdcp->config->terr_isr != NULL, "invalid state"); - ltdcp->config->terr_isr(ltdcp); - LTDC->ICR |= LTDC_ICR_CTERRIF; - } - - OSAL_IRQ_EPILOGUE(); -} - -/** @} */ - -/** - * @name LTDC driver-specific methods - * @{ - */ - -/** - * @brief LTDC Driver initialization. - * @details Initializes the LTDC subsystem and chosen drivers. Should be - * called at board initialization. - * - * @init - */ -void ltdcInit(void) { - - /* Reset the LTDC hardware module.*/ - rccResetLTDC(); - - /* Enable the LTDC clock.*/ - RCC->DCKCFGR = (RCC->DCKCFGR & ~RCC_DCKCFGR_PLLSAIDIVR) | (2 << 16); /* /8 */ - rccEnableLTDC(false); - - /* Driver struct initialization.*/ - ltdcObjectInit(<DCD1); - LTDCD1.state = LTDC_STOP; -} - -/** - * @brief Initializes the standard part of a @p LTDCDriver structure. - * - * @param[out] ltdcp pointer to the @p LTDCDriver object - * - * @init - */ -void ltdcObjectInit(LTDCDriver *ltdcp) { - - osalDbgCheck(ltdcp == <DCD1); - - ltdcp->state = LTDC_UNINIT; - ltdcp->config = NULL; - ltdcp->active_window = ltdc_invalid_window; -#if (TRUE == LTDC_USE_WAIT) - ltdcp->thread = NULL; -#endif /* LTDC_USE_WAIT */ -#if (TRUE == LTDC_USE_MUTUAL_EXCLUSION) -#if (TRUE == CH_CFG_USE_MUTEXES) - chMtxObjectInit(<dcp->lock); -#else - chSemObjectInit(<dcp->lock, 1); -#endif -#endif /* LTDC_USE_MUTUAL_EXCLUSION */ -} - -/** - * @brief Get the driver state. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @retun driver state - * - * @iclass - */ -ltdc_state_t ltdcGetStateI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - - return ltdcp->state; -} - -/** - * @brief Get the driver state. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @retun driver state - * - * @api - */ -ltdc_state_t ltdcGetState(LTDCDriver *ltdcp) { - - ltdc_state_t state; - osalSysLock(); - state = ltdcGetStateI(ltdcp); - osalSysUnlock(); - return state; -} - -/** - * @brief Configures and activates the LTDC peripheral. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] configp pointer to the @p LTDCConfig object - * - * @api - */ -void ltdcStart(LTDCDriver *ltdcp, const LTDCConfig *configp) { - - uint32_t hacc, vacc, flags; - - osalSysLock(); - - osalDbgCheck(ltdcp == <DCD1); - osalDbgCheck(configp != NULL); - osalDbgAssert(ltdcp->state == LTDC_STOP, "invalid state"); - - ltdcp->config = configp; - - /* Turn off the controller and its interrupts.*/ - LTDC->GCR = 0; - LTDC->IER = 0; - ltdc_force_reload_s(ltdcp); - - /* Set synchronization params.*/ - osalDbgAssert(configp->hsync_width >= LTDC_MIN_HSYNC_WIDTH, "bounds"); - osalDbgAssert(configp->hsync_width <= LTDC_MAX_HSYNC_WIDTH, "bounds"); - osalDbgAssert(configp->vsync_height >= LTDC_MIN_VSYNC_HEIGHT, "bounds"); - osalDbgAssert(configp->vsync_height <= LTDC_MAX_VSYNC_HEIGHT, "bounds"); - - hacc = configp->hsync_width - 1; - vacc = configp->vsync_height - 1; - - LTDC->SSCR = (((hacc << 16) & LTDC_SSCR_HSW) | - ((vacc << 0) & LTDC_SSCR_VSH)); - - /* Set accumulated back porch params.*/ - osalDbgAssert(configp->hbp_width >= LTDC_MIN_HBP_WIDTH, "bounds"); - osalDbgAssert(configp->hbp_width <= LTDC_MAX_HBP_WIDTH, "bounds"); - osalDbgAssert(configp->vbp_height >= LTDC_MIN_VBP_HEIGHT, "bounds"); - osalDbgAssert(configp->vbp_height <= LTDC_MAX_VBP_HEIGHT, "bounds"); - - hacc += configp->hbp_width; - vacc += configp->vbp_height; - - osalDbgAssert(hacc + 1 >= LTDC_MIN_ACC_HBP_WIDTH, "bounds"); - osalDbgAssert(hacc + 1 <= LTDC_MAX_ACC_HBP_WIDTH, "bounds"); - osalDbgAssert(vacc + 1 >= LTDC_MIN_ACC_VBP_HEIGHT, "bounds"); - osalDbgAssert(vacc + 1 <= LTDC_MAX_ACC_VBP_HEIGHT, "bounds"); - - LTDC->BPCR = (((hacc << 16) & LTDC_BPCR_AHBP) | - ((vacc << 0) & LTDC_BPCR_AVBP)); - - ltdcp->active_window.hstart = hacc + 1; - ltdcp->active_window.vstart = vacc + 1; - - /* Set accumulated active params.*/ - osalDbgAssert(configp->screen_width >= LTDC_MIN_SCREEN_WIDTH, "bounds"); - osalDbgAssert(configp->screen_width <= LTDC_MAX_SCREEN_WIDTH, "bounds"); - osalDbgAssert(configp->screen_height >= LTDC_MIN_SCREEN_HEIGHT, "bounds"); - osalDbgAssert(configp->screen_height <= LTDC_MAX_SCREEN_HEIGHT, "bounds"); - - hacc += configp->screen_width; - vacc += configp->screen_height; - - osalDbgAssert(hacc + 1 >= LTDC_MIN_ACC_ACTIVE_WIDTH, "bounds"); - osalDbgAssert(hacc + 1 <= LTDC_MAX_ACC_ACTIVE_WIDTH, "bounds"); - osalDbgAssert(vacc + 1 >= LTDC_MIN_ACC_ACTIVE_HEIGHT, "bounds"); - osalDbgAssert(vacc + 1 <= LTDC_MAX_ACC_ACTIVE_HEIGHT, "bounds"); - - LTDC->AWCR = (((hacc << 16) & LTDC_AWCR_AAW) | - ((vacc << 0) & LTDC_AWCR_AAH)); - - ltdcp->active_window.hstop = hacc; - ltdcp->active_window.vstop = vacc; - - /* Set accumulated total params.*/ - osalDbgAssert(configp->hfp_width >= LTDC_MIN_HFP_WIDTH, "bounds"); - osalDbgAssert(configp->hfp_width <= LTDC_MAX_HFP_WIDTH, "bounds"); - osalDbgAssert(configp->vfp_height >= LTDC_MIN_VFP_HEIGHT, "bounds"); - osalDbgAssert(configp->vfp_height <= LTDC_MAX_VFP_HEIGHT, "bounds"); - - hacc += configp->hfp_width; - vacc += configp->vfp_height; - - osalDbgAssert(hacc + 1 >= LTDC_MIN_ACC_TOTAL_WIDTH, "bounds"); - osalDbgAssert(hacc + 1 <= LTDC_MAX_ACC_TOTAL_WIDTH, "bounds"); - osalDbgAssert(vacc + 1 >= LTDC_MIN_ACC_TOTAL_HEIGHT, "bounds"); - osalDbgAssert(vacc + 1 <= LTDC_MAX_ACC_TOTAL_HEIGHT, "bounds"); - - LTDC->TWCR = (((hacc << 16) & LTDC_TWCR_TOTALW) | - ((vacc << 0) & LTDC_TWCR_TOTALH)); - - /* Set signal polarities and other flags.*/ - ltdcSetEnableFlagsI(ltdcp, configp->flags & ~LTDC_EF_ENABLE); - - /* Color settings.*/ - ltdcSetClearColorI(ltdcp, configp->clear_color); - - /* Load layer configurations.*/ - ltdcBgSetConfigI(ltdcp, configp->bg_laycfg); - ltdcFgSetConfigI(ltdcp, configp->fg_laycfg); - - /* Enable only the assigned interrupt service routines.*/ - nvicEnableVector(STM32_LTDC_EV_NUMBER, STM32_LTDC_EV_IRQ_PRIORITY); - nvicEnableVector(STM32_LTDC_ER_NUMBER, STM32_LTDC_ER_IRQ_PRIORITY); - - flags = LTDC_IER_RRIE; - if (configp->line_isr != NULL) - flags |= LTDC_IER_LIE; - if (configp->fuerr_isr != NULL) - flags |= LTDC_IER_FUIE; - if (configp->terr_isr != NULL) - flags |= LTDC_IER_TERRIE; - LTDC->IER = flags; - - /* Apply settings.*/ - ltdc_force_reload_s(ltdcp); - - /* Turn on the controller.*/ - LTDC->GCR |= LTDC_GCR_LTDCEN; - ltdc_force_reload_s(ltdcp); - - ltdcp->state = LTDC_READY; - osalSysUnlock(); -} - -/** - * @brief Deactivates the LTDC peripheral. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcStop(LTDCDriver *ltdcp) { - - osalDbgCheck(ltdcp == <DCD1); - - osalSysLock(); - osalDbgAssert(ltdcp->state == LTDC_READY, "invalid state"); - - /* Turn off the controller and its interrupts.*/ - LTDC->GCR &= ~LTDC_GCR_LTDCEN; - LTDC->IER = 0; -#if (TRUE == LTDC_USE_WAIT) - ltdcReloadS(ltdcp, true); -#else - ltdcStartReloadI(ltdcp, true); - while (ltdcIsReloadingI(ltdcp)) - chSchDoYieldS(); -#endif /* LTDC_USE_WAIT */ - - ltdcp->state = LTDC_STOP; - osalSysUnlock(); -} - -#if (TRUE == LTDC_USE_MUTUAL_EXCLUSION) - -/** - * @brief Gains exclusive access to the LTDC module. - * @details This function tries to gain ownership to the LTDC module, if the - * module is already being used then the invoking thread is queued. - * @pre In order to use this function the option - * @p LTDC_USE_MUTUAL_EXCLUSION must be enabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @sclass - */ -void ltdcAcquireBusS(LTDCDriver *ltdcp) { - - osalDbgCheckClassS(); - osalDbgCheck(ltdcp == <DCD1); - -#if (TRUE == CH_CFG_USE_MUTEXES) - chMtxLockS(<dcp->lock); -#else - chSemWaitS(<dcp->lock); -#endif -} - -/** - * @brief Gains exclusive access to the LTDC module. - * @details This function tries to gain ownership to the LTDC module, if the - * module is already being used then the invoking thread is queued. - * @pre In order to use this function the option - * @p LTDC_USE_MUTUAL_EXCLUSION must be enabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcAcquireBus(LTDCDriver *ltdcp) { - - osalSysLock(); - ltdcAcquireBusS(ltdcp); - osalSysUnlock(); -} - -/** - * @brief Releases exclusive access to the LTDC module. - * @pre In order to use this function the option - * @p LTDC_USE_MUTUAL_EXCLUSION must be enabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @sclass - */ -void ltdcReleaseBusS(LTDCDriver *ltdcp) { - - osalDbgCheckClassS(); - osalDbgCheck(ltdcp == <DCD1); - -#if (TRUE == CH_CFG_USE_MUTEXES) - chMtxUnlockS(<dcp->lock); -#else - chSemSignalI(<dcp->lock); -#endif -} - -/** - * @brief Releases exclusive access to the LTDC module. - * @pre In order to use this function the option - * @p LTDC_USE_MUTUAL_EXCLUSION must be enabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcReleaseBus(LTDCDriver *ltdcp) { - - osalSysLock(); - ltdcReleaseBusS(ltdcp); - osalSysUnlock(); -} - -#endif /* LTDC_USE_MUTUAL_EXCLUSION */ - -/** @} */ - -/** - * @name LTDC global methods - * @{ - */ - -/** - * @brief Get enabled flags. - * @details Returns all the flags of the LTDC_EF_* group at once. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled flags - * - * @iclass - */ -ltdc_flags_t ltdcGetEnableFlagsI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return LTDC->GCR & LTDC_EF_MASK; -} - -/** - * @brief Get enabled flags. - * @details Returns all the flags of the LTDC_EF_* group at once. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled flags - * - * @api - */ -ltdc_flags_t ltdcGetEnableFlags(LTDCDriver *ltdcp) { - - ltdc_flags_t flags; - osalSysLock(); - flags = ltdcGetEnableFlagsI(ltdcp); - osalSysUnlock(); - return flags; -} - -/** - * @brief Set enabled flags. - * @details Sets all the flags of the LTDC_EF_* group at once. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] flags enabled flags - * - * @iclass - */ -void ltdcSetEnableFlagsI(LTDCDriver *ltdcp, ltdc_flags_t flags) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC->GCR = flags & LTDC_EF_MASK; -} - -/** - * @brief Set enabled flags. - * @details Sets all the flags of the LTDC_EF_* group at once. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] flags enabled flags - * - * @api - */ -void ltdcSetEnableFlags(LTDCDriver *ltdcp, ltdc_flags_t flags) { - - osalSysLock(); - ltdcSetEnableFlagsI(ltdcp, flags); - osalSysUnlock(); -} - -/** - * @brief Reloading shadow registers. - * @details Tells whether the LTDC is reloading shadow registers. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return reloading - * - * @iclass - */ -bool ltdcIsReloadingI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (LTDC->SRCR & (LTDC_SRCR_IMR | LTDC_SRCR_VBR)) != 0; -} - -/** - * @brief Reloading shadow registers. - * @details Tells whether the LTDC is reloading shadow registers. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return reloading - * - * @api - */ -bool ltdcIsReloading(LTDCDriver *ltdcp) { - - bool reloading; - osalSysLock(); - reloading = ltdcIsReloadingI(ltdcp); - osalSysUnlock(); - return reloading; -} - -/** - * @brief Reload shadow registers. - * @details Starts reloading LTDC shadow registers, upon vsync or immediately. - * @post At the end of the operation the configured callback is invoked. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] immediately reload immediately, not upon vsync - * - * @iclass - */ -void ltdcStartReloadI(LTDCDriver *ltdcp, bool immediately) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - osalDbgAssert(ltdcp->state == LTDC_READY, "not ready"); - (void)ltdcp; - - ltdcp->state = LTDC_ACTIVE; - if (immediately) - LTDC->SRCR |= LTDC_SRCR_IMR; - else - LTDC->SRCR |= LTDC_SRCR_VBR; -} - -/** - * @brief Reload shadow registers. - * @details Starts reloading LTDC shadow registers, upon vsync or immediately. - * @post At the end of the operation the configured callback is invoked. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] immediately reload immediately, not upon vsync - * - * @api - */ -void ltdcStartReload(LTDCDriver *ltdcp, bool immediately) { - - osalSysLock(); - ltdcStartReloadI(ltdcp, immediately); - osalSysUnlock(); -} - -/** - * @brief Reload shadow registers. - * @details Reloads LTDC shadow registers, upon vsync or immediately. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] immediately reload immediately, not upon vsync - * - * @sclass - */ -void ltdcReloadS(LTDCDriver *ltdcp, bool immediately) { - - osalDbgCheckClassS(); - osalDbgCheck(ltdcp == <DCD1); - - ltdcStartReloadI(ltdcp, immediately); - -#if (TRUE == LTDC_USE_WAIT) - osalDbgAssert(ltdcp->thread == NULL, "already waiting"); - - if (immediately) { - while (LTDC->SRCR & LTDC_SRCR_IMR) - chSchDoYieldS(); - ltdcp->state = LTDC_READY; - } else { - ltdcp->thread = chThdGetSelfX(); - chSchGoSleepS(CH_STATE_SUSPENDED); - } -#else - while (LTDC->SRCR & LTDC_SRCR_IMR) - chSchDoYieldS(); - ltdcp->state = LTDC_READY; -#endif -} - -/** - * @brief Reload shadow registers. - * @details Reloads LTDC shadow registers, upon vsync or immediately. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] immediately reload immediately, not upon vsync - * - * @api - */ -void ltdcReload(LTDCDriver *ltdcp, bool immediately) { - - osalSysLock(); - ltdcReloadS(ltdcp, immediately); - osalSysUnlock(); -} - -/** - * @brief Dithering enabled. - * @details Tells whether the dithering is enabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled - * - * @iclass - */ -bool ltdcIsDitheringEnabledI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (LTDC->GCR & LTDC_GCR_DTEN) != 0; -} - -/** - * @brief Dithering enabled. - * @details Tells whether the dithering is enabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled - * - * @api - */ -bool ltdcIsDitheringEnabled(LTDCDriver *ltdcp) { - - bool enabled; - osalSysLock(); - enabled = ltdcIsDitheringEnabledI(ltdcp); - osalSysUnlock(); - return enabled; -} - -/** - * @brief Enable dithering. - * @details Enables dithering capabilities for pixel formats with less than - * 8 bits per channel. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @iclass - */ -void ltdcEnableDitheringI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC->GCR |= LTDC_GCR_DTEN; -} - -/** - * @brief Enable dithering. - * @details Enables dithering capabilities for pixel formats with less than - * 8 bits per channel. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcEnableDithering(LTDCDriver *ltdcp) { - - osalSysLock(); - ltdcEnableDitheringI(ltdcp); - osalSysUnlock(); -} - -/** - * @brief Disable dithering. - * @details Disables dithering capabilities for pixel formats with less than - * 8 bits per channel. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @iclass - */ -void ltdcDisableDitheringI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC->GCR &= ~LTDC_GCR_DTEN; -} - -/** - * @brief Disable dithering. - * @details Disables dithering capabilities for pixel formats with less than - * 8 bits per channel. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcDisableDithering(LTDCDriver *ltdcp) { - - osalSysLock(); - ltdcDisableDitheringI(ltdcp); - osalSysUnlock(); -} - -/** - * @brief Get clear screen color. - * @details Gets the clear screen (actual background) color. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return clear screen color, RGB-888 - * - * @iclass - */ -ltdc_color_t ltdcGetClearColorI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (ltdc_color_t)(LTDC->BCCR & 0x00FFFFFF); -} - -/** - * @brief Get clear screen color. - * @details Gets the clear screen (actual background) color. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return clear screen color, RGB-888 - * - * @api - */ -ltdc_color_t ltdcGetClearColor(LTDCDriver *ltdcp) { - - ltdc_color_t color; - osalSysLock(); - color = ltdcGetClearColorI(ltdcp); - osalSysUnlock(); - return color; -} - -/** - * @brief Set clear screen color. - * @details Sets the clear screen (actual background) color. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] c clear screen color, RGB-888 - * - * @iclass - */ -void ltdcSetClearColorI(LTDCDriver *ltdcp, ltdc_color_t c) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC->BCCR = (LTDC->BCCR & ~0x00FFFFFF) | (c & 0x00FFFFFF); -} - -/** - * @brief Set clear screen color. - * @details Sets the clear screen (actual background) color. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] c clear screen color, RGB-888 - * - * @api - */ -void ltdcSetClearColor(LTDCDriver *ltdcp, ltdc_color_t c) { - - osalSysLock(); - ltdcSetClearColorI(ltdcp, c); - osalSysUnlock(); -} - -/** - * @brief Get line interrupt position. - * @details Gets the line interrupt position. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return line interrupt position - * - * @iclass - */ -uint16_t ltdcGetLineInterruptPosI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (uint16_t)(LTDC->LIPCR & LTDC_LIPCR_LIPOS); -} - -/** - * @brief Get line interrupt position. - * @details Gets the line interrupt position. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return line interrupt position - * - * @api - */ -uint16_t ltdcGetLineInterruptPos(LTDCDriver *ltdcp) { - - uint16_t line; - osalSysLock(); - line = ltdcGetLineInterruptPosI(ltdcp); - osalSysUnlock(); - return line; -} - -/** - * @brief Set line interrupt position. - * @details Sets the line interrupt position. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @iclass - */ -void ltdcSetLineInterruptPosI(LTDCDriver *ltdcp, uint16_t line) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC->LIPCR = ((LTDC->LIPCR & ~LTDC_LIPCR_LIPOS) | - ((uint32_t)line & LTDC_LIPCR_LIPOS)); -} - -/** - * @brief Set line interrupt position. - * @details Sets the line interrupt position. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcSetLineInterruptPos(LTDCDriver *ltdcp, uint16_t line) { - - osalSysLock(); - ltdcSetLineInterruptPosI(ltdcp, line); - osalSysUnlock(); -} - -/** - * @brief Line interrupt enabled. - * @details Tells whether the line interrupt is enabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled - * - * @iclass - */ -bool ltdcIsLineInterruptEnabledI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (LTDC->IER & LTDC_IER_LIE) != 0; -} - -/** - * @brief Line interrupt enabled. - * @details Tells whether the line interrupt is enabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled - * - * @api - */ -bool ltdcIsLineInterruptEnabled(LTDCDriver *ltdcp) { - - bool enabled; - osalSysLock(); - enabled = ltdcIsLineInterruptEnabledI(ltdcp); - osalSysUnlock(); - return enabled; -} - -/** - * @brief Enable line interrupt. - * @details Enables line interrupt. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @iclass - */ -void ltdcEnableLineInterruptI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC->IER |= LTDC_IER_LIE; -} - -/** - * @brief Enable line interrupt. - * @details Enables line interrupt. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcEnableLineInterrupt(LTDCDriver *ltdcp) { - - osalSysLock(); - ltdcEnableLineInterruptI(ltdcp); - osalSysUnlock(); -} - -/** - * @brief Disable line interrupt. - * @details Disables line interrupt. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @iclass - */ -void ltdcDisableLineInterruptI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC->IER &= ~LTDC_IER_LIE; -} - -/** - * @brief Disable line interrupt. - * @details Disables line interrupt. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcDisableLineInterrupt(LTDCDriver *ltdcp) { - - osalSysLock(); - ltdcDisableLineInterruptI(ltdcp); - osalSysUnlock(); -} - -/** - * @brief Get current position. - * @details Gets the current position. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[out] xp pointer to the destination horizontal coordinate - * @param[out] yp pointer to the destination vertical coordinate - * - * @iclass - */ -void ltdcGetCurrentPosI(LTDCDriver *ltdcp, uint16_t *xp, uint16_t *yp) { - - const uint32_t r = LTDC->CPSR; - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - *xp = (uint16_t)((r & LTDC_CPSR_CXPOS) >> 16); - *yp = (uint16_t)((r & LTDC_CPSR_CYPOS) >> 0); -} - -/** - * @brief Get current position. - * @details Gets the current position. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[out] xp pointer to the destination horizontal coordinate - * @param[out] yp pointer to the destination vertical coordinate - * - * @api - */ -void ltdcGetCurrentPos(LTDCDriver *ltdcp, uint16_t *xp, uint16_t *yp) { - - osalSysLock(); - ltdcGetCurrentPosI(ltdcp, xp, yp); - osalSysUnlock(); -} - -/** @} */ - -/** - * @name LTDC background layer (layer 1) methods - * @{ - */ - -/** - * @brief Get background layer enabled flags. - * @details Returns all the flags of the LTDC_LEF_* group at once. - * Targeting the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled flags - * - * @iclass - */ -ltdc_flags_t ltdcBgGetEnableFlagsI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return LTDC_Layer1->CR & LTDC_LEF_MASK; -} - -/** - * @brief Get background layer enabled flags. - * @details Returns all the flags of the LTDC_LEF_* group at once. - * Targeting the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled flags - * - * @api - */ -ltdc_flags_t ltdcBgGetEnableFlags(LTDCDriver *ltdcp) { - - ltdc_flags_t flags; - osalSysLock(); - flags = ltdcBgGetEnableFlagsI(ltdcp); - osalSysUnlock(); - return flags; -} - -/** - * @brief Set background layer enabled flags. - * @details Sets all the flags of the LTDC_LEF_* group at once. - * Targeting the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] flags enabled flags - * - * @iclass - */ -void ltdcBgSetEnableFlagsI(LTDCDriver *ltdcp, ltdc_flags_t flags) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer1->CR = ((LTDC_Layer1->CR & ~LTDC_LEF_MASK) | - ((uint32_t)flags & LTDC_LEF_MASK)); -} - -/** - * @brief Set background layer enabled flags. - * @details Sets all the flags of the LTDC_LEF_* group at once. - * Targeting the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] flags enabled flags - * - * @api - */ -void ltdcBgSetEnableFlags(LTDCDriver *ltdcp, ltdc_flags_t flags) { - - osalSysLock(); - ltdcBgSetEnableFlagsI(ltdcp, flags); - osalSysUnlock(); -} - -/** - * @brief Background layer enabled. - * @details Tells whether the background layer (layer 1) is enabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled - * - * @iclass - */ -bool ltdcBgIsEnabledI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (LTDC_Layer1->CR & ~LTDC_LxCR_LEN) != 0; -} - -/** - * @brief Background layer enabled. - * @details Tells whether the background layer (layer 1) is enabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled - * - * @api - */ -bool ltdcBgIsEnabled(LTDCDriver *ltdcp) { - - bool enabled; - osalSysLock(); - enabled = ltdcBgIsEnabledI(ltdcp); - osalSysUnlock(); - return enabled; -} - -/** - * @brief Background layer enable. - * @details Enables the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @iclass - */ -void ltdcBgEnableI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer1->CR |= LTDC_LxCR_LEN; -} - -/** - * @brief Background layer enable. - * @details Enables the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcBgEnable(LTDCDriver *ltdcp) { - - osalSysLock(); - ltdcBgEnableI(ltdcp); - osalSysUnlock(); -} - -/** - * @brief Background layer disable. - * @details Disables the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @iclass - */ -void ltdcBgDisableI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer1->CR &= ~LTDC_LxCR_LEN; -} - -/** - * @brief Background layer disable. - * @details Disables the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcBgDisable(LTDCDriver *ltdcp) { - - osalSysLock(); - ltdcBgDisableI(ltdcp); - osalSysUnlock(); -} - -/** - * @brief Background layer palette enabled. - * @details Tells whether the background layer (layer 1) palette (color lookup - * table) is enabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled - * - * @iclass - */ -bool ltdcBgIsPaletteEnabledI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (LTDC_Layer1->CR & ~LTDC_LxCR_CLUTEN) != 0; -} - -/** - * @brief Background layer palette enabled. - * @details Tells whether the background layer (layer 1) palette (color lookup - * table) is enabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled - * - * @api - */ -bool ltdcBgIsPaletteEnabled(LTDCDriver *ltdcp) { - - bool enabled; - osalSysLock(); - enabled = ltdcBgIsPaletteEnabledI(ltdcp); - osalSysUnlock(); - return enabled; -} - -/** - * @brief Enable background layer palette. - * @details Enables the palette (color lookup table) of the background layer - * (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @iclass - */ -void ltdcBgEnablePaletteI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer1->CR |= LTDC_LxCR_CLUTEN; -} - -/** - * @brief Enable background layer palette. - * @details Enables the palette (color lookup table) of the background layer - * (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcBgEnablePalette(LTDCDriver *ltdcp) { - - osalSysLock(); - ltdcBgEnablePaletteI(ltdcp); - osalSysUnlock(); -} - -/** - * @brief Disable background layer palette. - * @details Disables the palette (color lookup table) of the background layer - * (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @iclass - */ -void ltdcBgDisablePaletteI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer1->CR &= ~LTDC_LxCR_CLUTEN; -} - -/** - * @brief Disable background layer palette. - * @details Disables the palette (color lookup table) of the background layer - * (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcBgDisablePalette(LTDCDriver *ltdcp) { - - osalSysLock(); - ltdcBgDisablePaletteI(ltdcp); - osalSysUnlock(); -} - -/** - * @brief Set background layer palette color. - * @details Sets the color of a palette (color lookup table) slot to the - * background layer (layer 1). - * @pre The layer must be disabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] slot palette slot - * @param[in] c color, RGB-888 - * - * @iclass - */ -void ltdcBgSetPaletteColorI(LTDCDriver *ltdcp, uint8_t slot, ltdc_color_t c) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - osalDbgAssert(!ltdcBgIsEnabledI(ltdcp), "invalid state"); - (void)ltdcp; - - LTDC_Layer1->CLUTWR = (((uint32_t)slot << 24) | (c & 0x00FFFFFF)); -} - -/** - * @brief Set background layer palette color. - * @details Sets the color of a palette (color lookup table) slot to the - * background layer (layer 1). - * @pre The layer must be disabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] slot palette slot - * @param[in] c color, RGB-888 - * - * @api - */ -void ltdcBgSetPaletteColor(LTDCDriver *ltdcp, uint8_t slot, ltdc_color_t c) { - - osalSysLock(); - ltdcBgSetPaletteColorI(ltdcp, slot, c); - osalSysUnlock(); -} - -/** - * @brief Set background layer palette. - * @details Sets the entire palette color (color lookup table) slot. - * @pre The layer must be disabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] colors array of palette colors, RGB-888 - * @param[in] length number of palette colors - * - * @iclass - */ -void ltdcBgSetPaletteI(LTDCDriver *ltdcp, const ltdc_color_t colors[], - uint16_t length) { - - uint16_t i; - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - osalDbgCheck((colors == NULL) == (length == 0)); - osalDbgAssert(length <= LTDC_MAX_PALETTE_LENGTH, "bounds"); - osalDbgAssert(!ltdcBgIsEnabledI(ltdcp), "invalid state"); - (void)ltdcp; - - for (i = 0; i < length; ++i) - LTDC_Layer1->CLUTWR = (((uint32_t)i << 24) | (colors[i] & 0x00FFFFFF)); -} - -/** - * @brief Set background layer palette. - * @details Sets the entire palette color (color lookup table) slot. - * @pre The layer must be disabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] colors array of palette colors, RGB-888 - * @param[in] length number of palette colors - * - * @api - */ -void ltdcBgSetPalette(LTDCDriver *ltdcp, const ltdc_color_t colors[], - uint16_t length) { - - osalSysLock(); - ltdcBgSetPaletteI(ltdcp, colors, length); - osalSysUnlock(); -} - -/** - * @brief Get background layer pixel format. - * @details Gets the pixel format of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return pixel format - * - * @iclass - */ -ltdc_pixfmt_t ltdcBgGetPixelFormatI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (ltdc_pixfmt_t)(LTDC_Layer1->PFCR & LTDC_LxPFCR_PF); -} - -/** - * @brief Get background layer pixel format. - * @details Gets the pixel format of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return pixel format - * - * @api - */ -ltdc_pixfmt_t ltdcBgGetPixelFormat(LTDCDriver *ltdcp) { - - ltdc_pixfmt_t fmt; - osalSysLock(); - fmt = ltdcBgGetPixelFormatI(ltdcp); - osalSysUnlock(); - return fmt; -} - -/** - * @brief Set background layer pixel format. - * @details Sets the pixel format of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] fmt pixel format - * - * @iclass - */ -void ltdcBgSetPixelFormatI(LTDCDriver *ltdcp, ltdc_pixfmt_t fmt) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - osalDbgAssert(fmt >= LTDC_MIN_PIXFMT_ID, "bounds"); - osalDbgAssert(fmt <= LTDC_MAX_PIXFMT_ID, "bounds"); - (void)ltdcp; - - LTDC_Layer1->PFCR = ((LTDC_Layer1->PFCR & ~LTDC_LxPFCR_PF) | - ((uint32_t)fmt & LTDC_LxPFCR_PF)); -} - -/** - * @brief Set background layer pixel format. - * @details Sets the pixel format of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] fmt pixel format - * - * @api - */ -void ltdcBgSetPixelFormat(LTDCDriver *ltdcp, ltdc_pixfmt_t fmt) { - - osalSysLock(); - ltdcBgSetPixelFormatI(ltdcp, fmt); - osalSysUnlock(); -} - -/** - * @brief Background layer color keying enabled. - * @details Tells whether the background layer (layer 1) has color keying - * enabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled - * - * @iclass - */ -bool ltdcBgIsKeyingEnabledI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (LTDC_Layer1->CR & ~LTDC_LxCR_COLKEN) != 0; -} - -/** - * @brief Background layer color keying enabled. - * @details Tells whether the background layer (layer 1) has color keying - * enabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled - * - * @api - */ -bool ltdcBgIsKeyingEnabled(LTDCDriver *ltdcp) { - - bool enabled; - osalSysLock(); - enabled = ltdcBgIsKeyingEnabledI(ltdcp); - osalSysUnlock(); - return enabled; -} - -/** - * @brief Enable background layer color keying. - * @details Enables color keying capabilities of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @iclass - */ -void ltdcBgEnableKeyingI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer1->CR |= LTDC_LxCR_COLKEN; -} - -/** - * @brief Enable background layer color keying. - * @details Enables color keying capabilities of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcBgEnableKeying(LTDCDriver *ltdcp) { - - osalSysLock(); - ltdcBgEnableKeyingI(ltdcp); - osalSysUnlock(); -} - -/** - * @brief Disable background layer color keying. - * @details Disables color keying capabilities of the background layer (layer - * 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @iclass - */ -void ltdcBgDisableKeyingI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer1->CR &= ~LTDC_LxCR_COLKEN; -} - -/** - * @brief Disable background layer color keying. - * @details Disables color keying capabilities of the background layer (layer - * 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcBgDisableKeying(LTDCDriver *ltdcp) { - - osalSysLock(); - ltdcBgDisableKeyingI(ltdcp); - osalSysUnlock(); -} - -/** - * @brief Get background layer color key. - * @details Gets the color key of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return color key, RGB-888 - * - * @iclass - */ -ltdc_color_t ltdcBgGetKeyingColorI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (ltdc_color_t)(LTDC_Layer1->CKCR & 0x00FFFFFF); -} - -/** - * @brief Get background layer color key. - * @details Gets the color key of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return color key, RGB-888 - * - * @api - */ -ltdc_color_t ltdcBgGetKeyingColor(LTDCDriver *ltdcp) { - - ltdc_color_t color; - osalSysLock(); - color = ltdcBgGetKeyingColorI(ltdcp); - osalSysUnlock(); - return color; -} - -/** - * @brief Set background layer color key. - * @details Sets the color key of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] c color key, RGB-888 - * - * @iclass - */ -void ltdcBgSetKeyingColorI(LTDCDriver *ltdcp, ltdc_color_t c) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer1->CKCR = ((LTDC_Layer1->CKCR & ~0x00FFFFFF) | - ((uint32_t)c & 0x00FFFFFF)); -} - -/** - * @brief Set background layer color key. - * @details Sets the color key of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] c color key, RGB-888 - * - * @api - */ -void ltdcBgSetKeyingColor(LTDCDriver *ltdcp, ltdc_color_t c) { - - osalSysLock(); - ltdcBgSetKeyingColorI(ltdcp, c); - osalSysUnlock(); -} - -/** - * @brief Get background layer constant alpha. - * @details Gets the constant alpha component of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return constant alpha component, A-8 - * - * @iclass - */ -uint8_t ltdcBgGetConstantAlphaI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (uint8_t)(LTDC_Layer1->CACR & LTDC_LxCACR_CONSTA); -} - -/** - * @brief Get background layer constant alpha. - * @details Gets the constant alpha component of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return constant alpha component, A-8 - * - * @api - */ -uint8_t ltdcBgGetConstantAlpha(LTDCDriver *ltdcp) { - - uint8_t a; - osalSysLock(); - a = ltdcBgGetConstantAlphaI(ltdcp); - osalSysUnlock(); - return a; -} - -/** - * @brief Set background layer constant alpha. - * @details Sets the constant alpha component of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] a constant alpha component, A-8 - * - * @iclass - */ -void ltdcBgSetConstantAlphaI(LTDCDriver *ltdcp, uint8_t a) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer1->CACR = ((LTDC_Layer1->CACR & ~LTDC_LxCACR_CONSTA) | - ((uint32_t)a & LTDC_LxCACR_CONSTA)); -} - -/** - * @brief Set background layer constant alpha. - * @details Sets the constant alpha component of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] a constant alpha component, A-8 - * - * @api - */ -void ltdcBgSetConstantAlpha(LTDCDriver *ltdcp, uint8_t a) { - - osalSysLock(); - ltdcBgSetConstantAlphaI(ltdcp, a); - osalSysUnlock(); -} - -/** - * @brief Get background layer default color. - * @details Gets the default color of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return default color, RGB-888 - * - * @iclass - */ -ltdc_color_t ltdcBgGetDefaultColorI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (ltdc_color_t)LTDC_Layer1->DCCR; -} - -/** - * @brief Get background layer default color. - * @details Gets the default color of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return default color, RGB-888 - * - * @api - */ -ltdc_color_t ltdcBgGetDefaultColor(LTDCDriver *ltdcp) { - - ltdc_color_t color; - osalSysLock(); - color = ltdcBgGetDefaultColorI(ltdcp); - osalSysUnlock(); - return color; -} - -/** - * @brief Set background layer default color. - * @details Sets the default color of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] c default color, RGB-888 - * - * @iclass - */ -void ltdcBgSetDefaultColorI(LTDCDriver *ltdcp, ltdc_color_t c) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer1->DCCR = (uint32_t)c; -} - -/** - * @brief Set background layer default color. - * @details Sets the default color of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] c default color, RGB-888 - * - * @api - */ -void ltdcBgSetDefaultColor(LTDCDriver *ltdcp, ltdc_color_t c) { - - osalSysLock(); - ltdcBgSetDefaultColorI(ltdcp, c); - osalSysUnlock(); -} - -/** - * @brief Get background layer blending factors. - * @details Gets the blending factors of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return blending factors - * - * @iclass - */ -ltdc_blendf_t ltdcBgGetBlendingFactorsI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (ltdc_blendf_t)(LTDC_Layer1->BFCR & LTDC_LxBFCR_BF); -} - -/** - * @brief Get background layer blending factors. - * @details Gets the blending factors of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return blending factors - * - * @api - */ -ltdc_blendf_t ltdcBgGetBlendingFactors(LTDCDriver *ltdcp) { - - ltdc_blendf_t bf; - osalSysLock(); - bf = ltdcBgGetBlendingFactorsI(ltdcp); - osalSysUnlock(); - return bf; -} - -/** - * @brief Set background layer blending factors. - * @details Sets the blending factors of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] factors blending factors - * - * @iclass - */ -void ltdcBgSetBlendingFactorsI(LTDCDriver *ltdcp, ltdc_blendf_t bf) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer1->BFCR = ((LTDC_Layer1->BFCR & ~LTDC_LxBFCR_BF) | - ((uint32_t)bf & LTDC_LxBFCR_BF)); -} - -/** - * @brief Set background layer blending factors. - * @details Sets the blending factors of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] factors blending factors - * - * @api - */ -void ltdcBgSetBlendingFactors(LTDCDriver *ltdcp, ltdc_blendf_t bf) { - - osalSysLock(); - ltdcBgSetBlendingFactorsI(ltdcp, bf); - osalSysUnlock(); -} - -/** - * @brief Get background layer window specs. - * @details Gets the window specifications of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[out] windowp pointer to the window specifications - * - * @iclass - */ -void ltdcBgGetWindowI(LTDCDriver *ltdcp, ltdc_window_t *windowp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - osalDbgCheck(windowp != NULL); - (void)ltdcp; - - windowp->hstart = - (uint16_t)((LTDC_Layer1->WHPCR & LTDC_LxWHPCR_WHSTPOS) >> 0); - windowp->hstop = - (uint16_t)((LTDC_Layer1->WHPCR & LTDC_LxWHPCR_WHSPPOS) >> 16); - windowp->vstart = - (uint16_t)((LTDC_Layer1->WVPCR & LTDC_LxWVPCR_WVSTPOS) >> 0); - windowp->vstop = - (uint16_t)((LTDC_Layer1->WVPCR & LTDC_LxWVPCR_WVSPPOS) >> 16); -} - -/** - * @brief Get background layer window specs. - * @details Gets the window specifications of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[out] windowp pointer to the window specifications - * - * @api - */ -void ltdcBgGetWindow(LTDCDriver *ltdcp, ltdc_window_t *windowp) { - - osalSysLock(); - ltdcBgGetWindowI(ltdcp, windowp); - osalSysUnlock(); -} - -/** - * @brief Set background layer window specs. - * @details Sets the window specifications of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] windowp pointer to the window specifications - * - * @iclass - */ -void ltdcBgSetWindowI(LTDCDriver *ltdcp, const ltdc_window_t *windowp) { - - uint32_t start, stop; - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - osalDbgCheck(windowp != NULL); - (void)ltdcp; - - osalDbgAssert(windowp->hstop < ltdcp->config->screen_width, "bounds"); - osalDbgAssert(windowp->vstop < ltdcp->config->screen_height, "bounds"); - - /* Horizontal boundaries.*/ - start = (uint32_t)windowp->hstart + ltdcp->active_window.hstart; - stop = (uint32_t)windowp->hstop + ltdcp->active_window.hstart; - - osalDbgAssert(start >= ltdcp->active_window.hstart, "bounds"); - osalDbgAssert(stop <= ltdcp->active_window.hstop, "bounds"); - - LTDC_Layer1->WHPCR = (((start << 0) & LTDC_LxWHPCR_WHSTPOS) | - ((stop << 16) & LTDC_LxWHPCR_WHSPPOS)); - - /* Vertical boundaries.*/ - start = (uint32_t)windowp->vstart + ltdcp->active_window.vstart; - stop = (uint32_t)windowp->vstop + ltdcp->active_window.vstart; - - osalDbgAssert(start >= ltdcp->active_window.vstart, "bounds"); - osalDbgAssert(stop <= ltdcp->active_window.vstop, "bounds"); - - LTDC_Layer1->WVPCR = (((start << 0) & LTDC_LxWVPCR_WVSTPOS) | - ((stop << 16) & LTDC_LxWVPCR_WVSPPOS)); -} - -/** - * @brief Set background layer window specs. - * @details Sets the window specifications of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] windowp pointer to the window specifications - * - * @api - */ -void ltdcBgSetWindow(LTDCDriver *ltdcp, const ltdc_window_t *windowp) { - - osalSysLock(); - ltdcBgSetWindowI(ltdcp, windowp); - osalSysUnlock(); -} - -/** - * @brief Set background layer window as invalid. - * @details Sets the window specifications of the background layer (layer 1) - * so that the window is pixel sized at the screen origin. - * @note Useful before reconfiguring the frame specifications of the layer, - * to avoid errors. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @iclass - */ -void ltdcBgSetInvalidWindowI(LTDCDriver *ltdcp) { - - ltdcBgSetWindowI(ltdcp, <dc_invalid_window); -} - -/** - * @brief Set background layer window as invalid. - * @details Sets the window specifications of the background layer (layer 1) - * so that the window is pixel sized at the screen origin. - * @note Useful before reconfiguring the frame specifications of the layer, - * to avoid errors. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcBgSetInvalidWindow(LTDCDriver *ltdcp) { - - osalSysLock(); - ltdcBgSetWindowI(ltdcp, <dc_invalid_window); - osalSysUnlock(); -} - -/** - * @brief Get background layer frame buffer specs. - * @details Gets the frame buffer specifications of the background layer - * (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[out] framep pointer to the frame buffer specifications - * - * @iclass - */ -void ltdcBgGetFrameI(LTDCDriver *ltdcp, ltdc_frame_t *framep) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - osalDbgCheck(framep != NULL); - - framep->bufferp = (void *)(LTDC_Layer1->CFBAR & LTDC_LxCFBAR_CFBADD); - framep->pitch = (size_t)((LTDC_Layer1->CFBLR & LTDC_LxCFBLR_CFBP) >> 16); - framep->width = (uint16_t)(((LTDC_Layer1->CFBLR & LTDC_LxCFBLR_CFBLL) - 3) / - ltdcBytesPerPixel(ltdcBgGetPixelFormatI(ltdcp))); - framep->height = (uint16_t)(LTDC_Layer1->CFBLNR & LTDC_LxCFBLNR_CFBLNBR); -} - -/** - * @brief Get background layer frame buffer specs. - * @details Gets the frame buffer specifications of the background layer - * (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[out] framep pointer to the frame buffer specifications - * - * @api - */ -void ltdcBgGetFrame(LTDCDriver *ltdcp, ltdc_frame_t *framep) { - - osalSysLock(); - ltdcBgGetFrameI(ltdcp, framep); - osalSysUnlock(); -} - -/** - * @brief Set background layer frame buffer specs. - * @details Sets the frame buffer specifications of the background layer - * (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] framep pointer to the frame buffer specifications - * - * @iclass - */ -void ltdcBgSetFrameI(LTDCDriver *ltdcp, const ltdc_frame_t *framep) { - - size_t linesize; - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - osalDbgCheck(framep != NULL); - - ltdcBgSetPixelFormatI(ltdcp, framep->fmt); - - linesize = ltdcBytesPerPixel(framep->fmt) * framep->width; - - osalDbgAssert(framep->width <= ltdcp->config->screen_width, "bounds"); - osalDbgAssert(framep->height <= ltdcp->config->screen_height, "bounds"); - osalDbgAssert(linesize >= LTDC_MIN_FRAME_WIDTH_BYTES, "bounds"); - osalDbgAssert(linesize <= LTDC_MAX_FRAME_WIDTH_BYTES, "bounds"); - osalDbgAssert(framep->height >= LTDC_MIN_FRAME_HEIGHT_LINES, "bounds"); - osalDbgAssert(framep->height <= LTDC_MAX_FRAME_HEIGHT_LINES, "bounds"); - osalDbgAssert(framep->pitch >= linesize, "bounds"); - - LTDC_Layer1->CFBAR = (uint32_t)framep->bufferp & LTDC_LxCFBAR_CFBADD; - LTDC_Layer1->CFBLR = ((((uint32_t)framep->pitch << 16) & LTDC_LxCFBLR_CFBP) | - ((linesize + 3) & LTDC_LxCFBLR_CFBLL)); - LTDC_Layer1->CFBLNR = (uint32_t)framep->height & LTDC_LxCFBLNR_CFBLNBR; -} - -/** - * @brief Set background layer frame buffer specs. - * @details Sets the frame buffer specifications of the background layer - * (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] framep pointer to the frame buffer specifications - * - * @api - */ -void ltdcBgSetFrame(LTDCDriver *ltdcp, const ltdc_frame_t *framep) { - - osalSysLock(); - ltdcBgSetFrameI(ltdcp, framep); - osalSysUnlock(); -} - -/** - * @brief Get background layer frame buffer address. - * @details Gets the frame buffer address of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return frame buffer address - * - * @iclass - */ -void *ltdcBgGetFrameAddressI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (void *)LTDC_Layer1->CFBAR; -} - -/** - * @brief Get background layer frame buffer address. - * @details Gets the frame buffer address of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return frame buffer address - * - * @api - */ -void *ltdcBgGetFrameAddress(LTDCDriver *ltdcp) { - - void *bufferp; - osalSysLock(); - bufferp = ltdcBgGetFrameAddressI(ltdcp); - osalSysUnlock(); - return bufferp; -} - -/** - * @brief Set background layer frame buffer address. - * @details Sets the frame buffer address of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] bufferp frame buffer address - * - * @iclass - */ -void ltdcBgSetFrameAddressI(LTDCDriver *ltdcp, void *bufferp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer1->CFBAR = (uint32_t)bufferp; -} - -/** - * @brief Set background layer frame buffer address. - * @details Sets the frame buffer address of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] bufferp frame buffer address - * - * @api - */ -void ltdcBgSetFrameAddress(LTDCDriver *ltdcp, void *bufferp) { - - osalSysLock(); - ltdcBgSetFrameAddressI(ltdcp, bufferp); - osalSysUnlock(); -} - -/** - * @brief Get background layer specifications. - * @details Gets the background layer (layer 1) specifications at once. - * @note If palette specifications cannot be retrieved, they are set to - * @p NULL. This is not an error. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[out] cfgp pointer to the layer specifications - * - * @iclass - */ -void ltdcBgGetLayerI(LTDCDriver *ltdcp, ltdc_laycfg_t *cfgp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - osalDbgCheck(cfgp != NULL); - - ltdcBgGetFrameI(ltdcp, (ltdc_frame_t *)cfgp->frame); - ltdcBgGetWindowI(ltdcp, (ltdc_window_t *)cfgp->window); - cfgp->def_color = ltdcBgGetDefaultColorI(ltdcp); - cfgp->key_color = ltdcBgGetKeyingColorI(ltdcp); - cfgp->const_alpha = ltdcBgGetConstantAlphaI(ltdcp); - cfgp->blending = ltdcBgGetBlendingFactorsI(ltdcp); - - cfgp->pal_colors = NULL; - cfgp->pal_length = 0; - - cfgp->flags = ltdcBgGetEnableFlagsI(ltdcp); -} - -/** - * @brief Get background layer specifications. - * @details Gets the background layer (layer 1) specifications at once. - * @note If palette specifications cannot be retrieved, they are set to - * @p NULL. This is not an error. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[out] cfgp pointer to the layer specifications - * - * @api - */ -void ltdcBgGetLayer(LTDCDriver *ltdcp, ltdc_laycfg_t *cfgp) { - - osalSysLock(); - ltdcBgGetLayerI(ltdcp, cfgp); - osalSysUnlock(); -} - -/** - * @brief Set background layer specifications. - * @details Sets the background layer (layer 1) specifications at once. - * @note If the palette is unspecified, the layer palette is unmodified. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] cfgp pointer to the layer specifications - * - * @iclass - */ -void ltdcBgSetConfigI(LTDCDriver *ltdcp, const ltdc_laycfg_t *cfgp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - - if (cfgp == NULL) - cfgp = <dc_default_laycfg; - - osalDbgCheck((cfgp->pal_colors == NULL) == (cfgp->pal_length == 0)); - - ltdcBgSetFrameI(ltdcp, cfgp->frame); - ltdcBgSetWindowI(ltdcp, cfgp->window); - ltdcBgSetDefaultColorI(ltdcp, cfgp->def_color); - ltdcBgSetKeyingColorI(ltdcp, cfgp->key_color); - ltdcBgSetConstantAlphaI(ltdcp, cfgp->const_alpha); - ltdcBgSetBlendingFactorsI(ltdcp, cfgp->blending); - - if (cfgp->pal_length > 0) - ltdcBgSetPaletteI(ltdcp, cfgp->pal_colors, cfgp->pal_length); - - ltdcBgSetEnableFlagsI(ltdcp, cfgp->flags); -} - -/** - * @brief Set background layer specifications. - * @details Sets the background layer (layer 1) specifications at once. - * @note If the palette is unspecified, the layer palette is unmodified. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] cfgp pointer to the layer specifications - * - * @api - */ -void ltdcBgSetConfig(LTDCDriver *ltdcp, const ltdc_laycfg_t *cfgp) { - - osalSysLock(); - ltdcBgSetConfigI(ltdcp, cfgp); - osalSysUnlock(); -} - -/** @} */ - -/** - * @name LTDC foreground layer (layer 2) methods - * @{ - */ - -/** - * @brief Get foreground layer enabled flags. - * @details Returns all the flags of the LTDC_LEF_* group at once. - * Targeting the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled flags - * - * @iclass - */ -ltdc_flags_t ltdcFgGetEnableFlagsI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return LTDC_Layer2->CR & LTDC_LEF_MASK; -} - -/** - * @brief Get foreground layer enabled flags. - * @details Returns all the flags of the LTDC_LEF_* group at once. - * Targeting the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled flags - * - * @api - */ -ltdc_flags_t ltdcFgGetEnableFlags(LTDCDriver *ltdcp) { - - ltdc_flags_t flags; - osalSysLock(); - flags = ltdcFgGetEnableFlagsI(ltdcp); - osalSysUnlock(); - return flags; -} - -/** - * @brief Set foreground layer enabled flags. - * @details Sets all the flags of the LTDC_LEF_* group at once. - * Targeting the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] flags enabled flags - * - * @iclass - */ -void ltdcFgSetEnableFlagsI(LTDCDriver *ltdcp, ltdc_flags_t flags) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer2->CR = ((LTDC_Layer2->CR & ~LTDC_LEF_MASK) | - ((uint32_t)flags & LTDC_LEF_MASK)); -} - -/** - * @brief Set foreground layer enabled flags. - * @details Sets all the flags of the LTDC_LEF_* group at once. - * Targeting the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] flags enabled flags - * - * @api - */ -void ltdcFgSetEnableFlags(LTDCDriver *ltdcp, ltdc_flags_t flags) { - - osalSysLock(); - ltdcFgSetEnableFlagsI(ltdcp, flags); - osalSysUnlock(); -} - -/** - * @brief Foreground layer enabled. - * @details Tells whether the foreground layer (layer 2) is enabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled - * - * @iclass - */ -bool ltdcFgIsEnabledI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (LTDC_Layer2->CR & ~LTDC_LxCR_LEN) != 0; -} - -/** - * @brief Foreground layer enabled. - * @details Tells whether the foreground layer (layer 2) is enabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled - * - * @api - */ -bool ltdcFgIsEnabled(LTDCDriver *ltdcp) { - - bool enabled; - osalSysLock(); - enabled = ltdcFgIsEnabledI(ltdcp); - osalSysUnlock(); - return enabled; -} - -/** - * @brief Foreground layer enable. - * @details Enables the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @iclass - */ -void ltdcFgEnableI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer2->CR |= LTDC_LxCR_LEN; -} - -/** - * @brief Foreground layer enable. - * @details Enables the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcFgEnable(LTDCDriver *ltdcp) { - - osalSysLock(); - ltdcFgEnableI(ltdcp); - osalSysUnlock(); -} - -/** - * @brief Foreground layer disable. - * @details Disables the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @iclass - */ -void ltdcFgDisableI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer2->CR &= ~LTDC_LxCR_LEN; -} - -/** - * @brief Foreground layer disable. - * @details Disables the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcFgDisable(LTDCDriver *ltdcp) { - - osalSysLock(); - ltdcFgDisableI(ltdcp); - osalSysUnlock(); -} - -/** - * @brief Foreground layer palette enabled. - * @details Tells whether the foreground layer (layer 2) palette (color lookup - * table) is enabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled - * - * @iclass - */ -bool ltdcFgIsPaletteEnabledI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (LTDC_Layer2->CR & ~LTDC_LxCR_CLUTEN) != 0; -} - -/** - * @brief Foreground layer palette enabled. - * @details Tells whether the foreground layer (layer 2) palette (color lookup - * table) is enabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled - * - * @api - */ -bool ltdcFgIsPaletteEnabled(LTDCDriver *ltdcp) { - - bool enabled; - osalSysLock(); - enabled = ltdcFgIsPaletteEnabledI(ltdcp); - osalSysUnlock(); - return enabled; -} - -/** - * @brief Enable foreground layer palette. - * @details Enables the palette (color lookup table) of the foreground layer - * (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @iclass - */ -void ltdcFgEnablePaletteI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer2->CR |= LTDC_LxCR_CLUTEN; -} - -/** - * @brief Enable foreground layer palette. - * @details Enables the palette (color lookup table) of the foreground layer - * (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcFgEnablePalette(LTDCDriver *ltdcp) { - - osalSysLock(); - ltdcFgEnablePaletteI(ltdcp); - osalSysUnlock(); -} - -/** - * @brief Disable foreground layer palette. - * @details Disables the palette (color lookup table) of the foreground layer - * (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @iclass - */ -void ltdcFgDisablePaletteI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer2->CR &= ~LTDC_LxCR_CLUTEN; -} - -/** - * @brief Disable foreground layer palette. - * @details Disables the palette (color lookup table) of the foreground layer - * (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcFgDisablePalette(LTDCDriver *ltdcp) { - - osalSysLock(); - ltdcFgDisablePaletteI(ltdcp); - osalSysUnlock(); -} - -/** - * @brief Set foreground layer palette color. - * @details Sets the color of a palette (color lookup table) slot to the - * foreground layer (layer 2). - * @pre The layer must be disabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] slot palette slot - * @param[in] c color, RGB-888 - * - * @iclass - */ -void ltdcFgSetPaletteColorI(LTDCDriver *ltdcp, uint8_t slot, ltdc_color_t c) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - osalDbgAssert(!ltdcFgIsEnabledI(ltdcp), "invalid state"); - (void)ltdcp; - - LTDC_Layer2->CLUTWR = (((uint32_t)slot << 24) | (c & 0x00FFFFFF)); -} - -/** - * @brief Set foreground layer palette color. - * @details Sets the color of a palette (color lookup table) slot to the - * foreground layer (layer 2). - * @pre The layer must be disabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] slot palette slot - * @param[in] c color, RGB-888 - * - * @api - */ -void ltdcFgSetPaletteColor(LTDCDriver *ltdcp, uint8_t slot, ltdc_color_t c) { - - osalSysLock(); - ltdcFgSetPaletteColorI(ltdcp, slot, c); - osalSysUnlock(); -} - -/** - * @brief Set foreground layer palette. - * @details Sets the entire palette color (color lookup table) slot. - * @pre The layer must be disabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] colors array of palette colors, RGB-888 - * @param[in] length number of palette colors - * - * @iclass - */ -void ltdcFgSetPaletteI(LTDCDriver *ltdcp, const ltdc_color_t colors[], - uint16_t length) { - - uint16_t i; - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - osalDbgCheck((colors == NULL) == (length == 0)); - osalDbgAssert(length <= LTDC_MAX_PALETTE_LENGTH, "bounds"); - osalDbgAssert(!ltdcFgIsEnabledI(ltdcp), "invalid state"); - (void)ltdcp; - - for (i = 0; i < length; ++i) - LTDC_Layer2->CLUTWR = (((uint32_t)i << 24) | (colors[i] & 0x00FFFFFF)); -} - -/** - * @brief Set foreground layer palette. - * @details Sets the entire palette color (color lookup table) slot. - * @pre The layer must be disabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] colors array of palette colors, RGB-888 - * @param[in] length number of palette colors - * - * @api - */ -void ltdcFgSetPalette(LTDCDriver *ltdcp, const ltdc_color_t colors[], - uint16_t length) { - - osalSysLock(); - ltdcFgSetPaletteI(ltdcp, colors, length); - osalSysUnlock(); -} - -/** - * @brief Get foreground layer pixel format. - * @details Gets the pixel format of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return pixel format - * - * @iclass - */ -ltdc_pixfmt_t ltdcFgGetPixelFormatI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (ltdc_pixfmt_t)(LTDC_Layer2->PFCR & LTDC_LxPFCR_PF); -} - -/** - * @brief Get foreground layer pixel format. - * @details Gets the pixel format of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return pixel format - * - * @api - */ -ltdc_pixfmt_t ltdcFgGetPixelFormat(LTDCDriver *ltdcp) { - - ltdc_pixfmt_t fmt; - osalSysLock(); - fmt = ltdcFgGetPixelFormatI(ltdcp); - osalSysUnlock(); - return fmt; -} - -/** - * @brief Set foreground layer pixel format. - * @details Sets the pixel format of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] fmt pixel format - * - * @iclass - */ -void ltdcFgSetPixelFormatI(LTDCDriver *ltdcp, ltdc_pixfmt_t fmt) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - osalDbgAssert(fmt >= LTDC_MIN_PIXFMT_ID, "bounds"); - osalDbgAssert(fmt <= LTDC_MAX_PIXFMT_ID, "bounds"); - (void)ltdcp; - - LTDC_Layer2->PFCR = ((LTDC_Layer2->PFCR & ~LTDC_LxPFCR_PF) | - ((uint32_t)fmt & LTDC_LxPFCR_PF)); -} - -/** - * @brief Set foreground layer pixel format. - * @details Sets the pixel format of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] fmt pixel format - * - * @api - */ -void ltdcFgSetPixelFormat(LTDCDriver *ltdcp, ltdc_pixfmt_t fmt) { - - osalSysLock(); - ltdcFgSetPixelFormatI(ltdcp, fmt); - osalSysUnlock(); -} - -/** - * @brief Foreground layer color keying enabled. - * @details Tells whether the foreground layer (layer 2) has color keying - * enabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled - * - * @iclass - */ -bool ltdcFgIsKeyingEnabledI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (LTDC_Layer2->CR & ~LTDC_LxCR_COLKEN) != 0; -} - -/** - * @brief Foreground layer color keying enabled. - * @details Tells whether the foreground layer (layer 2) has color keying - * enabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled - * - * @api - */ -bool ltdcFgIsKeyingEnabled(LTDCDriver *ltdcp) { - - bool enabled; - osalSysLock(); - enabled = ltdcFgIsKeyingEnabledI(ltdcp); - osalSysUnlock(); - return enabled; -} - -/** - * @brief Enable foreground layer color keying. - * @details Enables color keying capabilities of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @iclass - */ -void ltdcFgEnableKeyingI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer2->CR |= LTDC_LxCR_COLKEN; -} - -/** - * @brief Enable foreground layer color keying. - * @details Enables color keying capabilities of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcFgEnableKeying(LTDCDriver *ltdcp) { - - osalSysLock(); - ltdcFgEnableKeyingI(ltdcp); - osalSysUnlock(); -} - -/** - * @brief Disable foreground layer color keying. - * @details Disables color keying capabilities of the foreground layer (layer - * 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @iclass - */ -void ltdcFgDisableKeyingI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer2->CR &= ~LTDC_LxCR_COLKEN; -} - -/** - * @brief Disable foreground layer color keying. - * @details Disables color keying capabilities of the foreground layer (layer - * 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcFgDisableKeying(LTDCDriver *ltdcp) { - - osalSysLock(); - ltdcFgDisableKeyingI(ltdcp); - osalSysUnlock(); -} - -/** - * @brief Get foreground layer color key. - * @details Gets the color key of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return color key, RGB-888 - * - * @iclass - */ -ltdc_color_t ltdcFgGetKeyingColorI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (ltdc_color_t)(LTDC_Layer2->CKCR & 0x00FFFFFF); -} - -/** - * @brief Get foreground layer color key. - * @details Gets the color key of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return color key, RGB-888 - * - * @api - */ -ltdc_color_t ltdcFgGetKeyingColor(LTDCDriver *ltdcp) { - - ltdc_color_t color; - osalSysLock(); - color = ltdcFgGetKeyingColorI(ltdcp); - osalSysUnlock(); - return color; -} - -/** - * @brief Set foreground layer color key. - * @details Sets the color key of the foreground layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] c color key, RGB-888 - * - * @iclass - */ -void ltdcFgSetKeyingColorI(LTDCDriver *ltdcp, ltdc_color_t c) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer2->CKCR = ((LTDC_Layer2->CKCR & ~0x00FFFFFF) | - ((uint32_t)c & 0x00FFFFFF)); -} - -/** - * @brief Set foreground layer color key. - * @details Sets the color key of the foreground layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] c color key, RGB-888 - * - * @api - */ -void ltdcFgSetKeyingColor(LTDCDriver *ltdcp, ltdc_color_t c) { - - osalSysLock(); - ltdcFgSetKeyingColorI(ltdcp, c); - osalSysUnlock(); -} - -/** - * @brief Get foreground layer constant alpha. - * @details Gets the constant alpha component of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return constant alpha component, A-8 - * - * @iclass - */ -uint8_t ltdcFgGetConstantAlphaI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (uint8_t)(LTDC_Layer2->CACR & LTDC_LxCACR_CONSTA); -} - -/** - * @brief Get foreground layer constant alpha. - * @details Gets the constant alpha component of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return constant alpha component, A-8 - * - * @api - */ -uint8_t ltdcFgGetConstantAlpha(LTDCDriver *ltdcp) { - - uint8_t a; - osalSysLock(); - a = ltdcFgGetConstantAlphaI(ltdcp); - osalSysUnlock(); - return a; -} - -/** - * @brief Set foreground layer constant alpha. - * @details Sets the constant alpha component of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] a constant alpha component, A-8 - * - * @iclass - */ -void ltdcFgSetConstantAlphaI(LTDCDriver *ltdcp, uint8_t a) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer2->CACR = ((LTDC_Layer2->CACR & ~LTDC_LxCACR_CONSTA) | - ((uint32_t)a & LTDC_LxCACR_CONSTA)); -} - -/** - * @brief Set foreground layer constant alpha. - * @details Sets the constant alpha component of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] a constant alpha component, A-8 - * - * @api - */ -void ltdcFgSetConstantAlpha(LTDCDriver *ltdcp, uint8_t a) { - - osalSysLock(); - ltdcFgSetConstantAlphaI(ltdcp, a); - osalSysUnlock(); -} - -/** - * @brief Get foreground layer default color. - * @details Gets the default color of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return default color, RGB-888 - * - * @iclass - */ -ltdc_color_t ltdcFgGetDefaultColorI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (ltdc_color_t)LTDC_Layer2->DCCR; -} - -/** - * @brief Get foreground layer default color. - * @details Gets the default color of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return default color, RGB-888 - * - * @api - */ -ltdc_color_t ltdcFgGetDefaultColor(LTDCDriver *ltdcp) { - - ltdc_color_t color; - osalSysLock(); - color = ltdcFgGetDefaultColorI(ltdcp); - osalSysUnlock(); - return color; -} - -/** - * @brief Set foreground layer default color. - * @details Sets the default color of the foreground layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] c default color, RGB-888 - * - * @iclass - */ -void ltdcFgSetDefaultColorI(LTDCDriver *ltdcp, ltdc_color_t c) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer2->DCCR = (uint32_t)c; -} - -/** - * @brief Set foreground layer default color. - * @details Sets the default color of the foreground layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] c default color, RGB-888 - * - * @api - */ -void ltdcFgSetDefaultColor(LTDCDriver *ltdcp, ltdc_color_t c) { - - osalSysLock(); - ltdcFgSetDefaultColorI(ltdcp, c); - osalSysUnlock(); -} - -/** - * @brief Get foreground layer blending factors. - * @details Gets the blending factors of the foreground layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return blending factors - * - * @iclass - */ -ltdc_blendf_t ltdcFgGetBlendingFactorsI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (ltdc_blendf_t)(LTDC_Layer2->BFCR & LTDC_LxBFCR_BF); -} - -/** - * @brief Get foreground layer blending factors. - * @details Gets the blending factors of the foreground layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return blending factors - * - * @api - */ -ltdc_blendf_t ltdcFgGetBlendingFactors(LTDCDriver *ltdcp) { - - ltdc_blendf_t bf; - osalSysLock(); - bf = ltdcFgGetBlendingFactorsI(ltdcp); - osalSysUnlock(); - return bf; -} - -/** - * @brief Set foreground layer blending factors. - * @details Sets the blending factors of the foreground layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] factors blending factors - * - * @iclass - */ -void ltdcFgSetBlendingFactorsI(LTDCDriver *ltdcp, ltdc_blendf_t bf) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer2->BFCR = ((LTDC_Layer2->BFCR & ~LTDC_LxBFCR_BF) | - ((uint32_t)bf & LTDC_LxBFCR_BF)); -} - -/** - * @brief Set foreground layer blending factors. - * @details Sets the blending factors of the foreground layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] factors blending factors - * - * @api - */ -void ltdcFgSetBlendingFactors(LTDCDriver *ltdcp, ltdc_blendf_t bf) { - - osalSysLock(); - ltdcFgSetBlendingFactorsI(ltdcp, bf); - osalSysUnlock(); -} - -/** - * @brief Get foreground layer window specs. - * @details Gets the window specifications of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[out] windowp pointer to the window specifications - * - * @iclass - */ -void ltdcFgGetWindowI(LTDCDriver *ltdcp, ltdc_window_t *windowp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - osalDbgCheck(windowp != NULL); - (void)ltdcp; - - windowp->hstart = - (uint16_t)((LTDC_Layer2->WHPCR & LTDC_LxWHPCR_WHSTPOS) >> 0); - windowp->hstop = - (uint16_t)((LTDC_Layer2->WHPCR & LTDC_LxWHPCR_WHSPPOS) >> 16); - windowp->vstart = - (uint16_t)((LTDC_Layer2->WVPCR & LTDC_LxWVPCR_WVSTPOS) >> 0); - windowp->vstop = - (uint16_t)((LTDC_Layer2->WVPCR & LTDC_LxWVPCR_WVSPPOS) >> 16); -} - -/** - * @brief Get foreground layer window specs. - * @details Gets the window specifications of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[out] windowp pointer to the window specifications - * - * @api - */ -void ltdcFgGetWindow(LTDCDriver *ltdcp, ltdc_window_t *windowp) { - - osalSysLock(); - ltdcFgGetWindowI(ltdcp, windowp); - osalSysUnlock(); -} - -/** - * @brief Set foreground layer window specs. - * @details Sets the window specifications of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] windowp pointer to the window specifications - * - * @iclass - */ -void ltdcFgSetWindowI(LTDCDriver *ltdcp, const ltdc_window_t *windowp) { - - uint32_t start, stop; - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - osalDbgCheck(windowp != NULL); - (void)ltdcp; - - osalDbgAssert(windowp->hstop < ltdcp->config->screen_width, "bounds"); - osalDbgAssert(windowp->vstop < ltdcp->config->screen_height, "bounds"); - - /* Horizontal boundaries.*/ - start = (uint32_t)windowp->hstart + ltdcp->active_window.hstart; - stop = (uint32_t)windowp->hstop + ltdcp->active_window.hstart; - - osalDbgAssert(start >= ltdcp->active_window.hstart, "bounds"); - osalDbgAssert(stop <= ltdcp->active_window.hstop, "bounds"); - - LTDC_Layer2->WHPCR = (((start << 0) & LTDC_LxWHPCR_WHSTPOS) | - ((stop << 16) & LTDC_LxWHPCR_WHSPPOS)); - - /* Vertical boundaries.*/ - start = (uint32_t)windowp->vstart + ltdcp->active_window.vstart; - stop = (uint32_t)windowp->vstop + ltdcp->active_window.vstart; - - osalDbgAssert(start >= ltdcp->active_window.vstart, "bounds"); - osalDbgAssert(stop <= ltdcp->active_window.vstop, "bounds"); - - LTDC_Layer2->WVPCR = (((start << 0) & LTDC_LxWVPCR_WVSTPOS) | - ((stop << 16) & LTDC_LxWVPCR_WVSPPOS)); -} - -/** - * @brief Set foreground layer window specs. - * @details Sets the window specifications of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] windowp pointer to the window specifications - * - * @api - */ -void ltdcFgSetWindow(LTDCDriver *ltdcp, const ltdc_window_t *windowp) { - - osalSysLock(); - ltdcFgSetWindowI(ltdcp, windowp); - osalSysUnlock(); -} - -/** - * @brief Set foreground layer window as invalid. - * @details Sets the window specifications of the foreground layer (layer 2) - * so that the window is pixel sized at the screen origin. - * @note Useful before reconfiguring the frame specifications of the layer, - * to avoid errors. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @iclass - */ -void ltdcFgSetInvalidWindowI(LTDCDriver *ltdcp) { - - ltdcFgSetWindowI(ltdcp, <dc_invalid_window); -} - -/** - * @brief Set foreground layer window as invalid. - * @details Sets the window specifications of the foreground layer (layer 2) - * so that the window is pixel sized at the screen origin. - * @note Useful before reconfiguring the frame specifications of the layer, - * to avoid errors. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcFgSetInvalidWindow(LTDCDriver *ltdcp) { - - osalSysLock(); - ltdcFgSetWindowI(ltdcp, <dc_invalid_window); - osalSysUnlock(); -} - -/** - * @brief Get foreground layer frame buffer specs. - * @details Gets the frame buffer specifications of the foreground layer - * (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[out] framep pointer to the frame buffer specifications - * - * @iclass - */ -void ltdcFgGetFrameI(LTDCDriver *ltdcp, ltdc_frame_t *framep) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - osalDbgCheck(framep != NULL); - - framep->bufferp = (void *)(LTDC_Layer2->CFBAR & LTDC_LxCFBAR_CFBADD); - framep->pitch = (size_t)((LTDC_Layer2->CFBLR & LTDC_LxCFBLR_CFBP) >> 16); - framep->width = (uint16_t)(((LTDC_Layer2->CFBLR & LTDC_LxCFBLR_CFBLL) - 3) / - ltdcBytesPerPixel(ltdcFgGetPixelFormatI(ltdcp))); - framep->height = (uint16_t)(LTDC_Layer2->CFBLNR & LTDC_LxCFBLNR_CFBLNBR); -} - -/** - * @brief Get foreground layer frame buffer specs. - * @details Gets the frame buffer specifications of the foreground layer - * (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[out] framep pointer to the frame buffer specifications - * - * @api - */ -void ltdcFgGetFrame(LTDCDriver *ltdcp, ltdc_frame_t *framep) { - - osalSysLock(); - ltdcFgGetFrameI(ltdcp, framep); - osalSysUnlock(); -} - -/** - * @brief Set foreground layer frame buffer specs. - * @details Sets the frame buffer specifications of the foreground layer - * (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] framep pointer to the frame buffer specifications - * - * @iclass - */ -void ltdcFgSetFrameI(LTDCDriver *ltdcp, const ltdc_frame_t *framep) { - - size_t linesize; - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - osalDbgCheck(framep != NULL); - - ltdcFgSetPixelFormatI(ltdcp, framep->fmt); - - linesize = ltdcBytesPerPixel(framep->fmt) * framep->width; - - osalDbgAssert(framep->width <= ltdcp->config->screen_width, "bounds"); - osalDbgAssert(framep->height <= ltdcp->config->screen_height, "bounds"); - osalDbgAssert(linesize >= LTDC_MIN_FRAME_WIDTH_BYTES, "bounds"); - osalDbgAssert(linesize <= LTDC_MAX_FRAME_WIDTH_BYTES, "bounds"); - osalDbgAssert(framep->height >= LTDC_MIN_FRAME_HEIGHT_LINES, "bounds"); - osalDbgAssert(framep->height <= LTDC_MAX_FRAME_HEIGHT_LINES, "bounds"); - osalDbgAssert(framep->pitch >= linesize, "bounds"); - - LTDC_Layer2->CFBAR = (uint32_t)framep->bufferp & LTDC_LxCFBAR_CFBADD; - LTDC_Layer2->CFBLR = ((((uint32_t)framep->pitch << 16) & LTDC_LxCFBLR_CFBP) | - ((linesize + 3) & LTDC_LxCFBLR_CFBLL)); - LTDC_Layer2->CFBLNR = (uint32_t)framep->height & LTDC_LxCFBLNR_CFBLNBR; -} - -/** - * @brief Set foreground layer frame buffer specs. - * @details Sets the frame buffer specifications of the foreground layer - * (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] framep pointer to the frame buffer specifications - * - * @api - */ -void ltdcFgSetFrame(LTDCDriver *ltdcp, const ltdc_frame_t *framep) { - - osalSysLock(); - ltdcFgSetFrameI(ltdcp, framep); - osalSysUnlock(); -} - -/** - * @brief Get foreground layer frame buffer address. - * @details Gets the frame buffer address of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return frame buffer address - * - * @iclass - */ -void *ltdcFgGetFrameAddressI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (void *)LTDC_Layer2->CFBAR; -} - -/** - * @brief Get foreground layer frame buffer address. - * @details Gets the frame buffer address of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return frame buffer address - * - * @api - */ -void *ltdcFgGetFrameAddress(LTDCDriver *ltdcp) { - - void *bufferp; - osalSysLock(); - bufferp = ltdcFgGetFrameAddressI(ltdcp); - osalSysUnlock(); - return bufferp; -} - -/** - * @brief Set foreground layer frame buffer address. - * @details Sets the frame buffer address of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] bufferp frame buffer address - * - * @iclass - */ -void ltdcFgSetFrameAddressI(LTDCDriver *ltdcp, void *bufferp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer2->CFBAR = (uint32_t)bufferp; -} - -/** - * @brief Set foreground layer frame buffer address. - * @details Sets the frame buffer address of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] bufferp frame buffer address - * - * @api - */ -void ltdcFgSetFrameAddress(LTDCDriver *ltdcp, void *bufferp) { - - osalSysLock(); - ltdcFgSetFrameAddressI(ltdcp, bufferp); - osalSysUnlock(); -} - -/** - * @brief Get foreground layer specifications. - * @details Gets the foreground layer (layer 2) specifications at once. - * @note If palette specifications cannot be retrieved, they are set to - * @p NULL. This is not an error. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[out] cfgp pointer to the layer specifications - * - * @iclass - */ -void ltdcFgGetLayerI(LTDCDriver *ltdcp, ltdc_laycfg_t *cfgp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - osalDbgCheck(cfgp != NULL); - - ltdcFgGetFrameI(ltdcp, (ltdc_frame_t *)cfgp->frame); - ltdcFgGetWindowI(ltdcp, (ltdc_window_t *)cfgp->window); - cfgp->def_color = ltdcFgGetDefaultColorI(ltdcp); - cfgp->key_color = ltdcFgGetKeyingColorI(ltdcp); - cfgp->const_alpha = ltdcFgGetConstantAlphaI(ltdcp); - cfgp->blending = ltdcFgGetBlendingFactorsI(ltdcp); - - cfgp->pal_colors = NULL; - cfgp->pal_length = 0; - - cfgp->flags = ltdcFgGetEnableFlagsI(ltdcp); -} - -/** - * @brief Get foreground layer specifications. - * @details Gets the foreground layer (layer 2) specifications at once. - * @note If palette specifications cannot be retrieved, they are set to - * @p NULL. This is not an error. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[out] cfgp pointer to the layer specifications - * - * @api - */ -void ltdcFgGetLayer(LTDCDriver *ltdcp, ltdc_laycfg_t *cfgp) { - - osalSysLock(); - ltdcFgGetLayerI(ltdcp, cfgp); - osalSysUnlock(); -} - -/** - * @brief Set foreground layer specifications. - * @details Sets the foreground layer (layer 2) specifications at once. - * @note If the palette is unspecified, the layer palette is unmodified. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] cfgp pointer to the layer specifications - * - * @iclass - */ -void ltdcFgSetConfigI(LTDCDriver *ltdcp, const ltdc_laycfg_t *cfgp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - - if (cfgp == NULL) - cfgp = <dc_default_laycfg; - - osalDbgCheck((cfgp->pal_colors == NULL) == (cfgp->pal_length == 0)); - - ltdcFgSetFrameI(ltdcp, cfgp->frame); - ltdcFgSetWindowI(ltdcp, cfgp->window); - ltdcFgSetDefaultColorI(ltdcp, cfgp->def_color); - ltdcFgSetKeyingColorI(ltdcp, cfgp->key_color); - ltdcFgSetConstantAlphaI(ltdcp, cfgp->const_alpha); - ltdcFgSetBlendingFactorsI(ltdcp, cfgp->blending); - - if (cfgp->pal_length > 0) - ltdcFgSetPaletteI(ltdcp, cfgp->pal_colors, cfgp->pal_length); - - ltdcFgSetEnableFlagsI(ltdcp, cfgp->flags); -} - -/** - * @brief Set foreground layer specifications. - * @details Sets the foreground layer (layer 2) specifications at once. - * @note If the palette is unspecified, the layer palette is unmodified. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] cfgp pointer to the layer specifications - * - * @api - */ -void ltdcFgSetConfig(LTDCDriver *ltdcp, const ltdc_laycfg_t *cfgp) { - - osalSysLock(); - ltdcFgSetConfigI(ltdcp, cfgp); - osalSysUnlock(); -} - -/** @} */ - -/** - * @name LTDC helper functions - */ - -/** - * @brief Compute bits per pixel. - * @details Computes the bits per pixel for the specified pixel format. - * - * @param[in] fmt pixel format - * - * @retuen bits per pixel - * - * @api - */ -size_t ltdcBitsPerPixel(ltdc_pixfmt_t fmt) { - - osalDbgAssert(fmt < LTDC_MAX_PIXFMT_ID, "invalid format"); - - return (size_t)ltdc_bpp[(unsigned)fmt]; -} - -#if (TRUE == LTDC_USE_SOFTWARE_CONVERSIONS) || defined(__DOXYGEN__) - -/** - * @brief Convert from ARGB-8888. - * @details Converts an ARGB-8888 color to the specified pixel format. - * - * @param[in] c color, ARGB-8888 - * @param[in] fmt target pixel format - * - * @return raw color value for the target pixel format, left - * padded with zeros. - * - * @api - */ -ltdc_color_t ltdcFromARGB8888(ltdc_color_t c, ltdc_pixfmt_t fmt) { - - switch (fmt) { - case LTDC_FMT_ARGB8888: { - return c; - } - case LTDC_FMT_RGB888: { - return (c & 0x00FFFFFF); - } - case LTDC_FMT_RGB565: { - return (((c & 0x000000F8) >> ( 8 - 5)) | - ((c & 0x0000FC00) >> (16 - 11)) | - ((c & 0x00F80000) >> (24 - 16))); - } - case LTDC_FMT_ARGB1555: { - return (((c & 0x000000F8) >> ( 8 - 5)) | - ((c & 0x0000F800) >> (16 - 10)) | - ((c & 0x00F80000) >> (24 - 15)) | - ((c & 0x80000000) >> (32 - 16))); - } - case LTDC_FMT_ARGB4444: { - return (((c & 0x000000F0) >> ( 8 - 4)) | - ((c & 0x0000F000) >> (16 - 8)) | - ((c & 0x00F00000) >> (24 - 12)) | - ((c & 0xF0000000) >> (32 - 16))); - } - case LTDC_FMT_L8: { - return (c & 0x000000FF); - } - case LTDC_FMT_AL44: { - return (((c & 0x000000F0) >> ( 8 - 4)) | - ((c & 0xF0000000) >> (32 - 8))); - } - case LTDC_FMT_AL88: { - return (((c & 0x000000FF) >> ( 8 - 8)) | - ((c & 0xFF000000) >> (32 - 16))); - } - default: - osalDbgAssert(false, "invalid format"); - return 0; - } -} - -/** - * @brief Convert to ARGB-8888. - * @details Converts color of the specified pixel format to an ARGB-8888 color. - * - * @param[in] c color for the source pixel format, left padded with - * zeros. - * @param[in] fmt source pixel format - * - * @return color in ARGB-8888 format - * - * @api - */ -ltdc_color_t ltdcToARGB8888(ltdc_color_t c, ltdc_pixfmt_t fmt) { - - switch (fmt) { - case LTDC_FMT_ARGB8888: { - return c; - } - case LTDC_FMT_RGB888: { - return ((c & 0x00FFFFFF) | 0xFF000000); - } - case LTDC_FMT_RGB565: { - register ltdc_color_t output = 0xFF000000; - if (c & 0x001F) output |= (((c & 0x001F) << ( 8 - 5)) | 0x00000007); - if (c & 0x07E0) output |= (((c & 0x07E0) << (16 - 11)) | 0x00000300); - if (c & 0xF800) output |= (((c & 0xF800) << (24 - 16)) | 0x00070000); - return output; - } - case LTDC_FMT_ARGB1555: { - register ltdc_color_t output = 0x00000000; - if (c & 0x001F) output |= (((c & 0x001F) << ( 8 - 5)) | 0x00000007); - if (c & 0x03E0) output |= (((c & 0x03E0) << (16 - 10)) | 0x00000700); - if (c & 0x7C00) output |= (((c & 0x7C00) << (24 - 15)) | 0x00070000); - if (c & 0x8000) output |= 0xFF000000; - return output; - } - case LTDC_FMT_ARGB4444: { - register ltdc_color_t output = 0x00000000; - if (c & 0x000F) output |= (((c & 0x000F) << ( 8 - 4)) | 0x0000000F); - if (c & 0x00F0) output |= (((c & 0x00F0) << (16 - 8)) | 0x00000F00); - if (c & 0x0F00) output |= (((c & 0x0F00) << (24 - 12)) | 0x000F0000); - if (c & 0xF000) output |= (((c & 0xF000) << (32 - 16)) | 0x0F000000); - return output; - } - case LTDC_FMT_L8: { - return ((c & 0xFF) | 0xFF000000); - } - case LTDC_FMT_AL44: { - register ltdc_color_t output = 0x00000000; - if (c & 0x0F) output |= (((c & 0x0F) << ( 8 - 4)) | 0x0000000F); - if (c & 0xF0) output |= (((c & 0xF0) << (32 - 8)) | 0x0F000000); - return output; - } - case LTDC_FMT_AL88: { - return (((c & 0x00FF) << ( 8 - 8)) | - ((c & 0xFF00) << (32 - 16))); - } - default: - osalDbgAssert(false, "invalid format"); - return 0; - } -} - -#endif /* LTDC_USE_SOFTWARE_CONVERSIONS */ - -/** @} */ - -/** @} */ - -#endif /* STM32_LTDC_USE_LTDC */ diff --git a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.h b/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.h deleted file mode 100644 index 5db89e2fe6..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.h +++ /dev/null @@ -1,736 +0,0 @@ -/* - Copyright (C) 2013-2015 Andrea Zoppi - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_stm32_ltdc.h - * @brief LCD-TFT Controller Driver. - * - * @addtogroup ltdc - * @{ - */ - -#ifndef HAL_STM32_LTDC_H_ -#define HAL_STM32_LTDC_H_ - -/** - * @brief Using the LTDC driver. - */ -#if !defined(STM32_LTDC_USE_LTDC) || defined(__DOXYGEN__) -#define STM32_LTDC_USE_LTDC (FALSE) -#endif - -#if (TRUE == STM32_LTDC_USE_LTDC) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name LTDC enable flags - * @{ - */ -#define LTDC_EF_ENABLE (1 << 0) /**< LTDC enabled.*/ -#define LTDC_EF_DITHER (1 << 16) /**< Dithering enabled.*/ -#define LTDC_EF_PIXCLK_INVERT (1 << 28) /**< Inverted pixel clock.*/ -#define LTDC_EF_DATAEN_HIGH (1 << 29) /**< Active-high data enable.*/ -#define LTDC_EF_VSYNC_HIGH (1 << 30) /**< Active-high vsync.*/ -#define LTDC_EF_HSYNC_HIGH (1 << 31) /**< Active-high hsync.*/ - -#define LTDC_EF_MASK \ - (LTDC_EF_ENABLE | LTDC_EF_DITHER | LTDC_EF_PIXCLK_INVERT | \ - LTDC_EF_DATAEN_HIGH | LTDC_EF_VSYNC_HIGH | LTDC_EF_HSYNC_HIGH) -/** @} */ - -/** - * @name LTDC layer enable flags - * @{ - */ -#define LTDC_LEF_ENABLE (1 << 0) /**< Layer enabled*/ -#define LTDC_LEF_KEYING (1 << 1) /**< Color keying enabled.*/ -#define LTDC_LEF_PALETTE (1 << 4) /**< Palette enabled.*/ - -#define LTDC_LEF_MASK \ - (LTDC_LEF_ENABLE | LTDC_LEF_KEYING | LTDC_LEF_PALETTE) -/** @} */ - -/** - * @name LTDC pixel formats - * @{ - */ -#define LTDC_FMT_ARGB8888 (0) /**< ARGB-8888 format.*/ -#define LTDC_FMT_RGB888 (1) /**< RGB-888 format.*/ -#define LTDC_FMT_RGB565 (2) /**< RGB-565 format.*/ -#define LTDC_FMT_ARGB1555 (3) /**< ARGB-1555 format.*/ -#define LTDC_FMT_ARGB4444 (4) /**< ARGB-4444 format.*/ -#define LTDC_FMT_L8 (5) /**< L-8 format.*/ -#define LTDC_FMT_AL44 (6) /**< AL-44 format.*/ -#define LTDC_FMT_AL88 (7) /**< AL-88 format.*/ -/** @} */ - -/** - * @name LTDC pixel format aliased raw masks - * @{ - */ -#define LTDC_XMASK_ARGB8888 (0xFFFFFFFF) /**< ARGB-8888 aliased mask.*/ -#define LTDC_XMASK_RGB888 (0x00FFFFFF) /**< RGB-888 aliased mask.*/ -#define LTDC_XMASK_RGB565 (0x00F8FCF8) /**< RGB-565 aliased mask.*/ -#define LTDC_XMASK_ARGB1555 (0x80F8F8F8) /**< ARGB-1555 aliased mask.*/ -#define LTDC_XMASK_ARGB4444 (0xF0F0F0F0) /**< ARGB-4444 aliased mask.*/ -#define LTDC_XMASK_L8 (0x000000FF) /**< L-8 aliased mask.*/ -#define LTDC_XMASK_AL44 (0xF00000F0) /**< AL-44 aliased mask.*/ -#define LTDC_XMASK_AL88 (0xFF0000FF) /**< AL-88 aliased mask.*/ -/** @} */ - -/** - * @name LTDC blending factors - * @{ - */ -#define LTDC_BLEND_FIX1_FIX2 (0x0405) /**< cnst1; 1 - cnst2 */ -#define LTDC_BLEND_FIX1_MOD2 (0x0407) /**< cnst1; 1 - a2 * cnst2 */ -#define LTDC_BLEND_MOD1_FIX2 (0x0605) /**< a1 * cnst1; 1 - cnst2 */ -#define LTDC_BLEND_MOD1_MOD2 (0x0607) /**< a1 * cnst1; 1 - a2 * cnst2 */ -/** @} */ - -/** - * @name LTDC parameter bounds - * @{ - */ - -#define LTDC_MIN_SCREEN_WIDTH (1) -#define LTDC_MIN_SCREEN_HEIGHT (1) -#define LTDC_MAX_SCREEN_WIDTH (800) -#define LTDC_MAX_SCREEN_HEIGHT (600) - -#define LTDC_MIN_HSYNC_WIDTH (1) -#define LTDC_MIN_VSYNC_HEIGHT (1) -#define LTDC_MAX_HSYNC_WIDTH (1 << 12) -#define LTDC_MAX_VSYNC_HEIGHT (1 << 11) - -#define LTDC_MIN_HBP_WIDTH (0) -#define LTDC_MIN_VBP_HEIGHT (0) -#define LTDC_MAX_HBP_WIDTH (1 << 12) -#define LTDC_MAX_VBP_HEIGHT (1 << 11) - -#define LTDC_MIN_ACC_HBP_WIDTH (1) -#define LTDC_MIN_ACC_VBP_HEIGHT (1) -#define LTDC_MAX_ACC_HBP_WIDTH (1 << 12) -#define LTDC_MAX_ACC_VBP_HEIGHT (1 << 11) - -#define LTDC_MIN_HFP_WIDTH (0) -#define LTDC_MIN_VFP_HEIGHT (0) -#define LTDC_MAX_HFP_WIDTH (1 << 12) -#define LTDC_MAX_VFP_HEIGHT (1 << 11) - -#define LTDC_MIN_ACTIVE_WIDTH (0) -#define LTDC_MIN_ACTIVE_HEIGHT (0) -#define LTDC_MAX_ACTIVE_WIDTH (1 << 12) -#define LTDC_MAX_ACTIVE_HEIGHT (1 << 11) - -#define LTDC_MIN_ACC_ACTIVE_WIDTH (1) -#define LTDC_MIN_ACC_ACTIVE_HEIGHT (1) -#define LTDC_MAX_ACC_ACTIVE_WIDTH (1 << 12) -#define LTDC_MAX_ACC_ACTIVE_HEIGHT (1 << 11) - -#define LTDC_MIN_ACC_TOTAL_WIDTH (1) -#define LTDC_MIN_ACC_TOTAL_HEIGHT (1) -#define LTDC_MAX_ACC_TOTAL_WIDTH (1 << 12) -#define LTDC_MAX_ACC_TOTAL_HEIGHT (1 << 11) - -#define LTDC_MIN_LINE_INTERRUPT_POS (0) -#define LTDC_MAX_LINE_INTERRUPT_POS ((1 << 11) - 1) - -#define LTDC_MIN_WINDOW_HSTART (0) -#define LTDC_MIN_WINDOW_HSTART (0) -#define LTDC_MAX_WINDOW_HSTOP ((1 << 12) - 1) -#define LTDC_MAX_WINDOW_HSTOP ((1 << 12) - 1) - -#define LTDC_MIN_WINDOW_VSTART (0) -#define LTDC_MIN_WINDOW_VSTART (0) -#define LTDC_MAX_WINDOW_VSTOP ((1 << 11) - 1) -#define LTDC_MAX_WINDOW_VSTOP ((1 << 11) - 1) - -#define LTDC_MIN_FRAME_WIDTH_BYTES (0) -#define LTDC_MIN_FRAME_HEIGHT_LINES (0) -#define LTDC_MIN_FRAME_PITCH_BYTES (0) -#define LTDC_MAX_FRAME_WIDTH_BYTES ((1 << 13) - 1 - 3) -#define LTDC_MAX_FRAME_HEIGHT_LINES ((1 << 11) - 1) -#define LTDC_MAX_FRAME_PITCH_BYTES ((1 << 13) - 1) - -#define LTDC_MIN_PIXFMT_ID (0) -#define LTDC_MAX_PIXFMT_ID (7) - -#define LTDC_MAX_PALETTE_LENGTH (256) - -/** @} */ - -/** - * @name LTDC basic ARGB-8888 colors. - * @{ - */ -/* Microsoft Windows default 16-color palette.*/ -#define LTDC_COLOR_BLACK (0xFF000000) -#define LTDC_COLOR_MAROON (0xFF800000) -#define LTDC_COLOR_GREEN (0xFF008000) -#define LTDC_COLOR_OLIVE (0xFF808000) -#define LTDC_COLOR_NAVY (0xFF000080) -#define LTDC_COLOR_PURPLE (0xFF800080) -#define LTDC_COLOR_TEAL (0xFF008080) -#define LTDC_COLOR_SILVER (0xFFC0C0C0) -#define LTDC_COLOR_GRAY (0xFF808080) -#define LTDC_COLOR_RED (0xFFFF0000) -#define LTDC_COLOR_LIME (0xFF00FF00) -#define LTDC_COLOR_YELLOW (0xFFFFFF00) -#define LTDC_COLOR_BLUE (0xFF0000FF) -#define LTDC_COLOR_FUCHSIA (0xFFFF00FF) -#define LTDC_COLOR_AQUA (0xFF00FFFF) -#define LTDC_COLOR_WHITE (0xFFFFFFFF) -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name LTDC configuration options - * @{ - */ - -/** - * @brief LTDC event interrupt priority level setting. - */ -#if !defined(STM32_LTDC_EV_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_LTDC_EV_IRQ_PRIORITY (11) -#endif - -/** - * @brief LTDC error interrupt priority level setting. - */ -#if !defined(STM32_LTDC_ER_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_LTDC_ER_IRQ_PRIORITY (11) -#endif - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(LTDC_USE_WAIT) || defined(__DOXYGEN__) -#define LTDC_USE_WAIT (TRUE) -#endif - -/** - * @brief Enables the @p ltdcAcquireBus() and @p ltdcReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(LTDC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define LTDC_USE_MUTUAL_EXCLUSION (TRUE) -#endif - -/** - * @brief Provides software color conversion functions. - * @note Disabling this option saves both code and data space. - */ -#if !defined(LTDC_USE_SOFTWARE_CONVERSIONS) || defined(__DOXYGEN__) -#define LTDC_USE_SOFTWARE_CONVERSIONS (TRUE) -#endif - -/** - * @brief Enables checks for LTDC functions. - * @note Disabling this option saves both code and data space. - * @note Disabling checks by ChibiOS will automatically disable LTDC checks. - */ -#if !defined(LTDC_USE_CHECKS) || defined(__DOXYGEN__) -#define LTDC_USE_CHECKS (TRUE) -#endif - -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if (TRUE != STM32_HAS_LTDC) -#error "LTDC must be present when using the LTDC subsystem" -#endif - -#if (TRUE == STM32_LTDC_USE_LTDC) && (TRUE != STM32_HAS_LTDC) -#error "LTDC not present in the selected device" -#endif - -#if (TRUE == LTDC_USE_MUTUAL_EXCLUSION) -#if (TRUE != CH_CFG_USE_MUTEXES) && (TRUE != CH_CFG_USE_SEMAPHORES) -#error "LTDC_USE_MUTUAL_EXCLUSION requires CH_CFG_USE_MUTEXES and/or CH_CFG_USE_SEMAPHORES" -#endif -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/* Complex types forwarding.*/ -typedef union ltdc_coloralias_t ltdc_coloralias_t; -typedef struct ltdc_window_t ltdc_window_t; -typedef struct ltdc_frame_t ltdc_frame_t; -typedef struct ltdc_laycfg_t ltdc_laycfg_t; -typedef struct LTDCConfig LTDCConfig; -typedef enum ltdc_state_t ltdc_state_t; -typedef struct LTDCDriver LTDCDriver; - -/** - * @name LTDC Data types - * @{ - */ - -/** - * @brief LTDC generic color. - */ -typedef uint32_t ltdc_color_t; - -/** - * @brief LTDC color aliases. - * @detail Mapped with ARGB-8888, except for luminance (L mapped onto B). - * Padding fields are prefixed with 'x', and should be clear - * (all 0) before compression and set (all 1) after expansion. - */ -typedef union ltdc_coloralias_t { - struct { - unsigned b : 8; - unsigned g : 8; - unsigned r : 8; - unsigned a : 8; - } argb8888; /**< Mapped ARGB-8888 bits.*/ - struct { - unsigned b : 8; - unsigned g : 8; - unsigned r : 8; - unsigned xa : 8; - } rgb888; /**< Mapped RGB-888 bits.*/ - struct { - unsigned xb : 3; - unsigned b : 5; - unsigned xg : 2; - unsigned g : 6; - unsigned xr : 3; - unsigned r : 5; - unsigned xa : 8; - } rgb565; /**< Mapped RGB-565 bits.*/ - struct { - unsigned xb : 3; - unsigned b : 5; - unsigned xg : 3; - unsigned g : 5; - unsigned xr : 3; - unsigned r : 5; - unsigned xa : 7; - unsigned a : 1; - } argb1555; /**< Mapped ARGB-1555 values.*/ - struct { - unsigned xb : 4; - unsigned b : 4; - unsigned xg : 4; - unsigned g : 4; - unsigned xr : 4; - unsigned r : 4; - unsigned xa : 4; - unsigned a : 4; - } argb4444; /**< Mapped ARGB-4444 values.*/ - struct { - unsigned l : 8; - unsigned x : 16; - unsigned xa : 8; - } l8; /**< Mapped L-8 bits.*/ - struct { - unsigned xl : 4; - unsigned l : 4; - unsigned x : 16; - unsigned xa : 4; - unsigned a : 4; - } al44; /**< Mapped AL-44 bits.*/ - struct { - unsigned l : 8; - unsigned x : 16; - unsigned a : 8; - } al88; /**< Mapped AL-88 bits.*/ - ltdc_color_t aliased; /**< Aliased raw bits.*/ -} ltdc_coloralias_t; - -/** - * @brief LTDC layer identifier. - */ -typedef uint32_t ltdc_layerid_t; - -/** - * @brief LTDC pixel format. - */ -typedef uint32_t ltdc_pixfmt_t; - -/** - * @brief LTDC blending factor. - */ -typedef uint32_t ltdc_blendf_t; - -/** - * @brief LTDC ISR callback. - */ -typedef void (*ltdc_isrcb_t)(LTDCDriver *ltdcp); - -/** - * @brief LTDC window specifications. - */ -typedef struct ltdc_window_t { - uint16_t hstart; /**< Horizontal start pixel (left).*/ - uint16_t hstop; /**< Horizontal stop pixel (right).*/ - uint16_t vstart; /**< Vertical start pixel (top).*/ - uint16_t vstop; /**< Vertical stop pixel (bottom).*/ -} ltdc_window_t; - -/** - * @brief LTDC frame specifications. - */ -typedef struct ltdc_frame_t { - void *bufferp; /**< Frame buffer address.*/ - uint16_t width; /**< Frame width, in pixels.*/ - uint16_t height; /**< Frame height, in pixels.*/ - size_t pitch; /**< Line pitch, in bytes.*/ - ltdc_pixfmt_t fmt; /**< Pixel format.*/ -} ltdc_frame_t; - -/** - * @brief LTDC configuration flags. - */ -typedef uint8_t ltdc_flags_t; - -/** - * @brief LTDC startup layer configuration. - */ -typedef struct ltdc_laycfg_t { - const ltdc_frame_t *frame; /**< Frame buffer specifications.*/ - const ltdc_window_t *window; /**< Window specifications.*/ - ltdc_color_t def_color; /**< Default color, ARGB-8888.*/ - uint8_t const_alpha; /**< Constant alpha factor.*/ - ltdc_color_t key_color; /**< Color key.*/ - const ltdc_color_t *pal_colors; /**< Palette colors, or @p NULL.*/ - uint16_t pal_length; /**< Palette length, or @p 0.*/ - ltdc_blendf_t blending; /**< Blending factors.*/ - ltdc_flags_t flags; /**< Layer configuration flags.*/ -} ltdc_laycfg_t; - -/** - * @brief LTDC driver configuration. - */ -typedef struct LTDCConfig { - /* Display specifications.*/ - uint16_t screen_width; /**< Screen pixel width.*/ - uint16_t screen_height; /**< Screen pixel height.*/ - uint16_t hsync_width; /**< Horizontal sync pixel width.*/ - uint16_t vsync_height; /**< Vertical sync pixel height.*/ - uint16_t hbp_width; /**< Horizontal back porch pixel width.*/ - uint16_t vbp_height; /**< Vertical back porch pixel height.*/ - uint16_t hfp_width; /**< Horizontal front porch pixel width.*/ - uint16_t vfp_height; /**< Vertical front porch pixel height.*/ - ltdc_flags_t flags; /**< Driver configuration flags.*/ - - /* ISR callbacks.*/ - ltdc_isrcb_t line_isr; /**< Line Interrupt ISR, or @p NULL.*/ - ltdc_isrcb_t rr_isr; /**< Register Reload ISR, or @p NULL.*/ - ltdc_isrcb_t fuerr_isr; /**< FIFO Underrun ISR, or @p NULL.*/ - ltdc_isrcb_t terr_isr; /**< Transfer Error ISR, or @p NULL.*/ - - /* Layer and color settings.*/ - ltdc_color_t clear_color; /**< Clear screen color, RGB-888.*/ - const ltdc_laycfg_t *bg_laycfg; /**< Background layer specs, or @p NULL.*/ - const ltdc_laycfg_t *fg_laycfg; /**< Foreground layer specs, or @p NULL.*/ -} LTDCConfig; - -/** - * @brief LTDC driver state. - */ -typedef enum ltdc_state_t { - LTDC_UNINIT = (0), /**< Not initialized.*/ - LTDC_STOP = (1), /**< Stopped.*/ - LTDC_READY = (2), /**< Ready.*/ - LTDC_ACTIVE = (3), /**< Executing commands.*/ -} ltdc_state_t; - -/** - * @brief LTDC driver. - */ -typedef struct LTDCDriver { - ltdc_state_t state; /**< Driver state.*/ - const LTDCConfig *config; /**< Driver configuration.*/ - - /* Handy computations.*/ - ltdc_window_t active_window; /**< Active window coordinates.*/ - - /* Multithreading stuff.*/ -#if (TRUE == LTDC_USE_WAIT) || defined(__DOXYGEN__) - thread_t *thread; /**< Waiting thread.*/ -#endif /* LTDC_USE_WAIT */ -#if (TRUE == LTDC_USE_MUTUAL_EXCLUSION) -#if (TRUE == CH_CFG_USE_MUTEXES) - mutex_t lock; /**< Multithreading lock.*/ -#elif (TRUE == CH_CFG_USE_SEMAPHORES) - semaphore_t lock; /**< Multithreading lock.*/ -#endif -#endif /* LTDC_USE_MUTUAL_EXCLUSION */ -} LTDCDriver; - -/** @} */ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Makes an ARGB-8888 value from byte components. - * - * @param[in] a alpha byte component - * @param[in] r red byte component - * @param[in] g green byte component - * @param[in] b blue byte component - * - * @return color in ARGB-8888 format - * - * @api - */ -#define ltdcMakeARGB8888(a, r, g, b) \ - ((((ltdc_color_t)(a) & 0xFF) << 24) | \ - (((ltdc_color_t)(r) & 0xFF) << 16) | \ - (((ltdc_color_t)(g) & 0xFF) << 8) | \ - (((ltdc_color_t)(b) & 0xFF) << 0)) - -/** - * @brief Compute bytes per pixel. - * @details Computes the bytes per pixel for the specified pixel format. - * Rounds to the ceiling. - * - * @param[in] fmt pixel format - * - * @return bytes per pixel - * - * @api - */ -#define ltdcBytesPerPixel(fmt) \ - ((ltdcBitsPerPixel(fmt) + 7) >> 3) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -extern LTDCDriver LTDCD1; - -#ifdef __cplusplus -extern "C" { -#endif - /* Driver methods.*/ - void ltdcInit(void); - void ltdcObjectInit(LTDCDriver *ltdcp); - ltdc_state_t ltdcGetStateI(LTDCDriver *ltdcp); - ltdc_state_t ltdcGetState(LTDCDriver *ltdcp); - void ltdcStart(LTDCDriver *ltdcp, const LTDCConfig *configp); - void ltdcStop(LTDCDriver *ltdcp); -#if (TRUE == LTDC_USE_MUTUAL_EXCLUSION) - void ltdcAcquireBusS(LTDCDriver *ltdcp); - void ltdcAcquireBus(LTDCDriver *ltdcp); - void ltdcReleaseBusS(LTDCDriver *ltdcp); - void ltdcReleaseBus(LTDCDriver *ltdcp); -#endif /* LTDC_USE_MUTUAL_EXCLUSION */ - - /* Global methods.*/ - ltdc_flags_t ltdcGetEnableFlagsI(LTDCDriver *ltdcp); - ltdc_flags_t ltdcGetEnableFlags(LTDCDriver *ltdcp); - void ltdcSetEnableFlagsI(LTDCDriver *ltdcp, ltdc_flags_t flags); - void ltdcSetEnableFlags(LTDCDriver *ltdcp, ltdc_flags_t flags); - bool ltdcIsReloadingI(LTDCDriver *ltdcp); - bool ltdcIsReloading(LTDCDriver *ltdcp); - void ltdcStartReloadI(LTDCDriver *ltdcp, bool immediately); - void ltdcStartReload(LTDCDriver *ltdcp, bool immediately); - void ltdcReloadS(LTDCDriver *ltdcp, bool immediately); - void ltdcReload(LTDCDriver *ltdcp, bool immediately); - bool ltdcIsDitheringEnabledI(LTDCDriver *ltdcp); - bool ltdcIsDitheringEnabled(LTDCDriver *ltdcp); - void ltdcEnableDitheringI(LTDCDriver *ltdcp); - void ltdcEnableDithering(LTDCDriver *ltdcp); - void ltdcDisableDitheringI(LTDCDriver *ltdcp); - void ltdcDisableDithering(LTDCDriver *ltdcp); - ltdc_color_t ltdcGetClearColorI(LTDCDriver *ltdcp); - ltdc_color_t ltdcGetClearColor(LTDCDriver *ltdcp); - void ltdcSetClearColorI(LTDCDriver *ltdcp, ltdc_color_t c); - void ltdcSetClearColor(LTDCDriver *ltdcp, ltdc_color_t c); - uint16_t ltdcGetLineInterruptPosI(LTDCDriver *ltdcp); - uint16_t ltdcGetLineInterruptPos(LTDCDriver *ltdcp); - void ltdcSetLineInterruptPosI(LTDCDriver *ltdcp, uint16_t line); - void ltdcSetLineInterruptPos(LTDCDriver *ltdcp, uint16_t line); - bool ltdcIsLineInterruptEnabledI(LTDCDriver *ltdcp); - bool ltdcIsLineInterruptEnabled(LTDCDriver *ltdcp); - void ltdcEnableLineInterruptI(LTDCDriver *ltdcp); - void ltdcEnableLineInterrupt(LTDCDriver *ltdcp); - void ltdcDisableLineInterruptI(LTDCDriver *ltdcp); - void ltdcDisableLineInterrupt(LTDCDriver *ltdcp); - void ltdcGetCurrentPosI(LTDCDriver *ltdcp, uint16_t *xp, uint16_t *yp); - void ltdcGetCurrentPos(LTDCDriver *ltdcp, uint16_t *xp, uint16_t *yp); - - /* Background layer methods.*/ - ltdc_flags_t ltdcBgGetEnableFlagsI(LTDCDriver *ltdcp); - ltdc_flags_t ltdcBgGetEnableFlags(LTDCDriver *ltdcp); - void ltdcBgSetEnableFlagsI(LTDCDriver *ltdcp, ltdc_flags_t flags); - void ltdcBgSetEnableFlags(LTDCDriver *ltdcp, ltdc_flags_t flags); - bool ltdcBgIsEnabledI(LTDCDriver *ltdcp); - bool ltdcBgIsEnabled(LTDCDriver *ltdcp); - void ltdcBgEnableI(LTDCDriver *ltdcp); - void ltdcBgEnable(LTDCDriver *ltdcp); - void ltdcBgDisableI(LTDCDriver *ltdcp); - void ltdcBgDisable(LTDCDriver *ltdcp); - bool ltdcBgIsPaletteEnabledI(LTDCDriver *ltdcp); - bool ltdcBgIsPaletteEnabled(LTDCDriver *ltdcp); - void ltdcBgEnablePaletteI(LTDCDriver *ltdcp); - void ltdcBgEnablePalette(LTDCDriver *ltdcp); - void ltdcBgDisablePaletteI(LTDCDriver *ltdcp); - void ltdcBgDisablePalette(LTDCDriver *ltdcp); - void ltdcBgSetPaletteColorI(LTDCDriver *ltdcp, uint8_t slot, ltdc_color_t c); - void ltdcBgSetPaletteColor(LTDCDriver *ltdcp, uint8_t slot, ltdc_color_t c); - void ltdcBgSetPaletteI(LTDCDriver *ltdcp, const ltdc_color_t colors[], - uint16_t length); - void ltdcBgSetPalette(LTDCDriver *ltdcp, const ltdc_color_t colors[], - uint16_t length); - ltdc_pixfmt_t ltdcBgGetPixelFormatI(LTDCDriver *ltdcp); - ltdc_pixfmt_t ltdcBgGetPixelFormat(LTDCDriver *ltdcp); - void ltdcBgSetPixelFormatI(LTDCDriver *ltdcp, ltdc_pixfmt_t fmt); - void ltdcBgSetPixelFormat(LTDCDriver *ltdcp, ltdc_pixfmt_t fmt); - bool ltdcBgIsKeyingEnabledI(LTDCDriver *ltdcp); - bool ltdcBgIsKeyingEnabled(LTDCDriver *ltdcp); - void ltdcBgEnableKeyingI(LTDCDriver *ltdcp); - void ltdcBgEnableKeying(LTDCDriver *ltdcp); - void ltdcBgDisableKeyingI(LTDCDriver *ltdcp); - void ltdcBgDisableKeying(LTDCDriver *ltdcp); - ltdc_color_t ltdcBgGetKeyingColorI(LTDCDriver *ltdcp); - ltdc_color_t ltdcBgGetKeyingColor(LTDCDriver *ltdcp); - void ltdcBgSetKeyingColorI(LTDCDriver *ltdcp, ltdc_color_t c); - void ltdcBgSetKeyingColor(LTDCDriver *ltdcp, ltdc_color_t c); - uint8_t ltdcBgGetConstantAlphaI(LTDCDriver *ltdcp); - uint8_t ltdcBgGetConstantAlpha(LTDCDriver *ltdcp); - void ltdcBgSetConstantAlphaI(LTDCDriver *ltdcp, uint8_t a); - void ltdcBgSetConstantAlpha(LTDCDriver *ltdcp, uint8_t a); - ltdc_color_t ltdcBgGetDefaultColorI(LTDCDriver *ltdcp); - ltdc_color_t ltdcBgGetDefaultColor(LTDCDriver *ltdcp); - void ltdcBgSetDefaultColorI(LTDCDriver *ltdcp, ltdc_color_t c); - void ltdcBgSetDefaultColor(LTDCDriver *ltdcp, ltdc_color_t c); - ltdc_blendf_t ltdcBgGetBlendingFactorsI(LTDCDriver *ltdcp); - ltdc_blendf_t ltdcBgGetBlendingFactors(LTDCDriver *ltdcp); - void ltdcBgSetBlendingFactorsI(LTDCDriver *ltdcp, ltdc_blendf_t bf); - void ltdcBgSetBlendingFactors(LTDCDriver *ltdcp, ltdc_blendf_t bf); - void ltdcBgGetWindowI(LTDCDriver *ltdcp, ltdc_window_t *windowp); - void ltdcBgGetWindow(LTDCDriver *ltdcp, ltdc_window_t *windowp); - void ltdcBgSetWindowI(LTDCDriver *ltdcp, const ltdc_window_t *windowp); - void ltdcBgSetWindow(LTDCDriver *ltdcp, const ltdc_window_t *windowp); - void ltdcBgSetInvalidWindowI(LTDCDriver *ltdcp); - void ltdcBgSetInvalidWindow(LTDCDriver *ltdcp); - void ltdcBgGetFrameI(LTDCDriver *ltdcp, ltdc_frame_t *framep); - void ltdcBgGetFrame(LTDCDriver *ltdcp, ltdc_frame_t *framep); - void ltdcBgSetFrameI(LTDCDriver *ltdcp, const ltdc_frame_t *framep); - void ltdcBgSetFrame(LTDCDriver *ltdcp, const ltdc_frame_t *framep); - void *ltdcBgGetFrameAddressI(LTDCDriver *ltdcp); - void *ltdcBgGetFrameAddress(LTDCDriver *ltdcp); - void ltdcBgSetFrameAddressI(LTDCDriver *ltdcp, void *bufferp); - void ltdcBgSetFrameAddress(LTDCDriver *ltdcp, void *bufferp); - void ltdcBgGetLayerI(LTDCDriver *ltdcp, ltdc_laycfg_t *cfgp); - void ltdcBgGetLayer(LTDCDriver *ltdcp, ltdc_laycfg_t *cfgp); - void ltdcBgSetConfigI(LTDCDriver *ltdcp, const ltdc_laycfg_t *cfgp); - void ltdcBgSetConfig(LTDCDriver *ltdcp, const ltdc_laycfg_t *cfgp); - - /* Foreground layer methods.*/ - ltdc_flags_t ltdcFgGetEnableFlagsI(LTDCDriver *ltdcp); - ltdc_flags_t ltdcFgGetEnableFlags(LTDCDriver *ltdcp); - void ltdcFgSetEnableFlagsI(LTDCDriver *ltdcp, ltdc_flags_t flags); - void ltdcFgSetEnableFlags(LTDCDriver *ltdcp, ltdc_flags_t flags); - bool ltdcFgIsEnabledI(LTDCDriver *ltdcp); - bool ltdcFgIsEnabled(LTDCDriver *ltdcp); - void ltdcFgEnableI(LTDCDriver *ltdcp); - void ltdcFgEnable(LTDCDriver *ltdcp); - void ltdcFgDisableI(LTDCDriver *ltdcp); - void ltdcFgDisable(LTDCDriver *ltdcp); - bool ltdcFgIsPaletteEnabledI(LTDCDriver *ltdcp); - bool ltdcFgIsPaletteEnabled(LTDCDriver *ltdcp); - void ltdcFgEnablePaletteI(LTDCDriver *ltdcp); - void ltdcFgEnablePalette(LTDCDriver *ltdcp); - void ltdcFgDisablePaletteI(LTDCDriver *ltdcp); - void ltdcFgDisablePalette(LTDCDriver *ltdcp); - void ltdcFgSetPaletteColorI(LTDCDriver *ltdcp, uint8_t slot, ltdc_color_t c); - void ltdcFgSetPaletteColor(LTDCDriver *ltdcp, uint8_t slot, ltdc_color_t c); - void ltdcFgSetPaletteI(LTDCDriver *ltdcp, const ltdc_color_t colors[], - uint16_t length); - void ltdcFgSetPalette(LTDCDriver *ltdcp, const ltdc_color_t colors[], - uint16_t length); - ltdc_pixfmt_t ltdcFgGetPixelFormatI(LTDCDriver *ltdcp); - ltdc_pixfmt_t ltdcFgGetPixelFormat(LTDCDriver *ltdcp); - void ltdcFgSetPixelFormatI(LTDCDriver *ltdcp, ltdc_pixfmt_t fmt); - void ltdcFgSetPixelFormat(LTDCDriver *ltdcp, ltdc_pixfmt_t fmt); - bool ltdcFgIsKeyingEnabledI(LTDCDriver *ltdcp); - bool ltdcFgIsKeyingEnabled(LTDCDriver *ltdcp); - void ltdcFgEnableKeyingI(LTDCDriver *ltdcp); - void ltdcFgEnableKeying(LTDCDriver *ltdcp); - void ltdcFgDisableKeyingI(LTDCDriver *ltdcp); - void ltdcFgDisableKeying(LTDCDriver *ltdcp); - ltdc_color_t ltdcFgGetKeyingColorI(LTDCDriver *ltdcp); - ltdc_color_t ltdcFgGetKeyingColor(LTDCDriver *ltdcp); - void ltdcFgSetKeyingColorI(LTDCDriver *ltdcp, ltdc_color_t c); - void ltdcFgSetKeyingColor(LTDCDriver *ltdcp, ltdc_color_t c); - uint8_t ltdcFgGetConstantAlphaI(LTDCDriver *ltdcp); - uint8_t ltdcFgGetConstantAlpha(LTDCDriver *ltdcp); - void ltdcFgSetConstantAlphaI(LTDCDriver *ltdcp, uint8_t a); - void ltdcFgSetConstantAlpha(LTDCDriver *ltdcp, uint8_t a); - ltdc_color_t ltdcFgGetDefaultColorI(LTDCDriver *ltdcp); - ltdc_color_t ltdcFgGetDefaultColor(LTDCDriver *ltdcp); - void ltdcFgSetDefaultColorI(LTDCDriver *ltdcp, ltdc_color_t c); - void ltdcFgSetDefaultColor(LTDCDriver *ltdcp, ltdc_color_t c); - ltdc_blendf_t ltdcFgGetBlendingFactorsI(LTDCDriver *ltdcp); - ltdc_blendf_t ltdcFgGetBlendingFactors(LTDCDriver *ltdcp); - void ltdcFgSetBlendingFactorsI(LTDCDriver *ltdcp, ltdc_blendf_t bf); - void ltdcFgSetBlendingFactors(LTDCDriver *ltdcp, ltdc_blendf_t bf); - void ltdcFgGetWindowI(LTDCDriver *ltdcp, ltdc_window_t *windowp); - void ltdcFgGetWindow(LTDCDriver *ltdcp, ltdc_window_t *windowp); - void ltdcFgSetWindowI(LTDCDriver *ltdcp, const ltdc_window_t *windowp); - void ltdcFgSetWindow(LTDCDriver *ltdcp, const ltdc_window_t *windowp); - void ltdcFgSetInvalidWindowI(LTDCDriver *ltdcp); - void ltdcFgSetInvalidWindow(LTDCDriver *ltdcp); - void ltdcFgGetFrameI(LTDCDriver *ltdcp, ltdc_frame_t *framep); - void ltdcFgGetFrame(LTDCDriver *ltdcp, ltdc_frame_t *framep); - void ltdcFgSetFrameI(LTDCDriver *ltdcp, const ltdc_frame_t *framep); - void ltdcFgSetFrame(LTDCDriver *ltdcp, const ltdc_frame_t *framep); - void *ltdcFgGetFrameAddressI(LTDCDriver *ltdcp); - void *ltdcFgGetFrameAddress(LTDCDriver *ltdcp); - void ltdcFgSetFrameAddressI(LTDCDriver *ltdcp, void *bufferp); - void ltdcFgSetFrameAddress(LTDCDriver *ltdcp, void *bufferp); - void ltdcFgGetLayerI(LTDCDriver *ltdcp, ltdc_laycfg_t *cfgp); - void ltdcFgGetLayer(LTDCDriver *ltdcp, ltdc_laycfg_t *cfgp); - void ltdcFgSetConfigI(LTDCDriver *ltdcp, const ltdc_laycfg_t *cfgp); - void ltdcFgSetConfig(LTDCDriver *ltdcp, const ltdc_laycfg_t *cfgp); - - /* Helper functions.*/ - size_t ltdcBitsPerPixel(ltdc_pixfmt_t fmt); -#if (TRUE == LTDC_USE_SOFTWARE_CONVERSIONS) || defined(__DOXYGEN__) - ltdc_color_t ltdcFromARGB8888(ltdc_color_t c, ltdc_pixfmt_t fmt); - ltdc_color_t ltdcToARGB8888(ltdc_color_t c, ltdc_pixfmt_t fmt); -#endif /* LTDC_USE_SOFTWARE_CONVERSIONS */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32_LTDC_USE_LTDC */ - -#endif /* HAL_STM32_LTDC_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c b/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c deleted file mode 100644 index c04278e01c..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c +++ /dev/null @@ -1,1176 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Concepts and parts of this file have been contributed by Fabio Utzig and - Xo Wang. -*/ -/* - Rewritten by Emil Fresk (1/5 - 2014) for extended input capture - functionality. And fix for spurious callbacks in the interrupt handler. -*/ -/* - Improved by Uladzimir Pylinsky aka barthess (1/3 - 2015) for support of - 32-bit timers and timers with single capture/compare channels. -*/ - -/* - * Hardware Abstraction Layer for Extended Input Capture Unit - */ -#include "hal.h" - -#if (HAL_USE_EICU == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ -/** - * @brief Inverts the polarity for the given channel. - * - * @param[in] eicup Pointer to the EICUDriver object. - * @param[in] channel The timer channel to invert. - * - * @notapi - */ -#define eicu_lld_invert_polarity(eicup, channel) \ - (eicup)->tim->CCER ^= ((uint16_t)(STM32_TIM_CCER_CC1P << ((channel) * 4))) - -/** - * @brief Returns the compare value of the latest cycle. - * - * @param[in] chp Pointer to channel structure that fired the interrupt. - * @return The number of ticks. - * - * @notapi - */ -#define eicu_lld_get_compare(chp) (*((chp)->ccrp) + 1) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief EICUD1 driver identifier. - * @note The driver EICUD1 allocates the complex timer TIM1 when enabled. - */ -#if STM32_EICU_USE_TIM1 && !defined(__DOXYGEN__) -EICUDriver EICUD1; -#endif - -/** - * @brief EICUD2 driver identifier. - * @note The driver EICUD2 allocates the timer TIM2 when enabled. - */ -#if STM32_EICU_USE_TIM2 && !defined(__DOXYGEN__) -EICUDriver EICUD2; -#endif - -/** - * @brief EICUD3 driver identifier. - * @note The driver EICUD3 allocates the timer TIM3 when enabled. - */ -#if STM32_EICU_USE_TIM3 && !defined(__DOXYGEN__) -EICUDriver EICUD3; -#endif - -/** - * @brief EICUD4 driver identifier. - * @note The driver EICUD4 allocates the timer TIM4 when enabled. - */ -#if STM32_EICU_USE_TIM4 && !defined(__DOXYGEN__) -EICUDriver EICUD4; -#endif - -/** - * @brief EICUD5 driver identifier. - * @note The driver EICUD5 allocates the timer TIM5 when enabled. - */ -#if STM32_EICU_USE_TIM5 && !defined(__DOXYGEN__) -EICUDriver EICUD5; -#endif - -/** - * @brief EICUD8 driver identifier. - * @note The driver EICUD8 allocates the timer TIM8 when enabled. - */ -#if STM32_EICU_USE_TIM8 && !defined(__DOXYGEN__) -EICUDriver EICUD8; -#endif - -/** - * @brief EICUD9 driver identifier. - * @note The driver EICUD9 allocates the timer TIM9 when enabled. - */ -#if STM32_EICU_USE_TIM9 && !defined(__DOXYGEN__) -EICUDriver EICUD9; -#endif - -/** - * @brief EICUD12 driver identifier. - * @note The driver EICUD12 allocates the timer TIM12 when enabled. - */ -#if STM32_EICU_USE_TIM12 && !defined(__DOXYGEN__) -EICUDriver EICUD12; -#endif - -/** - * @brief EICUD10 driver identifier. - * @note The driver EICUD10 allocates the timer TIM10 when enabled. - */ -#if STM32_EICU_USE_TIM10 && !defined(__DOXYGEN__) -EICUDriver EICUD10; -#endif - -/** - * @brief EICUD11 driver identifier. - * @note The driver EICUD11 allocates the timer TIM11 when enabled. - */ -#if STM32_EICU_USE_TIM11 && !defined(__DOXYGEN__) -EICUDriver EICUD11; -#endif - -/** - * @brief EICUD13 driver identifier. - * @note The driver EICUD13 allocates the timer TIM13 when enabled. - */ -#if STM32_EICU_USE_TIM13 && !defined(__DOXYGEN__) -EICUDriver EICUD13; -#endif - -/** - * @brief EICUD14 driver identifier. - * @note The driver EICUD14 allocates the timer TIM14 when enabled. - */ -#if STM32_EICU_USE_TIM14 && !defined(__DOXYGEN__) -EICUDriver EICUD14; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ -/** - * @brief Returns both pulse width and period. - * @details The time is defined as number of ticks. - * - * @param[in] eicup Pointer to the EICUDriver object. - * @param[in] channel The timer channel that fired the interrupt. - * @param[in] compare Content of the CCR register. - * @return The number of ticks. - * - * @notapi - */ -static eicuresult_t get_time_both(const EICUDriver *eicup, - eicuchannel_t channel, - eicucnt_t compare) { - - const EICUChannel *chp = &eicup->channel[channel]; - eicuresult_t ret; - - /* Note! there is no overflow check because it handles under the hood of - unsigned subtraction math.*/ - - /* 16-bit timer */ - if (EICU_WIDTH_16 == eicup->width) { - uint16_t cmp = compare; - uint16_t la = chp->last_active; - uint16_t li = chp->last_idle; - uint16_t w = li - la; - uint16_t p = cmp - la; - ret.width = w; - ret.period = p; - } - /* 32-bit timer */ - else if (EICU_WIDTH_32 == eicup->width) { - ret.width = chp->last_idle - chp->last_active; - ret.period = compare - chp->last_active; - } - /* error trap */ - else { - osalSysHalt("Unhandled width value"); - } - - return ret; -} - -/** - * @brief Returns pulse width. - * @details The time is defined as number of ticks. - * - * @param[in] eicup Pointer to the EICUDriver object. - * @param[in] channel The timer channel that fired the interrupt. - * @param[in] compare Content of the CCR register. - * @return The number of ticks. - * - * @notapi - */ -static eicucnt_t get_time_width(const EICUDriver *eicup, - eicuchannel_t channel, - eicucnt_t compare) { - - const EICUChannel *chp = &eicup->channel[channel]; - - /* Note! there is no overflow check because it handles under the hood of - unsigned subtraction math.*/ - - /* 16-bit timer */ - if (EICU_WIDTH_16 == eicup->width) { - uint16_t cmp = compare; - uint16_t la = chp->last_active; - uint16_t ret = cmp - la; - return ret; - } - /* 32-bit timer */ - else if (EICU_WIDTH_32 == eicup->width) { - return compare - chp->last_active; - } - /* error trap */ - else { - osalSysHalt("Unhandled width value"); - return 0; - } -} - -/** - * @brief Returns pulse period. - * @details The time is defined as number of ticks. - * - * @param[in] eicup Pointer to the EICUDriver object. - * @param[in] channel The timer channel that fired the interrupt. - * @param[in] compare Content of the CCR register. - * @return The number of ticks. - * - * @notapi - */ -static eicucnt_t get_time_period(const EICUDriver *eicup, - eicuchannel_t channel, - eicucnt_t compare) { - - const EICUChannel *chp = &eicup->channel[channel]; - - /* Note! there is no overflow check because it handles under the hood of - unsigned subtraction math.*/ - - /* 16-bit timer */ - if (EICU_WIDTH_16 == eicup->width) { - uint16_t cmp = compare; - uint16_t li = chp->last_idle; - uint16_t ret = cmp - li; - return ret; - } - /* 32-bit timer */ - else if (EICU_WIDTH_32 == eicup->width) { - return compare - chp->last_idle; - } - /* error trap */ - else { - osalSysHalt("Unhandled width value"); - return 0; - } -} - -/** - * @brief EICU width or (width + period) event. - * @note Needs special care since it needs to invert the - * correct polarity bit to detect pulses. - * @note Assumes that the polarity is not changed by some - * external user. It must only be changed using the HAL. - * - * @param[in] eicup Pointer to the @p EICUDriver object - * @param[in] channel The timer channel that fired the interrupt. - * - * @notapi - */ -static void isr_invoke_pulse_cb(EICUDriver *eicup, eicuchannel_t channel) { - EICUChannel *chp = &eicup->channel[channel]; - eicucnt_t compare = eicu_lld_get_compare(chp); - - if (EICU_CH_ACTIVE == chp->state) { - chp->state = EICU_CH_IDLE; - eicu_lld_invert_polarity(eicup, channel); - if (EICU_INPUT_PULSE == chp->config->mode) { - uint32_t width = get_time_width(eicup, channel, compare); - chp->config->capture_cb(eicup, channel, width, 0); - } - chp->last_idle = compare; - } - else { - chp->state = EICU_CH_ACTIVE; - eicu_lld_invert_polarity(eicup, channel); - if (EICU_INPUT_BOTH == chp->config->mode) { - eicuresult_t both = get_time_both(eicup, channel, compare); - chp->config->capture_cb(eicup, channel, both.width, both.period); - } - chp->last_active = compare; - } -} - -/** - * @brief EICU Edge detect event. - * - * @param[in] eicup Pointer to the @p EICUDriver object - * @param[in] channel The timer channel that fired the interrupt. - * - * @notapi - */ -static void isr_invoke_edge_cb(EICUDriver *eicup, eicuchannel_t channel) { - EICUChannel *chp = &eicup->channel[channel]; - eicucnt_t compare = eicu_lld_get_compare(chp); - uint32_t period = get_time_period(eicup, channel, compare); - - chp->config->capture_cb(eicup, channel, 0, period); - chp->last_idle = compare; -} - -/** - * @brief Common EICU detect call. - * - * @param[in] eicup Pointer to the @p EICUDriver object - * @param[in] channel The timer channel that fired the interrupt. - * - * @notapi - */ -static void eicu_isr_invoke_cb(EICUDriver *eicup, eicuchannel_t channel) { - - if (EICU_INPUT_EDGE == eicup->channel[channel].config->mode) - isr_invoke_edge_cb(eicup, channel); - else /* EICU_INPUT_PULSE || EICU_INPUT_BOTH */ - isr_invoke_pulse_cb(eicup, channel); -} - -/** - * @brief Shared IRQ handler. - * - * @param[in] eicup Pointer to the @p EICUDriver object - */ -static void eicu_lld_serve_interrupt(EICUDriver *eicup) { - uint16_t sr; - sr = eicup->tim->SR; - - /* Pick out the interrupts we are interested in by using - the interrupt enable bits as mask */ - sr &= (eicup->tim->DIER & STM32_TIM_DIER_IRQ_MASK); - - /* Clear interrupts */ - eicup->tim->SR = ~sr; - - if ((sr & STM32_TIM_SR_CC1IF) != 0) - eicu_isr_invoke_cb(eicup, EICU_CHANNEL_1); - if ((sr & STM32_TIM_SR_CC2IF) != 0) - eicu_isr_invoke_cb(eicup, EICU_CHANNEL_2); - if ((sr & STM32_TIM_SR_CC3IF) != 0) - eicu_isr_invoke_cb(eicup, EICU_CHANNEL_3); - if ((sr & STM32_TIM_SR_CC4IF) != 0) - eicu_isr_invoke_cb(eicup, EICU_CHANNEL_4); -} - -/** - * @brief Starts every channel. - * - * @param[in] eicup Pointer to the @p EICUDriver object - */ -static void start_channels(EICUDriver *eicup) { - - /* Set each input channel that is used as: a normal input capture channel, - link the corresponding CCR register and set polarity. */ - - /* Input capture channel 1 */ - if (eicup->config->iccfgp[0] != NULL) { - /* Normal capture input input */ - eicup->tim->CCMR1 |= STM32_TIM_CCMR1_CC1S(1); - - /* Link CCR register */ - eicup->channel[0].ccrp = &eicup->tim->CCR[0]; - - /* Set input polarity */ - if (eicup->config->iccfgp[0]->alvl == EICU_INPUT_ACTIVE_HIGH) - eicup->tim->CCER |= STM32_TIM_CCER_CC1E; - else - eicup->tim->CCER |= STM32_TIM_CCER_CC1E | STM32_TIM_CCER_CC1P; - } - - /* Input capture channel 2 */ - if (eicup->config->iccfgp[1] != NULL) { - /* Normal capture input input */ - eicup->tim->CCMR1 |= STM32_TIM_CCMR1_CC2S(1); - - /* Link CCR register */ - eicup->channel[1].ccrp = &eicup->tim->CCR[1]; - - /* Set input polarity */ - if (eicup->config->iccfgp[1]->alvl == EICU_INPUT_ACTIVE_HIGH) - eicup->tim->CCER |= STM32_TIM_CCER_CC2E; - else - eicup->tim->CCER |= STM32_TIM_CCER_CC2E | STM32_TIM_CCER_CC2P; - } - - /* Input capture channel 3 (not for TIM 9 and 12) */ - if (eicup->config->iccfgp[2] != NULL) { - /* Normal capture input input */ - eicup->tim->CCMR2 |= STM32_TIM_CCMR2_CC3S(1); - - /* Link CCR register */ - eicup->channel[2].ccrp = &eicup->tim->CCR[2]; - - /* Set input polarity */ - if (eicup->config->iccfgp[2]->alvl == EICU_INPUT_ACTIVE_HIGH) - eicup->tim->CCER |= STM32_TIM_CCER_CC3E; - else - eicup->tim->CCER |= STM32_TIM_CCER_CC3E | STM32_TIM_CCER_CC3P; - } - - /* Input capture channel 4 (not for TIM 9 and 12) */ - if (eicup->config->iccfgp[3] != NULL) { - /* Normal capture input input */ - eicup->tim->CCMR2 |= STM32_TIM_CCMR2_CC4S(1); - - /* Link CCR register */ - eicup->channel[3].ccrp = &eicup->tim->CCR[3]; - - /* Set input polarity */ - if (eicup->config->iccfgp[3]->alvl == EICU_INPUT_ACTIVE_HIGH) - eicup->tim->CCER |= STM32_TIM_CCER_CC4E; - else - eicup->tim->CCER |= STM32_TIM_CCER_CC4E | STM32_TIM_CCER_CC4P; - } -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if STM32_EICU_USE_TIM1 -#if !defined(STM32_TIM1_UP_HANDLER) -#error "STM32_TIM1_UP_HANDLER not defined" -#endif -/** - * @brief TIM1 compare interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - eicu_lld_serve_interrupt(&EICUD1); - - OSAL_IRQ_EPILOGUE(); -} - -#if !defined(STM32_TIM1_CC_HANDLER) -#error "STM32_TIM1_CC_HANDLER not defined" -#endif -/** - * @brief TIM1 compare interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM1_CC_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - eicu_lld_serve_interrupt(&EICUD1); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_EICU_USE_TIM1 */ - -#if STM32_EICU_USE_TIM2 - -#if !defined(STM32_TIM2_HANDLER) -#error "STM32_TIM2_HANDLER not defined" -#endif -/** - * @brief TIM2 interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM2_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - eicu_lld_serve_interrupt(&EICUD2); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_EICU_USE_TIM2 */ - -#if STM32_EICU_USE_TIM3 -#if !defined(STM32_TIM3_HANDLER) -#error "STM32_TIM3_HANDLER not defined" -#endif -/** - * @brief TIM3 interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM3_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - eicu_lld_serve_interrupt(&EICUD3); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_EICU_USE_TIM3 */ - -#if STM32_EICU_USE_TIM4 -#if !defined(STM32_TIM4_HANDLER) -#error "STM32_TIM4_HANDLER not defined" -#endif -/** - * @brief TIM4 interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM4_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - eicu_lld_serve_interrupt(&EICUD4); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_EICU_USE_TIM4 */ - -#if STM32_EICU_USE_TIM5 -#if !defined(STM32_TIM5_HANDLER) -#error "STM32_TIM5_HANDLER not defined" -#endif -/** - * @brief TIM5 interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM5_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - eicu_lld_serve_interrupt(&EICUD5); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_EICU_USE_TIM5 */ - -#if STM32_EICU_USE_TIM8 -#if !defined(STM32_TIM8_UP_HANDLER) -#error "STM32_TIM8_UP_HANDLER not defined" -#endif -/** - * @brief TIM8 compare interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - eicu_lld_serve_interrupt(&EICUD8); - - OSAL_IRQ_EPILOGUE(); -} - -#if !defined(STM32_TIM8_CC_HANDLER) -#error "STM32_TIM8_CC_HANDLER not defined" -#endif -/** - * @brief TIM8 compare interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM8_CC_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - eicu_lld_serve_interrupt(&EICUD8); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_EICU_USE_TIM8 */ - -#if STM32_EICU_USE_TIM9 -#if !defined(STM32_TIM9_HANDLER) -#error "STM32_TIM9_HANDLER not defined" -#endif -/** - * @brief TIM9 interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM9_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - eicu_lld_serve_interrupt(&EICUD9); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_EICU_USE_TIM9 */ - -#if STM32_EICU_USE_TIM12 -#if !defined(STM32_TIM12_HANDLER) -#error "STM32_TIM12_HANDLER not defined" -#endif -/** - * @brief TIM12 interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM12_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - eicu_lld_serve_interrupt(&EICUD12); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_EICU_USE_TIM12 */ - -#if STM32_EICU_USE_TIM10 -#if !defined(STM32_TIM10_HANDLER) -#error "STM32_TIM10_HANDLER not defined" -#endif -/** - * @brief TIM10 interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM10_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - eicu_lld_serve_interrupt(&EICUD10); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_EICU_USE_TIM10 */ - -#if STM32_EICU_USE_TIM11 -#if !defined(STM32_TIM11_HANDLER) -#error "STM32_TIM11_HANDLER not defined" -#endif -/** - * @brief TIM11 interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM11_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - eicu_lld_serve_interrupt(&EICUD11); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_EICU_USE_TIM11 */ - -#if STM32_EICU_USE_TIM13 -#if !defined(STM32_TIM13_HANDLER) -#error "STM32_TIM13_HANDLER not defined" -#endif -/** - * @brief TIM13 interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM13_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - eicu_lld_serve_interrupt(&EICUD13); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_EICU_USE_TIM13 */ - -#if STM32_EICU_USE_TIM14 -#if !defined(STM32_TIM14_HANDLER) -#error "STM32_TIM14_HANDLER not defined" -#endif -/** - * @brief TIM14 interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM14_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - eicu_lld_serve_interrupt(&EICUD14); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_EICU_USE_TIM14 */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level EICU driver initialization. - * - * @notapi - */ -void eicu_lld_init(void) { -#if STM32_EICU_USE_TIM1 - /* Driver initialization.*/ - eicuObjectInit(&EICUD1); - EICUD1.tim = STM32_TIM1; -#endif - -#if STM32_EICU_USE_TIM2 - /* Driver initialization.*/ - eicuObjectInit(&EICUD2); - EICUD2.tim = STM32_TIM2; -#endif - -#if STM32_EICU_USE_TIM3 - /* Driver initialization.*/ - eicuObjectInit(&EICUD3); - EICUD3.tim = STM32_TIM3; -#endif - -#if STM32_EICU_USE_TIM4 - /* Driver initialization.*/ - eicuObjectInit(&EICUD4); - EICUD4.tim = STM32_TIM4; -#endif - -#if STM32_EICU_USE_TIM5 - /* Driver initialization.*/ - eicuObjectInit(&EICUD5); - EICUD5.tim = STM32_TIM5; -#endif - -#if STM32_EICU_USE_TIM8 - /* Driver initialization.*/ - eicuObjectInit(&EICUD8); - EICUD8.tim = STM32_TIM8; -#endif - -#if STM32_EICU_USE_TIM9 - /* Driver initialization.*/ - eicuObjectInit(&EICUD9); - EICUD9.tim = STM32_TIM9; -#endif - -#if STM32_EICU_USE_TIM12 - /* Driver initialization.*/ - eicuObjectInit(&EICUD12); - EICUD12.tim = STM32_TIM12; -#endif - -#if STM32_EICU_USE_TIM10 - /* Driver initialization.*/ - eicuObjectInit(&EICUD10); - EICUD10.tim = STM32_TIM10; -#endif - -#if STM32_EICU_USE_TIM11 - /* Driver initialization.*/ - eicuObjectInit(&EICUD11); - EICUD11.tim = STM32_TIM11; -#endif - -#if STM32_EICU_USE_TIM13 - /* Driver initialization.*/ - eicuObjectInit(&EICUD13); - EICUD13.tim = STM32_TIM13; -#endif - -#if STM32_EICU_USE_TIM14 - /* Driver initialization.*/ - eicuObjectInit(&EICUD14); - EICUD14.tim = STM32_TIM14; -#endif -} - -/** - * @brief Configures and activates the EICU peripheral. - * - * @param[in] eicup Pointer to the @p EICUDriver object - * - * @notapi - */ -void eicu_lld_start(EICUDriver *eicup) { - uint32_t psc; - size_t ch; - - osalDbgAssert((eicup->config->iccfgp[0] != NULL) || - (eicup->config->iccfgp[1] != NULL) || - (eicup->config->iccfgp[2] != NULL) || - (eicup->config->iccfgp[3] != NULL), - "invalid input configuration"); - - if (eicup->state == EICU_STOP) { - /* Clock activation and timer reset.*/ -#if STM32_EICU_USE_TIM1 - if (&EICUD1 == eicup) { - rccEnableTIM1(FALSE); - rccResetTIM1(); - nvicEnableVector(STM32_TIM1_UP_NUMBER, STM32_EICU_TIM1_IRQ_PRIORITY); - nvicEnableVector(STM32_TIM1_CC_NUMBER, STM32_EICU_TIM1_IRQ_PRIORITY); - eicup->channels = 4; -#if defined(STM32_TIM1CLK) - eicup->clock = STM32_TIM1CLK; -#else - eicup->clock = STM32_TIMCLK2; -#endif - } -#endif -#if STM32_EICU_USE_TIM2 - if (&EICUD2 == eicup) { - rccEnableTIM2(FALSE); - rccResetTIM2(); - nvicEnableVector(STM32_TIM2_NUMBER, STM32_EICU_TIM2_IRQ_PRIORITY); - eicup->channels = 4; - eicup->clock = STM32_TIMCLK1; - } -#endif -#if STM32_EICU_USE_TIM3 - if (&EICUD3 == eicup) { - rccEnableTIM3(FALSE); - rccResetTIM3(); - nvicEnableVector(STM32_TIM3_NUMBER, STM32_EICU_TIM3_IRQ_PRIORITY); - eicup->channels = 4; - eicup->clock = STM32_TIMCLK1; - } -#endif -#if STM32_EICU_USE_TIM4 - if (&EICUD4 == eicup) { - rccEnableTIM4(FALSE); - rccResetTIM4(); - nvicEnableVector(STM32_TIM4_NUMBER, STM32_EICU_TIM4_IRQ_PRIORITY); - eicup->channels = 4; - eicup->clock = STM32_TIMCLK1; - } -#endif -#if STM32_EICU_USE_TIM5 - if (&EICUD5 == eicup) { - rccEnableTIM5(FALSE); - rccResetTIM5(); - nvicEnableVector(STM32_TIM5_NUMBER, STM32_EICU_TIM5_IRQ_PRIORITY); - eicup->channels = 4; - eicup->clock = STM32_TIMCLK1; - } -#endif -#if STM32_EICU_USE_TIM8 - if (&EICUD8 == eicup) { - rccEnableTIM8(FALSE); - rccResetTIM8(); - nvicEnableVector(STM32_TIM8_UP_NUMBER, STM32_EICU_TIM8_IRQ_PRIORITY); - nvicEnableVector(STM32_TIM8_CC_NUMBER, STM32_EICU_TIM8_IRQ_PRIORITY); - eicup->channels = 4; -#if defined(STM32_TIM8CLK) - eicup->clock = STM32_TIM8CLK; -#else - eicup->clock = STM32_TIMCLK2; -#endif - } -#endif -#if STM32_EICU_USE_TIM9 - if (&EICUD9 == eicup) { - rccEnableTIM9(FALSE); - rccResetTIM9(); - nvicEnableVector(STM32_TIM9_NUMBER, STM32_EICU_TIM9_IRQ_PRIORITY); - eicup->channels = 2; - eicup->clock = STM32_TIMCLK2; - } -#endif -#if STM32_EICU_USE_TIM12 - if (&EICUD12 == eicup) { - rccEnableTIM12(FALSE); - rccResetTIM12(); - nvicEnableVector(STM32_TIM12_NUMBER, STM32_EICU_TIM12_IRQ_PRIORITY); - eicup->channels = 2; - eicup->clock = STM32_TIMCLK1; - } -#endif -#if STM32_EICU_USE_TIM10 - if (&EICUD10 == eicup) { - rccEnableTIM10(FALSE); - rccResetTIM10(); - nvicEnableVector(STM32_TIM10_NUMBER, STM32_EICU_TIM10_IRQ_PRIORITY); - eicup->channels = 1; - eicup->clock = STM32_TIMCLK2; - } -#endif -#if STM32_EICU_USE_TIM11 - if (&EICUD11 == eicup) { - rccEnableTIM11(FALSE); - rccResetTIM11(); - nvicEnableVector(STM32_TIM11_NUMBER, STM32_EICU_TIM11_IRQ_PRIORITY); - eicup->channels = 1; - eicup->clock = STM32_TIMCLK2; - } -#endif -#if STM32_EICU_USE_TIM13 - if (&EICUD13 == eicup) { - rccEnableTIM13(FALSE); - rccResetTIM13(); - nvicEnableVector(STM32_TIM13_NUMBER, STM32_EICU_TIM13_IRQ_PRIORITY); - eicup->channels = 1; - eicup->clock = STM32_TIMCLK1; - } -#endif -#if STM32_EICU_USE_TIM14 - if (&EICUD14 == eicup) { - rccEnableTIM14(FALSE); - rccResetTIM14(); - nvicEnableVector(STM32_TIM14_NUMBER, STM32_EICU_TIM14_IRQ_PRIORITY); - eicup->channels = 1; - eicup->clock = STM32_TIMCLK1; - } -#endif - } - else { - /* Driver re-configuration scenario, it must be stopped first.*/ - eicup->tim->CR1 = 0; /* Timer disabled. */ - eicup->tim->DIER = eicup->config->dier &/* DMA-related DIER settings. */ - ~STM32_TIM_DIER_IRQ_MASK; - eicup->tim->SR = 0; /* Clear eventual pending IRQs. */ - eicup->tim->CCR[0] = 0; /* Comparator 1 disabled. */ - eicup->tim->CCR[1] = 0; /* Comparator 2 disabled. */ - eicup->tim->CNT = 0; /* Counter reset to zero. */ - } - - /* Timer configuration.*/ - psc = (eicup->clock / eicup->config->frequency) - 1; - chDbgAssert((psc <= 0xFFFF) && - ((psc + 1) * eicup->config->frequency) == eicup->clock, - "invalid frequency"); - eicup->tim->PSC = (uint16_t)psc; - eicup->tim->ARR = (eicucnt_t)-1; - - /* Detect width.*/ - if (0xFFFFFFFF == eicup->tim->ARR) - eicup->width = EICU_WIDTH_32; - else if (0xFFFF == eicup->tim->ARR) - eicup->width = EICU_WIDTH_16; - else - osalSysHalt("Unsupported width"); - - /* Reset registers */ - eicup->tim->SMCR = 0; - eicup->tim->CCMR1 = 0; - if (eicup->channels > 2) - eicup->tim->CCMR2 = 0; - - /* clean channel structures and set pointers to channel configs */ - for (ch=0; chchannel[ch].last_active = 0; - eicup->channel[ch].last_idle = 0; - eicup->channel[ch].config = eicup->config->iccfgp[ch]; - eicup->channel[ch].state = EICU_CH_IDLE; - } - - /* TIM9 and TIM12 have only 2 channels.*/ - if (eicup->channels == 2) { - osalDbgCheck((eicup->config->iccfgp[2] == NULL) && - (eicup->config->iccfgp[3] == NULL)); - } - - /* TIM10, TIM11, TIM13 and TIM14 have only 1 channel.*/ - if (eicup->channels == 1) { - osalDbgCheck((eicup->config->iccfgp[1] == NULL) && - (eicup->config->iccfgp[2] == NULL) && - (eicup->config->iccfgp[3] == NULL)); - } - - start_channels(eicup); -} - -/** - * @brief Deactivates the EICU peripheral. - * - * @param[in] eicup Pointer to the @p EICUDriver object - * - * @notapi - */ -void eicu_lld_stop(EICUDriver *eicup) { - - if (eicup->state == EICU_READY) { - - /* Clock deactivation.*/ - eicup->tim->CR1 = 0; /* Timer disabled. */ - eicup->tim->DIER = 0; /* All IRQs disabled. */ - eicup->tim->SR = 0; /* Clear eventual pending IRQs. */ - -#if STM32_EICU_USE_TIM1 - if (&EICUD1 == eicup) { - nvicDisableVector(STM32_TIM1_UP_NUMBER); - nvicDisableVector(STM32_TIM1_CC_NUMBER); - rccDisableTIM1(FALSE); - } -#endif -#if STM32_EICU_USE_TIM2 - if (&EICUD2 == eicup) { - nvicDisableVector(STM32_TIM2_NUMBER); - rccDisableTIM2(FALSE); - } -#endif -#if STM32_EICU_USE_TIM3 - if (&EICUD3 == eicup) { - nvicDisableVector(STM32_TIM3_NUMBER); - rccDisableTIM3(FALSE); - } -#endif -#if STM32_EICU_USE_TIM4 - if (&EICUD4 == eicup) { - nvicDisableVector(STM32_TIM4_NUMBER); - rccDisableTIM4(FALSE); - } -#endif -#if STM32_EICU_USE_TIM5 - if (&EICUD5 == eicup) { - nvicDisableVector(STM32_TIM5_NUMBER); - rccDisableTIM5(FALSE); - } -#endif -#if STM32_EICU_USE_TIM8 - if (&EICUD8 == eicup) { - nvicDisableVector(STM32_TIM8_UP_NUMBER); - nvicDisableVector(STM32_TIM8_CC_NUMBER); - rccDisableTIM8(FALSE); - } -#endif -#if STM32_EICU_USE_TIM9 - if (&EICUD9 == eicup) { - nvicDisableVector(STM32_TIM9_NUMBER); - rccDisableTIM9(FALSE); - } -#endif -#if STM32_EICU_USE_TIM12 - if (&EICUD12 == eicup) { - nvicDisableVector(STM32_TIM12_NUMBER); - rccDisableTIM12(FALSE); - } -#endif - } -#if STM32_EICU_USE_TIM10 - if (&EICUD10 == eicup) { - nvicDisableVector(STM32_TIM10_NUMBER); - rccDisableTIM10(FALSE); - } -#endif -#if STM32_EICU_USE_TIM11 - if (&EICUD11 == eicup) { - nvicDisableVector(STM32_TIM11_NUMBER); - rccDisableTIM11(FALSE); - } -#endif -#if STM32_EICU_USE_TIM13 - if (&EICUD13 == eicup) { - nvicDisableVector(STM32_TIM13_NUMBER); - rccDisableTIM13(FALSE); - } -#endif -#if STM32_EICU_USE_TIM14 - if (&EICUD14 == eicup) { - nvicDisableVector(STM32_TIM14_NUMBER); - rccDisableTIM14(FALSE); - } -#endif -} - -/** - * @brief Enables the EICU. - * - * @param[in] eicup Pointer to the @p EICUDriver object - * - * @notapi - */ -void eicu_lld_enable(EICUDriver *eicup) { - - eicup->tim->EGR = STM32_TIM_EGR_UG; - eicup->tim->SR = 0; /* Clear pending IRQs (if any). */ - - if ((eicup->config->iccfgp[EICU_CHANNEL_1] != NULL) && - (eicup->config->iccfgp[EICU_CHANNEL_1]->capture_cb != NULL)) - eicup->tim->DIER |= STM32_TIM_DIER_CC1IE; - if ((eicup->config->iccfgp[EICU_CHANNEL_2] != NULL) && - (eicup->config->iccfgp[EICU_CHANNEL_2]->capture_cb != NULL)) - eicup->tim->DIER |= STM32_TIM_DIER_CC2IE; - if ((eicup->config->iccfgp[EICU_CHANNEL_3] != NULL) && - (eicup->config->iccfgp[EICU_CHANNEL_3]->capture_cb != NULL)) - eicup->tim->DIER |= STM32_TIM_DIER_CC3IE; - if ((eicup->config->iccfgp[EICU_CHANNEL_4] != NULL) && - (eicup->config->iccfgp[EICU_CHANNEL_4]->capture_cb != NULL)) - eicup->tim->DIER |= STM32_TIM_DIER_CC4IE; - - eicup->tim->CR1 = STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN; -} - -/** - * @brief Disables the EICU. - * - * @param[in] eicup Pointer to the @p EICUDriver object - * - * @notapi - */ -void eicu_lld_disable(EICUDriver *eicup) { - eicup->tim->CR1 = 0; /* Initially stopped. */ - eicup->tim->SR = 0; /* Clear pending IRQs (if any). */ - - /* All interrupts disabled.*/ - eicup->tim->DIER &= ~STM32_TIM_DIER_IRQ_MASK; -} - -#endif /* HAL_USE_EICU */ diff --git a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.h b/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.h deleted file mode 100644 index e72098effd..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.h +++ /dev/null @@ -1,554 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Rewritten by Emil Fresk (1/5 - 2014) for extended input capture - functionality. And fix for spurious callbacks in the interrupt handler. -*/ -/* - Improved by Uladzimir Pylinsky aka barthess (1/3 - 2015) for support of - 32-bit timers and timers with single capture/compare channels. -*/ - -#ifndef HAL_EICU_LLD_H -#define HAL_EICU_LLD_H - -#include "stm32_tim.h" - -#if (HAL_USE_EICU == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief EICUD1 driver enable switch. - * @details If set to @p TRUE the support for EICUD1 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_EICU_USE_TIM1) || defined(__DOXYGEN__) -#define STM32_EICU_USE_TIM1 FALSE -#endif - -/** - * @brief EICUD2 driver enable switch. - * @details If set to @p TRUE the support for EICUD2 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_EICU_USE_TIM2) || defined(__DOXYGEN__) -#define STM32_EICU_USE_TIM2 FALSE -#endif - -/** - * @brief EICUD3 driver enable switch. - * @details If set to @p TRUE the support for EICUD3 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_EICU_USE_TIM3) || defined(__DOXYGEN__) -#define STM32_EICU_USE_TIM3 FALSE -#endif - -/** - * @brief EICUD4 driver enable switch. - * @details If set to @p TRUE the support for EICUD4 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_EICU_USE_TIM4) || defined(__DOXYGEN__) -#define STM32_EICU_USE_TIM4 FALSE -#endif - -/** - * @brief EICUD5 driver enable switch. - * @details If set to @p TRUE the support for EICUD5 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_EICU_USE_TIM5) || defined(__DOXYGEN__) -#define STM32_EICU_USE_TIM5 FALSE -#endif - -/** - * @brief EICUD8 driver enable switch. - * @details If set to @p TRUE the support for EICUD8 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_EICU_USE_TIM8) || defined(__DOXYGEN__) -#define STM32_EICU_USE_TIM8 FALSE -#endif - -/** - * @brief EICUD9 driver enable switch. - * @details If set to @p TRUE the support for EICUD9 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_EICU_USE_TIM9) || defined(__DOXYGEN__) -#define STM32_EICU_USE_TIM9 FALSE -#endif - -/** - * @brief EICUD12 driver enable switch. - * @details If set to @p TRUE the support for EICUD12 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_EICU_USE_TIM12) || defined(__DOXYGEN__) -#define STM32_EICU_USE_TIM12 FALSE -#endif - -/** - * @brief EICUD1 interrupt priority level setting. - */ -#if !defined(STM32_EICU_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EICU_TIM1_IRQ_PRIORITY 7 -#endif - -/** - * @brief EICUD2 interrupt priority level setting. - */ -#if !defined(STM32_EICU_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EICU_TIM2_IRQ_PRIORITY 7 -#endif - -/** - * @brief EICUD3 interrupt priority level setting. - */ -#if !defined(STM32_EICU_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EICU_TIM3_IRQ_PRIORITY 7 -#endif - -/** - * @brief EICUD4 interrupt priority level setting. - */ -#if !defined(STM32_EICU_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EICU_TIM4_IRQ_PRIORITY 7 -#endif - -/** - * @brief EICUD5 interrupt priority level setting. - */ -#if !defined(STM32_EICU_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EICU_TIM5_IRQ_PRIORITY 7 -#endif - -/** - * @brief EICUD8 interrupt priority level setting. - */ -#if !defined(STM32_EICU_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EICU_TIM8_IRQ_PRIORITY 7 -#endif - -/** - * @brief EICUD9 interrupt priority level setting. - */ -#if !defined(STM32_EICU_TIM9_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EICU_TIM9_IRQ_PRIORITY 7 -#endif - -/** - * @brief EICUD12 interrupt priority level setting. - */ -#if !defined(STM32_EICU_TIM12_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EICU_TIM12_IRQ_PRIORITY 7 -#endif - -/** - * @brief EICUD10 interrupt priority level setting. - */ -#if !defined(STM32_EICU_TIM10_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EICU_TIM10_IRQ_PRIORITY 7 -#endif - -/** - * @brief EICUD11 interrupt priority level setting. - */ -#if !defined(STM32_EICU_TIM11_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EICU_TIM11_IRQ_PRIORITY 7 -#endif - -/** - * @brief EICUD13 interrupt priority level setting. - */ -#if !defined(STM32_EICU_TIM13_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EICU_TIM13_IRQ_PRIORITY 7 -#endif - -/** - * @brief EICUD14 interrupt priority level setting. - */ -#if !defined(STM32_EICU_TIM14_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EICU_TIM14_IRQ_PRIORITY 7 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_EICU_USE_TIM1 && !STM32_HAS_TIM1 -#error "TIM1 not present in the selected device" -#endif - -#if STM32_EICU_USE_TIM2 && !STM32_HAS_TIM2 -#error "TIM2 not present in the selected device" -#endif - -#if STM32_EICU_USE_TIM3 && !STM32_HAS_TIM3 -#error "TIM3 not present in the selected device" -#endif - -#if STM32_EICU_USE_TIM4 && !STM32_HAS_TIM4 -#error "TIM4 not present in the selected device" -#endif - -#if STM32_EICU_USE_TIM5 && !STM32_HAS_TIM5 -#error "TIM5 not present in the selected device" -#endif - -#if STM32_EICU_USE_TIM8 && !STM32_HAS_TIM8 -#error "TIM8 not present in the selected device" -#endif - -#if STM32_EICU_USE_TIM9 && !STM32_HAS_TIM9 -#error "TIM9 not present in the selected device" -#endif - -#if STM32_EICU_USE_TIM12 && !STM32_HAS_TIM12 -#error "TIM12 not present in the selected device" -#endif - -#if STM32_EICU_USE_TIM10 && !STM32_HAS_TIM10 -#error "TIM10 not present in the selected device" -#endif - -#if STM32_EICU_USE_TIM11 && !STM32_HAS_TIM11 -#error "TIM11 not present in the selected device" -#endif - -#if STM32_EICU_USE_TIM13 && !STM32_HAS_TIM13 -#error "TIM13 not present in the selected device" -#endif - -#if STM32_EICU_USE_TIM14 && !STM32_HAS_TIM14 -#error "TIM14 not present in the selected device" -#endif - -#if !STM32_EICU_USE_TIM1 && !STM32_EICU_USE_TIM2 && \ - !STM32_EICU_USE_TIM3 && !STM32_EICU_USE_TIM4 && \ - !STM32_EICU_USE_TIM5 && !STM32_EICU_USE_TIM8 && \ - !STM32_EICU_USE_TIM9 && !STM32_EICU_USE_TIM12 && \ - !STM32_EICU_USE_TIM10 && !STM32_EICU_USE_TIM11 && \ - !STM32_EICU_USE_TIM13 && !STM32_EICU_USE_TIM14 -#error "EICU driver activated but no TIM peripheral assigned" -#endif - -#if STM32_EICU_USE_TIM1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_EICU_TIM1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM1" -#endif - -#if STM32_EICU_USE_TIM2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_EICU_TIM2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM2" -#endif - -#if STM32_EICU_USE_TIM3 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_EICU_TIM3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM3" -#endif - -#if STM32_EICU_USE_TIM4 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_EICU_TIM4_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM4" -#endif - -#if STM32_EICU_USE_TIM5 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_EICU_TIM5_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM5" -#endif - -#if STM32_EICU_USE_TIM8 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_EICU_TIM8_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM8" -#endif - -#if STM32_EICU_USE_TIM9 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_EICU_TIM9_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM9" -#endif - -#if STM32_EICU_USE_TIM12 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_EICU_TIM12_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM12" -#endif - -#if STM32_EICU_USE_TIM10 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_EICU_TIM10_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM10" -#endif - -#if STM32_EICU_USE_TIM11 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_EICU_TIM11_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM11" -#endif - -#if STM32_EICU_USE_TIM13 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_EICU_TIM13_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM13" -#endif - -#if STM32_EICU_USE_TIM14 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_EICU_TIM14_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM14" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ -/** - * @brief Active level selector. - */ -typedef enum { - EICU_INPUT_ACTIVE_HIGH, /**< Trigger on rising edge. */ - EICU_INPUT_ACTIVE_LOW, /**< Trigger on falling edge. */ -} eicuactivelevel_t; - -/** - * @brief Input type selector. - */ -typedef enum { - /** - * @brief Measures time between consequent edges. - * @details Callback fires on every _active_ edge. - */ - EICU_INPUT_EDGE, - /** - * @brief Measures pulse width. - * @details Callback fires on _idle_ edge of pulse. - */ - EICU_INPUT_PULSE, - /** - * @brief Measures both period and width.. - * @details Callback fires on _active_ edge of pulse. - */ - EICU_INPUT_BOTH -} eicucapturemode_t; - -/** - * @brief Timer registers width in bits. - */ -typedef enum { - EICU_WIDTH_16, - EICU_WIDTH_32 -} eicutimerwidth_t; - -/** - * @brief EICU frequency type. - */ -typedef uint32_t eicufreq_t; - -/** - * @brief EICU counter type. - */ -typedef uint32_t eicucnt_t; - -/** - * @brief EICU captured width and (or) period. - */ -typedef struct { - /** - * @brief Pulse width. - */ - eicucnt_t width; - /** - * @brief Pulse period. - */ - eicucnt_t period; -} eicuresult_t; - -/** - * @brief EICU Capture Channel Config structure definition. - */ -typedef struct { - /** - * @brief Specifies the active level of the input signal. - */ - eicuactivelevel_t alvl; - /** - * @brief Specifies the channel capture mode. - */ - eicucapturemode_t mode; - /** - * @brief Capture event callback. Used for PWM width, pulse width and - * pulse period capture event. - */ - eicucallback_t capture_cb; -} EICUChannelConfig; - -/** - * @brief EICU Capture Channel structure definition. - */ -typedef struct { - /** - * @brief Channel state for the internal state machine. - */ - eicuchannelstate_t state; - /** - * @brief Cached value for pulse width calculation. - */ - eicucnt_t last_active; - /** - * @brief Cached value for period calculation. - */ - eicucnt_t last_idle; - /** - * @brief Pointer to Input Capture channel configuration. - */ - const EICUChannelConfig *config; - /** - * @brief CCR register pointer for faster access. - */ - volatile uint32_t *ccrp; -} EICUChannel; - -/** - * @brief EICU Config structure definition. - */ -typedef struct { - /** - * @brief Specifies the Timer clock in Hz. - */ - eicufreq_t frequency; - /** - * @brief Pointer to each Input Capture channel configuration. - * @note A NULL parameter indicates the channel as unused. - * @note In PWM mode, only Channel 1 OR Channel 2 may be used. - */ - const EICUChannelConfig *iccfgp[EICU_CHANNEL_ENUM_END]; - /** - * @brief TIM DIER register initialization data. - */ - uint32_t dier; -} EICUConfig; - -/** - * @brief EICU Driver structure definition - */ -struct EICUDriver { - /** - * @brief STM32 timer peripheral for Input Capture. - */ - stm32_tim_t *tim; - /** - * @brief Driver state for the internal state machine. - */ - eicustate_t state; - /** - * @brief Channels' data structures. - */ - EICUChannel channel[EICU_CHANNEL_ENUM_END]; - /** - * @brief Timer base clock. - */ - uint32_t clock; - /** - * @brief Number of available capture compare channels in timer. - */ - size_t channels; - /** - * @brief Timer registers width in bits. - */ - eicutimerwidth_t width; - /** - * @brief Pointer to configuration for the driver. - */ - const EICUConfig *config; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ -#if STM32_EICU_USE_TIM1 && !defined(__DOXYGEN__) -extern EICUDriver EICUD1; -#endif - -#if STM32_EICU_USE_TIM2 && !defined(__DOXYGEN__) -extern EICUDriver EICUD2; -#endif - -#if STM32_EICU_USE_TIM3 && !defined(__DOXYGEN__) -extern EICUDriver EICUD3; -#endif - -#if STM32_EICU_USE_TIM4 && !defined(__DOXYGEN__) -extern EICUDriver EICUD4; -#endif - -#if STM32_EICU_USE_TIM5 && !defined(__DOXYGEN__) -extern EICUDriver EICUD5; -#endif - -#if STM32_EICU_USE_TIM8 && !defined(__DOXYGEN__) -extern EICUDriver EICUD8; -#endif - -#if STM32_EICU_USE_TIM9 && !defined(__DOXYGEN__) -extern EICUDriver EICUD9; -#endif - -#if STM32_EICU_USE_TIM12 && !defined(__DOXYGEN__) -extern EICUDriver EICUD12; -#endif - -#if STM32_EICU_USE_TIM10 && !defined(__DOXYGEN__) -extern EICUDriver EICUD10; -#endif - -#if STM32_EICU_USE_TIM11 && !defined(__DOXYGEN__) -extern EICUDriver EICUD11; -#endif - -#if STM32_EICU_USE_TIM13 && !defined(__DOXYGEN__) -extern EICUDriver EICUD13; -#endif - -#if STM32_EICU_USE_TIM14 && !defined(__DOXYGEN__) -extern EICUDriver EICUD14; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void eicu_lld_init(void); - void eicu_lld_start(EICUDriver *eicup); - void eicu_lld_stop(EICUDriver *eicup); - void eicu_lld_enable(EICUDriver *eicup); - void eicu_lld_disable(EICUDriver *eicup); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_EICU */ - -#endif /* HAL_EICU_LLD_H */ diff --git a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c b/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c deleted file mode 100644 index 8eafa9e03d..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c +++ /dev/null @@ -1,295 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Martino Migliavacca - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file TIMv1/hal_qei_lld.c - * @brief STM32 QEI subsystem low level driver header. - * - * @addtogroup QEI - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_QEI == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief QEID1 driver identifier. - * @note The driver QEID1 allocates the complex timer TIM1 when enabled. - */ -#if STM32_QEI_USE_TIM1 || defined(__DOXYGEN__) -QEIDriver QEID1; -#endif - -/** - * @brief QEID2 driver identifier. - * @note The driver QEID1 allocates the timer TIM2 when enabled. - */ -#if STM32_QEI_USE_TIM2 || defined(__DOXYGEN__) -QEIDriver QEID2; -#endif - -/** - * @brief QEID3 driver identifier. - * @note The driver QEID1 allocates the timer TIM3 when enabled. - */ -#if STM32_QEI_USE_TIM3 || defined(__DOXYGEN__) -QEIDriver QEID3; -#endif - -/** - * @brief QEID4 driver identifier. - * @note The driver QEID4 allocates the timer TIM4 when enabled. - */ -#if STM32_QEI_USE_TIM4 || defined(__DOXYGEN__) -QEIDriver QEID4; -#endif - -/** - * @brief QEID5 driver identifier. - * @note The driver QEID5 allocates the timer TIM5 when enabled. - */ -#if STM32_QEI_USE_TIM5 || defined(__DOXYGEN__) -QEIDriver QEID5; -#endif - -/** - * @brief QEID8 driver identifier. - * @note The driver QEID8 allocates the timer TIM8 when enabled. - */ -#if STM32_QEI_USE_TIM8 || defined(__DOXYGEN__) -QEIDriver QEID8; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level QEI driver initialization. - * - * @notapi - */ -void qei_lld_init(void) { - -#if STM32_QEI_USE_TIM1 - /* Driver initialization.*/ - qeiObjectInit(&QEID1); - QEID1.tim = STM32_TIM1; -#endif - -#if STM32_QEI_USE_TIM2 - /* Driver initialization.*/ - qeiObjectInit(&QEID2); - QEID2.tim = STM32_TIM2; -#endif - -#if STM32_QEI_USE_TIM3 - /* Driver initialization.*/ - qeiObjectInit(&QEID3); - QEID3.tim = STM32_TIM3; -#endif - -#if STM32_QEI_USE_TIM4 - /* Driver initialization.*/ - qeiObjectInit(&QEID4); - QEID4.tim = STM32_TIM4; -#endif - -#if STM32_QEI_USE_TIM5 - /* Driver initialization.*/ - qeiObjectInit(&QEID5); - QEID5.tim = STM32_TIM5; -#endif - -#if STM32_QEI_USE_TIM8 - /* Driver initialization.*/ - qeiObjectInit(&QEID8); - QEID8.tim = STM32_TIM8; -#endif -} - -/** - * @brief Configures and activates the QEI peripheral. - * - * @param[in] qeip pointer to the @p QEIDriver object - * - * @notapi - */ -void qei_lld_start(QEIDriver *qeip) { - osalDbgAssert((qeip->config->min == 0) || (qeip->config->max == 0), - "only min/max set to 0 is supported"); - - if (qeip->state == QEI_STOP) { - /* Clock activation and timer reset.*/ -#if STM32_QEI_USE_TIM1 - if (&QEID1 == qeip) { - rccEnableTIM1(FALSE); - rccResetTIM1(); - } -#endif -#if STM32_QEI_USE_TIM2 - if (&QEID2 == qeip) { - rccEnableTIM2(FALSE); - rccResetTIM2(); - } -#endif -#if STM32_QEI_USE_TIM3 - if (&QEID3 == qeip) { - rccEnableTIM3(FALSE); - rccResetTIM3(); - } -#endif -#if STM32_QEI_USE_TIM4 - if (&QEID4 == qeip) { - rccEnableTIM4(FALSE); - rccResetTIM4(); - } -#endif - -#if STM32_QEI_USE_TIM5 - if (&QEID5 == qeip) { - rccEnableTIM5(FALSE); - rccResetTIM5(); - } -#endif -#if STM32_QEI_USE_TIM8 - if (&QEID8 == qeip) { - rccEnableTIM8(FALSE); - rccResetTIM8(); - } -#endif - } - /* Timer configuration.*/ - qeip->tim->CR1 = 0; /* Initially stopped. */ - qeip->tim->CR2 = 0; - qeip->tim->PSC = 0; - qeip->tim->DIER = 0; - qeip->tim->ARR = 0xFFFF; - - /* Set Capture Compare 1 and Capture Compare 2 as input. */ - qeip->tim->CCMR1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; - - if (qeip->config->mode == QEI_MODE_QUADRATURE) { - if (qeip->config->resolution == QEI_BOTH_EDGES) - qeip->tim->SMCR = TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0; - else - qeip->tim->SMCR = TIM_SMCR_SMS_0; - } else { - /* Direction/Clock mode. - * Direction input on TI1, Clock input on TI2. */ - qeip->tim->SMCR = TIM_SMCR_SMS_0; - } - - if (qeip->config->dirinv == QEI_DIRINV_TRUE) - qeip->tim->CCER = TIM_CCER_CC1E | TIM_CCER_CC1P | TIM_CCER_CC2E; - else - qeip->tim->CCER = TIM_CCER_CC1E | TIM_CCER_CC2E; -} - -/** - * @brief Deactivates the QEI peripheral. - * - * @param[in] qeip pointer to the @p QEIDriver object - * - * @notapi - */ -void qei_lld_stop(QEIDriver *qeip) { - - if (qeip->state == QEI_READY) { - qeip->tim->CR1 = 0; /* Timer disabled. */ - - /* Clock deactivation.*/ -#if STM32_QEI_USE_TIM1 - if (&QEID1 == qeip) { - rccDisableTIM1(FALSE); - } -#endif -#if STM32_QEI_USE_TIM2 - if (&QEID2 == qeip) { - rccDisableTIM2(FALSE); - } -#endif -#if STM32_QEI_USE_TIM3 - if (&QEID3 == qeip) { - rccDisableTIM3(FALSE); - } -#endif -#if STM32_QEI_USE_TIM4 - if (&QEID4 == qeip) { - rccDisableTIM4(FALSE); - } -#endif -#if STM32_QEI_USE_TIM5 - if (&QEID5 == qeip) { - rccDisableTIM5(FALSE); - } -#endif - } -#if STM32_QEI_USE_TIM8 - if (&QEID8 == qeip) { - rccDisableTIM8(FALSE); - } -#endif -} - -/** - * @brief Enables the input capture. - * - * @param[in] qeip pointer to the @p QEIDriver object - * - * @notapi - */ -void qei_lld_enable(QEIDriver *qeip) { - - qeip->tim->CR1 = TIM_CR1_CEN; /* Timer enabled. */ -} - -/** - * @brief Disables the input capture. - * - * @param[in] qeip pointer to the @p QEIDriver object - * - * @notapi - */ -void qei_lld_disable(QEIDriver *qeip) { - - qeip->tim->CR1 = 0; /* Timer disabled. */ -} - -#endif /* HAL_USE_QEI */ - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.h b/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.h deleted file mode 100644 index 950e9d276a..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.h +++ /dev/null @@ -1,414 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Martino Migliavacca - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file TIMv1/hal_qei_lld.h - * @brief STM32 QEI subsystem low level driver header. - * - * @addtogroup QEI - * @{ - */ - -#ifndef HAL_QEI_LLD_H -#define HAL_QEI_LLD_H - -#if (HAL_USE_QEI == TRUE) || defined(__DOXYGEN__) - -#include "stm32_tim.h" - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Mininum usable value for defining counter underflow - */ -#define QEI_COUNT_MIN (0) - -/** - * @brief Maximum usable value for defining counter overflow - */ -#define QEI_COUNT_MAX (65535) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief QEID1 driver enable switch. - * @details If set to @p TRUE the support for QEID1 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_QEI_USE_TIM1) || defined(__DOXYGEN__) -#define STM32_QEI_USE_TIM1 FALSE -#endif - -/** - * @brief QEID2 driver enable switch. - * @details If set to @p TRUE the support for QEID2 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_QEI_USE_TIM2) || defined(__DOXYGEN__) -#define STM32_QEI_USE_TIM2 FALSE -#endif - -/** - * @brief QEID3 driver enable switch. - * @details If set to @p TRUE the support for QEID3 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_QEI_USE_TIM3) || defined(__DOXYGEN__) -#define STM32_QEI_USE_TIM3 FALSE -#endif - -/** - * @brief QEID4 driver enable switch. - * @details If set to @p TRUE the support for QEID4 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_QEI_USE_TIM4) || defined(__DOXYGEN__) -#define STM32_QEI_USE_TIM4 FALSE -#endif - -/** - * @brief QEID5 driver enable switch. - * @details If set to @p TRUE the support for QEID5 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_QEI_USE_TIM5) || defined(__DOXYGEN__) -#define STM32_QEI_USE_TIM5 FALSE -#endif - -/** - * @brief QEID8 driver enable switch. - * @details If set to @p TRUE the support for QEID8 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_QEI_USE_TIM8) || defined(__DOXYGEN__) -#define STM32_QEI_USE_TIM8 FALSE -#endif - -/** - * @brief QEID1 interrupt priority level setting. - */ -#if !defined(STM32_QEI_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_QEI_TIM1_IRQ_PRIORITY 7 -#endif - -/** - * @brief QEID2 interrupt priority level setting. - */ -#if !defined(STM32_QEI_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_QEI_TIM2_IRQ_PRIORITY 7 -#endif - -/** - * @brief QEID3 interrupt priority level setting. - */ -#if !defined(STM32_QEI_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_QEI_TIM3_IRQ_PRIORITY 7 -#endif - -/** - * @brief QEID4 interrupt priority level setting. - */ -#if !defined(STM32_QEI_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_QEI_TIM4_IRQ_PRIORITY 7 -#endif - -/** - * @brief QEID5 interrupt priority level setting. - */ -#if !defined(STM32_QEI_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_QEI_TIM5_IRQ_PRIORITY 7 -#endif - -/** - * @brief QEID8 interrupt priority level setting. - */ -#if !defined(STM32_QEI_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_QEI_TIM8_IRQ_PRIORITY 7 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_QEI_USE_TIM1 && !STM32_HAS_TIM1 -#error "TIM1 not present in the selected device" -#endif - -#if STM32_QEI_USE_TIM2 && !STM32_HAS_TIM2 -#error "TIM2 not present in the selected device" -#endif - -#if STM32_QEI_USE_TIM3 && !STM32_HAS_TIM3 -#error "TIM3 not present in the selected device" -#endif - -#if STM32_QEI_USE_TIM4 && !STM32_HAS_TIM4 -#error "TIM4 not present in the selected device" -#endif - -#if STM32_QEI_USE_TIM5 && !STM32_HAS_TIM5 -#error "TIM5 not present in the selected device" -#endif - -#if STM32_QEI_USE_TIM8 && !STM32_HAS_TIM8 -#error "TIM8 not present in the selected device" -#endif - -#if !STM32_QEI_USE_TIM1 && !STM32_QEI_USE_TIM2 && \ - !STM32_QEI_USE_TIM3 && !STM32_QEI_USE_TIM4 && \ - !STM32_QEI_USE_TIM5 && !STM32_QEI_USE_TIM8 -#error "QEI driver activated but no TIM peripheral assigned" -#endif - -#if STM32_QEI_USE_TIM1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_QEI_TIM1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM1" -#endif - -#if STM32_QEI_USE_TIM2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_QEI_TIM2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM2" -#endif - -#if STM32_QEI_USE_TIM3 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_QEI_TIM3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM3" -#endif - -#if STM32_QEI_USE_TIM4 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_QEI_TIM4_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM4" -#endif - -#if STM32_QEI_USE_TIM5 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_QEI_TIM5_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM5" -#endif - -#if STM32_QEI_USE_TIM8 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_QEI_TIM8_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM8" -#endif - -#if QEI_USE_OVERFLOW_DISCARD -#error "QEI_USE_OVERFLOW_DISCARD not supported by this driver" -#endif - -#if QEI_USE_OVERFLOW_MINMAX -#error "QEI_USE_OVERFLOW_MINMAX not supported by this driver" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief QEI count mode. - */ -typedef enum { - QEI_MODE_QUADRATURE = 0, /**< Quadrature encoder mode. */ - QEI_MODE_DIRCLOCK = 1, /**< Direction/Clock mode. */ -} qeimode_t; - -/** - * @brief QEI resolution. - */ -typedef enum { - QEI_SINGLE_EDGE = 0, /**< Count only on edges from first channel. */ - QEI_BOTH_EDGES = 1, /**< Count on both edges (resolution doubles).*/ -} qeiresolution_t; - -/** - * @brief QEI direction inversion. - */ -typedef enum { - QEI_DIRINV_FALSE = 0, /**< Do not invert counter direction. */ - QEI_DIRINV_TRUE = 1, /**< Invert counter direction. */ -} qeidirinv_t; - -/** - * @brief QEI counter type. - */ -typedef int16_t qeicnt_t; - -/** - * @brief QEI delta type. - */ -typedef int32_t qeidelta_t; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief Count mode. - */ - qeimode_t mode; - /** - * @brief Resolution. - */ - qeiresolution_t resolution; - /** - * @brief Direction inversion. - */ - qeidirinv_t dirinv; - /** - * @brief Handling of counter overflow/underflow - * - * @details When overflow occurs, the counter value is updated - * according to: - * - QEI_OVERFLOW_DISCARD: - * discard the update value, counter doesn't change - */ - qeioverflow_t overflow; - /** - * @brief Min count value. - * - * @note If min == max, then QEI_COUNT_MIN is used. - * - * @note Only min set to 0 / QEI_COUNT_MIN is supported. - */ - qeicnt_t min; - /** - * @brief Max count value. - * - * @note If min == max, then QEI_COUNT_MAX is used. - * - * @note Only max set to 0 / QEI_COUNT_MAX is supported. - */ - qeicnt_t max; - /** - * @brief Notify of value change - * - * @note Called from ISR context. - */ - qeicallback_t notify_cb; - /** - * @brief Notify of overflow - * - * @note Overflow notification is performed after - * value changed notification. - * @note Called from ISR context. - */ - void (*overflow_cb)(QEIDriver *qeip, qeidelta_t delta); - /* End of the mandatory fields.*/ -} QEIConfig; - -/** - * @brief Structure representing an QEI driver. - */ -struct QEIDriver { - /** - * @brief Driver state. - */ - qeistate_t state; - /** - * @brief Last count value. - */ - qeicnt_t last; - /** - * @brief Current configuration data. - */ - const QEIConfig *config; -#if defined(QEI_DRIVER_EXT_FIELDS) - QEI_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the TIMx registers block. - */ - stm32_tim_t *tim; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Returns the counter value. - * - * @param[in] qeip pointer to the @p QEIDriver object - * @return The current counter value. - * - * @notapi - */ -#define qei_lld_get_count(qeip) ((qeip)->tim->CNT) - -/** - * @brief Set the counter value. - * - * @param[in] qeip pointer to the @p QEIDriver object - * @param[in] qeip counter value - * - * @notapi - */ -#define qei_lld_set_count(qeip, value) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_QEI_USE_TIM1 && !defined(__DOXYGEN__) -extern QEIDriver QEID1; -#endif - -#if STM32_QEI_USE_TIM2 && !defined(__DOXYGEN__) -extern QEIDriver QEID2; -#endif - -#if STM32_QEI_USE_TIM3 && !defined(__DOXYGEN__) -extern QEIDriver QEID3; -#endif - -#if STM32_QEI_USE_TIM4 && !defined(__DOXYGEN__) -extern QEIDriver QEID4; -#endif - -#if STM32_QEI_USE_TIM5 && !defined(__DOXYGEN__) -extern QEIDriver QEID5; -#endif - -#if STM32_QEI_USE_TIM8 && !defined(__DOXYGEN__) -extern QEIDriver QEID8; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void qei_lld_init(void); - void qei_lld_start(QEIDriver *qeip); - void qei_lld_stop(QEIDriver *qeip); - void qei_lld_enable(QEIDriver *qeip); - void qei_lld_disable(QEIDriver *qeip); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_QEI */ - -#endif /* HAL_QEI_LLD_H */ - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c b/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c deleted file mode 100644 index c55fae22ae..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c +++ /dev/null @@ -1,818 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - This file was derived from the ICU subsystem code, modified to achieve - timing measurements on 2 and/or 4 channel STM32 timers by Dave Camarillo. - */ -/* - Concepts and parts of this file have been contributed by Fabio Utzig and - Xo Wang. - */ - - -/** - * @file STM32/hal_timcap_lld.c - * @brief STM32 TIMCAP subsystem low level driver header. - * - * @addtogroup TIMCAP - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_TIMCAP || defined(__DOXYGEN__) - -#include "stm32_tim.h" -#include "hal_timcap.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief TIMCAPD1 driver identifier. - * @note The driver TIMCAPD1 allocates the complex timer TIM1 when enabled. - */ -#if STM32_TIMCAP_USE_TIM1 || defined(__DOXYGEN__) -TIMCAPDriver TIMCAPD1; -#endif - -/** - * @brief TIMCAPD2 driver identifier. - * @note The driver TIMCAPD1 allocates the timer TIM2 when enabled. - */ -#if STM32_TIMCAP_USE_TIM2 || defined(__DOXYGEN__) -TIMCAPDriver TIMCAPD2; -#endif - -/** - * @brief TIMCAPD3 driver identifier. - * @note The driver TIMCAPD1 allocates the timer TIM3 when enabled. - */ -#if STM32_TIMCAP_USE_TIM3 || defined(__DOXYGEN__) -TIMCAPDriver TIMCAPD3; -#endif - -/** - * @brief TIMCAPD4 driver identifier. - * @note The driver TIMCAPD4 allocates the timer TIM4 when enabled. - */ -#if STM32_TIMCAP_USE_TIM4 || defined(__DOXYGEN__) -TIMCAPDriver TIMCAPD4; -#endif - -/** - * @brief TIMCAPD5 driver identifier. - * @note The driver TIMCAPD5 allocates the timer TIM5 when enabled. - */ -#if STM32_TIMCAP_USE_TIM5 || defined(__DOXYGEN__) -TIMCAPDriver TIMCAPD5; -#endif - -/** - * @brief TIMCAPD8 driver identifier. - * @note The driver TIMCAPD8 allocates the timer TIM8 when enabled. - */ -#if STM32_TIMCAP_USE_TIM8 || defined(__DOXYGEN__) -TIMCAPDriver TIMCAPD8; -#endif - -/** - * @brief TIMCAPD9 driver identifier. - * @note The driver TIMCAPD9 allocates the timer TIM9 when enabled. - */ -#if STM32_TIMCAP_USE_TIM9 || defined(__DOXYGEN__) -TIMCAPDriver TIMCAPD9; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - - -/** - * @brief Returns the maximum channel number for the respective TIMCAP driver. - * Note: different timer perepherials on the STM32 have between 1 and 4 - * CCR registers. - * - * @param[in] timcapp pointer to the @p TIMCAPDriver object - */ -static timcapchannel_t timcap_get_max_timer_channel(const TIMCAPDriver *timcapp) { - //Choose a sane default value -#if STM32_TIMCAP_USE_TIM1 || defined(__DOXYGEN__) - if( timcapp == &TIMCAPD1 ) { - return(TIMCAP_CHANNEL_4); - } -#endif - -#if STM32_TIMCAP_USE_TIM2 || defined(__DOXYGEN__) - if( timcapp == &TIMCAPD2 ) { - return(TIMCAP_CHANNEL_4); - } -#endif - -#if STM32_TIMCAP_USE_TIM3 || defined(__DOXYGEN__) - if( timcapp == &TIMCAPD3 ) { - return(TIMCAP_CHANNEL_4); - } -#endif - -#if STM32_TIMCAP_USE_TIM4 || defined(__DOXYGEN__) - if( timcapp == &TIMCAPD4 ) { - return(TIMCAP_CHANNEL_4); - } -#endif - -#if STM32_TIMCAP_USE_TIM5 || defined(__DOXYGEN__) - if( timcapp == &TIMCAPD5 ) { - return(TIMCAP_CHANNEL_4); - } -#endif - -#if STM32_TIMCAP_USE_TIM8 || defined(__DOXYGEN__) - if( timcapp == &TIMCAPD8 ) { - return(TIMCAP_CHANNEL_4); - } -#endif - -#if STM32_TIMCAP_USE_TIM9 || defined(__DOXYGEN__) - if( timcapp == &TIMCAPD9 ) { - return(TIMCAP_CHANNEL_2); - } -#endif - - /*Return a conservative default value.*/ - return(TIMCAP_CHANNEL_1); -} - - -/** - * @brief Returns the maximum value for the ARR register of a given timer. - * - * @param[in] timcapp pointer to the @p TIMCAPDriver object - */ -static uint32_t timcap_get_max_arr(const TIMCAPDriver *timcapp) { - //Choose a sane default value -#if STM32_TIMCAP_USE_TIM1 || defined(__DOXYGEN__) - if( timcapp == &TIMCAPD1 ) { - return(UINT16_MAX); - } -#endif - -#if STM32_TIMCAP_USE_TIM2 || defined(__DOXYGEN__) - if( timcapp == &TIMCAPD2 ) { - return(UINT32_MAX); - } -#endif - -#if STM32_TIMCAP_USE_TIM3 || defined(__DOXYGEN__) - if( timcapp == &TIMCAPD3 ) { - return(UINT16_MAX); - } -#endif - -#if STM32_TIMCAP_USE_TIM4 || defined(__DOXYGEN__) - if( timcapp == &TIMCAPD4 ) { - return(UINT16_MAX); - } -#endif - -#if STM32_TIMCAP_USE_TIM5 || defined(__DOXYGEN__) - if( timcapp == &TIMCAPD5 ) { - return(UINT32_MAX); - } -#endif - -#if STM32_TIMCAP_USE_TIM8 || defined(__DOXYGEN__) - if( timcapp == &TIMCAPD8 ) { - return(UINT16_MAX); - } -#endif - -#if STM32_TIMCAP_USE_TIM9 || defined(__DOXYGEN__) - if( timcapp == &TIMCAPD9 ) { - return(UINT16_MAX); - } -#endif - - /*Return a conservative default value.*/ - return(UINT16_MAX); -} - -/** - * @brief Shared IRQ handler. - * - * @param[in] timcapp pointer to the @p TIMCAPDriver object - */ -static void timcap_lld_serve_interrupt(TIMCAPDriver *timcapp) { - uint16_t sr; - - sr = timcapp->tim->SR; - sr &= timcapp->tim->DIER & STM32_TIM_DIER_IRQ_MASK; - timcapp->tim->SR = ~sr; - - if ((sr & STM32_TIM_SR_CC1IF) != 0 && timcapp->config->capture_cb_array[TIMCAP_CHANNEL_1] != NULL ) - _timcap_isr_invoke_channel1_cb(timcapp); - - if ((sr & STM32_TIM_SR_CC2IF) != 0 && timcapp->config->capture_cb_array[TIMCAP_CHANNEL_2] != NULL ) - _timcap_isr_invoke_channel2_cb(timcapp); - - if ((sr & STM32_TIM_SR_CC3IF) != 0 && timcapp->config->capture_cb_array[TIMCAP_CHANNEL_3] != NULL ) - _timcap_isr_invoke_channel3_cb(timcapp); - - if ((sr & STM32_TIM_SR_CC4IF) != 0 && timcapp->config->capture_cb_array[TIMCAP_CHANNEL_4] != NULL ) - _timcap_isr_invoke_channel4_cb(timcapp); - - if ((sr & STM32_TIM_SR_UIF) != 0 && timcapp->config->overflow_cb != NULL) - _timcap_isr_invoke_overflow_cb(timcapp); -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if STM32_TIMCAP_USE_TIM1 -#if !defined(STM32_TIM1_UP_HANDLER) -#error "STM32_TIM1_UP_HANDLER not defined" -#endif -/** - * @brief TIM1 compare interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) { - - CH_IRQ_PROLOGUE(); - - timcap_lld_serve_interrupt(&TIMCAPD1); - - CH_IRQ_EPILOGUE(); -} - -#if !defined(STM32_TIM1_CC_HANDLER) -#error "STM32_TIM1_CC_HANDLER not defined" -#endif -/** - * @brief TIM1 compare interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM1_CC_HANDLER) { - - CH_IRQ_PROLOGUE(); - - timcap_lld_serve_interrupt(&TIMCAPD1); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_TIMCAP_USE_TIM1 */ - -#if STM32_TIMCAP_USE_TIM2 -#if !defined(STM32_TIM2_HANDLER) -#error "STM32_TIM2_HANDLER not defined" -#endif -/** - * @brief TIM2 interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM2_HANDLER) { - - CH_IRQ_PROLOGUE(); - - timcap_lld_serve_interrupt(&TIMCAPD2); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_TIMCAP_USE_TIM2 */ - -#if STM32_TIMCAP_USE_TIM3 -#if !defined(STM32_TIM3_HANDLER) -#error "STM32_TIM3_HANDLER not defined" -#endif -/** - * @brief TIM3 interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM3_HANDLER) { - - CH_IRQ_PROLOGUE(); - - timcap_lld_serve_interrupt(&TIMCAPD3); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_TIMCAP_USE_TIM3 */ - -#if STM32_TIMCAP_USE_TIM4 -#if !defined(STM32_TIM4_HANDLER) -#error "STM32_TIM4_HANDLER not defined" -#endif -/** - * @brief TIM4 interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM4_HANDLER) { - - CH_IRQ_PROLOGUE(); - - timcap_lld_serve_interrupt(&TIMCAPD4); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_TIMCAP_USE_TIM4 */ - -#if STM32_TIMCAP_USE_TIM5 -#if !defined(STM32_TIM5_HANDLER) -#error "STM32_TIM5_HANDLER not defined" -#endif -/** - * @brief TIM5 interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM5_HANDLER) { - - CH_IRQ_PROLOGUE(); - - timcap_lld_serve_interrupt(&TIMCAPD5); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_TIMCAP_USE_TIM5 */ - -#if STM32_TIMCAP_USE_TIM8 -#if !defined(STM32_TIM8_UP_HANDLER) -#error "STM32_TIM8_UP_HANDLER not defined" -#endif -/** - * @brief TIM8 compare interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) { - - CH_IRQ_PROLOGUE(); - - timcap_lld_serve_interrupt(&TIMCAPD8); - - CH_IRQ_EPILOGUE(); -} - -#if !defined(STM32_TIM8_CC_HANDLER) -#error "STM32_TIM8_CC_HANDLER not defined" -#endif -/** - * @brief TIM8 compare interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM8_CC_HANDLER) { - - CH_IRQ_PROLOGUE(); - - timcap_lld_serve_interrupt(&TIMCAPD8); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_TIMCAP_USE_TIM8 */ - -#if STM32_TIMCAP_USE_TIM9 -#if !defined(STM32_TIM9_HANDLER) -#error "STM32_TIM9_HANDLER not defined" -#endif -/** - * @brief TIM9 interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM9_HANDLER) { - - CH_IRQ_PROLOGUE(); - - timcap_lld_serve_interrupt(&TIMCAPD9); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_TIMCAP_USE_TIM9 */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level TIMCAP driver initialization. - * - * @notapi - */ -void timcap_lld_init(void) { - -#if STM32_TIMCAP_USE_TIM1 - /* Driver initialization.*/ - timcapObjectInit(&TIMCAPD1); - TIMCAPD1.tim = STM32_TIM1; -#endif - -#if STM32_TIMCAP_USE_TIM2 - /* Driver initialization.*/ - timcapObjectInit(&TIMCAPD2); - TIMCAPD2.tim = STM32_TIM2; -#endif - -#if STM32_TIMCAP_USE_TIM3 - /* Driver initialization.*/ - timcapObjectInit(&TIMCAPD3); - TIMCAPD3.tim = STM32_TIM3; -#endif - -#if STM32_TIMCAP_USE_TIM4 - /* Driver initialization.*/ - timcapObjectInit(&TIMCAPD4); - TIMCAPD4.tim = STM32_TIM4; -#endif - -#if STM32_TIMCAP_USE_TIM5 - /* Driver initialization.*/ - timcapObjectInit(&TIMCAPD5); - TIMCAPD5.tim = STM32_TIM5; -#endif - -#if STM32_TIMCAP_USE_TIM8 - /* Driver initialization.*/ - timcapObjectInit(&TIMCAPD8); - TIMCAPD8.tim = STM32_TIM8; -#endif - -#if STM32_TIMCAP_USE_TIM9 - /* Driver initialization.*/ - timcapObjectInit(&TIMCAPD9); - TIMCAPD9.tim = STM32_TIM9; -#endif -} - -/** - * @brief Configures and activates the TIMCAP peripheral. - * - * @param[in] timcapp pointer to the @p TIMCAPDriver object - * - * @notapi - */ -void timcap_lld_start(TIMCAPDriver *timcapp) { - uint32_t psc; - - const timcapchannel_t tim_max_channel = timcap_get_max_timer_channel(timcapp); - - if (timcapp->state == TIMCAP_STOP) { - /* Clock activation and timer reset.*/ -#if STM32_TIMCAP_USE_TIM1 - if (&TIMCAPD1 == timcapp) { - rccEnableTIM1(FALSE); - rccResetTIM1(); - nvicEnableVector(STM32_TIM1_UP_NUMBER, STM32_TIMCAP_TIM1_IRQ_PRIORITY); - nvicEnableVector(STM32_TIM1_CC_NUMBER, STM32_TIMCAP_TIM1_IRQ_PRIORITY); -#if defined(STM32_TIM1CLK) - timcapp->clock = STM32_TIM1CLK; -#else - timcapp->clock = STM32_TIMCLK2; -#endif - } -#endif -#if STM32_TIMCAP_USE_TIM2 - if (&TIMCAPD2 == timcapp) { - rccEnableTIM2(FALSE); - rccResetTIM2(); - nvicEnableVector(STM32_TIM2_NUMBER, STM32_TIMCAP_TIM2_IRQ_PRIORITY); - timcapp->clock = STM32_TIMCLK1; - } -#endif -#if STM32_TIMCAP_USE_TIM3 - if (&TIMCAPD3 == timcapp) { - rccEnableTIM3(FALSE); - rccResetTIM3(); - nvicEnableVector(STM32_TIM3_NUMBER, STM32_TIMCAP_TIM3_IRQ_PRIORITY); - timcapp->clock = STM32_TIMCLK1; - } -#endif -#if STM32_TIMCAP_USE_TIM4 - if (&TIMCAPD4 == timcapp) { - rccEnableTIM4(FALSE); - rccResetTIM4(); - nvicEnableVector(STM32_TIM4_NUMBER, STM32_TIMCAP_TIM4_IRQ_PRIORITY); - timcapp->clock = STM32_TIMCLK1; - } -#endif -#if STM32_TIMCAP_USE_TIM5 - if (&TIMCAPD5 == timcapp) { - rccEnableTIM5(FALSE); - rccResetTIM5(); - nvicEnableVector(STM32_TIM5_NUMBER, STM32_TIMCAP_TIM5_IRQ_PRIORITY); - timcapp->clock = STM32_TIMCLK1; - } -#endif -#if STM32_TIMCAP_USE_TIM8 - if (&TIMCAPD8 == timcapp) { - rccEnableTIM8(FALSE); - rccResetTIM8(); - nvicEnableVector(STM32_TIM8_UP_NUMBER, STM32_TIMCAP_TIM8_IRQ_PRIORITY); - nvicEnableVector(STM32_TIM8_CC_NUMBER, STM32_TIMCAP_TIM8_IRQ_PRIORITY); -#if defined(STM32_TIM8CLK) - timcapp->clock = STM32_TIM8CLK; -#else - timcapp->clock = STM32_TIMCLK2; -#endif - } -#endif -#if STM32_TIMCAP_USE_TIM9 - if (&TIMCAPD9 == timcapp) { - rccEnableTIM9(FALSE); - rccResetTIM9(); - nvicEnableVector(STM32_TIM9_NUMBER, STM32_TIMCAP_TIM9_IRQ_PRIORITY); - timcapp->clock = STM32_TIMCLK1; - } -#endif - } - else { - /* Driver re-configuration scenario, it must be stopped first.*/ - timcapp->tim->CR1 = 0; /* Timer disabled. */ - timcapp->tim->DIER = timcapp->config->dier &/* DMA-related DIER settings. */ - ~STM32_TIM_DIER_IRQ_MASK; - timcapp->tim->SR = 0; /* Clear eventual pending IRQs. */ - timcapp->tim->CCR[0] = 0; /* Comparator 1 disabled. */ - timcapp->tim->CCR[1] = 0; /* Comparator 2 disabled. */ - if( tim_max_channel >= TIMCAP_CHANNEL_3 ) - timcapp->tim->CCR[2] = 0; /* Comparator 3 disabled. */ - if( tim_max_channel >= TIMCAP_CHANNEL_4 ) - timcapp->tim->CCR[3] = 0; /* Comparator 4 disabled. */ - timcapp->tim->CNT = 0; /* Counter reset to zero. */ - } - - /* Timer configuration.*/ - psc = (timcapp->clock / timcapp->config->frequency) - 1; - osalDbgAssert((psc <= 0xFFFF) && - ((psc + 1) * timcapp->config->frequency) == timcapp->clock, - "invalid frequency"); - timcapp->tim->PSC = (uint16_t)psc; - timcapp->tim->ARR = timcap_get_max_arr(timcapp); - - timcapp->tim->CCMR1 = 0; - timcapp->tim->CCMR2 = 0; - timcapp->tim->CCER = 0; - - timcapchannel_t chan = TIMCAP_CHANNEL_1; - - /*go through each non-NULL callback channel and enable the capture register on rising/falling edge*/ - for( chan = TIMCAP_CHANNEL_1; chan <= tim_max_channel; chan++ ) { - if( timcapp->config->capture_cb_array[chan] == NULL ) { - continue; - } - - switch (chan) { - case TIMCAP_CHANNEL_1: - /*CCMR1_CC1S = 01 = CH1 Input on TI1.*/ - timcapp->tim->CCMR1 |= STM32_TIM_CCMR1_CC1S(1); - break; - case TIMCAP_CHANNEL_2: - /*CCMR1_CC2S = 10 = CH2 Input on TI1.*/ - timcapp->tim->CCMR1 |= STM32_TIM_CCMR1_CC2S(1); - break; - case TIMCAP_CHANNEL_3: - timcapp->tim->CCMR2 |= STM32_TIM_CCMR2_CC3S(1); - break; - case TIMCAP_CHANNEL_4: - timcapp->tim->CCMR2 |= STM32_TIM_CCMR2_CC4S(1); - break; - } - - /* The CCER settings depend on the selected trigger mode. - TIMCAP_INPUT_DISABLED: Input not used. - TIMCAP_INPUT_ACTIVE_HIGH: Active on rising edge, idle on falling edge. - TIMCAP_INPUT_ACTIVE_LOW: Active on falling edge, idle on rising edge.*/ - if (timcapp->config->modes[chan] == TIMCAP_INPUT_ACTIVE_HIGH) { - switch (chan) { - case TIMCAP_CHANNEL_1: - timcapp->tim->CCER |= STM32_TIM_CCER_CC1E; - break; - case TIMCAP_CHANNEL_2: - timcapp->tim->CCER |= STM32_TIM_CCER_CC2E; - break; - case TIMCAP_CHANNEL_3: - timcapp->tim->CCER |= STM32_TIM_CCER_CC3E; - break; - case TIMCAP_CHANNEL_4: - timcapp->tim->CCER |= STM32_TIM_CCER_CC4E; - break; - } - } - else if (timcapp->config->modes[chan] == TIMCAP_INPUT_ACTIVE_LOW) { - switch (chan) { - case TIMCAP_CHANNEL_1: - timcapp->tim->CCER |= STM32_TIM_CCER_CC1E | STM32_TIM_CCER_CC1P; - break; - case TIMCAP_CHANNEL_2: - timcapp->tim->CCER |= STM32_TIM_CCER_CC2E | STM32_TIM_CCER_CC2P; - break; - case TIMCAP_CHANNEL_3: - timcapp->tim->CCER |= STM32_TIM_CCER_CC3E | STM32_TIM_CCER_CC3P; - break; - case TIMCAP_CHANNEL_4: - timcapp->tim->CCER |= STM32_TIM_CCER_CC4E | STM32_TIM_CCER_CC4P; - break; - } - } - else { - switch (chan) { - case TIMCAP_CHANNEL_1: - timcapp->tim->CCER &= ~STM32_TIM_CCER_CC1E; - break; - case TIMCAP_CHANNEL_2: - timcapp->tim->CCER &= ~STM32_TIM_CCER_CC2E; - break; - case TIMCAP_CHANNEL_3: - timcapp->tim->CCER &= ~STM32_TIM_CCER_CC3E; - break; - case TIMCAP_CHANNEL_4: - timcapp->tim->CCER &= ~STM32_TIM_CCER_CC4E; - break; - } - } - /* Direct pointers to the capture registers in order to make reading - data faster from within callbacks.*/ - timcapp->ccr_p[chan] = &timcapp->tim->CCR[chan]; - } - - /* SMCR_TS = 101, input is TI1FP1.*/ - timcapp->tim->SMCR = STM32_TIM_SMCR_TS(5); -} - -/** - * @brief Deactivates the TIMCAP peripheral. - * - * @param[in] timcapp pointer to the @p TIMCAPDriver object - * - * @notapi - */ -void timcap_lld_stop(TIMCAPDriver *timcapp) { - - if (timcapp->state == TIMCAP_READY) { - /* Clock deactivation.*/ - timcapp->tim->CR1 = 0; /* Timer disabled. */ - timcapp->tim->DIER = 0; /* All IRQs disabled. */ - timcapp->tim->SR = 0; /* Clear eventual pending IRQs. */ - -#if STM32_TIMCAP_USE_TIM1 - if (&TIMCAPD1 == timcapp) { - nvicDisableVector(STM32_TIM1_UP_NUMBER); - nvicDisableVector(STM32_TIM1_CC_NUMBER); - rccDisableTIM1(FALSE); - } -#endif -#if STM32_TIMCAP_USE_TIM2 - if (&TIMCAPD2 == timcapp) { - nvicDisableVector(STM32_TIM2_NUMBER); - rccDisableTIM2(FALSE); - } -#endif -#if STM32_TIMCAP_USE_TIM3 - if (&TIMCAPD3 == timcapp) { - nvicDisableVector(STM32_TIM3_NUMBER); - rccDisableTIM3(FALSE); - } -#endif -#if STM32_TIMCAP_USE_TIM4 - if (&TIMCAPD4 == timcapp) { - nvicDisableVector(STM32_TIM4_NUMBER); - rccDisableTIM4(FALSE); - } -#endif -#if STM32_TIMCAP_USE_TIM5 - if (&TIMCAPD5 == timcapp) { - nvicDisableVector(STM32_TIM5_NUMBER); - rccDisableTIM5(FALSE); - } -#endif -#if STM32_TIMCAP_USE_TIM8 - if (&TIMCAPD8 == timcapp) { - nvicDisableVector(STM32_TIM8_UP_NUMBER); - nvicDisableVector(STM32_TIM8_CC_NUMBER); - rccDisableTIM8(FALSE); - } -#endif -#if STM32_TIMCAP_USE_TIM9 - if (&TIMCAPD9 == timcapp) { - nvicDisableVector(STM32_TIM9_NUMBER); - rccDisableTIM9(FALSE); - } -#endif - } -} - -/** - * @brief Enables the input capture. - * - * @param[in] timcapp pointer to the @p TIMCAPDriver object - * - * @notapi - */ -void timcap_lld_enable(TIMCAPDriver *timcapp) { - - timcapp->tim->EGR |= STM32_TIM_EGR_UG; - timcapp->tim->SR = 0; /* Clear pending IRQs (if any). */ - - timcapchannel_t chan = TIMCAP_CHANNEL_1; - const timcapchannel_t tim_max_channel = timcap_get_max_timer_channel(timcapp); - for( chan = TIMCAP_CHANNEL_1; chan <= tim_max_channel; chan++ ) { - if( timcapp->config->capture_cb_array[chan] != NULL - && timcapp->config->modes[chan] != TIMCAP_INPUT_DISABLED ) { - switch (chan) { - case TIMCAP_CHANNEL_1: - timcapp->tim->DIER |= STM32_TIM_DIER_CC1IE; - break; - case TIMCAP_CHANNEL_2: - timcapp->tim->DIER |= STM32_TIM_DIER_CC2IE; - break; - case TIMCAP_CHANNEL_3: - timcapp->tim->DIER |= STM32_TIM_DIER_CC3IE; - break; - case TIMCAP_CHANNEL_4: - timcapp->tim->DIER |= STM32_TIM_DIER_CC4IE; - break; - } - } - } - - if (timcapp->config->overflow_cb != NULL) - timcapp->tim->DIER |= STM32_TIM_DIER_UIE; - - timcapp->tim->CR1 = STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN | timcapp->config->cr1; -} - -/** - * @brief Disables the input capture. - * - * @param[in] timcapp pointer to the @p TIMCAPDriver object - * - * @notapi - */ -void timcap_lld_disable(TIMCAPDriver *timcapp) { - - timcapp->tim->CR1 = 0; /* Initially stopped. */ - timcapp->tim->SR = 0; /* Clear pending IRQs (if any). */ - - /* All interrupts disabled.*/ - timcapp->tim->DIER &= ~STM32_TIM_DIER_IRQ_MASK; -} - -#endif /* HAL_USE_TIMCAP */ - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.h b/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.h deleted file mode 100644 index 643798a7c6..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.h +++ /dev/null @@ -1,390 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/timcap_lld.h - * @brief STM32 TIMCAP subsystem low level driver header. - * - * @addtogroup TIMCAP - * @{ - */ - -#ifndef HAL_TIMCAP_LLD_H_ -#define HAL_TIMCAP_LLD_H_ - -#include "ch.h" -#include "hal.h" -#include "stm32_tim.h" - - -#if HAL_USE_TIMCAP || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief TIMCAPD1 driver enable switch. - * @details If set to @p TRUE the support for TIMCAPD1 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_TIMCAP_USE_TIM1) || defined(__DOXYGEN__) -#define STM32_TIMCAP_USE_TIM1 FALSE -#endif - -/** - * @brief TIMCAPD2 driver enable switch. - * @details If set to @p TRUE the support for TIMCAPD2 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_TIMCAP_USE_TIM2) || defined(__DOXYGEN__) -#define STM32_TIMCAP_USE_TIM2 FALSE -#endif - -/** - * @brief TIMCAPD3 driver enable switch. - * @details If set to @p TRUE the support for TIMCAPD3 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_TIMCAP_USE_TIM3) || defined(__DOXYGEN__) -#define STM32_TIMCAP_USE_TIM3 FALSE -#endif - -/** - * @brief TIMCAPD4 driver enable switch. - * @details If set to @p TRUE the support for TIMCAPD4 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_TIMCAP_USE_TIM4) || defined(__DOXYGEN__) -#define STM32_TIMCAP_USE_TIM4 FALSE -#endif - -/** - * @brief TIMCAPD5 driver enable switch. - * @details If set to @p TRUE the support for TIMCAPD5 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_TIMCAP_USE_TIM5) || defined(__DOXYGEN__) -#define STM32_TIMCAP_USE_TIM5 FALSE -#endif - -/** - * @brief TIMCAPD8 driver enable switch. - * @details If set to @p TRUE the support for TIMCAPD8 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_TIMCAP_USE_TIM8) || defined(__DOXYGEN__) -#define STM32_TIMCAP_USE_TIM8 FALSE -#endif - -/** - * @brief TIMCAPD9 driver enable switch. - * @details If set to @p TRUE the support for TIMCAPD9 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_TIMCAP_USE_TIM9) || defined(__DOXYGEN__) -#define STM32_TIMCAP_USE_TIM9 FALSE -#endif - -/** - * @brief TIMCAPD1 interrupt priority level setting. - */ -#if !defined(STM32_TIMCAP_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_TIMCAP_TIM1_IRQ_PRIORITY 7 -#endif - -/** - * @brief TIMCAPD2 interrupt priority level setting. - */ -#if !defined(STM32_TIMCAP_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_TIMCAP_TIM2_IRQ_PRIORITY 7 -#endif - -/** - * @brief TIMCAPD3 interrupt priority level setting. - */ -#if !defined(STM32_TIMCAP_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_TIMCAP_TIM3_IRQ_PRIORITY 7 -#endif - -/** - * @brief TIMCAPD4 interrupt priority level setting. - */ -#if !defined(STM32_TIMCAP_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_TIMCAP_TIM4_IRQ_PRIORITY 7 -#endif - -/** - * @brief TIMCAPD5 interrupt priority level setting. - */ -#if !defined(STM32_TIMCAP_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_TIMCAP_TIM5_IRQ_PRIORITY 7 -#endif - -/** - * @brief TIMCAPD8 interrupt priority level setting. - */ -#if !defined(STM32_TIMCAP_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_TIMCAP_TIM8_IRQ_PRIORITY 7 -#endif - -/** - * @brief TIMCAPD9 interrupt priority level setting. - */ -#if !defined(STM32_TIMCAP_TIM9_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_TIMCAP_TIM9_IRQ_PRIORITY 7 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_TIMCAP_USE_TIM1 && !STM32_HAS_TIM1 -#error "TIM1 not present in the selected device" -#endif - -#if STM32_TIMCAP_USE_TIM2 && !STM32_HAS_TIM2 -#error "TIM2 not present in the selected device" -#endif - -#if STM32_TIMCAP_USE_TIM3 && !STM32_HAS_TIM3 -#error "TIM3 not present in the selected device" -#endif - -#if STM32_TIMCAP_USE_TIM4 && !STM32_HAS_TIM4 -#error "TIM4 not present in the selected device" -#endif - -#if STM32_TIMCAP_USE_TIM5 && !STM32_HAS_TIM5 -#error "TIM5 not present in the selected device" -#endif - -#if STM32_TIMCAP_USE_TIM8 && !STM32_HAS_TIM8 -#error "TIM8 not present in the selected device" -#endif - -#if STM32_TIMCAP_USE_TIM9 && !STM32_HAS_TIM9 -#error "TIM9 not present in the selected device" -#endif - -#if !STM32_TIMCAP_USE_TIM1 && !STM32_TIMCAP_USE_TIM2 && \ - !STM32_TIMCAP_USE_TIM3 && !STM32_TIMCAP_USE_TIM4 && \ - !STM32_TIMCAP_USE_TIM5 && !STM32_TIMCAP_USE_TIM8 && \ - !STM32_TIMCAP_USE_TIM9 -#error "TIMCAP driver activated but no TIM peripheral assigned" -#endif - -#if STM32_TIMCAP_USE_TIM1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_TIMCAP_TIM1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM1" -#endif - -#if STM32_TIMCAP_USE_TIM2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_TIMCAP_TIM2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM2" -#endif - -#if STM32_TIMCAP_USE_TIM3 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_TIMCAP_TIM3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM3" -#endif - -#if STM32_TIMCAP_USE_TIM4 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_TIMCAP_TIM4_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM4" -#endif - -#if STM32_TIMCAP_USE_TIM5 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_TIMCAP_TIM5_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM5" -#endif - -#if STM32_TIMCAP_USE_TIM8 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_TIMCAP_TIM8_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM8" -#endif - -#if STM32_TIMCAP_USE_TIM9 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_TIMCAP_TIM9_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM9" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief TIMCAP driver mode. - */ -typedef enum { - TIMCAP_INPUT_DISABLED = 0, - TIMCAP_INPUT_ACTIVE_HIGH = 1, /**< Trigger on rising edge. */ - TIMCAP_INPUT_ACTIVE_LOW = 2, /**< Trigger on falling edge. */ -} timcapmode_t; - -/** - * @brief TIMCAP frequency type. - */ -typedef uint32_t timcapfreq_t; - -/** - * @brief TIMCAP channel type. - */ -typedef enum { - TIMCAP_CHANNEL_1 = 0, /**< Use TIMxCH1. */ - TIMCAP_CHANNEL_2 = 1, /**< Use TIMxCH2. */ - TIMCAP_CHANNEL_3 = 2, /**< Use TIMxCH3. */ - TIMCAP_CHANNEL_4 = 3, /**< Use TIMxCH4. */ -} timcapchannel_t; - - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief Driver mode. - */ - timcapmode_t modes[4]; - /** - * @brief Timer clock in Hz. - * @note The low level can use assertions in order to catch invalid - * frequency specifications. - */ - timcapfreq_t frequency; - - /** - * @brief Callback when a capture occurs - */ - timcapcallback_t capture_cb_array[4]; - - /** - * @brief Callback for timer overflow. - */ - timcapcallback_t overflow_cb; - - /* End of the mandatory fields.*/ - - /** - * @brief TIM DIER register initialization data. - * @note The value of this field should normally be equal to zero. - * @note Only the DMA-related bits can be specified in this field. - */ - uint32_t dier; - - /** - * @brief TIM CR1 register initialization data. - * @note The value of this field should normally be equal to zero. - */ - uint32_t cr1; -} TIMCAPConfig; - -/** - * @brief Structure representing an TIMCAP driver. - */ -struct TIMCAPDriver { - /** - * @brief Driver state. - */ - timcapstate_t state; - /** - * @brief Current configuration data. - */ - const TIMCAPConfig *config; -#if defined(TIMCAP_DRIVER_EXT_FIELDS) - TIMCAP_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Timer base clock. - */ - uint32_t clock; - /** - * @brief Pointer to the TIMx registers block. - */ - stm32_tim_t *tim; - /** - * @brief CCR register used for capture. - */ - volatile uint32_t *ccr_p[4]; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -//FIXME document this -#define timcap_lld_get_ccr(timcapp, channel) (*((timcapp)->ccr_p[channel]) + 1) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_TIMCAP_USE_TIM1 && !defined(__DOXYGEN__) -extern TIMCAPDriver TIMCAPD1; -#endif - -#if STM32_TIMCAP_USE_TIM2 && !defined(__DOXYGEN__) -extern TIMCAPDriver TIMCAPD2; -#endif - -#if STM32_TIMCAP_USE_TIM3 && !defined(__DOXYGEN__) -extern TIMCAPDriver TIMCAPD3; -#endif - -#if STM32_TIMCAP_USE_TIM4 && !defined(__DOXYGEN__) -extern TIMCAPDriver TIMCAPD4; -#endif - -#if STM32_TIMCAP_USE_TIM5 && !defined(__DOXYGEN__) -extern TIMCAPDriver TIMCAPD5; -#endif - -#if STM32_TIMCAP_USE_TIM8 && !defined(__DOXYGEN__) -extern TIMCAPDriver TIMCAPD8; -#endif - -#if STM32_TIMCAP_USE_TIM9 && !defined(__DOXYGEN__) -extern TIMCAPDriver TIMCAPD9; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void timcap_lld_init(void); - void timcap_lld_start(TIMCAPDriver *timcapp); - void timcap_lld_stop(TIMCAPDriver *timcapp); - void timcap_lld_enable(TIMCAPDriver *timcapp); - void timcap_lld_disable(TIMCAPDriver *timcapp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_TIMCAP */ - -#endif /* _TIMCAP_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/USBHv1/hal_stm32_otg.h b/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/USBHv1/hal_stm32_otg.h deleted file mode 100644 index 3322e5117a..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/USBHv1/hal_stm32_otg.h +++ /dev/null @@ -1,934 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_stm32_otg.h - * @brief STM32 OTG registers layout header. - * - * @addtogroup USB - * @{ - */ - - -#ifndef HAL_STM32_OTG_H -#define HAL_STM32_OTG_H - -/** - * @brief Number of the implemented endpoints in OTG_FS. - * @details This value does not include the endpoint 0 that is always present. - */ -#define STM32_OTG1_ENDOPOINTS_NUMBER 3 - -/** - * @brief Number of the implemented endpoints in OTG_HS. - * @details This value does not include the endpoint 0 that is always present. - */ -#define STM32_OTG2_ENDOPOINTS_NUMBER 5 - -/** - * @brief OTG_FS FIFO memory size in words. - */ -#define STM32_OTG1_FIFO_MEM_SIZE 320 - -/** - * @brief OTG_HS FIFO memory size in words. - */ -#define STM32_OTG2_FIFO_MEM_SIZE 1024 - -/** - * @brief Host channel registers group. - */ -typedef struct { - volatile uint32_t HCCHAR; /**< @brief Host channel characteristics - register. */ - volatile uint32_t resvd8; - volatile uint32_t HCINT; /**< @brief Host channel interrupt register.*/ - volatile uint32_t HCINTMSK; /**< @brief Host channel interrupt mask - register. */ - volatile uint32_t HCTSIZ; /**< @brief Host channel transfer size - register. */ - volatile uint32_t resvd14; - volatile uint32_t resvd18; - volatile uint32_t resvd1c; -} stm32_otg_host_chn_t; - -/** - * @brief Device input endpoint registers group. - */ -typedef struct { - volatile uint32_t DIEPCTL; /**< @brief Device control IN endpoint - control register. */ - volatile uint32_t resvd4; - volatile uint32_t DIEPINT; /**< @brief Device IN endpoint interrupt - register. */ - volatile uint32_t resvdC; - volatile uint32_t DIEPTSIZ; /**< @brief Device IN endpoint transfer size - register. */ - volatile uint32_t resvd14; - volatile uint32_t DTXFSTS; /**< @brief Device IN endpoint transmit FIFO - status register. */ - volatile uint32_t resvd1C; -} stm32_otg_in_ep_t; - -/** - * @brief Device output endpoint registers group. - */ -typedef struct { - volatile uint32_t DOEPCTL; /**< @brief Device control OUT endpoint - control register. */ - volatile uint32_t resvd4; - volatile uint32_t DOEPINT; /**< @brief Device OUT endpoint interrupt - register. */ - volatile uint32_t resvdC; - volatile uint32_t DOEPTSIZ; /**< @brief Device OUT endpoint transfer - size register. */ - volatile uint32_t resvd14; - volatile uint32_t resvd18; - volatile uint32_t resvd1C; -} stm32_otg_out_ep_t; - -/** - * @brief USB registers memory map. - */ -typedef struct { - volatile uint32_t GOTGCTL; /**< @brief OTG control and status register.*/ - volatile uint32_t GOTGINT; /**< @brief OTG interrupt register. */ - volatile uint32_t GAHBCFG; /**< @brief AHB configuration register. */ - volatile uint32_t GUSBCFG; /**< @brief USB configuration register. */ - volatile uint32_t GRSTCTL; /**< @brief Reset register size. */ - volatile uint32_t GINTSTS; /**< @brief Interrupt register. */ - volatile uint32_t GINTMSK; /**< @brief Interrupt mask register. */ - volatile uint32_t GRXSTSR; /**< @brief Receive status debug read - register. */ - volatile uint32_t GRXSTSP; /**< @brief Receive status read/pop - register. */ - volatile uint32_t GRXFSIZ; /**< @brief Receive FIFO size register. */ - volatile uint32_t DIEPTXF0; /**< @brief Endpoint 0 transmit FIFO size - register. */ - volatile uint32_t HNPTXSTS; /**< @brief Non-periodic transmit FIFO/queue - status register. */ - volatile uint32_t resvd30; - volatile uint32_t resvd34; - volatile uint32_t GCCFG; /**< @brief General core configuration. */ - volatile uint32_t CID; /**< @brief Core ID register. */ - volatile uint32_t resvd58[48]; - volatile uint32_t HPTXFSIZ; /**< @brief Host periodic transmit FIFO size - register. */ - volatile uint32_t DIEPTXF[15];/**< @brief Device IN endpoint transmit FIFO - size registers. */ - volatile uint32_t resvd140[176]; - volatile uint32_t HCFG; /**< @brief Host configuration register. */ - volatile uint32_t HFIR; /**< @brief Host frame interval register. */ - volatile uint32_t HFNUM; /**< @brief Host frame number/frame time - Remaining register. */ - volatile uint32_t resvd40C; - volatile uint32_t HPTXSTS; /**< @brief Host periodic transmit FIFO/queue - status register. */ - volatile uint32_t HAINT; /**< @brief Host all channels interrupt - register. */ - volatile uint32_t HAINTMSK; /**< @brief Host all channels interrupt mask - register. */ - volatile uint32_t resvd41C[9]; - volatile uint32_t HPRT; /**< @brief Host port control and status - register. */ - volatile uint32_t resvd444[47]; - stm32_otg_host_chn_t hc[16]; /**< @brief Host channels array. */ - volatile uint32_t resvd700[64]; - volatile uint32_t DCFG; /**< @brief Device configuration register. */ - volatile uint32_t DCTL; /**< @brief Device control register. */ - volatile uint32_t DSTS; /**< @brief Device status register. */ - volatile uint32_t resvd80C; - volatile uint32_t DIEPMSK; /**< @brief Device IN endpoint common - interrupt mask register. */ - volatile uint32_t DOEPMSK; /**< @brief Device OUT endpoint common - interrupt mask register. */ - volatile uint32_t DAINT; /**< @brief Device all endpoints interrupt - register. */ - volatile uint32_t DAINTMSK; /**< @brief Device all endpoints interrupt - mask register. */ - volatile uint32_t resvd820; - volatile uint32_t resvd824; - volatile uint32_t DVBUSDIS; /**< @brief Device VBUS discharge time - register. */ - volatile uint32_t DVBUSPULSE; /**< @brief Device VBUS pulsing time - register. */ - volatile uint32_t resvd830; - volatile uint32_t DIEPEMPMSK; /**< @brief Device IN endpoint FIFO empty - interrupt mask register. */ - volatile uint32_t resvd838; - volatile uint32_t resvd83C; - volatile uint32_t resvd840[16]; - volatile uint32_t resvd880[16]; - volatile uint32_t resvd8C0[16]; - stm32_otg_in_ep_t ie[16]; /**< @brief Input endpoints. */ - stm32_otg_out_ep_t oe[16]; /**< @brief Output endpoints. */ - volatile uint32_t resvdD00[64]; - volatile uint32_t PCGCCTL; /**< @brief Power and clock gating control - register. */ - volatile uint32_t resvdE04[127]; - volatile uint32_t FIFO[16][1024]; -} stm32_otg_t; - -/** - * @name GOTGCTL register bit definitions - * @{ - */ -#define GOTGCTL_BSVLD (1U<<19) /**< B-Session Valid. */ -#define GOTGCTL_ASVLD (1U<<18) /**< A-Session Valid. */ -#define GOTGCTL_DBCT (1U<<17) /**< Long/Short debounce time. */ -#define GOTGCTL_CIDSTS (1U<<16) /**< Connector ID status. */ -#define GOTGCTL_EHEN (1U<<12) -#define GOTGCTL_DHNPEN (1U<<11) /**< Device HNP enabled. */ -#define GOTGCTL_HSHNPEN (1U<<10) /**< Host Set HNP enable. */ -#define GOTGCTL_HNPRQ (1U<<9) /**< HNP request. */ -#define GOTGCTL_HNGSCS (1U<<8) /**< Host negotiation success. */ -#define GOTGCTL_BVALOVAL (1U<<7) -#define GOTGCTL_BVALOEN (1U<<6) -#define GOTGCTL_AVALOVAL (1U<<5) -#define GOTGCTL_AVALOEN (1U<<4) -#define GOTGCTL_VBVALOVAL (1U<<3) -#define GOTGCTL_VBVALOEN (1U<<2) -#define GOTGCTL_SRQ (1U<<1) /**< Session request. */ -#define GOTGCTL_SRQSCS (1U<<0) /**< Session request success. */ -/** @} */ - -/** - * @name GOTGINT register bit definitions - * @{ - */ -#define GOTGINT_DBCDNE (1U<<19) /**< Debounce done. */ -#define GOTGINT_ADTOCHG (1U<<18) /**< A-Device timeout change. */ -#define GOTGINT_HNGDET (1U<<17) /**< Host negotiation detected. */ -#define GOTGINT_HNSSCHG (1U<<9) /**< Host negotiation success - status change. */ -#define GOTGINT_SRSSCHG (1U<<8) /**< Session request success - status change. */ -#define GOTGINT_SEDET (1U<<2) /**< Session end detected. */ -/** @} */ - -/** - * @name GAHBCFG register bit definitions - * @{ - */ -#define GAHBCFG_PTXFELVL (1U<<8) /**< Periodic TxFIFO empty - level. */ -#define GAHBCFG_TXFELVL (1U<<7) /**< Non-periodic TxFIFO empty - level. */ -#define GAHBCFG_DMAEN (1U<<5) /**< DMA enable (HS only). */ -#define GAHBCFG_HBSTLEN_MASK (15U<<1) /**< Burst length/type mask (HS - only). */ -#define GAHBCFG_HBSTLEN(n) ((n)<<1) /**< Burst length/type (HS - only). */ -#define GAHBCFG_GINTMSK (1U<<0) /**< Global interrupt mask. */ -/** @} */ - -/** - * @name GUSBCFG register bit definitions - * @{ - */ -#define GUSBCFG_CTXPKT (1U<<31) /**< Corrupt Tx packet. */ -#define GUSBCFG_FDMOD (1U<<30) /**< Force Device Mode. */ -#define GUSBCFG_FHMOD (1U<<29) /**< Force Host Mode. */ -#define GUSBCFG_TRDT_MASK (15U<<10) /**< USB Turnaround time field - mask. */ -#define GUSBCFG_TRDT(n) ((n)<<10) /**< USB Turnaround time field - value. */ -#define GUSBCFG_HNPCAP (1U<<9) /**< HNP-Capable. */ -#define GUSBCFG_SRPCAP (1U<<8) /**< SRP-Capable. */ -#define GUSBCFG_PHYSEL (1U<<6) /**< USB 2.0 High-Speed PHY or - USB 1.1 Full-Speed serial - transceiver Select. */ -#define GUSBCFG_TOCAL_MASK (7U<<0) /**< HS/FS timeout calibration - field mask. */ -#define GUSBCFG_TOCAL(n) ((n)<<0) /**< HS/FS timeout calibration - field value. */ -/** @} */ - -/** - * @name GRSTCTL register bit definitions - * @{ - */ -#define GRSTCTL_AHBIDL (1U<<31) /**< AHB Master Idle. */ -#define GRSTCTL_TXFNUM_MASK (31U<<6) /**< TxFIFO number field mask. */ -#define GRSTCTL_TXFNUM(n) ((n)<<6) /**< TxFIFO number field value. */ -#define GRSTCTL_TXFFLSH (1U<<5) /**< TxFIFO flush. */ -#define GRSTCTL_RXFFLSH (1U<<4) /**< RxFIFO flush. */ -#define GRSTCTL_FCRST (1U<<2) /**< Host frame counter reset. */ -#define GRSTCTL_HSRST (1U<<1) /**< HClk soft reset. */ -#define GRSTCTL_CSRST (1U<<0) /**< Core soft reset. */ -/** @} */ - -/** - * @name GINTSTS register bit definitions - * @{ - */ -#define GINTSTS_WKUPINT (1U<<31) /**< Resume/Remote wakeup - detected interrupt. */ -#define GINTSTS_SRQINT (1U<<30) /**< Session request/New session - detected interrupt. */ -#define GINTSTS_DISCINT (1U<<29) /**< Disconnect detected - interrupt. */ -#define GINTSTS_CIDSCHG (1U<<28) /**< Connector ID status change.*/ -#define GINTSTS_PTXFE (1U<<26) /**< Periodic TxFIFO empty. */ -#define GINTSTS_HCINT (1U<<25) /**< Host channels interrupt. */ -#define GINTSTS_HPRTINT (1U<<24) /**< Host port interrupt. */ -#define GINTSTS_IPXFR (1U<<21) /**< Incomplete periodic - transfer. */ -#define GINTSTS_IISOOXFR (1U<<21) /**< Incomplete isochronous OUT - transfer. */ -#define GINTSTS_IISOIXFR (1U<<20) /**< Incomplete isochronous IN - transfer. */ -#define GINTSTS_OEPINT (1U<<19) /**< OUT endpoints interrupt. */ -#define GINTSTS_IEPINT (1U<<18) /**< IN endpoints interrupt. */ -#define GINTSTS_EOPF (1U<<15) /**< End of periodic frame - interrupt. */ -#define GINTSTS_ISOODRP (1U<<14) /**< Isochronous OUT packet - dropped interrupt. */ -#define GINTSTS_ENUMDNE (1U<<13) /**< Enumeration done. */ -#define GINTSTS_USBRST (1U<<12) /**< USB reset. */ -#define GINTSTS_USBSUSP (1U<<11) /**< USB suspend. */ -#define GINTSTS_ESUSP (1U<<10) /**< Early suspend. */ -#define GINTSTS_GONAKEFF (1U<<7) /**< Global OUT NAK effective. */ -#define GINTSTS_GINAKEFF (1U<<6) /**< Global IN non-periodic NAK - effective. */ -#define GINTSTS_NPTXFE (1U<<5) /**< Non-periodic TxFIFO empty. */ -#define GINTSTS_RXFLVL (1U<<4) /**< RxFIFO non-empty. */ -#define GINTSTS_SOF (1U<<3) /**< Start of frame. */ -#define GINTSTS_OTGINT (1U<<2) /**< OTG interrupt. */ -#define GINTSTS_MMIS (1U<<1) /**< Mode Mismatch interrupt. */ -#define GINTSTS_CMOD (1U<<0) /**< Current mode of operation. */ -/** @} */ - -/** - * @name GINTMSK register bit definitions - * @{ - */ -#define GINTMSK_WKUM (1U<<31) /**< Resume/remote wakeup - detected interrupt mask. */ -#define GINTMSK_SRQM (1U<<30) /**< Session request/New session - detected interrupt mask. */ -#define GINTMSK_DISCM (1U<<29) /**< Disconnect detected - interrupt mask. */ -#define GINTMSK_CIDSCHGM (1U<<28) /**< Connector ID status change - mask. */ -#define GINTMSK_PTXFEM (1U<<26) /**< Periodic TxFIFO empty mask.*/ -#define GINTMSK_HCM (1U<<25) /**< Host channels interrupt - mask. */ -#define GINTMSK_HPRTM (1U<<24) /**< Host port interrupt mask. */ -#define GINTMSK_IPXFRM (1U<<21) /**< Incomplete periodic - transfer mask. */ -#define GINTMSK_IISOOXFRM (1U<<21) /**< Incomplete isochronous OUT - transfer mask. */ -#define GINTMSK_IISOIXFRM (1U<<20) /**< Incomplete isochronous IN - transfer mask. */ -#define GINTMSK_OEPM (1U<<19) /**< OUT endpoints interrupt - mask. */ -#define GINTMSK_IEPM (1U<<18) /**< IN endpoints interrupt - mask. */ -#define GINTMSK_EOPFM (1U<<15) /**< End of periodic frame - interrupt mask. */ -#define GINTMSK_ISOODRPM (1U<<14) /**< Isochronous OUT packet - dropped interrupt mask. */ -#define GINTMSK_ENUMDNEM (1U<<13) /**< Enumeration done mask. */ -#define GINTMSK_USBRSTM (1U<<12) /**< USB reset mask. */ -#define GINTMSK_USBSUSPM (1U<<11) /**< USB suspend mask. */ -#define GINTMSK_ESUSPM (1U<<10) /**< Early suspend mask. */ -#define GINTMSK_GONAKEFFM (1U<<7) /**< Global OUT NAK effective - mask. */ -#define GINTMSK_GINAKEFFM (1U<<6) /**< Global non-periodic IN NAK - effective mask. */ -#define GINTMSK_NPTXFEM (1U<<5) /**< Non-periodic TxFIFO empty - mask. */ -#define GINTMSK_RXFLVLM (1U<<4) /**< Receive FIFO non-empty - mask. */ -#define GINTMSK_SOFM (1U<<3) /**< Start of (micro)frame mask.*/ -#define GINTMSK_OTGM (1U<<2) /**< OTG interrupt mask. */ -#define GINTMSK_MMISM (1U<<1) /**< Mode Mismatch interrupt - mask. */ -/** @} */ - -/** - * @name GRXSTSR register bit definitions - * @{ - */ -#define GRXSTSR_PKTSTS_MASK (15U<<17) /**< Packet status mask. */ -#define GRXSTSR_PKTSTS(n) ((n)<<17) /**< Packet status value. */ -#define GRXSTSR_OUT_GLOBAL_NAK GRXSTSR_PKTSTS(1) -#define GRXSTSR_OUT_DATA GRXSTSR_PKTSTS(2) -#define GRXSTSR_OUT_COMP GRXSTSR_PKTSTS(3) -#define GRXSTSR_SETUP_COMP GRXSTSR_PKTSTS(4) -#define GRXSTSR_SETUP_DATA GRXSTSR_PKTSTS(6) -#define GRXSTSR_DPID_MASK (3U<<15) /**< Data PID mask. */ -#define GRXSTSR_DPID(n) ((n)<<15) /**< Data PID value. */ -#define GRXSTSR_BCNT_MASK (0x7FF<<4) /**< Byte count mask. */ -#define GRXSTSR_BCNT(n) ((n)<<4) /**< Byte count value. */ -#define GRXSTSR_CHNUM_MASK (15U<<0) /**< Channel number mask. */ -#define GRXSTSR_CHNUM(n) ((n)<<0) /**< Channel number value. */ -#define GRXSTSR_EPNUM_MASK (15U<<0) /**< Endpoint number mask. */ -#define GRXSTSR_EPNUM(n) ((n)<<0) /**< Endpoint number value. */ -/** @} */ - -/** - * @name GRXSTSP register bit definitions - * @{ - */ -#define GRXSTSP_PKTSTS_MASK (15<<17) /**< Packet status mask. */ -#define GRXSTSP_PKTSTS(n) ((n)<<17) /**< Packet status value. */ -#define GRXSTSP_OUT_GLOBAL_NAK GRXSTSP_PKTSTS(1) -#define GRXSTSP_OUT_DATA GRXSTSP_PKTSTS(2) -#define GRXSTSP_OUT_COMP GRXSTSP_PKTSTS(3) -#define GRXSTSP_SETUP_COMP GRXSTSP_PKTSTS(4) -#define GRXSTSP_SETUP_DATA GRXSTSP_PKTSTS(6) -#define GRXSTSP_DPID_MASK (3U<<15) /**< Data PID mask. */ -#define GRXSTSP_DPID(n) ((n)<<15) /**< Data PID value. */ -#define GRXSTSP_BCNT_MASK (0x7FF<<4) /**< Byte count mask. */ -#define GRXSTSP_BCNT_OFF 4 /**< Byte count offset. */ -#define GRXSTSP_BCNT(n) ((n)<<4) /**< Byte count value. */ -#define GRXSTSP_CHNUM_MASK (15U<<0) /**< Channel number mask. */ -#define GRXSTSP_CHNUM(n) ((n)<<0) /**< Channel number value. */ -#define GRXSTSP_EPNUM_MASK (15U<<0) /**< Endpoint number mask. */ -#define GRXSTSP_EPNUM_OFF 0 /**< Endpoint number offset. */ -#define GRXSTSP_EPNUM(n) ((n)<<0) /**< Endpoint number value. */ -/** @} */ - -/** - * @name GRXFSIZ register bit definitions - * @{ - */ -#define GRXFSIZ_RXFD_MASK (0xFFFF<<0) /**< RxFIFO depth mask. */ -#define GRXFSIZ_RXFD(n) ((n)<<0) /**< RxFIFO depth value. */ -/** @} */ - -/** - * @name DIEPTXFx register bit definitions - * @{ - */ -#define DIEPTXF_INEPTXFD_MASK (0xFFFFU<<16)/**< IN endpoint TxFIFO depth - mask. */ -#define DIEPTXF_INEPTXFD(n) ((n)<<16) /**< IN endpoint TxFIFO depth - value. */ -#define DIEPTXF_INEPTXSA_MASK (0xFFFF<<0) /**< IN endpoint FIFOx transmit - RAM start address mask. */ -#define DIEPTXF_INEPTXSA(n) ((n)<<0) /**< IN endpoint FIFOx transmit - RAM start address value. */ -/** @} */ - -/** - * @name GCCFG register bit definitions - * @{ - */ -/* Definitions for stepping 1.*/ -#define GCCFG_NOVBUSSENS (1U<<21) /**< VBUS sensing disable. */ -#define GCCFG_SOFOUTEN (1U<<20) /**< SOF output enable. */ -#define GCCFG_VBUSBSEN (1U<<19) /**< Enable the VBUS sensing "B" - device. */ -#define GCCFG_VBUSASEN (1U<<18) /**< Enable the VBUS sensing "A" - device. */ - -/* Definitions for stepping 2.*/ -#define GCCFG_VBDEN (1U<<21) /**< VBUS sensing enable. */ -#define GCCFG_PWRDWN (1U<<16) /**< Power down. */ -/** @} */ - -/** - * @name HPTXFSIZ register bit definitions - * @{ - */ -#define HPTXFSIZ_PTXFD_MASK (0xFFFFU<<16)/**< Host periodic TxFIFO - depth mask. */ -#define HPTXFSIZ_PTXFD(n) ((n)<<16) /**< Host periodic TxFIFO - depth value. */ -#define HPTXFSIZ_PTXSA_MASK (0xFFFFU<<0)/**< Host periodic TxFIFO - Start address mask. */ -#define HPTXFSIZ_PTXSA(n) ((n)<<0) /**< Host periodic TxFIFO - start address value. */ -/** @} */ - -/** - * @name HCFG register bit definitions - * @{ - */ -#define HCFG_FSLSS (1U<<2) /**< FS- and LS-only support. */ -#define HCFG_FSLSPCS_MASK (3U<<0) /**< FS/LS PHY clock select - mask. */ -#define HCFG_FSLSPCS_48 (1U<<0) /**< PHY clock is running at - 48 MHz. */ -#define HCFG_FSLSPCS_6 (2U<<0) /**< PHY clock is running at - 6 MHz. */ -/** @} */ - -/** - * @name HFIR register bit definitions - * @{ - */ -#define HFIR_FRIVL_MASK (0xFFFFU<<0)/**< Frame interval mask. */ -#define HFIR_FRIVL(n) ((n)<<0) /**< Frame interval value. */ -/** @} */ - -/** - * @name HFNUM register bit definitions - * @{ - */ -#define HFNUM_FTREM_MASK (0xFFFFU<<16)/**< Frame time Remaining mask.*/ -#define HFNUM_FTREM(n) ((n)<<16) /**< Frame time Remaining value.*/ -#define HFNUM_FRNUM_MASK (0xFFFFU<<0)/**< Frame number mask. */ -#define HFNUM_FRNUM(n) ((n)<<0) /**< Frame number value. */ -/** @} */ - -/** - * @name HPTXSTS register bit definitions - * @{ - */ -#define HPTXSTS_PTXQTOP_MASK (0xFFU<<24) /**< Top of the periodic - transmit request queue - mask. */ -#define HPTXSTS_PTXQTOP(n) ((n)<<24) /**< Top of the periodic - transmit request queue - value. */ -#define HPTXSTS_PTXQSAV_MASK (0xFF<<16) /**< Periodic transmit request - queue Space Available - mask. */ -#define HPTXSTS_PTXQSAV(n) ((n)<<16) /**< Periodic transmit request - queue Space Available - value. */ -#define HPTXSTS_PTXFSAVL_MASK (0xFFFF<<0) /**< Periodic transmit Data - FIFO Space Available - mask. */ -#define HPTXSTS_PTXFSAVL(n) ((n)<<0) /**< Periodic transmit Data - FIFO Space Available - value. */ -/** @} */ - -/** - * @name HAINT register bit definitions - * @{ - */ -#define HAINT_HAINT_MASK (0xFFFFU<<0)/**< Channel interrupts mask. */ -#define HAINT_HAINT(n) ((n)<<0) /**< Channel interrupts value. */ -/** @} */ - -/** - * @name HAINTMSK register bit definitions - * @{ - */ -#define HAINTMSK_HAINTM_MASK (0xFFFFU<<0)/**< Channel interrupt mask - mask. */ -#define HAINTMSK_HAINTM(n) ((n)<<0) /**< Channel interrupt mask - value. */ -/** @} */ - -/** - * @name HPRT register bit definitions - * @{ - */ -#define HPRT_PSPD_MASK (3U<<17) /**< Port speed mask. */ -#define HPRT_PSPD_FS (1U<<17) /**< Full speed value. */ -#define HPRT_PSPD_LS (2U<<17) /**< Low speed value. */ -#define HPRT_PTCTL_MASK (15<<13) /**< Port Test control mask. */ -#define HPRT_PTCTL(n) ((n)<<13) /**< Port Test control value. */ -#define HPRT_PPWR (1U<<12) /**< Port power. */ -#define HPRT_PLSTS_MASK (3U<<11) /**< Port Line status mask. */ -#define HPRT_PLSTS_DM (1U<<11) /**< Logic level of D-. */ -#define HPRT_PLSTS_DP (1U<<10) /**< Logic level of D+. */ -#define HPRT_PRST (1U<<8) /**< Port reset. */ -#define HPRT_PSUSP (1U<<7) /**< Port suspend. */ -#define HPRT_PRES (1U<<6) /**< Port Resume. */ -#define HPRT_POCCHNG (1U<<5) /**< Port overcurrent change. */ -#define HPRT_POCA (1U<<4) /**< Port overcurrent active. */ -#define HPRT_PENCHNG (1U<<3) /**< Port enable/disable change.*/ -#define HPRT_PENA (1U<<2) /**< Port enable. */ -#define HPRT_PCDET (1U<<1) /**< Port Connect detected. */ -#define HPRT_PCSTS (1U<<0) /**< Port connect status. */ -/** @} */ - -/** - * @name HCCHAR register bit definitions - * @{ - */ -#define HCCHAR_CHENA (1U<<31) /**< Channel enable. */ -#define HCCHAR_CHDIS (1U<<30) /**< Channel Disable. */ -#define HCCHAR_ODDFRM (1U<<29) /**< Odd frame. */ -#define HCCHAR_DAD_MASK (0x7FU<<22) /**< Device Address mask. */ -#define HCCHAR_DAD(n) ((n)<<22) /**< Device Address value. */ -#define HCCHAR_MCNT_MASK (3U<<20) /**< Multicount mask. */ -#define HCCHAR_MCNT(n) ((n)<<20) /**< Multicount value. */ -#define HCCHAR_EPTYP_MASK (3U<<18) /**< Endpoint type mask. */ -#define HCCHAR_EPTYP(n) ((n)<<18) /**< Endpoint type value. */ -#define HCCHAR_EPTYP_CTL (0U<<18) /**< Control endpoint value. */ -#define HCCHAR_EPTYP_ISO (1U<<18) /**< Isochronous endpoint value.*/ -#define HCCHAR_EPTYP_BULK (2U<<18) /**< Bulk endpoint value. */ -#define HCCHAR_EPTYP_INTR (3U<<18) /**< Interrupt endpoint value. */ -#define HCCHAR_LSDEV (1U<<17) /**< Low-Speed device. */ -#define HCCHAR_EPDIR (1U<<15) /**< Endpoint direction. */ -#define HCCHAR_EPNUM_MASK (15U<<11) /**< Endpoint number mask. */ -#define HCCHAR_EPNUM(n) ((n)<<11) /**< Endpoint number value. */ -#define HCCHAR_MPS_MASK (0x7FFU<<0) /**< Maximum packet size mask. */ -#define HCCHAR_MPS(n) ((n)<<0) /**< Maximum packet size value. */ -/** @} */ - -/** - * @name HCINT register bit definitions - * @{ - */ -#define HCINT_DTERR (1U<<10) /**< Data toggle error. */ -#define HCINT_FRMOR (1U<<9) /**< Frame overrun. */ -#define HCINT_BBERR (1U<<8) /**< Babble error. */ -#define HCINT_TRERR (1U<<7) /**< Transaction Error. */ -#define HCINT_ACK (1U<<5) /**< ACK response - received/transmitted - interrupt. */ -#define HCINT_NAK (1U<<4) /**< NAK response received - interrupt. */ -#define HCINT_STALL (1U<<3) /**< STALL response received - interrupt. */ -#define HCINT_AHBERR (1U<<2) /**< AHB error interrupt. */ -#define HCINT_CHH (1U<<1) /**< Channel halted. */ -#define HCINT_XFRC (1U<<0) /**< Transfer completed. */ -/** @} */ - -/** - * @name HCINTMSK register bit definitions - * @{ - */ -#define HCINTMSK_DTERRM (1U<<10) /**< Data toggle error mask. */ -#define HCINTMSK_FRMORM (1U<<9) /**< Frame overrun mask. */ -#define HCINTMSK_BBERRM (1U<<8) /**< Babble error mask. */ -#define HCINTMSK_TRERRM (1U<<7) /**< Transaction error mask. */ -#define HCINTMSK_NYET (1U<<6) /**< NYET response received - interrupt mask. */ -#define HCINTMSK_ACKM (1U<<5) /**< ACK Response - received/transmitted - interrupt mask. */ -#define HCINTMSK_NAKM (1U<<4) /**< NAK response received - interrupt mask. */ -#define HCINTMSK_STALLM (1U<<3) /**< STALL response received - interrupt mask. */ -#define HCINTMSK_AHBERRM (1U<<2) /**< AHB error interrupt mask. */ -#define HCINTMSK_CHHM (1U<<1) /**< Channel halted mask. */ -#define HCINTMSK_XFRCM (1U<<0) /**< Transfer completed mask. */ -/** @} */ - -/** - * @name HCTSIZ register bit definitions - * @{ - */ -#define HCTSIZ_DPID_MASK (3U<<29) /**< PID mask. */ -#define HCTSIZ_DPID_DATA0 (0U<<29) /**< DATA0. */ -#define HCTSIZ_DPID_DATA2 (1U<<29) /**< DATA2. */ -#define HCTSIZ_DPID_DATA1 (2U<<29) /**< DATA1. */ -#define HCTSIZ_DPID_MDATA (3U<<29) /**< MDATA. */ -#define HCTSIZ_DPID_SETUP (3U<<29) /**< SETUP. */ -#define HCTSIZ_PKTCNT_MASK (0x3FFU<<19)/**< Packet count mask. */ -#define HCTSIZ_PKTCNT(n) ((n)<<19) /**< Packet count value. */ -#define HCTSIZ_XFRSIZ_MASK (0x7FFFF<<0)/**< Transfer size mask. */ -#define HCTSIZ_XFRSIZ(n) ((n)<<0) /**< Transfer size value. */ -/** @} */ - -/** - * @name DCFG register bit definitions - * @{ - */ -#define DCFG_PFIVL_MASK (3U<<11) /**< Periodic frame interval - mask. */ -#define DCFG_PFIVL(n) ((n)<<11) /**< Periodic frame interval - value. */ -#define DCFG_DAD_MASK (0x7FU<<4) /**< Device address mask. */ -#define DCFG_DAD(n) ((n)<<4) /**< Device address value. */ -#define DCFG_NZLSOHSK (1U<<2) /**< Non-Zero-Length status - OUT handshake. */ -#define DCFG_DSPD_MASK (3U<<0) /**< Device speed mask. */ -#define DCFG_DSPD_HS (0U<<0) /**< High speed (USB 2.0). */ -#define DCFG_DSPD_HS_FS (1U<<0) /**< High speed (USB 2.0) in FS - mode. */ -#define DCFG_DSPD_FS11 (3U<<0) /**< Full speed (USB 1.1 - transceiver clock is 48 - MHz). */ -/** @} */ - -/** - * @name DCTL register bit definitions - * @{ - */ -#define DCTL_POPRGDNE (1U<<11) /**< Power-on programming done. */ -#define DCTL_CGONAK (1U<<10) /**< Clear global OUT NAK. */ -#define DCTL_SGONAK (1U<<9) /**< Set global OUT NAK. */ -#define DCTL_CGINAK (1U<<8) /**< Clear global non-periodic - IN NAK. */ -#define DCTL_SGINAK (1U<<7) /**< Set global non-periodic - IN NAK. */ -#define DCTL_TCTL_MASK (7U<<4) /**< Test control mask. */ -#define DCTL_TCTL(n) ((n)<<4 /**< Test control value. */ -#define DCTL_GONSTS (1U<<3) /**< Global OUT NAK status. */ -#define DCTL_GINSTS (1U<<2) /**< Global non-periodic IN - NAK status. */ -#define DCTL_SDIS (1U<<1) /**< Soft disconnect. */ -#define DCTL_RWUSIG (1U<<0) /**< Remote wakeup signaling. */ -/** @} */ - -/** - * @name DSTS register bit definitions - * @{ - */ -#define DSTS_FNSOF_MASK (0x3FFU<<8) /**< Frame number of the received - SOF mask. */ -#define DSTS_FNSOF(n) ((n)<<8) /**< Frame number of the received - SOF value. */ -#define DSTS_FNSOF_ODD (1U<<8) /**< Frame parity of the received - SOF value. */ -#define DSTS_EERR (1U<<3) /**< Erratic error. */ -#define DSTS_ENUMSPD_MASK (3U<<1) /**< Enumerated speed mask. */ -#define DSTS_ENUMSPD_FS_48 (3U<<1) /**< Full speed (PHY clock is - running at 48 MHz). */ -#define DSTS_ENUMSPD_HS_480 (0U<<1) /**< High speed. */ -#define DSTS_SUSPSTS (1U<<0) /**< Suspend status. */ -/** @} */ - -/** - * @name DIEPMSK register bit definitions - * @{ - */ -#define DIEPMSK_TXFEM (1U<<6) /**< Transmit FIFO empty mask. */ -#define DIEPMSK_INEPNEM (1U<<6) /**< IN endpoint NAK effective - mask. */ -#define DIEPMSK_ITTXFEMSK (1U<<4) /**< IN token received when - TxFIFO empty mask. */ -#define DIEPMSK_TOCM (1U<<3) /**< Timeout condition mask. */ -#define DIEPMSK_EPDM (1U<<1) /**< Endpoint disabled - interrupt mask. */ -#define DIEPMSK_XFRCM (1U<<0) /**< Transfer completed - interrupt mask. */ -/** @} */ - -/** - * @name DOEPMSK register bit definitions - * @{ - */ -#define DOEPMSK_OTEPDM (1U<<4) /**< OUT token received when - endpoint disabled mask. */ -#define DOEPMSK_STUPM (1U<<3) /**< SETUP phase done mask. */ -#define DOEPMSK_EPDM (1U<<1) /**< Endpoint disabled - interrupt mask. */ -#define DOEPMSK_XFRCM (1U<<0) /**< Transfer completed - interrupt mask. */ -/** @} */ - -/** - * @name DAINT register bit definitions - * @{ - */ -#define DAINT_OEPINT_MASK (0xFFFFU<<16)/**< OUT endpoint interrupt - bits mask. */ -#define DAINT_OEPINT(n) ((n)<<16) /**< OUT endpoint interrupt - bits value. */ -#define DAINT_IEPINT_MASK (0xFFFFU<<0)/**< IN endpoint interrupt - bits mask. */ -#define DAINT_IEPINT(n) ((n)<<0) /**< IN endpoint interrupt - bits value. */ -/** @} */ - -/** - * @name DAINTMSK register bit definitions - * @{ - */ -#define DAINTMSK_OEPM_MASK (0xFFFFU<<16)/**< OUT EP interrupt mask - bits mask. */ -#define DAINTMSK_OEPM(n) (1U<<(16+(n)))/**< OUT EP interrupt mask - bits value. */ -#define DAINTMSK_IEPM_MASK (0xFFFFU<<0)/**< IN EP interrupt mask - bits mask. */ -#define DAINTMSK_IEPM(n) (1U<<(n)) /**< IN EP interrupt mask - bits value. */ -/** @} */ - -/** - * @name DVBUSDIS register bit definitions - * @{ - */ -#define DVBUSDIS_VBUSDT_MASK (0xFFFFU<<0)/**< Device VBUS discharge - time mask. */ -#define DVBUSDIS_VBUSDT(n) ((n)<<0) /**< Device VBUS discharge - time value. */ -/** @} */ - -/** - * @name DVBUSPULSE register bit definitions - * @{ - */ -#define DVBUSPULSE_DVBUSP_MASK (0xFFFU<<0) /**< Device VBUSpulsing time - mask. */ -#define DVBUSPULSE_DVBUSP(n) ((n)<<0) /**< Device VBUS pulsing time - value. */ -/** @} */ - -/** - * @name DIEPEMPMSK register bit definitions - * @{ - */ -#define DIEPEMPMSK_INEPTXFEM(n) (1U<<(n)) /**< IN EP Tx FIFO empty - interrupt mask bit. */ -/** @} */ - -/** - * @name DIEPCTL register bit definitions - * @{ - */ -#define DIEPCTL_EPENA (1U<<31) /**< Endpoint enable. */ -#define DIEPCTL_EPDIS (1U<<30) /**< Endpoint disable. */ -#define DIEPCTL_SD1PID (1U<<29) /**< Set DATA1 PID. */ -#define DIEPCTL_SODDFRM (1U<<29) /**< Set odd frame. */ -#define DIEPCTL_SD0PID (1U<<28) /**< Set DATA0 PID. */ -#define DIEPCTL_SEVNFRM (1U<<28) /**< Set even frame. */ -#define DIEPCTL_SNAK (1U<<27) /**< Set NAK. */ -#define DIEPCTL_CNAK (1U<<26) /**< Clear NAK. */ -#define DIEPCTL_TXFNUM_MASK (15U<<22) /**< TxFIFO number mask. */ -#define DIEPCTL_TXFNUM(n) ((n)<<22) /**< TxFIFO number value. */ -#define DIEPCTL_STALL (1U<<21) /**< STALL handshake. */ -#define DIEPCTL_SNPM (1U<<20) /**< Snoop mode. */ -#define DIEPCTL_EPTYP_MASK (3<<18) /**< Endpoint type mask. */ -#define DIEPCTL_EPTYP_CTRL (0U<<18) /**< Control. */ -#define DIEPCTL_EPTYP_ISO (1U<<18) /**< Isochronous. */ -#define DIEPCTL_EPTYP_BULK (2U<<18) /**< Bulk. */ -#define DIEPCTL_EPTYP_INTR (3U<<18) /**< Interrupt. */ -#define DIEPCTL_NAKSTS (1U<<17) /**< NAK status. */ -#define DIEPCTL_EONUM (1U<<16) /**< Even/odd frame. */ -#define DIEPCTL_DPID (1U<<16) /**< Endpoint data PID. */ -#define DIEPCTL_USBAEP (1U<<15) /**< USB active endpoint. */ -#define DIEPCTL_MPSIZ_MASK (0x3FFU<<0) /**< Maximum Packet size mask. */ -#define DIEPCTL_MPSIZ(n) ((n)<<0) /**< Maximum Packet size value. */ -/** @} */ - -/** - * @name DIEPINT register bit definitions - * @{ - */ -#define DIEPINT_TXFE (1U<<7) /**< Transmit FIFO empty. */ -#define DIEPINT_INEPNE (1U<<6) /**< IN endpoint NAK effective. */ -#define DIEPINT_ITTXFE (1U<<4) /**< IN Token received when - TxFIFO is empty. */ -#define DIEPINT_TOC (1U<<3) /**< Timeout condition. */ -#define DIEPINT_EPDISD (1U<<1) /**< Endpoint disabled - interrupt. */ -#define DIEPINT_XFRC (1U<<0) /**< Transfer completed. */ -/** @} */ - -/** - * @name DIEPTSIZ register bit definitions - * @{ - */ -#define DIEPTSIZ_MCNT_MASK (3U<<29) /**< Multi count mask. */ -#define DIEPTSIZ_MCNT(n) ((n)<<29) /**< Multi count value. */ -#define DIEPTSIZ_PKTCNT_MASK (0x3FF<<19) /**< Packet count mask. */ -#define DIEPTSIZ_PKTCNT(n) ((n)<<19) /**< Packet count value. */ -#define DIEPTSIZ_XFRSIZ_MASK (0x7FFFFU<<0)/**< Transfer size mask. */ -#define DIEPTSIZ_XFRSIZ(n) ((n)<<0) /**< Transfer size value. */ -/** @} */ - -/** - * @name DTXFSTS register bit definitions. - * @{ - */ -#define DTXFSTS_INEPTFSAV_MASK (0xFFFF<<0) /**< IN endpoint TxFIFO space - available. */ -/** @} */ - -/** - * @name DOEPCTL register bit definitions. - * @{ - */ -#define DOEPCTL_EPENA (1U<<31) /**< Endpoint enable. */ -#define DOEPCTL_EPDIS (1U<<30) /**< Endpoint disable. */ -#define DOEPCTL_SD1PID (1U<<29) /**< Set DATA1 PID. */ -#define DOEPCTL_SODDFRM (1U<<29) /**< Set odd frame. */ -#define DOEPCTL_SD0PID (1U<<28) /**< Set DATA0 PID. */ -#define DOEPCTL_SEVNFRM (1U<<28) /**< Set even frame. */ -#define DOEPCTL_SNAK (1U<<27) /**< Set NAK. */ -#define DOEPCTL_CNAK (1U<<26) /**< Clear NAK. */ -#define DOEPCTL_STALL (1U<<21) /**< STALL handshake. */ -#define DOEPCTL_SNPM (1U<<20) /**< Snoop mode. */ -#define DOEPCTL_EPTYP_MASK (3U<<18) /**< Endpoint type mask. */ -#define DOEPCTL_EPTYP_CTRL (0U<<18) /**< Control. */ -#define DOEPCTL_EPTYP_ISO (1U<<18) /**< Isochronous. */ -#define DOEPCTL_EPTYP_BULK (2U<<18) /**< Bulk. */ -#define DOEPCTL_EPTYP_INTR (3U<<18) /**< Interrupt. */ -#define DOEPCTL_NAKSTS (1U<<17) /**< NAK status. */ -#define DOEPCTL_EONUM (1U<<16) /**< Even/odd frame. */ -#define DOEPCTL_DPID (1U<<16) /**< Endpoint data PID. */ -#define DOEPCTL_USBAEP (1U<<15) /**< USB active endpoint. */ -#define DOEPCTL_MPSIZ_MASK (0x3FFU<<0) /**< Maximum Packet size mask. */ -#define DOEPCTL_MPSIZ(n) ((n)<<0) /**< Maximum Packet size value. */ -/** @} */ - -/** - * @name DOEPINT register bit definitions - * @{ - */ -#define DOEPINT_B2BSTUP (1U<<6) /**< Back-to-back SETUP packets - received. */ -#define DOEPINT_OTEPDIS (1U<<4) /**< OUT token received when - endpoint disabled. */ -#define DOEPINT_STUP (1U<<3) /**< SETUP phase done. */ -#define DOEPINT_EPDISD (1U<<1) /**< Endpoint disabled - interrupt. */ -#define DOEPINT_XFRC (1U<<0) /**< Transfer completed - interrupt. */ -/** @} */ - -/** - * @name DOEPTSIZ register bit definitions - * @{ - */ -#define DOEPTSIZ_RXDPID_MASK (3U<<29) /**< Received data PID mask. */ -#define DOEPTSIZ_RXDPID(n) ((n)<<29) /**< Received data PID value. */ -#define DOEPTSIZ_STUPCNT_MASK (3U<<29) /**< SETUP packet count mask. */ -#define DOEPTSIZ_STUPCNT(n) ((n)<<29) /**< SETUP packet count value. */ -#define DOEPTSIZ_PKTCNT_MASK (0x3FFU<<19)/**< Packet count mask. */ -#define DOEPTSIZ_PKTCNT(n) ((n)<<19) /**< Packet count value. */ -#define DOEPTSIZ_XFRSIZ_MASK (0x7FFFFU<<0)/**< Transfer size mask. */ -#define DOEPTSIZ_XFRSIZ(n) ((n)<<0) /**< Transfer size value. */ -/** @} */ - -/** - * @name PCGCCTL register bit definitions - * @{ - */ -#define PCGCCTL_PHYSUSP (1U<<4) /**< PHY Suspended. */ -#define PCGCCTL_GATEHCLK (1U<<1) /**< Gate HCLK. */ -#define PCGCCTL_STPPCLK (1U<<0) /**< Stop PCLK. */ -/** @} */ - -/** - * @brief OTG_FS registers block memory address. - */ -#define OTG_FS_ADDR 0x50000000 - -/** - * @brief OTG_HS registers block memory address. - */ -#define OTG_HS_ADDR 0x40040000 - -/** - * @brief Accesses to the OTG_FS registers block. - */ -#define OTG_FS ((stm32_otg_t *)OTG_FS_ADDR) - -/** - * @brief Accesses to the OTG_HS registers block. - */ -#define OTG_HS ((stm32_otg_t *)OTG_HS_ADDR) - -#endif /* STM32_OTG_H */ - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c b/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c deleted file mode 100644 index 8947490360..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c +++ /dev/null @@ -1,1613 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail) - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include "hal.h" - -#if HAL_USE_USBH -#include "usbh/internal.h" -#include - -#if USBH_LLD_DEBUG_ENABLE_TRACE -#define udbgf(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define udbg(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define udbgf(f, ...) do {} while(0) -#define udbg(f, ...) do {} while(0) -#endif - -#if USBH_LLD_DEBUG_ENABLE_INFO -#define uinfof(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define uinfo(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define uinfof(f, ...) do {} while(0) -#define uinfo(f, ...) do {} while(0) -#endif - -#if USBH_LLD_DEBUG_ENABLE_WARNINGS -#define uwarnf(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define uwarn(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define uwarnf(f, ...) do {} while(0) -#define uwarn(f, ...) do {} while(0) -#endif - -#if USBH_LLD_DEBUG_ENABLE_ERRORS -#define uerrf(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define uerr(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define uerrf(f, ...) do {} while(0) -#define uerr(f, ...) do {} while(0) -#endif - -static void _transfer_completedI(usbh_ep_t *ep, usbh_urb_t *urb, usbh_urbstatus_t status); -static void _try_commit_np(USBHDriver *host); -static void otg_rxfifo_flush(USBHDriver *usbp); -static void otg_txfifo_flush(USBHDriver *usbp, uint32_t fifo); - -/*===========================================================================*/ -/* Little helper functions. */ -/*===========================================================================*/ -static inline void _move_to_pending_queue(usbh_ep_t *ep) { - list_move_tail(&ep->node, ep->pending_list); -} - -static inline usbh_urb_t *_active_urb(usbh_ep_t *ep) { - return list_first_entry(&ep->urb_list, usbh_urb_t, node); -} - -static inline void _save_dt_mask(usbh_ep_t *ep, uint32_t hctsiz) { - ep->dt_mask = hctsiz & HCTSIZ_DPID_MASK; -} - -#if 1 -#define _transfer_completed _transfer_completedI -#else -static inline void _transfer_completed(usbh_ep_t *ep, usbh_urb_t *urb, usbh_urbstatus_t status) { - osalSysLockFromISR(); - _transfer_completedI(ep, urb, status); - osalSysUnlockFromISR(); -} -#endif - -/*===========================================================================*/ -/* Functions called from many places. */ -/*===========================================================================*/ -static void _transfer_completedI(usbh_ep_t *ep, usbh_urb_t *urb, usbh_urbstatus_t status) { - osalDbgCheckClassI(); - - urb->queued = FALSE; - - /* remove URB from EP's queue */ - list_del_init(&urb->node); - - /* Call the callback function now, so that if it calls usbhURBSubmitI, - * the list_empty check below will be false. Also, note that the - * if (list_empty(&ep->node)) { - * ... - * } - * in usbh_lld_urb_submit will be false, since the endpoint is - * still in the active queue. - */ - _usbh_urb_completeI(urb, status); - - if (list_empty(&ep->urb_list)) { - /* no more URBs to process in this EP, remove EP from the host's queue */ - list_del_init(&ep->node); - } else { - /* more URBs to process */ - _move_to_pending_queue(ep); - } -} - -static void _halt_channel(USBHDriver *host, stm32_hc_management_t *hcm, usbh_lld_halt_reason_t reason) { - (void)host; - - if (hcm->halt_reason != USBH_LLD_HALTREASON_NONE) { - uwarnf("\t%s: Repeated halt (original=%d, new=%d)", hcm->ep->name, hcm->halt_reason, reason); - return; - } - -#if CH_DBG_ENABLE_CHECKS - if (usbhEPIsPeriodic(hcm->ep)) { - osalDbgCheck(host->otg->HPTXSTS & HPTXSTS_PTXQSAV_MASK); - } else { - osalDbgCheck(host->otg->HNPTXSTS & HPTXSTS_PTXQSAV_MASK); - } -#endif - - hcm->halt_reason = reason; - hcm->hc->HCCHAR |= HCCHAR_CHENA | HCCHAR_CHDIS; -} - -static void _release_channel(USBHDriver *host, stm32_hc_management_t *hcm) { -// static const char *reason[] = {"XFRC", "XFRC", "NAK", "STALL", "ERROR", "ABORT"}; -// udbgf("\t%s: release (%s)", hcm->ep->name, reason[hcm->halt_reason]); - hcm->hc->HCINTMSK = 0; - host->otg->HAINTMSK &= ~hcm->haintmsk; - hcm->halt_reason = USBH_LLD_HALTREASON_NONE; - if (usbhEPIsPeriodic(hcm->ep)) { - list_add(&hcm->node, &host->ch_free[0]); - } else { - list_add(&hcm->node, &host->ch_free[1]); - } - hcm->ep->xfer.hcm = 0; - hcm->ep = 0; -} - -static bool _activate_ep(USBHDriver *host, usbh_ep_t *ep) { - struct list_head *list; - uint16_t spc; - - osalDbgCheck(ep->xfer.hcm == NULL); - - if (usbhEPIsPeriodic(ep)) { - list = &host->ch_free[0]; - spc = (host->otg->HPTXSTS >> 16) & 0xff; - } else { - list = &host->ch_free[1]; - spc = (host->otg->HNPTXSTS >> 16) & 0xff; - } - - if (list_empty(list)) { - uwarnf("\t%s: No free %s channels", ep->name, usbhEPIsPeriodic(ep) ? "P" : "NP"); - return FALSE; - } - - if (spc <= STM32_USBH_MIN_QSPACE) { - uwarnf("\t%s: No space in %s Queue (spc=%d)", ep->name, usbhEPIsPeriodic(ep) ? "P" : "NP", spc); - return FALSE; - } - - /* get the first channel */ - stm32_hc_management_t *hcm = list_first_entry(list, stm32_hc_management_t, node); - osalDbgCheck((hcm->halt_reason == USBH_LLD_HALTREASON_NONE) && (hcm->ep == NULL)); - - usbh_urb_t *const urb = _active_urb(ep); - uint32_t hcintmsk = ep->hcintmsk; - uint32_t hcchar = ep->hcchar; - uint16_t mps = ep->wMaxPacketSize; - - uint32_t xfer_packets; - uint32_t xfer_len = 0; //Initialize just to shut up a compiler warning - - osalDbgCheck(urb->status == USBH_URBSTATUS_PENDING); - - /* check if the URB is a new one, or we must continue a previously started URB */ - if (urb->queued == FALSE) { - /* prepare EP for a new URB */ - if (ep->type == USBH_EPTYPE_CTRL) { - xfer_len = 8; - ep->xfer.buf = (uint8_t *)urb->setup_buff; - ep->dt_mask = HCTSIZ_DPID_SETUP; - ep->in = FALSE; - ep->xfer.u.ctrl_phase = USBH_LLD_CTRLPHASE_SETUP; - } else { - xfer_len = urb->requestedLength; - ep->xfer.buf = urb->buff; - } - ep->xfer.error_count = 0; - //urb->status = USBH_URBSTATUS_QUEUED; - } else { - osalDbgCheck(urb->requestedLength >= urb->actualLength); - - if (ep->type == USBH_EPTYPE_CTRL) { - switch (ep->xfer.u.ctrl_phase) { - case USBH_LLD_CTRLPHASE_SETUP: - xfer_len = 8; - ep->xfer.buf = (uint8_t *)urb->setup_buff; - ep->dt_mask = HCTSIZ_DPID_SETUP; - break; - case USBH_LLD_CTRLPHASE_DATA: - xfer_len = urb->requestedLength - urb->actualLength; - ep->xfer.buf = (uint8_t *) urb->buff + urb->actualLength; - break; - case USBH_LLD_CTRLPHASE_STATUS: - xfer_len = 0; - ep->dt_mask = HCTSIZ_DPID_DATA1; - ep->xfer.error_count = 0; - break; - default: - osalDbgCheck(0); - } - if (ep->in) { - hcintmsk |= HCINTMSK_DTERRM | HCINTMSK_BBERRM; - hcchar |= HCCHAR_EPDIR; - } - } else { - xfer_len = urb->requestedLength - urb->actualLength; - ep->xfer.buf = (uint8_t *) urb->buff + urb->actualLength; - } - - if (ep->xfer.error_count) - hcintmsk |= HCINTMSK_ACKM; - - } - ep->xfer.partial = 0; - - if (ep->type == USBH_EPTYPE_ISO) { - ep->dt_mask = HCTSIZ_DPID_DATA0; - - /* [USB 2.0 spec, 5.6.4]: A host must not issue more than 1 - * transaction in a (micro)frame for an isochronous endpoint - * unless the endpoint is high-speed, high-bandwidth. - */ - if (xfer_len > mps) - xfer_len = mps; - } else if (xfer_len > 0x7FFFF) { - xfer_len = 0x7FFFF - mps + 1; - } - - /* calculate required packets */ - if (xfer_len) { - xfer_packets = (xfer_len + mps - 1) / mps; - - if (xfer_packets > 0x3FF) { - xfer_packets = 0x3FF; - xfer_len = xfer_packets * mps; - } - } else { - xfer_packets = 1; /* Need 1 packet for transfer length of 0 */ - } - - if (ep->in) - xfer_len = xfer_packets * mps; - - /* Clear old interrupt conditions, - * configure transfer size, - * enable required interrupts */ - stm32_otg_host_chn_t *const hc = hcm->hc; - hc->HCINT = 0xffffffff; - hc->HCTSIZ = ep->dt_mask - | HCTSIZ_PKTCNT(xfer_packets) - | HCTSIZ_XFRSIZ(xfer_len); - hc->HCINTMSK = hcintmsk; - - /* Queue the transfer for the next frame (no effect for non-periodic transfers) */ - if (!(host->otg->HFNUM & 1)) - hcchar |= HCCHAR_ODDFRM; - - /* configure channel characteristics and queue a request */ - hc->HCCHAR = hcchar; - if (ep->in && (xfer_packets > 1)) { - /* For IN transfers, try to queue two back-to-back packets. - * This results in a 1% performance gain for Full Speed transfers - */ - if (--spc > STM32_USBH_MIN_QSPACE) { - hc->HCCHAR |= HCCHAR_CHENA; - } else { - uwarnf("\t%s: Could not queue back-to-back packets", ep->name); - } - } - - if (urb->queued == FALSE) { - urb->queued = TRUE; - udbgf("\t%s: Start (%dB)", ep->name, xfer_len); - } else { - udbgf("\t%s: Restart (%dB)", ep->name, xfer_len); - } - - ep->xfer.len = xfer_len; - ep->xfer.packets = (uint16_t)xfer_packets; - - /* remove the channel from the free list, link endpoint <-> channel and move to the active queue*/ - list_del(&hcm->node); - ep->xfer.hcm = hcm; - hcm->ep = ep; - list_move_tail(&ep->node, ep->active_list); - - - stm32_otg_t *const otg = host->otg; - - /* enable this channel's interrupt and global channel interrupt */ - otg->HAINTMSK |= hcm->haintmsk; - if (ep->in) { - otg->GINTMSK |= GINTMSK_HCM; - } else if (usbhEPIsPeriodic(ep)) { - otg->GINTMSK |= GINTMSK_HCM | GINTMSK_PTXFEM; - } else { - //TODO: write to the FIFO now - otg->GINTMSK |= GINTMSK_HCM | GINTMSK_NPTXFEM; - } - - return TRUE; -} - -static bool _update_urb(usbh_ep_t *ep, uint32_t hctsiz, usbh_urb_t *urb, bool completed) { - uint32_t len; - - if (!completed) { - len = ep->wMaxPacketSize * (ep->xfer.packets - ((hctsiz & HCTSIZ_PKTCNT_MASK) >> 19)); - } else { - if (ep->in) { - len = ep->xfer.len - ((hctsiz & HCTSIZ_XFRSIZ_MASK) >> 0); - } else { - len = ep->xfer.len; - } - osalDbgCheck(len == ep->xfer.partial); //TODO: if len == ep->xfer.partial, use this instead of the above code - } - -#if 1 - osalDbgAssert(urb->actualLength + len <= urb->requestedLength, "what happened?"); -#else - if (urb->actualLength + len > urb->requestedLength) { - uerrf("\t%s: Trimming actualLength %u -> %u", ep->name, urb->actualLength + len, urb->requestedLength); - urb->actualLength = urb->requestedLength; - return TRUE; - } -#endif - - urb->actualLength += len; - if ((urb->actualLength == urb->requestedLength) - || (ep->in && completed && (hctsiz & HCTSIZ_XFRSIZ_MASK))) - return TRUE; - - return FALSE; -} - -static void _try_commit_np(USBHDriver *host) { - usbh_ep_t *item, *tmp; - - list_for_each_entry_safe(item, usbh_ep_t, tmp, &host->ep_pending_lists[USBH_EPTYPE_CTRL], node) { - if (!_activate_ep(host, item)) - return; - } - - list_for_each_entry_safe(item, usbh_ep_t, tmp, &host->ep_pending_lists[USBH_EPTYPE_BULK], node) { - if (!_activate_ep(host, item)) - return; - } -} - -static void _try_commit_p(USBHDriver *host, bool sof) { - usbh_ep_t *item, *tmp; - - list_for_each_entry_safe(item, usbh_ep_t, tmp, &host->ep_pending_lists[USBH_EPTYPE_ISO], node) { - if (!_activate_ep(host, item)) - return; - } - - list_for_each_entry_safe(item, usbh_ep_t, tmp, &host->ep_pending_lists[USBH_EPTYPE_INT], node) { - osalDbgCheck(item); - /* TODO: improve this */ - if (sof && item->xfer.u.frame_counter) - --item->xfer.u.frame_counter; - - if (item->xfer.u.frame_counter == 0) { - if (!_activate_ep(host, item)) - return; - item->xfer.u.frame_counter = item->bInterval; - } - } - - if (list_empty(&host->ep_pending_lists[USBH_EPTYPE_ISO]) - && list_empty(&host->ep_pending_lists[USBH_EPTYPE_INT])) { - host->otg->GINTMSK &= ~GINTMSK_SOFM; - } else { - host->otg->GINTMSK |= GINTMSK_SOFM; - } -} - -static void _purge_queue(USBHDriver *host, struct list_head *list) { - usbh_ep_t *ep, *tmp; - list_for_each_entry_safe(ep, usbh_ep_t, tmp, list, node) { - usbh_urb_t *const urb = _active_urb(ep); - stm32_hc_management_t *const hcm = ep->xfer.hcm; - uwarnf("\t%s: Abort URB, USBH_URBSTATUS_DISCONNECTED", ep->name); - if (hcm) { - uwarnf("\t%s: URB had channel %d assigned, halt_reason = %d", ep->name, hcm - host->channels, hcm->halt_reason); - _release_channel(host, hcm); - _update_urb(ep, hcm->hc->HCTSIZ, urb, FALSE); - } - _transfer_completed(ep, urb, USBH_URBSTATUS_DISCONNECTED); - } -} - -static void _purge_active(USBHDriver *host) { - _purge_queue(host, &host->ep_active_lists[0]); - _purge_queue(host, &host->ep_active_lists[1]); - _purge_queue(host, &host->ep_active_lists[2]); - _purge_queue(host, &host->ep_active_lists[3]); -} - -static void _purge_pending(USBHDriver *host) { - _purge_queue(host, &host->ep_pending_lists[0]); - _purge_queue(host, &host->ep_pending_lists[1]); - _purge_queue(host, &host->ep_pending_lists[2]); - _purge_queue(host, &host->ep_pending_lists[3]); -} - -static uint32_t _write_packet(struct list_head *list, uint32_t space_available) { - usbh_ep_t *ep; - - uint32_t remaining = 0; - - list_for_each_entry(ep, usbh_ep_t, list, node) { - if (ep->in || (ep->xfer.hcm->halt_reason != USBH_LLD_HALTREASON_NONE)) - continue; - - int32_t rem = ep->xfer.len - ep->xfer.partial; - osalDbgCheck(rem >= 0); - if (rem <= 0) - continue; - - remaining += rem; - - if (!space_available) { - if (remaining) - break; - - continue; - } - - /* write one packet only */ - if (rem > ep->wMaxPacketSize) - rem = ep->wMaxPacketSize; - - /* round up to dwords */ - uint32_t words = (rem + 3) / 4; - - if (words > space_available) - words = space_available; - - space_available -= words; - - uint32_t written = words * 4; - if ((int32_t)written > rem) - written = rem; - - volatile uint32_t *dest = ep->xfer.hcm->fifo; - uint32_t *src = (uint32_t *)ep->xfer.buf; - udbgf("\t%s: write %d words (%dB), partial=%d", ep->name, words, written, ep->xfer.partial); - while (words--) { - *dest = *src++; - } - - ep->xfer.buf += written; - ep->xfer.partial += written; - - remaining -= written; - } - - return remaining; -} - - -/*===========================================================================*/ -/* API. */ -/*===========================================================================*/ - -void usbh_lld_ep_object_init(usbh_ep_t *ep) { -/* CTRL(IN) CTRL(OUT) INT(IN) INT(OUT) BULK(IN) BULK(OUT) ISO(IN) ISO(OUT) - * STALL si sólo DAT/STAT si si si si no no ep->type != ISO && (ep->type != CTRL || ctrlphase != SETUP) - * ACK si si si si si si no no ep->type != ISO - * NAK si si si si si si no no ep->type != ISO - * BBERR si no si no si no si no ep->in - * TRERR si si si si si si si no ep->type != ISO || ep->in - * DTERR si no si no si no no no ep->type != ISO && ep->in - * FRMOR no no si si no no si si ep->type = PERIODIC - */ - USBHDriver *host = ep->device->host; - uint32_t hcintmsk = HCINTMSK_CHHM | HCINTMSK_XFRCM | HCINTMSK_AHBERRM; - - switch (ep->type) { - case USBH_EPTYPE_ISO: - hcintmsk |= HCINTMSK_FRMORM; - if (ep->in) { - hcintmsk |= HCINTMSK_TRERRM | HCINTMSK_BBERRM; - } - break; - case USBH_EPTYPE_INT: - hcintmsk |= HCINTMSK_TRERRM | HCINTMSK_FRMORM | HCINTMSK_STALLM | HCINTMSK_NAKM; - if (ep->in) { - hcintmsk |= HCINTMSK_DTERRM | HCINTMSK_BBERRM; - } - ep->xfer.u.frame_counter = 1; - break; - case USBH_EPTYPE_CTRL: - hcintmsk |= HCINTMSK_TRERRM | HCINTMSK_STALLM | HCINTMSK_NAKM; - break; - case USBH_EPTYPE_BULK: - hcintmsk |= HCINTMSK_TRERRM | HCINTMSK_STALLM | HCINTMSK_NAKM; - if (ep->in) { - hcintmsk |= HCINTMSK_DTERRM | HCINTMSK_BBERRM; - } - break; - default: - chDbgCheck(0); - } - ep->active_list = &host->ep_active_lists[ep->type]; - ep->pending_list = &host->ep_pending_lists[ep->type]; - INIT_LIST_HEAD(&ep->urb_list); - INIT_LIST_HEAD(&ep->node); - - ep->hcintmsk = hcintmsk; - ep->hcchar = HCCHAR_CHENA - | HCCHAR_DAD(ep->device->address) - | HCCHAR_MCNT(1) - | HCCHAR_EPTYP(ep->type) - | ((ep->device->speed == USBH_DEVSPEED_LOW) ? HCCHAR_LSDEV : 0) - | (ep->in ? HCCHAR_EPDIR : 0) - | HCCHAR_EPNUM(ep->address) - | HCCHAR_MPS(ep->wMaxPacketSize); -} - -void usbh_lld_ep_open(usbh_ep_t *ep) { - uinfof("\t%s: Open EP", ep->name); - ep->status = USBH_EPSTATUS_OPEN; - osalOsRescheduleS(); -} - -void usbh_lld_ep_close(usbh_ep_t *ep) { - usbh_urb_t *urb, *tmp; - uinfof("\t%s: Closing EP...", ep->name); - list_for_each_entry_safe(urb, usbh_urb_t, tmp, &ep->urb_list, node) { - uinfof("\t%s: Abort URB, USBH_URBSTATUS_DISCONNECTED", ep->name); - _usbh_urb_abort_and_waitS(urb, USBH_URBSTATUS_DISCONNECTED); - } - uinfof("\t%s: Closed", ep->name); - ep->status = USBH_EPSTATUS_CLOSED; - osalOsRescheduleS(); -} - -void usbh_lld_urb_submit(usbh_urb_t *urb) { - usbh_ep_t *const ep = urb->ep; - - /* add the URB to the EP's queue */ - list_add_tail(&urb->node, &ep->urb_list); - - /* check if the EP wasn't in any queue (pending nor active) */ - if (list_empty(&ep->node)) { - - /* add the EP to the pending queue */ - _move_to_pending_queue(ep); - - if (usbhEPIsPeriodic(ep)) { - ep->device->host->otg->GINTMSK |= GINTMSK_SOFM; - } else { - /* try to queue non-periodic transfers */ - _try_commit_np(ep->device->host); - } - } -} - -bool usbh_lld_urb_abort(usbh_urb_t *urb, usbh_urbstatus_t status) { - osalDbgCheck(usbhURBIsBusy(urb)); - - usbh_ep_t *const ep = urb->ep; - osalDbgCheck(ep); - stm32_hc_management_t *const hcm = ep->xfer.hcm; - - if ((hcm != NULL) && (urb == _active_urb(ep))) { - /* This URB is active (channel assigned, top of the EP's URB list) */ - - if (hcm->halt_reason == USBH_LLD_HALTREASON_NONE) { - /* The channel is not being halted */ - urb->status = status; - _halt_channel(ep->device->host, hcm, USBH_LLD_HALTREASON_ABORT); - } else { - /* The channel is being halted, so we can't re-halt it. The CHH interrupt will - * be in charge of completing the transfer, but the URB will not have the specified status. - */ - } - return FALSE; - } - - /* This URB is active, we can cancel it now */ - _transfer_completedI(ep, urb, status); - - return TRUE; -} - - -/*===========================================================================*/ -/* Channel Interrupts. */ -/*===========================================================================*/ - -//CTRL(IN) CTRL(OUT) INT(IN) INT(OUT) BULK(IN) BULK(OUT) ISO(IN) ISO(OUT) -// si si si si si si no no ep->type != ISO && !ep->in -static inline void _ack_int(USBHDriver *host, stm32_hc_management_t *hcm, stm32_otg_host_chn_t *hc) { - (void)host; - osalDbgAssert(hcm->ep->type != USBH_EPTYPE_ISO, "ACK should not happen in ISO endpoints"); - hcm->ep->xfer.error_count = 0; - hc->HCINTMSK &= ~HCINTMSK_ACKM; - udbgf("\t%s: ACK", hcm->ep->name); -} - -//CTRL(IN) CTRL(OUT) INT(IN) INT(OUT) BULK(IN) BULK(OUT) ISO(IN) ISO(OUT) -// si no si no si no no no ep->type != ISO && ep->in -static inline void _dterr_int(USBHDriver *host, stm32_hc_management_t *hcm, stm32_otg_host_chn_t *hc) { - (void)host; - osalDbgAssert(hcm->ep->in && (hcm->ep->type != USBH_EPTYPE_ISO), "DTERR should not happen in OUT or ISO endpoints"); -#if 0 - hc->HCINTMSK &= ~(HCINTMSK_DTERRM | HCINTMSK_ACKM); - hcm->ep->xfer.error_count = 0; - _halt_channel(host, hcm, USBH_LLD_HALTREASON_ERROR); -#else - /* restart directly, no need to halt it in this case */ - hcm->ep->xfer.error_count = 0; - hc->HCINTMSK &= ~HCINTMSK_ACKM; - hc->HCCHAR |= HCCHAR_CHENA; -#endif - uerrf("\t%s: DTERR", hcm->ep->name); -} - -//CTRL(IN) CTRL(OUT) INT(IN) INT(OUT) BULK(IN) BULK(OUT) ISO(IN) ISO(OUT) -// si no si no si no si no ep->in -static inline void _bberr_int(USBHDriver *host, stm32_hc_management_t *hcm, stm32_otg_host_chn_t *hc) { - osalDbgAssert(hcm->ep->in, "BBERR should not happen in OUT endpoints"); - hc->HCINTMSK &= ~HCINTMSK_BBERRM; - hcm->ep->xfer.error_count = 3; - _halt_channel(host, hcm, USBH_LLD_HALTREASON_ERROR); - uerrf("\t%s: BBERR", hcm->ep->name); -} - -///CTRL(IN) CTRL(OUT) INT(IN) INT(OUT) BULK(IN) BULK(OUT) ISO(IN) ISO(OUT) -// si si si si si si si no ep->type != ISO || ep->in -static inline void _trerr_int(USBHDriver *host, stm32_hc_management_t *hcm, stm32_otg_host_chn_t *hc) { - osalDbgAssert(hcm->ep->in || (hcm->ep->type != USBH_EPTYPE_ISO), "TRERR should not happen in ISO OUT endpoints"); - hc->HCINTMSK &= ~HCINTMSK_TRERRM; - ++hcm->ep->xfer.error_count; - _halt_channel(host, hcm, USBH_LLD_HALTREASON_ERROR); - uerrf("\t%s: TRERR", hcm->ep->name); -} - -//CTRL(IN) CTRL(OUT) INT(IN) INT(OUT) BULK(IN) BULK(OUT) ISO(IN) ISO(OUT) -// no no si si no no si si ep->type = PERIODIC -static inline void _frmor_int(USBHDriver *host, stm32_hc_management_t *hcm, stm32_otg_host_chn_t *hc) { - osalDbgAssert(usbhEPIsPeriodic(hcm->ep), "FRMOR should not happen in non-periodic endpoints"); - hc->HCINTMSK &= ~HCINTMSK_FRMORM; - hcm->ep->xfer.error_count = 3; - _halt_channel(host, hcm, USBH_LLD_HALTREASON_ERROR); - uerrf("\t%s: FRMOR", hcm->ep->name); -} - -//CTRL(IN) CTRL(OUT) INT(IN) INT(OUT) BULK(IN) BULK(OUT) ISO(IN) ISO(OUT) -// si si si si si si no no ep->type != ISO -static inline void _nak_int(USBHDriver *host, stm32_hc_management_t *hcm, stm32_otg_host_chn_t *hc) { - osalDbgAssert(hcm->ep->type != USBH_EPTYPE_ISO, "NAK should not happen in ISO endpoints"); - if (!hcm->ep->in || (hcm->ep->type == USBH_EPTYPE_INT)) { - hc->HCINTMSK &= ~HCINTMSK_NAKM; - _halt_channel(host, hcm, USBH_LLD_HALTREASON_NAK); - } else { - /* restart directly, no need to halt it in this case */ - hcm->ep->xfer.error_count = 0; - hc->HCINTMSK &= ~HCINTMSK_ACKM; - hc->HCCHAR |= HCCHAR_CHENA; - } - udbgf("\t%s: NAK", hcm->ep->name); -} - -//CTRL(IN) CTRL(OUT) INT(IN) INT(OUT) BULK(IN) BULK(OUT) ISO(IN) ISO(OUT) -// si sólo DAT/STAT si si si si no no ep->type != ISO && (ep->type != CTRL || ctrlphase != SETUP) -static inline void _stall_int(USBHDriver *host, stm32_hc_management_t *hcm, stm32_otg_host_chn_t *hc) { - osalDbgAssert(hcm->ep->type != USBH_EPTYPE_ISO, "STALL should not happen in ISO endpoints"); - hc->HCINTMSK &= ~HCINTMSK_STALLM; - _halt_channel(host, hcm, USBH_LLD_HALTREASON_STALL); - uwarnf("\t%s: STALL", hcm->ep->name); -} - -static void _complete_bulk_int(USBHDriver *host, stm32_hc_management_t *hcm, usbh_ep_t *ep, usbh_urb_t *urb, uint32_t hctsiz) { - _release_channel(host, hcm); - _save_dt_mask(ep, hctsiz); - if (_update_urb(ep, hctsiz, urb, TRUE)) { - udbgf("\t%s: done", ep->name); - _transfer_completed(ep, urb, USBH_URBSTATUS_OK); - } else { - osalDbgCheck(urb->requestedLength > 0x7FFFF); - uwarnf("\t%s: incomplete", ep->name); - _move_to_pending_queue(ep); - } - if (usbhEPIsPeriodic(ep)) { - _try_commit_p(host, FALSE); - } else { - _try_commit_np(host); - } -} - -static void _complete_control(USBHDriver *host, stm32_hc_management_t *hcm, usbh_ep_t *ep, usbh_urb_t *urb, uint32_t hctsiz) { - osalDbgCheck(ep->xfer.u.ctrl_phase != USBH_LLD_CTRLPHASE_SETUP); - - _release_channel(host, hcm); - if (ep->xfer.u.ctrl_phase == USBH_LLD_CTRLPHASE_DATA) { - if (_update_urb(ep, hctsiz, urb, TRUE)) { - udbgf("\t%s: DATA done", ep->name); - ep->xfer.u.ctrl_phase = USBH_LLD_CTRLPHASE_STATUS; - ep->in = !ep->in; - } else { - osalDbgCheck(urb->requestedLength > 0x7FFFF); - uwarnf("\t%s: DATA incomplete", ep->name); - _save_dt_mask(ep, hctsiz); - } - _move_to_pending_queue(ep); - } else { - osalDbgCheck(ep->xfer.u.ctrl_phase == USBH_LLD_CTRLPHASE_STATUS); - udbgf("\t%s: STATUS done", ep->name); - _transfer_completed(ep, urb, USBH_URBSTATUS_OK); - } - _try_commit_np(host); -} - -static void _complete_control_setup(USBHDriver *host, stm32_hc_management_t *hcm, usbh_ep_t *ep, usbh_urb_t *urb) { - _release_channel(host, hcm); - if (urb->requestedLength) { - udbgf("\t%s: SETUP done -> DATA", ep->name); - ep->xfer.u.ctrl_phase = USBH_LLD_CTRLPHASE_DATA; - ep->in = *((uint8_t *)urb->setup_buff) & 0x80 ? TRUE : FALSE; - ep->dt_mask = HCTSIZ_DPID_DATA1; - ep->xfer.error_count = 0; - } else { - udbgf("\t%s: SETUP done -> STATUS", ep->name); - ep->in = TRUE; - ep->xfer.u.ctrl_phase = USBH_LLD_CTRLPHASE_STATUS; - } - _move_to_pending_queue(ep); - _try_commit_np(host); -} - -static void _complete_iso(USBHDriver *host, stm32_hc_management_t *hcm, usbh_ep_t *ep, usbh_urb_t *urb, uint32_t hctsiz) { - udbgf("\t%s: done", hcm->ep->name); - _release_channel(host, hcm); - _update_urb(ep, hctsiz, urb, TRUE); - _transfer_completed(ep, urb, USBH_URBSTATUS_OK); - _try_commit_p(host, FALSE); -} - -static inline void _xfrc_int(USBHDriver *host, stm32_hc_management_t *hcm, stm32_otg_host_chn_t *hc) { - usbh_ep_t *const ep = hcm->ep; - usbh_urb_t *const urb = _active_urb(ep); - osalDbgCheck(urb); - uint32_t hctsiz = hc->HCTSIZ; - - hc->HCINTMSK &= ~HCINTMSK_XFRCM; - - switch (ep->type) { - case USBH_EPTYPE_CTRL: - if (ep->xfer.u.ctrl_phase == USBH_LLD_CTRLPHASE_SETUP) { - _complete_control_setup(host, hcm, ep, urb); - } else if (ep->in) { - _halt_channel(host, hcm, USBH_LLD_HALTREASON_XFRC); - } else { - _complete_control(host, hcm, ep, urb, hctsiz); - } - break; - - case USBH_EPTYPE_BULK: - if (ep->in) { - _halt_channel(host, hcm, USBH_LLD_HALTREASON_XFRC); - } else { - _complete_bulk_int(host, hcm, ep, urb, hctsiz); - } - break; - - case USBH_EPTYPE_INT: - if (ep->in && (hctsiz & HCTSIZ_PKTCNT_MASK)) { - _halt_channel(host, hcm, USBH_LLD_HALTREASON_XFRC); - } else { - _complete_bulk_int(host, hcm, ep, urb, hctsiz); - } - break; - - case USBH_EPTYPE_ISO: - if (ep->in && (hctsiz & HCTSIZ_PKTCNT_MASK)) { - _halt_channel(host, hcm, USBH_LLD_HALTREASON_XFRC); - } else { - _complete_iso(host, hcm, ep, urb, hctsiz); - } - break; - } -} - -static inline void _chh_int(USBHDriver *host, stm32_hc_management_t *hcm, stm32_otg_host_chn_t *hc) { - - usbh_ep_t *const ep = hcm->ep; - usbh_urb_t *const urb = _active_urb(ep); - osalDbgCheck(urb); - uint32_t hctsiz = hc->HCTSIZ; - usbh_lld_halt_reason_t reason = hcm->halt_reason; - - //osalDbgCheck(reason != USBH_LLD_HALTREASON_NONE); - if (reason == USBH_LLD_HALTREASON_NONE) { - uwarnf("\tCHH: ch=%d, USBH_LLD_HALTREASON_NONE", hcm - host->channels); - return; - } - - if (reason == USBH_LLD_HALTREASON_XFRC) { - osalDbgCheck(ep->in); - switch (ep->type) { - case USBH_EPTYPE_CTRL: - _complete_control(host, hcm, ep, urb, hctsiz); - break; - case USBH_EPTYPE_BULK: - case USBH_EPTYPE_INT: - _complete_bulk_int(host, hcm, ep, urb, hctsiz); - break; - case USBH_EPTYPE_ISO: - _complete_iso(host, hcm, ep, urb, hctsiz); - break; - } - } else { - _release_channel(host, hcm); - _save_dt_mask(ep, hctsiz); - bool done = _update_urb(ep, hctsiz, urb, FALSE); - - switch (reason) { - case USBH_LLD_HALTREASON_NAK: - if ((ep->type == USBH_EPTYPE_INT) && ep->in) { - _transfer_completed(ep, urb, USBH_URBSTATUS_TIMEOUT); - } else { - ep->xfer.error_count = 0; - _move_to_pending_queue(ep); - } - break; - - case USBH_LLD_HALTREASON_STALL: - if ((ep->type == USBH_EPTYPE_CTRL) && (ep->xfer.u.ctrl_phase == USBH_LLD_CTRLPHASE_SETUP)) { - uerrf("\t%s: Faulty device: STALLed SETUP phase", ep->name); - } - _transfer_completed(ep, urb, USBH_URBSTATUS_STALL); - break; - - case USBH_LLD_HALTREASON_ERROR: - if ((ep->type == USBH_EPTYPE_ISO) || done || (ep->xfer.error_count >= 3)) { - _transfer_completed(ep, urb, USBH_URBSTATUS_ERROR); - } else { - uerrf("\t%s: err=%d, done=%d, retry", ep->name, ep->xfer.error_count, done); - _move_to_pending_queue(ep); - } - break; - - case USBH_LLD_HALTREASON_ABORT: - uwarnf("\t%s: Abort", ep->name); - _transfer_completed(ep, urb, urb->status); - break; - - default: - osalDbgCheck(0); - break; - } - - if (usbhEPIsPeriodic(ep)) { - _try_commit_p(host, FALSE); - } else { - _try_commit_np(host); - } - } -} - -static void _hcint_n_int(USBHDriver *host, uint8_t chn) { - - stm32_hc_management_t *const hcm = &host->channels[chn]; - stm32_otg_host_chn_t *const hc = hcm->hc; - - uint32_t hcint = hc->HCINT; - hcint &= hc->HCINTMSK; - hc->HCINT = hcint; - - osalDbgCheck((hcint & HCINTMSK_AHBERRM) == 0); - osalDbgCheck(hcm->ep); - - if (hcint & HCINTMSK_STALLM) - _stall_int(host, hcm, hc); - if (hcint & HCINTMSK_NAKM) - _nak_int(host, hcm, hc); - if (hcint & HCINTMSK_ACKM) - _ack_int(host, hcm, hc); - if (hcint & HCINTMSK_TRERRM) - _trerr_int(host, hcm, hc); - if (hcint & HCINTMSK_BBERRM) - _bberr_int(host, hcm, hc); - if (hcint & HCINTMSK_FRMORM) - _frmor_int(host, hcm, hc); - if (hcint & HCINTMSK_DTERRM) - _dterr_int(host, hcm, hc); - if (hcint & HCINTMSK_XFRCM) - _xfrc_int(host, hcm, hc); - if (hcint & HCINTMSK_CHHM) - _chh_int(host, hcm, hc); -} - -static inline void _hcint_int(USBHDriver *host) { - uint32_t haint; - - haint = host->otg->HAINT; - haint &= host->otg->HAINTMSK; - - if (!haint) { - uerrf("HAINT=%08x, HAINTMSK=%08x", host->otg->HAINT, host->otg->HAINTMSK); - return; - } - -#if 1 //channel lookup loop - uint8_t i; - for (i = 0; haint && (i < host->channels_number); i++) { - if (haint & (1 << i)) { - _hcint_n_int(host, i); - haint &= ~(1 << i); - } - } -#else //faster calculation, with __CLZ (count leading zeroes) - while (haint) { - uint8_t chn = (uint8_t)(31 - __CLZ(haint)); - osalDbgAssert(chn < host->channels_number, "what?"); - haint &= ~host->channels[chn].haintmsk; - _hcint_n_int(host, chn); - } -#endif -} - - -/*===========================================================================*/ -/* Host interrupts. */ -/*===========================================================================*/ -static inline void _sof_int(USBHDriver *host) { - udbg("SOF"); - _try_commit_p(host, TRUE); -} - -static inline void _rxflvl_int(USBHDriver *host) { - - stm32_otg_t *const otg = host->otg; - - otg->GINTMSK &= ~GINTMSK_RXFLVLM; - while (otg->GINTSTS & GINTSTS_RXFLVL) { - uint32_t grxstsp = otg->GRXSTSP; - osalDbgCheck((grxstsp & GRXSTSP_CHNUM_MASK) < host->channels_number); - stm32_hc_management_t *const hcm = &host->channels[grxstsp & GRXSTSP_CHNUM_MASK]; - uint32_t hctsiz = hcm->hc->HCTSIZ; - - if ((grxstsp & GRXSTSP_PKTSTS_MASK) == GRXSTSP_PKTSTS(2)) { - /* 0010: IN data packet received */ - usbh_ep_t *const ep = hcm->ep; - osalDbgCheck(ep); - - /* restart the channel ASAP */ - if (hctsiz & HCTSIZ_PKTCNT_MASK) { -#if CH_DBG_ENABLE_CHECKS - if (usbhEPIsPeriodic(ep)) { - osalDbgCheck(host->otg->HPTXSTS & HPTXSTS_PTXQSAV_MASK); - } else { - osalDbgCheck(host->otg->HNPTXSTS & HPTXSTS_PTXQSAV_MASK); - } -#endif - hcm->hc->HCCHAR |= HCCHAR_CHENA; - } - - udbgf("\t%s: RXFLVL rx=%dB, rem=%dB (%dpkts)", - ep->name, - (grxstsp & GRXSTSP_BCNT_MASK) >> 4, - (hctsiz & HCTSIZ_XFRSIZ_MASK), - (hctsiz & HCTSIZ_PKTCNT_MASK) >> 19); - - /* Read */ - uint32_t *dest = (uint32_t *)ep->xfer.buf; - volatile uint32_t *const src = hcm->fifo; - - uint32_t bcnt = (grxstsp & GRXSTSP_BCNT_MASK) >> GRXSTSP_BCNT_OFF; - osalDbgCheck(bcnt + ep->xfer.partial <= ep->xfer.len); - - //TODO: optimize this - uint32_t words = bcnt / 4; - uint8_t bytes = bcnt & 3; - while (words--) { - *dest++ = *src; - } - if (bytes) { - uint32_t r = *src; - uint8_t *bsrc = (uint8_t *)&r; - uint8_t *bdest = (uint8_t *)dest; - do { - *bdest++ = *bsrc++; - } while (--bytes); - } - - ep->xfer.buf += bcnt; - ep->xfer.partial += bcnt; - -#if 0 //STM32_USBH_CHANNELS_NP > 1 - /* check bug */ - if (hctsiz & HCTSIZ_PKTCNT_MASK) { - uint32_t pkt = (hctsiz & HCTSIZ_PKTCNT_MASK) >> 19; - uint32_t siz = (hctsiz & HCTSIZ_XFRSIZ_MASK); - if (pkt * ep->wMaxPacketSize != siz) { - uerrf("\t%s: whatttt???", ep->name); - } - } -#endif - -#if USBH_DEBUG_ENABLE && USBH_LLD_DEBUG_ENABLE_ERRORS - } else { - /* 0011: IN transfer completed (triggers an interrupt) - * 0101: Data toggle error (triggers an interrupt) - * 0111: Channel halted (triggers an interrupt) - */ - switch (grxstsp & GRXSTSP_PKTSTS_MASK) { - case GRXSTSP_PKTSTS(3): - case GRXSTSP_PKTSTS(5): - case GRXSTSP_PKTSTS(7): - break; - default: - uerrf("\tRXFLVL: ch=%d, UNK=%d", grxstsp & GRXSTSP_CHNUM_MASK, (grxstsp & GRXSTSP_PKTSTS_MASK) >> 17); - break; - } -#endif - } - } - otg->GINTMSK |= GINTMSK_RXFLVLM; -} - -static inline void _nptxfe_int(USBHDriver *host) { - uint32_t rem; - stm32_otg_t *const otg = host->otg; - - rem = _write_packet(&host->ep_active_lists[USBH_EPTYPE_CTRL], - otg->HNPTXSTS & HPTXSTS_PTXFSAVL_MASK); - - rem += _write_packet(&host->ep_active_lists[USBH_EPTYPE_BULK], - otg->HNPTXSTS & HPTXSTS_PTXFSAVL_MASK); - -// if (rem) -// otg->GINTMSK |= GINTMSK_NPTXFEM; - - if (!rem) - otg->GINTMSK &= ~GINTMSK_NPTXFEM; - -} - -static inline void _ptxfe_int(USBHDriver *host) { - //TODO: implement - (void)host; - uinfo("PTXFE"); -} - -static inline void _discint_int(USBHDriver *host) { - uint32_t hprt = host->otg->HPRT; - - uwarn("\tDISCINT"); - - if (!(hprt & HPRT_PCSTS)) { - host->rootport.lld_status &= ~(USBH_PORTSTATUS_CONNECTION | USBH_PORTSTATUS_ENABLE); - host->rootport.lld_c_status |= USBH_PORTSTATUS_C_CONNECTION | USBH_PORTSTATUS_C_ENABLE; - } - _purge_active(host); - _purge_pending(host); -} - -static inline void _hprtint_int(USBHDriver *host) { - stm32_otg_t *const otg = host->otg; - uint32_t hprt = otg->HPRT; - - /* note: writing PENA = 1 actually disables the port */ - uint32_t hprt_clr = hprt & ~(HPRT_PENA | HPRT_PCDET | HPRT_PENCHNG | HPRT_POCCHNG); - - if (hprt & HPRT_PCDET) { - hprt_clr |= HPRT_PCDET; - if (hprt & HPRT_PCSTS) { - uinfo("\tHPRT: Port connection detected"); - host->rootport.lld_status |= USBH_PORTSTATUS_CONNECTION; - host->rootport.lld_c_status |= USBH_PORTSTATUS_C_CONNECTION; - } else { - uinfo("\tHPRT: Port disconnection detected"); - } - } - - if (hprt & HPRT_PENCHNG) { - hprt_clr |= HPRT_PENCHNG; - if (hprt & HPRT_PENA) { - uinfo("\tHPRT: Port enabled"); - host->rootport.lld_status |= USBH_PORTSTATUS_ENABLE; - host->rootport.lld_status &= ~(USBH_PORTSTATUS_HIGH_SPEED | USBH_PORTSTATUS_LOW_SPEED); - - /* Make sure the FIFOs are flushed. */ - otg_txfifo_flush(host, 0x10); - otg_rxfifo_flush(host); - - /* Clear all pending HC Interrupts */ - uint8_t i; - for (i = 0; i < host->channels_number; i++) { - otg->hc[i].HCINTMSK = 0; - otg->hc[i].HCINT = 0xFFFFFFFF; - } - - /* configure speed */ - if ((hprt & HPRT_PSPD_MASK) == HPRT_PSPD_LS) { - host->rootport.lld_status |= USBH_PORTSTATUS_LOW_SPEED; - otg->HFIR = 6000; - otg->HCFG = (otg->HCFG & ~HCFG_FSLSPCS_MASK) | HCFG_FSLSPCS_6; - } else { - otg->HFIR = 48000; - otg->HCFG = (otg->HCFG & ~HCFG_FSLSPCS_MASK) | HCFG_FSLSPCS_48; - } - } else { - if (hprt & HPRT_PCSTS) { - if (hprt & HPRT_POCA) { - uerr("\tHPRT: Port disabled due to overcurrent"); - } else { - uerr("\tHPRT: Port disabled due to port babble"); - } - } else { - uerr("\tHPRT: Port disabled due to disconnect"); - } - - _purge_active(host); - _purge_pending(host); - - host->rootport.lld_status &= ~USBH_PORTSTATUS_ENABLE; - } - host->rootport.lld_c_status |= USBH_PORTSTATUS_C_ENABLE; - } - - if (hprt & HPRT_POCCHNG) { - hprt_clr |= HPRT_POCCHNG; - if (hprt & HPRT_POCA) { - uerr("\tHPRT: Overcurrent"); - host->rootport.lld_status |= USBH_PORTSTATUS_OVERCURRENT; - } else { - udbg("\tHPRT: Clear overcurrent"); - host->rootport.lld_status &= ~USBH_PORTSTATUS_OVERCURRENT; - } - host->rootport.lld_c_status |= USBH_PORTSTATUS_C_OVERCURRENT; - } - - otg->HPRT = hprt_clr; -} - -static void usb_lld_serve_interrupt(USBHDriver *host) { - osalDbgCheck(host && (host->status != USBH_STATUS_STOPPED)); - - stm32_otg_t *const otg = host->otg; - uint32_t gintsts = otg->GINTSTS; - - /* check host mode */ - if (!(gintsts & GINTSTS_CMOD)) { - uerr("Device mode"); - otg->GINTSTS = gintsts; - return; - } - - /* check mismatch */ - if (gintsts & GINTSTS_MMIS) { - uerr("Mode Mismatch"); - otg->GINTSTS = gintsts; - return; - } - - gintsts &= otg->GINTMSK; - if (!gintsts) { - uwarnf("GINTSTS=%08x, GINTMSK=%08x", otg->GINTSTS, otg->GINTMSK); - return; - } -// otg->GINTMSK &= ~(GINTMSK_NPTXFEM | GINTMSK_PTXFEM); - otg->GINTSTS = gintsts; - - if (gintsts & GINTSTS_SOF) - _sof_int(host); - if (gintsts & GINTSTS_RXFLVL) - _rxflvl_int(host); - if (gintsts & GINTSTS_HPRTINT) - _hprtint_int(host); - if (gintsts & GINTSTS_DISCINT) - _discint_int(host); - if (gintsts & GINTSTS_HCINT) - _hcint_int(host); - if (gintsts & GINTSTS_NPTXFE) - _nptxfe_int(host); - if (gintsts & GINTSTS_PTXFE) - _ptxfe_int(host); - if (gintsts & GINTSTS_IPXFR) { - uerr("IPXFRM"); - } -} - - -/*===========================================================================*/ -/* Interrupt handlers. */ -/*===========================================================================*/ - -#if STM32_USBH_USE_OTG1 -OSAL_IRQ_HANDLER(STM32_OTG1_HANDLER) { - OSAL_IRQ_PROLOGUE(); - osalSysLockFromISR(); - usb_lld_serve_interrupt(&USBHD1); - osalSysUnlockFromISR(); - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if STM32_USBH_USE_OTG2 -OSAL_IRQ_HANDLER(STM32_OTG2_HANDLER) { - OSAL_IRQ_PROLOGUE(); - osalSysLockFromISR(); - usb_lld_serve_interrupt(&USBHD2); - osalSysUnlockFromISR(); - OSAL_IRQ_EPILOGUE(); -} -#endif - - -/*===========================================================================*/ -/* Initialization functions. */ -/*===========================================================================*/ -static void otg_core_reset(USBHDriver *usbp) { - stm32_otg_t *const otgp = usbp->otg; - - /* Wait AHB idle condition.*/ - while ((otgp->GRSTCTL & GRSTCTL_AHBIDL) == 0) - ; - - osalSysPolledDelayX(64); - - /* Core reset and delay of at least 3 PHY cycles.*/ - otgp->GRSTCTL = GRSTCTL_CSRST; - while ((otgp->GRSTCTL & GRSTCTL_CSRST) != 0) - ; - - osalSysPolledDelayX(24); - - /* Wait AHB idle condition.*/ - while ((otgp->GRSTCTL & GRSTCTL_AHBIDL) == 0) - ; -} - -static void otg_rxfifo_flush(USBHDriver *usbp) { - stm32_otg_t *const otgp = usbp->otg; - - otgp->GRSTCTL = GRSTCTL_RXFFLSH; - while ((otgp->GRSTCTL & GRSTCTL_RXFFLSH) != 0) - ; - /* Wait for 3 PHY Clocks.*/ - osalSysPolledDelayX(24); -} - -static void otg_txfifo_flush(USBHDriver *usbp, uint32_t fifo) { - stm32_otg_t *const otgp = usbp->otg; - - otgp->GRSTCTL = GRSTCTL_TXFNUM(fifo) | GRSTCTL_TXFFLSH; - while ((otgp->GRSTCTL & GRSTCTL_TXFFLSH) != 0) - ; - /* Wait for 3 PHY Clocks.*/ - osalSysPolledDelayX(24); -} - -static void _init(USBHDriver *host) { - int i; - - usbhObjectInit(host); - -#if STM32_USBH_USE_OTG1 -#if STM32_USBH_USE_OTG2 - if (&USBHD1 == host) { -#endif - host->otg = OTG_FS; - host->channels_number = STM32_OTG1_CHANNELS_NUMBER; -#if STM32_USBH_USE_OTG2 - } -#endif -#endif - -#if STM32_USBH_USE_OTG2 -#if STM32_USBH_USE_OTG1 - if (&USBHD2 == host) { -#endif - host->otg = OTG_HS; - host->channels_number = STM32_OTG2_CHANNELS_NUMBER; -#if STM32_USBH_USE_OTG1 - } -#endif -#endif - INIT_LIST_HEAD(&host->ch_free[0]); - INIT_LIST_HEAD(&host->ch_free[1]); - for (i = 0; i < host->channels_number; i++) { - host->channels[i].haintmsk = 1 << i; - host->channels[i].hc = &host->otg->hc[i]; - host->channels[i].fifo = host->otg->FIFO[i]; - if (i < STM32_USBH_CHANNELS_NP) { - list_add_tail(&host->channels[i].node, &host->ch_free[1]); - } else { - list_add_tail(&host->channels[i].node, &host->ch_free[0]); - } - } - for (i = 0; i < 4; i++) { - INIT_LIST_HEAD(&host->ep_active_lists[i]); - INIT_LIST_HEAD(&host->ep_pending_lists[i]); - } -} - -void usbh_lld_init(void) { -#if STM32_USBH_USE_OTG1 - _init(&USBHD1); -#endif -#if STM32_USBH_USE_OTG2 - _init(&USBHD2); -#endif -} - -static void _usbh_start(USBHDriver *usbh) { - stm32_otg_t *const otgp = usbh->otg; - - /* Clock activation.*/ -#if STM32_USBH_USE_OTG1 -#if STM32_USBH_USE_OTG2 - if (&USBHD1 == usbh) { -#endif - /* OTG FS clock enable and reset.*/ - rccEnableOTG_FS(FALSE); - rccResetOTG_FS(); - - otgp->GINTMSK = 0; - - /* Enables IRQ vector.*/ - nvicEnableVector(STM32_OTG1_NUMBER, STM32_USB_OTG1_IRQ_PRIORITY); -#if STM32_USBH_USE_OTG2 - } -#endif -#endif - -#if STM32_USBH_USE_OTG2 -#if STM32_USBH_USE_OTG1 - if (&USBHD2 == usbh) { -#endif - /* OTG HS clock enable and reset.*/ - rccEnableOTG_HS(TRUE); // Enable HS clock when cpu is in sleep mode - rccDisableOTG_HSULPI(TRUE); // Disable HS ULPI clock when cpu is in sleep mode - rccResetOTG_HS(); - - otgp->GINTMSK = 0; - - /* Enables IRQ vector.*/ - nvicEnableVector(STM32_OTG2_NUMBER, STM32_USB_OTG2_IRQ_PRIORITY); -#if STM32_USBH_USE_OTG1 - } -#endif -#endif - - otgp->GUSBCFG = GUSBCFG_PHYSEL | GUSBCFG_TRDT(5); - - otg_core_reset(usbh); - - otgp->GCCFG = GCCFG_PWRDWN; - - /* Forced host mode. */ - otgp->GUSBCFG = GUSBCFG_FHMOD | GUSBCFG_PHYSEL | GUSBCFG_TRDT(5); - - /* PHY enabled.*/ - otgp->PCGCCTL = 0; - - /* Internal FS PHY activation.*/ -#if STM32_OTG_STEPPING == 1 -#if defined(BOARD_OTG_NOVBUSSENS) - otgp->GCCFG = GCCFG_NOVBUSSENS | GCCFG_PWRDWN; -#else - otgp->GCCFG = GCCFG_PWRDWN; -#endif -#elif STM32_OTG_STEPPING == 2 -#if defined(BOARD_OTG_NOVBUSSENS) - otgp->GCCFG = GCCFG_PWRDWN; -#else - otgp->GCCFG = (GCCFG_VBDEN | GCCFG_PWRDWN); -#endif - -#endif - /* 48MHz 1.1 PHY.*/ - otgp->HCFG = HCFG_FSLSS | HCFG_FSLSPCS_48; - - /* Interrupts on FIFOs half empty.*/ - otgp->GAHBCFG = 0; - - otgp->GOTGINT = 0xFFFFFFFF; - - otgp->HPRT |= HPRT_PPWR; - - /* without this delay, the FIFO sizes are set INcorrectly */ - osalThreadSleepS(MS2ST(200)); - -#define HNPTXFSIZ DIEPTXF0 -#if STM32_USBH_USE_OTG1 -#if STM32_USBH_USE_OTG2 - if (&USBHD1 == usbh) { -#endif - otgp->GRXFSIZ = GRXFSIZ_RXFD(STM32_OTG1_RXFIFO_SIZE / 4); - otgp->HNPTXFSIZ = HPTXFSIZ_PTXSA((STM32_OTG1_RXFIFO_SIZE / 4)) | HPTXFSIZ_PTXFD(STM32_OTG1_NPTXFIFO_SIZE / 4); - otgp->HPTXFSIZ = HPTXFSIZ_PTXSA((STM32_OTG1_RXFIFO_SIZE / 4) + (STM32_OTG1_NPTXFIFO_SIZE / 4)) | HPTXFSIZ_PTXFD(STM32_OTG1_PTXFIFO_SIZE / 4); -#if STM32_USBH_USE_OTG2 - } -#endif -#endif -#if STM32_USBH_USE_OTG2 -#if STM32_USBH_USE_OTG1 - if (&USBHD2 == usbh) { -#endif - otgp->GRXFSIZ = GRXFSIZ_RXFD(STM32_OTG2_RXFIFO_SIZE / 4); - otgp->HNPTXFSIZ = HPTXFSIZ_PTXSA((STM32_OTG2_RXFIFO_SIZE / 4)) | HPTXFSIZ_PTXFD(STM32_OTG2_NPTXFIFO_SIZE / 4); - otgp->HPTXFSIZ = HPTXFSIZ_PTXSA((STM32_OTG2_RXFIFO_SIZE / 4) + (STM32_OTG2_NPTXFIFO_SIZE / 4)) | HPTXFSIZ_PTXFD(STM32_OTG2_PTXFIFO_SIZE / 4); -#if STM32_USBH_USE_OTG1 - } -#endif -#endif - - otg_txfifo_flush(usbh, 0x10); - otg_rxfifo_flush(usbh); - - otgp->GINTSTS = 0xffffffff; - otgp->GINTMSK = GINTMSK_DISCM /*| GINTMSK_PTXFEM*/ | GINTMSK_HCM | GINTMSK_HPRTM - /*| GINTMSK_IPXFRM | GINTMSK_NPTXFEM*/ | GINTMSK_RXFLVLM - /*| GINTMSK_SOFM */ | GINTMSK_MMISM; - - usbh->rootport.lld_status = USBH_PORTSTATUS_POWER; - usbh->rootport.lld_c_status = 0; - - /* Global interrupts enable.*/ - otgp->GAHBCFG |= GAHBCFG_GINTMSK; -} - -void usbh_lld_start(USBHDriver *usbh) { - if (usbh->status != USBH_STATUS_STOPPED) return; - _usbh_start(usbh); -} - -/*===========================================================================*/ -/* Root Hub request handler. */ -/*===========================================================================*/ -usbh_urbstatus_t usbh_lld_root_hub_request(USBHDriver *usbh, uint8_t bmRequestType, uint8_t bRequest, - uint16_t wvalue, uint16_t windex, uint16_t wlength, uint8_t *buf) { - - uint16_t typereq = (bmRequestType << 8) | bRequest; - - switch (typereq) { - case ClearHubFeature: - switch (wvalue) { - case USBH_HUB_FEAT_C_HUB_LOCAL_POWER: - case USBH_HUB_FEAT_C_HUB_OVER_CURRENT: - break; - default: - osalDbgAssert(0, "invalid wvalue"); - } - break; - - case ClearPortFeature: - chDbgAssert(windex == 1, "invalid windex"); - - osalSysLock(); - switch (wvalue) { - case USBH_PORT_FEAT_ENABLE: - case USBH_PORT_FEAT_SUSPEND: - case USBH_PORT_FEAT_POWER: - chDbgAssert(0, "unimplemented"); /* TODO */ - break; - - case USBH_PORT_FEAT_INDICATOR: - chDbgAssert(0, "unsupported"); - break; - - case USBH_PORT_FEAT_C_CONNECTION: - usbh->rootport.lld_c_status &= ~USBH_PORTSTATUS_C_CONNECTION; - break; - - case USBH_PORT_FEAT_C_RESET: - usbh->rootport.lld_c_status &= ~USBH_PORTSTATUS_C_RESET; - break; - - case USBH_PORT_FEAT_C_ENABLE: - usbh->rootport.lld_c_status &= ~USBH_PORTSTATUS_C_ENABLE; - break; - - case USBH_PORT_FEAT_C_SUSPEND: - usbh->rootport.lld_c_status &= ~USBH_PORTSTATUS_C_SUSPEND; - break; - - case USBH_PORT_FEAT_C_OVERCURRENT: - usbh->rootport.lld_c_status &= USBH_PORTSTATUS_C_OVERCURRENT; - break; - - default: - osalDbgAssert(0, "invalid wvalue"); - break; - } - osalOsRescheduleS(); - osalSysUnlock(); - break; - - case GetHubDescriptor: - /*dev_dbg(hsotg->dev, "GetHubDescriptor\n"); - hub_desc = (struct usb_hub_descriptor *)buf; - hub_desc->bDescLength = 9; - hub_desc->bDescriptorType = USB_DT_HUB; - hub_desc->bNbrPorts = 1; - hub_desc->wHubCharacteristics = - cpu_to_le16(HUB_CHAR_COMMON_LPSM | - HUB_CHAR_INDV_PORT_OCPM); - hub_desc->bPwrOn2PwrGood = 1; - hub_desc->bHubContrCurrent = 0; - hub_desc->u.hs.DeviceRemovable[0] = 0; - hub_desc->u.hs.DeviceRemovable[1] = 0xff;*/ - break; - - case GetHubStatus: - osalDbgCheck(wlength >= 4); - *(uint32_t *)buf = 0; - break; - - case GetPortStatus: - chDbgAssert(windex == 1, "invalid windex"); - osalDbgCheck(wlength >= 4); - osalSysLock(); - *(uint32_t *)buf = usbh->rootport.lld_status | (usbh->rootport.lld_c_status << 16); - osalOsRescheduleS(); - osalSysUnlock(); - break; - - case SetHubFeature: - chDbgAssert(0, "unsupported"); - break; - - case SetPortFeature: - chDbgAssert(windex == 1, "invalid windex"); - - switch (wvalue) { - case USBH_PORT_FEAT_TEST: - case USBH_PORT_FEAT_SUSPEND: - case USBH_PORT_FEAT_POWER: - chDbgAssert(0, "unimplemented"); /* TODO */ - break; - - case USBH_PORT_FEAT_RESET: { - osalSysLock(); - stm32_otg_t *const otg = usbh->otg; - uint32_t hprt; - otg->PCGCCTL = 0; - hprt = otg->HPRT; - /* note: writing PENA = 1 actually disables the port */ - hprt &= ~(HPRT_PSUSP | HPRT_PENA | HPRT_PCDET | HPRT_PENCHNG | HPRT_POCCHNG ); - otg->HPRT = hprt | HPRT_PRST; - osalThreadSleepS(MS2ST(60)); - otg->HPRT = hprt; - usbh->rootport.lld_c_status |= USBH_PORTSTATUS_C_RESET; - osalOsRescheduleS(); - osalSysUnlock(); - } break; - - case USBH_PORT_FEAT_INDICATOR: - chDbgAssert(0, "unsupported"); - break; - - default: - osalDbgAssert(0, "invalid wvalue"); - break; - } - break; - - default: - osalDbgAssert(0, "invalid typereq"); - break; - } - - return USBH_URBSTATUS_OK; -} - -uint8_t usbh_lld_roothub_get_statuschange_bitmap(USBHDriver *usbh) { - osalSysLock(); - if (usbh->rootport.lld_c_status) { - osalOsRescheduleS(); - osalSysUnlock(); - return 1 << 1; - } - osalOsRescheduleS(); - osalSysUnlock(); - return 0; -} - - -#endif diff --git a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.h b/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.h deleted file mode 100644 index 15413b42f1..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.h +++ /dev/null @@ -1,153 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail) - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef HAL_USBH_LLD_H -#define HAL_USBH_LLD_H - -#include "hal.h" - -#if HAL_USE_USBH - -#include "osal.h" -#include "stm32_otg.h" - -/* TODO: - * - * - Implement ISO/INT OUT and test - * - Consider DMA mode for OTG_HS, consider external PHY for HS. - * - Implement a data pump thread, so we don't have to copy data from the ISR - * This might be a bad idea for small endpoint packet sizes (the context switch - * could be longer than the copy) - */ - -typedef enum { - USBH_LLD_CTRLPHASE_SETUP, - USBH_LLD_CTRLPHASE_DATA, - USBH_LLD_CTRLPHASE_STATUS -} usbh_lld_ctrlphase_t; - -typedef enum { - USBH_LLD_HALTREASON_NONE, - USBH_LLD_HALTREASON_XFRC, - USBH_LLD_HALTREASON_NAK, - USBH_LLD_HALTREASON_STALL, - USBH_LLD_HALTREASON_ERROR, - USBH_LLD_HALTREASON_ABORT -} usbh_lld_halt_reason_t; - - -typedef struct stm32_hc_management { - struct list_head node; - - stm32_otg_host_chn_t *hc; - volatile uint32_t *fifo; - usbh_ep_t *ep; - uint16_t haintmsk; - usbh_lld_halt_reason_t halt_reason; -} stm32_hc_management_t; - - -#define _usbhdriver_ll_data \ - stm32_otg_t *otg; \ - /* channels */ \ - uint8_t channels_number; \ - stm32_hc_management_t channels[STM32_OTG2_CHANNELS_NUMBER]; \ - struct list_head ch_free[2]; \ - /* Enpoints being processed */ \ - struct list_head ep_active_lists[4]; \ - /* Pending endpoints */ \ - struct list_head ep_pending_lists[4]; - - -#define _usbh_ep_ll_data \ - struct list_head *active_list; /* shortcut to ep list */ \ - struct list_head *pending_list; /* shortcut to ep list */ \ - struct list_head urb_list; /* list of URBs queued in this EP */ \ - struct list_head node; /* this EP */ \ - uint32_t hcintmsk; \ - uint32_t hcchar; \ - uint32_t dt_mask; /* data-toggle mask */ \ - /* current transfer */ \ - struct { \ - stm32_hc_management_t *hcm; /* assigned channel */ \ - uint32_t len; /* this transfer's total length */ \ - uint8_t *buf; /* this transfer's buffer */ \ - uint32_t partial; /* this transfer's partial length */\ - uint16_t packets; /* packets allocated */ \ - union { \ - uint32_t frame_counter; /* frame counter (for INT) */ \ - usbh_lld_ctrlphase_t ctrl_phase; /* control phase (for CTRL) */ \ - } u; \ - uint8_t error_count; /* error count */ \ - } xfer; - - - - - -#define _usbh_port_ll_data \ - uint16_t lld_c_status; \ - uint16_t lld_status; - -#define _usbh_device_ll_data - -#define _usbh_hub_ll_data - -#define _usbh_urb_ll_data \ - struct list_head node; \ - bool queued; - - -#define usbh_lld_urb_object_init(urb) \ - do { \ - osalDbgAssert(((uint32_t)urb->buff & 3) == 0, \ - "use USBH_DEFINE_BUFFER() to declare the IO buffers"); \ - urb->queued = FALSE; \ - } while (0) - - -#define usbh_lld_urb_object_reset(urb) \ - do { \ - osalDbgAssert(urb->queued == FALSE, "wrong state"); \ - osalDbgAssert(((uint32_t)urb->buff & 3) == 0, \ - "use USBH_DEFINE_BUFFER() to declare the IO buffers"); \ - } while (0) - - - -void usbh_lld_init(void); -void usbh_lld_start(USBHDriver *usbh); -void usbh_lld_ep_object_init(usbh_ep_t *ep); -void usbh_lld_ep_open(usbh_ep_t *ep); -void usbh_lld_ep_close(usbh_ep_t *ep); -void usbh_lld_urb_submit(usbh_urb_t *urb); -bool usbh_lld_urb_abort(usbh_urb_t *urb, usbh_urbstatus_t status); -usbh_urbstatus_t usbh_lld_root_hub_request(USBHDriver *usbh, uint8_t bmRequestType, uint8_t bRequest, - uint16_t wvalue, uint16_t windex, uint16_t wlength, uint8_t *buf); -uint8_t usbh_lld_roothub_get_statuschange_bitmap(USBHDriver *usbh); - -#define usbh_lld_epreset(ep) do {(ep)->dt_mask = HCTSIZ_DPID_DATA0;} while (0); - -#ifdef __IAR_SYSTEMS_ICC__ -#define USBH_LLD_DEFINE_BUFFER(type, name) type name -#else -#define USBH_LLD_DEFINE_BUFFER(type, name) type name __attribute__((aligned(4))) -#endif - -#endif - -#endif /* HAL_USBH_LLD_H */ diff --git a/firmware/ChibiOS_16/community/os/hal/ports/STM32/STM32F0xx/platform.mk b/firmware/ChibiOS_16/community/os/hal/ports/STM32/STM32F0xx/platform.mk deleted file mode 100644 index 377acdf34e..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/ports/STM32/STM32F0xx/platform.mk +++ /dev/null @@ -1,9 +0,0 @@ -include ${CHIBIOS}/os/hal/ports/STM32/STM32F0xx/platform.mk - -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c \ - -PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1 \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1 \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD diff --git a/firmware/ChibiOS_16/community/os/hal/ports/STM32/STM32F1xx/platform.mk b/firmware/ChibiOS_16/community/os/hal/ports/STM32/STM32F1xx/platform.mk deleted file mode 100644 index a8f21bcdf8..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/ports/STM32/STM32F1xx/platform.mk +++ /dev/null @@ -1,15 +0,0 @@ -include ${CHIBIOS}/os/hal/ports/STM32/STM32F1xx/platform.mk - -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/hal_fsmc_sdram.c - -PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1 \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1 \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1 \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD diff --git a/firmware/ChibiOS_16/community/os/hal/ports/STM32/STM32F3xx/platform.mk b/firmware/ChibiOS_16/community/os/hal/ports/STM32/STM32F3xx/platform.mk deleted file mode 100644 index 92f033ce55..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/ports/STM32/STM32F3xx/platform.mk +++ /dev/null @@ -1,10 +0,0 @@ -include ${CHIBIOS}/os/hal/ports/STM32/STM32F3xx/platform.mk - -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c \ - -PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1 \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1 \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD diff --git a/firmware/ChibiOS_16/community/os/hal/ports/STM32/STM32F4xx/platform.mk b/firmware/ChibiOS_16/community/os/hal/ports/STM32/STM32F4xx/platform.mk deleted file mode 100644 index 2bb68cd32e..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/ports/STM32/STM32F4xx/platform.mk +++ /dev/null @@ -1,21 +0,0 @@ -include ${CHIBIOS}/os/hal/ports/STM32/STM32F4xx/platform.mk - -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/hal_fsmc_sdram.c - -PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1 \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/DMA2Dv1 \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1 \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/LTDCv1 \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1 \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/USBHv1 \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD diff --git a/firmware/ChibiOS_16/community/os/hal/ports/STM32/STM32F7xx/platform.mk b/firmware/ChibiOS_16/community/os/hal/ports/STM32/STM32F7xx/platform.mk deleted file mode 100644 index 2f9392f705..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/ports/STM32/STM32F7xx/platform.mk +++ /dev/null @@ -1,9 +0,0 @@ -include ${CHIBIOS}/os/hal/ports/STM32/STM32F7xx/platform.mk - -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/hal_fsmc_sdram.c - -PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1 \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD diff --git a/firmware/ChibiOS_16/community/os/hal/src/hal_community.c b/firmware/ChibiOS_16/community/os/hal/src/hal_community.c deleted file mode 100644 index 36c5805261..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/src/hal_community.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_community.c - * @brief HAL subsystem code. - * - * @addtogroup HAL - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_COMMUNITY == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief HAL initialization (community part). - * - * @init - */ -void halCommunityInit(void) { - -#if HAL_USE_NAND || defined(__DOXYGEN__) - nandInit(); -#endif - -#if HAL_USE_EICU || defined(__DOXYGEN__) - eicuInit(); -#endif - -#if HAL_USE_CRC || defined(__DOXYGEN__) - crcInit(); -#endif - -#if HAL_USE_RNG || defined(__DOXYGEN__) - rngInit(); -#endif - -#if HAL_USE_USBH || defined(__DOXYGEN__) - usbhInit(); -#endif - -#if HAL_USE_TIMCAP || defined(__DOXYGEN__) - timcapInit(); -#endif - -#if HAL_USE_QEI || defined(__DOXYGEN__) - qeiInit(); -#endif -} - -#endif /* HAL_USE_COMMUNITY */ - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/hal/src/hal_crc.c b/firmware/ChibiOS_16/community/os/hal/src/hal_crc.c deleted file mode 100644 index 63799e4418..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/src/hal_crc.c +++ /dev/null @@ -1,264 +0,0 @@ -/* - ChibiOS - Copyright (C) 2015 Michael D. Spradling - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * Hardware Abstraction Layer for CRC Unit - */ -#include "hal.h" - -#if (HAL_USE_CRC == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief CRC Driver initialization. - * - * @init - */ -void crcInit(void) { - crc_lld_init(); -} - -/** - * @brief Initializes the standard part of a @p CRCDriver structure. - * - * @param[out] crcp Pointer to the @p CRCDriver object - * - * @init - */ -void crcObjectInit(CRCDriver *crcp) { - crcp->state = CRC_STOP; - crcp->config = NULL; -#if CRC_USE_DMA == TRUE - crcp->thread = NULL; -#endif -#if CRC_USE_MUTUAL_EXCLUSION == TRUE - osalMutexObjectInit(&crcp->mutex); -#endif -#if defined(CRC_DRIVER_EXT_INIT_HOOK) - CRC_DRIVER_EXT_INIT_HOOK(crcp); -#endif -} - -/** - * @brief Configures and activates the CRC peripheral. - * - * @param[in] crcp Pointer to the @p CRCDriver object - * @param[in] config Pointer to the @p CRCConfig object - * @p NULL if the low level driver implementation - * supports a default configuration - * - * @api - */ -void crcStart(CRCDriver *crcp, const CRCConfig *config) { - osalDbgCheck(crcp != NULL); - - osalSysLock(); - osalDbgAssert((crcp->state == CRC_STOP) || (crcp->state == CRC_READY), - "invalid state"); - crcp->config = config; - crc_lld_start(crcp); - crcp->state = CRC_READY; - osalSysUnlock(); -} - -/** - * @brief Deactivates the CRC peripheral. - * - * @param[in] crcp Pointer to the @p CRCDriver object - * - * @api - */ -void crcStop(CRCDriver *crcp) { - osalDbgCheck(crcp != NULL); - - osalSysLock(); - osalDbgAssert((crcp->state == CRC_STOP) || (crcp->state == CRC_READY), - "invalid state"); - crc_lld_stop(crcp); - crcp->state = CRC_STOP; - osalSysUnlock(); -} - -/** - * @brief Resets the CRC calculation - * - * @param[in] crcp Pointer to the @p CRCDriver object - * - * @api - */ -void crcReset(CRCDriver *crcp) { - osalSysLock(); - crcResetI(crcp); - osalSysUnlock(); -} - -/** - * @brief Resets the current CRC calculation - * - * @param[in] crcp pointer to the @p CRCDriver object - * - * @iclass - */ -void crcResetI(CRCDriver *crcp) { - osalDbgCheck(crcp != NULL); - osalDbgAssert(crcp->state == CRC_READY, "Not ready"); - crc_lld_reset(crcp); -} - -/** - * @brief Performs a CRC calculation. - * @details This synchronous function performs a crc calculation operation. - * @pre In order to use this function the driver must have been configured - * without callbacks (@p end_cb = @p NULL). - * - * @param[in] crcp pointer to the @p CRCDriver object - * @param[in] n number of bytes to send - * @param[in] buf the pointer to the buffer - * - * @api - */ -uint32_t crcCalc(CRCDriver *crcp, size_t n, const void *buf) { - uint32_t crc; -#if CRC_USE_DMA - osalSysLock(); -#endif - crc = crcCalcI(crcp, n, buf); -#if CRC_USE_DMA - osalSysUnlock(); -#endif - return crc; -} - -/** - * @brief Performs a CRC calculation. - * @details This synchronous function performs a crc calcuation operation. - * @pre In order to use this function the driver must have been configured - * without callbacks (@p end_cb = @p NULL). - * @post At the end of the operation the configured callback is invoked. - * - * @param[in] crcp pointer to the @p CRCDriver object - * @param[in] n number of bytes to send - * @param[in] buf the pointer to the buffer - * - * @iclass - */ -uint32_t crcCalcI(CRCDriver *crcp, size_t n, const void *buf) { - osalDbgCheck((crcp != NULL) && (n > 0U) && (buf != NULL)); - osalDbgAssert(crcp->state == CRC_READY, "not ready"); -#if CRC_USE_DMA - osalDbgAssert(crcp->config->end_cb == NULL, "callback defined"); - (crcp)->state = CRC_ACTIVE; -#endif - return crc_lld_calc(crcp, n, buf); -} - -#if CRC_USE_DMA == TRUE -/** - * @brief Performs a CRC calculation. - * @details This asynchronous function starts a crc calcuation operation. - * @pre In order to use this function the driver must have been configured - * with callbacks (@p end_cb != @p NULL). - * @post At the end of the operation the configured callback is invoked. - * - * @param[in] crcp pointer to the @p CRCDriver object - * @param[in] n number of bytes to send - * @param[in] buf the pointer to the buffer - * - * @api - */ -void crcStartCalc(CRCDriver *crcp, size_t n, const void *buf) { - osalSysLock(); - crcStartCalcI(crcp, n, buf); - osalSysUnlock(); -} - -/** - * @brief Performs a CRC calculation. - * @details This asynchronous function starts a crc calcuation operation. - * @pre In order to use this function the driver must have been configured - * without callbacks (@p end_cb = @p NULL). - * @post At the end of the operation the configured callback is invoked. - * - * @param[in] crcp pointer to the @p CRCDriver object - * @param[in] n number of bytes to send - * @param[in] buf the pointer to the buffer - * - * - * @iclass - */ -void crcStartCalcI(CRCDriver *crcp, size_t n, const void *buf) { - osalDbgCheck((crcp != NULL) && (n > 0U) && (buf != NULL)); - osalDbgAssert(crcp->state == CRC_READY, "not ready"); - osalDbgAssert(crcp->config->end_cb != NULL, "callback not defined"); - (crcp)->state = CRC_ACTIVE; - crc_lld_start_calc(crcp, n, buf); -} -#endif - -#if (CRC_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__) -/** - * @brief Gains exclusive access to the CRC unit. - * @details This function tries to gain ownership to the CRC, if the CRC is - * already being used then the invoking thread is queued. - * @pre In order to use this function the option @p CRC_USE_MUTUAL_EXCLUSION - * must be enabled. - * - * @param[in] crcp pointer to the @p CRCDriver object - * - * @api - */ -void crcAcquireUnit(CRCDriver *crcp) { - osalDbgCheck(crcp != NULL); - - osalMutexLock(&crcp->mutex); -} - -/** - * @brief Releases exclusive access to the CRC unit. - * @pre In order to use this function the option @p CRC_USE_MUTUAL_EXCLUSION - * must be enabled. - * - * @param[in] crcp pointer to the @p CRCDriver object - * - * @api - */ -void crcReleaseUnit(CRCDriver *crcp) { - osalDbgCheck(crcp != NULL); - - osalMutexUnlock(&crcp->mutex); -} -#endif /* CRC_USE_MUTUAL_EXCLUSION == TRUE */ - -#endif /* HAL_USE_CRC */ diff --git a/firmware/ChibiOS_16/community/os/hal/src/hal_ee24xx.c b/firmware/ChibiOS_16/community/os/hal/src/hal_ee24xx.c deleted file mode 100644 index 632ffbb3e8..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/src/hal_ee24xx.c +++ /dev/null @@ -1,353 +0,0 @@ -/* - Copyright (c) 2013 Timon Wong - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to deal - in the Software without restriction, including without limitation the rights - to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included in all - copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - THE SOFTWARE. -*/ - -/* - Copyright 2012 Uladzimir Pylinski aka barthess. - You may use this work without restrictions, as long as this notice is included. - The work is provided "as is" without warranty of any kind, neither express nor implied. -*/ - -/***************************************************************************** - * DATASHEET NOTES - ***************************************************************************** -Write cycle time (byte or page) - 5 ms - -Note: - Page write operations are limited to writing bytes within a single physical - page, regardless of the number of bytes actually being written. Physical page - boundaries start at addresses that are integer multiples of the page buffer - size (or page size and end at addresses that are integer multiples of - [page size]. If a Page Write command attempts to write across a physical - page boundary, the result is that the data wraps around to the beginning of - the current page (overwriting data previously stored there), instead of - being written to the next page as might be expected. -*********************************************************************/ - -#include "hal_ee24xx.h" -#include - -#if (defined(HAL_USE_EEPROM) && HAL_USE_EEPROM && EEPROM_USE_EE24XX) || defined(__DOXYGEN__) - -/* - ****************************************************************************** - * DEFINES - ****************************************************************************** - */ -/* -#if defined(SAM7_PLATFORM) -#define EEPROM_I2C_CLOCK (MCK / (((i2cp->config->cwgr & 0xFF) + ((i2cp->config->cwgr >> 8) & 0xFF)) * (1 << ((i2cp->config->cwgr >> 16) & 7)) + 6)) -#else -#define EEPROM_I2C_CLOCK (i2cp->config->clock_speed) -#endif -*/ -#define EEPROM_I2C_CLOCK 400000 - -/* - ****************************************************************************** - * EXTERNS - ****************************************************************************** - */ - -/* - ****************************************************************************** - * GLOBAL VARIABLES - ****************************************************************************** - */ - -/* - ******************************************************************************* - * LOCAL FUNCTIONS - ******************************************************************************* - */ -/** - * @brief Split one uint16_t address to two uint8_t. - * - * @param[in] txbuf pointer to driver transmit buffer - * @param[in] addr uint16_t address - */ -#define eeprom_split_addr(txbuf, addr){ \ - (txbuf)[0] = ((uint8_t)((addr >> 8) & 0xFF)); \ - (txbuf)[1] = ((uint8_t)(addr & 0xFF)); \ - } - -/* - ******************************************************************************* - * EXPORTED FUNCTIONS - ******************************************************************************* - */ - -/** - * @brief Calculates requred timeout. - */ -static systime_t calc_timeout(I2CDriver *i2cp, size_t txbytes, size_t rxbytes) { - (void)i2cp; - const uint32_t bitsinbyte = 10; - uint32_t tmo; - tmo = ((txbytes + rxbytes + 1) * bitsinbyte * 1000); - tmo /= EEPROM_I2C_CLOCK; - tmo += 10; /* some additional milliseconds to be safer */ - return MS2ST(tmo); -} - -/** - * @brief EEPROM read routine. - * - * @param[in] eepcfg pointer to configuration structure of eeprom file - * @param[in] offset addres of 1-st byte to be read - * @param[in] data pointer to buffer with data to be written - * @param[in] len number of bytes to be red - */ -static msg_t eeprom_read(const I2CEepromFileConfig *eepcfg, - uint32_t offset, uint8_t *data, size_t len) { - - msg_t status = MSG_RESET; - systime_t tmo = calc_timeout(eepcfg->i2cp, 2, len); - - osalDbgAssert(((len <= eepcfg->size) && ((offset + len) <= eepcfg->size)), - "out of device bounds"); - - eeprom_split_addr(eepcfg->write_buf, (offset + eepcfg->barrier_low)); - -#if I2C_USE_MUTUAL_EXCLUSION - i2cAcquireBus(eepcfg->i2cp); -#endif - - status = i2cMasterTransmitTimeout(eepcfg->i2cp, eepcfg->addr, - eepcfg->write_buf, 2, data, len, tmo); - -#if I2C_USE_MUTUAL_EXCLUSION - i2cReleaseBus(eepcfg->i2cp); -#endif - - return status; -} - -/** - * @brief EEPROM write routine. - * @details Function writes data to EEPROM. - * @pre Data must be fit to single EEPROM page. - * - * @param[in] eepcfg pointer to configuration structure of eeprom file - * @param[in] offset addres of 1-st byte to be write - * @param[in] data pointer to buffer with data to be written - * @param[in] len number of bytes to be written - */ -static msg_t eeprom_write(const I2CEepromFileConfig *eepcfg, uint32_t offset, - const uint8_t *data, size_t len) { - msg_t status = MSG_RESET; - systime_t tmo = calc_timeout(eepcfg->i2cp, (len + 2), 0); - - osalDbgAssert(((len <= eepcfg->size) && ((offset + len) <= eepcfg->size)), - "out of device bounds"); - osalDbgAssert((((offset + eepcfg->barrier_low) / eepcfg->pagesize) == - (((offset + eepcfg->barrier_low) + len - 1) / eepcfg->pagesize)), - "data can not be fitted in single page"); - - /* write address bytes */ - eeprom_split_addr(eepcfg->write_buf, (offset + eepcfg->barrier_low)); - /* write data bytes */ - memcpy(&(eepcfg->write_buf[2]), data, len); - -#if I2C_USE_MUTUAL_EXCLUSION - i2cAcquireBus(eepcfg->i2cp); -#endif - - status = i2cMasterTransmitTimeout(eepcfg->i2cp, eepcfg->addr, - eepcfg->write_buf, (len + 2), NULL, 0, tmo); - -#if I2C_USE_MUTUAL_EXCLUSION - i2cReleaseBus(eepcfg->i2cp); -#endif - - /* wait until EEPROM process data */ - chThdSleep(eepcfg->write_time); - - return status; -} - -/** - * @brief Determines and returns size of data that can be processed - */ -static size_t __clamp_size(void *ip, size_t n) { - - if (((size_t)eepfs_getposition(ip) + n) > (size_t)eepfs_getsize(ip)) - return eepfs_getsize(ip) - eepfs_getposition(ip); - else - return n; -} - -/** - * @brief Write data that can be fitted in one page boundary - */ -static void __fitted_write(void *ip, const uint8_t *data, size_t len, uint32_t *written) { - - msg_t status = MSG_RESET; - - osalDbgAssert(len != 0, "something broken in hi level part"); - - status = eeprom_write(((I2CEepromFileStream *)ip)->cfg, - eepfs_getposition(ip), data, len); - if (status == MSG_OK) { - *written += len; - eepfs_lseek(ip, eepfs_getposition(ip) + len); - } -} - -/** - * @brief Write data to EEPROM. - * @details Only one EEPROM page can be written at once. So fucntion - * splits large data chunks in small EEPROM transactions if needed. - * @note To achieve the maximum effectivity use write operations - * aligned to EEPROM page boundaries. - */ -static size_t write(void *ip, const uint8_t *bp, size_t n) { - - size_t len = 0; /* bytes to be written at one trasaction */ - uint32_t written; /* total bytes successfully written */ - uint16_t pagesize; - uint32_t firstpage; - uint32_t lastpage; - - osalDbgCheck((ip != NULL) && (((EepromFileStream *)ip)->vmt != NULL)); - - if (n == 0) - return 0; - - n = __clamp_size(ip, n); - if (n == 0) - return 0; - - pagesize = ((EepromFileStream *)ip)->cfg->pagesize; - firstpage = (((EepromFileStream *)ip)->cfg->barrier_low + - eepfs_getposition(ip)) / pagesize; - lastpage = (((EepromFileStream *)ip)->cfg->barrier_low + - eepfs_getposition(ip) + n - 1) / pagesize; - - written = 0; - /* data fitted in single page */ - if (firstpage == lastpage) { - len = n; - __fitted_write(ip, bp, len, &written); - bp += len; - return written; - } - - else { - /* write first piece of data to first page boundary */ - len = ((firstpage + 1) * pagesize) - eepfs_getposition(ip); - len -= ((EepromFileStream *)ip)->cfg->barrier_low; - __fitted_write(ip, bp, len, &written); - bp += len; - - /* now writes blocks at a size of pages (may be no one) */ - while ((n - written) > pagesize) { - len = pagesize; - __fitted_write(ip, bp, len, &written); - bp += len; - } - - /* wrtie tail */ - len = n - written; - if (len == 0) - return written; - else { - __fitted_write(ip, bp, len, &written); - } - } - - return written; -} - -/** - * Read some bytes from current position in file. After successful - * read operation the position pointer will be increased by the number - * of read bytes. - */ -static size_t read(void *ip, uint8_t *bp, size_t n) { - msg_t status = MSG_OK; - - osalDbgCheck((ip != NULL) && (((EepromFileStream *)ip)->vmt != NULL)); - - if (n == 0) - return 0; - - n = __clamp_size(ip, n); - if (n == 0) - return 0; - - /* Stupid I2C cell in STM32F1x does not allow to read single byte. - So we must read 2 bytes and return needed one. */ -#if defined(STM32F1XX_I2C) - if (n == 1) { - uint8_t __buf[2]; - /* if NOT last byte of file requested */ - if ((eepfs_getposition(ip) + 1) < eepfs_getsize(ip)) { - if (read(ip, __buf, 2) == 2) { - eepfs_lseek(ip, (eepfs_getposition(ip) + 1)); - bp[0] = __buf[0]; - return 1; - } - else - return 0; - } - else { - eepfs_lseek(ip, (eepfs_getposition(ip) - 1)); - if (read(ip, __buf, 2) == 2) { - eepfs_lseek(ip, (eepfs_getposition(ip) + 2)); - bp[0] = __buf[1]; - return 1; - } - else - return 0; - } - } -#endif /* defined(STM32F1XX_I2C) */ - - /* call low level function */ - status = eeprom_read(((I2CEepromFileStream *)ip)->cfg, - eepfs_getposition(ip), bp, n); - if (status != MSG_OK) - return 0; - else { - eepfs_lseek(ip, (eepfs_getposition(ip) + n)); - return n; - } -} - -static const struct EepromFileStreamVMT vmt = { - write, - read, - eepfs_put, - eepfs_get, - eepfs_close, - eepfs_geterror, - eepfs_getsize, - eepfs_getposition, - eepfs_lseek, -}; - -EepromDevice eepdev_24xx = { - EEPROM_DEV_24XX, - &vmt -}; - -#endif /* EEPROM_USE_EE24XX */ diff --git a/firmware/ChibiOS_16/community/os/hal/src/hal_ee25xx.c b/firmware/ChibiOS_16/community/os/hal/src/hal_ee25xx.c deleted file mode 100644 index 102aef8873..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/src/hal_ee25xx.c +++ /dev/null @@ -1,404 +0,0 @@ -/* - Copyright (c) 2013 Timon Wong - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to deal - in the Software without restriction, including without limitation the rights - to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included in all - copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - THE SOFTWARE. -*/ - -/* - Copyright 2012 Uladzimir Pylinski aka barthess. - You may use this work without restrictions, as long as this notice is included. - The work is provided "as is" without warranty of any kind, neither express nor implied. -*/ - -/***************************************************************************** - * DATASHEET NOTES - ***************************************************************************** -Write cycle time (byte or page) - 5 ms - -Note: - Page write operations are limited to writing bytes within a single physical - page, regardless of the number of bytes actually being written. Physical page - boundaries start at addresses that are integer multiples of the page buffer - size (or page size and end at addresses that are integer multiples of - [page size]. If a Page Write command attempts to write across a physical - page boundary, the result is that the data wraps around to the beginning of - the current page (overwriting data previously stored there), instead of - being written to the next page as might be expected. -*********************************************************************/ - -#include "hal_ee25xx.h" -#include - -#if (defined(HAL_USE_EEPROM) && HAL_USE_EEPROM && EEPROM_USE_EE25XX) || defined(__DOXYGEN__) - -/** - * @name Commands of 25XX chip. - * @{ - */ -#define CMD_READ 0x03 /**< @brief Read data from memory array beginning at - selected address. */ -#define CMD_WRITE 0x02 /**< @brief Write data to memory array beginning at - selected address. */ -#define CMD_WRDI 0x04 /**< Reset the write enable latch (disable write - operations). */ -#define CMD_WREN 0x06 /**< Set the write enable latch (enable write - operations). */ -#define CMD_RDSR 0x05 /**< Read STATUS register. */ -#define CMD_WRSR 0x01 /**< Write STATUS register. */ - -/** @} */ - -/** - * @name Status of 25XX chip. - * @{} - */ -#define STAT_BP1 0x08 /**< @brief Block protection (high). */ -#define STAT_BP0 0x04 /**< @brief Block protection (low). */ -#define STAT_WEL 0x02 /**< @brief Write enable latch. */ -#define STAT_WIP 0x01 /**< @brief Write-In-Progress. */ - -/** @} */ - -/** - * @brief 25XX low level write then read rountine. - * - * @param[in] eepcfg pointer to configuration structure of eeprom file. - * @param[in] txbuf pointer to buffer to be transfered. - * @param[in] txlen number of bytes to be transfered. - * @param[out] rxbuf pointer to buffer to be received. - * @param[in] rxlen number of bytes to be received. - */ -static void ll_25xx_transmit_receive(const SPIEepromFileConfig *eepcfg, - const uint8_t *txbuf, size_t txlen, - uint8_t *rxbuf, size_t rxlen) { - -#if SPI_USE_MUTUAL_EXCLUSION - spiAcquireBus(eepcfg->spip); -#endif - spiSelect(eepcfg->spip); - spiSend(eepcfg->spip, txlen, txbuf); - if (rxlen) /* Check if receive is needed. */ - spiReceive(eepcfg->spip, rxlen, rxbuf); - spiUnselect(eepcfg->spip); - -#if SPI_USE_MUTUAL_EXCLUSION - spiReleaseBus(eepcfg->spip); -#endif -} - -/** - * @brief Check whether the device is busy (writing in progress). - * - * @param[in] eepcfg pointer to configuration structure of eeprom file. - * @return @p true on busy. - */ -static bool ll_eeprom_is_busy(const SPIEepromFileConfig *eepcfg) { - - uint8_t cmd = CMD_RDSR; - uint8_t stat; - ll_25xx_transmit_receive(eepcfg, &cmd, 1, &stat, 1); - if (stat & STAT_WIP) - return TRUE; - return FALSE; -} - -/** - * @brief Lock device. - * - * @param[in] eepcfg pointer to configuration structure of eeprom file. - */ -static void ll_eeprom_lock(const SPIEepromFileConfig *eepcfg) { - - uint8_t cmd = CMD_WRDI; - ll_25xx_transmit_receive(eepcfg, &cmd, 1, NULL, 0); -} - -/** - * @brief Unlock device. - * - * @param[in] eepcfg pointer to configuration structure of eeprom file. - */ -static void ll_eeprom_unlock(const SPIEepromFileConfig *eepcfg) { - - uint8_t cmd = CMD_WREN; - ll_25xx_transmit_receive(eepcfg, &cmd, 1, NULL, 0); -} - -/** - * @brief Prepare byte sequence for command and address - * - * @param[in] seq pointer to first 3byte sequence - * @param[in] size size of the eeprom device - * @param[in] cmd command - * @param[in] addr address - * @return number of bytes of this sequence - */ -static uint8_t ll_eeprom_prepare_seq(uint8_t *seq, uint32_t size, uint8_t cmd, - uint32_t addr) { - - seq[0] = ((uint8_t)cmd & 0xff); - - if (size > 0xffffUL) { - /* High density, 24bit address. */ - seq[1] = (uint8_t)((addr >> 16) & 0xff); - seq[2] = (uint8_t)((addr >> 8) & 0xff); - seq[3] = (uint8_t)(addr & 0xff); - return 4; - } - else if (size > 0x00ffUL) { - /* Medium density, 16bit address. */ - seq[1] = (uint8_t)((addr >> 8) & 0xff); - seq[2] = (uint8_t)(addr & 0xff); - return 3; - } - - /* Low density, 8bit address. */ - seq[1] = (uint8_t)(addr & 0xff); - return 2; -} - -/** - * @brief EEPROM read routine. - * - * @param[in] eepcfg pointer to configuration structure of eeprom file. - * @param[in] offset addres of 1-st byte to be read. - * @param[out] data pointer to buffer with data to be written. - * @param[in] len number of bytes to be red. - */ -static msg_t ll_eeprom_read(const SPIEepromFileConfig *eepcfg, uint32_t offset, - uint8_t *data, size_t len) { - - uint8_t txbuff[4]; - uint8_t txlen; - - osalDbgAssert(((len <= eepcfg->size) && ((offset + len) <= eepcfg->size)), - "out of device bounds"); - - if (eepcfg->spip->state != SPI_READY) - return MSG_RESET; - - txlen = ll_eeprom_prepare_seq(txbuff, eepcfg->size, CMD_READ, - (offset + eepcfg->barrier_low)); - ll_25xx_transmit_receive(eepcfg, txbuff, txlen, data, len); - - return MSG_OK; -} - -/** - * @brief EEPROM write routine. - * @details Function writes data to EEPROM. - * @pre Data must be fit to single EEPROM page. - * - * @param[in] eepcfg pointer to configuration structure of eeprom file. - * @param[in] offset addres of 1-st byte to be writen. - * @param[in] data pointer to buffer with data to be written. - * @param[in] len number of bytes to be written. - */ -static msg_t ll_eeprom_write(const SPIEepromFileConfig *eepcfg, uint32_t offset, - const uint8_t *data, size_t len) { - - uint8_t txbuff[4]; - uint8_t txlen; - systime_t now; - - osalDbgAssert(((len <= eepcfg->size) && ((offset + len) <= eepcfg->size)), - "out of device bounds"); - osalDbgAssert((((offset + eepcfg->barrier_low) / eepcfg->pagesize) == - (((offset + eepcfg->barrier_low) + len - 1) / eepcfg->pagesize)), - "data can not be fitted in single page"); - - if (eepcfg->spip->state != SPI_READY) - return MSG_RESET; - - /* Unlock array for writting. */ - ll_eeprom_unlock(eepcfg); - -#if SPI_USE_MUTUAL_EXCLUSION - spiAcquireBus(eepcfg->spip); -#endif - - spiSelect(eepcfg->spip); - txlen = ll_eeprom_prepare_seq(txbuff, eepcfg->size, CMD_WRITE, - (offset + eepcfg->barrier_low)); - spiSend(eepcfg->spip, txlen, txbuff); - spiSend(eepcfg->spip, len, data); - spiUnselect(eepcfg->spip); - -#if SPI_USE_MUTUAL_EXCLUSION - spiReleaseBus(eepcfg->spip); -#endif - - /* Wait until EEPROM process data. */ - now = chVTGetSystemTimeX(); - while (ll_eeprom_is_busy(eepcfg)) { - if ((chVTGetSystemTimeX() - now) > eepcfg->write_time) { - return MSG_TIMEOUT; - } - - chThdYield(); - } - - /* Lock array preventing unexpected access */ - ll_eeprom_lock(eepcfg); - return MSG_OK; -} - -/** - * @brief Determines and returns size of data that can be processed - */ -static size_t __clamp_size(void *ip, size_t n) { - - if (((size_t)eepfs_getposition(ip) + n) > (size_t)eepfs_getsize(ip)) - return eepfs_getsize(ip) - eepfs_getposition(ip); - else - return n; -} - -/** - * @brief Write data that can be fitted in one page boundary - */ -static msg_t __fitted_write(void *ip, const uint8_t *data, size_t len, uint32_t *written) { - - msg_t status = MSG_RESET; - - osalDbgAssert(len != 0, "something broken in hi level part"); - - status = ll_eeprom_write(((SPIEepromFileStream *)ip)->cfg, - eepfs_getposition(ip), data, len); - if (status == MSG_OK) { - *written += len; - eepfs_lseek(ip, eepfs_getposition(ip) + len); - } - return status; -} - -/** - * @brief Write data to EEPROM. - * @details Only one EEPROM page can be written at once. So fucntion - * splits large data chunks in small EEPROM transactions if needed. - * @note To achieve the maximum effectivity use write operations - * aligned to EEPROM page boundaries. - */ -static size_t write(void *ip, const uint8_t *bp, size_t n) { - - size_t len = 0; /* bytes to be written at one trasaction */ - uint32_t written; /* total bytes successfully written */ - uint16_t pagesize; - uint32_t firstpage; - uint32_t lastpage; - - volatile const SPIEepromFileConfig *cfg = ((SPIEepromFileStream *)ip)->cfg; - - osalDbgCheck((ip != NULL) && (((SPIEepromFileStream *)ip)->vmt != NULL)); - - if (n == 0) - return 0; - - n = __clamp_size(ip, n); - if (n == 0) - return 0; - - pagesize = cfg->pagesize; - firstpage = (cfg->barrier_low + eepfs_getposition(ip)) / pagesize; - lastpage = ((cfg->barrier_low + eepfs_getposition(ip) + n) - 1) / pagesize; - - written = 0; - /* data fitted in single page */ - if (firstpage == lastpage) { - len = n; - __fitted_write(ip, bp, len, &written); - bp += len; - return written; - } - else { - /* write first piece of data to first page boundary */ - len = ((firstpage + 1) * pagesize) - eepfs_getposition(ip); - len -= cfg->barrier_low; - __fitted_write(ip, bp, len, &written); - bp += len; - - /* now writes blocks at a size of pages (may be no one) */ - while ((n - written) > pagesize) { - len = pagesize; - if (__fitted_write(ip, bp, len, &written) != MSG_OK) // Fixed: Would increase bp forever and crash in case of timeouts... - return written; - - bp += len; - } - - - /* wrtie tail */ - len = n - written; - if (len == 0) - return written; - else { - __fitted_write(ip, bp, len, &written); - } - } - - return written; -} - -/** - * Read some bytes from current position in file. After successful - * read operation the position pointer will be increased by the number - * of read bytes. - */ -static size_t read(void *ip, uint8_t *bp, size_t n) { - - msg_t status = MSG_OK; - - osalDbgCheck((ip != NULL) && (((EepromFileStream *)ip)->vmt != NULL)); - - if (n == 0) - return 0; - - n = __clamp_size(ip, n); - if (n == 0) - return 0; - - /* call low level function */ - status = ll_eeprom_read(((SPIEepromFileStream *)ip)->cfg, - eepfs_getposition(ip), bp, n); - if (status != MSG_OK) - return 0; - else { - eepfs_lseek(ip, (eepfs_getposition(ip) + n)); - return n; - } -} - -static const struct EepromFileStreamVMT vmt = { - write, - read, - eepfs_put, - eepfs_get, - eepfs_close, - eepfs_geterror, - eepfs_getsize, - eepfs_getposition, - eepfs_lseek, -}; - -EepromDevice eepdev_25xx = { - EEPROM_DEV_25XX, - &vmt -}; - -#endif /* EEPROM_USE_EE25XX */ diff --git a/firmware/ChibiOS_16/community/os/hal/src/hal_eeprom.c b/firmware/ChibiOS_16/community/os/hal/src/hal_eeprom.c deleted file mode 100644 index f77d616daf..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/src/hal_eeprom.c +++ /dev/null @@ -1,197 +0,0 @@ -/* - Copyright (c) 2013 Timon Wong - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to deal - in the Software without restriction, including without limitation the rights - to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included in all - copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - THE SOFTWARE. -*/ - -/* - Copyright 2012 Uladzimir Pylinski aka barthess. - You may use this work without restrictions, as long as this notice is included. - The work is provided "as is" without warranty of any kind, neither express nor implied. -*/ - -#include "hal_eeprom.h" -#include - -#if defined(HAL_USE_EEPROM) && HAL_USE_EEPROM - -extern EepromDevice eepdev_24xx; -extern EepromDevice eepdev_25xx; - -EepromDevice *__eeprom_drv_table[] = { - /* I2C related. */ -#if HAL_USE_I2C - -# if EEPROM_USE_EE24XX - &eepdev_24xx, -# endif - -#endif /* HAL_USE_I2C */ - - /* SPI related. */ -#if HAL_USE_SPI - -# if EEPROM_USE_EE25XX - &eepdev_25xx, -# endif - -#endif /* HAL_USE_SPI */ -}; - - -/** - * @breif Find low level EEPROM device by id. - */ -const EepromDevice *EepromFindDevice(uint8_t id) { - - uint8_t i; - const EepromDevice *drv; - - for (i = 0; i < EEPROM_TABLE_SIZE; i++) { - drv = __eeprom_drv_table[i]; - if (drv->id == id) { - return drv; - } - } - - return NULL; -} - -/** - * Open EEPROM IC as file and return pointer to the file stream object - * @note Fucntion allways successfully open file. All checking makes - * in read/write functions. - */ -EepromFileStream *EepromFileOpen(EepromFileStream *efs, - const EepromFileConfig *eepcfg, - const EepromDevice *eepdev) { - - osalDbgAssert((efs != NULL) && (eepcfg != NULL) && (eepdev != NULL) && - (eepdev->efsvmt != NULL), "EepromFileOpen"); - osalDbgAssert(efs->vmt != eepdev->efsvmt, "File allready opened"); - osalDbgAssert(eepcfg->barrier_hi > eepcfg->barrier_low, "Low barrier exceeds High barrier"); - osalDbgAssert(eepcfg->pagesize < eepcfg->size, "Pagesize cannot be lager than EEPROM size"); - osalDbgAssert(eepcfg->barrier_hi <= eepcfg->size, "Barrier exceeds EEPROM size"); - - efs->vmt = eepdev->efsvmt; - efs->cfg = eepcfg; - efs->errors = FILE_OK; - efs->position = 0; - return (EepromFileStream *)efs; -} - -uint8_t EepromReadByte(EepromFileStream *efs) { - - uint8_t buf; - fileStreamRead(efs, &buf, sizeof(buf)); - return buf; -} - -uint16_t EepromReadHalfword(EepromFileStream *efs) { - - uint16_t buf; - fileStreamRead(efs, (uint8_t *)&buf, sizeof(buf)); - return buf; -} - -uint32_t EepromReadWord(EepromFileStream *efs) { - - uint32_t buf; - fileStreamRead(efs, (uint8_t *)&buf, sizeof(buf)); - return buf; -} - -size_t EepromWriteByte(EepromFileStream *efs, uint8_t data) { - - return fileStreamWrite(efs, &data, sizeof(data)); -} - -size_t EepromWriteHalfword(EepromFileStream *efs, uint16_t data) { - - return fileStreamWrite(efs, (uint8_t *)&data, sizeof(data)); -} - -size_t EepromWriteWord(EepromFileStream *efs, uint32_t data) { - - return fileStreamWrite(efs, (uint8_t *)&data, sizeof(data)); -} - -msg_t eepfs_getsize(void *ip) { - - uint32_t h, l; - - osalDbgCheck((ip != NULL) && (((EepromFileStream *)ip)->vmt != NULL) && - (((EepromFileStream *)ip)->cfg != NULL)); - - h = ((EepromFileStream *)ip)->cfg->barrier_hi; - l = ((EepromFileStream *)ip)->cfg->barrier_low; - return h - l; -} - -msg_t eepfs_getposition(void *ip) { - - osalDbgCheck((ip != NULL) && (((EepromFileStream *)ip)->vmt != NULL)); - - return ((EepromFileStream *)ip)->position; -} - -msg_t eepfs_lseek(void *ip, fileoffset_t offset) { - - uint32_t size; - - osalDbgCheck((ip != NULL) && (((EepromFileStream *)ip)->vmt != NULL)); - - size = eepfs_getsize(ip); - if (offset > size) - offset = size; - ((EepromFileStream *)ip)->position = offset; - return offset; -} - -msg_t eepfs_close(void *ip) { - - osalDbgCheck((ip != NULL) && (((EepromFileStream *)ip)->vmt != NULL)); - - ((EepromFileStream *)ip)->errors = FILE_OK; - ((EepromFileStream *)ip)->position = 0; - ((EepromFileStream *)ip)->vmt = NULL; - ((EepromFileStream *)ip)->cfg = NULL; - return FILE_OK; -} - -msg_t eepfs_geterror(void *ip) { - - osalDbgCheck((ip != NULL) && (((EepromFileStream *)ip)->vmt != NULL)); - return ((EepromFileStream *)ip)->errors; -} - -msg_t eepfs_put(void *ip, uint8_t b) { - - (void)ip; - (void)b; - return 0; -} - -msg_t eepfs_get(void *ip) { - - (void)ip; - return 0; -} - -#endif /* #if defined(HAL_USE_EEPROM) && HAL_USE_EEPROM */ diff --git a/firmware/ChibiOS_16/community/os/hal/src/hal_eicu.c b/firmware/ChibiOS_16/community/os/hal/src/hal_eicu.c deleted file mode 100644 index f75c58b052..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/src/hal_eicu.c +++ /dev/null @@ -1,153 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Rewritten by Emil Fresk (1/5 - 2014) for extended input capture - functionality. And fix for spurious callbacks in the interrupt handler. -*/ -/* - Improved by Uladzimir Pylinsky aka barthess (1/3 - 2015) for support of - 32-bit timers and timers with single capture/compare channels. -*/ - -/* - * Hardware Abstraction Layer for Extended Input Capture Unit - */ -#include "hal.h" - -#if (HAL_USE_EICU == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief EICU Driver initialization. - * - * @init - */ -void eicuInit(void) { - - eicu_lld_init(); -} - -/** - * @brief Initializes the standard part of a @p EICUDriver structure. - * - * @param[out] eicup Pointer to the @p EICUDriver object - * - * @init - */ -void eicuObjectInit(EICUDriver *eicup) { - - eicup->state = EICU_STOP; - eicup->config = NULL; -} - -/** - * @brief Configures and activates the EICU peripheral. - * - * @param[in] eicup Pointer to the @p EICUDriver object - * @param[in] config Pointer to the @p EICUConfig object - * - * @api - */ -void eicuStart(EICUDriver *eicup, const EICUConfig *config) { - - osalDbgCheck((eicup != NULL) && (config != NULL)); - - osalSysLock(); - osalDbgAssert((eicup->state == EICU_STOP) || (eicup->state == EICU_READY), - "invalid state"); - eicup->config = config; - eicu_lld_start(eicup); - eicup->state = EICU_READY; - osalSysUnlock(); -} - -/** - * @brief Deactivates the EICU peripheral. - * - * @param[in] eicup Pointer to the @p EICUDriver object - * - * @api - */ -void eicuStop(EICUDriver *eicup) { - - osalDbgCheck(eicup != NULL); - - osalSysLock(); - osalDbgAssert((eicup->state == EICU_STOP) || (eicup->state == EICU_READY), - "invalid state"); - eicu_lld_stop(eicup); - eicup->state = EICU_STOP; - osalSysUnlock(); -} - -/** - * @brief Enables the extended input capture. - * - * @param[in] eicup Pointer to the @p EICUDriver object - * - * @api - */ -void eicuEnable(EICUDriver *eicup) { - - osalDbgCheck(eicup != NULL); - - osalSysLock(); - osalDbgAssert(eicup->state == EICU_READY, "invalid state"); - eicu_lld_enable(eicup); - eicup->state = EICU_WAITING; - osalSysUnlock(); -} - -/** - * @brief Disables the extended input capture. - * - * @param[in] eicup Pointer to the @p EICUDriver object - * - * @api - */ -void eicuDisable(EICUDriver *eicup) { - - osalDbgCheck(eicup != NULL); - - osalSysLock(); - osalDbgAssert((eicup->state == EICU_READY) || (eicup->state == EICU_IDLE) || - (eicup->state == EICU_ACTIVE) || (eicup->state == EICU_WAITING), - "invalid state"); - eicu_lld_disable(eicup); - eicup->state = EICU_READY; - osalSysUnlock(); -} - -#endif /* HAL_USE_EICU */ diff --git a/firmware/ChibiOS_16/community/os/hal/src/hal_nand.c b/firmware/ChibiOS_16/community/os/hal/src/hal_nand.c deleted file mode 100644 index a2101d6907..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/src/hal_nand.c +++ /dev/null @@ -1,559 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file nand.c - * @brief NAND Driver code. - * - * @addtogroup NAND - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_NAND == TRUE) || defined(__DOXYGEN__) - -#include "string.h" /* for memset */ - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Check page size. - * - * @param[in] page_data_size size of page data area - * - * @notapi - */ -static void pagesize_check(size_t page_data_size) { - - /* Page size out of bounds.*/ - osalDbgCheck((page_data_size >= NAND_MIN_PAGE_SIZE) && - (page_data_size <= NAND_MAX_PAGE_SIZE)); - - /* Page size must be power of 2.*/ - osalDbgCheck(((page_data_size - 1) & page_data_size) == 0); -} - -/** - * @brief Translate block-page-offset scheme to NAND internal address. - * - * @param[in] cfg pointer to the @p NANDConfig from - * corresponding NAND driver - * @param[in] block block number - * @param[in] page page number related to begin of block - * @param[in] page_offset data offset related to begin of page - * @param[out] addr buffer to store calculated address - * @param[in] addr_len length of address buffer - * - * @notapi - */ -static void calc_addr(const NANDConfig *cfg, uint32_t block, uint32_t page, - uint32_t page_offset, uint8_t *addr, size_t addr_len) { - size_t i; - uint32_t row; - - osalDbgCheck(cfg->rowcycles + cfg->colcycles == addr_len); - osalDbgCheck((block < cfg->blocks) && (page < cfg->pages_per_block) && - (page_offset < cfg->page_data_size + cfg->page_spare_size)); - - row = (block * cfg->pages_per_block) + page; - for (i=0; icolcycles; i++){ - addr[i] = page_offset & 0xFF; - page_offset = page_offset >> 8; - } - for (; i> 8; - } -} - -/** - * @brief Translate block number to NAND internal address. - * @note This function designed for erasing purpose. - * - * @param[in] cfg pointer to the @p NANDConfig from - * corresponding NAND driver - * @param[in] block block number - * @param[out] addr buffer to store calculated address - * @param[in] addr_len length of address buffer - * - * @notapi - */ -static void calc_blk_addr(const NANDConfig *cfg, uint32_t block, - uint8_t *addr, size_t addr_len) { - size_t i; - uint32_t row; - - osalDbgCheck(cfg->rowcycles == addr_len); /* Incorrect buffer length */ - osalDbgCheck(block < cfg->blocks); /* Overflow */ - - row = block * cfg->pages_per_block; - for (i=0; i> 8; - } -} - -/** - * @brief Read block badness mark directly from NAND memory array. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] block block number - * - * @return block condition - * @retval true if the block is bad. - * @retval false if the block is good. - * - * @notapi - */ -static bool read_is_block_bad(NANDDriver *nandp, size_t block) { - - uint16_t badmark0 = nandReadBadMark(nandp, block, 0); - uint16_t badmark1 = nandReadBadMark(nandp, block, 1); - - if ((0xFFFF != badmark0) || (0xFFFF != badmark1)) - return true; - else - return false; -} - -/** - * @brief Scan for bad blocks and fill map with their numbers. - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @notapi - */ -static void scan_bad_blocks(NANDDriver *nandp) { - - const size_t blocks = nandp->config->blocks; - size_t b; - - osalDbgCheck(bitmapGetBitsCount(nandp->bb_map) >= blocks); - - /* clear map just to be safe */ - bitmapObjectInit(nandp->bb_map, 0); - - /* now write numbers of bad block to map */ - for (b=0; bbb_map, b); - } - } -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief NAND Driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void nandInit(void) { - - nand_lld_init(); -} - -/** - * @brief Initializes the standard part of a @p NANDDriver structure. - * - * @param[out] nandp pointer to the @p NANDDriver object - * - * @init - */ -void nandObjectInit(NANDDriver *nandp) { - -#if NAND_USE_MUTUAL_EXCLUSION -#if CH_CFG_USE_MUTEXES - chMtxObjectInit(&nandp->mutex); -#else - chSemObjectInit(&nandp->semaphore, 1); -#endif /* CH_CFG_USE_MUTEXES */ -#endif /* NAND_USE_MUTUAL_EXCLUSION */ - - nandp->state = NAND_STOP; - nandp->config = NULL; -} - -/** - * @brief Configures and activates the NAND peripheral. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] config pointer to the @p NANDConfig object - * @param[in] bb_map pointer to the bad block map or @NULL if not need - * - * @api - */ -void nandStart(NANDDriver *nandp, const NANDConfig *config, bitmap_t *bb_map) { - - osalDbgCheck((nandp != NULL) && (config != NULL)); - osalDbgAssert((nandp->state == NAND_STOP) || - (nandp->state == NAND_READY), - "invalid state"); - - nandp->config = config; - pagesize_check(nandp->config->page_data_size); - nand_lld_start(nandp); - nandp->state = NAND_READY; - nand_lld_reset(nandp); - - if (NULL != bb_map) { - nandp->bb_map = bb_map; - scan_bad_blocks(nandp); - } -} - -/** - * @brief Deactivates the NAND peripheral. - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @api - */ -void nandStop(NANDDriver *nandp) { - - osalDbgCheck(nandp != NULL); - osalDbgAssert((nandp->state == NAND_STOP) || - (nandp->state == NAND_READY), - "invalid state"); - nand_lld_stop(nandp); - nandp->state = NAND_STOP; -} - -/** - * @brief Read whole page. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] block block number - * @param[in] page page number related to begin of block - * @param[out] data buffer to store data, half word aligned - * @param[in] datalen length of data buffer in bytes, half word aligned - * - * @api - */ -void nandReadPageWhole(NANDDriver *nandp, uint32_t block, uint32_t page, - void *data, size_t datalen) { - - const NANDConfig *cfg = nandp->config; - const size_t addrlen = cfg->rowcycles + cfg->colcycles; - uint8_t addr[addrlen]; - - osalDbgCheck((nandp != NULL) && (data != NULL)); - osalDbgCheck((datalen <= (cfg->page_data_size + cfg->page_spare_size))); - osalDbgAssert(nandp->state == NAND_READY, "invalid state"); - - calc_addr(cfg, block, page, 0, addr, addrlen); - nand_lld_read_data(nandp, data, datalen, addr, addrlen, NULL); -} - -/** - * @brief Write whole page. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] block block number - * @param[in] page page number related to begin of block - * @param[in] data buffer with data to be written, half word aligned - * @param[in] datalen length of data buffer in bytes, half word aligned - * - * @return The operation status reported by NAND IC (0x70 command). - * - * @api - */ -uint8_t nandWritePageWhole(NANDDriver *nandp, uint32_t block, uint32_t page, - const void *data, size_t datalen) { - - uint8_t retval; - const NANDConfig *cfg = nandp->config; - const size_t addrlen = cfg->rowcycles + cfg->colcycles; - uint8_t addr[addrlen]; - - osalDbgCheck((nandp != NULL) && (data != NULL)); - osalDbgCheck((datalen <= (cfg->page_data_size + cfg->page_spare_size))); - osalDbgAssert(nandp->state == NAND_READY, "invalid state"); - - calc_addr(cfg, block, page, 0, addr, addrlen); - retval = nand_lld_write_data(nandp, data, datalen, addr, addrlen, NULL); - return retval; -} - -/** - * @brief Read page data without spare area. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] block block number - * @param[in] page page number related to begin of block - * @param[out] data buffer to store data, half word aligned - * @param[in] datalen length of data buffer in bytes, half word aligned - * @param[out] ecc pointer to calculated ECC. Ignored when NULL. - * - * @api - */ -void nandReadPageData(NANDDriver *nandp, uint32_t block, uint32_t page, - void *data, size_t datalen, uint32_t *ecc) { - - const NANDConfig *cfg = nandp->config; - const size_t addrlen = cfg->rowcycles + cfg->colcycles; - uint8_t addr[addrlen]; - - osalDbgCheck((nandp != NULL) && (data != NULL)); - osalDbgCheck((datalen <= cfg->page_data_size)); - osalDbgAssert(nandp->state == NAND_READY, "invalid state"); - - calc_addr(cfg, block, page, 0, addr, addrlen); - nand_lld_read_data(nandp, data, datalen, addr, addrlen, ecc); -} - -/** - * @brief Write page data without spare area. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] block block number - * @param[in] page page number related to begin of block - * @param[in] data buffer with data to be written, half word aligned - * @param[in] datalen length of data buffer in bytes, half word aligned - * @param[out] ecc pointer to calculated ECC. Ignored when NULL. - * - * @return The operation status reported by NAND IC (0x70 command). - * - * @api - */ -uint8_t nandWritePageData(NANDDriver *nandp, uint32_t block, uint32_t page, - const void *data, size_t datalen, uint32_t *ecc) { - - uint8_t retval; - const NANDConfig *cfg = nandp->config; - const size_t addrlen = cfg->rowcycles + cfg->colcycles; - uint8_t addr[addrlen]; - - osalDbgCheck((nandp != NULL) && (data != NULL)); - osalDbgCheck((datalen <= cfg->page_data_size)); - osalDbgAssert(nandp->state == NAND_READY, "invalid state"); - - calc_addr(cfg, block, page, 0, addr, addrlen); - retval = nand_lld_write_data(nandp, data, datalen, addr, addrlen, ecc); - return retval; -} - -/** - * @brief Read page spare area. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] block block number - * @param[in] page page number related to begin of block - * @param[out] spare buffer to store data, half word aligned - * @param[in] sparelen length of data buffer in bytes, half word aligned - * - * @api - */ -void nandReadPageSpare(NANDDriver *nandp, uint32_t block, uint32_t page, - void *spare, size_t sparelen) { - - const NANDConfig *cfg = nandp->config; - const size_t addrlen = cfg->rowcycles + cfg->colcycles; - uint8_t addr[addrlen]; - - osalDbgCheck((NULL != spare) && (nandp != NULL)); - osalDbgCheck(sparelen <= cfg->page_spare_size); - osalDbgAssert(nandp->state == NAND_READY, "invalid state"); - - calc_addr(cfg, block, page, cfg->page_data_size, addr, addrlen); - nand_lld_read_data(nandp, spare, sparelen, addr, addrlen, NULL); -} - -/** - * @brief Write page spare area. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] block block number - * @param[in] page page number related to begin of block - * @param[in] spare buffer with spare data to be written, half word aligned - * @param[in] sparelen length of data buffer in bytes, half word aligned - * - * @return The operation status reported by NAND IC (0x70 command). - * - * @api - */ -uint8_t nandWritePageSpare(NANDDriver *nandp, uint32_t block, uint32_t page, - const void *spare, size_t sparelen) { - - const NANDConfig *cfg = nandp->config; - const size_t addrlen = cfg->rowcycles + cfg->colcycles; - uint8_t addr[addrlen]; - - osalDbgCheck((NULL != spare) && (nandp != NULL)); - osalDbgCheck(sparelen <= cfg->page_spare_size); - osalDbgAssert(nandp->state == NAND_READY, "invalid state"); - - calc_addr(cfg, block, page, cfg->page_data_size, addr, addrlen); - return nand_lld_write_data(nandp, spare, sparelen, addr, addrlen, NULL); -} - -/** - * @brief Mark block as bad. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] block block number - * - * @api - */ -void nandMarkBad(NANDDriver *nandp, uint32_t block) { - - uint16_t bb_mark = 0; - - nandWritePageSpare(nandp, block, 0, &bb_mark, sizeof(bb_mark)); - nandWritePageSpare(nandp, block, 1, &bb_mark, sizeof(bb_mark)); - - if (NULL != nandp->bb_map) - bitmapSet(nandp->bb_map, block); -} - -/** - * @brief Read bad mark out. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] block block number - * @param[in] page page number related to begin of block - * - * @return Bad mark. - * - * @api - */ -uint16_t nandReadBadMark(NANDDriver *nandp, uint32_t block, uint32_t page) { - uint16_t bb_mark; - - nandReadPageSpare(nandp, block, page, &bb_mark, sizeof(bb_mark)); - return bb_mark; -} - -/** - * @brief Erase block. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] block block number - * - * @return The operation status reported by NAND IC (0x70 command). - * - * @api - */ -uint8_t nandErase(NANDDriver *nandp, uint32_t block) { - - const NANDConfig *cfg = nandp->config; - const size_t addrlen = cfg->rowcycles; - uint8_t addr[addrlen]; - - osalDbgCheck(nandp != NULL); - osalDbgAssert(nandp->state == NAND_READY, "invalid state"); - - calc_blk_addr(cfg, block, addr, addrlen); - return nand_lld_erase(nandp, addr, addrlen); -} - -/** - * @brief Check block badness. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] block block number - * - * @return block condition - * @retval true if the block is bad. - * @retval false if the block is good. - * - * @api - */ -bool nandIsBad(NANDDriver *nandp, uint32_t block) { - - osalDbgCheck(nandp != NULL); - osalDbgAssert(nandp->state == NAND_READY, "invalid state"); - - if (NULL != nandp->bb_map) - return 1 == bitmapGet(nandp->bb_map, block); - else - return read_is_block_bad(nandp, block); -} - -#if NAND_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) -/** - * @brief Gains exclusive access to the NAND bus. - * @details This function tries to gain ownership to the NAND bus, if the bus - * is already being used then the invoking thread is queued. - * @pre In order to use this function the option - * @p NAND_USE_MUTUAL_EXCLUSION must be enabled. - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @api - */ -void nandAcquireBus(NANDDriver *nandp) { - - osalDbgCheck(nandp != NULL); - -#if CH_CFG_USE_MUTEXES - chMtxLock(&nandp->mutex); -#elif CH_CFG_USE_SEMAPHORES - chSemWait(&nandp->semaphore); -#endif -} - -/** - * @brief Releases exclusive access to the NAND bus. - * @pre In order to use this function the option - * @p NAND_USE_MUTUAL_EXCLUSION must be enabled. - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @api - */ -void nandReleaseBus(NANDDriver *nandp) { - - osalDbgCheck(nandp != NULL); - -#if CH_CFG_USE_MUTEXES - chMtxUnlock(&nandp->mutex); -#elif CH_CFG_USE_SEMAPHORES - chSemSignal(&nandp->semaphore); -#endif -} -#endif /* NAND_USE_MUTUAL_EXCLUSION */ - -#endif /* HAL_USE_NAND */ - -/** @} */ - - - - diff --git a/firmware/ChibiOS_16/community/os/hal/src/hal_onewire.c b/firmware/ChibiOS_16/community/os/hal/src/hal_onewire.c deleted file mode 100644 index 06e63e68d3..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/src/hal_onewire.c +++ /dev/null @@ -1,889 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/*===========================================================================*/ -/* Main ideas: */ -/*=========================================================================== - -1) switch PWM output pin to open drain mode. -2) start 2 channels _simultaneously_. First (master channel) generates - pulses (read time slots) second (sample channel) generates interrupts - from where read pin function will be called. - -- --------------------------------------- master channel generates pulses - | / . - --............................. <---------- slave (not)pulls down bus here -- -------------------------------- sample channel reads pad state - | | - ------------- - ^ - | read interrupt fires here - -For data write it is only master channel needed. Data bit width updates -on every timer overflow event. -*/ - -/*===========================================================================*/ -/* General recommendations for strong pull usage */ -/*=========================================================================== - * 1) Use separate power rail instead of strong pull up whenever possible. - * Driver's strong pull up feature is very sensible to interrupt jitter. - * 2) Use specialized 1-wire bus master (DS2484 for example) if you are - * forced to handle bus requiring strong pull up feature. - */ - -/** - * @file hal_onewire.c - * @brief 1-wire Driver code. - * - * @addtogroup onewire - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_ONEWIRE == TRUE) || defined(__DOXYGEN__) - -#include -#include - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ -/** - * @brief 1MHz clock for PWM driver. - */ -#define ONEWIRE_PWM_FREQUENCY 1000000 - -/** - * @brief Pulse width constants in microseconds. - * @details Inspired by Microchip's AN1199 - * "1-Wire® Communication with PIC® Microcontroller" - */ -#define ONEWIRE_ZERO_WIDTH 60 -#define ONEWIRE_ONE_WIDTH 6 -#define ONEWIRE_SAMPLE_WIDTH 15 -#define ONEWIRE_RECOVERY_WIDTH 10 -#define ONEWIRE_RESET_LOW_WIDTH 480 -#define ONEWIRE_RESET_SAMPLE_WIDTH 550 -#define ONEWIRE_RESET_TOTAL_WIDTH 960 - -/** - * @brief Local function declarations. - */ -static void ow_reset_cb(PWMDriver *pwmp, onewireDriver *owp); -static void pwm_reset_cb(PWMDriver *pwmp); -static void ow_read_bit_cb(PWMDriver *pwmp, onewireDriver *owp); -static void pwm_read_bit_cb(PWMDriver *pwmp); -static void ow_write_bit_cb(PWMDriver *pwmp, onewireDriver *owp); -static void pwm_write_bit_cb(PWMDriver *pwmp); -#if ONEWIRE_USE_SEARCH_ROM -static void ow_search_rom_cb(PWMDriver *pwmp, onewireDriver *owp); -static void pwm_search_rom_cb(PWMDriver *pwmp); -#endif - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ -/** - * @brief 1-wire driver identifier. - */ -onewireDriver OWD1; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ -/** - * @brief Look up table for fast 1-wire CRC calculation - */ -static const uint8_t onewire_crc_table[256] = { - 0x0, 0x5e, 0xbc, 0xe2, 0x61, 0x3f, 0xdd, 0x83, - 0xc2, 0x9c, 0x7e, 0x20, 0xa3, 0xfd, 0x1f, 0x41, - 0x9d, 0xc3, 0x21, 0x7f, 0xfc, 0xa2, 0x40, 0x1e, - 0x5f, 0x1, 0xe3, 0xbd, 0x3e, 0x60, 0x82, 0xdc, - 0x23, 0x7d, 0x9f, 0xc1, 0x42, 0x1c, 0xfe, 0xa0, - 0xe1, 0xbf, 0x5d, 0x3, 0x80, 0xde, 0x3c, 0x62, - 0xbe, 0xe0, 0x2, 0x5c, 0xdf, 0x81, 0x63, 0x3d, - 0x7c, 0x22, 0xc0, 0x9e, 0x1d, 0x43, 0xa1, 0xff, - 0x46, 0x18, 0xfa, 0xa4, 0x27, 0x79, 0x9b, 0xc5, - 0x84, 0xda, 0x38, 0x66, 0xe5, 0xbb, 0x59, 0x7, - 0xdb, 0x85, 0x67, 0x39, 0xba, 0xe4, 0x6, 0x58, - 0x19, 0x47, 0xa5, 0xfb, 0x78, 0x26, 0xc4, 0x9a, - 0x65, 0x3b, 0xd9, 0x87, 0x4, 0x5a, 0xb8, 0xe6, - 0xa7, 0xf9, 0x1b, 0x45, 0xc6, 0x98, 0x7a, 0x24, - 0xf8, 0xa6, 0x44, 0x1a, 0x99, 0xc7, 0x25, 0x7b, - 0x3a, 0x64, 0x86, 0xd8, 0x5b, 0x5, 0xe7, 0xb9, - 0x8c, 0xd2, 0x30, 0x6e, 0xed, 0xb3, 0x51, 0xf, - 0x4e, 0x10, 0xf2, 0xac, 0x2f, 0x71, 0x93, 0xcd, - 0x11, 0x4f, 0xad, 0xf3, 0x70, 0x2e, 0xcc, 0x92, - 0xd3, 0x8d, 0x6f, 0x31, 0xb2, 0xec, 0xe, 0x50, - 0xaf, 0xf1, 0x13, 0x4d, 0xce, 0x90, 0x72, 0x2c, - 0x6d, 0x33, 0xd1, 0x8f, 0xc, 0x52, 0xb0, 0xee, - 0x32, 0x6c, 0x8e, 0xd0, 0x53, 0xd, 0xef, 0xb1, - 0xf0, 0xae, 0x4c, 0x12, 0x91, 0xcf, 0x2d, 0x73, - 0xca, 0x94, 0x76, 0x28, 0xab, 0xf5, 0x17, 0x49, - 0x8, 0x56, 0xb4, 0xea, 0x69, 0x37, 0xd5, 0x8b, - 0x57, 0x9, 0xeb, 0xb5, 0x36, 0x68, 0x8a, 0xd4, - 0x95, 0xcb, 0x29, 0x77, 0xf4, 0xaa, 0x48, 0x16, - 0xe9, 0xb7, 0x55, 0xb, 0x88, 0xd6, 0x34, 0x6a, - 0x2b, 0x75, 0x97, 0xc9, 0x4a, 0x14, 0xf6, 0xa8, - 0x74, 0x2a, 0xc8, 0x96, 0x15, 0x4b, 0xa9, 0xf7, - 0xb6, 0xe8, 0xa, 0x54, 0xd7, 0x89, 0x6b, 0x35 -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ -/** - * @brief Put bus in idle mode. - */ -static void ow_bus_idle(onewireDriver *owp) { -#if defined(STM32F1XX) - palSetPadMode(owp->config->port, owp->config->pad, - owp->config->pad_mode_idle); -#endif - pwmStop(owp->config->pwmd); -} - -/** - * @brief Put bus in active mode. - */ -static void ow_bus_active(onewireDriver *owp) { - pwmStart(owp->config->pwmd, owp->config->pwmcfg); -#if defined(STM32F1XX) - palSetPadMode(owp->config->port, owp->config->pad, - owp->config->pad_mode_active); -#endif -} - -/** - * @brief Function performing read of single bit. - * @note It must be callable from any context. - */ -static ioline_t ow_read_bit(onewireDriver *owp) { -#if ONEWIRE_SYNTH_SEARCH_TEST - (void)owp; - return _synth_ow_read_bit(); -#else - return palReadPad(owp->config->port, owp->config->pad); -#endif -} - -/** - * @brief PWM adapter - */ -static void pwm_reset_cb(PWMDriver *pwmp) { - ow_reset_cb(pwmp, &OWD1); -} - -/** - * @brief PWM adapter - */ -static void pwm_read_bit_cb(PWMDriver *pwmp) { - ow_read_bit_cb(pwmp, &OWD1); -} - -/** - * @brief PWM adapter - */ -static void pwm_write_bit_cb(PWMDriver *pwmp) { - ow_write_bit_cb(pwmp, &OWD1); -} - -#if ONEWIRE_USE_SEARCH_ROM -/** - * @brief PWM adapter - */ -static void pwm_search_rom_cb(PWMDriver *pwmp) { - ow_search_rom_cb(pwmp, &OWD1); -} -#endif /* ONEWIRE_USE_SEARCH_ROM */ - -/** - * @brief Write bit routine. - * @details Switch PWM channel to 'width' or 'narrow' pulse depending - * on value of bit need to be transmitted. - * - * @param[in] owp pointer to the @p onewireDriver object - * @param[in] bit value to be written - * - * @notapi - */ -static void ow_write_bit_I(onewireDriver *owp, ioline_t bit) { -#if ONEWIRE_SYNTH_SEARCH_TEST - _synth_ow_write_bit(owp, bit); -#else - osalSysLockFromISR(); - if (0 == bit) { - pwmEnableChannelI(owp->config->pwmd, owp->config->master_channel, - ONEWIRE_ZERO_WIDTH); - } - else { - pwmEnableChannelI(owp->config->pwmd, owp->config->master_channel, - ONEWIRE_ONE_WIDTH); - } - osalSysUnlockFromISR(); -#endif -} - -/** - * @brief 1-wire reset pulse callback. - * @note Must be called from PWM's ISR. - * - * @param[in] pwmp pointer to the @p PWMDriver object - * @param[in] owp pointer to the @p onewireDriver object - * - * @notapi - */ -static void ow_reset_cb(PWMDriver *pwmp, onewireDriver *owp) { - - owp->reg.slave_present = (PAL_LOW == ow_read_bit(owp)); - osalSysLockFromISR(); - pwmDisableChannelI(pwmp, owp->config->sample_channel); - osalThreadResumeI(&owp->thread, MSG_OK); - osalSysUnlockFromISR(); -} - -/** - * @brief 1-wire read bit callback. - * @note Must be called from PWM's ISR. - * - * @param[in] pwmp pointer to the @p PWMDriver object - * @param[in] owp pointer to the @p onewireDriver object - * - * @notapi - */ -static void ow_read_bit_cb(PWMDriver *pwmp, onewireDriver *owp) { - - if (true == owp->reg.final_timeslot) { - osalSysLockFromISR(); - pwmDisableChannelI(pwmp, owp->config->sample_channel); - osalThreadResumeI(&owp->thread, MSG_OK); - osalSysUnlockFromISR(); - return; - } - else { - *owp->buf |= ow_read_bit(owp) << owp->reg.bit; - owp->reg.bit++; - if (8 == owp->reg.bit) { - owp->reg.bit = 0; - owp->buf++; - owp->reg.bytes--; - if (0 == owp->reg.bytes) { - owp->reg.final_timeslot = true; - osalSysLockFromISR(); - /* Only master channel must be stopped here. - Sample channel will be stopped in next ISR call. - It is still needed to generate final interrupt. */ - pwmDisableChannelI(pwmp, owp->config->master_channel); - osalSysUnlockFromISR(); - } - } - } -} - -/** - * @brief 1-wire bit transmission callback. - * @note Must be called from PWM's ISR. - * - * @param[in] pwmp pointer to the @p PWMDriver object - * @param[in] owp pointer to the @p onewireDriver object - * - * @notapi - */ -static void ow_write_bit_cb(PWMDriver *pwmp, onewireDriver *owp) { - - if (8 == owp->reg.bit) { - owp->buf++; - owp->reg.bit = 0; - owp->reg.bytes--; - - if (0 == owp->reg.bytes) { - osalSysLockFromISR(); - pwmDisableChannelI(pwmp, owp->config->master_channel); - osalSysUnlockFromISR(); - /* used to prevent premature timer stop from userspace */ - owp->reg.final_timeslot = true; - return; - } - } - - /* wait until timer generate last pulse */ - if (true == owp->reg.final_timeslot) { - #if ONEWIRE_USE_STRONG_PULLUP - if (owp->reg.need_pullup) { - owp->reg.state = ONEWIRE_PULL_UP; - owp->config->pullup_assert(); - owp->reg.need_pullup = false; - } - #endif - - osalSysLockFromISR(); - osalThreadResumeI(&owp->thread, MSG_OK); - osalSysUnlockFromISR(); - return; - } - - ow_write_bit_I(owp, (*owp->buf >> owp->reg.bit) & 1); - owp->reg.bit++; -} - -#if ONEWIRE_USE_SEARCH_ROM -/** - * @brief Helper function for collision handler - * - * @param[in] sr pointer to the @p onewire_search_rom_t helper structure - * @param[in] bit discovered bit to be stored in helper structure - */ -static void store_bit(onewire_search_rom_t *sr, uint8_t bit) { - - size_t rb = sr->reg.rombit; - - sr->retbuf[rb / CHAR_BIT] |= bit << (rb % CHAR_BIT); - sr->reg.rombit++; -} - -/** - * @brief Helper function for collision handler - * @details Extract bit from previous search path. - * - * @param[in] path pointer to the array with previous path stored in - * 'search ROM' helper structure - * @param[in] bit number of bit [0..63] - */ -static uint8_t extract_path_bit(const uint8_t *path, size_t bit) { - - return (path[bit / CHAR_BIT] >> (bit % CHAR_BIT)) & 1; -} - -/** - * @brief Collision handler for 'search ROM' procedure. - * @details You can find algorithm details in APPNOTE 187 - * "1-Wire Search Algorithm" from Maxim - * - * @param[in,out] sr pointer to the @p onewire_search_rom_t helper structure - */ -static uint8_t collision_handler(onewire_search_rom_t *sr) { - - uint8_t bit; - - switch(sr->reg.search_iter) { - case ONEWIRE_SEARCH_ROM_NEXT: - if ((int)sr->reg.rombit < sr->last_zero_branch) { - bit = extract_path_bit(sr->prev_path, sr->reg.rombit); - if (0 == bit) { - sr->prev_zero_branch = sr->reg.rombit; - sr->reg.result = ONEWIRE_SEARCH_ROM_SUCCESS; - } - store_bit(sr, bit); - return bit; - } - else if ((int)sr->reg.rombit == sr->last_zero_branch) { - sr->last_zero_branch = sr->prev_zero_branch; - store_bit(sr, 1); - return 1; - } - else { - /* found next branch some levels deeper */ - sr->prev_zero_branch = sr->last_zero_branch; - sr->last_zero_branch = sr->reg.rombit; - store_bit(sr, 0); - sr->reg.result = ONEWIRE_SEARCH_ROM_SUCCESS; - return 0; - } - break; - - case ONEWIRE_SEARCH_ROM_FIRST: - /* always take 0-branch */ - sr->prev_zero_branch = sr->last_zero_branch; - sr->last_zero_branch = sr->reg.rombit; - store_bit(sr, 0); - sr->reg.result = ONEWIRE_SEARCH_ROM_SUCCESS; - return 0; - break; - - default: - osalSysHalt("Unhandled case"); - return 0; /* warning supressor */ - break; - } -} - -/** - * @brief 1-wire search ROM callback. - * @note Must be called from PWM's ISR. - * - * @param[in] pwmp pointer to the @p PWMDriver object - * @param[in] owp pointer to the @p onewireDriver object - * - * @notapi - */ -static void ow_search_rom_cb(PWMDriver *pwmp, onewireDriver *owp) { - - onewire_search_rom_t *sr = &owp->search_rom; - - if (0 == sr->reg.bit_step) { /* read direct bit */ - sr->reg.bit_buf |= ow_read_bit(owp); - sr->reg.bit_step++; - } - else if (1 == sr->reg.bit_step) { /* read complement bit */ - sr->reg.bit_buf |= ow_read_bit(owp) << 1; - sr->reg.bit_step++; - switch(sr->reg.bit_buf){ - case 0b11: - /* no one device on bus or any other fail happened */ - sr->reg.result = ONEWIRE_SEARCH_ROM_ERROR; - goto THE_END; - break; - case 0b01: - /* all slaves have 1 in this position */ - store_bit(sr, 1); - ow_write_bit_I(owp, 1); - break; - case 0b10: - /* all slaves have 0 in this position */ - store_bit(sr, 0); - ow_write_bit_I(owp, 0); - break; - case 0b00: - /* collision */ - sr->reg.single_device = false; - ow_write_bit_I(owp, collision_handler(sr)); - break; - } - } - else { /* start next step */ - #if !ONEWIRE_SYNTH_SEARCH_TEST - ow_write_bit_I(owp, 1); - #endif - sr->reg.bit_step = 0; - sr->reg.bit_buf = 0; - } - - /* one ROM successfully discovered */ - if (64 == sr->reg.rombit) { - sr->reg.devices_found++; - sr->reg.search_iter = ONEWIRE_SEARCH_ROM_NEXT; - if (true == sr->reg.single_device) - sr->reg.result = ONEWIRE_SEARCH_ROM_LAST; - goto THE_END; - } - return; /* next search bit iteration */ - -THE_END: -#if ONEWIRE_SYNTH_SEARCH_TEST - (void)pwmp; - return; -#else - osalSysLockFromISR(); - pwmDisableChannelI(pwmp, owp->config->master_channel); - pwmDisableChannelI(pwmp, owp->config->sample_channel); - osalThreadResumeI(&(owp)->thread, MSG_OK); - osalSysUnlockFromISR(); -#endif -} - -/** - * @brief Helper function. Initialize structures required by 'search ROM'. - * @details Early reset. Call it once before 'search ROM' routine. - * - * @param[in] sr pointer to the @p onewire_search_rom_t helper structure - */ -static void search_clean_start(onewire_search_rom_t *sr) { - - sr->reg.single_device = true; /* presume simplest way at beginning */ - sr->reg.result = ONEWIRE_SEARCH_ROM_LAST; - sr->reg.search_iter = ONEWIRE_SEARCH_ROM_FIRST; - sr->retbuf = NULL; - sr->reg.devices_found = 0; - memset(sr->prev_path, 0, 8); - - sr->reg.rombit = 0; - sr->reg.bit_step = 0; - sr->reg.bit_buf = 0; - sr->last_zero_branch = -1; - sr->prev_zero_branch = -1; -} - -/** - * @brief Helper function. Prepare structures required by 'search ROM'. - * - * @param[in] sr pointer to the @p onewire_search_rom_t helper structure - */ -static void search_clean_iteration(onewire_search_rom_t *sr) { - - sr->reg.rombit = 0; - sr->reg.bit_step = 0; - sr->reg.bit_buf = 0; - sr->reg.result = ONEWIRE_SEARCH_ROM_LAST; -} -#endif /* ONEWIRE_USE_SEARCH_ROM */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Calculates 1-wire CRC. - * - * @param[in] buf pointer to the data buffer - * @param[in] len lenght of data buffer - * - * @init - */ -uint8_t onewireCRC(const uint8_t *buf, size_t len) { - uint8_t ret = 0; - size_t i; - - for (i=0; iconfig = NULL; - owp->reg.slave_present = false; - owp->reg.state = ONEWIRE_STOP; - owp->thread = NULL; - - owp->reg.bytes = 0; - owp->reg.bit = 0; - owp->reg.final_timeslot = false; - owp->buf = NULL; - -#if ONEWIRE_USE_STRONG_PULLUP - owp->reg.need_pullup = false; -#endif -} - -/** - * @brief Configures and activates the 1-wire driver. - * - * @param[in] owp pointer to the @p onewireDriver object - * @param[in] config pointer to the @p onewireConfig object - * - * @api - */ -void onewireStart(onewireDriver *owp, const onewireConfig *config) { - - osalDbgCheck((NULL != owp) && (NULL != config)); - osalDbgAssert(PWM_STOP == config->pwmd->state, - "PWM will be started by onewire driver internally"); - osalDbgAssert(ONEWIRE_STOP == owp->reg.state, "Invalid state"); -#if ONEWIRE_USE_STRONG_PULLUP - osalDbgCheck((NULL != config->pullup_assert) && - (NULL != config->pullup_release)); -#endif - - owp->config = config; - owp->config->pwmcfg->frequency = ONEWIRE_PWM_FREQUENCY; - owp->config->pwmcfg->period = ONEWIRE_RESET_TOTAL_WIDTH; - -#if !defined(STM32F1XX) - palSetPadMode(owp->config->port, owp->config->pad, - owp->config->pad_mode_active); -#endif - ow_bus_idle(owp); - owp->reg.state = ONEWIRE_READY; -} - -/** - * @brief Deactivates the UART peripheral. - * - * @param[in] owp pointer to the @p onewireDriver object - * - * @api - */ -void onewireStop(onewireDriver *owp) { - osalDbgCheck(NULL != owp); -#if ONEWIRE_USE_STRONG_PULLUP - owp->config->pullup_release(); -#endif - ow_bus_idle(owp); - pwmStop(owp->config->pwmd); - owp->config = NULL; - owp->reg.state = ONEWIRE_STOP; -} - -/** - * @brief Generate reset pulse on bus. - * - * @param[in] owp pointer to the @p onewireDriver object - * - * @return Bool flag denoting device presence. - * @retval true There is at least one device on bus. - */ -bool onewireReset(onewireDriver *owp) { - PWMDriver *pwmd; - PWMConfig *pwmcfg; - size_t mch, sch; - - osalDbgCheck(NULL != owp); - osalDbgAssert(owp->reg.state == ONEWIRE_READY, "Invalid state"); - - /* short circuit on bus or any other device transmit data */ - if (PAL_LOW == ow_read_bit(owp)) - return false; - - pwmd = owp->config->pwmd; - pwmcfg = owp->config->pwmcfg; - mch = owp->config->master_channel; - sch = owp->config->sample_channel; - - - pwmcfg->period = ONEWIRE_RESET_LOW_WIDTH + ONEWIRE_RESET_SAMPLE_WIDTH; - pwmcfg->callback = NULL; - pwmcfg->channels[mch].callback = NULL; - pwmcfg->channels[mch].mode = owp->config->pwmmode; - pwmcfg->channels[sch].callback = pwm_reset_cb; - pwmcfg->channels[sch].mode = PWM_OUTPUT_DISABLED; - - ow_bus_active(owp); - - osalSysLock(); - pwmEnableChannelI(pwmd, mch, ONEWIRE_RESET_LOW_WIDTH); - pwmEnableChannelI(pwmd, sch, ONEWIRE_RESET_SAMPLE_WIDTH); - pwmEnableChannelNotificationI(pwmd, sch); - osalThreadSuspendS(&owp->thread); - osalSysUnlock(); - - ow_bus_idle(owp); - - /* wait until slave release bus to discriminate short circuit condition */ - osalThreadSleepMicroseconds(500); - return (PAL_HIGH == ow_read_bit(owp)) && (true == owp->reg.slave_present); -} - -/** - * @brief Read some bytes from slave device. - * - * @param[in] owp pointer to the @p onewireDriver object - * @param[out] rxbuf pointer to the buffer for read data - * @param[in] rxbytes amount of data to be received - */ -void onewireRead(onewireDriver *owp, uint8_t *rxbuf, size_t rxbytes) { - PWMDriver *pwmd; - PWMConfig *pwmcfg; - size_t mch, sch; - - osalDbgCheck((NULL != owp) && (NULL != rxbuf)); - osalDbgCheck((rxbytes > 0) && (rxbytes <= ONEWIRE_MAX_TRANSACTION_LEN)); - osalDbgAssert(owp->reg.state == ONEWIRE_READY, "Invalid state"); - - /* Buffer zeroing. This is important because of driver collects - bits using |= operation.*/ - memset(rxbuf, 0, rxbytes); - - pwmd = owp->config->pwmd; - pwmcfg = owp->config->pwmcfg; - mch = owp->config->master_channel; - sch = owp->config->sample_channel; - - owp->reg.bit = 0; - owp->reg.final_timeslot = false; - owp->buf = rxbuf; - owp->reg.bytes = rxbytes; - - pwmcfg->period = ONEWIRE_ZERO_WIDTH + ONEWIRE_RECOVERY_WIDTH; - pwmcfg->callback = NULL; - pwmcfg->channels[mch].callback = NULL; - pwmcfg->channels[mch].mode = owp->config->pwmmode; - pwmcfg->channels[sch].callback = pwm_read_bit_cb; - pwmcfg->channels[sch].mode = PWM_OUTPUT_DISABLED; - - ow_bus_active(owp); - osalSysLock(); - pwmEnableChannelI(pwmd, mch, ONEWIRE_ONE_WIDTH); - pwmEnableChannelI(pwmd, sch, ONEWIRE_SAMPLE_WIDTH); - pwmEnableChannelNotificationI(pwmd, sch); - osalThreadSuspendS(&owp->thread); - osalSysUnlock(); - - ow_bus_idle(owp); -} - -/** - * @brief Write some bytes to slave device. - * - * @param[in] owp pointer to the @p onewireDriver object - * @param[in] txbuf pointer to the buffer with data to be written - * @param[in] txbytes amount of data to be written - * @param[in] pullup_time how long strong pull up must be activated. Set - * it to 0 if not needed. - */ -void onewireWrite(onewireDriver *owp, uint8_t *txbuf, - size_t txbytes, systime_t pullup_time) { - PWMDriver *pwmd; - PWMConfig *pwmcfg; - size_t mch, sch; - - osalDbgCheck((NULL != owp) && (NULL != txbuf)); - osalDbgCheck((txbytes > 0) && (txbytes <= ONEWIRE_MAX_TRANSACTION_LEN)); - osalDbgAssert(owp->reg.state == ONEWIRE_READY, "Invalid state"); -#if !ONEWIRE_USE_STRONG_PULLUP - osalDbgAssert(0 == pullup_time, - "Non zero time is valid only when strong pull enabled"); -#endif - - pwmd = owp->config->pwmd; - pwmcfg = owp->config->pwmcfg; - mch = owp->config->master_channel; - sch = owp->config->sample_channel; - - owp->buf = txbuf; - owp->reg.bit = 0; - owp->reg.final_timeslot = false; - owp->reg.bytes = txbytes; - - pwmcfg->period = ONEWIRE_ZERO_WIDTH + ONEWIRE_RECOVERY_WIDTH; - pwmcfg->callback = pwm_write_bit_cb; - pwmcfg->channels[mch].callback = NULL; - pwmcfg->channels[mch].mode = owp->config->pwmmode; - pwmcfg->channels[sch].callback = NULL; - pwmcfg->channels[sch].mode = PWM_OUTPUT_DISABLED; - -#if ONEWIRE_USE_STRONG_PULLUP - if (pullup_time > 0) { - owp->reg.state = ONEWIRE_PULL_UP; - owp->reg.need_pullup = true; - } -#endif - - ow_bus_active(owp); - osalSysLock(); - pwmEnablePeriodicNotificationI(pwmd); - osalThreadSuspendS(&owp->thread); - osalSysUnlock(); - - pwmDisablePeriodicNotification(pwmd); - ow_bus_idle(owp); - -#if ONEWIRE_USE_STRONG_PULLUP - if (pullup_time > 0) { - osalThreadSleep(pullup_time); - owp->config->pullup_release(); - owp->reg.state = ONEWIRE_READY; - } -#endif -} - -#if ONEWIRE_USE_SEARCH_ROM -/** - * @brief Performs tree search on bus. - * @note This function does internal 1-wire reset calls every search - * iteration. - * - * @param[in] owp pointer to a @p OWDriver object - * @param[out] result pointer to buffer for discovered ROMs - * @param[in] max_rom_cnt buffer size in ROMs count for overflow prevention - * - * @return Count of discovered ROMs. May be more than max_rom_cnt. - * @retval 0 no ROMs found or communication error occurred. - */ -size_t onewireSearchRom(onewireDriver *owp, uint8_t *result, - size_t max_rom_cnt) { - PWMDriver *pwmd; - PWMConfig *pwmcfg; - uint8_t cmd; - size_t mch, sch; - - osalDbgCheck(NULL != owp); - osalDbgAssert(ONEWIRE_READY == owp->reg.state, "Invalid state"); - osalDbgCheck((max_rom_cnt <= 256) && (max_rom_cnt > 0)); - - pwmd = owp->config->pwmd; - pwmcfg = owp->config->pwmcfg; - cmd = ONEWIRE_CMD_SEARCH_ROM; - mch = owp->config->master_channel; - sch = owp->config->sample_channel; - - search_clean_start(&owp->search_rom); - - do { - /* every search must be started from reset pulse */ - if (false == onewireReset(owp)) - return 0; - - /* initialize buffer to store result */ - if (owp->search_rom.reg.devices_found >= max_rom_cnt) - owp->search_rom.retbuf = result + 8*(max_rom_cnt-1); - else - owp->search_rom.retbuf = result + 8*owp->search_rom.reg.devices_found; - memset(owp->search_rom.retbuf, 0, 8); - - /* clean iteration state */ - search_clean_iteration(&owp->search_rom); - - /**/ - onewireWrite(&OWD1, &cmd, 1, 0); - - /* Reconfiguration always needed because of previous call onewireWrite.*/ - pwmcfg->period = ONEWIRE_ZERO_WIDTH + ONEWIRE_RECOVERY_WIDTH; - pwmcfg->callback = NULL; - pwmcfg->channels[mch].callback = NULL; - pwmcfg->channels[mch].mode = owp->config->pwmmode; - pwmcfg->channels[sch].callback = pwm_search_rom_cb; - pwmcfg->channels[sch].mode = PWM_OUTPUT_DISABLED; - - ow_bus_active(owp); - osalSysLock(); - pwmEnableChannelI(pwmd, mch, ONEWIRE_ONE_WIDTH); - pwmEnableChannelI(pwmd, sch, ONEWIRE_SAMPLE_WIDTH); - pwmEnableChannelNotificationI(pwmd, sch); - osalThreadSuspendS(&owp->thread); - osalSysUnlock(); - - ow_bus_idle(owp); - - if (ONEWIRE_SEARCH_ROM_ERROR != owp->search_rom.reg.result) { - /* check CRC and return 0 (0 == error) if mismatch */ - if (owp->search_rom.retbuf[7] != onewireCRC(owp->search_rom.retbuf, 7)) - return 0; - /* store cached result for usage in next iteration */ - memcpy(owp->search_rom.prev_path, owp->search_rom.retbuf, 8); - } - } - while (ONEWIRE_SEARCH_ROM_SUCCESS == owp->search_rom.reg.result); - - /**/ - if (ONEWIRE_SEARCH_ROM_ERROR == owp->search_rom.reg.result) - return 0; - else - return owp->search_rom.reg.devices_found; -} -#endif /* ONEWIRE_USE_SEARCH_ROM */ - -/* - * Include test code (if enabled). - */ -#if ONEWIRE_SYNTH_SEARCH_TEST -#include "synth_searchrom.c" -#endif - -#endif /* HAL_USE_ONEWIRE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/hal/src/hal_qei.c b/firmware/ChibiOS_16/community/os/hal/src/hal_qei.c deleted file mode 100644 index 73cfbc03c8..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/src/hal_qei.c +++ /dev/null @@ -1,375 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Martino Migliavacca - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_qei.c - * @brief QEI Driver code. - * - * @addtogroup QEI - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_QEI == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Helper for correclty handling overflow/underflow - * - * @details Underflow/overflow will be handled according to mode: - * QEI_OVERFLOW_WRAP: counter value will wrap around. - * QEI_OVERFLOW_DISCARD: counter will not change - * QEI_OVERFLOW_MINMAX: counter will be updated upto min or max. - * - * @note This function is for use by low level driver. - * - * @param[in,out] count counter value - * @param[in,out] delta adjustment value - * @param[in] min minimum allowed value for counter - * @param[in] max maximum allowed value for counter - * @param[in] mode how to handle overflow - * - * @return true if counter underflow/overflow occured or - * was due to occur - * - */ -static inline -bool qei_adjust_count(qeicnt_t *count, qeidelta_t *delta, - qeicnt_t min, qeicnt_t max, qeioverflow_t mode) { - /* For information on signed integer overflow see: - * https://www.securecoding.cert.org/confluence/x/RgE - */ - - /* Get values */ - const qeicnt_t _count = *count; - const qeidelta_t _delta = *delta; - - /* Overflow operation - */ - if ((_delta > 0) && (_count > (max - _delta))) { - switch(mode) { - case QEI_OVERFLOW_WRAP: - *delta = 0; - *count = (min + (_count - (max - _delta))) - 1; - break; -#if QEI_USE_OVERFLOW_DISCARD == TRUE - case QEI_OVERFLOW_DISCARD: - *delta = _delta; - *count = _count; - break; -#endif -#if QEI_USE_OVERFLOW_MINMAX == TRUE - case QEI_OVERFLOW_MINMAX: - *delta = _count - (max - _delta); - *count = max; - break; -#endif - } - return true; - - /* Underflow operation - */ - } else if ((_delta < 0) && (_count < (min - _delta))) { - switch(mode) { - case QEI_OVERFLOW_WRAP: - *delta = 0; - *count = (max + (_count - (min - _delta))) + 1; - break; -#if QEI_USE_OVERFLOW_DISCARD == TRUE - case QEI_OVERFLOW_DISCARD: - *delta = _delta; - *count = _count; - break; -#endif -#if QEI_USE_OVERFLOW_MINMAX == TRUE - case QEI_OVERFLOW_MINMAX: - *delta = _count - (min - _delta); - *count = min; - break; -#endif - } - return true; - - /* Normal operation - */ - } else { - *delta = 0; - *count = _count + _delta; - return false; - } -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief QEI Driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void qeiInit(void) { - - qei_lld_init(); -} - -/** - * @brief Initializes the standard part of a @p QEIDriver structure. - * - * @param[out] qeip pointer to the @p QEIDriver object - * - * @init - */ -void qeiObjectInit(QEIDriver *qeip) { - - qeip->state = QEI_STOP; - qeip->last = 0; - qeip->config = NULL; -} - -/** - * @brief Configures and activates the QEI peripheral. - * - * @param[in] qeip pointer to the @p QEIDriver object - * @param[in] config pointer to the @p QEIConfig object - * - * @api - */ -void qeiStart(QEIDriver *qeip, const QEIConfig *config) { - - osalDbgCheck((qeip != NULL) && (config != NULL)); - - osalSysLock(); - osalDbgAssert((qeip->state == QEI_STOP) || (qeip->state == QEI_READY), - "invalid state"); - qeip->config = config; - qei_lld_start(qeip); - qeip->state = QEI_READY; - osalSysUnlock(); -} - -/** - * @brief Deactivates the QEI peripheral. - * - * @param[in] qeip pointer to the @p QEIDriver object - * - * @api - */ -void qeiStop(QEIDriver *qeip) { - - osalDbgCheck(qeip != NULL); - - osalSysLock(); - osalDbgAssert((qeip->state == QEI_STOP) || (qeip->state == QEI_READY), - "invalid state"); - qei_lld_stop(qeip); - qeip->state = QEI_STOP; - osalSysUnlock(); -} - -/** - * @brief Enables the quadrature encoder interface. - * - * @param[in] qeip pointer to the @p QEIDriver object - * - * @api - */ -void qeiEnable(QEIDriver *qeip) { - - osalDbgCheck(qeip != NULL); - - osalSysLock(); - osalDbgAssert(qeip->state == QEI_READY, "invalid state"); - qei_lld_enable(qeip); - qeip->state = QEI_ACTIVE; - osalSysUnlock(); -} - -/** - * @brief Disables the quadrature encoder interface. - * - * @param[in] qeip pointer to the @p QEIDriver object - * - * @api - */ -void qeiDisable(QEIDriver *qeip) { - - osalDbgCheck(qeip != NULL); - - osalSysLock(); - osalDbgAssert((qeip->state == QEI_READY) || (qeip->state == QEI_ACTIVE), - "invalid state"); - qei_lld_disable(qeip); - qeip->state = QEI_READY; - osalSysUnlock(); -} - -/** - * @brief Returns the counter value. - * - * @param[in] qeip pointer to the @p QEIDriver object - * @return The current counter value. - * - * @api - */ -qeicnt_t qeiGetCount(QEIDriver *qeip) { - qeicnt_t cnt; - - osalSysLock(); - cnt = qeiGetCountI(qeip); - osalSysUnlock(); - - return cnt; -} - -/** - * @brief Set counter value. - * - * @param[in] qeip pointer to the @p QEIDriver object. - * @param[in] value the new counter value. - * - * @api - */ -void qeiSetCount(QEIDriver *qeip, qeicnt_t value) { - osalDbgCheck(qeip != NULL); - osalDbgAssert((qeip->state == QEI_READY) || (qeip->state == QEI_ACTIVE), - "invalid state"); - - osalSysLock(); - qei_lld_set_count(qeip, value); - osalSysUnlock(); -} - -/** - * @brief Adjust the counter by delta. - * - * @param[in] qeip pointer to the @p QEIDriver object. - * @param[in] delta the adjustement value. - * @return the remaining delta (can occur during overflow). - * - * @api - */ -qeidelta_t qeiAdjust(QEIDriver *qeip, qeidelta_t delta) { - osalDbgCheck(qeip != NULL); - osalDbgAssert((qeip->state == QEI_ACTIVE), "invalid state"); - - osalSysLock(); - delta = qeiAdjustI(qeip, delta); - osalSysUnlock(); - - return delta; -} - -/** - * @brief Adjust the counter by delta. - * - * @param[in] qeip pointer to the @p QEIDriver object. - * @param[in] delta the adjustement value. - * @return the remaining delta (can occur during overflow). - * - * @api - */ -qeidelta_t qeiAdjustI(QEIDriver *qeip, qeidelta_t delta) { - /* Get boundaries */ - qeicnt_t min = QEI_COUNT_MIN; - qeicnt_t max = QEI_COUNT_MAX; - if (qeip->config->min != qeip->config->max) { - min = qeip->config->min; - max = qeip->config->max; - } - - /* Get counter */ - qeicnt_t count = qei_lld_get_count(qeip); - - /* Adjust counter value */ - bool overflowed = qei_adjust_count(&count, &delta, - min, max, qeip->config->overflow); - - /* Notify for value change */ - qei_lld_set_count(qeip, count); - - /* Notify for overflow (passing the remaining delta) */ - if (overflowed && qeip->config->overflow_cb) - qeip->config->overflow_cb(qeip, delta); - - /* Remaining delta */ - return delta; -} - - -/** - * @brief Returns the counter delta from last reading. - * - * @param[in] qeip pointer to the @p QEIDriver object - * @return The delta from last read. - * - * @api - */ -qeidelta_t qeiUpdate(QEIDriver *qeip) { - qeidelta_t diff; - - osalSysLock(); - diff = qeiUpdateI(qeip); - osalSysUnlock(); - - return diff; -} - -/** - * @brief Returns the counter delta from last reading. - * - * @param[in] qeip pointer to the @p QEIDriver object - * @return The delta from last read. - * - * @iclass - */ -qeidelta_t qeiUpdateI(QEIDriver *qeip) { - qeicnt_t cnt; - qeidelta_t delta; - - osalDbgCheckClassI(); - osalDbgCheck(qeip != NULL); - osalDbgAssert((qeip->state == QEI_READY) || (qeip->state == QEI_ACTIVE), - "invalid state"); - - cnt = qei_lld_get_count(qeip); - delta = (qeicnt_t)(cnt - qeip->last); - qeip->last = cnt; - - return delta; -} - -#endif /* HAL_USE_QEI == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/hal/src/hal_rng.c b/firmware/ChibiOS_16/community/os/hal/src/hal_rng.c deleted file mode 100644 index 5ff6d2dd99..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/src/hal_rng.c +++ /dev/null @@ -1,182 +0,0 @@ -/* - RNG for ChibiOS - Copyright (C) 2016 Stephane D'Alu - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * Hardware Abstraction Layer for RNG Unit - */ -#include "hal.h" - -#if (HAL_USE_RNG == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief RNG Driver initialization. - * - * @init - */ -void rngInit(void) { - rng_lld_init(); -} - -/** - * @brief Initializes the standard part of a @p RNGDriver structure. - * - * @param[out] rngp Pointer to the @p RNGDriver object - * - * @init - */ -void rngObjectInit(RNGDriver *rngp) { - rngp->state = RNG_STOP; - rngp->config = NULL; -#if RNG_USE_MUTUAL_EXCLUSION == TRUE - osalMutexObjectInit(&rngp->mutex); -#endif -#if defined(RNG_DRIVER_EXT_INIT_HOOK) - RNG_DRIVER_EXT_INIT_HOOK(rngp); -#endif -} - -/** - * @brief Configures and activates the RNG peripheral. - * - * @param[in] rngp Pointer to the @p RNGDriver object - * @param[in] config Pointer to the @p RNGConfig object - * @p NULL if the low level driver implementation - * supports a default configuration - * - * @api - */ -void rngStart(RNGDriver *rngp, const RNGConfig *config) { - osalDbgCheck(rngp != NULL); - - osalSysLock(); - osalDbgAssert((rngp->state == RNG_STOP) || (rngp->state == RNG_READY), - "invalid state"); - rngp->config = config; - rng_lld_start(rngp); - rngp->state = RNG_READY; - osalSysUnlock(); -} - -/** - * @brief Deactivates the RNG peripheral. - * - * @param[in] rngp Pointer to the @p RNGDriver object - * - * @api - */ -void rngStop(RNGDriver *rngp) { - osalDbgCheck(rngp != NULL); - - osalSysLock(); - osalDbgAssert((rngp->state == RNG_STOP) || (rngp->state == RNG_READY), - "invalid state"); - rng_lld_stop(rngp); - rngp->state = RNG_STOP; - osalSysUnlock(); -} - -/** - * @brief Write random bytes - * @details Write the request number of bytes.. - * - * @param[in] rngp pointer to the @p RNGDriver object - * @param[in] buf the pointer to the buffer - * @param[in] n number of bytes to send - * @param[in] timeout timeout value - * - * @api - */ -msg_t rngWrite(RNGDriver *rngp, uint8_t *buf, size_t n, systime_t timeout) { - msg_t msg; - osalSysLock(); - msg = rngWriteI(rngp, buf, n, timeout); - osalSysUnlock(); - return msg; -} - -/** - * @brief Write random bytes - * @details Write the request number of bytes.. - * - * @param[in] rngp pointer to the @p RNGDriver object - * @param[in] buf the pointer to the buffer - * @param[in] n number of bytes to send - * @param[in] timeout timeout value - * - * @iclass - */ -msg_t rngWriteI(RNGDriver *rngp, uint8_t *buf, size_t n, systime_t timeout) { - osalDbgCheck((rngp != NULL) && (n > 0U) && (buf != NULL)); - osalDbgAssert(rngp->state == RNG_READY, "not ready"); - return rng_lld_write(rngp, buf, n, timeout); -} - - -#if (RNG_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__) -/** - * @brief Gains exclusive access to the RNG unit. - * @details This function tries to gain ownership to the RNG, if the RNG is - * already being used then the invoking thread is queued. - * @pre In order to use this function the option @p RNG_USE_MUTUAL_EXCLUSION - * must be enabled. - * - * @param[in] rngp pointer to the @p RNGDriver object - * - * @api - */ -void rngAcquireUnit(RNGDriver *rngp) { - osalDbgCheck(rngp != NULL); - - osalMutexLock(&rngp->mutex); -} - -/** - * @brief Releases exclusive access to the RNG unit. - * @pre In order to use this function the option @p RNG_USE_MUTUAL_EXCLUSION - * must be enabled. - * - * @param[in] rngp pointer to the @p RNGDriver object - * - * @api - */ -void rngReleaseUnit(RNGDriver *rngp) { - osalDbgCheck(rngp != NULL); - - osalMutexUnlock(&rngp->mutex); -} -#endif /* RNG_USE_MUTUAL_EXCLUSION == TRUE */ - -#endif /* HAL_USE_RNG */ diff --git a/firmware/ChibiOS_16/community/os/hal/src/hal_timcap.c b/firmware/ChibiOS_16/community/os/hal/src/hal_timcap.c deleted file mode 100644 index 309c14791f..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/src/hal_timcap.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file hal_timcap.c - * @brief TIMCAP Driver code. - * - * @addtogroup TIMCAP - * @{ - */ - -#include "hal_timcap.h" - -#if HAL_USE_TIMCAP || defined(__DOXYGEN__) - - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief TIMCAP Driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void timcapInit(void) { - - timcap_lld_init(); -} - -/** - * @brief Initializes the standard part of a @p TIMCAPDriver structure. - * - * @param[out] timcapp pointer to the @p TIMCAPDriver object - * - * @init - */ -void timcapObjectInit(TIMCAPDriver *timcapp) { - - timcapp->state = TIMCAP_STOP; - timcapp->config = NULL; -} - -/** - * @brief Configures and activates the TIMCAP peripheral. - * - * @param[in] timcapp pointer to the @p TIMCAPDriver object - * @param[in] config pointer to the @p TIMCAPConfig object - * - * @api - */ -void timcapStart(TIMCAPDriver *timcapp, const TIMCAPConfig *config) { - - osalDbgCheck((timcapp != NULL) && (config != NULL)); - - osalSysLock(); - osalDbgAssert((timcapp->state == TIMCAP_STOP) || (timcapp->state == TIMCAP_READY), - "invalid state"); - timcapp->config = config; - timcap_lld_start(timcapp); - timcapp->state = TIMCAP_READY; - osalSysUnlock(); -} - -/** - * @brief Deactivates the TIMCAP peripheral. - * - * @param[in] timcapp pointer to the @p TIMCAPDriver object - * - * @api - */ -void timcapStop(TIMCAPDriver *timcapp) { - - osalDbgCheck(timcapp != NULL); - - osalSysLock(); - osalDbgAssert((timcapp->state == TIMCAP_STOP) || (timcapp->state == TIMCAP_READY), - "invalid state"); - timcap_lld_stop(timcapp); - timcapp->state = TIMCAP_STOP; - osalSysUnlock(); -} - -/** - * @brief Enables the input capture. - * - * @param[in] timcapp pointer to the @p TIMCAPDriver object - * - * @api - */ -void timcapEnable(TIMCAPDriver *timcapp) { - - osalDbgCheck(timcapp != NULL); - - osalSysLock(); - osalDbgAssert(timcapp->state == TIMCAP_READY, "invalid state"); - timcap_lld_enable(timcapp); - timcapp->state = TIMCAP_WAITING; - osalSysUnlock(); -} - -/** - * @brief Disables the input capture. - * - * @param[in] timcapp pointer to the @p TIMCAPDriver object - * - * @api - */ -void timcapDisable(TIMCAPDriver *timcapp) { - - osalDbgCheck(timcapp != NULL); - - osalSysLock(); - osalDbgAssert((timcapp->state == TIMCAP_READY) || (timcapp->state == TIMCAP_WAITING) || - (timcapp->state == TIMCAP_ACTIVE) || (timcapp->state == TIMCAP_IDLE), - "invalid state"); - timcap_lld_disable(timcapp); - timcapp->state = TIMCAP_READY; - osalSysUnlock(); -} - -#endif /* HAL_USE_TIMCAP */ - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/hal/src/hal_usb_hid.c b/firmware/ChibiOS_16/community/os/hal/src/hal_usb_hid.c deleted file mode 100644 index fa02f5628e..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/src/hal_usb_hid.c +++ /dev/null @@ -1,581 +0,0 @@ -/* - ChibiOS - Copyright (C) 2016 Jonathan Struebel - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_usb_hid.c - * @brief USB HID Driver code. - * - * @addtogroup USB_HID - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_USB_HID == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static uint16_t get_hword(uint8_t *p) { - uint16_t hw; - - hw = (uint16_t)*p++; - hw |= (uint16_t)*p << 8U; - return hw; -} - -/* - * Interface implementation. - */ - -static size_t write(void *ip, const uint8_t *bp, size_t n) { - - if (usbGetDriverStateI(((USBHIDDriver *)ip)->config->usbp) != USB_ACTIVE) { - return 0; - } - - return obqWriteTimeout(&((USBHIDDriver *)ip)->obqueue, bp, - n, TIME_INFINITE); -} - -static size_t read(void *ip, uint8_t *bp, size_t n) { - - if (usbGetDriverStateI(((USBHIDDriver *)ip)->config->usbp) != USB_ACTIVE) { - return 0; - } - - return ibqReadTimeout(&((USBHIDDriver *)ip)->ibqueue, bp, - n, TIME_INFINITE); -} - -static msg_t put(void *ip, uint8_t b) { - - if (usbGetDriverStateI(((USBHIDDriver *)ip)->config->usbp) != USB_ACTIVE) { - return MSG_RESET; - } - - return obqPutTimeout(&((USBHIDDriver *)ip)->obqueue, b, TIME_INFINITE); -} - -static msg_t get(void *ip) { - - if (usbGetDriverStateI(((USBHIDDriver *)ip)->config->usbp) != USB_ACTIVE) { - return MSG_RESET; - } - - return ibqGetTimeout(&((USBHIDDriver *)ip)->ibqueue, TIME_INFINITE); -} - -static msg_t putt(void *ip, uint8_t b, systime_t timeout) { - - if (usbGetDriverStateI(((USBHIDDriver *)ip)->config->usbp) != USB_ACTIVE) { - return MSG_RESET; - } - - return obqPutTimeout(&((USBHIDDriver *)ip)->obqueue, b, timeout); -} - -static msg_t gett(void *ip, systime_t timeout) { - - if (usbGetDriverStateI(((USBHIDDriver *)ip)->config->usbp) != USB_ACTIVE) { - return MSG_RESET; - } - - return ibqGetTimeout(&((USBHIDDriver *)ip)->ibqueue, timeout); -} - -static size_t writet(void *ip, const uint8_t *bp, size_t n, systime_t timeout) { - - if (usbGetDriverStateI(((USBHIDDriver *)ip)->config->usbp) != USB_ACTIVE) { - return 0; - } - - return obqWriteTimeout(&((USBHIDDriver *)ip)->obqueue, bp, n, timeout); -} - -static size_t readt(void *ip, uint8_t *bp, size_t n, systime_t timeout) { - - if (usbGetDriverStateI(((USBHIDDriver *)ip)->config->usbp) != USB_ACTIVE) { - return 0; - } - - return ibqReadTimeout(&((USBHIDDriver *)ip)->ibqueue, bp, n, timeout); -} - -static void flush(void *ip) { - - obqFlush(&((USBHIDDriver *)ip)->obqueue); -} - -static const struct USBHIDDriverVMT vmt = { - write, read, put, get, - putt, gett, writet, readt, - flush -}; - -/** - * @brief Notification of empty buffer released into the input buffers queue. - * - * @param[in] bqp the buffers queue pointer. - */ -static void ibnotify(io_buffers_queue_t *bqp) { - USBHIDDriver *uhdp = bqGetLinkX(bqp); - - /* If the USB driver is not in the appropriate state then transactions - must not be started.*/ - if ((usbGetDriverStateI(uhdp->config->usbp) != USB_ACTIVE) || - (uhdp->state != HID_READY)) { - return; - } - - /* Checking if there is already a transaction ongoing on the endpoint.*/ - if (!usbGetReceiveStatusI(uhdp->config->usbp, uhdp->config->int_out)) { - /* Trying to get a free buffer.*/ - uint8_t *buf = ibqGetEmptyBufferI(&uhdp->ibqueue); - if (buf != NULL) { - /* Buffer found, starting a new transaction.*/ - usbStartReceiveI(uhdp->config->usbp, uhdp->config->int_out, - buf, SERIAL_USB_BUFFERS_SIZE); - } - } -} - -/** - * @brief Notification of filled buffer inserted into the output buffers queue. - * - * @param[in] bqp the buffers queue pointer. - */ -static void obnotify(io_buffers_queue_t *bqp) { - size_t n; - USBHIDDriver *uhdp = bqGetLinkX(bqp); - - /* If the USB driver is not in the appropriate state then transactions - must not be started.*/ - if ((usbGetDriverStateI(uhdp->config->usbp) != USB_ACTIVE) || - (uhdp->state != HID_READY)) { - return; - } - - /* Checking if there is already a transaction ongoing on the endpoint.*/ - if (!usbGetTransmitStatusI(uhdp->config->usbp, uhdp->config->int_in)) { - /* Trying to get a full buffer.*/ - uint8_t *buf = obqGetFullBufferI(&uhdp->obqueue, &n); - if (buf != NULL) { - /* Buffer found, starting a new transaction.*/ - usbStartTransmitI(uhdp->config->usbp, uhdp->config->int_in, buf, n); - } - } -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief USB HID Driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void hidInit(void) { -} - -/** - * @brief Initializes a generic full duplex USB HID driver object. - * @details The HW dependent part of the initialization has to be performed - * outside, usually in the hardware initialization code. - * - * @param[out] uhdp pointer to a @p USBHIDDriver structure - * - * @init - */ -void hidObjectInit(USBHIDDriver *uhdp) { - - uhdp->vmt = &vmt; - osalEventObjectInit(&uhdp->event); - uhdp->state = HID_STOP; - ibqObjectInit(&uhdp->ibqueue, true, uhdp->ib, - USB_HID_BUFFERS_SIZE, USB_HID_BUFFERS_NUMBER, - ibnotify, uhdp); - obqObjectInit(&uhdp->obqueue, true, uhdp->ob, - USB_HID_BUFFERS_SIZE, USB_HID_BUFFERS_NUMBER, - obnotify, uhdp); -} - -/** - * @brief Configures and starts the driver. - * - * @param[in] uhdp pointer to a @p USBHIDDriver object - * @param[in] config the USB HID driver configuration - * - * @api - */ -void hidStart(USBHIDDriver *uhdp, const USBHIDConfig *config) { - USBDriver *usbp = config->usbp; - - osalDbgCheck(uhdp != NULL); - - osalSysLock(); - osalDbgAssert((uhdp->state == HID_STOP) || (uhdp->state == HID_READY), - "invalid state"); - usbp->in_params[config->int_in - 1U] = uhdp; - usbp->out_params[config->int_out - 1U] = uhdp; - uhdp->config = config; - uhdp->state = HID_READY; - osalSysUnlock(); -} - -/** - * @brief Stops the driver. - * @details Any thread waiting on the driver's queues will be awakened with - * the message @p MSG_RESET. - * - * @param[in] uhdp pointer to a @p USBHIDDriver object - * - * @api - */ -void hidStop(USBHIDDriver *uhdp) { - USBDriver *usbp = uhdp->config->usbp; - - osalDbgCheck(uhdp != NULL); - - osalSysLock(); - osalDbgAssert((uhdp->state == HID_STOP) || (uhdp->state == HID_READY), - "invalid state"); - - /* Driver in stopped state.*/ - usbp->in_params[uhdp->config->int_in - 1U] = NULL; - usbp->out_params[uhdp->config->int_out - 1U] = NULL; - uhdp->state = HID_STOP; - - /* Enforces a disconnection.*/ - hidDisconnectI(uhdp); - osalOsRescheduleS(); - osalSysUnlock(); -} - -/** - * @brief USB device disconnection handler. - * @note If this function is not called from an ISR then an explicit call - * to @p osalOsRescheduleS() in necessary afterward. - * - * @param[in] uhdp pointer to a @p USBHIDDriver object - * - * @iclass - */ -void hidDisconnectI(USBHIDDriver *uhdp) { - - /* Queues reset in order to signal the driver stop to the application.*/ - chnAddFlagsI(uhdp, CHN_DISCONNECTED); - ibqResetI(&uhdp->ibqueue); - obqResetI(&uhdp->obqueue); -} - -/** - * @brief USB device configured handler. - * - * @param[in] uhdp pointer to a @p USBHIDDriver object - * - * @iclass - */ -void hidConfigureHookI(USBHIDDriver *uhdp) { - uint8_t *buf; - - ibqResetI(&uhdp->ibqueue); - obqResetI(&uhdp->obqueue); - chnAddFlagsI(uhdp, CHN_CONNECTED); - - /* Starts the first OUT transaction immediately.*/ - buf = ibqGetEmptyBufferI(&uhdp->ibqueue); - - osalDbgAssert(buf != NULL, "no free buffer"); - - usbStartReceiveI(uhdp->config->usbp, uhdp->config->int_out, - buf, USB_HID_BUFFERS_SIZE); -} - -/** - * @brief Default requests hook. - * @details Applications wanting to use the USB HID driver can use - * this function at the end of the application specific - * requests hook. The HID_* requests handled here do not - * transfer any data to the application. - * The following requests are handled: - * - HID_GET_IDLE. - * - HID_GET_PROTOCOL. - * - HID_SET_REPORT. - * - HID_SET_IDLE. - * - HID_SET_PROTOCOL. - * - USB_REQ_GET_DESCRIPTOR. - * . - * - * @param[in] usbp pointer to the @p USBDriver object - * @return The hook status. - * @retval true Message handled internally. - * @retval false Message not handled. - */ -bool hidRequestsHook(USBDriver *usbp) { - const USBDescriptor *dp; - - if ((usbp->setup[0] & USB_RTYPE_TYPE_MASK) == USB_RTYPE_TYPE_CLASS) { - switch (usbp->setup[1]) { - case HID_GET_IDLE: - usbSetupTransfer(usbp, NULL, 0, NULL); - return true; - case HID_GET_PROTOCOL: - return true; - case HID_SET_REPORT: - usbSetupTransfer(usbp, NULL, 0, NULL); - return true; - case HID_SET_IDLE: - usbSetupTransfer(usbp, NULL, 0, NULL); - return true; - case HID_SET_PROTOCOL: - return true; - default: - return false; - } - } - - /* GET_DESCRIPTOR from interface not handled by default so handle it here */ - if (((usbp->setup[0] & USB_RTYPE_DIR_MASK) == USB_RTYPE_DIR_DEV2HOST) && - ((usbp->setup[0] & USB_RTYPE_RECIPIENT_MASK) == USB_RTYPE_RECIPIENT_INTERFACE)) { - switch (usbp->setup[1]) { - case USB_REQ_GET_DESCRIPTOR: - dp = usbp->config->get_descriptor_cb(usbp, usbp->setup[3], usbp->setup[2], - get_hword(&usbp->setup[4])); - if (dp == NULL) - return false; - - usbSetupTransfer(usbp, (uint8_t *)dp->ud_string, dp->ud_size, NULL); - return true; - default: - return false; - } - } - return false; -} - -/** - * @brief Default data transmitted callback. - * @details The application must use this function as callback for the IN - * data endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep IN endpoint number - */ -void hidDataTransmitted(USBDriver *usbp, usbep_t ep) { - uint8_t *buf; - size_t n; - USBHIDDriver *uhdp = usbp->in_params[ep - 1U]; - - if (uhdp == NULL) { - return; - } - - osalSysLockFromISR(); - - /* Signaling that space is available in the output queue.*/ - chnAddFlagsI(uhdp, CHN_OUTPUT_EMPTY); - - /* Freeing the buffer just transmitted, if it was not a zero size packet.*/ - if (usbp->epc[ep]->in_state->txsize > 0U) { - obqReleaseEmptyBufferI(&uhdp->obqueue); - } - - /* Checking if there is a buffer ready for transmission.*/ - buf = obqGetFullBufferI(&uhdp->obqueue, &n); - - if (buf != NULL) { - /* The endpoint cannot be busy, we are in the context of the callback, - so it is safe to transmit without a check.*/ - usbStartTransmitI(usbp, ep, buf, n); - } - else if ((usbp->epc[ep]->in_state->txsize > 0U) && - ((usbp->epc[ep]->in_state->txsize & - ((size_t)usbp->epc[ep]->in_maxsize - 1U)) == 0U)) { - /* Transmit zero sized packet in case the last one has maximum allowed - size. Otherwise the recipient may expect more data coming soon and - not return buffered data to app. See section 5.8.3 Bulk Transfer - Packet Size Constraints of the USB Specification document.*/ - usbStartTransmitI(usbp, ep, usbp->setup, 0); - - } - else { - /* Nothing to transmit.*/ - } - - osalSysUnlockFromISR(); -} - -/** - * @brief Default data received callback. - * @details The application must use this function as callback for the OUT - * data endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep OUT endpoint number - */ -void hidDataReceived(USBDriver *usbp, usbep_t ep) { - uint8_t *buf; - USBHIDDriver *uhdp = usbp->out_params[ep - 1U]; - - if (uhdp == NULL) { - return; - } - - osalSysLockFromISR(); - - /* Signaling that data is available in the input queue.*/ - chnAddFlagsI(uhdp, CHN_INPUT_AVAILABLE); - - /* Posting the filled buffer in the queue.*/ - ibqPostFullBufferI(&uhdp->ibqueue, - usbGetReceiveTransactionSizeX(uhdp->config->usbp, ep)); - - /* The endpoint cannot be busy, we are in the context of the callback, - so a packet is in the buffer for sure. Trying to get a free buffer - for the next transaction.*/ - buf = ibqGetEmptyBufferI(&uhdp->ibqueue); - if (buf != NULL) { - /* Buffer found, starting a new transaction.*/ - usbStartReceiveI(uhdp->config->usbp, ep, buf, USB_HID_BUFFERS_SIZE); - } - - osalSysUnlockFromISR(); -} - -/** - * @brief Write HID Report - * @details The function writes data from a buffer to an output queue. The - * operation completes when the specified amount of data has been - * transferred or if the queue has been reset. - * - * @param[in] uhdp pointer to the @p USBHIDDriver object - * @param[in] bp pointer to the report data buffer - * @param[in] n the maximum amount of data to be transferred, the - * value 0 is reserved - * @return The number of bytes effectively transferred. - * @retval 0 if a timeout occurred. - * - * @api - */ -size_t hidWriteReport(USBHIDDriver *uhdp, uint8_t *bp, size_t n) { - size_t val; - - val = uhdp->vmt->write(uhdp, bp, n); - - if (val > 0) - uhdp->vmt->flush(uhdp); - - return val; -} - -/** - * @brief Write HID report with timeout - * @details The function writes data from a buffer to an output queue. The - * operation completes when the specified amount of data has been - * transferred or after the specified timeout or if the queue has - * been reset. - * - * @param[in] uhdp pointer to the @p USBHIDDriver object - * @param[in] bp pointer to the report data buffer - * @param[in] n the maximum amount of data to be transferred, the - * value 0 is reserved - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The number of bytes effectively transferred. - * @retval 0 if a timeout occurred. - * - * @api - */ -size_t hidWriteReportt(USBHIDDriver *uhdp, uint8_t *bp, size_t n, systime_t timeout) { - size_t val; - - val = uhdp->vmt->writet(uhdp, bp, n, timeout); - - if (val > 0) - uhdp->vmt->flush(uhdp); - - return val; -} - -/** - * @brief Read HID report - * @details The function reads data from an input queue into a buffer. - * The operation completes when the specified amount of data has been - * transferred or if the queue has been reset. - * - * @param[in] uhdp pointer to the @p input_buffers_queue_t object - * @param[out] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred, the - * value 0 is reserved - * @return The number of bytes effectively transferred. - * @retval 0 if a timeout occurred. - * - * @api - */ -size_t hidReadReport(USBHIDDriver *uhdp, uint8_t *bp, size_t n) { - - return uhdp->vmt->read(uhdp, bp, n); -} - -/** - * @brief Read HID report with timeout - * @details The function reads data from an input queue into a buffer. - * The operation completes when the specified amount of data has been - * transferred or after the specified timeout or if the queue has - * been reset. - * - * @param[in] uhdp pointer to the @p input_buffers_queue_t object - * @param[out] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred, the - * value 0 is reserved - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The number of bytes effectively transferred. - * @retval 0 if a timeout occurred. - * - * @api - */ -size_t hidReadReportt(USBHIDDriver *uhdp, uint8_t *bp, size_t n, systime_t timeout) { - - return uhdp->vmt->readt(uhdp, bp, n, timeout); -} - -#endif /* HAL_USE_USB_HID == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/hal/src/hal_usb_msd.c b/firmware/ChibiOS_16/community/os/hal/src/hal_usb_msd.c deleted file mode 100644 index 6cc5386509..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/src/hal_usb_msd.c +++ /dev/null @@ -1,409 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2016 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_usb_msd.c - * @brief USM mass storage device code. - * - * @addtogroup usb_msd - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_USB_MSD == TRUE) || defined(__DOXYGEN__) - -#include - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define MSD_REQ_RESET 0xFF -#define MSD_GET_MAX_LUN 0xFE - -#define MSD_CBW_SIGNATURE 0x43425355 -#define MSD_CSW_SIGNATURE 0x53425355 - -#define MSD_THD_PRIO NORMALPRIO - -#define CBW_FLAGS_RESERVED_MASK 0b01111111 -#define CBW_LUN_RESERVED_MASK 0b11110000 -#define CBW_CMD_LEN_RESERVED_MASK 0b11000000 - -#define CSW_STATUS_PASSED 0x00 -#define CSW_STATUS_FAILED 0x01 -#define CSW_STATUS_PHASE_ERROR 0x02 - -#define MSD_SETUP_WORD(setup, index) (uint16_t)(((uint16_t)setup[index+1] << 8)\ - | (setup[index] & 0x00FF)) - -#define MSD_SETUP_VALUE(setup) MSD_SETUP_WORD(setup, 2) -#define MSD_SETUP_INDEX(setup) MSD_SETUP_WORD(setup, 4) -#define MSD_SETUP_LENGTH(setup) MSD_SETUP_WORD(setup, 6) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ -/** - * @brief USB mass storage driver identifier. - */ -USBMassStorageDriver USBMSD1; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief Hardcoded default SCSI inquiry response structure. - */ -static const scsi_inquiry_response_t default_scsi_inquiry_response = { - 0x00, /* direct access block device */ - 0x80, /* removable */ - 0x04, /* SPC-2 */ - 0x02, /* response data format */ - 0x20, /* response has 0x20 + 4 bytes */ - 0x00, - 0x00, - 0x00, - "Chibios", - "Mass Storage", - {'v',CH_KERNEL_MAJOR+'0','.',CH_KERNEL_MINOR+'0'} -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Checks validity of CBW content. - * @details The device shall consider the CBW valid when: - * • The CBW was received after the device had sent a CSW or after a reset, - * • the CBW is 31 (1Fh) bytes in length, - * • and the dCBWSignature is equal to 43425355h. - * - * @param[in] cbw pointer to the @p msd_cbw_t object - * @param[in] recvd number of received bytes - * - * @return Operation status. - * @retval true CBW is meaningful. - * @retval false CBW is bad. - * - * @notapi - */ -static bool cbw_valid(const msd_cbw_t *cbw, msg_t recvd) { - if ((sizeof(msd_cbw_t) != recvd) || (cbw->signature != MSD_CBW_SIGNATURE)) { - return false; - } - else { - return true; - } -} - -/** - * @brief Checks meaningfulness of CBW content. - * @details The device shall consider the contents of a valid CBW meaningful when: - * • no reserved bits are set, - * • the bCBWLUN contains a valid LUN supported by the device, - * • and both bCBWCBLength and the content of the CBWCB are in - * accordance with bInterfaceSubClass. - * - * @param[in] cbw pointer to the @p msd_cbw_t object - * - * @return Operation status. - * @retval true CBW is meaningful. - * @retval false CBW is bad. - * - * @notapi - */ -static bool cbw_meaningful(const msd_cbw_t *cbw) { - if (((cbw->cmd_len & CBW_CMD_LEN_RESERVED_MASK) != 0) - || ((cbw->flags & CBW_FLAGS_RESERVED_MASK) != 0) - || (cbw->lun != 0)) { - return false; - } - else { - return true; - } -} - -/** - * @brief SCSI transport transmit function. - * - * @param[in] transport pointer to the @p SCSITransport object - * @param[in] data payload - * @param[in] len number of bytes to be transmitted - * - * @return Number of successfully transmitted bytes. - - * @notapi - */ -static uint32_t scsi_transport_transmit(const SCSITransport *transport, - const uint8_t *data, size_t len) { - - usb_scsi_transport_handler_t *trp = transport->handler; - msg_t status = usbTransmit(trp->usbp, trp->ep, data, len); - if (MSG_OK == status) - return len; - else - return 0; -} - -/** - * @brief SCSI transport receive function. - * - * @param[in] transport pointer to the @p SCSITransport object - * @param[in] data payload - * @param[in] len number bytes to be received - * - * @return Number of successfully received bytes. - - * @notapi - */ -static uint32_t scsi_transport_receive(const SCSITransport *transport, - uint8_t *data, size_t len) { - - usb_scsi_transport_handler_t *trp = transport->handler; - msg_t status = usbReceive(trp->usbp, trp->ep, data, len); - if (MSG_RESET != status) - return status; - else - return 0; -} - -/** - * @brief Fills and sends CSW message. - * - * @param[in] msdp pointer to the @p USBMassStorageDriver object - * @param[in] status status returned by SCSI layer - * @param[in] residue number of residue bytes in case of failed transaction - * - * @notapi - */ -static void send_csw(USBMassStorageDriver *msdp, uint8_t status, - uint32_t residue) { - - msdp->csw.signature = MSD_CSW_SIGNATURE; - msdp->csw.data_residue = residue; - msdp->csw.tag = msdp->cbw.tag; - msdp->csw.status = status; - - usbTransmit(msdp->usbp, USB_MSD_DATA_EP, (uint8_t *)&msdp->csw, - sizeof(msd_csw_t)); -} - -/** - * @brief Mass storage worker thread. - * - * @param[in] arg pointer to the @p USBMassStorageDriver object - * - * @notapi - */ -static THD_FUNCTION(usb_msd_worker, arg) { - USBMassStorageDriver *msdp = arg; - chRegSetThreadName("usb_msd_worker"); - - while(! chThdShouldTerminateX()) { - const msg_t status = usbReceive(msdp->usbp, USB_MSD_DATA_EP, - (uint8_t *)&msdp->cbw, sizeof(msd_cbw_t)); - if (MSG_RESET == status) { - osalThreadSleepMilliseconds(50); - } - else if (cbw_valid(&msdp->cbw, status) && cbw_meaningful(&msdp->cbw)) { - if (SCSI_SUCCESS == scsiExecCmd(&msdp->scsi_target, msdp->cbw.cmd_data)) { - send_csw(msdp, CSW_STATUS_PASSED, 0); - } - else { - send_csw(msdp, CSW_STATUS_FAILED, scsiResidue(&msdp->scsi_target)); - } - } - else { - ; /* do NOT send CSW here. Incorrect CBW must be silently ignored */ - } - } - - chThdExit(MSG_OK); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Mass storage specific request hook for USB. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -bool msd_request_hook(USBDriver *usbp) { - - if (((usbp->setup[0] & USB_RTYPE_TYPE_MASK) == USB_RTYPE_TYPE_CLASS) && - ((usbp->setup[0] & USB_RTYPE_RECIPIENT_MASK) == USB_RTYPE_RECIPIENT_INTERFACE)) { - /* check that the request is for interface 0.*/ - if (MSD_SETUP_INDEX(usbp->setup) != 0) - return false; - - /* act depending on bRequest = setup[1] */ - switch(usbp->setup[1]) { - case MSD_REQ_RESET: - /* check that it is a HOST2DEV request */ - if (((usbp->setup[0] & USB_RTYPE_DIR_MASK) != USB_RTYPE_DIR_HOST2DEV) || - (MSD_SETUP_LENGTH(usbp->setup) != 0) || - (MSD_SETUP_VALUE(usbp->setup) != 0)) { - return false; - } - - /* - As required by the BOT specification, the Bulk-only mass storage reset request (classspecific - request) is implemented. This request is used to reset the mass storage device and - its associated interface. This class-specific request should prepare the device for the next - CBW from the host. - To generate the BOT Mass Storage Reset, the host must send a device request on the - default pipe of: - • bmRequestType: Class, interface, host to device - • bRequest field set to 255 (FFh) - • wValue field set to ‘0’ - • wIndex field set to the interface number - • wLength field set to ‘0’ - */ - chSysLockFromISR(); - - /* release and abandon current transmission */ - usbStallReceiveI(usbp, 1); - usbStallTransmitI(usbp, 1); - /* The device shall NAK the status stage of the device request until - * the Bulk-Only Mass Storage Reset is complete. - * NAK EP1 in and out */ - usbp->otg->ie[1].DIEPCTL = DIEPCTL_SNAK; - usbp->otg->oe[1].DOEPCTL = DOEPCTL_SNAK; - - chSysUnlockFromISR(); - - /* response to this request using EP0 */ - usbSetupTransfer(usbp, 0, 0, NULL); - return true; - - case MSD_GET_MAX_LUN: - /* check that it is a DEV2HOST request */ - if (((usbp->setup[0] & USB_RTYPE_DIR_MASK) != USB_RTYPE_DIR_DEV2HOST) || - (MSD_SETUP_LENGTH(usbp->setup) != 1) || - (MSD_SETUP_VALUE(usbp->setup) != 0)) { - return false; - } - - /* stall to indicate that we don't support LUN */ - osalSysLockFromISR(); - usbStallTransmitI(usbp, 0); - osalSysUnlockFromISR(); - return true; - - default: - return false; - break; - } - } - return false; -} - -/** - * @brief Initializes the standard part of a @p USBMassStorageDriver structure. - * - * @param[out] msdp pointer to the @p USBMassStorageDriver object - * - * @init - */ -void msdObjectInit(USBMassStorageDriver *msdp) { - - memset(msdp, 0x55, sizeof(USBMassStorageDriver)); - msdp->state = USB_MSD_STOP; - msdp->usbp = NULL; - msdp->worker = NULL; - - scsiObjectInit(&msdp->scsi_target); -} - -/** - * @brief Stops the USB mass storage driver. - * - * @param[in] msdp pointer to the @p USBMassStorageDriver object - * - * @api - */ -void msdStop(USBMassStorageDriver *msdp) { - - osalDbgCheck(msdp != NULL); - osalDbgAssert((msdp->state == USB_MSD_READY), "invalid state"); - - chThdTerminate(msdp->worker); - chThdWait(msdp->worker); - - scsiStop(&msdp->scsi_target); - - msdp->worker = NULL; - msdp->state = USB_MSD_STOP; - msdp->usbp = NULL; -} - -/** - * @brief Configures and activates the USB mass storage driver. - * - * @param[in] msdp pointer to the @p USBMassStorageDriver object - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] blkdev pointer to the @p BaseBlockDevice object - * @param[in] blkbuf pointer to the working area buffer, must be allocated - * by user, must be big enough to store 1 data block - * @param[in] inquiry pointer to the SCSI inquiry response structure, - * set it to @p NULL to use default hardcoded value. - * - * @api - */ -void msdStart(USBMassStorageDriver *msdp, USBDriver *usbp, - BaseBlockDevice *blkdev, uint8_t *blkbuf, - const scsi_inquiry_response_t *inquiry) { - - osalDbgCheck((msdp != NULL) && (usbp != NULL) - && (blkdev != NULL) && (blkbuf != NULL)); - osalDbgAssert((msdp->state == USB_MSD_STOP), "invalid state"); - - msdp->usbp = usbp; - - msdp->usb_scsi_transport_handler.usbp = msdp->usbp; - msdp->usb_scsi_transport_handler.ep = USB_MSD_DATA_EP; - msdp->scsi_transport.handler = &msdp->usb_scsi_transport_handler; - msdp->scsi_transport.transmit = scsi_transport_transmit; - msdp->scsi_transport.receive = scsi_transport_receive; - - if (NULL == inquiry) { - msdp->scsi_config.inquiry_response = &default_scsi_inquiry_response; - } - else { - msdp->scsi_config.inquiry_response = inquiry; - } - msdp->scsi_config.blkbuf = blkbuf; - msdp->scsi_config.blkdev = blkdev; - msdp->scsi_config.transport = &msdp->scsi_transport; - - scsiStart(&msdp->scsi_target, &msdp->scsi_config); - - msdp->state = USB_MSD_READY; - msdp->worker = chThdCreateStatic(msdp->waMSDWorker, sizeof(msdp->waMSDWorker), - MSD_THD_PRIO, usb_msd_worker, msdp); -} - -#endif /* HAL_USE_USB_MSD */ - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/hal/src/hal_usbh.c b/firmware/ChibiOS_16/community/os/hal/src/hal_usbh.c deleted file mode 100644 index befe17f948..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/src/hal_usbh.c +++ /dev/null @@ -1,1395 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail) - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include "hal.h" - -#if HAL_USE_USBH - -#include "usbh/dev/hub.h" -#include "usbh/internal.h" -#include - -#if USBH_DEBUG_ENABLE_TRACE -#define udbgf(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define udbg(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define udbgf(f, ...) do {} while(0) -#define udbg(f, ...) do {} while(0) -#endif - -#if USBH_DEBUG_ENABLE_INFO -#define uinfof(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define uinfo(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define uinfof(f, ...) do {} while(0) -#define uinfo(f, ...) do {} while(0) -#endif - -#if USBH_DEBUG_ENABLE_WARNINGS -#define uwarnf(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define uwarn(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define uwarnf(f, ...) do {} while(0) -#define uwarn(f, ...) do {} while(0) -#endif - -#if USBH_DEBUG_ENABLE_ERRORS -#define uerrf(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define uerr(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define uerrf(f, ...) do {} while(0) -#define uerr(f, ...) do {} while(0) -#endif - -#if STM32_USBH_USE_OTG1 -USBHDriver USBHD1; -#endif -#if STM32_USBH_USE_OTG2 -USBHDriver USBHD2; -#endif - - -static void _classdriver_process_device(usbh_device_t *dev); -static bool _classdriver_load(usbh_device_t *dev, uint8_t class, - uint8_t subclass, uint8_t protocol, uint8_t *descbuff, uint16_t rem); - - -/*===========================================================================*/ -/* Checks. */ -/*===========================================================================*/ - -static inline void _check_dev(usbh_device_t *dev) { - osalDbgCheck(dev); - //TODO: add more checks. -} - -static inline void _check_ep(usbh_ep_t *ep) { - osalDbgCheck(ep != 0); - _check_dev(ep->device); - osalDbgCheck(ep->type <= 3); - //TODO: add more checks. -} - -static inline void _check_urb(usbh_urb_t *urb) { - osalDbgCheck(urb != 0); - _check_ep(urb->ep); - osalDbgCheck((urb->buff != NULL) || (urb->requestedLength == 0)); - //TODO: add more checks. -} - -/*===========================================================================*/ -/* Main driver API. */ -/*===========================================================================*/ - -void usbhObjectInit(USBHDriver *usbh) { - memset(usbh, 0, sizeof(*usbh)); - usbh->status = USBH_STATUS_STOPPED; -#if HAL_USBH_USE_HUB - INIT_LIST_HEAD(&usbh->hubs); - _usbhub_port_object_init(&usbh->rootport, usbh, 0, 1); -#else - _usbhub_port_object_init(&usbh->rootport, usbh, 1); -#endif -} - -void usbhInit(void) { -#if HAL_USBH_USE_HUB - uint8_t i; - for (i = 0; i < HAL_USBHHUB_MAX_INSTANCES; i++) { - usbhhubObjectInit(&USBHHUBD[i]); - } -#endif - usbh_lld_init(); -} - -void usbhStart(USBHDriver *usbh) { - usbDbgInit(usbh); - - osalSysLock(); - osalDbgAssert((usbh->status == USBH_STATUS_STOPPED) || (usbh->status == USBH_STATUS_STARTED), - "invalid state"); - usbh_lld_start(usbh); - usbh->status = USBH_STATUS_STARTED; - osalOsRescheduleS(); - osalSysUnlock(); -} - - -void usbhStop(USBHDriver *usbh) { - //TODO: implement - (void)usbh; -} -void usbhSuspend(USBHDriver *usbh) { - //TODO: implement - (void)usbh; -} -void usbhResume(USBHDriver *usbh) { - //TODO: implement - (void)usbh; -} - -/*===========================================================================*/ -/* Endpoint API. */ -/*===========================================================================*/ - -void usbhEPObjectInit(usbh_ep_t *ep, usbh_device_t *dev, const usbh_endpoint_descriptor_t *desc) { - osalDbgCheck(ep); - _check_dev(dev); - osalDbgCheck(desc); - - memset(ep, 0, sizeof(*ep)); - ep->device = dev; - ep->wMaxPacketSize = desc->wMaxPacketSize; - ep->address = desc->bEndpointAddress & 0x0F; - ep->type = (usbh_eptype_t) (desc->bmAttributes & 0x03); - if (ep->type != USBH_EPTYPE_CTRL) { - ep->in = (desc->bEndpointAddress & 0x80) ? TRUE : FALSE; - } - ep->bInterval = desc->bInterval; - - /* low-level part */ - usbh_lld_ep_object_init(ep); - - ep->status = USBH_EPSTATUS_CLOSED; -} - - -static void _ep0_object_init(usbh_device_t *dev, uint16_t wMaxPacketSize) { - const usbh_endpoint_descriptor_t ep0_descriptor = { - 7, //bLength - 5, //bDescriptorType - 0, //bEndpointAddress - 0, //bmAttributes - wMaxPacketSize, - 0, //bInterval - }; - usbhEPObjectInit(&dev->ctrl, dev, &ep0_descriptor); - usbhEPSetName(&dev->ctrl, "DEV[CTRL]"); -} - - -/*===========================================================================*/ -/* URB API. */ -/*===========================================================================*/ - -void usbhURBObjectInit(usbh_urb_t *urb, usbh_ep_t *ep, usbh_completion_cb callback, - void *user, void *buff, uint32_t len) { - - osalDbgCheck(urb != 0); - _check_ep(ep); - - /* initialize the common part: */ - urb->ep = ep; - urb->callback = callback; - urb->userData = user; - urb->buff = buff; - urb->requestedLength = len; - urb->actualLength = 0; - urb->status = USBH_URBSTATUS_INITIALIZED; - urb->waitingThread = 0; - urb->abortingThread = 0; - - /* initialize the ll part: */ - usbh_lld_urb_object_init(urb); -} - -void usbhURBObjectResetI(usbh_urb_t *urb) { - osalDbgAssert(!usbhURBIsBusy(urb), "invalid status"); - - osalDbgCheck((urb->waitingThread == 0) && (urb->abortingThread == 0)); - - urb->actualLength = 0; - urb->status = USBH_URBSTATUS_INITIALIZED; - - /* reset the ll part: */ - usbh_lld_urb_object_reset(urb); -} - -void usbhURBSubmitI(usbh_urb_t *urb) { - osalDbgCheckClassI(); - _check_urb(urb); - osalDbgAssert(urb->status == USBH_URBSTATUS_INITIALIZED, "invalid status"); - usbh_ep_t *const ep = urb->ep; - if (ep->status == USBH_EPSTATUS_HALTED) { - _usbh_urb_completeI(urb, USBH_URBSTATUS_STALL); - return; - } - if (ep->status != USBH_EPSTATUS_OPEN) { - _usbh_urb_completeI(urb, USBH_URBSTATUS_DISCONNECTED); - return; - } - if (!(usbhDeviceGetPort(ep->device)->status & USBH_PORTSTATUS_ENABLE)) { - _usbh_urb_completeI(urb, USBH_URBSTATUS_DISCONNECTED); - return; - } - urb->status = USBH_URBSTATUS_PENDING; - usbh_lld_urb_submit(urb); -} - -bool _usbh_urb_abortI(usbh_urb_t *urb, usbh_urbstatus_t status) { - osalDbgCheckClassI(); - _check_urb(urb); - - switch (urb->status) { -/* case USBH_URBSTATUS_UNINITIALIZED: - * case USBH_URBSTATUS_INITIALIZED: - * case USBH_URBSTATUS_ERROR: - * case USBH_URBSTATUS_TIMEOUT: - * case USBH_URBSTATUS_CANCELLED: - * case USBH_URBSTATUS_STALL: - * case USBH_URBSTATUS_DISCONNECTED: - * case USBH_URBSTATUS_OK: */ - default: - /* already finished */ - _usbh_urb_completeI(urb, status); - return TRUE; - -// case USBH_URBSTATUS_QUEUED: - case USBH_URBSTATUS_PENDING: - return usbh_lld_urb_abort(urb, status); - } -} - -void _usbh_urb_abort_and_waitS(usbh_urb_t *urb, usbh_urbstatus_t status) { - osalDbgCheckClassS(); - _check_urb(urb); - - if (_usbh_urb_abortI(urb, status) == FALSE) { - uwarn("URB wasn't aborted immediately, suspend"); - osalThreadSuspendS(&urb->abortingThread); - urb->abortingThread = 0; - } else { - osalOsRescheduleS(); - } - uwarn("URB aborted"); -} - -bool usbhURBCancelI(usbh_urb_t *urb) { - return _usbh_urb_abortI(urb, USBH_URBSTATUS_CANCELLED); -} - -void usbhURBCancelAndWaitS(usbh_urb_t *urb) { - _usbh_urb_abort_and_waitS(urb, USBH_URBSTATUS_CANCELLED); -} - -msg_t usbhURBWaitTimeoutS(usbh_urb_t *urb, systime_t timeout) { - msg_t ret; - - osalDbgCheckClassS(); - _check_urb(urb); - - switch (urb->status) { - case USBH_URBSTATUS_INITIALIZED: - case USBH_URBSTATUS_PENDING: -// case USBH_URBSTATUS_QUEUED: - ret = osalThreadSuspendTimeoutS(&urb->waitingThread, timeout); - urb->waitingThread = 0; - break; - - case USBH_URBSTATUS_OK: - ret = MSG_OK; - osalOsRescheduleS(); - break; - -/* case USBH_URBSTATUS_UNINITIALIZED: - * case USBH_URBSTATUS_ERROR: - * case USBH_URBSTATUS_TIMEOUT: - * case USBH_URBSTATUS_CANCELLED: - * case USBH_URBSTATUS_STALL: - * case USBH_URBSTATUS_DISCONNECTED: */ - default: - ret = MSG_RESET; - osalOsRescheduleS(); - break; - } - return ret; -} - -msg_t usbhURBSubmitAndWaitS(usbh_urb_t *urb, systime_t timeout) { - msg_t ret; - - osalDbgCheckClassS(); - _check_urb(urb); - - usbhURBSubmitI(urb); - ret = usbhURBWaitTimeoutS(urb, timeout); - if (ret == MSG_TIMEOUT) - _usbh_urb_abort_and_waitS(urb, USBH_URBSTATUS_TIMEOUT); - - return ret; -} - -static inline msg_t _wakeup_message(usbh_urbstatus_t status) { - if (status == USBH_URBSTATUS_OK) return MSG_OK; - if (status == USBH_URBSTATUS_TIMEOUT) return MSG_TIMEOUT; - return MSG_RESET; -} - -void _usbh_urb_completeI(usbh_urb_t *urb, usbh_urbstatus_t status) { - osalDbgCheckClassI(); - _check_urb(urb); - urb->status = status; - osalThreadResumeI(&urb->waitingThread, _wakeup_message(status)); - osalThreadResumeI(&urb->abortingThread, MSG_RESET); - if (urb->callback) - urb->callback(urb); -} - -/*===========================================================================*/ -/* Synchronous API. */ -/*===========================================================================*/ - -usbh_urbstatus_t usbhBulkTransfer(usbh_ep_t *ep, - void *data, - uint32_t len, - uint32_t *actual_len, - systime_t timeout) { - - osalDbgCheck(ep != NULL); - osalDbgCheck((data != NULL) || (len == 0)); - osalDbgAssert(ep->type == USBH_EPTYPE_BULK, "wrong ep"); - - usbh_urb_t urb; - usbhURBObjectInit(&urb, ep, 0, 0, data, len); - - osalSysLock(); - usbhURBSubmitAndWaitS(&urb, timeout); - osalSysUnlock(); - - if (actual_len != NULL) - *actual_len = urb.actualLength; - - return urb.status; -} - -usbh_urbstatus_t usbhControlRequestExtended(usbh_device_t *dev, - const usbh_control_request_t *req, - uint8_t *buff, - uint32_t *actual_len, - systime_t timeout) { - - _check_dev(dev); - osalDbgCheck(req != NULL); - - usbh_urb_t urb; - - usbhURBObjectInit(&urb, &dev->ctrl, 0, 0, buff, req->wLength); - urb.setup_buff = req; - - osalSysLock(); - usbhURBSubmitAndWaitS(&urb, timeout); - osalSysUnlock(); - - if (actual_len != NULL) - *actual_len = urb.actualLength; - - return urb.status; -} - -usbh_urbstatus_t usbhControlRequest(usbh_device_t *dev, - uint8_t bmRequestType, - uint8_t bRequest, - uint16_t wValue, - uint16_t wIndex, - uint16_t wLength, - uint8_t *buff) { - - const USBH_DEFINE_BUFFER(usbh_control_request_t, req) = { - bmRequestType, - bRequest, - wValue, - wIndex, - wLength - }; - return usbhControlRequestExtended(dev, &req, buff, NULL, MS2ST(1000)); -} - -/*===========================================================================*/ -/* Standard request helpers. */ -/*===========================================================================*/ - -#define USBH_GET_DESCRIPTOR(type, value, index) \ - USBH_STANDARDIN(type, \ - USBH_REQ_GET_DESCRIPTOR, \ - value, \ - index) \ - -#define USBH_GETDEVICEDESCRIPTOR \ - USBH_GET_DESCRIPTOR(USBH_REQTYPE_DEVICE, (USBH_DT_DEVICE << 8) | 0, 0) - -#define USBH_GETCONFIGURATIONDESCRIPTOR(index) \ - USBH_GET_DESCRIPTOR(USBH_REQTYPE_DEVICE, (USBH_DT_CONFIG << 8) | index, 0) - -#define USBH_GETSTRINGDESCRIPTOR(index, langID) \ - USBH_GET_DESCRIPTOR(USBH_REQTYPE_DEVICE, (USBH_DT_STRING << 8) | index, langID) - -bool usbhStdReqGetDeviceDescriptor(usbh_device_t *dev, - uint16_t wLength, - uint8_t *buf) { - usbh_device_descriptor_t *desc; - usbh_urbstatus_t ret = usbhControlRequest(dev, USBH_GETDEVICEDESCRIPTOR, wLength, buf); - desc = (usbh_device_descriptor_t *)buf; - if ((ret != USBH_URBSTATUS_OK) - || (desc->bLength != USBH_DT_DEVICE_SIZE) - || (desc->bDescriptorType != USBH_DT_DEVICE)) { - return HAL_FAILED; - } - return HAL_SUCCESS; -} - -bool usbhStdReqGetConfigurationDescriptor(usbh_device_t *dev, - uint8_t index, - uint16_t wLength, - uint8_t *buf) { - usbh_urbstatus_t ret = usbhControlRequest(dev, USBH_GETCONFIGURATIONDESCRIPTOR(index), wLength, buf); - usbh_config_descriptor_t *const desc = (usbh_config_descriptor_t *)buf; - if ((ret != USBH_URBSTATUS_OK) - || (desc->bLength < USBH_DT_CONFIG_SIZE) - || (desc->bDescriptorType != USBH_DT_CONFIG)) { - return HAL_FAILED; - } - return HAL_SUCCESS; -} - -bool usbhStdReqGetStringDescriptor(usbh_device_t *dev, - uint8_t index, - uint16_t langID, - uint16_t wLength, - uint8_t *buf) { - - osalDbgAssert(wLength >= USBH_DT_STRING_SIZE, "wrong size"); - usbh_string_descriptor_t *desc = (usbh_string_descriptor_t *)buf; - usbh_urbstatus_t ret = usbhControlRequest(dev, USBH_GETSTRINGDESCRIPTOR(index, langID), wLength, buf); - if ((ret != USBH_URBSTATUS_OK) - || (desc->bLength < USBH_DT_STRING_SIZE) - || (desc->bDescriptorType != USBH_DT_STRING)) { - return HAL_FAILED; - } - return HAL_SUCCESS; -} - - - -#define USBH_SET_INTERFACE(interface, alt) \ - USBH_STANDARDOUT(USBH_REQTYPE_INTERFACE, \ - USBH_REQ_SET_INTERFACE, \ - alt, \ - interface) \ - -#define USBH_GET_INTERFACE(interface) \ - USBH_STANDARDIN(USBH_REQTYPE_INTERFACE, \ - USBH_REQ_GET_INTERFACE, \ - 0, \ - interface) \ - -bool usbhStdReqSetInterface(usbh_device_t *dev, - uint8_t bInterfaceNumber, - uint8_t bAlternateSetting) { - - usbh_urbstatus_t ret = usbhControlRequest(dev, USBH_SET_INTERFACE(bInterfaceNumber, bAlternateSetting), 0, NULL); - if (ret != USBH_URBSTATUS_OK) - return HAL_FAILED; - - return HAL_SUCCESS; -} - -bool usbhStdReqGetInterface(usbh_device_t *dev, - uint8_t bInterfaceNumber, - uint8_t *bAlternateSetting) { - - USBH_DEFINE_BUFFER(uint8_t, alt); - - usbh_urbstatus_t ret = usbhControlRequest(dev, USBH_GET_INTERFACE(bInterfaceNumber), 1, &alt); - if (ret != USBH_URBSTATUS_OK) - return HAL_FAILED; - - *bAlternateSetting = alt; - return HAL_SUCCESS; -} - - -/*===========================================================================*/ -/* Device-related functions. */ -/*===========================================================================*/ - -static uint8_t _find_address(USBHDriver *host) { - uint8_t addr, i, j; - for (i = 0; i < sizeof_array(host->address_bitmap); i++) { - addr = host->address_bitmap[i]; - for (j = 0; j < 8; j++) { - if ((addr & (1 << j)) == 0) { - //found: - addr = i * 8 + j + 1; - host->address_bitmap[i] |= (1 << j); - return addr; - } - } - } - return 0; -} - -static void _free_address(USBHDriver *host, uint8_t addr) { - uinfof("Free address %d", addr); - host->address_bitmap[addr / 8] &= ~(1 << ((addr - 1) & 7)); -} - -static void _device_initialize(usbh_device_t *dev, usbh_devspeed_t speed) { - dev->address = 0; - dev->speed = speed; - dev->status = USBH_DEVSTATUS_DEFAULT; - dev->langID0 = 0; - dev->keepFullCfgDesc = 0; - _ep0_object_init(dev, 64); -} - -static bool _device_setaddress(usbh_device_t *dev, uint8_t address) { - usbh_urbstatus_t ret = usbhControlRequest(dev, - USBH_STANDARDOUT(USBH_REQTYPE_DEVICE, USBH_REQ_SET_ADDRESS, address, 0), - 0, - 0); - if (ret != USBH_URBSTATUS_OK) - return HAL_FAILED; - - dev->address = address; - return HAL_SUCCESS; -} - -static inline bool _device_read_basic_cfgdesc(usbh_device_t *dev, uint8_t bConfiguration) { - /* get configuration descriptor */ - return usbhStdReqGetConfigurationDescriptor(dev, bConfiguration, - sizeof(dev->basicConfigDesc), (uint8_t *)&dev->basicConfigDesc); -} - -static void _device_read_full_cfgdesc(usbh_device_t *dev, uint8_t bConfiguration) { - _check_dev(dev); - - uint8_t i; - - if (dev->fullConfigurationDescriptor != NULL) { - chHeapFree(dev->fullConfigurationDescriptor); - } - - dev->fullConfigurationDescriptor = - (uint8_t *)chHeapAlloc(0, dev->basicConfigDesc.wTotalLength); - - if (!dev->fullConfigurationDescriptor) - return; - - for (i = 0; i < 3; i++) { - if (usbhStdReqGetConfigurationDescriptor(dev, bConfiguration, - dev->basicConfigDesc.wTotalLength, - dev->fullConfigurationDescriptor) == HAL_SUCCESS) { - return; - } - osalThreadSleepMilliseconds(200); - } - - /* error */ - chHeapFree(dev->fullConfigurationDescriptor); - dev->fullConfigurationDescriptor = NULL; -} - -static void _device_free_full_cfgdesc(usbh_device_t *dev) { - osalDbgCheck(dev); - if (dev->fullConfigurationDescriptor != NULL) { - chHeapFree(dev->fullConfigurationDescriptor); - dev->fullConfigurationDescriptor = NULL; - } -} - - -#define USBH_SET_CONFIGURATION(type, value, index) \ - USBH_STANDARDOUT(type, \ - USBH_REQ_SET_CONFIGURATION, \ - value, \ - index) \ - -#define USBH_SETDEVICECONFIGURATION(index) \ - USBH_SET_CONFIGURATION(USBH_REQTYPE_DEVICE, index, 0) - - -static bool _device_set_configuration(usbh_device_t *dev, uint8_t configuration) { - usbh_urbstatus_t ret = usbhControlRequest(dev, - USBH_SETDEVICECONFIGURATION(configuration), - 0, - 0); - if (ret != USBH_URBSTATUS_OK) - return HAL_FAILED; - return HAL_SUCCESS; -} - -static bool _device_configure(usbh_device_t *dev, uint8_t bConfiguration) { - uint8_t i; - - uinfof("Reading basic configuration descriptor %d", bConfiguration); - for (i = 0; i < 3; i++) { - if (!_device_read_basic_cfgdesc(dev, bConfiguration)) - break; - } - - if (i == 3) { - uerrf("Could not read basic configuration descriptor %d; " - "won't configure device", bConfiguration); - return HAL_FAILED; - } - - uinfof("Selecting configuration %d", bConfiguration); - for (i = 0; i < 3; i++) { - if (!_device_set_configuration(dev, dev->basicConfigDesc.bConfigurationValue)) { - /* TODO: check if correctly configured using GET_CONFIGURATION */ - dev->status = USBH_DEVSTATUS_CONFIGURED; - dev->bConfiguration = bConfiguration; - - uinfo("Device configured."); - return HAL_SUCCESS; - } - } - - return HAL_FAILED; -} - -static bool _device_enumerate(usbh_device_t *dev) { - - uinfo("Enumerate."); - uinfo("Get first 8 bytes of device descriptor"); - - /* get first 8 bytes of device descriptor */ - if (usbhStdReqGetDeviceDescriptor(dev, 8, (uint8_t *)&dev->devDesc)) { - uerr("Error"); - return HAL_FAILED; - } - - uinfof("Configure bMaxPacketSize0 = %d", dev->devDesc.bMaxPacketSize0); - /* configure EP0 wMaxPacketSize */ - usbhEPClose(&dev->ctrl); - _ep0_object_init(dev, dev->devDesc.bMaxPacketSize0); - usbhEPOpen(&dev->ctrl); - - uint8_t addr = _find_address(dev->host); - if (addr == 0) { - uerr("No free addresses found"); - return HAL_FAILED; - } - - /* set device address */ - uinfof("Set device address: %d", addr); - if (_device_setaddress(dev, addr)) { - uerr("Error"); - _free_address(dev->host, addr); - return HAL_FAILED; - } - - /* update EP because of the address change */ - usbhEPClose(&dev->ctrl); - _ep0_object_init(dev, dev->devDesc.bMaxPacketSize0); - usbhEPOpen(&dev->ctrl); - - uinfof("Wait stabilization..."); - osalThreadSleepMilliseconds(HAL_USBH_DEVICE_ADDRESS_STABILIZATION); - - /* address is set */ - dev->status = USBH_DEVSTATUS_ADDRESS; - - uinfof("Get full device desc"); - /* get full device descriptor */ - if (usbhStdReqGetDeviceDescriptor(dev, sizeof(dev->devDesc), - (uint8_t *)&dev->devDesc)) { - uerr("Error"); - _device_setaddress(dev, 0); - _free_address(dev->host, addr); - return HAL_FAILED; - } - - uinfof("Enumeration finished."); - return HAL_SUCCESS; -} - -#if USBH_DEBUG_ENABLE && USBH_DEBUG_ENABLE_INFO -void usbhDevicePrintInfo(usbh_device_t *dev) { - USBH_DEFINE_BUFFER(char, str[64]); - usbh_device_descriptor_t *const desc = &dev->devDesc; - - uinfo("----- Device info -----"); - uinfo("Device descriptor:"); - uinfof("\tUSBSpec=%04x, #configurations=%d, langID0=%04x", - desc->bcdUSB, - desc->bNumConfigurations, - dev->langID0); - - uinfof("\tClass=%02x, Subclass=%02x, Protocol=%02x", - desc->bDeviceClass, - desc->bDeviceSubClass, - desc->bDeviceProtocol); - - uinfof("\tVID=%04x, PID=%04x, Release=%04x", - desc->idVendor, - desc->idProduct, - desc->bcdDevice); - - if (dev->langID0) { - usbhDeviceReadString(dev, str, sizeof(str), desc->iManufacturer, dev->langID0); - uinfof("\tManufacturer: %s", str); - usbhDeviceReadString(dev, str, sizeof(str), desc->iProduct, dev->langID0); - uinfof("\tProduct: %s", str); - usbhDeviceReadString(dev, str, sizeof(str), desc->iSerialNumber, dev->langID0); - uinfof("\tSerial Number: %s", str); - } - - if (dev->status == USBH_DEVSTATUS_CONFIGURED) { - uinfo("Configuration descriptor (partial):"); - usbh_config_descriptor_t *const cfg = &dev->basicConfigDesc; - uinfof("\tbConfigurationValue=%d, Length=%d, #interfaces=%d", - cfg->bConfigurationValue, - cfg->wTotalLength, - cfg->bNumInterfaces); - - uinfof("\tCurrent=%dmA", cfg->bMaxPower * 2); - uinfof("\tSelfPowered=%d, RemoteWakeup=%d", - cfg->bmAttributes & 0x40 ? 1 : 0, - cfg->bmAttributes & 0x20 ? 1 : 0); - if (dev->langID0) { - usbhDeviceReadString(dev, str, sizeof(str), cfg->iConfiguration, dev->langID0); - uinfof("\tName: %s", str); - } - } - - uinfo("----- End Device info -----"); - -} - -void usbhDevicePrintConfiguration(const uint8_t *descriptor, uint16_t rem) { - generic_iterator_t iep, icfg, ics; - if_iterator_t iif; - - uinfo("----- Configuration info -----"); - uinfo("Configuration descriptor:"); - cfg_iter_init(&icfg, descriptor, rem); - const usbh_config_descriptor_t *const cfgdesc = cfg_get(&icfg); - uinfof("Configuration %d, #IFs=%d", cfgdesc->bConfigurationValue, cfgdesc->bNumInterfaces); - - for (if_iter_init(&iif, &icfg); iif.valid; if_iter_next(&iif)) { - const usbh_interface_descriptor_t *const ifdesc = if_get(&iif); - - uinfof(" Interface %d, alt=%d, #EPs=%d, " - "Class=%02x, Subclass=%02x, Protocol=%02x", - ifdesc->bInterfaceNumber, ifdesc->bAlternateSetting, ifdesc->bNumEndpoints, - ifdesc->bInterfaceClass, ifdesc->bInterfaceSubClass, ifdesc->bInterfaceProtocol); - - for (cs_iter_init(&ics, (generic_iterator_t *)&iif); ics.valid; cs_iter_next(&ics)) { - uinfof(" Class-Specific descriptor, Length=%d, Type=%02x", - ics.curr[0], ics.curr[1]); - } - - for (ep_iter_init(&iep, &iif); iep.valid; ep_iter_next(&iep)) { - const usbh_endpoint_descriptor_t *const epdesc = ep_get(&iep); - - uinfof(" Endpoint descriptor, Address=%02x, Type=%d, MaxPacket=%d, Interval=%d", - epdesc->bEndpointAddress, - epdesc->bmAttributes & 3, - epdesc->wMaxPacketSize, - epdesc->bInterval); - - for (cs_iter_init(&ics, &iep); ics.valid; cs_iter_next(&ics)) { - uinfof(" Class-Specific descriptor, Length=%d, Type=%02x", - ics.curr[0], ics.curr[1]); - } - } - } - uinfo("----- End Configuration info -----"); -} -#endif - -bool usbhDeviceReadString(usbh_device_t *dev, char *dest, uint8_t size, - uint8_t index, uint16_t langID) { - - usbh_string_descriptor_t *const desc = (usbh_string_descriptor_t *)dest; - osalDbgAssert(size >= 2, "wrong size"); - - *dest = 0; - if (index == 0) - return HAL_SUCCESS; - if (usbhStdReqGetStringDescriptor(dev, index, langID, size, (uint8_t *)dest)) - return HAL_FAILED; - if (desc->bLength & 1) - return HAL_FAILED; - if (desc->bLength <= 2) - return HAL_SUCCESS; - - uint8_t nchars = desc->bLength / 2; /* including the trailing 0 */ - if (size < nchars) - nchars = size; - - char *src = (char *)&desc->wData[0]; - while (--nchars) { - *dest++ = *src; - src += 2; - } - *dest = 0; - return HAL_SUCCESS; -} - - - - -/*===========================================================================*/ -/* Port processing functions. */ -/*===========================================================================*/ - -static void _port_connected(usbh_port_t *port); - -static void _port_reset(usbh_port_t *port) { - usbhhubControlRequest(port->device.host, -#if HAL_USBH_USE_HUB - port->hub, -#endif - USBH_REQTYPE_OUT | USBH_REQTYPE_CLASS | USBH_REQTYPE_OTHER, - USBH_REQ_SET_FEATURE, - USBH_PORT_FEAT_RESET, - port->number, - 0, - 0); -} - -static void _port_update_status(usbh_port_t *port) { - uint32_t stat; - if (usbhhubControlRequest(port->device.host, -#if HAL_USBH_USE_HUB - port->hub, -#endif - USBH_REQTYPE_IN | USBH_REQTYPE_CLASS | USBH_REQTYPE_OTHER, - USBH_REQ_GET_STATUS, - 0, - port->number, - 4, - (uint8_t *)&stat) != USBH_URBSTATUS_OK) { - return; - } - port->status = stat & 0xffff; - port->c_status |= stat >> 16; -} - -static void _port_process_status_change(usbh_port_t *port) { - - _port_update_status(port); - - if (port->c_status & USBH_PORTSTATUS_C_CONNECTION) { - /* port connected status changed */ - port->c_status &= ~USBH_PORTSTATUS_C_CONNECTION; - usbhhubClearFeaturePort(port, USBH_PORT_FEAT_C_CONNECTION); - if ((port->status & (USBH_PORTSTATUS_CONNECTION | USBH_PORTSTATUS_ENABLE)) - == USBH_PORTSTATUS_CONNECTION) { - if (port->device.status != USBH_DEVSTATUS_DISCONNECTED) { - _usbh_port_disconnected(port); - } - - /* connected, disabled */ - _port_connected(port); - } else { - /* disconnected */ - _usbh_port_disconnected(port); - } - } - - if (port->c_status & USBH_PORTSTATUS_C_RESET) { - port->c_status &= ~USBH_PORTSTATUS_C_RESET; - usbhhubClearFeaturePort(port, USBH_PORT_FEAT_C_RESET); - } - - if (port->c_status & USBH_PORTSTATUS_C_ENABLE) { - port->c_status &= ~USBH_PORTSTATUS_C_ENABLE; - usbhhubClearFeaturePort(port, USBH_PORT_FEAT_C_ENABLE); - } - - if (port->c_status & USBH_PORTSTATUS_C_OVERCURRENT) { - port->c_status &= ~USBH_PORTSTATUS_C_OVERCURRENT; - usbhhubClearFeaturePort(port, USBH_PORT_FEAT_C_OVERCURRENT); - } - - if (port->c_status & USBH_PORTSTATUS_C_SUSPEND) { - port->c_status &= ~USBH_PORTSTATUS_C_SUSPEND; - usbhhubClearFeaturePort(port, USBH_PORT_FEAT_C_SUSPEND); - } - -} - - -static void _port_connected(usbh_port_t *port) { - /* connected */ - - systime_t start; - uint8_t i; - uint8_t retries; - usbh_devspeed_t speed; - USBH_DEFINE_BUFFER(usbh_string_descriptor_t, strdesc); - - uinfof("Port %d connected, wait debounce...", port->number); - - port->device.status = USBH_DEVSTATUS_ATTACHED; - - /* wait for attach de-bounce */ - osalThreadSleepMilliseconds(HAL_USBH_PORT_DEBOUNCE_TIME); - - /* check disconnection */ - _port_update_status(port); - if (port->c_status & USBH_PORTSTATUS_C_CONNECTION) { - /* connection state changed; abort */ - goto abort; - } - - port->device.status = USBH_DEVSTATUS_CONNECTED; - retries = 3; - -reset: - for (i = 0; i < 3; i++) { - uinfo("Try reset..."); - port->c_status &= ~(USBH_PORTSTATUS_C_RESET | USBH_PORTSTATUS_C_ENABLE); - _port_reset(port); - osalThreadSleepMilliseconds(20); /* give it some time to reset (min. 10ms) */ - start = osalOsGetSystemTimeX(); - while (TRUE) { - _port_update_status(port); - - /* check for disconnection */ - if (port->c_status & USBH_PORTSTATUS_C_CONNECTION) - goto abort; - - /* check for reset completion */ - if (port->c_status & USBH_PORTSTATUS_C_RESET) { - port->c_status &= ~USBH_PORTSTATUS_C_RESET; - usbhhubClearFeaturePort(port, USBH_PORT_FEAT_C_RESET); - - if ((port->status & (USBH_PORTSTATUS_ENABLE | USBH_PORTSTATUS_CONNECTION)) - == (USBH_PORTSTATUS_ENABLE | USBH_PORTSTATUS_CONNECTION)) { - goto reset_success; - } - } - - /* check for timeout */ - if (osalOsGetSystemTimeX() - start > HAL_USBH_PORT_RESET_TIMEOUT) break; - } - } - - /* reset procedure failed; abort */ - goto abort; - -reset_success: - - uinfo("Reset OK, recovery..."); - - /* reset recovery */ - osalThreadSleepMilliseconds(100); - - /* initialize object */ - if (port->status & USBH_PORTSTATUS_LOW_SPEED) { - speed = USBH_DEVSPEED_LOW; - } else if (port->status & USBH_PORTSTATUS_HIGH_SPEED) { - speed = USBH_DEVSPEED_HIGH; - } else { - speed = USBH_DEVSPEED_FULL; - } - _device_initialize(&port->device, speed); - usbhEPOpen(&port->device.ctrl); - - /* device with default address (0), try enumeration */ - if (_device_enumerate(&port->device)) { - /* enumeration failed */ - usbhEPClose(&port->device.ctrl); - - if (!--retries) - goto abort; - - /* retry reset & enumeration */ - goto reset; - } - - /* load the default language ID */ - uinfo("Loading langID0..."); - if (!usbhStdReqGetStringDescriptor(&port->device, 0, 0, - USBH_DT_STRING_SIZE, (uint8_t *)&strdesc) - && (strdesc.bLength >= 4) - && !usbhStdReqGetStringDescriptor(&port->device, 0, 0, - 4, (uint8_t *)&strdesc)) { - - port->device.langID0 = strdesc.wData[0]; - uinfof("langID0=%04x", port->device.langID0); - } - - /* check if the device has only one configuration */ - if (port->device.devDesc.bNumConfigurations == 1) { - uinfo("Device has only one configuration"); - _device_configure(&port->device, 0); - } - - _classdriver_process_device(&port->device); - return; - -abort: - uerr("Abort"); - port->device.status = USBH_DEVSTATUS_DISCONNECTED; -} - -void _usbh_port_disconnected(usbh_port_t *port) { - if (port->device.status == USBH_DEVSTATUS_DISCONNECTED) - return; - - uinfo("Port disconnected"); - - /* unload drivers */ - while (port->device.drivers) { - usbh_baseclassdriver_t *drv = port->device.drivers; - - /* unload */ - uinfof("Unload driver %s", drv->info->name); - drv->info->vmt->unload(drv); - - /* unlink */ - drv->dev = 0; - port->device.drivers = drv->next; - } - - /* close control endpoint */ - osalSysLock(); - usbhEPCloseS(&port->device.ctrl); - osalSysUnlock(); - - /* free address */ - if (port->device.address) - _free_address(port->device.host, port->device.address); - - _device_free_full_cfgdesc(&port->device); - - port->device.status = USBH_DEVSTATUS_DISCONNECTED; -} - - - -/*===========================================================================*/ -/* Hub processing functions. */ -/*===========================================================================*/ - -#if HAL_USBH_USE_HUB -static void _hub_update_status(USBHDriver *host, USBHHubDriver *hub) { - uint32_t stat; - if (usbhhubControlRequest(host, - hub, - USBH_REQTYPE_IN | USBH_REQTYPE_CLASS | USBH_REQTYPE_DEVICE, - USBH_REQ_GET_STATUS, - 0, - 0, - 4, - (uint8_t *)&stat) != USBH_URBSTATUS_OK) { - return; - } - if (hub) { - hub->status = stat & 0xffff; - hub->c_status |= stat >> 16; - } -} - -static void _hub_process_status_change(USBHDriver *host, USBHHubDriver *hub) { - uinfo("Hub status change. GET_STATUS."); - _hub_update_status(host, hub); - - if (hub->c_status & USBH_HUBSTATUS_C_HUB_LOCAL_POWER) { - hub->c_status &= ~USBH_HUBSTATUS_C_HUB_LOCAL_POWER; - uinfo("Clear USBH_HUB_FEAT_C_HUB_LOCAL_POWER"); - usbhhubClearFeatureHub(host, hub, USBH_HUB_FEAT_C_HUB_LOCAL_POWER); - } - - if (hub->c_status & USBH_HUBSTATUS_C_HUB_OVER_CURRENT) { - hub->c_status &= ~USBH_HUBSTATUS_C_HUB_OVER_CURRENT; - uinfo("Clear USBH_HUB_FEAT_C_HUB_OVER_CURRENT"); - usbhhubClearFeatureHub(host, hub, USBH_HUB_FEAT_C_HUB_OVER_CURRENT); - } -} - -static uint32_t _hub_get_status_change_bitmap(USBHDriver *host, USBHHubDriver *hub) { - if (hub != NULL) { - osalSysLock(); - uint32_t ret = hub->statuschange; - hub->statuschange = 0; - osalOsRescheduleS(); - osalSysUnlock(); - return ret; - } - return usbh_lld_roothub_get_statuschange_bitmap(host); -} - -#else -//TODO: replace the functions above -#endif - -#if HAL_USBH_USE_HUB -static void _hub_process(USBHDriver *host, USBHHubDriver *hub) { - uint32_t bitmap = _hub_get_status_change_bitmap(host, hub); - if (!bitmap) - return; - - if (bitmap & 1) { - _hub_process_status_change(host, hub); - bitmap &= ~1; - } - - usbh_port_t *port = (hub == NULL) ? &host->rootport : hub->ports; - uint8_t i; - for (i = 1; i < 32; i++) { - if (!bitmap || !port) - break; - if (bitmap & (1 << i)) { - bitmap &= ~(1 << i); - _port_process_status_change(port); - } - port = port->next; - } - -} -#else -static void _hub_process(USBHDriver *host) { - uint32_t bitmap = usbh_lld_roothub_get_statuschange_bitmap(host); - -#if 0 //TODO: complete _hub_process_status_change for root hub - if (bitmap & 1) { - _hub_process_status_change(host, hub); - bitmap &= ~1; - } -#endif - - if (!bitmap) - return; - - _port_process_status_change(&host->rootport); -} -#endif - -/*===========================================================================*/ -/* Main processing loop (enumeration, loading/unloading drivers, etc). */ -/*===========================================================================*/ -void usbhMainLoop(USBHDriver *usbh) { - - if (usbh->status == USBH_STATUS_STOPPED) - return; - -#if HAL_USBH_USE_HUB - /* process root hub */ - _hub_process(usbh, NULL); - - /* process connected hubs */ - USBHHubDriver *hub; - list_for_each_entry(hub, USBHHubDriver, &usbh->hubs, node) { - _hub_process(usbh, hub); - } -#else - /* process root hub */ - _hub_process(usbh); -#endif -} - - -/*===========================================================================*/ -/* IAD class driver. */ -/*===========================================================================*/ -#if HAL_USBH_USE_IAD -static usbh_baseclassdriver_t *iad_load(usbh_device_t *dev, const uint8_t *descriptor, uint16_t rem); -static void iad_unload(usbh_baseclassdriver_t *drv); -static const usbh_classdriver_vmt_t usbhiadClassDriverVMT = { - iad_load, - iad_unload -}; -static const usbh_classdriverinfo_t usbhiadClassDriverInfo = { - 0xef, 0x02, 0x01, "IAD", &usbhiadClassDriverVMT -}; - -static usbh_baseclassdriver_t *iad_load(usbh_device_t *dev, - const uint8_t *descriptor, uint16_t rem) { - (void)rem; - - if (descriptor[1] != USBH_DT_DEVICE) - return 0; - - uinfo("Load a driver for each IF collection."); - - generic_iterator_t icfg; - if_iterator_t iif; - const usbh_ia_descriptor_t *last_iad = 0; - - cfg_iter_init(&icfg, dev->fullConfigurationDescriptor, - dev->basicConfigDesc.wTotalLength); - if (!icfg.valid) { - uerr("Invalid configuration descriptor."); - return 0; - } - - for (if_iter_init(&iif, &icfg); iif.valid; if_iter_next(&iif)) { - if (iif.iad && (iif.iad != last_iad)) { - last_iad = iif.iad; - if (_classdriver_load(dev, iif.iad->bFunctionClass, - iif.iad->bFunctionSubClass, - iif.iad->bFunctionProtocol, - (uint8_t *)iif.iad, - (uint8_t *)iif.curr - (uint8_t *)iif.iad + iif.rem) != HAL_SUCCESS) { - uwarnf("No drivers found for IF collection #%d:%d", - iif.iad->bFirstInterface, - iif.iad->bFirstInterface + iif.iad->bInterfaceCount - 1); - } - } - } - - return 0; -} - -static void iad_unload(usbh_baseclassdriver_t *drv) { - (void)drv; -} -#endif - - -/*===========================================================================*/ -/* Class driver loader. */ -/*===========================================================================*/ - -static const usbh_classdriverinfo_t *usbh_classdrivers_lookup[] = { -#if HAL_USBH_USE_FTDI - &usbhftdiClassDriverInfo, -#endif -#if HAL_USBH_USE_IAD - &usbhiadClassDriverInfo, -#endif -#if HAL_USBH_USE_UVC - &usbhuvcClassDriverInfo, -#endif -#if HAL_USBH_USE_MSD - &usbhmsdClassDriverInfo, -#endif -#if HAL_USBH_USE_HUB - &usbhhubClassDriverInfo -#endif -}; - -static bool _classdriver_load(usbh_device_t *dev, uint8_t class, - uint8_t subclass, uint8_t protocol, uint8_t *descbuff, uint16_t rem) { - uint8_t i; - usbh_baseclassdriver_t *drv = NULL; - for (i = 0; i < sizeof_array(usbh_classdrivers_lookup); i++) { - const usbh_classdriverinfo_t *const info = usbh_classdrivers_lookup[i]; - if (class == 0xff) { - /* vendor specific */ - if (info->class == 0xff) { - uinfof("Try load vendor-specific driver %s", info->name); - drv = info->vmt->load(dev, descbuff, rem); - if (drv != NULL) - goto success; - } - } else if ((info->class < 0) || ((info->class == class) - && ((info->subclass < 0) || ((info->subclass == subclass) - && ((info->protocol < 0) || (info->protocol == protocol)))))) { - uinfof("Try load driver %s", info->name); - drv = info->vmt->load(dev, descbuff, rem); - -#if HAL_USBH_USE_IAD - /* special case: */ - if (info == &usbhiadClassDriverInfo) - return HAL_SUCCESS; -#endif - - if (drv != NULL) - goto success; - } - } - return HAL_FAILED; - -success: - /* Link this driver to the device */ - drv->next = dev->drivers; - dev->drivers = drv; - drv->dev = dev; - return HAL_SUCCESS; -} - -static void _classdriver_process_device(usbh_device_t *dev) { - uinfo("New device found."); - const usbh_device_descriptor_t *const devdesc = &dev->devDesc; - - usbhDevicePrintInfo(dev); - - /* TODO: Support multiple configurations - * - * Windows doesn't support them, so it's unlikely that any commercial USB device - * will have multiple configurations. - */ - if (dev->status != USBH_DEVSTATUS_CONFIGURED) { - uwarn("Multiple configurations not supported, selecting configuration #0"); - if (_device_configure(dev, 0) != HAL_SUCCESS) { - uerr("Couldn't configure device; abort."); - return; - } - } - - _device_read_full_cfgdesc(dev, dev->bConfiguration); - if (dev->fullConfigurationDescriptor == NULL) { - uerr("Couldn't read full configuration descriptor; abort."); - return; - } - - usbhDevicePrintConfiguration(dev->fullConfigurationDescriptor, - dev->basicConfigDesc.wTotalLength); - - if (devdesc->bDeviceClass == 0) { - /* each interface defines its own device class/subclass/protocol */ - uinfo("Load a driver for each IF."); - - generic_iterator_t icfg; - if_iterator_t iif; - uint8_t last_if = 0xff; - - cfg_iter_init(&icfg, dev->fullConfigurationDescriptor, - dev->basicConfigDesc.wTotalLength); - if (!icfg.valid) { - uerr("Invalid configuration descriptor."); - goto exit; - } - - for (if_iter_init(&iif, &icfg); iif.valid; if_iter_next(&iif)) { - const usbh_interface_descriptor_t *const ifdesc = if_get(&iif); - if (ifdesc->bInterfaceNumber != last_if) { - last_if = ifdesc->bInterfaceNumber; - if (_classdriver_load(dev, ifdesc->bInterfaceClass, - ifdesc->bInterfaceSubClass, - ifdesc->bInterfaceProtocol, - (uint8_t *)ifdesc, iif.rem) != HAL_SUCCESS) { - uwarnf("No drivers found for IF #%d", ifdesc->bInterfaceNumber); - } - } - } - - } else { - if (_classdriver_load(dev, devdesc->bDeviceClass, - devdesc->bDeviceSubClass, - devdesc->bDeviceProtocol, - (uint8_t *)devdesc, USBH_DT_DEVICE_SIZE) != HAL_SUCCESS) { - uwarn("No drivers found."); - } - } - -exit: - if (dev->keepFullCfgDesc == 0) { - _device_free_full_cfgdesc(dev); - } -} - - -#endif - diff --git a/firmware/ChibiOS_16/community/os/hal/src/usbh/hal_usbh_debug.c b/firmware/ChibiOS_16/community/os/hal/src/usbh/hal_usbh_debug.c deleted file mode 100644 index 51ca1663f4..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/src/usbh/hal_usbh_debug.c +++ /dev/null @@ -1,536 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail) - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include "hal.h" - -#if HAL_USE_USBH - -#include "ch.h" -#include "usbh/debug.h" -#include -#include "chprintf.h" - -#if USBH_DEBUG_ENABLE - -#define MAX_FILLER 11 -#define FLOAT_PRECISION 9 -#define MPRINTF_USE_FLOAT 0 - -static char *long_to_string_with_divisor(char *p, long num, unsigned radix, long divisor) -{ - int i; - char *q; - long l, ll; - - l = num; - if (divisor == 0) { - ll = num; - } else { - ll = divisor; - } - - q = p + MAX_FILLER; - do { - i = (int)(l % radix); - i += '0'; - if (i > '9') { - i += 'A' - '0' - 10; - } - *--q = i; - l /= radix; - } while ((ll /= radix) != 0); - - i = (int)(p + MAX_FILLER - q); - do { - *p++ = *q++; - } while (--i); - - return p; -} - -static char *ltoa(char *p, long num, unsigned radix) { - - return long_to_string_with_divisor(p, num, radix, 0); -} - -#if MPRINTF_USE_FLOAT -static const long _pow10[FLOAT_PRECISION] = {10, 100, 1000, 10000, 100000, 1000000, - 10000000, 100000000, 1000000000}; -static const double m10[FLOAT_PRECISION] = {5.0/100, 5.0/1000, 5.0/10000, 5.0/100000, 5.0/1000000, - 5.0/10000000, 5.0/100000000, 5.0/1000000000, 5.0/10000000000}; - -static char *ftoa(char *p, double num, unsigned long precision, bool dot) { - long l; - char *q; - double r; - - - if (precision == 0) { - l = (long)(num + 0.5); - return long_to_string_with_divisor(p, l, 10, 0); - } else { - if (precision > FLOAT_PRECISION) precision = FLOAT_PRECISION; - r = m10[precision - 1]; - precision = _pow10[precision - 1]; - - l = (long)num; - p = long_to_string_with_divisor(p, l, 10, 0); - if (dot) *p++ = '.'; - l = (long)((num - l + r) * precision); - q = long_to_string_with_divisor(p, l, 10, precision / 10) - 1; - - while (q > p) { - if (*q != '0') { - break; - } - --q; - } - return ++q; - } - - - - -} -#endif - -static inline void _put(char c) { - input_queue_t *iqp = &USBH_DEBUG_USBHD.iq; - - if (iqIsFullI(iqp)) - return; - - iqp->q_counter++; - *iqp->q_wrptr++ = c; - if (iqp->q_wrptr >= iqp->q_top) - iqp->q_wrptr = iqp->q_buffer; - -} - -int _dbg_printf(const char *fmt, va_list ap) { - char *p, *s, c, filler; - int i, precision, width; - int n = 0; - bool is_long, left_align, sign; - long l; -#if MPRINTF_USE_FLOAT - double f; - char tmpbuf[2*MAX_FILLER + 1]; -#else - char tmpbuf[MAX_FILLER + 1]; -#endif - - for (;;) { - - //agarrar nuevo caracter de formato - c = *fmt++; - - //chequeo eos - if (c == 0) return n; - - //copio los caracteres comunes - if (c != '%') { - _put(c); - n++; - continue; - } - - //encontré un '%' - p = tmpbuf; - s = tmpbuf; - - //left align - left_align = FALSE; - if (*fmt == '-') { - fmt++; - left_align = TRUE; - } - - sign = FALSE; - if (*fmt == '+') { - fmt++; - sign = TRUE; - } - - //filler - filler = ' '; - if (*fmt == '0') { - fmt++; - filler = '0'; - } - - //width - width = 0; - while (TRUE) { - c = *fmt++; - if (c >= '0' && c <= '9') - c -= '0'; - else if (c == '*') - c = va_arg(ap, int); - else - break; - width = width * 10 + c; - } - - //precision - precision = 0; - if (c == '.') { - - if (*fmt == 'n') { - fmt++; - - } - while (TRUE) { - c = *fmt++; - if (c >= '0' && c <= '9') - c -= '0'; - else if (c == '*') - c = va_arg(ap, int); - else - break; - precision = precision * 10 + c; - } - } - - //long modifier - if (c == 'l' || c == 'L') { - is_long = TRUE; - if (*fmt) - c = *fmt++; - } - else - is_long = (c >= 'A') && (c <= 'Z'); - - /* Command decoding.*/ - switch (c) { - //char - case 'c': - filler = ' '; - *p++ = va_arg(ap, int); - break; - - //string - case 's': - filler = ' '; - if ((s = va_arg(ap, char *)) == 0) - s = (char *)"(null)"; - if (precision == 0) - precision = 32767; - - //strlen con límite hasta precision - for (p = s; *p && (--precision >= 0); p++) - ; - break; - - - - case 'D': - case 'd': - case 'I': - case 'i': - if (is_long) - l = va_arg(ap, long); - else - l = va_arg(ap, int); - if (l < 0) { - *p++ = '-'; - l = -l; - sign = TRUE; - } else if (sign) { - *p++ = '+'; - } - p = ltoa(p, l, 10); - break; - -#if MPRINTF_USE_FLOAT - case 'f': - f = va_arg(ap, double); - if (f < 0) { - *p++ = '-'; - f = -f; - sign = TRUE; - } else if (sign) { - *p++ = '+'; - } - if (prec == FALSE) precision = 6; - p = ftoa(p, f, precision, dot); - break; -#endif - - - case 'X': - case 'x': - c = 16; - goto unsigned_common; - case 'U': - case 'u': - c = 10; - goto unsigned_common; - case 'O': - case 'o': - c = 8; - -unsigned_common: - if (is_long) - l = va_arg(ap, unsigned long); - else - l = va_arg(ap, unsigned int); - p = ltoa(p, l, c); - break; - - //copiar - default: - *p++ = c; - break; - } - - //longitud - i = (int)(p - s); - - //calculo cuántos caracteres de filler debo poner - if ((width -= i) < 0) - width = 0; - - if (left_align == FALSE) - width = -width; - - if (width < 0) { - //alineado a la derecha - - //poner el signo adelante - if (sign && filler == '0') { - _put(*s++); - n++; - i--; - } - - //fill a la izquierda - do { - _put(filler); - n++; - } while (++width != 0); - } - - //copiar los caracteres - while (--i >= 0) { - _put(*s++); - n++; - } - - //fill a la derecha - while (width) { - _put(filler); - n++; - width--; - } - } - - //return n; // can raise 'code is unreachable' warning - -} - -static void _print_hdr(void) -{ - uint32_t hfnum = USBH_DEBUG_USBHD.otg->HFNUM; - uint16_t hfir = USBH_DEBUG_USBHD.otg->HFIR; - - _put(0xff); - _put(0xff); - _put(hfir & 0xff); - _put(hfir >> 8); - _put(hfnum & 0xff); - _put((hfnum >> 8) & 0xff); - _put((hfnum >> 16) & 0xff); - _put((hfnum >> 24) & 0xff); -} - -void usbDbgPrintf(const char *fmt, ...) -{ - va_list ap; - va_start(ap, fmt); - syssts_t sts = chSysGetStatusAndLockX(); - _print_hdr(); - _dbg_printf(fmt, ap); - _put(0); - chThdDequeueNextI(&USBH_DEBUG_USBHD.iq.q_waiting, Q_OK); - chSysRestoreStatusX(sts); - va_end(ap); -} - - -void usbDbgPuts(const char *s) -{ - uint32_t buff[2] = { - 0xffff | (USBH_DEBUG_USBHD.otg->HFIR << 16), - USBH_DEBUG_USBHD.otg->HFNUM - }; - uint8_t *p = (uint8_t *)buff; - uint8_t *top = p + 8; - - syssts_t sts = chSysGetStatusAndLockX(); - input_queue_t *iqp = &USBH_DEBUG_USBHD.iq; - int rem = sizeof(USBH_DEBUG_USBHD.dbg_buff) - iqp->q_counter; - while (rem) { - *iqp->q_wrptr++ = *p; - if (iqp->q_wrptr >= iqp->q_top) - iqp->q_wrptr = iqp->q_buffer; - rem--; - if (++p == top) break; - } - while (rem) { - *iqp->q_wrptr++ = *s; - if (iqp->q_wrptr >= iqp->q_top) - iqp->q_wrptr = iqp->q_buffer; - rem--; - if (!*s++) break; - } - iqp->q_counter = sizeof(USBH_DEBUG_USBHD.dbg_buff) - rem; - chThdDequeueNextI(&USBH_DEBUG_USBHD.iq.q_waiting, Q_OK); - chSysRestoreStatusX(sts); -} - -void usbDbgReset(void) { - const char *msg = "\r\n\r\n==== DEBUG OUTPUT RESET ====\r\n"; - - syssts_t sts = chSysGetStatusAndLockX(); - iqResetI(&USBH_DEBUG_USBHD.iq); - oqResetI(&USBH_DEBUG_SD.oqueue); - while (*msg) { - *USBH_DEBUG_SD.oqueue.q_wrptr++ = *msg++; - USBH_DEBUG_SD.oqueue.q_counter--; - } - chSysRestoreStatusX(sts); -} - -static int _get(void) { - if (!USBH_DEBUG_USBHD.iq.q_counter) return -1; - USBH_DEBUG_USBHD.iq.q_counter--; - uint8_t b = *USBH_DEBUG_USBHD.iq.q_rdptr++; - if (USBH_DEBUG_USBHD.iq.q_rdptr >= USBH_DEBUG_USBHD.iq.q_top) { - USBH_DEBUG_USBHD.iq.q_rdptr = USBH_DEBUG_USBHD.iq.q_buffer; - } - return b; -} - -void usbDbgSystemHalted(void) { - while (true) { - if (!((bool)((USBH_DEBUG_SD.oqueue.q_wrptr == USBH_DEBUG_SD.oqueue.q_rdptr) && (USBH_DEBUG_SD.oqueue.q_counter != 0U)))) - break; - USBH_DEBUG_SD.oqueue.q_counter++; - while (!(USART1->SR & USART_SR_TXE)); - USART1->DR = *USBH_DEBUG_SD.oqueue.q_rdptr++; - if (USBH_DEBUG_SD.oqueue.q_rdptr >= USBH_DEBUG_SD.oqueue.q_top) { - USBH_DEBUG_SD.oqueue.q_rdptr = USBH_DEBUG_SD.oqueue.q_buffer; - } - } - - int c; - int state = 0; - for (;;) { - c = _get(); if (c < 0) break; - - if (state == 0) { - if (c == 0xff) state = 1; - } else if (state == 1) { - if (c == 0xff) state = 2; - else (state = 0); - } else { - c = _get(); if (c < 0) return; - c = _get(); if (c < 0) return; - c = _get(); if (c < 0) return; - c = _get(); if (c < 0) return; - c = _get(); if (c < 0) return; - - while (true) { - c = _get(); if (c < 0) return; - if (!c) { - while (!(USART1->SR & USART_SR_TXE)); - USART1->DR = '\r'; - while (!(USART1->SR & USART_SR_TXE)); - USART1->DR = '\n'; - state = 0; - break; - } - while (!(USART1->SR & USART_SR_TXE)); - USART1->DR = c; - } - } - } -} - -static void usb_debug_thread(void *p) { - USBHDriver *host = (USBHDriver *)p; - uint8_t state = 0; - - chRegSetThreadName("USBH_DBG"); - while (true) { - msg_t c = iqGet(&host->iq); - if (c < 0) goto reset; - - if (state == 0) { - if (c == 0xff) state = 1; - } else if (state == 1) { - if (c == 0xff) state = 2; - else (state = 0); - } else { - uint16_t hfir; - uint32_t hfnum; - - hfir = c; - c = iqGet(&host->iq); if (c < 0) goto reset; - hfir |= c << 8; - - c = iqGet(&host->iq); if (c < 0) goto reset; - hfnum = c; - c = iqGet(&host->iq); if (c < 0) goto reset; - hfnum |= c << 8; - c = iqGet(&host->iq); if (c < 0) goto reset; - hfnum |= c << 16; - c = iqGet(&host->iq); if (c < 0) goto reset; - hfnum |= c << 24; - - uint32_t f = hfnum & 0xffff; - uint32_t p = 1000 - ((hfnum >> 16) / (hfir / 1000)); - chprintf((BaseSequentialStream *)&USBH_DEBUG_SD, "%05d.%03d ", f, p); - - while (true) { - c = iqGet(&host->iq); if (c < 0) goto reset; - if (!c) { - sdPut(&USBH_DEBUG_SD, '\r'); - sdPut(&USBH_DEBUG_SD, '\n'); - state = 0; - break; - } - sdPut(&USBH_DEBUG_SD, (uint8_t)c); - } - } - - continue; -reset: - state = 0; - } -} - -void usbDbgInit(USBHDriver *host) { - if (host != &USBH_DEBUG_USBHD) - return; - iqObjectInit(&USBH_DEBUG_USBHD.iq, USBH_DEBUG_USBHD.dbg_buff, sizeof(USBH_DEBUG_USBHD.dbg_buff), 0, 0); - chThdCreateStatic(USBH_DEBUG_USBHD.waDebug, sizeof(USBH_DEBUG_USBHD.waDebug), NORMALPRIO, usb_debug_thread, &USBH_DEBUG_USBHD); -} -#endif - -#endif diff --git a/firmware/ChibiOS_16/community/os/hal/src/usbh/hal_usbh_desciter.c b/firmware/ChibiOS_16/community/os/hal/src/usbh/hal_usbh_desciter.c deleted file mode 100644 index 63137d4ee5..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/src/usbh/hal_usbh_desciter.c +++ /dev/null @@ -1,165 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail) - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include "hal.h" - -#if HAL_USE_USBH - -#include "usbh/defs.h" -#include "usbh/desciter.h" - -void cfg_iter_init(generic_iterator_t *icfg, const uint8_t *buff, uint16_t rem) { - icfg->valid = 0; - - if ((buff[0] < 2) || (rem < 2) || (rem < buff[0]) - || (buff[0] < USBH_DT_CONFIG_SIZE) - || (buff[1] != USBH_DT_CONFIG)) - return; - - if (rem > ((usbh_config_descriptor_t *)buff)->wTotalLength) { - rem = ((usbh_config_descriptor_t *)buff)->wTotalLength; - } - - icfg->valid = 1; - icfg->rem = rem; - icfg->curr = buff; -} - -void if_iter_next(if_iterator_t *iif) { - const uint8_t *curr = iif->curr; - uint16_t rem = iif->rem; - - iif->valid = 0; - - if ((curr[0] < 2) || (rem < 2) || (rem < curr[0])) - return; - - for (;;) { - rem -= curr[0]; - curr += curr[0]; - - if ((curr[0] < 2) || (rem < 2) || (rem < curr[0])) - return; - - if (curr[1] == USBH_DT_INTERFACE_ASSOCIATION) { - if (curr[0] < USBH_DT_INTERFACE_ASSOCIATION_SIZE) - return; - - iif->iad = (usbh_ia_descriptor_t *)curr; - - } else if (curr[1] == USBH_DT_INTERFACE) { - if (curr[0] < USBH_DT_INTERFACE_SIZE) - return; - - if (iif->iad) { - if ((curr[2] < iif->iad->bFirstInterface) - || (curr[2] >= (iif->iad->bFirstInterface + iif->iad->bInterfaceCount))) - iif->iad = 0; - } - break; - } - } - - iif->valid = 1; - iif->rem = rem; - iif->curr = curr; -} - -void if_iter_init(if_iterator_t *iif, const generic_iterator_t *icfg) { - iif->iad = 0; - iif->curr = icfg->curr; - iif->rem = icfg->rem; - if_iter_next(iif); -} - -void ep_iter_next(generic_iterator_t *iep) { - const uint8_t *curr = iep->curr; - uint16_t rem = iep->rem; - - iep->valid = 0; - - if ((curr[0] < 2) || (rem < 2) || (rem < curr[0])) - return; - - for (;;) { - rem -= curr[0]; - curr += curr[0]; - - if ((curr[0] < 2) || (rem < 2) || (rem < curr[0])) - return; - - if ((curr[1] == USBH_DT_INTERFACE_ASSOCIATION) - || (curr[1] == USBH_DT_INTERFACE) - || (curr[1] == USBH_DT_CONFIG)) { - return; - } else if (curr[1] == USBH_DT_ENDPOINT) { - if (curr[0] < USBH_DT_ENDPOINT_SIZE) - return; - - break; - } - } - - iep->valid = 1; - iep->rem = rem; - iep->curr = curr; -} - -void ep_iter_init(generic_iterator_t *iep, const if_iterator_t *iif) { - iep->curr = iif->curr; - iep->rem = iif->rem; - ep_iter_next(iep); -} - -void cs_iter_next(generic_iterator_t *ics) { - const uint8_t *curr = ics->curr; - uint16_t rem = ics->rem; - - ics->valid = 0; - - if ((curr[0] < 2) || (rem < 2) || (rem < curr[0])) - return; - - //for (;;) { - rem -= curr[0]; - curr += curr[0]; - - if ((curr[0] < 2) || (rem < 2) || (rem < curr[0])) - return; - - if ((curr[1] == USBH_DT_INTERFACE_ASSOCIATION) - || (curr[1] == USBH_DT_INTERFACE) - || (curr[1] == USBH_DT_CONFIG) - || (curr[1] == USBH_DT_ENDPOINT)) { - return; - } - - // break; - //} - - ics->valid = 1; - ics->rem = rem; - ics->curr = curr; -} - -void cs_iter_init(generic_iterator_t *ics, const generic_iterator_t *iter) { - ics->curr = iter->curr; - ics->rem = iter->rem; - cs_iter_next(ics); -} - -#endif diff --git a/firmware/ChibiOS_16/community/os/hal/src/usbh/hal_usbh_ftdi.c b/firmware/ChibiOS_16/community/os/hal/src/usbh/hal_usbh_ftdi.c deleted file mode 100644 index 4bd729680b..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/src/usbh/hal_usbh_ftdi.c +++ /dev/null @@ -1,717 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail) - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include "hal.h" -#include "hal_usbh.h" - -#if HAL_USBH_USE_FTDI - -#if !HAL_USE_USBH -#error "USBHFTDI needs USBH" -#endif - -#include -#include "usbh/dev/ftdi.h" -#include "usbh/internal.h" - -//#pragma GCC optimize("Og") - - -#if USBHFTDI_DEBUG_ENABLE_TRACE -#define udbgf(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define udbg(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define udbgf(f, ...) do {} while(0) -#define udbg(f, ...) do {} while(0) -#endif - -#if USBHFTDI_DEBUG_ENABLE_INFO -#define uinfof(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define uinfo(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define uinfof(f, ...) do {} while(0) -#define uinfo(f, ...) do {} while(0) -#endif - -#if USBHFTDI_DEBUG_ENABLE_WARNINGS -#define uwarnf(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define uwarn(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define uwarnf(f, ...) do {} while(0) -#define uwarn(f, ...) do {} while(0) -#endif - -#if USBHFTDI_DEBUG_ENABLE_ERRORS -#define uerrf(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define uerr(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define uerrf(f, ...) do {} while(0) -#define uerr(f, ...) do {} while(0) -#endif - - -/*===========================================================================*/ -/* USB Class driver loader for FTDI */ -/*===========================================================================*/ -USBHFTDIDriver USBHFTDID[HAL_USBHFTDI_MAX_INSTANCES]; - -static usbh_baseclassdriver_t *_ftdi_load(usbh_device_t *dev, const uint8_t *descriptor, uint16_t rem); -static void _ftdi_unload(usbh_baseclassdriver_t *drv); - -static const usbh_classdriver_vmt_t class_driver_vmt = { - _ftdi_load, - _ftdi_unload -}; - -const usbh_classdriverinfo_t usbhftdiClassDriverInfo = { - 0xff, 0xff, 0xff, "FTDI", &class_driver_vmt -}; - -static USBHFTDIPortDriver *_find_port(void) { - uint8_t i; - for (i = 0; i < HAL_USBHFTDI_MAX_PORTS; i++) { - if (FTDIPD[i].ftdip == NULL) - return &FTDIPD[i]; - } - return NULL; -} - -static usbh_baseclassdriver_t *_ftdi_load(usbh_device_t *dev, const uint8_t *descriptor, uint16_t rem) { - int i; - USBHFTDIDriver *ftdip; - - if (dev->devDesc.idVendor != 0x0403) { - uerr("FTDI: Unrecognized VID"); - return NULL; - } - - switch (dev->devDesc.idProduct) { - case 0x6001: - case 0x6010: - case 0x6011: - case 0x6014: - case 0x6015: - break; - default: - uerr("FTDI: Unrecognized PID"); - return NULL; - } - - if ((rem < descriptor[0]) || (descriptor[1] != USBH_DT_INTERFACE)) - return NULL; - - const usbh_interface_descriptor_t * const ifdesc = (const usbh_interface_descriptor_t * const)descriptor; - if (ifdesc->bInterfaceNumber != 0) { - uwarn("FTDI: Will allocate driver along with IF #0"); - } - - /* alloc driver */ - for (i = 0; i < HAL_USBHFTDI_MAX_INSTANCES; i++) { - if (USBHFTDID[i].dev == NULL) { - ftdip = &USBHFTDID[i]; - goto alloc_ok; - } - } - - uwarn("FTDI: Can't alloc driver"); - - /* can't alloc */ - return NULL; - -alloc_ok: - /* initialize the driver's variables */ - ftdip->ports = 0; - switch (dev->devDesc.bcdDevice) { - case 0x200: //AM - uinfo("FTDI: Type A chip"); - ftdip->type = USBHFTDI_TYPE_A; - break; - case 0x400: //BM - case 0x500: //2232C - case 0x600: //R - case 0x1000: //230X - uinfo("FTDI: Type B chip"); - ftdip->type = USBHFTDI_TYPE_B; - break; - case 0x700: //2232H; - case 0x800: //4232H; - case 0x900: //232H; - uinfo("FTDI: Type H chip"); - ftdip->type = USBHFTDI_TYPE_H; - default: - uerr("FTDI: Unrecognized chip type"); - return NULL; - } - usbhEPSetName(&dev->ctrl, "FTD[CTRL]"); - - /* parse the configuration descriptor */ - generic_iterator_t iep, icfg; - if_iterator_t iif; - cfg_iter_init(&icfg, dev->fullConfigurationDescriptor, dev->basicConfigDesc.wTotalLength); - for (if_iter_init(&iif, &icfg); iif.valid; if_iter_next(&iif)) { - const usbh_interface_descriptor_t *const ifdesc = if_get(&iif); - uinfof("FTDI: Interface #%d", ifdesc->bInterfaceNumber); - - USBHFTDIPortDriver *const prt = _find_port(); - if (prt == NULL) { - uwarn("\tCan't alloc port for this interface"); - break; - } - - prt->ifnum = ifdesc->bInterfaceNumber; - prt->epin.status = USBH_EPSTATUS_UNINITIALIZED; - prt->epout.status = USBH_EPSTATUS_UNINITIALIZED; - - for (ep_iter_init(&iep, &iif); iep.valid; ep_iter_next(&iep)) { - const usbh_endpoint_descriptor_t *const epdesc = ep_get(&iep); - if ((epdesc->bEndpointAddress & 0x80) && (epdesc->bmAttributes == USBH_EPTYPE_BULK)) { - uinfof("BULK IN endpoint found: bEndpointAddress=%02x", epdesc->bEndpointAddress); - usbhEPObjectInit(&prt->epin, dev, epdesc); - usbhEPSetName(&prt->epin, "FTD[BIN ]"); - } else if (((epdesc->bEndpointAddress & 0x80) == 0) - && (epdesc->bmAttributes == USBH_EPTYPE_BULK)) { - uinfof("BULK OUT endpoint found: bEndpointAddress=%02x", epdesc->bEndpointAddress); - usbhEPObjectInit(&prt->epout, dev, epdesc); - usbhEPSetName(&prt->epout, "FTD[BOUT]"); - } else { - uinfof("unsupported endpoint found: bEndpointAddress=%02x, bmAttributes=%02x", - epdesc->bEndpointAddress, epdesc->bmAttributes); - } - } - - if ((prt->epin.status != USBH_EPSTATUS_CLOSED) - || (prt->epout.status != USBH_EPSTATUS_CLOSED)) { - uwarn("\tCouldn't find endpoints; can't alloc port for this interface"); - continue; - } - - /* link the new block driver to the list */ - prt->next = ftdip->ports; - ftdip->ports = prt; - prt->ftdip = ftdip; - - prt->state = USBHFTDIP_STATE_ACTIVE; - } - - return (usbh_baseclassdriver_t *)ftdip; - -} - -static void _stop(USBHFTDIPortDriver *ftdipp); -static void _ftdi_unload(usbh_baseclassdriver_t *drv) { - osalDbgCheck(drv != NULL); - USBHFTDIDriver *const ftdip = (USBHFTDIDriver *)drv; - USBHFTDIPortDriver *ftdipp = ftdip->ports; - - osalMutexLock(&ftdip->mtx); - while (ftdipp) { - _stop(ftdipp); - ftdipp = ftdipp->next; - } - - ftdipp = ftdip->ports; - osalSysLock(); - while (ftdipp) { - USBHFTDIPortDriver *next = ftdipp->next; - usbhftdipObjectInit(ftdipp); - ftdipp = next; - } - osalSysUnlock(); - osalMutexUnlock(&ftdip->mtx); -} - - -USBHFTDIPortDriver FTDIPD[HAL_USBHFTDI_MAX_PORTS]; - - -#define FTDI_COMMAND_RESET 0 -#define FTDI_RESET_ALL 0 -#define FTDI_RESET_PURGE_RX 1 -#define FTDI_RESET_PURGE_TX 2 - -#define FTDI_COMMAND_SETFLOW 2 - -#define FTDI_COMMAND_SETBAUD 3 - -#define FTDI_COMMAND_SETDATA 4 -#define FTDI_SETDATA_BREAK (0x1 << 14) - -#if 0 -#define FTDI_COMMAND_MODEMCTRL 1 -#define FTDI_COMMAND_GETMODEMSTATUS 5 /* Retrieve current value of modem status register */ -#define FTDI_COMMAND_SETEVENTCHAR 6 /* Set the event character */ -#define FTDI_COMMAND_SETERRORCHAR 7 /* Set the error character */ -#define FTDI_COMMAND_SETLATENCYTIMER 9 /* Set the latency timer */ -#define FTDI_COMMAND_GETLATENCYTIMER 10 /* Get the latency timer */ -#endif - -/* - * DATA FORMAT - * - * IN Endpoint - * - * The device reserves the first two bytes of data on this endpoint to contain - * the current values of the modem and line status registers. In the absence of - * data, the device generates a message consisting of these two status bytes - * every 40 ms - * - * Byte 0: Modem Status - * - * Offset Description - * B0 Reserved - must be 1 - * B1 Reserved - must be 0 - * B2 Reserved - must be 0 - * B3 Reserved - must be 0 - * B4 Clear to Send (CTS) - * B5 Data Set Ready (DSR) - * B6 Ring Indicator (RI) - * B7 Receive Line Signal Detect (RLSD) - * - * Byte 1: Line Status - * - * Offset Description - * B0 Data Ready (DR) - * B1 Overrun Error (OE) - * B2 Parity Error (PE) - * B3 Framing Error (FE) - * B4 Break Interrupt (BI) - * B5 Transmitter Holding Register (THRE) - * B6 Transmitter Empty (TEMT) - * B7 Error in RCVR FIFO - * - */ -#define FTDI_RS0_CTS (1 << 4) -#define FTDI_RS0_DSR (1 << 5) -#define FTDI_RS0_RI (1 << 6) -#define FTDI_RS0_RLSD (1 << 7) - -#define FTDI_RS_DR 1 -#define FTDI_RS_OE (1<<1) -#define FTDI_RS_PE (1<<2) -#define FTDI_RS_FE (1<<3) -#define FTDI_RS_BI (1<<4) -#define FTDI_RS_THRE (1<<5) -#define FTDI_RS_TEMT (1<<6) -#define FTDI_RS_FIFO (1<<7) - - -static usbh_urbstatus_t _ftdi_port_control(USBHFTDIPortDriver *ftdipp, - uint8_t bRequest, uint8_t wValue, uint8_t bHIndex, uint16_t wLength, - uint8_t *buff) { - - static const uint8_t bmRequestType[] = { - USBH_REQTYPE_VENDOR | USBH_REQTYPE_OUT | USBH_REQTYPE_DEVICE, //0 FTDI_COMMAND_RESET - USBH_REQTYPE_VENDOR | USBH_REQTYPE_OUT | USBH_REQTYPE_DEVICE, //1 FTDI_COMMAND_MODEMCTRL - USBH_REQTYPE_VENDOR | USBH_REQTYPE_OUT | USBH_REQTYPE_DEVICE, //2 FTDI_COMMAND_SETFLOW - USBH_REQTYPE_VENDOR | USBH_REQTYPE_OUT | USBH_REQTYPE_DEVICE, //3 FTDI_COMMAND_SETBAUD - USBH_REQTYPE_VENDOR | USBH_REQTYPE_OUT | USBH_REQTYPE_DEVICE, //4 FTDI_COMMAND_SETDATA - }; - - osalDbgCheck(bRequest < sizeof_array(bmRequestType)); - osalDbgCheck(bRequest != 1); - - const USBH_DEFINE_BUFFER(usbh_control_request_t, req) = { - bmRequestType[bRequest], - bRequest, - wValue, - (bHIndex << 8) | (ftdipp->ifnum + 1), - wLength - }; - - return usbhControlRequestExtended(ftdipp->ftdip->dev, &req, buff, NULL, MS2ST(1000)); -} - -static uint32_t _get_divisor(uint32_t baud, usbhftdi_type_t type) { - static const uint8_t divfrac[8] = {0, 3, 2, 4, 1, 5, 6, 7}; - uint32_t divisor; - - if (type == USBHFTDI_TYPE_A) { - uint32_t divisor3 = ((48000000UL / 2) + baud / 2) / baud; - uinfof("FTDI: desired=%dbps, real=%dbps", baud, (48000000UL / 2) / divisor3); - if ((divisor3 & 0x7) == 7) - divisor3++; /* round x.7/8 up to x+1 */ - - divisor = divisor3 >> 3; - divisor3 &= 0x7; - if (divisor3 == 1) - divisor |= 0xc000; - else if (divisor3 >= 4) - divisor |= 0x4000; - else if (divisor3 != 0) - divisor |= 0x8000; - else if (divisor == 1) - divisor = 0; /* special case for maximum baud rate */ - } else { - if (type == USBHFTDI_TYPE_B) { - divisor = ((48000000UL / 2) + baud / 2) / baud; - uinfof("FTDI: desired=%dbps, real=%dbps", baud, (48000000UL / 2) / divisor); - } else { - /* hi-speed baud rate is 10-bit sampling instead of 16-bit */ - if (baud < 1200) - baud = 1200; - divisor = (120000000UL * 8 + baud * 5) / (baud * 10); - uinfof("FTDI: desired=%dbps, real=%dbps", baud, (120000000UL * 8) / divisor / 10); - } - divisor = (divisor >> 3) | (divfrac[divisor & 0x7] << 14); - - /* Deal with special cases for highest baud rates. */ - if (divisor == 1) - divisor = 0; - else if (divisor == 0x4001) - divisor = 1; - - if (type == USBHFTDI_TYPE_H) - divisor |= 0x00020000; - } - return divisor; -} - -static usbh_urbstatus_t _set_baudrate(USBHFTDIPortDriver *ftdipp, uint32_t baudrate) { - uint32_t divisor = _get_divisor(baudrate, ftdipp->ftdip->type); - uint16_t wValue = (uint16_t)divisor; - uint16_t wIndex = (uint16_t)(divisor >> 16); - if (ftdipp->ftdip->dev->basicConfigDesc.bNumInterfaces > 1) - wIndex = (wIndex << 8) | (ftdipp->ifnum + 1); - - const USBH_DEFINE_BUFFER(usbh_control_request_t, req) = { - USBH_REQTYPE_VENDOR | USBH_REQTYPE_OUT | USBH_REQTYPE_DEVICE, - FTDI_COMMAND_SETBAUD, - wValue, - wIndex, - 0 - }; - return usbhControlRequestExtended(ftdipp->ftdip->dev, &req, NULL, NULL, MS2ST(1000)); -} - - -static void _submitOutI(USBHFTDIPortDriver *ftdipp, uint32_t len) { - udbgf("FTDI: Submit OUT %d", len); - ftdipp->oq_urb.requestedLength = len; - usbhURBObjectResetI(&ftdipp->oq_urb); - usbhURBSubmitI(&ftdipp->oq_urb); -} - -static void _out_cb(usbh_urb_t *urb) { - USBHFTDIPortDriver *const ftdipp = (USBHFTDIPortDriver *)urb->userData; - switch (urb->status) { - case USBH_URBSTATUS_OK: - ftdipp->oq_ptr = ftdipp->oq_buff; - ftdipp->oq_counter = 64; - chThdDequeueNextI(&ftdipp->oq_waiting, Q_OK); - return; - case USBH_URBSTATUS_DISCONNECTED: - uwarn("FTDI: URB OUT disconnected"); - chThdDequeueNextI(&ftdipp->oq_waiting, Q_RESET); - return; - default: - uerrf("FTDI: URB OUT status unexpected = %d", urb->status); - break; - } - usbhURBObjectResetI(&ftdipp->oq_urb); - usbhURBSubmitI(&ftdipp->oq_urb); -} - -static size_t _write_timeout(USBHFTDIPortDriver *ftdipp, const uint8_t *bp, - size_t n, systime_t timeout) { - chDbgCheck(n > 0U); - - size_t w = 0; - chSysLock(); - while (true) { - if (ftdipp->state != USBHFTDIP_STATE_READY) { - chSysUnlock(); - return w; - } - while (usbhURBIsBusy(&ftdipp->oq_urb)) { - if (chThdEnqueueTimeoutS(&ftdipp->oq_waiting, timeout) != Q_OK) { - chSysUnlock(); - return w; - } - } - - *ftdipp->oq_ptr++ = *bp++; - if (--ftdipp->oq_counter == 0) { - _submitOutI(ftdipp, 64); - chSchRescheduleS(); - } - chSysUnlock(); /* Gives a preemption chance in a controlled point.*/ - - w++; - if (--n == 0U) - return w; - - chSysLock(); - } -} - -static msg_t _put_timeout(USBHFTDIPortDriver *ftdipp, uint8_t b, systime_t timeout) { - - chSysLock(); - if (ftdipp->state != USBHFTDIP_STATE_READY) { - chSysUnlock(); - return Q_RESET; - } - - while (usbhURBIsBusy(&ftdipp->oq_urb)) { - msg_t msg = chThdEnqueueTimeoutS(&ftdipp->oq_waiting, timeout); - if (msg < Q_OK) { - chSysUnlock(); - return msg; - } - } - - *ftdipp->oq_ptr++ = b; - if (--ftdipp->oq_counter == 0) { - _submitOutI(ftdipp, 64); - chSchRescheduleS(); - } - chSysUnlock(); - return Q_OK; -} - -static size_t _write(USBHFTDIPortDriver *ftdipp, const uint8_t *bp, size_t n) { - return _write_timeout(ftdipp, bp, n, TIME_INFINITE); -} - -static msg_t _put(USBHFTDIPortDriver *ftdipp, uint8_t b) { - return _put_timeout(ftdipp, b, TIME_INFINITE); -} - -static void _submitInI(USBHFTDIPortDriver *ftdipp) { - udbg("FTDI: Submit IN"); - usbhURBObjectResetI(&ftdipp->iq_urb); - usbhURBSubmitI(&ftdipp->iq_urb); -} - -static void _in_cb(usbh_urb_t *urb) { - USBHFTDIPortDriver *const ftdipp = (USBHFTDIPortDriver *)urb->userData; - switch (urb->status) { - case USBH_URBSTATUS_OK: - if (urb->actualLength < 2) { - uwarnf("FTDI: URB IN actualLength = %d, < 2", urb->actualLength); - } else if (urb->actualLength > 2) { - udbgf("FTDI: URB IN data len=%d, status=%02x %02x", - urb->actualLength - 2, - ((uint8_t *)urb->buff)[0], - ((uint8_t *)urb->buff)[1]); - ftdipp->iq_ptr = ftdipp->iq_buff + 2; - ftdipp->iq_counter = urb->actualLength - 2; - chThdDequeueNextI(&ftdipp->iq_waiting, Q_OK); - return; - } else { - udbgf("FTDI: URB IN no data, status=%02x %02x", - ((uint8_t *)urb->buff)[0], - ((uint8_t *)urb->buff)[1]); - return; - } - break; - case USBH_URBSTATUS_DISCONNECTED: - uwarn("FTDI: URB IN disconnected"); - chThdDequeueNextI(&ftdipp->iq_waiting, Q_RESET); - return; - default: - uerrf("FTDI: URB IN status unexpected = %d", urb->status); - break; - } - _submitInI(ftdipp); -} - -static size_t _read_timeout(USBHFTDIPortDriver *ftdipp, uint8_t *bp, - size_t n, systime_t timeout) { - size_t r = 0; - - chDbgCheck(n > 0U); - - chSysLock(); - while (true) { - if (ftdipp->state != USBHFTDIP_STATE_READY) { - chSysUnlock(); - return r; - } - while (ftdipp->iq_counter == 0) { - if (!usbhURBIsBusy(&ftdipp->iq_urb)) - _submitInI(ftdipp); - if (chThdEnqueueTimeoutS(&ftdipp->iq_waiting, timeout) != Q_OK) { - chSysUnlock(); - return r; - } - } - *bp++ = *ftdipp->iq_ptr++; - if (--ftdipp->iq_counter == 0) { - _submitInI(ftdipp); - chSchRescheduleS(); - } - chSysUnlock(); - - r++; - if (--n == 0U) - return r; - - chSysLock(); - } -} - -static msg_t _get_timeout(USBHFTDIPortDriver *ftdipp, systime_t timeout) { - uint8_t b; - - chSysLock(); - if (ftdipp->state != USBHFTDIP_STATE_READY) { - chSysUnlock(); - return Q_RESET; - } - while (ftdipp->iq_counter == 0) { - if (!usbhURBIsBusy(&ftdipp->iq_urb)) - _submitInI(ftdipp); - msg_t msg = chThdEnqueueTimeoutS(&ftdipp->iq_waiting, timeout); - if (msg < Q_OK) { - chSysUnlock(); - return msg; - } - } - b = *ftdipp->iq_ptr++; - if (--ftdipp->iq_counter == 0) { - _submitInI(ftdipp); - chSchRescheduleS(); - } - chSysUnlock(); - - return (msg_t)b; -} - -static msg_t _get(USBHFTDIPortDriver *ftdipp) { - return _get_timeout(ftdipp, TIME_INFINITE); -} - -static size_t _read(USBHFTDIPortDriver *ftdipp, uint8_t *bp, size_t n) { - return _read_timeout(ftdipp, bp, n, TIME_INFINITE); -} - -static void _vt(void *p) { - USBHFTDIPortDriver *const ftdipp = (USBHFTDIPortDriver *)p; - chSysLockFromISR(); - uint32_t len = ftdipp->oq_ptr - ftdipp->oq_buff; - if (len && !usbhURBIsBusy(&ftdipp->oq_urb)) { - _submitOutI(ftdipp, len); - } - if ((ftdipp->iq_counter == 0) && !usbhURBIsBusy(&ftdipp->iq_urb)) { - _submitInI(ftdipp); - } - chVTSetI(&ftdipp->vt, MS2ST(16), _vt, ftdipp); - chSysUnlockFromISR(); -} - -static const struct FTDIPortDriverVMT async_channel_vmt = { - (size_t (*)(void *, const uint8_t *, size_t))_write, - (size_t (*)(void *, uint8_t *, size_t))_read, - (msg_t (*)(void *, uint8_t))_put, - (msg_t (*)(void *))_get, - (msg_t (*)(void *, uint8_t, systime_t))_put_timeout, - (msg_t (*)(void *, systime_t))_get_timeout, - (size_t (*)(void *, const uint8_t *, size_t, systime_t))_write_timeout, - (size_t (*)(void *, uint8_t *, size_t, systime_t))_read_timeout -}; - - -static void _stop(USBHFTDIPortDriver *ftdipp) { - osalSysLock(); - chVTResetI(&ftdipp->vt); - usbhEPCloseS(&ftdipp->epin); - usbhEPCloseS(&ftdipp->epout); - chThdDequeueAllI(&ftdipp->iq_waiting, Q_RESET); - chThdDequeueAllI(&ftdipp->oq_waiting, Q_RESET); - osalOsRescheduleS(); - ftdipp->state = USBHFTDIP_STATE_ACTIVE; - osalSysUnlock(); -} - -void usbhftdipStop(USBHFTDIPortDriver *ftdipp) { - osalDbgCheck((ftdipp->state == USBHFTDIP_STATE_ACTIVE) - || (ftdipp->state == USBHFTDIP_STATE_READY)); - - if (ftdipp->state == USBHFTDIP_STATE_ACTIVE) { - return; - } - - osalMutexLock(&ftdipp->ftdip->mtx); - _stop(ftdipp); - osalMutexUnlock(&ftdipp->ftdip->mtx); -} - -void usbhftdipStart(USBHFTDIPortDriver *ftdipp, const USBHFTDIPortConfig *config) { - static const USBHFTDIPortConfig default_config = { - HAL_USBHFTDI_DEFAULT_SPEED, - HAL_USBHFTDI_DEFAULT_FRAMING, - HAL_USBHFTDI_DEFAULT_HANDSHAKE, - HAL_USBHFTDI_DEFAULT_XON, - HAL_USBHFTDI_DEFAULT_XOFF - }; - - osalDbgCheck((ftdipp->state == USBHFTDIP_STATE_ACTIVE) - || (ftdipp->state == USBHFTDIP_STATE_READY)); - - if (ftdipp->state == USBHFTDIP_STATE_READY) - return; - - osalMutexLock(&ftdipp->ftdip->mtx); - if (config == NULL) - config = &default_config; - - uint16_t wValue = 0; - _ftdi_port_control(ftdipp, FTDI_COMMAND_RESET, FTDI_RESET_ALL, 0, 0, NULL); - _set_baudrate(ftdipp, config->speed); - _ftdi_port_control(ftdipp, FTDI_COMMAND_SETDATA, config->framing, 0, 0, NULL); - if (config->handshake & USBHFTDI_HANDSHAKE_XON_XOFF) - wValue = (config->xoff_character << 8) | config->xon_character; - _ftdi_port_control(ftdipp, FTDI_COMMAND_SETFLOW, wValue, config->handshake, 0, NULL); - - usbhURBObjectInit(&ftdipp->oq_urb, &ftdipp->epout, _out_cb, ftdipp, ftdipp->oq_buff, 0); - chThdQueueObjectInit(&ftdipp->oq_waiting); - ftdipp->oq_counter = 64; - ftdipp->oq_ptr = ftdipp->oq_buff; - usbhEPOpen(&ftdipp->epout); - - usbhURBObjectInit(&ftdipp->iq_urb, &ftdipp->epin, _in_cb, ftdipp, ftdipp->iq_buff, 64); - chThdQueueObjectInit(&ftdipp->iq_waiting); - ftdipp->iq_counter = 0; - ftdipp->iq_ptr = ftdipp->iq_buff; - usbhEPOpen(&ftdipp->epin); - osalSysLock(); - usbhURBSubmitI(&ftdipp->iq_urb); - osalSysUnlock(); - - chVTObjectInit(&ftdipp->vt); - chVTSet(&ftdipp->vt, MS2ST(16), _vt, ftdipp); - - ftdipp->state = USBHFTDIP_STATE_READY; - osalMutexUnlock(&ftdipp->ftdip->mtx); -} - -void usbhftdiObjectInit(USBHFTDIDriver *ftdip) { - osalDbgCheck(ftdip != NULL); - memset(ftdip, 0, sizeof(*ftdip)); - ftdip->info = &usbhftdiClassDriverInfo; - osalMutexObjectInit(&ftdip->mtx); -} - -void usbhftdipObjectInit(USBHFTDIPortDriver *ftdipp) { - osalDbgCheck(ftdipp != NULL); - memset(ftdipp, 0, sizeof(*ftdipp)); - ftdipp->vmt = &async_channel_vmt; - ftdipp->state = USBHFTDIP_STATE_STOP; -} - -#endif diff --git a/firmware/ChibiOS_16/community/os/hal/src/usbh/hal_usbh_hub.c b/firmware/ChibiOS_16/community/os/hal/src/usbh/hal_usbh_hub.c deleted file mode 100644 index 56257b2bc5..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/src/usbh/hal_usbh_hub.c +++ /dev/null @@ -1,303 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail) - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include -#include "hal.h" -#include "hal_usbh.h" -#include "usbh/internal.h" - -#if HAL_USBH_USE_HUB - -#if !HAL_USE_USBH -#error "USBHHUB needs HAL_USE_USBH" -#endif - -#include -#include "usbh/dev/hub.h" - -#if USBHHUB_DEBUG_ENABLE_TRACE -#define udbgf(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define udbg(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define udbgf(f, ...) do {} while(0) -#define udbg(f, ...) do {} while(0) -#endif - -#if USBHHUB_DEBUG_ENABLE_INFO -#define uinfof(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define uinfo(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define uinfof(f, ...) do {} while(0) -#define uinfo(f, ...) do {} while(0) -#endif - -#if USBHHUB_DEBUG_ENABLE_WARNINGS -#define uwarnf(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define uwarn(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define uwarnf(f, ...) do {} while(0) -#define uwarn(f, ...) do {} while(0) -#endif - -#if USBHHUB_DEBUG_ENABLE_ERRORS -#define uerrf(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define uerr(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define uerrf(f, ...) do {} while(0) -#define uerr(f, ...) do {} while(0) -#endif - - -USBHHubDriver USBHHUBD[HAL_USBHHUB_MAX_INSTANCES]; -usbh_port_t USBHPorts[HAL_USBHHUB_MAX_PORTS]; - -static usbh_baseclassdriver_t *hub_load(usbh_device_t *dev, const uint8_t *descriptor, uint16_t rem); -static void hub_unload(usbh_baseclassdriver_t *drv); -static const usbh_classdriver_vmt_t usbhhubClassDriverVMT = { - hub_load, - hub_unload -}; -const usbh_classdriverinfo_t usbhhubClassDriverInfo = { - 0x09, 0x00, -1, "HUB", &usbhhubClassDriverVMT -}; - - -void _usbhub_port_object_init(usbh_port_t *port, USBHDriver *usbh, - USBHHubDriver *hub, uint8_t number) { - memset(port, 0, sizeof(*port)); - port->number = number; - port->device.host = usbh; - port->hub = hub; -} - -usbh_urbstatus_t usbhhubControlRequest(USBHDriver *host, USBHHubDriver *hub, - uint8_t bmRequestType, - uint8_t bRequest, - uint16_t wValue, - uint16_t wIndex, - uint16_t wLength, - uint8_t *buf) { - if (hub == NULL) - return usbh_lld_root_hub_request(host, bmRequestType, bRequest, wValue, wIndex, wLength, buf); - - return usbhControlRequest(hub->dev, - bmRequestType, bRequest, wValue, wIndex, wLength, buf); -} - - -static void _urb_complete(usbh_urb_t *urb) { - - USBHHubDriver *const hubdp = (USBHHubDriver *)urb->userData; - switch (urb->status) { - case USBH_URBSTATUS_TIMEOUT: - /* the device NAKed */ - udbg("HUB: no info"); - hubdp->statuschange = 0; - break; - case USBH_URBSTATUS_OK: { - uint8_t len = hubdp->hubDesc.bNbrPorts / 8 + 1; - if (urb->actualLength != len) { - uwarnf("Expected %d status change bytes but got %d", len, urb->actualLength); - } - - if (urb->actualLength < len) - len = urb->actualLength; - - if (len > 4) - len = 4; - - uint8_t *sc = (uint8_t *)&hubdp->statuschange; - uint8_t *r = hubdp->scbuff; - while (len--) - *sc++ |= *r++; - - uinfof("HUB: change, %08x", hubdp->statuschange); - } break; - case USBH_URBSTATUS_DISCONNECTED: - uwarn("HUB: URB disconnected, aborting poll"); - return; - default: - uerrf("HUB: URB status unexpected = %d", urb->status); - break; - } - - usbhURBObjectResetI(urb); - usbhURBSubmitI(urb); -} - -static usbh_baseclassdriver_t *hub_load(usbh_device_t *dev, - const uint8_t *descriptor, uint16_t rem) { - int i; - - USBHHubDriver *hubdp; - - if ((rem < descriptor[0]) || (descriptor[1] != USBH_DT_DEVICE)) - return NULL; - - if (dev->devDesc.bDeviceProtocol != 0) - return NULL; - - generic_iterator_t iep, icfg; - if_iterator_t iif; - - cfg_iter_init(&icfg, dev->fullConfigurationDescriptor, - dev->basicConfigDesc.wTotalLength); - - if_iter_init(&iif, &icfg); - if (!iif.valid) - return NULL; - const usbh_interface_descriptor_t *const ifdesc = if_get(&iif); - if ((ifdesc->bInterfaceClass != 0x09) - || (ifdesc->bInterfaceSubClass != 0x00) - || (ifdesc->bInterfaceProtocol != 0x00)) { - return NULL; - } - - ep_iter_init(&iep, &iif); - if (!iep.valid) - return NULL; - const usbh_endpoint_descriptor_t *const epdesc = ep_get(&iep); - if ((epdesc->bmAttributes & 0x03) != USBH_EPTYPE_INT) { - return NULL; - } - - - /* alloc driver */ - for (i = 0; i < HAL_USBHHUB_MAX_INSTANCES; i++) { - if (USBHHUBD[i].dev == NULL) { - hubdp = &USBHHUBD[i]; - goto alloc_ok; - } - } - - uwarn("Can't alloc HUB driver"); - - /* can't alloc */ - return NULL; - -alloc_ok: - /* initialize the driver's variables */ - hubdp->epint.status = USBH_EPSTATUS_UNINITIALIZED; - hubdp->dev = dev; - hubdp->ports = 0; - - usbhEPSetName(&dev->ctrl, "HUB[CTRL]"); - - /* read Hub descriptor */ - uinfo("Read Hub descriptor"); - if (usbhhubControlRequest(dev->host, hubdp, - USBH_REQTYPE_IN | USBH_REQTYPE_CLASS | USBH_REQTYPE_DEVICE, - USBH_REQ_GET_DESCRIPTOR, - (USBH_DT_HUB << 8), 0, sizeof(hubdp->hubDesc), - (uint8_t *)&hubdp->hubDesc) != USBH_URBSTATUS_OK) { - hubdp->dev = NULL; - return NULL; - } - - const usbh_hub_descriptor_t *const hubdesc = &hubdp->hubDesc; - - uinfof("Hub descriptor loaded; %d ports, wHubCharacteristics=%04x, bPwrOn2PwrGood=%d, bHubContrCurrent=%d", - hubdesc->bNbrPorts, - hubdesc->wHubCharacteristics, - hubdesc->bPwrOn2PwrGood, - hubdesc->bHubContrCurrent); - - /* Alloc ports */ - uint8_t ports = hubdesc->bNbrPorts; - for (i = 0; (ports > 0) && (i < HAL_USBHHUB_MAX_PORTS); i++) { - if (USBHPorts[i].hub == NULL) { - uinfof("Alloc port %d", ports); - _usbhub_port_object_init(&USBHPorts[i], dev->host, hubdp, ports); - USBHPorts[i].next = hubdp->ports; - hubdp->ports = &USBHPorts[i]; - --ports; - } - } - - if (ports) { - uwarn("Could not alloc all ports"); - } - - /* link hub to the host's list */ - list_add_tail(&hubdp->node, &dev->host->hubs); - - /* enable power to ports */ - usbh_port_t *port = hubdp->ports; - while (port) { - uinfof("Enable power for port %d", port->number); - usbhhubSetFeaturePort(port, USBH_PORT_FEAT_POWER); - port = port->next; - } - - if (hubdesc->bPwrOn2PwrGood) - osalThreadSleepMilliseconds(2 * hubdesc->bPwrOn2PwrGood); - - /* initialize the status change endpoint and trigger the first transfer */ - usbhEPObjectInit(&hubdp->epint, dev, epdesc); - usbhEPSetName(&hubdp->epint, "HUB[INT ]"); - usbhEPOpen(&hubdp->epint); - - usbhURBObjectInit(&hubdp->urb, &hubdp->epint, - _urb_complete, hubdp, hubdp->scbuff, - (hubdesc->bNbrPorts + 8) / 8); - - osalSysLock(); - usbhURBSubmitI(&hubdp->urb); - osalOsRescheduleS(); - osalSysUnlock(); - - return (usbh_baseclassdriver_t *)hubdp; -} - -static void hub_unload(usbh_baseclassdriver_t *drv) { - osalDbgCheck(drv != NULL); - USBHHubDriver *const hubdp = (USBHHubDriver *)drv; - - /* close the status change endpoint (this cancels ongoing URBs) */ - osalSysLock(); - usbhEPCloseS(&hubdp->epint); - osalSysUnlock(); - - /* de-alloc ports and unload drivers */ - usbh_port_t *port = hubdp->ports; - while (port) { - _usbh_port_disconnected(port); - port->hub = NULL; - port = port->next; - } - - /* unlink the hub from the host's list */ - list_del(&hubdp->node); - -} - -void usbhhubObjectInit(USBHHubDriver *hubdp) { - osalDbgCheck(hubdp != NULL); - memset(hubdp, 0, sizeof(*hubdp)); - hubdp->info = &usbhhubClassDriverInfo; -} -#else - -#if HAL_USE_USBH -void _usbhub_port_object_init(usbh_port_t *port, USBHDriver *usbh, uint8_t number) { - memset(port, 0, sizeof(*port)); - port->number = number; - port->device.host = usbh; -} -#endif - -#endif diff --git a/firmware/ChibiOS_16/community/os/hal/src/usbh/hal_usbh_msd.c b/firmware/ChibiOS_16/community/os/hal/src/usbh/hal_usbh_msd.c deleted file mode 100644 index 7a4f826909..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/src/usbh/hal_usbh_msd.c +++ /dev/null @@ -1,939 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail) - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include "hal.h" -#include "hal_usbh.h" - -#if HAL_USBH_USE_MSD - -#if !HAL_USE_USBH -#error "USBHMSD needs USBH" -#endif - -#include -#include "usbh/dev/msd.h" -#include "usbh/internal.h" - -//#pragma GCC optimize("Og") - - -#if USBHMSD_DEBUG_ENABLE_TRACE -#define udbgf(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define udbg(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define udbgf(f, ...) do {} while(0) -#define udbg(f, ...) do {} while(0) -#endif - -#if USBHMSD_DEBUG_ENABLE_INFO -#define uinfof(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define uinfo(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define uinfof(f, ...) do {} while(0) -#define uinfo(f, ...) do {} while(0) -#endif - -#if USBHMSD_DEBUG_ENABLE_WARNINGS -#define uwarnf(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define uwarn(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define uwarnf(f, ...) do {} while(0) -#define uwarn(f, ...) do {} while(0) -#endif - -#if USBHMSD_DEBUG_ENABLE_ERRORS -#define uerrf(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define uerr(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define uerrf(f, ...) do {} while(0) -#define uerr(f, ...) do {} while(0) -#endif - - - - - -/*===========================================================================*/ -/* USB Class driver loader for MSD */ -/*===========================================================================*/ - -USBHMassStorageDriver USBHMSD[HAL_USBHMSD_MAX_INSTANCES]; - -static usbh_baseclassdriver_t *_msd_load(usbh_device_t *dev, const uint8_t *descriptor, uint16_t rem); -static void _msd_unload(usbh_baseclassdriver_t *drv); - -static const usbh_classdriver_vmt_t class_driver_vmt = { - _msd_load, - _msd_unload -}; - -const usbh_classdriverinfo_t usbhmsdClassDriverInfo = { - 0x08, 0x06, 0x50, "MSD", &class_driver_vmt -}; - -#define MSD_REQ_RESET 0xFF -#define MSD_GET_MAX_LUN 0xFE - -static usbh_baseclassdriver_t *_msd_load(usbh_device_t *dev, const uint8_t *descriptor, uint16_t rem) { - int i; - USBHMassStorageDriver *msdp; - uint8_t luns; // should declare it here to eliminate 'control bypass initialization' warning - usbh_urbstatus_t stat; // should declare it here to eliminate 'control bypass initialization' warning - - if ((rem < descriptor[0]) || (descriptor[1] != USBH_DT_INTERFACE)) - return NULL; - - const usbh_interface_descriptor_t * const ifdesc = (const usbh_interface_descriptor_t *)descriptor; - - if ((ifdesc->bAlternateSetting != 0) - || (ifdesc->bNumEndpoints < 2) - || (ifdesc->bInterfaceSubClass != 0x06) - || (ifdesc->bInterfaceProtocol != 0x50)) { - return NULL; - } - - /* alloc driver */ - for (i = 0; i < HAL_USBHMSD_MAX_INSTANCES; i++) { - if (USBHMSD[i].dev == NULL) { - msdp = &USBHMSD[i]; - goto alloc_ok; - } - } - - uwarn("Can't alloc MSD driver"); - - /* can't alloc */ - return NULL; - -alloc_ok: - /* initialize the driver's variables */ - msdp->epin.status = USBH_EPSTATUS_UNINITIALIZED; - msdp->epout.status = USBH_EPSTATUS_UNINITIALIZED; - msdp->max_lun = 0; - msdp->tag = 0; - msdp->luns = 0; - msdp->ifnum = ifdesc->bInterfaceNumber; - usbhEPSetName(&dev->ctrl, "MSD[CTRL]"); - - /* parse the configuration descriptor */ - if_iterator_t iif; - generic_iterator_t iep; - iif.iad = 0; - iif.curr = descriptor; - iif.rem = rem; - for (ep_iter_init(&iep, &iif); iep.valid; ep_iter_next(&iep)) { - const usbh_endpoint_descriptor_t *const epdesc = ep_get(&iep); - if ((epdesc->bEndpointAddress & 0x80) && (epdesc->bmAttributes == USBH_EPTYPE_BULK)) { - uinfof("BULK IN endpoint found: bEndpointAddress=%02x", epdesc->bEndpointAddress); - usbhEPObjectInit(&msdp->epin, dev, epdesc); - usbhEPSetName(&msdp->epin, "MSD[BIN ]"); - } else if (((epdesc->bEndpointAddress & 0x80) == 0) - && (epdesc->bmAttributes == USBH_EPTYPE_BULK)) { - uinfof("BULK OUT endpoint found: bEndpointAddress=%02x", epdesc->bEndpointAddress); - usbhEPObjectInit(&msdp->epout, dev, epdesc); - usbhEPSetName(&msdp->epout, "MSD[BOUT]"); - } else { - uinfof("unsupported endpoint found: bEndpointAddress=%02x, bmAttributes=%02x", - epdesc->bEndpointAddress, epdesc->bmAttributes); - } - } - if ((msdp->epin.status != USBH_EPSTATUS_CLOSED) || (msdp->epout.status != USBH_EPSTATUS_CLOSED)) { - goto deinit; - } - - /* read the number of LUNs */ - uinfo("Reading Max LUN:"); - USBH_DEFINE_BUFFER(uint8_t, buff[4]); - stat = usbhControlRequest(dev, - USBH_CLASSIN(USBH_REQTYPE_INTERFACE, MSD_GET_MAX_LUN, 0, msdp->ifnum), - 1, buff); - if (stat == USBH_URBSTATUS_OK) { - msdp->max_lun = buff[0] + 1; - uinfof("\tmax_lun = %d", msdp->max_lun); - if (msdp->max_lun > HAL_USBHMSD_MAX_LUNS) { - msdp->max_lun = HAL_USBHMSD_MAX_LUNS; - uwarnf("\tUsing max_lun = %d", msdp->max_lun); - } - } else if (stat == USBH_URBSTATUS_STALL) { - uwarn("\tStall, max_lun = 1"); - msdp->max_lun = 1; - } else { - uerr("\tError"); - goto deinit; - } - - /* open the bulk IN/OUT endpoints */ - usbhEPOpen(&msdp->epin); - usbhEPOpen(&msdp->epout); - - /* Alloc one block device per logical unit found */ - luns = msdp->max_lun; - for (i = 0; (luns > 0) && (i < HAL_USBHMSD_MAX_LUNS); i++) { - if (MSBLKD[i].msdp == NULL) { - /* link the new block driver to the list */ - MSBLKD[i].next = msdp->luns; - msdp->luns = &MSBLKD[i]; - MSBLKD[i].msdp = msdp; - - osalSysLock(); - MSBLKD[i].state = BLK_ACTIVE; /* transition directly to active, instead of BLK_STOP */ - osalSysUnlock(); - - /* connect the LUN (TODO: review if it's best to leave the LUN disconnected) */ - usbhmsdLUNConnect(&MSBLKD[i]); - luns--; - } - } - - return (usbh_baseclassdriver_t *)msdp; - -deinit: - /* Here, the enpoints are closed, and the driver is unlinked */ - return NULL; -} - -static void _msd_unload(usbh_baseclassdriver_t *drv) { - osalDbgCheck(drv != NULL); - USBHMassStorageDriver *const msdp = (USBHMassStorageDriver *)drv; - USBHMassStorageLUNDriver *lunp = msdp->luns; - - osalMutexLock(&msdp->mtx); - osalSysLock(); - usbhEPCloseS(&msdp->epin); - usbhEPCloseS(&msdp->epout); - while (lunp) { - lunp->state = BLK_STOP; - lunp = lunp->next; - } - osalSysUnlock(); - osalMutexUnlock(&msdp->mtx); - - /* now that the LUNs are idle, deinit them */ - lunp = msdp->luns; - osalSysLock(); - while (lunp) { - usbhmsdLUNObjectInit(lunp); - lunp = lunp->next; - } - osalSysUnlock(); -} - - -/*===========================================================================*/ -/* MSD Class driver operations (Bulk-Only transport) */ -/*===========================================================================*/ - - - -/* USB Bulk Only Transport SCSI Command block wrapper */ -PACKED_STRUCT { - uint32_t dCBWSignature; - uint32_t dCBWTag; - uint32_t dCBWDataTransferLength; - uint8_t bmCBWFlags; - uint8_t bCBWLUN; - uint8_t bCBWCBLength; - uint8_t CBWCB[16]; -} msd_cbw_t; -#define MSD_CBW_SIGNATURE 0x43425355 -#define MSD_CBWFLAGS_D2H 0x80 -#define MSD_CBWFLAGS_H2D 0x00 - - -/* USB Bulk Only Transport SCSI Command status wrapper */ -PACKED_STRUCT { - uint32_t dCSWSignature; - uint32_t dCSWTag; - uint32_t dCSWDataResidue; - uint8_t bCSWStatus; -} msd_csw_t; -#define MSD_CSW_SIGNATURE 0x53425355 - - -typedef union { - msd_cbw_t cbw; - msd_csw_t csw; -} msd_transaction_t; - -typedef enum { - MSD_TRANSACTIONRESULT_OK, - MSD_TRANSACTIONRESULT_DISCONNECTED, - MSD_TRANSACTIONRESULT_STALL, - MSD_TRANSACTIONRESULT_BUS_ERROR, - MSD_TRANSACTIONRESULT_SYNC_ERROR -} msd_transaction_result_t; - -typedef enum { - MSD_COMMANDRESULT_PASSED = 0, - MSD_COMMANDRESULT_FAILED = 1, - MSD_COMMANDRESULT_PHASE_ERROR = 2 -} msd_command_result_t; - -typedef struct { - msd_transaction_result_t tres; - msd_command_result_t cres; -} msd_result_t; - - -/* ----------------------------------------------------- */ -/* SCSI Commands */ -/* ----------------------------------------------------- */ - -/* Read 10 and Write 10 */ -#define SCSI_CMD_READ_10 0x28 -#define SCSI_CMD_WRITE_10 0x2A - -/* Request sense */ -#define SCSI_CMD_REQUEST_SENSE 0x03 -PACKED_STRUCT { - uint8_t byte[18]; -} scsi_sense_response_t; - -#define SCSI_SENSE_KEY_GOOD 0x00 -#define SCSI_SENSE_KEY_RECOVERED_ERROR 0x01 -#define SCSI_SENSE_KEY_NOT_READY 0x02 -#define SCSI_SENSE_KEY_MEDIUM_ERROR 0x03 -#define SCSI_SENSE_KEY_HARDWARE_ERROR 0x04 -#define SCSI_SENSE_KEY_ILLEGAL_REQUEST 0x05 -#define SCSI_SENSE_KEY_UNIT_ATTENTION 0x06 -#define SCSI_SENSE_KEY_DATA_PROTECT 0x07 -#define SCSI_SENSE_KEY_BLANK_CHECK 0x08 -#define SCSI_SENSE_KEY_VENDOR_SPECIFIC 0x09 -#define SCSI_SENSE_KEY_COPY_ABORTED 0x0A -#define SCSI_SENSE_KEY_ABORTED_COMMAND 0x0B -#define SCSI_SENSE_KEY_VOLUME_OVERFLOW 0x0D -#define SCSI_SENSE_KEY_MISCOMPARE 0x0E -#define SCSI_ASENSE_NO_ADDITIONAL_INFORMATION 0x00 -#define SCSI_ASENSE_LOGICAL_UNIT_NOT_READY 0x04 -#define SCSI_ASENSE_INVALID_FIELD_IN_CDB 0x24 -#define SCSI_ASENSE_NOT_READY_TO_READY_CHANGE 0x28 -#define SCSI_ASENSE_WRITE_PROTECTED 0x27 -#define SCSI_ASENSE_FORMAT_ERROR 0x31 -#define SCSI_ASENSE_INVALID_COMMAND 0x20 -#define SCSI_ASENSE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE 0x21 -#define SCSI_ASENSE_MEDIUM_NOT_PRESENT 0x3A -#define SCSI_ASENSEQ_NO_QUALIFIER 0x00 -#define SCSI_ASENSEQ_FORMAT_COMMAND_FAILED 0x01 -#define SCSI_ASENSEQ_INITIALIZING_COMMAND_REQUIRED 0x02 -#define SCSI_ASENSEQ_OPERATION_IN_PROGRESS 0x07 - -/* Inquiry */ -#define SCSI_CMD_INQUIRY 0x12 -PACKED_STRUCT { - uint8_t peripheral; - uint8_t removable; - uint8_t version; - uint8_t response_data_format; - uint8_t additional_length; - uint8_t sccstp; - uint8_t bqueetc; - uint8_t cmdque; - uint8_t vendorID[8]; - uint8_t productID[16]; - uint8_t productRev[4]; -} scsi_inquiry_response_t; - -/* Read Capacity 10 */ -#define SCSI_CMD_READ_CAPACITY_10 0x25 -PACKED_STRUCT { - uint32_t last_block_addr; - uint32_t block_size; -} scsi_readcapacity10_response_t; - -/* Start/Stop Unit */ -#define SCSI_CMD_START_STOP_UNIT 0x1B -PACKED_STRUCT { - uint8_t op_code; - uint8_t lun_immed; - uint8_t res1; - uint8_t res2; - uint8_t loej_start; - uint8_t control; -} scsi_startstopunit_request_t; - -/* test unit ready */ -#define SCSI_CMD_TEST_UNIT_READY 0x00 - -/* Other commands, TODO: use or remove them -#define SCSI_CMD_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1E -#define SCSI_CMD_VERIFY_10 0x2F -#define SCSI_CMD_SEND_DIAGNOSTIC 0x1D -#define SCSI_CMD_MODE_SENSE_6 0x1A -*/ - -static inline void _prepare_cbw(msd_transaction_t *tran, USBHMassStorageLUNDriver *lunp) { - tran->cbw.bCBWLUN = (uint8_t)(lunp - &lunp->msdp->luns[0]); - memset(&tran->cbw.CBWCB, 0, sizeof(tran->cbw.CBWCB)); -} - -static msd_transaction_result_t _msd_transaction(msd_transaction_t *tran, USBHMassStorageLUNDriver *lunp, void *data) { - - uint32_t actual_len; - usbh_urbstatus_t status; - - tran->cbw.dCBWSignature = MSD_CBW_SIGNATURE; - tran->cbw.dCBWTag = ++lunp->msdp->tag; - - /* control phase */ - status = usbhBulkTransfer(&lunp->msdp->epout, &tran->cbw, - sizeof(tran->cbw), &actual_len, MS2ST(1000)); - - if (status == USBH_URBSTATUS_CANCELLED) { - uerr("\tMSD: Control phase: USBH_URBSTATUS_CANCELLED"); - return MSD_TRANSACTIONRESULT_DISCONNECTED; - } else if (status == USBH_URBSTATUS_STALL) { - uerr("\tMSD: Control phase: USBH_URBSTATUS_STALL"); - return MSD_TRANSACTIONRESULT_STALL; - } else if (status != USBH_URBSTATUS_OK) { - uerrf("\tMSD: Control phase: status = %d, != OK", status); - return MSD_TRANSACTIONRESULT_BUS_ERROR; - } else if (actual_len != sizeof(tran->cbw)) { - uerrf("\tMSD: Control phase: wrong actual_len = %d", actual_len); - return MSD_TRANSACTIONRESULT_BUS_ERROR; - } - - - /* data phase */ - if (tran->cbw.dCBWDataTransferLength) { - status = usbhBulkTransfer( - tran->cbw.bmCBWFlags & MSD_CBWFLAGS_D2H ? &lunp->msdp->epin : &lunp->msdp->epout, - data, - tran->cbw.dCBWDataTransferLength, - &actual_len, MS2ST(20000)); - - if (status == USBH_URBSTATUS_CANCELLED) { - uerr("\tMSD: Data phase: USBH_URBSTATUS_CANCELLED"); - return MSD_TRANSACTIONRESULT_DISCONNECTED; - } else if (status == USBH_URBSTATUS_STALL) { - uerr("\tMSD: Data phase: USBH_URBSTATUS_STALL"); - return MSD_TRANSACTIONRESULT_STALL; - } else if (status != USBH_URBSTATUS_OK) { - uerrf("\tMSD: Data phase: status = %d, != OK", status); - return MSD_TRANSACTIONRESULT_BUS_ERROR; - } else if (actual_len != tran->cbw.dCBWDataTransferLength) { - uerrf("\tMSD: Data phase: wrong actual_len = %d", actual_len); - return MSD_TRANSACTIONRESULT_BUS_ERROR; - } - } - - - /* status phase */ - status = usbhBulkTransfer(&lunp->msdp->epin, &tran->csw, - sizeof(tran->csw), &actual_len, MS2ST(1000)); - - if (status == USBH_URBSTATUS_CANCELLED) { - uerr("\tMSD: Status phase: USBH_URBSTATUS_CANCELLED"); - return MSD_TRANSACTIONRESULT_DISCONNECTED; - } else if (status == USBH_URBSTATUS_STALL) { - uerr("\tMSD: Status phase: USBH_URBSTATUS_STALL"); - return MSD_TRANSACTIONRESULT_STALL; - } else if (status != USBH_URBSTATUS_OK) { - uerrf("\tMSD: Status phase: status = %d, != OK", status); - return MSD_TRANSACTIONRESULT_BUS_ERROR; - } else if (actual_len != sizeof(tran->csw)) { - uerrf("\tMSD: Status phase: wrong actual_len = %d", actual_len); - return MSD_TRANSACTIONRESULT_BUS_ERROR; - } else if (tran->csw.dCSWSignature != MSD_CSW_SIGNATURE) { - uerr("\tMSD: Status phase: wrong signature"); - return MSD_TRANSACTIONRESULT_BUS_ERROR; - } else if (tran->csw.dCSWTag != lunp->msdp->tag) { - uerrf("\tMSD: Status phase: wrong tag (expected %d, got %d)", - lunp->msdp->tag, tran->csw.dCSWTag); - return MSD_TRANSACTIONRESULT_SYNC_ERROR; - } - - if (tran->csw.dCSWDataResidue) { - uwarnf("\tMSD: Residue=%d", tran->csw.dCSWDataResidue); - } - - return MSD_TRANSACTIONRESULT_OK; -} - - -static msd_result_t scsi_inquiry(USBHMassStorageLUNDriver *lunp, scsi_inquiry_response_t *resp) { - msd_transaction_t transaction; - msd_result_t res; - - _prepare_cbw(&transaction, lunp); - transaction.cbw.dCBWDataTransferLength = sizeof(scsi_inquiry_response_t); - transaction.cbw.bmCBWFlags = MSD_CBWFLAGS_D2H; - transaction.cbw.bCBWCBLength = 6; - transaction.cbw.CBWCB[0] = SCSI_CMD_INQUIRY; - transaction.cbw.CBWCB[4] = sizeof(scsi_inquiry_response_t); - - res.tres = _msd_transaction(&transaction, lunp, resp); - if (res.tres == MSD_TRANSACTIONRESULT_OK) { - res.cres = (msd_command_result_t) transaction.csw.bCSWStatus; - } - return res; -} - -static msd_result_t scsi_requestsense(USBHMassStorageLUNDriver *lunp, scsi_sense_response_t *resp) { - msd_transaction_t transaction; - msd_result_t res; - - _prepare_cbw(&transaction, lunp); - transaction.cbw.dCBWDataTransferLength = sizeof(scsi_sense_response_t); - transaction.cbw.bmCBWFlags = MSD_CBWFLAGS_D2H; - transaction.cbw.bCBWCBLength = 12; - transaction.cbw.CBWCB[0] = SCSI_CMD_REQUEST_SENSE; - transaction.cbw.CBWCB[4] = sizeof(scsi_sense_response_t); - - res.tres = _msd_transaction(&transaction, lunp, resp); - if (res.tres == MSD_TRANSACTIONRESULT_OK) { - res.cres = (msd_command_result_t) transaction.csw.bCSWStatus; - } - return res; -} - -static msd_result_t scsi_testunitready(USBHMassStorageLUNDriver *lunp) { - msd_transaction_t transaction; - msd_result_t res; - - _prepare_cbw(&transaction, lunp); - transaction.cbw.dCBWDataTransferLength = 0; - transaction.cbw.bmCBWFlags = MSD_CBWFLAGS_D2H; - transaction.cbw.bCBWCBLength = 6; - transaction.cbw.CBWCB[0] = SCSI_CMD_TEST_UNIT_READY; - - res.tres = _msd_transaction(&transaction, lunp, NULL); - if (res.tres == MSD_TRANSACTIONRESULT_OK) { - res.cres = (msd_command_result_t) transaction.csw.bCSWStatus; - } - return res; -} - -static msd_result_t scsi_readcapacity10(USBHMassStorageLUNDriver *lunp, scsi_readcapacity10_response_t *resp) { - msd_transaction_t transaction; - msd_result_t res; - - _prepare_cbw(&transaction, lunp); - transaction.cbw.dCBWDataTransferLength = sizeof(scsi_readcapacity10_response_t); - transaction.cbw.bmCBWFlags = MSD_CBWFLAGS_D2H; - transaction.cbw.bCBWCBLength = 12; - transaction.cbw.CBWCB[0] = SCSI_CMD_READ_CAPACITY_10; - - res.tres = _msd_transaction(&transaction, lunp, resp); - if (res.tres == MSD_TRANSACTIONRESULT_OK) { - res.cres = (msd_command_result_t) transaction.csw.bCSWStatus; - } - return res; -} - - -static msd_result_t scsi_read10(USBHMassStorageLUNDriver *lunp, uint32_t lba, uint16_t n, uint8_t *data) { - msd_transaction_t transaction; - msd_result_t res; - - _prepare_cbw(&transaction, lunp); - transaction.cbw.dCBWDataTransferLength = n * lunp->info.blk_size; - transaction.cbw.bmCBWFlags = MSD_CBWFLAGS_D2H; - transaction.cbw.bCBWCBLength = 10; - transaction.cbw.CBWCB[0] = SCSI_CMD_READ_10; - transaction.cbw.CBWCB[2] = (uint8_t)(lba >> 24); - transaction.cbw.CBWCB[3] = (uint8_t)(lba >> 16); - transaction.cbw.CBWCB[4] = (uint8_t)(lba >> 8); - transaction.cbw.CBWCB[5] = (uint8_t)(lba); - transaction.cbw.CBWCB[7] = (uint8_t)(n >> 8); - transaction.cbw.CBWCB[8] = (uint8_t)(n); - - res.tres = _msd_transaction(&transaction, lunp, data); - if (res.tres == MSD_TRANSACTIONRESULT_OK) { - res.cres = (msd_command_result_t) transaction.csw.bCSWStatus; - } - return res; -} - -static msd_result_t scsi_write10(USBHMassStorageLUNDriver *lunp, uint32_t lba, uint16_t n, const uint8_t *data) { - msd_transaction_t transaction; - msd_result_t res; - - _prepare_cbw(&transaction, lunp); - transaction.cbw.dCBWDataTransferLength = n * lunp->info.blk_size; - transaction.cbw.bmCBWFlags = MSD_CBWFLAGS_H2D; - transaction.cbw.bCBWCBLength = 10; - transaction.cbw.CBWCB[0] = SCSI_CMD_WRITE_10; - transaction.cbw.CBWCB[2] = (uint8_t)(lba >> 24); - transaction.cbw.CBWCB[3] = (uint8_t)(lba >> 16); - transaction.cbw.CBWCB[4] = (uint8_t)(lba >> 8); - transaction.cbw.CBWCB[5] = (uint8_t)(lba); - transaction.cbw.CBWCB[7] = (uint8_t)(n >> 8); - transaction.cbw.CBWCB[8] = (uint8_t)(n); - - res.tres = _msd_transaction(&transaction, lunp, (uint8_t *)data); - if (res.tres == MSD_TRANSACTIONRESULT_OK) { - res.cres = (msd_command_result_t) transaction.csw.bCSWStatus; - } - return res; -} - - - -/*===========================================================================*/ -/* Block driver data/functions */ -/*===========================================================================*/ - -USBHMassStorageLUNDriver MSBLKD[HAL_USBHMSD_MAX_LUNS]; - -static const struct USBHMassStorageDriverVMT blk_vmt = { - (bool (*)(void *))usbhmsdLUNIsInserted, - (bool (*)(void *))usbhmsdLUNIsProtected, - (bool (*)(void *))usbhmsdLUNConnect, - (bool (*)(void *))usbhmsdLUNDisconnect, - (bool (*)(void *, uint32_t, uint8_t *, uint32_t))usbhmsdLUNRead, - (bool (*)(void *, uint32_t, const uint8_t *, uint32_t))usbhmsdLUNWrite, - (bool (*)(void *))usbhmsdLUNSync, - (bool (*)(void *, BlockDeviceInfo *))usbhmsdLUNGetInfo -}; - - - -static uint32_t _requestsense(USBHMassStorageLUNDriver *lunp) { - scsi_sense_response_t sense; - msd_result_t res; - - res = scsi_requestsense(lunp, &sense); - if (res.tres != MSD_TRANSACTIONRESULT_OK) { - uerr("\tREQUEST SENSE: Transaction error"); - goto failed; - } else if (res.cres == MSD_COMMANDRESULT_FAILED) { - uerr("\tREQUEST SENSE: Command Failed"); - goto failed; - } else if (res.cres == MSD_COMMANDRESULT_PHASE_ERROR) { - //TODO: Do reset, etc. - uerr("\tREQUEST SENSE: Command Phase Error"); - goto failed; - } - - uerrf("\tREQUEST SENSE: Sense key=%x, ASC=%02x, ASCQ=%02x", - sense.byte[2] & 0xf, sense.byte[12], sense.byte[13]); - - return (sense.byte[2] & 0xf) | (sense.byte[12] << 8) | (sense.byte[13] << 16); - -failed: - return 0xffffffff; -} - -void usbhmsdLUNObjectInit(USBHMassStorageLUNDriver *lunp) { - osalDbgCheck(lunp != NULL); - memset(lunp, 0, sizeof(*lunp)); - lunp->vmt = &blk_vmt; - lunp->state = BLK_STOP; - /* Unnecessary because of the memset: - lunp->msdp = NULL; - lunp->next = NULL; - lunp->info.* = 0; - */ -} - -void usbhmsdLUNStart(USBHMassStorageLUNDriver *lunp) { - osalDbgCheck(lunp != NULL); - osalSysLock(); - osalDbgAssert((lunp->state == BLK_STOP) || (lunp->state == BLK_ACTIVE), - "invalid state"); - //TODO: complete - //lunp->state = BLK_ACTIVE; - osalSysUnlock(); -} - -void usbhmsdLUNStop(USBHMassStorageLUNDriver *lunp) { - osalDbgCheck(lunp != NULL); - osalSysLock(); - osalDbgAssert((lunp->state == BLK_STOP) || (lunp->state == BLK_ACTIVE), - "invalid state"); - //TODO: complete - //lunp->state = BLK_STOP; - osalSysUnlock(); -} - -bool usbhmsdLUNConnect(USBHMassStorageLUNDriver *lunp) { - USBHMassStorageDriver *const msdp = lunp->msdp; - msd_result_t res; - - osalDbgCheck(msdp != NULL); - osalSysLock(); - //osalDbgAssert((lunp->state == BLK_ACTIVE) || (lunp->state == BLK_READY), - // "invalid state"); - if (lunp->state == BLK_READY) { - osalSysUnlock(); - return HAL_SUCCESS; - } else if (lunp->state != BLK_ACTIVE) { - osalSysUnlock(); - return HAL_FAILED; - } - lunp->state = BLK_CONNECTING; - osalSysUnlock(); - - osalMutexLock(&msdp->mtx); - - USBH_DEFINE_BUFFER(union { - scsi_inquiry_response_t inq; - scsi_readcapacity10_response_t cap; }, u); - - uinfo("INQUIRY..."); - res = scsi_inquiry(lunp, &u.inq); - if (res.tres != MSD_TRANSACTIONRESULT_OK) { - uerr("\tINQUIRY: Transaction error"); - goto failed; - } else if (res.cres == MSD_COMMANDRESULT_FAILED) { - uerr("\tINQUIRY: Command Failed"); - _requestsense(lunp); - goto failed; - } else if (res.cres == MSD_COMMANDRESULT_PHASE_ERROR) { - //TODO: Do reset, etc. - uerr("\tINQUIRY: Command Phase Error"); - goto failed; - } - - uinfof("\tPDT=%02x", u.inq.peripheral & 0x1f); - if (u.inq.peripheral != 0) { - uerr("\tUnsupported PDT"); - goto failed; - } - - // Test if unit ready - uint8_t i; - for (i = 0; i < 10; i++) { - uinfo("TEST UNIT READY..."); - res = scsi_testunitready(lunp); - if (res.tres != MSD_TRANSACTIONRESULT_OK) { - uerr("\tTEST UNIT READY: Transaction error"); - goto failed; - } else if (res.cres == MSD_COMMANDRESULT_FAILED) { - uerr("\tTEST UNIT READY: Command Failed"); - _requestsense(lunp); - continue; - } else if (res.cres == MSD_COMMANDRESULT_PHASE_ERROR) { - //TODO: Do reset, etc. - uerr("\tTEST UNIT READY: Command Phase Error"); - goto failed; - } - uinfo("\tReady."); - break; - // osalThreadSleepMilliseconds(200); // will raise 'code is unreachable' warning - } - if (i == 10) goto failed; - - // Read capacity - uinfo("READ CAPACITY(10)..."); - res = scsi_readcapacity10(lunp, &u.cap); - if (res.tres != MSD_TRANSACTIONRESULT_OK) { - uerr("\tREAD CAPACITY(10): Transaction error"); - goto failed; - } else if (res.cres == MSD_COMMANDRESULT_FAILED) { - uerr("\tREAD CAPACITY(10): Command Failed"); - _requestsense(lunp); - goto failed; - } else if (res.cres == MSD_COMMANDRESULT_PHASE_ERROR) { - //TODO: Do reset, etc. - uerr("\tREAD CAPACITY(10): Command Phase Error"); - goto failed; - } - lunp->info.blk_size = __REV(u.cap.block_size); - lunp->info.blk_num = __REV(u.cap.last_block_addr) + 1; - uinfof("\tBlock size=%dbytes, blocks=%u (~%u MB)", lunp->info.blk_size, lunp->info.blk_num, - (uint32_t)(((uint64_t)lunp->info.blk_size * lunp->info.blk_num) / (1024UL * 1024UL))); - - uinfo("MSD Connected."); - - osalMutexUnlock(&msdp->mtx); - osalSysLock(); - lunp->state = BLK_READY; - osalSysUnlock(); - - return HAL_SUCCESS; - - /* Connection failed, state reset to BLK_ACTIVE.*/ -failed: - osalMutexUnlock(&msdp->mtx); - osalSysLock(); - lunp->state = BLK_ACTIVE; - osalSysUnlock(); - return HAL_FAILED; -} - - -bool usbhmsdLUNDisconnect(USBHMassStorageLUNDriver *lunp) { - osalDbgCheck(lunp != NULL); - osalSysLock(); - osalDbgAssert((lunp->state == BLK_ACTIVE) || (lunp->state == BLK_READY), - "invalid state"); - if (lunp->state == BLK_ACTIVE) { - osalSysUnlock(); - return HAL_SUCCESS; - } - lunp->state = BLK_DISCONNECTING; - osalSysUnlock(); - - //TODO: complete - - osalSysLock(); - lunp->state = BLK_ACTIVE; - osalSysUnlock(); - return HAL_SUCCESS; -} - -bool usbhmsdLUNRead(USBHMassStorageLUNDriver *lunp, uint32_t startblk, - uint8_t *buffer, uint32_t n) { - - osalDbgCheck(lunp != NULL); - bool ret = HAL_FAILED; - uint16_t blocks; - msd_result_t res; - - osalSysLock(); - if (lunp->state != BLK_READY) { - osalSysUnlock(); - return ret; - } - lunp->state = BLK_READING; - osalSysUnlock(); - - osalMutexLock(&lunp->msdp->mtx); - while (n) { - if (n > 0xffff) { - blocks = 0xffff; - } else { - blocks = (uint16_t)n; - } - res = scsi_read10(lunp, startblk, blocks, buffer); - if (res.tres != MSD_TRANSACTIONRESULT_OK) { - uerr("\tREAD (10): Transaction error"); - goto exit; - } else if (res.cres == MSD_COMMANDRESULT_FAILED) { - //TODO: request sense, and act appropriately - uerr("\tREAD (10): Command Failed"); - _requestsense(lunp); - goto exit; - } else if (res.cres == MSD_COMMANDRESULT_PHASE_ERROR) { - //TODO: Do reset, etc. - uerr("\tREAD (10): Command Phase Error"); - goto exit; - } - n -= blocks; - startblk += blocks; - buffer += blocks * lunp->info.blk_size; - } - - ret = HAL_SUCCESS; - -exit: - osalMutexUnlock(&lunp->msdp->mtx); - osalSysLock(); - if (lunp->state == BLK_READING) { - lunp->state = BLK_READY; - } else { - osalDbgCheck(lunp->state == BLK_STOP); - uwarn("MSD: State = BLK_STOP"); - } - osalSysUnlock(); - return ret; -} - -bool usbhmsdLUNWrite(USBHMassStorageLUNDriver *lunp, uint32_t startblk, - const uint8_t *buffer, uint32_t n) { - - osalDbgCheck(lunp != NULL); - bool ret = HAL_FAILED; - uint16_t blocks; - msd_result_t res; - - osalSysLock(); - if (lunp->state != BLK_READY) { - osalSysUnlock(); - return ret; - } - lunp->state = BLK_WRITING; - osalSysUnlock(); - - osalMutexLock(&lunp->msdp->mtx); - while (n) { - if (n > 0xffff) { - blocks = 0xffff; - } else { - blocks = (uint16_t)n; - } - res = scsi_write10(lunp, startblk, blocks, buffer); - if (res.tres != MSD_TRANSACTIONRESULT_OK) { - uerr("\tWRITE (10): Transaction error"); - goto exit; - } else if (res.cres == MSD_COMMANDRESULT_FAILED) { - //TODO: request sense, and act appropriately - uerr("\tWRITE (10): Command Failed"); - _requestsense(lunp); - goto exit; - } else if (res.cres == MSD_COMMANDRESULT_PHASE_ERROR) { - //TODO: Do reset, etc. - uerr("\tWRITE (10): Command Phase Error"); - goto exit; - } - n -= blocks; - startblk += blocks; - buffer += blocks * lunp->info.blk_size; - } - - ret = HAL_SUCCESS; - -exit: - osalMutexUnlock(&lunp->msdp->mtx); - osalSysLock(); - if (lunp->state == BLK_WRITING) { - lunp->state = BLK_READY; - } else { - osalDbgCheck(lunp->state == BLK_STOP); - uwarn("MSD: State = BLK_STOP"); - } - osalSysUnlock(); - return ret; -} - -bool usbhmsdLUNSync(USBHMassStorageLUNDriver *lunp) { - osalDbgCheck(lunp != NULL); - (void)lunp; - //TODO: Do SCSI Sync - return HAL_SUCCESS; -} - -bool usbhmsdLUNGetInfo(USBHMassStorageLUNDriver *lunp, BlockDeviceInfo *bdip) { - osalDbgCheck(lunp != NULL); - osalDbgCheck(bdip != NULL); - *bdip = lunp->info; - return HAL_SUCCESS; -} - -bool usbhmsdLUNIsInserted(USBHMassStorageLUNDriver *lunp) { - osalDbgCheck(lunp != NULL); - blkstate_t state; - osalSysLock(); - state = lunp->state; - osalSysUnlock(); - return (state >= BLK_ACTIVE); -} - -bool usbhmsdLUNIsProtected(USBHMassStorageLUNDriver *lunp) { - osalDbgCheck(lunp != NULL); - return FALSE; -} - -void usbhmsdObjectInit(USBHMassStorageDriver *msdp) { - osalDbgCheck(msdp != NULL); - memset(msdp, 0, sizeof(*msdp)); - msdp->info = &usbhmsdClassDriverInfo; - osalMutexObjectInit(&msdp->mtx); -} - -#endif diff --git a/firmware/ChibiOS_16/community/os/hal/src/usbh/hal_usbh_uvc.c b/firmware/ChibiOS_16/community/os/hal/src/usbh/hal_usbh_uvc.c deleted file mode 100644 index 09a0f1df69..0000000000 --- a/firmware/ChibiOS_16/community/os/hal/src/usbh/hal_usbh_uvc.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail) - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include "hal.h" -#include "hal_usbh.h" - -#if HAL_USBH_USE_UVC - -#if !HAL_USE_USBH -#error "USBHUVC needs HAL_USE_USBH" -#endif - -#if !HAL_USBH_USE_IAD -#error "USBHUVC needs HAL_USBH_USE_IAD" -#endif - -#if USBHUVC_DEBUG_ENABLE_TRACE -#define udbgf(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define udbg(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define udbgf(f, ...) do {} while(0) -#define udbg(f, ...) do {} while(0) -#endif - -#if USBHUVC_DEBUG_ENABLE_INFO -#define uinfof(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define uinfo(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define uinfof(f, ...) do {} while(0) -#define uinfo(f, ...) do {} while(0) -#endif - -#if USBHUVC_DEBUG_ENABLE_WARNINGS -#define uwarnf(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define uwarn(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define uwarnf(f, ...) do {} while(0) -#define uwarn(f, ...) do {} while(0) -#endif - -#if USBHUVC_DEBUG_ENABLE_ERRORS -#define uerrf(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define uerr(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define uerrf(f, ...) do {} while(0) -#define uerr(f, ...) do {} while(0) -#endif - - -static usbh_baseclassdriver_t *uvc_load(usbh_device_t *dev, - const uint8_t *descriptor, uint16_t rem); -static void uvc_unload(usbh_baseclassdriver_t *drv); - -static const usbh_classdriver_vmt_t class_driver_vmt = { - uvc_load, - uvc_unload -}; -const usbh_classdriverinfo_t usbhuvcClassDriverInfo = { - 0x0e, 0x03, 0x00, "UVC", &class_driver_vmt -}; - - -static usbh_baseclassdriver_t *uvc_load(usbh_device_t *dev, const uint8_t *descriptor, uint16_t rem) { - (void)dev; - (void)descriptor; - (void)rem; - return NULL; -} - -static void uvc_unload(usbh_baseclassdriver_t *drv) { - (void)drv; -} - -#endif - diff --git a/firmware/ChibiOS_16/community/os/various/bitmap.c b/firmware/ChibiOS_16/community/os/various/bitmap.c deleted file mode 100644 index a17dfcb669..0000000000 --- a/firmware/ChibiOS_16/community/os/various/bitmap.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2015 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file bitmap.c - * @brief Bit map code. - * - * @addtogroup bitmap - * @{ - */ - -#include "string.h" /* for memset() */ - -#include "hal.h" -#include "bitmap.h" - -/*===========================================================================*/ -/* Module local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -/** - * @brief Get word number. - * - * @param[in] bit number of the bit - * - * @return Index of the word containing specified bit. - */ -static inline size_t word(size_t bit) { - return bit / (sizeof(bitmap_word_t) * 8); -} - -/** - * @brief Get bit position in word. - * - * @param[in] bit number of the bit - * - * @return Position of the specified bit related to word start. - */ -static inline size_t pos_in_word(size_t bit) { - return bit % (sizeof(bitmap_word_t) * 8); -} - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ -/** - * @brief Initializes an @p bitmap_t structure. - * - * @param[out] map the @p bitmap_t structure to be initialized - * @param[in] val the value to be written in all bitmap - */ -void bitmapObjectInit(bitmap_t *map, bitmap_word_t val) { - uint8_t pattern; - - osalDbgCheck(val == 1 || val == 0); - - if (val == 1) - pattern = 0xFF; - else - pattern = 0; - - memset(map->array, pattern, map->len*sizeof(bitmap_word_t)); -} - -/** - * @brief Set single bit in an @p bitmap_t structure. - * - * @param[out] map the @p bitmap_t structure - * @param[in] bit number of the bit to be set - */ -void bitmapSet(bitmap_t *map, size_t bit) { - size_t w = word(bit); - - osalDbgCheck(w < map->len); - map->array[w] |= (bitmap_word_t)1 << pos_in_word(bit); -} - -/** - * @brief Clear single bit in an @p bitmap_t structure. - * - * @param[out] map the @p bitmap_t structure - * @param[in] bit number of the bit to be cleared - */ -void bitmapClear(bitmap_t *map, size_t bit) { - size_t w = word(bit); - - osalDbgCheck(w < map->len); - map->array[w] &= ~((bitmap_word_t)1 << pos_in_word(bit)); -} - -/** - * @brief Invert single bit in an @p bitmap_t structure. - * - * @param[out] map the @p bitmap_t structure - * @param[in] bit number of the bit to be inverted - */ -void bitmapInvert(bitmap_t *map, size_t bit) { - size_t w = word(bit); - - osalDbgCheck(w < map->len); - map->array[w] ^= (bitmap_word_t)1 << pos_in_word(bit); -} - -/** - * @brief Get bit value from an @p bitmap_t structure. - * - * @param[in] map the @p bitmap_t structure - * @param[in] bit number of the requested bit - * - * @return Requested bit value. - */ -bitmap_word_t bitmapGet(const bitmap_t *map, size_t bit) { - size_t w = word(bit); - - osalDbgCheck(w < map->len); - return (map->array[w] >> pos_in_word(bit)) & 1; -} - -/** - * @brief Get total amount of bits in an @p bitmap_t structure. - * - * @param[in] map the @p bitmap_t structure - * - * @return Bit number. - */ -size_t bitmapGetBitsCount(const bitmap_t *map) { - return map->len * sizeof(bitmap_word_t) * 8; -} -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/various/bitmap.h b/firmware/ChibiOS_16/community/os/various/bitmap.h deleted file mode 100644 index 115b54cf84..0000000000 --- a/firmware/ChibiOS_16/community/os/various/bitmap.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2015 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file bitmap.h - * @brief Bit map structures and macros. - * - * @addtogroup bitmap - * @{ - */ - -#ifndef BITMAP_H_ -#define BITMAP_H_ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -typedef unsigned int bitmap_word_t; - -/** - * @brief Type of a event timer structure. - */ -typedef struct { - bitmap_word_t *array; - size_t len; /* Array length in _words_ NOT bytes */ -} bitmap_t; - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void bitmapObjectInit(bitmap_t *map, bitmap_word_t val); - void bitmapSet(bitmap_t *map, size_t bit); - void bitmapClear(bitmap_t *map, size_t bit); - void bitmapInvert(bitmap_t *map, size_t bit); - bitmap_word_t bitmapGet(const bitmap_t *map, size_t bit); - size_t bitmapGetBitsCount(const bitmap_t *map); -#ifdef __cplusplus -} -#endif - -#endif /* BITMAP_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/various/bswap.h b/firmware/ChibiOS_16/community/os/various/bswap.h deleted file mode 100644 index 64484984dc..0000000000 --- a/firmware/ChibiOS_16/community/os/various/bswap.h +++ /dev/null @@ -1,201 +0,0 @@ -/* - Copyright (C) 2016 Stephane D'Alu - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef BSWAP_H -#define BSWAP_H - -#if defined(__cplusplus) -extern "C" { -#endif - -#if !(defined(ARCH_BIG_ENDIAN) || defined(ARCH_LITTLE_ENDIAN)) -#error "Need to define one: ARCH_BIG_ENDIAN or ARCH_LITTLE_ENDIAN" -#endif - -#if defined(ARCH_BIG_ENDIAN) && defined(ARCH_LITTLE_ENDIAN) -#error "ARCH_BIG_ENDIAN and ARCH_LITTLE_ENDIAN are both set" -#endif - - -#define BSWAP_16(x) \ - (uint16_t)((((x) & 0xFF00) >> 8) | \ - (((x) & 0x00FF) << 8)) -#define BSWAP_32(x) \ - (uint32_t)((((x) & 0xFF000000UL) >> 24UL) | \ - (((x) & 0x00FF0000UL) >> 8UL) | \ - (((x) & 0x0000FF00UL) << 8UL) | \ - (((x) & 0x000000FFUL) << 24UL)) -#define BSWAP_64(x) \ - (uint64_t)((((x) & 0xFF00000000000000UL) >> 56UL) | \ - (((x) & 0x00FF000000000000UL) >> 40UL) | \ - (((x) & 0x0000FF0000000000UL) >> 24UL) | \ - (((x) & 0x000000FF00000000UL) >> 8UL) | \ - (((x) & 0x00000000FF000000UL) << 8UL) | \ - (((x) & 0x0000000000FF0000UL) << 24UL) | \ - (((x) & 0x000000000000FF00UL) << 40UL) | \ - (((x) & 0x00000000000000FFUL) << 56UL)) - - -#if defined(ARCH_BIG_ENDIAN) -#define le16_to_cpu(x) bswap_16(x) -#define le32_to_cpu(x) bswap_32(x) -#define le64_to_cpu(x) bswap_64(x) -#define be16_to_cpu(x) (x) -#define be32_to_cpu(x) (x) -#define be64_to_cpu(x) (x) -#define cpu_to_le16(x) bswap_16(x) -#define cpu_to_le32(x) bswap_32(x) -#define cpu_to_le64(x) bswap_64(x) -#define cpu_to_be16(x) (x) -#define cpu_to_be32(x) (x) -#define cpu_to_be64(x) (x) -#define LE16_TO_CPU(x) BSWAP_16(x) -#define LE32_TO_CPU(x) BSWAP_32(x) -#define LE64_TO_CPU(x) BSWAP_64(x) -#define BE16_TO_CPU(x) (x) -#define BE32_TO_CPU(x) (x) -#define BE64_TO_CPU(x) (x) -#define CPU_TO_LE16(x) BSWAP_16(x) -#define CPU_TO_LE32(x) BSWAP_32(x) -#define CPU_TO_LE64(x) BSWAP_64(x) -#define CPU_TO_BE16(x) (x) -#define CPU_TO_BE32(x) (x) -#define CPU_TO_BE64(x) (x) -#endif - - -#if defined(ARCH_LITTLE_ENDIAN) -#define le16_to_cpu(x) (x) -#define le32_to_cpu(x) (x) -#define le64_to_cpu(x) (x) -#define be16_to_cpu(x) bswap_16(x) -#define be32_to_cpu(x) bswap_32(x) -#define be64_to_cpu(x) bswap_64(x) -#define cpu_to_le16(x) (x) -#define cpu_to_le32(x) (x) -#define cpu_to_le64(x) (x) -#define cpu_to_be16(x) bswap_16(x) -#define cpu_to_be32(x) bswap_32(x) -#define cpu_to_be64(x) bswap_64(x) -#define LE16_TO_CPU(x) (x) -#define LE32_TO_CPU(x) (x) -#define LE64_TO_CPU(x) (x) -#define BE16_TO_CPU(x) BSWAP_16(x) -#define BE32_TO_CPU(x) BSWAP_32(x) -#define BE64_TO_CPU(x) BSWAP_64(x) -#define CPU_TO_LE16(x) (x) -#define CPU_TO_LE32(x) (x) -#define CPU_TO_LE64(x) (x) -#define CPU_TO_BE16(x) BSWAP_16(x) -#define CPU_TO_BE32(x) BSWAP_32(x) -#define CPU_TO_BE64(x) BSWAP_64(x) -#endif - - -static inline uint16_t bswap_16(const uint16_t x) - __attribute__ ((warn_unused_result)) - __attribute__ ((const)) - __attribute__ ((always_inline)); - -static inline uint16_t bswap_16(const uint16_t x) { - if (__builtin_constant_p(x)) - return BSWAP_16(x); - - uint8_t tmp; - union { uint16_t x; uint8_t b[2]; } data; - - data.x = x; - tmp = data.b[0]; - data.b[0] = data.b[1]; - data.b[1] = tmp; - - return data.x; -} - -static inline uint32_t bswap_32(const uint32_t x) - __attribute__ ((warn_unused_result)) - __attribute__ ((const)) - __attribute__ ((always_inline)); - - -static inline uint32_t bswap_32(const uint32_t x) { - if (__builtin_constant_p(x)) - return BSWAP_32(x); - - uint8_t tmp; - union { uint32_t x; uint8_t b[4]; } data; - - data.x = x; - tmp = data.b[0]; - data.b[0] = data.b[3]; - data.b[3] = tmp; - tmp = data.b[1]; - data.b[1] = data.b[2]; - data.b[2] = tmp; - - return data.x; -} - -static inline uint64_t bswap_64(const uint64_t x) - __attribute__ ((warn_unused_result)) - __attribute__ ((const)) - __attribute__ ((always_inline)); - - -static inline uint64_t bswap_64(const uint64_t x) { - if (__builtin_constant_p(x)) - return BSWAP_64(x); - - uint8_t tmp; - union { uint64_t x; uint8_t b[8]; } data; - - data.x = x; - tmp = data.b[0]; - data.b[0] = data.b[7]; - data.b[7] = tmp; - tmp = data.b[1]; - data.b[1] = data.b[6]; - data.b[6] = tmp; - tmp = data.b[2]; - data.b[2] = data.b[5]; - data.b[5] = tmp; - tmp = data.b[3]; - data.b[3] = data.b[4]; - data.b[4] = tmp; - - return data.x; -} - -static inline void bswap_n(void* const data, uint8_t len) - __attribute__ ((nonnull (1))); - -static inline void bswap_n(void* const data, uint8_t len) { - uint8_t* ptr = (uint8_t*)data; - - for ( ; len > 1 ; ptr++, len -= 2 ) { - uint8_t tmp = *ptr; - *ptr = *(ptr + len - 1); - *(ptr + len - 1) = tmp; - } -} - -#if defined(__cplusplus) -} -#endif - -#endif - - diff --git a/firmware/ChibiOS_16/community/os/various/crcsw.c b/firmware/ChibiOS_16/community/os/various/crcsw.c deleted file mode 100644 index 02a64f3efb..0000000000 --- a/firmware/ChibiOS_16/community/os/various/crcsw.c +++ /dev/null @@ -1,338 +0,0 @@ -/* - ChibiOS - Copyright (C) 2015 Michael D. Spradling - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file crcsw.c - * @brief CRC software driver. - @note SW implementation was based from: - * @note http://www.barrgroup.com/Embedded-Systems/How-To/CRC-Calculation-C-Code - * - * @addtogroup CRC - * @{ - */ - -#include "hal.h" - -#if HAL_USE_CRC || defined(__DOXYGEN__) - -#if CRCSW_USE_CRC1 || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/** - * @brief CRC default configuration. - */ - -#if CRCSW_CRC32_TABLE == TRUE || defined(__DOXYGEN__) -static const uint32_t crc32_table[256] = { - 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, - 0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3, - 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, - 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, - 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de, - 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, - 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, - 0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5, - 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172, - 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, - 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, - 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59, - 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, - 0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f, - 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, - 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, - 0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a, - 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433, - 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, - 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01, - 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, - 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, - 0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c, - 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65, - 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, - 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, - 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0, - 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, - 0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086, - 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f, - 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, - 0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, - 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a, - 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, - 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8, - 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, - 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, - 0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7, - 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc, - 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, - 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, - 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b, - 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, - 0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79, - 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, - 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, - 0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, - 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d, - 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, - 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713, - 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, - 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, - 0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e, - 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777, - 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, - 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, - 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, - 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, - 0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0, - 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9, - 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, - 0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf, - 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, - 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d -}; -#endif - -#if CRCSW_CRC16_TABLE || defined(__DOXYGEN__) -static const uint32_t crc16_table[256] = { - 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241, - 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440, - 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40, - 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841, - 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40, - 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41, - 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641, - 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040, - 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240, - 0x3600, 0xF6C1, 0xF781, 0x3740, 0xF501, 0x35C0, 0x3480, 0xF441, - 0x3C00, 0xFCC1, 0xFD81, 0x3D40, 0xFF01, 0x3FC0, 0x3E80, 0xFE41, - 0xFA01, 0x3AC0, 0x3B80, 0xFB41, 0x3900, 0xF9C1, 0xF881, 0x3840, - 0x2800, 0xE8C1, 0xE981, 0x2940, 0xEB01, 0x2BC0, 0x2A80, 0xEA41, - 0xEE01, 0x2EC0, 0x2F80, 0xEF41, 0x2D00, 0xEDC1, 0xEC81, 0x2C40, - 0xE401, 0x24C0, 0x2580, 0xE541, 0x2700, 0xE7C1, 0xE681, 0x2640, - 0x2200, 0xE2C1, 0xE381, 0x2340, 0xE101, 0x21C0, 0x2080, 0xE041, - 0xA001, 0x60C0, 0x6180, 0xA141, 0x6300, 0xA3C1, 0xA281, 0x6240, - 0x6600, 0xA6C1, 0xA781, 0x6740, 0xA501, 0x65C0, 0x6480, 0xA441, - 0x6C00, 0xACC1, 0xAD81, 0x6D40, 0xAF01, 0x6FC0, 0x6E80, 0xAE41, - 0xAA01, 0x6AC0, 0x6B80, 0xAB41, 0x6900, 0xA9C1, 0xA881, 0x6840, - 0x7800, 0xB8C1, 0xB981, 0x7940, 0xBB01, 0x7BC0, 0x7A80, 0xBA41, - 0xBE01, 0x7EC0, 0x7F80, 0xBF41, 0x7D00, 0xBDC1, 0xBC81, 0x7C40, - 0xB401, 0x74C0, 0x7580, 0xB541, 0x7700, 0xB7C1, 0xB681, 0x7640, - 0x7200, 0xB2C1, 0xB381, 0x7340, 0xB101, 0x71C0, 0x7080, 0xB041, - 0x5000, 0x90C1, 0x9181, 0x5140, 0x9301, 0x53C0, 0x5280, 0x9241, - 0x9601, 0x56C0, 0x5780, 0x9741, 0x5500, 0x95C1, 0x9481, 0x5440, - 0x9C01, 0x5CC0, 0x5D80, 0x9D41, 0x5F00, 0x9FC1, 0x9E81, 0x5E40, - 0x5A00, 0x9AC1, 0x9B81, 0x5B40, 0x9901, 0x59C0, 0x5880, 0x9841, - 0x8801, 0x48C0, 0x4980, 0x8941, 0x4B00, 0x8BC1, 0x8A81, 0x4A40, - 0x4E00, 0x8EC1, 0x8F81, 0x4F40, 0x8D01, 0x4DC0, 0x4C80, 0x8C41, - 0x4400, 0x84C1, 0x8581, 0x4540, 0x8701, 0x47C0, 0x4680, 0x8641, - 0x8201, 0x42C0, 0x4380, 0x8341, 0x4100, 0x81C1, 0x8081, 0x4040 -}; -#endif - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief CRC1 driver identifier.*/ -#if CRCSW_USE_CRC1 || defined(__DOXYGEN__) -CRCDriver CRCD1; -#endif - -#if CRCSW_CRC32_TABLE || defined(__DOXYGEN__) -const CRCConfig crcsw_crc32_config = { - .poly_size = 32, - .poly = 0x04C11DB7, - .initial_val = 0xFFFFFFFF, - .final_val = 0xFFFFFFFF, - .reflect_data = 1, - .reflect_remainder = 1, - .table = crc32_table -}; -#endif - -#if CRCSW_CRC16_TABLE || defined(__DOXYGEN__) -const CRCConfig crcsw_crc16_config = { - .poly_size = 16, - .poly = 0x8005, - .initial_val = 0x0, - .final_val = 0x0, - .reflect_data = 1, - .reflect_remainder = 1, - .table = crc16_table -}; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -#if (CRCSW_PROGRAMMABLE == TRUE) -static uint32_t reflect(uint32_t data, uint8_t nBits) { - uint32_t reflection = 0x00000000; - uint8_t bit; - - /* Reflect the data about the center bit. */ - for (bit = 0; bit < nBits; ++bit) { - /* If the LSB bit is set, set the reflection of it. */ - if (data & 0x01) { - reflection |= (1 << ((nBits - 1) - bit)); - } - - data = (data >> 1); - } - - return reflection; -} -#endif - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level CRC software initialization. - * - * @notapi - */ -void crc_lld_init(void) { - crcObjectInit(&CRCD1); - CRCD1.crc = CRCD1.config->initial_val; -} - -/** - * @brief Configures and activates the CRC peripheral. - * - * @param[in] crcp pointer to the @p CRCDriver object - * - * @notapi - */ -void crc_lld_start(CRCDriver *crcp) { - osalDbgAssert(crcp->config != NULL, "config must not be NULL"); - -#if CRCSW_PROGRAMMABLE == FALSE -#if CRCSW_CRC32_TABLE == TRUE && CRCSW_CRC16_TABLE == TRUE - osalDbgAssert((crcp->config == CRCSW_CRC32_TABLE_CONFIG) || - (crcp->config == CRCSW_CRC16_TABLE_CONFIG), "config must be CRCSW_CRC32_TABLE_CONFIG or CRCSW_CRC16_TABLE_CONFIG"); -#elif CRCSW_CRC32_TABLE == TRUE && CRCSW_CRC16_TABLE == FALSE - osalDbgAssert(crcp->config == CRCSW_CRC32_TABLE_CONFIG, - "config must be CRCSW_CRC32_TABLE_CONFIG"); -#else - osalDbgAssert(crcp->config == CRCSW_CRC16_TABLE_CONFIG, - "config must be CRCSW_CRC16_TABLE_CONFIG"); -#endif -#endif - crc_lld_reset(crcp); -} - - -/** - * @brief Deactivates the CRC peripheral. - * - * @param[in] crcp pointer to the @p CRCDriver object - * - * @notapi - */ -void crc_lld_stop(CRCDriver *crcp) { - (void)crcp; -} - -/** - * @brief Resets current CRC calculation. - * - * @param[in] crcp pointer to the @p CRCDriver object - * - * @notapi - */ -void crc_lld_reset(CRCDriver *crcp) { - crcp->crc = crcp->config->initial_val; -} - -/** - * @brief Returns calculated CRC from last reset - * - * @param[in] crcp pointer to the @p CRCDriver object - * @param[in] n size of buf in bytes - * @param[in] buf @p buffer location - * - * @notapi - */ -uint32_t crc_lld_calc(CRCDriver *crcp, size_t n, const void *buf) { - uint32_t i; - uint32_t crc; -#if (CRCSW_CRC32_TABLE == TRUE) || (CRCSW_CRC16_TABLE == TRUE) - if (crcp->config->table != NULL) { - for (i = 0; i < n; i++) { - uint8_t data = *((uint8_t*)buf + i); - uint8_t idx = (crcp->crc ^ data); - crcp->crc = (crcp->config->table[idx] ^ (crcp->crc >> 8)); - } - crc = crcp->crc; - } -#endif - -#if (CRCSW_PROGRAMMABLE == TRUE) - // Mask off bits to poly size - uint32_t mask = 1 << (crcp->config->poly_size - 1); - mask |= (mask - 1); - - crc = crcp->crc; - if (crcp->config->table == NULL) { - for (i = 0; i < n; i++) { - uint8_t data = *((uint8_t*)buf + i); - uint8_t bit; - - if (crcp->config->reflect_data) { - data = reflect(data, 8); - } - - /* Bring the next byte into the remainder. */ - crc ^= (data << (crcp->config->poly_size - 8)); - - /* Perform modulo-2 division, a bit at a time. */ - for (bit = 8; bit > 0; --bit) { - /* Try to divide the current data bit. */ - if (crc & (1 << (crcp->config->poly_size - 1))) { - crc = (crc << 1) ^ crcp->config->poly; - } else { - crc <<= 1; - } - } - } - - crcp->crc = crc; - - if (crcp->config->reflect_remainder) { - crc = reflect(crc, crcp->config->poly_size); - } - } -#endif - - return (crc ^ crcp->config->final_val) & mask; -} - -#endif /* CRCSW_USE_CRC1 */ - -#endif /* HAL_USE_CRC */ diff --git a/firmware/ChibiOS_16/community/os/various/crcsw.h b/firmware/ChibiOS_16/community/os/various/crcsw.h deleted file mode 100644 index 4483a34563..0000000000 --- a/firmware/ChibiOS_16/community/os/various/crcsw.h +++ /dev/null @@ -1,215 +0,0 @@ -/* - ChibiOS - Copyright (C) 2015 Michael D. Spradling - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file crcsw.h - * @brief CRC software driver. - * - * @addtogroup CRC - * @{ - */ - -#include "hal.h" - -#if HAL_USE_CRC || defined(__DOXYGEN__) - -#if CRCSW_USE_CRC1 || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief CRC1 software driver enable switch. - * @details If set to @p TRUE the support for CRC1 is included. - * @note The default is @p FALSE - */ -#if !defined(CRCSW_USE_CRC1) || defined(__DOXYGEN__) -#define CRCSW_USE_CRC1 FALSE -#endif - -/** - * @brief Enables software CRC32 - */ -#if !defined(CRCSW_CRC32_TABLE) || defined(__DOXYGEN__) -#define CRCSW_CRC32_TABLE FALSE -#endif - -/** - * @brief Enables software CRC16 - */ -#if !defined(CRCSW_CRC16_TABLE) || defined(__DOXYGEN__) -#define CRCSW_CRC16_TABLE FALSE -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if CRCSW_USE_CRC1 && CRC_USE_DMA -#error "Software CRC does not support DMA(CRC_USE_DMA)" -#endif - -#if CRCSW_CRC32_TABLE == FALSE && CRCSW_CRC16_TABLE == FALSE && \ - CRCSW_PROGRAMMABLE == FALSE -#error "At least one of CRCSW_PROGRAMMABLE, CRCSW_CRC32_TABLE, or CRCSW_CRC16_TABLE must be defined" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ -/** - * @brief Type of a structure representing an CRC driver. - */ -typedef struct CRCDriver CRCDriver; - -/** - * @brief Driver configuration structure. - */ -typedef struct { - /** - * @brief The size of polynomial to be used for CRC. - */ - uint32_t poly_size; - /** - * @brief The coefficients of the polynomial to be used for CRC. - */ - uint32_t poly; - /** - * @brief The inital value - */ - uint32_t initial_val; - /** - * @brief The final XOR value - */ - uint32_t final_val; - /** - * @brief Reflect bit order data going into CRC - */ - bool reflect_data; - /** - * @brief Reflect bit order of final remainder - */ - bool reflect_remainder; - /* End of the mandatory fields.*/ - /** - * @brief The crc lookup table to use when calculating CRC. - */ - const uint32_t *table; -} CRCConfig; - - -/** - * @brief Structure representing an CRC driver. - */ -struct CRCDriver { - /** - * @brief Driver state. - */ - crcstate_t state; - /** - * @brief Current configuration data. - */ - const CRCConfig *config; -#if CRC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the peripheral. - */ - mutex_t mutex; -#endif /* CRC_USE_MUTUAL_EXCLUSION */ - /* End of the mandatory fields.*/ - /** - * @brief Current value of calculated CRC. - */ - uint32_t crc; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ -#if CRCSW_CRC32_TABLE || defined(__DOXYGEN__) -/** - * @brief Configuration that represents CRC32 - */ -#define CRCSW_CRC32_TABLE_CONFIG (&crcsw_crc32_config) -#endif - -#if CRCSW_CRC16_TABLE || defined(__DOXYGEN__) -/** - * @brief Configuration that represents CRC16 - */ -#define CRCSW_CRC16_TABLE_CONFIG (&crcsw_crc16_config) -#endif - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -extern CRCDriver CRCD1; - -#if CRCSW_CRC32_TABLE -extern const CRCConfig crcsw_crc32_config; -#endif - -#if CRCSW_CRC16_TABLE -extern const CRCConfig crcsw_crc16_config; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void crc_lld_init(void); - void crc_lld_start(CRCDriver *crcp); - void crc_lld_stop(CRCDriver *crcp); - void crc_lld_reset(CRCDriver *crcp); - uint32_t crc_lld_calc(CRCDriver *crcp, size_t n, const void *buf); -#ifdef __cplusplus -} -#endif - -#endif /* CRCSW_USE_CRC1 */ - -#endif /* HAL_USE_CRC */ - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/various/dbgtrace.h b/firmware/ChibiOS_16/community/os/various/dbgtrace.h deleted file mode 100644 index b1fc2979e2..0000000000 --- a/firmware/ChibiOS_16/community/os/various/dbgtrace.h +++ /dev/null @@ -1,41 +0,0 @@ -#ifndef DBGTRACE_H_ -#define DBGTRACE_H_ - -#include "chprintf.h" - -#if !defined(DEBUG_TRACE_PRINT) -#define DEBUG_TRACE_PRINT FALSE -#endif - -#if !defined(DEBUG_TRACE_WARNING) -#define DEBUG_TRACE_WARNING FALSE -#endif - -#if !defined(DEBUG_TRACE_ERROR) -#define DEBUG_TRACE_ERROR FALSE -#endif - -/* user must provide correctly initialized pointer to print channel */ -#if DEBUG_TRACE_PRINT || DEBUG_TRACE_WARNING || DEBUG_TRACE_ERROR -extern BaseSequentialStream *GlobalDebugChannel; -#endif - -#if DEBUG_TRACE_PRINT -#define dbgprintf(fmt, ...) chprintf(GlobalDebugChannel, fmt, ##__VA_ARGS__) -#else -#define dbgprintf(fmt, ...) do {} while(0) -#endif - -#if DEBUG_TRACE_WARNING -#define warnprintf(fmt, ...) chprintf(GlobalDebugChannel, fmt, ##__VA_ARGS__) -#else -#define warnprintf(fmt, ...) do {} while(0) -#endif - -#if DEBUG_TRACE_ERROR -#define errprintf(fmt, ...) chprintf(GlobalDebugChannel, fmt, ##__VA_ARGS__) -#else -#define errprintf(fmt, ...) do {} while(0) -#endif - -#endif /* DBGTRACE_H_ */ diff --git a/firmware/ChibiOS_16/community/os/various/devices_lib/lcd/ili9341.c b/firmware/ChibiOS_16/community/os/various/devices_lib/lcd/ili9341.c deleted file mode 100644 index 979e502ccc..0000000000 --- a/firmware/ChibiOS_16/community/os/various/devices_lib/lcd/ili9341.c +++ /dev/null @@ -1,418 +0,0 @@ -/* - Copyright (C) 2013-2015 Andrea Zoppi - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file ili9341.c - * @brief ILI9341 TFT LCD diaplay controller driver. - * @note Does not support multiple calling threads natively. - */ - -#include "ch.h" -#include "hal.h" -#include "ili9341.h" - -/** - * @addtogroup ili9341 - * @{ - */ - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#if !ILI9341_USE_CHECKS && !defined(__DOXYGEN__) -/* Disable checks as needed.*/ - -#ifdef osalDbgCheck -#undef osalDbgCheck -#endif -#define osalDbgCheck(c, func) { \ - (void)(c), (void)__QUOTE_THIS(func)"()"; \ -} - -#ifdef osalDbgAssert -#undef osalDbgAssert -#endif -#define osalDbgAssert(c, m, r) { \ - (void)(c); \ -} - -#ifdef osalDbgCheckClassS -#undef osalDbgCheckClassS -#endif -#define osalDbgCheckClassS() {} - -#ifdef osalDbgCheckClassS -#undef osalDbgCheckClassS -#endif -#define osalDbgCheckClassI() {} - -#endif /* ILI9341_USE_CHECKS */ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief ILI9341D1 driver identifier.*/ -ILI9341Driver ILI9341D1; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Initializes the standard part of a @p ILI9341Driver structure. - * - * @param[out] driverp pointer to the @p ILI9341Driver object - * - * @init - */ -void ili9341ObjectInit(ILI9341Driver *driverp) { - - osalDbgCheck(driverp != NULL); - - driverp->state = ILI9341_STOP; - driverp->config = NULL; -#if (TRUE == ILI9341_USE_MUTUAL_EXCLUSION) -#if (TRUE == CH_CFG_USE_MUTEXES) - chMtxObjectInit(&driverp->lock); -#else - chSemObjectInit(&driverp->lock, 1); -#endif -#endif /* (TRUE == ILI9341_USE_MUTUAL_EXCLUSION) */ -} - -/** - * @brief Configures and activates the ILI9341 peripheral. - * @pre ILI9341 is stopped. - * - * @param[in] driverp pointer to the @p ILI9341Driver object - * @param[in] configp pointer to the @p ILI9341Config object - * - * @api - */ -void ili9341Start(ILI9341Driver *driverp, const ILI9341Config *configp) { - - chSysLock(); - osalDbgCheck(driverp != NULL); - osalDbgCheck(configp != NULL); - osalDbgCheck(configp->spi != NULL); - osalDbgAssert(driverp->state == ILI9341_STOP, "invalid state"); - - spiSelectI(configp->spi); - spiUnselectI(configp->spi); - driverp->config = configp; - driverp->state = ILI9341_READY; - chSysUnlock(); -} - -/** - * @brief Deactivates the ILI9341 peripheral. - * @pre ILI9341 is ready. - * - * @param[in] driverp pointer to the @p ILI9341Driver object - * - * @api - */ -void ili9341Stop(ILI9341Driver *driverp) { - - chSysLock(); - osalDbgCheck(driverp != NULL); - osalDbgAssert(driverp->state == ILI9341_READY, "invalid state"); - - driverp->state = ILI9341_STOP; - chSysUnlock(); -} - -#if ILI9341_USE_MUTUAL_EXCLUSION - -/** - * @brief Gains exclusive access to the ILI9341 module. - * @details This function tries to gain ownership to the ILI9341 module, if the - * module is already being used then the invoking thread is queued. - * @pre In order to use this function the option - * @p ILI9341_USE_MUTUAL_EXCLUSION must be enabled. - * @pre ILI9341 is ready. - * - * @param[in] driverp pointer to the @p ILI9341Driver object - * - * @sclass - */ -void ili9341AcquireBusS(ILI9341Driver *driverp) { - - osalDbgCheckClassS(); - osalDbgCheck(driverp == &ILI9341D1); - osalDbgAssert(driverp->state == ILI9341_READY, "not ready"); - -#if (TRUE == CH_CFG_USE_MUTEXES) - chMtxLockS(&driverp->lock); -#else - chSemWaitS(&driverp->lock); -#endif -} - -/** - * @brief Gains exclusive access to the ILI9341 module. - * @details This function tries to gain ownership to the ILI9341 module, if the - * module is already being used then the invoking thread is queued. - * @pre In order to use this function the option - * @p ILI9341_USE_MUTUAL_EXCLUSION must be enabled. - * @pre ILI9341 is ready. - * - * @param[in] driverp pointer to the @p ILI9341Driver object - * - * @api - */ -void ili9341AcquireBus(ILI9341Driver *driverp) { - - chSysLock(); - ili9341AcquireBusS(driverp); - chSysUnlock(); -} - -/** - * @brief Releases exclusive access to the ILI9341 module. - * @pre In order to use this function the option - * @p ILI9341_USE_MUTUAL_EXCLUSION must be enabled. - * @pre ILI9341 is ready. - * - * @param[in] driverp pointer to the @p ILI9341Driver object - * - * @sclass - */ -void ili9341ReleaseBusS(ILI9341Driver *driverp) { - - osalDbgCheckClassS(); - osalDbgCheck(driverp == &ILI9341D1); - osalDbgAssert(driverp->state == ILI9341_READY, "not ready"); - -#if (TRUE == CH_CFG_USE_MUTEXES) - chMtxUnlockS(&driverp->lock); -#else - chSemSignalI(&driverp->lock); -#endif -} - -/** - * @brief Releases exclusive access to the ILI9341 module. - * @pre In order to use this function the option - * @p ILI9341_USE_MUTUAL_EXCLUSION must be enabled. - * @pre ILI9341 is ready. - * - * @param[in] driverp pointer to the @p ILI9341Driver object - * - * @api - */ -void ili9341ReleaseBus(ILI9341Driver *driverp) { - - chSysLock(); - ili9341ReleaseBusS(driverp); - chSysUnlock(); -} - -#endif /* ILI9341_USE_MUTUAL_EXCLUSION */ - -#if ILI9341_IM == ILI9341_IM_4LSI_1 /* 4-wire, half-duplex */ - -/** - * @brief Asserts the slave select signal and prepares for transfers. - * @pre ILI9341 is ready. - * - * @param[in] driverp pointer to the @p ILI9341Driver object - * - * @iclass - */ -void ili9341SelectI(ILI9341Driver *driverp) { - - osalDbgCheckClassI(); - osalDbgCheck(driverp != NULL); - osalDbgAssert(driverp->state == ILI9341_READY, "invalid state"); - - driverp->state = ILI9341_ACTIVE; - spiSelectI(driverp->config->spi); -} - -/** - * @brief Asserts the slave select signal and prepares for transfers. - * @pre ILI9341 is ready. - * - * @param[in] driverp pointer to the @p ILI9341Driver object - * - * @api - */ -void ili9341Select(ILI9341Driver *driverp) { - - chSysLock(); - ili9341SelectI(driverp); - chSysUnlock(); -} - -/** - * @brief Deasserts the slave select signal. - * @details The previously selected peripheral is unselected. - * @pre ILI9341 is active. - * - * @param[in] driverp pointer to the @p ILI9341Driver object - * - * @iclass - */ -void ili9341UnselectI(ILI9341Driver *driverp) { - - osalDbgCheckClassI(); - osalDbgCheck(driverp != NULL); - osalDbgAssert(driverp->state == ILI9341_ACTIVE, "invalid state"); - - spiUnselectI(driverp->config->spi); - driverp->state = ILI9341_READY; -} - -/** - * @brief Deasserts the slave select signal. - * @details The previously selected peripheral is unselected. - * @pre ILI9341 is active. - * - * @param[in] driverp pointer to the @p ILI9341Driver object - * - * @iclass - */ -void ili9341Unselect(ILI9341Driver *driverp) { - - chSysLock(); - ili9341UnselectI(driverp); - chSysUnlock(); -} - -/** - * @brief Write command byte. - * @details Sends a command byte via SPI. - * - * @param[in] driverp pointer to the @p ILI9341Driver object - * @param[in] cmd command byte - * - * @api - */ -void ili9341WriteCommand(ILI9341Driver *driverp, uint8_t cmd) { - - osalDbgCheck(driverp != NULL); - osalDbgAssert(driverp->state == ILI9341_ACTIVE, "invalid state"); - - driverp->value = cmd; - palClearPad(driverp->config->dcx_port, driverp->config->dcx_pad); /* !Cmd */ - spiSend(driverp->config->spi, 1, &driverp->value); -} - -/** - * @brief Write data byte. - * @details Sends a data byte via SPI. - * - * @param[in] driverp pointer to the @p ILI9341Driver object - * @param[in] value data byte - * - * @api - */ -void ili9341WriteByte(ILI9341Driver *driverp, uint8_t value) { - - osalDbgCheck(driverp != NULL); - osalDbgAssert(driverp->state == ILI9341_ACTIVE, "invalid state"); - - driverp->value = value; - palSetPad(driverp->config->dcx_port, driverp->config->dcx_pad); /* Data */ - spiSend(driverp->config->spi, 1, &driverp->value); -} - -/** - * @brief Read data byte. - * @details Receives a data byte via SPI. - * - * @param[in] driverp pointer to the @p ILI9341Driver object - * - * @return data byte - * - * @api - */ -uint8_t ili9341ReadByte(ILI9341Driver *driverp) { - - osalDbgAssert(FALSE, "should not be used"); - - osalDbgCheck(driverp != NULL); - osalDbgAssert(driverp->state == ILI9341_ACTIVE, "invalid state"); - - palSetPad(driverp->config->dcx_port, driverp->config->dcx_pad); /* Data */ - spiReceive(driverp->config->spi, 1, &driverp->value); - return driverp->value; -} - -/** - * @brief Write data chunk. - * @details Sends a data chunk via SPI. - * @pre The chunk must be accessed by DMA. - * - * @param[in] driverp pointer to the @p ILI9341Driver object - * @param[in] chunk chunk bytes - * @param[in] length chunk length - * - * @api - */ -void ili9341WriteChunk(ILI9341Driver *driverp, const uint8_t chunk[], - size_t length) { - - osalDbgCheck(driverp != NULL); - osalDbgCheck(chunk != NULL); - osalDbgAssert(driverp->state == ILI9341_ACTIVE, "invalid state"); - - if (length != 0) { - palSetPad(driverp->config->dcx_port, driverp->config->dcx_pad); /* Data */ - spiSend(driverp->config->spi, length, chunk); - } -} - -/** - * @brief Read data chunk. - * @details Receives a data chunk via SPI. - * @pre The chunk must be accessed by DMA. - * - * @param[in] driverp pointer to the @p ILI9341Driver object - * @param[out] chunk chunk bytes - * @param[in] length chunk length - * - * @api - */ -void ili9341ReadChunk(ILI9341Driver *driverp, uint8_t chunk[], - size_t length) { - - osalDbgCheck(driverp != NULL); - osalDbgCheck(chunk != NULL); - osalDbgAssert(driverp->state == ILI9341_ACTIVE, "invalid state"); - - if (length != 0) { - palSetPad(driverp->config->dcx_port, driverp->config->dcx_pad); /* Data */ - spiReceive(driverp->config->spi, length, chunk); - } -} - -#else /* ILI9341_IM == * */ -#error "Only the ILI9341_IM_4LSI_1 interface mode is currently supported" -#endif /* ILI9341_IM == * */ - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/various/devices_lib/lcd/ili9341.h b/firmware/ChibiOS_16/community/os/various/devices_lib/lcd/ili9341.h deleted file mode 100644 index 007c4fd674..0000000000 --- a/firmware/ChibiOS_16/community/os/various/devices_lib/lcd/ili9341.h +++ /dev/null @@ -1,593 +0,0 @@ -/* - Copyright (C) 2013-2015 Andrea Zoppi - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file ili9341.h - * @brief ILI9341 TFT LCD diaplay controller driver. - */ - -#ifndef _ILI9341_H_ -#define _ILI9341_H_ - -/** - * @addtogroup ili9341 - * @{ - */ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name ILI9341 regulative commands - * @{ - */ -#define ILI9341_CMD_NOP (0x00) /**< No operation.*/ -#define ILI9341_CMD_RESET (0x01) /**< Software reset.*/ -#define ILI9341_GET_ID_INFO (0x04) /**< Get ID information.*/ -#define ILI9341_GET_STATUS (0x09) /**< Get status.*/ -#define ILI9341_GET_PWR_MODE (0x0A) /**< Get power mode.*/ -#define ILI9341_GET_MADCTL (0x0B) /**< Get MADCTL.*/ -#define ILI9341_GET_PIX_FMT (0x0C) /**< Get pixel format.*/ -#define ILI9341_GET_IMG_FMT (0x0D) /**< Get image format.*/ -#define ILI9341_GET_SIG_MODE (0x0E) /**< Get signal mode.*/ -#define ILI9341_GET_SELF_DIAG (0x0F) /**< Get self-diagnostics.*/ -#define ILI9341_CMD_SLEEP_ON (0x10) /**< Enter sleep mode.*/ -#define ILI9341_CMD_SLEEP_OFF (0x11) /**< Exist sleep mode.*/ -#define ILI9341_CMD_PARTIAL_ON (0x12) /**< Enter partial mode.*/ -#define ILI9341_CMD_PARTIAL_OFF (0x13) /**< Exit partial mode.*/ -#define ILI9341_CMD_INVERT_ON (0x20) /**< Enter inverted mode.*/ -#define ILI9341_CMD_INVERT_OFF (0x21) /**< Exit inverted mode.*/ -#define ILI9341_SET_GAMMA (0x26) /**< Set gamma params.*/ -#define ILI9341_CMD_DISPLAY_OFF (0x28) /**< Disable display.*/ -#define ILI9341_CMD_DISPLAY_ON (0x29) /**< Enable display.*/ -#define ILI9341_SET_COL_ADDR (0x2A) /**< Set column address.*/ -#define ILI9341_SET_PAGE_ADDR (0x2B) /**< Set page address.*/ -#define ILI9341_SET_MEM (0x2C) /**< Set memory.*/ -#define ILI9341_SET_COLOR (0x2D) /**< Set color.*/ -#define ILI9341_GET_MEM (0x2E) /**< Get memory.*/ -#define ILI9341_SET_PARTIAL_AREA (0x30) /**< Set partial area.*/ -#define ILI9341_SET_VSCROLL (0x33) /**< Set vertical scroll def.*/ -#define ILI9341_CMD_TEARING_ON (0x34) /**< Tearing line enabled.*/ -#define ILI9341_CMD_TEARING_OFF (0x35) /**< Tearing line disabled.*/ -#define ILI9341_SET_MEM_ACS_CTL (0x36) /**< Set mem access ctl.*/ -#define ILI9341_SET_VSCROLL_ADDR (0x37) /**< Set vscroll start addr.*/ -#define ILI9341_CMD_IDLE_OFF (0x38) /**< Exit idle mode.*/ -#define ILI9341_CMD_IDLE_ON (0x39) /**< Enter idle mode.*/ -#define ILI9341_SET_PIX_FMT (0x3A) /**< Set pixel format.*/ -#define ILI9341_SET_MEM_CONT (0x3C) /**< Set memory continue.*/ -#define ILI9341_GET_MEM_CONT (0x3E) /**< Get memory continue.*/ -#define ILI9341_SET_TEAR_SCANLINE (0x44) /**< Set tearing scanline.*/ -#define ILI9341_GET_TEAR_SCANLINE (0x45) /**< Get tearing scanline.*/ -#define ILI9341_SET_BRIGHTNESS (0x51) /**< Set brightness.*/ -#define ILI9341_GET_BRIGHTNESS (0x52) /**< Get brightness.*/ -#define ILI9341_SET_DISPLAY_CTL (0x53) /**< Set display ctl.*/ -#define ILI9341_GET_DISPLAY_CTL (0x54) /**< Get display ctl.*/ -#define ILI9341_SET_CABC (0x55) /**< Set CABC.*/ -#define ILI9341_GET_CABC (0x56) /**< Get CABC.*/ -#define ILI9341_SET_CABC_MIN (0x5E) /**< Set CABC min.*/ -#define ILI9341_GET_CABC_MIN (0x5F) /**< Set CABC max.*/ -#define ILI9341_GET_ID1 (0xDA) /**< Get ID1.*/ -#define ILI9341_GET_ID2 (0xDB) /**< Get ID2.*/ -#define ILI9341_GET_ID3 (0xDC) /**< Get ID3.*/ -/** @} */ - -/** - * @name ILI9341 extended commands - * @{ - */ -#define ILI9341_SET_RGB_IF_SIG_CTL (0xB0) /**< RGB IF signal ctl.*/ -#define ILI9341_SET_FRAME_CTL_NORMAL (0xB1) /**< Set frame ctl (normal).*/ -#define ILI9341_SET_FRAME_CTL_IDLE (0xB2) /**< Set frame ctl (idle).*/ -#define ILI9341_SET_FRAME_CTL_PARTIAL (0xB3) /**< Set frame ctl (partial).*/ -#define ILI9341_SET_INVERSION_CTL (0xB4) /**< Set inversion ctl.*/ -#define ILI9341_SET_BLANKING_PORCH_CTL (0xB5) /**< Set blanking porch ctl.*/ -#define ILI9341_SET_FUNCTION_CTL (0xB6) /**< Set function ctl.*/ -#define ILI9341_SET_ENTRY_MODE (0xB7) /**< Set entry mode.*/ -#define ILI9341_SET_LIGHT_CTL_1 (0xB8) /**< Set backlight ctl 1.*/ -#define ILI9341_SET_LIGHT_CTL_2 (0xB9) /**< Set backlight ctl 2.*/ -#define ILI9341_SET_LIGHT_CTL_3 (0xBA) /**< Set backlight ctl 3.*/ -#define ILI9341_SET_LIGHT_CTL_4 (0xBB) /**< Set backlight ctl 4.*/ -#define ILI9341_SET_LIGHT_CTL_5 (0xBC) /**< Set backlight ctl 5.*/ -#define ILI9341_SET_LIGHT_CTL_7 (0xBE) /**< Set backlight ctl 7.*/ -#define ILI9341_SET_LIGHT_CTL_8 (0xBF) /**< Set backlight ctl 8.*/ -#define ILI9341_SET_POWER_CTL_1 (0xC0) /**< Set power ctl 1.*/ -#define ILI9341_SET_POWER_CTL_2 (0xC1) /**< Set power ctl 2.*/ -#define ILI9341_SET_VCOM_CTL_1 (0xC5) /**< Set VCOM ctl 1.*/ -#define ILI9341_SET_VCOM_CTL_2 (0xC6) /**< Set VCOM ctl 2.*/ -#define ILI9341_SET_NVMEM (0xD0) /**< Set NVMEM data.*/ -#define ILI9341_GET_NVMEM_KEY (0xD1) /**< Get NVMEM protect key.*/ -#define ILI9341_GET_NVMEM_STATUS (0xD2) /**< Get NVMEM status.*/ -#define ILI9341_GET_ID4 (0xD3) /**< Get ID4.*/ -#define ILI9341_SET_PGAMMA (0xE0) /**< Set positive gamma.*/ -#define ILI9341_SET_NGAMMA (0xE1) /**< Set negative gamma.*/ -#define ILI9341_SET_DGAMMA_CTL_1 (0xE2) /**< Set digital gamma ctl 1.*/ -#define ILI9341_SET_DGAMMA_CTL_2 (0xE3) /**< Set digital gamma ctl 2.*/ -#define ILI9341_SET_IF_CTL (0xF6) /**< Set interface control.*/ -/** @} */ - -/** - * @name ILI9341 interface modes - * @{ - */ -#define ILI9341_IM_3LSI_1 (0x5) /**< 3-line serial, mode 1.*/ -#define ILI9341_IM_3LSI_2 (0xD) /**< 3-line serial, mode 2.*/ -#define ILI9341_IM_4LSI_1 (0x6) /**< 4-line serial, mode 1.*/ -#define ILI9341_IM_4LSI_2 (0xE) /**< 4-line serial, mode 2.*/ -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name ILI9341 configuration options - * @{ - */ - -/** - * @brief Enables the @p ili9341AcquireBus() and @p ili9341ReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ILI9341_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define ILI9341_USE_MUTUAL_EXCLUSION TRUE -#endif - -/** - * @brief ILI9341 Interface Mode. - */ -#if !defined(ILI9341_IM) || defined(__DOXYGEN__) -#define ILI9341_IM (ILI9341_IM_4LSI_1) -#endif - -/** - * @brief Enables checks for ILI9341 functions. - * @note Disabling this option saves both code and data space. - * @note Disabling checks by ChibiOS will automatically disable ILI9341 - * checks. - */ -#if !defined(ILI9341_USE_CHECKS) || defined(__DOXYGEN__) -#define ILI9341_USE_CHECKS TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if ((TRUE == ILI9341_USE_MUTUAL_EXCLUSION) && \ - (TRUE != CH_CFG_USE_MUTEXES) && \ - (TRUE != CH_CFG_USE_SEMAPHORES)) -#error "ILI9341_USE_MUTUAL_EXCLUSION requires CH_CFG_USE_MUTEXES and/or CH_CFG_USE_SEMAPHORES" -#endif - -/* TODO: Add the remaining modes.*/ -#if (ILI9341_IM != ILI9341_IM_4LSI_1) -#error "Only ILI9341_IM_4LSI_1 interface mode is supported currently" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/* Complex types forwarding.*/ -typedef struct ILI9341Config ILI9341Config; -typedef enum ili9341state_t ili9341state_t; -typedef struct ILI9341Driver ILI9341Driver; - -/** - * @brief ILI9341 driver configuration. - */ -typedef struct ILI9341Config { - SPIDriver *spi; /**< SPI driver used by ILI9341.*/ -#if (ILI9341_IM == ILI9341_IM_4LSI_1) - ioportid_t dcx_port; /**< D/!C signal port.*/ - uint16_t dcx_pad; /**< D/!C signal pad.*/ -#endif /* ILI9341_IM == * */ /* TODO: Add all modes.*/ -} ILI9341Config; - -/** - * @brief ILI9341 driver state. - */ -typedef enum ili9341state_t { - ILI9341_UNINIT = (0), /**< Not initialized.*/ - ILI9341_STOP = (1), /**< Stopped.*/ - ILI9341_READY = (2), /**< Ready.*/ - ILI9341_ACTIVE = (3), /**< Exchanging data.*/ -} ili9341state_t; - -/** - * @brief ILI9341 driver. - */ -typedef struct ILI9341Driver { - ili9341state_t state; /**< Driver state.*/ - const ILI9341Config *config; /**< Driver configuration.*/ - - /* Multithreading stuff.*/ -#if (TRUE == ILI9341_USE_MUTUAL_EXCLUSION) -#if (TRUE == CH_CFG_USE_MUTEXES) - mutex_t lock; /**< Multithreading lock.*/ -#elif (TRUE == CH_CFG_USE_SEMAPHORES) - semaphore_t lock; /**< Multithreading lock.*/ -#endif -#endif /* (TRUE == ILI9341_USE_MUTUAL_EXCLUSION) */ - - /* Temporary variables.*/ - uint8_t value; /**< Non-stacked value, for SPI with CCM.*/ -} ILI9341Driver; - -/** - * @name ILI9341 command params (little endian) - * @{ - */ -#pragma pack(push, 1) - -typedef union { - struct ILI9341ParamBits_GET_ID_INFO { - uint8_t reserved_; - uint8_t ID1; - uint8_t ID2; - uint8_t ID3; - } bits; - uint8_t bytes[4]; -} ILI9341Params_GET_ID_INFO; - -typedef union { - struct ILI9341ParamBits_GET_STATUS { - unsigned _reserved_1 : 5; /* D[ 4: 0] */ - unsigned tearing_mode : 1; /* D[ 5] */ - unsigned gamma_curve : 3; /* D[ 8: 6] */ - unsigned tearing : 1; /* D[ 9] */ - unsigned display : 1; /* D[10] */ - unsigned all_on : 1; /* D[11] */ - unsigned all_off : 1; /* D[12] */ - unsigned invert : 1; /* D[13] */ - unsigned _reserved_2 : 1; /* D[14] */ - unsigned vscroll : 1; /* D[15] */ - unsigned normal : 1; /* D[16] */ - unsigned sleep : 1; /* D[17] */ - unsigned partial : 1; /* D[18] */ - unsigned idle : 1; /* D[19] */ - unsigned pixel_format : 3; /* D[22:20] */ - unsigned _reserved_3 : 2; /* D[24:23] */ - unsigned hrefr_rtl_nltr : 1; /* D[25] */ - unsigned bgr_nrgb : 1; /* D[26] */ - unsigned vrefr_btt_nttb : 1; /* D[27] */ - unsigned transpose : 1; /* D[28] */ - unsigned coladr_rtl_nltr : 1; /* D[29] */ - unsigned rowadr_btt_nttb : 1; /* D[30] */ - unsigned booster : 1; /* D[31] */ - } bits; - uint8_t bytes[4]; -} ILI9341Params_GET_STATUS; - -typedef union { - struct ILI9341ParamBits_GET_PWR_MODE { - unsigned _reserved_1 : 2; /* D[1:0] */ - unsigned display : 1; /* D[2] */ - unsigned normal : 1; /* D[3] */ - unsigned sleep : 1; /* D[4] */ - unsigned partial : 1; /* D[5] */ - unsigned idle : 1; /* D[6] */ - unsigned booster : 1; /* D[7] */ - } bits; - uint8_t bytes[1]; -} ILI9341Params_GET_PWR_MODE; - -typedef union { - struct ILI9341ParamBits_GET_MADCTL { - unsigned _reserved_1 : 2; /* D[1:0] */ - unsigned refr_rtl_nltr : 1; /* D[2] */ - unsigned bgr_nrgb : 1; /* D[3] */ - unsigned refr_btt_nttb : 1; /* D[4] */ - unsigned invert : 1; /* D[5] */ - unsigned rtl_nltr : 1; /* D[6] */ - unsigned btt_nttb : 1; /* D[7] */ - } bits; - uint8_t bytes[1]; -} ILI9341Params_GET_MADCTL; - -typedef union { - struct ILI9341ParamBits_GET_PIX_FMT { - unsigned DBI : 3; /* D[2:0] */ - unsigned _reserved_1 : 1; /* D[3] */ - unsigned DPI : 3; /* D[6:4] */ - unsigned RIM : 1; /* D[7] */ - } bits; - uint8_t bytes[1]; -} ILI9341Params_GET_PIX_FMT; - -typedef union { - struct ILI9341ParamBits_GET_IMG_FMT { - unsigned gamma_curve : 3; /* D[2:0] */ - unsigned _reserved_1 : 5; /* D[7:3] */ - } bits; - uint8_t bytes[1]; -} ILI9341Params_GET_IMG_FMT; - -typedef union { - struct ILI9341ParamBits_GET_SIG_MODE { - unsigned _reserved_1 : 2; /* D[1:0] */ - unsigned data_enable : 1; /* D[2] */ - unsigned pixel_clock : 1; /* D[3] */ - unsigned vsync : 1; /* D[4] */ - unsigned hsync : 1; /* D[5] */ - unsigned tearing_mode : 1; /* D[6] */ - unsigned tearing : 1; /* D[7] */ - } bits; - uint8_t bytes[1]; -} ILI9341Params_GET_SIG_MODE; - -typedef union { - struct ILI9341ParamBits_GET_SELF_DIAG { - unsigned _reserved_1 : 6; /* D[5:0] */ - unsigned func_err : 1; /* D[6] */ - unsigned reg_err : 1; /* D[7] */ - } bits; - uint8_t bytes[1]; -} ILI9341Params_GET_SELF_DIAG; - -typedef union { - struct ILI9341ParamBits_SET_GAMMA { - uint8_t gamma_curve; /* D[7:0] */ - } bits; - uint8_t bytes[1]; -} ILI9341Params_SET_GAMMA; - -typedef union { - struct ILI9341ParamBits_SET_COL_ADDR { - uint8_t SC_15_8; /* D[ 7: 0] */ - uint8_t SC_7_0; /* D[15: 8] */ - uint8_t EC_15_8; /* D[23:16] */ - uint8_t EC_7_0; /* D[31:24] */ - } bits; - uint8_t bytes[4]; -} ILI9341Params_SET_COL_ADDR; - -typedef union { - struct ILI9341ParamBits_SET_PAGE_ADDR { - uint8_t SP_15_8; /* D[ 7: 0] */ - uint8_t SP_7_0; /* D[15: 8] */ - uint8_t EP_15_8; /* D[23:16] */ - uint8_t EP_7_0; /* D[31:24] */ - } bits; - uint8_t bytes[4]; -} ILI9341Params_SET_PAGE_ADDR; - -typedef union { - struct ILI9341ParamBits_SET_PARTIAL_AREA { - uint8_t SR_15_8; /* D[ 7: 0] */ - uint8_t SR_7_0; /* D[15: 8] */ - uint8_t ER_15_8; /* D[23:16] */ - uint8_t ER_7_0; /* D[31:24] */ - } bits; - uint8_t bytes[4]; -} ILI9341Params_SET_PARTIAL_AREA; - -typedef union { - struct ILI9341ParamBits_SET_VSCROLL { - uint8_t TFA_15_8; /* D[ 7: 0] */ - uint8_t TFA_7_0; /* D[15: 8] */ - uint8_t VSA_15_8; /* D[23:16] */ - uint8_t VSA_7_0; /* D[31:24] */ - uint8_t BFA_15_8; /* D[39:32] */ - uint8_t BFA_7_0; /* D[47:40] */ - } bits; - uint8_t bytes[6]; -} ILI9341Params_SET_VSCROLL; - -typedef union { - struct ILI9341ParamBits_CMD_TEARING_ON { - unsigned M : 1; /* D[0] */ - unsigned _reserved_1 : 7; /* D[7:1] */ - } bits; - uint8_t bytes[1]; -} ILI9341Params_CMD_TEARING_ON; - -typedef union { - struct ILI9341ParamBits_SET_MEM_ACS_CTL { - unsigned _reserved_1 : 2; /* D[1:0] */ - unsigned MH : 1; /* D[2] */ - unsigned BGR : 1; /* D[3] */ - unsigned ML : 1; /* D[4] */ - unsigned MV : 1; /* D[5] */ - unsigned MX : 1; /* D[6] */ - unsigned MY : 1; /* D[7] */ - } bits; - uint8_t bytes[1]; -} ILI9341Params_SET_MEM_ACS_CTL; - -typedef union { - struct ILI9341ParamBits_SET_VSCROLL_ADDR { - uint8_t VSP_15_8; /* D[ 7: 0] */ - uint8_t VSP_7_0; /* D[15: 8] */ - } bits; - uint8_t bytes[2]; -} ILI9341Params_SET_VSCROLL_ADDR; - -typedef union { - struct ILI9341ParamBits_SET_PIX_FMT { - unsigned DBI : 3; /* D[2:0] */ - unsigned _reserved_1 : 1; /* D[3] */ - unsigned DPI : 3; /* D[4:6] */ - unsigned _reserved_2 : 1; /* D[7] */ - } bits; - uint8_t bytes[1]; -} ILI9341Params_SET_PIX_FMT; - -typedef union { - struct ILI9341ParamBits_SET_TEAR_SCANLINE { - uint8_t STS_8; /* D[ 7: 0] */ - uint8_t STS_7_0; /* D[15: 8] */ - } bits; - uint8_t bytes[4]; -} ILI9341Params_SET_TEAR_SCANLINE; - -typedef union { - struct ILI9341ParamBits_GET_TEAR_SCANLINE { - uint8_t GTS_9_8; /* D[ 7: 0] */ - uint8_t GTS_7_0; /* D[15: 8] */ - } bits; - uint8_t bytes[2]; -} ILI9341Params_GET_TEAR_SCANLINE; - -typedef union { - struct ILI9341ParamBits_SET_BRIGHTNESS { - uint8_t DBV; /* D[7:0] */ - } bits; - uint8_t bytes[1]; -} ILI9341Params_SET_BRIGHTNESS; - -typedef union { - struct ILI9341ParamBits_GET_BRIGHTNESS { - uint8_t DBV; /* D[7:0] */ - } bits; - uint8_t bytes[1]; -} ILI9341Params_GET_BRIGHTNESS; - -typedef union { - struct ILI9341ParamBits_SET_DISPLAY_CTL { - unsigned _reserved_1 : 2; /* D[1:0] */ - unsigned BL : 1; /* D[2] */ - unsigned DD : 1; /* D[3] */ - unsigned _reserved_2 : 1; /* D[4] */ - unsigned BCTRL : 1; /* D[5] */ - unsigned _reserved_3 : 1; /* D[7:6] */ - } bits; - uint8_t bytes[1]; -} ILI9341Params_SET_DISPLAY_CTL; - -typedef union { - struct ILI9341ParamBits_GET_DISPLAY_CTL { - unsigned _reserved_1 : 2; /* D[1:0] */ - unsigned BL : 1; /* D[2] */ - unsigned DD : 1; /* D[3] */ - unsigned _reserved_2 : 1; /* D[4] */ - unsigned BCTRL : 1; /* D[5] */ - unsigned _reserved_3 : 1; /* D[7:6] */ - } bits; - uint8_t bytes[1]; -} ILI9341Params_GET_DISPLAY_CTL; - -typedef union { - struct ILI9341ParamBits_SET_CABC { - unsigned C : 2; /* D[1:0] */ - unsigned _reserved_1 : 6; /* D[7:2] */ - } bits; - uint8_t bytes[1]; -} ILI9341Params_SET_CABC; - -typedef union { - struct ILI9341ParamBits_GET_CABC { - unsigned C : 2; /* D[1:0] */ - unsigned _reserved_1 : 6; /* D[7:2] */ - } bits; - uint8_t bytes[1]; -} ILI9341Params_GET_CABC; - -typedef union { - struct ILI9341ParamBits_SET_CABC_MIN { - uint8_t CMB; /* D[7:0] */ - } bits; - uint8_t bytes[1]; -} ILI9341Params_SET_CABC_MIN; - -typedef union { - struct ILI9341ParamBits_GET_CABC_MIN { - uint8_t CMB; /* D[7:0] */ - } bits; - uint8_t bytes[1]; -} ILI9341Params_GET_CABC_MIN; - -#if 0 /* TODO: Extended command structs.*/ - -typedef union { - struct ILI9341ParamBits { - unsigned : 1; /* D[] */ - unsigned : 1; /* D[] */ - unsigned : 1; /* D[] */ - unsigned : 1; /* D[] */ - unsigned : 1; /* D[] */ - unsigned : 1; /* D[] */ - unsigned : 1; /* D[] */ - unsigned : 1; /* D[] */ - } bits; - uint8_t bytes[1]; -} ILI9341Params_; - -typedef union { - struct ILI9341ParamBits { - unsigned : 1; /* D[] */ - unsigned : 1; /* D[] */ - unsigned : 1; /* D[] */ - unsigned : 1; /* D[] */ - unsigned : 1; /* D[] */ - unsigned : 1; /* D[] */ - unsigned : 1; /* D[] */ - unsigned : 1; /* D[] */ - } bits; - uint8_t bytes[1]; -} ILI9341Params_; - -#endif /*0*/ - -#pragma pack(pop) - -/** @} */ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -extern ILI9341Driver ILI9341D1; - -#ifdef __cplusplus -extern "C" { -#endif - - void ili9341ObjectInit(ILI9341Driver *driverp); - void ili9341Start(ILI9341Driver *driverp, const ILI9341Config *configp); - void ili9341Stop(ILI9341Driver *driverp); -#if (ILI9341_USE_MUTUAL_EXCLUSION == TRUE) - void ili9341AcquireBusS(ILI9341Driver *driverp); - void ili9341AcquireBus(ILI9341Driver *driverp); - void ili9341ReleaseBusS(ILI9341Driver *driverp); - void ili9341ReleaseBus(ILI9341Driver *driverp); -#endif /* (ILI9341_USE_MUTUAL_EXCLUSION == TRUE) */ - void ili9341SelectI(ILI9341Driver *driverp); - void ili9341Select(ILI9341Driver *driverp); - void ili9341UnselectI(ILI9341Driver *driverp); - void ili9341Unselect(ILI9341Driver *driverp); - void ili9341WriteCommand(ILI9341Driver *driverp, uint8_t cmd); - void ili9341WriteByte(ILI9341Driver *driverp, uint8_t value); - uint8_t ili9341ReadByte(ILI9341Driver *driverp); - void ili9341WriteChunk(ILI9341Driver *driverp, const uint8_t chunk[], - size_t length); - void ili9341ReadChunk(ILI9341Driver *driverp, uint8_t chunk[], - size_t length); - -#ifdef __cplusplus -} -#endif - -/** @} */ - -#endif /* _ILI9341_H_ */ diff --git a/firmware/ChibiOS_16/community/os/various/devices_lib/mems/l3gd20.c b/firmware/ChibiOS_16/community/os/various/devices_lib/mems/l3gd20.c deleted file mode 100644 index 1cc52c931d..0000000000 --- a/firmware/ChibiOS_16/community/os/various/devices_lib/mems/l3gd20.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi - - This file is part of PLAY for ChibiOS/RT. - - PLAY is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - PLAY is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - Special thanks to Giovanni Di Sirio for teachings, his moral support and - friendship. Note that some or every piece of this file could be part of - the ChibiOS project that is intellectual property of Giovanni Di Sirio. - Please refer to ChibiOS/RT license before use this file. - - For suggestion or Bug report - roccomarco.guglielmi@playembedded.org - */ - -/** - * @file l3gd20.c - * @brief L3GD20 MEMS interface module code. - * - * @addtogroup l3gd20 - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#include "l3gd20.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Reads a generic register value. - * @pre The SPI interface must be initialized and the driver started. - * - * @param[in] spip pointer to the SPI interface - * @param[in] reg register number - * @return register value. - */ -uint8_t l3gd20ReadRegister(SPIDriver *spip, uint8_t reg) { - uint8_t txbuf[2] = {L3GD20_RW | reg, 0xFF}; - uint8_t rxbuf[2] = {0x00, 0x00}; - spiSelect(spip); - spiExchange(spip, 2, txbuf, rxbuf); - spiUnselect(spip); - return rxbuf[1]; -} - - -void l3gd20WriteRegister(SPIDriver *spip, uint8_t reg, uint8_t value) { - - switch (reg) { - - default: - /* Reserved register must not be written, according to the datasheet - * this could permanently damage the device. - */ - chDbgAssert(FALSE, "lg3d20WriteRegister(), reserved register"); - case L3GD20_AD_WHO_AM_I: - case L3GD20_AD_OUT_TEMP : - case L3GD20_AD_STATUS_REG: - case L3GD20_AD_OUT_X_L: - case L3GD20_AD_OUT_X_H: - case L3GD20_AD_OUT_Y_L: - case L3GD20_AD_OUT_Y_H: - case L3GD20_AD_OUT_Z_L: - case L3GD20_AD_OUT_Z_H: - case L3GD20_AD_FIFO_SRC_REG: - case L3GD20_AD_INT1_SRC: - /* Read only registers cannot be written, the command is ignored.*/ - return; - case L3GD20_AD_CTRL_REG1: - case L3GD20_AD_CTRL_REG2: - case L3GD20_AD_CTRL_REG3: - case L3GD20_AD_CTRL_REG4: - case L3GD20_AD_CTRL_REG5: - case L3GD20_AD_REFERENCE: - case L3GD20_AD_FIFO_CTRL_REG: - case L3GD20_AD_INT1_CFG: - case L3GD20_AD_INT1_TSH_XH: - case L3GD20_AD_INT1_TSH_XL: - case L3GD20_AD_INT1_TSH_YH: - case L3GD20_AD_INT1_TSH_YL: - case L3GD20_AD_INT1_TSH_ZH: - case L3GD20_AD_INT1_TSH_ZL: - case L3GD20_AD_INT1_DURATION: - spiSelect(spip); - uint8_t txbuf[2] = {reg, value}; - spiSend(spip, 2, txbuf); - spiUnselect(spip); - } -} -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/various/devices_lib/mems/l3gd20.h b/firmware/ChibiOS_16/community/os/various/devices_lib/mems/l3gd20.h deleted file mode 100644 index 08d90927e1..0000000000 --- a/firmware/ChibiOS_16/community/os/various/devices_lib/mems/l3gd20.h +++ /dev/null @@ -1,243 +0,0 @@ -/* - Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi - - This file is part of PLAY for ChibiOS/RT. - - PLAY is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - PLAY is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - Special thanks to Giovanni Di Sirio for teachings, his moral support and - friendship. Note that some or every piece of this file could be part of - the ChibiOS project that is intellectual property of Giovanni Di Sirio. - Please refer to ChibiOS/RT license before use this file. - - For suggestion or Bug report - roccomarco.guglielmi@playembedded.org - */ - -/** - * @file l3gd20.h - * @brief L3GD20 MEMS interface module header. - * - * @{ - */ - -#ifndef _L3GD20_H_ -#define _L3GD20_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#define L3GD20_SENS_250DPS ((float)131.072f) /*!< gyroscope sensitivity with 250 dps full scale [LSB/dps] */ -#define L3GD20_SENS_500DPS ((float)65.536f) /*!< gyroscope sensitivity with 500 dps full scale [LSB/dps] */ -#define L3GD20_SENS_2000DPS ((float)16.384f) /*!< gyroscope sensitivity with 2000 dps full scale [LSB/dps] */ -/** - * @name L3GD20 register names - * @{ - */ -/******************************************************************************/ -/* */ -/* L3GD20 on board MEMS */ -/* */ -/******************************************************************************/ -/******************* Bit definition for SPI communication *******************/ -#define L3GD20_DI ((uint8_t)0xFF) /*!< DI[7:0] Data input */ -#define L3GD20_DI_0 ((uint8_t)0x01) /*!< bit 0 */ -#define L3GD20_DI_1 ((uint8_t)0x02) /*!< bit 1 */ -#define L3GD20_DI_2 ((uint8_t)0x04) /*!< bit 2 */ -#define L3GD20_DI_3 ((uint8_t)0x08) /*!< bit 3 */ -#define L3GD20_DI_4 ((uint8_t)0x10) /*!< bit 4 */ -#define L3GD20_DI_5 ((uint8_t)0x20) /*!< bit 5 */ -#define L3GD20_DI_6 ((uint8_t)0x40) /*!< bit 6 */ -#define L3GD20_DI_7 ((uint8_t)0x80) /*!< bit 7 */ - -#define L3GD20_AD ((uint8_t)0x3F) /*!< AD[5:0] Address Data */ -#define L3GD20_AD_0 ((uint8_t)0x01) /*!< bit 0 */ -#define L3GD20_AD_1 ((uint8_t)0x02) /*!< bit 1 */ -#define L3GD20_AD_2 ((uint8_t)0x04) /*!< bit 2 */ -#define L3GD20_AD_3 ((uint8_t)0x08) /*!< bit 3 */ -#define L3GD20_AD_4 ((uint8_t)0x10) /*!< bit 4 */ -#define L3GD20_AD_5 ((uint8_t)0x20) /*!< bit 5 */ - -#define L3GD20_MS ((uint8_t)0x40) /*!< Multiple read write */ -#define L3GD20_RW ((uint8_t)0x80) /*!< Read Write, 1 0 */ - -/****************** Bit definition for Registers Addresses *******************/ -#define L3GD20_AD_WHO_AM_I ((uint8_t)0x0F) /*!< WHO I AM */ -#define L3GD20_AD_CTRL_REG1 ((uint8_t)0x20) /*!< CONTROL REGISTER 1 */ -#define L3GD20_AD_CTRL_REG2 ((uint8_t)0x21) /*!< CONTROL REGISTER 2 */ -#define L3GD20_AD_CTRL_REG3 ((uint8_t)0x22) /*!< CONTROL REGISTER 3 */ -#define L3GD20_AD_CTRL_REG4 ((uint8_t)0x23) /*!< CONTROL REGISTER 4 */ -#define L3GD20_AD_CTRL_REG5 ((uint8_t)0x24) /*!< CONTROL REGISTER 5 */ -#define L3GD20_AD_REFERENCE ((uint8_t)0x25) /*!< REFERENCE/DATACAPTURE */ -#define L3GD20_AD_OUT_TEMP ((uint8_t)0x26) /*!< MEMS ONBOARD TEMP SENSOR */ -#define L3GD20_AD_STATUS_REG ((uint8_t)0x27) /*!< STATUS REGISTER */ -#define L3GD20_AD_OUT_X_L ((uint8_t)0x28) /*!< OUTPUT X-AXIS LOW */ -#define L3GD20_AD_OUT_X_H ((uint8_t)0x29) /*!< OUTPUT X-AXIS HIGH */ -#define L3GD20_AD_OUT_Y_L ((uint8_t)0x2A) /*!< OUTPUT Y-AXIS LOW */ -#define L3GD20_AD_OUT_Y_H ((uint8_t)0x2B) /*!< OUTPUT Y-AXIS HIGH */ -#define L3GD20_AD_OUT_Z_L ((uint8_t)0x2C) /*!< OUTPUT Z-AXIS LOW */ -#define L3GD20_AD_OUT_Z_H ((uint8_t)0x2D) /*!< OUTPUT Z-AXIS HIGH */ -#define L3GD20_AD_FIFO_CTRL_REG ((uint8_t)0x2E) /*!< FIFO CONTROL REGISTER */ -#define L3GD20_AD_FIFO_SRC_REG ((uint8_t)0x2F) /*!< FIFO SOURCE REGISTER */ -#define L3GD20_AD_INT1_CFG ((uint8_t)0x30) /*!< INTERRUPT1 CONFIG REGISTER */ -#define L3GD20_AD_INT1_SRC ((uint8_t)0x31) /*!< INTERRUPT1 SOURCE REGISTER */ -#define L3GD20_AD_INT1_TSH_XH ((uint8_t)0x32) /*!< INTERRUPT1 THRESHOLD X-AXIS HIGH */ -#define L3GD20_AD_INT1_TSH_XL ((uint8_t)0x33) /*!< INTERRUPT1 THRESHOLD X-AXIS LOW */ -#define L3GD20_AD_INT1_TSH_YH ((uint8_t)0x34) /*!< INTERRUPT1 THRESHOLD Y-AXIS HIGH */ -#define L3GD20_AD_INT1_TSH_YL ((uint8_t)0x35) /*!< INTERRUPT1 THRESHOLD Y-AXIS LOW */ -#define L3GD20_AD_INT1_TSH_ZH ((uint8_t)0x36) /*!< INTERRUPT1 THRESHOLD Z-AXIS HIGH */ -#define L3GD20_AD_INT1_TSH_ZL ((uint8_t)0x37) /*!< INTERRUPT1 THRESHOLD Z-AXIS LOW */ -#define L3GD20_AD_INT1_DURATION ((uint8_t)0x38) /*!< INTERRUPT1 DURATION */ - -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @name Gyroscope data structures and types - * @{ - */ - -/** - * @brief Gyroscope Output Data Rate - */ -typedef enum { - L3GD20_ODR_95Hz_Fc_12_5 = 0x00, /*!< Output Data Rate = 95 Hz - LPF Cut-Off = 12.5 Hz */ - L3GD20_ODR_95Hz_Fc_25 = 0x10, /*!< Output Data Rate = 95 Hz - LPF Cut-Off = 25 Hz */ - L3GD20_ODR_190Hz_Fc_12_5 = 0x40, /*!< Output Data Rate = 190 Hz - LPF Cut-Off = 12.5 Hz */ - L3GD20_ODR_190Hz_Fc_25 = 0x50, /*!< Output Data Rate = 190 Hz - LPF Cut-Off = 25 Hz */ - L3GD20_ODR_190Hz_Fc_50 = 0x60, /*!< Output Data Rate = 190 Hz - LPF Cut-Off = 50 Hz */ - L3GD20_ODR_190Hz_Fc_70 = 0x70, /*!< Output Data Rate = 190 Hz - LPF Cut-Off = 70 Hz */ - L3GD20_ODR_380Hz_Fc_20 = 0x80, /*!< Output Data Rate = 380 Hz - LPF Cut-Off = 20 Hz */ - L3GD20_ODR_380Hz_Fc_25 = 0x90, /*!< Output Data Rate = 380 Hz - LPF Cut-Off = 25 Hz */ - L3GD20_ODR_380Hz_Fc_50 = 0xA0, /*!< Output Data Rate = 380 Hz - LPF Cut-Off = 50 Hz */ - L3GD20_ODR_380Hz_Fc_100 = 0xB0, /*!< Output Data Rate = 380 Hz - LPF Cut-Off = 100 Hz */ - L3GD20_ODR_760Hz_Fc_30 = 0xC0, /*!< Output Data Rate = 760 Hz - LPF Cut-Off = 30 Hz */ - L3GD20_ODR_760Hz_Fc_35 = 0xD0, /*!< Output Data Rate = 760 Hz - LPF Cut-Off = 35 Hz */ - L3GD20_ODR_760Hz_Fc_50 = 0xE0, /*!< Output Data Rate = 760 Hz - LPF Cut-Off = 50 Hz */ - L3GD20_ODR_760Hz_Fc_100 = 0xF0 /*!< Output Data Rate = 760 Hz - LPF Cut-Off = 100 Hz */ -}L3GD20_ODR_t; - -/** - * @brief Gyroscope Power Mode - */ -typedef enum { - L3GD20_PM_POWER_DOWN = 0x00, /*!< Normal mode enabled */ - L3GD20_PM_SLEEP_NORMAL = 0x08 /*!< Low Power mode enabled */ -}L3GD20_PM_t; - -/** - * @brief Gyroscope Full Scale - */ -typedef enum { - L3GD20_FS_250DPS = 0x00, /*!< ±250 dps */ - L3GD20_FS_500DPS = 0x10, /*!< ±500 dps */ - L3GD20_FS_2000DPS = 0x20 /*!< ±200 dps */ -}L3GD20_FS_t; - -/** - * @brief Gyroscope Axes Enabling - */ -typedef enum { - L3GD20_AE_DISABLED = 0x00, /*!< All disabled */ - L3GD20_AE_X = 0x01, /*!< Only X */ - L3GD20_AE_Y = 0x02, /*!< Only Y */ - L3GD20_AE_XY = 0x03, /*!< X & Y */ - L3GD20_AE_Z = 0x04, /*!< Only Z */ - L3GD20_AE_XZ = 0x05, /*!< X & Z */ - L3GD20_AE_YZ = 0x06, /*!< Y & Z */ - L3GD20_AE_XYZ = 0x07 /*!< All enabled */ -}L3GD20_AE_t; - -/** - * @brief Gyroscope Block Data Update - */ -typedef enum { - L3GD20_BDU_CONTINOUS = 0x00, /*!< Continuos Update */ - L3GD20_BDU_BLOCKED = 0x80 /*!< Single Update: output registers not updated until MSB and LSB reading */ -}L3GD20_BDU_t; - -/** - * @brief Gyroscope Endianness - */ -typedef enum { - L3GD20_End_LITTLE = 0x00, /*!< Little Endian: data LSB @ lower address */ - L3GD20_End_BIG = 0x40 /*!< Big Endian: data MSB @ lower address */ -}L3GD20_End_t; - - -/** - * @brief Gyroscope configuration structure. - */ -typedef struct { - /** - * @brief Gyroscope fullscale value. - */ - L3GD20_FS_t fullscale; - /** - * @brief Gyroscope power mode selection. - */ - L3GD20_PM_t powermode; - /** - * @brief Gyroscope output data rate selection. - */ - L3GD20_ODR_t outputdatarate; - /** - * @brief Gyroscope axes enabling. - */ - L3GD20_AE_t axesenabling; - /** - * @brief Gyroscope endianess. - */ - L3GD20_End_t endianess; - /** - * @brief Gyroscope block data update. - */ - L3GD20_BDU_t blockdataupdate; -} L3GD20_Config; -/** @} */ -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - - uint8_t l3gd20ReadRegister(SPIDriver *spip, uint8_t reg); - void l3gd20WriteRegister(SPIDriver *spip, uint8_t reg, uint8_t value); -#ifdef __cplusplus -} -#endif - -#endif /* _L3GD20_H_ */ - -/** @} */ - diff --git a/firmware/ChibiOS_16/community/os/various/devices_lib/mems/lis3mdl.c b/firmware/ChibiOS_16/community/os/various/devices_lib/mems/lis3mdl.c deleted file mode 100644 index 99b71e45e9..0000000000 --- a/firmware/ChibiOS_16/community/os/various/devices_lib/mems/lis3mdl.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi - - This file is part of PLAY for ChibiOS/RT. - - PLAY is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - PLAY is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - Special thanks to Giovanni Di Sirio for teachings, his moral support and - friendship. Note that some or every piece of this file could be part of - the ChibiOS project that is intellectual property of Giovanni Di Sirio. - Please refer to ChibiOS/RT license before use this file. - - For suggestion or Bug report - roccomarco.guglielmi@playembedded.org - */ - -/** - * @file lis3mdl.c - * @brief LIS3MDL MEMS interface module through I2C code. - * - * @addtogroup lis3mdl - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#include "lis3mdl.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Reads a generic sub-register value. - * @pre The I2C interface must be initialized and the driver started. - * - * @param[in] i2cp pointer to the I2C interface - * @param[in] sad slave address without R bit - * @param[in] sub sub-register address - * @param[in] message pointer to message - * @return register value. - */ -uint8_t lis3mdlReadRegister(I2CDriver *i2cp, uint8_t sad, uint8_t sub, - msg_t* message) { - - uint8_t txbuf, rxbuf[2]; -#if defined(STM32F103_MCUCONF) - txbuf = LSM303DLHC_SUB_MSB | sub; - if(message != NULL){ - *message = i2cMasterTransmitTimeout(i2cp, sad, &txbuf, 1, rxbuf, 2, - TIME_INFINITE); - } - else{ - i2cMasterTransmitTimeout(i2cp, sad, &txbuf, 1, rxbuf, 2, TIME_INFINITE); - } - return rxbuf[0]; -#else - txbuf = sub; - if(message != NULL){ - *message = i2cMasterTransmitTimeout(i2cp, sad, &txbuf, 1, rxbuf, 1, - TIME_INFINITE); - } - else{ - i2cMasterTransmitTimeout(i2cp, sad, &txbuf, 1, rxbuf, 1, TIME_INFINITE); - } - return rxbuf[0]; -#endif -} - -/** - * @brief Writes a value into a register. - * @pre The I2C interface must be initialized and the driver started. - * - * @param[in] i2cp pointer to the I2C interface - * @param[in] sad slave address without R bit - * @param[in] sub sub-register address - * @param[in] value the value to be written - * @param[out] message pointer to message - */ -void lis3mdlWriteRegister(I2CDriver *i2cp, uint8_t sad, uint8_t sub, - uint8_t value, msg_t* message) { - - uint8_t txbuf[2]; - uint8_t rxbuf; - switch (sub) { - default: - /* Reserved register must not be written, according to the datasheet - * this could permanently damage the device. - */ - chDbgAssert(FALSE, "lis3mdlWriteRegister(), reserved register"); - case LIS3MDL_SUB_WHO_AM_I: - case LIS3MDL_SUB_STATUS_REG: - case LIS3MDL_SUB_OUT_X_L: - case LIS3MDL_SUB_OUT_X_H: - case LIS3MDL_SUB_OUT_Y_L: - case LIS3MDL_SUB_OUT_Y_H: - case LIS3MDL_SUB_OUT_Z_L: - case LIS3MDL_SUB_OUT_Z_H: - case LIS3MDL_SUB_INT_SOURCE: - case LIS3MDL_SUB_INT_THS_L: - case LIS3MDL_SUB_INT_THS_H: - /* Read only registers cannot be written, the command is ignored.*/ - return; - case LIS3MDL_SUB_CTRL_REG1: - case LIS3MDL_SUB_CTRL_REG2: - case LIS3MDL_SUB_CTRL_REG3: - case LIS3MDL_SUB_CTRL_REG4: - case LIS3MDL_SUB_CTRL_REG5: - case LIS3MDL_SUB_INT_CFG: - txbuf[0] = sub; - txbuf[1] = value; - if(message != NULL){ - *message = i2cMasterTransmitTimeout(i2cp, sad, txbuf, 2, &rxbuf, 0, - TIME_INFINITE); - } - else{ - i2cMasterTransmitTimeout(i2cp, sad, txbuf, 2, &rxbuf, 0, TIME_INFINITE); - } - break; - } -} -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/various/devices_lib/mems/lis3mdl.h b/firmware/ChibiOS_16/community/os/various/devices_lib/mems/lis3mdl.h deleted file mode 100644 index e55978e9bc..0000000000 --- a/firmware/ChibiOS_16/community/os/various/devices_lib/mems/lis3mdl.h +++ /dev/null @@ -1,258 +0,0 @@ -/* - Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi - - This file is part of PLAY for ChibiOS/RT. - - PLAY is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - PLAY is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - Special thanks to Giovanni Di Sirio for teachings, his moral support and - friendship. Note that some or every piece of this file could be part of - the ChibiOS project that is intellectual property of Giovanni Di Sirio. - Please refer to ChibiOS/RT license before use this file. - - For suggestion or Bug report - roccomarco.guglielmi@playembedded.org - */ - -/** - * @file lis3mdl.h - * @brief LIS3MDL MEMS interface module header. - * - * @{ - */ - -#ifndef _LIS3MDL_H_ -#define _LIS3MDL_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#define LIS3MDL_COMP_SENS_4GA ((float)6842.0f) /*!< compass sensitivity with 4 GA full scale [LSB / Ga] */ -#define LIS3MDL_COMP_SENS_8GA ((float)3421.0f) /*!< compass sensitivity with 8 GA full scale [LSB / Ga] */ -#define LIS3MDL_COMP_SENS_12GA ((float)2281.0f) /*!< compass sensitivity with 12 GA full scale [LSB / Ga] */ -#define LIS3MDL_COMP_SENS_16GA ((float)1711.0f) /*!< compass sensitivity with 16 GA full scale [LSB / Ga] */ -/** - * @name LIS3MDL register names - * @{ - */ -/******************************************************************************/ -/* */ -/* LIS3MDL on board MEMS */ -/* */ -/******************************************************************************/ -/***************** Bit definition for I2C/SPI communication *****************/ -#define LIS3MDL_SUB ((uint8_t)0x7F) /*!< SUB[6:0] Sub-registers address Mask */ -#define LIS3MDL_SUB_0 ((uint8_t)0x01) /*!< bit 0 */ -#define LIS3MDL_SUB_1 ((uint8_t)0x02) /*!< bit 1 */ -#define LIS3MDL_SUB_2 ((uint8_t)0x08) /*!< bit 3 */ -#define LIS3MDL_SUB_4 ((uint8_t)0x10) /*!< bit 4 */ -#define LIS3MDL_SUB_5 ((uint8_t)0x20) /*!< bit 5 */ -#define LIS3MDL_SUB_6 ((uint8_t)0x40) /*!< bit 6 */ - -#define LIS3MDL_SUB_MSB ((uint8_t)0x80) /*!< Multiple data read\write bit */ - -/**************** Bit definition SUB-Registers Addresses ********************/ -#define LIS3MDL_SUB_WHO_AM_I ((uint8_t)0x0F) /*!< CONTROL REGISTER 1 */ -#define LIS3MDL_SUB_CTRL_REG1 ((uint8_t)0x20) /*!< CONTROL REGISTER 1 */ -#define LIS3MDL_SUB_CTRL_REG2 ((uint8_t)0x21) /*!< CONTROL REGISTER 2 */ -#define LIS3MDL_SUB_CTRL_REG3 ((uint8_t)0x22) /*!< CONTROL REGISTER 3 */ -#define LIS3MDL_SUB_CTRL_REG4 ((uint8_t)0x23) /*!< CONTROL REGISTER 4 */ -#define LIS3MDL_SUB_CTRL_REG5 ((uint8_t)0x24) /*!< CONTROL REGISTER 5 */ -#define LIS3MDL_SUB_STATUS_REG ((uint8_t)0x27) /*!< STATUS REGISTER */ -#define LIS3MDL_SUB_OUT_X_L ((uint8_t)0x28) /*!< OUTPUT X-AXIS LOW */ -#define LIS3MDL_SUB_OUT_X_H ((uint8_t)0x29) /*!< OUTPUT X-AXIS HIGH */ -#define LIS3MDL_SUB_OUT_Y_L ((uint8_t)0x2A) /*!< OUTPUT Y-AXIS LOW */ -#define LIS3MDL_SUB_OUT_Y_H ((uint8_t)0x2B) /*!< OUTPUT Y-AXIS HIGH */ -#define LIS3MDL_SUB_OUT_Z_L ((uint8_t)0x2C) /*!< OUTPUT Z-AXIS LOW */ -#define LIS3MDL_SUB_OUT_Z_H ((uint8_t)0x2D) /*!< OUTPUT Z-AXIS HIGH */ -#define LIS3MDL_SUB_INT_CFG ((uint8_t)0x30) /*!< INTERRUPT1 CONFIG */ -#define LIS3MDL_SUB_INT_SOURCE ((uint8_t)0x31) /*!< INTERRUPT1 SOURCE */ -#define LIS3MDL_SUB_INT_THS_L ((uint8_t)0x32) /*!< INTERRUPT1 THRESHOLD */ -#define LIS3MDL_SUB_INT_THS_H ((uint8_t)0x33) /*!< INTERRUPT1 DURATION */ - -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @name Compass data structures and types - * @{ - */ - -/** - * @brief Compass Slave Address - */ -typedef enum { - LIS3MDL_SAD_GND = 0x1C, /*!< COMPASS Slave Address when SA1 is to GND */ - LIS3MDL_SAD_VCC = 0x1E /*!< COMPASS Slave Address when SA1 is to VCC */ -}LIS3MDL_SAD_t; - -/** - * @brief Compass Operation Mode for X and Y axes - */ -typedef enum { - LIS3MDL_OMXY_LOW_POWER = 0x00, /*!< Operation Mode XY low power */ - LIS3MDL_OMXY_MEDIUM_PERFORMANCE = 0x20, /*!< Operation Mode XY medium performance */ - LIS3MDL_OMXY_HIGH_PERFORMANCE = 0x40, /*!< Operation Mode XY high performance */ - LIS3MDL_OMXY_ULTRA_PERFORMANCE = 0x60 /*!< Operation Mode XY ultra performance */ -}LIS3MDL_OMXY_t; - -/** - * @brief Compass Output Data Rate - */ -typedef enum { - LIS3MDL_ODR_0_625Hz = 0x00, /*!< Output Data Rate = 0.625 Hz */ - LIS3MDL_ODR_1_25Hz = 0x04, /*!< Output Data Rate = 1.25 Hz */ - LIS3MDL_ODR_2_5Hz = 0x08, /*!< Output Data Rate = 2.5 Hz */ - LIS3MDL_ODR_5Hz = 0x0C, /*!< Output Data Rate = 5 Hz */ - LIS3MDL_ODR_10Hz = 0x10, /*!< Output Data Rate = 10 Hz */ - LIS3MDL_ODR_20Hz = 0x14, /*!< Output Data Rate = 20 Hz */ - LIS3MDL_ODR_40Hz = 0x18, /*!< Output Data Rate = 40 Hz */ - LIS3MDL_ODR_80Hz = 0x1C /*!< Output Data Rate = 80 Hz */ -}LIS3MDL_ODR_t; - -/** - * @brief Compass Full Scale - */ -typedef enum { - LIS3MDL_FS_4GA = 0x00, /*!< ±4 Gauss */ - LIS3MDL_FS_8GA = 0x02, /*!< ±8 Gauss */ - LIS3MDL_FS_12GA = 0x04, /*!< ±12 Gauss */ - LIS3MDL_FS_16GA = 0x0C /*!< ±16 Gauss */ -}LIS3MDL_FS_t; - -/** - * @brief Compass Low Mode configuration - */ -typedef enum { - LIS3MDL_LOW_POWER_DISABLED = 0x00, /*!< Low Power mode disabled */ - LIS3MDL_LOW_POWER_ENABLED = 0x20 /*!< Low Power mode enabled */ -}LIS3MDL_PM_t; - -/** - * @brief Compass Mode - */ -typedef enum { - LIS3MDL_MD_CONTINOUS_CONVERSION = 0x00, /*!< Continous conversion mode */ - LIS3MDL_MD_SINGLE_CONVERSION = 0x01, /*!< Single conversion mode */ - LIS3MDL_MD_POWER_DOWN = 0x02 /*!< Power down mode */ -}LIS3MDL_MD_t; - - -/** - * @brief Compass Operation Mode for Z axis - */ -typedef enum { - LIS3MDL_OMZ_LOW_POWER = 0x00, /*!< Operation Mode Z low power */ - LIS3MDL_OMZ_MEDIUM_PERFORMANCE = 0x04, /*!< Operation Mode Z medium performance */ - LIS3MDL_OMZ_HIGH_PERFORMANCE = 0x08, /*!< Operation Mode Z high performance */ - LIS3MDL_OMZ_ULTRA_PERFORMANCE = 0x0C /*!< Operation Mode Z ultra performance */ -}LIS3MDL_OMZ_t; - -/** - * @brief Compass Endianness - */ -typedef enum { - LIS3MDL_End_LITTLE = 0x00, /*!< Little Endian: data LSB @ lower address */ - LIS3MDL_End_BIG = 0x02 /*!< Big Endian: data MSB @ lower address */ -}LIS3MDL_End_t; - -/** - * @brief Compass Block Data Update - */ -typedef enum { - LIS3MDL_BDU_CONTINOUS = 0x00, /*!< Continuos Update */ - LIS3MDL_BDU_BLOCKED = 0x40 /*!< Single Update: output registers not updated until MSB and LSB reading */ -}LIS3MDL_BDU_t; - - - - -/** - * @brief Gyroscope configuration structure. - */ -typedef struct { - /** - * @brief Compass Slave Address - */ - LIS3MDL_SAD_t slaveaddress; - /** - * @brief Compass Operation Mode for X and Y axes - */ - LIS3MDL_OMXY_t opmodexy; - /** - * @brief Compass Output Data Rate - */ - LIS3MDL_ODR_t outputdatarate; - /** - * @brief Compass Full Scale - */ - LIS3MDL_FS_t fullscale; - /** - * @brief Compass Low Mode configuration - */ - LIS3MDL_PM_t lowpowermode; - /** - * @brief Compass Mode - */ - LIS3MDL_MD_t mode; - /** - * @brief Compass Operation Mode for Z axis - */ - LIS3MDL_OMZ_t opmodez; - /** - * @brief Compass Endianness - */ - LIS3MDL_End_t endianess; - /** - * @brief Compass Block Data Update - */ - LIS3MDL_BDU_t blockdataupdate; -} LIS3MDL_Config; -/** @} */ -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - - uint8_t lis3mdlReadRegister(I2CDriver *i2cp, uint8_t sad, uint8_t sub, - msg_t* message); - void lis3mdlWriteRegister(I2CDriver *i2cp, uint8_t sad, uint8_t sub, - uint8_t value, msg_t* message); -#ifdef __cplusplus -} -#endif - -#endif /* _LIS3MDL_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/various/devices_lib/mems/lsm303dlhc.c b/firmware/ChibiOS_16/community/os/various/devices_lib/mems/lsm303dlhc.c deleted file mode 100644 index 070c49cc82..0000000000 --- a/firmware/ChibiOS_16/community/os/various/devices_lib/mems/lsm303dlhc.c +++ /dev/null @@ -1,205 +0,0 @@ -/* - Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi - - This file is part of PLAY for ChibiOS/RT. - - PLAY is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - PLAY is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - Special thanks to Giovanni Di Sirio for teachings, his moral support and - friendship. Note that some or every piece of this file could be part of - the ChibiOS project that is intellectual property of Giovanni Di Sirio. - Please refer to ChibiOS/RT license before use this file. - - For suggestion or Bug report - roccomarco.guglielmi@playembedded.org - */ - -/** - * @file lsm303dlhc.c - * @brief LSM303DLHC MEMS interface module through I2C code. - * - * @addtogroup lsm303dlhc - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#include "lsm303dlhc.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Reads a generic sub-register value. - * @pre The I2C interface must be initialized and the driver started. - * - * @param[in] i2cp pointer to the I2C interface - * @param[in] sad slave address without R bit - * @param[in] sub sub-register address - * @param[in] message pointer to message - * @return register value. - */ -uint8_t lsm303dlhcReadRegister(I2CDriver *i2cp, uint8_t sad, uint8_t sub, - msg_t* message) { - - uint8_t txbuf, rxbuf[2]; -#if defined(STM32F103_MCUCONF) - txbuf = LSM303DLHC_SUB_MSB | sub; - if(message != NULL){ - *message = i2cMasterTransmitTimeout(i2cp, sad, &txbuf, 1, rxbuf, 2, - TIME_INFINITE); - } - else{ - i2cMasterTransmitTimeout(i2cp, sad, &txbuf, 1, rxbuf, 2, TIME_INFINITE); - } - return rxbuf[0]; -#else - txbuf = sub; - if(message != NULL){ - *message = i2cMasterTransmitTimeout(i2cp, sad, &txbuf, 1, rxbuf, 1, - TIME_INFINITE); - } - else{ - i2cMasterTransmitTimeout(i2cp, sad, &txbuf, 1, rxbuf, 1, TIME_INFINITE); - } - return rxbuf[0]; -#endif - - -} - -/** - * @brief Writes a value into a register. - * @pre The I2C interface must be initialized and the driver started. - * - * @param[in] i2cp pointer to the I2C interface - * @param[in] sad slave address without R bit - * @param[in] sub sub-register address - * @param[in] value the value to be written - * @param[out] message pointer to message - */ -void lsm303dlhcWriteRegister(I2CDriver *i2cp,uint8_t sad, uint8_t sub, - uint8_t value, msg_t* message) { - - uint8_t txbuf[2]; - uint8_t rxbuf; - if(sad == LSM303DLHC_SAD_ACCEL){ - switch (sub) { - default: - /* Reserved register must not be written, according to the datasheet - * this could permanently damage the device. - */ - chDbgAssert(FALSE, "lsm303dlhcWriteRegister(), reserved register"); - case LSM303DLHC_SUB_ACC_STATUS_REG: - case LSM303DLHC_SUB_ACC_OUT_X_L: - case LSM303DLHC_SUB_ACC_OUT_X_H: - case LSM303DLHC_SUB_ACC_OUT_Y_L: - case LSM303DLHC_SUB_ACC_OUT_Y_H: - case LSM303DLHC_SUB_ACC_OUT_Z_L: - case LSM303DLHC_SUB_ACC_OUT_Z_H: - case LSM303DLHC_SUB_ACC_FIFO_SRC_REG: - case LSM303DLHC_SUB_ACC_INT1_SOURCE: - case LSM303DLHC_SUB_ACC_INT2_SOURCE: - case LSM303DLHC_SUB_ACC_CLICK_SRC: - /* Read only registers cannot be written, the command is ignored.*/ - return; - case LSM303DLHC_SUB_ACC_CTRL_REG1: - case LSM303DLHC_SUB_ACC_CTRL_REG2: - case LSM303DLHC_SUB_ACC_CTRL_REG3: - case LSM303DLHC_SUB_ACC_CTRL_REG4: - case LSM303DLHC_SUB_ACC_CTRL_REG5: - case LSM303DLHC_SUB_ACC_CTRL_REG6: - case LSM303DLHC_SUB_ACC_REFERENCE: - case LSM303DLHC_SUB_ACC_FIFO_CTRL_REG: - case LSM303DLHC_SUB_ACC_INT1_CFG: - case LSM303DLHC_SUB_ACC_INT1_THS: - case LSM303DLHC_SUB_ACC_INT1_DURATION: - case LSM303DLHC_SUB_ACC_INT2_CFG: - case LSM303DLHC_SUB_ACC_INT2_THS: - case LSM303DLHC_SUB_ACC_INT2_DURATION: - case LSM303DLHC_SUB_ACC_CLICK_CFG: - case LSM303DLHC_SUB_ACC_CLICK_THS: - case LSM303DLHC_SUB_ACC_TIME_LIMIT: - case LSM303DLHC_SUB_ACC_TIME_LATENCY: - case LSM303DLHC_SUB_ACC_TIME_WINDOW: - txbuf[0] = sub; - txbuf[1] = value; - if(message != NULL){ - *message = i2cMasterTransmitTimeout(i2cp, sad, txbuf, 2, &rxbuf, 0, - TIME_INFINITE); - } - else{ - i2cMasterTransmitTimeout(i2cp, sad, txbuf, 2, &rxbuf, 0, TIME_INFINITE); - } - break; - } - } - else if(sad == LSM303DLHC_SAD_COMPASS){ - switch (sub) { - default: - /* Reserved register must not be written, according to the datasheet - * this could permanently damage the device. - */ - chDbgAssert(FALSE, "lsm303dlhcWriteRegister(), reserved register"); - case LSM303DLHC_SUB_COMP_OUT_X_H: - case LSM303DLHC_SUB_COMP_OUT_X_L: - case LSM303DLHC_SUB_COMP_OUT_Z_H: - case LSM303DLHC_SUB_COMP_OUT_Z_L: - case LSM303DLHC_SUB_COMP_OUT_Y_H: - case LSM303DLHC_SUB_COMP_OUT_Y_L: - case LSM303DLHC_SUB_COMP_SR_REG: - case LSM303DLHC_SUB_COMP_IRA_REG: - case LSM303DLHC_SUB_COMP_IRB_REG: - case LSM303DLHC_SUB_COMP_IRC_REG: - case LSM303DLHC_SUB_COMP_TEMP_OUT_H: - case LSM303DLHC_SUB_COMP_TEMP_OUT_L: - /* Read only registers cannot be written, the command is ignored.*/ - return; - case LSM303DLHC_SUB_COMP_CRA_REG: - case LSM303DLHC_SUB_COMP_CRB_REG: - case LSM303DLHC_SUB_COMP_MR_REG: - txbuf[0] = sub; - txbuf[1] = value; - if(message != NULL){ - *message = i2cMasterTransmitTimeout(i2cp, sad, txbuf, 2, &rxbuf, 0, - TIME_INFINITE); - } - else{ - i2cMasterTransmitTimeout(i2cp, sad, txbuf, 2, &rxbuf, 0, TIME_INFINITE); - } - break; - } - } -} -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/various/devices_lib/mems/lsm303dlhc.h b/firmware/ChibiOS_16/community/os/various/devices_lib/mems/lsm303dlhc.h deleted file mode 100644 index 46b51bce83..0000000000 --- a/firmware/ChibiOS_16/community/os/various/devices_lib/mems/lsm303dlhc.h +++ /dev/null @@ -1,352 +0,0 @@ -/* - Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi - - This file is part of PLAY for ChibiOS/RT. - - PLAY is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - PLAY is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - Special thanks to Giovanni Di Sirio for teachings, his moral support and - friendship. Note that some or every piece of this file could be part of - the ChibiOS project that is intellectual property of Giovanni Di Sirio. - Please refer to ChibiOS/RT license before use this file. - - For suggestion or Bug report - roccomarco.guglielmi@playembedded.org - */ - -/** - * @file lsm303dlhc.h - * @brief LSM303DLHC MEMS interface module through I2C header. - * - * @addtogroup lsm303dlhc - * @{ - */ - -#ifndef _LSM303DLHC_H_ -#define _LSM303DLHC_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#define LSM303DLHC_ACC_SENS_2G ((float)1671.836f) /*!< Accelerometer sensitivity with 2 G full scale [LSB * s^2 / m] */ -#define LSM303DLHC_ACC_SENS_4G ((float)835.918f) /*!< Accelerometer sensitivity with 4 G full scale [LSB * s^2 / m] */ -#define LSM303DLHC_ACC_SENS_8G ((float)417.959f) /*!< Accelerometer sensitivity with 8 G full scale [LSB * s^2 / m] */ -#define LSM303DLHC_ACC_SENS_16G ((float)208.979f) /*!< Accelerometer sensitivity with 16 G full scale [LSB * s^2 / m] */ - -#define LSM303DLHC_COMP_SENS_XY_1_3GA ((float)1100.0f) /*!< Compass sensitivity with 1.3 GA full scale [LSB / Ga] */ -#define LSM303DLHC_COMP_SENS_XY_1_9GA ((float)855.0f) /*!< Compass sensitivity with 1.9 GA full scale [LSB / Ga] */ -#define LSM303DLHC_COMP_SENS_XY_2_5GA ((float)670.0f) /*!< Compass sensitivity with 2.5 GA full scale [LSB / Ga] */ -#define LSM303DLHC_COMP_SENS_XY_4_0GA ((float)450.0f) /*!< Compass sensitivity with 4.0 GA full scale [LSB / Ga] */ -#define LSM303DLHC_COMP_SENS_XY_4_7GA ((float)400.0f) /*!< Compass sensitivity with 4.7 GA full scale [LSB / Ga] */ -#define LSM303DLHC_COMP_SENS_XY_5_6GA ((float)330.0f) /*!< Compass sensitivity with 5.6 GA full scale [LSB / Ga] */ -#define LSM303DLHC_COMP_SENS_XY_8_1GA ((float)230.0f) /*!< Compass sensitivity with 8.1 GA full scale [LSB / Ga] */ - -#define LSM303DLHC_COMP_SENS_Z_1_3GA ((float)980.0f) /*!< Compass sensitivity with 1.3 GA full scale [LSB / Ga] */ -#define LSM303DLHC_COMP_SENS_Z_1_9GA ((float)765.0f) /*!< Compass sensitivity with 1.9 GA full scale [LSB / Ga] */ -#define LSM303DLHC_COMP_SENS_Z_2_5GA ((float)600.0f) /*!< Compass sensitivity with 2.5 GA full scale [LSB / Ga] */ -#define LSM303DLHC_COMP_SENS_Z_4_0GA ((float)400.0f) /*!< Compass sensitivity with 4.0 GA full scale [LSB / Ga] */ -#define LSM303DLHC_COMP_SENS_Z_4_7GA ((float)355.0f) /*!< Compass sensitivity with 4.7 GA full scale [LSB / Ga] */ -#define LSM303DLHC_COMP_SENS_Z_5_6GA ((float)295.0f) /*!< Compass sensitivity with 5.6 GA full scale [LSB / Ga] */ -#define LSM303DLHC_COMP_SENS_Z_8_1GA ((float)205.0f) /*!< Compass sensitivity with 8.1 GA full scale [LSB / Ga] */ -/** - * @name LSM303DLHC register names - * @{ - */ -/******************************************************************************/ -/* */ -/* LSM303DLHC on board MEMS */ -/* */ -/******************************************************************************/ -/******************* Bit definition for I2C communication *******************/ -#define LSM303DLHC_SAD ((uint8_t)0x7F) /*!< SAD[6:0] Slave Address Mask */ -#define LSM303DLHC_SAD_ACCEL ((uint8_t)0x19) /*!< ACCELEROMETER Slave Address */ -#define LSM303DLHC_SAD_COMPASS ((uint8_t)0x1E) /*!< MAGNETOMETER Slave Address */ - -#define LSM303DLHC_SUB ((uint8_t)0x7F) /*!< SUB[6:0] Sub-registers address Mask */ -#define LSM303DLHC_SUB_0 ((uint8_t)0x01) /*!< bit 0 */ -#define LSM303DLHC_SUB_1 ((uint8_t)0x02) /*!< bit 1 */ -#define LSM303DLHC_SUB_2 ((uint8_t)0x08) /*!< bit 3 */ -#define LSM303DLHC_SUB_4 ((uint8_t)0x10) /*!< bit 4 */ -#define LSM303DLHC_SUB_5 ((uint8_t)0x20) /*!< bit 5 */ -#define LSM303DLHC_SUB_6 ((uint8_t)0x40) /*!< bit 6 */ - -#define LSM303DLHC_SUB_MSB ((uint8_t)0x80) /*!< Multiple data read\write bit */ - -/******** Bit definition for Accelerometer SUB-Registers Addresses **********/ -#define LSM303DLHC_SUB_ACC_CTRL_REG1 ((uint8_t)0x20) /*!< CONTROL REGISTER 1 FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_CTRL_REG2 ((uint8_t)0x21) /*!< CONTROL REGISTER 2 FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_CTRL_REG3 ((uint8_t)0x22) /*!< CONTROL REGISTER 3 FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_CTRL_REG4 ((uint8_t)0x23) /*!< CONTROL REGISTER 4 FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_CTRL_REG5 ((uint8_t)0x24) /*!< CONTROL REGISTER 5 FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_CTRL_REG6 ((uint8_t)0x25) /*!< CONTROL REGISTER 6 FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_REFERENCE ((uint8_t)0x26) /*!< REFERENCE/DATACAPTURE FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_STATUS_REG ((uint8_t)0x27) /*!< STATUS REGISTER FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_OUT_X_L ((uint8_t)0x28) /*!< OUTPUT X-AXIS LOW FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_OUT_X_H ((uint8_t)0x29) /*!< OUTPUT X-AXIS HIGH FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_OUT_Y_L ((uint8_t)0x2A) /*!< OUTPUT Y-AXIS LOW FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_OUT_Y_H ((uint8_t)0x2B) /*!< OUTPUT Y-AXIS HIGH FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_OUT_Z_L ((uint8_t)0x2C) /*!< OUTPUT Z-AXIS LOW FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_OUT_Z_H ((uint8_t)0x2D) /*!< OUTPUT Z-AXIS HIGH FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_FIFO_CTRL_REG ((uint8_t)0x2E) /*!< FIFO CONTROL REGISTER FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_FIFO_SRC_REG ((uint8_t)0x2F) /*!< FIFO SOURCE REGISTER FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_INT1_CFG ((uint8_t)0x30) /*!< INTERRUPT1 CONFIG FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_INT1_SOURCE ((uint8_t)0x31) /*!< INTERRUPT1 SOURCE FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_INT1_THS ((uint8_t)0x32) /*!< INTERRUPT1 THRESHOLD FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_INT1_DURATION ((uint8_t)0x33) /*!< INTERRUPT1 DURATION FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_INT2_CFG ((uint8_t)0x34) /*!< INTERRUPT2 CONFIG FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_INT2_SOURCE ((uint8_t)0x35) /*!< INTERRUPT2 SOURCE FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_INT2_THS ((uint8_t)0x36) /*!< INTERRUPT2 THRESHOLD FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_INT2_DURATION ((uint8_t)0x37) /*!< INTERRUPT2 DURATION FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_CLICK_CFG ((uint8_t)0x38) /*!< CLICK CONFIG FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_CLICK_SRC ((uint8_t)0x39) /*!< CLICK SOURCE FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_CLICK_THS ((uint8_t)0x3A) /*!< CLICK THRESHOLD FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_TIME_LIMIT ((uint8_t)0x3B) /*!< TIME LIMIT FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_TIME_LATENCY ((uint8_t)0x3C) /*!< TIME LATENCY FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_TIME_WINDOW ((uint8_t)0x3D) /*!< TIME WINDOW FOR ACCELEROMETER */ - -/********* Bit definition for Compass SUB-Registers Addresses **********/ -#define LSM303DLHC_SUB_COMP_CRA_REG ((uint8_t)0x00) /*!< CONTROL REGISTER A FOR MAGNETOMETER */ -#define LSM303DLHC_SUB_COMP_CRB_REG ((uint8_t)0x01) /*!< CONTROL REGISTER B FOR MAGNETOMETER */ -#define LSM303DLHC_SUB_COMP_MR_REG ((uint8_t)0x02) /*!< STATUS REGISTER FOR MAGNETOMETER */ -#define LSM303DLHC_SUB_COMP_OUT_X_H ((uint8_t)0x03) /*!< OUTPUT X-AXIS HIGH FOR MAGNETOMETER */ -#define LSM303DLHC_SUB_COMP_OUT_X_L ((uint8_t)0x04) /*!< OUTPUT X-AXIS LOW FOR MAGNETOMETER */ -#define LSM303DLHC_SUB_COMP_OUT_Z_H ((uint8_t)0x05) /*!< OUTPUT Z-AXIS HIGH FOR MAGNETOMETER */ -#define LSM303DLHC_SUB_COMP_OUT_Z_L ((uint8_t)0x06) /*!< OUTPUT Z-AXIS LOW FOR MAGNETOMETER */ -#define LSM303DLHC_SUB_COMP_OUT_Y_H ((uint8_t)0x07) /*!< OUTPUT Y-AXIS HIGH FOR MAGNETOMETER */ -#define LSM303DLHC_SUB_COMP_OUT_Y_L ((uint8_t)0x08) /*!< OUTPUT Y-AXIS LOW FOR MAGNETOMETER */ -#define LSM303DLHC_SUB_COMP_SR_REG ((uint8_t)0x09) /*!< SR REGISTER FOR MAGNETOMETER */ -#define LSM303DLHC_SUB_COMP_IRA_REG ((uint8_t)0x0A) /*!< IR A REGISTER FOR MAGNETOMETER */ -#define LSM303DLHC_SUB_COMP_IRB_REG ((uint8_t)0x0B) /*!< IR B REGISTER FOR MAGNETOMETER */ -#define LSM303DLHC_SUB_COMP_IRC_REG ((uint8_t)0x0C) /*!< IR C REGISTER FOR MAGNETOMETER */ -#define LSM303DLHC_SUB_COMP_TEMP_OUT_H ((uint8_t)0x31) /*!< OUTPUT TEMP HIGH FOR MAGNETOMETER */ -#define LSM303DLHC_SUB_COMP_TEMP_OUT_L ((uint8_t)0x32) /*!< OUTPUT TEMP LOW FOR MAGNETOMETER */ - -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @name Accelerometer data structures and types - * @{ - */ - -/** - * @brief Accelerometer Output Data Rate - */ -typedef enum -{ - LSM303DLHC_ACC_ODR_PD = 0x00, /*!< Power down */ - LSM303DLHC_ACC_ODR_1Hz = 0x10, /*!< Output Data Rate = 1 Hz */ - LSM303DLHC_ACC_ODR_10Hz = 0x20, /*!< Output Data Rate = 10 Hz */ - LSM303DLHC_ACC_ODR_25Hz = 0x30, /*!< Output Data Rate = 25 Hz */ - LSM303DLHC_ACC_ODR_50Hz = 0x40, /*!< Output Data Rate = 50 Hz */ - LSM303DLHC_ACC_ODR_100Hz = 0x50, /*!< Output Data Rate = 100 Hz */ - LSM303DLHC_ACC_ODR_200Hz = 0x60, /*!< Output Data Rate = 200 Hz */ - LSM303DLHC_ACC_ODR_400Hz = 0x70, /*!< Output Data Rate = 400 Hz */ - LSM303DLHC_ACC_ODR_1620Hz = 0x80, /*!< Output Data Rate = 1620 Hz Low Power mode only */ - LSM303DLHC_ACC_ODR_1344Hz = 0x90 /*!< Output Data Rate = 1344 Hz in Normal mode and 5376 Hz in Low Power Mode */ -}LSM303DLHC_ACC_ODR_t; - -/** - * @brief Accelerometer Power Mode - */ -typedef enum -{ - LSM303DLHC_ACC_PM_NORMAL = 0x00, /*!< Normal mode enabled */ - LSM303DLHC_ACC_PM_LOW_POWER = 0x08 /*!< Low Power mode enabled */ -}LSM303DLHC_ACC_PM_t; - -/** - * @brief Accelerometer Full Scale - */ -typedef enum -{ - LSM303DLHC_ACC_FS_2G = 0x00, /*!< ±2 g m/s^2 */ - LSM303DLHC_ACC_FS_4G = 0x10, /*!< ±4 g m/s^2 */ - LSM303DLHC_ACC_FS_8G = 0x20, /*!< ±8 g m/s^2 */ - LSM303DLHC_ACC_FS_16G = 0x30 /*!< ±16 g m/s^2 */ -}LSM303DLHC_ACC_FS_t; - -/** - * @brief Accelerometer Axes Enabling - */ -typedef enum{ - LSM303DLHC_ACC_AE_DISABLED = 0x00, /*!< Axes all disabled */ - LSM303DLHC_ACC_AE_X = 0x01, /*!< Only X-axis enabled */ - LSM303DLHC_ACC_AE_Y = 0x02, /*!< Only Y-axis enabled */ - LSM303DLHC_ACC_AE_XY = 0x03, /*!< X & Y axes enabled */ - LSM303DLHC_ACC_AE_Z = 0x04, /*!< Only Z-axis enabled */ - LSM303DLHC_ACC_AE_XZ = 0x05, /*!< X & Z axes enabled */ - LSM303DLHC_ACC_AE_YZ = 0x06, /*!< Y & Z axes enabled */ - LSM303DLHC_ACC_AE_XYZ = 0x07 /*!< All axes enabled */ -}LSM303DLHC_ACC_AE_t; - -/** - * @brief Accelerometer Block Data Update - */ -typedef enum -{ - LSM303DLHC_ACC_BDU_CONTINOUS = 0x00, /*!< Continuos Update */ - LSM303DLHC_ACC_BDU_BLOCKED = 0x80 /*!< Single Update: output registers not updated until MSB and LSB reading */ -}LSM303DLHC_ACC_BDU_t; - -/** - * @brief Accelerometer Endianness - */ -typedef enum -{ - LSM303DLHC_ACC_End_LITTLE = 0x00, /*!< Little Endian: data LSB @ lower address */ - LSM303DLHC_ACC_End_BIG = 0x40 /*!< Big Endian: data MSB @ lower address */ -}LSM303DLHC_ACC_End_t; - -/** - * @brief Accelerometer High Resolution mode - */ -typedef enum -{ - LSM303DLHC_ACC_HR_Enabled = 0x08, /*!< High resolution output mode enabled */ - LSM303DLHC_ACC_HR_Disabled = 0x00 /*!< High resolution output mode disabled */ -}LSM303DLHC_ACC_HR_t; - -/** - * @brief Accelerometer configuration structure. - */ -typedef struct { - /** - * @brief Accelerometer fullscale value. - */ - LSM303DLHC_ACC_FS_t fullscale; - /** - * @brief Accelerometer power mode selection. - */ - LSM303DLHC_ACC_PM_t powermode; - /** - * @brief Accelerometer output data rate selection. - */ - LSM303DLHC_ACC_ODR_t outputdatarate; - /** - * @brief Accelerometer axes enabling. - */ - LSM303DLHC_ACC_AE_t axesenabling; - /** - * @brief Accelerometer block data update. - */ - LSM303DLHC_ACC_BDU_t blockdataupdate; - /** - * @brief Accelerometer block data update. - */ - LSM303DLHC_ACC_HR_t highresmode; -} LSM303DLHC_ACC_Config; -/** @} */ - - -/** - * @name Compass data types - * @{ - */ - -/** - * @brief Compass Output Data Rate - */ -typedef enum -{ - LSM303DLHC_COMP_ODR_0_75_Hz = 0x00, /*!< Output Data Rate = 0.75 Hz */ - LSM303DLHC_COMP_ODR_1_5_Hz = 0x04, /*!< Output Data Rate = 1.5 Hz */ - LSM303DLHC_COMP_ODR_3_0_Hz = 0x08, /*!< Output Data Rate = 3 Hz */ - LSM303DLHC_COMP_ODR_7_5_Hz = 0x0C, /*!< Output Data Rate = 7.5 Hz */ - LSM303DLHC_COMP_ODR_15_Hz = 0x10, /*!< Output Data Rate = 15 Hz */ - LSM303DLHC_COMP_ODR_30_Hz = 0x14, /*!< Output Data Rate = 30 Hz */ - LSM303DLHC_COMP_ODR_75_Hz = 0x18, /*!< Output Data Rate = 75 Hz */ - LSM303DLHC_COMP_ODR_220_Hz = 0x1C /*!< Output Data Rate = 220 Hz */ -}LSM303DLHC_COMP_ODR_t; - - -/** - * @brief Compass Full Scale - */ -typedef enum -{ - LSM303DLHC_COMP_FS_1_3_GA = 0x20, /*!< Full scale = ±1.3 Gauss */ - LSM303DLHC_COMP_FS_1_9_GA = 0x40, /*!< Full scale = ±1.9 Gauss */ - LSM303DLHC_COMP_FS_2_5_GA = 0x60, /*!< Full scale = ±2.5 Gauss */ - LSM303DLHC_COMP_FS_4_0_GA = 0x80, /*!< Full scale = ±4.0 Gauss */ - LSM303DLHC_COMP_FS_4_7_GA = 0xA0, /*!< Full scale = ±4.7 Gauss */ - LSM303DLHC_COMP_FS_5_6_GA = 0xC0, /*!< Full scale = ±5.6 Gauss */ - LSM303DLHC_COMP_FS_8_1_GA = 0xE0 /*!< Full scale = ±8.1 Gauss */ -}LSM303DLHC_COMP_FS_t; - - -/** - * @brief Compass Working Mode - */ -typedef enum -{ - LSM303DLHC_COMP_WM_CONTINUOS = 0x00, /*!< Continuous-Conversion Mode */ - LSM303DLHC_COMP_WM_BLOCKED = 0x01, /*!< Single-Conversion Mode */ - LSM303DLHC_COMP_WM_SLEEP = 0x02 /*!< Sleep Mode */ -}LSM303DLHC_COMP_WM_t; - -/** - * @brief Compass configuration structure. - */ -typedef struct { - /** - * @brief Compass fullscale value. - */ - LSM303DLHC_COMP_FS_t fullscale; - /** - * @brief Compass output data rate selection. - */ - LSM303DLHC_COMP_ODR_t outputdatarate; - /** - * @brief Compass working mode. - */ - LSM303DLHC_COMP_WM_t workingmode; -} LSM303DLHC_COMP_Config; -/** @} */ -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - - uint8_t lsm303dlhcReadRegister(I2CDriver *i2cp, uint8_t sad, uint8_t sub, - msg_t* message); - void lsm303dlhcWriteRegister(I2CDriver *i2cp,uint8_t sad, uint8_t sub, - uint8_t value, msg_t* message); - -#ifdef __cplusplus -} -#endif -#endif /* _LSM303DLHC_H_ */ -/** @} */ - diff --git a/firmware/ChibiOS_16/community/os/various/devices_lib/mems/lsm6ds0.c b/firmware/ChibiOS_16/community/os/various/devices_lib/mems/lsm6ds0.c deleted file mode 100644 index da67f126fc..0000000000 --- a/firmware/ChibiOS_16/community/os/various/devices_lib/mems/lsm6ds0.c +++ /dev/null @@ -1,184 +0,0 @@ -/* - Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi - - This file is part of PLAY for ChibiOS/RT. - - PLAY is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - PLAY is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - Special thanks to Giovanni Di Sirio for teachings, his moral support and - friendship. Note that some or every piece of this file could be part of - the ChibiOS project that is intellectual property of Giovanni Di Sirio. - Please refer to ChibiOS/RT license before use this file. - - For suggestion or Bug report - roccomarco.guglielmi@playembedded.org - */ - -/** - * @file lsm6ds0.c - * @brief LSM6DS0 MEMS interface module through I2C code. - * - * @addtogroup lsm6ds0 - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#include "lsm6ds0.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Reads a generic sub-register value. - * @pre The I2C interface must be initialized and the driver started. - * - * @param[in] i2cp pointer to the I2C interface - * @param[in] sad slave address without R bit - * @param[in] sub sub-register address - * @param[in] message pointer to message - * @return register value. - */ -uint8_t lsm6ds0ReadRegister(I2CDriver *i2cp, uint8_t sad, uint8_t sub, - msg_t* message) { - - uint8_t txbuf, rxbuf[2]; -#if defined(STM32F103_MCUCONF) - txbuf = LSM303DLHC_SUB_MSB | sub; - if(message != NULL){ - *message = i2cMasterTransmitTimeout(i2cp, sad, &txbuf, 1, rxbuf, 2, - TIME_INFINITE); - } - else{ - i2cMasterTransmitTimeout(i2cp, sad, &txbuf, 1, rxbuf, 2, TIME_INFINITE); - } - return rxbuf[0]; -#else - txbuf = sub; - if(message != NULL){ - *message = i2cMasterTransmitTimeout(i2cp, sad, &txbuf, 1, rxbuf, 1, - TIME_INFINITE); - } - else{ - i2cMasterTransmitTimeout(i2cp, sad, &txbuf, 1, rxbuf, 1, TIME_INFINITE); - } - return rxbuf[0]; -#endif -} - -/** - * @brief Writes a value into a register. - * @pre The I2C interface must be initialized and the driver started. - * - * @param[in] i2cp pointer to the I2C interface - * @param[in] sad slave address without R bit - * @param[in] sub sub-register address - * @param[in] value the value to be written - * @param[out] message pointer to message - */ -void lsm6ds0WriteRegister(I2CDriver *i2cp, uint8_t sad, uint8_t sub, - uint8_t value, msg_t* message) { - - uint8_t txbuf[2]; - uint8_t rxbuf; - switch (sub) { - default: - /* Reserved register must not be written, according to the datasheet - * this could permanently damage the device. - */ - chDbgAssert(FALSE, "lsm6ds0WriteRegister(), reserved register"); - case LSM6DS0_SUB_WHO_AM_I: - case LSM6DS0_SUB_INT_GEN_SRC_G: - case LSM6DS0_SUB_OUT_TEMP_L: - case LSM6DS0_SUB_OUT_TEMP_H: - case LSM6DS0_SUB_STATUS_REG1: - case LSM6DS0_SUB_OUT_X_L_G: - case LSM6DS0_SUB_OUT_X_H_G: - case LSM6DS0_SUB_OUT_Y_L_G: - case LSM6DS0_SUB_OUT_Y_H_G: - case LSM6DS0_SUB_OUT_Z_L_G: - case LSM6DS0_SUB_OUT_Z_H_G: - case LSM6DS0_SUB_INT_GEN_SRC_XL: - case LSM6DS0_SUB_STATUS_REG2: - case LSM6DS0_SUB_OUT_X_L_XL: - case LSM6DS0_SUB_OUT_X_H_XL: - case LSM6DS0_SUB_OUT_Y_L_XL: - case LSM6DS0_SUB_OUT_Y_H_XL: - case LSM6DS0_SUB_OUT_Z_L_XL: - case LSM6DS0_SUB_OUT_Z_H_XL: - case LSM6DS0_SUB_FIFO_SRC: - /* Read only registers cannot be written, the command is ignored.*/ - return; - case LSM6DS0_SUB_ACT_THS: - case LSM6DS0_SUB_ACT_DUR: - case LSM6DS0_SUB_INT_GEN_CFG_XL: - case LSM6DS0_SUB_INT_GEN_THS_X_XL: - case LSM6DS0_SUB_INT_GEN_THS_Y_XL: - case LSM6DS0_SUB_INT_GEN_THS_Z_XL: - case LSM6DS0_SUB_INT_GEN_DUR_XL: - case LSM6DS0_SUB_REFERENCE_G: - case LSM6DS0_SUB_INT_CTRL: - case LSM6DS0_SUB_CTRL_REG1_G: - case LSM6DS0_SUB_CTRL_REG2_G: - case LSM6DS0_SUB_CTRL_REG3_G: - case LSM6DS0_SUB_ORIENT_CFG_G: - case LSM6DS0_SUB_CTRL_REG4: - case LSM6DS0_SUB_CTRL_REG5_XL: - case LSM6DS0_SUB_CTRL_REG6_XL: - case LSM6DS0_SUB_CTRL_REG7_XL: - case LSM6DS0_SUB_CTRL_REG8: - case LSM6DS0_SUB_CTRL_REG9: - case LSM6DS0_SUB_CTRL_REG10: - case LSM6DS0_SUB_FIFO_CTRL: - case LSM6DS0_SUB_INT_GEN_CFG_G: - case LSM6DS0_SUB_INT_GEN_THS_XH_G: - case LSM6DS0_SUB_INT_GEN_THS_XL_G: - case LSM6DS0_SUB_INT_GEN_THS_YH_G: - case LSM6DS0_SUB_INT_GEN_THS_YL_G: - case LSM6DS0_SUB_INT_GEN_THS_ZH_G: - case LSM6DS0_SUB_INT_GEN_THS_ZL_G: - case LSM6DS0_SUB_INT_GEN_DUR_G: - txbuf[0] = sub; - txbuf[1] = value; - if(message != NULL){ - *message = i2cMasterTransmitTimeout(i2cp, sad, txbuf, 2, &rxbuf, 0, - TIME_INFINITE); - } - else{ - i2cMasterTransmitTimeout(i2cp, sad, txbuf, 2, &rxbuf, 0, TIME_INFINITE); - } - break; - } -} - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/various/devices_lib/mems/lsm6ds0.h b/firmware/ChibiOS_16/community/os/various/devices_lib/mems/lsm6ds0.h deleted file mode 100644 index 57e2057798..0000000000 --- a/firmware/ChibiOS_16/community/os/various/devices_lib/mems/lsm6ds0.h +++ /dev/null @@ -1,482 +0,0 @@ -/* - Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi - - This file is part of PLAY for ChibiOS/RT. - - PLAY is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - PLAY is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - Special thanks to Giovanni Di Sirio for teachings, his moral support and - friendship. Note that some or every piece of this file could be part of - the ChibiOS project that is intellectual property of Giovanni Di Sirio. - Please refer to ChibiOS/RT license before use this file. - - For suggestion or Bug report - roccomarco.guglielmi@playembedded.org - */ - -/** - * @file lsm6ds0.h - * @brief LSM6DS0 MEMS interface module header. - * - * @{ - */ - -#ifndef _LSM6DS0_H_ -#define _LSM6DS0_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#define LSM6DS0_ACC_SENS_2G ((float)1671.095f) /*!< Accelerometer sensitivity with 2 G full scale [LSB * s^2 / m] */ -#define LSM6DS0_ACC_SENS_4G ((float)835.547f) /*!< Accelerometer sensitivity with 4 G full scale [LSB * s^2 / m] */ -#define LSM6DS0_ACC_SENS_8G ((float)417.774) /*!< Accelerometer sensitivity with 8 G full scale [LSB * s^2 / m] */ -#define LSM6DS0_ACC_SENS_16G ((float)139.258f) /*!< Accelerometer sensitivity with 16 G full scale [LSB * s^2 / m] */ - -#define LSM6DS0_GYRO_SENS_245DPS ((float)114.286f) /*!< Gyroscope sensitivity with 245 dps full scale [LSB * s / °] */ -#define LSM6DS0_GYRO_SENS_500DPS ((float)57.143f) /*!< Gyroscope sensitivity with 500 dps full scale [LSB * s / °] */ -#define LSM6DS0_GYRO_SENS_2000DPS ((float)14.286f) /*!< Gyroscope sensitivity with 2000 dps full scale [LSB * s / °] */ -/** - * @name LSM6DS0 register names - * @{ - */ -/******************************************************************************/ -/* */ -/* LSM6DS0 on board MEMS */ -/* */ -/******************************************************************************/ -/***************** Bit definition for I2C/SPI communication *****************/ -#define LSM6DS0_SUB ((uint8_t)0x7F) /*!< SUB[6:0] Sub-registers address Mask */ -#define LSM6DS0_SUB_0 ((uint8_t)0x01) /*!< bit 0 */ -#define LSM6DS0_SUB_1 ((uint8_t)0x02) /*!< bit 1 */ -#define LSM6DS0_SUB_2 ((uint8_t)0x08) /*!< bit 3 */ -#define LSM6DS0_SUB_4 ((uint8_t)0x10) /*!< bit 4 */ -#define LSM6DS0_SUB_5 ((uint8_t)0x20) /*!< bit 5 */ -#define LSM6DS0_SUB_6 ((uint8_t)0x40) /*!< bit 6 */ - -#define LSM6DS0_SUB_MSB ((uint8_t)0x80) /*!< Multiple data read\write bit */ - -/***************** Bit definition for Registers Addresses *******************/ -#define LSM6DS0_SUB_ACT_THS ((uint8_t)0x04) /*!< Activity threshold register */ -#define LSM6DS0_SUB_ACT_DUR ((uint8_t)0x05) /*!< Inactivity duration register */ -#define LSM6DS0_SUB_INT_GEN_CFG_XL ((uint8_t)0x06) /*!< Accelerometer interrupt generator configuration register */ -#define LSM6DS0_SUB_INT_GEN_THS_X_XL ((uint8_t)0x07) /*!< Accelerometer X-axis interrupt threshold register */ -#define LSM6DS0_SUB_INT_GEN_THS_Y_XL ((uint8_t)0x08) /*!< Accelerometer Y-axis interrupt threshold register */ -#define LSM6DS0_SUB_INT_GEN_THS_Z_XL ((uint8_t)0x09) /*!< Accelerometer Z-axis interrupt threshold register */ -#define LSM6DS0_SUB_INT_GEN_DUR_XL ((uint8_t)0x0A) /*!< Accelerometer interrupt duration register */ -#define LSM6DS0_SUB_REFERENCE_G ((uint8_t)0x0B) /*!< Gyroscope reference value register for digital high-pass filter */ -#define LSM6DS0_SUB_INT_CTRL ((uint8_t)0x0C) /*!< INT pin control register */ -#define LSM6DS0_SUB_WHO_AM_I ((uint8_t)0x0F) /*!< Who_AM_I register */ -#define LSM6DS0_SUB_CTRL_REG1_G ((uint8_t)0x10) /*!< Gyroscope control register 1 */ -#define LSM6DS0_SUB_CTRL_REG2_G ((uint8_t)0x11) /*!< Gyroscope control register 2 */ -#define LSM6DS0_SUB_CTRL_REG3_G ((uint8_t)0x12) /*!< Gyroscope control register 3 */ -#define LSM6DS0_SUB_ORIENT_CFG_G ((uint8_t)0x13) /*!< Gyroscope sign and orientation register */ -#define LSM6DS0_SUB_INT_GEN_SRC_G ((uint8_t)0x14) /*!< Gyroscope interrupt source register */ -#define LSM6DS0_SUB_OUT_TEMP_L ((uint8_t)0x15) /*!< Temperature data output low register */ -#define LSM6DS0_SUB_OUT_TEMP_H ((uint8_t)0x16) /*!< Temperature data output high register */ -#define LSM6DS0_SUB_STATUS_REG1 ((uint8_t)0x17) /*!< Status register 1 */ -#define LSM6DS0_SUB_OUT_X_L_G ((uint8_t)0x18) /*!< Gyroscope X-axis low output register */ -#define LSM6DS0_SUB_OUT_X_H_G ((uint8_t)0x19) /*!< Gyroscope X-axis high output register */ -#define LSM6DS0_SUB_OUT_Y_L_G ((uint8_t)0x1A) /*!< Gyroscope Y-axis low output register */ -#define LSM6DS0_SUB_OUT_Y_H_G ((uint8_t)0x1B) /*!< Gyroscope Y-axis high output register */ -#define LSM6DS0_SUB_OUT_Z_L_G ((uint8_t)0x1C) /*!< Gyroscope Z-axis low output register */ -#define LSM6DS0_SUB_OUT_Z_H_G ((uint8_t)0x1D) /*!< Gyroscope Z-axis high output register */ -#define LSM6DS0_SUB_CTRL_REG4 ((uint8_t)0x1E) /*!< Control register 4 */ -#define LSM6DS0_SUB_CTRL_REG5_XL ((uint8_t)0x1F) /*!< Accelerometer Control Register 5 */ -#define LSM6DS0_SUB_CTRL_REG6_XL ((uint8_t)0x20) /*!< Accelerometer Control Register 6 */ -#define LSM6DS0_SUB_CTRL_REG7_XL ((uint8_t)0x21) /*!< Accelerometer Control Register 7 */ -#define LSM6DS0_SUB_CTRL_REG8 ((uint8_t)0x22) /*!< Control register 8 */ -#define LSM6DS0_SUB_CTRL_REG9 ((uint8_t)0x23) /*!< Control register 9 */ -#define LSM6DS0_SUB_CTRL_REG10 ((uint8_t)0x24) /*!< Control register 10 */ -#define LSM6DS0_SUB_INT_GEN_SRC_XL ((uint8_t)0x26) /*!< Accelerometer interrupt source register */ -#define LSM6DS0_SUB_STATUS_REG2 ((uint8_t)0x27) /*!< Status register */ -#define LSM6DS0_SUB_OUT_X_L_XL ((uint8_t)0x28) /*!< Accelerometer X-axis low output register */ -#define LSM6DS0_SUB_OUT_X_H_XL ((uint8_t)0x29) /*!< Accelerometer X-axis high output register */ -#define LSM6DS0_SUB_OUT_Y_L_XL ((uint8_t)0x2A) /*!< Accelerometer Y-axis low output register */ -#define LSM6DS0_SUB_OUT_Y_H_XL ((uint8_t)0x2B) /*!< Accelerometer Y-axis high output register */ -#define LSM6DS0_SUB_OUT_Z_L_XL ((uint8_t)0x2C) /*!< Accelerometer Z-axis low output register */ -#define LSM6DS0_SUB_OUT_Z_H_XL ((uint8_t)0x2D) /*!< Accelerometer Z-axis high output register */ -#define LSM6DS0_SUB_FIFO_CTRL ((uint8_t)0x2E) /*!< FIFO control register */ -#define LSM6DS0_SUB_FIFO_SRC ((uint8_t)0x2F) /*!< FIFO status control register */ -#define LSM6DS0_SUB_INT_GEN_CFG_G ((uint8_t)0x30) /*!< Gyroscope interrupt generator configuration register */ -#define LSM6DS0_SUB_INT_GEN_THS_XH_G ((uint8_t)0x31) /*!< Gyroscope X-axis low interrupt generator threshold registers */ -#define LSM6DS0_SUB_INT_GEN_THS_XL_G ((uint8_t)0x32) /*!< Gyroscope X-axis high interrupt generator threshold registers */ -#define LSM6DS0_SUB_INT_GEN_THS_YH_G ((uint8_t)0x33) /*!< Gyroscope Y-axis low interrupt generator threshold registers */ -#define LSM6DS0_SUB_INT_GEN_THS_YL_G ((uint8_t)0x34) /*!< Gyroscope Y-axis high interrupt generator threshold registers */ -#define LSM6DS0_SUB_INT_GEN_THS_ZH_G ((uint8_t)0x35) /*!< Gyroscope Z-axis low interrupt generator threshold registers */ -#define LSM6DS0_SUB_INT_GEN_THS_ZL_G ((uint8_t)0x36) /*!< Gyroscope Z-axis high interrupt generator threshold registers */ -#define LSM6DS0_SUB_INT_GEN_DUR_G ((uint8_t)0x37) /*!< Gyroscope interrupt generator duration register */ - -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @name Generic LSM6DS0 data structures and types - * @{ - */ - -/** - * @brief Accelerometer and Gyroscope Slave Address - */ -typedef enum { - LSM6DS0_SAD_GND = 0x6A, /*!< LSM6DS0 Slave Address when SA1 is to GND */ - LSM6DS0_SAD_VCC = 0x6B /*!< LSM6DS0 Slave Address when SA1 is to VCC */ -}LSM6DS0_SAD_t; - -/** - * @brief Accelerometer and Gyroscope Block Data Update - */ -typedef enum -{ - LSM6DS0_BDU_CONTINOUS = 0x00, /*!< Continuos Update */ - LSM6DS0_BDU_BLOCKED = 0x40 /*!< Single Update: output registers not updated until MSB and LSB reading */ -}LSM6DS0_BDU_t; - -/** - * @brief Accelerometer and Gyroscope Endianness - */ -typedef enum -{ - LSM6DS0_END_LITTLE = 0x00, /*!< Little Endian: data LSB @ lower address */ - LSM6DS0_END_BIG = 0x20 /*!< Big Endian: data MSB @ lower address */ -}LSM6DS0_END_t; -/** @} */ - -/** - * @name Accelerometer data structures and types - * @{ - */ - -/** - * @brief Accelerometer Decimation Mode - */ -typedef enum { - LSM6DS0_ACC_DEC_DISABLED = 0x00, /*!< NO decimation */ - LSM6DS0_ACC_DEC_X2 = 0x40, /*!< Decimation update every 2 sample */ - LSM6DS0_ACC_DEC_X4 = 0x80, /*!< Decimation update every 4 sample */ - LSM6DS0_ACC_DEC_X8 = 0xC0 /*!< Decimation update every 8 sample */ -}LSM6DS0_ACC_DEC_t; - -/** - * @brief Accelerometer Axes Enabling - */ -typedef enum{ - LSM6DS0_ACC_AE_DISABLED = 0x00, /*!< Axes all disabled */ - LSM6DS0_ACC_AE_X = 0x08, /*!< Only X-axis enabled */ - LSM6DS0_ACC_AE_Y = 0x10, /*!< Only Y-axis enabled */ - LSM6DS0_ACC_AE_XY = 0x18, /*!< X & Y axes enabled */ - LSM6DS0_ACC_AE_Z = 0x20, /*!< Only Z-axis enabled */ - LSM6DS0_ACC_AE_XZ = 0x28, /*!< X & Z axes enabled */ - LSM6DS0_ACC_AE_YZ = 0x30, /*!< Y & Z axes enabled */ - LSM6DS0_ACC_AE_XYZ = 0x38 /*!< All axes enabled */ -}LSM6DS0_ACC_AE_t; - -/** - * @brief Accelerometer Output Data Rate - */ -typedef enum { - LSM6DS0_ACC_ODR_PD = 0x00, /*!< Power down */ - LSM6DS0_ACC_ODR_10Hz = 0x20, /*!< Output Data Rate = 10 Hz */ - LSM6DS0_ACC_ODR_50Hz = 0x40, /*!< Output Data Rate = 50 Hz */ - LSM6DS0_ACC_ODR_119Hz = 0x60, /*!< Output Data Rate = 119 Hz */ - LSM6DS0_ACC_ODR_238Hz = 0x80, /*!< Output Data Rate = 238 Hz */ - LSM6DS0_ACC_ODR_476Hz = 0xA0, /*!< Output Data Rate = 476 Hz */ - LSM6DS0_ACC_ODR_952Hz = 0xC0 /*!< Output Data Rate = 952 Hz */ -}LSM6DS0_ACC_ODR_t; - -/** - * @brief Accelerometer Full Scale - */ -typedef enum { - LSM6DS0_ACC_FS_2G = 0x00, /*!< ±2 g m/s^2 */ - LSM6DS0_ACC_FS_4G = 0x10, /*!< ±4 g m/s^2 */ - LSM6DS0_ACC_FS_8G = 0x18, /*!< ±8 g m/s^2 */ - LSM6DS0_ACC_FS_16G = 0x08 /*!< ±16 g m/s^2 */ -}LSM6DS0_ACC_FS_t; - -/** - * @brief Accelerometer Antialiasing filter Bandwidth Selection - */ -typedef enum { - LSM6DS0_ACC_BW_408Hz = 0x00, /*!< AA filter bandwidth = 408 Hz */ - LSM6DS0_ACC_BW_211Hz = 0x01, /*!< AA filter bandwidth = 211 Hz */ - LSM6DS0_ACC_BW_105Hz = 0x02, /*!< AA filter bandwidth = 105 Hz */ - LSM6DS0_ACC_BW_50Hz = 0x03, /*!< AA filter bandwidth = 50 Hz */ - LSM6DS0_ACC_BW_ACCORDED = 0x04, /*!< AA filter bandwidth chosen by ODR selection */ -}LSM6DS0_ACC_BW_t; - -/** - * @brief Accelerometer High Resolution mode - */ -typedef enum -{ - LSM6DS0_ACC_HR_Disabled = 0x00, /*!< High resolution output mode disabled, FDS bypassed */ - LSM6DS0_ACC_HR_EN_9 = 0xC4, /*!< High resolution output mode enabled, LP cutoff = ODR/9, FDS enabled */ - LSM6DS0_ACC_HR_EN_50 = 0x84, /*!< High resolution output mode enabled, LP cutoff = ODR/50, FDS enabled */ - LSM6DS0_ACC_HR_EN_100 = 0xA4, /*!< High resolution output mode enabled, LP cutoff = ODR/100, FDS enabled */ - LSM6DS0_ACC_HR_EN_400 = 0xE4, /*!< High resolution output mode enabled, LP cutoff = ODR/400, FDS enabled */ -}LSM6DS0_ACC_HR_t; - -/** - * @brief HP filter for interrupt - */ -typedef enum -{ - LSM6DS0_ACC_HPIS1_BYPASSED = 0x00, /*!< High-pass filter bypassed */ - LSM6DS0_ACC_HPIS1_ENABLED = 0x01 /*!< High-pass filter enabled for accelerometer interrupt function on interrupt */ -}LSM6DS0_ACC_HPIS1_t; - -/** - * @brief Accelerometer configuration structure. - */ -typedef struct { - - /** - * @brief LSM6DS0 Slave Address - */ - LSM6DS0_SAD_t slaveaddress; - /** - * @brief Accelerometer Decimation Mode - */ - LSM6DS0_ACC_DEC_t decimation; - /** - * @brief Accelerometer Output Data Rate - */ - LSM6DS0_ACC_ODR_t outputdatarate; - /** - * @brief Accelerometer Antialiasing filter Bandwidth Selection - */ - LSM6DS0_ACC_BW_t bandwidth; - /** - * @brief Accelerometer Full Scale - */ - LSM6DS0_ACC_FS_t fullscale; - /** - * @brief Accelerometer Axes Enabling - */ - LSM6DS0_ACC_AE_t axesenabling; - /** - * @brief Accelerometer High Resolution mode - */ - LSM6DS0_ACC_HR_t highresmode; - /** - * @brief HP filter for interrupt - */ - LSM6DS0_ACC_HPIS1_t hpfirq; - /** - * @brief LSM6DS0 Endianness - */ - LSM6DS0_END_t endianess; - /** - * @brief LSM6DS0 Block Data Update - */ - LSM6DS0_BDU_t blockdataupdate; -} LSM6DS0_ACC_Config; -/** @} */ - -/** - * @name Gyroscope data structures and types - * @{ - */ - -/** - * @brief Gyroscope Output Data Rate - */ -typedef enum { - LSM6DS0_GYRO_ODR_PD = 0x00, /*!< Power down */ - LSM6DS0_GYRO_ODR_14_9Hz_CO_5Hz = 0x20, /*!< Output Data Rate = 14.9 Hz, CutOff = 5Hz */ - LSM6DS0_GYRO_ODR_59_5Hz_CO_16Hz = 0x40, /*!< Output Data Rate = 59.5 Hz, CutOff = 16Hz */ - LSM6DS0_GYRO_ODR_119Hz_CO_14Hz = 0x60, /*!< Output Data Rate = 119 Hz, CutOff = 14Hz */ - LSM6DS0_GYRO_ODR_119Hz_CO_31Hz = 0x61, /*!< Output Data Rate = 119 Hz, CutOff = 31Hz */ - LSM6DS0_GYRO_ODR_238Hz_CO_14Hz = 0x80, /*!< Output Data Rate = 238 Hz, CutOff = 14Hz */ - LSM6DS0_GYRO_ODR_238Hz_CO_29Hz = 0x81, /*!< Output Data Rate = 328 Hz, CutOff = 29Hz */ - LSM6DS0_GYRO_ODR_238Hz_CO_63Hz = 0x82, /*!< Output Data Rate = 238 Hz, CutOff = 63Hz */ - LSM6DS0_GYRO_ODR_238Hz_CO_78Hz = 0x83, /*!< Output Data Rate = 476 Hz, CutOff = 78Hz */ - LSM6DS0_GYRO_ODR_476Hz_CO_21Hz = 0xA0, /*!< Output Data Rate = 476 Hz, CutOff = 21Hz */ - LSM6DS0_GYRO_ODR_476Hz_CO_28Hz = 0xA1, /*!< Output Data Rate = 238 Hz, CutOff = 28Hz */ - LSM6DS0_GYRO_ODR_476Hz_CO_57Hz = 0xA2, /*!< Output Data Rate = 476 Hz, CutOff = 57Hz */ - LSM6DS0_GYRO_ODR_476Hz_CO_100Hz = 0xA3, /*!< Output Data Rate = 476 Hz, CutOff = 100Hz */ - LSM6DS0_GYRO_ODR_952Hz_CO_33Hz = 0xC0, /*!< Output Data Rate = 952 Hz, CutOff = 33Hz */ - LSM6DS0_GYRO_ODR_952Hz_CO_40Hz = 0xC1, /*!< Output Data Rate = 952 Hz, CutOff = 40Hz */ - LSM6DS0_GYRO_ODR_952Hz_CO_58Hz = 0xC2, /*!< Output Data Rate = 952 Hz, CutOff = 58Hz */ - LSM6DS0_GYRO_ODR_952Hz_CO_100Hz = 0xC3 /*!< Output Data Rate = 952 Hz, CutOff = 100Hz */ -}LSM6DS0_GYRO_ODR_t; - -/** - * @brief Gyroscope Full Scale - */ -typedef enum { - LSM6DS0_GYRO_FS_245DSP = 0x00, /*!< ±245 degrees per second */ - LSM6DS0_GYRO_FS_500DSP = 0x08, /*!< ±500 degrees per second */ - LSM6DS0_GYRO_FS_2000DSP = 0x18 /*!< ±2000 degrees per second */ -}LSM6DS0_GYRO_FS_t; - -/** - * @brief Gyroscope Output Selection - */ -typedef enum { - LSM6DS0_GYRO_OUT_SEL_BYPASS = 0x00, /*!< Output not filtered */ - LSM6DS0_GYRO_OUT_SEL_FILTERED = 0x01, /*!< Output filtered */ -}LSM6DS0_GYRO_OUT_SEL_t; - -/** - * @brief Gyroscope Interrupt Selection - */ -typedef enum { - LSM6DS0_GYRO_INT_SEL_BYPASS = 0x00, /*!< Interrupt generator signal not filtered */ - LSM6DS0_GYRO_INT_SEL_FILTERED = 0x08, /*!< Interrupt generator signal filtered */ -}LSM6DS0_GYRO_INT_SEL_t; - -/** - * @brief Gyroscope Low Power Mode - */ -typedef enum { - LSM6DS0_GYRO_LP_MODE_HIGH_PERFORMANCE = 0x00, /*!< High performance */ - LSM6DS0_GYRO_LP_MODE_LOW_POWER = 0x80, /*!< Low power */ -}LSM6DS0_GYRO_LP_MODE_t; - -/** - * @brief Gyroscope High Pass Filter Cutoff Selection - */ -typedef enum { - LSM6DS0_GYRO_HPCF_DISABLED = 0x00, /*!< HP filter disabled */ - LSM6DS0_GYRO_HPCF_0 = 0x40, /*!< Config 0 refer to table 48 of DOcID025604 Rev 3 */ - LSM6DS0_GYRO_HPCF_1 = 0x41, /*!< Config 1 refer to table 48 of DOcID025604 Rev 3 */ - LSM6DS0_GYRO_HPCF_2 = 0x42, /*!< Config 2 refer to table 48 of DOcID025604 Rev 3 */ - LSM6DS0_GYRO_HPCF_3 = 0x43, /*!< Config 3 refer to table 48 of DOcID025604 Rev 3 */ - LSM6DS0_GYRO_HPCF_4 = 0x44, /*!< Config 4 refer to table 48 of DOcID025604 Rev 3 */ - LSM6DS0_GYRO_HPCF_5 = 0x45, /*!< Config 5 refer to table 48 of DOcID025604 Rev 3 */ - LSM6DS0_GYRO_HPCF_6 = 0x46, /*!< Config 6 refer to table 48 of DOcID025604 Rev 3 */ - LSM6DS0_GYRO_HPCF_7 = 0x47, /*!< Config 7 refer to table 48 of DOcID025604 Rev 3 */ - LSM6DS0_GYRO_HPCF_8 = 0x48, /*!< Config 8 refer to table 48 of DOcID025604 Rev 3 */ - LSM6DS0_GYRO_HPCF_9 = 0x49, /*!< Config 9 refer to table 48 of DOcID025604 Rev 3 */ - LSM6DS0_GYRO_HPCF_10 = 0x4A /*!< Config 10 refer to table 48 of DOcID025604 Rev 3 */ -}LSM6DS0_GYRO_HPCF_t; - -/** - * @brief Gyroscope Axes Enabling - */ -typedef enum{ - LSM6DS0_GYRO_AE_DISABLED = 0x00, /*!< Axes all disabled */ - LSM6DS0_GYRO_AE_X = 0x08, /*!< Only X-axis enabled */ - LSM6DS0_GYRO_AE_Y = 0x10, /*!< Only Y-axis enabled */ - LSM6DS0_GYRO_AE_XY = 0x18, /*!< X & Y axes enabled */ - LSM6DS0_GYRO_AE_Z = 0x20, /*!< Only Z-axis enabled */ - LSM6DS0_GYRO_AE_XZ = 0x28, /*!< X & Z axes enabled */ - LSM6DS0_GYRO_AE_YZ = 0x30, /*!< Y & Z axes enabled */ - LSM6DS0_GYRO_AE_XYZ = 0x38 /*!< All axes enabled */ -}LSM6DS0_GYRO_AE_t; - -/** - * @brief Gyroscope Decimation Mode - */ -typedef enum { - LSM6DS0_GYRO_DEC_DISABLED = 0x00, /*!< NO decimation */ - LSM6DS0_GYRO_DEC_X2 = 0x40, /*!< Decimation update every 2 sample */ - LSM6DS0_GYRO_DEC_X4 = 0x80, /*!< Decimation update every 4 sample */ - LSM6DS0_GYRO_DEC_X8 = 0xC0 /*!< Decimation update every 8 sample */ -}LSM6DS0_GYRO_DEC_t; - -/** - * @brief Gyroscope Sleep Mode - */ -typedef enum { - LSM6DS0_GYRO_SLP_DISABLED = 0x00, /*!< Gyroscope sleep mode disabled */ - LSM6DS0_GYRO_SLP_ENABLED = 0x40 /*!< Gyroscope sleep mode enabled */ -}LSM6DS0_GYRO_SLP_t; -/** - * @brief Gyroscope configuration structure. - */ -typedef struct { - /** - * @brief LSM6DS0 Slave Address - */ - LSM6DS0_SAD_t slaveaddress; - /** - * @brief Gyroscope Output Data Rate - */ - LSM6DS0_GYRO_ODR_t outputdatarate; - /** - * @brief Gyroscope Full Scale - */ - LSM6DS0_GYRO_FS_t fullscale; - /** - * @brief Gyroscope Output Selection - */ - LSM6DS0_GYRO_OUT_SEL_t outputselect; - /** - * @brief Gyroscope Interrupt Selection - */ - LSM6DS0_GYRO_INT_SEL_t irqselect; - /** - * @brief Gyroscope Low Power Mode - */ - LSM6DS0_GYRO_LP_MODE_t lowpowermode; - /** - * @brief Gyroscope High Pass Filter Cutoff Selection - */ - LSM6DS0_GYRO_HPCF_t HPCfrequency; - /** - * @brief Gyroscope Axes Enabling - */ - LSM6DS0_GYRO_AE_t axesenabling; - /** - * @brief Gyroscope Decimation Mode - */ - LSM6DS0_GYRO_DEC_t decimation; - /** - * @brief LSM6DS0 Endianness - */ - LSM6DS0_END_t endianess; - /** - * @brief LSM6DS0 Block Data Update - */ - LSM6DS0_BDU_t blockdataupdate; -} LSM6DS0_GYRO_Config; -/** @} */ -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - - uint8_t lsm6ds0ReadRegister(I2CDriver *i2cp, uint8_t sad, uint8_t sub, - msg_t* message); - void lsm6ds0WriteRegister(I2CDriver *i2cp, uint8_t sad, uint8_t sub, - uint8_t value, msg_t* message); -#ifdef __cplusplus -} -#endif - -#endif /* _LSM6DS0_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/various/devices_lib/others/max7219.c b/firmware/ChibiOS_16/community/os/various/devices_lib/others/max7219.c deleted file mode 100644 index 0e511671cb..0000000000 --- a/firmware/ChibiOS_16/community/os/various/devices_lib/others/max7219.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi - - This file is part of PLAY for ChibiOS/RT. - - PLAY is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - PLAY is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - Special thanks to Giovanni Di Sirio for teachings, his moral support and - friendship. Note that some or every piece of this file could be part of - the ChibiOS project that is intellectual property of Giovanni Di Sirio. - Please refer to ChibiOS/RT license before use this file. - - For suggestion or Bug report - roccomarco.guglielmi@playembedded.org - */ - -/** - * @file max7219.c - * @brief MAX7219 display driver module code. - * - * @addtogroup max7219 - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#include "max7219.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Reads a generic register value. - * @pre The SPI interface must be initialized and the driver started. - * - * @param[in] spip pointer to the SPI interface - * @param[in] adr address number - * @param[in] data data value. - */ -void max7219WriteRegister(SPIDriver *spip, uint16_t adr, uint8_t data) { - - switch (adr) { - default: - return; - case MAX7219_AD_DIGIT_0: - case MAX7219_AD_DIGIT_1: - case MAX7219_AD_DIGIT_2: - case MAX7219_AD_DIGIT_3: - case MAX7219_AD_DIGIT_4: - case MAX7219_AD_DIGIT_5: - case MAX7219_AD_DIGIT_6: - case MAX7219_AD_DIGIT_7: - case MAX7219_AD_DECODE_MODE: - case MAX7219_AD_INTENSITY: - case MAX7219_AD_SCAN_LIMIT: - case MAX7219_AD_SHUTDOWN: - case MAX7219_AD_DISPLAY_TEST: - spiSelect(spip); - uint16_t txbuf = {adr | data}; - spiSend(spip, 1, &txbuf); - spiUnselect(spip); - } -} -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/various/devices_lib/others/max7219.h b/firmware/ChibiOS_16/community/os/various/devices_lib/others/max7219.h deleted file mode 100644 index e672be946c..0000000000 --- a/firmware/ChibiOS_16/community/os/various/devices_lib/others/max7219.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi - - This file is part of PLAY for ChibiOS/RT. - - PLAY is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - PLAY is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - Special thanks to Giovanni Di Sirio for teachings, his moral support and - friendship. Note that some or every piece of this file could be part of - the ChibiOS project that is intellectual property of Giovanni Di Sirio. - Please refer to ChibiOS/RT license before use this file. - - For suggestion or Bug report - roccomarco.guglielmi@playembedded.org - */ - -/** - * @file MAX7219.h - * @brief MAX7219 display driver module header. - * - * @{ - */ - -#ifndef _MAX7219_H_ -#define _MAX7219_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name MAX7219 register names - * @{ - */ -/******************************************************************************/ -/* */ -/* MAX7219 display driver */ -/* */ -/******************************************************************************/ -/******************* Bit definition for SPI communication *******************/ -#define MAX7219_DI ((uint16_t)0x00FF) /*!< DI[7:0] Data input */ -#define MAX7219_DI_0 ((uint16_t)0x0001) /*!< bit 0 */ -#define MAX7219_DI_1 ((uint16_t)0x0002) /*!< bit 1 */ -#define MAX7219_DI_2 ((uint16_t)0x0004) /*!< bit 2 */ -#define MAX7219_DI_3 ((uint16_t)0x0008) /*!< bit 3 */ -#define MAX7219_DI_4 ((uint16_t)0x0010) /*!< bit 4 */ -#define MAX7219_DI_5 ((uint16_t)0x0020) /*!< bit 5 */ -#define MAX7219_DI_6 ((uint16_t)0x0040) /*!< bit 6 */ -#define MAX7219_DI_7 ((uint16_t)0x0080) /*!< bit 7 */ - -#define MAX7219_AD ((uint16_t)0x0F00) /*!< AD[11:8] Data input */ -#define MAX7219_AD_0 ((uint16_t)0x0100) /*!< bit 8 */ -#define MAX7219_AD_1 ((uint16_t)0x0200) /*!< bit 9 */ -#define MAX7219_AD_2 ((uint16_t)0x0400) /*!< bit 10 */ -#define MAX7219_AD_3 ((uint16_t)0x0800) /*!< bit 11 */ - -/****************** Bit definition for Registers Addresses *******************/ -#define MAX7219_AD_NOP ((uint16_t)0x0000) /*!< No operation */ -#define MAX7219_AD_DIGIT_0 ((uint16_t)0x0100) /*!< Digit 0 */ -#define MAX7219_AD_DIGIT_1 ((uint16_t)0x0200) /*!< Digit 1 */ -#define MAX7219_AD_DIGIT_2 ((uint16_t)0x0300) /*!< Digit 2 */ -#define MAX7219_AD_DIGIT_3 ((uint16_t)0x0400) /*!< Digit 3 */ -#define MAX7219_AD_DIGIT_4 ((uint16_t)0x0500) /*!< Digit 4 */ -#define MAX7219_AD_DIGIT_5 ((uint16_t)0x0600) /*!< Digit 5 */ -#define MAX7219_AD_DIGIT_6 ((uint16_t)0x0700) /*!< Digit 6 */ -#define MAX7219_AD_DIGIT_7 ((uint16_t)0x0800) /*!< Digit 7 */ -#define MAX7219_AD_DECODE_MODE ((uint16_t)0x0900) /*!< Decode mode */ -#define MAX7219_AD_INTENSITY ((uint16_t)0x0A00) /*!< Intensity */ -#define MAX7219_AD_SCAN_LIMIT ((uint16_t)0x0B00) /*!< Scan limit */ -#define MAX7219_AD_SHUTDOWN ((uint16_t)0x0C00) /*!< Shutdown */ -#define MAX7219_AD_DISPLAY_TEST ((uint16_t)0x0F00) /*!< Display test */ - -/*************** Bit definition for Registers Configuration *****************/ -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !HAL_USE_SPI -#error "MAX7219 requires HAL_USE_SPI" -#endif -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @name MAX7219 data structures and types - * @{ - * - */ - -/** - * @brief MAX7219 operation mode - */ -typedef enum { - MAX7219_OM_Shutdown = 0x00, /*!< Shutdown mode */ - MAX7219_OM_Normal = 0x01 /*!< Normal mode */ -} MAX7219_OM_t; - -/** - * @brief MAX7219 decoder mode - */ -typedef enum { - MAX7219_DM_No_decode = 0x00, /*!< No decode */ - MAX7219_DM_CodeB_0 = 0x01, /*!< Code B on Digit 0 */ - MAX7219_DM_CodeB_1 = 0x03, /*!< Code B on Digits 0-1 */ - MAX7219_DM_CodeB_2 = 0x07, /*!< Code B on Digits from 0 to 2 */ - MAX7219_DM_CodeB_3 = 0x0F, /*!< Code B on Digits from 0 to 3 */ - MAX7219_DM_CodeB_4 = 0x1F, /*!< Code B on Digits from 0 to 4 */ - MAX7219_DM_CodeB_5 = 0x3F, /*!< Code B on Digits from 0 to 5 */ - MAX7219_DM_CodeB_6 = 0x7F, /*!< Code B on Digits from 0 to 6 */ - MAX7219_DM_CodeB_7 = 0xFF /*!< Code B on every digit */ -} MAX7219_DM_t; - -/** - * @brief MAX7219 intensity mode - */ -typedef enum { - MAX7219_IM_1_32 = 0x00, /*!< 1/32 intensity */ - MAX7219_IM_3_32 = 0x01, /*!< 3/32 intensity */ - MAX7219_IM_5_32 = 0x02, /*!< 5/32 intensity */ - MAX7219_IM_7_32 = 0x03, /*!< 7/32 intensity */ - MAX7219_IM_9_32 = 0x04, /*!< 9/32 intensity */ - MAX7219_IM_11_32 = 0x05, /*!< 11/32 intensity */ - MAX7219_IM_13_32 = 0x06, /*!< 13/32 intensity */ - MAX7219_IM_15_32 = 0x07, /*!< 15/32 intensity */ - MAX7219_IM_17_32 = 0x08, /*!< 17/32 intensity */ - MAX7219_IM_19_32 = 0x09, /*!< 19/32 intensity */ - MAX7219_IM_21_32 = 0x0A, /*!< 21/32 intensity */ - MAX7219_IM_23_32 = 0x0B, /*!< 23/32 intensity */ - MAX7219_IM_25_32 = 0x0C, /*!< 25/32 intensity */ - MAX7219_IM_27_32 = 0x0D, /*!< 27/32 intensity */ - MAX7219_IM_29_32 = 0x0E, /*!< 29/32 intensity */ - MAX7219_IM_31_32 = 0x0F /*!< 31/32 intensity */ -} MAX7219_IM_t; - -/** - * @brief MAX7219 scan line mode - */ -typedef enum { - MAX7219_SL_0 = 0x00, /*!< Scanned digit 0 only */ - MAX7219_SL_1 = 0x01, /*!< Scanned digit 0 & 1 */ - MAX7219_SL_2 = 0x02, /*!< Scanned digit 0 - 2 */ - MAX7219_SL_3 = 0x03, /*!< Scanned digit 0 - 3 */ - MAX7219_SL_4 = 0x04, /*!< Scanned digit 0 - 4 */ - MAX7219_SL_5 = 0x05, /*!< Scanned digit 0 - 5 */ - MAX7219_SL_6 = 0x06, /*!< Scanned digit 0 - 6 */ - MAX7219_SL_7 = 0x07 /*!< Scanned digit 0 - 7 */ -} MAX7219_SL_t; -/** @} */ -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - - void max7219WriteRegister(SPIDriver *spip, uint16_t adr, uint8_t data); -#ifdef __cplusplus -} -#endif -#endif /* _MAX7219_H_ */ - -/** @} */ - diff --git a/firmware/ChibiOS_16/community/os/various/devices_lib/rf/nrf24l01.c b/firmware/ChibiOS_16/community/os/various/devices_lib/rf/nrf24l01.c deleted file mode 100644 index f526fbeffa..0000000000 --- a/firmware/ChibiOS_16/community/os/various/devices_lib/rf/nrf24l01.c +++ /dev/null @@ -1,440 +0,0 @@ -/* - Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi - - This file is part of PLAY for ChibiOS/RT. - - PLAY is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - PLAY is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - Special thanks to Giovanni Di Sirio for teachings, his moral support and - friendship. Note that some or every piece of this file could be part of - the ChibiOS project that is intellectual property of Giovanni Di Sirio. - Please refer to ChibiOS/RT license before use this file. - - For suggestion or Bug report - roccomarco.guglielmi@playembedded.org - */ - -/** - * @file nrf24l01.c - * @brief NRF24L01 interface module code. - * - * @addtogroup nrf24l01 - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#include "nrf24l01.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define ACTIVATE 0x73 -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Gets the status register value. - * @pre The SPI interface must be initialized and the driver started. - * - * @param[in] spip pointer to the SPI interface - * - * @return the status register value - */ -NRF24L01_status_t nrf24l01GetStatus(SPIDriver *spip) { - uint8_t txbuf = NRF24L01_CMD_NOP; - uint8_t status; - spiSelect(spip); - spiExchange(spip, 1, &txbuf, &status); - spiUnselect(spip); - return status; -} - -/** - * @brief Reads a generic register value. - * - * @note Cannot be used to set addresses - * @pre The SPI interface must be initialized and the driver started. - * - * @param[in] spip pointer to the SPI interface - * @param[in] reg register number - * @param[out] pvalue pointer to a data buffer - * - * @return the status register value - */ -NRF24L01_status_t nrf24l01ReadRegister(SPIDriver *spip, uint8_t reg, - uint8_t* pvalue) { - uint8_t txbuf = (NRF24L01_CMD_READ | reg); - uint8_t status = 0xFF; - spiSelect(spip); - spiExchange(spip, 1, &txbuf, &status); - spiReceive(spip, 1, pvalue); - spiUnselect(spip); - return status; -} - -/** - * @brief Writes a generic register value. - * - * @note Cannot be used to set addresses - * @pre The SPI interface must be initialized and the driver started. - * - * @param[in] spip pointer to the SPI interface - * @param[in] reg register number - * @param[in] value data value - * - * @return the status register value - */ -NRF24L01_status_t nrf24l01WriteRegister(SPIDriver *spip, uint8_t reg, - uint8_t value) { - - uint8_t txbuf[2] = {(NRF24L01_CMD_WRITE | reg), value}; - uint8_t rxbuf[2] = {0xFF, 0xFF}; - switch (reg) { - - default: - /* Reserved register must not be written, according to the datasheet - * this could permanently damage the device. - */ - chDbgAssert(FALSE, "lg3d20WriteRegister(), reserved register"); - case NRF24L01_AD_OBSERVE_TX: - case NRF24L01_AD_CD: - case NRF24L01_AD_RX_ADDR_P0: - case NRF24L01_AD_RX_ADDR_P1: - case NRF24L01_AD_RX_ADDR_P2: - case NRF24L01_AD_RX_ADDR_P3: - case NRF24L01_AD_RX_ADDR_P4: - case NRF24L01_AD_RX_ADDR_P5: - case NRF24L01_AD_TX_ADDR: - /* Read only or addresses registers cannot be written, - * the command is ignored. - */ - return 0; - case NRF24L01_AD_CONFIG: - case NRF24L01_AD_EN_AA: - case NRF24L01_AD_EN_RXADDR: - case NRF24L01_AD_SETUP_AW: - case NRF24L01_AD_SETUP_RETR: - case NRF24L01_AD_RF_CH: - case NRF24L01_AD_RF_SETUP: - case NRF24L01_AD_STATUS: - case NRF24L01_AD_RX_PW_P0: - case NRF24L01_AD_RX_PW_P1: - case NRF24L01_AD_RX_PW_P2: - case NRF24L01_AD_RX_PW_P3: - case NRF24L01_AD_RX_PW_P4: - case NRF24L01_AD_RX_PW_P5: - case NRF24L01_AD_FIFO_STATUS: - case NRF24L01_AD_DYNPD: - case NRF24L01_AD_FEATURE: - spiSelect(spip); - spiExchange(spip, 2, txbuf, rxbuf); - spiUnselect(spip); - return rxbuf[0]; - } -} - - -/** - * @brief Writes an address. - * - * @pre The SPI interface must be initialized and the driver started. - * - * @param[in] spip pointer to the SPI interface - * @param[in] reg register number - * @param[in] pvalue pointer to address value - * @param[in] addlen address len - * - * @return the status register value - */ -NRF24L01_status_t nrf24l01WriteAddress(SPIDriver *spip, uint8_t reg, - uint8_t *pvalue, uint8_t addlen) { - - uint8_t txbuf[NRF24L01_MAX_ADD_LENGHT + 1]; - uint8_t rxbuf[NRF24L01_MAX_ADD_LENGHT + 1]; - unsigned i; - - if(addlen > NRF24L01_MAX_ADD_LENGHT) { - chDbgAssert(FALSE, "nrf24l01WriteAddress(), wrong address length"); - return 0; - } - txbuf[0] = (NRF24L01_CMD_WRITE | reg); - rxbuf[0] = 0xFF; - for(i = 1; i <= addlen; i++) { - txbuf[i] = *(pvalue + (i - 1)); - rxbuf[i] = 0xFF; - } - switch (reg) { - - default: - /* Reserved register must not be written, according to the datasheet - * this could permanently damage the device. - */ - chDbgAssert(FALSE, "nrf24l01WriteAddress(), reserved register"); - case NRF24L01_AD_OBSERVE_TX: - case NRF24L01_AD_CD: - case NRF24L01_AD_CONFIG: - case NRF24L01_AD_EN_AA: - case NRF24L01_AD_EN_RXADDR: - case NRF24L01_AD_SETUP_AW: - case NRF24L01_AD_SETUP_RETR: - case NRF24L01_AD_RF_CH: - case NRF24L01_AD_RF_SETUP: - case NRF24L01_AD_STATUS: - case NRF24L01_AD_RX_PW_P0: - case NRF24L01_AD_RX_PW_P1: - case NRF24L01_AD_RX_PW_P2: - case NRF24L01_AD_RX_PW_P3: - case NRF24L01_AD_RX_PW_P4: - case NRF24L01_AD_RX_PW_P5: - case NRF24L01_AD_FIFO_STATUS: - case NRF24L01_AD_DYNPD: - case NRF24L01_AD_FEATURE: - /* Not address registers cannot be written, the command is ignored.*/ - return 0; - case NRF24L01_AD_RX_ADDR_P0: - case NRF24L01_AD_RX_ADDR_P1: - case NRF24L01_AD_RX_ADDR_P2: - case NRF24L01_AD_RX_ADDR_P3: - case NRF24L01_AD_RX_ADDR_P4: - case NRF24L01_AD_RX_ADDR_P5: - case NRF24L01_AD_TX_ADDR: - spiSelect(spip); - spiExchange(spip, addlen + 1, txbuf, rxbuf); - spiUnselect(spip); - return rxbuf[0]; - } -} -/** - * @brief Reads RX payload from FIFO. - * - * @note Payload is deleted from FIFO after it is read. Used in RX mode. - * @pre The SPI interface must be initialized and the driver started. - * - * @param[in] spip pointer to the SPI interface - * @param[in] paylen payload length - * @param[in] rxbuf pointer to a buffer - * - * @return the status register value - */ -NRF24L01_status_t nrf24l01GetRxPl(SPIDriver *spip, uint8_t paylen, - uint8_t* rxbuf) { - - uint8_t txbuf = NRF24L01_CMD_R_RX_PAYLOAD; - uint8_t status; - if(paylen > NRF24L01_MAX_PL_LENGHT) { - return 0; - } - spiSelect(spip); - spiExchange(spip, 1, &txbuf, &status); - spiReceive(spip, paylen, rxbuf); - spiUnselect(spip); - return status; -} - -/** - * @brief Writes TX payload on FIFO. - * - * @note Used in TX mode. - * @pre The SPI interface must be initialized and the driver started. - * - * @param[in] spip pointer to the SPI interface - * @param[in] paylen payload length - * @param[in] rxbuf pointer to a buffer - * - * @return the status register value - */ -NRF24L01_status_t nrf24l01WriteTxPl(SPIDriver *spip, uint8_t paylen, - uint8_t* txbuf) { - - uint8_t cmd = NRF24L01_CMD_W_TX_PAYLOAD; - uint8_t status; - if(paylen > NRF24L01_MAX_PL_LENGHT) { - return 0; - } - spiSelect(spip); - spiExchange(spip, 1, &cmd, &status); - spiSend(spip, paylen, txbuf); - spiUnselect(spip); - return status; -} - -/** - * @brief Flush TX FIFO. - * - * @note Used in TX mode. - * @pre The SPI interface must be initialized and the driver started. - * - * @param[in] spip pointer to the SPI interface - * - * @return the status register value - */ -NRF24L01_status_t nrf24l01FlushTx(SPIDriver *spip) { - - uint8_t txbuf = NRF24L01_CMD_FLUSH_TX; - uint8_t status; - spiSelect(spip); - spiExchange(spip, 1, &txbuf, &status); - spiUnselect(spip); - return status; -} - -/** - * @brief Flush RX FIFO. - * - * @note Used in RX mode. Should not be executed during transmission of - acknowledge, that is, acknowledge package will not be completed. - * @pre The SPI interface must be initialized and the driver started. - * - * @param[in] spip pointer to the SPI interface - * - * @return the status register value - */ -NRF24L01_status_t nrf24l01FlushRx(SPIDriver *spip) { - - uint8_t txbuf = NRF24L01_CMD_FLUSH_RX; - uint8_t status; - spiSelect(spip); - spiExchange(spip, 1, &txbuf, &status); - spiUnselect(spip); - return status; -} - -#if NRF24L01_USE_FEATURE || defined(__DOXYGEN__) -/** - * @brief Activates the following features: - * R_RX_PL_WID -> (In order to enable DPL the EN_DPL bit in the - * FEATURE register must be set) - * W_ACK_PAYLOAD -> (In order to enable PL with ACK the EN_ACK_PAY - * bit in the FEATURE register must be set) - * W_TX_PAYLOAD_NOACK -> (In order to send a PL without ACK - * the EN_DYN_ACK it in the FEATURE register - * must be set) - * - * @note A new ACTIVATE command with the same data deactivates them again. - * This is executable in power down or stand by modes only. - * @pre The SPI interface must be initialized and the driver started. - * - * @param[in] spip pointer to the SPI interface - * - * @return the status register value - */ -NRF24L01_status_t nrf24l01Activate(SPIDriver *spip) { - - uint8_t txbuf[2] = {NRF24L01_CMD_FLUSH_RX, ACTIVATE}; - uint8_t rxbuf[2]; - spiSelect(spip); - spiExchange(spip, 2, txbuf, rxbuf); - spiUnselect(spip); - return rxbuf[0]; -} - -/** - * @brief Reads RX payload lenght for the top R_RX_PAYLOAD - * in the RX FIFO when Dynamic Payload Length is activated. - * - * @note R_RX_PL_WID must be set and activated. - * @pre The SPI interface must be initialized and the driver started. - * - * @param[in] spip pointer to the SPI interface - * @param[in] ppaylen pointer to the payload length variable - * - * @return the status register value - */ -NRF24L01_status_t nrf24l01ReadRxPlWid(SPIDriver *spip, uint8_t *ppaylen) { - - uint8_t txbuf[2] = {NRF24L01_CMD_R_RX_PL_WID, 0xFF}; - uint8_t rxbuf[2]; - spiSelect(spip); - spiExchange(spip, 2, txbuf, rxbuf); - spiUnselect(spip); - *ppaylen = rxbuf[1]; - return rxbuf[0]; -} - -/** - * @brief Writes TX payload associateted to ACK. - * - * @note Used in RX mode. Write Payload to be transmitted together with - * ACK packet on PIPE PPP. (PPP valid in the range from 000 to 101). - * @note EN_ACK_PAY must be set and activated. - * @pre The SPI interface must be initialized and the driver started. - * - * @param[in] spip pointer to the SPI interface - * @param[in] paylen payload length - * @param[in] rxbuf pointer to a buffer - * - * @return the status register value - */ -NRF24L01_status_t nrf24l01WriteAckPl(SPIDriver *spip, uint8_t ppp, uint8_t paylen, - uint8_t* payload){ - - payload[0] = NRF24L01_CMD_W_ACK_PAYLOAD | NRF24L01_MAX_PPP; - uint8_t status; - if((paylen > NRF24L01_MAX_PL_LENGHT) || (ppp > NRF24L01_MAX_PPP)) { - return 0; - } - spiSelect(spip); - spiExchange(spip, 1, payload, &status); - spiSend(spip, paylen, payload); - spiUnselect(spip); - return status; -} - -/** - * @brief Writes next TX payload without ACK. - * - * @note Used in TX mode. - * @note EN_DYN_ACK must be set and activated. - * @pre The SPI interface must be initialized and the driver started. - * - * @param[in] spip pointer to the SPI interface - * @param[in] paylen payload length - * @param[in] rxbuf pointer to a buffer - * - * @return the status register value - */ -NRF24L01_status_t nrf24l01WriteTxPlNoAck(SPIDriver *spip, uint8_t paylen, - uint8_t* txbuf) { - - txbuf[0] = NRF24L01_CMD_W_TX_PAYLOAD_NOACK; - uint8_t status; - if(paylen > NRF24L01_MAX_PL_LENGHT) { - return 0; - } - spiSelect(spip); - spiExchange(spip, 1, txbuf, &status); - spiSend(spip, paylen, txbuf); - spiUnselect(spip); - return status; -} -#endif /* NRF24L01_USE_FEATURE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/various/devices_lib/rf/nrf24l01.h b/firmware/ChibiOS_16/community/os/various/devices_lib/rf/nrf24l01.h deleted file mode 100644 index 86ba1279de..0000000000 --- a/firmware/ChibiOS_16/community/os/various/devices_lib/rf/nrf24l01.h +++ /dev/null @@ -1,575 +0,0 @@ -/* - Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi - - This file is part of PLAY for ChibiOS/RT. - - PLAY is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - PLAY is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - Special thanks to Giovanni Di Sirio for teachings, his moral support and - friendship. Note that some or every piece of this file could be part of - the ChibiOS project that is intellectual property of Giovanni Di Sirio. - Please refer to ChibiOS/RT license before use this file. - - For suggestion or Bug report - roccomarco.guglielmi@playembedded.org - */ - -/** - * @file nrf24l01.h - * @brief NRF24L01 Radio frequency module interface module header. - * - * @{ - */ - -#ifndef _NRF24L01_H_ -#define _NRF24L01_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#define NRF24L01_MAX_ADD_LENGHT ((uint8_t) 5) -#define NRF24L01_MAX_PL_LENGHT ((uint8_t) 32) -#define NRF24L01_MAX_PPP ((uint8_t) 5) - -/** - * @brief Enables Advanced Features. - */ -#if !defined(NRF24L01_USE_FEATURE) || defined(__DOXYGEN__) -#define NRF24L01_USE_FEATURE TRUE -#endif - -/** - * @name NRF24L01 register names - * @{ - */ -/******************************************************************************/ -/* */ -/* NRF24L01 RF Transceiver */ -/* */ -/******************************************************************************/ -/****************** Bit definition for SPI communication ********************/ -#define NRF24L01_DI ((uint8_t)0xFF) /*!< DI[7:0] Data input */ -#define NRF24L01_DI_0 ((uint8_t)0x01) /*!< bit 0 */ -#define NRF24L01_DI_1 ((uint8_t)0x02) /*!< bit 1 */ -#define NRF24L01_DI_2 ((uint8_t)0x04) /*!< bit 2 */ -#define NRF24L01_DI_3 ((uint8_t)0x08) /*!< bit 3 */ -#define NRF24L01_DI_4 ((uint8_t)0x10) /*!< bit 4 */ -#define NRF24L01_DI_5 ((uint8_t)0x20) /*!< bit 5 */ -#define NRF24L01_DI_6 ((uint8_t)0x40) /*!< bit 6 */ -#define NRF24L01_DI_7 ((uint8_t)0x80) /*!< bit 7 */ - -#define NRF24L01_AD ((uint8_t)0x1F) /*!< AD[4:0] Address Data */ -#define NRF24L01_AD_0 ((uint8_t)0x01) /*!< bit 0 */ -#define NRF24L01_AD_1 ((uint8_t)0x02) /*!< bit 1 */ -#define NRF24L01_AD_2 ((uint8_t)0x04) /*!< bit 2 */ -#define NRF24L01_AD_3 ((uint8_t)0x08) /*!< bit 3 */ -#define NRF24L01_AD_4 ((uint8_t)0x10) /*!< bit 4 */ - -#define NRF24L01_CMD_READ ((uint8_t)0x00) /*!< Read command */ -#define NRF24L01_CMD_WRITE ((uint8_t)0x20) /*!< Write command */ -#define NRF24L01_CMD_R_RX_PAYLOAD ((uint8_t)0x61) /*!< Read RX-payload*/ -#define NRF24L01_CMD_W_TX_PAYLOAD ((uint8_t)0xA0) /*!< Write TX-payload */ -#define NRF24L01_CMD_FLUSH_TX ((uint8_t)0xE1) /*!< Flush TX FIFO */ -#define NRF24L01_CMD_FLUSH_RX ((uint8_t)0xE2) /*!< Flush RX FIFO */ -#define NRF24L01_CMD_REUSE_TX_PL ((uint8_t)0xE3) /*!< Used for a PTX device */ -#define NRF24L01_CMD_ACTIVATE ((uint8_t)0x50) /*!< Activate command */ -#define NRF24L01_CMD_R_RX_PL_WID ((uint8_t)0x60) /*!< Read RX-payload width */ -#define NRF24L01_CMD_W_ACK_PAYLOAD ((uint8_t)0xA8) /*!< Write Payload for ACK */ -#define NRF24L01_CMD_W_TX_PAYLOAD_NOACK ((uint8_t)0xB0) /*!< Disables AUTOACK*/ -#define NRF24L01_CMD_NOP ((uint8_t)0xFF) /*!< No Operation */ - -/****************** Bit definition for Registers Addresses *******************/ -#define NRF24L01_AD_CONFIG ((uint8_t)0x00) /*!< Configuration Register */ -#define NRF24L01_AD_EN_AA ((uint8_t)0x01) /*!< Enable ‘Auto Acknowledgment’ */ -#define NRF24L01_AD_EN_RXADDR ((uint8_t)0x02) /*!< Enabled RX Addresses */ -#define NRF24L01_AD_SETUP_AW ((uint8_t)0x03) /*!< Setup of Address Widths */ -#define NRF24L01_AD_SETUP_RETR ((uint8_t)0x04) /*!< Setup of Automatic Retransmission */ -#define NRF24L01_AD_RF_CH ((uint8_t)0x05) /*!< RF Channel */ -#define NRF24L01_AD_RF_SETUP ((uint8_t)0x06) /*!< RF Setup Register */ -#define NRF24L01_AD_STATUS ((uint8_t)0x07) /*!< Status Register */ -#define NRF24L01_AD_OBSERVE_TX ((uint8_t)0x08) /*!< Transmit observe register */ -#define NRF24L01_AD_CD ((uint8_t)0x09) /*!< CD */ -#define NRF24L01_AD_RX_ADDR_P0 ((uint8_t)0x0A) /*!< Receive address data pipe 0 */ -#define NRF24L01_AD_RX_ADDR_P1 ((uint8_t)0x0B) /*!< Receive address data pipe 1 */ -#define NRF24L01_AD_RX_ADDR_P2 ((uint8_t)0x0C) /*!< Receive address data pipe 2 */ -#define NRF24L01_AD_RX_ADDR_P3 ((uint8_t)0x0D) /*!< Receive address data pipe 3 */ -#define NRF24L01_AD_RX_ADDR_P4 ((uint8_t)0x0E) /*!< Receive address data pipe 4 */ -#define NRF24L01_AD_RX_ADDR_P5 ((uint8_t)0x0F) /*!< Receive address data pipe 5 */ -#define NRF24L01_AD_TX_ADDR ((uint8_t)0x10) /*!< Transmit address */ -#define NRF24L01_AD_RX_PW_P0 ((uint8_t)0x11) /*!< Number of bytes in RX payload in data pipe 0 */ -#define NRF24L01_AD_RX_PW_P1 ((uint8_t)0x12) /*!< Number of bytes in RX payload in data pipe 1 */ -#define NRF24L01_AD_RX_PW_P2 ((uint8_t)0x13) /*!< Number of bytes in RX payload in data pipe 2 */ -#define NRF24L01_AD_RX_PW_P3 ((uint8_t)0x14) /*!< Number of bytes in RX payload in data pipe 3 */ -#define NRF24L01_AD_RX_PW_P4 ((uint8_t)0x15) /*!< Number of bytes in RX payload in data pipe 4 */ -#define NRF24L01_AD_RX_PW_P5 ((uint8_t)0x16) /*!< Number of bytes in RX payload in data pipe 5 */ -#define NRF24L01_AD_FIFO_STATUS ((uint8_t)0x17) /*!< FIFO Status Register */ -#define NRF24L01_AD_DYNPD ((uint8_t)0x1C) /*!< Enable dynamic payload length */ -#define NRF24L01_AD_FEATURE ((uint8_t)0x1D) /*!< Feature Register */ - -/*************** Bit definition for Registers Configuration *****************/ -#define NRF24L01_DI_CONFIG ((uint8_t)0x7F) /*!< CONTROL REGISTER BIT MASK*/ -#define NRF24L01_DI_CONFIG_PRIM_RX ((uint8_t)0x01) /*!< RX/TX control - 1: PRX, 0: PTX */ -#define NRF24L01_DI_CONFIG_PWR_UP ((uint8_t)0x02) /*!< 1: POWER UP, 0:POWER DOWN */ -#define NRF24L01_DI_CONFIG_CRCO ((uint8_t)0x04) /*!< CRC encoding scheme - 1:two bytes, 0:one byte */ -#define NRF24L01_DI_CONFIG_EN_CRC ((uint8_t)0x08) /*!< Enable CRC. Forced high if one of the bits in the EN_AA is high */ -#define NRF24L01_DI_CONFIG_MASK_MAX_RT ((uint8_t)0x10) /*!< Mask interrupt caused by MAX_RT - 1: Interrupt disabled, 0: Interrupt reflected on IRQ pin */ -#define NRF24L01_DI_CONFIG_MASK_TX_DS ((uint8_t)0x20) /*!< Mask interrupt caused by TX_DS - 1: Interrupt disabled, 0: Interrupt reflected on IRQ pin */ -#define NRF24L01_DI_CONFIG_MASK_RX_DR ((uint8_t)0x40) /*!< Mask interrupt caused by RX_DR - 1: Interrupt disabled, 0: Interrupt reflected on IRQ pin */ - -#define NRF24L01_DI_EN_AA ((uint8_t)0x3F) /*!< ENABLE AUTO ACKNOLEDGMENT REGISTER BIT MASK */ -#define NRF24L01_DI_EN_AA_P0 ((uint8_t)0x01) /*!< Enable auto acknowledgement data pipe 0 */ -#define NRF24L01_DI_EN_AA_P1 ((uint8_t)0x02) /*!< Enable auto acknowledgement data pipe 1 */ -#define NRF24L01_DI_EN_AA_P2 ((uint8_t)0x04) /*!< Enable auto acknowledgement data pipe 2 */ -#define NRF24L01_DI_EN_AA_P3 ((uint8_t)0x08) /*!< Enable auto acknowledgement data pipe 3 */ -#define NRF24L01_DI_EN_AA_P4 ((uint8_t)0x10) /*!< Enable auto acknowledgement data pipe 4 */ -#define NRF24L01_DI_EN_AA_P5 ((uint8_t)0x20) /*!< Enable auto acknowledgement data pipe 5 */ - -#define NRF24L01_DI_EN_RXADDR ((uint8_t)0x3F) /*!< ENABLE RX ADDRESSES REGISTER BIT MASK */ -#define NRF24L01_DI_EN_RXADDR_P0 ((uint8_t)0x01) /*!< Enable data pipe 0 */ -#define NRF24L01_DI_EN_RXADDR_P1 ((uint8_t)0x02) /*!< Enable data pipe 1 */ -#define NRF24L01_DI_EN_RXADDR_P2 ((uint8_t)0x04) /*!< Enable data pipe 2 */ -#define NRF24L01_DI_EN_RXADDR_P3 ((uint8_t)0x08) /*!< Enable data pipe 3 */ -#define NRF24L01_DI_EN_RXADDR_P4 ((uint8_t)0x10) /*!< Enable data pipe 4 */ -#define NRF24L01_DI_EN_RXADDR_P5 ((uint8_t)0x20) /*!< Enable data pipe 5 */ - -#define NRF24L01_DI_SETUP_AW ((uint8_t)0x03) /*!< SETUP OF ADDRESSES WIDTHS REGISTER BIT MASK */ -#define NRF24L01_DI_SETUP_AW_0 ((uint8_t)0x01) /*!< Addressed widths bit 0 */ -#define NRF24L01_DI_SETUP_AW_1 ((uint8_t)0x02) /*!< Addressed widths bit 1 */ - -#define NRF24L01_DI_SETUP_RETR ((uint8_t)0xFF) /*!< SETUP OF AUTOMATIC RETRANSMISSION REGISTER BIT MASK */ -#define NRF24L01_DI_SETUP_RETR_ARC_0 ((uint8_t)0x01) /*!< Auto Retransmit Count bit 0 */ -#define NRF24L01_DI_SETUP_RETR_ARC_1 ((uint8_t)0x02) /*!< Auto Retransmit Count bit 1 */ -#define NRF24L01_DI_SETUP_RETR_ARC_2 ((uint8_t)0x04) /*!< Auto Retransmit Count bit 2 */ -#define NRF24L01_DI_SETUP_RETR_ARC_3 ((uint8_t)0x08) /*!< Auto Retransmit Count bit 3 */ -#define NRF24L01_DI_SETUP_RETR_ARD_0 ((uint8_t)0x10) /*!< Auto Retransmit Delay bit 0 */ -#define NRF24L01_DI_SETUP_RETR_ARD_1 ((uint8_t)0x20) /*!< Auto Retransmit Delay bit 1 */ -#define NRF24L01_DI_SETUP_RETR_ARD_2 ((uint8_t)0x40) /*!< Auto Retransmit Delay bit 2 */ -#define NRF24L01_DI_SETUP_RETR_ARD_3 ((uint8_t)0x80) /*!< Auto Retransmit Delay bit 3 */ - - -#define NRF24L01_DI_RF_CH ((uint8_t)0x7F) /*!< RF CHANNEL REGISTER BIT MASK */ -#define NRF24L01_DI_RF_CH_0 ((uint8_t)0x01) /*!< RF channel bit 0 */ -#define NRF24L01_DI_RF_CH_1 ((uint8_t)0x02) /*!< RF channel bit 1 */ -#define NRF24L01_DI_RF_CH_2 ((uint8_t)0x04) /*!< RF channel bit 2 */ -#define NRF24L01_DI_RF_CH_3 ((uint8_t)0x08) /*!< RF channel bit 3 */ -#define NRF24L01_DI_RF_CH_4 ((uint8_t)0x10) /*!< RF channel bit 4 */ -#define NRF24L01_DI_RF_CH_5 ((uint8_t)0x20) /*!< RF channel bit 5 */ -#define NRF24L01_DI_RF_CH_6 ((uint8_t)0x40) /*!< RF channel bit 6 */ - - -#define NRF24L01_DI_RF_SETUP ((uint8_t)0x1F) /*!< RF SETUP REGISTER BIT MASK */ -#define NRF24L01_DI_RF_SETUP_LNA_HCURR ((uint8_t)0x01) /*!< Setup LNA gain */ -#define NRF24L01_DI_RF_SETUP_RF_PWR_0 ((uint8_t)0x02) /*!< RF output power bit 0 */ -#define NRF24L01_DI_RF_SETUP_RF_PWR_1 ((uint8_t)0x04) /*!< RF output power bit 1 */ -#define NRF24L01_DI_RF_SETUP_RF_DR ((uint8_t)0x08) /*!< Air Data rate - 0: 1Mbps, 1: 2Mbps */ -#define NRF24L01_DI_RF_SETUP_PLL_LOCK ((uint8_t)0x10) /*!< Force PLL lock signal */ - -#define NRF24L01_DI_STATUS ((uint8_t)0x7F) /*!< STATUS REGISTER BIT MASK */ -#define NRF24L01_DI_STATUS_TX_FULL ((uint8_t)0x01) /*!< TX FIFO full flag - 0: Available locations, 1: Full */ -#define NRF24L01_DI_STATUS_RX_P_NO_0 ((uint8_t)0x02) /*!< RX payload number bit 0 */ -#define NRF24L01_DI_STATUS_RX_P_NO_1 ((uint8_t)0x04) /*!< RX payload number bit 1 */ -#define NRF24L01_DI_STATUS_RX_P_NO_2 ((uint8_t)0x08) /*!< RX payload number bit 2 */ -#define NRF24L01_DI_STATUS_MAX_RT ((uint8_t)0x10) /*!< Maximum number of TX retransmits interrupt */ -#define NRF24L01_DI_STATUS_TX_DS ((uint8_t)0x20) /*!< Data Sent TX FIFO interrupt */ -#define NRF24L01_DI_STATUS_RX_DR ((uint8_t)0x40) /*!< Data Ready RX FIFO interrupt */ - -#define NRF24L01_DI_OBSERVE_TX ((uint8_t)0xFF) /*!< TRANSMIT OBSERVE REGISTER BIT MASK */ -#define NRF24L01_DI_ARC_CNT_0 ((uint8_t)0x01) /*!< Count retransmitted packets bit 0 */ -#define NRF24L01_DI_ARC_CNT_1 ((uint8_t)0x02) /*!< Count retransmitted packets bit 1 */ -#define NRF24L01_DI_ARC_CNT_2 ((uint8_t)0x04) /*!< Count retransmitted packets bit 2 */ -#define NRF24L01_DI_ARC_CNT_3 ((uint8_t)0x08) /*!< Count retransmitted packets bit 3 */ -#define NRF24L01_DI_PLOS_CNT_0 ((uint8_t)0x10) /*!< Count lost packets bit 0 */ -#define NRF24L01_DI_PLOS_CNT_1 ((uint8_t)0x20) /*!< Count lost packets bit 1 */ -#define NRF24L01_DI_PLOS_CNT_2 ((uint8_t)0x40) /*!< Count lost packets bit 2 */ -#define NRF24L01_DI_PLOS_CNT_3 ((uint8_t)0x80) /*!< Count lost packets bit 3 */ - -#define NRF24L01_DI_CD ((uint8_t)0x01) /*!< REGISTER BIT MASK */ -#define NRF24L01_DI_CARRIER_DETECT ((uint8_t)0x01) /*!< Carrier detect */ - -#define NRF24L01_DI_RX_PW_P0 ((uint8_t)0x3F) /*!< RX PAYLOAD WIDTH FOR PIPE 0 REGISTER BIT MASK */ -#define NRF24L01_DI_RX_PW_P0_0 ((uint8_t)0x01) /*!< Bit 0 */ -#define NRF24L01_DI_RX_PW_P0_1 ((uint8_t)0x02) /*!< Bit 1 */ -#define NRF24L01_DI_RX_PW_P0_2 ((uint8_t)0x04) /*!< Bit 2 */ -#define NRF24L01_DI_RX_PW_P0_3 ((uint8_t)0x08) /*!< Bit 3 */ -#define NRF24L01_DI_RX_PW_P0_4 ((uint8_t)0x10) /*!< Bit 4 */ -#define NRF24L01_DI_RX_PW_P0_5 ((uint8_t)0x20) /*!< Bit 5 */ - -#define NRF24L01_DI_RX_PW_P1 ((uint8_t)0x3F) /*!< RX PAYLOAD WIDTH FOR PIPE 1 REGISTER BIT MASK */ -#define NRF24L01_DI_RX_PW_P1_0 ((uint8_t)0x01) /*!< Bit 0 */ -#define NRF24L01_DI_RX_PW_P1_1 ((uint8_t)0x02) /*!< Bit 1 */ -#define NRF24L01_DI_RX_PW_P1_2 ((uint8_t)0x04) /*!< Bit 2 */ -#define NRF24L01_DI_RX_PW_P1_3 ((uint8_t)0x08) /*!< Bit 3 */ -#define NRF24L01_DI_RX_PW_P1_4 ((uint8_t)0x10) /*!< Bit 4 */ -#define NRF24L01_DI_RX_PW_P1_5 ((uint8_t)0x20) /*!< Bit 5 */ - -#define NRF24L01_DI_RX_PW_P2 ((uint8_t)0x3F) /*!< RX PAYLOAD WIDTH FOR PIPE 2 REGISTER BIT MASK */ -#define NRF24L01_DI_RX_PW_P2_0 ((uint8_t)0x01) /*!< Bit 0 */ -#define NRF24L01_DI_RX_PW_P2_1 ((uint8_t)0x02) /*!< Bit 1 */ -#define NRF24L01_DI_RX_PW_P2_2 ((uint8_t)0x04) /*!< Bit 2 */ -#define NRF24L01_DI_RX_PW_P2_3 ((uint8_t)0x08) /*!< Bit 3 */ -#define NRF24L01_DI_RX_PW_P2_4 ((uint8_t)0x10) /*!< Bit 4 */ -#define NRF24L01_DI_RX_PW_P2_5 ((uint8_t)0x20) /*!< Bit 5 */ - -#define NRF24L01_DI_RX_PW_P3 ((uint8_t)0x3F) /*!< RX PAYLOAD WIDTH FOR PIPE 3 REGISTER BIT MASK */ -#define NRF24L01_DI_RX_PW_P3_0 ((uint8_t)0x01) /*!< Bit 0 */ -#define NRF24L01_DI_RX_PW_P3_1 ((uint8_t)0x02) /*!< Bit 1 */ -#define NRF24L01_DI_RX_PW_P3_2 ((uint8_t)0x04) /*!< Bit 2 */ -#define NRF24L01_DI_RX_PW_P3_3 ((uint8_t)0x08) /*!< Bit 3 */ -#define NRF24L01_DI_RX_PW_P3_4 ((uint8_t)0x10) /*!< Bit 4 */ -#define NRF24L01_DI_RX_PW_P3_5 ((uint8_t)0x20) /*!< Bit 5 */ - -#define NRF24L01_DI_RX_PW_P4 ((uint8_t)0x3F) /*!< RX PAYLOAD WIDTH FOR PIPE 4 REGISTER BIT MASK */ -#define NRF24L01_DI_RX_PW_P4_0 ((uint8_t)0x01) /*!< Bit 0 */ -#define NRF24L01_DI_RX_PW_P4_1 ((uint8_t)0x02) /*!< Bit 1 */ -#define NRF24L01_DI_RX_PW_P4_2 ((uint8_t)0x04) /*!< Bit 2 */ -#define NRF24L01_DI_RX_PW_P4_3 ((uint8_t)0x08) /*!< Bit 3 */ -#define NRF24L01_DI_RX_PW_P4_4 ((uint8_t)0x10) /*!< Bit 4 */ -#define NRF24L01_DI_RX_PW_P4_5 ((uint8_t)0x20) /*!< Bit 5 */ - -#define NRF24L01_DI_RX_PW_P5 ((uint8_t)0x3F) /*!< RX PAYLOAD WIDTH FOR PIPE 5 REGISTER BIT MASK */ -#define NRF24L01_DI_RX_PW_P5_0 ((uint8_t)0x01) /*!< Bit 0 */ -#define NRF24L01_DI_RX_PW_P5_1 ((uint8_t)0x02) /*!< Bit 1 */ -#define NRF24L01_DI_RX_PW_P5_2 ((uint8_t)0x04) /*!< Bit 2 */ -#define NRF24L01_DI_RX_PW_P5_3 ((uint8_t)0x08) /*!< Bit 3 */ -#define NRF24L01_DI_RX_PW_P5_4 ((uint8_t)0x10) /*!< Bit 4 */ -#define NRF24L01_DI_RX_PW_P5_5 ((uint8_t)0x20) /*!< Bit 5 */ - -#define NRF24L01_DI_FIFO_STATUS ((uint8_t)0x73) /*!< FIFO STATUS REGISTER BIT MASK*/ -#define NRF24L01_DI_FIFO_STATUS_RX_EMPTY ((uint8_t)0x01) /*!< RX FIFO empty flag - 0:Data in RX FIFO, 1:RX FIFO empty */ -#define NRF24L01_DI_FIFO_STATUS_RX_FULL ((uint8_t)0x02) /*!< RX FIFO full flag - 0:Available locations in RX FIFO, 1:RX FIFO empty */ -#define NRF24L01_DI_FIFO_STATUS_TX_EMPTY ((uint8_t)0x10) /*!< TX FIFO empty flag - 0:Data in TX FIFO, 1:TX FIFO empty */ -#define NRF24L01_DI_FIFO_STATUS_TX_FULL ((uint8_t)0x20) /*!< TX FIFO full flag - 0:Available locations in TX FIFO, 1:TX FIFO empty */ -#define NRF24L01_DI_FIFO_STATUS_TX_REUSE ((uint8_t)0x40) /*!< Reuse last transmitted data packet if set high */ - -#define NRF24L01_DI_DYNPD ((uint8_t)0x3F) /*!< ENABLE DYNAMIC PAYLOAD LENGHT REGISTER BIT MASK */ -#define NRF24L01_DI_DYNPD_DPL_P0 ((uint8_t)0x01) /*!< Enable dyn. payload length data pipe 0 */ -#define NRF24L01_DI_DYNPD_DPL_P1 ((uint8_t)0x02) /*!< Enable dyn. payload length data pipe 1 */ -#define NRF24L01_DI_DYNPD_DPL_P2 ((uint8_t)0x04) /*!< Enable dyn. payload length data pipe 2 */ -#define NRF24L01_DI_DYNPD_DPL_P3 ((uint8_t)0x08) /*!< Enable dyn. payload length data pipe 3 */ -#define NRF24L01_DI_DYNPD_DPL_P4 ((uint8_t)0x10) /*!< Enable dyn. payload length data pipe 4 */ -#define NRF24L01_DI_DYNPD_DPL_P5 ((uint8_t)0x20) /*!< Enable dyn. payload length data pipe 5 */ - -#define NRF24L01_DI_FEATURE ((uint8_t)0x07) /*!< FEATURE REGISTER REGISTER BIT MASK */ -#define NRF24L01_DI_FEATURE_EN_DYN_ACK ((uint8_t)0x01) /*!< Enables the W_TX_PAYLOAD_NOACK command */ -#define NRF24L01_DI_FEATURE_EN_ACK_PAY ((uint8_t)0x02) /*!< Enables Payload with ACK */ -#define NRF24L01_DI_FEATURE_EN_DPL ((uint8_t)0x04) /*!< Enables Dynamic Payload Length */ -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !(HAL_USE_SPI) -#error "RF_NRF24L01 requires HAL_USE_SPI." -#endif - -#if !(HAL_USE_EXT) -#error "RF_NRF24L01 requires HAL_USE_EXT." -#endif -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @name RF Transceiver data structures and types - * @{ - */ - -/** - * @brief RF Transceiver RX/TX Address field width - */ -typedef enum { - - NRF24L01_AW_3_bytes = 0x01, /*!< 3 bytes width */ - NRF24L01_AW_4_bytes = 0x02, /*!< 4 bytes width */ - NRF24L01_AW_5_bytes = 0x03 /*!< 5 bytes width */ -} NRF24L01_AW_t; - -/** - * @brief RF Transceiver Auto Retransmit Delay - */ -typedef enum { - - NRF24L01_ARD_250us = 0x00, /*!< Wait 250us */ - NRF24L01_ARD_500us = 0x10, /*!< Wait 500us */ - NRF24L01_ARD_750us = 0x20, /*!< Wait 750us */ - NRF24L01_ARD_1000us = 0x30, /*!< Wait 1000us */ - NRF24L01_ARD_1250us = 0x40, /*!< Wait 1250us */ - NRF24L01_ARD_1500us = 0x50, /*!< Wait 1500us */ - NRF24L01_ARD_1750us = 0x60, /*!< Wait 1750us */ - NRF24L01_ARD_2000us = 0x70, /*!< Wait 2000us */ - NRF24L01_ARD_2250us = 0x80, /*!< Wait 2250us */ - NRF24L01_ARD_2500us = 0x90, /*!< Wait 2500us */ - NRF24L01_ARD_2750us = 0xA0, /*!< Wait 2750us */ - NRF24L01_ARD_3000us = 0xB0, /*!< Wait 3000us */ - NRF24L01_ARD_3250us = 0xC0, /*!< Wait 3250us */ - NRF24L01_ARD_3500us = 0xD0, /*!< Wait 3500us */ - NRF24L01_ARD_3750us = 0xE0, /*!< Wait 3750us */ - NRF24L01_ARD_4000us = 0xF0 /*!< Wait 4000us */ -} NRF24L01_ARD_t; - -/** - * @brief RF Transceiver Auto Retransmit Count - */ -typedef enum { - - NRF24L01_ARC_disabled = 0x00, /*!< Re-Transmit disabled */ - NRF24L01_ARC_1_time = 0x01, /*!< Up to 1 Re-Transmit on fail of AA */ - NRF24L01_ARC_2_times = 0x02, /*!< Up to 2 Re-Transmit on fail of AA */ - NRF24L01_ARC_3_times = 0x03, /*!< Up to 3 Re-Transmit on fail of AA */ - NRF24L01_ARC_4_times = 0x04, /*!< Up to 4 Re-Transmit on fail of AA */ - NRF24L01_ARC_5_times = 0x05, /*!< Up to 5 Re-Transmit on fail of AAs */ - NRF24L01_ARC_6_times = 0x06, /*!< Up to 6 Re-Transmit on fail of AA */ - NRF24L01_ARC_7_times = 0x07, /*!< Up to 7 Re-Transmit on fail of AA */ - NRF24L01_ARC_8_times = 0x08, /*!< Up to 8 Re-Transmit on fail of AA */ - NRF24L01_ARC_9_times = 0x09, /*!< Up to 9 Re-Transmit on fail of AA */ - NRF24L01_ARC_10_times = 0x0A, /*!< Up to 10 Re-Transmit on fail of AA */ - NRF24L01_ARC_11_times = 0x0B, /*!< Up to 11 Re-Transmit on fail of AA */ - NRF24L01_ARC_12_times = 0x0C, /*!< Up to 12 Re-Transmit on fail of AA */ - NRF24L01_ARC_13_times = 0x0D, /*!< Up to 13 Re-Transmit on fail of AA */ - NRF24L01_ARC_14_times = 0x0E, /*!< Up to 14 Re-Transmit on fail of AA */ - NRF24L01_ARC_15_times = 0x0F /*!< Up to 15 Re-Transmit on fail of AA */ -} NRF24L01_ARC_t; - - -/** - * @brief RF Transceiver configuration typedef. - * - * @detail This will select frequency channel beetween 2,4 GHz and 2,525 GHz - * @detail according to formula 2,4GHz + RF_CH[MHz]. This value must be included - * @detail between 0 and 125. - */ -typedef uint8_t NRF24L01_RF_CH_t; - -/** - * @brief RF Transceiver Air Data Rate - */ -typedef enum { - - NRF24L01_ADR_1Mbps = 0x00, /*!< Air data rate 1 Mbps */ - NRF24L01_ADR_2Mbps = 0x08 /*!< Air data rate 2 Mbps */ -} NRF24L01_ADR_t; - -/** - * @brief RF Transceiver Output Power - */ -typedef enum { - - NRF24L01_PWR_0dBm = 0x06, /*!< RF output power 0 dBm */ - NRF24L01_PWR_neg6dBm = 0x04, /*!< RF output power -6 dBm */ - NRF24L01_PWR_neg12dBm = 0x02, /*!< RF output power -12 dBm */ - NRF24L01_PWR_neg18dBm = 0x00 /*!< RF output power -18 dBm */ -} NRF24L01_PWR_t; - -/** - * @brief RF Transceiver Low Noise Amplifier - * - * @details Reduce current consumption in RX mode with 0.8 mA at cost of 1.5dB - * reduction in receiver sensitivity. - */ -typedef enum { - NRF24L01_LNA_enabled = 0x01, /*!< LNA_CURR enabled */ - NRF24L01_LNA_disabled = 0x00 /*!< LNA_CURR disabled */ -} NRF24L01_LNA_t; - -/** - * @brief RF Transceiver Backward Compatibility - * - * @details This type specifies if trasmission must be compatible to receive - * from an nRF2401/nRF2402/nRF24E1/nRF24E. - */ -typedef bool_t NRF24L01_bckwrdcmp_t; - -#if NRF24L01_USE_FEATURE || defined(__doxigen__) -/** - * @brief RF Transceiver Dynamic Payload enabler - * - * @details Enables Dynamic Payload Length - */ -typedef enum { - NRF24L01_DPL_enabled = 0x04, /*!< EN_DPL enabled */ - NRF24L01_DPL_disabled = 0x00 /*!< EN_DPL disabled */ -} NRF24L01_DPL_t; - -/** - * @brief RF Transceiver Dynamic Acknowledge with Payload enabler - * - * @details Enables Payload with ACK - */ -typedef enum { - NRF24L01_ACK_PAY_enabled = 0x02, /*!< EN_ACK_PAY enabled */ - NRF24L01_ACK_PAY_disabled = 0x00 /*!< EN_ACK_PAY disabled */ -} NRF24L01_ACK_PAY_t; - -/** - * @brief RF Transceiver Dynamic Acknowledge enabler - * - * @details Enables the W_TX_PAYLOAD_NOACK command - */ -typedef enum { - NRF24L01_DYN_ACK_enabled = 0x01, /*!< EN_DYN_ACK enabled */ - NRF24L01_DYN_ACK_disabled = 0x00 /*!< EN_DYN_ACK disabled */ -} NRF24L01_DYN_ACK_t; -#endif /* NRF24L01_USE_FEATURE */ - -/** - * @brief RF Transceiver configuration structure. - */ -typedef struct { - - /** - * @brief The chip enable line port. - */ - ioportid_t ceport; - /** - * @brief The chip enable line pad number. - */ - uint16_t cepad; - /** - * @brief The interrupt line port. - */ - ioportid_t irqport; - /** - * @brief The interrupt line pad number. - */ - uint16_t irqpad; - /** - * @brief Pointer to the SPI driver associated to this RF. - */ - SPIDriver *spip; - /** - * @brief Pointer to the SPI configuration . - */ - const SPIConfig *spicfg; - /** - * @brief Pointer to the EXT driver associated to this RF. - */ - EXTDriver *extp; - /** - * @brief EXT configuration. - */ - EXTConfig *extcfg; - /** - * @brief RF Transceiver auto retransmit count. - */ - NRF24L01_ARC_t auto_retr_count; - /** - * @brief RF Transceiver auto retransmit delay. - */ - NRF24L01_ARD_t auto_retr_delay; - /** - * @brief RF Transceiver address width. - */ - NRF24L01_AW_t address_width; - /** - * @brief RF Transceiver channel frequency. - */ - NRF24L01_RF_CH_t channel_freq; - /** - * @brief RF Transceiver air data rate. - */ - NRF24L01_ADR_t data_rate; - /** - * @brief RF Transceiver output power. - */ - NRF24L01_PWR_t out_pwr; - /** - * @brief RF Transceiver Low Noise Amplifier - */ - NRF24L01_LNA_t lna; -#if NRF24L01_USE_FEATURE || defined(__doxigen__) - /** - * @brief RF Transceiver Dynamic Payload enabler - */ - NRF24L01_DPL_t en_dpl; - - /** - * @brief RF Transceiver Dynamic Acknowledge with Payload enabler - */ - NRF24L01_ACK_PAY_t en_ack_pay; - - /** - * @brief RF Transceiver Dynamic Acknowledge enabler - */ - NRF24L01_DYN_ACK_t en_dyn_ack; -#endif /* NRF24L01_USE_FEATURE */ -} NRF24L01_Config; - -/** - * @brief RF Transceiver status register value. - */ -typedef uint8_t NRF24L01_status_t; -/** @} */ -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/** - * @brief Flushes FIFOs and resets all Status flags. - * - * @pre The SPI interface must be initialized and the driver started. - * - * @param[in] spip pointer to the SPI interface - * - * @return the status register value - */ -#define nrf24l01Reset(spip) { \ - \ - nrf24l01WriteRegister(spip, NRF24L01_AD_STATUS, \ - NRF24L01_DI_STATUS_MAX_RT | \ - NRF24L01_DI_STATUS_RX_DR | \ - NRF24L01_DI_STATUS_TX_DS); \ -} - -#ifdef __cplusplus -extern "C" { -#endif -NRF24L01_status_t nrf24l01GetStatus(SPIDriver *spip); -NRF24L01_status_t nrf24l01ReadRegister(SPIDriver *spip, uint8_t reg, - uint8_t* pvalue); -NRF24L01_status_t nrf24l01WriteRegister(SPIDriver *spip, uint8_t reg, - uint8_t value); -NRF24L01_status_t nrf24l01WriteAddress(SPIDriver *spip, uint8_t reg, - uint8_t *pvalue, uint8_t addlen); -NRF24L01_status_t nrf24l01GetRxPl(SPIDriver *spip, uint8_t paylen, - uint8_t* rxbuf); -NRF24L01_status_t nrf24l01WriteTxPl(SPIDriver *spip, uint8_t paylen, - uint8_t* txbuf); -NRF24L01_status_t nrf24l01FlushTx(SPIDriver *spip); -NRF24L01_status_t nrf24l01FlushRx(SPIDriver *spip); -#if NRF24L01_USE_FEATURE || defined(__DOXYGEN__) -NRF24L01_status_t nrf24l01Activate(SPIDriver *spip); -NRF24L01_status_t nrf24l01ReadRxPlWid(SPIDriver *spip, uint8_t* ppaylen); -NRF24L01_status_t nrf24l01WriteAckPl(SPIDriver *spip, uint8_t ppp, uint8_t paylen, - uint8_t* payload); -NRF24L01_status_t nrf24l01WriteTxPlNoAck(SPIDriver *spip, uint8_t paylen, - uint8_t* txbuf); -#endif /* NRF24L01_USE_FEATURE */ -#ifdef __cplusplus -} -#endif - -#endif /* _NRF24L01_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/various/devices_lib/sensors/hdc1000.c b/firmware/ChibiOS_16/community/os/various/devices_lib/sensors/hdc1000.c deleted file mode 100644 index 39e47ecb98..0000000000 --- a/firmware/ChibiOS_16/community/os/various/devices_lib/sensors/hdc1000.c +++ /dev/null @@ -1,265 +0,0 @@ -/* - HDC100x for ChibiOS/RT - Copyright (C) 2016 Stephane D'Alu - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file HDC1000.c - * @brief HDC1000 interface module code. - * - * @addtogroup hdc1000 - * @{ - */ - -#define I2C_HELPERS_AUTOMATIC_DRV TRUE - -#include "hal.h" -#include "i2c_helpers.h" -#include "hdc1000.h" - -/* DOC: http://www.ti.com/lit/ds/symlink/hdc1008.pdf - */ - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/* I2C Register */ -#define HDC1000_REG_TEMP_HUMID 0x00 -#define HDC1000_REG_TEMP 0x00 -#define HDC1000_REG_HUMID 0x01 -#define HDC1000_REG_CONFIG 0x02 -#define HDC1000_REG_SERIAL 0xFB -#define HDC1000_REG_SERIAL_1 0xFB -#define HDC1000_REG_SERIAL_2 0xFC -#define HDC1000_REG_SERIAL_3 0xFD -#define HDC1000_REG_MANUF_ID 0xFE -#define HDC1000_REG_DEVICE_ID 0xFF - -/* Configuration */ -#define HDC1000_CONFIG_RST (1 << 15) -#define HDC1000_CONFIG_HEATER (1 << 13) -#define HDC1000_CONFIG_MODE_ONE (0 << 12) -#define HDC1000_CONFIG_MODE_BOTH (1 << 12) -#define HDC1000_CONFIG_BATT (1 << 11) -#define HDC1000_CONFIG_TRES_14 (0) -#define HDC1000_CONFIG_TRES_11 (1 << 10) -#define HDC1000_CONFIG_HRES_14 (0) -#define HDC1000_CONFIG_HRES_11 (1 << 8) -#define HDC1000_CONFIG_HRES_8 (1 << 9) - -/* Value */ -#define HDC1000_MANUF_ID 0x5449 -#define HDC1000_DEVICE_ID 0x1000 - -/* Delay in micro seconds */ -#define HDC1000_DELAY_ACQUIRE_SAFETY 1000 -#define HDC1000_DELAY_ACQUIRE_TRES_14 6350 -#define HDC1000_DELAY_ACQUIRE_TRES_11 3650 -#define HDC1000_DELAY_ACQUIRE_HRES_14 6500 -#define HDC1000_DELAY_ACQUIRE_HRES_11 3850 -#define HDC1000_DELAY_ACQUIRE_HRES_8 2500 -#define HDC1000_DELAY_STARTUP 15000 - -// Deefault config (high res) -#define HDC1000_CONFIG_RES (HDC1000_CONFIG_TRES_14 | \ - HDC1000_CONFIG_HRES_14) -#define HDC1000_DELAY_ACQUIRE (HDC1000_DELAY_ACQUIRE_TRES_14 + \ - HDC1000_DELAY_ACQUIRE_HRES_14) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static inline msg_t -_apply_config(HDC1000_drv *drv) { - struct __attribute__((packed)) { - uint8_t reg; - uint16_t conf; - } tx = { HDC1000_REG_CONFIG, cpu_to_be16(drv->cfg) }; - - return i2c_send((uint8_t*)&tx, sizeof(tx)); -} - -static inline msg_t -_decode_measure(HDC1000_drv *drv, - uint32_t val, float *temperature, float *humidity) { - (void)drv; - - /* Temperature */ - if (temperature) { - float temp = (val >> 16); - temp /= 65536; - temp *= 165; - temp -= 40; - *temperature = temp; - } - - /* Humidiy */ - if (humidity) { - float hum = (val & 0xFFFF); - hum /= 65535; - hum *= 100; - *humidity = hum; - } - - /* ok */ - return MSG_OK; -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -void -HDC1000_init(HDC1000_drv *drv, HDC1000_config *config) { - drv->config = config; - drv->cfg = HDC1000_CONFIG_RST | HDC1000_CONFIG_MODE_BOTH | - HDC1000_CONFIG_RES; - drv->delay = (HDC1000_DELAY_ACQUIRE + - HDC1000_DELAY_ACQUIRE_SAFETY) / 1000; - drv->state = SENSOR_INIT; -} - -msg_t -HDC1000_check(HDC1000_drv *drv) { - uint16_t manuf, device; - - msg_t msg; - if (((msg = i2c_reg_recv16_be(HDC1000_REG_MANUF_ID, &manuf )) < MSG_OK) || - ((msg = i2c_reg_recv16_be(HDC1000_REG_DEVICE_ID, &device)) < MSG_OK)) - return msg; - - if ((manuf != HDC1000_MANUF_ID) || (device != HDC1000_DEVICE_ID)) - return SENSOR_NOTFOUND; - - return MSG_OK; -} - - -msg_t -HDC1000_start(HDC1000_drv *drv) { - osalDbgAssert((drv->state == SENSOR_INIT ) || - (drv->state == SENSOR_ERROR ) || - (drv->state == SENSOR_STOPPED), - "invalid state"); - msg_t msg; - if ((msg = _apply_config(drv)) < MSG_OK) { - drv->state = SENSOR_ERROR; - return msg; - } - drv->state = SENSOR_STARTED; - return MSG_OK; -} - -msg_t -HDC1000_stop(HDC1000_drv *drv) { - drv->state = SENSOR_STOPPED; - return MSG_OK; -} - -msg_t -HDC1000_setHeater(HDC1000_drv *drv, bool on) { - if (on) { drv->cfg |= HDC1000_CONFIG_HEATER; } - else { drv->cfg &= ~HDC1000_CONFIG_HEATER; } - - msg_t msg; - if ((msg = _apply_config(drv)) < MSG_OK) { - drv->state = SENSOR_ERROR; - return msg; - } - return MSG_OK; -} - -msg_t -HDC1000_startMeasure(HDC1000_drv *drv) { - msg_t msg; - osalDbgAssert(drv->state == SENSOR_STARTED, "invalid state"); - if ((msg = i2c_reg(HDC1000_REG_TEMP_HUMID)) < MSG_OK) - return msg; - drv->state = SENSOR_MEASURING; - return MSG_OK; -} - - -msg_t -HDC1000_readSerial(HDC1000_drv *drv, uint8_t *serial) { - msg_t msg; - osalDbgAssert(drv->state == SENSOR_STARTED, "invalid state"); - - if (((msg = i2c_reg_recv16(HDC1000_REG_SERIAL_1, - (uint16_t*)&serial[0])) < MSG_OK) || - ((msg = i2c_reg_recv16(HDC1000_REG_SERIAL_2, - (uint16_t*)&serial[2])) < MSG_OK) || - ((msg = i2c_reg_recv8 (HDC1000_REG_SERIAL_3, - (uint8_t*) &serial[4])) < MSG_OK)) - return msg; - return MSG_OK; -} - - -msg_t -HDC1000_readMeasure(HDC1000_drv *drv, - float *temperature, float *humidity) { - msg_t msg; - uint32_t val; - - osalDbgAssert((drv->state == SENSOR_MEASURING) || - (drv->state == SENSOR_READY ), - "invalid state"); - - if ((msg = i2c_recv32_be(&val)) < MSG_OK) { - drv->state = SENSOR_ERROR; - return msg; - } - - drv->state = SENSOR_STARTED; - - return _decode_measure(drv, val, temperature, humidity); -} - -msg_t -HDC1000_readTemperatureHumidity(HDC1000_drv *drv, - float *temperature, float *humidity) { - msg_t msg; - uint32_t val; - - osalDbgAssert(drv->state == SENSOR_STARTED, "invalid state"); - - /* Request value */ - if ((msg = i2c_reg(HDC1000_REG_TEMP_HUMID)) < MSG_OK) - return msg; - - /* Wait */ - osalThreadSleepMilliseconds(drv->delay); - - /* Get value */ - if ((msg = i2c_recv32_be(&val)) < MSG_OK) { - drv->state = SENSOR_ERROR; - return msg; - } - - return _decode_measure(drv, val, temperature, humidity); -} - - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/various/devices_lib/sensors/hdc1000.h b/firmware/ChibiOS_16/community/os/various/devices_lib/sensors/hdc1000.h deleted file mode 100644 index e4eae4c6a3..0000000000 --- a/firmware/ChibiOS_16/community/os/various/devices_lib/sensors/hdc1000.h +++ /dev/null @@ -1,240 +0,0 @@ -/* - HDC100x for ChibiOS/RT - Copyright (C) 2016 Stephane D'Alu - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hdc1000.h - * @brief HDC1000 Temperature/Humidiry sensor interface module header. - * - * When changing sensor settings, you generally need to wait - * for 2 * getAquisitionTime(), as usually the first acquisition - * will be corrupted by the change of settings. - * - * No locking is done. - * - * @{ - */ - -#ifndef _SENSOR_HDC1000_H_ -#define _SENSOR_HDC1000_H_ - -#include -#include -#include "i2c_helpers.h" -#include "sensor.h" - - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#define HDC1000_CONTINUOUS_ACQUISITION_SUPPORTED FALSE - -/* I2C address */ -#define HDC1000_I2CADDR_1 0x40 -#define HDC1000_I2CADDR_2 0x41 -#define HDC1000_I2CADDR_3 0x42 -#define HDC1000_I2CADDR_4 0x43 - -#define HDC1000_SERIAL_SIZE 5 /**< @brief Size of serial (40bits) */ - -/** - * @brief Time necessary for the sensor to boot - */ -#define HDC1000_BOOTUP_TIME 15 - -/** - * @brief Time necessary for the sensor to start - */ -#define HDC1000_STARTUP_TIME 0 - - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#define HDC1000_I2CADDR_DEFAULT HDC1000_I2CADDR_1 - - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief HDC1000 configuration structure. - */ -typedef struct { - I2CHelper i2c; /* keep it first */ -} HDC1000_config; - -/** - * @brief HDC1000 configuration structure. - */ -typedef struct { - HDC1000_config *config; - sensor_state_t state; - unsigned int delay; - uint16_t cfg; -} HDC1000_drv; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/** - * @brief Initialize the sensor driver - */ -void -HDC1000_init(HDC1000_drv *drv, - HDC1000_config *config); - -/** - * @brief Start the sensor - */ -msg_t -HDC1000_start(HDC1000_drv *drv); - -/** - * @brief Stop the sensor - * - * @details If the sensor support it, it will be put in low energy mode. - */ -msg_t -HDC1000_stop(HDC1000_drv *drv); - -/** - * @brief Check that the sensor is really present - */ -msg_t -HDC1000_check(HDC1000_drv *drv); - - -msg_t -HDC1000_readSerial(HDC1000_drv *drv, uint8_t *serial); - -/** - * @brief Control the HD1000 heater. - */ -msg_t -HDC1000_setHeater(HDC1000_drv *drv, - bool on); - - - -/** - * @brief Time in milli-seconds necessary for acquiring a naw measure - * - * @returns - * unsigned int time in millis-seconds - */ -static inline unsigned int -HDC1000_getAcquisitionTime(HDC1000_drv *drv) { - return drv->delay; -} - -/** - * @brief Trigger a mesure acquisition - */ -msg_t -HDC1000_startMeasure(HDC1000_drv *drv); - -/** - * @brief Read the newly acquiered measure - * - * @note According the the sensor design the measure read - * can be any value acquired after the acquisition time - * and the call to readMeasure. - */ -msg_t -HDC1000_readMeasure(HDC1000_drv *drv, - float *temperature, float *humidity); - - -/** - * @brief Read temperature and humidity - * - * @details According to the sensor specification/configuration - * (see #HDC1000_CONTINUOUS_ACQUISITION_SUPPORTED), - * if the sensor is doing continuous measurement - * it's value will be requested and returned immediately. - * Otherwise a measure is started, the necessary amount of - * time for acquiring the value is spend sleeping (not spinning), - * and finally the measure is read. - * - * @note In continuous measurement mode, if you just started - * the sensor, you will need to wait getAcquisitionTime() - * in addition to the usual #HDC1000_STARTUP_TIME - - * @note If using several sensors, it is better to start all the - * measure together, wait for the sensor having the longuest - * aquisition time, and finally read all the values - */ -msg_t -HDC1000_readTemperatureHumidity(HDC1000_drv *drv, - float *temperature, float *humidity); - -/** - * @brief Return the humidity value in percent. - * - * @details Use readTemperatureHumidity() for returning the humidity value. - * - * @note Prefere readTemperatureHumidity(), if you need both temperature - * and humidity, or if you need better error handling. - * - * @returns - * float humidity percent - * NAN on failure - */ -static inline float -HDC1000_getHumidity(HDC1000_drv *drv) { - float humidity = NAN; - HDC1000_readTemperatureHumidity(drv, NULL, &humidity); - return humidity; -} - -/** - * @brief Return the temperature value in °C. - * - * @details Use readTemperatureHumidity() for returning the humidity value. - * - * @note Prefere readTemperatureHumidity(), if you need both temperature - * and humidity, or if you need better error handling. - * - * @returns - * float humidity percent - * NAN on failure - */ -static inline float -HDC1000_getTemperature(HDC1000_drv *drv) { - float temperature = NAN; - HDC1000_readTemperatureHumidity(drv, &temperature, NULL); - return temperature; -} - - -#endif - -/** - * @} - */ diff --git a/firmware/ChibiOS_16/community/os/various/devices_lib/sensors/mcp9808.c b/firmware/ChibiOS_16/community/os/various/devices_lib/sensors/mcp9808.c deleted file mode 100644 index 4b22ea9f34..0000000000 --- a/firmware/ChibiOS_16/community/os/various/devices_lib/sensors/mcp9808.c +++ /dev/null @@ -1,207 +0,0 @@ -/* - MCP9808 for ChibiOS/RT - Copyright (C) 2016 Stephane D'Alu - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#define I2C_HELPERS_AUTOMATIC_DRV TRUE - -#include "hal.h" -#include "i2c_helpers.h" -#include "mcp9808.h" - -// http://www.mouser.com/ds/2/268/25095A-15487.pdf -// http://ww1.microchip.com/downloads/en/DeviceDoc/25095A.pdf - - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/* I2C Register */ -#define MCP9808_REG_CONFIG 0x01 -#define MCP9808_REG_UPPER_TEMP 0x02 -#define MCP9808_REG_LOWER_TEMP 0x03 -#define MCP9808_REG_CRIT_TEMP 0x04 -#define MCP9808_REG_AMBIENT_TEMP 0x05 -#define MCP9808_REG_MANUF_ID 0x06 -#define MCP9808_REG_DEVICE_ID 0x07 -#define MCP9808_REG_RESOLUTION 0x08 - -/* Config */ -#define MCP9808_REG_CONFIG_SHUTDOWN 0x0100 -#define MCP9808_REG_CONFIG_CRITLOCKED 0x0080 -#define MCP9808_REG_CONFIG_WINLOCKED 0x0040 -#define MCP9808_REG_CONFIG_INTCLR 0x0020 -#define MCP9808_REG_CONFIG_ALERTSTAT 0x0010 -#define MCP9808_REG_CONFIG_ALERTCTRL 0x0008 -#define MCP9808_REG_CONFIG_ALERTSEL 0x0002 -#define MCP9808_REG_CONFIG_ALERTPOL 0x0002 -#define MCP9808_REG_CONFIG_ALERTMODE 0x0001 - -/* Device Id */ -#define MCP9808_MANUF_ID 0x0054 -#define MCP9808_DEVICE_ID 0x0400 - -/* Resolution */ -#define MCP9808_RES_2 0x00 /* 1/2 = 0.5 */ -#define MCP9808_RES_4 0x01 /* 1/4 = 0.25 */ -#define MCP9808_RES_8 0x10 /* 1/8 = 0.125 */ -#define MCP9808_RES_16 0x11 /* 1/16 = 0.0625 */ - -/* Time in milli-seconds */ -#define MCP9808_DELAY_ACQUIRE_RES_2 30 -#define MCP9808_DELAY_ACQUIRE_RES_4 65 -#define MCP9808_DELAY_ACQUIRE_RES_8 130 -#define MCP9808_DELAY_ACQUIRE_RES_16 250 - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static inline msg_t -_apply_config(MCP9808_drv *drv) { - struct __attribute__((packed)) { - uint8_t reg; - uint16_t conf; - } tx = { MCP9808_REG_CONFIG, cpu_to_be16(drv->cfg) }; - - return i2c_send((uint8_t*)&tx, sizeof(tx)); -} - -static inline msg_t -_decode_measure(MCP9808_drv *drv, - uint16_t val, float *temperature) { - - /* Temperature */ - if (temperature) { - float temp = val & 0x0fff; - if (val & 0x1000) temp -= 0x1000; - - float factor = 16.0F; - switch(drv->resolution) { - case RES_2 : factor = 2.0F; break; - case RES_4 : factor = 4.0F; break; - case RES_8 : factor = 8.0F; break; - case RES_16: factor = 16.0F; break; - } - - *temperature = temp / factor; - } - - /* Ok */ - return MSG_OK; -} - - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -void -MCP9808_init(MCP9808_drv *drv, MCP9808_config *config) { - drv->config = config; - drv->cfg = 0; - drv->resolution = RES_16; /* power up default */ - drv->state = SENSOR_INIT; -} - -msg_t -MCP9808_check(MCP9808_drv *drv) { - uint16_t manuf, device; - - msg_t msg; - if (((msg = i2c_reg_recv16_be(MCP9808_REG_MANUF_ID, &manuf )) < MSG_OK) || - ((msg = i2c_reg_recv16_be(MCP9808_REG_DEVICE_ID, &device)) < MSG_OK)) - return msg; - - if ((manuf != MCP9808_MANUF_ID) || (device != MCP9808_DEVICE_ID)) - return SENSOR_NOTFOUND; - - return MSG_OK; -} - -msg_t -MCP9808_setResolution(MCP9808_drv *drv, MCP9808_resolution_t res) { - struct __attribute__((packed)) { - uint8_t reg; - uint8_t resolution; - } tx = { MCP9808_REG_RESOLUTION, res }; - - msg_t msg; - if ((msg = i2c_send((uint8_t*)&tx, sizeof(tx))) < MSG_OK) - return msg; - - drv->resolution = res; - return MSG_OK; -} - -msg_t -MCP9808_start(MCP9808_drv *drv) { - drv->cfg &= ~(MCP9808_REG_CONFIG_SHUTDOWN); - return _apply_config(drv); -} - -msg_t -MCP9808_stop(MCP9808_drv *drv) { - drv->cfg |= (MCP9808_REG_CONFIG_SHUTDOWN); - return _apply_config(drv); -} - -unsigned int -MCP9808_getAcquisitionTime(MCP9808_drv *drv) { - switch(drv->resolution) { - case RES_2 : return MCP9808_DELAY_ACQUIRE_RES_2; - case RES_4 : return MCP9808_DELAY_ACQUIRE_RES_4; - case RES_8 : return MCP9808_DELAY_ACQUIRE_RES_8; - case RES_16: return MCP9808_DELAY_ACQUIRE_RES_16; - } - osalDbgAssert(false, "OOPS"); - return 0; -} - -msg_t -MCP9808_readMeasure(MCP9808_drv *drv, - float *temperature) { - - msg_t msg; - uint16_t val; - - if ((msg = i2c_reg_recv16_be(MCP9808_REG_AMBIENT_TEMP, &val)) < MSG_OK) - return msg; - - return _decode_measure(drv, val, temperature); -} - - -msg_t -MCP9808_readTemperature(MCP9808_drv *drv, - float *temperature) { - osalDbgAssert(drv->state == SENSOR_STARTED, "invalid state"); - - msg_t msg; - uint16_t val; - - if ((msg = i2c_reg_recv16_be(MCP9808_REG_AMBIENT_TEMP, &val)) < MSG_OK) - return msg; - - return _decode_measure(drv, val, temperature); -} diff --git a/firmware/ChibiOS_16/community/os/various/devices_lib/sensors/mcp9808.h b/firmware/ChibiOS_16/community/os/various/devices_lib/sensors/mcp9808.h deleted file mode 100644 index 857f2f98bd..0000000000 --- a/firmware/ChibiOS_16/community/os/various/devices_lib/sensors/mcp9808.h +++ /dev/null @@ -1,204 +0,0 @@ -/* - MCP9808 for ChibiOS/RT - Copyright (C) 2016 Stephane D'Alu - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef _SENSOR_MCP9808_H_ -#define _SENSOR_MCP9808_H_ - -#include -#include "i2c_helpers.h" -#include "sensor.h" - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#define MCP9808_CONTINUOUS_ACQUISITION_SUPPORTED TRUE - - -#define MCP9808_I2CADDR_FIXED 0x18 - -/** - * @brief Time necessary for the sensor to boot - */ -#define MCP9808_BOOTUP_TIME 0 - -/** - * @brief Time necessary for the sensor to start - */ -#define MCP9808_STARTUP_TIME 0 - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#define MCP9808_I2CADDR_DEFAULT MCP9808_I2CADDR_FIXED - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Different possible resolution - */ -typedef enum { - RES_2 = 0x00, /**< @brief Resolution of 1/2 = 0.5 */ - RES_4 = 0x01, /**< @brief Resolution of 1/4 = 0.25 */ - RES_8 = 0x10, /**< @brief Resolution of 1/8 = 0.125 */ - RES_16 = 0x11, /**< @brief Resolution of 1/16 = 0.0625 */ -} MCP9808_resolution_t; - -/** - * @brief MCP9808 configuration structure. - */ -typedef struct { - I2CHelper i2c; /* keep it first */ -} MCP9808_config; - -/** - * @brief MCP9808 configuration structure. - */ -typedef struct { - MCP9808_config *config; - sensor_state_t state; - MCP9808_resolution_t resolution; - uint16_t cfg; -} MCP9808_drv; - -/** - * @brief MCP9808 measure reading - */ -typedef struct { - float temperature; -} MCP9808_measure; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/** - * @brief Initialize the sensor driver - */ -void -MCP9808_init(MCP9808_drv *drv, - MCP9808_config *config); - -/** - * @brief Check that the sensor is really present - */ -msg_t -MCP9808_check(MCP9808_drv *drv); - -/** - * @brief Start the sensor - */ -msg_t -MCP9808_start(MCP9808_drv *drv); - -/** - * @brief Stop the sensor - * - * @details If the sensor support it, it will be put in low energy mode. - */ -msg_t -MCP9808_stop(MCP9808_drv *drv); - -/** - * @brief Control the MCP9809 resolution. - */ -msg_t -MCP9808_setResolution(MCP9808_drv *drv, - MCP9808_resolution_t res); - -/** - * @brief Time in milli-seconds necessary for acquiring a naw measure - * - * @returns - * unsigned int time in millis-seconds - */ -unsigned int -MCP9808_getAcquisitionTime(MCP9808_drv *drv); - -/** - * @brief Trigger a mesure acquisition - */ -static inline msg_t -MCP9808_startMeasure(MCP9808_drv *drv) { - (void)drv; - return MSG_OK; -} - -/** - * @brief Read the newly acquiered measure - * - * @note According the the sensor design the measure read - * can be any value acquired after the acquisition time - * and the call to readMeasure. - */ -msg_t -MCP9808_readMeasure(MCP9808_drv *drv, - float *temperature); - - -/** - * @brief Read temperature and humidity - * - * @details According to the sensor specification/configuration - * (see #MCP9808_CONTINUOUS_ACQUISITION_SUPPORTED), - * if the sensor is doing continuous measurement - * it's value will be requested and returned immediately. - * Otherwise a measure is started, the necessary amount of - * time for acquiring the value is spend sleeping (not spinning), - * and finally the measure is read. - * - * @note In continuous measurement mode, if you just started - * the sensor, you will need to wait getAcquisitionTime() - * in addition to the usual getStartupTime() - - * @note If using several sensors, it is better to start all the - * measure together, wait for the sensor having the longuest - * aquisition time, and finally read all the values - */ -msg_t -MCP9808_readTemperature(MCP9808_drv *drv, - float *temperature); - -/** - * @brief Return the temperature value in °C. - * - * @note Prefere readTemperature(), if you need better error handling. - * - * @return The temperature in °C - * @retval float humidity percent - * @retval NAN on failure - */ -static inline float -MCP9808_getTemperature(MCP9808_drv *drv) { - float temperature = NAN; - MCP9808_readTemperature(drv, &temperature); - return temperature; -} - -#endif - diff --git a/firmware/ChibiOS_16/community/os/various/devices_lib/sensors/sensor.h b/firmware/ChibiOS_16/community/os/various/devices_lib/sensors/sensor.h deleted file mode 100644 index bd544b1338..0000000000 --- a/firmware/ChibiOS_16/community/os/various/devices_lib/sensors/sensor.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - Copyright (C) 2016 Stephane D'Alu - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * - * Example of function calls. - * - * @code - * static SENSOR_config sensor_config = { - * }; - * static SENSOR_drv sensor_drv; - * @endcode - * - * - * @code - * osalThreadSleepMilliseconds(SENSOR_BOOTUP_TIME); - * SENSOR_init(&sensor_drv); - * @endcode - * - * @code - * SENSOR_start(&sensor_drv, &sensor_config); - * osalThreadSleepMilliseconds(SENSOR_STARTUP_TIME); - * @endcode - * - * If using SENSOR_startMeasure()/SENSOR_readMeasure() - * @code - * while(true) { - * SENSOR_startMeasure(&sensor_drv); - * osalThreadSleepMilliseconds(SENSOR_getAcquisitionTime()); - * SENSOR_readMeasure(&sensor_drv, ...); - * } - * @endcode - * - * If using SENSOR_readValue() or SENSOR_getValue() - * @code - * #if SENSOR_CONTINUOUS_ACQUISITION_SUPPORTED == TRUE - * osalThreadSleepMilliseconds(SENSOR_getAcquisitionTime()) - * #endif - * - * while(true) { - * SENSOR_readValue(&sensor_drv, ...); - * } - * @encode - */ -#ifndef _SENSOR_H_ -#define _SENSOR_H_ - -#define SENSOR_OK MSG_OK /**< @brief Operation successful. */ -#define SENSOR_TIMEOUT MSG_TIMEOUT /**< @brief Communication timeout */ -#define SENSOR_RESET MSG_REST /**< @brief Communication error. */ -#define SENSOR_NOTFOUND (msg_t)-20 /**< @brief Sensor not found. */ - - -/** - * @brief Driver state machine possible states. - */ -typedef enum __attribute__ ((__packed__)) { - SENSOR_UNINIT = 0, /**< Not initialized. */ - SENSOR_INIT = 1, /**< Initialized. */ - SENSOR_STARTED = 2, /**< Started. */ - SENSOR_MEASURING = 4, /**< Measuring. */ - SENSOR_READY = 3, /**< Ready. */ - SENSOR_STOPPED = 5, /**< Stopped. */ - SENSOR_ERROR = 6, /**< Error. */ -} sensor_state_t; - -#endif - - diff --git a/firmware/ChibiOS_16/community/os/various/devices_lib/sensors/tsl2561.c b/firmware/ChibiOS_16/community/os/various/devices_lib/sensors/tsl2561.c deleted file mode 100644 index a4ac8ec567..0000000000 --- a/firmware/ChibiOS_16/community/os/various/devices_lib/sensors/tsl2561.c +++ /dev/null @@ -1,386 +0,0 @@ -/* - TSL2561 for ChibiOS/RT - Copyright (C) 2016 Stephane D'Alu - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * Illuminance calculation code provided by www.taosinc.com - * DOC: http://ams.com/eng/content/download/250096/975518/143687 - */ -#define I2C_HELPERS_AUTOMATIC_DRV TRUE - -#include "hal.h" -#include "i2c_helpers.h" -#include "tsl2561.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -// Integration time in µs -#define TSL2561_DELAY_INTTIME_SHORT 13700 // 13.7 ms -#define TSL2561_DELAY_INTTIME_MEDIUM 120000 // 120.0 ms -#define TSL2561_DELAY_INTTIME_LONG 450000 // 450.0 ms - - -#define TSL2561_COMMAND_BIT (0x80) -#define TSL2561_CLEAR_BIT (0x40) -#define TSL2561_WORD_BIT (0x20) -#define TSL2561_BLOCK_BIT (0x10) - -#define TSL2561_CONTROL_POWERON (0x03) -#define TSL2561_CONTROL_POWEROFF (0x00) - -#define TSL2561_LUX_LUXSCALE (14) -#define TSL2561_LUX_RATIOSCALE (9) -#define TSL2561_LUX_CHSCALE (10) // Scale channel values by 2^10 -#define TSL2561_LUX_CHSCALE_TINT0 (0x7517) // 322/11 * 2^TSL2561_LUX_CHSCALE -#define TSL2561_LUX_CHSCALE_TINT1 (0x0FE7) // 322/81 * 2^TSL2561_LUX_CHSCALE - - -// I2C Register -#define TSL2561_REG_CONTROL 0x00 -#define TSL2561_REG_TIMING 0x01 -#define TSL2561_REG_THRESHHOLDLLOW 0x02 -#define TSL2561_REG_THRESHHOLDLHIGH 0x03 -#define TSL2561_REG_THRESHHOLDHLOW 0x04 -#define TSL2561_REG_THRESHHOLDHHIGH 0x05 -#define TSL2561_REG_INTERRUPT 0x06 -#define TSL2561_REG_CRC 0x08 -#define TSL2561_REG_ID 0x0A -#define TSL2561_REG_DATA0LOW 0x0C -#define TSL2561_REG_DATA0HIGH 0x0D -#define TSL2561_REG_DATA1LOW 0x0E -#define TSL2561_REG_DATA1HIGH 0x0F - - -// Auto-gain thresholds -#define TSL2561_AGC_THI_SHORT (4850) // Max value at Ti 13ms = 5047 -#define TSL2561_AGC_TLO_SHORT (100) -#define TSL2561_AGC_THI_MEDIUM (36000) // Max value at Ti 101ms = 37177 -#define TSL2561_AGC_TLO_MEDIUM (200) -#define TSL2561_AGC_THI_LONG (63000) // Max value at Ti 402ms = 65535 -#define TSL2561_AGC_TLO_LONG (500) - -// Clipping thresholds -#define TSL2561_CLIPPING_SHORT (4900) -#define TSL2561_CLIPPING_MEDIUM (37000) -#define TSL2561_CLIPPING_LONG (65000) - -// T, FN and CL package values -#define TSL2561_LUX_K1T (0x0040) // 0.125 * 2^RATIO_SCALE -#define TSL2561_LUX_B1T (0x01f2) // 0.0304 * 2^LUX_SCALE -#define TSL2561_LUX_M1T (0x01be) // 0.0272 * 2^LUX_SCALE -#define TSL2561_LUX_K2T (0x0080) // 0.250 * 2^RATIO_SCALE -#define TSL2561_LUX_B2T (0x0214) // 0.0325 * 2^LUX_SCALE -#define TSL2561_LUX_M2T (0x02d1) // 0.0440 * 2^LUX_SCALE -#define TSL2561_LUX_K3T (0x00c0) // 0.375 * 2^RATIO_SCALE -#define TSL2561_LUX_B3T (0x023f) // 0.0351 * 2^LUX_SCALE -#define TSL2561_LUX_M3T (0x037b) // 0.0544 * 2^LUX_SCALE -#define TSL2561_LUX_K4T (0x0100) // 0.50 * 2^RATIO_SCALE -#define TSL2561_LUX_B4T (0x0270) // 0.0381 * 2^LUX_SCALE -#define TSL2561_LUX_M4T (0x03fe) // 0.0624 * 2^LUX_SCALE -#define TSL2561_LUX_K5T (0x0138) // 0.61 * 2^RATIO_SCALE -#define TSL2561_LUX_B5T (0x016f) // 0.0224 * 2^LUX_SCALE -#define TSL2561_LUX_M5T (0x01fc) // 0.0310 * 2^LUX_SCALE -#define TSL2561_LUX_K6T (0x019a) // 0.80 * 2^RATIO_SCALE -#define TSL2561_LUX_B6T (0x00d2) // 0.0128 * 2^LUX_SCALE -#define TSL2561_LUX_M6T (0x00fb) // 0.0153 * 2^LUX_SCALE -#define TSL2561_LUX_K7T (0x029a) // 1.3 * 2^RATIO_SCALE -#define TSL2561_LUX_B7T (0x0018) // 0.00146 * 2^LUX_SCALE -#define TSL2561_LUX_M7T (0x0012) // 0.00112 * 2^LUX_SCALE -#define TSL2561_LUX_K8T (0x029a) // 1.3 * 2^RATIO_SCALE -#define TSL2561_LUX_B8T (0x0000) // 0.000 * 2^LUX_SCALE -#define TSL2561_LUX_M8T (0x0000) // 0.000 * 2^LUX_SCALE - -// CS package values -#define TSL2561_LUX_K1C (0x0043) // 0.130 * 2^RATIO_SCALE -#define TSL2561_LUX_B1C (0x0204) // 0.0315 * 2^LUX_SCALE -#define TSL2561_LUX_M1C (0x01ad) // 0.0262 * 2^LUX_SCALE -#define TSL2561_LUX_K2C (0x0085) // 0.260 * 2^RATIO_SCALE -#define TSL2561_LUX_B2C (0x0228) // 0.0337 * 2^LUX_SCALE -#define TSL2561_LUX_M2C (0x02c1) // 0.0430 * 2^LUX_SCALE -#define TSL2561_LUX_K3C (0x00c8) // 0.390 * 2^RATIO_SCALE -#define TSL2561_LUX_B3C (0x0253) // 0.0363 * 2^LUX_SCALE -#define TSL2561_LUX_M3C (0x0363) // 0.0529 * 2^LUX_SCALE -#define TSL2561_LUX_K4C (0x010a) // 0.520 * 2^RATIO_SCALE -#define TSL2561_LUX_B4C (0x0282) // 0.0392 * 2^LUX_SCALE -#define TSL2561_LUX_M4C (0x03df) // 0.0605 * 2^LUX_SCALE -#define TSL2561_LUX_K5C (0x014d) // 0.65 * 2^RATIO_SCALE -#define TSL2561_LUX_B5C (0x0177) // 0.0229 * 2^LUX_SCALE -#define TSL2561_LUX_M5C (0x01dd) // 0.0291 * 2^LUX_SCALE -#define TSL2561_LUX_K6C (0x019a) // 0.80 * 2^RATIO_SCALE -#define TSL2561_LUX_B6C (0x0101) // 0.0157 * 2^LUX_SCALE -#define TSL2561_LUX_M6C (0x0127) // 0.0180 * 2^LUX_SCALE -#define TSL2561_LUX_K7C (0x029a) // 1.3 * 2^RATIO_SCALE -#define TSL2561_LUX_B7C (0x0037) // 0.00338 * 2^LUX_SCALE -#define TSL2561_LUX_M7C (0x002b) // 0.00260 * 2^LUX_SCALE -#define TSL2561_LUX_K8C (0x029a) // 1.3 * 2^RATIO_SCALE -#define TSL2561_LUX_B8C (0x0000) // 0.000 * 2^LUX_SCALE -#define TSL2561_LUX_M8C (0x0000) // 0.000 * 2^LUX_SCALE - - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -#define CEILING(x,y) (((x) + (y) - 1) / (y)) - -static inline unsigned int -calculateIlluminance(TSL2561_integration_time_t integration_time, - TSL2561_gain_t gain, - uint16_t broadband, uint16_t ir, - unsigned int partno) { - unsigned long channel_1; - unsigned long channel_0; - - /* Get value for channel scaling, and clipping */ - uint16_t clip_threshold = 0; - unsigned long channel_scale = 0; - switch (integration_time) { - case TSL2561_INTEGRATIONTIME_SHORT: - clip_threshold = TSL2561_CLIPPING_SHORT; - channel_scale = TSL2561_LUX_CHSCALE_TINT0; - break; - case TSL2561_INTEGRATIONTIME_MEDIUM: - clip_threshold = TSL2561_CLIPPING_MEDIUM; - channel_scale = TSL2561_LUX_CHSCALE_TINT1; - break; - case TSL2561_INTEGRATIONTIME_LONG: - clip_threshold = TSL2561_CLIPPING_LONG; - channel_scale = (1 << TSL2561_LUX_CHSCALE); - break; - default: - // assert failed - break; - } - - /* Check for saturated sensor (ie: clipping) */ - if ((broadband > clip_threshold) || (ir > clip_threshold)) { - return TSL2561_OVERLOADED; - } - - /* Scale for gain (1x or 16x) */ - if (gain == TSL2561_GAIN_1X) - channel_scale <<= 4; - - /* Scale the channel values */ - channel_0 = (broadband * channel_scale) >> TSL2561_LUX_CHSCALE; - channel_1 = (ir * channel_scale) >> TSL2561_LUX_CHSCALE; - - /* Find the ratio of the channel values (Channel_1/Channel_0) */ - unsigned long _ratio = 0; - if (channel_0 != 0) - _ratio = (channel_1 << (TSL2561_LUX_RATIOSCALE+1)) / channel_0; - unsigned long ratio = (_ratio + 1) >> 1; /* round the ratio value */ - - /* Find linear approximation */ - unsigned int b = 0; - unsigned int m = 0; - - switch (partno) { -#if TSL2561_WITH_CS - case 0x1: // 0001 = TSL2561 CS - if ((ratio >= 0) && (ratio <= TSL2561_LUX_K1C)) - { b=TSL2561_LUX_B1C; m=TSL2561_LUX_M1C; } - else if (ratio <= TSL2561_LUX_K2C) - { b=TSL2561_LUX_B2C; m=TSL2561_LUX_M2C; } - else if (ratio <= TSL2561_LUX_K3C) - { b=TSL2561_LUX_B3C; m=TSL2561_LUX_M3C; } - else if (ratio <= TSL2561_LUX_K4C) - { b=TSL2561_LUX_B4C; m=TSL2561_LUX_M4C; } - else if (ratio <= TSL2561_LUX_K5C) - { b=TSL2561_LUX_B5C; m=TSL2561_LUX_M5C; } - else if (ratio <= TSL2561_LUX_K6C) - { b=TSL2561_LUX_B6C; m=TSL2561_LUX_M6C; } - else if (ratio <= TSL2561_LUX_K7C) - { b=TSL2561_LUX_B7C; m=TSL2561_LUX_M7C; } - else if (ratio > TSL2561_LUX_K8C) - { b=TSL2561_LUX_B8C; m=TSL2561_LUX_M8C; } - break; -#endif -#if TSL2561_WITH_T_FN_CL - case 0x5: // 0101 = TSL2561 T/FN/CL - if ((ratio >= 0) && (ratio <= TSL2561_LUX_K1T)) - { b=TSL2561_LUX_B1T; m=TSL2561_LUX_M1T; } - else if (ratio <= TSL2561_LUX_K2T) - { b=TSL2561_LUX_B2T; m=TSL2561_LUX_M2T; } - else if (ratio <= TSL2561_LUX_K3T) - { b=TSL2561_LUX_B3T; m=TSL2561_LUX_M3T; } - else if (ratio <= TSL2561_LUX_K4T) - { b=TSL2561_LUX_B4T; m=TSL2561_LUX_M4T; } - else if (ratio <= TSL2561_LUX_K5T) - { b=TSL2561_LUX_B5T; m=TSL2561_LUX_M5T; } - else if (ratio <= TSL2561_LUX_K6T) - { b=TSL2561_LUX_B6T; m=TSL2561_LUX_M6T; } - else if (ratio <= TSL2561_LUX_K7T) - { b=TSL2561_LUX_B7T; m=TSL2561_LUX_M7T; } - else if (ratio > TSL2561_LUX_K8T) - { b=TSL2561_LUX_B8T; m=TSL2561_LUX_M8T; } - break; -#endif - default: - // assert failed - break; - } - - /* Compute illuminance */ - long ill = ((channel_0 * b) - (channel_1 * m)); - if (ill < 0) ill = 0; /* Do not allow negative lux value */ - ill += (1 << (TSL2561_LUX_LUXSCALE-1)); /* Round lsb (2^(LUX_SCALE-1)) */ - ill >>= TSL2561_LUX_LUXSCALE; /* Strip fractional part */ - - /* Signal I2C had no errors */ - return ill; -} - -static inline msg_t -_readChannel(TSL2561_drv *drv, uint16_t *broadband, uint16_t *ir) { - msg_t msg; - if (((msg = i2c_reg_recv16_le( - TSL2561_COMMAND_BIT | TSL2561_WORD_BIT | TSL2561_REG_DATA0LOW, - broadband)) < MSG_OK) || - ((msg = i2c_reg_recv16_le( - TSL2561_COMMAND_BIT | TSL2561_WORD_BIT | TSL2561_REG_DATA1LOW, - ir )) < MSG_OK)) - return msg; - return MSG_OK; -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -void -TSL2561_init(TSL2561_drv *drv, TSL2561_config *config) { - drv->config = config; - drv->gain = TSL2561_GAIN_1X; - drv->integration_time = TSL2561_INTEGRATIONTIME_LONG; - drv->state = SENSOR_INIT; - - i2c_reg_recv8(TSL2561_COMMAND_BIT | TSL2561_REG_ID, - (uint8_t*)&drv->id); -} - -msg_t -TSL2561_check(TSL2561_drv *drv) { - uint8_t rx; - - msg_t msg; - if ((msg = i2c_reg_recv8(TSL2561_REG_ID, &rx)) < MSG_OK) - return msg; - if (!(rx & 0x0A)) - return SENSOR_NOTFOUND; - return MSG_OK; -} - -msg_t -TSL2561_stop(TSL2561_drv *drv) { - struct __attribute__((packed)) { - uint8_t reg; - uint8_t conf; - } tx = { TSL2561_COMMAND_BIT | TSL2561_REG_CONTROL, - TSL2561_CONTROL_POWEROFF }; - - return i2c_send((uint8_t*)&tx, sizeof(tx)); -} - -msg_t -TSL2561_start(TSL2561_drv *drv) { - struct __attribute__((packed)) { - uint8_t reg; - uint8_t conf; - } tx = { TSL2561_COMMAND_BIT | TSL2561_REG_CONTROL, - TSL2561_CONTROL_POWERON }; - - return i2c_send((uint8_t*)&tx, sizeof(tx)); -} - -msg_t -TSL2561_setIntegrationTime(TSL2561_drv *drv, - TSL2561_integration_time_t time) { - struct __attribute__((packed)) { - uint8_t reg; - uint8_t conf; - } tx = { TSL2561_COMMAND_BIT | TSL2561_REG_TIMING, - (uint8_t)(time | drv->gain) }; - - msg_t msg; - if ((msg = i2c_send((uint8_t*)&tx, sizeof(tx))) < MSG_OK) - return msg; - - drv->integration_time = time; - - return MSG_OK; -} - -msg_t -TSL2561_setGain(TSL2561_drv *drv, - TSL2561_gain_t gain) { - struct __attribute__((packed)) { - uint8_t reg; - uint8_t conf; - } tx = { TSL2561_COMMAND_BIT | TSL2561_REG_TIMING, - (uint8_t)(drv->integration_time | gain) }; - - msg_t msg; - if ((msg = i2c_send((uint8_t*)&tx, sizeof(tx))) < MSG_OK) - return msg; - - drv->gain = gain; - - return MSG_OK; -} - -unsigned int -TSL2561_getAcquisitionTime(TSL2561_drv *drv) { - switch (drv->integration_time) { - case TSL2561_INTEGRATIONTIME_SHORT: - return CEILING(TSL2561_DELAY_INTTIME_SHORT , 1000); - case TSL2561_INTEGRATIONTIME_MEDIUM: - return CEILING(TSL2561_DELAY_INTTIME_MEDIUM, 1000); - case TSL2561_INTEGRATIONTIME_LONG: - return CEILING(TSL2561_DELAY_INTTIME_LONG , 1000); - } - return -1; -} - - -msg_t -TSL2561_readIlluminance(TSL2561_drv *drv, - unsigned int *illuminance) { - uint16_t broadband; - uint16_t ir; - - /* Read channels */ - msg_t msg; - if ((msg = _readChannel(drv, &broadband, &ir)) < MSG_OK) - return msg; - - /* Calculate illuminance */ - *illuminance = - calculateIlluminance(drv->integration_time, drv->gain, - broadband, ir, drv->id.partno); - /* Ok */ - return SENSOR_OK; -} - diff --git a/firmware/ChibiOS_16/community/os/various/devices_lib/sensors/tsl2561.h b/firmware/ChibiOS_16/community/os/various/devices_lib/sensors/tsl2561.h deleted file mode 100644 index 75e7c78ec8..0000000000 --- a/firmware/ChibiOS_16/community/os/various/devices_lib/sensors/tsl2561.h +++ /dev/null @@ -1,241 +0,0 @@ -/* - TSL2561 for ChibiOS/RT - Copyright (C) 2016 Stephane D'Alu - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file tsl2561.h - * @brief TSL2561 Light sensor interface module header. - * - * @{ - */ - -#ifndef _SENSOR_TSL2561_H_ -#define _SENSOR_TSL2561_H_ - -#include -#include "i2c_helpers.h" -#include "sensor.h" - - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#define TSL2561_CONTINUOUS_ACQUISITION_SUPPORTED TRUE - -#define TSL2561_OVERLOADED (-1) - - -/* I2C address */ -#define TSL2561_I2CADDR_LOW (0x29) -#define TSL2561_I2CADDR_FLOAT (0x39) -#define TSL2561_I2CADDR_HIGH (0x49) - -/** - * @brief Time necessary for the sensor to boot - */ -#define TSL2561_BOOTUP_TIME 0 - -/** - * @brief Time necessary for the sensor to start - */ -#define TSL2561_STARTUP_TIME 0 - - - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -#ifndef TSL2561_WITH_CS -#define TSL2561_WITH_CS 0 -#endif - -#ifndef TSL2561_WITH_T_FN_CL -#define TSL2561_WITH_T_FN_CL 1 -#endif - - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - - -#define TSL2561_I2CADDR_DEFAULT TSL2561_I2CADDR_FLOAT - - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief TSL2561 configuration structure. - */ -typedef struct { - I2CHelper i2c; /* keep it first */ -} TSL2561_config; - -/** - * @brief Available integration time - * - * @details Available integration time are: - * 13.7ms, 101ms, 402ms - */ -typedef enum { - TSL2561_INTEGRATIONTIME_SHORT = 0x00, /**< @brief 13.7ms */ - TSL2561_INTEGRATIONTIME_MEDIUM = 0x01, /**< @brief 101.0ms */ - TSL2561_INTEGRATIONTIME_LONG = 0x02, /**< @brief 402.0ms */ -} TSL2561_integration_time_t; - -/** - * @brief Available gain - * - * @details Available gain are 1x, 16x - */ -typedef enum { - TSL2561_GAIN_1X = 0x00, /**< @brief 1x gain */ - TSL2561_GAIN_16X = 0x10, /**< @brief 16x gain */ -} TSL2561_gain_t; - -/** - * @brief TSL2561 configuration structure. - */ -typedef struct { - TSL2561_config *config; - sensor_state_t state; - TSL2561_gain_t gain; - TSL2561_integration_time_t integration_time; - struct PACKED { - uint8_t revno : 4; - uint8_t partno : 4; } id; -} TSL2561_drv; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/** - * @brief Initialize the sensor driver - */ -void -TSL2561_init(TSL2561_drv *drv, - TSL2561_config *config); - -/** - * @brief Start the sensor - */ -msg_t -TSL2561_start(TSL2561_drv *drv); - -/** - * @brief Stop the sensor - * - * @details If the sensor support it, it will be put in low energy mode. - */ -msg_t -TSL2561_stop(TSL2561_drv *drv); - -/** - * @brief Check that the sensor is really present - */ -msg_t -TSL2561_check(TSL2561_drv *drv); - -/** - * @brief Time in milli-seconds necessary for acquiring a naw measure - * - * @returns - * unsigned int time in millis-seconds - */ -unsigned int -TSL2561_getAcquisitionTime(TSL2561_drv *drv); - -/** - * @brief Trigger a mesure acquisition - */ -static inline msg_t -TSL2561_startMeasure(TSL2561_drv *drv) { - (void)drv; - return MSG_OK; -}; - -/** - * @brief Read the newly acquiered measure - * - * @note According the the sensor design the measure read - * can be any value acquired after the acquisition time - * and the call to readMeasure. - */ -msg_t -TSL2561_readMeasure(TSL2561_drv *drv, - unsigned int illuminance); - -msg_t -TSL2561_setGain(TSL2561_drv *drv, - TSL2561_gain_t gain); - -msg_t -TSL2561_setIntegrationTime(TSL2561_drv *drv, - TSL2561_integration_time_t time); - -/** - * @brief Read temperature and humidity - * - * @details According to the sensor specification/configuration - * (see #TSL2561_CONTINUOUS_ACQUISITION_SUPPORTED), - * if the sensor is doing continuous measurement - * it's value will be requested and returned immediately. - * Otherwise a measure is started, the necessary amount of - * time for acquiring the value is spend sleeping (not spinning), - * and finally the measure is read. - * - * @note In continuous measurement mode, if you just started - * the sensor, you will need to wait getAcquisitionTime() - * in addition to the usual getStartupTime() - - * @note If using several sensors, it is better to start all the - * measure together, wait for the sensor having the longuest - * aquisition time, and finally read all the values - */ -msg_t -TSL2561_readIlluminance(TSL2561_drv *drv, - unsigned int *illuminance); - -/** - * @brief Return the illuminance value in Lux - * - * @details Use readIlluminance() for returning the humidity value. - * - * @note Prefere readIlluminance()if you need better error handling. - * - * @return Illuminance in Lux - * @retval unsigned int illuminace value - * @retval -1 on failure - */ -static inline unsigned int -TSL2561_getIlluminance(TSL2561_drv *drv) { - unsigned int illuminance = -1; - TSL2561_readIlluminance(drv, &illuminance); - return illuminance; -} - - -#endif - diff --git a/firmware/ChibiOS_16/community/os/various/devices_lib/sensors/tsl2591.c b/firmware/ChibiOS_16/community/os/various/devices_lib/sensors/tsl2591.c deleted file mode 100644 index c0bbee0ce6..0000000000 --- a/firmware/ChibiOS_16/community/os/various/devices_lib/sensors/tsl2591.c +++ /dev/null @@ -1,272 +0,0 @@ -/* - TSL2591 for ChibiOS/RT - Copyright (C) 2016 Stephane D'Alu - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * - * DOC: http://ams.com/eng/content/download/389383/1251117/221235 - */ - -#define I2C_HELPERS_AUTOMATIC_DRV TRUE - -#include "hal.h" -#include "i2c_helpers.h" -#include "tsl2591.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define TSL2591_LUX_DF (408.0F) -#define TSL2591_LUX_COEFB (1.64F) // CH0 coefficient -#define TSL2591_LUX_COEFC (0.59F) // CH1 coefficient A -#define TSL2591_LUX_COEFD (0.86F) // CH2 coefficient B - -/* I2C registers */ -#define TSL2591_REG_ENABLE 0x00 -#define TSL2591_REG_CONFIG 0x01 /**< @brief gain and integration */ -#define TSL2591_REG_AILTL 0x04 -#define TSL2591_REG_AILTH 0x05 -#define TSL2591_REG_AIHTL 0x06 -#define TSL2591_REG_AIHTH 0x07 -#define TSL2591_REG_NPAILTL 0x08 -#define TSL2591_REG_NPAILTH 0x09 -#define TSL2591_REG_NPAIHTL 0x0A -#define TSL2591_REG_NPAIHTH 0x0B -#define TSL2591_REG_PERSIST 0x0C -#define TSL2591_REG_PID 0x11 /**< @brief Package ID */ -#define TSL2591_REG_ID 0x12 /**< @brief Device ID */ -#define TSL2591_REG_STATUS 0x13 /**< @brief Device status */ -#define TSL2591_REG_C0DATAL 0x14 /**< @brief CH0 ADC low data byte */ -#define TSL2591_REG_C0DATAH 0x15 /**< @brief CH0 ADC high data byte */ -#define TSL2591_REG_C1DATAL 0x16 /**< @brief CH1 ADC low data byte */ -#define TSL2591_REG_C1DATAH 0x17 /**< @brief CH1 ADC high data byte */ - -#define TSL2591_REG_COMMAND 0x80 /**< @brief Select command register */ -#define TSL2591_REG_NORMAL 0x20 /**< @brief Normal opearation */ -#define TSL2591_REG_SPECIAL 0x60 /**< @brief Special function */ - -#define TSL2591_ID_TSL2591 0x50 - -#define TSL2591_VISIBLE (2) // channel 0 - channel 1 -#define TSL2591_INFRARED (1) // channel 1 -#define TSL2591_FULLSPECTRUM (0) // channel 0 - -#define TSL2591_ENABLE_POWERON (0x01) -#define TSL2591_ENABLE_POWEROFF (0x00) -#define TSL2591_ENABLE_AEN (0x02) -#define TSL2591_ENABLE_AIEN (0x10) - -#define TSL2591_CONTROL_RESET (0x80) - - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static inline uint32_t -calculateIlluminance(TSL2591_integration_time_t integration_time, - TSL2591_gain_t gain, - uint16_t broadband, uint16_t ir) { - uint16_t atime, again; - - /* Check for overflow conditions first */ - if ((broadband == 0xFFFF) | (ir == 0xFFFF)) { - return 0xFFFFFFFF; /* Signal overflow */ - } - - switch (integration_time) { - case TSL2591_INTEGRATIONTIME_100MS : atime = 100; break; - case TSL2591_INTEGRATIONTIME_200MS : atime = 200; break; - case TSL2591_INTEGRATIONTIME_300MS : atime = 300; break; - case TSL2591_INTEGRATIONTIME_400MS : atime = 400; break; - case TSL2591_INTEGRATIONTIME_500MS : atime = 500; break; - case TSL2591_INTEGRATIONTIME_600MS : atime = 600; break; - } - - switch (gain) { - case TSL2591_GAIN_1X : again = 1; break; - case TSL2591_GAIN_25X : again = 25; break; - case TSL2591_GAIN_415X : again = 415; break; - case TSL2591_GAIN_10000X : again = 10000; break; - } - - // cpl = (ATIME * AGAIN) / DF - float cpl = ((float)(atime * again)) / ((float)TSL2591_LUX_DF); - float lux1 = ( ((float)broadband) - (TSL2591_LUX_COEFB * (float)ir) ) / cpl; - float lux2 = ( (TSL2591_LUX_COEFC * (float)broadband) - - (TSL2591_LUX_COEFD * (float)ir ) ) / cpl; - - return (uint32_t) (lux1 > lux2 ? lux1 : lux2); -} - -static inline msg_t -_readChannel(TSL2591_drv *drv, uint16_t *broadband, uint16_t *ir) { - msg_t msg; - if (((msg = i2c_reg_recv16_le( - TSL2591_REG_COMMAND | TSL2591_REG_NORMAL | TSL2591_REG_C0DATAL, - broadband)) < MSG_OK) || - ((msg = i2c_reg_recv16_le( - TSL2591_REG_COMMAND | TSL2591_REG_NORMAL | TSL2591_REG_C1DATAL, - ir )) < MSG_OK)) - return msg; - - return MSG_OK; -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -void -TSL2591_init(TSL2591_drv *drv, TSL2591_config *config) { - drv->config = config; - drv->gain = TSL2591_GAIN_1X; - drv->integration_time = TSL2591_INTEGRATIONTIME_100MS; - drv->state = SENSOR_INIT; -} - -msg_t -TSL2591_check(TSL2591_drv *drv) { - uint8_t id; - - msg_t msg; - if ((msg = i2c_reg_recv8(TSL2591_REG_COMMAND | TSL2591_REG_NORMAL | - TSL2591_REG_ID, &id)) < MSG_OK) - return msg; - - if (id != TSL2591_ID_TSL2591) - return SENSOR_NOTFOUND; - - return MSG_OK; -} - -msg_t -TSL2591_start(TSL2591_drv *drv) { - struct __attribute__((packed)) { - uint8_t reg; - uint8_t conf; - } tx_config = { - TSL2591_REG_COMMAND | TSL2591_REG_NORMAL | TSL2591_REG_CONFIG, - (uint8_t)(drv->integration_time | drv->gain) }; - - struct __attribute__((packed)) { - uint8_t reg; - uint8_t conf; - } tx_start = { - TSL2591_REG_COMMAND | TSL2591_REG_NORMAL | TSL2591_REG_ENABLE, - TSL2591_ENABLE_POWERON }; - - msg_t msg; - - if (((msg = i2c_send((uint8_t*)&tx_config, sizeof(tx_config))) < MSG_OK) || - ((msg = i2c_send((uint8_t*)&tx_start, sizeof(tx_start ))) < MSG_OK)) { - drv->state = SENSOR_ERROR; - return msg; - } - - drv->state = SENSOR_STARTED; - return MSG_OK; -} - -msg_t -TSL2591_stop(TSL2591_drv *drv) { - struct __attribute__((packed)) { - uint8_t reg; - uint8_t conf; - } tx_stop = { - TSL2591_REG_COMMAND | TSL2591_REG_NORMAL | TSL2591_REG_ENABLE, - TSL2591_ENABLE_POWEROFF }; - - return i2c_send((uint8_t*)&tx_stop, sizeof(tx_stop)); -} - -msg_t -TSL2591_setIntegrationTime(TSL2591_drv *drv, - TSL2591_integration_time_t time) { - struct __attribute__((packed)) { - uint8_t reg; - uint8_t conf; - } tx = { TSL2591_REG_COMMAND | TSL2591_REG_NORMAL | TSL2591_REG_CONFIG, - (uint8_t)(time | drv->gain) }; - - msg_t msg; - if ((msg = i2c_send((uint8_t*)&tx, sizeof(tx))) < MSG_OK) - return msg; - - drv->integration_time = time; - - return MSG_OK; -} - -msg_t -TSL2591_setGain(TSL2591_drv *drv, - TSL2591_gain_t gain) { - struct __attribute__((packed)) { - uint8_t reg; - uint8_t conf; - } tx = { TSL2591_REG_COMMAND | TSL2591_REG_NORMAL | TSL2591_REG_CONFIG, - (uint8_t)(drv->integration_time | gain) }; - - msg_t msg; - if ((msg = i2c_send((uint8_t*)&tx, sizeof(tx))) < MSG_OK) - return msg; - - drv->gain = gain; - - return MSG_OK; -} - -unsigned int -TSL2591_getAcquisitionTime(TSL2591_drv *drv) { - switch (drv->integration_time) { - case TSL2591_INTEGRATIONTIME_100MS : return 100; - case TSL2591_INTEGRATIONTIME_200MS : return 200; - case TSL2591_INTEGRATIONTIME_300MS : return 300; - case TSL2591_INTEGRATIONTIME_400MS : return 400; - case TSL2591_INTEGRATIONTIME_500MS : return 500; - case TSL2591_INTEGRATIONTIME_600MS : return 600; - } - return -1; -} - - -msg_t -TSL2591_readIlluminance(TSL2591_drv *drv, - unsigned int *illuminance) { - uint16_t broadband; - uint16_t ir; - - /* Read channels */ - msg_t msg; - if ((msg = _readChannel(drv, &broadband, &ir)) < MSG_OK) - return msg; - - /* Calculate illuminance */ - *illuminance = - calculateIlluminance(drv->integration_time, drv->gain, - broadband, ir); - /* Ok */ - return SENSOR_OK; -} - diff --git a/firmware/ChibiOS_16/community/os/various/devices_lib/sensors/tsl2591.h b/firmware/ChibiOS_16/community/os/various/devices_lib/sensors/tsl2591.h deleted file mode 100644 index 8320eb8aae..0000000000 --- a/firmware/ChibiOS_16/community/os/various/devices_lib/sensors/tsl2591.h +++ /dev/null @@ -1,238 +0,0 @@ -/* - TSL2591 for ChibiOS/RT - Copyright (C) 2016 Stephane D'Alu - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file tsl2591.h - * @brief TSL2591 Light sensor interface module header. - * - * @{ - */ - -#ifndef _SENSOR_TSL2591_H_ -#define _SENSOR_TSL2591_H_ - -#include -#include "i2c_helpers.h" -#include "sensor.h" - - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Device sensor continuous acquisition support. - */ -#define TSL2591_CONTINUOUS_ACQUISITION_SUPPORTED TRUE - -/** - * @brief I2C address. - */ -#define TSL2591_I2CADDR_FIXED 0x29 - -/** - * @brief Time necessary for the sensor to boot - */ -#define TSL2591_BOOTUP_TIME 0 - -/** - * @brief Time necessary for the sensor to start - */ -#define TSL2591_STARTUP_TIME 0 - - - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/** - * @brief Default I2C address (when pin unconfigured) - */ -#define TSL2591_I2CADDR_DEFAULT TSL2591_I2CADDR_FIXED - - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief TSL2591 configuration structure. - */ -typedef struct { - I2CHelper i2c; /* keep it first */ -} TSL2591_config; - -/** - * @brief Available integration time - * - * @details Available integration time are: - * 100ms, 200ms, 300ms, 400ms, 500ms and 600ms - */ -typedef enum { - TSL2591_INTEGRATIONTIME_100MS = 0x00, /**< @brief 100ms */ - TSL2591_INTEGRATIONTIME_200MS = 0x01, /**< @brief 200ms */ - TSL2591_INTEGRATIONTIME_300MS = 0x02, /**< @brief 300ms */ - TSL2591_INTEGRATIONTIME_400MS = 0x03, /**< @brief 400ms */ - TSL2591_INTEGRATIONTIME_500MS = 0x04, /**< @brief 500ms */ - TSL2591_INTEGRATIONTIME_600MS = 0x05, /**< @brief 600ms */ -} TSL2591_integration_time_t; - -/** - * @brief Available gain - * - * @details Available gain are 1x, 25x, 415x, 10000x - */ -typedef enum { - TSL2591_GAIN_1X = 0x00, /**< @brief 1x gain */ - TSL2591_GAIN_25X = 0x10, /**< @brief 25x gain */ - TSL2591_GAIN_415X = 0x20, /**< @brief 415x gain */ - TSL2591_GAIN_10000X = 0x30, /**< @brief 10000x gain */ -} TSL2591_gain_t; - -/** - * @brief TSL2591 configuration structure. - */ -typedef struct { - TSL2591_config *config; - sensor_state_t state; - TSL2591_gain_t gain; - TSL2591_integration_time_t integration_time; -} TSL2591_drv; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/** - * @brief Initialize the sensor driver - */ -void -TSL2591_init(TSL2591_drv *drv, - TSL2591_config *config); - -/** - * @brief Start the sensor - */ -msg_t -TSL2591_start(TSL2591_drv *drv); - -/** - * @brief Stop the sensor - * - * @details If the sensor support it, it will be put in low energy mode. - */ -msg_t -TSL2591_stop(TSL2591_drv *drv); - -/** - * @brief Check that the sensor is really present - */ -msg_t -TSL2591_check(TSL2591_drv *drv); - -/** - * @brief Time in milli-seconds necessary for acquiring a naw measure - * - * @returns - * unsigned int time in millis-seconds - */ -unsigned int -TSL2591_getAcquisitionTime(TSL2591_drv *drv); - -/** - * @brief Trigger a mesure acquisition - */ -static inline msg_t -TSL2591_startMeasure(TSL2591_drv *drv) { - (void)drv; - return MSG_OK; -}; - - -msg_t -TSL2591_setGain(TSL2591_drv *drv, - TSL2591_gain_t gain); - -msg_t -TSL2591_setIntegrationTime(TSL2591_drv *drv, - TSL2591_integration_time_t time); - -/** - * @brief Read the newly acquiered measure - * - * @note According the the sensor design the measure read - * can be any value acquired after the acquisition time - * and the call to readMeasure. - */ -msg_t -TSL2591_readMeasure(TSL2591_drv *drv, - unsigned int illuminance); - - -/** - * @brief Read temperature and humidity - * - * @details According to the sensor specification/configuration - * (see #TSL2591_CONTINUOUS_ACQUISITION_SUPPORTED), - * if the sensor is doing continuous measurement - * it's value will be requested and returned immediately. - * Otherwise a measure is started, the necessary amount of - * time for acquiring the value is spend sleeping (not spinning), - * and finally the measure is read. - * - * @note In continuous measurement mode, if you just started - * the sensor, you will need to wait getAcquisitionTime() - * in addition to the usual getStartupTime() - - * @note If using several sensors, it is better to start all the - * measure together, wait for the sensor having the longuest - * aquisition time, and finally read all the values - */ -msg_t -TSL2591_readIlluminance(TSL2591_drv *drv, - unsigned int *illuminance); - -/** - * @brief Return the illuminance value in Lux - * - * @details Use readIlluminance() for returning the humidity value. - * - * @note Prefere readIlluminance()if you need better error handling. - * - * @return Illuminance in Lux - * @retval unsigned int illuminace value - * @retval -1 on failure - */ -static inline unsigned int -TSL2591_getIlluminance(TSL2591_drv *drv) { - unsigned int illuminance = -1; - TSL2591_readIlluminance(drv, &illuminance); - return illuminance; -} - - -#endif - diff --git a/firmware/ChibiOS_16/community/os/various/gdb.mk b/firmware/ChibiOS_16/community/os/various/gdb.mk deleted file mode 100644 index aa636a844a..0000000000 --- a/firmware/ChibiOS_16/community/os/various/gdb.mk +++ /dev/null @@ -1,13 +0,0 @@ -GDB ?= arm-none-eabi-gdb -GDB_PROGRAM ?= $(BUILDDIR)/$(PROJECT).elf -GDB_PORT ?= 2331 -GDB_START_ADDRESS ?= 0 -GDB_BREAK ?= main - -gdb-debug: - printf "target remote localhost:$(GDB_PORT)\nmem $(GDB_START_ADDRESS) 0\nbreak $(GDB_BREAK)\nload\nmon reset\ncontinue" > .gdbinit - $(GDB) --command=.gdbinit $(GDB_PROGRAM) - - - -.PHONY: gdb-debug diff --git a/firmware/ChibiOS_16/community/os/various/i2c_helpers.h b/firmware/ChibiOS_16/community/os/various/i2c_helpers.h deleted file mode 100644 index 4b57174490..0000000000 --- a/firmware/ChibiOS_16/community/os/various/i2c_helpers.h +++ /dev/null @@ -1,283 +0,0 @@ -/* - Copyright (C) 2016 Stephane D'Alu - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef I2C_HELPERS_H -#define I2C_HELPERS_H - -#include "hal.h" -#include "bswap.h" - - -typedef struct { - /** - * @brief Pointer to the I2C driver. - */ - I2CDriver *driver; - /** - * @brief I2C address. - */ - i2caddr_t addr; -} I2CHelper; - - - -#if !defined(I2C_HELPERS_AUTOMATIC_DRV) || (I2C_HELPERS_AUTOMATIC_DRV == FALSE) - -#define i2c_send(i2c, txbuf, txbytes) \ - _i2c_send(i2c, txbuf, txbytes) -#define i2c_transmit(i2c, txbuf, txbytes, rxbuf, rxbytes) \ - _i2c_transmit(i2c, txbuf, txbytes, rxbuf, rxbytes) -#define i2c_receive(i2, rxbuf, rxbytes) \ - _i2c_receive(i2c, rxbuf, rxbytes) - -#define i2c_send_timeout(i2c, txbuf, txbytes) \ - _i2c_send(i2c, txbuf, txbytes) -#define i2c_transmit_timeout(i2c, txbuf, txbytes, rxbuf, rxbytes) \ - _i2c_transmit(i2c, txbuf, txbytes, rxbuf, rxbytes) -#define i2c_receive_timeout(i2, rxbuf, rxbytes) \ - _i2c_receive(i2c, rxbuf, rxbytes) - -#define i2c_reg(i2c, reg) \ - _i2c_reg(i2c, reg) - -#define i2c_reg_recv8(i2c, reg, val) \ - _i2c_reg_recv8(i2c, reg, val) -#define i2c_reg_recv16(i2c, reg, val) \ - _i2c_reg_recv16(i2c, reg, val) -#define i2c_reg_recv16_le(i2c, reg, val) \ - _i2c_reg_recv16_le(i2c, reg, val) -#define i2c_reg_recv16_be(i2c, reg, val) \ - _i2c_reg_recv16_be(i2c, reg, val) -#define i2c_reg_recv32(i2c, reg, val) \ - _i2c_reg_recv32(i2c, reg, val) -#define i2c_reg_recv32_le(i2c, reg, val) \ - _i2c_reg_recv32_le(i2c, reg, val) -#define i2c_reg_recv32_be(i2c, reg, val) \ - _i2c_reg_recv32_be(i2c, reg, val) - -#define i2c_recv8(i2c, val) \ - _i2c_recv8(i2c, val) -#define i2c_recv16(i2c, val) \ - _i2c_recv16(i2c, val) -#define i2c_recv16_le(i2c, val) \ - _i2c_recv16_le(i2c, val) -#define i2c_recv16_be(i2c, val) \ - _i2c_recv16_be(i2c, val) -#define i2c_recv32(i2c, val) \ - _i2c_recv32(i2c, val) -#define i2c_recv32_le(i2c, val) \ - _i2c_recv32_le(i2c, val) -#define i2c_recv32_be(i2c, val) \ - _i2c_recv32_be(i2c, val) - -#else - -#define i2c_send(txbuf, txbytes) \ - _i2c_send(&drv->config->i2c, txbuf, txbytes) -#define i2c_transmit(txbuf, txbytes, rxbuf, rxbytes) \ - _i2c_transmit(&drv->config->i2c, txbuf, txbytes, rxbuf, rxbytes) -#define i2c_receive(rxbuf, rxbytes) \ - _i2c_receive(&drv->config->i2c, rxbuf, rxbytes) - -#define i2c_send_timeout(txbuf, txbytes) \ - _i2c_send(&drv->config->i2c, txbuf, txbytes) -#define i2c_transmit_timeout(txbuf, txbytes, rxbuf, rxbytes) \ - _i2c_transmit(&drv->config->i2c, txbuf, txbytes, rxbuf, rxbytes) -#define i2c_receive_timeout(rxbuf, rxbytes) \ - _i2c_receive(&drv->config->i2c, rxbuf, rxbytes) - - -#define i2c_reg(reg) \ - _i2c_reg(&drv->config->i2c, reg) - -#define i2c_reg_recv8(reg, val) \ - _i2c_reg_recv8(&drv->config->i2c, reg, val) -#define i2c_reg_recv16(reg, val) \ - _i2c_reg_recv16(&drv->config->i2c, reg, val) -#define i2c_reg_recv16_le(reg, val) \ - _i2c_reg_recv16_le(&drv->config->i2c, reg, val) -#define i2c_reg_recv16_be(reg, val) \ - _i2c_reg_recv16_be(&drv->config->i2c, reg, val) -#define i2c_reg_recv32(reg, val) \ - _i2c_reg_recv32(&drv->config->i2c, reg, val) -#define i2c_reg_recv32_le(reg, val) \ - _i2c_reg_recv32_le(&drv->config->i2c, reg, val) -#define i2c_reg_recv32_be(reg, val) \ - _i2c_reg_recv32_be(&drv->config->i2c, reg, val) - -#define i2c_recv8(val) \ - _i2c_recv8(&drv->config->i2c, val) -#define i2c_recv16(val) \ - _i2c_recv16(&drv->config->i2c, val) -#define i2c_recv16_le(val) \ - _i2c_recv16_le(&drv->config->i2c, val) -#define i2c_recv16_be(val) \ - _i2c_recv16_be(&drv->config->i2c, val) -#define i2c_recv32(val) \ - _i2c_recv32(&drv->config->i2c, val) -#define i2c_recv32_le(val) \ - _i2c_recv32_le(&drv->config->i2c, val) -#define i2c_recv32_be(val) \ - _i2c_recv32_be(&drv->config->i2c, val) - -#endif - - - - - -static inline msg_t -_i2c_send(I2CHelper *i2c, const uint8_t *txbuf, size_t txbytes) { - return i2cMasterTransmitTimeout(i2c->driver, i2c->addr, - txbuf, txbytes, NULL, 0, TIME_INFINITE); -}; - -static inline msg_t -_i2c_transmit(I2CHelper *i2c, const uint8_t *txbuf, size_t txbytes, - uint8_t *rxbuf, size_t rxbytes) { - return i2cMasterTransmitTimeout(i2c->driver, i2c->addr, - txbuf, txbytes, rxbuf, rxbytes, TIME_INFINITE); -} - -static inline msg_t -_i2c_receive(I2CHelper *i2c, uint8_t *rxbuf, size_t rxbytes) { - return i2cMasterReceiveTimeout(i2c->driver, i2c->addr, - rxbuf, rxbytes, TIME_INFINITE); -}; - - - -static inline msg_t -_i2c_send_timeout(I2CHelper *i2c, const uint8_t *txbuf, size_t txbytes, - systime_t timeout) { - return i2cMasterTransmitTimeout(i2c->driver, i2c->addr, - txbuf, txbytes, NULL, 0, timeout); -}; - -static inline msg_t -_i2c_transmit_timeout(I2CHelper *i2c, const uint8_t *txbuf, size_t txbytes, - uint8_t *rxbuf, size_t rxbytes, systime_t timeout) { - return i2cMasterTransmitTimeout(i2c->driver, i2c->addr, - txbuf, txbytes, rxbuf, rxbytes, timeout); -} - -static inline msg_t -_i2c_receive_timeout(I2CHelper *i2c, uint8_t *rxbuf, size_t rxbytes, systime_t timeout) { - return i2cMasterReceiveTimeout(i2c->driver, i2c->addr, - rxbuf, rxbytes, timeout); -}; - - -/*======================================================================*/ - - -static inline msg_t -_i2c_reg(I2CHelper *i2c, uint8_t reg) { - return _i2c_transmit(i2c, ®, sizeof(reg), NULL, 0); -}; - -/*======================================================================*/ - -static inline msg_t -_i2c_reg_recv8(I2CHelper *i2c, uint8_t reg, uint8_t *val) { - return _i2c_transmit(i2c, ®, sizeof(reg), (uint8_t*)val, sizeof(val)); -}; - -static inline msg_t -_i2c_reg_recv16(I2CHelper *i2c, uint8_t reg, uint16_t *val) { - return _i2c_transmit(i2c, ®, sizeof(reg), (uint8_t*)val, sizeof(val)); -}; - -static inline msg_t -_i2c_reg_recv16_le(I2CHelper *i2c, uint8_t reg, uint16_t *val) { - int msg = _i2c_reg_recv16(i2c, reg, val); - if (msg >= 0) *val = le16_to_cpu(*val); - return msg; -}; - -static inline msg_t -_i2c_reg_recv16_be(I2CHelper *i2c, uint8_t reg, uint16_t *val) { - int msg = _i2c_reg_recv16(i2c, reg, val); - if (msg >= 0) *val = be16_to_cpu(*val); - return msg; -}; - -static inline msg_t -_i2c_reg_recv32(I2CHelper *i2c, uint8_t reg, uint32_t *val) { - return _i2c_transmit(i2c, ®, sizeof(reg), (uint8_t*)val, sizeof(val)); -}; - -static inline msg_t -_i2c_reg_recv32_le(I2CHelper *i2c, uint8_t reg, uint32_t *val) { - int msg = _i2c_reg_recv32(i2c, reg, val); - if (msg >= 0) *val = le32_to_cpu(*val); - return msg; -}; - -static inline msg_t -_i2c_reg_recv32_be(I2CHelper *i2c, uint8_t reg, uint32_t *val) { - int msg = _i2c_reg_recv32(i2c, reg, val); - if (msg >= 0) *val = be32_to_cpu(*val); - return msg; -}; - - -/*======================================================================*/ - -static inline msg_t -_i2c_recv8(I2CHelper *i2c, uint8_t *val) { - return _i2c_receive(i2c, (uint8_t*)val, sizeof(val)); -}; - -static inline msg_t -_i2c_recv16(I2CHelper *i2c, uint16_t *val) { - return _i2c_receive(i2c, (uint8_t*)val, sizeof(val)); -}; - -static inline msg_t -_i2c_recv16_le(I2CHelper *i2c, uint16_t *val) { - int msg = _i2c_recv16(i2c, val); - if (msg >= 0) *val = le16_to_cpu(*val); - return msg; -}; - -static inline msg_t -_i2c_recv16_be(I2CHelper *i2c, uint16_t *val) { - int msg = _i2c_recv16(i2c, val); - if (msg >= 0) *val = be16_to_cpu(*val); - return msg; -}; - -static inline msg_t -_i2c_recv32(I2CHelper *i2c, uint32_t *val) { - return _i2c_receive(i2c, (uint8_t*)val, sizeof(val)); -}; - -static inline msg_t -_i2c_recv32_le(I2CHelper *i2c, uint32_t *val) { - int msg = _i2c_recv32(i2c, val); - if (msg >= 0) *val = le32_to_cpu(*val); - return msg; -}; - -static inline msg_t -_i2c_recv32_be(I2CHelper *i2c, uint32_t *val) { - int msg = _i2c_recv32(i2c, val); - if (msg >= 0) *val = be32_to_cpu(*val); - return msg; -}; - -#endif diff --git a/firmware/ChibiOS_16/community/os/various/jlink.mk b/firmware/ChibiOS_16/community/os/various/jlink.mk deleted file mode 100644 index 00fedb32ce..0000000000 --- a/firmware/ChibiOS_16/community/os/various/jlink.mk +++ /dev/null @@ -1,37 +0,0 @@ -JLINK ?= JLinkExe -JLINK_GDB_SERVER ?= JLinkGDBServer -JLINK_GDB_PORT ?= 2331 -JLINK_IF ?= swd -JLINK_SPEED ?= 2000 -JLINK_START_ADDRESS ?= 0 -JLINK_BURN ?= $(BUILDDIR)/$(PROJECT).bin -JLINK_COMMON_OPTS ?= -device $(JLINK_DEVICE) -if $(JLINK_IF) -speed $(JLINK_SPEED) - -jlink-flash: - printf "$(JLINK_PRE_FLASH)\nloadbin $(JLINK_BURN) $(JLINK_START_ADDRESS)\nverifybin $(JLINK_BURN) $(JLINK_START_ADDRESS)\nr\ng\nexit\n" > $(BUILDDIR)/flash.jlink - $(JLINK) $(JLINK_COMMON_OPTS) $(BUILDDIR)/flash.jlink - -ifneq ($(SOFTDEVICE),) -jlink-flash-softdevice: - printf "w4 4001e504 1\nloadbin $(NRF51SDK)/components/softdevice/$(SOFTDEVICE)/hex/$(SOFTDEVICE)_nrf51_$(SOFTDEVICE_RELEASE)_softdevice.hex 0\nr\ng\nexit\n" > $(BUILDDIR)/flash.softdevice.jlink - $(JLINK) $(JLINK_COMMON_OPTS) $(BUILDDIR)/flash.softdevice.jlink -endif - -ifneq ($(JLINK_ERASE_ALL),) -jlink-erase-all: - printf "$(JLINK_ERASE_ALL)\nr\nexit\n" > $(BUILDDIR)/erase-all.jlink - $(JLINK) $(JLINK_COMMON_OPTS) $(BUILDDIR)/erase-all.jlink -endif - -jlink-reset: - printf "r\nexit\n" > $(BUILDDIR)/reset.jlink - $(JLINK) $(JLINK_COMMON_OPTS) $(BUILDDIR)/reset.jlink - -jlink-pin-reset: - printf "$(JLINK_PIN_RESET)\nexit\n" > $(BUILDDIR)/pin-reset.jlink - $(JLINK) $(JLINK_COMMON_OPTS) $(BUILDDIR)/pin-reset.jlink - -jlink-debug-server: - $(JLINK_GDB_SERVER) $(JLINK_COMMON_OPTS) -port $(JLINK_GDB_PORT) - -.PHONY: jlink-flash jlink-flash-softdevice jlink-erase-all jlink-reset jlink-debug-server diff --git a/firmware/ChibiOS_16/community/os/various/lib_scsi.c b/firmware/ChibiOS_16/community/os/various/lib_scsi.c deleted file mode 100644 index 55aeb7ed2b..0000000000 --- a/firmware/ChibiOS_16/community/os/various/lib_scsi.c +++ /dev/null @@ -1,507 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2016 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file lib_scsi.c - * @brief SCSI target driver source code. - * - * @addtogroup SCSI - * @{ - */ - -#include - -#include "hal.h" - -#include "lib_scsi.h" - -#define DEBUG_TRACE_PRINT FALSE -#define DEBUG_TRACE_WARNING FALSE -#define DEBUG_TRACE_ERROR FALSE -#include "dbgtrace.h" - -#define ARCH_LITTLE_ENDIAN -#include "bswap.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -typedef struct { - uint32_t first_lba; - uint16_t blk_cnt; -} data_request_t; - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Combines data request from byte array. - * - * @notapi - */ -static data_request_t decode_data_request(const uint8_t *cmd) { - - data_request_t req; - uint32_t lba; - uint16_t blk; - - memcpy(&lba, &cmd[2], sizeof(lba)); - memcpy(&blk, &cmd[7], sizeof(blk)); - - req.first_lba = be32_to_cpu(lba); - req.blk_cnt = be16_to_cpu(blk); - - return req; -} - -/** - * @brief Fills sense structure. - * - * @param[in] scsip pointer to @p SCSITarget structure - * @param[in] key SCSI sense key - * @param[in] code SCSI sense code - * @param[in] qual SCSI sense qualifier - * - * @notapi - */ -static void set_sense(SCSITarget *scsip, uint8_t key, - uint8_t code, uint8_t qual) { - - scsi_sense_response_t *sense = &scsip->sense; - memset(sense, 0 , sizeof(scsi_sense_response_t)); - - sense->byte[0] = 0x70; - sense->byte[2] = key; - sense->byte[7] = 8; - sense->byte[12] = code; - sense->byte[13] = qual; -} - -/** - * @brief Sets all values in sense data to 'success' condition. - * - * @param[in] scsip pointer to @p SCSITarget structure - * - * @notapi - */ -static void set_sense_ok(SCSITarget *scsip) { - set_sense(scsip, SCSI_SENSE_KEY_GOOD, - SCSI_ASENSE_NO_ADDITIONAL_INFORMATION, - SCSI_ASENSEQ_NO_QUALIFIER); -} - -/** - * @brief Transmits data via transport channel. - * - * @param[in] scsip pointer to @p SCSITarget structure - * @param[in] data pointer to data buffer - * @param[in] len number of bytes to be transmitted - * - * @return The operation status. - * - * @notapi - */ -static bool transmit_data(SCSITarget *scsip, const uint8_t *data, uint32_t len) { - - const SCSITransport *trp = scsip->config->transport; - const uint32_t residue = len - trp->transmit(trp, data, len); - - if (residue > 0) { - scsip->residue = residue; - return SCSI_FAILED; - } - else { - return SCSI_SUCCESS; - } -} - -/** - * @brief Stub for unhandled SCSI commands. - * @details Sets error flags in sense data structure and returns error error. - */ -static bool cmd_unhandled(SCSITarget *scsip, const uint8_t *cmd) { - (void)cmd; - - set_sense(scsip, SCSI_SENSE_KEY_ILLEGAL_REQUEST, - SCSI_ASENSE_INVALID_COMMAND, - SCSI_ASENSEQ_NO_QUALIFIER); - return SCSI_FAILED; -} - -/** - * @brief Stub for unrealized but required SCSI commands. - * @details Sets sense data in 'all OK' condition and returns success status. - */ -static bool cmd_ignored(SCSITarget *scsip, const uint8_t *cmd) { - (void)scsip; - (void)cmd; - - set_sense_ok(scsip); - return SCSI_SUCCESS; -} - -/** - * @brief SCSI inquiry command handler. - * - * @param[in] scsip pointer to @p SCSITarget structure - * @param[in] cmd pointer to SCSI command data - * - * @return The operation status. - * - * @notapi - */ -static bool inquiry(SCSITarget *scsip, const uint8_t *cmd) { - - if ((cmd[1] & 0b11) || cmd[2] != 0) { - set_sense(scsip, SCSI_SENSE_KEY_ILLEGAL_REQUEST, - SCSI_ASENSE_INVALID_FIELD_IN_CDB, - SCSI_ASENSEQ_NO_QUALIFIER); - return SCSI_FAILED; - } - else { - return transmit_data(scsip, (const uint8_t *)scsip->config->inquiry_response, - sizeof(scsi_inquiry_response_t)); - } -} - -/** - * @brief SCSI request sense command handler. - * - * @param[in] scsip pointer to @p SCSITarget structure - * @param[in] cmd pointer to SCSI command data - * - * @return The operation status. - * - * @notapi - */ -static bool request_sense(SCSITarget *scsip, const uint8_t *cmd) { - - uint32_t tmp; - memcpy(&tmp, &cmd[1], 3); - - if ((tmp != 0) || (cmd[4] != sizeof(scsi_sense_response_t))) { - set_sense(scsip, SCSI_SENSE_KEY_ILLEGAL_REQUEST, - SCSI_ASENSE_INVALID_FIELD_IN_CDB, - SCSI_ASENSEQ_NO_QUALIFIER); - return SCSI_FAILED; - } - else { - return transmit_data(scsip, (uint8_t *)&scsip->sense, - sizeof(scsi_sense_response_t)); - } -} - -/** - * @brief SCSI mode sense (6) command handler. - * - * @param[in] scsip pointer to @p SCSITarget structure - * @param[in] cmd pointer to SCSI command data - * - * @return The operation status. - * - * @notapi - */ -static bool mode_sense6(SCSITarget *scsip, const uint8_t *cmd) { - (void)cmd; - - scsip->mode_sense.byte[0] = sizeof(scsi_mode_sense6_response_t) - 1; - scsip->mode_sense.byte[1] = 0; - if (blkIsWriteProtected(scsip->config->blkdev)) { - scsip->mode_sense.byte[2] = 0x01 << 7; - } - else { - scsip->mode_sense.byte[2] = 0; - } - scsip->mode_sense.byte[3] = 0; - - return transmit_data(scsip, (uint8_t *)&scsip->mode_sense, - sizeof(scsi_mode_sense6_response_t)); -} - -/** - * @brief SCSI read format capacities command handler. - * - * @param[in] scsip pointer to @p SCSITarget structure - * @param[in] cmd pointer to SCSI command data - * - * @return The operation status. - * - * @notapi - */ -static bool read_format_capacities(SCSITarget *scsip, const uint8_t *cmd) { - - /* An Allocation Length of zero indicates that no data shall be transferred. - This condition shall not be considered as an error. The Logical Unit - shall terminate the data transfer when Allocation Length bytes have - been transferred or when all available data have been transferred to - the Initiator, whatever is less. */ - - uint16_t len = cmd[7] << 8 | cmd[8]; - - if (0 == len) { - return SCSI_SUCCESS; - } - else { - scsi_read_format_capacities_response_t ret; - BlockDeviceInfo bdi; - blkGetInfo(scsip->config->blkdev, &bdi); - - uint32_t tmp = cpu_to_be32(bdi.blk_num); - memcpy(ret.blocknum, &tmp, 4); - - uint8_t formatted_media = 0b10; - uint16_t blocklen = bdi.blk_size; - ret.blocklen[0] = formatted_media; - ret.blocklen[1] = 0; - ret.blocklen[2] = blocklen >> 8; - ret.blocklen[3] = blocklen & 0xFF; - - ret.header[3] = 1 * 8; - - return transmit_data(scsip, (uint8_t *)&ret, - sizeof(scsi_read_format_capacities_response_t)); - } -} - -/** - * @brief SCSI read capacity (10) command handler. - * - * @param[in] scsip pointer to @p SCSITarget structure - * @param[in] cmd pointer to SCSI command data - * - * @return The operation status. - * - * @notapi - */ -static bool read_capacity10(SCSITarget *scsip, const uint8_t *cmd) { - - (void)cmd; - - BlockDeviceInfo bdi; - blkGetInfo(scsip->config->blkdev, &bdi); - scsi_read_capacity10_response_t ret; - ret.block_size = cpu_to_be32(bdi.blk_size); - ret.last_block_addr = cpu_to_be32(bdi.blk_num - 1); - - return transmit_data(scsip, (uint8_t *)&ret, - sizeof(scsi_read_capacity10_response_t)); -} - -/** - * @brief Checks data request for media overflow. - * - * @param[in] scsip pointer to @p SCSITarget structure - * @param[in] cmd pointer to SCSI command data - * - * @return The operation status. - * @retval true When media overflow detected. - * @retval false Otherwise. - * - * @notapi - */ -static bool data_overflow(SCSITarget *scsip, const data_request_t *req) { - - BlockDeviceInfo bdi; - blkGetInfo(scsip->config->blkdev, &bdi); - - if (req->first_lba + req->blk_cnt > bdi.blk_num) { - set_sense(scsip, SCSI_SENSE_KEY_ILLEGAL_REQUEST, - SCSI_ASENSE_LBA_OUT_OF_RANGE, - SCSI_ASENSEQ_NO_QUALIFIER); - return true; - } - else { - return false; - } -} - -/** - * @brief SCSI read/write (10) command handler. - * - * @param[in] scsip pointer to @p SCSITarget structure - * @param[in] cmd pointer to SCSI command data - * - * @return The operation status. - * - * @notapi - */ -static bool data_read_write10(SCSITarget *scsip, const uint8_t *cmd) { - - data_request_t req = decode_data_request(cmd); - - if (data_overflow(scsip, &req)) { - return SCSI_FAILED; - } - else { - const SCSITransport *tr = scsip->config->transport; - BaseBlockDevice *blkdev = scsip->config->blkdev; - BlockDeviceInfo bdi; - blkGetInfo(blkdev, &bdi); - size_t bs = bdi.blk_size; - uint8_t *buf = scsip->config->blkbuf; - - for (size_t i=0; itransmit(tr, buf, bs); - } - else { - // TODO: block error handling - tr->receive(tr, buf, bs); - blkWrite(blkdev, req.first_lba + i, buf, 1); - } - } - } - return SCSI_SUCCESS; -} -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Executes SCSI command encoded in byte array. - * - * @param[in] scsip pointer to @p SCSITarget structure - * @param[in] cmd pointer to SCSI command data - * - * @return The operation status. - * - * @api - */ -bool scsiExecCmd(SCSITarget *scsip, const uint8_t *cmd) { - - /* status will be overwritten later in case of error */ - set_sense_ok(scsip); - - switch (cmd[0]) { - case SCSI_CMD_INQUIRY: - dbgprintf("SCSI_CMD_INQUIRY\r\n"); - return inquiry(scsip, cmd); - - case SCSI_CMD_REQUEST_SENSE: - dbgprintf("SCSI_CMD_REQUEST_SENSE\r\n"); - return request_sense(scsip, cmd); - - case SCSI_CMD_READ_CAPACITY_10: - dbgprintf("SCSI_CMD_READ_CAPACITY_10\r\n"); - return read_capacity10(scsip, cmd); - - case SCSI_CMD_READ_10: - dbgprintf("SCSI_CMD_READ_10\r\n"); - return data_read_write10(scsip, cmd); - - case SCSI_CMD_WRITE_10: - dbgprintf("SCSI_CMD_WRITE_10\r\n"); - return data_read_write10(scsip, cmd); - - case SCSI_CMD_TEST_UNIT_READY: - dbgprintf("SCSI_CMD_TEST_UNIT_READY\r\n"); - return cmd_ignored(scsip, cmd); - - case SCSI_CMD_PREVENT_ALLOW_MEDIUM_REMOVAL: - dbgprintf("SCSI_CMD_ALLOW_MEDIUM_REMOVAL\r\n"); - return cmd_ignored(scsip, cmd); - - case SCSI_CMD_MODE_SENSE_6: - dbgprintf("SCSI_CMD_MODE_SENSE_6\r\n"); - return mode_sense6(scsip, cmd); - - case SCSI_CMD_READ_FORMAT_CAPACITIES: - dbgprintf("SCSI_CMD_READ_FORMAT_CAPACITIES\r\n"); - return read_format_capacities(scsip, cmd); - - case SCSI_CMD_VERIFY_10: - dbgprintf("SCSI_CMD_VERIFY_10\r\n"); - return cmd_ignored(scsip, cmd); - - default: - warnprintf("SCSI unhandled command: %X\r\n", cmd[0]); - return cmd_unhandled(scsip, cmd); - } -} - -/** - * @brief Driver structure initialization. - * - * @param[in] scsip pointer to @p SCSITarget structure - * - * @api - */ -void scsiObjectInit(SCSITarget *scsip) { - - scsip->config = NULL; - scsip->residue = 0; - memset(&scsip->sense, 0 , sizeof(scsi_sense_response_t)); - scsip->state = SCSI_TRGT_STOP; -} - -/** - * @brief Starts SCSITarget driver. - * - * @param[in] scsip pointer to @p SCSITarget structure - * @param[in] config pointer to @p SCSITargetConfig structure - * - * @api - */ -void scsiStart(SCSITarget *scsip, const SCSITargetConfig *config) { - - scsip->config = config; - scsip->state = SCSI_TRGT_READY; -} - -/** - * @brief Stops SCSITarget driver. - * - * @param[in] scsip pointer to @p SCSITarget structure - * - * @api - */ -void scsiStop(SCSITarget *scsip) { - - scsip->config = NULL; - scsip->state = SCSI_TRGT_STOP; -} - -/** - * @brief Retrieves residue bytes. - * - * @param[in] scsip pointer to @p SCSITarget structure - * - * @return Residue bytes. - * - * @api - */ -uint32_t scsiResidue(const SCSITarget *scsip) { - - return scsip->residue; -} - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/various/lib_scsi.h b/firmware/ChibiOS_16/community/os/various/lib_scsi.h deleted file mode 100644 index 97badb0047..0000000000 --- a/firmware/ChibiOS_16/community/os/various/lib_scsi.h +++ /dev/null @@ -1,278 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2016 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file wdg_lld.h - * @brief WDG Driver subsystem low level driver header template. - * - * @addtogroup WDG - * @{ - */ - -#ifndef LIB_SCSI_H_ -#define LIB_SCSI_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#define SCSI_CMD_TEST_UNIT_READY 0x00 -#define SCSI_CMD_REQUEST_SENSE 0x03 -#define SCSI_CMD_INQUIRY 0x12 -#define SCSI_CMD_MODE_SENSE_6 0x1A -#define SCSI_CMD_START_STOP_UNIT 0x1B -#define SCSI_CMD_SEND_DIAGNOSTIC 0x1D -#define SCSI_CMD_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1E -#define SCSI_CMD_READ_CAPACITY_10 0x25 -#define SCSI_CMD_READ_FORMAT_CAPACITIES 0x23 -#define SCSI_CMD_READ_10 0x28 -#define SCSI_CMD_WRITE_10 0x2A -#define SCSI_CMD_VERIFY_10 0x2F - -#define SCSI_SENSE_KEY_GOOD 0x00 -#define SCSI_SENSE_KEY_RECOVERED_ERROR 0x01 -#define SCSI_SENSE_KEY_NOT_READY 0x02 -#define SCSI_SENSE_KEY_MEDIUM_ERROR 0x03 -#define SCSI_SENSE_KEY_HARDWARE_ERROR 0x04 -#define SCSI_SENSE_KEY_ILLEGAL_REQUEST 0x05 -#define SCSI_SENSE_KEY_UNIT_ATTENTION 0x06 -#define SCSI_SENSE_KEY_DATA_PROTECT 0x07 -#define SCSI_SENSE_KEY_BLANK_CHECK 0x08 -#define SCSI_SENSE_KEY_VENDOR_SPECIFIC 0x09 -#define SCSI_SENSE_KEY_COPY_ABORTED 0x0A -#define SCSI_SENSE_KEY_ABORTED_COMMAND 0x0B -#define SCSI_SENSE_KEY_VOLUME_OVERFLOW 0x0D -#define SCSI_SENSE_KEY_MISCOMPARE 0x0E - -#define SCSI_ASENSE_NO_ADDITIONAL_INFORMATION 0x00 -#define SCSI_ASENSE_LOGICAL_UNIT_NOT_READY 0x04 -#define SCSI_ASENSE_INVALID_FIELD_IN_CDB 0x24 -#define SCSI_ASENSE_NOT_READY_TO_READY_CHANGE 0x28 -#define SCSI_ASENSE_WRITE_PROTECTED 0x27 -#define SCSI_ASENSE_FORMAT_ERROR 0x31 -#define SCSI_ASENSE_INVALID_COMMAND 0x20 -#define SCSI_ASENSE_LBA_OUT_OF_RANGE 0x21 -#define SCSI_ASENSE_MEDIUM_NOT_PRESENT 0x3A - -#define SCSI_ASENSEQ_NO_QUALIFIER 0x00 -#define SCSI_ASENSEQ_FORMAT_COMMAND_FAILED 0x01 -#define SCSI_ASENSEQ_INIT_COMMAND_REQUIRED 0x02 -#define SCSI_ASENSEQ_OPERATION_IN_PROGRESS 0x07 - -#define SCSI_SUCCESS HAL_SUCCESS -#define SCSI_FAILED HAL_FAILED - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a structure representing an SCSI target. - */ -typedef struct SCSITarget SCSITarget; - -/** - * @brief Type of a structure representing an SCSI transport. - */ -typedef struct SCSITransport SCSITransport; - -/** - * @brief State of SCSI target. - */ -typedef enum { - SCSI_TRGT_UNINIT = 0, - SCSI_TRGT_STOP, - SCSI_TRGT_READY, -} scsitrgtstate_t; - -/** - * @brief Represents SCSI sense data structure. - * @details See SCSI specification. - */ -typedef struct PACKED_VAR { - uint8_t byte[18]; -} scsi_sense_response_t; - -/** - * @brief Represents SCSI inquiry response structure. - * @details See SCSI specification. - */ -typedef struct PACKED_VAR { - uint8_t peripheral; - uint8_t removable; - uint8_t version; - uint8_t response_data_format; - uint8_t additional_length; - uint8_t sccstp; - uint8_t bqueetc; - uint8_t cmdque; - uint8_t vendorID[8]; - uint8_t productID[16]; - uint8_t productRev[4]; -} scsi_inquiry_response_t; - -/** - * @brief Represents SCSI mode sense (6) request structure. - * @details See SCSI specification. - */ -typedef struct PACKED_VAR { - uint8_t byte[6]; -} scsi_mode_sense6_request_t; - -/** - * @brief Represents SCSI mode sense (6) response structure. - * @details See SCSI specification. - */ -typedef struct PACKED_VAR{ - uint8_t byte[4]; -} scsi_mode_sense6_response_t; - -/** - * @brief Represents SCSI read capacity (10) response structure. - * @details See SCSI specification. - */ -typedef struct PACKED_VAR { - uint32_t last_block_addr; - uint32_t block_size; -} scsi_read_capacity10_response_t; - -/** - * @brief Represents SCSI read format capacity response structure. - * @details See SCSI specification. - */ -typedef struct PACKED_VAR { - uint8_t header[4]; - uint8_t blocknum[4]; - uint8_t blocklen[4]; -} scsi_read_format_capacities_response_t; - -/** - * @brief Type of a SCSI transport transmit call. - * - * @param[in] usbp pointer to the @p SCSITransport object - * @param[in] data pointer to payload buffer - * @param[in] len payload length - */ -typedef uint32_t (*scsi_transport_transmit_t)(const SCSITransport *transport, - const uint8_t *data, size_t len); - -/** - * @brief Type of a SCSI transport transmit call. - * - * @param[in] usbp pointer to the @p SCSITransport object - * @param[out] data pointer to receive buffer - * @param[in] len number of bytes to be received - */ -typedef uint32_t (*scsi_transport_receive_t)(const SCSITransport *transport, - uint8_t *data, size_t len); - -/** - * @brief SCSI transport structure. - */ -struct SCSITransport { - /** - * @brief Transmit call provided by lower level driver. - */ - scsi_transport_transmit_t transmit; - /** - * @brief Receive call provided by lower level driver. - */ - scsi_transport_receive_t receive; - /** - * @brief Transport handler provided by lower level driver. - */ - void *handler; -}; - -/** - * @brief SCSI target config structure. - */ -typedef struct { - /** - * @brief Pointer to @p SCSITransport object. - */ - const SCSITransport *transport; - /** - * @brief Pointer to @p BaseBlockDevice object. - */ - BaseBlockDevice *blkdev; - /** - * @brief Pointer to data buffer for single block. - */ - uint8_t *blkbuf; - /** - * @brief Pointer to SCSI inquiry response object. - */ - const scsi_inquiry_response_t *inquiry_response; -} SCSITargetConfig; - -/** - * - */ -struct SCSITarget { - /** - * @brief Pointer to @p SCSITargetConfig object. - */ - const SCSITargetConfig *config; - /** - * @brief Target state. - */ - scsitrgtstate_t state; - /** - * @brief SCSI sense response structure. - */ - scsi_sense_response_t sense; - /** - * @brief SCSI mode sense (6) response structure. - */ - scsi_mode_sense6_response_t mode_sense; - /** - * @brief Residue bytes. - */ - uint32_t residue; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void scsiObjectInit(SCSITarget *scsip); - void scsiStart(SCSITarget *scsip, const SCSITargetConfig *config); - void scsiStop(SCSITarget *scsip); - bool scsiExecCmd(SCSITarget *scsip, const uint8_t *cmd); - uint32_t scsiResidue(const SCSITarget *scsip); -#ifdef __cplusplus -} -#endif - -#endif /* LIB_SCSI_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/various/memtest.cpp b/firmware/ChibiOS_16/community/os/various/memtest.cpp deleted file mode 100644 index b92430888f..0000000000 --- a/firmware/ChibiOS_16/community/os/various/memtest.cpp +++ /dev/null @@ -1,310 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2013-2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include -#include -#include -#include - -#include "memtest.h" - -static unsigned int prng_seed = 42; - -/* - * - */ -template -class Generator { -public: - Generator(void) : pattern(0) {;} - virtual T get(void) = 0; - virtual testtype get_type(void) = 0; - virtual void init(T seed) { - pattern = seed; - } -protected: - T pattern; -}; - -/* - * - */ -template -class GeneratorWalkingOne : public Generator { - T get(void) { - T ret = this->pattern; - - this->pattern <<= 1; - if (0 == this->pattern) - this->pattern = 1; - - return ret; - } - - testtype get_type(void) { - return MEMTEST_WALKING_ONE; - } -}; - -/* - * - */ -template -class GeneratorWalkingZero : public Generator { - T get(void) { - T ret = ~this->pattern; - - this->pattern <<= 1; - if (0 == this->pattern) - this->pattern = 1; - - return ret; - } - - testtype get_type(void) { - return MEMTEST_WALKING_ZERO; - } -}; - -/* - * - */ -template -class GeneratorOwnAddress : public Generator { - T get(void) { - T ret = this->pattern; - this->pattern++; - return ret; - } - - testtype get_type(void) { - return MEMTEST_OWN_ADDRESS; - } -}; - -/* - * - */ -template -class GeneratorMovingInv : public Generator { - T get(void) { - T ret = this->pattern; - this->pattern = ~this->pattern; - return ret; - } - - testtype get_type(void) { - if ((this->pattern == 0) || ((this->pattern & 0xFF) == 0xFF)) - return MEMTEST_MOVING_INVERSION_ZERO; - else - return MEMTEST_MOVING_INVERSION_55AA; - } -}; - -/* - * - */ -template -class GeneratorMovingInvRand : public Generator { -public: - GeneratorMovingInvRand(void) : step(0), prev(0){;} - void init(T seed) { - srand(seed); - step = 0; - prev = 0; - } - - T get(void) { - T ret; - - if ((step & 1) == 0) { - ret = 0; - ret |= rand(); - // for uint64_t we need to call rand() twice - if (8 == sizeof(T)) { - // multiplication used instead of 32 bit shift for warning avoidance - ret *= 0x100000000; - ret |= rand(); - } - prev = ret; - } - else { - ret = ~prev; - } - step++; - - return ret; - } - - testtype get_type(void) { - return MEMTEST_MOVING_INVERSION_RAND; - } - -private: - size_t step; - T prev; -}; - -/* - * - */ -template -static void memtest_sequential(memtest_t *testp, Generator &generator, T seed) { - const size_t steps = testp->size / sizeof(T); - size_t i; - T *mem = static_cast(testp->start); - T got; - T expect; - - /* fill ram */ - generator.init(seed); - for (i=0; ierrcb)) { - testp->errcb(testp, generator.get_type(), i, sizeof(T), got, expect); - return; - } - } -} - -template -static void walking_one(memtest_t *testp) { - GeneratorWalkingOne generator; - memtest_sequential(testp, generator, 1); -} - -template -static void walking_zero(memtest_t *testp) { - GeneratorWalkingZero generator; - memtest_sequential(testp, generator, 1); -} - -template -static void own_address(memtest_t *testp) { - GeneratorOwnAddress generator; - memtest_sequential(testp, generator, 0); -} - -template -static void moving_inversion_zero(memtest_t *testp) { - GeneratorMovingInv generator; - T seed; - seed = 0; - memtest_sequential(testp, generator, seed); - seed = ~seed; - memtest_sequential(testp, generator, seed); -} - -template -static void moving_inversion_55aa(memtest_t *testp) { - GeneratorMovingInv generator; - T seed; - memset(&seed, 0x55, sizeof(seed)); - memtest_sequential(testp, generator, seed); - seed = ~seed; - memtest_sequential(testp, generator, seed); -} - -template -static void moving_inversion_rand(memtest_t *testp) { - GeneratorMovingInvRand generator; - T mask = -1; - prng_seed++; - memtest_sequential(testp, generator, prng_seed & mask); -} - -/* - * - */ -static void memtest_wrapper(memtest_t *testp, - void (*p_u8) (memtest_t *testp), - void (*p_u16)(memtest_t *testp), - void (*p_u32)(memtest_t *testp), - void (*p_u64)(memtest_t *testp)) { - - if (testp->width_mask & MEMTEST_WIDTH_8) - p_u8(testp); - - if (testp->width_mask & MEMTEST_WIDTH_16) - p_u16(testp); - - if (testp->width_mask & MEMTEST_WIDTH_32) - p_u32(testp); - - if (testp->width_mask & MEMTEST_WIDTH_64) - p_u64(testp); -} - -/* - * - */ -void memtest_run(memtest_t *testp, uint32_t testmask) { - - if (testmask & MEMTEST_WALKING_ONE) { - memtest_wrapper(testp, - walking_one, - walking_one, - walking_one, - walking_one); - } - - if (testmask & MEMTEST_WALKING_ZERO) { - memtest_wrapper(testp, - walking_zero, - walking_zero, - walking_zero, - walking_zero); - } - - if (testmask & MEMTEST_OWN_ADDRESS) { - memtest_wrapper(testp, - own_address, - own_address, - own_address, - own_address); - } - - if (testmask & MEMTEST_MOVING_INVERSION_ZERO) { - memtest_wrapper(testp, - moving_inversion_zero, - moving_inversion_zero, - moving_inversion_zero, - moving_inversion_zero); - } - - if (testmask & MEMTEST_MOVING_INVERSION_55AA) { - memtest_wrapper(testp, - moving_inversion_55aa, - moving_inversion_55aa, - moving_inversion_55aa, - moving_inversion_55aa); - } - - if (testmask & MEMTEST_MOVING_INVERSION_RAND) { - memtest_wrapper(testp, - moving_inversion_rand, - moving_inversion_rand, - moving_inversion_rand, - moving_inversion_rand); - } -} - diff --git a/firmware/ChibiOS_16/community/os/various/memtest.h b/firmware/ChibiOS_16/community/os/various/memtest.h deleted file mode 100644 index 9c31b54d00..0000000000 --- a/firmware/ChibiOS_16/community/os/various/memtest.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2013-2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef MEMTEST_H_ -#define MEMTEST_H_ - -/* - * Memtest types - */ -#define MEMTEST_WALKING_ONE (1 << 0) -#define MEMTEST_WALKING_ZERO (1 << 1) -#define MEMTEST_OWN_ADDRESS (1 << 2) -#define MEMTEST_MOVING_INVERSION_ZERO (1 << 3) -#define MEMTEST_MOVING_INVERSION_55AA (1 << 4) -#define MEMTEST_MOVING_INVERSION_RAND (1 << 5) - -/* - * combined types for convenient - */ -#define MEMTEST_RUN_ALL (MEMTEST_WALKING_ONE | \ - MEMTEST_WALKING_ZERO | \ - MEMTEST_OWN_ADDRESS | \ - MEMTEST_MOVING_INVERSION_ZERO | \ - MEMTEST_MOVING_INVERSION_55AA | \ - MEMTEST_MOVING_INVERSION_RAND) - -/* - * Memtest data widths - */ -#define MEMTEST_WIDTH_8 (1 << 0) -#define MEMTEST_WIDTH_16 (1 << 1) -#define MEMTEST_WIDTH_32 (1 << 2) -#define MEMTEST_WIDTH_64 (1 << 3) - -typedef struct memtest_t memtest_t; -typedef uint32_t testtype; - -/* - * Error call back. - */ -typedef void (*memtestecb_t)(memtest_t *testp, testtype type, size_t index, - size_t current_width, uint32_t got, uint32_t expect); - -/* - * - */ -struct memtest_t { - /* - * Pointer to the test area start. Must be word aligned. - */ - void *start; - /* - * Test area size in bytes. - */ - size_t size; - /* - * Allowable data widths mask. - */ - uint32_t width_mask; - /* - * Error callback pointer. Set to NULL if unused. - */ - memtestecb_t errcb; -}; - -/* - * - */ -#ifdef __cplusplus -extern "C" { -#endif - void memtest_run(memtest_t *testp, uint32_t testmask); -#ifdef __cplusplus -} -#endif - -#endif /* MEMTEST_H_ */ diff --git a/firmware/ChibiOS_16/community/os/various/ramdisk.c b/firmware/ChibiOS_16/community/os/various/ramdisk.c deleted file mode 100644 index 08abdca309..0000000000 --- a/firmware/ChibiOS_16/community/os/various/ramdisk.c +++ /dev/null @@ -1,219 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2016 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file ramdisk.c - * @brief Virtual block devise driver source. - * - * @addtogroup ramdisk - * @{ - */ - -#include "hal.h" - -#include "ramdisk.h" - -#include - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/* - * Interface implementation. - */ -static bool overflow(const RamDisk *rd, uint32_t startblk, uint32_t n) { - return (startblk + n) > rd->blk_num; -} - -static bool is_inserted(void *instance) { - (void)instance; - return true; -} - -static bool is_protected(void *instance) { - RamDisk *rd = instance; - if (BLK_READY == rd->state) { - return rd->readonly; - } - else { - return true; - } -} - -static bool connect(void *instance) { - RamDisk *rd = instance; - if (BLK_STOP == rd->state) { - rd->state = BLK_READY; - } - return HAL_SUCCESS; -} - -static bool disconnect(void *instance) { - RamDisk *rd = instance; - if (BLK_STOP != rd->state) { - rd->state = BLK_STOP; - } - return HAL_SUCCESS; -} - -static bool read(void *instance, uint32_t startblk, - uint8_t *buffer, uint32_t n) { - - RamDisk *rd = instance; - - if (overflow(rd, startblk, n)) { - return HAL_FAILED; - } - else { - const uint32_t bs = rd->blk_size; - memcpy(buffer, &rd->storage[startblk * bs], n * bs); - return HAL_SUCCESS; - } -} - -static bool write(void *instance, uint32_t startblk, - const uint8_t *buffer, uint32_t n) { - - RamDisk *rd = instance; - if (overflow(rd, startblk, n)) { - return HAL_FAILED; - } - else { - const uint32_t bs = rd->blk_size; - memcpy(&rd->storage[startblk * bs], buffer, n * bs); - return HAL_SUCCESS; - } -} - -static bool sync(void *instance) { - - RamDisk *rd = instance; - if (BLK_READY != rd->state) { - return HAL_FAILED; - } - else { - return HAL_SUCCESS; - } -} - -static bool get_info(void *instance, BlockDeviceInfo *bdip) { - - RamDisk *rd = instance; - if (BLK_READY != rd->state) { - return HAL_FAILED; - } - else { - bdip->blk_num = rd->blk_num; - bdip->blk_size = rd->blk_size; - return HAL_SUCCESS; - } -} - -/** - * - */ -static const struct BaseBlockDeviceVMT vmt = { - is_inserted, - is_protected, - connect, - disconnect, - read, - write, - sync, - get_info -}; - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief RAM disk object initialization. - * - * @param[in] rdp pointer to @p RamDisk object - * - * @init - */ -void ramdiskObjectInit(RamDisk *rdp) { - - rdp->vmt = &vmt; - rdp->state = SD_STOP; -} - -/** - * @brief Starts RAM disk. - * - * @param[in] rdp pointer to @p RamDisk object - * @param[in] storage pointer to array representing disk storage - * @param[in] blksize size of blocks in bytes - * @param[in] blknum total number of blocks in device - * @param[in] readonly read only flag - * - * @api - */ -void ramdiskStart(RamDisk *rdp, uint8_t *storage, uint32_t blksize, - uint32_t blknum, bool readonly) { - - osalDbgCheck(rdp != NULL); - - osalSysLock(); - osalDbgAssert((rdp->state == BLK_STOP) || (rdp->state == BLK_READY), - "invalid state"); - rdp->blk_num = blknum; - rdp->blk_size = blksize; - rdp->readonly = readonly; - rdp->storage = storage; - rdp->state = BLK_READY; - osalSysUnlock(); -} - -/** - * @brief Stops RAM disk. - * - * @param[in] rdp pointer to @p RamDisk object - * - * @api - */ -void ramdiskStop(RamDisk *rdp) { - - osalDbgCheck(rdp != NULL); - - osalSysLock(); - osalDbgAssert((rdp->state == BLK_STOP) || (rdp->state == BLK_READY), - "invalid state"); - rdp->storage = NULL; - rdp->state = BLK_STOP; - osalSysUnlock(); -} - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/various/ramdisk.h b/firmware/ChibiOS_16/community/os/various/ramdisk.h deleted file mode 100644 index 0860662d70..0000000000 --- a/firmware/ChibiOS_16/community/os/various/ramdisk.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2016 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file ramdisk.h - * @brief Virtual block devise driver header. - * - * @addtogroup ramdisk - * @{ - */ - -#ifndef RAMDISK_H_ -#define RAMDISK_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -typedef struct RamDisk RamDisk; - -/** - * - */ -#define _ramdisk_device_data \ - _base_block_device_data \ - uint8_t *storage; \ - uint32_t blk_size; \ - uint32_t blk_num; \ - bool readonly; - -/** - * - */ -struct RamDisk { - /** @brief Virtual Methods Table.*/ - const struct BaseBlockDeviceVMT *vmt; - _ramdisk_device_data -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void ramdiskObjectInit(RamDisk *rdp); - void ramdiskStart(RamDisk *rdp, uint8_t *storage, uint32_t blksize, - uint32_t blknum, bool readonly); - void ramdiskStop(RamDisk *rdp); -#ifdef __cplusplus -} -#endif - -#endif /* RAMDISK_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/various/tribuf.c b/firmware/ChibiOS_16/community/os/various/tribuf.c deleted file mode 100644 index 6ba78d3125..0000000000 --- a/firmware/ChibiOS_16/community/os/various/tribuf.c +++ /dev/null @@ -1,214 +0,0 @@ -/* - Copyright (C) 2014..2015 Andrea Zoppi - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include "osal.h" -#include "tribuf.h" - -/** - * @file tribuf.c - * @brief Triple buffer handler source. - * - * @addtogroup TriBuf - * @{ - */ - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Initializes the tribuf handler object. - * - * @param[in] handler Pointer to the tribuf handler object. - * @param[in] front Pointer to the initial front buffer. - * @param[in] back Pointer to the initial back buffer. - * @param[in] orphan Pointer to the initial orphan buffer. - * - * @init - */ -void tribufObjectInit(tribuf_t *handler, void *front, void *back, void *orphan) { - - handler->front = front; - handler->back = back; - handler->orphan = orphan; -#if (TRIBUF_USE_WAIT == TRUE) - chSemObjectInit(&handler->ready, (cnt_t)0); -#else - handler->ready = false; -#endif -} - -/** - * @brief Gets the current front buffer. - * - * @param[in] handler Pointer to the tribuf handler object. - * @return Pointer to the current front buffer. - * - * @api - */ -void *tribufGetFront(tribuf_t *handler) { - - void *front; - - osalSysLock(); - front = tribufGetFrontI(handler); - osalSysUnlock(); - return front; -} - -/** - * @brief Swaps the current front buffer. - * - * @details Exchanges the pointer of the current front buffer, which will be - * dismissed, with the pointer of the current orphan buffer, which - * holds the content of the new front buffer. - * - * @pre The orphan buffer holds new data, swapped by the back buffer. - * @pre The fron buffer is ready for swap. - * @post The orphan buffer can be used as new back buffer in the future. - * - * @param[in] handler Pointer to the tribuf handler object. - * - * @iclass - */ -void tribufSwapFrontI(tribuf_t *handler) { - - void *front; - - osalDbgCheckClassI(); - - front = handler->orphan; - handler->orphan = handler->front; - handler->front = front; -} - -/** - * @brief Swaps the current front buffer. - * - * @details Exchanges the pointer of the current front buffer, which will be - * dismissed, with the pointer of the current orphan buffer, which - * holds the content of the new front buffer. - * - * @pre The orphan buffer holds new data, swapped by the back buffer. - * @pre The fron buffer is ready for swap. - * @post The orphan buffer can be used as new back buffer in the future. - * - * @param[in] handler Pointer to the tribuf handler object. - * - * @api - */ -void tribufSwapFront(tribuf_t *handler) { - - osalSysLock(); - tribufSwapFrontI(handler); - osalSysUnlock(); -} - -/** - * @brief Gets the current back buffer. - * - * @param[in] handler Pointer to the tribuf handler object. - * @return Pointer to the current back buffer. - * - * @api - */ -void *tribufGetBack(tribuf_t *handler) { - - void *back; - - osalSysLock(); - back = tribufGetBackI(handler); - osalSysUnlock(); - return back; -} - -/** - * @brief Swaps the current back buffer. - * - * @details Exchanges the pointer of the current back buffer, which holds new - * useful data, with the pointer of the current orphan buffer. - * - * @pre The orphan buffer holds no meaningful data. - * @post The orphan buffer is candidate for new front buffer. - * @post A new front buffer is ready and signaled. - * - * @param[in] handler Pointer to the tribuf handler object. - * - * @iclass - */ -void tribufSwapBackI(tribuf_t *handler) { - - void *back; - - osalDbgCheckClassI(); - - back = handler->orphan; - handler->orphan = handler->back; - handler->back = back; - -#if (TRIBUF_USE_WAIT == TRUE) - if (chSemGetCounterI(&handler->ready) < (cnt_t)1) - chSemSignalI(&handler->ready); -#else - handler->ready = true; -#endif -} - -/** - * @brief Swaps the current back buffer. - * - * @details Exchanges the pointer of the current back buffer, which holds new - * useful data, with the pointer of the current orphan buffer. - * - * @pre The orphan buffer holds no meaningful data. - * @post The orphan buffer is candidate for new front buffer. - * @post A new front buffer is ready and signaled. - * - * @param[in] handler Pointer to the tribuf handler object. - * - * @api - */ -void tribufSwapBack(tribuf_t *handler) { - - osalSysLock(); - tribufSwapBackI(handler); -#if (TRIBUF_USE_WAIT == TRUE) - osalOsRescheduleS(); -#endif - osalSysUnlock(); -} - -/** @} */ diff --git a/firmware/ChibiOS_16/community/os/various/tribuf.h b/firmware/ChibiOS_16/community/os/various/tribuf.h deleted file mode 100644 index a5f7d378e5..0000000000 --- a/firmware/ChibiOS_16/community/os/various/tribuf.h +++ /dev/null @@ -1,225 +0,0 @@ -/* - Copyright (C) 2014..2015 Andrea Zoppi - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file tribuf.h - * @brief Triple buffer handler header. - * - * @addtogroup TriBuf - * @{ - */ - -#ifndef TRIBUF_H_ -#define TRIBUF_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Triple buffer configuration options - * @{ - */ - -/** - * @brief Triple buffers use blocking functions. - */ -#if !defined(TRIBUF_USE_WAIT) || defined(__DOXYGEN__) -#define TRIBUF_USE_WAIT TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Triple buffer handler object. - */ -typedef struct { - void *front; /**< @brief Current front buffer pointer.*/ - void *back; /**< @brief Current back buffer pointer.*/ - void *orphan; /**< @brief Current orphan buffer pointer.*/ -#if (TRIBUF_USE_WAIT == TRUE) - semaphore_t ready; /**< @brief A new front buffer is ready.*/ -#else - bool ready; /**< @brief A new front buffer is ready.*/ -#endif -} tribuf_t; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Checks if a new front buffer is ready. - * - * @param[in] handler Pointer to the tribuf handler object. - * @return Availability of a new front buffer. - * - * @iclass - */ -static inline -bool tribufIsReadyI(tribuf_t *handler) -{ - osalDbgCheckClassI(); - -#if (TRIBUF_USE_WAIT == TRUE) - return (0 != chSemGetCounterI(&handler->ready)); -#else - return handler->ready; -#endif -} - -#if (TRIBUF_USE_WAIT == TRUE) || defined(__DOXYGEN__) - -/** - * @brief Waits until a new front buffer is ready, with timeout. - * - * @post The ready signal, result of the back buffer swap, is consumed. - * - * @param[in] handler Pointer to the tribuf handler object. - * @param[in] timeout Timeout of the wait operation. - * @return Timeout error code, as from @p chSemWaitTimeoutS. - * - * @see chSemWaitTimeoutS - * @sclass - */ -static inline -msg_t tribufWaitReadyTimeoutS(tribuf_t *handler, systime_t timeout) -{ - osalDbgCheckClassS(); - - return chSemWaitTimeoutS(&handler->ready, timeout); -} - -/** - * @brief Waits until a new front buffer is ready, with timeout. - * - * @post The ready signal, result of the back buffer swap, is consumed. - * - * @param[in] handler Pointer to the tribuf handler object. - * @param[in] timeout Timeout of the wait operation. - * @return Timeout error code, as from @p chSemWaitTimeout. - * - * @see chSemWaitTimeout - * @api - */ -static inline -msg_t tribufWaitReadyTimeout(tribuf_t *handler, systime_t timeout) -{ - return chSemWaitTimeout(&handler->ready, timeout); -} - -/** - * @brief Waits until a new front buffer is ready. - * - * @post The ready signal, result of the back buffer swap, is consumed. - * - * @param[in] handler Pointer to the tribuf handler object. - * @return Timeout error code, as from @p chSemWaitS. - * - * @see chSemWaitS - * @sclass - */ -static inline -void tribufWaitReadyS(tribuf_t *handler) -{ - osalDbgCheckClassS(); - - chSemWaitS(&handler->ready); -} - -/** - * @brief Waits until a new front buffer is ready. - * - * @post The ready signal, result of the back buffer swap, is consumed. - * - * @param[in] handler Pointer to the tribuf handler object. - * @return Timeout error code, as from @p chSemWait. - * - * @see chSemWait - * @api - */ -static inline -void tribufWaitReady(tribuf_t *handler) -{ - chSemWait(&handler->ready); -} - -#endif /* (TRIBUF_USE_WAIT == TRUE) || defined(__DOXYGEN__) */ - -/** - * @brief Gets the current front buffer. - * - * @param[in] handler Pointer to the tribuf handler object. - * @return Pointer to the current front buffer. - * - * @iclass - */ -static inline -void *tribufGetFrontI(tribuf_t *handler) { - - osalDbgCheckClassI(); - - return handler->front; -} - -/** - * @brief Gets the current back buffer. - * - * @param[in] handler Pointer to the tribuf handler object. - * @return Pointer to the current back buffer. - * - * @iclass - */ -static inline -void *tribufGetBackI(tribuf_t *handler) { - - osalDbgCheckClassI(); - - return handler->back; -} - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void tribufObjectInit(tribuf_t *handler, void *front, void *back, void *orphan); - void *tribufGetFront(tribuf_t *handler); - void tribufSwapFrontI(tribuf_t *handler); - void tribufSwapFront(tribuf_t *handler); - void *tribufGetBack(tribuf_t *handler); - void tribufSwapBackI(tribuf_t *handler); - void tribufSwapBack(tribuf_t *handler); -#ifdef __cplusplus -} -#endif - -#endif /* TRIBUF_H_ */ -/** @} */ diff --git a/firmware/ChibiOS_16/ext/fatfs-0.10b-patched.7z b/firmware/ChibiOS_16/ext/fatfs-0.10b-patched.7z deleted file mode 100644 index bd9a7747a1aa85097d8c84b7e9ae962a18570fb2..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 432540 zcmV(qK<~dddc3bE8~_7l3%a0KnFas=0000a0000000028ek)-BM3e=@dMEbx?um|2 zkchLY%o{G5^TDYpn5lTJPGim7F>;R%Oz+Jc1Hr=aMw74+pxMef2(_U0-bRsIlKbGy4M2JNkyU z)*d7bW+r3YJ%N;*^s%VeXJO+SILgZQV~M>y#bvCK8jsay@Y%};`4JOZ>xYdHUGji4 zJI=8-y-tzDa3!^{K*H^NLz-4B5ZWeH|Fpz-WP4&BrQ(w%@0lQ@(RMhfH_{`N^9yQn ze(+yk&TiyX9hb`|Q?;TI;VbVTlNCMc;P2+2 zno~5wiZO1(;#k0?(E10;Sbq{k`e6mxt5i2h;bo%H{Y0lgf3MLKC1l{o`l(2M1K}K2 zTB^5}u=iib*t!eJk^X=Nsq&E!-)I&U0Otw2CQx8TyOFU&&YhB+9aTaVP_#~#xF%_N zLo#uCZB+yk^rT29xsDvQ3L<+nw|O7QEUst;KpqVGC$~y8^=k7Oe#@7x4 zFOC=zpPGl}$&JLEXyIt}(cB+cP&~tSXRNYUuAH!-;$#M6fckxrst-X{f=qA)!T}6S z0*>{^fSM*1tZTNzY9t-2KF!4q$2STYpBwvqS(Heq@co{alXug#BdM@QRGccJ9i%cO z#6I$sKANKXZ0I<4flt~vCRfmEXyNpG%YQgY#f8}M-Oysvx6Az)SVwBNF5Aj#}$st z9+^)2{+KlOGY}}Ru;_Nf<`hYa#>*M5R1ucoo%AQX?)QdwD3?jrEezv@;;MU@vo zk)I@$CN2DM^*T|cDYAJyP9bI)Cz7MG54TCcC7{>DxrNwD&->sS9 z$!{0>Qe&*wzo7eQfU3bN(H;qNDNrEVRb5^JLj(BQE z)jKMe->2tcR@3WiAUDA^*}N)Sl*t+|`hE@De>%_rU`Zvqf#h=BG>hRX#|T%+j#8Fs zSZoN7+fm`OHn!0!F&Su=0TZu6501Y+2lTo-3ldApPRriNYl5&IA2&{|E+1kO3!PhK zPWN1i*X$s(DOQm1jpvbU*~&5$AvD2%WbPH>~fA zbh&Yqd~7FK^1^j1%k9y`);i{1UsmCey+#9F>s(bs3?^wqx@yFD$z-PRGTO~v>S@dM zwv{%@KKAhJ-;;u=%nzEirW{jyIC_UH>|W*1FUc}r0Y$NtVO)BkoC}xIIlwlmD;qsp zNAz);Nn#$1KzpwrsJZta}^uf;X4=O1z^l@zwCTMZbD1#vzs)JD~AhdUlSFj zt@rw}sMLrXww10IW6%FgMG?UT;3Ih)pLu^o)#->jTJSn_|3u2mFKKL=2zxjk;$yFB z224k*=~{s_%>s#)hQPv`f|R+8`TltUF1b6SZ&fNsnyO?_SMMqL&&4~UGIjt5g!N+h zLE4bd*NW?2CykR--q;uBtwkU)hD#vxl`2e|CCLVHRSTLUHEoik{QV*e$s2NG;$OS! z*S0eR&&Ue)vjmP4bL?(|=WoXKf?G~;Nh2k^85^?`PXD?WT46`+5}Q8}Mq_sBYr9DQ zW!O>WOv5m+h&9l}Qoq5medN(}v9Ju1nrdfSSlcHDFJlW2aK%A&_0T}g-BT;?BB#Lr z>(iR-1jYI*_Cp^XiINZ6H^f$$4jBoUw89;DdIrPporFd_4&=5jo$iotb45YV}C>m#+l4_==gOHExNU{1Z~pNib+=qCOr=q5Z- zwbG%8@75Q%{mw`>Xh7}DG)q>XZ+0=%oBp^h$AEO08qbK1S7x~FvwEempY?(eyH zdoU2FV8hc+-PQcvxY-Qa09yVIE8cuzcpeN}6DlB5pLJhMi4@!7=j~56Y&6?M!6L)G zAL9fV;RcEjp6C#XLpnd%<=e+PA-oRTXOR&UAW-$3H3@c|1tv>Lb)a#E?)oue#B+SD zh)twlqT`<^Em?^H-CA2s`Lg{jMzdT7eBvy0MrV$X#~ne^67om!gO^+pCU&C@I4L$`Lb4&XMrC-;ZJdM zM=Yg{RxPi*A6HF0I!us1_K~0^%1KLOaGb*GP*x*K1Y{+FjIp8GS$J8h7F_cI{h@icCy;vfYlMMwK2+dbFKVixF7ro=>(yOc^*7|gWf!lO5 zBUwa);`Lf4KC!*6!EtU-GxV^jkw@xyvK`Z3=+4N}<3DV$U9{m=1|A0_tT^@@a8i?f z>TK(LAIezHY3QR0ghNkJ?=-Wm{;K32@3RNEa@8MdVb;V~QGI#JK;3V4U`6p)*lnh` zkbm8*pAB)Rk5J&qWm(g%W2$Na+ErPAP_C98#gEdAYkAU5C z*Mj=g&G`V!kF`IU$dFElgJyKF`6QLr9q~I`IXCF7IdOcTe;;K@A#Ge&Z_9E6+k+@r zGV(t$3Vkek#UTn} zs=uMC+@F0{lxc5QR-G@?jL78Tf&TSv?KkWP^S;T;BwK1kU*b$xnpdQ(CzQE(qevz% zM?+3xK;Pjxc*)Io$#>s|3j0S?9gj;k?xAfjclrAv6zYS9q5&V{*yJ9y(he=B)IGV+ z2$rSKK>H7#JF*uOZ||NX$zZS#Z9xwX+air3$H-x*)})*&fEo(dgGEHEzg+W6Uk)Ek}*Svm&f zc^$^V6@b@8x2iDA3Rkqm!Xy<8#HIM##$%@Opr5Jq|9%T_(of8$1Wm4R_6hTiHPrT- zu{d{z4}7Xfz^%W*iWhCbrs)!&UjVX&gPCaGP6QewRdb}hAla`Kz<66A*QO>3sbeLF z59QG@3x#7trkESHpPUfKP65I(rM@I64DC$t-xRh`#qRODeI`zrU~)s{fdfVNtsq?{ zfGJNxn*bOF=s7XM3!BAF+S*KboD??A?kzL|Z~c~g&?f(eWdNya#zd(>`=abroV6s( zObcfB0VH)CVDu>0+IW3PhuOUkQ$l1TF+n;`CDn$>E$$6gyuJgzBequkvwI_10lm4V zyI(DF;l0ZFBi8l#?s~$z*|j|H(Xm{Nv&ym9Nwq(S(*xp}~= zs;&+!)rQ^T3K@EPCYi4mj`kz(epvE*x9%(CO=nKcarb-<=J|&qn9u1^@I1#NfWz*4 ze^c<|v44Y@E50mEEL?j7(7YRIgmoq26|Bx;+|8bR*1vn}&{t0%zKSD36 zLef@pvdsr0pQ8!^pR)#3#lKH&sFhLhdk{yCILQfUx3S;j17T4}3t9_CATF?z8I!o= z%iZ8plOUZwvS*AqJ1i3BdqpwM3U*1WJ};*ZCDmMACjjwPYm0B3%lSi4n9jkRb=dKh z=7i^}d^2ypr0gQ$0@Sn`%!nyA4L-CrA@`!n43tD))lm zS#+Mnb-qxzS}AVH6dxjdrJm`?)l9J5dZV*&oUW2@81L%OMw7Ir$3)NcHwx1KL_z5s zN-^DQA2f{>rigYqfzJPY?hHl(PUH%2GMu7lDsV{S#{)v(OdMR(@Y~jubShjg8Lf@Z zc5|Y2a6y2QcyeEg9XGZLyeeuXfI~Z5e$5^xK=tJZl+n6lAh6T67f;_!ivD`xN?1tIwNLsAH07LIfKcs!y_AbnYG&p4Cnd*GwR&^ZLLG6>Zdq)P7K%qOQU9z z;31}$Y|~%Ls<{N5p!mBy3i*m1yg6fW!WVX1uMl*#ZXjAjhUCQ)jTD+u2|U7z*tf_E z%B4=&lH7*vLH9$CT(zB?M!dd#bxi46UZzgUU0AwfFEwt0HHj*JrHg3U#WAToF%TKCSWUTK?@WB3%t?D2zRL0!gA$ zQ*nM|N3$aWSrr)ZS(rS!Lg7MS5}Ni*Uq9#ScvQ;zeVFcyG_(&q?&9UdfoL>=p&rAA zH`)Z`sd=ch!JrUfU$7YSoDvnNaAnga)SC7hK48l*Ie*q`4UTG^vpely?KcE4sjL~7 zeo1qd_w708lLp{}refMN`E=AdC%32NAUk0_vrTTN$&{H7`2rao_6Bo}8ww`KzGb&i z^0&Gnon-=wpLsfmp?&}+qs~KBu*izZK9Dw){c-(==8ecD3+|q$I24|qY1(phCMoBUP$BU zAVl*mfA$D8YNbrr>7lPuaJ&g%?8VSJO^gQH_nJ{gCH_1NDm^~EKZZe%P4^)2)&R5M zhGrEy6gj>PB{JulXCqUM(5$hfp3PX>n`IO*s@Z}CD9}zP+kcp={ z-puqw#fO=w`Gp^npSGX3wdOY%dks{wBZcnsIx~4m>kg4Vay0ksXgR(hsRGijrlS&J zQ64_-xtds3%U86!P?N`5(ibp4L!s~*XaZnknBQ}&=y{yop?y(u#yI+HA=A(TISLk- zs`cMV^|zOfNm4pB`gak~m(sJEYD7;osmre#q=wkP%nBmuFzjI$huRhXW+g@75y@EJ z=r&dS*3YVf6+@E19=?YURTb`;;lHG~5yi><`}QId^pkq{gAZmZkIB?aAsvUFS}gQ0 z9KnzA+Y5y$;(K{yPRTc5$v6<0gfLS|H}>DYQaUd)woi>|&XPfAV&+d6*=v)$NHSIK zt#`PAxB%|pj-uR_CaJTvj(F`gVUH;X&9{aRvS)IFgA`<_=ef1kCDhvHS%B( zMCCavaD(BMHEdjUp*Un0xRy;#Iqjjg z&iAYJC`1rR<-Q>QR}inM5gfK1L1ETw+&yc-Yd(UUhb!Gwy@M3DIHc>WF4B9s1ndk% z-`rlHy75-%e#s-AgESPhmhI)BkzCcyIp`mNVZT7ux}JKNzfD8Q6;iwV;0p+Q0w#Ls zdvUkv#@jv&q>~#f0mymhva-hTXL?`2YfK}`lr!gEWL-e2hFGL{Gsz#?-xo5*b$G!@ z!EcW#cLhK7L@Hh0Pyq4iz^K7L#)24+Ey9zbqbeLobLC9fLQ2^fOr1O|`LaI5dFKsY zeuo?x(`9NsaqUi&{k6?(o;bqt*VDB`h-TGN2A;@{k+*v0vuRTQ8B{gkFs#5NiI|6V$8`5<>B z$6|uhd<#w{ereyEc7z;9D_}fa(u8HP=RDp;Gxj}o01mmMwgDDHpghBoW;P#crNL-i z{ui{}EtLTwp7L}Q)@QUmq~5w_e8tHAV)T)#2iTQ@A;rW`@8JJcuvG=bDXLv>=s6H|6I=nu8;#SF!j^&q+&&y-em1y4A8NV?utv6&#GJsz zsHVSr*`Xyo{w6s5J{K}~=5fObQq#HU+ZCcaGI{4Z2jM&UPd1kUM^l0`1;U)Co6F;R zY*uE~L_#^QnSL`4Sb(C@m$oLFfZq1LHAsV}My8@(fp)hCA1~NL3K7FP9S)e#n2#lv zr?eUM+t6^-21cO)({eA<$-@?`jZu|xas!g$va5iLK8=397~gS28%_gl^KW`R&3!C9 z#mI*eHX`$4V3wWh3zOCU8Db}`uqXXxHYk4Y24+mP-TA#YLs@%`h*SMS!j;!Z+!M3h z4v>R#L6jiO>d5pC69p0+G=to|A>c;wE_xKtqk;dY4y zMuWj8H``A&G&~sWAJF=ef;6CYc)x{1v(vyGi=qe1D$188nr@UTb#{orCk!=Zmwz z<6gqTQPDosr|c=Fxn3z-4g{^#3v$y*UfH+K^O~zI-Qx*Rv>-tM{~lW+4yO?$P?nKJ zc~){GUpKG{eb7%jFlkD8o|R*^6h-0e`hJ}(dmiOW&dw5YW3l`AVk_cRm{@nf-Mi*m zu^Yiz+^*^Z&4Oi{mpCoSyIfd@uM;cA5ck; zSvTIP+{eQXHy$##u*?kjj(&FJiEq7#!gMiq6R6rYp3A7!k-Upi`p^<+QeWb)ITXiQkU#A$ zoaX)}-|<_f8;}Tj{fa}2@oym%tQT#g=RKDsXNIA}4fH}w1ja11=rNo-La;vTB6;oy(Y#he?B z@cG$Ij@c6apl-)jscxV%=n*0qV*6}>?$Y1JBSC53d7%D(iwENHNA$)KVQ@=;o#p40 zsyZlyDGMyM1t?>yBFkb5}e{ zr39oIJYyD&JZtIWMH6}BhH-?)em%Jw&QC%B&%0&Ap*TZ;8`%G+f; zyq>3N4-eBwSk?c%Ig#(!y3?8my&W1f^r-eVunlYu?j_@#E6|4OeS9u^EQ-i3M<0zs zW1xM#_-3fTSca1LX_`A4U|EKYPB!ECN!^z4%TAD0DUjL5t;gMUVMpX{6^LTyJh2<; zHFJd0lO0@|3XWqKnl~nw;+hZc@E;GS7xTggkJr6kZ|A~=uWf6H7&N257GHMF8NL8i z?$3UMx^eZ$PE z;^WB8_i*AcHY2!^d1)M*4JN=*_U$1UE|x=E0XC<}tGFgN!*G7cnAr+ql0kEFwKiR# zDi1Y!3Dvm)|GSfidj{faRncv6M<|>-*9TPg8wwqklW@}QrP+-TU?kL);BQV3>I`I5 z$h><~v@!yY2!K7O>WraB&svQaaz=lbY$(9ezg_^p!$ykpVVx2XlE}UGEs(KsTO0{z zb&U)+1$$g6BsyG&Ex6+zR(+wAv$sP;DSN)cPkkB zc?RK$>kA^yup4Xg^86z0z?WlG#x`HB9Z7nJV_mCJE_&cnSh}@5g?2dN?~Df z>4gh6jG9)zWVJnR#6ooc;RL+TH=A-x4|Y|H-4I7q)PPdRmCK)sSy0j@wdp|rLkh1i z$K1RUBuYhE_ZB$StbU2?@(Fm>?EO31faQh~3i1>qip}t{JotvQP>hJKxd3Uy&Np0uxu~PKzE!`Y<+t9KD*QnJ zd^nn9h;wrcKOkGg9v$cwajsT9JW6X_D{MV8c;@39STWq<_RVML+OLOl6>e{ykukbg z;C$Wl_EZ^PcLZvNE?xZ_h@f0Ov8_Qm-hbl0qmI2rY z@Xu0QP{d}u(Jca*xmGPeMzBZxUU5#>g$+N-a}N=^uqp%U?6&j;ga1IIKr+%}!FLNO zYLTR9wG`l}WM{OiqS{^{sq#eF$(d%!{dT^14m`BhW+tLYJ^NKMBu;%y3HL{U{UV0G zb10O8stK8}&u&Rr_;_e0oE1+19tkk5W$=rG<%HSi`k%)r|O zqDPe*051K!C`lBEpR!NNNkB&ZgB9`RTo`x{SKm0t_u}Zf2cC3_ryJo?KOLS~avNM~m$+U2Cu5wEN-YV);?h8JH zdP8h%6K3Yb5g#HU(8Jp6;S2Sa33SN(Gv{act9(6gxd&udjayeW_co7djodu5-Vs|l zfA2pU)CxXbjg>d}GX7~K?$8VRQaFaRQ0)9NAAz}zb1Sc8zE6)Q2kpnrCI+uICa>CS z-45Vc-yYD6>UmixCX(C=v&JO6N!s2!J+v^qW2_c!f6OyTTb@T@06~Dr52$7``;UHD zov;fHQM*k zIPSd0Ciup;HaenSbXmd*Z~6+QUq(OwV2c0{Xmxr%QM&_wCz>(wyC#I~e3ylKY(Qw$ z{me#i5Q7=`_~_pzj1bFSl17ynbG|tl%X02k`i9ASFlPshZ#YC=;VpEI8n0J-Kv672 z_ZXoY7ssv|pueZ{2D%GLjyS4-fh-uxBns0MKZo6qml*g2JXHx5bLZ@x9wb4 zCGFbRxw2PQwfDyzno1Gtd5S;IG1me<^zZX-163-d8=UpGi>cS& zYLQDdw}R-`?9b(5`=VpRZ%sHosTu!>>c+92s;0hq2epxqF((phLe*Y>Z&aG3?4arB zvkY-3mR-y9m~y>@0FFekOARIn?%{klImR#C0s@IYfjq>gi0=W&0nqgm#CArVGH9V0;;XGa0Sw7Hbigb~{ z)7c|N$N*%AS@vMW5bobf=@hKpGaH8Cleul?kHtIJb8v!?2jB``Ll;_jlQKmyTS>o5{LnrJXw0)|f-*)#wtZ4r~hHO&HfrNu;A9 z;#pAtCuv>U0`v~Ouvt<;Nt85fa5IUL5_+IhiGo5|60$`mr#EM*iv&g|iI|Lnw{#YO z%MFBNX>@}+oc03jlTu;*c9#_WZkVgr6P1QM-_!v;baL!+9!=P|L!O-7pNB7yI}W0D zwM?WYklw4F;>v2bIVPR7Z9E^7f4PfHS)6?S+c|4t%Oo<+n#$=r{vB zd~%R}scdUe$|vclFyz|ZX?_G8s-L?{wk_jq0g}3&@ZjgRqwi{pRPV0c2~b7mix@jr zIk+iVrB~WRrr`VJZ*3AwjA@1}AjNi%^r-?&I`(-3 za=h~RJj-pImD-ATzT$gd+WndH#~}#!rMw9NnD?+Y3e;~7iP~(7?}%=PC^IAGt!r(= zWSeV^2;*#MgZ5>Hw}8bYdb!S(MfyLU&wj=b#_DW@oN0{gE{YCQf@em0YUb+lc#W!% zy%5TzkTuq^gn{>>8EY?XCf5a%ICGf+GJQu|X{PyqPqMW3;#`gyvY`(cD(~QYeY{lR zg1No73Sz+!WZqZ-GT5pNey&}kP-*R_eiUdy5jwyNFzSLyg-^O)%oH<+(OBVU(j`u0Qkv6s+CPB*WbqG_^Z=h3%bI<5*p5 zkooD8fJEYjkT-z?hbHg2GVnZ|q$+vi(y+1XlXcd86!7C=;5Lz4HF;S$-V%76hZ0$k zqfo}AXKt}Jv?XYgx!?TmNOx*;IXA}k;w=$oW$ybr7f!rXkASX{=x2stT80gexG4yb zmD`!q|Ll3%8$^OkEUk+($>g=6dbF=bsdy=E5k+xjPZ<)qn**Eh%a(YM6bw9B-Y!tC zcHaLvSm!{6_@!vYbg&#NTqhW`XC^X&ck&xfTZaE&3k+l)4h1%$%uzB*WmfaDJC{EX ztDcv&DV6+zpy{wqddzi$NhKdTe!#UFF8$TuWQZiR->h-YZCi4`QbvcPKAQ38t^`6Y z$8*%r73CosQYwj1sEoTYy?xp(Vi?d;#paGUPOGYb-^)K`QsAA7lRD1KK4%4711CjyfQb) zjM=&_J`bNeXmS!|oANY$f80NLdl2fb1JQR(mOr^v39|DyAykp}v48K{%21vsJ~jlD z+hJvS2GV!Io&%Hr2+H_m7Q6T*iRHfxll(=sagM*I4x8B&^Y6h~jF;d@C?J!&PLVyH zW(ceCg_K`!i&)g5MD=Lt%XIVZc8F60|H-t11YL-XUe=5MUyrGJX zzZf8Ur004^2)dQGD^H_5RWD@{Y`c=t0tLR%r132H~vw4ZHt8sZBA597z)fm{Ax>qhR?Yd?ls;G=a4XPwjT4Fjx?SnfX(v0tLUL9DwbV^c z5^8#YD-Gs-=#cwH5^Eqy(4}x!wQ#V+-@skhOb4MWoXx1!oS#w84;pEHHzM@l>qq4H zEZ5s^lpf1gj-U6AkYZ^~X7eiLN{}ks=IPg*ExG%sN$;q6xjJ@p#Aia=6G!K_WR4ki z=2$>h=e6vAM+p*Cty`7?BSp+~AK2?t;e{;h8WNnCM-PF1iQYInzEImklIonS=udM1 zROVe%7}E_L-VLw4?B*dm96G?eDF$6l4$8QK- zy}*k}B~T~sD9dRe+91oh!&;k`C1LB8`ye>XV^GoeW^Zfy{rl$%e-C5>LD7&D!n~); zxr{I#xhkegV?!ce@jC$AmIL(N1djvG1XiBc7D*22w^juh_eOjUD+hle3`?Wy35f8Q?g>(HPn7hYO*FquQP~I{AFVq zSP8EH>)tqjOP4kEtsvH#BilD-eZsd4!rw+9pT$`C9<|Z0xFnR28y1-S=4&9zx^0w|0_3BC9|rW4 zlTGP=L8=B^DU=urWVMvIS1^taE@4xp^j-5g9F2Wf6skJ2%g~iB33$P?8u|1I*In9` zQfzJkoqEJpjPVnm0R2vNLo2kY-*KX&cFUYzOP7~RO70NXBsmGb*mrKImgh&wDfOx3 zssj|OX-Rd(_?D%U&Mbp2L6+N`qtxm1t%?^3=EBh|GUih6SP~4hrlEk61b-?PMXqsL z9;tzQ_p|J~00~(EDJr4B(Nq#?PBV|v8{q##|J&4*`2A`n*&9GKiD-Y#8$HnnKHg3k z<1*k54~ivv)E_tzR^V)a?nH9B^q@w#1lO&6(e^}aX|Q&TRr+EUpW)U6%hpoYGykRZ z`BC;zyxTCM>~)njtXl%e5@GlCZQI(YISIoLXsg1ZRh{yw8*0Jk?Rw^aX$E?Zg)%ln z;ev5YX*hNWhFaX+{@R&*PzOF6++c_huW^+WpPFhzA-EA$%gq+*rw66dtxD|A*macPR#>z%2IKl18rsv|KXntk+0)THCHwuFNl-OJLU8Y?a-ZRuxTpwet>&& z=xN=)o;_UICd0tuD2Y?)OJ$+y@uNyK0Qfogm0habLtqnARk}9gTJ^*aZ-s>DnY`{eGXyGN^*-C!W8cn#GPFr^dZ{QHi}fhftbtr8X50EXJe2It$2oY>PEs=A2;#em7d z?ppXcUEpaQJJcu3u}gW9j7;@0PHE#orEs@5KQCOYhv7Y&_(PI37C0p-JY(!Lo~i5D zt>h*vpQb2DJ10oXTQC0t0f8}upaHd#%j8ja#h=F+H=F#3zr(sjm3PYM5W~|lEtPMi z#|J)yeBrMpt^5-q0CN4PI@@(ncd$_l2H&mB;u`CIE#~0A)Q!Us-EZc1ur6+Ri5)ST5qhA00=wy7 z(KGG%_rG`{JhP|XN=pxBvv*T{k&epS3%pm&Jl1nc?KagMgNC^npVxBU>qw zjFMCm+yKUvi-!#DCD)C9V<337m+NCLXh@(kTUf2D5ys$mH?F>WNoRyEj`DeD%8xTv z^<}dkn_m&0{LtstTv2CA9-!6sO#a=1)vT1j1-Eg>V-09^etD%m=DZAL^ALp6KsLZe z?Gdq5Q#-rs_MTCBDaK|Nrt;M?Wt@y}4hvbJ86nDdVXfe0)tllPyN*8GH5)d6H(_k6 z9g;vE6W%j#nfbPqb(z~vwFu;Z<$r`o-L(W_g#9iG>6t6e;(Tx#@Udx-xKECj^lQE~ zkt{IwgOsKq0G8<71_X5$)+>}CUY)v{qdNrJycQ7w#wL{fxn!^s@R~YT2?pGpdr)<& zlKA_CcFLXL=dx~%7k)j=5=e7Mq?;#;Jj0f76M`kotkh}F$mP{Kw(jZ+(o)o%xPHiz zk}Tl#nGHiaiqYiyet_|w;OSr4y*wjM8UjinRs}sx8J-6d`lU!oT@-_<+;vyWBYP`6 zJy|7zld)DLnf&dbDrwJS%pgP5D+9+Vlu3)BaHCzdK=cyKe`Easf&T5rIKmNpD>c?=mrm61QBb zA8YuBVce(}vqR09>^xrTf!mYxY`A5(P)<&A)xy7D2P|OvdGqt`FPI6&$D^4x>CWP` z8S?MkWM>`dd<*2%(U1RegvnktHfdlQo_x43xk24mn4- zJha9&WPL*HhUl!A(5i@jr`kP52uq`>5^yMS>0fD$65o)2?6aT-SIq}@u%9Q%K&D`` zV?Ms@?xj@6h_8a`>S$l?zDj!zI)ogC(cKYCl#p0)#QyI@>TfD%^SV9*^J@M+PMKv{Qz+FrH4x|^Yz#>`_rI?al7{9rxm z70OC!;mCv$2(_+hy=Bk|Pi2RULQE)(*V$DcK%z4t)(--_SnG~mvLzlvQK~9oN%aK7#5;JcXkd97BPjl<8Ecd7;j0?S&JY zWQo9cuQ`WaLd{u4qMv_2$Ztrbp5iZuA~DQtyD__rLM$BDqGeOuUZ2gHD9+m(6 z1l7!o6vbM%i>x3yI?m-^4t`3lEoK$eu{$T2AEZNE1)=~!{S^M~x}s9CMQ_aN+@{Jz z%X5o?V4V7q8^amw-H`l7lm_8mX{1@oc5sUpMwCKS+UMm49gW))fhXk38BBHrjV3&- z7_5{6BFZIS{0-Oq-;T8vOn-ZddtUz9cHVm(yB(^=J*?u!{__FXkdX=~uZI_LAf7dUz-zRQeHXQY{IBhJ=fUMJ-_4k`~oWo*%%R!rm|x4+pWN zDPXa{)Nby>nMuJjTjP=sr_#_fa}5`L01zk$e;NucH)FKNA<)GPu?3AYpabcqG809z6K=up)gCuC${sE!E0oUSD{w24aEganU<leVPo17C$m{j$M}Zc`AciKOfZJA^Uc~aZT)xKgALMSG&$CSttrV8Wq4jEM zZBt_cjWrYqVm%TEnc-*?o@k-oC6W!;RYWsK>5q&aC}e@ z=GjIA$>G{77pj%yF(Ziwdo&0>9T&ymu%ZoTj9NL4&dQKYMu7CJ16ox!cf3kDMHlPi z;q8f%j6Imu1aLg=^qBQt$xx(%d&1BZHG2*WvG=% z&^SE`0&Yg!JM1ozGZ-^D-o!0d67S-B|DI_bK3ERK*n@&)h?rOA>4R_Q)xcN^Tp=0l z^D*Z)S@TGix0a>f9FtbWe%ou}Nt-Ev4xKN9_i=u)ePttu@1W4QvRh~DBmM0}ZfTe% znB!>5pU;?xpcbsGbNe!TU)Rtq z%}{GqmJ8cA510NOA%2AOJa39{(H}45UcRCLZ<7~DfNyF;k?YW}Hl|&Bvr;`+$@>(P zCbZeB2ssnm9%@QJw zM#+9~5=rmWH8Y?Cm&}Z_1vsIu$CtSh>llL;rWzV>RHk3RuWJV*Cfy1yy#Q@C!8L&+ zm0wf~xoxr$~uNh|_ z(1y6rLa}OQ-g_=86cGy*&*nK|A1KbknmRnE34g>L?Z(xIdBssLpwIAP^_nBWtd$Ms z;ZPf@(n(Q#l)#*vX5f6XZtkdYO|%Sr-Dux>;v6W@@pRd1%-)wV3<||uf#dIIdvPW* z=+|hba0~s>vQh|ngv_9xF#cIz)TG>!9M(}ey z!Yq#%mJc8!jl@L^3=S6Sfe7-P*{5go3DJ3uidBkDpKWoG#k|5}PsgMeTKF*U*VV#> z9A|`a;<&rT?ZG^9=7Hf?wScUv=--a8V^OX57R#%d;oSI&XJhc4thx%ChCD7&$C9>V zd0pXsN&33vMVJBOAnZhyktns2CHhyO7EEMTI~Zlw4}ome&~*q>c%#JWk$bNM7J2N} z|CjmIGLUT7#lCt0$5pqfbiBzlG>S;utpxCbujx$P!qPF3##*{=GH3Hv{R7>~i-c*h zSZ;=WA#bbogJuPl9)do!JY>th0LY8J$0n#^ofbfqoil9MZVTI`>_Uua0c-}`ay4}@ zfo#@I2oFiemzHdzXt-gQ{TbERpk0Oy*ip}cL5P$4-rCEk?d0oTkEh~hQm<%nkp!A? z6PdI^p60zJ1%HHxey2s8#opsVsz-T$`N@tl1t5!>O4AH^BM7 zoP8O+f&CXYiHhUA5Bd_xwA>}l5k`06qg^I;WGN7BlY4PoHF!uiZ}$+QCA|-R)r+;I zTvbHM-o*^951=}lv>+Sh1kcm`=~jLAK54MYrIJ2}^Us|V18cx3*4>;8=#L7=)@0bi z9?|B=mB`aeHVJK$e#*91O4Sy~&gwEMuji@&D?rr0V?KYm52yGcG?$&r!y(j)dCG~6 z&!0Z%4DFyRD&e-sY^(tSr+{m~CHMK&AsM9rBIH|2MwcxpS@QULIt`d@6{N_MUPI8Z zbBi#>{snD28Y>qHE6P({KtUB*xj2bpyc*ZQg%B+$SGT*P@aRpCjHOs0+ zf_cxc*pnr!GTbsYldh()mwy{!m36ySI+p5e@j&Hmm}KIPvta6r>>jXcul`B4MQ>bF zAWhwPO7AHZ6j&n+*d0^FpD-bTpi2j|8o5h_A*1yNU)qkY`ipUSWkQOrWs5hJ>K*G~akZOhnKmd-|z z84n@-D~r(~0Y<~$epvTTkka{rq!h&`ds1!n`93v9+>?@rn{B3mpG`#A0!RpR_ed#D zQ-L^-2H~mu20XCvxn%AdQ|?F}S)IhP%SgF_uU3fJXE6xii@+;;G84hmKN_vk^5B1U zi>W*tVN-dPQq^*HZ+_0aox1n1ov;ll$X>O%8S8t{h)@rH0(dDpzaP$zrWms##8`lv z6_)$bBuTUM8Z3FS2R0#M;wlETwC0tqz8`m29Yr}>4nFQU6RwtyORsF>>`#gUu}DG97wUHle3=Ok%8uB>)mV!@H=t2rA5q@-UDa#CCYx11nlfH}e(+QIiC^{#&A)w=aCc4xJrmS7tB znv)32z>nXEM2YaPj0V!1^c~*GEsQ7srfBDuRP}Y_g7Da$$q?J|agiTn(vTn6Bm=YA zaiWhn!ZI?A<8#o8o769|*G zN4VI*vv|}{NG@3tSW#DR8@SN9!lr(6h-ixb;C>ObJG(F44~Vt@u0R3=+PBaaF4X-l zF4j*aFrVrd^oLTQ^jBc)!c@;FKO`!X!G$CM@R*up*(O20#Av6FYgrqL7)&!X2CPuH z;0odg>-!Ob{hwE1Eq>2Yp3m*B0i9FmCvT<&fx8<{9q43;#?x?bvN5{l+dJ30kVEwm z$>3#6>@T(sE4}J_qm&Jc0fGqDW0Y471?}XgixbUYFy{fO@l$4E&FdE6Nm>ex&O-YQ z23C?o0bKj2?cno!;WyI@std*AhDPj6B}K(E zLeM7}R@Tg#Ocj~|^gAr+$mhOrZIl~LoP5UXj^Tp)2U2uK!Mws2L5avFf)aJ7@6v&s zv2dV_%YBuoOu*kEhpn>Vz;ssp7SfoRXX`h`32?YGE<|?zN|ftH_5$Gnar~|P_p7>D z_9p4C2}I`y)gIdr^m!@4kQJjs`KRTsPc$=4QG1mO{nXCBW*lz#pvF>W$nN>E%G*9a z6~8ZjeyXs1`iSZqrqgEGE^*&be2TGO2#&BRxs6Enic)2~ z)FYY1mz`t-gh5_(F5oNh*o&F2x+@T8EjD!ui2XqDOd!z3Du^@A$jL)yB}l;FdXF%; zj@E}c&^F(bCTQk=$`|m?SKaI|1d5fbnUOd~fB1khM)nM9w z3YkGofCStl_bIGcKt;TKx0kdZASYfK3GY}W>ce{UOPKmbu8bq5`#Ww;Vi-z36^N2PJVNM83%v!-&l zFk!XdAV?AB452|wxL_UqVD^Vuq&ZFXy-TWkxV8*b5H>p;+8c|gavAWKxw0Ps32u;W zN0vl`j##21aWQ%;MWI7z4YE!pv_ofT4eWJ{QO|soHZZ|BZd-gn4N-k*reXukgX&=I8%Opw!Ocax zWT+Zzuui*Qh8t{pof`?}{c9BavyE}xl9b|Q=!k`A2C3#wN=!-F9niH;!sgR0rZpXw ziAr*g>O;B=Je67&`ZDHz1QdtEfst5_l`R7>$s1*9n0o5CToy3ezYPPK&1bo?mnwBg z!Yr%?jf0?NnImzhVRo9*ZuA$DTrjU>n`GA^^|n-=-Y_9y@vJOz0GA;MD5N&^O@X<@ z(iK>*LSl8W?G}tKk@|&oV{KeDu`;bA=oI8LHIq*8RV}+88*Bl-IYey|l!8A}|FhgL z%s*YT-^AwrjSa>btrN=e^L~<>_|>M#*g=wj;B`Z`*eS}5{+TT83S_gtGWzQc=jbMT zuq&GHjAW`LDMHovXk@(3O6e1rCtP>$Z|8@_g)P=?%3%b%2t}lEdVj%7F?T0qbeiaX zs{*t}uok*U0p~__9OJ%tdFPiBY9un8njkNnUHnioHUeYI$17>sIhmuL(BxgXrr?CW!}(UaemupbVKHZ$5iWkyo(=6cgLlU$k*C%&9xiU%KG<^n{z z%bAn-0KH|*$p?Gde|+kfSJxv ztf`CGf8mkMJDznPe$VHTEX6(lQFUQ_ZB<#YQKu_Hhv4F!HnLkDwE7rW=q_u0hSXRT zNCHw4nfpPh^A6T9^BKlfWXdy2r9%b;8Ci>4Pisk&z_;Gam1_{+{oFGYA$ve5(u(ww zR`uwq<6J1;FC$PyE30#;3E7|F;Z+AlIRW5p%b>N%j7Ga73^VyXN6xYDO?bR|Mn7iRkC+7wod=NF@E`=pSwVkA$W8VN^C3=r3sUvW_m1 z9020;ARTy_j_i z8=F`z2sv2Zl7o7hL-KQ0X>&tda22?lfAQH&63GfP+GC2@Dy_@3eN?JBpj)QW>yLhb0liGvxCDAx@gKN$1R%9d*E)EQr zKuQ{p?y4iFohd5JlV_C7c^gFXUNwNF;d*V;^q*bA#KMrn$z7D6kl=)6 z2JEW%KfKhQLQA5-_QqC0il_F}J)x55w2#2*LbV(JyiNjpJAm-Bwh)VBWC&QWe$~rJn&&2zu*MSdIP4{Oxv(`LZJ7k6j-0C zHQQZ-Y65_)@w&hckqwmUVLm}K5HjWI%b)xYv_S>&`Z7u;58)bU&n*l>=eys`8>Yhp z=*mCroQ3-X-1^6BN=aO%EYjIVUn0D+wKZ<0IU`f-9iS68+@KhKI0_t{LXx)@NG^TE z%OB2yT`=RZNO3Sccp<6h5ds(?ITh- zHvu@{WRAj-an7RpL1!c_PSy^Z*u)d5It1&XV9WUGMTI&%32R%*DAZh2DvuT&i1o_2 z(TLfNbUw6sRg*ItVQgp^TSswc*j8)X5=5ve@(sr*E$~5(M+v=)8+8ex_zWta1vl9k zVg!7;Jus(At3jp~H!fD1@@HF`TR595l|ZoI{ub%97mPBc}$AIfN~Xc`w`-CGNs zsdoAyOw-&+1R2Rcg#^-=W)PT7JBnRs2_4R30PoKPQI316U)zfODY?A|W{#n??hF(I z?xnXYUZ_-R^0JGjnKzp72)DQQ>i;hh!QTGsw3a*vS}&O9G4>dxgu-qawsFvmaZ-?b zFh!uWLXV$QGoC#u)qW|~pj(ODgkGkV%9ILitkby%EvPk+Z+li4mkQlC!J6ziqXi%5 zoSJnB;^JN`X>H&TjOhl4&1Rh;erTas=3*uNl!cm=VNnl`Eyy5qwjfOFxb{@@^yC(N z2a@vV9-(L?hm_I-z^rGvJj(jcN0*QBim@IJ4)Y_S{}#$3@F%bH6_<0YM2IA``k$>S zNrMm%TN+>&sdr9!S1(RDz!^EZ3Z>@&m((C4iMT3R5|zD*k7BD_`q&<~!p4_j6k$h+ zNn#^tBWZw(UWQLA_fB{b1`wW2l0qCNrgP{UVZy%Kep)$0SmJEVJVY~uV0^c9)%pw- zZG?*aI9FTNw5w_2pl0TuxF@QCPProEATdc}vRZ>B)_fU5PNTvVRihH-p?6EI9c zrea>2QL`)*UFSWj>lvV(YBefU*sofB!OyWMcy1j2eSpPS<+VLaonS`K{XZ|9Ovs`Z?FIXKF*R@Ikk)L`1D)$L}vHU6=R?@htU zjNf=4D`){Bkm7#(__%U?^YPZMTo*-PS)IQrxLlQbp0)=K8#-{cxv{{ve`!ro*Fju! zj*NTy>#`;M2!eeFoV~c`lDHlh2Z}U6ah?~sZ)jy3H;DR65B4t$>jzqg{v?gKbhy#R zN={cOK61~xdZ*xzE`h`KK8b`lP=mxBf%({gOy>bh{xcF`4hJqH24et4!QSkDF$t$zzK8XTx5a3o zqJtYnmT6E9;p+7>N$oxk?8sw9+}`$?8+VVzo9vA_afckU^_GHNlO6E1>#H9$bbJ%o z^3KMtqqgKL-70KD;!a#`OJV;pSMnKr4Gbth`W6vMV5<(rJvOL!Cs5TzTwc>Wu}X&Mf~Py zM;a8i+p^yl4tyTn;KZzUa*|kC5y>w<4tL+F{C3wgeikQyy=v^5ulaXXt&E!XYAW0< zKXmw+?btS@Ajdg&|LBe&SS-|45XeXbN-rC`*f4I;yt4Dw1)bWNaZRL(oS>?qJU`OA z*^21Fi#UMe#|ERGef>B^bY*i7uBC^i5P>v~?i`iM9-r``@Y*aBNdJDMMB&A7kc853 zT!SaSj|84l0{JT3@{$S#r8ebqGliJdN~Fz|m~<`_yn=~^mRVbhb5=lk>B1jk zh*~%_@yS2P%V$P&#tfyN@bG1k96hU18H$)Zb`#TgI&$J`PF8aIlu~dxU>3Nqjy7k` z*Q09Aj@EzOD;vewXs1X$7eNUG6ZS92jqY8olmB)@(!|2rge8X`Qf@;SN8F;<=CK)o z3ArT)_{C;iZFHvvb^F>BwDfPSJP0sO&-WKjz>#GU)}CK7swJ3J9S1G#6d7v;>oY)PBBd|M(}v3cJo`ws^%<*VQ%y#gTOdmd@bya+Dw zWUKs${4oX>T)69&d{mt*g$W#Sm&wZaoh=%<66Bj2~sW(8}+;Ghzo%Eil^lD?PNI z`-4x*!AKVNJEhRjTzZVSC?KF8GV}acd`^BXEAZP6cy`GUjpR`lce5D)7jXzX$Wvif zUlTI0u_VT*9n(9(q+yhS5R)h5Pz{>oAs`0lWfvMm4^~TE^Ql3p{&aD<;LG!3W$;`3 zIK=GZBJ3_4fBd@@Q`*J8&+D3jShi;NX&-w^cmVN$-_S383?a*)@PF$`-rWQUbCa>{ z|H8h?(K2nZU3vat+p~f>T}szky$~H1w5x*WX5c;_jXBFjC_@?V*deJL( zdaI0d4ddmR*sFL|DGUJ>&HLsm(OqzsEdUx$b=sn9N%8~AU~t;p$!UCfe5)YP5B}bs zDVo}h{a5rLLxklN)}$EDuz!c`70b-C<|r(JS0M&XO`up#WGtehBt~@b;e{qhwv3IQ z=xIa?{^Wy)l1@5;XA7*?j!&FafcZ=0m$8$;4cJ< zlyGx&tOM~rmF+D{)*g%ik=YHhpNyv+(4EWT?=!l*hp+;1LoT%@o8e3SLJelDsv2D8 zVB1Lj+Uc@6duD1wiPDF((z`j$XdGo z^!|)+)$g0GHQ`8QsvTc|l*IEp+NPC0%$x68eQjjC)^xD1wMu@S={m)X7_DdWAQA{d z6~wT;^S8r^sue-GHC|;ZkE3r~yN7d6~D=fm*5|B&;T9`pC^?ARytM*KHq>sV!~b$!|;%>Oho$0`GsR0h-xx(+mu zLq!~${`{s2Z-%7)pT$Y?#UyOG;e2p>c+OGt>WlzF&(wS(p>r*lsSn8IFOtbrq21Xa<9XUQ)7LLn~uHMsfgS9 zWV#svfMiSWiqm~jFdwQxHGl|{#@r>EoVS)NGI^Cw}#ri63kYPP(eq@gOu33g^h4t#> znj|vBeHYSvgyvMzzumA@P%I{J>Wx48Dd(^dJP%jHcisXeGauA3d#VrGsI92E*Pak$ zEGke%_cY(U%>zXS3fr0B4SIqGU~&$PCm`E{&mWIE)xe$y+MQTK3F8o%j8RC=0h}{1 zv$AArP!}rl-5RRc!H3er-{b0X1#LB{|NNGbA4G*c6^Q3+hB6Cp)AHGpMq49C?sWAF zMDrz0F5##aAD}2vmlCbnq*Gz)cPHZyG{(L9^Sw54Gl(wxRh zfn=7bYG}!JWy=^R7%Q!Mq9XrJvp+tN*bGOE&myZP(3|g`%)y4cPCVlK;Y^im5OeH5INpN1r<}so zA#!5JhnkpmcRgEW+=_KNACn+0?!!x9PRvQej?=iW`Jw&n)ulM=JZ|(I9GL#Bezp75YIMv_XmETHHypZh`+xoE_IImZzDGYPiBV zPLhXdtLDuh^_r0p5nu2~V&#>cPNNnY(Q;M)Brk4V=>b)wg;>}5Gofhq@qn!!P zv4Np1U${kqkj+aV%P+L|<^OLi(aAPXG?TW|#r(VkTLqaz1&~AK1t>PD?ZiA?MBu|> z$0!cg`9R5(?=o#GjL?i1U0tY_{frkUj^$y7)K~{At7|~8xNKx-%ZeUhT5m@pQ!NG^ ze%XdL`hbBLbGU8yT@qU@PR+VqUGQjg#Ay^HP`!8+Q#ZU(&yw#Ws}@v`-gZB$u9dT? zk~bhDi8-^qo}3tli_i0c0Fx`D2snHTpREIO%jzMq{I z((`YDh86I?9avi>?XeME{5M9?IPh!^z~4TaQ}{iJYdjrZ3hDtM1 ze7iK80E*Ug6aE~*iSq~_;|bnXbZpHQVxB+T%rY_@isFcIWgD~eTPQZCLtrf-^ggknD1RPU!=okIFYY$7!X>lM zmGBbPe7_H}drJBHFvLpEnWyB6(1Z5S6*##qkuXJOIzw6O_HtP>+>f9%$pC)1eNf0Su^G2q%?YHoZZ34_T&k_%lcr=eF zu`Bl4T&BD(thb!8dJ$G}p9{Jq(69M#FSgFh0({E06|r$cPifAsoBU4!Hm$itlunZY zg0Kjgs&zY<>r~1EiE9o8xH*otK96RY8s3hXld?a+B zvTa$$QB&8vZSW$=$jk@-xH;sWG&FY?>*c?#t)6W1`a7=0c^gftX4-r+qS!|%1#dUv;mc}>@ht!}TZ}jQA8mSMz@MbH&*%V9KS~Kl zIal%qu%kQo(1+Y`rO1@M=69#hlFDp5o3A9O_r2X$#xbqRW7O^eS@bVNx=sUey%CsW zWmsH@9!M*k=S93_lg7)3%54!`_eC74A4)$BsHbEtb(pA2+;>TDP}d+eInw+v;aGgg z;%N@ABWL{)nrUzQ)y6%cN@W3M-$1|K1C$&dv5PyGdkY#V*ksZ(9x=~>O#t)HtNB8Q zN2=@Hp6@}Mr)=C|9u9Z5HAZ7oSMu)#@rO}?qraIKrfqb6Gut^^)sF^%BXQGE1?y3- znm&1Rvm=E6fzhu6(1$a&0=W}_a523|vuCVNfl`|drDuTHZVo#{&my&GX6|Llib{r4O_>lB3t zrGWtBiL6yV7fB!6-$fvRBDx~N<3O6ieqooBK@wv1`7W_g__wD}My>(7p zyy6Ehn_Y}VsbWqUj7Z3JlfrmZS_C2yD$Lmp?gfpVqX}YdcDw>CUcnKoe^Wn3Ny?em zN|p{ssL{R5FP#*=Cc#9P4GPFPp~Een;G_jQ;3D=fPb| zF0#~*hw)JLFD>0Z*j@EjzjGxN9Kh;f{s(MUU8Ll#|NdBdV)o+G4q4toA=}@@Jvc|2 z*Q)TqZ_pv4Lc^JkO`&ZGehm72mBQ87v1m}Agf$cQSic}AF&wxibuufzuV)6p&@%T`gdZ2B}{?ii@ci~ zj)*U5185rLvTm!W5h_lVo`B+lODyrp(Q{q5e<(SktXLO2()&5%Vq7bEA;F06LxmK~ z0$SeKn{3%RK0`++@Ic~AnIR;T?1-@!2!=hb2cU#^WCUQ*1n zL6e2d99dbpK&WwSCR3`hvawF7>4{P*wOOL`sxcfM=hE znSwLvZVi*;PRlAz@-LLaBYk%{-3QyQ;FLvajR-u@Q0 zGWiX@NwM(Y=}v*F`?#&-t@WT^v)DaS6zL{te-kcoejGqgXkPAfR+8I_wahxwKqf|m?;Coqnm$x1X-v%a&tF~Juj1QCrz9i z??$KUyA?@P1eC@1EK1DLi5DbSM}SUU6)+Hbpy`clC&RZGp8X>`PxsIN5e(1X`D$1EA}T;;Mdqtsn?RtIny8cFbxX3?%2#3QByS| zY|Fjp|NSK9?p!sm!wwzX9@muw80d9!iaZE)fSE}Rk;O_x&h4T+7vUS9)32ffh850n=|?$fy5E$R3`&?^QEw-nYLL>>FDF zu`M}j9E^mjmZHZxO?}oHGn91682-_b>E}*{-B&y&2f)#TXIR#$1*v77g!?vn5tBlX znZ4t#g^lndwwSzs=|Py`obh^(bhrWGqey&fjr`$Eyx@wjJ)U*x+q%eGT-S&(HJOF@ zi(9o~bO5=Jk+|17>4_2Xmx2qi7I~(t@7B0}KU{caW_snLumne-m;iR{CQT#sYX%4s zlQf|2RW0QSkb|jEkQ4%>YiIu=pR+y#59?daGo9wWLXBU5riaEZzGfOt!tDtB&x~gu z8fE_jmNxPiH`()bMNB(dv$xBU^{B=|w~D#<(L@&f=vb=DSnX1bMwG==WcHfdh-CPs zL%6x!JQB2|5@ zpL()Hu6He_qLlGC{jbycm21RCzvpmcp&s2W;KG@g zju8)D4DIcuJd6a=k{4T7&DI3hWEUW|gWU$TxJD<~bXIp?U}DD-A?`omY3a8M;VF3W zZDnV$pQ7Wk5tDZ6cZl%$J4d#!C=c{Nf+ZF=@dmx-X^@GA0|yTVBt7S#j;bDG-L;Vp z6fHWuh3GOiZ+H7(@(q2Z4*7tUT<>@F5j|t%sS+1`nbbunB2}rD4IJxe^4xY_bvw;D zlPl|gw^qfPmXy8Q(}0S&2X;ODtq>*&LKAccKraQ?B_43AG6xjxz-=M~MiPQd%>5gC zsC1aEgq#pb@9Zv=qlA$PTp?gUm3!zW$*71lWe=F>;c>Z*7F;fJZpZ z&gj?FITdI~^vX+_2dL{&nP|s#pOQ_~!K7)=XiTf#*t!?}|R1MV7h%=zb82U-Dzfu!fWs_? zZ;L*OnCp+f5LvamkUYXq=o?pz30ONYMoO4lNd@Nor`B5-!I71-z{h`p^N4R~fC_9x zosLr{b7?Wfb*T2@LK9p6(HEJo^8|KlyL({^0!D}gTgv8MMMo6_2f(b4oM&PT02rTZJtdK*~@A5)K z*WKQ+%1~tV@4XQex^=5< zU^VvFW+O-FR}<*JR#7!B{9;xyFWTjfUUH!+lr|7$7BexkM7IpEB75PW$`AKdjvl8k zo1vVwg)jXaL0QH}^AQ14!>fsg7ix6HT^n55e(sDE%$8U1g@c&WbMdgKOT57~=xSZp zLdWIFwS`D}R_n5y!_iEz8#A5v8_D6-k(!lwNgD)Dcrmu$d^pEw0yO}zWCZiD7#17e zj~_k5zUFq^U~raOOh@StNti=xm3|!@1>q6ed|@ciT$!q>?B@jb8oIja9|yM+pBc>7 z9k|y%@^Xq6u*T92Q0$`LKgwI7Dmo#m>gu-inc!A_IF%;PrP!5oRpuGV!BY z44_p$lQxk(GwcdI2W}K^yl;<+zqDYpWg)tIa*wa+gl0NIOYc_q&8pjVWW1)4qce23 zc=ny{fTACF)QKyq({Em@XA8D;x@n3ibwzn&TJ$d}o^i>s_gaC`DmVTv$op-90#r0RPq2KlqPP4R05Bb;#MhBPqQ$GmYSU>VnrMuyx(JqA+(PY{r0apx?B&~txc z`>ZL7(6pno!ZTmOl2CVzGFQ#^Xb~skJ*16&k0F5=&mPu&gwrYBLI`RTXn%_h` zLIpu8s?FP&Y6F7IKAA9oc-?Uxq7CjU@RLhXYKK1RO0 z#&tUu&FDB>=pD=UkmF87zUmB5H6pgpEeW+;%71 z=%b5N)<$ao%v8d6AceR1t$}->9yiZzOx`yvZ5Rg(TyMq<#mF&ic0MJ?PU84go^B!# z=W+uDaA8`e55;_Mvj8L@+Lp)8C-?0=mR|AN4Kpz)8u@LYqvE|-X- zN(+X_pnso}e%r6pVq|*=a<}95NS4ul=ow})A{<3H0xF=MClqZqBn`EIpXq$0j_?J^ zemjAr5Hbd1+jkD&p#u!Vmm;3omayorlpI87;nR;N{!)I5+`AFTOk4aj^emlXG$6hK ze}zTf`l4teS--P52~t4jZ~v4YXfwSkZ%XP}LWzaspRaq_T2%d5BkY)1H+J8oUF)oI zGS+B%ux8={v$sM@ub-%rro%j9AjgFs=E?StH=e-*rtasXD5hwH33qn+Nv^CX&{L1bS; z&XNtcHEC`^VCQNxKGN|r=z1Ca4GY_&1nc^3X@dC2%9;?|SE^Me#fJZ7|1TmR_P?bZ z>q3iRvIkpM80*2O%50?>A-(=Zr83rITP*_%xxmnhALuJgkwG9dxcrMPv%G}xGjTGe zLPp!Wt^_pw-zr~23I3Fg*7&x59H+^~*+qrY@5MZ69XVkMjyQ66tTTk%*FeSDvJ z9X-L(E=EM^?4R)I@ta?uDCP``hG`Ywp9k6l1M7I%(d_&v(tm{m$1j}{#-?Moe%8c> zNOIA%&ms1I!{GwS*+B~9SQlfVCT-V!seI2)#K3;URl*UG#C%ZI%F<5mGEIu2iX3}f zX8<-*00$-!Fj(n#g0gWQHEho_!C5-`>i{e2rJGq7<#k#|%vho9?oLW5YM3(hIVNiHTQ= zW=6HF?Qu62n}spB#qd-==jYyH|KbGg0bCz*`;{Gu`9$|zzw%%<4wM!A)`?OO+!IUT z#cS{YOaQ*ij&gxCHQ~AU&@t|fWW43S_&bnKH6#dxK|S;50#qGSWH4Z3t!-8iyilI3 zWz!w*fwcNH!d!R_!U!Lne=;Oc*xyiNk$;}f;hIqk635mhct0g#c`x33h-4Y|AHV)-89-2Lx=bTzjjmC**{kPWWD+q< zHDkxC2BwM5>CeK52ekxW264`jlOmf4)Y_^3JCb^vDCr-Cfll!ybi0#B6KQSRa^) z3Mc9Jq>o7{l?f24b;KYs`fN5>e8-KwWA{*{QuI>j(xCqLm-Nz9$*yW~FjXc2zM&tN~#51!9c^>B3mn) z)6wp4sk1kHKz<3MP^wE)lCrXVztxlq?j2t& zJY6qd+}^k>D?bN3GjgyX#G(X*zosU_lhER|_kjdsp9rW+X1wtYZJsoI^$5b;nPKht zb%0O_MZ@e`z^Uv=$bb~BHrE1jdbIC<;r@h4drkTES+u1?y>lr%!D+R`_KZam`$M2J z`Av;L3WDh(NL@LvlXkaCX^fjJhO7J0*f%X)5i#=GD7RD_12>RU`E?B?ISUiw z@NhHq^<`|9X`(I(cLT~-YLk#z9UR8R8+1Vc%a0k`$yd6XwG|FieoiN!J7)XL+X)$Z zFFvl|($u{Z+8=(Hxb9rFm*#oH=W~v!{{GcoVdH;8f)?NjlKcIxf+-W^DmfwPlWtc@ zO3Wb;-aym_R*_@B|7kuZJ4ws61c`og6XwzwQv7mndS|Tu*@+jd9Qc?XfH6%b8u_+s z(NG@5WZa*PtQW+z-uLm{v+=PFq)S{vQQF6zWqNP4b6#7iFg$BSaT&VE|2y~2O2;cC ztcxFuYtRuPdEQe5=sm|_Q+S?LNg!c?kE>x+!3VyF*&00iKeCE`_6-E_}S!O^}f!Uajkh2nxnrh#QkJI?4HkqxNJ$5Dy|OyaH) zbS4_pm%m_HZX0V{162G|-+T}#E5b{WK}lN+j>6Gnn*6#G6|YePT`Zg@)&s~OPJgy- zX8cRS|7Y>!1W(bA+pnh3du2X=PU#Vo0%rM|0>X1Itt}?iAYVFtU6znUF|>nSxH>(V z){LSS-+ZfSEoX=6Hc-O9d!aUZ;KA=JoY~RFsdC0dPpF_HVT85z){-ZGXQk zJiFXp5(eRkxMM5?Tcr+}14px45<1pQtgeckNvsE=D(2(-&KpmuQ#Mt+g%~IrIhRK5 z5A0VlItgx53Otje3}#pZy{8MQ{6^p7gLFRtI}+)j-JXzC&&y51*$D4o;)XF3^Mn*P zo24M1KVx7{(3`65?yu6(RqIlxS(n3X?krVQ8Wj&v9p9_`>Lc(~UzFfvtyH5S9)?=t zl%?^I%bC;x6h{I1hQ5o)a^q{<+3&SPcRB55zwD!btwvFCYz=(L2a8%jsi#*&>HRC0 z385(T$?07{T7yjENyy2sS(Vh$G2F`ZF@q}T>?DJc+8`Gc;8(@*AS}M-UMt82wk9s& z_$b7#42^3VGZeVUd&$#3a#7MXYyfWqK@WR#ZJ$;^9up* zQiTOuK25x(MiDm4&|iuSx3lz^x25j*uhg`fZ>OHamnZ-y?Tc#=H1T|U>4+)*N!lw#_?Ot>jg3S%a8zY*khFn#q;QQuKf^w zKAmw&?H6JIL*uGNV+ygJvY#5b1%IMp%UcOsAG z8=+|>?_f}cT2=(BB&+PRIDsI)S=0w_7r#ju%9JG){KGT#DpID}84)m?rq9_%tfZv{ zlgPZKA1=Uh35rRs+6T3&z}e4tcaDV3ltR^Lxby)+-*+5{%?eW?y=RgNgp4S9R3JOS zmcB~-S>9CO)L4MeA+6M(Md#s)?m`cx&slJ~Zuf=GVtdEgF`5gX;U5y6RWXG?m7`($ ziK!XecqRjT#&LZacp?z?f?<+d@=y)SFdxN-uXTA3u-Gsd)4Yf6OPs>+w~=WRZ+5#G z_E#zqo!0H7B9RaJb!<&#RTFX|tGDL#oI#+mwC2 zH#Si+))D>4>iTGD7}5t=-o?^u+N+Zx1u45ok@P_GmB(zrAY%t!)Qyl|@=^H(x9>bb zBQvJE)c4C)UC?YKh>3`JXR=}nw-03IiMzxfc$<3)~&z7^(i+j zC((`OY!~?G=4Kxsq*1wWDYSIprUpnV)tL%5a*eg#nQK-49bjd35)KPo}YM; zLc|eVl9682Y08P_0ITV^oc(E=s+j;$7$~W(MM1evTgri@2AZ0IVCgJ0x54I>w_0T* zW2|AQ7rV)VCF|5FYEAk%H=KknZmqgd$Yx07`7N=q8XpEnnAI)KFV}RWBh? z|B z3;0uo&VhnGOm085cHx6qL=`7`;33NwNh8B`x8O-6C}KLuhydcpijhD1l{LY+L+$k+wGQBzkQ_B*Fr9dJShw4$!&8GUbK$CUZe8=9ONN2ei=83w3YC zqy+OI-DG%Hn^Bnh08h%02owSQB~riT>+}iAt=fCWY8uDf*m?2vsbCEFbXgOqrnXGH zRkZ-!2M!)M+U_Vjv_|$mg4NDB6SqXyQBsCy;0D<7;O558Kx;kRZUE-ETptv9dydwF zN$|FQ)t_GJl>DTe!^Ewg(~8Jye}P8S|F|0H-Bz%lE4UH?#lt?{lig-_{piSbs;b|< zutACUhE(Kk^6BIR^yx^bVI`!}Dbxy($-UNC_XR^V0 z`B<%%AS<{w4x;C4rjRnFhi?cnr;1Y{=^g9mMBk-IK~XqWmzwIQrunmhr~58*7q7ip zH~6n#&2fiVT7X0LIRcU93bu+jY7fpyJNvy&7YOHg3n16K1qYY9f?KbJ46?9vA7^Kq zB|k42Y!@gH5C_|b_CFM+h&hS}3T+%A;WaGEI1)aKmtT(GOvoC2=(LS~YQ7eo zTAt~HTC`4%ve9?m#mME}5iQ%2B1Z8X!SCJqO}QF@0Nt z@3X4Ce9vcTQhcJI;QIaZKhAPKhh6-RedZRf&?Lq%%y~7>b5Dq`9EFsDX>SgEW+Tsy z2#E{VyT}w2{HAIgA~K0QP}Yu;(D8OQW_6w29l_ekwc_v(yg(eE9qZDusL~DQeY<+% z%O<2>2~>0+VMut&UNpRA{j&3VKDsnqu7klfp!!4{H}LZtpc2g*w0lAb{a@~V_$)pi zoNQPAZurOpWqCmXS8`KdDeoW?Al>2Jr~rk;!9Ytq+{{m0d8!UX?xNu1VUOkP}#$q^jXU} zH-vv&F-h>J2z3sI+l;|3xD1+S3`Bq+V-e~~Goe(UliT?@zxGBRX^~b{Muiq5UT+dQ zxL|j&Tfz5R;Dy3tb9kcy5}%%7@-o-4*B=pcldlDnb)ryZqU{``zEjVMr52w&*Ey0jel6OwgB|9BIN6;#UvW)gM8evU`Am;$(q=QJKR9ZF9>NP}_sn?r z8^b%vsw&`YKlKTEX80o&$VXq^ZV^^6EG$~)Pm%(XHP#Vv+#I4%FB+IoiopU6^%IM( z0N-kr6lkVvTZNYFsg)gfD2b}}9k$6zd*vt8psGT;gDsT8N)N~wTSi#zPm&)p!{7h+BzH{j zHa^;(MND8awIw5r$sE&=E3Jj)6N`_uqlOgQ3pwsPWb#|jTR>yGS#s=i4)*IlYI%xN zr62B}PO%NL1z~C~_tJhk>6zp1lhaiuzAIOSrTYHM%3*eM@@1WXu)FrT{H(QEx5h! zq4am?u8;}k4*d*bxP;i2hrGtkqlDDHn2SxS?3hS%aY8NTdZa=A3ln6I5sOS7qDJngcur>T7=BII8?4)#M2O6W3bblROD8 z{Qu1nIajhQxdDJf>&j};Y8mQ$Ri-zU{0vBcW1k%EFR1MVRug;OiQ&+jD`3u%Gzq~t z(cD2vpG#!GKktKqkiH)%)@{x>Z#0K(E$CU`Pux!+sdamidHS^*@Lk>BnTht2nlipO zqgZUWGlE}WjeF5f-JKqH&HD@(@1bF4^zXaZ4B$LC2pg2>u6s_<@88Xmgdt+~1A)va zF`S3P7()F9=l#kt?4&5FKD0oj#jtwmYEMezs~!Uo!BsD8GIVr?k7k$;*4P98&S<78 zPA1O1Kc%CSn=f=G33>{?qF;x~%a?F4 zUau3%*=-C(vo}Pz;E)Utg|J0K&|3}hRARFD`EyTKv3R$r*FapDuXobO(E&XSE4~`w z=tChNrHchg&tTg!Q$vCfx0bG z+B2bY6?+W&vQlAOmpmV4)nL)Z$90ttj4pwY_XG#sd(hs8_b!ZW^!oG7GRdf<{F zB3=mY3{DXr+iO^5t(cM&W~g(y&jI?S0PDstT}(?4oIK3cFWv3V9LW@;KDW>r7=3fl`PKWCZ&^?Js&i05Q=2Xg z5Np_C^la5PW~P_sqUX6F(KfpX*lgPL$!DUR<;{IgrEy}2U1w8vHhOR?vgjW{U!Dlq z{n7xkD1^@PmDKGCopmmBX!1%QVjCc>2qq-1`IaU|43MZhU2OfPX{oj0-J3ky@H)BkXpge6h{l{VsNswEb)i% zOSBA!3E&$HV{ppLqHcmfBF?oxl*bQ#D<7nvV#_3{&41(xP&UX5dtMwqq)!K21$Yf% zF#($q81ya@WmQli&yewENwne9RncPuyASrIncUAJSQmc5^+ip9K@iRnlcnkex$eC( zX#UAjk-oDI%fEteDVc$7nGQM8IT`M-c6kvfh{*4sATQjpf&Q2lr-zLMhV##vQPNd; z17rP#vBig9Ib0sJ zo#CKIb^)wVmuTbLR|{G6;ig3>mfpQ5&yJ!b1*Fw^6I*Ilghdj~P`F4xTA?g&?S387 z!6q(i?Kz0ePsEc4rmd@a!_S7kXHbXx(B;MWl_1r*Geu9A3e;kj>UFZq3FjXQ;p?2- z!n795lW+WOp8_yC#)<&@{uhs)A1<<8>ac3o>m93h=FGt!72*PKlV#7mH;SETU$F># zXEu&Kie(*~{8EAKB}U`|LM^#eM8VQrGUc*F#Q7?3A_kPwNHfyFB-RA}A2ZP#L z)c;?y-K13!DV_$O{jY-d6C+(gx2`)2fPsc}W^NxOwZi8_AwEXWOpnkzV!CyAlr zyDPHlb6Rs0P{qq?d86mJosR!e1%Cc)c? zZNm?n_~bgGJ^!|^H0`X@pTrGU+)>4LRZV!G$nX6RM+IyX+ZSa!ga!Js2Cr)HwhG%O z;ceG~wGp7J@Cog_xHh+aW^qHFe#~sfp$50GiWGR+lPtK3q5jnnP4B#DF|0fd;TaGt z$7%c-BOf()l>@2?A~+WbtMIjM(9_Ip@U!t?dp-B3F4sVbY?X)tx_FkgOM=}DeGB&; ziq}?%muSNEDKq9TE7^y~IU%~|$Vkyb68?vQ3``VNjcxC!4oeq{%QQRk!YtV@(|7|wtSlp&2?s(DWZ z0t|b27z7XCM{m)zXoD&T> zHqet8IlA}hjEU7;4b>r&MJYrszeBuFd4@tfx576sI^3(wXXnBy5TA3<{veH*Yc3o* zWC^Hg-M%TT6;(Y0n*ubi37dVRUBfZq%W2_r{L%Vi91%i7jsCUYJ7}|($ps1NO&18~ za4-R463}Ndx|<++hfI^7nYBJtmIMq;9yth35*EOzx4Od>#LJg#Jm$T##F<_LWiB1j z#@U;P|6RoWZ|8s`=qV#C2^I^`11#qzEiRXZK*zi@BonD~dHv0*yg@d+1{egC_|8Cr z^;_AqSW@?rzCdjI`uwL3ASZnAt`AEn3<>barhSU%kVSV^dp&Z3RKw=e?YFBxiDuHr zqg1S`;@a5!{jFpZH@(BZSLyR{oh!%xue-?&OI;`ohKXLf>N8c@Z9zOb$G5*oir9^H z`e^T6q;Uo3^ zdQrQN2~ABed(Vwl6qV(!prLnF;Gqdto>2wa%bvwyO_EhrnL}#VDQE((6gmMeGIEFp`xw*9=4DC306FCq5v#|jbm9N zAj{=Fwq=PGmwmo*D=Lj-$uh>Q+#b{;8)&jz)6D~%XZIZB0cH;tO(W!}*AM8h=CGA6 zifeY|s9q{b639ZE!2tpiDm#W&1b~l0`JD1jT7n;lG(yS`hi`JfHgtSy>}dM}al{q_ zaHb$k@;VEmn}+7QUt&P?C7~wS-N5%>XXL@vE=MezcPfV7r8%wO+tkw14%zCcK?|)= zJp<~oY4yZVDjABmPr~-Z3An?PU+On7-Md@RsffwoiqA4d&9EtZ6VIJ4mtdM~$R9dC zBLB^g*2gej>}vc`==S@A+ls8oW#N@GCw62cc8>v=*fv6$!ZaKD508VQo#))E^0zU z^bA0!>Nsi|d84gR{%K7+DtL!FlqbBI6rMX~EvY{|n@X_n&3VjE9y0dYYnb)>Z6WL4 zn&^X30E@AL%Z{SU{xJi_`}}t4W-><}Z2%P}kc(wri#cGnKyXx@kZ7QZw@_)v{9n>f8CP%jD13--D*dn#s@5djg3F3H3 zHTaOPX+I_Iy+7n%I4UhM6;TXMmLWHc^(~ZLz2Dz!-*=QO~a;*DV z4@MMt%@^fIg1g27XBQ3RXBygwY1_Gc%@_(GLy(gbPV%{Rh>iU&MGo5od`qf1agLMr zrK?+s`!)FO{unofUn~(`EJ~KDW@BcU5JCsQcw2*|*cJ>KyzVnmfE%Wh`v9wLhdSk& zs}R!;9{fz%Z1I$IWYGElO*kF4}tc|WbvDbn&PbvjyRS2eJRzvUk# z{1h( z&mIo^L_>6AGDII_)}YiOFCMvS?{(|>@Btl#$+^E)&KDYc;GxG>%vPr=_qW!b=eo)CCLJnU?i~J_UzI6 ziJ(t87FF~3pw-33tKFkP9>Ut86#i1-g#cG;@j(emYUi)H87EHlRf|mpJv*xe{h{H% zedh<`(bj{=KTe*Pb&}^{Gs{S0E({(h53OIiWB&DbB(X?v>zKN0Ujk zY%Z@y5quO9pWf)Hj(UijwA!~B*tvTrfO-|(D7Dx|&0gJSa2{I)8qc59Dc&1~@dRSc z)*E<^{zOM@7)17R+v<(ZB`uN^84UnV%yfqCF?>W9uf4tg==-zzRYvcba*^A{f!k?4 zMFrWCYJ{MllB5@Cmnev80T zr!enRmEzfTW6=XAiMRDhex_MFOUD%&Zm*~(vYzS@gqHvKX^A5<{zAQPQ4YL&NXGrz z=yo8`QtQqXjmHIv3sQHl5L^?2--75w=jKLyDK@gd!qlM2V|>@QUpV|p7MeRxf?i8T z(asHz6C1Y!2i1Z@F5hx-6`m_=MF(2~bM*WB*|?vao4X0TQ7_naU1r4hgsDDzW^56B z|LqNSI0Y*CTxjoZ@TrAAPuNDC7=*)-a`pfM{Ius~cKtAYC>ULib4lR_v3m*@Su$_( z443|y4=L7C;SxcVcI_u$X1|bORlK_x0-7i(RO!%L*8_T)E#6hx%T~7V@@vICQa#zm z-ow8&jx?-&mi3xFGuA#(JJUu_5L?O(wBplY2w82djxUeM`D5%J;%55x3Gq?wy6T?@< zOtTavO$X_eE1x?^KX&LY6?Y%d)9h8nkWIeieCF5iCaC-|aF#HPyK}*s-XiBe{bV zfQP8kH-Gqn_MlK1u9&v4Mz~q_5h8B(N3kc`)d%8nz`P+Ndhs+NE+52J$q*P0#Qilf zw-GO6aSsZOw$QjPK@HA_VXz}`y)0Y!d+SW)Fm1O*SmnWQgCpZw25QFB@>8;S2@V1J zGv!S4CZb^u5_0E!6fY|^2FO5Id>wre+2C%(zNn29+I*l9$8g|je;^6h!CtsEc884u z0_+Rk#L0~uCGg=~-k&3oT@cyPf~4L~jHWhAY|l8~@3w_gR8?-#RXI!T-avTCoeh`S z4Fo5qtVQ){a3%dGJXKKsr@|28G9ou+Ghu6ptsCZ18Nl4UVX{@Soxq!P_B7=zXlMHw z{s=tTh%JH4V&6Pt>D=;=pl^pfnnP9qA0cE28G5e0_!1$@eOP);qqTjc!wtLB5KwqVCJ^OaJO61G z$J{5oyg{YhNVT2?)^7{5#!dJs=_G-51`=VWMhciP9Zyy{EH;fkNrl$(y&nWR)-FWu zx*-heZg+UB;?hj^I-tQQ40Tf&uJ*jEUATQr>&5#u_KD3~H&gDIlD98u#j8v{%M68M z`xN)dX}59W`{A4H?zM{Xld$UqafT8q2Euz1(1u26cgll7BzPI$ObF1cdOr~dZ>uw& z!7$y_V%84Ihzs`7rOEUfO}(n6jDC5|fDl{&9E#$bfWI^#!j}CQs479_G z%hhiN8Dp-JjnR{sp*)emzfZCZWGWC40CYJbM^s95Yf#SF^6RcKh#**yDig8zhNbW@6|Im3S0U?$uSqFs>nJ&Fa zDzGje--Q=7$GFLz8gQf?@3U5SYaV@~Nx82i0IWTG^yywKaai2L-GIO1O=}ftWltkR zW7u_qpJXx#a@;7o#R5_Vri@e6-dsBx4{e%ci8!+R>w$K75EpP4G!JuFjMM_EHs4ku zcu&gnNvW%T)+4uIXDwSgsOKuTzlcI6=?K>D$s}`;D@S1n0wqkHnKW?4$OYPh4L(wj zeheWP9BB53j}rpWPSzL2S6tTtd#gUdh?(d?Y5D6Ak#75v!vLk}+qy`3m0x#y((wi{ z9Q=?`$XtM_8Pf5qXQA?hHI_A<(uuwtI#%e|kMr}qVrZ|+ zG$k!lNc={Sr8yF5tGue28V85m{B=!6W7xvV!>?if=ml213HaT3GV5FgczY7)F@8 z)onq;kUaO~Z0kl#ZKrum1N|Cb-?H5Q@{g)P{7BB0=ORe=yG0^iYO@1MSXDeIlkEi# zO;tx_PTVDOza@Rf!Ln`wbVcP-y~8rVvgkVCWWH}}yrQ4Cts2LU8O{<1a$lTbUkS1n zPi=b)i0!SMD5$bNvwNDoN;xKCRJ=OIU=nZ87tm$$6ZsMe*%zy<7VYHiX~Te&+nYt{4Wa7=!4s-!Zha{*W~+Uq}(Mu$X97Gj-`jgekd_fVwP6!+)A^ zuQ%R3@YT=7+`9_8xJ|i|2Y#nDYouD#!P`Jo0e$hfLX*F()1R^axGHrSb~8u&RM`hm z*p+;4Q^q{hL)0IW$TJ=_C<5-eP|OFE#cGs;sd9?JoU;$R9q%EDNbplIc%cgvKnvbW z5Q9-Bmyhr9Q+MJ88}f?gg!Sa3zf|g+P}_?)6Ca!+OdWvSBK%g$LpMdZskYHN%ZdLMRsqmeDkd_qp4HX_Gxv)LBCG?Eg? zSvj<4h6KD<>r=`m|H{8r12$%Ao*xkw{N5JGYnmJWZ4iM-f_~ps3*anUwk=IKKZOi02rHj@%<~<7JZBeXN zrmxECwg%|{noU%mZl41gyn}xa=+%w)SepH~MYx4fDFxHq!A1GZY>F;eT584}GTUyv z?+`|P1$U3DH#40-q|EdysC;+TRs8J3spk=Wj4 zhjq+bevKX^`l8tm!QSD+CD&_${UaJ@NSm71q`FCXiho$&T2oxPE)JGKpRZPcv*zR} zW0*hxkV6jr*>|}$pU}01F6C&FIzkUeE7BP)&Zf+4k}lz_^yL>65j?Si)5BDglVZLW znddXY7cVct;tXjRXRC_E#jy)PaCv!{)~Ctg@_dKe*JhPwBF2`SQL)XIy^>VB=GTOSCMN}5H`e55fA zz@wc&!596TU~5a|eZ#MHLh&kzf%XEvk~g=hm=y?D*#9(*ge}kR)WVX^4}{V!h1=%- z?0QhDR^!Toe4h%GmJBv{@X=^lE?Bvm`G1U zo|zNbNmK|ab$88@o{ST};UOMajrDP5Z#m@Cb{{mpGUi2uxY5=*3lwB;0a*ZR`l z)WKdZvm?5Dh(l9+R%xRI|0uNL5*7_?`@-9V`pbC3&Y6jmRh0lFB}8q|_s@0ud5arK zu=?bQ1Vocs(juN1h*TMuVI6Jrc@Lh{%G|EFO`Xuaba7TjsS&~o)&j?JK-i@a63Ao( z`v@H9YT}Zo@jz>j1XkyyB4&Cdx}CYEMX}?R8*f=ygz(EbWbD>2kdXpr;coH(G^-B( zTA_PtSCuYv5+8zuDB}XVLZ)1w^&olS#n7;WbNOvWwAI53$*pSW%uhlO{2|P{jDX$Y zIk*PzX!?3|)jQGjhh=?L|I0HBo$GSdwu;|6ATspYT8|UT0{|MAB7GP&7(sTOAaI#eY7Fm>h(!J@iR*~376}MI2X{j%5i}Ig&-2dHlj#mYX_me(%<|VaTuH8 zB9TCuMXDY(g0PVF84-DN4`QS9nlwO;CJOT{M8KFO$qX;FTU<`+HN%>Mt5ww4qI1j9RF)Pm=MM}X0qGT&L zNKd}}=^~T^o~*u{7~*v&9BUchJ^npCUq48|6D+w~9%cQ)yAu^ojc$re{`q*q+4Kl1 z`BSrgui#QK##elx?o6r!@}ir)yL0_UP4^k8myMPJqNbjHdwLuT6&HVN;A5iKIKnGU zLx5*^e^mF`MUsA-DU~I3a_{pU{C!7L^RI`-R{iZ4EGUWqnotLo>eYW^RV{H0H>S|3 zjKQto8LOi+<|i_V0{}gC|4$UQ(RWsfP!$(f|AdsDD>;r$jW?`s?ay-*xgr;;-KB{h zOBO?kwpv+SZC2&y9z|QM!#6=OrpZQpC>Wv8yb7fBgmq25dDi1$cOb4jNP}@sUCFaV9oB?y}i88chSg0{QMlFb9fNm-t zx?DJ9M`OOnQ{Z@m)3n)8A)jMzI1=Obaht?w;+K;OI$qYam}KAf5W3{5gMx!NXi-Wx zE~Z*KwS19rxq{4q(DD5!$g#Z6lN)p{!l$OfaerI$CsJ7wTA5JG?GX(>QkZ9S=;wA> zXupjMvUCh0t7viZ(`N-eh{-l#xy_B{=muE72g5hWSUE(aLSK4~JXz>@s?xGLsh3C{ zY)#PC5Zr(2v44>*y-(F);&S$lUvzVKfVH(zg^F$%PeZ((*Uy`!*w|M8Le^&2*AdsE zJ*#At3>W+I&-8ZM`EOF|74%}+GaSlZb$MB1Y;(QVVE_|oK=I?kFaS>xEJ$NiR*mc& zjCbN@5wAjI;(z1OTpNc_)p;g%z4yIl4!MupXH{Tw}iwq+hWqi z()1LX$$<+?BGt!U^K&}Q+cLzj(Kw!6$osX)_$xCkD+S-F&5H)Fz5c6nx5i<*wVp(c zIP~F$w<|Lx#17J*or_9q$_or}RI7h7_d6&ae%b$5Eb!R=#K1npMU7uR zsi_%m25K@06eprb0)^APkV-SSse^GrAyHay)I(bI z7oB*-3F<;fXQ>n!jI-~Pong~ zBjWUY=8TcLe^5jW5pwV%?D0fsVJ4?=up^lM4WgTW&oJyAU#Xcrp9$puXod*(gPn%1 zf8-&TuPJ+vP$!3sN>}T0#qlOG2GxC071<)qo>U`nx1|m)sMno9O>K0~rw=Y_JmkPG zGwfv3a7OG4X@#W}ma>2txKrI&nc_u~1s!lB%nu_b?)}VFwiX01W4Uwmw8f;d#4wyCY+hS+l*%SUXY_E`;$aIN=nVK zG3`R_z1JQ-ldvQkdEs42qor+0w?^jQ)Rq!yy~VhmPbKHObeRkKz?-hcta&u%{(H4G z^6s8%F_k&R5p0(igHh(vDASrvY!P=Z!h;&^hC0BOc6<4% zl+Sg!Uqyk3IRpv8LCgWMaYfDUQ2mfRfq*8`kuWX)Z-_oQlkhn`JpOo$V}BYCqSikm zaVQ`}PIhi}GW&*6_^2NleFWeC^?~RgF~svo!(^cy9381Uzy$t-?t#O5sL2;L>ee zjWk0ZT~Xif2FZ=z{s;hinqyh%w*^a(5PJXhI4Sx_*#5n^Ms%8(hk>!$6OvX~rn%Qf zdb#G(0L7;O22%cf+@C6w^lf8oIVpm3dNlF$n@^s;8TML@U1n+D*$LH687pH;pzPIR z09RHVYK7>qeuvKqxP27D;boa@tta)%WK^>6E_R=y_| z0T6&fVMUCGiAl-#)^u~x=D*RmIFS1{K;j8bwNr7noBYaB+EeIN{{87uW)_4tUHUBu zm0<+sk|pGTv=LHwqdZedYirlI{}S4OjQ-IkcUqyR{Sw@Wf2$G>*1lQmtYV29!*nC+ zfMbRq{;hu^3+<;^Dh8(h)W$vd-XwTql!XLJZAzYU^xaApB|9TXSvI_=*L*J@mf2}= zp)4`Ei*LT0HI-ncHv*t_VP_+Y7rCB5r!P>JBMh8znUu>gKm`#YJJsX{2snAU38V@D zu%4b`NhD-hbQYXa(RDsRPplrpwsV^Z&BHU-Q%fv@<4AF@#(`(Sq%f-Vb}n`N3IDw% zD4w?#Cjc696EH#bG{PR%({7q1PAp>;&82sX&Il(9F4ZI}Va?lu^I^v<3`Nzchi+9;=n zf8KR9*d*HD&YF*V(ZY({vC3yat%=#EhgrYA^9l@8XQ|Cm*F9B;ixx z7PBJt?x7ybpA>hyH@-~i5tmlQ{}Soh_}=AB@eKt}E=wHco*kk{-Yl{^J_QZD5sgz) z=GO!cvW4AI)*N|P8CQ_rWYA9GW!jpyT+KMPtS($^fBVCNe6VI2!^MA-DTKU(`9dHy z3v6z$54z$M8bSQm6qK2#m<;T@TSi#$k1LwB4LJ9ESu}%e3`wZvKf!&f$<9=W`JV0c zqnE2SGmNr>@wTCQPZBkzh*eK0w--l<{BF9zW4|x9rsN^BkWlyvLWsr;`N3@P@F|Mb z7|-3C3VziapfvlS#eu>4nq-2R}Y6<~N z!KuFW8<`6El4Ce;bwHCOjczcph&lmk0@mB2se|3Zu@BTy#V^vb@zL|--sjnqBL%g;2 zR%2ZGFA5SVO|52_W688`9S%eLbsCJqWGL^q23)}i*JcPAK;Y{_5dftp_qQ)?wj+mMX0^#D+( zj8aDNeX@~z6@I-&iSy{v^^ahPx?}41fhe`e*}de;qkb4Pw)Q~rL0Ci;4e(Kj2v7my z2Xy>t#APja+1q0OcIefaFVQsHgP!c4MlLOLAv+Ww_-Cqc5IX{i5s`QW+b*plx1$8} z>fAm6z!HFR!03tD8=&=?^BIcp!bF8mm?7xOL8B-yRBmG@(oi>=El~q?WbvxxKlSG8 zMV4WM19uUGK}}Yjf=_Ibxt}WU7T&;> zO4Ccxbcbj#u)?e1*8h0d|G0PeFSSEm47=L5Fdk@(@f=cHD>G$Q3KL zbAAu?+C--Mi8-Dt1618T?~Or@e-)NINnVK~dk;Y<%q_uMQOlBP#MwQ{-W6WjUV`Dy z4>sK}K<>~(Rkp%WN=tPJ!Oro9nnNoexcj16E*)2UcK84qI;8J`J!`E|Dt(Y+)Ef2H zA&|#Ux(tnKcMa%6zmy3#++KuHbbAkQ8%hpR+#7DA z$e{T+JIh~WHBLwrBdOc#-M5$=l~j?@R6EAkZc(*Dehl;IJ=>QQ7l%(LN*H1ORpZZu zK#VnB;Qd7X425*q)6*7}n8>esNhPl6Na`xCD|R!OT8>$5C(z}QQ( z{}B!~1Uavitix+{W9;{dq57-~>$zLn)MN#P(mC2;{?KF+F4sR}3|& zhF_XVyVR;FIlA526KyH9Gt0oR05A)QGzeyGey>E@H;!ni0NxO3(;1@CB+5x7Vtxza zEt~mf`NP_C1!}rROn=*Gw}x9JKyYyn%syxcm&itY$`CpY=(Cs6{(H(Ua0_zN!{#tFPJ+d#lm1z z$#*;OzCU@7z?=+od@V!Zhu6fRgT)4p#UFcu&)8vo)3OjIJL8z_i;{SCIir&#qVK~K zx{Rsx%;&{3kLQx-rhZ=VcNgdrd<_}5na^KUYT1#Zqg1%Oru(V2uLFuh`kwp@Xr$~hv>~i zQj$8Ky!Vm`IOcc4YlYv~e3$VYC24V`K0;@+$$6A6*sA4U@lsIE;7#W)uKl>7D(j&m3|?Wc#H<054X^waCjeNwNGFu zPZPyjGl|G8U@~HE1;0tb0LQ)FC8UWSQd0v1-gUvgy+z_Na=> zn};ZI9b--KjcTx!A zein!IiysY~xfllkRAH(fp}D#kl>-;6tFg&txSFiZ*2BB{bE`LK@;B+Aorlp#A1RV} zMgcu0rISVp0!l)BToMzyotofkqORV|)UWzz$&pwIk4z*d`#7~yr4Vcyy~F+o1p0W1 zx>E~eam_3a&lYmBF*{QaAYkS!eY2r>(#>zCNdI`Fn>jE(OfO89(*3Y6fn7`cKv?mJ zMBTTCRB#gj4v$*Lu}IT~@qM1f306ZeBDuVcE0)@=WtwSdNLQ5LGlGRi7@QAUJ8#AT zG+^iQuKi!ep_SOoYdcXOAJlf3m4mq{q`hG*#dn)Ql51_Ax(&#QA5!17Dx8$P<6q7Q z9KnG-D0}*qNDtGB5kUQnY~s>~*OLyCOIFlh_E*7MuUJFN6;Ny^TQ>&$b49)O_ucNR zsBkk2vM8O%Xq@8wvCn>+5IZ$RPeCoR%_L_*~zIiKeCRlT4=GAs?Aw}RZN0@Z1U*x`o)?;h4NWsL&OA!$`9JmwQV*2 zgbZj}w6XLfTR+J3&43I1#3&>LJ2L2*GcQ`*?$IqICQ)0h8-7{mnM)q>Ty{LfsV^C- zbJ`P>?le5^P(Vps@pV@`V3EHY7j*LqqhpMqhW*JEK{5HX*=F^%t*;RC`T{DCJB54< zBfEYi%a}ot9us(z5BDE(rMfS6#?}-HokUbnn*sd&@FoMNMUyQ^0KFiOE3chd)^s^D z3q++?89p96am@3-E+o!MG0eSgK{h|&hlH;CDX5owCu)PCC@b%Y!23<0oT~kO+-ur_ zPIi)aQ=l4%#`cE`OXLs!JWUym)>=YBnScc-pV^RDjg2s$0)BOsasD0W5dI@w)GAZN(^DwF?62 zk=9yps1TLc+NfHvli`8X0$reHl`^Fs#L17~xoJs-_(7x^G;z&R!5;xlpUqUCfXAzx$-(3W+Bb~aC&ZJxTA-CRC zFXiypU5EYCpxSL~Ft+_mna!fS;dexTcV_Kl&`c+0}ooT0)7=k~cNuQD?S5 zPcB$7J;`1P8wTH(vN-h)KuR)gzT&@w8nd7P0&4AgXsrvk+l;dK691T43vV2?Y}iRU ziBdW)%K0N`06-yk1XFGtHxU6~aN^se0o|D!aD3dbxnxG)_Zqq|<I~Z6&haVg_=sm9iBN2C-nBb;It<#O2TrS zl(PGYYc`af5TCZlE2ocjF(nEKpgBfIjnKv@@~WA2SlUZk`xo832p>$l`=Yv?ScSLK(N2^&fVNs z577xZrVPF9K?%JWs$-Maap9IJw0|y3;L-$3NtR-DRP)_JfqDspE24+jBsX_T4P*ZS z?TZ6J%(XT&lHzx!8E7mr)AvuLb2H|z;oo`2!nwMw;u+33a$@QHt<8k7^xxic(stIX z2)fndL5VrFGaZ(sdgQ0}+U84Bt@s*cyF_?=7R-&KX()$gD)NMo&6tBQApHcWq{Ln% zwR7i;tz8;*kfL;}zCkml*J2a@IgjF;k{x8moZ#U&52JhR(HvSaeZ*O_(Bg6o3U3Y_ zB@>mZK_%eo+~`R-3{cm`wNcTzXGIy4Se2*k3)hXWe^-FkzKg<)3?vG-(%2LpykpVG z*^{}jt-I!A21=9qNz;a(t@DK16p4!%>4M7W5u;xqZLZn$GRDUElv zlq>g!!n%~c$A@x$?Fa`+MPXT7dC}bY-IWcUku;E3U))E4w_Oo}NDnBH;1CBsLm$eY&7^JCw;poTNakUzvux4i8TDn^tfRn%5Wd)@PUM zE_}kjTuNXyty#so~%qG$Xxu zEU+7}#5d5SiVNph&w|C@g_POKJZ+h?z=0wZOMmKIP?U5k2m|d%=jUw0(&eQ#L8t&_ z(wgIrn78hlgbFXnLk`Vw%K7e>m*-Iw>c!>fvmw~dZb_v?AN()HftuV{*dIaL@7iK% zJFX=UGX{SmULo7UAg6>86p8NYJ^thM#9Jj2gj8#qg%GsX7{DB=rtS2bmFb;izSD+RZ0FcJ)b*iHoppnRLQj~w0e*4yARt2P zh%L3S0T^aJOVUn1zdYK{Y(8z6C=kX@UR<=;mlSjltIIf@>P zq@!qeG*7jkaC~`ZR3R&WT|lkfvxm;_F&n!pvrfNg1t*LbG?S|i=wJk7@lGp8iI(o& z3L#QA^=t?hQDxd#>Hi+MHaB%m=^Sw6{azW;p$!y;56kMg&3>F)q$3qt7%N3`ur4~Q zo>ELp1dP_RnoZvy%zl9yJW<|_x*;ZWz{ZQ;3OH^J3O^jM@J8n6MaRq4|tl2fn zS4UuckjHIURY(X9>%}kuH>s%t2G3~kS7RnEJk69i0gXav&&D>5y z;<(Exy8sGOr)$AGDZ1cAhc(MOJnK#h9YStMZau@&OBB*YUjAitQcP9qA>) z`!)#mi|Y7Hr!DgA}YpWb-;(Sr-;OMn}$a<>V*TN!~`yY=NEOU`-AJT?-mf03Oq zxUvqKRG6RK@kIWGNfKL;80Y@i_A}^+-@OPc0m+h)VzaV~8-|M-TlJxKoET0cQq`dM zIHW5&f|tm%y4Id{Jn&5#ROK=q6?;Io%O}!mz*Yous$$wS*tNE_e58@e++elS<>YP~ zSZ^F@ZkyhE(&2cfJSdU5)VFTPW&3wPI5n?rR&;${KKPHwI2hZH;*&WmM3T5_Pv2x! ztpnrjfl7ih9Puw~?VatrPI7Mk4RdKT7l%+67}SFr@E@FxC}wzo(p}JcOERxX@eqVmSVPf^znWKl|mSt z9aAxEMhvD@*a_h2OV~>x&rxKyS7N__k%PC51mF;oE36h&*(I<*_RC0#vlJM7D`Zx8 zec_omv`YdFg-PnWpl%Pc3_Z(GeRm}Dg;}LYBT|;X!Ur8Uy@q-PWTdWBeknc&uRbbk z1nR9#kj~22w0QlIPQwAIvS1s@rqS4vE##a@b&ctyAG0xoVml{w?8OnUxc{XR*_o4$x*1_D56A)WW1gb}0aSgEP6RhVtI38JB>qX*es2$y)v4b76 zTPcgFHVpAY)uOMR4|~Cl$ zOP7j=&iCIfwieOz%cr`G8tiEPM%#RGXK&c;N|gItFV&(WFL^uYwh}(e zcy@NZ_(zU7SgRoEFPV@Uv^o2o@@(HzA-_(t4t6*Fhc{#?PT&0!cf@m2q{Ny=wo_f! zJ~U+y+=1)vAuZhM0p9mnk&f4QhKDV3QW?zo0$5v$-aFa3vAmVG}95;0`UWgSEXsJD(1w=*z2Wrs0qi~yv2)7a5Qn>EDnXTW>mAZP6<}_r+yjV-lzkHpo2<-vqdE5>5Ly7B_+0 zraf%Vnn8$xg`<*&Y1_iQakVbd+gXsw2wN2_Hk=!to8>#%y@@^z{Dz??TjdpnE@w}k zqmG{{TRC!L5)&0?=TiH#+TUB=MRMlF4}Mb9lk*hpTjXTtdV|yL!M4h;L6vc-{hJ9T zsg&IJO)dc>0`MZ^Jw7000_RB=!}kxVBj+ol*fzb+y)G`_c9fmM#Dz2pW1Bs3-C?n@ zmambVcl0PrsXn848+nG(5_-=+@BNEgUf_wlCz>4R!_GIj1y~6IHMZ?4Z~NylVcZW3 z??k%+i2ohW2FMqX%jh=PNK1{u=ccap=ju80(iZ)|`;Ch`TTmU# zkoPQUy_*KAhM~`BE~uJB4_amIsx%|-SA`1`!w4Rf(tL(Qhs5F7@`I;as?JY~4}^wa zS^78;6(9T#wDmu;}q?oya4 z$}>kSg)eJE)S(m;Yq_>D1mGb7i_b_z0HmkW)U+(Erf5KMAS09G^w^?zC={6DI<`1K z^Q+KXk=KrGMorSNV23D)A!k6BJ9S3BH&3H=s`;728ies?lD|1KiLmcI_qYdSC9hu<=FE*H>|B#WZ7@~O+W)Qum z5lxnVXwKIQ zI#B_q%R*xhh0&l9zH-G+OYC^1ixcMg&Eu&wj+6Qx5V@1eA$OBlIj$qO`(2p*JyvW; z#tCpBn%Duc@R7>=o2;zhJ8z8it+#99X8dAX+~iV`(FtWxQ7}e5j(sv^5);%2i4e=X z@#T$$v#}MtdhNHL*p&ar1k`5DMxZC18YVV8zD5_YLFKga-V`b6RU}W$l0#Dd%#E1( z;30W17tQFSJ`6f}fNZmtvZiOFxhzkve=pSgAlYu3W|~tk#a2qy9c-`COQ@}D3bpmY zdd zZF-gZimiJN`FK+->i&^>e#D2R zrO~1UylzWoMr*;ppOo)w-OjXdwWSxk`Tc)==C2;6ATLf!XZA|%MB^1HoTMSkv*BS= z8og>F(K;S#VQMm8J(Rj@sdny>^HpnMUb|n6YXt82nJByX0EHvwcMyw4JMvC1R%9@y zEy(~}8h&pmzpu|%DrBiU!!?W~UeLU6QJ=zz&9bT(mYHt1K2?K~Or)bI5cUR`kQLhUVJmZmIYrczkh z&7gN(5kE&**|^ZbyUbps@Pm4>%MrzTxPcrIc}-yjt()Z84({)X{J;QOts zN!pZB1@n&2AHRT$%(;BYLtvY&U1*3-YB1avaDXPuVm|z*a)o-2NfasJg$VR`ytIJ) zJOWsZN;UJ{V%F8c+0x4yt+H5y3!r(on3@lhk57m&GDLfXENOPD1INLzOSrv@kh`6Y zWK-O)5A^0`Dysh|gxF+u-WVLI*W~hp?H)DIA~)?e#588hX=<(+_aJGP(~=jgxElSU3XJ0FsW;EoZtIX!c#<4Yl)-JBRG z^XV1(>L1~QRJH!8+AR?u8_waYHQn)QRjGYPm&PYTnG|iY7g9k zf{UbX+j0_A-rn*lPd43&fsDRDLafmODDH?%l*Ezjo^C^SrVj)z3DEg&%wFccCkUti zBp_?sAv+Scl^+v|8YKAnJk`fNPm<*p_SxH~lG8nEqaiB~RH?w$V9Puggk{-IPs&`w ztG-Pven)QwJeuIA_YS|YmEZAjibPaXZO`yuvxZw(K%y$5t|EEgbk{$!t|Gy-zAud^Ypx@Sye~@^gFnL@fCYwVB(ry)?72mlQs8v{MSj6-uvjk zkwAuwobx4GF%!l3w^7^UsTYLhb|V;O|hrmUqC3VL7NpAAj-Em0Cer{LC{0EGKMLLW(LRK_rwj zNW$Z9mZ8M<3O^<)B|55}JS!%OC)PtPEiwYjXsTl=5q6}^I#PuC$(9G4fbHr}p96$3 z(o*H-d~{V0SkCJt6{HuV3%Ljmw)h)O*^uq{!bmlStZ@Z%N>hWwWms=S`m{LXpc^BD znTz!@mWyqcfmLRqoUA=tU_i8_C^<*ru$`g>d4X$zi08^}=CyB&dYs<$zcj}R+x3Ps zFPYjs!?G?{$WB9_C^@5=_P#j4BO@f9EeQY2>w+4>a%5_Btxe4(G)0j}L zLs*H&(x(ZxDrjRL7TF2(>{ujgEq78T`rW0Fx_;bmt-0A;MK9?q@rc>E-nDMgTEP-$ zOQ-5Aus^(mTTq<4*O5Y9dAC;xZzHeL+d7G1PB*X=6S{uuB;p(*)IR1)naWld<^S(24@Y?QJo4|dPdG;?)aTg?Y)@2w z1}u!&!s}_!(@-^KU|*d_hF7H>A^4fO8_R%OB|?%B-{NRp_lmGxKG} z+pGnu1~f=Uj3G_uA{)k3*YN}XB#sR=8Gr2pb!`V2wTH7>u0wI;QHE>{<0xqtD_DGr zAFd@q0pasP{7=fyDUivdz^SrG_7p=X0}6zWj`fR`sW^DPflOec=;w{IsE_5!@uqp_ zUsW5*Md`@GLlCh0+IHR7aF>^;mIyA#_pi@M^~velsq>-|;uXG!Q>(U7L={B&+t`7y+I}gKWqb-{oUB7*qc^ zp8#}gfQ`xYmdiGAPZfm6CuR<2J0zc3`iGP(=*1jZd@f!1WG)&ToYiQl{l8o?|A70% zCf)%P5Z<0;H^+S5Bkp$;lr-*ZsE%=;V%Ab|zMuGjOGlYO0 z@WlRq%p7RfsX?R|Y(tH1uHb<{dTr&VF0EoMTi;(28zVEO zunFL4KOcY!EH#%>0p$1JN1*wBhCTD{WC)^4u-skk&4Do=x$%X9J>s384YKR7ciur3 z8veTA&1c18+Q8YkPY02g!@ilSSHfkDoAKjXn?f&IBi=9%Dh@s)c5UIwRasp>tgE{r zc1pup1-1`vRdbW|=t~TZyq4_roaQ&kdfAWZzhmE*?)^Bbd%`q*P?dYaB`hWQz`lY- z*&UqZT({%Ii?cRB19^R(tSzd1YP7o1kuJ35${=AWfkL@*bTq~`a2f@}%RH-DD09UXAYrU}NFA=qlBxu%?uNQ5!+TC%?gCEEMXfC%2sZW3C|DNs8R{gA z^$C;8BXAMsg=n1_Ov4?NT)8mfJfA7@30A7io)uJ^U|bM#D@>BI-kDS%4|QM67CpbkuS#c0u%n{I1~7D z9T+2+hz&~R+t%TwL`-3?MSNAION5TwMb6SPVyWN8~?FSf?cTA8y$JVFKc~1eCG!(8b)Sb{;fhTXuEgglJp29Jnd4 zXZ`G?^xaK7o~*8K71OG-Qym_@y0i2r^ZlL4kphOI91xUur^E`_VSSldPZB|)1P?jK znO`9OBoetd)ua)fRizYfEh3+aVJWUP1z+kR(XNbh-08^}7L7>0lx=0#Ya@(~gY>BG zhE~nsCK1fPP5PGHnX@r{A`-!+xq4Y)fbvQTed^yTSuV8yJL1_c#7dSdKa$Zx9?#^d z4nlJZDJjm2StnhKwx2*CNQCaWq@LExMYThn8p}LwKqSTw?Rn=eGu|!G!BVMjEp*4o zf`Sy#cQ1abfDZ)SxF)ZuImGE)S_uJW2_6D1q12Q}`y!Z<=%Rmu?|I-lGg(JP2sQ|! zzK;Vw5q>Xh(wPduSR=gsaZX04arxV&{f}`K5n^S%%nRy?=>`&qRL-JAmm#|b9czg`zFw1!7DyuWHnSt>F^^6jy2 z6b(s%_G6PR@IWvUvt$dV$#y0wIXl#T?7FIz;Ied0Vf>GIU(uDaIAeYQg2-P*Okth` zLj|U~^0*XHn6MVsQ>rtwU|>bk zW5t$tCbqWrx09X5>zfN}^5sjhjNs$Kv)!P2@aV7a$kPxFz!UYCLA3)cp`$-N-(*@c z$zrX`Yk|dCb4c=)BG}+TY6Odh`mOn7qNeyXyySO5u+&r#RC1M9H~{gMizltltKnS# zQFpyqU}_a3rEXX8Uflrq^OVHrlSdSJV|RK4CDjTKN;hv<3M1u?2(Zw(lcPVH7`Dln z#55!zTJe(X2Q_f2=++ix9{Cxg>d9y<{VaV~2THYfCCX@Xnlv$2ivon(k(m7H8D$$L zg73bNPZG(eL5@vfe{0tvM2mk6{y-5C@cZR$89%*y#0U-dvG_?DM%Yh+%(vXB0BM+G zt#v0DA&n`Z8ky?jY{VPG19$A52coRPH)JZJJi~V&R*;{$}4#;p$;lm ze_XtO&+T)!Sx3LmSsnzK@sJqpeC4)fWMELn&tgr#g2$d<<`Mh5zyitrS!%gF7)-im z{g+1ZE}91#Y01Wi(qtB;vV%|8YT9bpNadsv;P_2?IN76iyppy)M@(da7f!*f>s2oK z`5FF&eS)Lw_8P9)h_Cf)=V;KhpQiIS_OU9qq%fsS9{o)rp{^vphFx`fr%$gs33{co z9Ny48l=c(FUjqM#{<-K@1@f=yB01D87`fV{m%7+n_4J;3LkDHu;nDC((x9zixT;cv z^QieTQcmeo0?@iFS^mZ;!o)h7fAt|d&92~?juAig6t_&=S;z6V!; z@zH!+<$f_N6Iu+ucIgyrqNFL6`E5hnMs}|g&KZ^3ye^WRLgkGPX7TkE_P@oK<8`U- zdUiWUwF)?JvB}Fk2C@he`mNM zV0uawxoi#T2>g6CuH3||4bl*gd~fZhcIXpMl@6V!uXuXk^4)5uWe}JTkB*P_X_gC> zX%=lgwc#<@{*GoV$@m(T6x9o6Yek&-N=5Wge&TL|b1SfD!w)Wfq17mJ!rZtSto47M z{RpUogAp^nHMt68oq*r++p&k~hkd|=EI6@qII(99H{u(JzE_K0^_X~7LwEPUUvdOt zH;MJZi#iM8M;t^;^W@;`3hjudJz7jM+PXzf~gr&^t{Pc>Q= zkPNTb1{D^HK#O!_Qn)7OZv8~)0+$uQ{G9_Mb|}{9IVec9D%2I65;BIZ^YwGJUOR@h z5#=ts-Nrp73Sjf01@1Y8IiVge)J;1H_E5j zJT_hFNocwMn#Ztl|NF#pm!rsClblhX|IjA?kTjPvc}_gPw=$XyAVFv*56d^;Qu6E0 z61~jMAxf{mo7vH#XdC!{oqh=d_WFLQLwN|r=I%o3;H7=p)r2O_%K|{9T_aV9=qO zU_1G-%LhNDYt?5exdsS&Ra1!!dXf@=gLl5&P2WbjlI9A{HGU> z;P}!H=r17~eyT2!UB@hb2lr^ps4p2GDud<)1-8_qqVwOkEHI2V*`o+TO3+$MLOJ@2 zh5ywZ9EfPkTL;mv7#+6I=PLN9pcXTEKXxv>DQX11+PKhzf%;Wj z17#M}ER~hLt)kFl4(@5`+M&9m9tu_q#?FTWk1DP-Er~ucMMStC%B>!{SdUMnK2s2V ztr~{67gww6c)KwFJ30y>84MBxvv8eiO9@5VcBqdHh5|RW!bQOxn@U3o{Fy93pxw)r zoskH7z8`eu@q%s0Weg7WIS08Evhq-(a{B{BlMnH`4$8O1;L#94*-_dLtMgjwBedG< zk&NA}hqMlOa*eCC10JSOL0~sDaeev9qvpRxmwtyXED`bV*5Fw%^AHm|8{w znXYY3u1-H8P*q5UaIZw65|sg9zx$v8d-nIww{-2-#dQ}&<(a4tgzjhK+TV>v16$FKNfEk zPQoFE3nO1ZN;wYliiXXc&dUooXUu?7;DdP@QU3J=%qyV-v1s*(BizW(^y!YIb(`+7@P)QHqL zfT~2pPZ|j90OF#5O+gd4D{&;~mn@KXqWAgQ7Lxy`b7AxWw!2RO@Kx4CtsSqCENsAi zuxK_3+7k3mQ}W22Wc-46vOgS0w5e%_6iK_fUylWG3Ewje^+jU!csWxCwI(NMUW%C#St$q{NECBA);yrUk$2H#4x{ICWP3FDjER$)W+3Vb+xko6fWtU4?d1Bv7I4=?^t+{5bPE( z^l@En)ltqoSo(oN6Isv={xAN_E|Tvku2&d7(S}Ptu}7d5Ts6>r^}jE09=N|Y^TyL( z_9{n5BB~lN-v!J5^U4&%ALX;}@Xf*0OvUG%_PPM|=*?Z3lXM~>gVp#y1ar;S`WjCd z|HB>3*1XeMi(E6@dMxEKVxxE)y%gH8x#)hePMnphKQD5t*0@5fy6S#j;Edzzur1&z zCU%qxldi4mSlf%RlFS-?LUHVy;!EBNBP5epI$P?JWsv0ntoCRGh?<3jG`p=0L(XAH z6R%o`(yWBAXRzYe8DK{(NAC;DM|>yYe%OR*J~*5u&gjExt!=M%U&)<2<((vwt}&^c zwspp>$D)NEmQ|DfrBc=7qf}YHiDy?6$~dF?2CU#GA{rh2v~sPW)=YfBRy~mu@IRskeJV5obY-<7WR4IBHZH~P6@ulk zf0+P45s-X8qp|6Hurq+x zxo{Vu!LDziql{-BqM?I0RBC9sa+3KL5S>M~`?=y|A&{kdKFs=v5BO9QC)_@nB)1P` zwwUn3{v&Yk1ATpjM_+}=OuAEy`s4`g zQ(rkv-MOp=6W6~k-56v#Bsy3fBmn~6l@mbvf_pNH zZoqymYcLlHp{V>rN^V~p^qHy`A0JsA48EJazS{6!gjUW+YbL^v7%Z=Z_WM9@de*hi zQnRh7pGn>}pg!Cu0tRYPX8LNcJyCgal=$riizt%3cr;;@fG#U>)!n&N`9yXtRwD2HojJ=2g71H7t zBr_KpOOIjNL4@gzABlDyT?*Ws$FOlBFx(^vL6YWiQwOq8(sJj^U-eu;R=kC~M%(q| zwaJ3w8~1|?&Iesi6V}EHYhqvY_%N5S#WDb}2K?Rs*eK)drT$8q;M5%t2+PzO=?yW{ zzZF!~nOMw66BULtPY5OqH+&=Yx+XJ`>p3+8Xw!Pg!*&CK9on2Kvl{Snp@`r)BaZ_5?q8T z>T3N(;@8n0vtk|&98mybnOcJ|prZGm?uEe_O7HK<#_+qzt~q<>C2-NofOjVc<8PWM zVi*G-3z%ZS)|}{3qEUk6QQB+cmitJCqRa(58V7{6xsaScpuK*H!i zW>e!SSy#on?)O=4M6wNegoxiEwBBS0YSf4d1o7A@qkE#hH@@oC5w&Djkgwp)&Jxyl zP;2>CBI5*PnBnCJ()nQ^LNP_6x^PV4Lz7Lzq7N1$!!2XVp0WN40y2~Z&mTFn|M$U0 z8V{>s(V87?W!L$_|W;2znQ%X`1JNp5qCP{+Yyx2 z$jRb=4e`#ygN5>L1_)4G8i`8VAi^8Q+A7t__68Q~Hod`biE~{4NdGTt-Z(I4)z^7B zEhsmvnxke4;ivU6%9VJ!G-0AZa+|@;1SubIK0Eai2n&ez`*DFQQ{E9PDJo+=Tfldo z_(PeSMgd5*i*Qh-6PBW9IDkkNw8PRMPd=V)v?7ZhLBH%peX;zFN5Bvb(a0V?2_2!BVOv!iB8 za)e+7AcZ48(@K#i8?`!Eh5VIgO<|xYHJF4B?H3zBPn*Q3&(m=irUf8P+VS663kR+` zJi&ujGizz{F-n;siVcql^%I^e^s=N?;IKiqf;?V z9dBW^EQyD`&*${VbJ-3PoS({ZxFRvI+mPp@gtY}xv@60^4h}?~Cvbu8T;2ANoAQ|2ZrDpfbp2qX39SsMx95seU4Sk_^ zQjwTR9}`(0_w5p!j}4^FV2$+Z5y%FE{K*@c3gil|Lh~CZtXVbBODlq_v2=+?SQ)v< zGOS?v)*mCIu`H|((dLTrtKYV-kQpr>YGN#1eF!QwiOqFJ=A>|oq@O zQEG=u(82t0NGvV0d6iTa=5R9EuS0D=preFO+*A)RGPxZ0d7KepouZ%<1nkXt7w@y= z@F*suDj#bfKUg`9(@<3PkILDTUT$e;^kTN+^#sj4#pM00CSc>z1u1kjhYnk1iA0e) zQLBU1e5udZleLLC=HL^bG^D7P)dS>hOyg`g2(F-^O}%;>B0gL351OKLEPM{s0fhl| zORJ*sS4{8&09cmj(l=noQk5yGKM^}qD_%?jLNz=7T>n(z@@e~BcqPbJ;@yR zkwb4r_kN(+0ON5%WgEQ_7A_R90oTZmZR?GsBa`yrpRRDDBqpB*NsS!ORG2LJ?6>_H z)RS2?u~=@qh}6^|rvap&GO6-1OR3dJPCmHp;hdTgA|~xKy08J-Jm@n>+PQQkya=9- zh2z^)Peao@^}d9xUcv$gA%F{MLR7lEpqdouFxpk?B0_ZrYnGN(!@W z5VmH1>U^BByWHtiDI83mR(2P^i=)i9s)rkfpkmM*M=KP!cWfR$Of^y|2#hl-){9ix z_{Hgd?KUUX5_K7H7&N<(&5Bf)G0(gH;iR!HY>ONOE5h}?^b@l2(^!0tXNZ2*O(6S> z=S3wB5Tvj^GKGGBWYjluuc@NX|0#L9O(z6pd2Ray_Y1mBu*6j$4X}G8&OZ-9Pq*5%AO=$nt`@5^G z2TiKU4i{LsHO2GEPch3ew!LJ11C&M>!sH-3_AU7S*k}?WxFm(6F`284?G`-qZ}*?< zWPaDc5bsBD;X_LMA_0JLngUF9uO#~tiI>d3?||Y$C_TYe!^n9~(ahV#iYW2-w!K1%Q`cL4kLTDTS)8vLjFw%X0Xt85 zKhBz$Pyq`TGj>Ndkv!CH$^HzZdKGqxsRZfJ#(G)kLcj=p<_Jik#_ z;Yrt^()N~V37d+q5Vz78bQZ*sT?&QUMOx4IRmXM~cCN6c5)Gy3Z{Xfz9b4>Z<>C8z zCP^ndg0NvcRpKufL}Skd#GP8Q;6!2~`O?_v2}4%Yi9IbrrfSw zp-uoh$bhxS;ZWGx!=vt(kTa?*FJ~#O?hD(reQf~;fjeGCV`{Cxi zp{?rzj`!ypNhx73{BqQ=?%4yUcIz%0y4j}0=JE47qRwJ^)|A=aY{~A2sal|f1d;AE ztuj)|mpaS7#B8{oL{G7K6UCIw-|`l=q=ueR+U@d0Dc z`nJ6XnJV4`s2PONV-pcwTB&rxVwddpU5ap$jA7SLjaH}ynF7ouY+m^()smtWDPVt} zvSH@iY1s-YaH^#}@4)A9%q3@XtVoGzuUOUUfR>etoA)?$&`dD8Y-a6FAWW<>mwR5a zM^-Lk$OO5(Y>hD$8LEo<+dKBk9Od>kfJEnT9jHh$0a7U!=dl139Zh|!5w@2FI(@B# zc;zyE=x4<^PERS!l{BR0yDu!@H5oq?KFZa~UEu_*AA0}uCUO{Bv(t1$Ztw7zQtv>_ z7V{m@xI)rBh)~8Ri&G%icafn&ozWb^_`(=_2%k4XLPh;OoHqSId9IW3IILqT;sUWZ zTj^5pY5LMRdwMICZlvPAs}QVYpHFca(Ya6PcA4S28Ytk;rgAxrSGTBmv%vNV@R#!n z8)X9_pZ&U{5$5O4Zm#!6EA(t2JlXZ8&!H^TS~opYDI9)kJQ# zPbwMKh4LTvMY0K%vIRd;36!Pa|Hdlzz2IY$TxW+f-R%{t!O@PTN;1)8lTFL= zlYiPEkvG5=o>m`C)QPjEDhloI0#1?RCTwFYDw-QUy7OO_U;+dK##Z+JqBW{PQaK1} zsxeE;=pwW%iUV56y`c_{RvFC{iRT8gV+9T3^?L^=-puZ`NjQ-8!D|u({0*;$DN0xh z1zcFQMWwb#fR~k*mLr0IX=cbIHt<_I0|R8R{Yn0;EuOgri_xXTB+# zc>N5{_=XIAuyQuBCdepr#UizpUG+vs17YHY;f>r)GB*>6E^%-akF-p*#ss}E_k0)E zrADa~{ImK_N>r0YEhum%j_J?C<8i9E)y4Ok7zu?CoYI%Gw`(!SL6XWpg#0{sTH{lW zIUJ6;^g_BBH8~1@a@?TDEv`rGW6)~Q2^~U;V3r>DXHAr1`Bc>YKnkMRks*u+UWJtu zRv&W~85q{S5Zff8#b|C=(|0fSMCgU4Wp%Q;WWdi3sBgO?#}jgpsJBFhnR_tn^&XSo z-#~T+aC1+v{#rCms(3n&F6SS;SLb?}PU7GQ>}2C&YDI<8WJMNZ4%|;JRIvguTC8I{vyREqlFH*6gn{C99d7xUw-Pk7bW2z#u zzn?qO^hpB&g+(TDtOBL)kg#FN#;6ifA6y_Ae z1tQKRz?;qq#<0f}6Zgv(d@mi2pge++!0o6wV;Az&`a_?hxG^XdHH8IF5mNOi1T*~2 zyZVGS{@E=(WQIpTQ-zx$3$4*PjK4%HiP25s97M$w!j2bkPVy@DEphc_w23tjU13a{ zSO!JXc#FBizv6_z=0*eG$r+s2^zB~K0MD2$W*|5H8TXeK*bDHZgvJ_0Rfu4ji63Y4 z%QMR(45RRECO;LVgZwbBMNP9H8`QZ1IiE*r=bV#jHcg5UkwdSBjvUE z%)(?lsON|#2|M)U1oec{@g;F|b@-yind0Q*G}LNQaFfb;k+t2hXjjGEsHevoMWi@X z1IMR|qRjXSNSk=H{t>FZ_n-&;t}n_m2kMHpv@TE@5EJ~Y9jg!w>m@&|6+H*y{l>Er z_S-{jWp{6>+lPMq*-N~pG=)Nt;Np%rHZO%$rkZou-^AmBZsejO zD?CIwI+GK8r-Q1-GGpe<(z$Rg0m928UT-T$-ZD3*>vxG@)JZ~)%SM)oDj~1d8r&gY zh!Q=6W+|Wf-zl^v#C{=Nzefver7t}?nh2#0kyvr=yZT7#9b$6Zg1dR~Hmgo)DeVGL zmOY2-A7GsND7FGc<$pjJuR|DWsf9x96oP=x{_?%J&D|tJ`ubFzX_h1?Vj0;w{pSe- z`P}A>X!8s9F!aR%4D4J0Yk=y+Vh+3g*PFd?}1AB2#3rU3By%L@uSr)tCZFm`jVr0+G-`fp8_wK6J<aidk5d!8R(i{-H1iB)!X?dSU-bsH6a(EfV~91?+>38Ltf25yE_U%yl@J!B4JZc2%wip(76%S@ zH3UzC_GMinkMGqkhFktQPY``#-0PdVh;r*%C{cq!!6i4tQ~g&C_~n4RLIu|kb-ipE z?kYw_;qpGhhIWccYy4k(1McL+MZi$Dd3YbsXLLtb?&}(BaHoMrYG9Y=Vd@l$uUKtK z?{1PSa*!WcPsjOW;C+dNuXu@7#D*Ztek|%9AF2srfU<_RDoInj*>1(U3vL^h3~ceR zpO>f0mqU#$&ixp4o&nv8*{@2zjFQP+ZnXF_pXdTz2DJ z<9rtJN@`cQKM%6n{d3pv7srAYX2t4RYU-Z9X} zt~a1=t*jxEkZq5T)I&w{IBvv(`{75I5Xfnqu+#Wh?{i~0&BD5}zGVf#6MRcmoPZ-i zj!i_*Z;j({n%|(EW2rY_ zJD}$$fS=11Umjpf_<#6*02eN7Oiyw}Q&kCAxWRklvRs(o&@X$2_kHe<2lw~^I=$Z! z@uBU<%LO(VxaU?P+))nnH-cjwOo5={KXpcue@Nm5eIWOT|B9pa!de=Z$_PrF28Y=@ zH~x`%k~s^N&qGb2Z}y7U6nF7oN0Xa6AFmLFJ(8>F(6YHQV4{nvx68z5c^(;`KTPb( z{4QDhK6=z|%e`OocQ;Ng9tXoIz)?_tmIm~KyYpJ!{@ar8AW|%v6NL`@4{lOIL*0%a zOvm6*mAz0jUqTriEa>Ap)ls)CYs7Axr7?0p50nM4jYa#S*Pdl5`P^$!5hx#ozDnH^ z4Kz`anG&OYFNxtvE-vUf;eh;tYNo!CYolaSY{X_YeG*v%xrJ~m&vPOxN-(w#;~>33 zp}lApM7ZzprpqQUabr7&(+fr3!7EXl*1!mnSvMXbs&AiO0WaPE-k`q|9mkPbO5jgF%v4C^b;h zELlyW7nG!Qkyc@e3>Sas<9%xS=~iNVJweKM+mc~Z-?<(-lW!i%<+*m6!>j50w4Qc) z-7gpiR(33hcNm0S>pe4QqF@cz9lmV3&2b8xVy_Xh#VtxydKN&egvh%_N6;@5G#a#p9~!v z{-IJO2GGd7O#sC%en%pVFH3MM*G$hA!#!@|fF~Yd@+YW9zMpm8_)|9u=w0L>gRquM zqx!~pTK{Gm`#i*=il;1SHahLpMp5F|0{o84tM z;*g)}(n$w=rz)DnogQ#Z(NMQUVG5z~fDmHhyQ?XW)c>S+HT_;R4Mi$x7^uJ!>lT3C z1F7jtuY>aab4{-nrZ!`j0Vzu>qjV(_b1jc+;Iz=KCh6F2{WQ?|1ItS5g`Mt@Rn4e6 zGFoX&=*TIHll%&_(bq!Xn=ef$GU>{3@go-t^1drWYV@-anwR`hLDC4-%w#5%*tw%5 z!zq9m_qqjv>kHlHpyA4|>?7pK%2_*=?X-Al)V@o1y~Gv6qtn2%MUT-_-j#Ne0I7t8 zjq!dgv@g6OKwSph$#EfmVZn9;swC^NA$;0PMfehbW>DA!U2Tllkx>Vi?4+qNu%2JLTk>kW(F2wr`5(In$H9{y|MZMUdhb7<-C>i4 z8+^|SkgIl5$dKY?EGMHCDMl+Zsyo+Vw8@j&@%9|aQUG`Kyax1yxPJu;F0fHI4Dehi!n?d#l`I47! z!vyp3NpBu_$UiVIx?k_loPXYcymqxXXM2)XT!~^#=CnGEd6C;*&8E0W96g5vF$`O( zDetrz{U9uxQ1VsCDUv&%<3vh#_$KMEn?!{fxG^m`j)M11OH6O_cwK<$bG$E~r7MJ6 zzEd9{x|d$!q8l87{FN?cfCNQ3c-_wFq^*twA$GWnz4k^wAQ+aihm%7!coHCLr3#ib zA}Jf5I73$7+fl1zU3Hk2aT~CYwMZxVD5Kj!2$1w++{A^?xt+xhED~>-0boXue~(h5 z)~$Du$luyO5hozCpwBUTku8++gg53rIILo0=Xa>e>n&KjAM~IA(&nL8h_uVUS~7d+ zQkgtq4!L$;y9kP|H&e@+2D9JILNY!S=CyXYGuB)qeB0HxBV(9e6GVo*Tx%|zGl4gn z3X{xi`#(oOPR^iEDN4=@zu;=E8?YTj`9>u;dT6B$YP8;fu~{9eHHYN{3sg3))r9Ux zk!IWEauDK?!e0QEx)T}dj~{OyAiG4X2Sn#p z!&e$AG;W-i@W-PA$%4b5-}Tc=ww-1bUnM!5U*i(yjd83)UkpeGJDAIf{^}m@-Fco zh7qYf(VuRN2aBv^Lp#l}2*g0R^0dOUKzC3&pR78EOm0?H@cWH0^*J+}&7O`n!z}G! z5bCj5OvM3WHoOdZI8pxLCG|PQ2n)wZ&L}`9fqxr)g$dpKrcc&9K7dbJVhzfim4Dg7 zlPzd=aFWJ(^WC)yjs%LsgN4X;l_2O?lupGIZH$JmtHxw4r%cW>1)BN39|4gwI@>6@ zLW59}1!)7}#pVCk1IdC7g009p|EGQ~mED!IjKvFuY=e)vEOy%NxBL!KJl+Q^KA>itS6%9Wn;%78e;}9&y*o47 z6?24l>0Q)xw;^(lCD*6N198chtoOih-As-2@)}dGuI))7E;x_>zI|azuzOoW^JCeT zm*I2G&5Ky?WGfcqzVA8hg%AJX=|~y+PyNP%BbGf196=Q_@l^U=G5_L1ZJVgpYhqu) zV)MXk-LoNw7qi6oFI|??@8{Y?P|FA8pP6&Q$Tw|sg>R`JGFGZ1j!T_Y@Hu0Q73fi0 zba40%(DaF=ndGSL*0DtG81(y<4}Z#!f@T}-VZy6s?adkt`6(NR z6J)B;h00P6=Z^_~>3dDrQWimPm+u1G=KtO{w*P5Q@=Ss8{e%zZiHu+qofM%`T@WrGG;#( zPr!DG+k8NNQVc0HNb?5taKf+1fgk-%X7QiCOQO%X_0pAUHlCTo1?8 zMsbvbIn&BF_V;NpIQuCk!ra&|@83;icnW+SC?WeO+bwld*^Z*9CYZ?s!*YK#zRPSV}7IUQ}(|YEMtOHk(7%(;Z~!9 zf*T{pJRlY~Wwch_FR+SO7_7l#?zWieJ=e5&D<@)$igpR5kmhPPs9IMqW_201*PBGynkh3dZ3W-& zk8OUvCsCmG;wxo>FUAON3QjM1J+>MZVq~+3WenP!mbA_mDb^*%;#k9TpqzCh22#x) z&P@H6ff5}u!C@+mYqB8z4r6zxzXW_PP+1T`H6W_aNJdy{uC(|m;9)hL*d9VK>hyVE z!!{DZ!UOg(Urtu2t}Lj%Pge%=GUe`&^Q4$+>MuvIcO3RMtD@mtUayet7EIzj^}NN1 zr%mFMSAfN>y~MxVn+d^2O_H^;%$wt#o{%JU{~eC{6>4>IsN$RK%sW*aTSroylBf37 zF)-BCFqn#FIox~qM%F@x9D7rw$pnNFB+HFD2Fi*<1a~XdJjpH@MM8-Iew(`iab!XP z6&zw>%Ny@%>X|xrl~|Bbt2t2fW()h5PcAIu0KM5^3_i%Kk*pCo1G*cNm(si6f|#2V z7-GhEaYl%{Lco}BW=~kQzFF?&XugX2sD;<-O5{ExXWlp;_k!a=h7+f*RqpK?YO|=) z2gRmSSbu^t%*Y39OYh4&{6vb-(2o6PG0vh75qiLW2+=4`sL3)3Mzjh? z!$&wiF`M8dL2$=Jt9U@$`nKL<%1?^hABDwYn2xDC{Soan2?*o<6t#5Q8m8AQD&ZZ8 z2e(4_jU2DOWfSHRx08nEX5-JMR&&fOnq9ywjJ6|T?~4VLBb($-;5i=>t&=k-Rlv|P zYBLfshddaNT42*~1aT|F$_Wtn20D9_AXx0~qm$xj7eKj5s)j!xL~=VxyH^b#I=Eg3 z4f}ZvO+u*f5o@n4r0$!tgxh-j8(qh0!DM))Jzo|3K~VUMHg(J`RrV$&aWo22VR7k} zso68wk^R$(j;T+%jq`}muUAUQHR3=Mgz2LvVdc`$b);qtp$p2$rU6?Xc#FyqzBERy z9{ejBIxjySRa5!e_`mvfzlQn*JyS0y)rR!Ncg_hn!G`^QB z$R$y@uas^D7m)sYGW=9i;zvZ zHlOz`>kI5aM|pTtSa^A!sv~B!77|rg15oK)_KCi46T_Xs?7sr3^pxszzDn@kHS<9o z_9zV|Ax5rX%y|=QB#d*N*|lj~WJa($1Pm#0ZPPv<|QOzYv}r-ONr6}m@r?+9$TC>LVZ~Y z=>T2%PQ>X{51)#QXpZq-rm`2nV?@Gd< z)TOwqI3!Z~Y(s6;8r(#Zb_Fj}yA6Fj+Zt_e%(fa?bq^6LT@v7vkE?!X?r@+yAB7Y` zx&_@d;iYCM1@eZ|P0JRTylT7X!B~;fD;cFOpHo$ZXG_u|yXPJmPN3If4sJ5x%f;4G zc5v6L%aeM|aHNrzpNV(muZlQ*OU||ltfe{Z#nblTQ}{vTz3(cUa?!t?-+PVixW)er z6s{y>7gTFnRTl`W1)DzY-|^)jxjn8KqxO~RU?33^`e)_=7gkno2cATqjq+vxFMx!P z`CHNz{TN5D#O`ckN_^t9)4*V+M`?q>Xgs2NUF{|zj+axMtQX8U5^JBi-6&w^n`1F1 ziun(`?xz3EHFU>P$Ycp}ylh&itR-304r2*Ix+iA#M|s@4*XO1(ZdmcD@+nT-D&AIr zQTX(|BL0O<^5&E9o%sMei5%iu4lB(&qaU7cD-kGhE$lqc&eO7xSv~B*6nDO`_6pvzqa#6&aW{gNq zsGN8Rdj>o-HGR_2ZH@=;%N;Yg7L66#qN{8H3f;gh7R2C86g5`d-fpeCRh8@TOi$Qr zx6XHrRnwp0l1Bo?)kyZJ!ta!d_Oj=OE6Zo5wNq4Ho$+p2bys(u|)zWrU1ixuUSIq7+gaWwDO*6gym9g&t{ zbn(5sAoK2ZQ9Sbwh5~$iZ1HfzO4Gs9+qXG6!*t#U>CBju0*gF21cl~o(YiLyy#4bp zL-Q)WxOttgr{Ch;T#&*4qwiY7FS{RZuW)wWrrDY0&y!5YCt4{o@%$Cb&O0xqXKkdi zDW1JfsGT2rU2oid?F50OB^bl}k_jxo#b~19P1s@x4B?oTemYaL2;@S07!b6W$Q87E zYLoD;LVK_7YUeT{-9|tH!yjP;GkAbvI>H1vjuKjb$N!|bm}}R}CyjmuQW3sxLV|=_ zUXZ30h@ErsXB~kab$wOyKP(k+B7?0$h{iYM7ZI+$3tsFrY_K+an66R?hNoyacj=*! zU`vqEq<>)hlo1q6g16j1{bB%J$Ni(%`+Hn02H+w zoX^&FJ1}<1Iag2upy$&!I7#H&EEX$+_!&>aOG<;m0lHHjD(bTm8Fo~8nAVm{Wkzs% zG~Rfk>F!DDk8cLVn?ijo=MF+-esFv&M09gdb+~Dr2@VfFF7Xsz20~6_5{qFnj{AK# z8|hOXU;+t#+MK${4QP>ppd^a4Coa{sD_9_KKra*#sZyovhUolw6kD?%qfT*Tw?(!O zErU+vG>5N7;H?&!Ss&Opuy6tx!U!@)i;q6rX(xNBVGweN?|5%)H+1OgjSp>L3@~P- zTHC1jq}3KJiL0z(u}y#`i2=|U{BU6^k}1W~}*MqWTc zYk;L4eYf(2qO37x%*jx*p&*{ing2`4_7dY^#Ydanv}dd+J4g!}j9KDHnlAvH*D6PZm>@a;We zD>U(t5fwEfWH~n{dZ#8ll{vO2$%|@bB{6D{b$7xhu7-SAI~hiO@^H%I{*IqZ2|y1b znt6L$-LbhybuEE?bPO-qdG{C{>Ff_qNj)kBQuwr%-$GFPh&lLFzTG3f2MHoBF#{=N zm$HU#GMtbTU5Q9$Sp7Eo(N5#UQ9LLO{z?P@2o#N%8C`~NQ#Q&#!S=gxeR;5? z`?o}1)BNK%kCi&-Z!aU9jb2ks3^jmP=_U$-Od>#*N%W?zv=j3Itmtx&x!nG#4(0~s zppai`OB>)fhw$L_x+)u)Ovxu~XHa8>P zBSsdoSk^M7(Gw`YyE0hnmeriZ((2er(ZUvW1U}Sdp!4WKrt884D5|xywvkpgR!*=| z=CKQq>&BGffuNn>kw>YAQ&c3Vv4Z9PM3t-DB##^8J=q3AR|QVgDpXd4AY4uB!P-X- zo1JMv&DP71PT%{dp7d%Q^jluBa3`Df=5N0AXvghm)tQ5oJin6TCc!J3&yE=QR9irX z*o^CsM)<^(aJwpzusm*A$+|2%k)YDmkYt+_djEDl!s8cVnuj`M36qwo!L603h=xe| z+BHkY<&;lfd(X~G)km)y($;k=B(lkzZ1!em!T?S#hW-UT(L&I=B>U8vKF&_V+Ph?3K)(dDhw=fz#D@+#H%fFjC?*rPF1vK``#h!~6F!+p6eiTec-4vUWo>?x3xW2B#*N3EBwDzeRf zDoxg)&S9w*5WFj~Dm#czk*47;66+{rdi}hX>%oVI*5OS=KyFo_u=-ZXx!<1l|LIBJ z`WIDs?HJ-olYLWp~}=&SJcZz@zFy>iX^mhjLj`MRWc+29BB&kuvBB!uRjt zkV4M?(nUH_%jcHjs3L7=&2zc_dGUsMh9;0?qeX5%be%cgPfym@q2KuQNZ4NWe94Jh zpz&>~P|tT&y-CEH3je5`PtR3dW#r#3DVPk~q@tXjW~vgA+BCV2h7dzKAaJPUjkGGg zAT zp&yGYQ)tGPZ38Ypk3ZzD{qoTvYHj>*4m|Yu;$re1X(GzI%#zB-M!L50)kAbz4q@hO zR>AsK1;8V0vkrf~OA(OA;yy@djVLBe=fSlZ3K_=t!Tt`{uZ*-{>O6oH^$0Ymht&l3 z*Fo5yf>HLwkUl5K!Do~hEs-XU^#u~LgKD~8!w|bO>KnwKVMz@N<_lzFN=v)${*MI19)IvWRX@Y{R zPQwbBwx*~$SYr&41!cv=DdkNH448SFP7z()87iYxnl@oq&$rKb*R%obU{!y273aX* zL)Vnu|GmK-_BztUiibCik@n0XA(8rT;IZVNAb7JL`^%(n^|X0&SQ~PNn;abv)R-*F zz{|@=smyr1*5V=--~`*2u5_Fpm!3h_c(Egr<9O%;s^6REf9HhO-@KnuGeJZxl?JE5 z<O0VeQb>i zP|(Q|M9DSMHg=b+=Rfm16vu2xo5pyjC@7HY5Z$wXw!XeyICr6QNDVwNfddKd|lrkQJX2F5duZPrDUUOFHy3 zD6SP_|8ZXp#&UwYG<;DJWz*<>&Z3;{I(3}UgNZRCI@xV?H|V5U=}Ao_&n$hpd}$4& zdDYa2@)mD@hDYnkZIo%9g6`7#Qpez=D8(%MNisDkZI+kkW=HXcbEg#%iesS~ajBa~ z<wCO$29?CWH2M>AjhtMpJH-S0DE5q|^ng=-MTu|DzksD-_4~xx4>zkt?{+M2I z$_yXsjM(^xSJ1{-vX_ohKiwc!5>o^0*u9oE9G$=cUZENp4q;TYVZ*d-ozVO2M9lf^ zTbkftIzQ8HQ)d(Jd19?1v;WHx5^wMnP3Z-f+ozmmYV0Kw%$RmdQyQnO*E|wWi-G7A%54hlg(~EknI-(ateuq!Z?>}=_1pZ z$d(^AZ2w-+rgk&Gth1iFX18c)AmkB1NcUFqENp|^J%xfy4F4tTT8M_khi9br7cMleF7&8NUo zQnE|t9kSG(Gb3>A6{%RIl>@ax&ZiPI+`y7}_vE$;}=JDQi>{ z#q>{Ea~kt_bj)M9g_0XZ2f%XAQZY5gR!+JO2>d;Izw^=T9ZMWU!Id zgu6{zi2`a~zZ(5+EzwL6-3BQj%+0sH5_l{TX5e^;UTTl444CxIS`{-7$E|R|C643% zj>q|>w471K+zWXwv9FWEJWXn)~I}SvK4WbepU9F*78H*Dy2O z#*+<9Wj$GRpI;d$_WDB+l4y(e%Gi`_Xt{$LcM){2$J>j~=`ZvhS|E43wA@{sXC8kUZ{N7FRSq}K+?sb|DB?k?so#`6&zK-nEy|o*1LAI=ULE}|HFY7~&AetbNIrdOIOmc5 zzuz9$`KWJxiSK*MzU_ox2iBBvi$!Cl@{#ThIh3>mK^7-_wLuvoBDDZwHIQNXl*9`Fy$V~MZwhJP`o&}vo|S~l z6IQkF{`r7w5KILv2&Cpv+v7h1C7vytc!rm}hJoV~7~gN&N|pb#JTth)vXz4w;6LXx z<|K^+*PgV`!%Yz3c0Bl4tA2BrIqEa5%4_5EGSnj?DlsY>6Q278{(&4f6{=E*DTz6g zaY5qr9c3|&BBvSg#!jUD_TBKzy)?orQ9QrgDDr=S$#15}EI$m*nCanZ*<&XToJnLj zk3uo6Ap_rZKI+parR~{Ez?i(=nycXM(0gEHh%u}s2=fJRo&INpGTU;T8oTC~NqsIv z5xnieHiSfdwNGT%5+3={J>UDS$gkqCL;{8Y-)!PTJ^(6KL(<<+2))cMPs%=PoI@9+ zU1m;C@pr|)ej!=_P{8CVPQW{8`u9fVvl*VvS{OwT42;5O11%%Y^sFW3PrXx_i`r4X ze4FdY^iwi#VH^CDaO}k0{#aiM!YT}NU438T`rWYKQucBIAhTFxPhgQOFJ}BpDmNV6 zw!z)&`MvYa6#0yEvP+^TpW?nS=u<;|)sPB9o!LTl8zaC}QxKQkclcrCwD&{Rq^U}< zX8(necqk!#2+yXOj5<6FpMalhTVAHf%p}#o=yCLK=dwCV1s;y1nU(uD`jBO&{1{_fAy$!ai5;JprE0Ida zAtw;mzyoUI&_y^5aZo}pV3XW@3bfrDWwSCckwR*sr!YEJM^7eX>nWA^zUHmckJ=e0 z7m4&MwPZxFiO4z#?M=6xwx9KZu*!Pin+(B6hf{YHDpalqDl@?7F5%Bj3dfz0q|8`l zltO)0_zl-C3nh30>Pj52&v&Hj5^(E0+NLf-15YgEssV_m{rW`gig?%Y+160kCWK{H za|}11Zr35GvQU!_$kr$k&{jIX6LZnHHE-elOPFiNbZdSAx(;|ZJVU14W+yAIWey|d z^mF~gA)0~M&vthu$qJBnod%mz*D+*IDaDctPyc_Pp4tL%24siFLeAOtqJC|Rz~2n- zFlm*K9`)1aV(q?pc>t-rl@~d^g43IkMwmXI@eWoH_;)K;o|LL!z5lqJ;2Pe))-diA z>8!+m%DYX{seVK8C>JxixeKn6^lzFA0Xf@Pmbx(`IME}$@1N;J=^?iN$t)UOIA?0B zB0@7qxS_Xpjk}O7ITdG=&8MR^zrOrX8+%p%AAXcS?wB2~J?1NHfcw|#)wxj%c~iG6 zD%Djv?sI@m5o^`Ok>^TROC7~?Noc(~48hOfxkBSmr!;&khjff$1~;Jbbwww?#`!>uOQMiI?6~)BaxMA|1;KEukmp4{qb2rLpl=d?9^gtVMJq=dZAF!l3 z$BUf!Ld7if_d;>nwz>O{Bkc15b{V(C(>!d9d&Sfw>Zkj=%g7r^jAKIeqS`4ndSCM8 z;;jCe^Ryey-fVUN(WK@5;Ei2R-T|tl>$<5Scv$jT#52*b!}Xj04c5-)*mazC)TCv^ z;mux4iFyysqzPeZbRiUH4tYlJ1460voAe#|!5>z)#_$7#hdma;57}}-TwsZXl_@&q z4R#`0)e^|bm%8wwc@IfUfPm9I<>pMB1czCkwk40_W&7fw@sYJZv*1j!U@~gQnUwVFjrQ11zBC`Vg~A>&PekC^8@&jP*&F;D;qW>X7t>L}0^J zvKh>)?CCBD)<%9k^TGu+s^sH zB;qQ=wT+IUxI|oS+V**@Z%l{K(chAz=;@oHSlXJGp? z58Y+;Q3;$zEz;K1X90PlA%EYuNnXho|{uF_GZ4LH*Kcg9=P+u(G>z`RhwCac*N z8!sZojdT{g@5c`C&$t<+nn*3f;c&!GhTC2tG8;DzY%9*va>FKJ>%*_aMiQbIwmtu) z%62@P-Y3MPB>z^X{k{9XR|oEtpUA+VWxDGvlb$sAV^b$NIG9X)S}^{l=7~KI&0Fn1 zaOsyaT-60BbF}+WnsFSZ;WroF9!~wiU(HOPo5hhmofnsm?MR_|3=-=tDHg#g5P1xH z@79c92lvgWBB^LD3qVsYj2bE-*~y-X?Oi&F9>Dh~{@tq+_}r;{fv%e%iCo`XJGU|M z9tBGH;5-nVUZ-Yv!u3ZX_gMijo{?sE($;a*pd;VbykNj1-SVAHl&JY$OJj`rok+(I zgBw`dL=dkDd^mwd+N9GOU~Bet@Y|Nb*QhobdX{uI%m~g#IRrxe>np`>NXENBm33j} z9#q^*MeSFBQr?he9;hkm30LcJG{{6`ka?yrPdG~tybsp6`mJl;gwIzRE)VmO&zdk+J4{?bQ&(%r`UGb?xV*jsksG@7P)iXs= z{eoQxcjlM_P0)HYNF!B-a4s}L3bYK=KP|&p2j?4~!2?Q9b#tP8z}Di1%YBFT$O-1Q zUexf-JqGlS^<5a$1b@)%G1JQ_IGsM-7Rl@K+QXEW7FUM2Hn1u(#aSpB>hW3S{DZ z-0tViA4aXPkk;Y%R@5dMI-^)44uUV_F*rU-wlfd?rPh9*r*Pc<%3AH${j?pbjVpYx ze@9;9b%bf!Hhdk0b<6YomjTlsq$ zvkH3uQP~KvMWwF9Mj5C0;iJ)tbgjTQr71?7{~n66w5Vdy)QWV1&jM3EAC$6R%nu97 zSGo&4llze}+xJRX1yUPI0Zz7R?6T!&(%s$W>1+DF)8zZGgTEO%;sUxw)%Lnk`RBR$ zoFcT56ZeNe7*F#7_PrL~uQkI6c&>oqbkw)p0}FVFf%dIN%17lwS24t#;pT z1Xv=dY0CDGW%CCf~nU`ep zd{eBT(;q*Z=b~2-DXr^M22=PJ$$O%dTNK zGjwM$Z6HAR46zehmC$2kM+2}B3zzrBF0y0 zcR*XHbs?UAZg$S?!jJU`vgr#x^nR||>w5Xd_i65dW;yYJ+KM}hBy?(|ITNRDMi4_6 z{`0ySsiOdcgE7Y&_R(Vw;0n%`7zcP-YdogLwANWkm zBh+4nICJnkOXqKi&;V5vDn!qg{wUd534S8=lktekL|xR4E4cP3FUokHU@;2C zD%^qU*%*RDqk3;GHx2@<0BSXjr{8P;bp$Mxj&zPc`rk5^Fp-k;o+h7l${9zd(^Jjd z+w{kaDA_+Jy#c`B3>Xzdj_W;nl?jD2A&Iz>XvLW;Wz2B7UeYaD(TEJZph8}%6R$D` zA{8j*1%E{7nDF;Dt|uP?M|&|1>ITB4mc>{4i5iTVJ-3$X;GVlhU#s59c{`4dd@2-_ zmJ#kNV)E1GFdh^O#+Fw5@fO+b=Og+P<*@Sv`&8q8(suXVRB<}O9Xtav-e2Ls_A!t; zHO7SMoPA%>EP1K-#W^h_%BStwb_z{;} z2dLIP@RL`RAnq2Fb2~;LTBVp2jy6ZBd^QRwgU8S}AGaZ@62-3!w#>|P2EU`!o4*k3k1vr>;zUG^GN%2OZz1CtPGF$`Z$!{-<;4u{m%fqe8Du*&yqSt$=UGV#weN2XR9;(#VqD?Zo{l%>1CyMh=13^~8OXec5Gf@-LmGaEO z-M7kH*)fx!r%EUv#Sbl=tQ;d%cwmHCk(;xAg#Z3ogn#uxBIdPoxC`IH;EATd&*2TK zTquLX8V^K90zL8T9En~0+mLZX!Zs&V$53r1P%80Jo4mbk02T=ZFbiC}S6r_B?KIdn zc3#(ca9mUiQy5zMum78Gr>>A%@LQsOCGk@hSg zSdRt0Uc{Omi&wr}ElaT>`kH8{;Uf}m^STjYnJZ~eK7GAib_oPKd%b7<{YNZa9`rSH z)LyrW3C@vRU`X~XB|Iw?Dohw3I0|qUPefTR`vZ_;w|*@Qv?T(91M1_uWwXCn9@|VX zO|#GFV8uVW#hnIIZGrnWY)+iS=|6grs*u0GzV$`<&u3!L!7hh`aIQjWz26DNrr18N zYj&I%0-Ys@u>Y#Gf>1|>&3D`m7Hu-7(3owk@RNh;9{?2Be5~q`YE@!eeu8hlEj_V3 zaFwY{?Rpgg1h;YYNB(N2B0V=yIgIJXUN$FH-h6W%-vsBcfs7cRlG#hn^j_a!hjnbR zsV9C;)moX7e`;3n48fSk+^JBJlj~g6OBN5*_{#``Lr9Q4Y@V2fOx3i>c=sL4-$slB zd1X{uj|??Wc-Al+iL-oUab?SQK$jU|i&#Hy!2boCJ}47Yb+A15;_o+D=QULq^gY_@SapMAx~v3(NZyXpz1d6v((@JX^%io?Lovz`~88|5+Jg?%V};^-_shMI!4=$U`aH zZ}rBzkh+d7i~G|@A3#8gqfc>e;hTh97cM#~TEedjpLgj7PA+cTB(#9oRqL6EvVM)FnQp>p2{+R#Kx#OYkAfd{h7(@Y<0Gr?*Ucj^st2%V5`GEEogbo$Xx<* z}nQ* zsm+)o<4JMD3nx{_P42S7F^~Z>wz;gvetcwinKcDc2}ekx(E7-bC^o!CzyAO&K+?am zmS5lPYSIv*9~?&uQIPNgNgpO@e-kJwk4%(@ulS`32^f%A$nQ{>RnShgCP8?+aZab%>T)rW>6agCb9D}>h$wuFZ-sp2UlUVGS>DInIvdPx_#3xyPuC>cY zJEC(AfDb>wc!5-Cd^0d=+DwaKRoip4n*8#Rvox{_NYlQ9oyYj-Sw#NdUjMiBBAe^j zR|RODcD=1KK0MgU6Ut_v-!^556*9I$lM9Y&Z)uU z{cg|{n{^ZtgPqDPDi7>H`^PNZ8@yzk2U>1{#;}G>=N3tiM!JO_(`Nhlp{pj4Fh{sp z>&j8S4)TfBb8W=YvH(|DvPc6;LowdIbe;>zhleB__%*0nCb4ZtH9+HOB_SR=d49x2H3&$vkYuBak_W8 zZ~$)wTX36zYbQoba^TA%O`{Q7PtB@dtN}4qIF*_`%f-a9OK%zrx~uO2lWLAm2>C5N zMcThKpdt(HYGX>s4a3%hfjvpkR-qQWY z+VD)xy0Yzj$iHx2*U0c9r5gMo@-Pox;az>4{DX8w&c33$Lp#b6Ti}-LNwV}Wv2Iw3OY@S`)6<(iZ6EPMcuv9 zehXcFNuy>>K_C=8*3ds8v4`ibzzaK)oR?t~DFO=Rvf{xXj8EP-#s<@eYm)f3=))$- zyQB<|5m`*1JV>FP?GOw}(}Hrm?lO|VhBb7SNk~qkioW$oow=K!>tuV>@(}Njq%*J> zi!BkCHUn?!nSek~)3;rG(tf$_pN@;vbBS}TSh-DZaVmEK0q?@(V}hmZwc~IWP$e6oZG%r;Wpb`pf!0ZcGsJRC* zvc20RKeizh`kxjml8Vgl`#RsR-45~oU1C=Eb*v}a^X**K3Q-XWviWWv1wQjq5fQr) zQ=Lvd;lD$O_cz_7DW9+1V6X<9YeM!IFfU{(+JAIk4`w{eF{uK2tlm}#dZG(r2xR18 z;YUu1L{Z%4B5{yfpfTiqLY;DGh{iT?9>5&;+3yV~F>l5?w^r$`8@k`1#x~KiRZ}hX z_ojX2DJdJ8nb9nORlo-3(P&<6hv7DJ#HFB>RdTr1rF|Zbq}fG*yd}i2?d_5>PK@*U z4Z&=Ef6m#AgIfVqSqi$4iVrxey9qMH`l0V3X{~h0v8Ksr$FEn6gbl1!cgaUw_34RE zFJtf`ZObYs8*{*ZPnN+EJQ{HI(BTQlcw-tD=KO`1qo^5Ss!C21VJH}U`g*iKP1=FL ztL&A?{JMB8$Mg^;cNu&aXme2uHl8X7&b}l~SSfQaWno(qT56=Y_9Zoj_%Yol5D)=* zEV7uAHACd7yXLT8V+ZHsD{#9g4wA#sToY%~bJN8e=e~c`u@D5iP3}LNT zbI@4r^#y_>X%QpW8)XM1NPd-(q{sL*_`&al*wutQjn!u0T}oawo)bqhxRA0f2ufK! zccTIm0-tbQlcv4zy;O&i2L-h1(sc>JX-^`L`72W2VgA)H_L23}+p!eUzLGg9TKm@1 z+b+Eyx&8K7;67a24ITZA$O6CZ=_r0RHC6En*|wzm*eLL!3T`2*d7n$ zG(dDxQl*yUgR)5>YBz2Lhz#dCc+bZmRB_HJ4yVr_^C$?0)W9vKiM(f;3ZhBp5Mm3v)yRRPfokVrS3-^PY@WzO6$#BGn4f27}`-lpb;`uFuQGll^Rko1gCp_auIJ26T zs+`{EY4Lp~dYUWoVDya;Mj7}@hAN#7JbaLaI_rFgF5Q$BS=|b@ja3QDrt#d;Qx2VU z)1uy}aW$m6fioWu@9?>BcRbon61xrW#d^|D`a3k%MM?AL-G7_43inV$@|WHW6&sQr zJa9fa-`xXtK~7R`k73?JRNH!C1|-$?8o#NZ_`L`Q0#nM>1BWY8bYVB9DKV5U*ps zMMJny>G)CtfK8I_OHQ%!1T_+SgHd}-gKmGJ=Q#_wn@Ew#PX&jBtlVM#a8ODKrm2y3 zZ6bIeK}6)-&H#9IN?KazE9-b!$I3`H3LPEHb$9zWo`r=t=1n3Lub6HE`>e|ot~R5y zucIjDrVw53wMf#jy`n8twv8fA#sbuyD)GDOWvbbDaO7$L6FK1h>7qP{Js^&mx!Qb$ z)>bab$J3oifGpk6iVf~<0B`RyBTt&Xe_}5@{BqHj1oM(9nd`UO@wdoE-W?E_g- zeLv2Fl8k%+3Y?A!ttWXiimeb_C~;~9{3InG;+nL%THs)NgLR__tXu(6LC{A`#-#sRJ z)BJ0ysf^5fhVIt1PGZHvF+k&iY}{*f?}u~|nKILqD!$?50!6mYh=hqN6mpEu zpb|#Hl>W={ww%{2882dsv>mKgCi8HMc=0MF^?Ov1%-07H9f?}>s8suw3y zVWCs0)}qRq!U$9t5KEUt*0<}-UUdo6!=VAc&y@O6#Bw4}KlZ|0LeP2aYJ=ML@Hz1N zb*{QYso;|_{?|!h9Ro)OmADiN8+pG_dIn*Nk_q{j@&JHyRs5z%DLyfkakqn^TPpTC z$ZY(!zMI#P;-|S<3j?(Efpjh~w(3R81O#!yn?L8McD$>`@5Y)y*9Iw9I}GJ(LFMnq zn6K})6x#Y-n`h95;;vT8VjoJL+B4SOkyfMZ~e__ojsA_`?K-(-S3 z)g$l^8FGL=b>+n$p94>Jy9Tee2y3smtYTpkTVsLT^J4H`>-aqj(5DudO?7ACeIY@0 zB4lNq+anv+pp$iMmzhQN1o$#}US>26>XRnltr{HWGMVRoagb4bQ0xh~IOg#o5|i$p z^A8%+^=L4xIQNYKtNQg;y{|LD0FS=U5Qh$A5Ymyv(h0>7z+^$dr7bN^du23a=RH`@xmk{rLLs*hE0qaVci_(_FXs&Wy53U`M<5DVAeiS z#Sjz(VWcx03i(@^0mUFCgfqPyK`hKPJ0xnYKoF3cceL^o%C7oXU0|EI7AHKWu=cLp zn?N&rkeC;-I5y{{2L%|jy2-{w%L)`9?7{Vvpfmm6rl>x zg{^m;!?F_PAuu%fb?cpD4~BZ*VBiL>pl%}(l4T<<%UTF@IxSv3qdeK|TRH&SK? zvD3B7jJc~K-TtvjoL5xl;B*|Pw`^ij1bmSK0=?B#t|6`plNHPU(H z2#4|^b5~8360d&|r?lL@ni@ka2~{r=VvBpbu!bwW{Xn{($bKuMVk<#J2Zo<#-S3@# z0S<<6mEf|n9)$MF1u*cGZQ-R>9$K{sb-wL%Ac)AzlDQBZ!rGZq;VbzA%SL9_R=*{FgCcCsmD`SzWhLHvFtWshFsH3ddFWwF6yIRA za72KED%=%HUBO}L?D8<(*RWcrndkN>$$p4%C4;~Ak3FvlVnR)vUeb;>VcSL>oC`;@ zs0!`_$$v=vFWO4HTEbUuj_Yx8Y_MS}9lN%;;%;fPSRW_dFyO;jRBhQ)6vb9)Rpau~ z=1A(R0olVnnf$s`uhe17nqQ~4^^rqUivJR-cR81tgy1xbqED&PRKt?B81q2k;(gek zvKA$l9m#7jzy+v|0#?%-1)t;34jdr*4**`mxckM;ePXEJ&cl55Ysa{K40gH}sP@ar zMVCCps(sKL(#BhKg_-rh=4uDu0Q!}GM*lPp+IJ?{nak2ck8*QG)WHLbpa{G<`Frw) z#j|ItvA?{%_RlyGn8wo&l`Cb4o7gI&iw_(*j+5CryfcnPW28~l!Ofqb8;{2N9qB54 zLjVfgL0^W2+|jw5W=+8& zHOl^{Bn1jS-FcB3yD3NZf(3eX0HJiv-w4stHZuU^dv?M$s>F~p|Js|47rW%O>KmY2 zMeBb@HOKwii2{r4pyuWlj|;C|V5Q_*u{W;SB&rk6ay)y#t#mwtAUK7Sw82XfYZAsr zD*FajGbm*rX^vrI#)RSd7fq27qqqQLG3(LZN+4Z7T9;6wi(by!LJ#2N2y#5k?`xb- zPV0%oF8%GR>WQw8%Nm;Jw!3*q`}734KqGLfIcYB1@|!ppC5&bAviaHm&RL++;VVLf zGd;`#WIS)cn+?X=fAft0#<-i9-h8)`dfo2iz4Cy>YTaWghh=w`JtJ2p$>r)g-5arq zyT0JI$Ohd8BmZLjDnNZ~Uv1V`)+jDP``&h#oMbYhtj1QGV{K7+BkQw8oV&#D1rw-d^$Vr=uJQwkSwwh$rei|2}0 zx{?&0y6{nuMcaD)kE;z*7qbJN<7tOEFUJZozhg$-@LIjnt4G+!Zf8k4%ZcKG(-J^1 zAC8VtGca#`ooy%rt{V37#2Q_m|H?Y&H~1=l(y5}@R~$7tvsuEUkG7=Rd-d5r&Pic$ zCs+sEJz zuS5mK>jn=F!JZd!BlFQ`>^6fo>JC6h0qn?{N}}`th?td%dPL!t^bK6u_QSkLwK*Mb z>X1A9r&%NB{)m!Ptvj~(oa2Gc<_0XULc&#(xpZ zJoS$S*x06U7j7>(;Tw?BC7?9kYr zrb0NirxP;RBaoMN{Uk#Np^Vx>y&n*}{b8E@)w9HzLQfLYOOL#Y-AOpn`ONO`U2lxWGBwT2)N>n?j~hS z!iO}x3owm;_ue(RWW+1_#+`T8-Yy21tfjelWQEdhApMpX?zdf?@;dB^OmfE@4aa_c z>MoKTZ1An&5=6Iz_`h_%F38&_zmKoj?P{HhUP0OWmoh$*)8*F14n-ajx!ESr%mm$V zo({g4roYD`@AE9)NU$*IY-!X)0I>9W`R`!xSfI`=-sq?7Dh`jKgxWmGyRvU7f*P13 z*6}sv!jz)7KUGAhGy?F;N_6LXIO66TDk@4keL4~I=Sndky5`;S|;V!eM#e=9a zSIf9vT4-R!CAL#73>(au#{$PB$+Vs(WEs2_MOWlarspV%2bs)nC-nWM4XN8a{&pc9 z^O8nnV&NCU5uc8`r3ji_l*Q+i?%nDw%WpD&+bf4z%zkVIfnf7(hNp3w8-IWDX!r6J zU16^E6eqZRq=C6f3&mD_dS6CZdLz}F6tlAHC+N0oqr-b;34GThy z>hx&=Gs9s9#pKHhQ6W_;<6Bo`(ui?~pM_UeHdnsM3a-?!!!(ij$-or1GfP96?JyVW zpn$Dy+{;jkqB{Z^wLZ&GY7!rH_-7nb4#%VJSW&102{P?q=VtKO5o=BXoWYTm8Vm;G z=Gb6lxp6_G<*;dNB`=nXnO(f_h$3)8dY$*rXud7TWv}C;i><1)TJ7GPWt8;D37IZ%hHV&ibw=Z_gN}ZrXm(01iLyGdf1JoF z)S|fh^7$;O8J@0fz6B@$kj`{U9zhX=(vjMxboTm}lD4yawRp`lR;Ir|hLK`RDp^$@ zy0!zKMsZEFJO=Uyy6Lh1mrqB-hJ(o*n>z!=LjH78|7uw=Lz79(KpQ>N8PNP>+UgMP zcdKhtgV8}C%<pV za881ss6Uj=?mAwBcW=H3bj|rCEd@Yf2pXonyO?sKx_99mUTh|(sKj*~sBK5yLB z=oM{j{uVedW)dfoYPbtea-xjtHC^J^&~RJHtTdGyH+*(KBM81fuo!zglVm@%Ub3#H z5T!wI8zH;2Y+Wl0)W<}kQ;{8mzZ_^bUg*A$Y}(7Rtv9l+t*tEiBHywR{Y*bf;OQ|mfbt|rTk@>4=wI!0 zt|$yZA^lQ++#o`U%~IJd&&193^8^}EL98m$M8-#waKdcg%(*XJUQ#Kfcr5lD|; z-d32Do5+;gvz!9U_SOoTL(J8ZQVE=IzorGf*wGt8CNwVe?XFcLm5UE(a0epa&dnRPG2iDw+bP0xboHorB4Y-@5str9ze6b+sfp z4uy4%+UH_-a{Tzt-;c7$GzOxWSP#}SDB9gZ#$Pc1Op9m4d_l6aQI(`i^@z4=UWZ-F zTqp&vrSi~|&#U@6YB6i3NF z$zidiBIfe^dk2>LcGiU}u4aFC{7zwO)0x6qSB(Td56gCRM`mn0$ieR5Onr%fduByZ zO>&5zoV2ce|B+a1jCjwE`LsNnlc)#GAF{G2;*@Fo>6q3Eh%ZAG<_D&YSYsGf47fGS z%TsCc&B;RB<-ZCi8xP|X4AzJ!k{QadzGy8yXxL)ksU*k8BMp8dzFE5wkAmE5L(_NLTUIzhFCJmSz^|k7M>}^y z+S&{QXK5q8$av`HW3Vm284|^|M`5ON%lL7bg;K1si6WH~p$~R(R{a8Gp!4w^5%(_L zr}~0V5Df3BCWRlgkuzOU8DqT$Awz z<@^E7{RhucC(N)V9pWcpdOFskN4&b5-q`;?iU-SykymouiaxjWh`0K6MHz;E&T;lH zOXj{Pq^i|0HlW8Ea&je?xb`#;e%_RRMnHeQ#ZVL{l!@-B2$~^!YzPJv^SAASWGgiT zPi^XjUt)zWxz5IRJCe^+W5SS57Nz8Ck6&(mgkziYe50GdDv($QrUKHN3z>5=Tkak-OnsV5K;0 zyPx^V&ljHqDTUXL6DVuJC(IVOzdp9T!}WXKL(Em3N!1}8ETqf%nf}|nn9`8$1)Q7Y zgA=s;kh!A@m6xWtAVn1HkO1Y?Sq#uC()5;%AUAR;WDm~f_0;f)3o zaPGJ#o4Eb=@QQT^JmXZ0ed})f!#;xS88vSpL#07fRE1? zul8m@G#t7kZmECN$Ni@eh;^%v3hde4Hwn+=U^Cg^pl`8ixB!9c2KC}(X~OnWs*Y4O z45mFGBXjTLJ!r`Ww{m8No0G3L?^m6LO#<6bDZ!$aNi5D-DVSF2gLmsyJkBxn8>qc% zt)0cglO^mc4!z|-FfaPfd;S#BEn-cssLZ9c+Pvx?6r*E$2zK4^^i_d_R+?&VN+`bU zYx6p6oe3SMKoZ3*4Nr{8#4i`gbhjm~vuYGVy-SgywQTjyu_d4bLk`rk>%wVvPNvoQ z2;GD^Xv(lwzG>oMtd>hm7Xp=UuB_=qO6t(~Us1de`FG^-U?aO2ZJ5H%Au>_!$^C#* zgDR}5n)p$cI%7oiY2tnpao+y?^VSi1wnGf9)#5B8b#@sMSgjIG|K2HPxiGMHe+(_A zim-FyRZtT~$k?H<%G~tLEg7Jkc%bfkbFW!jh8*HXQ1;>oyy;1yZeGpP&ZFCcHL@rp zIiHR0lY|wO9I}-e4UT+z=QR`4fG)&wSgU=JXT*xceI646xS0M=W9lInf|bs7-s1qa zt;9V=*k-{l#m;JM!tN71bt;ny*d0$9Z~DWo^sr%{FGk)8MPy=U^6o}@CTQGR*re9& zzUqYY$MZN9J|MNtPf|H`k%wA>k`Nf!L-6T7neR0pQvgHL@lYYo>y*}d!=?*YIX?(+ zD}&FS)6s0QTg=S<+6+ta|1VBcu13E%=?0kmjU0bRnV1aHW^G3Yh|ecHpC~4{@PUNs#7~a~$#I0GfIVP{zQ=o5S&b#05U@=^v$+#~qb_%9abBDw=^mD>I>*`dai_S9(A=`#t0^YxI=zI;rY|!J0-AEG9#D zbAt<^!!>{Q*e`v8TX;-{!Xd}KVD#>HGH^>xeeXYxOw}Y|kK;y83EsXP{!}2f>m|(p zfj>@vs+oxNHQnV%`SPa7)S+H??K*dp!$k>-@+Tf4bD5P}N;H^pn}K^+cSG*?E@c2? zr!-WH^?KoL!sSC`s-DF!&w`QP7Je~pxgYt8em5&;`Sj}T=gf)5Y1sc8A9NgZa&o$N zLn^O-d4y(`z~Zi1sw?-{YFv<01#0#Y1CPlI2t@PrwL6<+rVksXL|kf<2$b9Mv_67+ z1ks|96}DDd=t3OVq+~?OWr_HGZu;Qh$x7Q-@HbU9bJR6-tYIwh<+@X1l1rp527262 z|A(kD?X!pB5VEL>DXyD1^TDR$hYlE!XFFIbEJR~ICc`5ZGxKI&b-6}0yqA0zc7LkB z-gogVQi@Xq`{%8%vM?jw50U@L9M~%KJaF_=M1L5eCwfzB=e5iR7vO8 z0n!fjyJt5U6=^|qJ(wzdsn!8S_$mCI#IWe$Rtj%KmBD^{57twIxk5%L^r_^QvKz1x z<>Tucqt0v4u)As%ga0`1rD9%o@M)=3CplrZ!WsDvfGBoWLj7D2Z{us(QdoCBb1p0# z`ZEGo2Rc1PlO~o(swbS!z+^!7iw&loGdQgY{9|En#68=hPu;j;iJ@}aWW4sbG7y^dB-~1?`dCv=dteV`8-?uGpE=r9;{~tq; zCXJYM)Xg>BdyjP7Yr!ZD;PukYYYf`%SkQw31&l`_b2!;r$(+!Q_}Zvk5>opg)Me@D z56ikb$je_%uJ)Q_1EQ`IuG$P6Sq-xxvD(#MIsj4KAAhhSjQm^~A}4Pp~zJBTpm-B(0xocw`F z8^4de#apnPJ7Q5BZnhuJ?$5v1v?q0CbHU7+{Nfa_h4kak=J2c_8FG9&Xp=C_FBd*3 zdn54ct<)4nx7n_G>wym7HJH4tf{FNsN6QxGsW5_oqoGd$#d^%;PJr0*9*4t#*>vf& z*dD-^bR46Tv`q6!{HO7C&N1Qa@q66PHps49eroOKaK1s~NSP`C1st&=;Ni96hA|(h z>U+|Q?i(^)SEI^!(_^=E_EH6BflDv9sn8q<|6ZWX!Lb!J8GKq;KEk610=1GY7+36@ zo;#i>&apWWuU1fiCHd1`S4jN<%(F;k;?E1}Iedr#eG7+5K~hrv`W_zOBIS3`hDOEl zw1{Uo&}se<;2@hV0YfP2paiAS!?=E_pQs18nzO6sxE0RKH5##@9$midH13OFq||E= zrrpCHk8qQao7y0Uwz;j-O;N!zA&gnbQQ_VyHThL!RLUOi@wzRL*+g{wCu$MZtwoti z0}kNP8>H*-(*}!ImKmIH=`mv(2mq2P>VKC$l!hq0PZK1 zF$&`^{AK!aMU$71UH9EOdVSOB1A7gP{Hf^Ib9Jg;=&up>#3bEQIsUg)isxZ#$tSQ4 zv`GHZmbDW{qRjM)Q(o6ncH%U=;iCeNTNF|p2w^UN&FiR+e3f^9%DyIUWrY|Eopg)K z$oA7@*C_5zlfcg#4vU6;i5SXPC=b`dE~mkGy;Yx3!7K-jiVc8>L!mBhOy;A@1XoTF=Bcx*=8(7ANl_K#>7H zS+cT5O+)48ZW~^b&aRR01XmlD?d4%W&?>`CpnyMQ4o+t~WE2Zu9%UXU=5NUQ;Bz(9 zLd_?Gwd*KOr>cA#!Oc)lx7^=~7I-tsSU!Vx-|6_njpRa1yXu;dvTl1wZL)V@S%5^r zsO*a+dn%UqfxB812`tqI%I~31>l2|xPzs9@#>TaP~<+sGr}^K?HXTxBF3>k`KV2LuMS3CY?BR&856=q3 z??sJc_u14#?VFoNo=rG(z)QI-g*-Q*`%@;uea#wMDG+^+gV`{wJ}kv9iV#IDQ4>6k zG@aveJT0^;=yn7iT&C+B*{5phs`mP%wea(QKfm}7+~eK9TH-xN*0 zYt&u|2wg+Cq)+usffPsUK7na2Ouz?iVZ?=M1^^H6uwFP+nBTex=HR!<*4 zPnlD?7L9v0y()>ONqvm|fE-jwj2WkSDaD{4VO9bYFcgFdf6MSPzG&F9rlahZC z{$y(CNs!QNz}55uu^3Liv^iI1zW9|jG|r(~tZbb_8m&nfq_K-8rAK(yRR3-lNL-|9 z*V&RL;mewF+dCiju;GpY@|>Qf4s|f_!R91Cq;_$u^4)IML&!M~5QbndyXd!z44rFgdFbZF3q)b{E$D7)%h=>Ecg2`Xbw$$BVTT9r; zkdaQw1aLRS?4+FSBgTcGBbpiE(W6H3hgHEiJdG;S+qH! zTDX2#ZU7W*wnltKndBY5XJyyDm?T%pTqY$WyaLjgV{|2z})#kGR>wmSbSyz{@`|Vh?QveB!7XB?`%MzUz7>`8Ravsp+<;{Y6oo z>S4*6ap~MUFV~@wuo;napP%(fV2XL#qQoR$C0G;B^{1HqT)FtNvzo1f-1ZtI@ru>I7mY~(p4@adP1PFAmH=o>Z{cexngjPR0ikX#~ z6O=PoPW$E6r_*qN_<0vawZS^gfs8RZD8dOFdkwI^W{@Lx2)uE@VF<<1%kl=W+)AF* zW&Ax^@YrF3-U6T*yQhBNg>wv7CAFg-vAHA4p)G0xv9nyb2rei|zH2AZE~~iWo}C$g zrYy!5W?FfrK2u)LXT^J>f-eW(H`($vn2{#u(?afzVzcHTp9LV&fDSf}VjB1!;8*FUYhqGdAE=k&&@&K_p1(YnDRw z7167l=7WXGn8N-;(}JsR21lB6A`9wd3L$BM!xW+FPJupi2PVA^N10Do127*l?Jf@m zY{fk_p7~p2k@&9ubC_V{5Z(^u1?tM7O5d2VL*~RPAZDESO1bk0x$sN=^?FblE@eWn zX2f8)X9*#hDVz#N-S?px9iEOO8S{??jc=9G9k<}Uv!{LF2cMA3aJU(@~4#RC}ywl*|!Bikx0X*}v$^l^-bd@#WYD{0Zq^HXi zmWn9sE*D`$Qf0zmU&z>J+8F0c6cE|rR8VoXWDpAh8oqq#eO`}Q6sOqa->&^r?zNKq z`*LNgS4K8NBk zViQizS2!Tl*a811s2uc?e{w^D>k~!r;$nXHg2`Gi02|ciXPTUPNk{Xmz8g);6j9mN zt&NQMeMxX{S`Xht|A$W44TJ-qD6oti7qF|XA~Y^Wj`LqrZ6Br8V3y<=Z{*geHH2YE z+uM9exqql~cK9d0J^vIsI!Z2-WJ7o?SOk=w1IV&-z0p_R32YK~G1XbuOL4mlTNKcn zfKWA}Bh6$m+42bZ)^6aoCFHwc5x6sCI1tPg_NbFXA#6y_|)#uy?cP5FOXPO=gjhj&$WU2t^I(@w<}#N{viqT-fg(nAYs6 zIe~=r#36i7aP@AS#5^5akP7ynHr?-!I?eH}%xEqJIP_^2VTOwey|I8+GCui&Fc`bw z&UKefm@1=?TcKfbRp_TW#$uZ<(MG-cm+Cv5{xGgHU=2{)B{57O%478IYXNSJ6Me%Y z2!zCf*HdI<2%Q$fKyM8c)JJhN5r8QTi>_pbV~fw9N5HOm@Cli<+{eqGhPEMdI||F5 zqmHc>S4U9=rumg}zZ-qPK$3&oNh~jmkdf*)G~S&oZCxmtsrJ#oL_uxBiExKfwd-d5 z&SI9(_!Xz_qXt?cOf%FvV#~a-n-Uudyn&4&NVvmiai`Qg_cUR()I9JM9#0Yin|J-& zgrO#>pc*+C2)*1LNg^wsYB3Dp{ffa>G(%>SrKj>7XvBU2CO`dI4WaD#<9|OZwl)Jt z%u85$55~-xx!xA&;FpU>k!g?jGaP7L(M_$%X$!$*36?W>n*8cpJ3lbLB;HEB;~KV~ zfx-CUvwc}nI&O*G`67{1ayjtktxOGWTY8)!xKWCL)|(l3SsPUD3SUsyTIy}R%Km9V zvjfm|zF^Q#!6tx4)S*lRKas=nEy2< zhapn-2H0$g6^J%_?ZFuBIm_vyny--h8XvGgh2DsfRE{wP@V%s)qycb8$T{K zLOwLD+6;zB67CBA%7{{6bgdg!d&V}YkTz6pZdUOMi|;6DH1;3^&Ux?;UyIYM?XY5! zx=Z(B_oQ}*@8GLiUSV!s)t^@nb{Aq{@f1@SHm_iB0UsnK5X+zaTXn2TWz|9!HJf>oHq@SP2lgdc3vGt!>o#Cbr5agOaC8NO&QxZLM%5B zWqCSoh(!vNiOrqh&hMrS4SJJZl6=1D(4^PEi8oh5GtV6Qfj>Aa{m!o6?k_b6d4Ny5j~m z_AUq^3r{AnW_6kOd!n+)ZN(sLPcjJUE!1u(=V8aupG(c-?19W?#unjr!<-vySnZlI zX)$jr%pw?tzgy_A+#8|6v_o-K9ouWZx3W}pcK$}jtJD-SUHVT=EGrB~rPf&D&rr$A zQvOxq&eHfG!dYT-N!(hV)DzQhe){X1KEY7qvkOi)s7JR$kfqPEg4^B>RLi{xzrZ~T ze#jn}T`zO2pCb&Y5Vw>4zZ0m(aUL`$|!vD!3o8{{YcaOI+8 zRiGrP1KU#*Uxk&qCQybG>ik`!onjw$fMk+7KU~E}T|uqc1F6k>6roc866Gq%rd~2^ zpI`61r%01-@p%@GF@d9a{e6=}D}nZRlKJbVk+F;>T8MA_q_{dS%}Kq=#HX?KMyOL54tkXn??bEFC++e+(Ya0MRTKK*Ept+F>11)r_cEPFA}M^%vrv>4;4mRw7U|| zIC<^+H3Tg{sEmYya%kc}6=IaeG#TrT{5hZb!;FsfJLQw2@4r^B2A`2tFu_b0?AIX^ zIgo|ox{LLBIb!2ChH6HEdT%~Xl66yG1U1Ku9`bd>aI`GyiwT{gF;+Cdy)X$z?%$7BEAJKk*2v<{G6 zH+~&uDtrH~%`STWL5omDC(j%(941ZJ`aeYOC2&~wBOvh!5H@FqZiWiyDf*gsf@|2n z->xpKa&Qr?)^^7Q__R7Z;1L$w`z-MigBDVMngC^9mm2o1RKS`9OzIBh!h{qo?;%MS zY%&@Lng3a2WO?f>*F%F|_)vuF9W6ZLvDjuTOT(=yBQ=Sj zWlLU^@*cGMRL%>EVh%bI&q#od=)Mx@x7c&B-s?5q%VvCT&4aJ*tSa%2mabbZ;gJbXowmpn|O(wU~K~SyMXA!n7}&sNyZS zxW34gU!$%5pJ}OUE;!o`8d* zPLM>M)VdzU2TZWv!Dl{%ym*?l8mKC zkZ&gMNE)Gozxqq{IsNN#Bx2W)Gdy1iVLxv~6xF^PuEpd%55-XLr*tK*uZng%neLre zQ0El1X1;gJiS<%6k3Ym1P5a-INXD8;J1$gZe3xc36JKnijYyP1$Qc3;zj+~<4)dWL zwl2yLE5R6+dfDD1AUdd6JHIp!&dxvW$QxOxh_WxQfQ ziN1lblBu#2&BW`lBZAxPGkV<&e#-_s;zWDbe+|dSw*7PRMH!|{NE5GjTo4qlO6+WW zciK=_^+7?G&2y?z8CY=hDZupxcsPdx_xt4{^2sFgD5Tu)YTjGbevY&r6{2aG7)_tx z=>DiId0^`E$^o}5ajX=MoRKgV7Fn$?6B;A6IF>p%HLNCeyFPJ_rQ98W!oh*_8DXBA z{NxR-;5C=0arF9N4x@ceY`!_)(6wIrdqueh;!^AW4_k~+;G&Mg@KA*i?y`4UV?uzs z)FxiZjDy?Sc&oa~tFb#2Q4@p1Nf&*jZ2YB^(YOj`UOoL2mrS=^IOVM3;iH+2zymAJ zaNp412Fo;zdgxcvA<`Z5o*^6vUz)ojc%!#}#SJiSr>LaBY%ee+xPG}zX|KHYM}m9x zxSI+`H+Qr>bB&*S!v$He=vR8mTJ&HyvlXy99Ca$=?M>U*+GnBGn2(<`4=e!aBHuxX z0-eR5WFDKs?h)OFj*StUOcAfzB_0PUp3R^WDWWEVk#MK2ui;2!-(%_y_wMmRgeLQ- z!^BCN64r-2uR?xx+0>*L7dWxo4~HSq6#c9f%4X3_9i>a2Ci(}Ecp#gc#>+{1$t%%iw4W*06{>$ zzoXscd+b2=dW5P)FL)VP!llT_*=wum!sEoc)Pzm2sLZ>wC~h#ukV}VDvK_aj+fL$- zpkHNX!>DH?m^G{;-{@1S99bn?(1L?q$Dvw+SURrjiwWZ! zg=R-Vkq`%jNcjg20DKUjauF1K#)GRE-wPB?f~8`CNTU+WGmUi(fp3>BD4zS3_MT)q z3HJ={CFKHli3D%ucYiYx$uDW*`;%xlQ zT9?mBDur_@uNZPJ`CRX+^{0`;QyHuQiPggx*ZR%|Y$9ARvX0$8b_DZuJAi}F*zrdb z_Y+C*wS==W2`h@ZhwwLm-9ei?CDRrLn`r@o$pWQIN1x(Lg-6^t)y1YawWw`%!N=KH z21*?3^}E!r08WaABqYq-XEP^kj24|0o!(%1aF0}KEh-@qKud28SANJ%ztCyX4v5Gi z>z7cWws=R`jW=HV@YzRZ7-P;5u}s6Ah}_~eftyNNQ#uH8487rY5(R=S) zc*uMkeIp5P%C0LXd@6W24VJFrRbkQY3EM|@1UxM#ngg0UPS=_aHt;!sm#lbNkM=$e zXJ8eeN(6J+cvZ%mj^z1F6P~~%Ze2A7d}@4Bjy;moVAc@-j*q)V*xFbWaYohv2{Tfa z6J&w-1h$pCu^)O95((JK45Bz`z@e8^*Qw6vKPly;aWbFproou^xs(NTSLh)1|L4z8 zD6FM?_mrqR&zFsQh#UH@(!PX-X9$>d>Cv4FlDcQwRU+|3D4y{@ngWQ0MK^YT!aJF& z=Ju1r%sWBgGx$-q-`NEjXCVc$u=CW)h4O4D%S&@!&ZH2RKa?nJS3`D^D|}gLV$1Rl zouqlI4`0jnU{EcFRofY=-TF!%?U>m2!#^~ntdxcD_{*6&0|T(+m1$H3^XvwNae7*( zXZrh#v)e%-p9=6@g%TCc>PH=d)-Ny3~6 zZu4UyD~A(*74wpvW8bS5Jhbesw#Z)7&pQPP7y^!%ML;cn+~A0%Wu1+h%9z|Q+8(5$ zU*Wu-*_&NErfpg?0gJIB(M9C5-1ad80LL-}x3BUY%cv7hgLAT_3Z5_$N&L48A5h|F z+Zc8{b?SjM@3p6T_pKy!iiuz8x!FZfWFRIR4v=lw%wIN^K{fAL_(D#H+<&BPeO2{o zEmLt#K4XUzzf*Q6RvWgOn5#}H=?*80u(e3ld8R*b{R!Lf?sD7f+|5IYg5{;n@^@6z z^F!Cny#Y@H&9QTRb69vt#$(vP{=kB6*;%C-6v>hAQ(y6DdIX!!iw5B1;^=}By_U^8 zb=C5AZOS6YNHH)lE#ZGADzEHnZY1-_5{0+aNE752^p(_}w7YLul6bz`Pf&4~^d1l) zqWq{nehNW|@f2!!$?W-aCB`2Xgrjtlk8tR<;S(au5fJKz;ArA=BLYq0Mm@DrzcMH! zB;9vfOOWSO@&TJv==ZVxWW1$J2l+b08_mquy!}cWYSZs@*GUo#HaCamZO~vJ@#K!Zxms5hQkDhuQajTC2V;Sj{AOa9DHbkJU&wpcA&7`%msf zzGJUfZcf@y(m1~}ZPv2dVC{Knyd*=DZUu0YExG`Op(5M2>p-{!$GrL=rFarkG2S7e z6Vqy6PMPbq58{E;5*Q)08aI$`<}8%6ULq*7>cJjNml;{ii_XDHp+p_;)Ao)+VPATU zLHcdkuFKHfAZWjFxFY$|MD7<%&kN!+YW3!BHikc1&)z~^RLvI`=4#B~rw=7W@Nd;M`qnW+&#^yo6dVh=jn7yMp3QLH zAoE*o)TG=iut>Jt$^8_tBg%wshl3PQS0U4(6EDqzkSJ%YQ#`GcZ583&nFhY&RWhWn9FuNHOx)(*$#R)PQ@g-MV~czPmr~ zP6p1Yr1JeQXeQGvd^!Z9l7sh9$VZ{DAGahlHdASaiMQerr>_7SkKV#anEmix0wHgD z6(}cyqN1&h0z8FWlju&9-gmQ!+3P zHQbrv!DJY#;ab3-a2>pgz$*-04yuMlOiz3hYazIpGrQ-}uJhtERZ3Jw%gS&ps-ql~ zGjNC9IUO{mUG=Nv#$6v)F-ob1Bf54i8KzIBdcUMan_3EnVFVP|k2IueCn~^5vhg48aKoF8>9-#ZM5{Gg(~RVR7f{9C*rs*tKzstNRwg+*l-kT1q~zJ+z_Lv(c9FFo5gNvbAQc*5f-99hOXMmN$bM0;Yhnuz~1rP5~ z0_~}U^MKc2rM-|(JW~#32LIVd6mxAePeg9GJ?04w%zQf;PH;o`^+ho#&Ul*>F+(Km zQ8=_aSmDsiDU5d2;W0!+Gwyj%?E8u~2d#n9uwpco4mlc712%ov4KVv8pG&GdlIhy4 zlgV6vwmS9N6RlzTpg**64nLLZpYjj(i|8|m-za-0vu71)??Tc^iB)~D{EKFMBJcSb zi*6sgKmU}Tw#Ar`(_znEB{*XFHMeFND{x)R>og+Koj35HI8=;Gm~>!&!j3;7Z(xI( zawT%&sQIhV!vnIxv#=;4A2gJKv7jzG!ogZGJ6mF$PInzUFByawB zlWI6>5$?!nMmk%Lw@?B~8)13lTZKsCGKM!{8P7w@GfRsEs(NF`LHLw`T~*iG6P&<&d&cj}-=-W(2qEO$BcoUFBRjaR9BeHbfh=1y2 zX13*E$F4b)I$IyDx0u+{%3ylo`D8nJW;~snwT?i)leWyM27VFI*{NnxzdI2X2V^h7 z0hg_(D6CX4X*Zdb0SuwnE1#F=8Fp0qxP?^u6e1yg z7((-JWT5zL8hG-q4s>0L%H#2buze;EUw_}@a%n7QA`gGvSM;#d%^H?U0*u}YtB|yg z+svnvz#bHq#Cm($kdaqi_!@8rHZXFId<(koA9^Tw7v>ec&AwG&mEuivJ+n4@%s1cG zxeBfaT^2FAqlr7djuUN^7>dA#YI=q+Em8py7g+6s+2F(=MufIGj9a>f8{ud-M|J+? zph+14;h7~6f=akBlnJ{P6B$riJM68c3Dpod&ebp4Be;-Q!x|M+CJ2%Y_uyJt9`+Ng z;!A^WLh&GBRFra=kQ(>@zvl`nsxR2!);T>JD~fZ6QzTOQto;Iyv$X9KB3cK{z($Z>uW(MEm=SB4(7d~1d@dac zwD8t>LpdK$DH@3MnPqIoqn4MvYN{8otr>T+KXJG*;3KR_emQCt$AZK$zjW|W6+D{* z$pdPc#rOE#TfK>J`<7WQas^T`63X)_`y4?KF5TY)V{9_`$eU?^)Txl`dN|Q38x^w& z;e6$<3yT;i6imA^!A|Uefb!3|F1KbzHoo3fHI+)~(0~SIpX{BY547&^{nvDy75Y}M zGyasZ$w1f?=CBr>^=~4ICPYjs--`zbdhKqh&7HB0Io0o~axd8J2Qpd(V_9Q;EfmlM z8>kgS=9?hJ!6{K*ktb5&2F;BX60agmh2q4n=piI75<4(OcNiTCe*^P++@6FwAxVvk zXT|k8`Va79fQomQ3{2igIGi`}sSXa>&1EP^?lubZzMLs&AnbVag@g zOWWqOa?1*kbpLT4yi@O}#YHA$Bl>}vk#&rsb4p54)4eut0wMA@2W~je=POeJ6tq7V^edn3?%8 z`)BrOx^4!61+6QoItmCXRX9QvMP;yh!12Ou+?c#(QeG~=X%p$Q6T7?@m$B(G;=x@K zZ}DCLA(BfM6@QbDyJg}YVSe7*=`d4CZq8b-T7ZKV1+$T@D)5D#W9ZH&DP`I&dmS!2HDmVn|?=xX|R zZOmAccD0DdFOH7RXDqP@TT92liuX9L(Ydh%2} zqXb)0jptG|*Wt4~>p_LM0e~Rwl&{J_a`drpq0tci)Z8YCA8SZ%-?8h!j80Z4sLA3A zUnFEsilrxTarrP{dZ2=Q|46LPzT-ecs<{?Vtf*5TCISY!v2oV^jT2{)KjRZf3mGUT zpS8z-r0^~O1qm*bo0-mhpWUe@SHzDwRPT93Cg#$<-Ka#S{d8*papW2OS`oKJ?~dzZ z9fP-?be4AKu1T4~s>BzsvL6p^n#a$2Bzv+w~ zFu5>Zk&H}ae)3iPy9O&!{&5Um$NnSvNW-%J9a2xVb;ze$yJn+7IAw5c>+jn-eFT^%!mYMhzc`y{By6T-hA+l29csu|EA#ZyFt3Q_n*$w zI7T?+%Awf?aJ~}nyvK>v3c=>X5I49;Ibi`u0uHtA|5KHvzO}<&FpXwuOtvM`^5a4h z)P`scBUn{mK(I!Tzzxyx7UQ{?d>4??8pf>Nr{Q2Pp6&c<#JqbwC{L!MH^&)D0MBP! zR2q(+8Z`b=eRcYr)F8@j)dycWaRygi!(D=_ap8{}a7{hQ_=(?N$EZfB#QKtc^9Yv_Oq{NO-ew}M zSTSQngQ=@9f^`UR*0Xb#re9;8ZEURMdO3M*LzSBwW}oTBkLEz4Kx8QV!R2DPa)^_Ad){6!K02N-EcZN=5+|F0m0w?cO52W_J zC3OBx4OF*G-tbu8%OVDW#?r9p}TM-sM7QYCYhZ@E4z{DjyGYZLM(I`_hzd@*QX^= zMbCDxzVZZs5FElT*=#kB`!R-jw zd(3%^-e@a8D#gnaL$qwibH15JnI4^t(w49ys@DoSU)$_23iyd)NGkyjjv=7AMcW(K zlOHdVk)2Og;4LZkpL{2kNfYRdNuV+v!_LTca6M@onj~oH?6@VCQUG&cdFQoCrpiR} z)Sc;J0?B3Wp?5fy9I=A>iZw8>r4m~mt5Wf9j%;qAZwMr_gjp*g)naIeg%3 zbgJE{9BA2{^vgx;V)7yjV$ZvS7tCO^kjVohUREElx?m3giJ*kvyx03+T7d8+`L<#>qKldzJQK+sWT)E`9V@@)|nr1fs2$_?u~|Nl04aEUc*z6 zWA5(z7rJ^nW-_d~VoH^4xY}bcwWc>HQ1&#UasaVF@SvW&BO;wl9LI7c9dat1q z)ZdY}L+RpR9)Q*#_ak!}D++BoH@hyZj9S%^Tu13-|6s;8) zSltR-1__(|1(Mm;--Vu|iqw!D4JCLUL&Wtxk(LZ->Y}Jf-bcp8!ozZFQ4nfMSa$j# zgbfcNQD2tXL95!d8UrOgIhvALld^ysqN1v9$uH&qgyL_jd$1Sm&X)zrlM>hBWf zn(&SQwEc~_KN$7e>GIRMlZDq((3*5^F0}=dirk?JqkG=b7hIk22PLL?#6vp2X0zD= zXvTu0x#9~T40b5u2T+%J`szb-=7FktLO9KgmEc#wYfbwewFtpMzyKh$H08=3`4F0{G>E zr#YDUX#>>X4gt>leFx4kBa>jF9Z5PM4Byn=P|X;>5#;W0BE{M;S}-E?*1AahzcUJ;4Gm`x$AqgS#GU&f(cc=UE{|KAC?7bk39{h#>mpYB(Jc zk0Qsapr~j-A311>@AAHft8#x^dv*Ti2sv{^cG76~qub`bp%nLXx!BBolQWjr5@I6D zKd5^hY`F_Tq^wj|XD6P1_Wmyt@FS{Sq>znI^Wp?F(0d_DGBIotoN%u?*3PG_pEGw~ z{Rka$D=x3T{N840?cXk>W4Zyxz@{uK-Q6w|etBViHg-d0l$S(>RR8h-iYq## zwV@_@!uQ}-O&b2fQzCqcpy935UEi9B>fSZzw@?qyLR=I;!fSs;>Fu(3J1-%RCSh}h zd+^EjnYpgH`{xqNliyWmkA#tx?xlwA?16) zmLn}Yr;ddQ6TR+;JN1{?VXx_i9k=k)BZ`LSFg#yoK@?odj6X7ff7)Xq+P`b29sIe2 zg5&Ne8c_jMOt|-x@l9}&b?aPDs%yN1fSk>>bQMZ>Bg-jEA{`+gX`eGQw%{WL2jFTC zkx0wq`wi=1UCp$6EIq&C`w0^`l!=#u=B^{5L(a;<1(3q+8op~pb0C_A?1q6J7;ctF zW5IouJHQ^}yd=9VsY50q-_4`hm4hu-VqS=oikfZY0EWa7pzW8G1MZK~HJ{A81Upyr z*f%(r8k+5{zMtb7p*mOJ*#u%!EB;=RI9lwf8;^7~zXV)~6IP=^IQ39%KmoM>;FLXR zeS>98cE9k8yo=tA{^(T(OCcA!F_(p5qwCIxACL>3WdzdkzfmBj45lmJk2U#j^lW`_ zEqSP7k{JSoE#XMy>Sd~#*n;Yq+9mf=o~z*1otiH~b8)YN(ZOf9P;Fu(A90Jcuv*4j zKAAPX5j?bgehYGkvq(&0wrr5R<13FP$Yt@EOyX1><>-2^Bv-19Wd z{D?W#SXqlOU&{KBMz7as`0y5r(M9ko#}@Eg(;J#Kh4upls+`>SW*8rZZ`JPrH`Des zE86mo|Ed$`JhW6!+{b*r=ex=?V`V28Hb|_8%OSUC^^UIS?XEJ`e>*TCH&<9=&#P2( zN;cI5u?=2Jj)Kj@8Sqo`wa2W(E}F^SDfh81?~X-Iy%j(I5}xfXg0%Z-t9v9nqNC$G z`W)@tg$kuW>nyeu7DuRE)D&r_#vI&MOIXmveeY_N3;Biwc9B#8vv(75F;FmBQ~({L zW7nNb$u}h)<`fASGvhxWl;x(6Kdll=^dS3(WnGpMT&hUUKlb9>VT_DjVwQKkG@NwT zDWYFOKaoR-7+wKTw3Is*>39yz$9R)(&|G1(IkvZ3F}=U5VA#NoT@2Hgkv=1>3d_c8 z!MYOtr3&VbW!Ko;Bcd5~qH8ei#*iBgcE%VIOctK{$^!rmcK^b>*cn&{@&94PZ9rp! z2!|vUB42L8axBF-hu31nX_*-00pfe4HLd~cuMFBAzz(DVyD`}}L8=x4Y)EP|!}0m} z=BA)A3#n7Hj0}iAqQRF359f?8&yi^Pn1PL&a8LQ7ok`CwJCSHuYVNvfi}a2AwXE_{Y0Zy;y)jn6@X7R^je#AtI!a?4f5C@{bFYn z5$t*IKzo2j=xi7Y#dD+4m4-iZ{TIwX?W?-fAXQ?5&*Y44CuE^>(zZ3jQR>R6P+F28 z>*QwJDV(o^ClsbQPl~zhl(0ZqI}0g zUn0yZC9}KupTT**1a`A35?~Vd9`)i?kcGltNRN^tQDWjAs^eBOc&@Es7^7cuU~aG6 ze&vxR7)jJP@)ne=E0AQ9e3c%C6&GbZfn`EV15ubb+3bpYc3gnpERt(90PtrVjf{?c zN`y7=%!A3;PwcRGnuO-&)<7mIcE7U!qbX=_=0?p%LyEw=8&idj*$vO4uv?Y>rLEqZ z0ej|1%j%)1G$mw@Eb*6(K*TE1Q$tz3P;(z{0Qu>BHrw*w6;gRV<}%mWpn!2V%Lt%T z-@w7;^BVCu_lWR&fzQUuoG24flGrwZx)7>Xe!b~dPq@E+D=(`#{Z?(qa3|e9o&Dmj z>&2P-7_!$Zu2&I!SJq`x1FBc{4I`!>5U9FvCjFZJBiWODIHg(NIMNCi1#qvUOgFtb z_V5HG6Km{FH+}ebsmpJFJ+h-fgC^DR%pyO#nF)iIp#f^3rGo&b;rgsxFTs)%)0 z^Yh!urJEKWJ2`(fw71BBNgj{PKIB&2jwLrjXR&U8Wx)7l^<%v+76Lr4m|&Iu`o7UT zv?yIq6F{+GcfR%3oU~ZRHU&~P(M%+V2bmUpRTIfbif&1SeJMvcC4x~gT^tM8-Y8eQ ziCXpRt>VMUcEFBXj;lmB;ZhK5Bu5d+*&FYi2EMYeuG1qSU8(Y(~F>6Q67zG@~tK>%e`L3L0$FmTr}^g2Y<9 zkEdT3a)CZZ^CSad7Jzvou5_-O7}E%(SDj&{Is^ohx|#e(K3=IS!H zQGK~E8B6sa^0m(5&`kE^^bN=cdW3f96JDnXGL205j0SVbTW~qo*jt1HCpgY`dJRA3 z_cuiH6sL=>+&Y>hAjugh^)sFl!W$*Gq+q9;hU_YI;@G2RJ*-Nlqx35xXPzgcFItCT z5HwKW8mSEzK0j*{jI9(y(ef*~P_nzi1iwyslEmI7C(#uReoV4XzmSIx zE*~uJAvd2xyi~K1DJsEubL%(ky}F|g#v>eNfF><6UGu|2nx6Qtp!R`(Y82X@x8E*? ze{%N&2MmcGg;AM-KN9e={yc42lvi`{2W|vf$|O0WN$d)W zqiay%V|z0c#Gg)7HXpqQhm1rBa+=WpR#4OLYsTX25kgjHKW7x@GOph`cQZSxM_9vS zBubR*{+A8of23g=O!>lQ_&IHVY4w#Me*oTXAS8MOrEt(Y63skfkc#g5J#eWhk!iWx zi2d4OlEM`>9M0V0SBv&O@NpK(5!u1M?5eEJzS{>JxW1mSMa(^e;Y0|Aup>=ck)i+* zbtFEggjI>J(~_376k2IkvwJ|!@&sH#*8hK6F(_49Ih6r-uW;Rh6AR5}CZ19ShFH|a z1f7*pb!G&Ds?>EkENUNHozi^WN?Z8l-SLM}YyEG3E0U&fl=ZU#oH>P{3(Jm9QS(;- z%USfph|okmp2j{&G(g`mRARq3{&zgYb>yA~q9*;o^PGcF6H+~cyrYx218%!H5CaC4MRz5vM5#|yGMOd#}s z#1lsIdAMriV2VO&9lf(4?5JkxKA9Vs+e_UvX`&IJHd$KMdT>ERjHT5k=tpS`@Y>9- zHLf?d;$k)4hA6xUEKouJo)>Y68bT%avi2sM(HOBha<#qY#Vwjt07&Y7Zr~8GEE^e? zYX?PW?d+rC391b+1uD4+n&k=pyt?YugU>GdRa zKlRUD69*f|=#@~+cb9?NL2WqyrM3R&~FN^5`IM@%zFpip2Ej!}_a#0_puS76j-BLmWXdOU7Hcl#^ z&cWGo->6p z;jesRD#XG8mwVC@W~lJ|lG1!=mQX~#fBNRhbP*q>p5L}1SQCx-_x^R}PNOAXIB|Tm zB>2;xUsAY%azgy_Ce@5=&;^_0aWuhLQt)9lNpPK6NgNC_P`@WY<~Ghm$TDRJ zt`e=M2*666z5Q5!v1;(;!$XXTgb~?StnOuP088tq^)Zoa@xhPu zCr=fty=?rwgCEp+M-7a5ix?Rly~z24)J#HXXiMe&=R%Qsp_~fty8vBM%$)Zk3#%gf zK)3EUmMTW3?Wq8rmDcz{hL$+6zUG3kJzQi5KRVH*c>ic;w{S1`QjP<&Nird`J(k;5<22aD~b z9P`~CfL|lxQeDdV8e7i4D?~lMO~A^L6>q&d#kD;dH9^JEz|hA@$>d#8VR&(}8Wa4F zSWlc~f#*y?v;F-}-56h6>MOHHcF_KdU20NVSUw_~uMYE;W zPw8-8y}VT>d-XHOxxRR;kdp>KC6&x^Xml;)aO4&!G5bi`?5PJa;0&5anZAuywBzj1 zXbiH!584aco5y$2>vb;AfcPrxmbCk*h^^MC$t$GInswgQn^g?Hw?JR6YI@Dj>l?bd zA=@o88;zTxcY3wUfHb)N;j}N^qL{r!ggm?DM0nSj=ROiw*+LEEo=kb|UD$8d&uOql zkPBe<74y&&@l@Ow4R}WNoL?&9yG0J~V{s855tQ6bRSyOwHtPn%bMOJ2Im+Jm)7#Sh z%!O-FH-N`$_Jj<)HQq~VLs94zxIn=)^aE|stKh;n2uA-z!(5o~ms05{UPM;cy*DW+ zr;_1N+F(Wq`}?+q93pFk@tX^b9}!WVB$(Ey<(T7q&7X*OvH_2PuasA>2T0*HYxep~ z%|Q62-Pw%KJ_AK>TH)bPpvD>QvPW@51Fhn%xOc|m{ZS_8Ja9FY6bpIhB$Iod+;G{3 zvgO~ly0>#4(#Y?xH|NuA5Bm4ViOhil$?vMnM*;IpPSnlVL`BvmBbU7Mdj0M74R`-9 zGF?FM3RkxF&Id&hAb|7W(T=Ky4*$rEaqV^HCtrNi^i2A$61XQ{Y@y6CIk~|OP`s#f zF-bsup{5jWP{Oa@4~;2Qr`&(;rxk>y5B=ST9%laQs~#y`e@se!t^c-b8Ar zSyFluzza<1{_K;}m|lB66Q1KM-#IF}JDvkN7mdOHtsJb1iLS36HL6jkw78OTU*n6* zkhJXV{)UZ}?kgqo3uBd4Rd##1YNt9igjz3_E|yOWfXU>clJ%5ZvGC`Tk^J=36l9|N zQ*Y&W_u0RX6&UT6L0q$zKEU<&3UmmNvBrjrPY)^U-NtH1&8#19eLYK8Xgb7H;)_8( zN56Wpkd?Ms^6jmyXgzndwnb>k0sX47%rL^3dqwm8nXoS75xabkvL^*Unqknb)%y&g z5T3jDIKY$gmjekP`A_gtSg+@HPED6T1e%L*Ok!!g+yd`Ksw`GL*{7+T__P;T!DxkX zFnOYzTt=hdN#?`HTs`G<36*-o|GAkI2ZxsPKyQ|jHh4THPPYO;sL>)i>4S~aT236F zeJ@IcQjhFSs9tUxCF}+)qY5?2nf4nYM%wW$UUWuMqhC_JbCocxW)7c95(zTEyw?MZ z2-dwGhH0y!c za!6X7dvy#Q7UX3i=x9};v2>|Z;fuXLCf1WE@|nRzq&5oo_0?R|$&F7z8uME3ehIFF zUfD{ElXV!GrRz}uA8D!6k{F}40h1chZUET1d@?E?S3Iv*B!DF-+~~@%z`=i-J3Z6^ znY3-s875iGaI4GM&4-Y%7*ao5Jen8sS!WAt9^L}rAz5Bf*P)MvGA|E)T6PmvEIrgY zzSmi&C6Or^7z+;~^Qg9+_5IixNRNP#TD->}K;C*I-o5~P(1VKXV!8W^%rO2aX1cjbvvGp2lvSoTScOdF~m-ks{LHbI#zoL8Z$Z|WYy0C zwC)NjA+G5;ON50kS`$!p|I8+wR_|OgLV*_T-Skz<>$p_-JgQng}1Q4x4C0t@?~6*evbr*e=XOOfYdV zU0GmXB+ZbvQL-tWaGfnxgg@LY2Q^7hB)KgPa_$5Y`x3Muf zg{`g~F~U1GF-90iv|z>^9VSKj&7$Jr;?}5ULYBSa)~|9zjvNJakh7V%X3UUlt+sU% z)A~yZQM4mDr{&I`IQ3_K9+2vA>=ha6B%_^@gF3mUm7^#A5jXT{OtgnOlX@ni4Hge` z!33Z|04|tK9B$bMbVL_+890MN9BN3{F%s$9CocTdfH z)i9JFb;uF7FezO6|MDsLPkEA6U4`mKrs5P46`mK0jc90agVD3q)R5I8Tdv~YCd0f^ zyGEGm&kAP*?=N}dZZi=(eATXvYJ@zYhWRmAjOv(#OOQt-lR!wduaUMPRu3e8K6iTV z)!3QK2O?=gJE+vg6)b;>U7 z*c6zLfvV%5S>@zpWseSc6M$lfGVu{qWe!(hV&E6Fl8-TMab=C1 zk9~guvfVAHKy#US@Dc2#3jFNljlM0KQ~Ah1G#~KPbK-XaDGIBQ2(jXMta|hs8}VlZ zOS$jPRv3l&&X>9yAZufv&@D0G!nFW6dKo}C_o2WblI;aG|H1wO{pB`C7t4ev=zS=P zPbZiJGK}Xqa}2Y3W5_``^*O;cmyH0_JAOo`ovr<4^EtOieBHOylz}z_;(7F$dd4S2N zBeCUNt|jTp;`3HNflVy(V~OF(1SwzQLQmPW2b?+hPs$w(%*LZ;Bln=2XJgr zh7V#}BNaN8ELY+ZSH1$Q#mAhZJqnl{OV8bz zgy@F9%Yz8u3WVqAA9$oSXHU$PDE7O8xx`n(^i)vz)xJ>T+F+xQiXHc6e(IrC{p#9z z5LAW4la^DE96~+V5zF#4&6eO4EC?OCAQ$!jk6%$?cEO|HqOuwAyMa-J?jfQIg_-D76GwfMtl!il$4P%lhsORii z-b4%LZ@WKU7>WyoU$5vPe$yfsD1=ipWSVNPVfgTc_+931V}3Du!V=%x1e=wj_2FS< zJ&|U}DeQpVBaA)S&cG=V7Rr63Qi&Xx7}ZWV2S}lFv42Le(E6{{s96CQ2{N+hkjy^K^Hr%7)qTlP`3wgGgta(y#DZ|Mk{>frox|8MSZ z!uX^JghTxn86pI;YG2XoYSKvZ$Cl%!+0yv=@0g|EG^{WiQ#gKyf~hb`92;0^(MyWJ zx87r_3``7+WUl^d&iyC-Iw}vfXG>>usbnxSjmvjG|k1G1W+w?qb?7Y~hwL z0|4q>Qb+-htXnyfYmT*pjNSmeVFo(ttKJ03Vc&wLH>|>hy{*Z}dw{~X+(|FfXMZ86 zCscdcSN@fvxt!&~VWr*Ucc7K!mDAC3+uT+5ADWd2E`ihrTSfDpjh5p>8*lgsBykAI zbn|9)e#S_5W8?y*4HM6yn9;UB;5}wDSObCYY5ycnusC5?k1#vuTj#lA(q729@D`M+ls8Bst-G;}k5o z`FcFgFxgB_k#JB11uC(M+~+^YYX>JbZ#NpzmoG{ONGlTF8+wQ&wNk> zU>AV`I=|E%zMz(7N%_sF%0)t@b(*e;xW1;j1RVEQZz~ zD437_P&<){0ihW@;+Fc+^9Gi*UT~ZyZ(&6ND`7`uZlbYnzY0Sn)ao`A#u4Xdc;nad z+&e1`B`gO_ZSALs4YE{>?CcHEg?8f3+tRPN8#is-kLv!jP=t8f)&KTEUs-txTa?oOZNm1Yy&b@IEOlVFx9o1L7nVJQSRujb9 zWl;OH#^%6OEUxY)Mfzvobvo=@KGFVu^nNiEPk@U8C7^;j!~h&$HlxI zboV`s<7DRI{!#SrAY@ql#Ou}X%si*8n~Bxgey=pLPsw?bT{8w1qiVU2Dkj|<9jXog zZ{^Vnnf;O#y2>(4VP^V1p~sWf$N{jE*s<+x$>7rF_;YjR5I_`VGFh>J3HO(Zn-M15 z#^lGDeM4v+Y@9_LIY*ku;!4aI5N;UnehWmilXzu(nHo9YB4S^zBNJFg_11glvW2y8 z*wRy&-GiYCr-HInei@#pD1#}q7=s^L=pX)=H)AZcHCc=T2Nm5i0sTJ2%%8<&ic3P) zp(2KWFmwTv=9vfI)gu-N71V*5wR{w&TB`T>+?oLfn+AHWUnl<@6JH6NRHyGc>q#Fo%!uIhyuKg5x+a)6#or~B<$E+ru> zqK0W8nU=M>3w!zcVROC`5z23K8B4wCvQ^q0r;UM(bO)Ye(+SrV4P zl#azCOa0gx6?~nl?eczEO?Lr|b-%-2ccdP0dZ&D~;NAh=Nj}iN@sy&ARg$cV6fDlH z_7m#~ShFI(v})+P*UDe2qO}n^EHNa&Z5aZsXXM&r?o|c35~fufcTN0tvgwvK5^th- z&C9CxO*c|a+GlzFD|G%c*N-~2ur`pefUj*}+r3IYD`&q>OU*@RwnDbRms6^E;{gQ3 zqu1{;#;^?Z+KQ}`7RCARKGOqO$3sm92ZfHLIMD@TLvoc>8AD!h@aZMUQ-Kp+z12V7 zH8=hK$JrMhjY#@wROO8%h|r-DtVRBN7!(UNna&x-T?=)30STlc8%O0RdHq?X@Jm&e zq4VP!)}6yi`#@IX=36+vkXwC>&n`uZm)N6_@V^GF8AJ&J*f3`Tr{Vu_3ZGDB&dkE_ zZLFVLxGKm#rLSnX#7or^JmUP-bElVbV3MjmBoXJYojw4uL$OF+sal`km?o85C+eZX zD@3qQG<;mQx`ZEcba@=I?^vAYwNk-Qa2l*8MRILH*@;a;R2JNe8HqQV-OG$RdbmgS zgVI#Gh&CFsw{NiM_aON$K}5qweUn&6bGbzMUGnO!6C}W$mfK{aHmSRBG70=(9~Gm^m}*828ou!$!0%xX8FaSeO@&{@u3it~B|1 z5Lq{>wGp8PDuUhn2ylQH397W}eS-X$BHJ{OdmQp*f==Z$0(JwlskP;J{gWWzZGYyE z0fo?t1%JdzePyrd3`zaYyJ~PZiRc)JQv7rl)$@q?3~7HGGb;DW7MS3=cF105m*hUg zKj++&o99JD0a&(im6p)5RI?Y3{3^AM_GsaT)lgXmPxPp=rQ|ugnmU&@U#ohqI;Ywq z!ZxCy2*l_|C{VQL9SZcoCbtSjI{ZBAY^AVu?X{pMug+EmM1ANSwog>ylA%9Eu@{<) zJeNlUt*+YVcm0C7U@924;`NIrFv<1P$XWU)Iu%cX4y=Rb1eej9)RPz%VanBg>iSPf7GT8IqF}dlGmgo0-v%wqm0i+*NyQrT zVlv)(4&$08T5!e1e0(xD;ok99{6k~iOwz*Am%HDp%ram3M1aXjg^E?zZ?f?gJLdZ- zPzib{9xNUP?xE!B!x!qlfpPtm3IQS%r41aP=t}Y10?{S1OjYW;&*`D;)T0=WF+SpE z!E0lr@c9u|tJI8^JfhfRYgNbt^(9+(`Ol|FsyddAL0{DuaVZN1;{p^Pz1ioa)UG_G zDYl9El_MSEM#T05!B2xd7GQ+Faj(6L7E1gr7!B|J4Ri(}bpV?r9a(Dg-FxBhZ<4F| z_QL!N_NZoTehbl6sC|9fdxQ9cS(Qpea-wk8^%OB!U8MMQt|$fKY$0-wNbBA_-^>8RwyuNmK&SuHs0GSy()W> z&qsE?YLNrUhmMd1&;60cwgkzDo#fbW!TnxO;CSa3zB5^D;0bpXR+XBIq8j9Y+XKmv zl!YXDai?>&0NwkXwMV9FJtVDT(D z!XEcc80KZQKmdX*-Lg; zE)~*L<|bQ`q}R!lNwm7h8xB8IL*Xk}@K-CYkKT4hF9Jz$?*Jb#^IA%#2yQA0HNFUy z98+p_bZ3>X9Im&vt5EY&#G_eAspMX`81xO+0;RO8+_1|X+2dphk-OtoQjJ5(<@frPK`18Q*_d)^#7c_@jngVH~ zX~EqmUaC|h_-yo*@`Pf3iw3fphY=}DBdbt$S^<3~7YCmglS;0Ib)it03UoiVEe!-U zw8O>{rb}5r7wJc5R!L~LdnWSk*cRZ+ed%Ok0I7l2j#&a_t3gD4P;vr&hC?JQiy^nl zn$u0O)iQ?JWat|pD~%bS`8?~JZlkXC_=-!PWOtn?1@eX-jia2(5y3r)KWRZqoS4Jc7>G~;J-jL6LNL1c8_TdmMC5kix zIrY-OS0W1$<>e!H^7%-BPcTn;%Hb86*5%zT8>iqrQmRDIa?W6a#p0Gv6$DMP`l$!> zjJghij7kBJI5I%>XLOkGIm_P zPJ42RIjAXb-pFD$%d_J!ZcQ~8fe702g|EtRA`{G8mOe6qK$XVYmT1&ARQXm03dxgD zz3^pc>B><~OX_|GyqW685_fuZ7fHW>6WSM>h>{AZV7Ah-f^aNo4|JzDul}WwboRQ( z9=*Uh(RH8yUhl04#T^_$DwL~2bkU=Jt*m~)I1!knJG8yreQ`xWgt@f^8l6*sR+NFC zxCi-DJPPnM!_KOSFa2~@9pa~4-^pJH87C6ZES^^4Rx&Jx8sQdQ-jdT&U}U>Ap)u%u z3qU~JPPRX1oH^B| zAT(0DO;Co?luq($+%K-dXath6g~!v?OQ+OJzFMK*JUPZu`$)s9lBsJd2E73Xi-Zcr zymdGwVD~l>`$O^h?4aw%&FAvh%hRnNXQRLWt12y z2uvD2_-s&w4ad78g#v|dV{}fbMjOxS9=@;#irn@rig5DqiN7_;&UIPcHu!c~*2I!_ zTtI@WEnZ~)ANPY-fe-URzBno`Iux4|c--$aGVir=%0`(g#y6zWpH}4IXNBnZP;%l% zBw!EzOnQF@7}gPJQQSJ(4{PeyYam~c;nMov$-Kq)o;=Q)IyGzBu!_5k z6SG7}Asknx!`9)jal8O1(&j`%2O`?_R7>km*b`VaF5bxSfmbv3ATn|@FXj(I?2I}O zql}EzCZsqB0rma>IQ)y5%5UZlU3&pHj0eQks?^)PJQqjiU8OyWX{Qjl=>@@?W2x<9 z1$vaue|qY7Q`Vq%hGO`?(6)lHV)U?{W!{+=DnYs=G`Z-bh>wAgr25Rf;Zkic;-y*y zWa?&fuD(Pl_l7hQSI>dIBUU)xC>c2&;?rm55krRI&2jZ8n$>gP+~ntgXqN&Ruy7a7 z*$B`4fp}zxVA3vn|4)V64DdI~4LWbni3_xv;>i-_1|tC*iahpH90MxNpRsat(@ZiI zfsDR!*Mv5(i`P@fd|pFaK|XLVx>;Fx0z70*krDCs0#@F|VuXyXWBtGJM)!Ky@ok;4 zSw<;2ThsC>2s#b8{%_+wT|W~$6TibR*1khZ!P2bhJl9s0jHLDF^S8L<<1nW1_swDH zRiqUYYes-#7@$mL3SD>B3^NzD`u~@G6UyN&x*684x)s7d%j%_N#a7De*0P>D!5S8P zsVTjkvav-$8Nj)cZdVQ@A08Z4*)g5|??MxcU z!KxuD9#kZT+&L3#5c+Q>kmVj8H$uIrslH_XKd!I~$UF^iL{ZA)OjIod;G1XZ| zfA}y`2P1QT|0)lZK+qC}r_r79;>Axf?9-gw5%_0GvlKpd@=xSR_9x7c*w-T(L!QBt`j zULWR$uhgNha;Z1(XB3f-sV16%A3D)uZwjY7w+@{*9I2~AXgN&?`rg|YX-Fb}89Yxx zH^Vv&bV{kWIpjy@!{H6OsE;OkjDY5qGy!?;miA9X&Y2IwU-2OKwtspGrXolQg4yR; z-&~=CFdBp@*%h@)J#|=P-Krt)h0*pHXaCXN80EQEek0zQ-X|IYzi3O26j5&L2>qipyDgR8tisrc#w{3LP4is&r?t0Py3;1!?!=uRX#^;Jxu$ob(%1Sg zUs5t#j$|4yA(5^)XdJg*Q24G6nwS!esFIBRNFtc=i^z2`l@2teDExC}(h)UHj#%*R zGxcv(l!skrdQ|P;p^24-2U3Mm)^^xu14PAPT*Q&&i3%IC%u`$(3%tVr z9Hf7rJWnP?xUYW?AY^^H&Ir+R;XObm$QsT}{_w;iU8jz8g>`YCw{x?H$_ruqufIr@1xsHl|8`I)@}-_%e?U z7g*X%W}0PCG-U-xf{s|0T5)Gv6<%*EY>wHSv9a7MWvV+X^=PwO zzjh4`0X6p`vCURD(C^e~3E_qEu=a;Mx%6JN6P(N;tS<(Cd{zM@-pof13&%*AI%#Ya zG?ml%UFDZfUo@4~hhR7vOgqjqHp`Wd2_n08ShOgB zitMG$Sy2vKKTvyh>;vpk_~HB2G}f@odaMCXYaaSF76N2fe(3%`X3?y%_)z1uP#5l^HEWGlgI_-oO>e)i0N0;`HzuoY50DPT0M7DFVOjJ=!{rTn z^{(Mh{HJ)zse{58QKd>}AvOYkO~@!a@2mj4i}%friMR+zuPq@B4|2=?yzYwk;Zze=j zw+OeUQLhe}j21$Wmjo`-MrymYc*O_08Rtb=h)F2CJh@7HltW3C52(W#YmW4w!Nx7D zun>&XjO5$=3vaPg#rYdq{6X!0to_EWRb;SFmUF;^e=QeF@aG&1o?{N!bO1wk3EhH( zC=BOE_G5^eg=#M z^)LMh$^5cqpg~dX0b97oo9>d-{b=sj-(31ZYT^6gX#{?&P84^c$e) zSavLUt|h?%S5S=%#ne<_50>Y+$s`B6{CWu&)!^s1L?zWqKhslX2WQl&+dO2t!s#dzdH~&1CAbrIS~y*Tl#C@%9Y_o9vXUB@FP*)R0GGswRgU0 zZWpCgrLj;PoeQQO=4>W~Zkh=ftlm%wMe6vI=50;41X+4_bt#6oqUXT!a!}{R`BZ+c zl6`W@~!BtM0XafCnLYMvHmC+ZnU7;uoGOeukC9DoXMqkC(Y z2{NT)omzZdK}3`HT{32J_!DbAu(rFnE2yCTx%S%dg4iV2$(cT@qoKOq}_J>GVc-S)_t43mI(i(B% z4I8l9*a&O8e*drwBDZ!RI;h7rfJx1GMiy;vATU1peFbxMgqgR1&|VT(pq)bL4w4<(ZPawp6spY{bxF*swVzj)TnKi4 z@h7=o4e9zPna{RJ()|i#FC%Bh8OVO@yYQBhOoN&d7l{}x1)Q1R%~l@=<&qko=6sYH zt=}HUAe~b3(8Dcq)`@yIy-S7gi_w9vr1-MtvXkOc<0 zu6(!NpV0P=dIz-s`68Y;#0V5%!u}JPfrm5(N zh?E{RwRKw4G29w4VWKc{T#1X)Y(~wH-yq58l^m|)a{rsAer1Sn(Q$uk#Wnyo35ZGa z^*)W?U|EdZKMt_bhIky_kT#wv1H>&sZnV7;Y_FL5FwWsPkp_$p0GZysJ%Om_4Wfuf zul}vz_(6x^=M~EViwtM9c?lTh4WUk<$~E_4!;ts5QWT_)CSg!iTLpNoAo+~_015>L zAm3|hoTGt37AWTmi=5iYqk_(hQV=J1u1jot7qrA)JFHJ9{mT_mKdPD*|sS7 z6&5s?b{cWAV%~J9P!!v;KxA#zX%bVo->d;kYfLS`*G)xOR&)Yyv98>rD{gY$4$RKc z1(72JPCj*AOvF{qI3Uk^Ap z4WG_IQ}3ae=pD6sZ6A~6k`$K%e`HiFmabJwoFZQS-8!!TpR%r%4usl^9nIl&`P6|W zZ=ZsOHS)kWTJDa-bLV6oNBRlRhMRbh{-XC>^C3JfV!Yn&=C`NNV$`_vi60KdGDD&H zPC7XkhjiXp%p_J$wj1&&YxihG&qsjz=1u|ZAbHY-qTd=PBLf_7_%ov=f225xB4ki$@EN^(%9qz4 zkg^D;F-vFBm&Z}lP2}?Qp^Qv#TmzgSAFoWVXD%a?11fII{2~-x7MAAHPZ*8w0A=Hy zs7gEiaRmsOO~pk$&|C+_qN^hLd?7{1?OCp~m0M5i-P8RywxWGilc6@{37{IK9Duk| zq5JhkX!tB`8RX|UuX1Ixa`Oh`@bI<+s{eoegNGk?J@&XE1dc$rhP8`-Q7RH0mU6$cNdLvD9oTZAvu&!{ z1Mi6rxHw)gOY|v|!($~wHo73sSy77tcWN?cOb~nudh8n_%$&{cj=^$=Ga_kX{aH}g zJk$)>@Tl+T63$b9p$_HY_Sr$a&c<+eY95hR=w%U0!%4^mXqX|C!!^ht#@o~bz0u@ zHxF$Ij?Gs*;^Ka!D)i=cW|}-9J}IJS6*Aq>9KbxOpbu7Xf9`agGRg!Zv-pU!f`}Lz z%S@4t;DzFWQY~vJ^GRF+Y7t$#>z5rSklC0;^rW~=AUwdO3qx*8r@oGrJ18B|GF~Gr zR#39Bh;SO2i=8eLy2oM!<%XwX^he1oaS&}n=%(O2OCuE6f9p%TDY=ZIDhRMcnF(QT;CQzV5Ce^rQD9e2O#Q3K^X zC;@nyLNa`PD)R%jECRSuiYf}1_Lh*eW9k>gT>%gnmi? zrDV#+Q+RG`7lIA}abZS17|7X=4M?aqf*dsRRaKNZ$eF5P@OYQdcc@Y{%|dx>I1NnN z=75_pJkD!V%MxsKO55AxG=S9@$b(+rSddO{nz=Z2UongSd~>Q1!)RPhQj}s({e0$) zOc$InU|=>V@n-zg0AW0*!p(+{8k>GkJf>@$(zraz%(VD+Gr5EI;jeC&wA;$Nh&WXX zr6o=hH2mGz1=L~V0%%YO6-1IbMt9gok3BKSf&Krk=}0*EH-OXncFY9n#|R$A|C)u z+)6SdvnfHZXV{}e=-Qiq7NE$GhA?mXOfgU5P`Kddoa=FwU?4cjCW7b8%0{!|qEUqY zm_n(3fra`CKG`-%7p5rUZmpFhLX6B&ApdHbK0eGSX7g8KrX;)bUgA=M4}{X=hl)3k zdXXz-h6fqMQdh7EF7NGi2nMgz!OiLCp&_Q!yV1$n?}I(eQBFmzbz2sem(zvz{AzyrhM>lqpw6=or2MNg9>zb3Apo{d+7JX7GEV?V3-&Oc!J_H~)c4 zcQLI_;?P%!qVjAz#Njd5vokyR!9|#HNIp*pEK^yk+1*^4{eydqO8W(grm?#Cwzpi23>I`4apy`?v?>seVps zx2%TQf)J+pPa1h$;C`(E-wmmraJKK!U0FZxPJ68<%YdA{Y_)7W0gx0Hxj{-rY(I}n zdCG>FM?Xj}lmE=%ltn6umx)!K zSuWrHQ=QF!@Zk;PbCUqoy(~+&q1hmudN=s%v930d2(ioCycWgZ4aozj(~$>tC~<69 zHcq;2jmjc^v}lGSlucf+DGf6yB@4MXCa9d!A9CM6)J8ZL`l^r=$U7bp=kjBDk{5ZX z7^sB_hxX>=!Sx;LC9bac!(^x;*TcOnp3|3BNqG|h>6`G4DUv_PB@%z3%f#m^Azh}= zk*Bc~alUhF$HUM)Y3Rk4A}SbizrMmr7i~DKLKWYe z(c;|E@x}6J>K{l{zj$D)OTw}bLlNTr`nHE`=G+)#RkBbULPi18jQ6TMA>dQb}uvE8(gRprv~#VLIm zcLeW6#(S-P&83ASwrNukh+@GW>67&{GPP&QrQ_0CbnjGdzB$7>JI^qntd9Qeoq#oG zwrs4!W1tIJdGmvUf2EC9uVbkzK!mRDo3`jFV*WpB^W2f`-sq7FX-K-Bk`8!s!S*P# zC{`$uD0AGvL>f0sqT6HlM3}N6Hf!LP`$dw~&$YO+C7c)~WG|1=lf29PTVacPAvG6} zN`ceSRGM|-F;J<*umU?;F45KHtR8L|3@|V2_3%gJ6^*Oq5YJ+6oOm*UE&uj-uS!~> z)3b!|p3}`rtA#{m?CqHz==ayo#8k|nVQF=p~(ED_qD zDLdjwWJ?^aCi0-nHnqOF!NBiZy#K|TfVRQi!SHvQCv-}o`hmdqFSKf6g-?jobq*_0 zVc(ICqUs~Wf{hk_eDG`HOF*zZsHG?1VH}Skq>U`Vbv1)wy61#I5HH)l1bwi~mVHBL z<%-(2lO@JwF$;O}(-@12$cYrf`YQxn76L0QVujZp!RWDEI9UG%Ht!wsc2&uSmvp>F z$9~4e3sGOTpG1mt!Wvevbd*mSIsp#bM}+>g-)KD(1!Ug#A6$9xN2$5V1-cOMs3jrG z%&hoQ^2Jgoa#5emWXhqP-xzit$C)oNRlys2>z*}!d~gGhM|N(56S{1PC3q^C z@Da1sF~w*(Z-N;w#-1-&Ow@L!Vnfq!D+K?70qGNs@P`Ga_GpPL9;~Sc5xL&U_`}#n znrj5o;ct)+iur`HCrn>I)a0BNw_17h5cc@}34;z0HbRpCb}Y;~sjd>>$|TK{xl9bL zCu5@)vW~`yw^PO>{%u>#F&du9vOSN&u1U9kxFCiPMBl$RxDzccT1zRR05|toI(dqD z9@7z!gQg7jOC_y0())R&Zz?aNLkurC8*j6B-T^v)9(T(a=gf);L9D<)JL)tB?d4km z2Y~w4#nK`N?S5|YHiMf@hu|^{_4DrzBz|goUse+h}Gv5)Y`RvoHxY@3e4KS{p@Vi%&ct6_X>1dxnF*l z1-0j{`3@nu|Nf~Ei2-r!E&{wv7(Z3x?=Al~gBl43`*KL3(Pu3{57OV_o0jp~1skIF zyTXmt1fsHI?i5+90RQB_t&I+l>_`~IsN1EJ-`ASzPDmkOk2BC&)f>I%;v8p*WhYN! zX{#yiWw0Q4bDpUS`u*dsQ zyXyt~%P^D>^zqRW7Im9^e8tb_6tdy>PdlXcMOGoOL}!LbC8A%TckRJXj1Y9%jU!N0 z^n>w(Z3i5hXJxgTLWoltGR`Z8Dd4ttpr4%C+q6A$DcM@1w(`6@8<3^lE zj?ZJY;$Uu#)W7G%W!c+bYteg3t6hO&@pO2mVl6&6|Ja(%z>`5S9V=zlto#c#a=v** z!yk0){KM}x-KoI^CPRu9$4h3nvy}-{4-$-DBS@5CmA?L!s}fswyCm|FszvD1@yA37 zw>tpS_GQY?oq^=%b@Jo1S>h31jkDSp2I9t9`C_7QC5U96V!WBI&FK)BNaoc@r7s}R zzNYcB!6aSHv8Va9uE-T+gv9xpE-$S!)&UAMiCJyq~^}0`x zvp*IW(j22F>T&~UKxp=bgn?hvYBMFrlq|LfkmEO1LNN+bX}P&aVPvX3=wKGJJ{2OQ z5m0eP?Wpfrt^6_lKWyNIMWLxYd@mk?mEVBcGJLRn^e^#aYe90%(g{_|I5X#5J<2)+ z5N6bT-HDu#2^}C)0C&eO$IikIZ!v6thUbUKfEE~{Y2cH5QN1-_DPECwyRja9P&7Rw z>i6E<&bK2qVzHaDfD%lCi&IdrdH9b=)xf%_8U3)|BWV} zg>|hj23CEl{^2_0h0?chuqod<@Yf;vF*QziJT;{3RRTQbx1%Vpbg5v#tBxN;Yvr2y zd4nkEr)S6Y6)+E;zXU$=6WVT3c;S2USduSfiB%Ma!QKtUxZ1`{Od80vjQQ65)6l zY!ZKH)M+u2lxsBIO$EDAjP~>wYYmvDn)+0LrdwHBK?=CI76EB0$JqQiPeq-rkpI{A z!V!=96~0ub8*?iup&RC6{lRtHIrCEj?^DJS`!8&F-(RDm9kZC-5qQaVMt+a*xC#4$ zC4RCMZ9vOwW~t10*r|b`Ehe!LDlcv*w9{sY{{F)zauSy}5jmFh-bIYgHMQ%UcAYFx zXE9KGHDMx`uzi?gfSZSmu2Z6I)O*`Eh3!f_`8F;%I%vn}gMzR`p;qVv=+c!c9sK*M z#ZhMdtl95aJd+^U=z7AXanwTUVZU(69j+$6@uzeVbs&;u;Xp?2rnrpf30j2aj}vIh z!%fD8;smEWMxT%n5S)W$8TK}UElC}^R7=pZBeIHj`-*}|G?4El7W zWr?&|YQ)SNJclICWiL*wA1t0q-7~;;oI>!98@!_YrGkN?)*6DZ+@d6M{7NiufK4-` z&M;AsShZ5vCBaFhY~W?odoSsB7V>__Km2dATx2d9az)M-FZss8e0Km=rr2&NPKi*gmD_D1JzB+)aVO{t%g&o! z*(kd{JAdw;z~Jn8bqM6UCnLnsYqHTz z+pU>ykGgBQ{ItLfDw26k&D{xrxLxUw$Y;zb8bugKr9)Y7U$-vO4{pr>LG;)vrBxE| z=`Dz92fOG=Tfla<`Q(_3@ODZQ5DY;-7uiRV^@t4C-MQSdWY6&MGHX(^vc7f~JdB!J zp;cp2y2rtd5CZuQlq;!&&)E5G4^GL%`BkCP z*n~TlaA5ZEyB`vB7Mta4VR`I2v&E*7E`R9CuKOnZmv>Cm!3-_;uZgmK|1C^jKqc6h z*AI&3N8TE=5#wM#v&e)mQN$=0-ya6-%5p_vTJxe%8JU8#9eZ2`T#x5cvA6Jn@1LdML3nf4nnMP#c0sB7NoVyivq@7_!=qI*kSxAG z!~WdW&~+cd<3bH<&b2C2C5~w}Nrf&slGqL7&2Z~ip13w0c+H&8xNHbhmNiG2LYO#$ z`;RyUQ)n^5#^nt`q1Yhc1TY^vsPr4a_sC{z53QK|>^OqVzP)>HL$hYL2<*gFF~a?j zx($~+k?t=xk@m+FPFE{glr58Ue4SN&2(H>gdD+fPx}}cy3JDGnkxbVVyN{eMCxk3w zBDz_eI8N)NxL+T(H7iH5*k8Hydw~F^GQQ_j_e2!EQLicXJkF$+*6aRcp8AzB+@Tuqv1{ffEv)K-i$%G*Lj96tMerB<*1P(|O z6@$5_vjKBupL3;0(6(*xkRfn%s@%RMk*b^csDh&<@>KJr_I>fKV?@(`jQ)tWS?=%` zCxgi&k_Ol?;K_6==j8?7_=$JR!Eom+?efhSuuY||d*fFlEJob$)cLV!By(Lcf? zM^*P;U`vynPOkIdq;V3`#}bf3XpF=zBYIh}r-`q|)*GzN+IwErdg@A(k~@dk){f(y z)~E_|0Ny)@1&v5qA$1@>Z}GFB)nV%*I*BHQ|Ik|6H31m>lqBd8BB7*{EjAbH6H-$D zW7mLz!Ye>w(R@E&T0cB<{y)=g*}*J%133JV*w_dS4L=pFpxTvS)3DQPrADdtM5@Nj z{DI0mKty$cl@Dci9I|SGYQG*~t*f2db)y9m5+iJ5u1Cr=di2SGRwO}dV@W6_%d z52_1xaOVC-TIhQw0S$Kx8oQ+_L=mVGdjNaq%%){hZPo6;d4Z3;v((j*v9{bfC>8rm zegZj{QArt7YFyP#2124TJq+C68qt>lJ6Khw(hCZvy(sT%KTVP}G4ZE`VcY$BfLKI1 zR;a=kXRB0%^2HAkvI56kYm@D8k(behJALv_&3-z}zf*leu6rk7GbVwBr(iClnfIYZhpvfyc zmqBFAhu;pG#%1U)3_bFzwbsaews(LKX9xUtjH$+Hzf-;@RJk|B2)QeB0*X``plbuG zLLO2!+|vmTGCx1Xx%<|y>LOB-M_E@OW9$vLumhRazUI3iEumN84fwBz=L%WE>PZ~d zS94T2!-lENDA;V+U$ayPv;RuRCshksBlP8z-Wf_p_VO9m(ixPQA?&S{06t;OCnJs zh1e$CMD(QfKIPHv5O2i=c?ge}*#NR7)-tDJbEqn2P?E74o_Bv#fT)7S3MpJ&7&k5h zods5ID94CD+oT$8JK3mD4eYOwz`Tx72=XIcloS5(f6*)RBG?l6gJHzWmOzugo+3+h zN1ihTXz7e~8d;y$55a{U%5bx2krXrBp^tc`Q32dT-c$+{*AcqPaop_ER_6l~SZP)n z)JL=V@9(l~#C_Bwym*ym!+SJbU7EofVH_D(hHlj{0ed!{hG-@8ZYsNrVO7K3^__^8 z7V*JmqMA~G1Hb0oc-6f^ak&bxO<_f$)0;ic{F02IiB%LCcOo~&do90SOvr(iOg!j= zS#Wc_xQAq<%_*Wqd0{6d^!paG@7|Z#%@ntSwc6Y@w^lNt+UQyo; zMI#lNeK2poT+Qd8$EGV}>kTM+!x+ZX;zEpCF32lkMaBhePL@Uf&>75~R1bvPJi3xR zYE`WClcwGyZxUdm&DoPBnSf_=B(sl3bZL*Ni4n-SR~b8$w&=~HmLKcM+(P%iD3T<+ zL#riVL~`B&T#_Bg9=~quKTzjI6W1$?i#WheSb@PE)KS@KD@8h5M3`2Gj z83M|SMAz&TUXOC$W;4#9|+!x&vHmXH(PFhQaI?t96I8Mn|59;d~U|oU# za=>nT-Y`Q}8A#!rbWK(*1Bj7`A$y|`oiorOeCJ}>CO(1s#4w|9qa(M5Ytt9;MS~Ph zQBV5cOsbI2nEzGWWiG97l~mqok)*C|2_b1u%Hc~h9<1Vwd!pqk+0dqfxCF>y7#=1) z>xwkgi6Nw3B?8+i8B7|C>ljXn!SAy+fWA` z#Poqfr*fx5KnV6jZHU4{Gh}@>gL6CfK(1hsM$3%{1tsm}B`qHzl0{JdV}rh+NS8;; zHv@u{WqD2p>x)(|?G`0nG9DyzKE~(Wvnr$|a?tYh!<)v@hNUcX*OGlUPyK-Wr+nW^ z+3y9>K3V!r*f~TG}<)k zEEQB>o_xI%}tlW~x0>}AL+UE!Um;2flD!>{NeXb-vdV8E%V*mgr2Og?Nd#G)nzT9nnm#+@Y9Fye+0 zeo7K_pNa5@T@m7M{NsUrA1eq=nmix(-a4S?RFK+C%za1yB&dzx2RTIp2;~$pwy3Fs-g1+95A%9v1P(f`Y7yA7Y9MSnFs| zv>0G}asr+t<3Qxj8N~=;)0%d@+j@;{2*hpl&$)!_VN2*+pW#tFmk45l=n8g%T_@Up;0W z_J**d0|iEAvFiYhwU7B_{28BVN1Mv_zE=H9j3Wp29}h4x-9S?jK+r7hnO~i5av~@M zgH@D}K;w82Nh@vsFEr(GA-4T-jbHo5o<;D+D|{ofsG->rn;BhmYi`jO7fa#A-%kGv zD5{$r2AM~xO8i$lXd++`8)akp9Ue?X9tqRJY3dhN$VQ%CClTy7HtAr^IUEZ=&Q+sL zGSgxfCR5`j@)UoGttY09n_^Vj{Zum>>?UR#F6)A45++obontLXvZx~HK?%i-oCWYr zO#=79STbq$feHdt>6;sEVUu&@Y4J9>425()_+J~OOB}srb{mE(-=U(TO_o2e{bGM8 z({=@|Rs*aZl5Ok2DG@>NLfgfs;fF<2PTq{>uaep(i$A0nNhCo=^^8NCUfg z+UgdPfWk+80F_e@o_;-Z=TB@C65fX?CVwaL3eWgpJ(UOmJi6xy{xmS2?T{rSog)Q1 zAxFahp9BWdFC82}N>%-gfY<^HcgD}cL}B{rdx~FcUCP-B&2NT06O5#JpiMP0s&!t2 zeh+46#2b$`6}JZ*xKm?ox_NJg8M@#)4~YuK?y+>|8_p%>8{M_3CPD*#q*h4n{X73G z*vw^r4N5G(711%GhRh2eQ7pDLsM@2JTNWpkWl3l_DB{SV2NEgsF(L}Ixb5s-vF{=p zW+8u3Pb9qQ=aUHs%jUXwVP~Ex|16l0OE@;-2a*HT<5ROL4>#(hmdEB{NH@Gb##T2F z9`vhXcxKRrJNsLYMjT1JrXAY7X#`UV3Qqg0g-BIYEghk7Fq14@XqldU+J8;xOHIaZ z18Dy+igw8P@PQs#Mo2`87(UjDXwigrW}G3tGYAyC2mX1gUcHRr^;Vt?_|P|xwl{Fm zMC_JcE`5JQGm|wgCK-A~HkHAC1uD6qIG+|=Z z8KZU+YSDeKyErXfpeQIX^F^GfZ#so^;5?3Hp@2_dFru&S6%@d?KoZ;FI)fBFNU6fp z%jOUiY1*?7GzyV8xE@enj@m=WQ&#Y{I7%9QKOIDgtEP7*Y?k6c>_KY!(HMwk$!=oV zn!C)o*)ePpcKUGV-wp3}-!=+(`DEr=b;+~RM|J3;Dkrs~Qfl2AI}=HZwzlE=TmYI4 zuQk|5;s2+yK`|K)$_5HyMZGY zLur=6&kX>ntmO0`(98h88D?_0Hjb|C-%$rJ zsyB5d=ah9OmAb3ztUEL}8iIO&Ebhb)9mM@K_r#}^^kHY9wuvlo!QyZp3wGUsoLGiG zk^t18=9@RFgwE^<>WmO>0mG&b)G%jiXKfNYni|~Xtn15e>;=7OUTM3$t$7fF4`bYu z=J@rzEfY{W{@r}td6&JBOIAAg77+Enlc2M9hE$;??uJ-qxIt|Ed=Gtlkct7S3q0ZO-@8uk}PX{dhz|M!VuX#3h@kL93Xn zZ-X_DRnXSg5UP69Pou=WQfxnH22=v^I2UJ^z}F{hf11Xg22pT?EP?SJiI$puDsjgi z*jLVSM+ZzDB|)Qvl~3$Bnqj@zg%Q|oSK_VlcKKNuPXd3|j5F0xYlJIqHOB$S`?vmt zG+Pmon`){|D{WaGA%qw3tWdwTTSK6}!mo3Fp^uuLe`P8$gBY|;&@~$MvYtWPkgG-hedpLCZ9?XKJUX@sCx(6T zs#W!@SGl}G%vCZS4gZ~=bg9|!@02p}sW?;f zN<#PgY-;!m9US_tf*6|rpsKH1dDgaortgxR*c8q?(_a-g(F73E-X%yPnLYQZnXw@? zX~X~$VY*;BZ;3wX7NCmZ$0q~eWXDi@eO>n7E!TB7>fYpzog4=qtB z*>lKgUI?wElVa5LB^w^342Lg}pgN5akvYzqsWGN}hQuI{R!5?aU>dse(fZoGx3rWf zPuUoGq_f%Fgd{okKld0VUkP})*3$Iq7D{dojF61nFZ^waEOF{O7@#%cR$dRQ89v+;PdH|tBDCEQAg201&pQd%3^EC z_S)}3l7?{+qO62N#MjJ5n^_QcB_k)BXpam($_t(QwF$Bx&?8O{U3cDya8PL~ALIC3 z7-Fv3FED4ba6YQ!{UMYE(a0T>7c^tp#H_vCn8J@Zud zExybt@0U$MC4~ZPNtv75VA+N-4g-v7^#aGa0`o^yX#=yK7jWD32ArzT<|$M3OC~HS z3<@X?V@8%<07XE$ztHfh%v!^AWDH$&pthtT@2w$$e0E7WTlf#+8E?h#;A2ydz`3U& z^`?JqC1>%Pw)VCUBG@`~&^KMLO8mD07K|<~|NWPrKx!BfOLKmb=d@2WkTEn1THdmn3Na-X z-E|?-d~^dHddxsi;z|B zwLH4$)T29_D;EJVDt@|oTGw>ysan2(EJCXR8Y{~{cD2Y2AM2%1cjP`8d?ArOZ$K+T zT#`|%t}cQuWsv@bNr0`8R~$H>?`_x4D8usI#6evt)qC<0C1_HA4x8X2a&>+|nbYLF zID{gP7EE2K()t{v<6jQ9q+8drN{kp(&3kuNcR5lyPuS+CMeVh(Nloz*`MwUK$!S4d2 zfm!j#j;s)qWgBJE=t_S@aM1v*A$egJJR`bqlK?9`FF;JlKxh$}_PL>2;>5s725g{kO--D|GnXC zQm`dkRb&IYO#kl)uGi<8@%v8cZ??D=Fsv23H@$vFNdz9kCvM?}Fd{m@(^Ny-i%U{+ z$xsfuiG`I$8p7U3wO3T$V~dtW5^4c*d$#Vu0ZwQ~&76g)u|wf1ccgG>tW!%{wCaEI zuEcgA5XkV4jj??8!Q5mEFy^dz>AieC8jQcmTQbw6EX(s4yp3H!gK7QnCquU#0od`j znWAI%Rzoq@SmQW{_3s_L{9sri9V+yDO%L{D{SSkKhke;@NW9_5t_Cc;TikL!o|W0O zd{5aRm!e<%=ds!90w<_+pzekAfjHJpD#e0bhX*u$u~cgc=;n+1pzP#x>OUgp>Al{IMcL#rt>R${Sv^h)sMvl(pQ;Kg&B z_2LS`bshp1+lWj+>kHn}Sb(Xx|ZY9g3i@ zcUCi+5NSv;8|gtOJuv~ z5!b?A7Nwthsjgl(Uj0NUbR(f@}u%?wQ`ZxWf4mZdi70CT;G}AvB4=3V8 zldg4%RV5T3mx^jc#1v%wZ0?Pa%u}uimNM_pxuIz|(W3Vw&gB9tPnrRUh(pynAn8SH z1pzIH*6VWZLT)9^5;GO&`I#)`^H8!Q&`^LkjzjVphn#Ta2RNN1k?^9JH;dYv!yQ5n zg&UTR68{}jw_h~XTlUc|IWhzp@lYA{EMRT2_;@L2VhEKbwu&+Nq_N^?#ib5g;tDWz zg6{`Pyj9Qey@Gk!HlCNUZr~CnT|yP{%Ko=H15IdN{ZypyMlCi+TPd15--}3=Sko*| zslhj#*tK7ymF32T*Fg4_-M{;00g=Ij@_cqKK84`tPPU(&;SB8!+axGG*Y>LacR!9A zB7v;hktq?zhraSz^ zPiHId7x-L7uFiX>Zf1L}ON~pOnVlgzU#6Y5SurKQk0YdrcH03o49KTuDcqy)b7ldx zbsa1lCp#8r3kHIrCxO+xv(djEl2oe5@3zr4BxvN)>COd{R%Ryihk9(Jnz4aWl_Sgd zeB~}!D|3p-(-#T$Yv%h!H%iLNOlA4EAEvDJT-8S&nKbQSYM$* zA|t>yYMo*aHiH=PIj?X`z>eDauM{BA_nOvLX) za5A{qV?C9pTuNMw3CW|@SxUsTpSd@%{ed1_-oN5xH=sV+Bhl?;4c^^`}MdLp8{2rsy)L>`aN)J(Nt-dF_fD z9r_Q;&~1;WydL5J{i%{rzQnqz0J*rlbZmPAcoZ_R32jpN*p@EWJfhkfzh`|J&=LksmUA$tRS!oq%b&F~+8=;wGy4R^;?ujMyWy9GC^l&ps)`k>4}9?1AaC%e_Nw%rYiRXL zGes|4xqb`m@zpv8yxW^ItHxTG{VN|iFrK2H61MSszZKhZc@h6jOv=Ud@hOqa;A;}3 zUFq^s_)K7g{BtKpt`mmr2n}hjSiGoX*jiThOuz6hxw)20QR@~+BHc=qk36PO6jX>MF9O^SSgA@;B;Mbi-3BiGeKJ}ox3+q1S((0GQ}s?vA@Q}yYU6HWD}Kt0+u#bEWN-6+ z^3)-yQSEiy14Uy~f3VY0x@ETxM-fBIlIc)z;NVB7Cmb3kbSd6-klpV88<>}J_0(gc z%liu&rMvre!`s`2>l`V12i^eRcdv@h8`D3|odTW-EwqqSDqoAPO8TeD+}ZamQrRj^ z;-}57gE;S{bqE5O`=6TFxs2Gm13znlbI$H~bS42$L&(pm(5=DQwM#(fLeEHBP%L@4 z9W$Kr5USl1p2efSo-(r>5sGdSSWWLIzxIfw_j;T|rpDD&Ot(B|nC#A*(O}5V`Cb9R zziW)P1-P}imJJlCFiZ>7`Wvh`ahKu66$f7oF8+@uBGcLss=}Kk?GZjA$egFCm>FUv z;e9yv`^ZXkqPvpD8GnA}rt#;<9g2s(Ba= zL@sEJ_&J7Qa_YE1yYscL4i2N84GxBXbNV$es~jx?TQg*!Z9s}mpM*0@fw?-%Bvk$K zgb*2_1fPkd_e9gUNgIOac#IIsyp0GB!iHenZzHn@{3d>SlNH|d;zu*U^bGybud!Da zGkJnm%$0WHD4laIFeQ>K#0<)sHJ2~I=GEovQ{Su0SLu4mT`==nq9CG+ynl2S8(L40 zJHsoP11P6UY7QxId-B{%deikXjd2OtTSj|3ixc-b!#uH5Q`<<+qoTCh$C#=PyV$OE ziON*b&8022+E#+bWhEHSmylH=Oe{?0?EkI;qxD=lO<0{*q4KT$1t~?2iP=Qa$flK% z-FxrE*(}pp?jN+&-u6L-1|oz9RF0UxowWv}R{>S*j`hCLJ}{xTE8BlXXXP)v_YhQA z5^(f}z5B%VEK|y`+>CpTmVNEDG!A5HwtKQ`uN9IOuV+Yw`&ah&6ib&vCBZ@Ofcw4R zm>q;2g-UXOhyRH|f_rV<9(FC5Al5j5hrTS{3#O%SP2}j8J`xudJG1O*Da>&2L$P8}F}(?; znWA~3tbpHPbS|7<{YW15p~QtgPg{P4@bwK8QpODnuR@vhM=O(mOYrb30nMv)8h*@~ zu}A?|!R7Kr5b8Z0Jtugr+lb@%zO@l6Ccc4r2 zP<3NC;&P6GnzdMoiGLbotp7XbR~;WfGnk{@)WF9pp$?*pV2`=8l9`0A!@qNF>>aj^cc6P|G&R`#)-Std*Ig{s z*bKKDps7VVM5X0{bK2uo&SIl`q-la*u$hM&2cj4$d-pQe7lgdccH`zVU$aE}5$dpX zO`qU%YXq1q^D&@i74CC4mXCL-ooIg75e)mmG46;)U*~M!vvi04Wq+Yc0c7*Fu+la7 zgyG0L7qZoQIJ1Aol^4^X>v4Q+N_vi|u4azhACX2RD_C?e-JXy`C8BFvIs@E$ZJJmR za51GGs}S%sya}=lI*-CJ`1z7HEYzK8p_-+%h=ka^TtTs1|8w6djrr$-I|r`K^0nuj z1JQtD&^K}-Zj&?3=Re;4lqkVfGj6+n;hC9r;r{_w8~_yfHL_9mH4%C)Ha=XB(=bIU zf>Bbj)I`^L!0lzriDG)tiFppQ<1eMq!#>KIBYEC!mBwd_;E+$NZ|wd@9BH#JYCSyqrlV!_V#8^L-o4yq;!%&%Z(J*txXtkd;+ z#vZMAh}()yB@-La?=+n!Z?jIF*)B4rSZZ>-hNhFD*Pl_Jl1UuJO6Gf|wV%Oqq~42ELEp3W=}q*J|BC-b$EJkj7{0s$Eb6*r%; z+2kI>ddow+e#Lwca2i2ZoGs{rn+;V9|M;c8LzjJK45WRU_2dojssB2C=kD4~tL?qr z@|tK6FqE-tF*d;+I})Ll5Sz`Y48|WW;;su(pR3;cf4{huPE-E;18;!0F{_rSYs$6B9R5$}oFkNaP*;fwQtyS1N{`0U zd|l~L#dmr9M78AToU($Mrm+)=G)MBcTmV1$Sb?tAR?chpMmg@yAd z9adI}`@UHQdfc?PaGGCvFm33@x+)lQ1UMKXwL+@B)(#H%DPkrvqmtsu*W*_Ak(0Hi zr=G1BKfC!t^+uQF<^G?Av!wnKb^+_;QWE+q?ro~ZHr!;cQ=F7?M19|N%ez-<8{qq> ze6)P^D4SaFrR|a2h%nV5(BC-YWYoS;AuBRZi@HIot3hQ*T?yj(8JV_C@s5I2nWLd! zPU{wssIu(mkc_KB9tri^?5!F=3`YjKPLW6UsR1B-Xy&oB6y|P2B6?vbw1^cRdinRp z`AT%)4}0k*5V%eAcfuE9>Z?l_jzfE_!So?R3ESG2EEJ+GBa82Lju%%U!6NoJN0eSq zz~a;32{k45DcYvujKA@+BgoWexBd#ZHMx`mWdM0PG&hbK9!T) zaM3rE%R%vKYUrvdB(Yq_E@bTeJx1sHPIqo4Huzb)F6Z39?32N1h_p%m`3?HVZZY&< z00W?MkY#R#~MX?oaSm1~fX z3c3us`48JYJV@;t!HmefvqbZKF;393;^zp0Sg_iNKS?zmu5EHU7(Z%IKr%k$hY3Qw zLTK}QtS%WgTa&<7vQI{cM>KMXwh;8uyBb=8VZNMAMDM7>2){ETOBJ&I{lSgE89Is6 zDW)OPtw!ILci0!*o8{dfj4*QAhip5VDjA8;TAwkXSUBZMWdd zT1W%na;gV}@8H}icl(`z);yvuFq(WizU#CdyD@Wh4Ug(0f3<*Cny?;vva=V+pBCp` zN9%*#MloE5+n^-(>+HTLnvc&pP)ToqJ&dWe2^z2eCP-Zm6CovKh;jdSb0l9@EMME7 zUs?jeGN;e*UG{Nq3_!8bh+4w`G|2L+vK{qxWUEoNMo}h>kX({aP!Geylm$Jk?=;e{ zVhZzuP^i4r=O3s8VTCNI*(2`{=YfohQX}pq1{jaLPwdbxYbkl_*s-UIGK1tkG> zKlY<3mvqLFP+eyR^736#@yU_0`rwEnr4=}sagfmqW9ZKlQ2K zO=407Wb75JHV2~IOa4M)TX7ppofS`TUUClQp8MJ@2^h%Bn)yl3@jWuoRU&d)Pqr%m z!pkVA-zdv$+xS{m0km9N?NaJpUv*x2!4Y_nE^hh^i?GQL`aL{J7q7bXA%x9Ne>&(C zrA7Xc1(dBrxy8T=O#V;gy_jfLH0M!G^-5ZyhJrsfccNUd=zw2@9>E(aeOgrLu`{nU zeY5@~Qcs`1LYK~60m6ht@MQv5go2dAcEbUXW=$30eHY$5v}^kV^v|@8+G}6%e$j$} zqS8$w_YPsn?}ri%T0z-zKFcS$zn==Tg032hd>g9!nrDR8Hif4eX5ND|!J{Yuul{A2(0@P)`*1-&h=^X# zny%e|II(q2=n;w?x^*UFRs-G!NvI3GLog1v{tR=M?bS^V;;P5_=?C~@)U<1rtZWv9 zC2MI@4b)2@orE7>SydeLEi~}KG7YF{Ke|^)%!BcyqCl5E3)dqT)7XM_&+-E>Z^1YF<J+TX7;-ro?>3i{G^C~^Ms-y2p7r&Ib2TV@SA^@188vf zrPP@iS&>}kabR5_*oDK2CC89-4KGV-9!vZEdpo{Y8sI6q82$G^hOAY1P;3k*Qdcg4 z0G6O4(K&_wyvO$S3nBeI(A-h9^^Om$VgZ1}2vEsoWdwr4HD`F}!x`pS5Xesmynh61 zn6G_;-twHd(fnuQd1p+i3(Hr{vA>k#fTk)?k0L*HG zp*t)=iw0_IraEJpS%08+`Tyx83-9+o`sKyOTy^+n-KXNNL}Nq@M@t{l&WP;}Ge3pn zyt00D{kZPmdFJ@2^4nWH7Tmu7?h%R$KKHvjZ&T+LTgZ)KFY5N4zXja5 zoC}bnI8oo?kFF5>^2FEYq@sLsA%4WRp~W3*UQ$wWZNYIC_3nixjp?u8f~vkEEZnYLg2B0Jeg7Yrzf?7c81`fp3OVSU-J?V@i1VCB z&uOqA8jDOv1I~XN0pf$_1HO9>ZA+LR3|>J5%*%_Y;=44Kvscoh5cHU*I5+$n)M|$@ zbhBd+dzKN$XP#OKmqa;_1MZ(l=#vZ%z@WapJI&3dXebR)3ke^_a_No{`pwhwQIm=w zUf7-`ZI+W6!89VBR);gnAA*AwxNkTa(-=7f3)6MRnM8p};zA+-3H_vbbnu3rg{k-L zJB&!agdXpmYNMtFCYja+yaeDTI;sh19NUUgUC@`e+#YuZ_+lE9=k7pS2#=JgW1R};#L(pS47($7{;UPtMg7?vdgmX;CPgR|=Ee!ptzqH%18Xxp74JQ{! z)ee{WB}dGw7-&D<{RaEUPOlSM5xB*Z95u1`9^M#IrN0Q*n=yfZO@$(EFt#Hw+Do$q zPSWZDWK&ENG>$#h5-r=eh_uJrNqNXFvL=QHadpvY=>IHt23+;Fmuma37Fl zB=HmtD?9tGpR}z_Z*FzrL+7g5e#{AfY_`O|{&#~DC))D<=_vuXh5XG*s;UdyG8HB! zLk6@;mHbG9#gE2M6mxf}Ud}h6h5k0HGw=Gi*LcZX#K{Mtb!)y2w~`K11%~|>8pi9J_?AClgMy-%%wPdx4*^h3+k!<6D^ z>@5NOpRDljarsh1V{;5b068|blN|haIHuMT)!t+Cc;zQNl6-|bT@X97KPcC#4x^qH z#7*Bn{6Z^r8p-CLjyU}rjOK(Q9#x@zVC#J9Z1MYPrn^u;eml(cHd94 z!f}pNqvdzT+?Lf_#UI6eF%8_U{5Sb`&G7ECq0SV&kIaIFI-yoPK8iJzX*4mtx^BL! zQK`no@oUwnI+7no`x4c~Hh_nYy%EWjEx9pTfDjw~2uoAtU>0Z$Yp$}}LL{@(R&*~K zHr8T(%O|xC{jpuwm>Mj@@oxs7@zELi&H?DW9_FZNRX$9(c<4ml+ST|n(O+&S35d11 zUJ&Qy@YN&DLTrh< zKk0V;N2(oEJJ#@Dh_dSCwZ@f0;*C~8Z{r=?cEHOWOqL@Uh7smxQPMZBz5%|N%u(Bq z2<`!KZ=%+aiIwStR-*YE<|D%_XPJZPsLi<$A9w~g<3^qYlx7{UW-zda-Xv?U2W>|oQ!8%}c}Qdp-Q97)J%dI>_>Lvaprf(_ZsKp7{-S>UcxNvd9T*BCu@|= z%Xr{G(Q2&U@N_=b+sIf48+;#HpS(*t5D-vG{;omt;r)!-te9g-{Vq2r!n%>#I#hjp z4)Sq3;Oez=geu(5_yQydN@|rx;wf{uW}s!)^GFq7$XvYLrjOrRw%k9XHOH-td%}dt zyw+h+o5<{%3G8L-dDgO-N&cVYN;;-(8*bMbMznC_&b>s~GMJ=OFbvSw4(CCn6M98S z>SA&C-OzX_swBR+{+bV?Z-z!(xn}#+!1V)1gl^2Z($M7~@N7`I;~iM{eTwFMAc@hD z&y!{2*3qVJb84S3PVmJj`QB2KUtOaYD4iP+p8Y}*-svTCCV%7sufm=na}&DX4~?$A z`4oo9fdS3=jKti#_;{PUu~Q~hn>z)tmVv@ACj2ahBcN zQ;TI84L&Q4qQuYT0Rd|ti6RzO|*wdvQoVJ zXq;0)R#mpQ$L(P^=FhEj=>k6(tGmBdbjKjagur;0BgFW4aw}#z_g2d+8Ntmk;C;gu zph;k4ymuLcc0sC{h|NQ@qRe&QesBWi-7&~Hg`kpyaWM|+`*io+^@p?|{B|LV85%lT z=#_221r>L{b*FxG9U8H&rAvLsW4$Pif~-1lXFxoYvV=mOuPK6CcxO{H%#)+?5I8XV z_B4zNmi6)NQIR!FiZmHyqaFIL7ZZ1j`5B#UUybEX0#fp7#7;d{PS|mvi`NT>P=E=| zb^_Z@Oa=;($F9TJknC05hQ>#;@R_{liKe36tu=NU3|QeiT0@)83$= zK>hV%|DSV;@R_9~R_YH;BzY3u4b-+Z?Y5Q9-@(zV2pbwGo4dBQ543vmJ-QyNy{wq$ z_Ww)6owTLI)|_2+wB*_DLUPbce$nz`VEnMV{Rt?kVEsC$GXLdfKzwX=2I0|;+|y=o zpVse%_53TNI}7fPwZ`7O`CFk{0UJGg=DKuYu^|lSBaO99J`iD6>laB8Yi?=|3VO;x z$fE^dy+mDCZsG!!m-&#N@Y9@PvBEc!$j`6l5>(PtqfKsGPko`H-csYu*>shWO)Yi6 zZ#slRJ6gYiC_2I%sQ9JL2;&wl&vC7?1X$H+Yzs{%W+2BZy{hF=^8~CbT*>my+EAJ) zk%zi1aL|1S6wa)X!$DStoaVmH2-# z^@_((o-V>9;rfx2Ulud*-nvTrhFC7C+I{OqHqRDbpBw&_OFfOLHnxrxIRmWG^NqCq z6)SD`(DwO?4I$LWj)-#}1%yw3p@O6zv?MW&)W}#>>X#1P zXqRE(A9e1G^+l#&S>}3`XR6SU1X+*w=q=gZC69FycpqS$QJ+XfXDt)ZP^guq45U5q zg^w1|FfguewhR7NZ0BsAUi=dgxkfwONqE~YV$}3C?OhQz?&oQ{vq-9RYF&tqo!UNd zv(uE2!UX;s;=0T2O>Jm#iRJ>)``NrlL+qiY_sFva9;l9rU>6j?U~!8yv(- z(9t@88fyG4Pu+fiB2Fr-J`z-X--AghoCt{eiqW8d{Ir-$bN!JNFN@R?& z=PQMZIhq;G)oqjt%vZlmRkv!`W;GD0J9bQM<(1M*=Zo<++A>8eJD%b}2wn11qz)8( z+K;Q|iX$J+SR)fmTC%)kwGc(@zNBXF;;VAnU(@=l=m`-K5VF#XjZL&v;vXZEK8YD^!pSHm>WN{?V#2!6p zSFyK73DWq^#6dDRciR6tJTD8pvJH?>b zBuzC;v8GXQ2##i#j(T0%6Q6Y#XI+rAQ0|10=`5GuMv{V-RE|jU9#(AlwbdM;D(VaP zQl$e|xy#0xev7KS@QSuS2&1&g)_y#(O6x$g zzcGpjP`dOIV^5i66Wy|j)+GGK^GzpGGFkJLk6KFRm`=y#c~^WG3Qph)GO2$*EJFAQ zeTjWf=5R23Yj&*O>MEMSGKLx;1hGj19DxLJC#Q$W%KWms@A4c2 z=IbOe{4G@7zQr8|in$Y%HJIgh>&%?S0jQ-Am zGUAjteKhLg>SZ@92~I-}&J*&Y)q@u{#<9b`ZaYzVipdjl=dmLtaqo`Ns}|AJ*0!`Z z6_uUb@~c7@f~IE6$OV@$&}`}}q@3&p(yfkMt1dv}kE%(ulh?Ji$3mlU^uYRhC@aJi z7c7C0CvG$%n5Y6m1xESz@(n}#nUW-TfBG#yv7w-}?ay8On2QhnSX#&fg`fbHOzX-CF5!#QdQb1$ibK$m0IBc6l2Rw zbpikPZJnCB%ZJ^;y@~Yplx(aFGQ7T__=9XUIAg>^A%py*U@*aIp2xGvR*7B{ zm;1RZ!T+^&gE0?~P2!5BUDRN&r~eA2nu!_Jf#z4<>NzQ%?ujsdF!%|f+;q!{*was4XiF{VX9<&K2cf+A(C=li@Vhyr7Aq&8U^Pxxj@Q#9a+WcozY6|w0gC~b1yjbQQU(1q6W$rVaUAT#Y z0I;o3yaGvv5|o_-AvgAe_ZFL{9l~O=pcIm)5$tik)XQuRQn&QUx6qV;y0mKQ;XSKZ zFd6kqu0Q7kd9sTg*T_h(<`{?r-l@2`286bE^d(ROn@N5{@8Jjb{zlKFH=Yde%oa!t z^{|vkdL;tVB8jp?oj|$UO6CP!fZr2Y@aGLy?QhZSIU+R&Aeo2z2j(tBggT_B$b|FvJIC;B!{H<*t&b*o+Pxj37+rW__x zQvZJP?DUx0?t)ox zMib$!z|PhY;At27#id&KkUISe*ddZS@-hwBzh5SVU(oYgF$6&!Fm7m3pe_Wx`Q_(F zcDmJdwtfQQeMQ*_0-_w&`7b>lrUoRak>7LTR70lZ5iYU}E|-ZySFamUj-hJ{nU32D z)r#W#NP;+~0Xd*@D_#$xk019Et`Ba3->i%@<3XT%;d+J-1U2S~MNOc3IEA&k^>tCm zx*R9JcTQj0-W4FJDhPc+e^>oaNtqTy~g8RqBXk3ng?#)pZ^1yxWM%6GaCD_|MQv;&V z@pXQdlfj8ypbKJ?NuR*oQG}=(M(_pjTa9$aKbdt$G7i;hPn9Y}C=s{!{;8ro2LQ&; z^;f-zFa4K~DaD1A!PVBuQ$n%@_+wIRQ%e*~LY-27Te9?9>H(NQ zY2u38kS5DA2V^Owj@0AikB-2O(-4VBHT0JPO2}54vL0`rvh3PD4x_*&<1r`@-nlv( zbb$q*4q=)5WT?E`X6N_?lR}sS%{rBTD_Q?e$q9W8!jfR-OP5xc!`-}isd5pmIwT_<9kI0+$sWp@v=6Xkn<`Zu0^1lxZaSmoTbGeS1b@LP$kUA zlkff!ZNgtl<O~zNYiAbon~c5P<~Esu|GA0^KUA%O-U{_=%)}Ag54c z5;I8WExo1n#h1p4Td>=kgdhmno`Z&X45UpYZ6d2GygU7vhFf5rxL(+wDGipTmND-I zRuku(qw^V~CJJ9#IB!NE1BTI}5{+g=#ycw`g`DLQu8g`?h^LFEz61eO+ZyY4m)5}o zbmTQa5_Nb%k{ZukqmY>r#w}a4gvNnw&ps&8fdPCM=a8{2H%4w9K0KeYA|C z^o5KX26dIzLevZQaKhksYxD0ltFOwomM?6-)~hSQK=uwK+syap&wUN?%arJ0r1=53 zx9)vnRguhxHx>xnsDR{e z955w$iC_1Adp2Y+yj7_vAf@UhFRbdX81fv5Jszj5`>(=Qvu!U5Ai&Iwa)hAj_n^5- ztxjj#!V%T~H}d2X4Bac6DyE^5jmvG~{-&JdiF#MOd8LP6Dzx@~g6roAcwr5Kqk26v z%_*0e^Gi`CS1`3TM#e_fS0q6<(YFsE7=$)sf@Q4vso6t%&6-HMTm>S19Lj`I7^*5n zs13tzY&AIC<)E;O@!_f&naRe@evJlzy)gU^Cikag_#<$>W#NNl^NR#BcEulv@`lcM$~s#EyXEfV{Y9|;2rED%aqgcG$1{mo#mJR z?_=%so)39=!* z3vM;u>^zPb4>x^5(W@-Th7q8r$Wlk+#vR*foot;JR7ArLJx-XpI@&LBO462dV6(I@ z?<}q>3v+<#?|hkolTK-Mp~3iSgZ@NAk%;%4(xxQD(N@2BQb0414eA<;Lg{fjE}IcQ%CJIV##XI^J%zw5EJxg(|G|KF>yQSbU3*O3`T6@Us-t z=N%6;p(0p^xug8k%`W)q-pqKjT2Ws4&qZOW&ai}BG_@P$VX}7aVH-GhOA4VIylF7F zt(cn+VZ?J@&jd0GqE#$_BM|;B*U7X$os=J0@>@e77#5z6?fh zxO%1tGY*yd=)CsaU!IK6-zJE=_&yCwt)xyRvS+6_N6jq%AVznLRD%Ne$B}kk!7`zG z&#qa6Mi=YrA&XEg-Wp(*Jz}c9D(T{F$vx^B_3`1V1drF;b0?;x{B!zg?PWb@-|{U{w)--4yTKh;)w_StAQd?QNH z4@ve?ARr32HAUbOF2hcPi`)+BuGnaER(6z3gF9R`&r{QzIeO-_IqNU>+<{n!FZnwa z9kdZ6N^WKn)-u`l%M9t`BLp_TPisT;JWF*KRC{ZmffN1CVQN5LR_}KUH@{9 zISkszHyT9}hSB}c{qczU72b(I_6Y{5rS8$GUVaTyVUw+ zaW||26D$i+)74oR_QNwf6Ol0@R$j^KpVMm4)#N^^I0EM_-L{dhpS1QITNhOXEGUkB zwYfn%e`)Yv>;UD>m*OPa$PYcZN1HNA{apYm_|2dh!8G!fBw~n}rDS*}%ntqpfgdLS z<9tIm`$N1f6I=wKo?Bc0{Vg^QI}m-9N|MlVdW8Xf-ogKHGAz}-l(J7|LQnn4 z(}xa9U5b|=+^AUxV3!=(Y^acDX3rCisoxi zLMR@xn~7;E$Tz#d&OG6t4=qiH#^50f$!5TA7K8IQP?H@Jk4^a8g6px#GGE9*Pu>&; zF}|!JLm#|-BSot1i)}&q268?=vpjA+hxZ)Uf=`qv0!63G@Wy`R4i^4Rd zk;9eLL3dNyiL51fbBCe~2ptq8A*o{{n{!i8 z4BI?d!lS*dB_Hk-kZ&(I2pdC~D@yF)E+pV=d$bAqDb=nJ40&Mr(6p(M@4p+DT|1+xHf7)LjsjX@d4`MS1Nqy?H|;kTivG?&+PYB*8rZ4bJ|WJ{>S? zg2qMLqQh+;MjMfbx|%ysIXEBYH;Q&L_c>3=!n3Ku;`*&9_un_8mRDz*nf93~d4k1| zgsHMZ#97yiIzW%{v-<5&>>a+xV}5a?Ri&E2fi8XW$i%y8BhI+hI{nY5=d~H-N6eA( z5T>hg=^I_@?Reg?5i#drzcN%&rt9>6ByR_=pX-P#gQI5RGJ9_bN1Xle0FAi&&t5$alMHhr$XWz^L#=jXLITw+-K9B}p zf20%R+?@66@ab1C>!ncEJ(U#KiLe7c5n&!~`19$`=j z%nh2gGSh`1|AD8lmPz){L%^17Be6+yX=O@p*7St$j6o!+;jMch1^gt8xCsgPPxDkh zb^RYd|POxp;@JqB;`T zy>unh*vD%>KSd4wo{ZtprY%V|(zpup!c_H|7?}-cw>pMyY%xWdgt_~r2@ZW%LMoI`iyU20; zmPtYZ*rCe~hEMja1K<59L?H!EhU@tM5PWL}ZZ~hcFrL0=FtOdg{}F%cDu+-+Iu#jm z?`%?;&EdkQtXow{2cMeg?=~lmcxi8ST>p5m4tfeCL5B&v7%K&^kfLbzrCaUXPvO6} z<@xD7FQ!OO{(#(Pn9dqF&uZfqZTQk3Y@fpiv68uZa1-e(G9 zUPoPsk9h!`)&;SJX`uUF)&kw;k5V|Dg(90@+$OtY%A@c)n{vNA?{;MkaHg$IU}2d< zRx}KBwLABU#gVdf*SHgAvLL5ijG z;~9Uh>b04B86!aU1vtY0mf_uGOElPUUhxH2n+8wtWx*NQCceWkUAou7ElIk4&O=1N z2IAU|qNOcnIwhN^JF}{Upj0ECK`Daej9m)2_D5;;hH5sxQR8C>E~LLDf@imPCMX0p z$jFb4>6Kc4sqOKYV<0YW$u!XGPw0W2>(S?cB{1p#;GiPfmXC%AYIVwl$RDzkLl+%n zsg_1|P_0Ve9DQB^t(16N%tV@S_-W~f*YDV9)Z-rUgb164=`kyZKA~WZuFzsT+P+Mp zvB+Tq(QR8@+fZb|&VrUyD=GTcj;8Z+DPEQ+60t)bH7x)wK+?a9X6#_|HZB`to<}%` zEWS7g6d@$J44M}S7ywT?V&wH}QCNftCO+MIs)f9BMXjjG*B(+f?WldcU9O3McRAWs z{Mx7qPa9WK>yQM(Xv>nhn8^XEHtRJ2@4ra~d>i)uhUA3vEBEn|0B=j)a8L8iHJGb* zhys+S_@i62kIs|;z7${{)t%MZcQ=Ld+OFODE`Zz;+5fto2A3JjkELV5lMoh?Jk;`-R3{i^Ck@hc2%%^it<(Hiz2 zDG0A_TzO90Q!7Do%dYf$xl)qtgw7#?eM7-tsvDqRV(@eVDN>->xPt4_;?Ve}>jwBqA+yT^>r7rMYD*H15A#UQQ^&cks&yn&m zfYkbkbGB|SF!Ww3u243F7|l=1Gd7TMQ+;_q{!+Is#pCn9l3TB4#5}J77W%JgUoM*G z(sV>HD(DwmGQGirp#`*C?!I0Xn&tTEKU?oDoHdlT@_NMV`Ve;}FBc0v+(S-GdNPZa z^|wjb>;YN5J!TbSFrKphG(LyxIJl4!=jzz`RHM92OmYxHWRhMIzN}D1c%W%%dJ`+;d z9w0WV6|8FK9<@Xx@v{e@NhCJdI0Q?=Kg#x#SLQM?#=seql^)LV=vlEaD{^vfD{&;T zH$Q?&^FZIIEy!XEA(UcU8??NKc!su3h`K>tEvkZGPfMxAUwNub$3gICSfXqCUdZhR zz_u2sy7E+XYS(gXBzOz&@HS^SxWL3>zfQv5(?Sn?_VnhiQvH-3A%{4FlyV#<_fbQD7bb? z_aJ8MBDwuizna5)2>USWjemDSe~Sr8@Q6=s>Bu@@y*KG)nLAs9P;0*TCc6(=4;aT> z6a2jok1e_h(u`=A*-`4E&i4lKa~ip3Mh%6(+qoR-tTTR17ROuPiW@f~QVeuB%$`vs zbF8jI?%->UOTFlx*qk?jKoO&O5!CaUksz8oGNDG+QqyjsQ(%{U~9L zVJ{0yLWV!wKTgE(TKOs=GVn?JX$WitlBiRDMsi_G)tg+{K_fKuJf>*U7pw3PClIG9 z;{J~W={$t7?1?nJA2Y{+i_dUY8O$ml9MO8Llw)^Yrtq#_v^-SG9V4TZ1-78BL~+4X zX2z$(#`QhJWrAXhUG(0$(^GvY4?9!$bhfe49&!+dq_N_LlcY27qC2ys^w=z_BhRw5r-CSz0a%KQRaOW@&0*YOy2K8DFuJnPT z9OTVIlAsi2rq+JdKx}bdXAgAPobOMJOYfI1+&hOlmq-z&5SwlJgU%p@l!uP*e1)ObKqYN+PQ(}5t#lKcHD05{?hQX0EC?SFS94g;h z7h7{sqymMxNr`@I9liAVqINFg)omWPb{MZ8*R8t``Q600@n(o%9Gj=Le@i*n(hKw? zz_U-5%>)i__6;BI{8bn%8CzN9z60UVKXph= z?w=BfEGZ$LUhp*VI#{NaB6Kn+z4B+E{@yp-ncSNB-l%5w*EI|mGmW&$7lh$*&1TnEuO?-SH{(d#H2{3Ybuxo&>Ixy zs=}@_B3KnUBn)R5glSBoXnUM_o014Rr|LdeHb(`1Jx)hInO_+cJ&?hT0qWng2HRg8 z8}lJlk*jSQD*f(S_A+x9#s)VHCN?!~@oOhG%9&9K>=>!!wQ&j?xfo@~qhBFYk-4!7 znkvtJi|l8WvMM`F&yRP3cw^^=mYU!b#)Xya>eyCJauu|w?s_N0tCWAMX_e)L{@o}HQ6X^g^+TQ&2yUA)(lR*@imwLRpX=9sv4?w@L zk9*1+wrZ}kBv&a3Qo;dYojh9!B1u1taiG$Nmof_1;Ib@Y9^G}jyWxkw>5zljs5^r< zvkepQ^WGvx}6#*qjtYtZJ+UiK5@C#SvD~gugu8H6^P&(lB6W z3UDBbADIsRh=&z(0CfmHp!2vFtAb@okQO9W*qcf0#K5wG;XD^FZB6kBH4?ZN9CM;t zm{M2^)jCi>K-oy#kMAd5H7XH?XMw=3|BzEmR^T9rk%7fpxK@ow#aPy=XUwF$DN(KN zFfTod%~-zZ11`fd)gxy31Kj=OF53V&d)={h4xr~Eo$kfR9)9E71<@8)9%La(h;^11 zbjmnV_a}^VLscEplW85!p|(qO@4kFv%%L*{_%Po|-B$<`JsPQH8d3!B7INDr&v=j~ zzNyi4!|^QI3vG_me-3z?+u_xlfPYNnWx+hswd)_egnw?`k_nH>7|6)Kyi@O?0T}M5 z>`2JDMW7fJuC1@6k5?RQ9t9mDkw^-r;zutUu5@{%iU-h+EqqWp@fS2TzBxOz1vlWo zka_p8eUa27k_+(__Cl; zo$})>0#FSTz=*M3)x!Ks7*y?rwxm97(qRgC=g_>+@z;=*OL>PgeDkYHx%oa)(jiZ= z57!LJbZvBlrQ7Ji8WTpg$>Q`eR9tisB`;GtJwBO7S-7J80Y$Zz9ARr^B&l}8yRuVk>=MNA>1Gj=Bk!)aJ>7W^NhD>lSZ?v8QW&0D0g zqRa>dTbO*~$A9~%ng$9~-R&Tj2T=G3XUAGErjh8FX4wsMP5{ht7w4gp4S7=7%jT1X zH#Q!AKb8_`EVD(+l*_9`3NX}5#C!j+$FI#zhhsZ_mb|DrXaX>hk^=Ow+C)NXsv7ZI%!bGSIv8MM`_4RUa`U@24ynE4 zkYhkiV7dEQ3+wR|R-##HWI`q4` z&2B2D+L=#LRO~~20MfTDZMq%Mb8cX$ebH(h0xGIZZ0d7RCr}0QBAM0x(?>DE5b4v^D1F6>ER0J z+?}wQ8XYxS&X@`O;e@4M^MXZk#%2Eo2YpR+4B`PqH5uzhl3X3%cJB_p;;kMHI5?Ij z_tfe_-NAf-QoKC(=OBQLE@_iN?E#m4)FTb$bt%rQwF)pSyL10psR361T^> zp(lGF4D5>*m38zypV>r`6jaM_FDvM4e83e$bvmC9HS~tCjf+{kU;7FW{7k)vT7Kd) zoDP_#eyX_t1Kr;*2K}+;d|pwiW7s6jI0&aHVaf8mSObn=mD4(jJ9eO*HfJC%37R}U zH5R+b!K1u2C%r=o!X?fEyMMUr5t1xr1Y10V+H1p`tg+NzBwQqU&Gid^NSQ{d=12+Y z0qEpoZa~Sp%T^nYVlNuqf~H?RLUaW{u6QO#ITg80zL`7oQb^)SgzHLU^KGz>b*m?M#Y3jPrG1; z%FaCkdTMufz8G-!7v>Doe{Kn?!4taPk)sNUu(=_^%NN9m9_{R6@qI(D+Tuk(|N(#5O<*y`%CW0*AYUtDOF|h3BN3`5!N`%`28RWjEJ{e)DS z6rYH3UvNDY8=}z&761v1Pe1-n1<I;hv;uhe6e!aqC7b&-eZ0hZC{(k=W=9YBIC4*l7L_%eM@OkIs1Sr z0q+KS<@r}643$}Og+qjfL}1w z?l}<#M&)CnM3dNik#6jlx3E;TzM^D^wRtGRq7bF=ELc1Z_@}KB@xXY(TQjoj#pjx} z-I8J_9AuSfw+9K0)Gai5F<2eLo$T#gX&+V5Nx&Mk`yu;z27=3oMmGS0+a#azBK`GJ z80^z{!CaaugKlQ{nJOO>NSi1));nB{law{?r17tQGn&lZph&6*;Fn$2!>YsSDfT$) zcAv!Cl#0O5qig}k(gHND0Jm8FvLJs?}8H?s7 z#a3Ux>0K9Z%xKdTd!^|FQd1BD+lHU9??xs=`a!pMw5(x-<( z--UvLJZ7=$L^GIDdpn(Q)ES_vS#DyakSNGh2lZBYolXENb(B!(0`NN5Sn}EIE<+0G*BUfc`RvS+u1#@CM`^*Nma07A$Jl3RvD3D7 z^^u9gGV!^Xer}jkP$mZ(D$9ycD)|7$%5;!S*Tp(EHy5zNO2f1Ld83C@k_EPU?I+#_ zJWH?kcDD36ON^NrTlyl9g$9~zR#;yypejTvrsqGPsW=Pt_ti1mQ(moH%~-&tmLyYZ z;1!FqmTVWZnw6bF-CI!d#!_EJxvXglXLB_Ira8@kzlK>$R7{jIuEV7xIC1mQIpxWK zF86f&`*t}EcR<(v0+C%@Q22yO@=k&vBPkm6%us;tej4e%ymGI+^;GD}Z@XN-x(DSh z6<%7k=VL9+ai+oRmJn10whaiw1t4BV=TzSd8X9r6SO#fV5C14#hL_R?y!e=N|X ztPC+3XI;--Wpi3zlkdbEveY*px`K~bq~1CY1-jpfGdJ|#ha}znz%dd|Q7}-A`q&-g zGp0D-u-hGYQ2?Pg9j<}un%(tYGHGvrC*7x)GBMfZ;!8QLr?vm!h&{B62?)EtMbDxw zoHNQq+!Egb6TS3JcTcD=gNvAt_SN<;IVT;o3Vyp;3Q2&-yL{3GrmQ}HN{H>k!vfgp zcOUS^$|#Xr$Tt+Tgwtj1DtP|fwx(%KM`o|CGd0@HV{&22HR~*ZhyHye_}(K+uSQu7 zQO!t1vv`GVO=jL79)AaskeDeH_trXV6wL&Xs;w{`)IRWdNi3;H|B-;7`PhAoU5{q$ z#!{Tj&b;}c9B0PazgQhK3RevQ3$*zHDD+B!57uS0%$Vu&_Xy}Hs>uTB#-P>p8EKGCU9ErELtrq=;x+}Zr_@B=&I6KEs znOYUxx4d^alzo8B^#hO)(B`Li8j+-d6l;APw3*tJD5!8IwE04oSeDQ;i**#bP0+@& zWa@@joyfvQM;nWOG9ztv1L4FFS`1)y<+#I|d~H(%g?_X3jfzjLl?K`)!(FQoK7?w9 zS%B-JHUekCCm+k<#YvX8GMF3VG6Zgy=`AsC$s8t$Di(x+!Y!GIG)#gIoGs~aGTEp< z3PR3ph~h9e-7x5oS79pb2b|k$4Cp+C-hMbWj1S+mOAJ*B%rq9Q0Dp2@tju5Z`l4Dm z>Dy6RB3Z?z2zX`j7(vNK7vnW)@&$>sT(-1ac!!z^O|k5@D_a}I)k-JHQz({VqmFNE zq(?cu{i9Ys)f zpq#lnqdJo%I(KPJ{XE`s6~z*>fDh>yrSh|!!7rUiX5 z*aZ{F)j?V_dUT+S>J8)atv)o{Ev{KcH>pgjp{M>D@%A%Kwh#RYK{%rY-YO)04_rDT zyY%$?Dk)`CL(g_6v$2REffeY=OYO?{bNI25F`3ejDjk=F#TL<29&jJyfq&VTCPdu4 zIHxvmR_B@pGlN_#Jd$9wcT-tW|t}lBIr)x5Vad}uy zzW6hDj+3NUZ9vkW}bP+F~H&G|hKO&j(*Onroj(31Z6 zlzl0pJb?&k%&fJm!xD#q869PmYEqo#_u&xrlg}Lqkj#>WbZ5o@m$=neObi@gKZKeE z@y_Af-^X=$dZ3v%^)D$$$2Gw*s%a9`=lV}D7-$sEuY?oD^zNN4>BSzZ>w0|w+MV+# zg;EZE%igDUj=^j^HlIrPy%`fhKZn9x=P zR<1aKq!CHZd@O}8+-*}MLGNCfA3kUn&;Mi&27$m@p#8H$!RCGzJjT%RsK&jSrId)vkwQ!HsDCMRbUDS zNtoplc%wfr2t(c(&QZ13PyuX=DZd~j3fO3SPfPzdR&D~=nzh=p4Dh?krUC{b^ADg0 z7I26y8O&DTbItqM14xkRX@YnzsjlZ^y@0DhFm}Tk4S?zggVa-Me%CimQ)K{Ri<1elD(ft$_?#fwN3vJ2nXd zp7_ngdK~)6yt>1-06Qa4X5w=8rU9H-ph++*?=NxtgSy&$+})CY7G1heLj{`vNJCSc zw-II`rG>;PB3L{as{+Dy3pz9v@8pZ(Rq9+!s&Lpb)(v%7$elDnGy&M>*)GO)-%mDNkcGoIT=~b+$-`z4T z^^dJJDr;UlH;MDF$Sg+q=izwG zL(q3@{59AWpf7NE>|sOrhSpoiVPql&Vw84dE~z#8E6%X;ZIk%~63n!ueA$5hfCJ`zOzUOF z2}44^yA^~Q*x!s6wFe3hD#R>_pSh+G^7v{Mx&h?9H)zUF^%A1f{-@**0w!LN5WhBj zjk6`|yIJS+d9(H(uLEL_oQG5%X{pyjq`{xD+N!cj@`U|)RJOyophH=5FR0BQkF^@= zBgls@l-Yi1e)12*hXXF~bfa9Eb-DdzFq|o_Q&zM%ol0M?{yAqagS=8`{Lrk{$%cH{ z$Z$7<>lGjJdz=zZnY94D_siz21hp!m#A@(UB58$P|D0hsYXp$d=xB*_v2}9XVpnXr z&g9FqvHh-8FA)6U7!Z~&eCR!J#Mzri!Bw7u|KX;7;-l|~0B2KyRr8WZ4UGKawK2HJ z7IK)oOf#bpVY|y#Cw6g9`b&V1!|B1MW>Wv89bQuF9y?e}=WVh;uMDL>@3V7lX}J={ z_@jRx)MuQ4xch*KEx8yPZn84#mbR=!{|^HxlU2)B_wzy;3#q zb(sc2d^j|Jg7S!tugI7MwS1zN)fgjpaF$`4VFYkAME_iW(gsk0NhUH@mz>yjfq6=1V z&8@sK&R(+(J3+&!PmBq_o6&%G<0?@vM&f#mlK4mO1#_hG2mu=S)?3GK8B2iW|116j z1_!;H;K08Ua+=v(AG6Y(k zwKJ!BbF7Wy^gmF>Tbu>rG_Uv*nG8Xm{zXW|{dE7*ke?LX4cKt#VHw%}ObiNC4=BHA zi&5`KU9sgT63Z?d)&iuwXSbDPpY9}JzMMU_taeOB5XCOL3ui`4YhFWn(S3;ls)Bz< zS|%X7szW<8c-kcymyt%3jAknj$oY}O>Z_$;a07fzn+%LXr5_?vAI;O!96U9mfvd*& z+2y=Tl#I5uBGPJnLQGQe`gk%;dCOizD7)QPp9fseD##4g8!<2HRqIc-wzj7s_cQ`9 zLH><&rB@`9rP50RO~91+y}~mVl1qG&P+RT@A!FnT)SAl3AdW=A7>sv}jDV1Z8xkbd3 z{a*ZP%cqduK80-Ff3oUZY2HCggOoE3Y0fdC%k%$HT;W+c|NSdC`k_4*v}uQl8NQHa z3dW-klGbx*HuK~lq$w<+0IPCGxAAVw2@e(CIfy5@JvaohAS7+mi|tIx9gQQDT+1(%w!DGTum8(#AkW+qXu_XA9{qo)H&EZx-$2)_ zb-Xf~n^)e5?YNMY$@qB2X-XGgZW1X8V+M+~2f)NzpBAtq47QQUOXlMhkQH3(P!A9k z^nNhdx$mY4P#Abl>F+%?sZgHiGOXt9tB;ep2U$j>A_}GC&LG#}9+_#5y>5&N-Y$Hv zs)xwCK{&SZ9W~swfHf}zI%_Bb%;3Tkfkljso@Sv$`?eY%6>0*JvqjoZO2F%=zn695 z_ET}7tB=o$ntiQty;6v{hw1eLM(C28k)5Lbq?;d)AO?J}e6MOBez8{gTW~%CB%)*K z#z^8zj93E;T8EHt+s|veb$1y-Y22{($oHJ=`B&`)V3TIZtFu}b z-5{ICEBGI4a#329D?DqS*-Sgem-#YUP2{3dKMsiC9xL&+Q4I?AIFL1ikp}*!s*nWy zU~glz%+`l@dSH4sCX;b#(*2{gcPjStr~m3w!>rss<=8<+yt`Mlshhk4MZIL6`l%3J zSmWQnNu*msre}zUbLb%9fInNGEJ~fk{ewgdH^P#Z_@_CE16uKfq4@k9F?B!oXu^3Q zh~c7K(In0)ON-qu6Z7GfcMtKgWVs3X>U2<*zG7yazh7WA-fz}?uYUx)=Lqgh> zncCWH&>}B&2@n)Trp=DDxh(V69@=yTYssin=+AK-Uc-ggzbq(r|HSlv>CAK`&I-(L zGk5!I85hF z_D3)B_SYfc*k;-4V|=l`&_a(B8oXUjzc+eYlCLZ^hKBu{Up*)k2ytbv;S4b<;)ie* zDn=EN_ z^Y28zhYaHGoOMfQ)5z@V5SqeqIhnq5rj@X^9Usm8Vxylu6N=4tB8Gf{V1oLUj;tWd zq`Ttci2Y#EUh%Y>EV%D198P_6D=4?3-sG1<`_Ir!OD~jxmNUk+vXx=202CTEZ)Q`( zMn)d?ny{jzi57f?4`W?GeOb+0hhgT+I)h_o$BQm z=x`fZpyJW)(q~`Vu6q^a3ck9s&}A0N>p!OIMbdx3u2JgVrwHZsI%A#X?sMuO;^ZU1O=XgzN%`sH{?OJA>HcS!D=qs%FC>;~y=@J+jp;m=lZ6n85~#s_!O z`r`&|i{9N?+U)%PDi7E_d{=!XK*D)lI0|YpLkYi!gN=wafcXT%Gx0)jqM=ehL#07e zGn!mmH|ls+L6Jwt5uRlMfx2}BV==@gXUB41e4=Owd+#qqlZvxcBr?PH`1Wp%N7aLr zepL=e)>tUTjKW3LU7aFFS>WX7bp9!D+)n|Cz2yaz0fi*x-WsndS-i~3_#YW}nq?%# zg);IUAdz1#$gU9v{<;EYH zX09o`mzhLz@Y`#2qlvfyc0Ie&z`1FoVGys&pS3I?L6{360Kd~%=os)fKa!X8A#pc( zRUVAt4`NPxeY5sFR#spd6__SF1fe^g?*^iR&Fj3ah6NjLlz((GQiu0tcOav7tD~?~ zi1vu>E+%JRChKndQnV+HZbOb|o7sw`!#=59;hN$?(9eI%Do0MRmD9o4eQ(*pn_&w7 z&D99utgIT_*`&lcyFQ9EZ&IwAfzB>XnZM~8CtH80p`yR9qVujKoc;}DFclBWXR>XV z%DNWs%vi=7rGj1^OegUt&($uU>Tzn8p_c7K0jCI_<5U)iQ`!a7EaVr6VNT{|l9j6m zX316ez7nC#(XR?0y{d_NfFWGaX_74$0*RrP1~{fm#$$$8s+gMi<#=I5zQSbX_Eqm# z!8Y^w9k>M^*T6@05m@>hn-JlEh1(ZMA@9xkp(s9xjTN*pe4KPt_a4kL+wh=6ntMG2 zTO8J^^>Lo2HBMN8hwwz0Mdtiohq!%C`f+d)tgE1^digd_f}OhNe3>Z>6i85zhNAbp z6x}PJEeyAwsd6~}KK~p);ZY>PAB@P)+&8qudV_UFQ+9Xs!4O?X=ujh8G(zwGT`Ivd zb>uAKILP^w6jLRE30Xjt43*~1wsUF(7R;Dw2nnS@D=<^bMv^r%GbWFwpa(0O1P;2j zJaaQg=~VK|oiO0aokr>67RU*%8A-88@S`=V*WaJBYE3s+QK;IVgUbv&s;2ejFydC_ z!zx`?7_Gdr%?6Uf+)PvFm+{{Fd3yh=;3UyWr3HqW`R*8LWzi@bGm2EJg+Y-En%|;v-{fs8+NKCrG=}HIX%zG2VdZ^eWHH(f12p&GHTZIoK2LW?q)3hidQ5T zB=3Yvj(I9QldTqv#p5Me^khB&I@{+0Qj2Y;LRWrdumnRjlaZZkjv z?ROPBaW4n< zuqz=aG-lA5HU>!%Ye574>|+}?QrUdv{vSxhv2LaHGU#C9i8U@jd{c8>s)lENd-!Qi zQUOk~uVDaIC)*IcV6w^W4kfd!s>tqcEg6FnRA0(|o$Wd8k$x6fgWTV&CJ@b{gCH-T z=Eg#a!4;vC83C)J&;y1W1Vc%~kssO=ya%+^<;O#vHI9>=F}HTGr#MB6O==sh=X2{_ zT4W1PptsX=9!BCD8oQ8LJO23ORt>OCxO6;LK~Z#zHI+!J^`bFnx<4#*2a$mhM;i zdLbATn_6)X4U44m@=rhNKT8S%1*q}}tX_|v9V=`w5S%FmE%1|#9eA~eP4(rbOzt3& z|AZZ1=>`ZnnS|s}#a}q*ClLaOFAu;Gjq|@^wxcq@4v0}S2J`U$Mx|r+g#O`Th@X`s zE#-S%j@B;GkV)2){^R+myd}3=LxUQ*k_=QM=?yTqLmsn0$`bs<+5`4v2)g}fwMXKi z!7Nw3hWT3;uan-9bnnq4q#2IXdw{!LrXIeqiSOLlPBY*$f(2L&8!r>T|J( zl6n%Z7@6{OCY?@n9-DnEE;g}0>ZR*Rj6F@?jIhuCtk0D`0EOd`mVSx(IJ{^oTNn7r zum#B@T<0zzRr^Mxq17LxtwJ{?anS@g`Z}>%?E83smpXTwy-8l~{;y=bsJkvbEz!D+ z&t31+l=HTYtHPxv;)WB1Rh`_~hm8rU&om_DH_2nHx!LQfb^3WxwB3 zF&*SWSmt3$dh-~x*ShM|5#tNY7+#G09em$ft5QLX0jZh}u2-)n_mz&ySk2TFUq%Hs z0eSJ$DcJyMiC68ix}+5N2Al&s5M2-CCST_l-(di;@4c#`y&(d_>mROgL8GwCwW1_E zG#k+@wYkYGW3h^o++#09=J!q8s?SJN`Ry*54GKjuf^vc)+lHirJg~SkhtgZ!E587x zvwmnT-V!LhMgM3XysRs=zb|I*jj79~R7M0AiJFK>AP9m+F&TmZGt)V=J4n2IM|3Fs zYHAWLcwhKn^Zd+gqY&KWh`<8dh@92vkznu=Gzrf_SwBlkrGBMoC|~*BMSc>!E@Km*Oa3xfr z6iCM{Fq3Gd=pykK`ea*U+8?9tt50`pLe&;)hvhRW<+Udj@!>1f1+a#sXPefte6+g; zVK?$1gIfl1k$L37ztG`4Edw~fkZ)Z~@@K8q{RXc1ym<81%n}0hk~;p;dq=5h;wY?U z_ctMhsSFL>h3R>qh&r`CJ9JAJ6}VA4O12UT?!I*0269qb-qr3^LCXn zR17k*T5=ns2bCsDe*>OB46NAKmr9IYIj| zf%Iw+Y+gGWPaipOlMV+WqneBGj?gUj@cj&!1G1!xTkE5Goh6xat%g^Y+`^VAx4QYt z;a^DAJeE7zL0}s{ItQqWeGb2bJ+IOaJu^ZKa0}}K9>px z`ExZS3YJk|w^5^K$1?Fbv~fB1_K!IM*$qlB*p`Kt%mJAxEPR_>-OytIdu)gfpLh4g)(~F zih6Sid4|2*vc3!DBfPBy%&pezta0cxvvjW1D2}D-w@-P|axIVZJ449|Sb_0{G<>A4DoL6p*P*1YPprltb$r;iyUh4wO4C zDk?oYAa!S^}x)UsFw$c&-Pe(qi(#080oJR-0TEzRL_Fezi4Xyb<@ zhy=L|^gsq>rk1m|UgyV4@b?cQQjz?P1J%Xx(8pRMa9mO57Cv8H9fA3}x2cq|V>XSa zjSWoy1l%VoDVO4c3auOIU(&DXudgRkN)_=#Ba$#^ z4z0oSIGfZ@8t}mb$R$kZk&qtQK%l8!ONeL4`#pasnC(WKZn!(TCAl$iY$c8xNwu3t zH}}W*x>0zfl{Zti6!w94%Tq|9$51KeN)mjM+kMc8u>I%2PAb%XZyc%as`n;hIlob-e@f3Lb z;yg}gz+Qu+4BME&hJC-F{r4FJa9SeK&E-TQf;$1D(Zroc~+b?2G$ z*r9R&MGS@QExD4@q?=K?l_fccpn$)!s8+}}QBM! z3nRY|4z^!D&c^%|-n9Z)Cj}!j_5{*)86uG+#E2ohuU2yof=z@TBRv`t45BKvuNI!l z87^~^A!;Jklq*eJUgDo92xqc)6mDbna_MgOnSEsw-^R+$idU|zky5EEGmo5qSsMXo z@gDZB%`SCB4o?D_R0``*46U`mR3HyTbUr9i3XRf)#F8?o!s%jadf!jQB<$VTLV=c* zASU`SZKkLC^TPxOEa0u6R626_C4D-0bs%&xbJI#tn0H_0`#lZIa`n?(nqra}#sggO z%IBI&P2Y*iJGPqbu72uF0j3vpIIAprxmNl@0Pg0HO`nJ7Atlxx#_ z&}8w>^p2Y+c|0%&WYR8~0$x2&e8%}h)yT3Ug~)|K0;wYb{%Dnp-(_T(=(Oc|XtRZD zBD*D7o6kA|J-Tj&wePhL5q0hnNXd#M=s?-y$>s8`xyE+-SHS3X6e^#V{^f4SE_n^E zf+@P$D9>Ttyk@~U(X6;OgvS!b*J$k5-BU+A@m#fLDK^5}321^$Tx=w!;Y{CI8W?aF zj0%F6fCwGqXM74$T0ija1kDL9v!=9rPK2$z}38`h)uuR_GL@ooAZ2?z^$$%b-` zDRnj}lA(IbP339fpEQ*Wqdmb=?%Ns;+Jxl_rc5mTQw}%4W4qNPY@b1@04LJoO0i|a zqhx$&?!>-zvJ)vy@SRqg)9q<%r;Wa<29#VFzS%C(vEOM+Dy>0B*cw^E0zcZ`S5G3% z7^(xY!dabht4l4e?;bjxRpBWk9`q@uYelI6M+qJaCR1W@``y1M?H`{pP+mnFr;ATkO)^s z1<}5$m+s(;89s2Lk;KCkFQ#xwRFTB0$vZy;P>b}DZ3h(&%62=9$9j&TCUjk*dvrGl#cUd7}7ksB%?EAt*9uxlH-zl+@Oow0d|&ie0|7wDP@ZB3Q4Tq5Ps`v+N1&zQ?uK?g^(Vt8d%A7wub>B$9n$ig1`AW2_t ziwaYQe&m#~cEdLGSUy^L!A=);?Im!X87dc9@T;VGuR&^(CMa&J<`jKo1f)V7Zn^Sc&TWN7dHxWz4LOi}H+*~73ha;+Zw&8?-$(^*DQUPKnJ z5PDws{~+_yj`+51wNp6KCHP)0G5$-S3PDjlH3Br^PF@Y#kgD+(Yt#guwOW7nq7I!OJVUPv-Jd@CP=a);9*JeM=<-QpjDQertRhLkgm6S@mNf#~s( z8$URhv~J%&o^Aa-dGT_Rc0Q+3RAvylNw6qB%r{<&Ad~qwt}O+fzlS=bfhBdle`HZZ zcjcTCjMZ&|7@ZIfp52ZmHV~|HYEdC!SO-NZk%S2{kitZS%9Kfbi(yxVgdyyjb)Rp; z!ef0k!5h;y;kKze=)25FdKbPQZ=%{=E(ngae-Y3}q;~3(y=n3U&e)9D-AZ3bdB1-K8y6(plQ|(Lkr~hu?7mS8!I@KxVE8sc)Me$F zn+i5920WfV92=Y#dwJUUxXuzgOZ+hyEEDpUJgJz`<|6+l#qJc&xpHFneOfr)OAOl2 zNBu5l@=){Ph+?h|VGTTsZ0Q@T9&K6Rj01b$_yDFSemna)#YE^$>@1lLZo)%7h`p*# zX_;3qRt>vp?K9ji&`REMxZ0tnWvZ7=m5Fy}cwii7#J18x_eFy*z)%$|GOs=J7 zTWESH_Kwt-Fu?kiSv)B5P#Tdos_HBA13)inR!|_<%jBh2gR#8IKKvC37X2?~zE|!D zqVQifB`DRi1s?{N=?feo${}NBz9sRp?1n!@;e3k9Lt5UB`;1A~6T;SW9&<<)o`ID2 zQk{g-!yyv+`$Zd17M15xmb-817eDgN;_U+u1MQH8m)fDaqXXa_tg!WLxFT3djype5 zjCbo#bWhBLGyv&l zpD&LflX}P?SNN!Sf2CZb(?3p|68uVx3$~$pRbU&LsT(Ulg>|HxRtlqK(Ia28)&%JC zu$AP**{eB#>ugM47pvpu3|N9}llH>~&>=<80p)`3Bv_{xOXv9RX#YP&5N5_K6on6{ zC`w;dmJ|@p+a+a2_H#K;Bxp>}LkD*DJg5{l+=oYNZdE9&Ky#O`Np->fRvGHn5Bh1S zAb+uuScr4ODT#BwjgAhv5FD<505w3$zilJAOyRk9>f5JO zq)*=ZHdD=Bii7UW5i`ANn{Oms?5yjKBL+{XcUe55D>VTN*)~N zg6_0w`l)WV>wSZ0%AMl&2(rMA|Iw}@t{L>djdjW>SF^m3e}T4F4S7RuXGgt~5y^;H z=iuD?=~+2W$weDgV@JS1Iwe|mn!)kkS8cq8cdpj&atmr~^8vf3tD7PZG0)e$z~ z6dc8`NH=c;Oflp|o=(Y}zCRL>Q1MuyIGB0V^cIu$O>&2oHnPB4zEl%Q$d; z59E>yu)GuzPTjq?X^l&gY`&igOV9#PL!O^=5}qr*mwQOdUFH@m59JY+N`i8~8e*n1 zcTX52P(hG6kVW7F3dl%?Sbp#Y11Yg%L6YAy5J4-thnChX~ zTEa`4pp;g1?sx)+MAh<1OjJ7>e|Q9{=dFX8m#n#X@_W)MgabURrIXn_@oY<(HX9iF z+-;OM>Dy%Twd)|%g(j|#5Iu0@gCgtQn*(Ec(F6G7Fi6mP<##D{~28boPXog>2 zl+c@9yRbn5X`;-dcXm`-2tNT*DbyHVVcS=^k;Tbcx|>4&spe%zVZYqXEGOG*NIv#6 zXfi$*2|KF_iVC;3&WGN-bYXTs-}?9hmu?1>N9cTuM|&;_YP@Y9Kbh=wBJh4sxOb2l zg!)5aGYG`FpZ|uX77OgJ+@b}2LM620!!?Uh>P{r6P=1bjsY}A?KcYfB+ZE%?u zs$V*U}@O^RBX^+=Z_QFETm)HT#mh)b;W zxz{{}T?Gx8>A!q1&P(pB{xXypYYi$Pe){(-ZQ$Fcxbc7xnY?ue-V|IT4VRVhoLeuN zZ}=nXE)Q954(fEgC-q5+6yeG#hkFxuP(-Oyi%W4q!Q1>RKIO4=Z-$mz_(^B`pKMa( z+q5`9pAz5&aEr<~BPVujhkjcvy^*iGJvxLb-NLlDLdAshCRbSGUBbLYo??-?<(Vu7 z5$LbN5{E@cql=3gtGrMVXYd=;t7<^vaFEpt`ZL>~7zdv1rY!g5ZB@o`DD$il3uj)% ztQsFH`FSIEKDR>UCvWvExx`RG=q>bay6P{pF=?bDA$Q60jByQwlP^piD5kvmoY z1zeQWDLDAxeg`{FmXC2-f6ng|NY}A@1_xg|H#_|Fh!2}$Ush@CqEUJc@nzH{6~_Mm znDw0Apkt5ny-a5*t5kN&p#nZ5R-e~_QEB|FM^Te9#xT~cG)w%Spr%LTUE`L4OE?Vj zcs^x)UFX6>l$<6+EfPEG&gx??JpQl!3mtG$2uxfVY#%mzVKsWTu85zz0(GwvwZ5yC9 zs4v%>&p-0QpBZL~9Eh>WBY{zb?MLcv+NR)7?lD;Y=*xb(=2JtqrdgnSK*wSJm=j|5 zovY(;u3-<^`#nI&K$&7-%j!7o(a(MIH8g zH?GeJcO(W1Iz#0OCHO)SsT3sScq@4?x8FmxdkdAse3%o%;VkSKX78u;Ug`>^Q6mIz zD&rS~u=tP=Ga9`}H4BZ7i%IbbURwrrgihlh^m|Wrgk6$V%MXbAtlR%s`9C-;h&r?E?!lX13GMo+5P9Bs*?;t4JZQRww^MD{pA1lZ5tkoS4KT75u6lQNIN z)t>4;$x?j5N)kQ)+FjQ$XOio1E9tvM`sa3tTtZ5f z){jUTk0nD%;=k~V+;5hUD@|L&SdL+P2IK!!0DG;$?C+HUif;JmvLuWZchRS!lbdy+ z*ayQ%3L%eNw8e=bGa&q=^dh;k>P{>e$;hgGZ9#*QT85!h!1s}GNy^5}%trg1qjWtu zB(`I;jLqi!<6up1!WEpCkvw0Myb`a*2w<7~@boNbwHN7IOhr}+o+iaztl_E`m67_6 zU^|U~O`N>q8^y=;m=$0On(#@g(fGaR-eQWCcO{K}Fvw}Egp!sG#V8i@&%i&Gw5ug^m6!-8GDoQnv)NPkD444_$5R zHj(J39V(%COTW&d3UOs5ZJGg(fn$*k7=;NB-OdKSW)^Fw@@yrmi1hD0KzMz;n`|HQ zev%4BLmtL|>;z&DEBJP__A&@VTToh<;k?g;b<5<^+eK+72;kvhfvdb*+=wztA$(__ zI(nhXG$fEp?hARRlCkALwn%_lS-hU_7ShlP2OwDxnBNXC(bw;<;}zVx(*33Z(oMg-Q732H+Qfc0nSE(Htm4$^h}Uh{2j=(vE_9E|G5f zLz}34|m{oGz|&|eqc++y_;_;<~~n<#gA6vzE0ugYdw;TO*U{G4?03cd)@G>qQUle z_(eA8`5&-wnMzilg9*=dB{${$2D#^=Z9jZHR!#ObsL{wghx?^1?S>DAY8Ha2lbRTh#_s{W@FTX~)x;`1d)0Phv zpG4)}47s1A>>WYxklmK{(>K(iRu07RH$b+0TM&G1acP@*}`R{&b z=-%5LQwZD#vub6akw90f?D8AXn8N{{=<`k6PNVY>{Nf4X&KXd)_kq2`WTv4f6*r+v;piiPw6&25Dqpqn}tw&kyB*t()9TsX) zA5Y9m*=gk2!&ZIT7K3Yy-r#-u=DD{Hq6k&x#X)9QzCQQ1O7Rrqi&OwA+FN$_b2K$w=91X6uL8-*;jHu(<88zb`Thtmz<5;BG%$ZBsunbcA zRb-kmlXQ{Pa8K@h1)tgHfm;_nzQ1FW9Ln>xRTgamVeq&Wtv3Bgf{b`b5|MF%@Y_n} zlzo>w>rt^WmobZm^|6uESL5bsPI-1yO^0GbgRoSRrT0>qpc{E*yDG_@jy@e1+h3oE z;Lghrnd`^pEx_%TtYK?Yk>JE)jUQb`kk~%GC*-?ZmE9wax*D=Z=7AAKpYykFU z^fl2*aWFHh8D~o+8UUnSoTu$tpj|k?YoW$QwVX?*;CJ9+{?J2e@xpZ#Uo9Sy|2Hlm z0Rx#`8MWVWK;Ou2#)*LaWOsljOnUZ~4hfF&F(%BhEe z3+p}mc9<)f9oG>O`L5|vnrJO+0>_*%l&fdIy@rEMGQ=XyD# z7+h4c>4VAozi8Lz|2qMWs1ns*e^V#Za9$p-7r9Oqmr2JWE`X1KoBCjFmd-#K8js$R zD4`(<7EERa9yiMp)XvwVEa>eS$8`-@+R13?KOFPC);KimelZ+vLges!mbTj&D75*( zn8n78ZNMS8O6m0xez}@`w!==sOnxivXm%J!8tep)E*+!uy&8!WmMJg}kY1O1PQzrJ zOI2?x8?wiQQ}=d=80qU7^blfsB@TR0ZqBK^XBni+6A=HO<$IrAkYD~pwOv6BX5K5_ z+Hj=8)>OeZWK{C^O8OjFUVw&=p0Ja|f_bUl%kWvs3OQfo1=zg=>T0Tx{WwkznOvaf z?Vv%=SLeIqr!E(S;QT_@I+eByKmg6!-nGKOyEi%lC>rl!j;ej$!9|CEHV#m4+i2UO z@Xm%oj`RrKNBQg#<8o3ED?$mdUxC)l&)>@65m*h$SKz5CRVxvDq zhHT7Og|X~g_Kd))=u7}?8LT>4%21(=9`GQsVIX85$bSKS{&#OF0sm))TW7Q?@bxYp zDss=JnHl*UYzK^}2%-R=TLTRbrQa3TTSPm1MP$0H6Np>s!njX#rK{+siv3sbdV`;h zJ=p4}N<39`E)dfKEYq?S)01v%R@`FJ=!(jnj)d+tu}&o4@ZEJ^0|8HDx#X18#(c~RcuXBnAy{)kRCK}6%0U#WDbVvrc3(9^i*xu?~m*2yls z$$jHuI@p^xjWf??yISJN0<(;*8S!5cgYWxskA$`E_oQ8|dd!}}=IEeZTz@5~lB>&V zXQ{Qg;#MQ?B?TC@87^(Pe-$I0Re=q0jJMts#nXcl85Eg`xvO|@RA)Mix--29?kg=9 zv{QgNGTa3`=zJ$F7{PfY&5B{jo*qR&@#NbKZvtGAD-b1##Z{352d6jk*~)_;&l@8( zN5d-GO<1jnQ-5xrmYh~XfmL*Mt|4IfVRa_(p(xVD4`cHjL<2Vr9FTo8YxKUf2fCvA z!j93P;FQ;$tD#kfnkOzVz?hR%XM?3yvuKXJcC*xZFB-Ww{Dc{PaT|d!V1>I(YIEr8j#aHE-+t$IicB3qD`&2N|6$Q> zR_AOac`b%ecYxSPVPdJ#B+@pc;!Mk>Ar>}p?W=a5@9*oMZHEzave?OTu?HBUbRfh! zjkgU(28!qq&bpzRxyCV(+ugTd;D23$0JTCTvQiREr_0hTyil?SSJMG)&(m0gD2!K| zz3yTSUF`~@yP>OJ1rXuwO&b1dm|+qk!Xb^m@H_V}9#?+BBMkQ(iuA9WCa*nyaGkEB zK^u<7ztx>QO?D?v&e{)s0egb@WmL>^(V)hvb}N0V1N>YoN_D{9H;Pq>(Mr_+%T&O4 zu@;JJ9%C5Qi?F3eoPklG^596Bt$>va)U`BK6jKs-X&r!&$Vj2?sR#!-daz`n@}_P{ z|0aM7{?whC7y9I$zIfb;cBEpyTfC=AtI@`@&M{GIT0q^?`0Q|3n$)%OOdqd-K8 zct>3l?JfDxU^!kO388LCmn|Ttq8vQk$xa4$*Y?*ZtzOYZCztoF>$X#CG z&DyH?eS(DUWSVXfjFILJdIvGq#j=qq4G6jVMIZIrV%n7JiD+st>Sl+*V+?eOfl|Bm zZU`FDU-m|BdZxK{N1>VZY+OYpX#W>4dP!w2==47ZWUL?E8^#2yC7Y`?FIgfgul<@? zEHw+f3far@79nPD0nB%gVqY>{gg}r(?K#^6mB)IianH)(6UVT0mGQM0F=~sx`xTdC zd*}&h+q)z6r|QeTlPIc))_|<%Dgaufv1{i!$<+Ce9+HA=mlp9(mqYZwCHFnKPRG-p z8@Ti%Mu?Hw#P5JO8mU{Oxip#gVf7 zNINKyVRiNyM}6HIF5aePn4=Kt`+PtnHd%_Z?vvMQa{$I_ZnP@%0$n2I07Sl@i6myj zXAi}^M_Pvx8A1rhk=2@dP#xp&8)DgFjs##l-rfYvy2yhO((}YnV!8@Xf+yL_CrzKl z6Z^YLVRN&^Ote3159OVcC@}x}qjU4BB?LJL+9O{QDz$hic_RRT+8|14 zEmE<53{7P$^SFePYJDe%G6ZHHKZVrI0)AJf!GUCX>*A*NcI<8iz@MK3iR0qsx(=Ww zKl>efSSQ6yp!+rb%Aj#`S6jTxfo>6b?rM7A>pqm_db3B4F4&@RpYm>tvAhC!sT5tis;|761ldVI z^lhzQ9Tz*@#HNvZ1xCvCAZp~x*jX(5DUa8$JxaioIw@Y_!BC+>zZDQ72i8pf1#X|_ z@2?G}EHITAKu1+cL+m|5nyWSz*kX!C(8yCW2O_%f%KMb>#@yjjuEm-rt#ZVpyPa;h zKO7S(2deXc$}se8Y|3il%cX!tRdTK>ci6XwDFB6GZ2Wq9=-_vV@WLu!N1#;wxHi4H z<81c1YY5o~w6u_Fq0(-|)Qe;lQ|1X5g5z9$5n493u4CO2z6>={1>S5}@A=*o!lk!$ z)r~tq%5jd|KTb4StDc@TyqxJtA?2h*WjBTI|f&_AhU5e(lVBX-$8vhHI5z?P^|TpLSq`~iM_dnEitIP zMe+}r^i&6f3(Q;GUn+i9wj!SM5Pc^gu+DB;spG)W!g&xJDUGaxP(m$$5x32J6pMZj zHFNnJTeuu16Q)y8J06L74$$-ADrT&GZMIj+DUoxHEjdDkVwixkgl1r4?OJQw6PhHE zpXpmG$@93vPr)thc96w@Xsa+Qc_K4*sWUl;wKJzUNh_P+)X!_jvzRpZ9H2IX@CE4X zbF{1nZvG>gkM=zn;^P`AKVSi*Z`%L_p!0M{N;W%U?&&ld0JVVt(GiRj?<+tc`5oIH zH)LkXGmBp;e~bry>E3Q?<$UmAJYxhEKTH^nUnweD`xr}TFp^J%73A28LvPtov@#P7 zaZH*gwU7jkLQsWbVt=}Z)XWnPdL-85R>?3AsPj4MAE2zY@ZR^S6A}TnI@mWDkum`o zKhEjNkzNHS9{&rr=|#2Y$bfvH@?M`8bU*`G40sF9yKq`a>ENirl|tNY+G8A8cy!9R zi~Qua$ttX{a-g4XU!yo6a>qVc!*{w~*rhuvew%3=RmB++(ra``DI|IIF})f36x-;4MOv4^@M2j@o+BG< z7kohjy|ll?O0?fpP7(eO`J=jETR=684@EOZXoj-k1%@+v{$41W>^Kdrw{MKWCIqvY zig!)&(Q6(hMbpPR%!IOIhsseK&{xrfZJ$!ySc|Qy zye3FVxQLp&^noH5V+4r{Ifg+2eQSPaOF3T1-A;mn-Ez|gG zlD_vD0`u_!F}>Q`y_a1J1-w_|s|U?^mVxuNascls->uXl zm0BfK5w`%3G+oxrF;}rsBA3t~*+a^XJ*2vN;I6O2=T^>MSo=a$!~obspmDjgeS>x6 znn)#x3k+b_Y4>f~Y6uC7FVu<<70yi7E5gZ7TeopHRvUKYtJ=eBQ6J7;lSFdr1%0!C?6rr z$;p-+A>VsT%I&#nO21oA3*JR|3LCV3=$a5Dz|Go4T=iuR9=-J@G%2!RujIhq$otU2 ziCc^P{YJMFg_y{VGTPIGHaFZscZmXTy8UcY8XOyqM_#$y2qBvi)E56FJ|QtkVt&VG za7_M2Ul#9tFF}wo8*NlAYd~;-vCRLuK#!}Q7d52b-8kC%$xGc>RhpUY2Q-5c_0n4{8lh*}fgZ+~aD{9G9yLn=COAppQ zUBO6uk_V5g>U4Y_n~5A}Y*+#_9N9dO(_~V|{^h-3w>6Iu4V!;!o@hS>g(ZJ|wYHwMZ_+T}6GA5qzKXLHt)5SEIX5)} zg+25y2Et`#dnw#6wOV}Zqyks_^#@k68jxYg=WVY)gayz{_-CI38hsV_(AQhm+5uPh zb)4FDgqlSzP$5<=j0>q_k{lg!%EMQX2t)N0i0*XNSa{=aY&}pbe_EJjN3dFHse}p- zgN0qY!%2NE6?(Uqe1f4}+QXWSZhlk|*-Uxo!?-`#vN}UZr+*uRM_nykXLx&F3JLTK z@+SlcwML3;Jv5pBls=Mb>?AZ5k|LVmRxyr3&GYVv^w3$JILIOP6zvWp!|qjudtj6_ z^XdjXS<7a?sZRra*rfydC-{>nn92sx_@3mc=)mRSm4k+G)fQld#T=@yOp*R=VkOMv^v4%7Qe*=Ke2}% zEN%oVUj$Yx97~=FO;og;8 zu#C)BK*qMJ&+m*DzQu9W**`>z9mpPA>;tXICVyI|bbz6<$RAFK&_*nicHXA%RtFc{ z;cy4przpao)N%*LSINOJV)+z?2XyxtHlyShBEGt;4J!#uR{D|TsB*GPk^@jR;Pa+0 z(l#in+bu%TlrbfY#5d4@y11i%;lFl3UOR#FclSWwRdA$2096Nya`q~nU=WMM1@<;G z5m)iv|9<8w7OO6>4k!q_v7u`9P(N+W)+mz86RPRzeXJepm?3H_^o3y3^BJ9c zv%O%{(rt~!zdb}vYfWQG3r$>GLzOT`H|6ziShz#wtK)o}r&k|SKa##qmrG(O&lfeN zgeyQCIR&;E)Q6lSbP0_(6X5;N6Tv)AY`j*oh7|X?8lJ)RuHGawkLU!Aqvfu0>sR}h z>yd9x6fUhCjRG7K2<|1Ev_sISe(QWo^IS8T&4H3$9T99PVtmVJz!0YiB3;UC9w(*f zbnA|RvN84_7_mAw20p}d922rbp)&$iq4?rrHd8?N!`)EZ+qM_I58AFS=5PaR%lRXs zQDokm6stwJ7TQ$42o|x{5l9 zC$GI(teL$ac=C;!nQao8j+TCmWltQC<)dn<6BpW!JPvmjcH#i$#n9L|&#@aUQV|(l z9)Eb2RCEvg_C6MUw9Rx?hk95LMSx%*79rrk4)m-veysLtt6tz?wKH+zD$f| z>D~K8cqnu%m5b@B5igbrcA#Nv9f&P~g3zR3Q9IQsMfBllk#WL8nW{mxP0@KNo_8oM z>2h}QkS-23Rn?rK)iTrgtp2)S(L)4j>uNPw4rtmBrD{tI8K|-vvPbY3*^s6?X4LwY zAiUITKi^~9JykCwbfv6Tv~mTfosC5WgsFN(%#CpBu^E^YykA^d40+xL_b^hxhQ0(S zn3T9TQ)m_gtjSJJkooA*Nro~9fg)1B@*tguJCfVJTJ@#`oQuHUO~)GAXytpzee^Lj z?;i{~^D{i8p}J|#V{q$QT7}X#yTk{MH!TcFvcRYW%CT74qU&5Ct7&a$9a!fyFaiN3 z>0otKVf{N1RK@$!(?SZ`n7kpcsq>e=PdkxB-x!S>ocFw|w9}o91tB)(MwF81!+pJR ztt%-2wMsf9O2Pm$7HJod_6%qW>jOVE<}P4-Es({lY^(D2aD544EU`yWQQ+2PEko-2xCw2*fjXm>EC0oNaohwt5hKreaY zn>D?Kqcg4>IA>zXX*fEor;-JIbq>$NRC$V>2UkWxzo={9JpYs*G58Awu&o1bycT zgYJJU_V2-N6XksTw42qtv3B4|VK@hp^?vj4%gP4R(WXl>ZUVA?)~JEbnT$W!lL&I- zl&M(&q6}CfO$e&dLcBw4=~phLQrv)OMGWj&Y;^1EH2hARd?&t_XdZnZHUwKsymP0C zg0buO>E##`T_w_HT5DILj%~w;veyQ`rXH9t_)2m4u;(WMuZXOAk8=ywouNqFi)SX2 zepaJ#hKa?OdAeiRSZ{67{Hys^dY42n(xYL|i9_I|e6_QH@1NG7v-dA)3Ag>*z{KBp zg}T6V?^Kh4Ss~slrf1sFqXu>GIFU$AJ?VHZNW_(<`EfjwOjnM0peo7K^u`7nE|Wz6 zW<7<@uV1R!-ih|J@|1$?N6^K10E{KlRN`&K5^9ZeR(&KmIoV5e zd%#2n|D>f-Nlf_K9<9~rwql}>rpwruU51!aLI(G``eaju*_N|Qqe$=R*AM9{Gf+wD)C0w@elc-OHIoC| znLqhHN^pUihNdQ|eUKvh9NSw8&U)7!q)nub%6HrsQGZav&z>5}+s2e!Ehgk|*8o<5 zackT;YZOal_lCZ{Fcq(;>>C5*t4{>?+Z|U}7P`M`on_ql$F>f`ay%!(AU3#kT~F&5 zgO$JX>hn^oRf8Tq<8a#A1jWu1yfZpjQ5Rxz34bmLsI$`f$@T#g^CpCvQ$^6E{}p^R zFG6%Y@@H@C()oISlO4Zh(B`t^eLoZ?K)#7VqDxYN^&C}f)&fZ%s6vm=KL;pmFVY63 zmz>My#BdyDtYlxhU@!K0KfS4>HCtLV&R(dm$LRiYl94y>APNT)@`u9P+1D09-j@XF zJRFFKVhAHGJPq0(JG8pH|NWEV-`OCe0F)08;s7j$E<6EJC8tS&@1`Alpo~`VLnLcS zo+SSE^J1^}?v3&d&4hbFJEm3_?Gq7Kf<`-MDNg=7Y=E8!RiyF&DcI zSD_;k<|_Inet(k8^%+pm`Um>{O*OP0S@*Qdw zI4P!ZW?3O11#AFuBfUG0lAV}~l9k~@>Z%EUSByghjC!lmv=XZ`&rI&Z4wV&FKGtX2 z_%|U*36S@cI7al7GT_t~*qQQY!VNr=8-QpfD+%^*J6cW95odZ4Yp#7pvSMcFDL^f_ zQphk($Zq>azHEh-q3)(bo_Z_Jc}MbA6ecf08oxqXpOJAm(toaVzZNtom4*#JE7~uP zpm#hAiWEiCw%XF=w9&nue@ua+S%1`(+bz=~LcThobW1El4F+M-eY0)L6G-4CrRhGs zG>gMbNiJ@wuN%}cd2r$OtY%QN{&{F@11&^uP{Y9sJG~m~Bj!tf(8zu+U;bn*xbs~D z3KKWTSD=zC(-01wlW`!rh;I&xoF^@h6!2Hiq}9)1?m*V$0*f%XYbp>Kg)?^5Nr-AG z0fo&7SSi5R5V=0EyhDCSyfLY9CKyMX1GBX8<8Hc<_wU8roAWx~Ek#||W)mcf}+#i&1O%G##P=<~^8ktzH_Ia^i$x7o%cjk1AaTTI%K9syG z2^cklq~N#8sF$YBk;&MxwSr$KjKgY_rkR@MQ}eS5O8{7@CPC@@UMMe2N^J(k7+9n= zi8i? zJ_;PSKwJ+_e%X8vswmJ>Ee)ebJQ2kS81WFjJnWtsMh)@knknN`m>GI6zS&nL;bQ}L z+&!w}|9jlXqu`A-60waWjXbf`_U0D_$)bk` zl!(rsrAl0>vvKj$?PkM95M^Axo@v)ioND%8#_B(ui%B`xgmBtvl&rQB(10(D((aS? zjv|7+#!!EoxW3lvpCJq?*kTwe0-YSACcwpD{(%>Ra4PISszb4KzGkg_Z^1{~;lb#3 zF1E26V^V3(n3`T?p?Qp>UEw5gZ!&pwn1*m@quQ%_yfdLh^AOv3$?dM}lQWOypU;L8 zjkEa}a0N>@OW;7YaD-$M=T-<(s3aY8G`uPruo`r&Xb8;N_b5Np(VgD2{Y;?)SZ<5} znU!Xbu6B=?0)~sfa^Qqlh()^GP-OgUV~&~U);`pFo4qVdZ>$=?~7Rlg?^Go1jO9w*gPQGf6J!k#Jv0*^C* zA0^*#sXge^u#hKtIvch)AmsXKd3;~r@9kr&oxw3xyGa` zdJ2p7AqAt4&wCD19+d^YLs|D^#uniaP{r?bc9%$d0Q6KYE5Lx{CId&w&a&2p2!8QD zWMlExyS*Ty&WjGWO?03bZLPUso8Fb)$IH#Bh)1jwSeA~HUIeR>oZO-{{b(ZqVrh85 zbv(OH2IRH&^2a{KnH%{Y9#J~A005x8b;mIY6#=xpqMn9RkI%-PMi6?R*4V+(1scvpfmQ;Wsl{Prq}Kfwms#Au7*-+v%%9Iqg);px=Bd|>mprhIZ@Q9-$Aqj zKBUPnSwHxr0VA$yoVxn={ZxsMl=kxAbph)BCb})S;8p^zN{t5pOBA1Vf4>y!+a>KMn#m_fSBhA` zI302v7b0Sf@O5mT$S%9Df+JE_z-Bz_kk7!%3guDdBc#ATyW&Vdq8;pWq{kYt?{^V5 z5G0_xv_UyLIKMzxgnlDU8^4NDZV8uxU{2K`g|bzLg~X~&&hwg4Ab}YfsZ*o76C^;4 zu6*FF+B1tvYz1TBVPy~3`Zr)`%dJplbg1OGp5w7&t)kMo_OeWZ`bf!!c( z?TNtEp-9J{y1((AK$*i8ejiev*Z6-YIcT}SQw{u3FA_9y^(4eeaV&4~N zP=gy{HPEucPv-7h6#+o&Ung2_B?{hSrqr5Y18H z-(?!?vdO-8*h}En>-|5>4?KwJS^qiAjGUdTAjL9++~yYOMO-PcUFJKbhDSRkNKCK+ zr*bXXG)gHq2_PGAsLmvxkBCKB4`vaZYFL1Cp^vX2lF4?S{vrT!dih>`MbL=ZY z&wMF(v3p!Ndhtynf>noZ`;(rh>JCrp=Q-~yu4@LcZrQaRqEsRby}Dm>mg|{NNj*@M z7YwX2*EXZcXLU)*WW?bYEK+4z=0UjS+t-$?7*{EIT<)qk%E>OlkhyR%#JN(Ib^gBx zL1xB=D7(st`u4gEIAVvC#R5N$TUOr1x05}OR}uJM#U>CbWp|5Aqy?6lB(wsXsfqJr zXz2OYdUf>P3j@-vuXj4=XNZuVP}3}w*}5Jfr!!%di!Z`DpqK#lP#6-_WX%cv zS&wy7d!1QrQtx_Z_&i74Se$SU##e@T2p4o5$M6>QXtOmwQ`_k!xVPbekH4a1`jjS5 z|Jf*y3Cw#S@3wbgmELYq^^$F5;WdwLnE-YLMvQ(G1?isRNt9_+F0Io^gq*)s$p(g| zq4oPymyMfMtCh@4`g>da<7dZMB@O$-*3%>FMUOebt8LSBeE33N34sqe76sN3te_9F z2T&M>n1^$HQ32Di09*ve$5}=>E=EpWuIR*|=(x$H8W9Cc*7Tt9}h5gJ%>huJt z?qvF`i$E+=yT#oy@efTg4;N%7@OEDw9!hQo1p~NzvDR;FKoPsD4xPETkl*ay*H=U9 z+7U@9`~aSF&61(XZr$)7s4J6>pKYP(D0oG}>qFT!)RRj@E}^AJiUMd~kxa}LLvU3< zZ2N6!OC7>_VlABn`ltJ}0JF|fcJ@m~-GHhfZlqqaT7+v<9DunnDI7HA4#1_EdG{8N z1|#MjWEf~Mu8dI<=!5qtt#+zOum{pO1Xg}jRAR>Mx9_N*J$@PepX`zH_2T}R&|nPg zw!{tOtg+0q1+9KyLIH+nl38YW-nO42$L7i9~-<#&`b3Cd8wQk)JJ z_DW>#iN_PsGN#=56HFyf_(2QmJ#FSh_(^DqfNOs|w?bco;@1scO6?;2UFTTeigR!$ z=KvjAItGHhL5-0&Q!z<(lM-9Mz5}sj+&osdJ{|8pnl_U!)|g_hKn$V@GdTE@(XAv?fVC?)jXfB?ljAkGvEiD&qru8mDE1c zWODFuC=zMIM;HtW?8u!*vtOj-4aGTbXH{-rzoWj5{QlO!p$zbnQfh>uXy6dII+d}Z z_%u-u1P5zpXR;$3%~R4rqI!mWCOt_5!Kd}F7VQ1RS4>|#5kDPv==p59$tjBt{s&qy zfoWfh5jgxtpAe9N0P>`Uz=)F+P7YUv@M31Uh1$1M1ov;)NS;D!>Lv-Mc%Qtk9h69) z=RH@+;~n}4qfn&aED=C)iG+3TTYe!c(*!vyPd+C!6`Z!XpB22D{4QNf={yRA15544n3PdZfV}XC)t8w;OBP{5dj;qfEz>15zV}cNgy=0z4 z&H6K>++#o*2->r~K9@ZZ)_@fW1BkxON@E5zn%I)G{!(zHr?eUhHp)oay=F(2h>k6B1= z=dVE9Cm@S|1SS>TtVgj(XdTSs+Hmqm?HE4C?!4g;Eo6f_gH$ z!IC-4roA~-QCZIk!`g!M-=z5M7Y=<#TrCIwaEtylKSvvP)lM2G6B~U@JZi;Hp@bJj zU@P)8LpWi6Cl`k}HySFxEbd@lZMmbvFMH04Va<;zjTAD$RLcO-(3D6ShC&_4{)Whc zuDg}Pjj%H~TqaPS?j~n=^+UzIG&%-cCoW>K21&4gl@NN<5riNcYeZ~<0h7qancz}! z_jaU`=zt@aK^9S(slwDF%X^xZjN7JRl^s@P*Jc2C1H%a&ghpE3VSzaSyi&=%o3?SfC>dGL}yxa{?m#5I9QJQ2C_SRymyC9TT1s_fGfXDUrB z^rV|u<95lqGbJiB#f7|ORvnpt<2cKPla-eispU@U%P7fA1MVrog?|Oe4lc&eor*kU z&ZC>B)d|5a`FB!m%^arcy0hgQTz_BIo-IY3wJt8YD#@hNmn7Sw_k2-16j?YBT|QbH zY0)4Im>R8C)pJ*pOuAm9SzTQqltCg_49h7ile#*ouC$^>K5lToiRj3SlxYh&p&)M1 z=L@TMZ#$N2a8lGvUC{-Gf{b1B*TFFimevWZWLUa}^-8#}6O^Qe{%m_&2Gv_zLXsAU zUH)p@=WOX&bdIbz5d^zFQmPrRAKdvNUePgIy8}|6 zHv7d~&~op}_;QJM#H^9vPD+~R7trEC<1xe*M+`_5o_;!AH+caXdolrG!LWx+CCWpX zl#!M+7}3#LeTlcQi>Bf?7euQxk}2;XF*&}P9xXzzK2t5YdZyk8L2-iaDC4w$-GVfx zEHllaw4&D|j^#_6!Ee&8(%O(jNb$;0Od_S=Y@rfmMCqV*TjTJ~T+uID8yxt#Y+&(X zxzvJ2ZE+3FHkV^p`4ntw7cG3z;F=rbsnvtQI={4eszE)xsX>wo@E=G1R%j^m#TCLn zR8?7CTF>ms3b`fbO0)tecL+)b*nOg5$@5kCCA#@j_6kwEQR7Fhm)P8>t&s6oD5??U`03&Y-|92blH2F`y(0)B`+u+K zQWeK-GnP^!rXi`gjx!ol!HS^pU<;}O{gytJUY_4Zf%KSp0*VeZFLN4b!Fo zoD;)?XKm1yMWerqOR8a99=H}(LY?t1Jq1|c^Z6cEE0xvY)zGOf>ZWmnta8W_wb!dS z&Q{NwK{X8f;&`9*Q^#Sl^?&ysE&^1xx$Z{6niDW4SV4T!N)P1i+5_D2%Ue6)qv{cc zm?pUN76kDBdVW&~$>1D>(1<-`?#e*Xsw(N?P7vWBW=rmIr&rEf&CoN1#NAtf)#ijgOg%ixSgR+5uc9VG8b37sDP-V>-alZ zy{1*=h=*^TYmosN!d0&>zq;sUZO-Wje*oIXZ23nZ^}3f&uaC|AG7pi|1f+C|z`}c% zspL#C5_wi_;Epg}b2^jDJ+**M74<>g+%lCpMS?0KBuro@?YEU@uy3h5cB926^Ec(z z$t{(p-iPRkA?2)8NsHHcLh?4a@YM<``YYT%w3`zzWtG3@l3Y;LmUBF`B87QjV$S&A z%@<;BttWIlvQW9A-F7Kz6g7cNpp?{RtDNHWN+@Me-o;xcxoGoeg}y}%4{0p#;D0DF z0lXDa^EVt&mScIEXRXquqa3B1S;lZ>3i5lJM7Bl3q@hX{eGuaXxd_I?SMMW?P=Lx)>PiQ&%s!E>|w|KUC3 z8f(^JBH*%JEGc_YGrXx}G)1-b>Z0_Gv(C<&`g=QO&L%5ILpgZTo6MYPy@c}y^BCBs zHs*R8+!UReZ?&x>p4NivjFjveq7JM)jN-#T6O*w1-unEHM?qksmmL1F#pDX}5(WY+ zm68ar)RUb%_|drJ*4h`#Q3Wn#A_=fvt+wbLHhOacwO9%Cuh1hRbxU6~g%Un7CI9t# z5j)NW7(#zm>$(OF`Zt5@2MW4O%%j z#mAAC<5m*?YPK`8;~KW77>vngmOC2c{_JL4h-OL4Mf0>U*^YL+U>@Ao`G<69cB0r` zU(Opi5ha7jG^3zq>PD+*cLyduR~S4E)r>@EGIADV^+-w5==|tz)oejA5)UD1#7xLm z5hj`*k_h5UiV&r!DZRfpUR)WGxw~qFA^7}xA{z>6OA2AdJJiR&3Ayg4ESAj-Nu{&M z3o1s<;hG{_ zqhznIdAgGBUtZYtbv#g>uW%9~b)?F9i%PD1JR>AnX_FM3Mc$uBK zb)e~YT&R=rif#f_t#r=FQ8Kp8AB!E>9r=g`@>FFiD&3$stRSR|xP+HyXEmD@XdVoX zE4e1hG)BcQ@Ucb-#OXIsX>Qs|HV^NC3G>st1>~r{6MH(tUaXO`y%%B+o6d$E2ynRn zw3pY7bmxhzwbWx4OWToBbs*)#*IqJ%6nb9@nbn!P?}n2FeK?%;8%=kwy+}+#gFtwG z4}`FE!d`SDmJ)Q-^H6)^g)LS|3`Bh_hNv9thkFu2Iy&1JrV;i!!R{&3FsK-CU#MSL zowKa<{+x{!ahxD}O+s9ke9B_dyD< zIFL9guCoR%b6!z7iI!Lk{j|UNkFPr)&`-<&l?C-x3pBpz^=A;{<92jINa>rhW*Egz zsCg^L1vn8{AaDtOcQ#c6J1KfWi~yDAK`Ydo0X}C25FK#7y1Uz<=+7+bW`Z8}j?6?n z7;?!SWmf$8(W8+d>bRyLfz}jY79D+i-@dgtx1yX+rd+Me1KP=Uaa{FqmSB2rc~(id zl1F#T$uJ(-OzKoUTH~07^kAf}+x;0PcK}jkAhkzdEq!pYF`qk#ryYk}tAKE<_OO%FAWU;1tdN9&veLZIG? znIfX3d^kU~9r{18pCb@+GmqI95(Z=J5g0!DV(69@lu0Avg`w@_>YVCNgUu957v9Dc-qFs8^APD~xdTa??^o!pnfX-5ln44MNhs;&si(MsCsM64rvJq}l}H&=-UC8z`i z(oZ1wCY7SDR!-HEUWZL{mbeNa*E>~^0#9a7W!=>CYnWlzY4_}%982B^uLrX+1APslG}On ztk;C!2Nd6I4bt72LM(R>2AUZA+%Hexe5uluJy+96BbVko55FK|c2{tUw(bbhLem%0 z2*yLz+lBM%NsL%$hKnLz7MP>{UDfaQE@vE~#|s<}K_uv=Mf6KxPzt$WwAEV^7$u2a z47XIi*uCQhhxZ>eM|od1qt%=n=H<=F_u}2c=0ymg%!5Z-ytKB^dn~Z7;T^6(Gw~np zCOO_6ajtM59;l0^5=ghwp>ULv;>&Ei5zW*`+H{KX?CxqOMjx0wn|bHUoX|(}hz( z$CUY|{uzv;#}-DZ4={$=`Fm%oeewFGlNDb4-$Y`VUyi!)SmT5kf`wD3Y&0zfxKBV4 zCKTpP>^sdL7R7R~F)VNkgtDT4Rdv{`?OX}xB91__4=(@>wd?8;x(E-f^i$>75rciL z1+eE^CBGUnIX+E8^oRg^5Z$vJ0>>Fr&I%+Jt6e>lACdH&^+^Mrb8ZsKyoWlA*Xn#{ z%&`h3gVkOj`y3$kklLxZ_y*Ga$uOCqYOk)OeC{dFjMBZKe?pB^N=Wr#Z{#Q_;pnpO zBSD~?74fMhR{f3o^}ati!0z%=6THY1f1L6)n}WRFJK;1!zt_ePP$wnvvc--&8F0Qn zmD1nn$cFTF7$vnpDd&$y#!JYdsE$ip`2j#!-TMNIgP29XX;bsYpWF{kb;SI%!&u%l zg%N4#8duOLvaZAU8_WOs7JrU&O13LayanEj9Nr?*pc!sPY*<%r|Aq9=rp@%YoFMO@ z-Olrw3}sB=3Rxt2k)~@C%QLSx+{){_cb9hf zoV1&`n>A$%FvU=#$yZrSCJ2m`==grNtm~{@RXsEt7SzrGB50x3HndZIC&*2QP37lp zRu-bE{wSB_A*Wg=czBoz)+VWu@M(H#N=_o*k%Ki0Gov~8olh}}D zsm-}^qdjy6*5wWxYd+pL27HP$iD&1L?nw!V?2claXfGHKx^QEt^x99U7oF2_t~gJP zeU#)j9_vJr)Q!b}(fIt=r|mnh0UChr9^8513?5}3+UCxr1At80$8e0zE5;R*&B`79Kvh(f`>)Jl~GI9D+uO$w!wx0{N^5ahkig^&aa$mWbJUIp54ic65q$MU) zbgU0dr1;M?Ec0d=lj-4hL*0m!7To-s;EZK}hcyEnjRH%yvB#Zq)5&r#E88p5?iU{YdiIF2JD$d@Cw~z3b6+aHqP z-0e>*I;HT}z-yj#-#{R3xvf5;FEGuSD)mWS`rZx3#nDqg%26W8iPejuBc{EOJwo_X zA6SN|R@VEkpwCa`twiI#dDG>)Wdu&9@DOB>oPHYpTk#eJc3K$W^5P9Y*l{fb%1SUV z#;E6KMiI4@8(Mb8NARalXI&@bAC|6WIi3acT0 zcl@@eFv&FQtbxE@bm4Jcote1S^i9mp7%sooTim#$fE$$x;9uigChu`t)?gu4(e&gn zB~vKGCFC0SdE0Wd7D@;q#TXWhsim031I?J-$)@7xy^6z|8TO%!=^eBkz^x+{wq=x6d-E;gq+kghM#oO{q0Xae3y;Ny|6W?&nkM=q1xfB(!`KP}{dJ#Z zzfqs#dzI%s=AljAQH{X7jSjroxar8~t5l#>p80Mvnunm?BI>{36-DGSeI0O;oSPW} znG%+Z`!yJ)BO@woB`R=;LejBMnOZ3bA%-Q&}41}{=21TMAw{m>LSH3QMTc| z?-}m_&nqMy7qGgFQ#b8#T05K}0Hm;{8^4VjxOiT?kcnR#P%r<^NthKc!AdqQ-3x~V zdX4cS;aNCdV@EiC*(z>=guf>zR=G|kUVCo`=P#7Xl)R(25VoSqXv&U$%S^qK(Yx5x5$@Nckw zkgRc5GLj}Bpb;bq1q2le%Sme9+?c~83mWu}W@i={>ynmRS~xn#6@|Ga19i6L54O~0 zWv++Mmi8EGXRo7=A*rL}g;)4uI4t`>(EMbO^Bq^;nmxIG7x<6 zi}M^h0ZukQL0KyR^$eKFXXgEq9GH66Kf=eq z-Ae<>Q)Ho7wsBDA``lbpd=81}N)PB3xTrYIC+b}Au92-wsiOhRcU5)KJnT(IrDlSp zBAvveR)KnY915^C-cBiKvqYH#Yv*43aa69T_AvFv-lU8DOHyovFE5OMTysPeK{@Br zVQx8{*er5aFY5wE5hn0YaS)jk2cHz85RabQ*EVQ`PPW$M{!M%G`sIFRma(mWVo|YwIjUI) z9QnLjfqRDCtLQM@TJvIcsouexzOKU4+N7}*^Ue9a0Yq*`l{#Q`-% zMWECJeIuL;eXFY#k(qWbYN*`oUp=VaWivCO0UYp6J7&mPts+Ga(KHw?FwT>|m~IfO zxT_x%Z>K7@D-w2?a)K(|LP?Dhc5pplti~YLH=cz-mB;9t9t(@B7B6ndYe{|1xRKl_ zdvnXikud}#;j^wqZqrCs2|daP+CP02WQfLW4rX1$k9N$LZ^x8Jve%BZn~diNNM($= z-GXvGu9t;le%S}C(M^qtQen-t`$Uv3Ghv*F{)o;c7d|vK;-WmPsKD} zd<&NBAdIe#2O_~wuXjf|7ZyL#A1Z8=yF<*8bG7RtFm|QtCzvsi^w%y$G{$6FIt4jz zjrMTq0P-$=<6l(vyF zf#?u;YP>m-RH-z)INEg}%t^MqW1&*@YLAv2)gVcsWPVL0hPxHqn2fgEM*gy5Tg8jX zq3dauYU<6GGwJcl$)00f^Zh7pn3mS%_JOPc;(@G#u)>>d4@u$ero_q98g3{i1uFG7 z>c!r-$*Msqf$Z11H#z-!5c1x_Bsvu4#T?6HirZbz`tKFlFWN5mwh<;)uU?Uj*vXuZ z-6!a&dh6eEb|`RjXGj9<>D`(M=bSH*z_7yx7;L)I9uo=?nQ!VT+q%n+CHW<^1=mLI zqgT~@Vr_BTLgv->a9L(T;dc+p@VMYA@FeH3?BafoyT5g~Xv0uk@#%)r!v~?8bP=zZ z^Lj$*!f{|^XIYurw<2vT(v}nFQ;4p4D0xZ|Ex5ZuVVq$F)}wg@U;t~{v)ANN!##<* z7wJ$5Sz0GYRze3~B?n335D*pZTl{>oEg`if(i`{&rmumyWDX5BZanc(>)}2LB&saf(;k!e$ zAo}IWsSF?HN&fah%9N)2MHRRy`~5eSx%y93iBV7X3Cp$EsWPrN>Lbt@CjSudCuq%c zsh$2M@4;7~f3Os(P7_q7|KzBM&G+UTg^w>$SNPCHq5XM;L&x=ls~Pn?Jg@F*29E)s z=C`m2K=)Z5%%IW#TcM8pEzAcL0IK}$yycl^v&o*OKetYMTIt%QY-!5%>)rfhm<2i@ zK^3~$l}+e@t0$0?1WK0{n7_E*3| zghsmlYc)K_-)Lx9knC$|y$^u)=%DcPAfR)|8$wIMg$~m7VF9=2A4df~EINGQxob@& zl}aH?jdqP98C#?9K{@7ZX*v)J&8H*fVwduWPb@Ukn& zp_o^iaGgmod;a}}+Q{qXAnMoVy=c@^3p3N;4LoO0zlvC8;7l+hDUp~$9Vv}gL3_dy zc@PJ>F+bCRtbcuq6x2*R<*Y^~iscgYBAe~? z_ARK~j(>#FKr5IoJUPE~=wy#3uRp31=m13whM3pVrDzey&WLr=(cqUx3uROmckQXL zy@K0v(+r*7i0yd2H*TJj7w(qjoY7@<+pdl@4Id%3T07;E2_gxhA&>Rk2}%W4ZDRE>H8t!g++*#$}O|} z5lUaLwCpqK%;>g=3pk|Ot*#Ln^?L@8U7y_~Spg}_i<~4scB%AwF=}>6SwetS# zM(daI4x~V$AtgelEGl-C7W;Pn6a%;{XEABKIbASL_!F3M^mFo@#CudbZnVLeGsww( zYGik4|UsXntl#tz5PWcTsQq|Il{ zVZ{IM1R9b&)=QTbUY^Z?omEVFgP#y`Jc9-k$wHQKFV62+A76+5I*_p@w_u3VyrixI z;t9@QxM}AmtA9av6~yVLqM=AapYzK?ENKts9U$RbB}<|}yD%^vbU@`9KKN{o+;AKL zgnbEw!t?Z`W}W)Zcpcy#7-dJ8qB+F20igesBhDC zWD1b{%3?Gk0LpoD4eE>9Og}@xfIeyVD}!%ARO#4~zWRV^7P^)emXXG?XOb>t)~+q!hjEZV)c(=1KAXR7Ncc#AQ_BmaPzuL`6Q;-xIqK!PN!@*!@?^DW zyFyf{1$$&zR`9v9y9laHZSB;i6?rmp_H_mme=~9c?ZMxNBN73?=x`+XYR?Pzj zek$7u8=Xm5=G=jP6AQ8fyZu|G_i}x+0_sP|st!hqXvQJ&tQu7f8A|jz6SM%%{Aw8p zGMRr5Mbc2WvEirz!|Xbcb~qZJf)^8)JtGR%DvWr??{|)@%VEc{YbwvFWBNLZybVTR z&|Gfq5R*qXT2?Ut=PcAgelW<0sRDZpvl29OqHf)_jH?P`RhBao2{+u+h$w53l&Fn4 z|1Z%420$u1HTY6lGP*+9MC@Zq(7r_3(Tj$6C!t_jD$_`(Gw(?3==HYqUEbubx&GFz zq%nW63K<5We0jOLYt%w>xn}>n&9z@J($jz(-pz8s05iy{e>sbHfH235w{$o&oAc|1 zu%So&6TYb&$-Ytcc;uqW!DoNvoo`Mrj_A`OPXVd%bM%h6?$%p$yK!bhLxP=aihy=< ze!+l_XB#({7z1gutc2r4BW%Slr`QyUD5a*KsMZHmSZ}&Eu=2p`9bM{#{M7XBDPa8)9wd`z|>}1KI63A}gP%oBLi~QRH8Z~9( zoz+a3XM1PiE+UU4n)97Q3y6}uP=uD}9WQIE6Y`)i{TQhu_OW22i|rPDAz=S+O;dUa z^Pa8ICk=LOmhzpK?jPpAH5KVMw!yRS(|trpAyRx4UJxEFTrGRy=aL{L#1?Vv{^LB&) zf#Sk>SxG<7Z!>m}-U+zwW0{}ybg^n1&8T>A_4--u^*IT2-z+5L7A@gOu{?01+H+Yf zN8RJd2Vx}`xn`rO>p+8>w5YW}YfHmqn8Bq8S>o55B&?Y~!87Ue2b!=K$btuxL)@$* zb{DQ)D{+CB+#`&zYp>T_^j{}q;7ao_2303}296*9#xT%9_!F1}Eo-zD=)_BO;9d%0 zX4gd*@f3*sI^YC>TJ)*8Qis}~VC(8y!>Jw9(E7LX!SoaqHxDF+uRZ((mkMfxmEu*b?R;hTl80(jCW8DfeHXt-p}nuZvf&fu?dBv=e@B=mE+BM>U<-BnOK>(V-;y!D z-mEwrC&+RTi2^gQ<)uhlaI@I<{d3p!Q0m{h(EJuDvhleRx0qv1-7h7z zWm-CPsnFP^$6Z>SwnQ&4GmCvURITd%d(27qVezjjM6s6}9 zI^NX#k5h&ze)GPMZFPO;hy|8KnKpK5YWXPCg%S>)>5pL}%3s5tPQjxLxgtX3b5t(tePJOhR@>J@U@Y)&HY=w(2_ zC0R)`VkMhO-6)vV8fQtkugX#ywQ?}QWD%P)U=r7uwd?YVu^haF4WIV)wWqr5Jt$*~ z%Xbg6bqoGfNjXrq|MUxKTOT6{drY~D7*^J@k@-Xu*4?oQOKm_s4>@{Ut__brav`hP ze%)l?(!8-umy$qSgNT>^2)sUhcWY=;9p8Zd2!WI*AtHo((w zV{I7@P;6msJ=#y3nUibxyFiqasja|2@flT4ffOB~|5|ge&x@bwAZ{EgyjVKWs713k zzHUGGHWI8Pk8PkMK!(kpw7hC5Dp24Axn2k*myX$>dd|p8Hez^4aw?I0e5Wj1X`PaA zZsfl;P%9ma%P5l)6t1ECw`7{2Ji%tEn)l^Nsx$id7Pjw8=+tFUO3{fs_L`DBeHdjgOpwuRq`F;m?>M9c}!scRp8B?N}IF- ziwr)h92shPHJ9aKM|`AMw$bK|#v__BXsf#BB&DsfFr);jUpb+2u1^`7P^JK?9UYCY zq!dLc2knPVfY*HBiB#X~8TsOGr%>Ktw+2&s)J?5#Mb3d5h$~EUWzDoI_W}U8Ij%g{ z+&>>xz&t$xqq{N@oV4LZOq|3QvNsw5S?DON1&j~Fu^iMbE$+~2Z7x?Al}R2(X1|N; z6B|qvKuf58h@N~LeV#lUl<>dP#sXj-@1jv*ajbuBMrn~|%iKZ?y(ecYDxx9wvfH%ph>y_2?+lYw*zyOAcIOjX-^NrHd1c0)MKe+r5Ao&owcg@T-?`K(&sI-Ak|D8Y%2RT7s8n;eJ|9~sWb zXF3zVt0CD**&(1~@*pPLPqj_j3RYh&IQa4yfN29A-+MHTthuWaXWl?7h1NGFlchx?nNNeDEU`A=7*J04tEBvLg0|)<2KFFM)2|g zvb_3}$>TM@a?K*F6gO9&ufzd5bMj~FrkHgfi#R&rTzd<-@T9sXfQB*nz`7p86)hRc z{L1W)Al>?h*WAqiN%2OvKw6%HEP(A?WyFq2Lm?YBkl%%4>wi3k5xCkGC=3wryQe-Y z^m_hqsOZqB7$A1ZKzOC0cim5%j3)*B2(TQ94b>i8v2vc%9zI+&+N~^;N(0FFG6b?f zeiVKIxPk(*2lf0 zFCXE#U?PxbrQ|^kF}2s_a0h8|C?~HDLCvOEVid?Z=WEZ`t|Z0+8jr{9h^|wFP*kCZ zQ|rm56l}EFs^an!51A==^=-qGy^cnU(0H>v?`b3k@(@E-0sb|LK-GL#{ zHI(Rr0o?bN?2%#5%q0@qpo$<69&?o}I)TuUaNMilFZZMkb$pX*rIl|~io^Z*$x9)4 z`22f^JW|qG#HXZW>1)!WL+(H@{rD^xoDAr^GPU4OG1Y~)LoVv(q>=<@D9y?pjCEja zc4kD0qJxi8jX~9C^%pG-zTOj9fwmaRyiY)t5;m&@UoxSMmZs6ro0q=l!7V>22#JB1 zPXW_G8}GY3^Cw3Wj7Q2H#Ann1P^MLH5dtXd9a|=_ zp_DT3cNf}^q`*m zw)I4A$1mGoUS9KX zF{_7k0+t%PDNoJ;tsR@FYM(&4;XBCO!_{{GlJQAPLk?=ufn*^ei3j_QcN}jbTsXVe zC^v#}x0F84_y{0F@z=Ek#B{*O*#^bVUlLR+2eF}M!LC$b=9Ykaq+&v@$fsO_cT(0- zFUB-iYBsm=!oiw&5K1vEg+-Igw@f|Ro-Jdrvz1bC?i2-Q5HEh$Lq)tl;u!q8XJcW5 zdc^&TTwJUM9}X1jO1a&NYqeQRn4CTgeB0j7a<{VXCnKWcOu&(HRm{_m-g+DZ`}Um7 z9Xru1D3i07M#8`y5yzp)-PB+(bk;E7bQsYS)Uy%EmH#Ro7n9U@^Pe^XaI3Dq`%5FFC-`tyTj;l2B%5v=pw5BpJ0*bm7N9%odfsK&0Ho zpC{7M!@FPyM^8*@k%fd%MSxbBwsc8pAjTJ5Xx~~5(nz0 zcyzrB_<2nlgAiOB0b%^Mz7ujOUf8@(o6e#A63ysupXU^Ci$F_KCiBFKE~hwva~hf) zQuLBE4)EDzh1m<}_z&DSbXL}yDVF(;FHr2i{^zv`fUzn|!#2~}V60E!96N}}vB~w; zGcziH<4e?mckZ5uI}TFtk<~*amRuy&UK?Xu-G*ZG85JR5t=Gg5I3e_r8|oG9Wf0|_hF-|h!O;OCTZ>6`1yfMv$Z zC8H@Sl+QBWjmSlHxNozxqYu4f)-NDkJOg40@Xbgvcg92jRZdwcvD4P|UUog;8@fV| z^axhUnNX&qjSt~wiTSdV07I_oSpMDLiL}YDEb21^dgS!dbHn6<&qiVROPFTC16cKo zO{t+$uZ%t}9ys2le13ol@CIVbT#rNr19GAAw#!Y7%V0ld?JFzGYg8VN@d0IGb;D!- zvPyOs8N42Yk4IgKrz_a#sOKc3YL$OTdBgqRXV?CM_hx52e7%zpa^f?c_gq{lc(^+D zOn&V#uAPb1WQM&ILgT=B7-%(`6KCx}G(NuOKE7yfqgwO_GeX(__cDmfBq%HkXjl$L z#o*mVokPT8ZRWm2?ez|IEMWymZE_DJsp_+nOUfA|` zuJJV!3!18K#2t04V}b)I)_lmxWBOyBB&<w2kv+T7bTUaVx>M&4u$*$^9iRD4U?-V;s$ioGbMzNu&YQhr7Pkh0>aVA>F$hs z8Xo6f=!V~k2~12QeLjP@u9$lykqCj`^V+a+Y0v8{hwO9x*Ba?grs|kD{%oR$w()C! zQ6&{e>iZc3fC!{}C44ZfpQ^X8#ZBZ^l?GM&KTvZ-FxV?PIs)0u>uukUQl?41tJQ(k z0URxWCW%YMme${VAz))o#Vm3tDES9ndC!}n+V-~Q$YnIP4zB5n;)W-c9NkMC833gR z4VlLlxMC4J2cX^*vX;6yBHlLo&+eXrM>s{;f;}aE;E7g&omx9rvwK)8x)69QGXeO{-xm&>MH$ zN&L|ub2?(Yw)}_X$Np|dKn)0uJB&plCp!%yQv=exSSz6~DNc^T{-`Xz zeA8m(?XIY#G=kMRZE8t>+s3vg$uYu5kBjvZY_TV{r>d*t!>Ly?m@eZCe18v;x#oT( zyu2{Li?8g4Nd5uQ0}C@yL`k3jPLGE!twPkWuN*xo{{X*eDq)_76i3KEr4`;Mr1ZW4{A!y;m7r3&^~-hD zgn-_mzhkPL6#?tH@++^A7bPX{@X$?3W>SnAhwd*3TIr5`^_BPts)%8~nrCP9S-2=4 z#9;Bj6MpIQvOblvm~l4M(A5%gzvpas1d`#impt>CYNa+TrB{e}_t(#6sNY;~p#@Q@em#A72M>9$cJVZ87ZUnfY5 znZ~-mejAjYkfdibEPMoju{IdRZ#$uAT#?K^O%Ho~;-Z$fCoSFg?1!^mkaL4J3_@!mvWl(@{4DSPEp()j~57iU1S=iUb9n`2s>wrNrR7GLyFF-Z>%QU;wYO)&9T9}Z-B0V4qoJG1>V#f;m28T zhk!%IeHesNF)?YI21eXZ4HO*(JUT^b)w(Yl=rDfo^t^J_x(?(^wviqxHl;bxguF|F z@(Bc&7eIO5;54nCN@K2)Q7PbmZNDpAGRCY;IW0E*6J_Wt3%PB7gPIw5D-2U@?_;h{ zl3YMMHc>NfhRp)rSAQ62H|`G^)T&WISQ$j=x(S^cy9>DFBa~=~M?x+yXom|;ZWr{w z`o*nBpBWL8H1B(9TIa*Hr}n?z?VDRf%het_Lr!&r-Bnr!hLvw#@Ew4#X>N zL%BN;20V)SVCgClyYQ;&Hs~^YMKwmdm%`s30#bI{Nq6+}gR{sRzP zymxj2IisoqHJj`r0xAVklgOeJKbjcah|(65yC`uc$u{)P6IVp7+q|cT;@QAJO~HBu z8G^;yAq_vzg>5_b* za)y%>DenQ<(zyn)jeS#ehxO*!&n)r6`_=$51n$hS2B$4M{jQ1hLMuw?g8Z>(5j8an z`K(N059^e$1};;}2y{o;TNXp!o6VA()H-~6eI9#fo!xCNTdfrfOZs|xRvO>v1HKb( zkk57NPfB5an?0DLGfrIlojJjV&=ou`EQ^&d{=WHyNxlF#HeJ1hCtF#KT!CQNmw%rW zFYm-4obK(#(&@zb#yl;EE-wCD)yM3Qe8hCT7~=E^o7GPwpaTg(n1 zP0?rvXrgl`M&-pw^wh);)SqB$dFx4Mtz!^`Oo}%f&A^GJz;pGP|(z{AZE!qcssv(zS9 zqZ2x@P2&3&36iQU@eN0!+ab(fpjG{1D%Uw(MfWvd0aDyaNkuhFXi654WyAORgh$Py zZKtL+!Dy#q*|~z-E-x*0@o<5*Jww9Vyq4@}tO)eO?4RA;;?zZ^;bV;%4u&CMZ@4mq zIsH}5LEK;_%Te4uW_>isFi~+I@URu=;C)>9t3$L~n>5py_AbnR+a)n`YyhI*2##9; z*;6A=zQEVaph^A_%RLA88Q(FwASiqn2MaDBfuR~73m)LM_x&a;`^MYke!Er$TYj_eN9RPX07K?Uptn(L5z31ZH29%I|d8 z?)$Bg-}2P`1yFjy65FtQe%4CAi3J-a(+MI_HksA>X_r-58(=u~cQ%Hj0n5+GP9veK zBK)pioVwuw!zC$~S@X(vA}2=$ueG_?(@3I(Cms)XZ0QRyExk58E!a4#Ye9&d=_(FMeS%FiP|( z-2(=K!~RKlfizK`xZk+WHX^+q-I|9LxhTTf(7>G4Xy1YJx=jNTfX@=h7hTS?H<7N3 z4Y$tXy`X~g%ON$^0@bGN!xd|$tIQY8zkZ(X2+;@Cc@G?5Xj{HkB2w+{asbcUD;Z8> znyowN>M{fK&PaMY;f&r_fxyl1)Bwpv!S3Lx)JD*5FQX^Y<^QpBe=YfjS^nZ#r#Gnl z;ZW#;%M85w6e+Y(x~9+y*kwqmWt9X$_2~2JJd!IzX<`JP5-2O){F5APAA6<`{I1TE z=d7Ief`sQ`s$`BC%Jy#9EE${cP*u-&L``gG9pL%`iH?sqnZ;T z&1ZLcMtyiU5$5X$r7Cix?x{c+6Lji|tyjD>VWZ{(;)U5%q3t`cStsl81(ah$Yzj#( zD6pIwd1s$dnJ;0pBJcQK+j#@@jiGMRpSkZBeW7Y9wHE*`X=yr=T%S`r{HPEJeU>cP ztk0zY`OE8Vb{foh{8oZmDZFRL$;Kt7qpon9+`Sgi&j3(jA*v%sbtIPYR;~|jn33@M z{{GTJ@gyH|3y=h&$BodM!@Jj?&tRmwTNE((Pw+$G!*2cciL+k-TO7}qThV>`G8qaX z6Gz3_q~^HURb_ECl;y^Ja*0)FX#d&>&;-L}U&6&aSxkBa0Y&nq#jAoEmLGo&q?#|O zjcZ(^!2a(E$#ynJrLQEuXMG^N6b*_-P8c?+m4q9=WtS5ZAal%{+_2T}%+xTI<9TVJ zL?%i9O`sAbJRW$RM^I7FsD`=$n#R1JR245sz~4rr-d}n;U%dv|tOb{v&_4OGa6GfO4Ar4~f=H~|rQClGuX48gatwk8yBz28 zQ%=gPK=lqmr6Z*HZ47kVkclAx%SSeevfeb)>>m}OfEzX1xVSB+Pp-_-aSFzkPb;dy z0Iki-heo5j#Z1hBOw9EqlUJdYG0Q{w=cgvEMeTV-BV$qLCpO^dQ8hNT}(N39Z%LGavW|iC&ndLxg z7}R>UXZC*g>K!M&HCm-M?FoYs$NLDxB6_pjj&4d~My(WH7hp&kQ~ZdH8FI})fnxC` zrlQ9b(|vggzQ(engMy`WY)ft{89+}|;*&1t*K3@X8=LD)Ax<|8H^^xfP^;WT_)9?V zYt;5=@0K)K`+>-Ii-Rv->K9*9*QH1oy3~Tm93XUFsYQe@E@K#{0pq{rqFtGq!c?>b zz&yUx>S)S-RH3(2t!~}thU|t|DC#e^N%w)N)vmwGuMTcU4v*ttMs;8(*F*FYGE@2m zLeE7dR|~D?Zo{7jcsmXJqjG7epX()AJZ`;3WHk>D9;#!+@GuG-T|>6{@;WL(Az8 zs3Ad`3O)}7Rl*R6 zXJMKF(wcjpR5yYU{E~At*n|K<0ARHo>|+Mb57*xv#4%$P{lr-|X+STlEx2 z!gc3|baSl=357AJu7)~vJv_-!+e`?XAEYc*gT~5yo4^ixH zdCi(!qg|?1#(f`e2QR}hc)RFpi*8(9paq)Rn<_6)JMiATFYduC`%!%vjq;_5*!O5i zEN(*jF)GwRvchQu-pSc%t_k?FT=n6dE7|%GW~o36P!=Zl3Z3}2PEt-eEt8l)1_BqN z4c&ik0Gt6m7Z{>g@RQeOi(&hvvLFBfoQ`3rM@mj<63^C-5s*h0=AqQ0wFCDJ*fddz zodwKo#WX5VfaL)q$s2tn?cns({&>AL!wig+Q>?878~w)G<*y1#GLL+2N6Gj@Zq_!} zc&~#Mh|}zD;H<1bP5U?my>ueUN!=~k?1N3aVZ!A40w)UTYoT7tUhTfv{-95y9b-n<0K6QW+I& zHByzn8Yv(Tws2z1#HeOAbV5hnwD?dHHyt^khEatp9ObR$J=-61 zNmDk`9V5XgS~a>7O32Fd;j=W3g%!zmxoK;GOg5tD_Z8p~662KvX-zQ$C1R3h8e?ow z+;<~^I{RNWU^RCEv<8yXO@O&#mTG#W2<A=VjcBqjoUUkIXV18krl$*en&(92_&}c(ow5bH+tGR+f zLS}0TfkWUIY)iJUILIo!_;u)_9~s0B>}<{xuQx(4tSgRn_w^7dD?^;Jn$Z6izpZga zF~~($WSAb_7Nx>R0)G0h&cENAQ}U@<_3trN<{lR>DVA4`k*7EVLa`F(Tm{f-#JFuV zsVWPb1FGkP@SOBJLazOGdA%d$Q!VPAKfV~YGG0Y?SW56mMx>Z$?CWE91aKs_*!F7a z5?bZ>RPTGYJyL*x(+Ljh_22wJF#knkzimuVtU+wkoFGevU$KVBt(VoAEbV00z|Nb&?zRmvuz+83Y-RuqtM zs0C=l5E6^1J;j!9Qsev=G9X;|qs0*lnSnv5?(DFIF~efu_kS%jYT2R^{q#V-6i0CL zY;=C-4^Ut?g`b3(e1|X%h)2a?K<{<2Mq)f)Exf`=K|MsrQwmj0HW^!o0&g3)9MIoZhMMs_P96#081K=8IqjgPa!u9SZ{7U`L0@+$HE%KX zy1S00(O-dl?5kticu(4~^cy&dGTpOPA?OSc%*~Z-T8=-uPy-I>F!k4(zo${rvSTF4 zn>JW)T6MtpiHzTxA~RhySGn>kNDzy`w6&VuG-V%?aI|2Sqv5r#tO_4eF|k$lu4iltogyz`gHbvvHn zr%|9|mIW-vhpIMC>n*OhBpy8tY`8mtEYGI|SDg_#ias>S+}6wLwRwP2G2pol^z8Wy zzT`O8w(79x*`oo$2mmU-5&urGlT>A532%U_Q=^+H?OJ|S)NSp`GQdio38_k9>IJQb zIYPHPJ(d!Y%-hWQkk7fo1enMz#+-h){*t2hX)rFP0Gz8w7g_7U<|oPGKE6tNkPae9 z`^djCu>&7GEtnQ@a8~`iaxs3_(HwNOS!%UQZs>-)>M!rUL*cf=Cj?$NPOpm^+~!_i z*?KebSvR7}9o%ym^%eFC`^&=B{o2d%&!6y$hJ%L5C4e`|s9c2<#UkPXa$N42Zzp;V zQaUJR$KH^{t?AcJPHFzP8f;5HCN9p4#;$SvhkV+R+C}QoP0sC#Z%0o_!O`sgtV`EKA{$_zSR18$0MqbmDYjYkVfdpMx1yXR5IjY^}ZtM&M|G-CGdk=;05&X ztSOz6nqcuNgOQbb5T1Nycya&0i#m(!3gu-XwE;9ldPl*>@8}uy47g~P1)<=tClQAi z!mO}p{;r**eB+&JOL7JrE_r(V`y0<0Jv8JNNx!vHjnxV>Kh+XisBVZl>o2Jh@R_H- zh}b@kEH*OrE_=0N)ChqDy?jbNGmv;U$(FComD0lW%yged=mEO-NR|wrr&yvK-k#a9 zOuL^WKo~AkZa7cXRRHvANhK%j>>GiX0}%L>{=)>B*SV}}{P3#$_`9(Wkc8G^gzz%~ zig6<=P&)Mi>rjIJ<(Ks}%zpdIm+-c~4C`K0Ggod|e)CmgKGp;3h#MHBDjz)dy*tax zMpavLr+F#ZT}+?pvFKSxK-5Q$d%$ZaO88ygUkGuY$p+fk6Jk&}XZ66t3ImXAJr!XW zO1ND5p5DI)Rr56JS>bf`EzOUb(+e~Cp2Lt-Em|ZUJBaAe2mlHr^ z-lCxlixF^J!Qaycv91W)63x7&+|tKlIeY|7LR2d3Dla*pM1+I&Vj-@wow z?&2Xy8luBG98XoTrJXQjf%$seW=b2^tDHyvBqAVZTWPr;#^1g3woWz+#q}~Zy)#u5 z|I!C$cD(uoeDo)hjWiA%j`6}Fa#6D=mYd-cV_iKv?8*+Uytu4o^OY~xQxNaf(Of@m zL0beewuVqgShYV`W}Rzp5Bv9Ux;M1JFjYP(^r|cn$Uey7D7VmL`g#ybnJa|g@Zk*e ze{InivRkmooAHQv%2z5I2(1mG$qknz6$Z#JvX|NW4Fm3y>M*J ze*;Ei%gJ0hV8i}*G4d5gk zHOyKDkL?|ihNr71$^p*41D_h(K<5jc{B5PjP?dSsvvPU zOClDhbp~jF`QeHtN9+};Ybls2vlAapezd6c2C~@TBo0D?W@lhMX7)rL+O|?&>Bx;aXP^OMDEN(aEok+pfOoRjKg80ppZN=LjtUZ|>Jey3HiU>BcJ&_%e) zC=1QqYqw8Rg&rC6F`&6PrHON%m#ydW2f5^A!LVBml@roY? zDFa%k+7Eq&gan^^opuMjjIoH26y?DU!@jA+EUx;$6Utj*zW}+VDI}%EOoaHI@!~wx z=+$6{R!B-Oa8xmXtXkbDluF|8@c)4PT{=m5i#pM^$iIk07M6lc#Ye<`7vwri8F0zA z`x!)~SPkR*UJ(-zxM__OhcB0))&5zkgvLDZlA zcZufzxTEl&ogmZ#rNVvOMqO7UHCJFu5#p-9F^ni(g#5@0R=i>;7zan9x)b2#6n6aU%`rXl8i0NEJ!ymA?*uv)%@zj%_wZ{mxp_=#8VNi( z&+tcKIQ}lgGVh!GMtW;b%4O=TnMCa!{jXm@4ryMuHeXRhy!X{CWyPSHvZs45v}EP8 z&QV@m3@wI(E=G`-@5Fm%M;XPdW{TapZ)RxY3Oww{Swn-nqu4(o_jt z+ER8pY(5K@j!rDZ+RhGxLNWTCzKFZ#r{!0J-G>K%xl|Ydis#2rctM2|z-^pqi{z~f z7BE0w59VJ;;h!@xId{|5WNs5Ei3wezW7>o{vm2M%4E`(886O(}9 zeq0C}Krw%mxYOiDLBLfTLOl-H(wjOz@Rz}gUp%o&ItrDjp%`rcZBi$v?SZsu!7+P$ z-?AfY_wAx!&fpof(Wl*`-C4sGevt2FOVcmRnUT#w(9M2ji-x~+(5*5~yZ{YvQ?tF^&`kaIh7kJ!ynJFFxQjpmZ4L&566g6ZcTAmTe- z_0oj|Eo1&Ofyg@UzLeg1cXvuW*o)2DCHQ>~xG|DTm?kV<*ynwqpEbwHcjf*-#JB6H z@rkPHxS>O>b2>3E28JHyaM`?;Hk6D70<40y(c2E7WQH*Uh5PqWz&V$A#Ck{~aCZU9 zW(xDM?tFA<%kjDy54$5j_B*q;qeHO86`M3Z-e~A`L-8JG4?8N&2PwApbTH_dWn)FjE-o^`O#; z3k`e=_scH3(p`PN1w_)0lhB!{d5`jgnezFmE^MaJmI8Zoyt>_0Ob1 zwpQ9V+^_zyaYAsy&DV47CJ?2#Sk4x_c>1x)Irj!Yz4Uzjklb5*lU-nx@tggGWg`hVyH%*mbrbCn%)90a4`)tIao+N*odY1m zZvtPMvjBkK!kdaMtPN|Xx^1utb>wsv-uIHnpA^`RtDmv0w*Yx9&J>CV%RtKwTs@#N zFjQ#D{~-mM-71unDycYJ>987|0pm$ZB@)q4?#){Mk1NI?HG;3{#uNQkrm=@aW2tlf zKQfgZp|-dyEL9RUme-!6g ziafi19}{qjDbmaM9l)_^c5RFb)jkCPm!1W6EYhsA>G8!fhUrZ(48SXGCBY{rKjkEpEF!+LI-H` z+a6VDRd^a1ayZzYh7!g`%R3YiC=h*ug8&iWub7k~(5tl{3Lv7c3q|ZE`&oKQDedLxn4q4m zPVFw$(KfeApinlwMq@OQi3PksVCSm$l^m<^8vT5F@U1n}%nVF!n@0ipnIKBkMdCn< zAT*szfBjE^kiHr9rJ+d&C6NA&B%x z?ld#-sPq_@M3Ib061hGUym>lz^ck7)8JQn2W~TFC{Tu|o>t(=E{3V&1?=5*i+q0z# zu=09yMG>S;#8(gq5c~PDwoz8E2FB$HHjZ*5w}+0d_6l<`(7h%7`cZaVu%T?HVzSbS}Fx-u|eHYl!=3kN^u#~w*Yn_{>47S4~ULdtTZ9O#c?*{xkUHxMHc!e*zNX1?V`<(}v zPpl@M=!lCSxK>xt$*w_f;;10ls&SfnAmMJhBGmz-*04Hl_|!?PW4k@uAah7oD~w%_}Xd4`!2IQ+SjJs0*rV%So13{A~Zcc8<~eY zpQDQ4jutH4y5*^=D6ce*%$h{fqLc z`^BhLij=XYCbi-?W9?Q=y_=UdJ`0N0f(N%ciXD6xGC6;rhl;bzgQPE&sSdw~Y@6|B zV-g$3+=xfVvHI>GZVMOdysj#iU^FpH3-oY;V+YX(=|C8Hrq+4sXle%1O^hHEK!s8| z_%4TgQFV!Y*xUX)BJK6yQwcFZ}KYP~GRmH-ag=7wzy??|bh4&c?g=xmDcnzHQX9ErFH?1Dg2ELHa*lI-j( z&5$K^kKjI{YWSs5602L5Y@2NswaoxuL_3F^>Feyhf}@Tj-(E8@?AUGrwix5qGtS1X zhX@I}dTThC4ye6X>T?EU-L5`wjU6Y7&Br=+z1!raz48*7U;WhP4t;n3t(!uuM|wo} z!Ji8e>s#pP>Lrh8dyc+Z4@At9O#9|Bjh%6O2AC$ank*vEp3gBpoxi+@+ki7T(V!&3 z%=JIXKk&E<=N*&p7}w;&&T7XVnsN)4Xge%fh29F_b35ph90s{girpfET?GK(Qz3$c zb@&-YC2bI5AFX)MmGt?y`ykuCY8Gb)ermqHyw??#W>WJokWf69s-Fsz$8&>7zLO5# z&Y#iUn*76F5aV}*plAf{b+2R?*?C&Gjzx19>`%7Du|(^w{#V2Sp-%(H+ygPLTch;K ztUiBAODf&trYt%<`+CmSEpv2n%^YIMrBYeqhdp%r9;~m$%(uMsILx|tHxt5Crr|a1z?z^Eyb2lF*X~-a1%d=K_=LcJ^X1Z@3C|{Zk9U1@BX*Wm@eeBIJb>q zTVP~MZuvR^O=Ss%7D}hFb17b5Rx@iYPqW&Now2<1gEKJ34INUQ9}cZ{bS!T0abK*_ zH&jA9C7Izb57j`;Nw}pHTDZ1mM41Mx9q9p%p#grnx}Wu;OCHE)+IhW9i`Tfk`cK#G zu}#&jKEMTH>4Kf*2Lb4P9GyuX&kIahx2B2FW0R(xz*ptrRIlD!tzz2R-edkY_+;kwD-M?mretsb<)Q*7&4| zt+2nUh2%6sxZU}FJdiGQUE)ia$Y1dIK-(q+==0m;9K^EU_T`XM4d6zgUG4-7ol@{D zG-t6r&P!zZ2vpivm;Ga#LRMcVx+> zSv%S1#>wG=nyNzqlTgO-#=%KlP z+SwQsF}c;vi8ZkY6<|&>ndA-5! zM$e4$?%KAvQ{;$sIAO%}gmUY!F4Mt&HiSUr%M8r+Q}CyW2m_s^B@3lqaaZ}T)okqC z(Yl|vosoB9Wy?c}neY_eq5wNPDF$v+liCe(p??X-YX%{8T(Jrfn>FQPF5RpasuqKg-yZ{x`!+EOidXA^*NBF z6zbWgWvne9({1uXMKg7`wQ5PTb)ci;crmQ0PUk#u?)mfrov;5iVIw<3-sNKA&#~s)VB-V zIE8?k@n?_8pM6lLt)@Czk+#TUo)j-W)95Cu1r{v(M|K$%EC2E_k`_s)F z^QY+4K#S6ln0iDZsWlI=5o_hm{;M1P)&l<|9jgk_AumEI4u)JNhXFPZF=x6j4>n7? z`MZB3>;1r)(}?J)4~8d311?G)tmndBkYdbQLf z2-c46`m&nzZgXaEVM3kC zI@w=bSRk|X}vhYss#`gi=TDl!uG{e^)z5xxjObGR6^zea#yR z>Nv6_s@9aMg1IF#ZJE$yVRNTnGSp3LGZWP4Q)+&nTfo(Fwa{5MA0hAjl}q!ohhTy9 zGu^^J$qlju1TjM9oEH?*AcIl+oPN8cVnmeB61DB{3jTM2e8?`f_dJP&G0X@utc4rO zF;)6>YbJR?rs?OmKo5E1`suX+^qHutmtnWAmV~$&m>qZxG(+VMB47d7mfqsbGU)&2 z5v1GyOxt(1tHZ8i6ao@RG}bHFW1l@jl|=6B)o}o)xlZdBoSa$yMoW5=GXY|BRFJNT zVAYSo31D?GEP~J!T@qRH5Lf!Q=m6NDJx*{>>r6N}KJJCItHR&~%EJMXXoril>qTSy z9b@7EskuDcFFTnPF^R-O@0B%4ER9d6mGZ(+_Cz=mn}KXPlS0OF9NO^nLl9ptJdkav3ci*kjM!AvpKQcOs*48;Eu`!r2c!!|fIM+PrOrOgre25twj>N#;~hKjA?T3Kr^9Xoaht2f<|AZTGGJCvtcO%~Vsq=WW{T7$=;j=s z>tC-cPf1xWNNDl#UqkmdR~~FBN#K-Rt}aP&>@c+@X1p3^AXjh^bgTjRn!dRUkr*;! zwSVaO#wguGHRKl(j+9l;o=dAR;3wjPKLvG=HhlWV8naduX0vv@V?7E=6&FH}QFzj| z$ob6=j@uduae(IEr$nNz!g(a3Z>zi7;pRiIN9wu4HI1$X(N}Jc&!_FSzYDbZL$TDa zth+(YRN5qrM$l*EUx4VH?V*Yict~kNQ)?nl-GC^hekS22I(|=qTihO+`qG8{q1~11 z=ptGuUEIJ$3~y`*@|uyr3^rAzFqg{9&6A)kYL}8_MY>(47Cy7cm`oi4($T;24>Opw z-Q&Ka zRr_avxc=$wKPfdp`KO14+84th-=u7aEBiE1*YeQoTaDPxfURppM*UWbG`{5JJ$@0) zlPZ#n4GoHeL1-BAO0|8+tiJVlV9*>8C7n2r^Bz;W-v?CEX+%!L$2ps0B<>$>k&?Ha zeB*88E9SL&(30sGfXf$n_!`$SF+dhp=fihk9y5+i)6TJ7%)=nv>N!`-}vZ2 z!Ia5N+6*ulF7lzV!ZnkLtl=GwQt{I_wCk;JL99|I?`a`^_5s}+c!B?Zl@>r&_`dF; z{yQB~YVAUgbmF!UKb|9p(q7)zLT2=W0Lvp|T|Sk0Nz46q!mL3h2=a5S6*@?Snth_+ z$Wtb0-;in<_eV_%C}e2-a|wjEwhoez+#XdW=y2nye$r#;@=!gO&=HBJ_%~%M3>?a< zndj~TBX`9PRj*eD6>)n&D|D6K0IMv>-7Bg5(EQCCfc^{m)W?y6S*TBMLq@2k(UyV!l^fg_a4 zji{-(>xjF!t(v}A2Z`)Plsyfoq_40F_Td^<%%R{NpLbAS~Y+HNf4SoFd?0$|RZ%S>COfe;G7 z!<^QQ9SubkAc{-?bdv=Fk*jRZ2Co9m!Kw_3p>lc2XzUTUGkxzhE4QO1N=S=K8z(+P zJKNXL?FZuk*-5%3+xw^&LC}LERoL<0O;?amAt4OZl*rIz@qmMTo8ZiKuqv4Pt)pKW zH&&~XoVzIN=%O+T=Q6HSCf=pjty^Fwri+EJ?$z-q-8 zL1HM*fuEYzuGQphaKncNJfVx|uz6@EEav}|ut@stYuME1}VIfYX&7;iKSlqve@kG%o*sJ$|ql?|lA5d4kO*dYT@nqh1F zfJ1y3&a8i3-VUT*OvPLJAdX)Gm^qWw+azqZi2CGy-U~jtldzyfemBD!`v1sdmR|%v zPLNb-GzW7iNctzOLOchVrY9)||FC8&VKSHsk5VRSFPJ1bNat8e;bFeX^~i6E=IMO$ zP8OaOEFcfolMVe}6McP1SObiEi{dYP&2fjVVo{iCVT;+$5Ilt?-0lK-q;#x2>kYCm z*Qj|s^wxd)cXQ%gO*Kk9?64o-kYXJY7k2o3Ii-x^IcEW=ehJc8}w3Gxs>;;K)2UTrufGKtiU%AwnFm&}OC;nsZY<)iMQ^ zE-8|kV1cr4Y4YJT+)Tka@q3ax8fN;8Qp@0z!^-*b5^H8(vmHRAzkmzYP3i5TS|%XE zkMi(S#De&(*~xio*(XeBzX(c$T=XmUL;me;`6ilH1)q+55y9YyQ3OucjgMDACg$HdhahtN_B$jydw$h{u{^mvT*c{w zCN_FcJ|sB;l8OtRjbVqG-$7Nvk~Ckknk<@zvy6!-fv_LWa@~b+y2Nl7!|N zJ*F|pN{SXutbQL4H|vvO0+CO!;}Y*@Fo!sf?>&`)>X;h;iPumxnD>%s9OudF#NOpG zr#2SDdeFAk_~G_0$FZhwSR!?{EgC65G+Kd|iDUB@WIXVDqnptGg2eOIATbmhKQQxq zr=nsAFueS!w}}5dW$|hi!!MNVsCB8F{fQOEtm@?s1o8vAZw14)0;)w+bdb6>>TcHC zTKJUj)V^j*a~~STo^f4<0y8%oDdQ41OsxQ0=r8FJm?HQBgQMS0vV_1l)8L7Ad8GtD zUdmszj0L`HMVueSqm%$Oaxie4lVJH-dAaivGF4_k!VLUA9sCQijry`A2a8ISvp&ST z0)V`x@APiZ@w&O8u+PsOgh(+B?AMSHmr@tEp6Hh}^u{XFYhHl@`S31xF`P^>Z8Bk9 z{>XsHZgyZWYk@xo&d@fcFDO=My^&m(ENPTW_sq)Qt$EVOualW&I`nZ0B0ZcFJ~d4L6ch z5m1=;gHsI)x}Iurq;la>bRnh?rZhTCPbA2B7Y)`ED)7)uV6uL%$gM)&0qsU1{PLs!g)OS)H>$5ld`CM}r)g7l(!QWnA1$Zc z7*wNVxSz=Bv>l&5upC75Vha3O9bCoh?U8HOc9^%ZQrUbVO>dDe@3Eds)SyI`?b&RH zB)C@~x$R=*qJcgis1_ny)>hqd4Bf^HI{jy27Cx5TBdKod&UyksYHHp|G`ztH8f~G}IHkZUcaZ84)_nMoY>8;d=Q++y)MD zVzU=M&mz_sLa$k2N>F1PRr+wfYDC4E5S z*<&cf<)PsGjX~n0d@d|gRgWY^5cz#*`{tolih*?r8Xg>+i= zZGBdar2rzClV>0`=WOzvSlZ^!_!l_s$U~>!`-`ok%v25Kvo5QoOhgXSUpbG3?evA(5u%r-Rf11pnA6q=c%AAfB)LGwh0@tt9aWQb00|jSWO(+kPDIt( z!(=jRkJdvH=fNCEDNY}3I!+!g*&(6{LoXjf-O=BKRQ%20C(fsPbC0I1acF4O=%-z? z7()!EZ?N53)^3J0c`sC6qdCQnyX-_q1Fy=)w%;JGV8e~sI%L#sc+^0?5ijkU`tY?v za5*$`9NNTfEA{5^>@wnR8!i%&>2K?|&nk`TAsK>gz7;$N8n&`Wy6xwi7k%D?Uo#m` zjo&XrY-9z;fXOT$mik57Cq20YM!xMORqQ_P*Fk7F&*Tu9e@TaIlZ%xZ4G3(?fd6>pQJN{;a((( z5>uuqhB!P@3EpiK3G8Irg*4}bnHBLxk%Oti!+6JmHWMWZb$|q+IjxBwNo}}Xca$=& zNk}@!!f}`70M-2oV4 zK66@2#SfL7Y*tm(A!@hZL!M0F#Nz)dGVNNxpN}fFJcYJq9WJ~#s_I!`*z^AUBnW7^ z^s6>KG4P#SJ?;HCe9fR+rzefztIb2)WBQr>ZLOAkbPE1@+&2*c`DN3{)@b9NN`mX- ze3IWCm?i-TjVg}5EI)(m1r@XEiXrApfAn$Eo+?7jB!@%|&5{FdBFvoug)|alE(@(2 z#Fu*d(#=hwmDv=wzGOY&_gCM1hdjh{_8#RBKge1^K1BTEVS;m30I#_2E3lwNNBiIx z$vigH+oh6_&RxsEu1JdWrqU3U1aq$qqzrsj1UH-y#j@=wf=Ovjr$V&vLu)t*%}ho=lYu$3p~6@>)-fHWTOD6k9J+N3i5Zdi ztZb6~80YhO2f5>%M5kE5lF5YK89Hg@&|Lx1LdYn(PB3Wcd?eBStZvWD9$&3M6zdlx z)OU~b?VKmVh24}#yTYHttDr1Qk7O}(FRXuj*rAPk1hOnPM^K#z33%MC49Mp5^LvSG6YiN$}4ps6DZl_mkS-8}Wqim*PcTlHkOS6C0; zq&4VtrsjSXNL3bwuERA0#LTcLFQnIVIz>i74^s2nVnR|p_X~SQ5wyQbFi{Nl@5Gzl{gENqYLlkb! zTyXVmKmk=3pDuV{c9;f)>`|XsQ531iy`$-XhGUSLqc)sCmO5Obgb(Ddz>RDPG1vC> zH+Q#=Xh_5&u@C9Np;a4X4+yiF|zAKBTW+TI)St%y)YPTYch8y)c`jG%+Cm z_$9g$cQ(5O6yz%~JOf3tfS75QOJK@?t8T70qdY$Ba)<`@wGH{y&o#yrV0HKPpz^O7 zV|9$}(M0=fWz41ZiOxxuzf(BbuJQB@Z) zPlHCY>Ll(8@X*9+^{2bHRemx!tkPSn!{QgNsk_YN9omSdi!ku_s039Kl3&8)(|_MW z1aPsy0YS%w&SosNt$fmBzUD$GwxjC>ly^!Wn1qhqe}h*jl^>tj8Vi?@iHEUd6~SQ+ zOBY?aeR3+}4Jlz8v%^>kn<<%3^DyU3E_zw@Uy`h*(BA(Ff>PxV3Z#Y1wnh(}X*J&m z9nW7o$iY%Td4Csc3jGEVZb~hquq84~_=uv`{WweAV5E zk&V5kH{Q>!Waw3e=YKORmv|>ImL`g6+eocZ>xgxmxm;tDL2{nY{7xf+0jOvd zm4sE}WvDP|mwf)G12yBHtU>6_;DS7xeefi`Ci=reOvNmEIb8FB{MAnh^(p|ByF_XAj%KwkMO=A zJ0ZbV$1fyAvQD1d!(ILCBB9OT8nWe zHCml-IJx?Em<<%8(H+g>kvbg@!1dUG+8| z6#^>Q3&X|2ez~OXc}o(BU+5#n^9hyzgpT$V=l$PP^rIh2YHEh`-F*iEmdWw>#wn>B zT4Z4n8f=&h7J-&v7`WT(B6KMoahMzvuYs{^+cX{WUf|_SmuWz_Y)MejEqu^lN*HhZ zw-whB2h22C{B}wY+X6f3*I)Qc;D%G!yBoGU(26-=j@q;Gqe!_Sq2$6GMEPMvmd(U1 zhdXLj!7QTR9xR{bT!fPagS1`S@yHdW8@0?x*Uf|)vS9&&pc0xfLd>LL`6;s59IG)U zsjCbHptcTOddytg=1dd+H)&R;x4poQ$~i|fYT=%f?s-M(W+9zF=iNLz5_Y`L6swDH z7UG&tmAv{;q!_w?-w8L}dinjNB|EvzT7>9(>`veXc(#&=kfM(<55oDWb$+BF?K}~y z;Vdmfpps9xhO+3xaTEZc@Un~Rft1%VN;~RSGKBcjBd$2vM*lu#dJz8aEY=YZKxOo* zXF&Po{y%)Ru|?m-k4!;~@Lj5E0%_iQ8qqbJYrQSMXhtSvndg(YPDuiMM2NEX>T`sy z_Hx=2DD7)Be(ip~@v$hVn)pbCIJzNYlgYsHU$&PBDkho**MpQ9yQ7b&{5lE8aJos~k;h{cJ>OBT0mjYQm(g)mVxAM-KFPB(VFFNim!S5=7Fr)kN{GO_Q0M+YBtig&m07F2$zrcYDyZ>Qm z`cR>JzR)3+fQs->33Y?ZJNONDborwoyot0jRj`>H9Sv%4V@H_WT+K@3WU?mm!t_0C zoRoDmRsw_zW0ZSX+)^&`XLD`7>`FF*{6s8T%#{$83raB3?tMfu|9+wy z1L`B??pQJ=04kL9w+@jeH6l7xthPwfn{nsvx#BtFSHvZCpN-}#q>$k0=Fl2|N;CGT zvgB+XKJ+RU%iUdYRi_g1K?k)Us7A><97g$U#M{%?1m9cxhYOvD2=r#w=Sg9EIuhp% zi+l_izU2v*Pz2Jqa4@Ms4mtd5oPT5r&Lb?rv|&8=urlvH2zhJj?UGy2)9(Y6v1U2z z-V-3aHU;7RGFbix)33#rtgn;15I}1UCT@FfvLQF%PH|2TEkn?^?+!z6i7eYqOS;%L z%c5>>-_{otlDD3=UVWv*S3Z)e#mbS^6(Q^TL$NGFG%#N6Cx@@}veuP0YO5XrOUHKbFc-{0}R*{FVP{L2AZ*49`TlVF#a~ z8(kXDM8C7Vgb&o|({P(P+z6YUc@5!Z$M3Z1914fRzNwm`(OL!HjoPgX+)QT$PZQE^h9JD-q+H7X(ZupYP*oc z?MhV);I`0DV5Ww?RVS51LBR9yvm|@?57|4*{;VfeE7p3_ed3r$-}+>{w9<(R@*y(g z#&~il2@)#2j=pgk?jv8}3!)_e@_*4?42u}$VBt76N!L3V#)m`A`o8Mg*RZIt?^h30 zsKcI29C4d*z9KZ1^eCFI`l>kLa!pZqMj-pmoK1714v3kCGXlvfDm#xnC$g2 zBVEUQXVdQ5jK5V4RZk7D5yi6BaoEX{l87ns{SBckIM2`qIl+t~$E<5|M!kriom~%> z-iK{JT?;Kimt3>Iv zHg@b@O_e`*ZAIuB>Jy7Z*jPBvKVN%N;ncgWjIl5&H3+|1j@fP?{JM1yCu^8&Pqsi( zeM5dGsgkK8?nCC!#k#~~p)?VUaHsyx<39a+%`$S5jrxJqKvkkpJ72SCqEE7HzbtK= z2M6D4&&-y*mKJTBlh4H+154{x*1|rlaMP+a5b&iE^v$^!mnDSxfwJzvP3#x^l_cr` zi?gmCE_^W36NqdV=$g?kzNQMSaT_SyQ9sAyeTEHA=S5jOl_J)@G$h&mv{kK)2lnK2 zffvY-d+`l{XBBjQiIe$0$SX)B_kN|-ll9ag2Q*k@1loOJJCw6m5)Gw#{~u=0?2A06 zJ?HQLsHx!bm*w(VOflPrD}uxqJMmM;@IP58XYDa^hpNWY3~!wU21}{*=@m}cCgHt6 zZ|@j@dr=)`L~w-OrG(Jc@VD<#X2-FreyU{D{c;`k(DyDujau;)nf5PaZQl=$pyi_k zEvaQT&j}ZS^zA7CRnEc2Yx!V};7JYybsir>)*W5wlH=h45c#bna|OV*9au@R>5rCn9{;1ffWc*`!enbnn3M735eb0IFaM>9(sG=KZ~>)T z!=2eS{}TWX>NP(o`gbW-${0-j@`)+5wSffuO>sVxgi!c7<5rl0OWmt^klNg|Yguuq z%h&ICD9>%g!SWcJ2_wPjqCuzmH~874&DNZ`{^Mj~SH`$eh!z{AC%8}pAXaB!7~y}dCo zBv0JPy11hsO65wxYbFab0XQhWvy1r+4{FZlp3NJN=<$Lc41Y^Np?-;{^~j>x?+0!x`GYpf^tx|Gx&W^Ppwi zrbCf}5#D9IW{tLv5JB0uyEcBNyDHdey+u7N#Rg(XGVA;kPJ=o z;&j4bAso=D;Q<{l^418xGl)1!%J&~tb;$UMzafJhWFS}h{9^NI($;3u#`7i@&#$z=c)(bPlym7e z9`A^OD9jbA-H0VlF`V9v)g)$aPz8$OM~J4p&Y4wJc~d22E~0NmvzXTR%~ibC;C2)&Wm zs*ciSE1-nlw3c>UszYqL+J`soTX}}3LX9DX8n_!i__?Lx<56Tu+*xrb&{c5CuM-iQWk4i!a8CnoqDO$XpA(Nu&Bk<5Xc21i-(H7 z15n&*TR*~A7(Aho>^(Jd!eo`Mt*;-zDo_+mQ;%8q-+w$UEuoxb(e~(y)J@3%7 z*XA41Ydsll_e z7|B3H`V<6^sup?u1wmfHMVzt6XunFe2eK?0YAcj4`v_lAJ0K3j^w%yI;Q)8s62s{Z zRdR3cE4|=cmO~tiWS!MoTW8ypYR`cw^SquNlUvU{AJrJ0bSZ5b7f|i`Ub)`Fa@U+lxgKfxLGb@9DR(7n;MjKB-O*XP-Fk`K?xr`|XU%vwHo%1%zlcp-Sr6IP zQkqv})`;g~erYOp%dI=YM)?Y`p2O{-2@S%zDvzHSu)1s*ESdkl4&vY!Y;}k`w6oFB zNf*m}f$7KEV!Cv@uq7rw{HT?kt;+NI<2X9aPfk@saNa$#iFsxtagaTIK?YkZ^Uyed z;6QymQ*1S$)VP4x7k%LJYC!*=wjd{D7@I}cek3&d&NF176UUDR3j(8AmWWJ43)!ie*wnQjTO8eEwF?Wt=SIEgL6SRr&ETg zqe%{$4w}Jgx5P_KOU2l@++y2jk!_6S0BNy#=WNL{Kb%LDfL9gpf zj!9RxBIrQ~(xDptj-QZQeK7>A?;ZdTf9;C_?4nLzZP4co%v_Acya)t+xEebmIIDc8 z3Vzq3xmCV2=i@Si<~)UCYZK0UiHm>vjPU1yzW%@O%k;Z+t8~kS#1@Dpq6OUpCbC8y za1I&>Y)8kmBirrP5{Gd(t@jYub0kd@J3c?Z_WtuC3td<<0EN}3jsbkY1-H9RY1nQ4 zf=4$2r}F#>rcb}!8tc|l5%$w&qsZvHRq9Wy36X6l&gTWEJI)g9e=dhu@I-U`tiq$+ zzS@fNj~Fr7OHn0TClJR~)~^0$Tj;cg9t1@Nmk(*KTs3w=P-?6@>h_Liao0-qrFe{_ zlECf3Sg@`A%gYIb`5&N69wJ{;TO|9fs(OV`kGjr|1F;CeXXvW`ePE-Rd91THa&nbX<*E2=K|EX%r=oQub{K9*(C~7L=-PiK&EJ$@qRRo zv|=jtz6*V$+)rEKb0=v+gC5{Np-?6vo#5Kuj2Dh4sx6$7%-n%n_`^CdXU8`QOfKhQ ztCfIn?jbS6c3Zu)(RL~1_sqPb>qF{@MSfFaVYHSX=Nnw?)oas(EAQL2@WMDS_tl$>eGaL0`Zo>h{ykJ_ zdEyUeJAq$bBWfJDf?<7m&Y&Fw$({!-VjUSlhuz1}Q33mAI~a03dA}Ij#W+CG)&A9k z!??ob{*QsvF}mXl4#nj|-<4y=4l1r#%`zLeJhW4*>M0)9sdrX_5zC&(Vj z1;fJ@m`)x=mLy(X=-J0U_diu#8Ae%~>0Nsk^gmk6 zAep$*PH8BeTAOnHzbiyYSz#gBcujC>LIIHw{vNuC`Au~f5JvlJx085$F(*emCP1kd zbW1qsHaCt{VzIMPZt;c>oqM9HQ408kB1QGlM%4k*_;pDxOck4OG1AJ$oQMI;#o}u!GM1-Bv7t>klC#E5d$uhcO!SPn$L%#PA)u6`2s z?8*Pr*?9N8(hIaixVHPtDrtz~LbfP(1AF%h=B3_mb`#gJhq`*W;_suv!Hni??1}VwS!IT>poM!>Q_4P1wRt!3spCxXy8= zB54nHHfGRF@g+7UqFuvKa+QW0Vk^pCAeMNmi85spoc<$*3MELH(AL-7ch0vK15vs$ z)79Va#V~RX>96gn^pTlcdvMyo9xSJA40|>P^?pl9zn9LbiMNohO&fq{%r@h9E6t)| z{drMy6-;snWb~tqD9W>{Zr;E8aH~?foE_zOl63l^>drH%N_)kjNB`0_A_825-SBPQXv|E* zVaqSnNa_?7)W02-OiacLI20$YT;OG&C{XyY;_wXE8EO{hfqITVeZQ)fUWK%XznSr> zfrrG=7UCB2!r@wcB^w-$$PC|AD)j62DUR$BU@3aHC10ML_RzT!)0PLEy&(4aVhy|| z7pS`rC=3y<8K}CjZe0)TK%5QN+FCQgiu!p*Ek*%vZ5ym`#R?)}YLvdhr)>#|P+Bd> zTuSF|H!oDO;YGl30(q$&1jtF|w{d5%R?iC4q?|}?HNdK}zEwsytk;2=z*1;KIs?Kf zLQ9NKSfCCMHs4pRX=}7@(9Y6$@Yw=zN>vN>G^-xgC8+HEJOn01qeh;7kM{ z*wdrFF`giSvy$<*>k;N9DFGEFDQHA`(JA>eiEu4MTOX7c5!D22FBmJ=M; zC;yqW5_-TaK#RE#7fooPwq{lJXLkAwj_Jo1kQE|l5wU*aV*LRK~XIkxm04k*_U zatU~exJt@<--{@Q&`-VhA7MPTmj-6lDb&gui~M)}9ww+7s8W-WLCOOD+dI}n&UnY% zQ0NP*%hx7?v4$i?wGeX{x?62(4f}0nx1&)dCavp{e>^h#4~iwtjk?;yX$x%4%#t@e$Z<|NI7R;m8b^V=hS) zeiSUJ%yTPi- zqpbm60}ACkCgx0v^zVPQ69>|@%O-1unc|alfTk-=Ir_he?wWojA{=1&s_c{>kQ+$R z!lD@bEFZ6G7Ov?TU8N8JXRO1@poYAHK8+7TFSAN2fIM6zwQ_BEV7y|+gECVm>oMy~ z%bOupcP&REFv3u^^6^Ql&`Hcu=6$FfJVr1Xs7|jHm81pN7?X&QTK@3Qk$K6yV#`FW zLd{Jv*GV*Km^VfA3h1@)pgs7FitjiPh_L=)iob6}(n*X-)z{j1)JUOHS zVv;DqkuoC&C-vx+G(!#|+}5OI6h~Rx zsJdkeVg%9hB&|u)L02T}>cC$IHT6FL4r7a)z3i%+(d%A(5 zcE1X)cG3D0>h9oQ6wp@>nwY+qJf6UubRpe80pih)6T|!PM35nF>?~uQVBbrC`h1O+ zx)stz)_n2)dtLzNfvIOIcRfaaWO4H1oZNJ{b}k=NzHER!4`hb+J~Nc>IZ)$epHvuF zKg6<$AG|UFbv;4{Kdh%OR}V%vRx?j#;(zF)L~oW%jm8pi%>6Vl@n;EL*2!;AJoW1> z2co6QvN_kf+*UH9(pvYLvy2+Ik~J&_9UF(eAPKaBSH%#1oj$gIa8;m9d%*m7|9zpErQX@=O0}dtk7Q|4FdyaCErMT-4Iz3BmZ9OV&P;2j#dyd-?MdA^3(GspB1f4_2zHd1+m3=U z?5o?rxa^6AtSgh6Cb_{dLCNeYs_=VrpFUTKV(@~^p9sVr3pL=_ zTb5}az>h!1*c=q}2(Q5eutN%9(#Ko>ZsgYd+06zH8IP~BGH~wO1(AEn zS@2WYAPi)Z`AfpafyyawT@mi)OtoSf|v=vVi{1bdT% zUOWd(>lZ5S(=S7rAQk-wDp%)7aE1mv-J05BjMyl4GB25iCD6%le0X(zs)w{PZFVh! z{c!+x-@?quAcz9#lkW>b0Y^e@+G;#M%dhpYCZ>y$8vu^j;6hVOB#@Cbw;K2?OJC+U zwc7_Lcd<;M=|<|#;8u1QuVdEs4u`UnPq;X*zCR5?6k9=+v<+ST858$MuLMfXUK7Bb z<*%bq9HN8`?|Ctk$&bnKW+z?<|Gne5lrYt^^-kaR#dcL>F+un{Kh6gI_t{+M7rHuC z%ANXcmQ-`xLpB8%dICsHTiSj+icRYP__JM6$FxzO+!2B{gOoYN`^_~00y*g9XxJFf z)VlD;`b6()kO$2cGqHup? z7L+qz*3_$o5)ZQgfE(ZDyb=>Zf?+0JI8MF!L*v9q3PMD*I*fX#)=Ey@Z6)NDk%Ei( zOd~=dbIWaVfL;7$773k~sP{C1PnZ-lg!4SuwfsB;jwsitpKodDhSuE5ifV^jqK&}1 z-OSRK3)kSCsN*Vb@@MSnUIdwbxqX2x8730LXontLU&oL2KVL(WcxdZO3^K$n@EQPm z40QCn2;s_g_`AayJ+yIVnBv&ByvqEgXO3H*3$`K7MSRG!AJUwf0XbbPzPhz1z9sfg zxi!1E10aFl#3tW>g)h?R#-%Sxr_|ZNboxswq>n4xMJGbtG={P?8oqC!GK-a@JwJIE zZ8~-&vu+8!Yy(y30kf}NyF*AqmmR%-&C0#gBoYqR<@qae9Vk1B^uXrHi$30ZUH8?$ z@+6u(lwuAm5-CarLO1@{@e|CNOvaLtxj!2ZB`(LlmOuCEo0nbXK=eTQmVT9Fiuc~u z{S6+*psz;ApTpcwWpLuEK<~zd7xZEP@z~n8!<5%J8>3JH$Yga!{TkAfG){=4B54^^^pwjARX4ee2O6==nvdsghGXHB)Ena}a@ zbmD+-p7cKi&mJ~3YeaM3E=UEm4zB?`_ca^c84@^SLUC;7-VjMcM7)6#LHU70_$(TN z1;P%XSq36RRr)OJLYK$8ETIynTG!}>zKMFCNO+}R3zDYH*_Ey_oiQD@bLz-4!t-G* z9NUh0phF4K)n@kAaCb%|L|@Ws6T}m!ZMIWf5jHT^bmiyB+m6xI05jc z8{_oZ^TC^cLhPV)LZtg5-ciKS47msR1#fW4rNFGF*tVE`e;O2M6kF}nZ^c2Pk_m3X zFpmFkApb&9aM_D_iIOl^3AbJ#Q*49i&MyaxwbbKj_-QcMKZ~{UT_DZ)NgBAZbGmi@ z<^Ju+j1)UOm-oJEXYNR&+oUpvM!T*PMU*bi|uepO+GIs7He!{K+c_s8N)l-bd zMWkO~CFo(o1cZrJwJZ7o8re&&uqCoaTce4YX3<+ zRnK#}#wTM>y|pNfh8%!Mlc7S^r^(9ceC^CYZoygd(ZlN_>^|-eI`>))x}hldhQbg# zO8H7?rdE6L&Z)_e^cZ=S10bABZHc&PQomy!^E|mwfet*Vg^lxktBGfjpPNlv2iSb_ zRgz61CQw8*6UGCa%(TGK>A<919R+t^lSll-^=YDD!k2o6td2oF0rqZfcHT5E0m$P| zeHFF~JUt8v;$Ln?dfB=D+}?EaodRl9R-J2-?6ba!<2bjXNw7pOEp5QWpFfA2K0)ilqm| zHGk{n>nCHApY))G>Y}noPlI?vSiASXoarhgLb|yDr4<#(yvOep8ZL+Y61HB83&_bH z1^cN(YyQ=d0l0cGXsbE0GEx+ddJvJ3e5P%-51{MWQwxQl@_1ya9mj(IGg^yNM%Um< zcts%0k(Oo;M>F-zXKSN@vtE84NKquUjviV8Nj8ej$|brVRn0*IeKf$`wTcqss$#$k zNFyc_KGhgJNL-M?wU{mKSJ1z7@pQA%(U&-R4cS~Wj!43zE8rGS+m?V#wDgFOUM4qN z(C1VM;3#Fnbp9$TJ>f=@BV5)n#)yh`fQ(g`%4=B1{$t)Mhv-AR;R94?$W+xd|2q<% zzdsm=x?@dh6>e)sMnfhb$!A7lPq0f#>{=%;4YgZEEyxQXN;0nk*G`BiL3;Im9;c?M zD6p&~Gf3ewh(4FvN9Zb)v;VG4ZqyzLiW?3&)5p@!C1S=AL8L_G8D9zky`-$5f_vQ- zG(DFJ16Y@rmhYD`^tLz2u;m8Gf9bE8FAI18*cy+kkKWYQj$Dk6znP;4ih5c2Gr-d3 z3sJ;;oq5(OGd4 zUQ!qHb>JQR&@*%k9ESaH&9>|ru8!RW4bUgZ)k&Cy-x0%H|G+Hn3KnwcnSTYm=1*Fs zNaiD9^4`)kNbx)icI7ZOav|IIti^`E#B}VUr15b^&^iBdGgDQrJ|_|BMLCvb$PY9ku6XfFcW!q?ImPs+qwbTY`k_ zZwei?LM_8f6ey%1hq?c)BI-SV$6IV*t1+dlWTb&9Ma#qx=Y257W%^VUmWn|}ClhDq z$`S+^P(Lz(}XdutSKYJ{zNL4_}b0+bH&~b6;rKEsOP)1GXsT=pA zp=PqVao6KV7l)xXK|qO`FzN6WmDWln4T7z4w~<#8 z3G@ob1T!!g%!sMV*WdWlX*DOMF7zSuJ?YDNJ1SIV+ntaoULnQ$bytH-t_43uASJJV zQ+QQo_rBYq1(+hcS!G8C7^b%OlefO*g8rMALqLapwruj-AVT1Y; zwY2R7v=ZebAAnP10I$b=ca6B&8X0V~qMQE!b1 zWu5aicq=d6|8^LIvBB&oIwbk{nB%@=sMEiG&I&Ji`wD^s5OTZ(w;X%D4Cr z$*i&G&p=Xoqr%`e4nH68mKS>l_gbSzKM*^)KJZ4a`yCeXvGYJmX8w0|P*EZf=o3r5 zEFtX2P2_gBXdp!{{Ap?LLpXQ4`S||&c3|!f$3j;%-C8bZZcbF@o#`=rB5bySV=6`V zU=KOU#bSw7h=AqR4z6(fwB@OkHB7pMoYr%yJK@rV87 z*rcCD&%IN5=VD#bF`BC~#3Ow=fY!1kEM!rCsIzk{IRGq8E6x^humssWB7<%<*nP@c z6`mtotCz|yEtRHiStRyYenT;=%{tY2iaS~$ouS>jPEk4X47a()gUec*zSxx zODJvz;GR8jE7Z1;bycp>k+{Ma4v;Y3U?>Yvh0L{px|5MA1tT_$(^SmoIKiLHM|)2ca<*=0>giKM_QnoTwca44hea)vtCwn%Gb7@+!)$Svla7iOPM^zRa# zOy_tuNwlT@ynIk`xzJv!+sCNqWq)w?lR|TlJer7HDtVtoBi>j0uCa=}w4(X*f85zj zz_C`OU0qj2=-kNSVnEApJzRX7Lh@`iX&N)r{hw1xtN@&5aS;?1;E~62e}WTo9}(0| z1W2sl0BoxqXXA>(8Q+@KxMt}vDcnj58c(z~q5!<(gLtPwMy9Ti(RP&13`-^=KIsuq zOEJMSO#9`x@LH>K|9RE`E zyU~k5V#t^@YIgx^nF8^5F#<^G5-PiGaUiP}1a+C# z?awU?vevghrVpn-p>f3-N@OIsHSq5$8grm~Wf`MdpC#hwgXBt6lN0jZ*2T&fw75|2 zx^ilRn;{HBy@m)ztSTEesTkovIZMnmg%cTO;>^Jd!1Yt5I?6>-E(3{sIKQ3dMy9_r zLatN3mOHOE*f^nlndT_45NptgG= zDQLY9FPgi+OF_d|l+&M7qHS(A_J3pXXlQrUKYA`s`UB*hU6Y zFvm)F*X(B$(2tlgUv9_o&V=pBb%~KJ4h4A`*_k#%;`Vmg`^wVgaB@3d@FbhAcsku+ zs0a?hM!0M#l493_iJk%#_vG7)(gb7cHIHRI%%A|*xQ6V4)|42J%BI>RJV`m1t@^)|6}E^tXHZ#;S!{Ez-^QrD(>`M|7Z&OPBFIjq!#W z&na!sc?1kj@Sez*$Yjda6=zW^qq{39q<`{4j4)*TJzVXsBkwZ!)hInHcSwWGRxg%iqFE{FzFVut0QcY9?I%INh) z59fE;p<%F|^4%ij10h)5YT)|1vjkISj#Nww6GvX3p7O<`s_@I->_LoUHkGaH zlf>quk>Vcb?1k^w%w7=BhdaKcom5GpAK)54;|rhuI(aP0mc;nwSC-{?j0)Q+1V)uG zD>ZT^V+U%80Ma#mG$WqTd)`)WH36F_$mt21D|n2*h|kivlEGY6DIpJH1DALFey6}! z;-?)tTZoxGI0F~8~sG*KtUTU>@6Vr=@5FIQ^F^X8^LoKesu`v zwWKu{O;OBPGwafZbMTH5jaF}T{afsps~P))1Q$pb@ScXHPvg4+kNHHC}l1U&+KYx)eu=4!&yacoBTwR@hEa!_rhQ<}35 zFgx|aL6aZ3K z3fc^x)lbf4Q1q(hmL03Q{BIZdIPPCnqtJ*0MshVeaeX*6cH|bCaAWb^Dr27}2%HnU zdw%d2Z)8KX#-0Ypk!0B9>_WCs1Fiy`T*y$b%wl>mN=gJvb}1WOQWAYw%6d6fNnx=P z%@Wk>gB4oVp@0VEW2yPDS4TJteWs3m7fk2AhNwj&*&Q;>AFc(m$&X(3jB2tLuyX41 ziZO3zKdfJ`FIC%!OWbj*^0guVIz6IN8m4^JPS-h(lWzUnyS)d~Aw|-AV*h1P7V>b0 zgu;^3;TPqz>?L{VeD5t@l*cQ?R*l21v;q^X3f4TKB~k&URh`0`^cKPe#F>W~lmx4kb@uPy~_2EJ8h(mD1&9yW7h|Y1mEZvK!dKTREEVAkuQmF4Wo~ z;u`?ZtO?#h8@9TRNi=h;Y$e_o=_{tzKgPcVL8e6&iP-n+qjUbxSOSk3KK2biXlydv z;3tT{NAZQ4u3DRQCYTq=#GUiL#r1$ITj9v$dlw`EjqbGGPPSoQX^lq#|5V%sk>DiG z5lqN+M&6Sax`C76=D|OlCTgn&8}d}VO$(ZkQ+{paq0ii{VZv%Dz{h!_WF*RU&zX;M z2Bj@`74%gDJrM(;gV*(@V@F2l*8qM?cnt21o}8JkZNKBUb8q(s!E>8gkdRuGa(e~z z`rhYI6`_6sj3`&v`OHH*-FlwVeh)kQpP z0v_V!JqD_f)2w4_R;{W1T1XfXad_gEx%Wx#+j@pZrecIf(dzP*OYB~zn$*H(G30c6 z^D&JAE#9~AjS#&ul>mUg;Khj*YpZ#a_>;m@;I6&o?~HNnTgplcZGCcvvAPKJ($y8I zKolzaGLW|`(1uGujt2Fv85xrBtT{<4etMHZ4Yq_eAfj_btA`Lxg9{TAuMd4<^)x{S%u!T>Wt-H!aRY6;@3|9*xP$HE zC9e_SPh-I(m?>_aFk=U#^yHsfK5tD4;c+7C*SCi+lHl^Q^1wy_!?=3G zdt%(0n)*$yxq666SVx1OY{&MtuL*_`)YCiwhUgq3ZlCC8w*)CcakZ3Ydt{fJ@7L}C z#*{Hh2v~2T9E7c%zPA}QUY)tlX@?(Pe#3B|$}ZC6_Q?#@IK#qN*Rjm7%c$_x*lQzV zm*uUu68U@6$PX{FJ?x^|IbD0mOd76!588^W(7tXM)-MI zss;yGPaEN*yTFu$Iy1Mo2vqCP+T^P96y?{V!$5wtqKo}OJ>oK${x6-hxqFi5ZX!la z!f#~LUrXXULo9$u>~*`)NUw8GK1(hUc|((i_{N#Qa{y0~8mC9$pYYh|et|=0fprM1 zbh=Jo6~qt~E7?$HuI5nwrjBTBHVeKO)Cf2TMW6kdG?Lt1;78*u)7_nAGd1qDhnR)KU-c`nsv^py>eO=oRB2@$# zTYUyY2M6m-hI{n+0@slM`*$Vz1h1ZZbY?lzNAl2(;O&fPy7|m7^^1~6BS~-EmKh99 zfYzF`+Su*W?f?oLRvquONn5C~*x-CDErT4M3HDBd51uuzirn$WvcX%K<5x&+@+Bxh%_2+aD{Z#EGtTBw<%_{ty@UE*eT(upsev!-K#)N$KaAm+o>Y3 zn-68uk`VA9G%u+hCr^H}dT0er{vh0+tcInFsNI3Ju(#XZq{u*cmjD4A0El(065@>} zN>o$Hmk$(wUVhyWrTFDU_Iz;R21lhp5%#^zHCI=#tjGa-$NjdM?>LKIdQMsG=B&@G zX%)@Y_8E=pK7+f6MZq^O|L~h?k{Il_EdgdTu{1dYavQgi3!8=da7j0eJ?A7LlHqEj zkW;YN{b(`~z&OCT^gA53+=??!-Vb0D>Vw3hy2~-4dQwy}&w{Oj^e)UM7H3R$vPn3G zzJ|ZCV0h+EZzW+0`IQs{sLMZ#$RTvGV99lV%Z!=v1qH7epYFr=Bmx|&!-%8N5G9;1 zDv!4g1Y`%4bW|>ZgOto07>(}S#g0KohpSth&8a53w?apFYEDg}W8yG|qH;FttXDEe z7VSzyhcPLvX$%NGetSYnfJfB#L5wKcM=-HH*<1J_$n4H}tR@2%WxFz~{_$=!&V!}QmFV$g|fT4vdW_iS)Jf)WfNvp!#+X!id4CRfFGMjHc zmAfe|;z~CIsT0zx=`Z^Wy5bA1{L@NDk_e97}M_;{wBL*dc8v2BFWVd zDh>jBjlTY(J#U4Q@VwL$bZfBZ{SFwdhBIuL`}a(Z|2><`$z6U(*k|cC$JCYP6uFn# z+6y`yC<}%rAfZPs+$lb(&xyM5wt&eS4p6b}~)f zf=}JkUjUzqX3xSUMj9f1vT0#Oh1{{xP+K)%=f{O%q&VjDu9vKAwn;96>g3t+O|vr* z<70B5UD-}S#_bKU9AT;lv73t}RFnI2n{)!9Sv3R^4La-h6vPlGG*YC#g?mSv{>N4N zYe(c=I}L(GlJp8EVhfm)WiVzn@gkRf@~025gfG;@nVh+u9FknOhyN12A`AGD3bbl}RQd<1u1QIO z*^0C)l{Lm`B%iWfZ@0%BD7XCp2FdO22Es;qD&18W-dPc6jCEdUdf)>5;8*;Qt#$)bAjnGqPPW6_D z^1!egp(DSrmlRcK&}6+hQIZ)~N01EG;ay7P<7xAu0=?F`;#ODrzBj9vH`X2%O-iTz ziwen}SZ)6cHEhu!y!Or2Hj4M?T4bS+#Jn=g?#sduQoGyUAV{K8`IcdWdTA(ok(%>H zSo6(CP;U7*VcE=y8il-`?yK(rz(H|sfvX-T0cPT;5NBE$y_`}peC`^|c{u*C(bB`L zOaYjV@;SyL1tA#O<*W|JWc6SG%;y-8OJum-)jnZD*Q7`iAN<7STicIo=SJneoE6jP z-dNC(8M~0d8Tno7wD5qjjYcgZ=mC0$Ur*deTS@Sxo26OW*%DJ=1~^q~5UB>wmrfiE z8ynrw%rsOk=`H!)QfJi26#&&k!y|ReO2`;(;+y-#75S?ib*j@UIG2} z^N*9Lvk905w3$znFXS8}a&nY*X|8f#=}-;(2-5!UUcK|g31dbHQkh!K$U2zEm?Gx zfzc`I)J@k#cn2IJ(veyj&ygu(B{X)I@Aij#1|Q5)5a4-D*L>&+plfQIjPH`))(4Xn zvHil`6t48^>t*9nAd+krVyr#Eyk+8r+y1oGama%!z*07%86)6`NWcQ=Zj;$aR=ab&M(OYJ(T1hppmnp8y2_b2}B<67bN3@iwIP zd*o$`WA=!)M#SV4_9tkjnA0ox3`cz`1ETG(av)nThj+%7=6~ zgK#>cVGfOrx{X}Og#D6m^FZC|^E2RsosFwbD2!dA+N0Ss1Skdixlu?62))a!Kd*}r zyB_!npk)7Pp<*XV|0oBRpVX}BXisq5vPFSglUZCzNs}Y!!C;l*H6zXjD0$7+!hP$= z1v5%PZ!ST!c4nL8yFdo%MPnxbu*uvr`gg)gYnf}EM?c9{6$L78$3SaRmPy`OOIR>k zEod%Gavj)95?{K)Y-FXi zwI5L={xvx(pSCxgS|9DsEpwhoTCrK4Xtg;A2+0RZ>WM^7?)GIQR64rS+BK07Mn@IX zn1GZ4f;h0oGu5B#GD^Q;D)7(NmxK;BB%QscrB4C-pCD)YT8VrU*NCKDtrz22)#8?) z)_51Pm0JDhQ!vzMiIX)0FBWp0tQg~T)C9=>OmE9&7!GP%K!`Y(X*kZX(x&M?iKgdy zPyRWz*GaLM4d|gPQQWouC$UEQgDMJ-DoaMQE9^x~=e;n7e>Y_@HtHplrQwoH(|8tq zX?7dNFd3EEV;obTzTk%BG@rhPE*HA(j*&Ni@`jjJZs2@-t&sWd;FY!VePi*t zp#}$usOmBt#$3d(NxP0##(nQQ#+7H14w9^}NLQBXNj2$(B$;R?v7JyrEu@G}ZRph{ zSqrR43+7-K-vJU5SLQ9i%bR zsILtx4wI+1P7JvQvK-=_OE-w*=!UAn^rX!$<0+iRIk!<#Xy(6|=nDlnovQpV(+ulK z?_ps-%o`BYRgi#Rr*i9_Kef$B!Jx}8sG%`ZA&*fa9N1o~L1aR(Vu%|OxQH306^k4Z z;fPv>ZGIk}o2K2c&<`Nm>nu57S}rkNDmSY*o};IE7;JmkYd1cj0nbKd z*ObU(6I6tWHTXu;j{Lm}S=h(;vNLL)M;OUtCNwY=JUmeIGc&=W*{DI8{X$;d>G#P*kCs6YlL?vK zoIHa259_P0v*#q)`0Ds&^ueMd_%lC8LLU7{v^*GAlFoTYqF92)j8#X^{-KV(P_HWE zZQ{%a&Y#Q8{_0>CXU+3_p|*GezPkRN2cNBMMIyWN?^T`n8mj>gt7KSExnxQmz0tNF zr5*kQ2n9kJZzaY3NHSaEtraAH`%9rE9IAT_-vXuo85YJ8Erj5-G>?#vX+**{pkYzZ z=7n#RjzW3vV10(CFH2Nwc_drPJExj`DFGHXj@u^?5hy5SGMRz{sl}KQ!^bI)^fv*M zEZv}i)90W4=uzh2{$`FO^xd|y(F?>oJ$Zf+yTl1p?ofKf2$4tnlqbtfUqXMwLHt7Q zP+o#qvE`_5BCUl2a{LPZc&|ba>1%{Ns1?{&LS?%n-)fs!iX1Va?#bO_mzd-c2nz?MIx+yK}v0 z)?13hzk-NKa2+#@5=nwc_ z_tRzdTwy`e)ZZWn;4X>rX3gZyvbq@$*Vonl=rWJfAiS zo|-};UV!k!tyJzPx|$;D(5P&7PAXg$FUMJ5AG(h>Hqit^0BMKKhC@Eitd&^_$8-Rr zddPK4HlMFtKDc&Jg;q=~?5Vo)G1AfFb}h%vj&_g_-|6ks%#GK)!FRU{0#|p%-#qup z1qT@^o&e{*#2J@^Ds%w?M50JTw1X-`iO^O+NMZEvtR=K@EB|-bocGV)H->G6hnp1JB zb?dl>`{CsJcS{_34We%I3zAol_ZlK~2n|&l4>wSd6C76|hsyozAc-jkC3m5WmqDw5 zJmV#gpfe7bj__)@5+taUf|=;Xzi!#fm~3D=63Dnc`?|-7rz&kSG4@^&P4R$0LaX7- zJsDiOyUda82EuHg%c<4zjMV$k<@ml-M6AO8mr6S;;bLH+MA*aiqWLFlkrNdZtgu(x z8@ZXm;#$WPKq?RG=Zm$I&cBjF(zCcEEQahkDH=2)5x3-6md;_ma*!Zw^J2yX@s@ry zI0BTJM7W9zVur6)Euyc+hJ?y*UtKhEn`aqW~~ z8*O)S_m%vMXa*nXwFFSC%xaii+RYm~=P)D&7(x{=gU8h(s}qhd{Njl%@~h30Q1jyD zk2~uY)6(grU`yvWZtXIq4ay)>(GsN?z7JZVrs|*-m4#C;ybwD_VV+&8kc9~PQ7{A# zso28GCV}=`a8oCe+)TH&`t3%3HEOC?9DPEGuan3ahpv3BCbCa|t?>N+b2(u)s9SGJ z3@tQtj$>|p%h-4$EKX{*w6+5Iz>tof$wpUe!vVe zdAuSbAbP(E^-0s%G=e~G*Y5%Z-Pus2QuSv(8K@Zi|q6L2vh)Pu+lcMpP^15S?^p!34aph)0s;1RNM^0rc=QajqKQK_zWDI2tDD> z;bMZ8Ir5UbVkER@VVT-An{BNiJ(CxKW9T=%ID(_k6i6MF;?h zxJgdIrnqL4;Mky{xS$!pP5qYu5=E1*U*_zbcQxpag_6ee>s8*k3s+1?FET_KqCETn zdxwnq0^_K_PyxA`)cnxOeA99cQ08Fy=!143na^l|Y2|b79N>hoS@3S}2^7qsM&E3? z%7&uH!D6;KBXOac;0GlJ9KOq z*VP=g(A>N-26V_%X4Om2CUEoS?i4mDv*?eS^tjRiy!IA=M&}$vvmAqgUANnQIU#DEad|0 z?_12Y3b!1Tkx(hQq~@`erHPofs!E)I8L(D@Aa3pe#Cy;Z*yigCQ`YsZy8!$&XJN7V z(1-EWZm1%J4y@uA}BpkjKepm50 zBi?e~fFV$pjU55|;cQAX!`)uYTTTFV(S495WChQYKEVn~iqa7i#d3t_!(p&r_n=j) zpekEsL7|@6%*W9Un_<>O?>}E$ZI_EBYR>X!HWUlB)jrW?{g!TH^aGLUKy*qN3$ets zOhqw;2J{?AweezNS#!n=G})X(El=lDY-c8e-k1@$3P5Npi3I{U#_2#by^_7+HreTR zhz`RhKf)tN5YIs<-V#z>>{82VaZjL{S;};0lCUL}OiS;vZ0&AflGO zgr}k$oeiKr=V!W9^gBVTz*GP=*-CI? z=AS=<6znI)OX-kzNG_Q{^-a&~yytnZ?3+)`&d3qRtb?WQ*>H>4NFx(H>NokUsfnip zq2yLi&fZ@@qIsNO61z?!=fT({ts|WN=oO^i@G!{4oUQNGE$IO6Gkli&+(NHMRGTxY zrkC?2Rv9>hi4p2XG4GZtmtbw#`utNrMtyFmRVFv-=Iyoj@q{_Sz};(O-0Zaze!`@` z{To?Rb3`EVwt=x?(MQ)sd^#Y;fX_YbRVQOY>knb?&o_rz4Xvcr{Z-PmIU>tAkm|#r zFlQgY;aCIK#l3f0KP*@(hxr)xf;{pbE85biU-r+T70h{|X^dA+s2;P={|IJo81s1T2L z+PjIWHyM9r27COM>OXXNXGsWh;qmDaScL2gw-7~JwY>G2Pk6ulLu^e(ALyz7m!BDk5UM6ryl9>K%};Bfo*R`KDPjC+d@f zgP48#pzDlQXj>v)z@QEB`grD)2Zamnkaukmas2-G8;wOqKrx`{QFfH zdR(Ag6KR2<#%r>UD`|fwmXG`u#2}YRb$E-&0k!@(MNUW>IWtH1b!G5B@}$PNPWszm zrzJk)osSqHdCw8yO^n#q2WsMT*Z$jJT?H5$x$1S-5e5p0Wm608FC|NiE>z3EYGg6> zU|!?bXa$q46YwItXj}Wq!Nc+Kpu@arw!VI|UU-Z>ZU>FT!YBW~nRhfXueOa&f$;~- zAh_w%X3yUD_<$1aFp*CLr5Q@~b*CS$MV6A9L#4~p$h$)QT&Jxno2B;@u_TpuUJYL| z5`1;wkCAv`Y2tmrzt{F&@;9RI1W#JH7-GirZkxA_H+zIQu;mFp)@cw0F6GgF4@b!$ zRR-Jl48B?3UFHgup+aS}klh=XmI?-Eq=j2$^Lkoi2O^P0-8s~OQ9%vdGLycu_E=3* zESCNwegcsNe?ZR~5*1G0MZ1B?PF5ZeBxg$&IWVi2gZ$)beciH7=+j*H$mNKB#%yWTD$hr~$_PE&7tg6nwO5N0OaoNQeW+#Y#5S6_< zSt7VvVyosq^8(}MJ>8-dl2PHjaf47bfqxfw ztX|eQ^Ss+RBJroVnTk%+@mQq6w2wQ49fWPW!e+`2ka-X0$FpYWm_`AZuuyaY8s~jq zp~bkL3Lj$9i&0$J%uQf9;+$ta_$R`si)N3O=AlhUBp`!MlJrpAwK6QEQbbKSi&Hsr zOWy7^{d7pvHF^KEIOzeL9(-Eaes}?MsgXM;v>U|2a5BkL8kx(%c9oC5P^qHC<}U!K zMJ>lSkhkG=R^<>Ws6TVuXy%*$z7wbU1R}XgSyE6@jQU=pKgoBA4-92owu)(b>#I{3 z^m@TVFIP861j!l4FzLD*2V3r7lhxO^>J)m0cG1pCo^iCQns+tLIRO-e3R$&XWZ#4b z-R<8+z5$qPVnyOOP^1+;cl_;(xegz;u;MWoIp-LFGb??okUi_XiaA8NeCd?&iqxHS z53$s?$_gA5QE6#nif-SM?dw-Euzwfn?_|t8>v#~+|3pkOVuqG50qFMC`qJy3B(^EJe}K2I)7f$5AkeQg=|mx| z6Qh`nm!|&p++6)5#G+^_ib={ixzc2bH?kkAO5YKdBFmQ4;{dSZIEPnIPSwLZ zpj-n8p29{_dvq~yX#C*9c{xgKI~XaBK+t^LYY8#pC#g(H4y1_@&^!Yu-Z!#76x;$a zc|Tm(hYYX5&=NosV;dyA>W+YoHpR!s*tc4V?%BK`MkU~sC<3d8W{TYEeO8m|CfJ$} zVVw~9+2$qk(V)0h>d^zs~qNF*Wg36i9!3LR++zW0rV2QJk3d zgl_5M4n?P|TRle;AGpWxoZde8uHIiE!lGaT{0XU86hK#cBnH}fL{-_sWZvk|G9g!n zKG6m}b*ey^hwES0P>T+Q1}J6D01M@DU`4v+_`s!?@F)Dtl#0nvT1ou?=ZAVH;_+Pv zKZ1nWB z@d77{i1*h(=9Y8Y^n^X7t~hUTNx*8GnF1@X7@*CPQSd_5NWMrh{@?>PRYr+OynPVb zSZdOwv#m6wAbkM^-ax{a!J#bj$DU*lL{}I8Wu9mc6NoVE`MFmBh+WgdMdx^_{YaZq z!77he1(Q%+bg7-M1ES-V=lWjlsfqsuq%VOxx$nCc$ z`1M{dME6*DT)12^9`?4H65dLeSvIgNebH@27LpmPZcMeL3Fw5WIU-g2$0U5`y1`(cSgeE(Qzhpo?T)5u5K_ z7mA?j8p8ZPRJ&Q zvnD&30%{)**?X1LhtOS{MK zFl3FuDvm!iu(UsMR=%64*%?`UrItY8N%0qOPKS9IRtmVmrU*kF8>~64Qx9s}gY&ZxnTPI>ge0i_ zAx&L2ojXEjMEy@f)->FtRqEbs5gdU;x&th26l#oaf$RSm25$<-EkC=Fx^yAaOfs(u zRlV`Zb_1f1uoM{dNwd-~?CZIGVYbj=bF6{0z9v>O_+cr_sLmVyu*V zaqYHq`gQ#oTU_EKbGE3L2x9TaBik=RQ`MRV{@Hn*z zY@3NCedER%{?<`u(l~MOcA`4LB25%~cpk+aAkzBPk_vDEtK^s6m_A_A6fo2-hI*D^bOSN3k>2efc=%8q!7^mjeJtT!F-eF2${# z-#u@kN|ukdVUB2YKh3NuoCXstDx}rqTTPJefoFNH0vpay-a6?0Ugq|k;HO_e`%9Uy zaF*+FtPW@8E%({)%uB2rJk@>{NC;Er=R9CWF(F%G-BblAiZ4qvUO-HT;>8o3uT}CO zHsO#km)`7#MPCnv*t6Q~B<2gzvv1jua}MOpD$L=%p${-YAn(+K||0-8X&dp;y1&S=`l%bWeYLi)V9=xyJ1gWW9*2GGxw8;Aqmw_ z)wb=V;O9JM-Fi#okpe1`h1oNp-0`-l^!fGhE@YWg|Jg6=Tk!x(le`kjXm~QJ4NJDm zirumnxH9;zsm%RMv5Fv@EIN39w+*uRT3;S(8(RLT$T5&-i(cw$I{r9Nd+o2}O-;9Z zoU%i?MSv`q;AbPvp;%nDaHr*SbaBbbo!Mx}8GT(he~RUGm$jJ2;aYza_4CyCgDSK2 z)*Za{{~|_LNRs(JvFbPEay}fwu^6I1SBlp|*}KI_Hp5nF{z0VrenK8k#MCC=tv}w@V9Mj%-AW@~r9|8|-_ zEy>!6&~-bYG1W0-EPawV41AxI;P$G+HV8O}lnp?EjW=9zy@25qbU+_B@{!{&6J{J8 zCU@8dB^e8ar{)8J4|#(=-ZXY+`hUf?u2;sNv{wQl!@ApPphA{DBigK`*Vf0G^_# zvymjA1P!UOI4WiSJAWe!G&MZ+{!FKQLx3I+!*9X^^aH?&i)5DtPs#9cdi_9~p$zi!(BH;DTX5my4w9j=6ZB?+0MmFC5QeqNo4} z{qvG5q~J93sN_``)3&Z8l({LfeYbre#LYSAJJl-nN{lUSR2ITlpvgNoSVuP-wOd7i zOpM8dspPKo^A14=DIm}fGqLCkzf`C! z+ja?{yOm~4c@gf2@lT2llGrfOA<@F_`}x}p$7_JE;Tm7;08BfDyutX#aFVu9Z6=B+ zBtibQXmZ_3#F0qPTf=>BT&~ikZ(# zA1Ssu0lLkaV3fzqXn|o_WA1CJpy~hw?#F{B@!mJXJ$Eo8R!{cPd&vWQ1gDNxSt;(C z+5I2rPVh1)jNFO1opm7l{|!fzxkA^rhDwfm&gGwHrf)myk4}7K{4<0OXOE9t&}m1; zDGi|jTJOSb<{+~Yu%6(Fk5ws5hd*r5mgD?mi`M>LvI{)364TwzTlwg_YeUn?Lx`?uj|#5IpnwduE+%;+U_sB_h*u}w8t+V9q8>9+D z9G4QAy4P@_Eqh;wz6<0N7Oco; zi`&f93!qU^XORPYcWWmJ(MM@bXmgWEAZ!u?Mw-C@WTE?7-fC)LN+yV^fr<5u# zS1eE1-M5EpFIFOt#Xu!CqJ%z4BqcS{3dbcxvyvc(ww`H5#dGKOOQh;8U%P3#s&cRz z!w}kv`O%p)bq`)CaXV6vjl&h+L7^|ktn~Z;Ok;F!PpBhE@*S{#Zz-;G&N2O)Wy9xt zrw#ot?yX|HGXwp5X6*v!`87gBm?#WrQJ%huZ=)1rzNCU@tX}+FbaPB%>jJv>5X)!7 ztN;kV_Yw^uDAzl!B~Vvc5?=A(@PzKbJ#SwkyvggOC#j0NonY7Oo`z%IL5yO+B3+FA zXH6hD!jFu&`%1fq8ceE+21XoHRE` z2@)nyzF?@-!SKS*S?0S|xBeuy$Xu^k|3t+hxRWZj+fp@N^#yZved{2Vept=ruAYm7 z$+ER-0crJMV%sBU#C8PG2}4~-BV!5HDSD;QW6L~2|DLwq#C^W+sP_}U3^&j=M-}3aUOz3= zdVbvkTQ;ZGL9b-MKki6#B7YPsxrtcW6@Acack3>)u$KGERM5_g&e{~Lh2f6gLeCz= z0`+7ndM{5nOrRHbM_BndLAuhs7H+pA*=n7Rx!cuI|^vn9{y^g;|z z=BGkSk1mkHNO=NUu!Y;IXb%naw5WgGBt?$RH94J`%pjnk41<^SHlV{Ei_jGIuwlMxcZVe0L#0Az*EnWG|lfZ)2Ic& z*W7u!l{14obVn!?cWL?=ZxhS$STx6m^r#TT>A7BIa?;+gc(aTvSzebHYLKE5e7Q5z z=#g(U^Wh!f4s&5HOyV`ms_M!mqyt!%mU>3vIjOL%c@U@%u;4Y?5{OO)hPwWn6~<`M>}tWK%!G#Rr{~A}L5S^Bq87x8_nu5}dH?1yMkY7JQ~F zt=gadh-*UP6<0MgVjf=04xb>YKNC~^Zx_50w!wI8EwF&o-vcska5LYN?(Bnr-YW_q zl}PqQQEy2dH3)*v^>S|*XurY4OX~}S4(XXy{&BdDpSgAa`9=ZD67V?XtG(qvfeLp% zC`t)Ba#Ig?ZI6#|O$j{ez&a)yuH=7>iy)^@%pSYW1v^OK@P!7J%cZ;GKsWbyi+ue@ zvvb?kjeUi@!{DDxEmywhUPTEg4VJ{=x}DOEg0 zEp;qad;AG!ihb%r!11D}$FvIx*O9 z)As4BzjCNbz0P|3@$6dgUEwzAZ&_-#(-K?kkR9+KG5yymibm`}Lz)`u%F!ksUmvfz z3z&R-*;CK(m3aNkICn$RL>U%ur&0M<zBtyuM07qEf3`@G^=GilwVnkkY0E6P%0D)J;JB+R}& z6;%)~tU~D{;pnkwefLqcpJt3ZU&w<$F9+EdJQ#B3l$+rG#_v%EvtLR$a|SHb7rY&3 z*VeQ_;wK;o$i+LcUrwr12zfL+E7(814e_oWSh;MBr<1NSa+P&pxVqghu1 z3Y$OrSoG&ym>~Cp_n^U>yni;@97SWCm|t!PTzRG2>EVR;hr&{Sa^*VNds%p+$UlPtS(7p+&{ch&;8XRBg1ZV4d(xlVsu<*>VsbJl|GN$6ns<<=C?7EAW;Msg{k7DV53aJiODVfyhCy`9*{BjcevvWB!BSVfYr zZ8@G-+Kp;hsprD9Ht2sX;CF& zyjTnGg|7#`b^f;X3{_p5z-8)4(nR#KopT`Ei5@F8skpfD2Bfz|IMX8_GNR^th9fWF zs`^B;**b)lg4d!aeLx=S_TPEfsN7j#Ha)ulhsm|>uO-D!JhiHiK!J$@HBs_d)fsr> z5&hsY%TA>ZhouYRr?PPrIgX{-vD(=KIDPChKz-CW1Z)K+x&(FxqXfE%n$@P@Z@m!P z;~Sye9P7g`$8bWZtj5uu+Prz=K7Ng%mJ=6@DqsEz`IE>jai2yHe!R(gTeiz6B{NgA zvtvQI8*+IJeS0~Eeo2bCu?Zn<0>PrD;7nG70#Zp6c`#=UIq%+|+=DSFOZ~$|Rc+xG ztOum>@B}!R*EFketXPbQJg*F>cc9e7yH;c1k!p^4Q_ z4Q>fo#!T7#T?1VYb`ohhFk6{8g{W}929Q%wkE7;(FU{SsSNLWAs_s-y=~22w*t{J) z{nbFDM^w@k*|1R9hk0t2JAxkf%e1qnV?G&Z{)Kq2=u{l9EV&7ID>3Uj<#S6aG0dvy zF%C>+wf1)Z!6!ZgLHZfg#{J|tW&3zjsmQG7zq5+?V;U8rNjz?s$`X~U{1nK~r}VD2 z1Gj%a`q4if^B!-lI-ql`gRT~Ei~RJGgTFHAl4(0~*g$hE^YOq{$1I4n zoK37Juyy`57)WZ%D}TC?%173!CA0Za;;d{m0?LE*l61ePueR$3?EWRYHyhsRBc zS&r2ZVhz7nHbT=8Ht0<=VGXwR+T`ll5T?(N@i7vHj`j_N~T7K&Z5@gs4NcSe9CX8n1f%IYKVFpqMHJ)B&xu)O_V$r^ z0rCma3;%h3jVhN%w<4MAmrbw~?L=toij2?_-mmbr4Qat-CvFv~y1LQka+;#m?CKEL zShFcOKjQ{JDfqjd6)}NVE&iwC<7pf%_0logeh90JB1!D!KoXi_~-L6i+_?+ul=T z@@o{JhaNcuYPyn$dW79V708paP}Ybgyg~9+c?6EUJ6tz}CvjI=X!+Cb`KB3Jpjp(Va1XU)xF(?nwaE8op)BE!`3I!naFw>B+v*T0~j!$Yjde z$H&mn{n|kcp9{=;9IT>3eeSqe2h&27<;)wO71Nem-i^_B}BMR23XCt01gh#T@)&2B{8{;qJk<6a#H)9nA z5M^NH%ia&Q*Uwr2%>u6%#O=1~w6_g~q`uqV-n}u3rSIB2f*K_X%|(L75lSVXN#tgT z=KsY^npvS73gT29;$4_n{rerjdq_oPk0?2^=b#uhzwEi#r=j_D^A4a!jf}C9z*;Tq zzkl}Ye)v&lc-&XBfq(|p1Y((LcVjzja|vt@D9TQzaCJXB{m6@nu*CW zgdstFnsW9^Sih31X(A%SIcJPA{ufm!!Ce2CO=CI-s=-1h&Jthgp|O__2YhNV#WfmQ zq7FjyXOxuY)d9epyD_mZSfi0jgdqMyAYkJ>vz*s14)F$uRqZEKve2^jKakd0U3qPC z!@))SWv{FrC_kLZvgK4RTQ%{*f2PuHn1!FC7#keKIJGJeh6e1LA!kDJBEt7!j5Cqt zW=zR5#`T{gg($Q|2}j#?`F6~R z4kNM_JSJ$21UhRPT<}87U;BRgym1`gv|HhUCkQN}VoD3b7@~3U3_W4Ki4kkkDbGfl z+I3UnhyEDke2bYPAO4gdfC|}0gp$-OBD_#c+#!ZZ-pUuuV^1!x$ywNx>TD51Q5I6Z zdQx7Hi>=@_-#;aMO_+IaH+J=O+xZSwX|?072E;Df2EX>6f@^l^;)WW;0qY3XGom5P_oW%ZLl+HgrN0Zgfn zr#Q1=W%x|R4en~?eJjY2tP=sbE|qLhKpE+;SxM~EE&2-VqB&kXPmBC z*wFP$ckCGWj9jmW7Kh6eCSNzFX2C*S7UNPEr-T)s#{;Mtxj%WNo{2=AmQ~+@a1&I9 zk0KvcgDQs4-}ftf{2;J4RN9KY2>z|Ng$J)N`D{t=Zzrw_AuX?3P6*2OVhB&5nA1Sf z3BDcfjhWPz&sVmM#Pfc`PJ%GaKYfEZo5=>w>so(Sx!PtI)yaK&`m zGU`a79A&Q~Zu34{tT7;*R(=^pkg!O0?qCQiz2XV}h-SFa3=o|mg7{qnkFebUN8;gOMBx0koXW;mlvq;`}o6_=&z0*b0X8GEPkeeJPxnG+}04-Y*rxXf+#-$+D!@*w7ved>#~g~ z`U{o!f)&6i0@a^_APk2c*7`FNA`6?X(QsizPTQdTrWb1m8zEW{N)6D##}$$+%2N}N zqvi?~uFPXxMS!R&I4lyOFNNo-sT1m(3v?9PFi_PXttGz4Lx!s7(hyAMDH~=cZTE=z z0hAq;H16STEtT*r$h6>H3g=gJCj3}Sq)Q(m`>0E;v5wE z*D|lSgMF#pxKo-gA;?DhDsmP65LA+T;W2}%%#Y5^)3PfpB)Vf>*xejvuein1f~+cg zos}Y}QtF{TFl=1MEKm&!{$ac8FJ_JN%W|K@P_A>cIScu!igJ2Xn*3IKgZjYJQ^>2d=bzg=r_KB*;nc=Gzf*kf)->H^# zp81+ZnK(yx))dEEF98#Z7<5XV;I7L40ITl$DO@c{nI)4p(~Q}*1}PNy`$149Jqj*pi|~HTJyH%FYr*hq z{(PrPCm>Q{v2toOF0l61VvA@6L*Xk};$g_=Lu6-`GdaJ}w+L8~ujP6OH`?F) z&pN;o)#hLvZt8xQMX^?;(rtOu* zc3^imfL6aj49M&3XKjCv10-qjQ;FLnxytGLlzGlFxwOlCP{Brp8ZRL+&zGWS;iYx$ z-U(2Ns&#z}GQ)3ktC;gGeycLjYU))3g1b}hpNkxERLSUlaic-&hjj_)A&F|%(4y@; zGl({^ui*3T(Y@fK;xPx^6)x$pIw08P1Qc*@0I+kT6@4F^tLgMc+2T)d6yIPwIcErN z2;m1=$uF~tJ31&R*?7adLB+&{L<*pB15HxA-vn9aed^!D)*_2e3j-#Tx}lY(SMTIV zH5PZ~scf}Whxk$6s6IQf_(`kkEoI{Wqrdn(@I(3AeXLwwRboevt|4rdnhz6+V0ND8 z%OAr9I!OIyR*~D&ET6k}xovcIDtW+bJqCT`7hP#!MV6mz2(b}FA-0k;I)RJ!@(gim z*PXsmw;`%3y=p&`h)u<$FhTP&a@Q?F_9=x@JO~1m^9y1P_RvJJ{t-vu ztFY)YJNDXaU(3nBA|UFJorc=DNGIKw#_4|9Y_vF;WOKZr8Qr`Eaw?fLVHgzh-4;dz zNF*@Sg>B9p)mpn`ftpsm#_9Ne$0($6w{XHp)~7X6-T%8#Y$-}wSZ^I=xR9vL{*I>8 zq1i1!&(vnjEI2_1jLq0{$@I*vZG-pvD)6R3NmOyxvWH7TQ{RC2P%z@AzD?(80<}-X zU1gc)y*mQ`=|d_p3;p$ikt1YQQZFLZj+3@!qJVK02?rh$^+O0>2enjar*5p@Klb4U zeKLYcxrfN-clxV~m2N~cb{RaJV!+lMqcnS?(PA%!sYKbyd59}J2ccvmTh*P=N8>L2 zGEo>~Akt$ zT}-GZ|LCCU6dIv{jEipOU=6o=A{(``Ifolz4+a!9ecQB(K87R7-iOUOWG2k}>0W==0q=5-BhRW8@9(nC+n2 z5!sZ(jFIHe*Y9dF*r>6qU22bOl-JM!_~}OPz(dNqQAglQSe z@GCv?Htnye?p`%#S*Z0R#g=`4`$ULaKm?>i*2Inh%Rq?AnU;gH0d)(R<4q_8KKOf8 zNFv>bB7s6-$vRCs++uJ$7H^z?FTa1-;HpIO{vj4x<4m1BEIXhM4AD2~x^RX`>F967 zuTK$Qj%yF4eiXBvJB z%747l0X)ERDH#p_oY;H^(^vRZ2Fk*K^R$ULM0bIl7`#g?-oxxYx|gXVblDFehO(R! z(O_TC+y8YCH`f^Er+FD-tJOfJAZ72|(Zf07xM(`*W}v9mn}lez$X_>C%8jRrIo!Y( zo!;1R35J@7_HzoB+hSIrpH7?ree$Yl-X7M^ichYE7mCIqop#u$0=bPiKq_iw5R&>S<~k zlly5?7u>CZerXbi8y6NsT|NS1oq*F0$~dmk9(zNJzrl=hTjd-dDx+y~#TGO($PH!m zJ|WmKO}^zv6pBwh$Q6OnW1LX9Z91?MR#MEXM0P)v61p9UCFKI(O8hYJBih?=GoALZ7d{C|3SS!9 z{BT2ZGb%;*i2>y++!s@^^u50mqx(PzZEy6ssU!+^Zk9oCvx=rev%&>c{^ddjXr~&2W zgf>@F5#nYSi4RqPxZkC^I>eC$c5PRIsT+|tC5PaMyxMAAB4x{)dlI4^i=)a~d^U4o zT84exg^RB`!F+^*DcZYNsWC$^J;2>=^>pw~9DS#P@p1FLo@KU-^CQ=&8hts$9s#0* z2>T-Gj9Mq|9cmP7wJ8|fu36Z6(7(Xw80=B05cJ!7o*0y?-zuZ*_^F(S?gs{v8H#|M z$d^QbNaghKh^g^;e)vMko8-#8>*3Dw*36j%_zn{^vT%Or8^QPzyasG-lK#YM>H?SC z0i5WD5NM9bg+l!?Z>b=91e9fR!5TMIOFL2I)Y2{kJUrtfesuwJ;6DB@4Xn>kSKu*K z=j?3q(uoUvg<>aL1pB&{VOQDr>u%f9AbJGVyWlN{1dmdq1^V;)^=brM1^YlRZ6i3& zIlF}utt8$Z{@q5V7#MwwgYiorjl_3<8m8@ia*36{T1+xq#fB-6GxCdz=;**&n`?nq zWhVBm6_n=XpFxAe(hX~)FRub?LEPfd=cm*{n_+NFK9lA!vJ`1)sZMyN@p$$+O)zGy zK_6nLr)t&zE5429^fKB*&6-(y|oYA7*)Z*#cz*2v^y(03-lW)4iGiJobXhbWi_V7P|2( zvO-D&&;Of)5f1x#LkTKHi}(B>F*Z97jg~^0nLwX&S@bm1G!??~Wu>kTA;?uXy)ynb zvZO2~l9atJQNs-{u;wNcE<+qMUj(9C!B~rD|KKe7$EqDCj0y9Mt4`}wuH?EAiL+gQ zlGbFAWfIjkf)kHHSgR~O)6rZOnPnCHJ*AGCN59W&%FP&D4dAz@R=P9S!oy4w2&~Zs z=q3F@A^HMw*;uB+XNQvIszvbBUxM4AC~QE8pp_=YIGxn4d7FYSSAefr3TfdvUwbnB z*<7}9pcMKm_Jj;(t_ILML84cfof=XH9L#+1Qtn%zjJ(ACoj>oTbBYG4YYF3WFu2(Q z@|NMy=g#YFfp5WJ3?xNWKM#R@DbXa_kj(x9+ReECVq+Y^~r4K*r7EuQ#k zOB#@2x6fPrc9hTCOGhgj1LqN2?wJ#;RoQmAk)`1^g}p&Fu`cO{Zhgmo{3~ES6f(0i zW{inE0<{Az66|fER6E(L7L7TplS6@+4X!;Gy8e`VjG*KQ=xA)L^SZzogV*60xA}a! zjZZA}((OtRqIj&MTd|sbu2NnRlAQo!4F}%W^1ifgXjgE=MM`-W%#~b8O)r6^(eR4` z-R+e5i!X|pEP1=9Hop_~TkLTB8#m$)k)~QKvCsr`XUF0UL&u)r300%&oqUPElN?9BfJo;2Y ze8bZl9QZT42S^i;NyC1{$wtRge~bgY-g3d4N{JYF1ct?RVcitqFVL6r)t}s%_ZEl$ ze;Ngf{JWqBxi_Dw_ZXoioG2}~pVeJAduEHd{|aa}xl8M=Mj#i(eNCv6rbmT-0_5b8z#5;rDFcd@zoRoM$O#1)0zf`ebe0vJ{#%u zq|0pXUh3bvhZOR3UXSSvQ>__Z6cCrv>x=&XQtbjUFyUw-Wpx_&d_6{H0Op$n);eb6 z?@{@1^{?>u8-@G49w1IMgoaG5>};9;2Li1o(%d28XsR+i-qNj4V*XwH|GGiKUi{)( z6Ng^ec}5Fq&$Sh^63~@Xra|)FjK9y<&j=ai{0^%kn2hTn2EJVR=4iWn(@d*IjbtGB zZ%f)GfERIB|8{8$ZVD`}KjZT~6S6Tuw2~Dp2u@v4y-*~|ZdEbWD^BuS`ko#_pSn$y zyl{apk7Xyc9lbpfNbHhl)9YQQh)JVZ)*>0WMvm+Xcq*bPF88lnI*9jTKL~^)852+O zI7gxb)ED{>KR^KN{xUQB=8`W>eAGbrT~?tK5$lhTG_Pq?QIstaa+d>5MNnp&7MvHn zO^jkAs^ZhX;+z3f$K+T-x$Qid?2}pM5s6c|Kblj`y2s#7kMsc3>2qO>{C{ZU6;=bX znU~wuDIyn(vlc@uZgEn4q~3!2-1Qp56iD~~-=9Sa$z;Ha&t3FnWeG;N*yAEzh!t!w z*nWS)eg4dy6Y(dxn?C*M{AC{U$rhyD?CArIG0S?zTb5ndOV&t*>6M?U1LekVg`lbq zbHuJ~%rn-4BZ{NH4Rj^arH-hsv+0Fi-lVW8uys~q=l2fRj|J->Cx3yKTm;}$WKH*E zMzX|s(RLyS;+V$gs59R7EqoMiuEZ~ve?4f!K`v>Z2)~ZIq!vzpokP-U%V`EndwYJ> zJ&HEXDsE_Rm$8*5#>dcUw%cg1*>~TFQ>Pz`N{}!zUCoqaPO(mN6&!z3@ z*q^%@#i<{u#uOuclsb#jR=p+^S0MxUttKdLm2`rHFdRZ#F=Vw1h!3a=6VZf?sGyy? z1}u?R5m&hBuE11+V@VN%Cex2TPmU~Q4RKiAmw}R?nJG*vb^k>{%q;+Z^({9VEAMq% z%HNL#34RDGFFx~9)8bC}5kCe7 zL@s(d9om+ian>r80&B<~xPiKm2-gWvfzcWas(kDo(NG8!RWJ}AxPu$9yh{Jzru!p^ znxOdgQ0_QghMQ-Din3&t+~39Ul$qRjc%hEJl8c!@x2sK;a{XN=04%BSYXgv<<8N^j zVUjzB&x;cElp^~XVO*(8re>G9rHM|y4$U0yOiA;y0QScx1VwazXhLx_5rtB zr(V!iVT=DSNlG;q5pt;cwmt}Fu=7crm;#XlQhw{lpPMhqPmhBDywHKm>baGV{-oUC z%KAQy`f6xB3bwq7a&!;lGAIA>_&%#7g9IXtZi>(v!dUgxm}i(2PZ$J)38A-Zf6}C&qjO0^X~Lt_m#afqY)YD)=wGqTZLrU+f8$ zOvS}AM!B7q1JLR+GDQ6Ix`=qEFm+$_IwDmv^l2MH#$WwSLgt*^>Ubj7U&ND=jlA$a zxC+UAymLq?&MwrGgy@a@(Y5ixC??j_5*x5xUMcRQ6f^O4Q2qZ$jBwhG&~YRYC?LC% zCJdws4XyPj4cUh#CXs0qU}SF5cfMt#rA(tWLR>snIC#7pMumRnDcG)~S~(XH&0pT? ziN&89&kE^iF4ET&H|>9gUd$HA&1VQO7P5vT*$nrG_cc-VP>}Zn=<@svJ#poxcvwTs zdgxtxlS}DZ31mj6WYkD9RDkT2)MV9ukoI(zDTEQ8ez$JWS1!S3m2Rd)IBv;xl1Up(hic{%WGm})0&uquOk zDA+PtdeJyOR7Y@~s2upLv+zX!8>-%@1H3`}E#Uy3F#}xn7;Dq| zEHj3k4fr>~3l^0*32)6AgUoP5-%K*xDLu|6WQcFJ61`js>@2@*^E--)=wo}=Hgu6f zjh`=Ju+~R|aBkL|i)9#TR?lNq2;0&~$;;U|SwDv#@=xT!6Q7Xlj9SH?^Bv(86SBf; zNI&$J&*o`vC7I$tlZFkmAmld13wY1W)*sOg6!_GD=~#F)l>@N`is6Pnq4oQr&3k^n z$iHRxkW1vTZHKlOzVJ@H-k?U@$6UCz59&3Ob`dl(u{#~N1@!inM?}nmaaO$C0Vg*k zgBj4wr>5nlYUJ;@A8S>)i$HZKAc^iLr)tRsgg;Tzwez0+@klptGH8BSGoUspvu8U1 z3<*EQgx{iEU6!pMIprE~&twdaERzrGLE|A~llS}aA&jdMxtM;}Wx1SR9YS=14q|0h zTkA+DIVX3Ouv1T-&&!DPXDzkY&V&^$=NN(Tj*cow3(?_?q}?UY;aOyakr@G7eAO>yt`hy~DDjBRsgE>hk; z$_2-2YOrrCfbq$pqhza%MLUAINYLz$K3Aw|t=PqlLMF6j8T-?y6dHt&HVtYDJ?)=g zG|X_D&1e2fFtRHE2?G-%mW8~hZ;;&25D%{|leK>MSc!yZrzyx!NB7A+X)AkU5^um?vL6ULxWhAlT4vz!SU&j<%qo z$o$Tq$CajDPY*j`d7sI>;)zMWelmDO;pufK4ho20^+Gdh7hC2HoP*q%;w?tIqjscT z3~MK>=1P3aRY5|tWGB5jl#MWxP=``)@#?-j(e+ERNQJl^D}9M;9uVY11jN7dO<952 z11m%u3%?<+m8%84BbW(Gaai6xtJ#Qm{(~OeSq367Tb*utYEqblx+zQdDjp-gDsyji zXPihyB%aM~zBRS2FR>2C@(TrqK};kjJH;AJLZb7P@96EP%^r4>k=&jpWC`)!RJPMr z&OvEdvN_|?ZZ|>5>Red)eQPD;yY2otkM+4~Kq=N`zg7NhjXamTPY~|*C95(OpnZ>! zF$py_pVE#^ssnaE50n+9_r0ohVGyDe1mSgN1;OpDq`4haa7GaVCjPK2T}Nv*?~T!m zV{R*JAKXXjO!W5GtIIkXy8g_Ne06N~aB2RP%aynFZxr*@p#vKXU?;-!riH9j;g?KV z!2PuAI}juJe+V13V}Zxm(1d`0TIkP3mKu%+21~w8gdfVpSgZwZ6H+p1o)x-Lhjr=m z64N7hKjGobzCbxVUO>}dTP@I2{`u56Uu zRpqYP%^iFg1WE%JtM(aZlap zw+;l-!^5?QAleHNisnLbHK%bP6TI_HbGFM*?yi1`RhxNAj{nhvTJ$cCv3MfRipdki z9JM3C5$X?QhU5jSTQSRU-tu{~i^rf$Lt^s66-8)N9oE(14Zx zn0kgY3Ksso#zAiLS&>RYrRgZw_7eZ%~EK?Jz)dIS%J33@(&>Inv7ZQ(7C2 z4`XW~dq3rs-Ldv4EuK5UsPwA%t|{4eOF6(2cQ>pEdqjTp-~CmfmHnEx=+Kl*%%dQs;7dW#;T;vl^P%? zf1XD=NH_kZZVT8nVvHTmXn9zzC+Qgaknns12Qq4<3P)bKq1h%s-6cjX-B~$yjh!eJ zb+vRnS~S33QWyCg_fW)PZD(WQW z_aM9Mm{T=KAm~&@x(2ALgs}ZV@s~EKwB)wn0v%k%^u>l6s}$#wFwc+|Lto9*jy54Ydr`Ti>O($% zvfk=D0Jo2$a8;Z$nV`jA6J)xSafp}5l6?li>ApP4Ck6GTnP;3RgR#{OTu(ikl)fPg zzS#;3e((uL?E0`|ED~KZ{M$P&jA$Z(g*}%v>pc+GL8^K1=;0CZx^r~JMdF5&H!7Ti z>MTGs5f1hhKu|3*Fr(oV0$p}?{#+8dvl&8D}f?08<(=!_4F(KlFkP4n6TY`t<*+st1 zNf$ZoGZ;h=E>Db-(YL)Y*xU%IQP~@MeKPaE>C#02Y~#&03Ph-N|7@n3SV(wFyLufkKl%JWNNf@0M7zE|g65i<{$)_Jd)r1UPg2V_W|io$9S!-S9kJ;Qgz6j-Ll=Eml+i10f0E&YHRc~CjV!{~sRHw(KBnaZqDFHe?QUK93 zSuHCKLAv*4_Y1##2 zIotu_|Hsk&L3(`UVQ~R0yx)K=^;Y&W3=aeK)7LG za7{O8L#FLl0)WY2aG%P1g05Dw8~emtF7(H(UgQI0qRTvkY15h2>$e&!gN{cCfD|EV zAu;D^*hj2mX^}`RvZvqlvuUVg1wAvfw&gC1-8~Y8IRgU&NAIqzw9Doi2Z*3f{NT5> zmUGOFn=wr_5%IY%83?r@=P?bd{vq26ab>*(zVhZ+WGBhBAG3?)5>idfrpOvlibBsxKMe z+;C%3UvzW|fDRM1@OHa2rBd)H9rbIAY-;YT4PW~5>!w8QJe&fR7VDuai z(zn5^ULJHMFHSo|lOdqcFHKazD0M$Zu=`>ueK*yEyPBvq{=laW4Q<#g**k{?4a zI~2M~fn1$G&|$Dlbk}*KB>y2*6hOM57<5+IUI9wgJz3aXH@%Y!te9J#N6dR~DT}~i z56lMO4AGs4p7rqyY&(~z5J^GJTQf-gtuWrgkSE&u7%wtSlAyu^f4l8&jHMrQapg$V z{2le#liqp>k!1v7cO~G|R@-xJZF$M3_EFvyFwt5Sfl7@{8wRn&)Q*2&0IS~IT%NWb z00UU*sMUGFNrTDzNJ!jD2VC67csbAn2q<x%=|pBtWE4Nup_Aq0^5A_aM^8gU0D6i1K@W$dC6x=XaEGaJ+w5UHe_9< z$sT;;|5=pId-T!@K&`@=1h?2=4}sfkfIdHJ5vwN!MaNjhUbDjHt~|n zUiM#g(EQ3=pKmp1xA5!aj4RLHkiA1aHQgS>l}77c3M_2Of?{MoM@Nn3klSU|U*RLF z_zTiG#!Ui3=04c|89DAiLk;69V{_S5P9;lmb;MI0+?xMtD||NChsOs7z{QlCzJ11&PoD+dN*+(Aay!r zuFyUPO*Cd6)hLQ@g~@ZK05nU?jtH`>)>flDgh=Nc=17eMMkMAM(G(04eDN5~j0@a) z6jbS(+0|BDhV#0;u)lM--Wn@BQfgCgxaQlDRx_r?*ty0C)|Tv#4q*BcZ*yA`^S#Z1 z^G~d<0V>Vm^o1m=>^2f(X%V}ILIAQ!TyH!9<*Q4tRmIeGe9o1h_YjFcv%CdS+<`by z%?{D`D*Blq+|j&S1sAow3%Xkd5mw%~xw#m-jK*mZT6p;0?fWSzVJVg_!ujM@IK+9j zmvX$>y_Ci=@T|poqAaU`c74kyrq1`!95Pvj;OZ=)E%4de-1tLPMg32M2#Dus$1&s{ zz{4i!9Ch{hMn;*k9^Cj#Cy%#h5Z&l+hXfUgO%?O)h6(%dbByl zsGy!C`A)@tiVYb9yJBEgaxyxI6~wO$9>chddJkvPli3U0s`YQ7W+QmPI*fh^dn2^y zIPqSbNQLF=F;p?*7YS|z8&QAt3V|ec9wu}q+-`-)v;8ASnQNU`-;D~+guB&T?531RU`BYdy%VfR(DL*BBOyW8k z&UAmX(Rr3khA$pOtV2clNJQlG$Qn$rq{{CvQTe0TeFeE=AeNE#d0+~*g!aihc>4M& z6i31nWMf~b^P#VP^r6I6JF&dx0$?+RTU9OOx86| zJ_`qQQ{ghb>$7{zgx-g=zK0!-CPw1veO*)O#nC0z%f+pA5VNvN1fBZVFlYlfz~{+ENi2}StG*SG%ig2YJ8kz$o82wEhq5zF7+p9d4Dar z$$9Ao?$R6A#xp+zgwWqs+!gGT6xuOQh&jE8aIvl0W+K(7F{9HTL!CD>kTi1I;CY^T_q;|sjY7p@=* zxgyMAwpIt~T9-wXY=N{3p7@Oj>m_$fsutbeDE0S+w4^4?LbRU15a8O&tU&toC`kv-k z5#CfwpoX?9PK$ME=2G%S*HhrWE4mRes}s5jyqi7-x=CVR020$ZhHq(rjZRaLrdy^7}e8tw;ElF7Kf@pC7} z)~6TDjo*4$GK?&bW}5aeOjE@o_`1Hh?bb24`l_2x&pNC2vbZf0f01cWTBlh&aXzX` zn;98FGD4`mbFNIaKZKMUH&<2F_H{EAliQo~!%kPE-{3POp;#HVzJ%h@7OUSqg32BT z6C7{nS$F|7ba$*V++IVng+3ieJVlov5X{XHUtiJ5Pj4q|xA$Jb0_PpTR9t_6g!H=! z1-QC4P{JjlB&c&T^mWek2N@qTAx+trmXsynR7Er87iI$2d-^*0HPC2vinW_vbz2_B>j*Z=k5F2=E& zIZA!F529N2YlWzCuqSsHA?D1bhv1Z%D-2{owc zmf?-Bs? zIb7oECJOWQok=s!upHi@f``QHG!#LYMj^PU^q*r|?B&=sc3cf5O1S;@e)`V@V#5#r zRQZ)tz)i)AzW{LiUqdsB+MrD0v;8vp3lAkep5cR)Vj_HjW(T;hovmr}8%PW!PiQXy zUUsa}L-uii2Y1U*ZpJ zJ{c!Fy8Xa*1AI%NI6IQ0jEXwf+Or2TVZbJQUK`J4?>z`Y+rbt69>fU=yX5_xkS)+< z)as36T^T&^L9O(1JjbIgy|thY1ZlYY;wa{S#BAfAHBcTVZE)8_n4*cEzNndf9eVHM ztqthX1}68a`jn|?Sr;5oJxp*kz@>j@!C7%=x{)F*OlN4oujnynHXH4kq;G1Gtv#6t z%jb`1=VotMoMi`h@4-|ZoGBWc3X}Ox;wZO7HCTU>+175WOeq)zI2AWzn`Ob*ck6;%|LXcW*k&{O8`?v%1gA)@LSJ`R zJZ~pZ;5G!_1q1A&Jc0+)(>6-Hg>AMMZ-qn%-vGY;b@f!J>7G3#O9PQ7K$2>iA`3J2 z4JPJ?DAoX%sD+b&Z#-#~Zdhtz;TyrhUcuiH8Lgu69fm~uR9@(()Qw141ylL7l|E+@ zgZUOO9;}$N78z<~AFd%incV+PEXH(JUh%gKZ!>t$1M!j5$DS8d;=0-?&>6`PC~oNW z7JcF@!asYhsU-#&a=SFKKd7UwSIMu{PZftBUYW!aaND~-H^m_HYm&5)Qf>1C8vyUX zawRLtZh2K8rr^`-{GPF4!?Rg!6^O|t_Y~}KW%Ci_b24gO#Id-FE&Ffnc;VVsRk_D~ zHM3OCHRiH`;FJkvBAA4q(dzL8cjCdS_7>JS2vMcX6z-_e$~CXVeX`N7Ew(n(B=deC zDLjr4TLJiHz=T*3>$pV!KI>Ri>-H!yya8c@7I1=0dJk@?DgZC23|^}t&oF5dHu^Ha z!4Fh6OAEa8x`eC39T3ooX_J7uu2UM0OA(m;>I28`9hr5{040g#qwO$rNw?5$%bVug z?X&i(J9W`+k8tvk^*gzVjWlBvNV4gY{R*K}u!cVWmGvkG-3bhwb=CbG*Gn&?F$?OZ zNfG9fm=-CS3Xx;AQ4l|-Vt3E$I-*$tCfv`#=i7h~awd7q>J@M?wQ%c~WZL0IigJ$0 z4*ClBbMRakm5ZL+j>1-u0?*%0!xOT}!-zh0dID;+DNLZPnF0|Xi!iS$&WM=4dakwD zC`B}W?Hx30RKxd3%n&r>EXVZ(s-V#Yu?1mm!E(Vg126?|=1=k7u+}Hhpp;GhS}CKR zRywtjS6O{zYAYVjnJ%3V4gReZ+_>t_y$R*yRQuZWxYRzJ(J~F-O6W3z7m7CJkSb>- z_sRVLqG-O=N>gA7hlQ&ekF`ExCksv#`Com4lOs{pX}xigO*_l0Ik6m1R4l%Qqx4K# z7K&$tTT+QZY2V-cfZVDvom7DA;pQN{;FD?g1U1-(>-aUP+6yI@91p11(A)UwR$8`8U>+?0R;l?(na*Vm>yFXccY1 z)Bel}A`)PFv38O~SywaPW*2$!K>5gxX7`W0TlI%98fs&<0U@N4!FXKT0tZY!K>EAt zIhwLzXGUoTlUw{p$vjv6@bmi$t=s)+XxSAtSk7oTF#TLz5BL()Bghu20J*6YmW{K3 zerr3{JwIq;+gGrpIX{!JDR!NucSaPGyAZ+f7_K?|iKq-AT)G*9>n>K>=ehO~_UP{7 z;mX`iKgNc}!F#UNJD_|y(HIM#i=EUr<}%9?yz*K1u*lH===tu2D`*|s%61~dPzMdF zvA}0ge>vgGNYYUyapyrk@AY;ex<0jfqHp&l%9^l=SjTKj3H+hHEye056+N=V^#Cq5 zthTH7)Qh zt5(m{m|Lq8U()<{XVnexy&cmtII9s?-R-X)JT4ywi~Y3f@-xM}f$Ge7RDipwg2Yw) zT#hva?0O*B4m72xN@vDlyt$uDSI};l*gJx$`~eEG$h!L=4=s6l!Li+0>(RVi!=Z)} zWVm)N6uCOfE)!yNY2NGmAFx?#4;2w*+R7e~;q~Qi(BVg$PZgT$qe^&0Xf8#nvLL!J z_jL~T5Kdmo=Qz3;|7M1JFKuqz2giE`4Q;(g2FJXpz8sDJ&y@*e{3D+E{<^3FST1Ns@5-|~s$ zP-epkMr}Kpqa}faKtX^nJW2Q@?fhCV`^0J|dNT}RY<8x(PYtsVa$y$1T(8=dL@WoT zkPQwnwx_3O28-(^hFyVdxW0%7YvmhI_*Y**sd2tEHByLu$O%mWnuM6mH z{Sk~iFVdiF1(fiV$v(1Yv{%|_^1B6e2aY;-^$zP`lEg7~clB3;_dd}UYjlb)ulX0{ z%Z#qXy2REeEeGElMkhXa$j&8FWrz09hD}-o`?5IO5glikRX=3Huyckk%`5xf_6S`1 z*Zxuh(>7{mO)QTsL&cAfO_bppsh<2kj?$57#nEoIykbHr9FIQ&=A5aBM6-)ivZ&^w ztT&!^jF%}=Pio$0$cG~vq=oSmaz=R8;{LuvIyL(Ugq$ZAmlCUCK(lB|G+v6>?-yGj z^zq!IoZ(m5FcJ8XheS5scix0W>ElcQs=5*oI^ss>fvcg_KAEprprtx8=r)nj+Fkd^ z2t?#o?1Yfg94< z9c9>Ta4fM}$)t8+3j)&p=D$Q?hkS*Vd7`E6JazDyrmNM7QNX#Xn@n~f3jvxANc=uL z$-8b6cmn%&lm%2(4wYuv4g`Q@}<{Xz88wgiIMZ>K)Z2dV)wD`f!n}R2=eRm2fUH>ATOhP$djtvhI0id01zHil&@OF(Z z#)FD#Xx!u6neX^3eAz)^@cmgo`8;$!Ph}qp@q3SE1_3Mz2QUA@p)|fZg~?#}+sg=^ zgs=x+g;g?@ig@OXi+EiSwozDYWgt=WatB!3^L8j}W?#kpXye!tV8g**6WjixpS{+3-DKWpgl9knurQh@uJ~%16Q0I~Q#iBeb?#cb};R5d7FF;WuGVU#xc6fEg5e($^jrgcSoEcMUlN z+)V`q)hi+o%9rD_K!sfun zrHQZmR*=s`i{ga4B+dGf9)Pl6k6;0MP&_0Le64S6*-J_}`0pmX0R1Yf`*XosPiFrX zb5jd;0Gr?N@-ebccyp{BZ*7PmNNJhqTh5W;N?WL&SRqo$j0Ny@Zced7*RKtML9lp)?&}we!`N|iwWwwDB+Y@Eo3~q^k8o_pCh&rN;rM!$tXm{s-a?t z_B)|UKi{r2SY^2-c*GaJX-tVcaa3oZ?eSJC@uUY_9V=3J6M@#xcmlWE2mOVS|tG%%6v5HHMF4MhI&>0zby;st;QR zL6va+)ventlF!?U7k)v}$)`l+z4ujn4aYq7^qV`W2R}iub7Ez5g0xnLp_^yz3sh~R zhVHoSKGO(9BF07#k=1!_VjF|poP&{F`GFo)j2|L{+98xxy+cf9GlnLW!*pVBdB2%d;2Ko?3R2{f97C^Fivk3X) z7p}#cC=^jOI|UnfJl8L4we`nWrm*d9FJpZgisFAlm#W4dnaR&|41^&ME$_sJC{@g2 zQ4HaxvN=n6x8zu2^wo&?2?dw) z&aF7znWlz;DBzomXBbj)@{BJ)SA4w1X+lWzce9a(NqtP(=n|BPwZqSv8MYIczjyjU z?m-8@uPG#)nLhL--v5-fvNJu}b+{mwR))(8p$0s5oo^ZYU#JqN;CK|Xs+qhX!)sEBoL{UN16}CqUgfwMF&N)s4 zOhEe=H~$~t6$1WomAIxA5S@_|%iHi+r;vmG?F%D~tnoH%88lD!>({u7J)5#@YcXTJ+^O z-In?iC4V{Ed(U3@jo^+$P{l+vF2KfX;=r}k;H19mJ*wy6Clsbl>7S;J7Ej!QkANoI zr(sSl;L(w`9!KRx zXJ%*7Ev4Iu#B}2S^21xYqmmr>O26vu1SLhh4P9Seyj$em?V6AJY`;gHs-?&gfI{tQ zVdBLT-NOrm?)WN|=Nf!z=KG*HkFa8?&JCsB%*5HULx(9!CqK4~hu%P_ znve5abNuAi7gY++{EpNRt}u{%MeyXY`HO-!rw0}S{@O(AT{ zqyj_L;;C?Fo&Bm$B~Dhr^2OwsR?p&fjmp(5zXlc7${8I*9`f{D`pfhEllHk$9Ym08 zaxza^!Wdy>yq{+Bwmw26R%7&J1xJu4;{;aPn~+~Dg>O7JG>!1v$nkV^V_C48sb6v|abq*uQBvK>p&H|$7wK8!{9 zb^sz8VYs}9Buw?lQcl+*;GybAWl8>)&+4vz@J&&PSzVBZK_xNo%0RFZbtsGc=A=73?)0G&C2Hph zT=BDTU``{{{$}u?^}AT}zDy_5hZUo)E5w|hhSoW`)Or9Aq^$GajY2J^zfuRI%v(i0 zH%p8>eib@8L9(Ipel*|dg_i?y3vyHt zb%0|dek$dWoWo4POv`_lW&#E@#K3MUg1f|$fl~qnYT%_VI##|wdz6Sy>%<;Wb_Z}_ z-J0k?NjDbI$+Tcp=@WRf-3EOVoL3eVrLGGL(YxpQ#Rz;@Bit>b&JzJEO>eLUIG{fYhe`-Xo6paV1Azv&?8bVb!!du z6JdX|L90v%*QUZLqWug3R0(Jq+-w@;(8<(V+_8WOS}on87-*0rwQ(wCoHV8)mlTb3 z7FyRLiBXUcsvWSzi)6WB4FuBIQ({WFz2nQ^0u0VTc|lKz5|Nu9#A4IVm_dg(H!?F6h}{J9+Qu4(Sp$G9dO4)kEo@uz8)M5yV(YF4qPXzYB*doq$0wcM7F;W z2e?MX?ccwOi)VrZuink|$g1=7KUKN@zHstt%EUZ-1WB#t@;l9f#xB~kt6&yJiIpPK2+aIvpq>cm_;9l#c>`3z6z@wpC6t$ceCO5$L707F2$ zztLHdN|m#7?2}ykAJ}YJ9vcrmgLCTza7MDcHoo|4)N;JB2oZfxJ)i0@x0?!`aFoS@ zO2D%`e)-kkgy{PNJ-l$#4x2Z~F*dMlp2cW3BX;0XRJ_NbX`kh7BGd@P#$v>4V8WWt zjG@l9gtU<|m!RBdPpNvy!yu2|P@i9#4LYY&Ig8*gU2mL!fn7e&ic#_O49Ft#6SRw* z>*N;w%sVg8IfPq|URp1F8VR1UegbX9Vx`y!%d|yB%9tj}q2RE^!q48#skT>Nv~3g> z@~AEo$0HB@Xb-$?V%zUXHj5|lUbLN4p5q&ePfmWS#F38@><8K`R`rwg^GHRC|My|B zEUNiIvxo?Uuozm5@9xnKbU{zR=hph+%=qr>xE%f~kfSROWp>npO!1MZAXNRy-wi^l zZRrwcI~j+12=3_IJc3sktB(d9k`Ju4DB)BmmgPW~a`0X5Zw#RpO-S@=ZSLkr9r;Bn zS}zwW1Mgm3HJsCdu27DltJN_4n|ys7Qi^7=&jclh;yXTonE9J!w=%<`!Vu;XVJlB7zSR}! zjRZaGC<YS)6ETMW?Y(>yhabJ8kO z``k8=yhVJv$~2COveUBxL_T6m;0nBL@d~Hpbj*(pYXbFkZBhP_dX&mFgJvo(00rTr z+!TiUuofUP==F%Bq5n=}JUBQajLI1giUELvo@rbYZn;+PhJzL?UKA6)38?JGAD-Yu zB|Hi#VJ|EHG|S9Hr_zI!ay8PTR|cZ#=3Onz-@+#Eb22`3#*D_Wrkb@)W-VP}f8#jD zcvI(lEVx`KRsl0#icag@(DO>~7kLS?d#D~Em%GW*g)^T(NLMiPT6sYh;};4Nw~8T| zX8HDOwI|D#cEYs3f^FN3imBR|UMK6E6+rQq9arr6IK{y>pwQ}{pH2=z z?ra>W*_0w#=9i@Vu8?1~?p!U{Qe*Y8^fEePEnjWLQ0{8PWv2efow4V8ecC{Gs{*Et zJR9~%5}N3kmLscMN1Gr`J2HZISLaez-xV(?t97g;=TY2%OQ=r}8FSid1%7EWj{|_Qh(2HqfG8kx1R+&t2TZ&8M;1$+ zMfVMT3IWIM0{5F^i-XoD_nM*-P~Jo#KD>|jU1e++NCv&Q5%*(v79S1gkIb0W5m-lF z0_gxst5wR(q}{r1ll_%J`Zc+6f$A*Y#PbEdgE2k@Lna==Ty<3Q84~rlsdFkvT+VZS zkE1qRN0KEFbVwff7l`ppbW{OiQGKu@i`xpT#ReM+Dm^78xS~|QLTIsDnz6ex@uIL4 zAbil%n(WrDsb)>rGee1>1=Bl7hPA>Bn}jR z({~b;bbrDaVL9SNzFWQRZ^k`Bn{jfr;{U3gq*(b5D}vLD7h6@-7dKUw_6t4>{)M%h z==>}K5p6<|Zs&lHaniqz}H~em7q7;SJ419 z@Hm0SLL(o|Qs)&9Ik+6)k*(N?%^t_*3)uwAQIcuD({gGl*O&WdNbAacZgT^H_N$(j z|7VcN|0WJX`b6X13D{ANRkID^!V^;OQm;Mhro;B-URy7wGgx^?N*k$I?)~&Z`26pC zST?kLXBa%a)ybtfs{B4^0CVq5u~grIae|g>HP@GEa?9h|X@}!Csf3C0YMlFq>KuOl zooHKcO3uKdL^CjU?+u*^ZynSOB~!K)jI(}1+U&17+j|Kv*X7Fgs822CJHpg=>x++X zy^tje@@%aqA;$QzD}9bZ7SBZ3wKwG#2hZ)yUE~4@hm-$o36vw`d3FU*TGNGg`FYP$ z>;K!z1s7pq*P0r0lOJW$nx@#*P%!*q*+>=T?H0G`U2Ea2-5UgCY5K?f2S-1n$Y4h& zk+w2IKo%0|5mWy3&!8c%y}~sWuFigk!5?@2=+o=SaB0*C|%V zRNTAT0E<~RVhcvFG<8pC7edbZ!^bzeZFLMxqip^1f>PE~pAFu4oI{b}NQ}ut=(pD& z(VpnLi=$da;f}Mx#;5eZj~_RBzcb0K3lEK}5h8EQQSq(*IR^67{X<}im$}w#Th%j7o zS@HM=Iz%7X62??MW=rX*prv2`LJ}bXjf8x($U*CK>B{R|rjy-->^+?^gjz9;UyJ$I`(CoC#dUhkn8bT zr71&i#FlOXlx!sWvMqk9V}9n^)&^M7{K2_NH>3Yk$FUJ(^d+vO22$*)-*PeVC+A~9 z|9MbqW>CYo6%<&7*yAODh15i9C8R-F}_aFVn{_O|} z7R30P)}=F5y^X}4^&2K+#g=;xKhTL@n?Vy1uqM$2^~c}REanS7ycb2RA?7=jd?FL9 zN}w0#jViUg8pSaY{joNyx}P=^Kc4c?Wv(DU$3#excX}>buIiinso@tMDJJ%G;Bm+YyM!0Zw3MC~-xivit!b(xT(BOIi{&^*qWiq5rso z-JE4nhjCgI2~=E|CPGt~CYJqX9PHMK*U!HzN&*%?yNbTZ9Kr?2@Xb8*Qj(3^4bd~) z_$QLJb?Y`i{Hl+pW$+cqce`%7#T>2P+L+)aD({d}pu_LLs9oZ@5WHiAO#mEj;-1`f zWHFRjx`9x^#88WCVxI7uAEyJbbjaZGhT-h=+p4qW;Erg_BjR?2op*7*D{f=m1=~cN z0-QvTqn-Gqc)!4RVOiB)nqO#uS$Dz#vj@ zKb!)XBH#-cJeFn>jo*~5z_$=_dXIK@IIbk#NpL0))2LJNMTiDH3DoJa_C8>7X zH|lwG?N#b88bM$sTh5^WwZ;1}`^Ypj%YNT`AIZ#`npF@QtUCq^J_t>CX0dd2I;v^a z?3zmIXhzuLc8y}pz|B#R6O3%01L$%nqqO_<)zksQDoy_*~t;sN55lG=NZ-oB%cW+B#T?9a{`>pJxh%gSNof9sx}+mne`nSW)zQW9Dn-#1}PJ3^yJ1 zHi(i>5;iy{4%ps1(lH~&ao4dSXV%U1Y_lNs*`jHPMzk><344Q&}3L4Np!gg zvER|?Om&rE5b>J>BDQi3?b%k1 z+6L3_wFw))pX?IHhux4wfcwPL8ONgK(S(8THj24f5^(7E zlY7BlRyANU_L)qG&E7@dR#^YW4T`gwuP^Np%bKz^yHM1KkD1Ivp^xZ%I7pbV)K zg}yXx!?BHZG1JQ)VZN6a{VnbVxP`fWnI0E&Y9y@JBFwHIybhJ}wiz9M$Pm`;j>D6z_Q^ zO?=T517Prfn`$^b>VtG5Yca#`z0Ap3%ln8*B{3vIaf}j>_Fytn$Rp~N=$!j+BjhO* z#=h66B3sK-%7!(zWL(!0>exv2`6Evou|FN|UpRnS(B8113q4k(uwzTEsIBCeb)3;5 z=Syh)*Wyhv9P{Gtv(^WvTL_!BZPFH9g z1zv$jLDRc^sbui_a>Sji2Qk+m#~<5P4!gf^t#0YCqo%Wpf4FD}Xgh#Aa^dN=;E~5x z0O4!?`yn;>n+*i~<~*jJ9PGA~mb4Dw5O29QWIir&Zl=U27JrEp#SbS5B!CzEV*}+5)6!(66Nj!f@j(6}PHU zJ|;n_lt?&FIe{DxDxpN4b07YU1!4jzq66X0&(dm`RQ8VZQP z9GU(aDwBJy!XzuoEk_=aD4H4}SO{91b6k|`>Ii&4(`_BH;m5jCG~!0}<7L+dgj0Ez zy4yu9eDhL6lQm)b*8{m9ia)Q4CK4*u2koi`V+bOx-qbI7KNW49+I<9b@d$Vg_0xu4 z{zyq)rUz4!ASrHbqJW+k5B0MIpdra%nJ!r+uwv&;C_WPVXfrV%U2i?hw#h=G(;Dv* zPqr=OPRMg@Qj#~5g1%hRJlm6;#!+k0hb2s*s=Bs0CN4KpIgYXR<39+cOxO~`N}zHZ zHxi)%nJO2v`@NJi6ZgAE-W0ZOA66QVmj#k_{98@>_rnXOX_&+hxRa03x$ts6*tc*h zVnmS)N#Sk-LVb%lV&=kP(mr+luD_9G^R2Y(;vLhl`KPSR&zB-)ks^a@e?R!cu9<$M zC&HyU1{J(v{NT27r5rxwH#($Cv_PeG)Rkj9kZEtXb3);W_>fX(YZpIXylKu3EI(~) zjjuynBp&a!LA3l3a8Vsxus+MQQTm-bT{$5%4>u7dS$`?=fjy-yrJU+Nu)mDt9gpbXyFngJr@7+ zm&NuE(%&x@m#=FNFgT8KOMAWCPfLnlmXff8j$ziMEoekv=*w?Q?ei_qAm+vH77akYg`G9CLbmbtNpOYOU!Rg3C=2*M?7?;^y??KXn+3KjO=3 zQ@x{5M~%bRoW~=J!mQ7@k_%iG9}+jxfK3aD5Y0y2!iY~zU4ruApy4XZyywo*BpV}S z+FS*-5U4p@=@kpV?9M&3w zoQ5aT7?n!Yuyx}`hxffqz|ZyLr@XiOG2LgAhY+mT#P1965*nTcA{9?hxp5)$5{)HA zKz(5Fz~htL;Yzw7(G4{6ZoibIv@Nv1Lw?IE*bv>ele;?qTA!y=k}0paT;?cgVV4T8II(IaJTj<89V z{%NW%!LkbR@?XFjJT+@ri(WQ$B+sVmjhNKR`bvXTs4$@cimh1g#QGSf9JSco{Keo2 zQQW?+>;Qk?8%xkOiN@EnxJ|ARF0m1gbP)6P-)jKp0O)x1O5@MR?&K*nr@R-BY_L5v;xvkv}_Lyx~+XavK7b&mOa=lwDmo?$g9y z=uJlWnyv%aHf%N;TrDcXbi3)U8_V+Q-ca(T=kjXIR{R}xZeqxd`WdN*5dRK#&_|zG z_ROMR9o^1#%qR%o8Xtzfh6Jgp3Fn5G6Qde8oeJoU4s51Z(YG4&^1EiQZDm-g7N8r+ zz>#Tccw@y%l~ABcJD6gK|CXJm4cbd~U0-MuyPKcxkAl*xth@Bj5wWPM?W9|1S>?iH zjmBE00OvsI0Nl1xuZs+)Al z2Jnd2z!)q`J*+Sfw=@44Cczlu{=2dLXvw!L7zg$``UEl*?x8pt^em=B{-7G*?2v!- z(Qp)-_k0j5eW2{KqCOCLo}-7C1}6ezRvO@_jHJiWNVn9U@UKSGJ@N{r&{5a@ytUgy(P4Da6QAF;=#8 zNulnt2Elc3?Yy#4oeLsOzlPoKPuIlHqQAqevqp_X*;!hAVV{DHX0J8xU+ zPX(?fe7&t-1mBXA3F+&wJiwB^GASAyL=j^R)-Th=@{2%v@s24vrs1yaUib>Y4qW!k z#M?(R3DdWeKa>n+m%FWMB}Q{AsU|f3yBd6pSjTr5_eF%Y2tFe$MY;~IK}K-vG7fef z*twx_&6gL8IOb&VqDm5R{(Ia_2-nVQ{gTCI>jknvbmUq_o8het{V;GrMXtLK=re8= z^&*BEw-;}3uILgmzWPapn+TEYoNFdQ@fJaF4PX+5y7hNCMq=UI$g)N8^Z#)=ArVxWU&M<}2Wk7%C!581;rGOkwWX%w)YpF##6_tu3;r2LDO1LLDP>Qr< zl?-nYC{K_3j?sG?Y(erBg6d@(LPU88fJCxOOOf8*6-H0gWdB1M2nTtw`by&bb{oJX z^W|TorjB66_0R_hVP+4k)gitBzwnDnnbeP*`uIdh`isc2;fp6pdpAytD>+eR2^|2z zh0MjIh{)k@D?fH}T{bPxB1B1VWa7c4{(Hic zsH+)9T{9#LdnGFBxeqV2FIIhARGXm0vG5p!6tdo{GVUPyYQ~ZxVGp zjbB7NC%F-WfUejEh^2uQee)ZDBYD}1w(P=G;z&|gt?ff|i}g|)NPr$DHHsWeld;qmaSkpR0+48}Bb_Ssu%6pasjI zL;oc57~zK6>g(?|vLM2}As;_vt{C-%0QEqU&&ywHHd=fK^_zz&OL2(u>-_gjIAP?t zDNz4V68cf5=J=0zFMW=Mq-BsJ{Q zoH8#0xqQEf-$E=^w>+j`yixQ-Ho!6O z?uab-XT|EqemdVs^31}~&Q#m6@3m0EC}F^sDFGJHs|2hoO`T0pSxJeSue#CW3-+X-FmRU_NOTqH0_a3cG-F4JjC&AcP6BWIhZI6?i(*;(FU%w?c(CGl!=rY?|lP zFb^ZL>zg4D%Iaz(a?@Tk;AC!MKL`%A%~1mdFV;;^{4sh$412%m(R4y|VR`)N2^}0J z6?xW*%A<)EGuC!bE?vH(6&-u?Qu9juz8*T0YSBs4_AL2N;dmpq+9MC9-O>4XPJiYq zS_`{cUgfOb7?+l&r;1D3dlWt8(0T1-D);%s)?=rO32Jrc&J_A*wot7&%&&}$6*$yD z_6Y1|%w-VHiUvc?J0ZS&9Sd1n^6sokW5uZoI5JmPi6lShSBj~Rpa`JmYf1VpYxbww zRbU@GKdQ4)dnAMGME5`RO9{}A)q1Foz?yW|3D%`! zM&nGbNAb%~Wy@qUM!8^3F8sz92(^ZsZ(35yAHt^&$cdDXSuK4$<{@B3Nuo8n6L#Ju z*Tr3qMV=NGF0s|fKk6lH;=j)9A16UM3?bOYcJSH2y*l^V82JwJtS>y-E5T zv)?Dh>}{Y;B6aiIQ|fL#l=OC;G8=PFnt#>;?I$uUn;x$3_OKsn-Ewg8$oz?jTueXm z#^#csKZESKUuUCGLY;Bw2sATUFx+ci!09VcXjv|EQCJh%O=Wcr?GBOrI#5bkFR)s# zw_Xt`ji!0`rctgEODD~!FBLO!GbK_ryra1tq(P*TU2+`1D&92ocYS;y`*vxI(dJYc zn3#lY~;q3*RMav=ihL1=N*K9jB#JYBv49`CU03yr2fX~IE|!M|MLn1Klad-krf3O;4!T}V@GR(-gNRJkvSta zGFK3vIA0ZILmXBENfh$T)Gs2v_lV?Ftzm{$OLml+N#$6`GDN(BmzB@>Yii>pty#pb~3o~)#q$RgxAQcA~htrcGpU_M0Nt%YEWi^Uz zq}Isn*Y?(Uj&z?u#b@#mf44ybDsz|tnx+Acy{m@gL{vZM!q98wCi*XPAA>CT>KRBa z_M<{x*s@*%4AFKJyY{KWZ0BE`T9|gIOIKrbL@{JvFDJ;rEZ7zGK)f^EcDqv3GOskvIoiTC9f zWG&wARE-XjCa5AfS3AU-zEb(CSs&hxDz^exm)X}Nhj(6tYNr?tni|hF8@UrVKF%Wy zuY2to8DsM02WU8-2x!tP@*5p!;t7lTbN2`a6%YDmx#!uf@^et8KeP0f?e!`cPF7kVJ9PG`diW&$xS4U z@X|kJX|1(D@UdA?&Pb~^aUGjhXWsL{2-?s61Yk@Y{fPZ-&`s3ftKeI>d{5_glV#C| zelY^Uj1EC>!S1Xebs35Far4BJrkL+EZCGair5ly##pD>vrC7@rwBdV)dW>kyVF?hamXwmd{tgQXXU+((a$jR0q*RWby!`X^DyzbYt|aL4(<-ruyd~J z+O;1#J2uxC@KL(38;MOrepjSz4uzLd+Ddhddk&GVg&Z#z=NLHEH=NcQa;kylTM zMOCFcRnf5qgEAZ&<=86}HHAAPckS+m!=Eo@&PEaGCMsb>2bU=@wENn7f>U58XVec> zPM9*5u>}BAn!kq$J!b5DHivBaYMB=tNB-9+g_ID*x|uD!uTGo?KL*Y{HO>8^DP98} zO{X9C_%($l&2F@*>2Ql;^>{->e?l)UIPu!qL(x)8W|{V43*_8JsA{86k~$YHyN7Opjc8Q z<{pJmy{(G$`iXE~3PHqa_()98)+tkP8Fl*$5m9AvA5=elm$s7);OA&wzUyLWjpI$)5S7r@@=QzWHK_uu7r13w7 zKGIkqq;{+HlmOe_At3)c&nlBtJ2)t$)5VPhOIB{+-apl})PEUgDdVE)g?f>zFE}Fq)fvw}x;V@TX*u^iF^##y~{c{ivsaTMF=dHL56H6BBO zxm<7O&ZR?!B(Jj?_XX&Ki_+bK^5R#@-P1`z6Lnf>{(|Xy)qu<+RCP|Lo-Lu94H1$3 z^3b8$VKEb)Y{x&8DADF?Vz}jdX(i%epktUyo<7+~dZ!MqZOnF!+23fE`+%KJD~r?# zu&R~BFy@QCGq2*f%CH6IB%>~JU+sgLNKE%P6=#Hq4O3d~h1INC6CZ<8| z{i;m^RplKgDd!o)+Wow79MPMhSnTE4?gdqS`s{jzSBa?)m z1~1D_kK_fL`uUJx5CIH}z4$l7FR!VQDVtSVGyB84X^8VS??#qj)1>T0C+c9v!bo&8 z5hGkA|D}`+tj^od0`wgEx@#B2^vRlXH3frPrg*l_l~{KvhR=A3XOJayh(zeX8B$FIH+3&{fN1JQS*vqItG|^xLSWiR(VW{^O3LqZ0BbX0kOHYjxBs#M_7rAKlb(Nx>Ex!=3kLD(=AXE zwjjtGr>E)l^%RnIddI}xCyi|tGpR5*`8Srx76d0ZMUgz6<z&p_vgrOkt zdIlK;beL(YLsOvb{`pN(rlUw!5dCMF-<+0+5A$sUct%^;Lo1#2t29rFJ)q`6_o_M$ zcy9n@sK}uy*cZ5FYVP}U{-c-(avuid%$zsk{A&Z@lO1tz$)&1Mx(Nxk1-JmJ)$)mP zk{oTb9bw7&;Kex(bPd+*#kmiz`v3>T0d3TLVvR@84RExvTEB}lx_t8dS|yJ0r>kXB zdFep&T0HV6P~Es5)H*w2{MFMyXh{Tz0;eSZ5{wm8}s0@|PmD)LS9B`vRpa40FUPX1lu zz^(etts6)r_sintAkAy*S3dUyDS}*^LB~8=mX_LSpL-?K`Cyoca6=@&!yiHG$na=D zMJY2Nf9@cQei^67mGKQKmJT)9`2 z#!D*P5KzF)J~ehYo@4nY!IIiI-=7~^jRvNxLKrF|1C8fgwp>9qBKDf!0sG?g03RmS z8gwZEN4>9ls3dRU_P-;G8fynuo^-AZE-nX z*pM7@peKN51`sJW3-MVozh!$ytBi-C`+5fzU-BHYWGo!}Md-#P2g=-&aoutg`A5^= z5u0rbFJYqR+QDD_gy=GC!-$I!ftSzlxQHNi|!Y=_)qb9d+SR6(;)K+ZS@FH`{-lY&P8+BbXLG4*W|e*1S2riF^*3Ll^91Nre?f#B z3ljzc@G;&`xHph0m+NWhhXw;r`4zphqu<^(Z38(h+tim8pC!DUD591YHs@4mj!DjH z{cw^=LH`($5nk5ih3zB$160>})Z(tsgopcnis>;3MkV{I9QA+M6Z*3C3K5-goIhJx zHY09Q2S%}uSH-uO`EliZiB5C=T;9#zQ?y=rM0X zf$6tWL=U$G9?Ykqax}FUx5#f>lsaKgAag}w_DX_wJH{9;*Os#Y3&QAUsTb4=7e_)V zFL4RyfE82@w=yrEs#>k^#O`Do13dUT7p8n()&ld5MKG=tQ8PKqN9?_Vl@W(=jjrMI5-pGJ15(&27QBrcoYO1|OdyZP!gC z>{+yfY<*=PCp(>Gq{|-=3w%O(2t>-W8F%U-3n!}t;@`IDX0Ix+J~m8boI4cadbOp` zsQxfDkEI||AVZ35@&6ViO`$rUu_!}xL8R`=j*h>{^};#=-|^7k_z?7q%^CTYm;`n; zN`HF!j08OC^`GD$Y1zW$I?k%nh9LvNnZvClv!{<)l{2H*+Cc^_L~ww; z6fp4&W~M(r_X=VFNokQd5aJJ@c@RjKpMjdFD)JbJ`*B^BZu& zQsOg9Z>`@RcsKon?TLtV!+Cngnp%n7X_lvVf746(!iv+l>Tx9c5B6D#Uu zDoUK%3*V1UjFO;KODrKncLklqzDLdeFoO7#INZMQgXWVe+OSB!GEV5xwcDIEV-u|mQ zg>%>QR?*5>l*D-_hiDASzoJX_E4EX>C1|sgv0YYg;jFeEIIPd#z=l&DX?hDfufKMu zhUM~~aCI;9_<^2kJ*#Yqp;|~siu=Ohr?gxLV`oBmE0>%ePlzV{IH| zL%ct$aeA(p4Q6hF1s3)u?6IE+j&CiWU}PCLgB(>@9NV@qq+_pK>ZZ77#gS%yPKEV- zC|Jw%!H`2Co_l|!nqqmfQ3B3-98(9$P~G%BrfYdjOg9HvSpAM;WLZQ&y#)W^TVe}2 zqutf2XY-jF6D)_+(^0yChpZrQ;$@u|9-m4|=^8N28(GOooD{soS;O8f3HWwwOl=1I z+%z$>JIoI1S+05eqZyd9{PJexN>`8kJiAuO7^DAJe>%;_LZY=wPy)9T2+_R^f+atE zkxWqoHDMZB0ftYtp#Y%EsDhd72utm%b$4@oTVwwoYEXGMhzdT}W`}{hh01;m9%WlA zMJ=o+g5MhdZ78xE#}UC<@{b4XTKOBtgNC0bOdPIaxOXq)BUC<_nEW#gOo0jNb*oD* zCsjri5r4wQ(fVrW-76gz;E6q~HQiOirp^86-V~zj4$j`X%QW7CZw*%TfS1>M(~{P$ z2qryZ7Wbcd<8=+ybGJwnyFfsR7>kLbJWHWjh?7B<#y&IKiKcAZ5q?r(h-ot+yGUAd zMdJ$;9D6&zT(kiR4mDR8T(T1&OFOyzq~eNQ8#Y(s+t>M=F|ul_&7X{SWjW`&zcU!z za58qQF<{y87EOciK}R35$d|JIoQxy8)|fR=+C&PwW11)UVnLS0>BGm#wQ`3gYrK-s zre4aoR>P%s8ieKD1wIM6(XESsV zw8j2KksAbUsdX1V1~N*gA$$+{cd~T2n%+a1_usgPM2N|bZ#s;zOi~VXqP4h+1+&r9}GT-K6e9_ zvE0&^pKcDw)vcuyX)r_YZ*9%-H;PfcfJ-Eq)?~~P4zPDVy`{|d1t?&}=ip|xg-9k_ z8>z}`?uHsnp@y9^&(KHv=0(eqII`B!j2{6Ggfefn1Fi1550DK;zU#}txie9+>PiDf z<5`!DRBU*3$w}NMYA~SMTNT=;*OydkF4S5#;MRiDnY#&sd)$@G4<0p;W#MBVXAU)@ zS_)}sZtYZ8X)T`EDb)r z-6997)G3O50;=!^=F!0iZ~f8N?{S2%1%s^QymJL#^e)&5H%z)tp>*ftj`Rwspn{uf z4G~$v1*LtN8;GMpg>r&_aqB&P!rld2mo$1kXh$2*eOM8>eg2?+EuEd2XjZv;VrpuG7!C=?m$cc{TPs{`qnzHe|)jLlP3DgRIF>8rd42k*tA zweMTc^e)~ggiykODYsMrgE6Z22r1;4V&QP6as;$^Sv8jtWUJ#0KH1OnohGq46?aaB zBJ)JvJKC0Hirs|9lix@MK%9GJJPj)IVSpy?k(8ldJlAqbq+n|2pmWnQ;^+QH;@WDNdu^y6 z2V;OsD%IAO_&o_u)}o(wx=t?Mv{;=bg)V;-)|%({&(j2lrb--2BSWOZ-Hd6E6cRM6 ztMeF#@^UWMxloF*xK6DFx{5^lc*dQ^TDefR5b$iXXKD7%$(?G`?q#wzVD@A9P9IB4 zn8ljF@8ai|p8A0XrKAIO=bIaO%{TGqx+<{2D09G2o=^_U$0G~rm1hO-20ZT?-eK$Z z#cnCzI`R*B14UgwuV{KX)6WbX-HmuN@e1vr$2~2xXg?>qR^S)GwWZrFj}FZ{+MH3^ zcDum9I@73xU$r@z1qxRmb0e}H;0|yyf@Xs;iqCH?s?>sas;=_r0NbHZQ%N6sBV{Yg zp+{z-r_NqFa$A6K+;Xcip=w3%lTBp~&lD!7{@HvdKqZ_e^VoTk@xH?ag%|#rB&DZN zkYoBvGq2{W9!{`0113bRpzo790^i@4I@DuCg1@369|yKAY4$kxvB)4iWI$%*i8q$Ht(;L%Yk+|i15c5jSFiaY`2C*lno?v9P1aU(TPYwm;MYLWh8_JUBq zF4(L!BnlM>d5br~oN%r%p-(d}_0b+`<4ap9x|@P!3yO|*xY$7@@Q)qr#l~tJ3z6uv zUS7G)WU1>GHI?pltbfE(^K@S!7$Z95To-rM<>6I)Ba=SelrcvE5tvKQf#z4%?5gv^ zu{TFTXhwuK79iVeM-uF_M=1!!zTbrW&hGQd1_OT40*b3wSxvI2HAN`2GU0XSh_6lf z6Ft+5tOC(Q;Stgp!$6QUBY<{8a1sPN`9#kH&pbMo7LfpsFai42j)jme}a}hR}PF&EjI&@Tci`(=D{3Ya`XL%1()G*})^RrSm zf`&Dh1Kq=5^|*OpS@x_=B{4aRcf$bvk~7X}_Kml}N^3L_AiK#UUdg4en?}p}qqoSWE^JngQ6_X?7x>EQlIAO9*QjbFJCeKaYyD#E&rihzV>&(g8-9e>1D81 zz3w}~_;*BfTW-V{IF7zo?)t2^_u^)tY9|Zb2hd%1atc+?29$XzrExoke@J`hQ(*ds zPw;GHHePcUn-tv4RAr}wP}Ql!Fh$^ne5{l|*c7Xf%osAbjs=5oaQ6=`bYH!*pWRBKlnG~6+A^M z|M!+GbCf8>>7BXGrPQh#ptYwYl#s0e(_iCK`$oH8NSp>0*qS08Jxrm8#UDD%En$T8 z!k+3QU#2DW@>ckctTyS~yl_nJvDDhtWMLLh;!keZC_O!lhjN*QXgLJVYHbKwL!gAO zWLWK2Bo=w`31YndIRY3sA1*awhkbm`SPL?$<~Er9yH}0l)~zG&6m*Uu5}ZVIhb#}) zDy*ykpco+B>E?5|f=eeg7m|9^gI9t{H?5`imqfv32WdzqQbgQ}ihpm^q$pz@7{+?4 z>h4~!=j}7e;TD-Oz>tsyh;Q~SetCA=fgXp#RHiY~^A>5fvYO`${lw>=q1!CQ2GCGV zaF3>ta9?FK+hSM0;YreD(dox&cZipgE4+Xp|K5LnUn28AMjZ6HSjDEsMdZJ6Xw9sA z8c7yPkJg>xzgYb@Hb9!hOgAQ+@?v<9{;==R8b`E9{2uakbTpODAn7%9w{#0QwVOTD(#Xj%KsFPV4k`f`_61A>WKz~~)(azlHHR1@%% z-rXS*G~Ce6E6r83n`Xmqg~GO@;YS;mMJHki%?qYXq;$I(gxX6xN-b7CIgJ1rZ)N@? zp%pt~bOuPr{KvyPm>~TAtmN7OQFq~yj5cY4+ol30{e=1z3=Fs!{}2Uj_cAy+>zXjm ze^x=SJZie9dfW*%D+2YsNAgr!O2sJ*kGZlNW=~$^)uljhD0O~wNo4619KaL2S+^h7 zSTWx^O;zAAJIZP$>nCqcDg!=+*z%*-eBR}w_^K`fl3)FbQHS8_W*fRmGQaq4O0BXZ zLEq4+9t9ideFr(HG%y008a0}b*hYu>q%eqjo)ayWkh$7=kjmVnrYa1X4rQ}St#;+Db8v3wx227 z9f-`lfi*ZM%YwcDk6o7@7Zs-pLggwS}Et z?;$Y?%zQlZ15h0Py27(m-;@=yq6Rn{S>DQ`7O|4T6p#{U5|1{spBSo(RF#Y^X{M-n z5?JpejRvr+QBoYr4k`MM1t23sX^CRCno)80rGq)c0({NCJCOv29=;>>?I|ox@NFF^ z=PxPyaW0|o)l*`mYx%AmMZJBEP;zBMA^}KoK^cF`OVjWehS96jj?r4n*GW5O?Apdl zPvwGW0v;+&$@ro0xo99+kyjcRIZ|))yMv1X0tpM0XrhLv_paB1L*Nk*^X5jJID3bv z=&j3|%uU8bxbPMs4n&jBo>L+K5lIWr^ZI$(AQ(}(HHa4$q|MqGr2xLchRIn-qkIkW zXEG3xdk9t};j-<_q8=RAgbtbsKJX?pUL=))xH7_Uboc!oW`Nz=?qOu(#!zZ|Ja`@`WW?Y zxk4%SLQ1k;kpr5iDE%i9J`OotR8QzUqW_=ATVkD7wTj)lYBVB{{*H1xI-wqQ(%2lP1Mgp)c}R=^Zu1N zVRQa&`If{+Q_!-v=Y&$=oPWTd^A5(%N4y6^@oRv2QoAlRA{;kcs`y4=QU$$pEQs^v zA?o_y&P+2Gfx4Oq(Ds;h>k3I#p0+|%DqB0Qc? z?l~K@MacAy$2L(JuCX`DxS|o(D((xq9E{+r#HwfVL1<(zUBWq6twt10j#o-2TEPn<#L9eB!NLM2-Z;Pr>PK>8-<3UyFKz= z0O7Og&`s(l-E-qLg4kLuL5SA@fD(F{aT&~MaZhW-VdwRX^Y@bh7qkbc7?^~;<)@G} zPA?O>F536c_FG0y8LDTcbH+*a*mkJsJ-UPDZEiv;v-`$Sy&`8b58`56)44&ylnYRa z(1Zmf7- z#JH;BXo5QDNTk4BAV+%+_&S^A8A5^QUZZkUedIq}fAl@Zra%DSfpA+|e#ZeAgq9xx z{m^(h`QNX$j9u6M>7c?>x13xIvpU?jeP(XBg_&UO_eWhxR8Z2g=8QQ!?Uy%xheN02 zhu$6`xiF-?J<(Oib5&o<(|#zOVL39^`3CS!_p%<7t+gNV-}E#I42j3VlZYEubRa-z zd6+7sLzLkx82>q7g>p5*e)OIksLy+Om>x|GQuA=rff%r~os1qn+qV;W(fpJI!hwMB zR)jfhY`}?YK5rqzI#0pDFFzO2EJaU9T)e|$>?F%D!3FNH1}`~%x_dfe z$g7-ul(k2gMj1%NVw5l*-qHp@rZacB@?bxLn!f#EKZcEsc=X}rWP=SVr5;!w1G`ZG zF@*=4HHBZ@P;q=REFDE*M}Shsu{)vO0uBDf(vg1Kv3 zaL&9a+I>8!ZF}+ZTEE1PXwTo*nt_Iyr|_SHnY-_FwY|AA~qKbyUH-oLAoCc)nKvrN$vg7o;(E^imk&L5WoW%pm4c+|g=>lL52 z5Oziwg0joSuPuHq^WVe{3?;@9)BNSa&uPIZyqq&8r%j$0$dHjxM3(@Tksc6id>jRR zWzT4eu1&sZG8W(+eaYw2a`At;3WH;qHFR9F8c8Zdo%vC*K~$92D4J@{u>QP)A@-r7 z`P%oJthbUQ=PX(MDDFtZa76~E{UTL*#$htFEIBxzw#+!^byG7<%HnIBO|IP!%jVzk(E<73lGt#I~0ac3O;tspBJ#J^~?^0~i5IiCB?5_ar z{>Cjp$oHY;n9{r=WU&63A)Z566$<3D-C_;LrEGDIj72(vvo>H3_VA5TXa~j+-@qM0 zcK$FRT2O2RC`4cMojfa=FSrV)j`=QRDss;I*1qyvqZqn@hVd=UNsmQ$u(c^s(upf% z+eW7G<1aoz7X~mAZu&1-I`AF;o76*1# zcE68$51;mTB}0#D`!(=hSf2V>mL^APOD_Z^l3ZsMu8If(Pn!BLjRd}67oc!-py5JJ zFOD0T6Eq8+2;`1)S)qNk?;dau2^p4B(_pl9uu@eN)~>(Lr?rxQmUWrT2+2s>ZT zOI=3hZa4DsZkW<$5-1%1)4D~UW9HYgV)chic_I(1G|X`Ta+R&ghQAgn(dq|zFVJhQ zKzGH6T_eE*hARsq$q@K1XmBGjX8E)_g6+IZ{5n}O z%-imDik#>(&PgPgGFkpfWOkw(_S-dP!$*B)jt+F7^XTwQnYL4{`Bh=nlb_8TJY%TF z9Nd8?1`k-*wzny&b5N0U$tsB2$?-IB$1qe-Un1SnMyyeh%jCtZ_h9Nd^Jagzha|pwdHGC|yO`g9qzBVlh!f zf`#Z~0QS=@`7Jm-EEyd{AuFyBSFwc!E8dL78d|ty0=(y>2(Vq9w?~Mv@}2W1=>D-9 zxpJaCn~o-ThE>f?SjNZEvItakX^-A6Iwl~BeZTfr(oY7jk8qv@zN8BZ7y5|@n z4Gtx-(qJgwPNHL-tX=of35G)f--AG}pQCur!wkPmX=J)eTM*f7UaAoMM$N6Xh@5$Q zu~U8FK6rGnom_?fxvu^|X}VpCa3YEfr6SBn;{zx^QzpMFRVT^TUV(}E&Qw^)^2zA za)`@)2^2uXN0jmv#(b zR5%fz0hx=spQwaqBK$3-{Q5*ES4=2X0_O9%C0-c_aA1VM&NWM#*2AF)yY)S)9g@KA{*@=8mbU#V@vSn*|bzXcX0HE|K!ho{qkzKvLN6FOlxU z&*SdC4aI%lDa|X87XMqypb0*$Dcuh{ue^3SVE+J7FRTZvCj??8*l0=s(+U7KN>o)1 zEOHwFg;FXGF9&-OJlN)orfWmgB=>@GAW`ct&XAF!Z>fE7CLbEO>piCfpYh^{RVWWkGAp#|uQ*oKY=-;1x?CohXLfgh~64<_6QMAH0V^+7jC@j)jX5F+fCn^@@eJWrRGq1f1; zd{%4@8$g^5p90H3zqi}lFlSM3@`G-#%hawhIsv7xIbi^=^o>6!c%nfxCN*nq- zW=fJ2$^Gd<6`PnipDfwBXWrO&=*~mcq;=OV`VbJYmE$#F|{dLtW#$|DtVEDqZxYNYpuoH zTq1*mL*Fej9F%r)Z7NY|#3o4FC_h zL+b8>2PCOyqM>~7nLK=6&X@H8g8ISvuZ$SG>ZsR0c0>OrbmUZyG`ypqBvhSSO1Aa_ z`lB;7s57a>BbnbUAQBcR)AA~yIU%^$gvfj0vR+1R^&?qvpCPd)_AXe~&=jc@y(#{T5;LPVKp0%0swE9R*5nv)^ zJz;xV;Y`#50aw=8e$<*p72QWUVPE1bX>=Q0vi}1TroTuow~a(adAb$|!%(_@ z?G^28866riU02FI15w@rK(yB~(vZNMiKc;13H0l?n46#qyYP}Kocx{=aF3Yyho-rH z7Q$iF;?>q|jW5kR?_p3N)SLo<-X&-` z09Hno?Cn-ez-)8{5k->aNO{9IjN}sBd;7JydYxcOruxhr*ehTb59Z;CP6UTr%>#IV zGdfaYC%mZHLjQtChY}3h3(mwKkjM4-0;h*gk|0@s8Wu6PbxMe+$u(BspO@?Nhk)A$ z4Al0r-QK3?^$X<)5d(9DDc~M@7!jfFiWo1zu(Fd-vtW!8Vip=O2Dp3$ow$-5I;?We zhyGs04>8E5>^!(Td3-A!#xHjf=hK=yIn}^OL}Un z0dB7bL%Tr-BicNMbZX1XJOrm~rztbC)`z!mp*M1K#4$nCXcncd`F^n3#O@f3RRHyu zHy6#M!w!aQu0} zb7{w%qRUU>tjT@LajHY?s<<^43<)DH3$--V!J0yqTAEnGb#2NbXX}HR5pUfzvx^V6 z_|-7wI7G#d-zomxz{B7hLEZ|@8c&bSE9YZg{7Nqw730_qB@e%P214$~z*H0H$vw%K z6pHsVpE-Nf&>scD3rX}n7`O)bQVe_OjGXIZ*B=e`X1PS)-4u(3^GX_#9jYqL{l6L_Sv!4bn_k| zlb9s&wOAdx?+QbvTCbcTDlWpzPzHQ)skq7l3LtBJfj-#XSJ@u@_2;+Yc8VWxOSn|| zX$@GcoP`XbvMlE2`l57FjiNt|+T*2SICiN>3$*L-L78Yad@2+)YdtGh7d`;nUTtm| z4Ks#^c)ua&vb>R~4Z4#g9lpZ?F#{xwI3S|*`fplPPu(g>uFuXaBfIcougVIjEQ$wQ zI@)kOd2Z0^$|LZHglj0-jVV(@=G;@IP$>eTQkSNEB)HQ~DV7Sd;i){H``BnH{swU4 zf$Fc-(LH7mlS`-LLvgJXmT>yFSX6FPA&{(4WBE@sX$)q)S+S8@sPQ8I68UKqabH_` zK0J<8B4l#+6LOs#93tt#$xC_|B0}#(#m|2VRVVjyH9=YyoS=$ZvK-|IG-naEmsLQD zd&i6g`p8p5ZnMGsAz?j;^>(~i>~LzCE+VaU7l^)flqQ{A#O^n7@=kLS8V!PEmtml4 ztAzH_^)EJ6b24aoU&j0iYmA_!^-z84fLrt3Hb-mNkY_PJ;?)UW6zmV^;4G)Q7{qq` zv`qs2*3v@YBnJ1Hn1KqzsuRdky+6cVNp^Q5Di+UENHL&sKmk~Gd=mZQQ>Pmh89qr| z!^q<5&8ha}k>yl96F}?^oRwFFF3@hvRv6JfrJEGiOK_X$cfw`r&@m}>*RQoJuXYzS zD?M=L#Urno&iNyh#OUQ@D%MI>00!3~zKv4`1K5HQrq?H5BQ=;j6};=3S>EQ3HGgp^ zGa#F#Dws@xko+qgv^EI+h|q8$X=YE~g+0d~2(Q6(a!NS6)%ysEwl5ov=aDo^+zb!T z#~;e|Hd(3k7lRYXNm*J7q=@sdAb#QH-n}CIT5~2hs&oK?W z?*fH8+~MPJ%7BtHXvX#L8gd$bX+Wt_p_st;Em+6w;B`ZRP1w?Bq@ zKJXa0=b@*C1Snf$k|V@#~7mg3B5(r2Ls z#~AjkM``x8qP)=7&dQR@ajlZp3QcM>_!_`g3cfUh2I%Qsxb`;UjWcLMlmY*yJK&(S zBX_=dg;%C^RIuq>`dP-nDi@{PJ>kwmAS!~6(}R13B3+b30@jN2*XBpL6#_5wQ&V~X)7bFZF2aUU|Dug~kZ zGwFb-Vc$f#rt=^{id#FFW|H>8;pv>wzxJ}K2ZqZ*&Su*OkkoUF)pzDKUG4w=@EFpc zvWoK6Ow>E8S&G)eY_4T$fJ8@>B)@Hlsqeo4%}1e{atNtaAyO)y(tU+*p23*Wom@o4 zV3V~Qe2#(=Z0*KR-aJLczgg!!Urnlzb@ae(tptYPg~7Z@mNNl`12Wh6DdRn$qE0En z!Me`A<-?rO90i_iDU8l`;k~f@ZkN2QHHk1S=Zta90K2R;Y7GS@ygWU8XTSTYGR=}jTzAUs8fL>xG$W4br+Op zdgcXPVJ9jVWR-_)#GQhUOj_#*9(EljhbqM)H9k8>nnN9z%tiyMF#dq@{P6U}($v)P z%x8H^faM#MGU~Pzg)gr>ZF&nU#_KrE)ccmhb2sq1Zp|m{O$ld@6pAK-4Q|vo72o7> z+LFWREC|7e6u%1vqgRMqtkKGN-BHl<@)y7fR5vybC#{G1Y- zDr#-`D0cS4S`?;2G~(>C(VTZM_M#z$&|S`ycwi1iHQJw$7Is4I{} z3dK%_vh>14h7n#@4(7ZJZgCkYb@Wy~(hB0dgAOg`hsNRUk%*ec^J@^hscZ?HTT*5F zoYhYh-pTkMz0SwJuzZ&3=;vqpP-`69+c*TskSP>=KFRX?sZsjYksW*JGf=rPcurK$ zVuh<%r>v|LZk)MD3M}Pw~tyRp#)xbe6VK=u(z`M?ba_tHs^o1gCc zi{-KmUs5{JmAY(t$kPkf^ezQ2CtJ-FLYW(|JOKdQXCLp*;1@H*V1#Y0heipo38my# z*Fi;bSo$fJ@^~wyAzEgE<9de|X{naFv(w4oPOCa|75kp`juoxguL2SRW6Y3m`za}a zeIFHP*Wk;D_}rV44n%}yQ%AN-Qf_{{9N5QKNi}D84DQKJMioaGO|MLn`qflldRpXM9TAj2Ym{8n?KRh{~&$=?0t-?45#JUfh|IaN9p z8w%dSvJ!_I#RU`3IS%hIq2)a#(**+>$QDIT>>Z`s5R{N)ro8cNBER;S5p9U47K_wq z|JKGBR2H|%k?PZ`5@hAk;jtzZI-M7g95%h7?woLq$HQ{5aEge}3%*#jy9u5py#7Qn z5&Q9+}X_tW55_-2-9R536qL;Lt}&xp+O_#`w~wxd)OJBWl1&SVy}|c{)i2vo5Y#XG+0pC- zIRwB!hHlz3*&N+-_!=WXsv5)g{Ay3PYltwg@xYYH+axWjp#Pq3X6WXNeI&wwHl5;x zyC~L- zeL&7l5D>t4j%8IZ|I4|6hdrH0uP2EtCNx_jj!t$8J3@NYxdCV|vBPaFFcKkw85d3- zX<4?D5|q$A*6eUN9BUamHQ?fppQ5-)h!*p6^1Q4|b(TT(yonM(=G z;vXr@Z86e%7cI>TlvQg&>|J1mjJm6!=n`gws^7K}A8QboT^{_tk>?)msX?N@ChNhV zB2|Wjdt|sYjgfa5zwmPf#sYe^m_X`C$OlD?A=IzVU;_~z-=2w8Br?F{)o=Ls;~HND zaVkD6zN5eJ7Dz{mJVc+EIuYs8NZM7oX`(2$8hhU2V%A`a=HbDqy<74#+4E*jdqw^? zs-L^?!H$Nr3gZ5%w9*jJ1dy!S4R+B`0B0@zP(ypLx8Y966lp6%dInaw!0ar@7rJ$? z`wq8#F>*K5e#M^(E)nh|<=`BdyEOZs;eD;~=X-$*OnCY|IK!~A1JaU(bXlf@iUy60 zNfB}jX3NDq*L@_~Pg7v{1ALY6xmZnC9up)4wh6c}2 z2=#Uay0Jbt)pw*BPh0Oc4~W{uvvwUAMe(a}mV%x4KeRWF&V6cWL!52GOdr1wiiI== z6|6vLV0Fv?BQKA;%?a@PKLWeI|B`=|vd7~Z8(HrCy7B6dMf(;K(i@2o9QZdj53-&} zntV?lo}G%zy~94XKnnZ7$o3ij8z)5EH+e=?)k2Yr@1Op@XWd>$;(CrmV=Bjc|Co+_ zRp2QARXqjPDX#SS(BI+ zKk59Zz($nJ0G=J@v%pXHmDlCEj5&}V9lNO(uzCmRd5kb$3GxT)vAEd)wPHz5vm8mX zkkbIKGfl=B$28k~VX&~gU?|hUda~3`NaN{Z9~DulLy^FlZ<6dN&@lODQ(Cr#*r5Gj z0$*tV01$c~H{u3jMB#L2efHqBZV+DOI)({4J4hiA=4hT_6oxNBEpLsieX`YY?nl1* z@6EF-d>NAnHUcIZC2+6Scd_JNX|0YG;bByy2NxFW6od7(<)-=nm%k(!nz|Gf7UVy^ z{ny)<=Niv`0iu1hg~d{jNCE=mjmKEBi+j8H=r;Qf$=f(OV46zl$mjNDGzgj;6{vGPvbNzS~f0 z1ouErHoz%%I=I%yAPv=KI}Og>0GDna+J}noKtwNWN{ly557UWOaTWUUN(GaROb7&} z@S)=RPJV>9g|U{%2@ss_h)o2lL?jX!?twdc0}al*h9QjHt}>+&~4`5zS5|!p*%+nD;FUUw#coW zRSPp1fTy5CP9YFnjz+>vSNyc|6e0O2)K0cT8`{(rx51K5cC6#Ur|o<*G*k*HmqU#w z%2as%TA6zxdtC?ix4O~3BE%Xp-OJVQD#ll+rqTKvWf0$~IGwt$a!($!|NSIGg2jL#j^4NiP}Ec9gvwd?RI07-|d)1442>1#biy4K5MdD$>D% zj!3Uf1Cw_$RQ2DlXPA#3S~G$t2ba%gu`n^;;3~pjy9#3*;5up;Z}I;dAmN09;9*Ym zJ|*(TReeaD*wOz61G6IC$Qb<{CYTH0EQ!LTMEkWi#ViN{L z+XU@#0`NM!EMB=VP?ZXc;qqz05v`dY&p{Asb%jI z$Fwcx>^$pksON0RVJE=EBuho*6#n=>J)Zv(zMP?MJHxFd@lbo73VYte14nd1ZdFiF z_zmZaubz!5)v#Po4#YpUXeN$eAl|J?iXVuX9(y)|vS z;Npjfyl~GT9U*x~ZxsR&^e5c2+z~Exi3vfCFa@LcJ`XKY8Hs^zUi~;1b1>U20 zJR|}L!-zd22uSVPN@ceojk&^HW-!D$Y|!sxC}Q0y>E~Kbx^Kt**_JQYqJ9Xft0e#! zI(~$s+?(r{F+|P;AhND}gC+k4I6VJ>9G85Y$e8{*5W8J&vThv>E?3|D#?x)VD&v|* zYnobbL6V|TUF~8g4?jPY85dx}i7yj-TL%I}8E}jsR;$HY6P0S`K06XT)l`tgq~S_x z^TfgHmFXB=N&;7Z2NVXvdKi@~zRL%3+S(;E_W;*}-=ut9P>)-C0klY{Dfw(3Ku`P>n@^g6mMGZWG{V45O8L^MV5Zz6go{m`mPeez`} zzr|0;=TdBxKdJB_(T{GCDDt?AwRAi0>hS=3y|*ExqV_abo(S&S+dG2ona8PjYV{TR zkjr&g@X&ZSe?tQ(6sv2tf{b;RAyY1QYs3fUc9&F3R z{{-7(5hg{0E%WgFE)ml2XHd%Ra4suJJ45*lzu{KtD9NRA2^bcr)`mdDN2i|@oe zTJwU_2Tnoj6_ql*6^yxn!R(d7J|8G%<*wu?>J_U0Uqm7@XlNe=vz?szH-%{3w>Wvy zKw+!4r_MYo$z3)Vz-$X(7|(=OTXDegq5xmrpWYvk#(0%1ozQ8-r;G*G#2uQWbmF6X zk$S>rCqqi1?x4Ol^;KKCI$cn2;_SE~v2599aO#z@#o8bay-9>UvA-Q&ed1Cx($+X5 z{~k&4Nml$GAg%ew#S*YIW>uGvP$8H$g?pS>8zxTzhSBW4IoaKDQ%j%1I>8|_-Xa2B z3+WeO8wq!VAv)yYhwwoxOefxKYml)k35)=Z6e2{rk8ar2ZHWC{;xQS$t^RG&thFiD zxLN{pX!ebSKcZi5mwT6%20kcZ3Lh*OaJOVh%*U2-tR1@d?X`J#n-&0t8gS=cM?niZ z*a@VSU!<}~Qur zWvL1RQ^8hBUWaEGYy!fw2Bbo#^hyfU^C}Iw?PQdvJR^zXi|bXXp&M%q!$Rh1pU@Wu z_&d&mv?NJ)vFf~h3KeBfrKPGKC{mTgoZO1cd35n9p}3iKYu+7`x#n)O-ZuY+`F-G- z;0)@QMn*pzNqh{-pezZJ#YE=tOiHclL5z}mLd`DA$w*Fw0=||$Xp@f*&c0;8AQ%mY zJfcoCiPS=52nim`IEM7h#<`lKiS7zBDzq}1txr$hFJrkXAnq515}m7)C#EZ9T(xON zRvsW1Y7@aLS1o}X5NZYX#Kl{ON%SH6@$aUb&lWil^^*n*yA`F z)@0AJg3x;D8>qaF+{^Rv2wg=$F{gU3FamuzK8sVT#S7(p2Bht7tyDmU;jvHa#6<2AEEm7O5Zy1PskSt&-%>L`Tz-PiwjZG8fZ* z(nIXdoWd<9FpN~pp$KsqNLv48?!?iuzzwgwd6uVxzMT;{sFCGN7eRq9RWj4er+h?gKD zGOBWCB8VSg0Q+Co%3Rj9DceJ_a4x6fF)>+g{Z}9l+K;g*aUf8#yACVc;mjA`Zo5u4 zmktf&%_DdM>yL>-LRPR$H_FhWgtJ7m6{+zZf#2^|zZkd?|0Q@Znm_LnI~SNiADaZZ zR4SX7qHro`$H|xksxsRJOs8X-UiPi-hYxHH!XDlx?dx{;(VrP?*Q*OoVg1jDpkf`! z>Jvb(w8H7r59R|ppC&)&esQ=}UqF(}COIn21$(fKh1LMK2K3;rmcKM=$_8npdM&kT z^iP#>j6);+usoxlJ(|UUjTfWX>1o@lohqfT!HbsY01>v({bm|}Ww-Dr>YJO&VStSi z@90D$u@Ro=kcmb?u*$JZLC;v0}CgyeFM?})1MEXnCC@iu7nxZ8Va$@I7BAJ zVnjX+`aCIsDZy>l5 z^iwr~&lG8GTgqc6 z4PqCDDhxM0Mo;*fI)S~`kz|$GZED)QW&8btu-6|lb<`=zj$MSTR=Wl;_cs*WKVl&q zN<=+*&f-oY1$|35w#mC-@;$He;ca}%UplR$ek(wJ6(Gls1m%oEf^7`6&?jC4IeZwC z;uN3CvupU6i+uecG$Y0(Y>RYvY1;EfdS~5RRvw2}tfysk6t4PF;yISfLkYDkZ(%%R zZU-^Nv9pkZ66c&D?GVH%pxbgL*e)7KRu_Tm)gR{Qoh`c^Rfb}9(A{g=1>gg*pP0XK zJvUWAk?s21gn?B6aocHo&+H!TlYiq$Uzi~P@hoa3HBwRbg005jm_xkoSEjx3>D1c^ zh6`LVSiKocw#J?b5tKuylvu6&9?iNtrxNVALpG_+S6gSu&iQgG_foD4tJsd~((b6e zc5Q_qbfCc(;(wJ&`Q-q?-A0nz(Z1U}dY1H%2W?ZV!B=;tb3Q0J@6cEUK}vS$zY;TW zq-wi2KZdS4%hUx4`lS(bvbi%tW}wdd@PpYAurpC|Bed{;2c-#RnyK?OoFF<4%@M>B$ z(tg*O^xHT15Z@#3fgsw~yT8E&24>WIlksBVcfKeHXJUR6{*c`vg{y|O{3B9g?szR& zKKXr!b~`Uqyi9F=H|nkFEfEHdWxL z?@|-50R1#JqKa=B@lG2dEVpf6iXRN~iM2H%ds}uKpeaf&^bQ79@v15f902vK`@kME z6jGxVg4Eh@l!5zaHTQjOsjgX)YLJ^=3+!1JJz~0MolBRGaVMDFZ11ZSyUrX#uzb+@lUsgh>a?M+B;jh;uD7`t zZsp117E2?bn$@b#n98y_$-|B$x5B+5aU^N& z*ZSU#UfZ{tSt7vZEUm#$UHQaPytAF0UfxGerdNsiSqf zpu#}lvzZwd#f2apr3o5D77)7|tYp)n^`v%n;FwwO(#&2cNA_CjVs4S%>Htg0LN5nv z3dR|F{Ca0w1=x8WxJ|LEKsjblh*DFpD>yf>;TR-H=A2pabXB;CpqE=H6tkL^VvBl= zuBowc@eW4~o7%p6X64xM@b|n(P8aLTpCJ*+$L;|v4*pY-S@J4xDQ_o`l>;}#EM%Ml zU2kE|GM`-b_<8mB<@g%|F4}jurTmc9dk|$_P6T1ZDAb3aLUaBI5xMYVZ&nA>=I#Pv z{5h@v+691rs^~2nM|N}4G)y=sI-E-ZhRpB}&u|r&11FQgqY9G>=@u9OpNdr;)vdRQYHqlo3d{?rzl^tf!^7+_PuD-p2)Xyt zZ0m^Hs0YN?0hIyb=b070rUqA>7ucyF2h5J8fPMKLnAekN!Rg8HQ_=G`uURJmgLt;N zNSZNC&$1Y4pUZx@@Baj`lEXXNSYzSqb^Iy}m?*y)T6u@HdeeCrM*L~V6`GxY49hN! z*`i(SzbmaL>{FJeyrro{JP%g^G0-j zN9vU)QxtySY)eT)vNm;tRkZu#!NvJA&^N0d*!V54Lke{rKU(sOsckJPu?O-#87ong znP#wts_49`PD=Lv($>_z6m|r3;+Lq$^PYI%HtDD5_z!}#8T>7vW6hQ`BiQY0r}mGv zqFD?`JJb`sY8oStyNAhD#ks+GLdAgBeDR&0AfBRCWJ?YS4AAlWW&&B9jR+wPFg0RH zSwSL#Rq)CN5U!troD~C_BIDIl)B1_h_%)K3HM?uDK;V;Q>}?j(35+sSiG@8;;>v%) zZZUTZI+@K-Eya#m`)No|J*OWur}@jEtGNTsk7JQ!%;K*D|8!3phLT|ML^EsJa*JNj z!=ZHmEMpt|+W4@D!|*c*j35!b1!;l;&sEkbrubm|F$w8EKb@I}`);I-F=wYcf`}Z+ zgd^oL8`dttIb2-)G|98Y>*9~yzae7=z~^Mdv6-3LO&6kK99X><3TfJ~@6&&lln{Fy zNG=SHzlDn!4zKAX*5K+DsuE#>u`Z(@w$Izb=+j>)7{s5>)fe6cNS=8#mGn>DeY@QN zk7VQA!87;#LjqXSX2~=yx^wZ4K5uu7M!$@}TNy#-zX`Nt_Kqb$)58YoyE~(UXI*lE zm-n`$;HUE?M+pf;{27bQ+whZXpbAOBp~FOVdq_Lrw-x{D!lLH3Dw7q7=F{ql#n+Ss zkH74@j}*j*|0(@l-GdpE{vEvW&<@8VBC^pXJg!MAfwB#JKdMLoGwBkqNF6(LUc5sl zkntJnOQ2--_GLPU4V&Kpy{rV(?RJE{WF&3`gKt}2z`DoF9XdhvaGRYPf6(U z;hFZyC_|&50N_Hj-g$qnkC2u)pc|7T;X$h6?b^{JGhV5F`@oHUi7NUjy-7X$9%ODV z;L?+CM;Q>fC2ZsApY_)ID9f$JXdvywi6dv|3%A~O+_%nMva5=Yxh`$u@ z2z{;IboH-`*y*Jhbm*?I3%{UPH{>pj*Pl*K5V&z>DC`O?G77@W`yr`%Kl9){f&e@t zE9^k+Ht~Xmn+xVQv{Dqg`%8_?nvO)t3R`qanx=T-j~}Exev7)ML1iG zW*{5zLd^|1vdg`9Zh*Ry>jiz`zQI6LA)A59XUYFt9L-?u7l5rs>v&1Yb&67ik9jf_ zxiUeix{h?;finI7XPcnQ+wUn-NhoyoF1`^i!xk~fd|$k%1%c@KjUII6g5^mR+ zZ5}coa`o;FoIQ$QmAwP4?g(zIh8}}TpNWhu>0Jn>bpow_D*sYhB5oD<-y(;z`SvF6 zI`+Ksu>pYMfY5%5L6oIbnl!JFf8+CZV``J;htuBYRv*fvFp=^MZ)i=vDlFXF*Q;&p zk3Nw>%JM?0e#E$*jMVGG1(g;+i1wLtyAaGUxBm8?NH>RNu~!8z5YY?jWtJFny{6SB zl+`0NzP*=6ybvfI+u^h_iowKiS&!JP0StAgJ46Mo+vDo2*3#=XwdqWE9#+~{T4`)0!b_9H5z3_UXR+eoR?qUdbQ5;d4%AY+>-x~dY)$@>Vk5waY4l=F2CaUJ zoN0((zlj3zon);QW8-uYhH`6o5Ip!{o74%Tx_^>J<*fn^@HEl}b`}B>D|z|+RNjH+HV2N%n?$z-7NjxoP$>Wajc<6Q;EB1UUOLP? z6TzkEmt2M18l!ZptOoz}H^tH&PBZPtG7hT>pD>CY=v z;>hY>c|bQVA>3Nzbz(jDRG``Ueje!c^CX58W~?QchdR=6Z*?ZY66ErQ@2(#wGsgET zkP5W$eJht2(RC6v(so~Qp)W9d(;pFzTY)MdL7YCfs7%RILoS%unv6R|LHRS8}Qr8N}!&O$*r9Xq|{zbKh0V+ks4xpPD$5mflJinWFxZ6@mrfb9kO z%RAs%n_d}UVmsesg22s5S*-6mBO?Sj(nnxus??{vpR^~~Q5RP%3y6Vi6y9%pzI1?T zHW4BB2Jx=0N?CGk>x}0x=Q62bV8g}^8l#c)&GfIP%dhb}>ltuF2WoI-TBvFh2W1XM z_qn})vAyP#Z6=)hDpb4Xc-D*#y2|Y_|1sY%V(A1R-gfTiHNdqJ0W+(Zg%!SK-j;*7 zW<=Ls?@HV$=qq6h4KMLGr=jF(QxM+{UX_QGi2ZV;kEX{d`;EbpkUi#|e~p@ipFzhA zMP=+*-s}QX!;&ca&=BG)&W}QsW9=l%hl1Z5K;=w%yEE71kxMS%j5H$libY+n3{;929d z(3)jC4Wv-qKc|L$Hp&5oaPg^9!);c0fR+T)3iT*qRyAk5fLah60h*DlC;>NOOv$A= zi6Tyro8aXVQJ$}%Yikl~B-2FW|0I(P?7+ngd}X=RFwTD8JQ*V~F1w;YstMHfm6lip z4c;}rGKI3ITWh%2Oi3~mhU@CbfXdsXxY}r0s{FozXEe=Vz^y25BDcK!bOo4>Pj*v! z&b)X=9cUu!St&u~CmCI!tc~wcsi0t>dNb=$q4ptnxQ8#_m9Ea0$3MQf|0uNToW?OUC-JBrTFhNU58t zeMEbukEIAv+0#Q23rOr{D$tGz%`J%nA5Gdt8*GM7Ogbb+iyYwG`=m;b1Q}u^QAJ8d_vy;z*)4sx#>tTB z-~i4??CwBqRUh<~{v3FwPl#=oV10TVw$lxr6cdAC{vEsC2A(u%G+2~GJ}0fd%dIU< z@RsQ6OXkN%SgaIW&z0?8H}Qr2MMvXam>ZMnrs98fr0j!9DTyw*e2OotQPM;ZzVIx z<)9(LJl{s++9UUT1-A5y{@4QMU2)vhmIzXh#2j)CgSAnqya6~^wo(uAMrf~1Xx+XA zY7}G-Aa<=b)}v?hHX+lD+Q()}D1W8Ff$0cwrpkYtSHGZOp{3Z`(!u z38Dlu><$~4V?Fd@Cn(x!Or5~vFXDQqm%CD(G^1O8hx-BklJPH z9Y{MU@XUDqxI=ctzc|;2-8q(En|B%uVTmdIA)I(fNY&>ka_H)9?#1zxGR`Ex7AMKl z1A0_xP*l#WqHUP7jhNdjK5XN89uDOE^Qt){5MsRTbREOyP$^zN1FsTGxN(CmYZ0{( zY5UWpko^`CGx~YY0%+JuksSI|aom6QqLW_`88O|vkV9vfe3>@oM;du6Gy{3@@*^WQ zs1z^zl|<6p*Te!11wyQ#ABE9;)B_88`pfn)KLN5yDwh+=AKT>|>@36r8A70w0<}B!|p; z<7fI_LK+`2@mV-03ZIi2uZ3!7gWI>H%Uw3FLs7v$2L3x|)p#ed0UuHI6K~x2I4qUgKA>jF2%*$X~5-LiYa=fB+h)X zGkX(2be2}TA#E?7t}#glbfhcbGT|@;Co@2g>)UI`5_BbiU{A*A)f*Y31>gOV8J>Z_LEnsuYxBPCAC!HQ}A9Ak46XKC{TB2O1(KGxD;*d>)B1jE)!!Y4T+-;7n$$-1J+IU6F++?WS#{0H?kPti+|JCbcrhyd_?y+B zg2%(Vm&jnUXj&(qK7WlMhZ5E15GbhYiPI*lEP$swK|WQDGBM>jC|-AvlDT&NzW9PRMp z5mK_>);qN|qVU@cLt%0KeJhFq_|`k{we z21+?-zu%u1u^nA1cm3Z+%NVw4hP&=5Tjm`k(g&3rxL{`z7cx*6pphAlHb?tRAcX~U z4x2F;sB5ysUzpUW^GYvN6cN$;26!=*Rc+d$m0V zwZ~RW&3e~ImL`xjV^a@My(IiXIX``SX=?Qi&#J{A=}T)-@Q;Z0RGf(`Pc0Q8`npT% z-z6;+?&^HsLeuJ;yILIQ0M>*>?2xYx8bZ;iml1wctkgCKs9I86xdNe(f}o zo!7WSjSRIcXP%RuXvP_M9wT?3rWvyZ1KN^gH{nquVlp^*@iioA;&DF=0upR9Ojcgx zOx_X{@iQU^@&a|mg}d%WT;x_AIdPRgtR;oX71%*0pLY%V(=9Z|| znW!uQ4U?w)zqQi&4<`Na@PLB`L+@Q`hytH7z^O=B;hUVM>L4eN3^-nK*LOak@Bz}$ zlk{=*?V5HLe(R`ysep_9Am(Igh5|gkKHUvrJu>EMS+e#^5|r$y%-C-mjNl9{xE^sr z%y*Rd0J++cYsYq*7|}7Yx^(c{yp$#BqIKXM8B71;DuU^!W4XQkPB)!EjS6X6r7y@w zGQ;RpaMy|X)-_SVgIZkAbBwKtq_IChWcZi2k8#R5O^fJx1ILqNf4agOha_(n?A~Hl zxKpF=VkVzl=8UwvxKX6Y3U&s#m&|IgQ=3)iCg`Q77q-#SeqQ$}?@F|{HxxGcSH#Vw znZv0HyI^SU)y;+5a)-I3E7{_K9*<*APgC6E3uuT+h*3;C^jc9E?aM^3wsz?)h`+~; zOQf#fm^aApZ0uyid=6MeY@mTGQmzG3PZ0H@{oQHgA-39lj2_Kz`|FupD!cM!-7|Tx zxxo;}co`zR+6_9fje1H5<216FwVn~AcOGf}_L&X|75cVG>;zvZphYxnFF_nUGsx|# z&KF0DOn)@~Me0+6la7YsG1d;y?Wf7<3#hUOW}AuLC#zc;`P{?SsXNi zvfi{eRVMZ%N-mgv5xLxI8~h_sl*d|X?;^WV=~1+;7+P_U`fo<3v8}^|K0cfxhBMFm zpOeW3dJ$kQmi$2jIGVF%%!A{u(HL)RBWS*cE|dS>A0dQ;^_yJQApyt!2|Wq8J zmjvFmQ)i;jDgI#<;`>K0D4PA^CG)R1U#=Ib#=Yn0<_n(vw6WZ?&$^?kFy}S&G2G3t zibMtlP6s%&eQZN0OwDO$^=ca1PHqIBJ>WG%i^y!>5q|~#$!OErNq+fIdp*2g+}3gyesvTdy3U30dd z9DYT!x+cT5k?`DH#0?DB)l514`DZKTZ;+grrIMxHE~pXQ155sbok(7&=&Nm%do+I~ zYmkg;F-zd)XUgHM1D4~y>#n-RW#Dy< zKz>i#+4GyB*mMTRQ%Oo^$p-kPP23`u2H|U6Wn_^UcF?^=!gM-IjJMabisCPw1M}%( zu02}qB-loUCwyYch?Te2JB|MRhq~d5BX8qL-$YvZ7teytLH_CJzP|bjg>m$Rw+fl= zJInH&6^E(=(qU%;c;186UvSS-ce~8Y%7emWQrP&u-g+}c+FyX#TD0T!#Fn(Zzb|d8 z+lGZq&B()?U77SL;t0S`Gt;R9eH`OqLi=Dl{vw#R4d(_kG(4Prs( z9C0mXFqU8?ad8}&tm01m#lUr4ai?b}4quNYEADL~n~ZY>0GdC;_hC*Hvvh(_V86Z} z@J%5y-+tc}tmRBcs~RUxhMZ&>&2ef@!(=v|#wYzdLSPvJq!xlD4aWTA6z>rciOU-I z-jC|sP=2p8kN~WjZHnO_wlS-leVYp|nDu*;T3P{usAhC{2bFewt0#hW@f9cdW%_49 z@R)#_824c@CE^pI_&8_8{dplrZ}*IgBPa9wpf}aydk+GF3z+gYD~}=k-h!JZSD=87 zt0`(lhCC+w*M(_@`75tl&=?mv9bgVVoXpP&z}<0VQ0Ll=WAqW}z;HMP4O3IB>@gz< zP6@m4TW@6!@+ByVw#ljjv@t>Ik$dL%Xxcolo_!Ld;Z5DZm4}!C%TmTYH6*V66Dv^8 zyQW8-UxCsA_uaoEz$i%fw?35nGvYo{m}=mXusH=ec{eR#xPb`w5!_;lq)5(H5>vz@ zvU*Lk8`(ad24g}nmzRRWTsVAj_|iOe{q4xW4{b0*d0_hava{5TN5?utU}8=P+-MhM z_+`%FD~iG;iht%4RE?5puanr(>Zz3e3NPkKySd&0aO`LhIqNJ1A556?HicD6`(}?@ ztDRxM!LYSW6C6gg6S|Ez;?AfYYsX8q>b#RLIaQ&*U(58l0T2Ri==Q)!q2>R9@B@um zOf#H9zSbOeeTRgKS$rxwAnva9G9t3wb#)`*#zi4gkk0v@YFA~WcMYBzt3TtKmXV46 zg%MQ*krN|d7e@gBb0BedmksgdAQh?*HTMH%1!$f{b1-=~K)51U{#G-Z0unBHGtE{T z_bnv{mLgR0EHYc+?LTbO(AG3rCFHG7R_x#9W`V<(P-lHtQF#SuFNtKz@D4S9LK^4_ zGHFyHnwYNS#}YhRlK0cQgf}m^zbI`__RQ+O=a>nw?uu^0UV7ZP0mpwo8vkTFN$-1w z6OQ1{8k>N(+(3+9pz&}it8Ria-PtQTF@v|iBvBLPl|yZAwH=E(=4#YfzsRY^Rir!? zHS$?)QaAgFq({+82dWn6h)lMZ*_s~gCAM{&MdP_eM&nA1$6C2u5G`F5tABh;txWofi{g+Qz7x&*|Ww^+5`M8FWHbgbOu1kBWamaHrxME{t6 z_Xi+CG+*5WNuA#owhs!4gsq>!%$qpEv;XcFb&mYz<8PsL!{oPsjD`-RqPYcvf->s0 zJLW#ebNlz+=P7OZX5=+>@yBfFtQeesj>XKwentM|ayt0iSJ`1W0Zic&Cd-IN?u~tR z{Z|{fI~B_QEsT<=P>5ZPF1!ax2}FnA`Q7P%b}-hxJC|}X!8?ao9_Qq3pYyt$%!K^b zI(H_f2~LyYV$F%!^s3wwqVR>@VU>+7W}6cCvkj46Ew$Q-=ES=VfDet*FP;l*C4b7y)H!uouKH&BA zri+$M{m_#Da~OKOWYa;?^D4&myt5hhSGI0F`spa6d94uUNG0m}3&gR2h~&RRk>{SK zS_Eb028vK?6$vR`8)M#yF21;2EBK!yN2N!{rzd)k>*jOGV1`oHB)kGki>9$rBnaK; z$F0h!S>%Ia{4n-GCE5irKk9~j+cxZ_qC2prr)-}vRrAhQVs17A{jm{}C*R~^Hl2+Z zh4LGN&dM>cM7>`quRaE**1MAu+{D7abTHZz(j0|u>0v^tq*z{r6sabHmgR`d0+-)y zzN9ix%PLLjW#T#!mu|rMpgmm>4y;?Q6CLs#8;+8PGwEfXIcASMKvkYg>tGG3X<5*Zt8f5@BD{GK=d6}8fCOsE2nVCw|Y z^Z?{dY6QDiI2C2vlu|j&63XH?*=$CHhK0zMxk3_<(+R(cO`=XY=2jzSkJ8*DDYpil0)hydmEYVOgxKi?M4tD2hU)_U?A$8-HIE8iN*($W;;* z#>T<5)xPoofc z!vGEzK4(DO>(0f}d4X0nKSIu;;}3pKj#ZH~xq(ou{Z+m{}` z`)7>>ROrFat~@sXiH@!T#%XsAtP14#jI6$b2twpUId>U2Im_aea(j7TD>5h5cap2J zfYN+^UO*K0=czBJ*u>+DutD&sd+xOh)i1OcS+(ou=$P3a@wdSmol?0gGdBMFpCy0| zX>`}N^`#!sp~%KXhPB`!DZuD6?*m8n@Yq}4OlHo6b{LGUj6pOp=L0nfdhPj+`lZu! zZ9AUfA*M@-n5<__Gk*P!dQo)mc1F^hFQ6&b^e5=9B${+S1zKAU0nq4VjK`bO%~9;S zYXU?AFufUBGaL*(t|aQDgVQW%3ym~^=|9tSE3LLZdoM8gzm&F=t7Xaxo(Y%xKFV`~ zoWsa{lq{5l2+tC8NreyVBi>LTHf@YzpJOjR$CP>^x&|r)gzQ$z$fdSR=z;`Bh;EPn z5YQ4TM?&i%inP19eF{j&+pq7|f?YIcDDm~IOkxW`;hp7-@{^la0YtdJI4fa6L63z= z!x`v?H;fy}m(CZkbxMzBJlnOca$~$zxcWAp9vDCV6pq);6d~Of&qmi3V8F(jMPQK% z{?2b`ZJjI~NTxc6&h4r38OLm-CmCC|kNfPPJ9*x`ndj9OArz>t88EobR`EfZ<^P*V zx&-eU@6>T6EkJqwE($S$D}u)?f>3MHlm_PGgbk@xY;XI4)HtI~2Ol5)QlO z+5f)(J3Y{5`n-DkrUop>@^_EmvzRoW$}B)t<>HK{tAvfNY&BIn0!8+Xjf9$9)C^FV zH4Ao;h43mzYA&L~JsAFyctm%hL21Nhj@+>MQJGJ?m~2%dDkiaVF4 zv$o!zjtugz2F1Q4lshU@K1TaaU3U>V+#Z;zb1TOcvVFZcLw!6B%+nw9+Z}{d1u_1D z5Rp$~h8qzUpCqY?zookkRBbMmb4?Jl5e$AcwMLE^dJ#D$*b3pFUW0-auXV)@h1yLX z)Eu3emrh+knSeUs5RS0nnfKcoM0iq%iaQf#B_x;Uc!yw6{1oJDF2_Fp8D4ur%Su#H zM)Zh|#0Qwa-(jp)IMhsgB(60pn zm&Odl>vU&GW5KDE{NNF-UJKU0ZKU}0%@cOy;E;p(m33rI8~g7}vlvG1-4vcWhj|b( zgMx1rKsg=3KRt3)+g>qx!PphNc+i0<_r$v~25z5L)L%;9%D#D;hq%!h84(M8Z#|Eh zBPMrsUvnoczrO6qx`{8OSp%*00ggg|Hy>A}df(RAy>CQt;y*5%RqN+5aqfvRHrO&| zG!;1A-x3|Ei7DV{gVKJ~@X7H^DC;5d9=L}@Dg(cpM_$Hna<&}cFZ~{%(uWx9easAI zJNAIz3Yi8LA*Wk6!_VnR;=l-KR28S;^OX2QvfgzRnAuegLI0Z%$oFUDN3{xOKH{-W zd6fZipg?A|?WzdqZ&S!Ed{zxqWG@@CW>D+D!O7#BhO(E>*3j-p7$&sk&eC^i&5)inXmPU7oXs1DE#Pc8h!~(tC zoKycbYC*GZp<$kG4@LrFfg15Q*%TgZ2BMATPiW|^zx=6E&3$233v6G3WqjUK@Io}V z&gmPGC8eQa{nHTO<1Ghs#%+r!Grru1QEPt;YjYxkd&5W}JP49yLSnrv((q{C-%`nE zij;T%+qRHqH=7Vcu0CB{t&mg>qqLVw%7a4vP%ov}`iK69yZGzQF_#gMf9Dyx`&UMX zx+fii#Po@1fkD_n?vQZGRvukP+-xj~q_;(Cuj&CGIsUIL_lexH7YUI=HnVD&ef+MIDeC#>_em@aq6?v13q=E<#POSV%kE`P?9tGc!HXr z$;0s7bJRAi(iq|JZ{Sh8NzFyFp`7n`NB)xLAm4eRiT93|^gtTzo-db$61^WzE_y*u8oapBWaNUH)KZH=N*y}JJ*&ZI1B-N+_;tJk`ZuzADq8C4ne;AOKB4m zG;sUBZAx0S3JI3fY#4;Z`@_4hw&5ef)H}7Tm0a!unyRlQM7K?fAGQk93nCg*Z~0f* zR6Oy`(Uwv`cO1OY%HF3F-OPhOsi0^*Be45YQOAsXb zr|cpJ7Qx&&&Tg#gkjZ-=N}Eo0i=g6dff#Rj$x5&cZU>Ewt39~c7;-2o52sAe`A_}L zsn~RBdApgDWgMau`(=w*xDqcTJ0N>S@#g6ap*zP%S|TWvzkRa^ncNJ@@wWIsT-{($ z4Q)NnnH6Nz*_h$<)NIe)a6Ce>qx2ar>p-!7n4?Z88&lW`j|SsG`X?V&2wcL>byp07 zdemh)zOJ)CVo_g_cJZp zAHq9He;jQ!4`s!?ZF==uq4RlAD-7zXm}-RcX93F=nBmvqMaQ*k;k+LX&H6ILR?2>j zZxcFPKOoF^iK`mm?^Wd)gq#DeZo|56CInI`k(~JfFPW)^c(_}pLC=GpG#t$9(OpWB zQTh?0N-3HHB+4$h7AebT&I77Ks>0n$u3?L)Elj8So^`#jBw-&)YR3q`8 zdb7Zzl2wCeDY9SE1&B3qg$_MexD7IyllBInTdMOU2 zR|gOGeKvZ`HIG4bD2{^mK`riTF`oLRs2mxfi7^C5iV}n zrT;33)FrRkh{6Q~a3kpuJImF-MsE`8vPh_)3DC8>*-dimbttv@t7mPz<9sxF$k(Gm zz7e}yNy328bHIH@0(!b3l+g!?tEWT*Z5AaccK6f_-k&2u=h-Zkr+Oa%4lvxyBacYm z^|w`p$_Z$%;Coi&-RU5d%AwFI-{PTjL3D{WQk|LIGV!!7J9eg--8A zoWyaBZV|!Le=?mugTSb^3qEX92r$Vf!m#8VQ2Ts*1hT%l4Ykc52+>HL&tvMm=WL}n zD04L({Xq@eWo%RU;HxF_cAV-uJN0!`U$pevJPnLzN*c6{s&N{gZjg%b)b6}0pUAgd zKettekv+8#qwP;RCeK)ym#aHr#yIvW;SA%yob>)K+JCyl$Ok<q1c82Q2f)la@H#DF0j1G-q1M z5&um_-6{g#yNh&Uh)b%JVp}FSw+=dzXC1C~BI~xwcDOjdD>BFKK01zjhI_41BDWTB zZEPkuQ-^b(seH%LiIzb1z@Ac&q39*qL(5gUaaTO{7$b7?$a zOB;Q(!Q5P)RyNU%#RCRsAV@8uj7)#M`q_HNe?R_dEkO&W%L`0f(r@A=xab$gbzY|# zpN?&R*h@#IB0h1Yuos)|17}?uX!FcP0%9S5Rky~W)>gqOsLV8bzo)FCol&qFIX9mx}4^aYnycsw|6k8XK+8pslcJe4Cy=U9-uYi(P2`Dc6KjuCJ zt<%Yw=SXa3|B+-Wx``Aiu2hPk2^%;Hl%;RK6rlo{`R#lN@&4M=SH?sK8B9zr=6BvF z^__xS&ZVK*-MM-0lXf%6Zf>W!p1FlHZ&RJXa{5o~BYZijp+~+$be^CR;$ZUYPxgfe z-#VU(URN|c%=a8H2OD!0r}btl2}bbGmxQQ4$UY3)ut3dkES(bWB4g2nL>C>Ro0a?( zc?%b%X$irt=OrGbSRHn*;K8WM^#YPr)|sS;{FWEF=OAF5<6sY3D&~q42`kk!?-Q8m z%3L2)0d{mIOsT| zrj9N@LS+um0zid<1gZ7CDkhqm`N$DKrmsL*(7!RI+w+N-OrLT|sHxqTE5%e6b?WP* z1T!^KPfB~OUv>liw+g+ueYb=5U?Era$Qx1^1g%YqDC^Z+yb`l_aKO|}11ZPGZ!=5L1vz&8!{0V7C+*3ZSjfcB z^WIcood(JWJV~Lu!A?lYN^9MO7aYZ%Yz~CTZbufr3xL3Jx03JI0XuE+uIh^4Ie7xd zG0qyWPbpFH?fD&UHf1w{(?A@v$$2H2)rC}fINo~iiF-^v1$CKLSIamFRN}z7t;h&4 zQ*{@ycnygxjg<0=kd2RYP6}P`}(q0F6><5y*HKP zR1UKC9FMJzIxIhVT8X$4uw{^;-kyLtpbqm5rV)EWW1=Ot;S!a{9ISkCn~+`xk8}Z7 z1q4!Hun0T-(0)myT+CtYCMk_USbFB8AK7ostUEKIW*x%e>nHru)COM%gfy!L+rE5rtz z=g-%x*~Cbk*R}}+Cc~xKjj>3416;!cu+%5I>w#;Z{g0L`0t%p+#qB*3B)>CU5t`7s zO)`B#cI<3wM%oL+I8;bjPc*DEnjLfo@6G6atPPrGF>7A^^>V-f`mnx(g0FPV|-G$KHTgjR|;HNlfNbq#in6`uANe`* zU$Q~pwF8O|8sqf+*bIweKJ6;D0~mbbsgG6`M7Bk#X2%gPb#e5yTkbuT<*jNgy|`It!SFc}y>Hj~fm=R#1<= zkXcE(ek5;Hk9im=Qx6)|^==4J&9j}OJ>cG{RqI}PyjT&{lpmY`qn(d?;r@@KxHYd? z=kyl)=>aB39VNbzW<<>oTT_ZacFpx!sKDd`iPWRFJteDGbBIYgvhlHlAuoH)NITqE zTkh<$7l*?Z*?3@&|2H$UlJh6C2Y!NVn> zFiL}h$^7tX$q;t8oT}MfX;w6sij7N}=G=)#^+jBWHdVd83!qT6wmz$S8}vzw!POwU zTsBf!HlUU&6FF_idsaj0&LQXkSpv`_Iqe7BU>)abvlqr@y3CVh_idyh>#t20MZea= z2~_l~Y0`9d>0U=qPF#;`Hb(*j6-%{>H&{)OT%MoOreO^i7IP8w%^)D7Ztl)HQ4G!H zq6JR7VUJ%&Ahgu^m@AJY7}2{^E=|wH@QPDgQkUnMRN26t!RC3Im|QBTTc<^i8i0w+ zuLp~okw1OxAH*P%*ZF#qQ5~CaqDjtg3zd)|wAw`DkQCC%UVl$JtO!Cbe(fIEl^7T; z>L%es9vpE$?g+hJRle#}W~og?VTGAy6KjMA_AC|kh2;q zAp!ox+J*mKSUw;lDftiN>Qaa$IzBy(&a{b`v_=sJkxUBs(d!xwUJlwz2S zIE5@+_j%8^$1?PcTGhN)YtIe+Ud-i&z3%|dCrW8eOwHh_akEBVydZtLO+wsa)+mON z4L(){8U8jOK>?Bg!+SBW$}3qtKjaS}zT7%coNS#xTz29V|v8OiVxZ4~FDIqWMTI1^I902n4`;~Q^9&OXbMeU_$xl8WJ9K;_1 z*nq{_8;b~=sd-dvGCNs-chZJ017J6N2FPQX;}2PlkL;{9quB+&XD@l@fw!;0Rs9p1 zePcTH(bl0M2OW>iKs_n7f)VlRmGfHYi9$ubsV})V>)B6z2{98?Z^8VtB|z!<1Cd10 zc_HKh;^K71+!t#1qMB^*m~I6-18+D$j#5Az@pmTatDAG<2d+a{*_wR*edE_^@1s-b zVE(_vG}ch5Y(vpQs|fjcxtF}07Q9<*uN}&U*l~X(>UR%F1LD)j(ig9sibvDGP^sW@ z5@I(>vxQ&Yi-sCpUm{9B>N-h4<+A{LA(TU7`sryRs41-vCzwCPk|H?jFu%Fh8 za2Z5o3YltZE-u;8+ewS`y7=@!d3DYio~~`*5pAEyz&Qy(y2FtwvF>!lGgwZAo?!K+8JZ-nh~LUiPmSpEfdYw&-F2!f8hqsQ_7`)CZNV??VM420kalXj@UAr zPTjO{6vZ%ST3{DO;<-tD)MUIemgXP46?O$&YD#_TlZX-#XN3w~6#!$cP(dnD@5W$J z@5U$k@hcTCzxDkb$RAupl-ijUF1|V16>h-7BYeuI*n(TcdLao!Q~e+Zm%)T&Ex0C| z7o5diH%|Pj9jSIU@);TzMznxm)aMAn7s03S2m&&PmUg9O@)p3V4M3#Rk8u`cGb`o@ zx*><~fBoc+dQ_o#cH12kP6TLCv_ySHfaaZAo_W@(v8_H8)tmMbjdHzsw7Q?q`PZv+ z+1=6815D=Fc0XZ9y^FF@T+k1NVt@~jitLAFR*9+GaYx>%>c2p_X!U8pZ}>3>7XcS5 zJY``D4gRJ~Bvl8|S)S$qwNjK4cz!;$=7fe24lb^UwDxI=uWz|X#&Z!_tfXNZ8-5fa z^yYhKhgeOm;yZNwD7piU+uB#E}gs1vZmps9*hw*l3vrooxrtO+p23c$ZPta6c^i965cJ}awPX6I1fYzgrtv27CdGKqTKf#brNW@g1Ki{Ncj z054X=>h2p151SzjcXh>(FuJ4bANT~6!E8v)ev_2L(-y4g`*fx`Mha|@ly-8c-P8%ZrVannIMTj+yKQRv>!SJY8cCR9*98A4~iPwe^qGrG;5uTf#+Mp&m!rgXI{@j-Mh z`I@Ae+XQBsN}&n*A^tH7s;ni>yHFrKppoxVU`KHvOZ>K4US7(bfn)Q{(-tKoc!z-q z00D*psvKuEi%L zJ+nBx+8(#fJ*Z?D@d$U1&en+9$(r$V_S>3E5Mw7)&6`;=JB#KQWlZs;2z&Ow)PSv~ zG1N1UWGrr#Y$1lvO~smJgAFJ(Pz@JOQJJy%yPOoEqtAPuU&J^P=HCIK$*wYA0ufT= zR#BwS$Y*>?jn{R1DHF?gYYvFU?sAD4BYf4rgM<>^N)qPpC}}YawT|h)j7O&Ete#z_ zLQlH0+<=?%Y;)oj(e7(rrI8KB9fmLtqcIGv*LYcT{+tC`T#Ow2+h6H_%x)pt_ z{wYs_PbC3(=cY&2mLhh^kj$`(O2!E`t-$2o zE_9Xct{6Nj#2L}k_&ikh&;*TcOW@q`m{%X@o3=dYaL7YA|5{?TS`Vi3$JV@Xlqb0C zyKYp6vPTbL55?g#Z&^IQE3Q>&ilSsZoa;uMyyk)95b%9It7C5OVR4r@d-*m#65Pys zXt7XGwOXeW$7WjztrYk3W-?6H5ha=&(NcU~TRyrCm3Ghl`I8$mV8^96l|CPL@Vi6&g|Zn zFXqbQ@SV@$>Z4FS(R)0q`riMK$(RYojy&sHPNzGjQ$w5O_G+!eO80Q(=NXE zYtWErTh(TV9oFNdPQgD|vj;0}^5Z4K`_xy{(_H}}#Dg1^>y(v4q@fuJz3s|JF9v$m z_G+896*ixI`VSLI8gwr%b)TKlh(@(pz5z4X#BpgL%_1yC>|e6Wul18#$RBJQqz@sk zds@#;Z>QrDl>E+ob5Q1|$JJag5C!7T8-13YFwf0)DM`(Bd1lZ$W8;<@X6R56W#Qnf zj-T>AqP5ntc zt7SXngnFxsl~bNgRp#HLni-mSMzEY?5Jt4-0ZhvicgjGCerWuB2qT%887#tvy4#%f z2L1r{$Oi?6&VZhP8^$S>F`kRqO9BkHlHcx($dF{FuX=JnsY+x*4bnD z7k4tktkLzl8dD@iLx!$GKz$9?0LIotG{f=F;1OzONr%!8-Boh)H4x?u%+ti2iqO4q z&D!4_1PNlu8kwtyyI0{I;m6`&V=WswF>*Lda6kw8wpDu5&_=*z7jf8e=pMRN0i5jSLx}e&ZXHXsCH&PNja9 z!KHb_ZP71vsI&$W54^3`W^Em^_E}h#)JHQ2O0$8g6~fa)QT;U&fwth#lp_B)IGs~~ zQb`D1Dqee!oP8|h!Hy^^>X_~wp)B1bM(P09N}(PQsKUcwh$n6kOx6>W6(aFY)a&U@ z9L%Gr7&0K@xvrW7m$3luIF*PlWuYRvCNiC?_nKxf^ z2~G{}mO?Sz+^dIgLP62#py`brX;V(RmRPjl{JkV6yi8C~hx^LAi_8UD!iJq6Ca_M; z+huqjr|XCHY-6X7oA77qzr>I+^8AzK@NgqD5I0fS`2Z827^u0xwh!$C*cgE^qFt$b ziY}Ca-qQ+N9hJW9-x-op1Jo6~anP=G=%{j9mFzpTgvMxakDxV)jKNBkhm9+7xYoU`3KIOdt~3o? z&_xK=1hnE610*Z>I~XgclPN!z@+3%wO?|gWvDw7O)1BF%K)5WknktajA^O9rG2!bA z@16WzO5Mm8HyQR;qvf$jGt?p)BFYCcpUh)V6`fKY4_4^(5x`6gGJvmZX2R;9G8y}D z6EwwWqT2-UH!Hoa5b*>XRo`DrQ35M)^{FgqkX~@p78Vwik8y)#7FbiC(s%$wK)b() zc50{$Qec|gkeKVEOYh(LL|Ne2UHe85zIfh5!lLg;TdXLV zTwv|FCH!wtXDUr?Gb5+1b0|!=$C16{Ev&j%hkKFTs>hUUU>}NPqr+Gm9j=f4L7%M}uvmU(jnn0E)+f zCPbgyi?M%wp`fZu%K}r&ru(i7f4dYmiWz9zUP*^`fA7ldP~W!1;r^rm*){7;U!Pzr zaf=kxmSUeRm0B~j8Fh8l(!zj=BvpFUy2O&oZY#|lH3TDV=lp`Qf>{SXjJ<36eD`r` z<)=V#kRjct@r3^;o~N-@(3(N<>vQeTdL$wSLx_L(M6Wz69g$b>lD@-GaySp~^>3W5 zBMhT|zUjC^I`L0e4;pqmc{=cUqd(JFoC{kGxYXYiGq;X}Y9sWx1#6CT>VP11u8&Mq zfpYfyGLvCK^=@ZySMsQ@MDfx`f^)i8?W0r81-)-~NplMsUd2}6ZTo5_BNr=7uO%`3 zE7WhQoNjCjFq6c}a+mklc-PV+jNbkEZ_>{pi%jl}mPVQ)!=A)SIE)X$<$~0y5bRTT zPuY%E$DfFxO2jg~j*%z|7>==pU9vRy46s%8%wA%PCB|{*pqdo)Ir%Rle=183sKVaJ z;6TFO!aS=5yM)H@e*t`k*n32d4I)-33fdqQX7db(z$89eG}Fn>$4n3yLHqjxxjIx6?=S;w z0d@$Lsn_N=A47c^m+~zM#waD~eKRe(be(rGl`&f`R57H5oP;R(@+tAM;a-U{m7VV=Bx`>jM`3Y<{eB#)aktrHC>QB9r)KI&zS*Zzv%CRl+Lut1^r91kI z-K>!p-t8kUpvll2xtKi@oAmw=k2j>70$cproO>g(! zqst6;YA>rmxNnCkjcwHmFn^%o^ckUFBGaWsc|zQobe*YmYHy6;Nd5AVnV}sGPuo8@ zMkg`ZO5n?bvvoF({5j=MAy-;m<{TqyN9KQz8#SZrr=udv4^l6X+4AWtiux6THjQZ! zRib2MLT_r8BtAJw;hsR{siny|2>c$0$J?KUqD*Ut=F+i#6%GM8(Z>2~u|3?-PmqQ@ zl4f{R6Aj zFcZZo;R=Z(Uz9QU6(->a(?JM{DFEn8sG*Iq`O+#%K!o_#jgIfuzT|!`o;;kK`xz9J z;I*2U@?IBBv5ve`PIB2=&DWk62}OyX;5OY#3(N;yS%H%sx?i=daJ&|mf<-8L>=8k# z4kREdZ`^}51JFj>y}Cs{!kHH_AAmYw)6azI6~-yU61#cC@UvKDD?ia**8C~7e{Uy2 zCWByQWf>N@Pn?-{7Br*)8|Fu>--{YYspA|_rNDWG+;{#}tpQP|V%z-FvM1A4U-D5% zHAUqmU~OMZ;-tm$sksYd?9*7(XfaJshnO|m1#^rqVBK#uZQg)lPK6{3<=m6)fGVA8 z75}WNHqeXCOTR_vo(r(4*fX{qf6kM_jcZa01xm#@oyy&F&z6}iqUdED42w~p#oRt= zT^>He<3|i($g3)xN(t&|7q3XQVyRqeQqlk$YD?B_lt(_kUF)hcUNg5(1=AKj4o^4k z_)mFNDwtwJ-%kx6EqOZ2kti{s=Q7xb9N+Y+|RfSG>X+^{ZPH#mQ*u zkXZZtHVnlDV5{;l^PT$qXhhra6oM|?k7||srjKvbFR-ql%AIa^Js=)sv&U&+JL^6B4h2Bn z5e6~$BrKP!yL4I^?acn>XZ4*5itd=L$}C4` zH-gS}W}l>g_Nni*fo2(%%AsYh+&y-HtJLb(}D?TF5PvNXdWT?*@5|lW_@mRz`mgS^Ptgzrx2b- zX(ViyHqLxYp864S)rHAvNsJ^=G07zX63vl={!UO~05`bSGX#OA=94&`;X>KN^54rC zQaHDEYn!QWzX=c2XMg;wB~p$;I51T%)f_B9dCx!V#h%X!P{A?Ub3Igk&!C==oCdD(a7lAIAVuE)$g7?hky7~>T_ zH<|LDLR|yQye>F<#Q&_Jr;QE}U`%L(-{CY~KFey~#@Q3-V0r&_Q(f>qX`;-zDMc?t zMNw?y8rTY>h;$$4`sc&^GXeWeeZsdrcShzNA<`@vpJS7s1)RD7cSVYv;t64izZ}EY z#f1VH4+Hocb@Ft;VxcDp*&vSlckz z>Zg|;-}z-XKsnw3=)VPO5KZTQP%$eF7)7)U{*Q61BkmLU=+y0NwdJYNC>3V27uatS zRQH4qNA@O-+RnDwGhA0{-BzwZ zY^X9A^PFsg>(~y(^3T&byWQa1dKd{1;jO4O;`jEzIbN4_RnG!6sWW``=T7EXGr#z~Nys-$UKn@--^+Yl+Xd4Mj zlcBt-rb(f+KEffW;}=9@e5sG4@gpuvcIrvkLk*&|)>{d2qm#uMl_V8S0UG-{qplRN|>|BgG8g6|f{r{kM zOcv@Q1&&&SBn}GtW;J>ra5NI(b6XxPqTr6#gt|B8{>2HFk?Mw&7N!g*Ut&G#*Xw{V zPvZ7@@|UBlF-v=9d!51ZBARp+6%%K7hNDzC*|xsujyN%t*6$EP<0CJS`gRk8)3FUf z9hh%9wt)j_i8%^1*hP!&T2yT0c|sf2VIiuG)Cw3+tZ2l2(~HAb7AbvtNQyNx1D$4q zgRkO={+vOXw@oz5^5~A-H^^!3vJ^`KShD!qDJDD~^V6>eW$Chkz+@@ocC6xsYUI3) z^Nn!k%J5+M%$X-UQwC;@P17S&4h)s93{s<5k-J$HY#O=u62unj#ar|Ve#UYRIh*%_ zm5;)wd7v?RKvz}=?vUn8=^0pV?tT3$0s=Gvh>QQ=Qari-O3G;Dh$G zm^Q**+YgW7#RagmEhBKY(l;wlh&QohkA`iKq@hBCt1M_pO^voLJAF+ZfDB}zvu*_moSGf+)?(x}+TpA~cJ+29EP6rSZ)ME7xYocV z$%ov?^01r;oH1kEE3tICsbS9igYWgw=BM}o3(u`z*|rWfP18H*rM3LKN2o0_VM&c- z+JtS1sLs}oKQY8_kOmA=;(v(L61M%=t>FFpBjA}D*C+=OxU3Rf4~?a!v&He_+DRk^ zGWjzR_SuIlB*;T%a!W4OVb4`u${^#?W>At5-U-Snk4&PKqEugx{=bQJE0g%+zoKNk z31<$i(thv?udR|%fQ$-F}){^f-;54kA$V!XK6eD`!E8A(pHH|ck0-5 z1PaA3|1zDsR1=LFzKDK>$36}6PAT}N{Ah5U?cZaEb!oFarLUq)eQ(mhKe$s7-2Y$E zq;ZiR8X`wEfMo5(G@WmpzlPxtnB1k=MprD%MC&lwa6>ex?@W3Ebi%VwyiiFL0yl5; z`_h=kZktcaD7x!~xHAX;rn=N_!U#M30zBhZR_yR_NU;U9W=fxNW%#GJDZT> zqa-;7v`=0wymC2NF;twoaV$Sn0%>}*?&>38AR(QAo{FMXCqo93v&uzOSEG0kljNa6!U044)Dp`8bzx&> zshMLJ^vN`SRZ(FNYH#EaZQ}6ozJe_6rYRv8R+w-a$Ln6KE#vzb z#!R4;J@Q;|MxlxDrd9h%zrT)=FaK6RTVIQ)ND%j`E1qtV=_3~v3bZkcp(aUseswnO z1K-vz6fEkAcb+j6v&KmGmg}n{Mjf84nf!PhI4tIS9(6tGUA0s9nMzqU0&SRUpWluV z8!!&Qb^b8k3e{0K>oZmP_r9;fr2L+j;m>DT)~F_@n;4TlFIbH{21A5*iqoX`=EQ{g z7H9AoNr`irj{{=2L~2?k!id`YHfKWF#rbU#uQ7F|yf0 z$tQJh%Sk4Nk0SM&H3}L}go7;y`sN(dwAi)*NLvR}E&4!Zy7b8CE#laUu`!Wp<3Gei z>jcg+T!^UqqB^^9dc#Lj{Gw78*q3A<_fX7`Xi+Hyt*$)G| zg(i%)X-F@s7X5PX+w^~GJ%W<2?0mPU90Oq_54)!5X>@REYtb5?b;}}3SsGy^lTDm& zdfe4WPa3$!KzYxyjPb0;H-OPQcvvT@EJ*_Hn3F|HX=-HWMij-cUCTIhww*)<=ZLfA zZOa8>h;;|^{j~acO_M^X$CtMkaz}^d_r@FAqq?MzPqMMz%KF$)29?sEt|J8~%q0p5 zK0^=lT|HIFuPWDV z8Ake&RBdR@c@-*f$$)dzEya3A2Hq~t>5{d=o}HUj?t>0fm9JTIEOx`Z{H^+cOTUw0 zZsBO7ku*^7&c*P zRPcW>&gdq{)A#)aI${17;>L7cC)f&CZS}&E({($oQ!^{0?0e{)+yMcX`1Mc6K%6&7U z7oAcsfaT)^oXVZplfjymuM=-zRzKEjNaGAf$ky9PY;k%fl-EdZb?p=vZ< zivRS?_^l?_vjwqs=N>FtU;4VM`xLx`QD56{2%_Z>axo3)Y~@Zl{66H43edJ0YBYVZ z)nOk+76|xmRct9XrkUwh`#YVpPSe2T@-=?cP3;!|UyjQYP`ykT&_o?G-xO17Hfoml zcuaK;e#pBD0RsVL=U>mB;~#HF4yJHc23XEl)PYY%pKr_A_3LfTy`*YyHhb+dQFYWH zV-h}#AhXT^2COi6KV77sH(?0!rMOPp`>HHZ2JS7S1p|Zd0b081sl$-aEw{ph{6#=~ z1*3=KP;)BKW+i}DnDx=D9Wno2z`9!sTDWqsd3EtC|?kdVIuKoQjw^*`h!->1))@Fh2LE+0z5Ic&_-07Nm>L4ST4OtoF70zDx??0=pwgmpkl(41&_GXzz6hHQVX$axpU{K+U8Ucxtmv$&y7 zj_4d#of0^eM?JS#~rP>oy>0pYBE?dR`$+kLU>1qr)z>yjOUwj}{aXOSV9zN5~GK2@i8 z>>NDH8Sfkg1nV%64$gGyM^CT?EJ&RK?S?U@@cXe%?-D6VPUO9$;1D#uOMxPsX^Rzn zH^vgz6oj(4mdTJ0&AB-0nhMI>p6Cw%?oOV6X({+GT7RW91?*O=sp6c0ee>FegAPUqVA0I0lrt>JT%CR)LdF5V~OctKR5Xv#E zu_ON4R09r-N}?dgCUhIVW2ZFpDV_IQ{&@^u1)%d)ZE?`kGUf7UcJ$rOHiDLQwd!ta zFmiRz{)5Wu;c@)f_Lgqx5(~-vRkqwP_&zdOB@{<}zwaiHn`XZzs%NJ>e??obYmd6C z0GFIb-d%ilAP&sEn=1;JbYK0saO%o+sK)rP~qPXuA8d~u2NDbt+%w-J?wWfEI zBoWhQ!kQzfSUjgP;{bMwme8Ptvfa*p0`ybi&XFcOKcbajpc^;fdxIJ!I~DO(VeYV+ zG%~^N1p#qSKZ>K?e(4V+$Zl#gh#XQXsuGe55%PlmWkb+s{brrO@95ZtZQB!Nl9-3$ zfgGtvBRNBqH&=Zlw5YJr#XXihufRT~Cn=3shxU8Mm__I@k(~Cli0hJNvzrv* z4@83NyjT*i*xA#aU2swX>@)&`+_u|Uf}`4kae1+I7=HW*qXAiSVbPgraDd!3=mZf( z&7k*cUC79IX!UO9Td-JmJ9;(15EGovHOO2jzeg+dm8|RhZMX$0nb#sGJ&0Pwwa_%` z)Qv0TYnfir&OER?E?C5`8?jAL|Ez9S4!dvlq%h_|OB)Q?+uu(p>5y?TrpRBMNl7Lz zq}F~cx-$l*>v1+hicB{fkzC2zL_4}VTUBA}o$9o1$D*0RIai&-^VH8*%*}SIN8+?@ z*tKyo&h2>2{Nh#s+Mkrk99@FVFVWED$iD3;i2p(lUFm#wV>N?(d?!r^k^DAf}aHyq+(=ft0>1#T(H2A1$VUabzAR3>xv%upq!Y#8q zIqLc1R-!`-3|cjV+;c-M7j)w3VdEtqCFzse2^Mg+U8=)UZ6)fxeI6B(UeARIQ%JJ$ zvDfL(;O4|A%Ga-Xdg$><$=1CpVpGzwx_cg)E!5uTV9*nsYZiMo>gW}yck6W1lMB#s zSI(mO=So-F4e9=Cfa zp-eDy$@H<>FxfPt1P8nXx5%_#Q@&`qefxvmN6)wM5v$zSgaP$did?3|ia3K49`@-94QeEZ4p> zV@m(ZGV9~uxx&zoKs%w%DhXQO(8GP;SyE-PNYn9(=WKu zxQ-zWIu}JqoS+g2fVfiCER!u-joID-uqD!DvK63)YP;Y<^mJpH zn>rVX=8C;t9HHAhE}f#bWVsQB9xaCGAk|SDM{_i}5QpT|K}=W=rf!3zB8*+ohC!8f zw}riPf-pAlTDeatA>CEi5c;ggO!-IPY^6W2EY8C~)>q}QWoKv?sC+#XjrjvyR7T^` zz;kVIUb*CVUUV{JyKrP>ca5lZhtu~Ijsw|C`|6*nmB376^3P2i^exSDB48G9%4&;i~OxCkZ7^D$n|V@iGIY$Bbkh|wCR0EX7R5jfjOZJxw!#(wKOXf6dd z&i=DTc{j>qGEpSby)RLxm|VQ=>R%Bq%!OPx^T`ABn;n0%Yg?{V*BNyl z0&Q)7h9u9ID9yP$wZWgv)bF|+Urh83qQl-F);L0E$z!F%PIIM zgwmz=_ZBOP|M}T{rSN!%NN&(~L3NilK%)ve(2-v;Be_bgf>SyglZ+^;s2s zo)hAzKmkl%a3g-05>f0J2GMq~2qMGO>c0ihzvA~8iuiYG7{+=NN{3S3f(iX$F-T2E z0nR}X(DzTA-fe;Kr4}H;zBm}FG$&Vr5+qhcAmw)Il42BLl$iW{KT0lIX5zc`jVaOd zMYs!iUA=9Yzp>5*Ug1hcl?<#GF6R_w@TwCHnOpHqy|GYl%()#VUyx_deh^nh8L6KSgL-d#+ zgW`%%{U2l>`UBvYin5^kh^MRM73OM_@r6IzJ~UxVDQe%!5~!%r65v8M*z=SdwN{BO z7Wtx1iu&KW=-C||z+ye<o58xA+`Vib3qh@@n>Dffu0h4c#s;O8D(TRB2IHlw-X)70o z>_1_%8?iRV7DlUCp<0XV*3@d*dyA-LHt`9fj{gPTXaK_2-z?36#yXZ!f%BQRWqKir z`J^^dC#5X0HTWP2$RNN>iYbjo@{gPUJEdtF`rlItVyH=cb-Kr@o~8mIu@A!c@OF|9 zR`YK!Yvv=cTl3WkXjDhvCusYyNRkNIBSU5OyMn7hQ}F!!%xZxYgicOXm#V|Q%2|p~ z^%dw44*7M6RNZBK>FKd27^zSg(vB!+5}((N2-^28zsh>oAxwK*XNeU@mn`aJv}cP0g8u2oNvms^A+hlZypOT6+qgNCR z{=n^(t!o`^~^iJQ`nVCEX+r7{Xb@lL2xqWxt-nP-o&ep$0RGylq zbt!j`;G-hXJ`!c`&)NKM@KDRtelY+R4Cea1pT?$kNt;SxZ?fOiz>dj@X6hRoo_d^G z`;q3bK=^uBKrm+#v07B6A=NHh>x+gLg>)I=RdrE=d=J|UBn$w-6t7pe0}S%75fpy` zl=xPzjGO&a4agR$d?M%;STX?fYw7!`fXktk#m@uEzO4!0hME))nzIux@<+pu{Il6< zsDJo(rOTjqIXRQhcZVei^>7zCQVL0{mM%5OGz!-nz0^|~ZJ_bQQAj@SSn781E14r( zJx$VOa)WeFrf4%t%BC<-Vgb}+wabP$efuN3(M=P+a79E1RhVsdatHQH25S&(v{U#_;%LijR^AC#ky zVaXQv*B%u2A|zci{;qyS`4CcE7tWEQUWqE`pi4S-M-p!#^)?$H2uG-h#p`0Bk1(7r z1xu~|_l}AhBe7Wz6>Y&GCHM36=&B+rh2O>kqC!f6u*IK2d2~AwImY=*Lw@v0teWR> z3OQEN91RVW-jX<+DCyw9+~mJN;{1dTDO8NCRo5C*1smw0&LVb3;e`%h1X--BrTkp6 zy=gS+EAX$p02{Y5U5yBr3XEQ(UK4Iu(ST)}e%VU-OoE0%z6~Zz&oe)c&gqxT)3wef z1$?R~k>w4QeMq!KNC79glh1~j0*~KKm5yuIMM7 zU>uo6>UJ}#@NmJw)+D9B>Dtor5KpJdAcnF(7vq3pJHh~+?$N{~?ClDWP9wPrrlCua zcQlN3FRg>|sVCdZw#*Jpb`B;J@aH`CG4ucxYIeDTJwOuR~AI z?1Lsu&X$g&jeI}>ZU&1^_^3Ul;-r!KLFf-rUI*v4??#h^;v#MhD(Sgs*z+wm#APxqWfSKq%B?d?n$j^!0F4g1OaUTgSv2 zX;aVL*N$s8sSXR@`-fvFr+}HqUxtO;iic(Cgm_JpIM{O}BIarP@ANVW(8 zWVADI*~_CuGa~GConD0&O0f$~DEllHGM@LN;fm(?028Gjp>5y2xRXCRPV?Y_J)Com=c&imPkt>R1>EVr<{(6Z$3 zV8e=(<9AP8W5hGEk+@0ZOrbtQ(xvo1j&sy*1RpkoDRG@INPwrLL2M?Gn%f4fY^Lo- zdpUFcK*FmRpI{11x6 z$R&li`c}=z*Vnp$LfHYp5(fkriW*J63`nUr+ySuMvdUnN3D=fB2PFKHs<1b-{JnQJ zeqM|#ChqE@3)VwM@o1+$JA*55yMx?wo5tIr*S4??>D0%7E5>B-`^B=6rX{hVmqIcn zaz=0`((J-Mz*0V(GAOKaMVRH8~mSS`bZbS zof8aDU!Ljzj5LCWkPI|$?$NJ9d22mnAS;PA@$3BjPRvQ=<5y#|PIl&Ax5ZMZmbj|X z==ti<8)*KRyPHMfup3LiuYyo5KwjOvxOF-dN}EJi#O%8etUT`m(o0AJ@zb&pH}x(( z#WOWV`JffH9e$lqb>|nAIHus92QyU)BCi4%Ih}QF_X_rTV*mE(t^2>d;PkIdo^oQ_{a-Y^@)3l;UFci-=HGbO! zi9Wstu;`-ZuuBo&VHLk~{aNUn(j2@f?P+~2foRL(1S+T+w4}2zXh~jSMdw?ukT0$@ zfqyC{HF!W9ZHd`}fAPLUg5o7*fv#b38|b%fzAAlf9nPiHG7Hs%8L`xzQeR%a)YF`d z()#5}$=Co9H$+V_t=QP7GTgA2l$UCai55JPX@j<2VW@ZK%O`A88e?xqNVMNJ7weq< z67!GzWGm9V!of>; z5l)pXD>~jo*A^%lb6|9hefjMCDT7*@L?jtSjsWbmHm0#vLr`|n|6q?YD@0^0Ko1d8 zA5z)swLa^6&{f!~+{w;qPU6RRKCiP4=~<^U6fgbSlHT*bX{w72cwD8~oB9k^Nh;>p z!>$O%1J(sX%aC-7lJwMrD8a3hn2T%dRU8LZO(eSb{()}1y*I8EM3q)_v|^H8<4^OU z#os4_qw7!l%9;mM4RmVb9Q-Oa{jixOXB*VAUKP>2GNj4=9f9XK1&kG$UI^^+!PztF zCd+|c!ev{VI|-6DtZGN|rpROEt3c!|qygT~hZwkVd^lEc$Z0Ys{00UmDTypr;aXZ= zz`HX?5Ga$8bU1sO8eK}Vcurp%5ImpQPXlgDKwuRbQHhphs)|pM*phRTg)uFWZ;KI1 z>Hb7g4z?L%l4PlmTfA&#(02?#f6E+`W?$O_EEMrYomRu80$j_c8)Y#Po}1vDS{X>wH~s z%|I>kJ+MIFLAlEj{4mCsXQr<-`c3kzXKV43C$Q-hwyuY5|FOgAwwA_SynsuLvNun+ z%cirokc`xV+VEtR*WsBUX7buAv({hDu4?}R>Ab(s*#|o{!>M;SEva8e&r7aSTKv8a z^fn=1$LD~fl}Y);z+n7^H4>FuvBu2_=8q>ZeDT)DrMsfE-x>t+#n=4L>Ba6H^Q9{X5fW5EUM)^jcr55$mpzF!JvsF5ycZtQKQsSxHdl@1)WX zf*n#SW)ABg`|R=Du~g#{S{wxRQ|OACU{y{l4U(OMTd>jEY61T4qS7xc65h@_$E(ym z#>CXX=QS$TwxaBdeLD^GRsanmN(#_C)0u*lZDnLp?lIYd!Gp-S=(@$$5Liw5vyE^9 zgi5prnJ+VSSF{6i^P1XI$zA6+D&;Sp)-6+LA(asV4Ehf-E(~;j)BCKSEsm5y6*UlE zC4x3_KTRlS64xb;gfi9b9N31ax3VR`+ViHJ^D69Cz0l1|eE~u(!^Rx`bWWrcQz|iY z1~{GS__qD7hRf=mWNbwaHs;_B*44KJ!TAS>^)ia@XyE}$+KeMT3=&I*L!oM~!%eRG zgfJWX4XmX>;vsRN&&$$Is3%tFtMPOA_Y48VmLK;>JIrv^1rds6=5^0|O)pw=^Vpks zV*&$eR6Y4{kanxc0$sCV8)6dm#Uubaw2qLKKpIstUFekm7a*oBo#WIjokLpy^ zC2#6d_-Wz`WAw{A9kF{~%9I^*j|1a7^L$`AnNO~&)FZ4ddIP43K-p({Pn4kQF;-Y) z8^KXRcYwP4x4*Ujxgj|5Z?n9;a7ekVM{R_hKKk@0oQAa&Dc5t`5`NoJ*9A|i@W(zc z11pfdY-B0#%s~;(JQ)=_hjKq^2UZGIqK;6FA|bIvkCJy(`@fZ3SlXq-GD zEd$$XB{GBl`1W@re?UcHoAHe$gx{Rm>v)Ga9(bk*KdMgVb6k6guOtZEW>bC%Y7Yo4 zj1VK#@DT}#kkS74Pr_K!*2C*yFn>?PV|z-ndlX7aU~tSl#Divq%?*t&tMe$DW}wHH zlzeFA6&t;Jp}5Y`YmVk{WZ z_JBAZ42!c29rJf+pI)v~UVFVubj%9KtiCrh6?cCGT#?R+SMElk5a8^i^h=S=d^S~;Vasc$S)16!6|<%(P(+6i}$u%nxG zmMQSRoMA>v#Cky^u!dd`YF$r70RBjAk{1O0xCTqdW}qO5-8pUm51N3X-n$N2V{ zQVG)Adl@&6xC#NlvB%VKzg;=U-{D{UuJY`~&DJR80L1?x?U2-KoRqn!Le~ItQR#;O zQYWU{5lM!gWJknx&p2TzAlCP=Gh$$&1g6b*WRjic)YBqN?wm+Hov=mAWtaKo<-B+| zR$>dad%bRbr)`#>T8)n)pt}9dT9b*93=@}?%J9`ov`sNj%DL~_Wgb1=`iJ--mEw2$ z6(R}pHTN{_*kvFXK7?w}U3~k8@Qp;X4!FdvoZl=K^o44+g_<|DI*Z8PZ{}+&2xkcU z|Hyw!z2W{NgXAL6tAF8{14FQA&urdg8V6Za>@Ub^-u?!tSFPZR5)3|vgS<{34|bbL z;Pn|(v;eI^4->xu=m->P>V)zQdy8f-BV0~cvxV(92NVoKRt%-8_8-Oa2|lTk)kb)e zxMjDkXg{F4`4YN32+1(bkTz*_&VYfl_!7Z3*n3&05d$UKVbDBp^M&dp`#!%ID&GaR zxkso6ql~2GnWf?7MNO$Z)+S8#C6E<36lbXZWo3lgZ_}z zT2z;#k^N7Yt&|DB%-`kh!YXjm_E>7N1ZSKlU5ognA5E;SNe5d*Uat*ZPh-qyTQK+z zLn7jm5|%K7_W$w!_BhgVf6o^hMsTzsuyy;{QY!?SPod5P-J_27&_NmsJ=59PBgK{Qk-fyOB{OSPV+&x+23Wj!?w zNjP4Q7JLIiCiI`YA_@?Mq)-ka%c}tH{1RY{{mmOMSO5lo3TaU+z5I~M4QLnm+aWO_ zPldss`9P6%Z@7CwRo3=yb%=*QOwHf+g9Wrohl`yp1qTrf$9czWa;uq^fz4Jw`SDyp zrM*jk?79$T;Vk3y-Hj>**|+wM0^_h{UGa~V)M3#m?K6MynmT$u5n;soCOK02A?a)7 zB9go;AW$axvm_rk8a4m29q}oSW)hfFSH1MJ`mdk8FTVaqNS`7f`ZXpC+`s%n<>(Wo zxZhXzntrO;g16YRFKeC}HRolzDQ(RpeU;XJ&D)zDUa*KkLuyOmSw|MmS!k>7>1F!5YZi5F zQs@sWiORAk1;;=`j1GX?Sb6>E#q#+oaWoCGwAgo?Ds;JJ=4bdwdof@ehmyQ@8kJ-X z9kl^0GN>$O;KS`HXs?@+U_iTm5G`G(9UB^V1c(ppJAhE z+!*LCx35N;kMYG94ZD6n&8ygP2Svf$ZirXB-_ixrh3EW|OfQG_)o6VZNT{}LYHy_fTdD4w>Tqjqg>3=O|oz%A+auDi_sS3_YD`@q_4 zK{aT{^ItDAIN@7_=6Lp;$9?Q_tRv0Y7$N=-F(6&l0e*gT)yH*1eSyStvDsB`VQ&?2 zQi@;wAk#U=Rhu`9b;kY%k>3;W?|yb24PS!vlrlyoM$=NUF$ftj8Y#enhYQ@n!hK?f zqyf;U@b%68-L@a|$%siy7M^K8W$4XBDWUTxV>R$8kOmpf9JE_9veQb23tm~}=tFF4 zD%9-0AD^ogQ46s6EvV@IE6#tXn0)A}UYlkr_k!v6)oZ}>yh{>+D;fonQxI+qRs(oR^ax9*k>ZobzZ<>-;UrjyQ!Cq zew$Nl+g5;ZCtr5+3BQm+4X7XFh{)_coFu1-7>W72UyiqCf-xxyksFlQ%5Hwl@@jXk z(31b~5wuKP*~Zncsf#E~z+d76@aJtA`_ZqO%}mzS!G3K;H|E9)ww}9yJ zO(i2gqD17q#v?`z)568a`jsZ1O4G&^X}z-#PENq$k)?5q?fn>J%g8T0RNKk_`pPLf zpolr_c3D*^GyRE8_HBMvEeAG@3KI-Zq_h!qwzIy-JzSJxMqoVLy_MVw%(+2--&kG8 zpNZ}~r7mh;bpTkz0AbH!H!9ypWV9OXUG`vVS~TxVlp%y;&o=rv$8*$niwWK z>$Nwxa{RnSNPIEGyp(#S(!Kxdvnp!mcT|JT0PK%McyP58VUgVgaA3fLCA;zqGqivm za}g!=KXRZR{V)<IV+N6^8wHYHP@u~iX9Q)w-U zCsi)igkfc?cX?7VhgP~Z>9!+$GtjxY$NUi>u+|Z^jCr=7%<5g)fk>6Wz*b!>5>iI& zOzIC;9dc&dy%-9YmRzrHW1ju&`s#`5H{PAT;ujHz6n8=7KyqrxD{;^X+HCkDr;dyN zpRs8o61hY=2R1V;$4SX}IhKdjoYaypiaB@2f)Ey|l#FW=+|!r6W?_mlKv2h?SZXw` zM419?`55=H=m$KqddUoFkP;^CaQh4O1F@H*_>XPdJuzU%W{U^br7Zyb-6e~PbABD# zAzE)9A(TZ8oZBh1%kj=3*}WkVa%J5FFk<^#sFfQBQyTvh)fEzD$SL>zZuCntL1CiF z(bR#aT8@B*^dO8#InLSZ58|t9Qi`~HY!{lkVBkno!#fh7$x=64G2Y$BGQ-a4jZhCO zMdx^NI=4V1&x{;Bm@`!bcf$)XSGcP&{;EO~m2NvSA1VGXe`tUuVw6 zxQ!OJMs)gNyP4&6>zpCW<>WZ<04wu^4A*e&`X<$vRQWt#MJgeOk0dT>X!Agj{b{DE zh4T+f6(MvWa&SX#r>}FR%oH4DumWH%tv4s{b33C`c3RS zUXxuMF+>%%A#EJycWx)76VCdzdZ7gG@nO}??h{>0!Zg;ZN-xU!K81I}QvZZQQ zmg)BmdBEzj(SF^wc3)1u-;fS`LC0*=^9?N@zVUSK^t=>Yji*fRJ%b%JPTXua4cEl5 z0W1FS968tdBS)B2ArK0*ezW{9!?$f*5}L*?Fh@|Tl2r)}{2mj*UiTffy`Kt&2-B@TQWv(;Xj-XmD7l$cBT=PUKcErNq-!KH> z*wjp-s7F0k0JwU?0)ljFs&>-{1In_3gp7($-lMA&t4|f-4_gs(K z`aDPmlVL^FI{RnP(?rGxwR`7koI!UVQ#xfsef{fV zCx%(xg)9mMK+lE8LKMmp|DRQZ+9d2H)=S_ttC^OAD1gsR&M13Qe;FN()_15x=<=^t zEs2(h;A4M_@JH-y%cFtm^qe+Az8;+bzk1z!Jify_m%Dj(k`d9m9sVHZZ%6Hu*673_ z-C)Z0vV?C)B!7!Lp;+LW0^lmk(B@HAXzn>yT&|=qj@JWXjxF& z4Vu{xGeRWJDjC@)jRSVoNqzg@B|GU0eB*2CWD&GpgV;}Q%6MEN$NX%9AIE>8mygxp zN0EbYJ{zXx1EI%LxPbNeE7A(O&^@H7?GPp!!T|D}q6T7Eu_4MxFNe`lg;Yze zt*k15{u7w()k~meM>&QWnjDK>C2YwAhK%Kg8Pe;kWLp+j$Y=Zl*-VCwBC;7dx4xw8 zfE=m2d97ul+bK@+W}_!qmfQ4HM11JLv61v+$IpcPoo4XL&ElFWoBpwEi01S)Qs&*h zy0`X#0k*o$S^GNdHs56i77jjyB6bR8FZnDjv-Pil?_pJ0Vy3Tp2jtPs}Yuy_K z0Ruph;O*6REA-0T z8^C^~(}>6m!~-eV4k9a6AZsyvoLIF*$ZB+Y*()S(J5+oGox_)|)2tc%LL0N?$M|u; zFao=y-tQ8-IsvekZXFULH)xR`GY$uJ^M+126(z~ufanP?I>qMeexl>YbB?4u%g33{Re~AxAdj_oj2>RRKVKxaOfnFAe*gj%)b`}a zcm7xzR;^wHc1p{<0@X}Hm1$US(hbuH$E~C>cp#Ylp-s906TW6Ix@8pTDx;vDI_}_e zJ7U7|Q#C}(6=X!0altRfcGYW1_X8p(VkBqg6B+Aleb z4O2s0TJP!wM#(s1&|G|yV1VD{h}?L7pI)MP#)%#@VHyyVU|Gw}(AebP8PGt<+wh@u zL6M9r5{|eIe`|GN3%c?MlTjFh3=5-kMS0Rzm^l{2km$U6a|xwUX^CJf4r2jTz7h#L z1#KP6vEYRoW8FAB!XawzyK&abP`7RuR2r#D%)*#=sKOL}6VEFBL+wMW{^#c9c7)Q6 z?J6!mRHi$OYKBYb3NG+Kg zbN~W7Cf%RJ^Ob6B$i*&_2U-~9t4A+V^751`+M_?fa5z1%wA5lKBFcHyc;}XB`3LIU z_t4<}9pB4Y8apm#^*9J?-6!XQ0L;;)WPycZ47{HMR-wIPcUTik=pi^U=P%MW$XyZ7 zlUl@&mRNvd^?of5I92OJJd+u5F>Y4?4e)NDU?XM<4K2syihSsxz*&k+CB0H&dRn@Z zAChriyZAP3pNA1! z6@h?RnO!FZFxKl5yt!6+3Je1^rwpU>&`y~<8A5X`&2^Lro(`};Stnp8mI^0LkC{}H zvR_M1V##VC%4U@ih8;XhwP|1xsJ0gq67_M1;bgFQ|1ONqc&@sj)u~6^wAr;JVUjx+ zr?6Nl)Mohogbl$%pf6@owVAM28o2_>BXJ{~`KVvV?TgB(d&)fxsaA4|`|wisaJ1qLIXZSlNgt z89)Z+A=QYm$i4DoZjtu)dp-F&&ne4gUK*gd4Lp(3GvToZ4ZHnm_}m0xq+6pg&? zcCZYVjPV}{lN&?2-NZ>JP3*4)yoY&?ZfYw*_6%Z(Y3?|I9-icJ{;r_g=ZED<^3Pma zKJT5V?pR`A3q?ap`DhIX>2bQX$-Q@~*tjldUj%?((>yU88^Fxe&2v7y^(oaEpA4l( zCps=?@ELy_r$hsros{f9G(kHSwA*76p)8bl%3MQG(92=p_&Di0YCBPRK-xz-!k zJ3iswh&uUD4!Kg@d_Rn7HfxLZE;brYMzJi-1qQiJgAuf-PK_NEemh=e3}b!b1^QJ% zno8K7Q@TnRKgnzvc&4Pv9hDprYb*@qtit0qX4qC3u5}xb8AbRUO-}h4l!JG&p2}}F zAQpKsL40iMc|K84bTk}?pAbYc-5(C4w#hfvg3+&a4$$RhKM?K= zT+{w`^8^x3tjdB~XKUuXDRBSsk#3I`_pxSojPj~j2Cct>(P|VL!Xgx`k)}a%hhZzX z9{>DeXKKERoJp;#2parMv+3UVG|omPy5_p972^Oj;xgo83i-J0yI+aH7mH`C5>Uk3 z{WvMjCB{p)r1@7t`X;C8p}bsmA(ODoh0EnnA!XS;9!WMht59%!o zr4ZclsK6QLB9W#4^+i*CFm$D_LjbLl)Y!6ygLT4gR%y!+Qb5f3*-X8F-c*Efo3h z(%d*YaLbw8%y{?w_8UhJWu4{C=w{1%D7(P4%@{?4+xF=_2BC*>@QevkhM-lZfa`p* z?LElSdx2ATR>tNMli_;sEl(q?5N$FlRV1v0aTmIpqQ{SGLJ*NFW_n>9hyHd^t83Ho zMypBktCrdr5L&z-1cO>xWyw^N(d$t>isw_cH5E=0xD-!1Qa$TnfA^i-MqC7q;7~a4 zie5QHR*kp9sOm@KCsV0&!D|1X-Fsy(Y=h~t^Zl&wFZ74%V@O>V%V1CVFVqqZPWz%r zm;@^5g|Q2J-vSucJ?b~g(>z7~ZRDg0HJ@(NtOhpL3e8iusy`n4P3;00&kyep=ysVk zlWAH}7CR%{k*W7u2;^M;6Xi;qBkg`WzI{+5ymi~8Y^g&;sndIXZJ3;n3bjL4uCpl# zW;%A|6Yke?%;nJNcEX=RL^X|mQ0!aBhKMhcAI*v-(^#X$HB@Q?Xp92@BAQvx@p!cW$kvi3ea73u&e zg97WxF(r;sw5hbUH?N2Fet^--#ET3~zn0fwC5GP4w<;bH`|667e?W`l zd_2a3z6vf<>TlO96|c#mU?e8|)*96uW{~O{V&sSc+5B*qPXv1kstk&j_XWRSsBAc1dg@zfD<210rc9{gQTq zu1OvbjospAn~6a`<+J`YUM^UDNW-6Oxhq)vcgA@hx9^Ne!|@fD&t{8Z$@{sKs`Zn( zbGWc8{dBGKBw!Dw|C=pCYiij>1ze1G*Dl6vt0@(VMF_7!CDNR3dDh<~rMzR^^g;SH zI;&lFFY_Mvbc&4)$LlqdGEJ(Uvp%^XAiA2}h^=(sx(9lMB+PE~t$zI%fcMW8xG#X9 z&88b~Aw`5NjC2Xe(;F2{n_cJnM%{{W>&d8B8{OSLp&Q9bTw!X1qWF~~Wjo70NvWyA zKI49fYV@0?+$+H%TQ$M)KgU4PaVp&iN-U#E?gQDn?dLP@(pug46zNNH~1yeNV zwdWuukhK=%VT)sy$}akpnVW(3?{Ijt8*&Mb(3xrU@Yhclx;sWYf`X)E@W=)$iu2cP zl~b>T54HO-wG9N16~nLgV=bf-{NEW_MdgTf!^NP^p{6Q}M$`+t&T5-a5i#pJ?x!Yy zb?mY|25QO(5_Bd~(IVrbZ#jnPR6Q7KMMAz!>-wXD9_F}g6N5?Ct6OVSTEcdQqqXi> zvT5Fj(odQzKPJW%nG*%s|Z=G!>fIwZ*8Se-oJRyr9;!K2qPLt;`o4H znMaRblY01;uROH@S@hoT^&z_&;e-JVWd~<&am? zX;=MOwN%~k%I5JMnEx1Gt0DZCNLS54zIS5`v?>PqfT>Pj_@}OIq{OM^m=_|HIAE?t z7>A9QQB1xIDczSR0Qw%e;9m2~yN8Q$c+|y_RFlm(<(#7VV?lp9=j;2wF4Bxe2N2(G z68mBg#yDDgG0d@@GvE$GRJ0pf3m{{5#Jz8RIbiBLGA zs+H-3pF~5~fP!4XxHRb4!qeQXnO1=oJ>pX=5EE5R(!51`xNaD_%0gy=*fs(^`dCB` zO5(ZbA^>1{LTq238Jhj!uc^^=0rD17gJhK=7>C%VP58m&M- zYMt#{h2gNrc#qHo`8cPCXwKLaCk&;Yh;Or+!NC*BN@+T&M%|`A`M^nUR1?~Z#FWKi zB0EhnAN_Ak_-u4&Xn!XYs-b<}5O;u726x9{kfz{j@!`kEYo*^&VxPq?C&C9@_eWaO zPG1bjv_xFFSk2b~0wV}1?dih56Z)9?5B6Q1v?YZ@oWgKR5T&x>_xr3CVx8(Mc^GhH zA*H1X8z>Kmb1>En0;bx~bJ)rM(`U=1Fk3Clf7S5&ZgC{z%-GND;j@@{f4COJG`G+P ztrG3Qj}N(B=LG;3$+nk-oe&r3pGRikg$j}C6qc|K` z1{i35?&W^k>%GEL2TJxvD?@b0*mW{ggDQ-j?cR%7mZBggx1NKD|7ODc0v{7~UQUQ< z?*t72G78-thFTfk!lUiO_mQJnCRYjAqKDV_kIJ|$gMqj-=hD@*O<<2QkDv`rw%8ec zb8C^VX9@;+gHl?*gOlR?cynvk-Tzyy{KNtgG{e`g~FjpbGJ}m*1I7 zHbi$0kzll|{s9M1u9`bvyX{32<&iBN?Gar7E$}da{Bdy zsZ%m#8Ec}FTHphyUndc0@B+0^s{hMi8J0fegDfn~{f0=PUEtQj`j^z`B@`lt){<}H z$Ic%4w2qHde0F0srszAFlzO*kHvjG>@g89LtR;*^m`$j`Ro&c&Aw{-hyD%nHt)+~3 z-3u3;fM4K)MBqWKW4wl0lQ5Y}Tx<`E%LtkO$rTdXLSDA0nlUmTU<)tlhZ7X>7fGiW z=>|&X#V%TjWmXJ#!Ohty-Q9B`{=k*(hY5_(v(7IM^BwNYE}`}mOyTqTpaYc()_xJ~ z79rrr^Rh1GHk%(+PJ_8{_bZk_;mez_K>PMGsjVEqcGX=wJ(QxVa4rKxe*!5}4cmPE zCrHwqVLAW(0ihF=q^xI`)N3wgw{j;dcR}PS$N6|s3@!3&UF1v_mZNtAVEvU$axM+V zAroA=1L)RauLI>jC@n!$(7S_V6L+Im0IdaCtJpP-V9243!pOGJ-<~)~js5O2cA} z^&bM!JPwhd}9)er2> zm@1r3H~KD**J%y(FF`&s@7y%xS6VEm&N=%c)&;%K!<@Qh>@aO7iWRl+Wd|{~D5h@} z)#~B&vo_7Uw#fs7HYH@LH^30*Qp4ZGN`?9cs)s@SC9#*SFSK3Ak<}!8J6_ z-+5Qt*V#RjKjPrKM2AGQWtt6=`Mk};WeY#PB<8L69#T{4{)H?a=?I?ixQ&3~Ca?fs z+M**#?C46v(I@GwSr0JF<*^2jLxp7Ct|rOHDc$KwmkZFh5c)kEUW&T0nsgQ~{Fvfx zXKZhZ!&NUvBw21dlQT3x@1uYj*Zl|&Gq{(e`LI{t$9&}#zpSF1hLN8& zvh(uGv=pYphv#%^U+Kj!!p)iBBDvo3I7w+=QZyt%NpMPhrDZKei#HEn7S2dXYLF}Z zaE`&ikm$1drj4q{H?9+JMe#RH=W(^S`O(e+Cf`GG?sw|Tf#{;Bt|Ijs0 zBB4BqOm>mm1#9RFrb$0x{`W!X*$eDr zB4FvH;0duXDlKiCFsD&LxUt2t0Pm#9NR)muJU5C&-v?qP~=r2auGFIf=Yn0;jzq4&Dl0rqJPPR=cthV9G~d^Kp@Hiqyl z+iNGW@)3-9I~kdbj^y==x`^>=O$l0^0UeegY1Zg7oul(I!nPw3JKF`qLoYs62bBps z{N3DK@hmsY^C)|Q(9qpE7XABj*hH34E#RxrfuyWcTF3xz(E^HwL-_8tt&6WBjU;ym zr9V&>STvA^I+lz@&tSCUL10v;r57?u%rk|KI$Gi5m?o5!TQm&}vA?A%$G-i;ZW^-S zM~9FmUSx=dujOzW@{LmiOKbc+{Qt9kX?i1pI=?^q-JcSCw!5TWr5DPwtcSI2ONx?zL>>jxV zt5?B$U}4Am>+a7_pXX_Rbbl`R+*DgDp+V)J3RUeUMxDj6=Hlwf;57b(5~61|m4pSq zM~OD!Ao&1TZ0TTaQZW483`np1$TDMaqPR3JEe^CL9PhqCsy@t&#|J4b630jWS1;Hk z%?B^FlFV$CA@+J(AFNl^az^v}`+g&O$dD+NKDSdcWkacx7HK7v!%qx4u=|!d_N>&e-7XWX_w&gGUIVsBP5|GSwm+sQKUT8TH~!!dhj4KgF3f zwB77B@7>px!qEDyPbH6BrBvIx8_2JiHZLM~ie*xH3WoR!?({rmkV`$+=}oi%8=S6R7?d`!4)6eg zurxJPAyYRAp@J?T{O6T?+`MowFr>SZt6T3;S^W}Nh5cE4Jk2Io^2dMOI`&5%hue)& z@;?MI&+V`?xB;@Z*)CW3!Fm29WTME=4*7u(xKyX+N5Y(Cx9vTe3b)0ra=4jm#`#O6 zGi4-?|7x&_`ILkEViYMmt+(IB;dog1h-W7@%Vls5FtwMkDqh)Cnx0Teu;sv)=RLkl zJSCPUS%+2J9>%V9ib(@lpP)JoAu>Cp%eTlhtXH_Rq_@BjhjTkRFRCQ*ahK{|vLL1T zOkWiX6Vhw+oeNEyi1`ZvoZu6b=Px&%o_H#CZq1pLr zJf)#`3S_M5KhV_BFZemZsk17>tuoIo3CNSM<-qDvaQ+c`#y_FMz}-O8n#JT>WL0wX zc&`5%lqz1C`eLPRH#!#2fVNCb(6)`;rq(VZy<+o)+=pbf z7wzRXcch21nRLP6Wqb9@#7OSKF+eqAsYH>k`JzO>oL{Rvp{wI?6l$eDiQ)3 zaDo1!xxg%p@cDN(fzuf zjDh)0p#=kzP`1;@(!dw{63tDFRC|%b3FV&MGe=8SSnaodZ!#e+H6F8`%Qg8MGg$gd zCF-Bis!D*P(v@<{VMu@Adh zvgjpkgUT%W_GAw@+X!%94l zJ;6)Zt;!Kc@XIP|+f&MkXOj8YYBCNU6lp8>r<^!a)qylaA*JUYI8i1g z=kcE9RLuRXY)2v(K9$aiDMr`Qk(pQ7dg&t|V7TWx+B_O+Kxt|{^N`-Fv5(=6#lsN7 z-Nc1?Xxj-r+Z3Gg%)=`wnXavd7$n9q6(+`_C1s%5leBj})kHjwWHQUUt%o^h4Wjz+lo-RwrUe3PRM__N~$L^35s=9fH1H)+Fo+p12v{Em=!l z1Hbyo8K(k}WphbnzKhLx$A(~R3&|s-?*M)xH+pO|nxkN(x z8TkY~1~L4VmDWIhS3T`1IN}F?m-ewZ4cF5QcOvUu{8)!DYBWp^fz(N|q*!A3L zN-_4aJB)o#(QcT9lGMQCe64nK{ewJ4tVWWsT16GjK7=?(g?|zssYDWS*$?U9>4{)c zpxx2NqNS6?U-E&Oc+9Lu&~!mTagJFLKkzqp_t#@sO`nt3@9H2|@7@U+fYL3x0onWh z!V-YaEScv-FzSDBLGS(#RNelIvNcVy_iG}LBnJUhnl_5R<)xRuG+OU(dgXo3Tbwd<9AFLeVMTot z-l);%#OF8@;ay1VBfr?AR*4wRWld#auyCSMFKFTWvwJaoY&raV-F<-?clv3-(hIb0 zcA_m!XhJNNty9q5gaN*sX%zbEmVCATbQOdeg@j9C5~siG zC_YD;p^(QVXkvu3N>O2&40Ml;U6?Gsa5Rv`X%eQ&3MHbP2lu#Dav^UcV-QA2v1FZ7 zr@&{+nUe0|0yzpw)2uEGNn9|&K1`zvRlUqGb3?s`{)2VLb+a zG}59;Byi{VpN^u%xaTLhf~yXK%Mg;naN!8qX|?TOJPa7PWA&C42YtQ80sShKCEWBR zsMMeD=Cc5Y^!_pTIu-cPles0hOEb8;82Fmk6EYl53#ZIEe!D)y{Tp@cb(PDmOoc*% z`^>Q<2KDeF+7Qy#yFUpbvQalr|7aUIj@sCC_h19tT7W!;uxC>5*S!_$BB|pV0Eo(J zSORta0DX#TTZ_jwhcn`lRs`{H$OgTlGfS2Trg=B)XP$~BU%D0|4MqqV+|)(fX3UI` zTHY$B!h@b29RC=uRDT;vzauDO@;-UYe!L15{iAQ>!b;R} z9|DWY0pK3vg{2_3qyb8D-VUv$^Q>Wtm7n>0DzRc=81U4B%KJagLzDHZm)oM4CzaHj zNsxBMxkPLyetNI&DUSdY4Fv;7S6$`4x=Tv+qn=u~k|aw>SH;ZS#vN!XcdccW1g>`a z^hZETjhXRyNAy$I8-0qwqwC#&B`kOg(K2>$hP;zg1rww5B&8|tIst+2#ycFXE$-$Q z&_`9FA9O~mIFcsZNr3(c&2Jz_tjdg}80B9TtbuI;Xrf?FYb-I?W~nd%)@@rn?8PO@ zW3tx|`QEn3-IgYzH1ggXVGz9YfW+9#zB85L3*j`&rCJH1{4?BAd&iX#=j4VUkO@m& z-*all^UPf~Gg6Y!|1*lL7e;Ka?qBf65uYfuOlc^YYK60v=@1-uTkDMdwkZE4ZYLKj zhacW;z1RFek)spu6ac&8!D_ikmUiQRyrxk{BebvUTfjG!$PLAmnjpxxQa`7wgM|BR z=JQdCsT18&2bI!LxwSBLTW7lpW-IBgDP?w41=~Kgz3d3OEu(jf_ytHqR7!k^m0qe` z%mpEUFxWRm*P75)clit}V3sgw9w@LbR8yq$Ja8=jErtISt~sVaS9iSy4IjUYlSpeh zv2`2z5UuYG*!4`Md%F^vUF-bxU5M3=#&Y!n6rGdN&7Z~U=VRf>yCsANMTCJ4z>H(7 zZ+g-E>pq)clKLQ0w)R9%=Ey+qryh1?q$zTP{|1|GE|Eyl1>U^2XHP8gkNA$6rgE;b zgSsd@;}F>6b?X)R9x+((=@~IdAA-z=1oZR)DrkbD7U2`rtb7I-XplxL7wJXB(k|tA zOVS700`p?6>)H;bOjfg`PPt!HKqPTFuWPMcgE)Hqyp2t<$ z=5-yofT~DJg!=6OZ61<`A2mByrru@S9-&j5Iz*gXZ8R0`=4-Al?utqPw3o=w#fK%_ z&ch<~Qrbn~(Mc)9jhOiJaFaLAe1dqa>6nOO$BP5E`}7_Nnfu6YcBNx6(L%E)Z>}lS ze-s}gI~wYffULY2^_eKcB%_sSq#fc6A9?mI>K~y>5#wU>3zG3mNtWJ8stFZM0KzYU zi1wCZTLxtPOOL2_yjv?&UtDogx{@41)QUc8aTb_9NB^B`7z0<8a#p}x66Pa2R$zoK z_m%de`7=D-DS7@@qCJtAo0E9%t}YIvKt&U_KRMg5Ioiv5@O=WS0q(_D4D$A`fCT!r zgzfBMuJfeR8r1yy9SnkE7Goyo`zgB)c0PuTn?ziDfbTLcu>Hqb@qTiz8xB}T9jiiU zM4%Una$rIk{3xLUhib&^qc zj_~>MFVZ;G?(_%-dJ)NJqJ~0ZUtGI7IILrhTCgmBnJ|!eQN(LDp3Lsk$quFMaWyF8 zW0bb^*HV~Bl&QOqAQ({k5^QLm>2HZ8z;a9x5kWfM?R<_{f`J_T$58p zDGDye?flTmFn4Y+=~17%z=9MpWcUL1`tQ5gj_>yW0L_}@fp05-Y~Y#i&J1WxXghU6 zq9TZE!(Gj<7#vgV3e&bYH)S5VRtMu4gY_e5USiwE4JWOu(EG;~T%CU6fXnuS_*cMh zl+7j*^e_H`J>(GrDKJoMU6QS=a}|((EX%+u!inAMukrRDDWy`OjV52p0c?rdZObw_ zYA$J0RyC7ulJ4~-yn_c;k$B;vwPBL&c=4ujOsa;v%_--GtY zH~)M&vpno@V{eiwhknr%#!y@p2B5W{ z=>Gg9lG|n0quGo;i-{-9ZK$vtTStauNvk^Z?5TawqB#ixYAq31Kjs{HDZF;5bVH6@ z{BxwCFB_GQoYWd{yIsqQwp{=z?Nn{`~2~M z!ryBXs zbA4^wRA#4)q|@0hPLDSRSFU}xr(AsiiF(bDm8xARrb=xW4rqCc=5V6F9`Bg@nh0yu zty!@=)E3w$BpG-YJ7hjwLDN>Jr+1KI@_UBG9Nm7+2FZ-A_+{ovqOEYtu385ZgtNY7 zyoYd5S9|^(SnNzY)-o zJgAq2gzQiL*4{|KGXkfsXhoXeW5LiEyjnpXWFKDuoAux(zFOo#X4aAPEGV4R6R)!| zX38?j2E&F2t7bd$g!G+l*Xcvt6BGBSeG{~RwJ|Gqpk7~b>Bwnp8^J$h_2tqC`&dL9 z5jIxiKjO9j44F}`(0yj9V#opcI7T7%>{E~?Z*A)td=PxRqxIrchL6qno1y4^!8|nz zq0GK1#gEhDR_z zqBcNab%jGlx}WebAT!)4g@?Q4t6>jEet7!iasr69b@vY76&(7&7R!VUSQa0rkcvBcC8c5iHRYrFHDULG(Bn)tdUdePN>up~9Dt`kC!x#GU{Tq)bTvQ?Ic zdjXWK8;-J*Rn$oj&at|~)(;d3?*;G}-e4*c2l78GTH;9Q>>cfxX+YQ&TrMBzdox|v zi$3HuRK{3mksB^4OimQF0ovB2E@p+LRRzmVup}ZfoQ+lNffewPbgMRr8}G5HTlUA3 zu(B%JifcnS5H3m56PDO-FMkWW5ZbC@5G#X%S~{OfRmRo`iEuMj!>HS-@)w-{>DuPl zJMOMBFm;D^4VXeyfS0epsRhi+wa>j=um2Sv`66PO7DK+ZuikP(H2WF5pc5CerW6C@ z>GoLn#vvJ^>0~hDA7Uk*qWuGWTtK&tBdSU>D<9L0lH>m0_3t$UtXW7&fc~ET?&&`l zG~`YYboxx}plEJc7)x-@GHV3rr3M&V#KHi@q?|kZ5#((>D(+bI-f za_uJMDRNhu%BHD~qE+MFa8*_a5Iya9B#5~MGBjG$lhVa%54(~*?A@9j)h>QDh zxUHV`D5v3E4b3Q8m9lKr6h7Vj`McX4#(z38i*9%Gu0g4N;+8MK<8_n%T!#2&rUzqQ zbk_7e76JhMn`e~|^5v2{2?sa_VgkCE4@wwf1)89K9ccW$Mx|l7!_sqW$^SO} zFp7LhtuSx1h0GGbW(|<$HQ`dAw5A___nfLca2||Avk;YHkR`8*R8$pAP{u5d}?}md;!io&7e8$jMf}tm>JAd2aM8{wD0xdJ+hy7@zm_Rim*V-YjEp?#%<;}A<+S_+`G zV87O>*{;;!pViX9K<80tYC{x5UI#;dNXL2SEH4?>FRfnnS{GHX5CH%PIp?MC#12V| zwr!=f31ce}Hy~#vQB4_m+s)l@MnTU*cKLwJ-9mZ$Le~dG&B*7Z>By(fu*EUNEFKwx zTtOY<229i}ftzNZNN~gQkPJ%(1U%UgGnynE-E=*{#u&R=?S?qApQxR{H z9jOjzH^$F)oZgzgRSYG1C#023tFz{Ch)%^{uAo!<&AE`xTzGP-Ui&8R#$<@|SKH(E zi>8`Ng3&CVC^y*Uo7fgYI`ZwK;@r9N)}O{W3}&R1fW7F__f-;$ z;DfD;fkoCAd6D{F{@Z>3YOQw<86ruM0-BJ6;}OrwmSBq;?K=C0`ELU?{2mlD8%mMz zk@-B2y@Se6K*K(?Jfl80d9#`K!%LY_CK!3Fc=U@6g6vhr3sV;J4IxxEWi`9Ott$I6 z5(Kg%8V7Al}M9bd%L72?_g>E5zbiyzb z-N$rvEG0u`qZ7K7X(}D`P47sa3z1em;xuPH?)Z#owZGrVCI_M#MyM3|32E+s_#XeG z5cl6MSQ|>-M@dR355b zCNx?2U2eGP+Wj8Ttbq*$+7%uuc>T{|EwjX|lqYc}x&mjx$%^s}&I~;R1q-*@-?jobit8t}9{>T>hPW5|8#evIHV3MX z%FD)!@U)z`7w(e}w(V8@IjcG|zH7kM2p}l;s9;ngZBsd2*OraxdMY%UleRtdWN*iU znhRSuq;{)C;{~n|#58cw{q23slzs3&vs-00j<1nTr}p*y#r)fi!GPAXUxv(Dv^X(n`C6QOkqDB6{tdB-=~m@9YYRZ$Q^Mz4D}4 zFFUFtTR@dK{@ZmS$m$8ko)toQqRXjw^MA)3_qo-0mAL^1JNkr2=7CmsF}yE&sacG1 z!=5Wy#kAahIoArPq(*mhHRluSTs+uWWIKR!bjR{jz@0LI(k5DscqJ}yR&E`TSO-zbJ zxFTmkx0=V$p$J<(yl?ZM$0yv^4&*o`(XM;K6j=D86x2X=STUSCA>ogDfNlDk4m6?2 z@$0-W7rl}*2>I|@e7^6D;|Nt^INT97IBHZuO+9;dSSn4mGQNjWuGKm(oKaSQoLd3Zx&w% z!zl|59v(6O!YiPHGTpemy}g>ZxkH_B_Chvsb=2r72~@R;2)TmXv;{dKzRcvA#$Ow- z?1G`aH!K59^6AV-D&S7y_|1y?ZmA5@ABM@Z?#fD(7Kj0%8P0RJQ==3~rBzGSj=g$b zgj5j@njqF1IE%L}aQ-{e{xQ7}K0JE-&+7xf!tDoWvcBe^wxM`7T5}Ryii3$jftBFJ z;M4-li1=zII$PaHR`DQ}!>S0xQ}gZ9{jcP+t4m?8RHfB}CESU)MBh;blq3;bIkw|M zpl(mQ*Z1O&fml>}&JjQ4vB{7TTzPGj>Ku6%KGvLkIy3|Jcx zfCsJGz)cltWN^Z6%Xa#~6^bG7m@s6##dcl%1zQA`saQA%sQIEAx48$&B8y_~x$^U0 ziA(TN&lHV$WGZ(=*niwYJoH|JYNNNt)&)nV`gEt7MJjU`>$T!KfV!?tgWixJ?m6I- zpq+9c@vqdd)e$|`jM7cC05(3*cQ`pAu~cH28(+-B^4d$-{ard#f+yg~! zM(<)-wwdaW-Ap=o5G+^v4J!K=a3-MeQxht*~Cjc7$f#dj4l%xsZx1N!4dQ5~@kMcwcbj))ZEM zx5~&p94#Rg53d#U@npcj*_3j{d$ry-H2<69CV5kWHoyzc%DkofCtgr_W}YbTSh%L4 z=^d;Y{_8-A$`4oC&P5mlxbMM(Ly_hKLn>t)8nUo0X<4A!>_@1%v&&?pT?>QMrWtFGkD{W^p~4qIoX*1~M*30DiT+P+pa;zfoCEyPjh7 zRtpXuia9>|4-9J<)t2 zIbj#|gHxboF5@*3PX8In3ZxbFAnK(b#n;JB4!>_etVWZr6{ zxFtB9bJc)oc{vW|Cij|q{TL@69!oK`4LC}X0?d0UF-kkJxB#;YD5>8JkYkw-aaHtNd51i&b^kzn+c~k32u=j#<0iRRXcWC2DVH z@Uv63X7<#_8+E%@a1hL$bfBA^Lpb>F<9eg zyVlW1CjTqXp}($3hYpjfM!)lRB_t+?<|0*mSa|bi89{4s-*DsTuR?FKvJ$|+S*l69 zJ4z&sU+h6hHn!o!bhg{(e-J#(vI(Bxammb5wWa?&zMevJ)bum7N!%kkwgI8K!TuTz zNIyDb6(#mrO!A#sF8{0-PJ1%OmL)~k7;>>KD~I(b_RsCkB-3R;RxBA-tpDk65{G7}nrWkPk&}6;%i1oTQ!-JYgyI*^~utENKC8NllJlV+NfB9hSqm zKPK`o5ji5~4=j_)`obwBpNQJmL44qcg2)R(a(Pa&pT8>bunp@6oxv6Q2%Q#jPKCy1QMY6yJ>4`+6C-YYv>9bgr1Q1!6n@ z=})MAe$LkC(~T+U{kXW9#Wfi0>oMh|G1wwR2S7V72HD!0^^PsIa}fQKPbMq~QKw(( zQcQiOI0NavB?mzB>&QmN`-*;K7&7AD7Sc+SF%@wrd3FwBh$O6f> zwws%eo5*c4R}4(WvzIVoOwg}dC(bL`o$}w${}3gkM)SpD-w|zh^m}S(CETJDaD83y z_oNRM#Z7(06&K;ICR1~fe$tV7w4nyVRSuBjr#}|pNx=bxnYrJ&4rFv_WEbp2^%cx@ zlbgC5)!pjaJ>Skws-nCr5N@-a?q;xDS$jefo!$i$wbZuiYVXXKNCZP&yqPm9O&X9e zXwn+J=xS8uWq_X{qqpMCX_s!Yxr~huCU#^ZmM(ZxY%9rVFY-d(UhUttxnu&fXWj9* z%X<+Wv3p$J3(SVbr&Lzg+PEbtZ|tO`kT(8?IpwZ-fko%`U>@-^Iw2;|vbGG>wVqj} zC&A{7xE#>ylg5o<5#Fy+-B=^VN^hATycxu{_olJ96GtT^Ppw5e;!wy)*3B<)Cpz-} zp4Sza{mrDilFPAIfy2jfH)|wJCI#}<^^n}7$wt2PzI-rEifuNr+$fZUFv?m#e;EM6 z|DK>l@ui~3(r zb<{tygCH`N;*ha|`^YV38{Ke8cnWfqZ4l0ZcTfbD%Ml(a`3X}0;F3xWBya*>XI)n@ zV-;`w0gFI3>$e|Oml;jb4rZZc!gHm%T%Y3Y<_qxWS8Udo~46IucZrRU|JrAp>W}+tqn#x*r zkiW%r8;Tqb0PhT0S>|24z(lI11*y$h#77WCi7V0mm5b3^x5&WPQ+>~5sX8C4Jz6WF z)u6p3k}!I1>b;iT?NH@;yc89?<7~g3$$5ig6U-jQ&*-)zid*=x`-$+LgUOpF{3Fol zykg7Dx~0&6sI68D>v} z!T<+COmu!m2T5#=1UexfgrD-c^o~z+TQg8L`UiJmYQE(};SgH2k4_iz?sA zwy3zuZ;`et5@R88|Iz1n*cl9V67z!K<0dir{}T};g?lGc+j6Yd@bb8%J>))q=)l$h zYgwL?AyXRJiac(~AaK7r)}jc|KhlEN`kiZc%m7RX9FtAEdI0O)!biA(Pg!Nz9X|%h zdQg)G1o(izr%l5Xyed-hi*Fv8iNf+fV{Sd$?YNPj%6;1UA-YvUeVvJyZoU_{e6X&* z>Oj{*c&Bia*SP)|74&n5hCYvEcZ^edZ`)bjv1R0mnkjRE*e9S3UD$C^liM%?v#^*+ zOL8UD%zeP?BmjUg_R*bzatl831&U<#2pTXA@WB*GNphHjSNC0tufPh*g0qYoO^}TM zh`hJCfxs#bmwjH`-e^pykB3uUV~!E$q(<~HeZ-9Xip=wPXveBT;v``|kS3-M!wYqo z|1=?l60Q08`bwzmo#)o3rGBMz4?Z%8__r*X_eo)Qrx=Jn!!B38Lt-p`xIoU^-RqNX z)nbLN&71&dg=uk)wzQ*l5zf2QdRXn745XaFf_muaa|vVef5g)rW+*TeY1_qk0A01`JYW6`K@T7?Ie2 z_o&UPa>!Uix4CMXO{a7{nG!i&9_%>gWJCmKPWVWe|NYJY;9%`}H%={1AZfW3Up7Mt z0WD|>YubJJ6vpZ9KkX;=2qzqpP{vgsMoYhhTI3GUTt3ayjYj&UxgVob6|^N?>~?bS z2H(7xG%s9Sl=RF?it#Oc44oxpofg&-I@zDU{c>%c4@ITLxfvejRdB{UeX56q7w4MZ z!rhzh1UVbVqjz8Gt^C2R-^$-{i3~ALae$ZjIuy=lrCQEle;y_*kL^d#t=k|(erU1^ z5RN|@y2J=le?qlbrAM&CfH&U5G@!=Z#%a<_^ab11UDlR7Wty(muB+DUrt6-Mlo(e2 z?qA&pZ}I)oPyVu_ha=?GS~vQ0dEZxe@mB7EMZjDf%y{vG8D^RB=l(~EFwRD0@6eyQ^_P@0wU(hvBxJ-e6+oMUykYMa=Bk>XZ#tV5WYsNc2+=h0AWhQ|>S78+J$37=Dw}K)VQChr z5JPqe`UUhrYHZ!vE_PLWKeAJ=)1-9gr_Zy4+U=6NQb6utF<8bEU!k?L$Z$r6?=H8a z;)C7kR@vu()j*Z>hU)+{elnNn)w*XW79n9sIWju7C*ChP-(=Yq_ex0___Uypf>+fP zw~_gn`n-Jj@&UHONa?F<^%UUbpw*T_l3ZP4h*hJ0zJTS zL5Jcl5*!($E@v?yfNK$u{%Uh5Oh#mbUorzaCmkW?4|+~VuQgMiAz5toX*9xr(agrG zHin#RCQj_m$DRIxE0et@%ZQvTBXf9GwDN$dh!_%^OWwM{jA8-=Kr?D~i^yE@^4a6q z3ft-7Jh8+R2gG4p4E$v#g%LU5tr0+2yuNxS9Q*+1Gf|7elw}m$3F~V~sIZjK^YCY& z{3m`Flg3p{Z(Z_?imB9%Kf7=Lqk@o3NIpwegOoa%r<8*OVX zR(qE5l0%g*nDA3OD36pzyLOZJ`NA@;Ql!}hb$Yw z$!7Y&yt}#qH9TLk}20Ta?t1fj7TW@kExa5`WJA=&W~ zhsE!0r~IgMsxOrmV#&FtrnTGFIme-*5+?ylC>_263peX_9!o9Wv7I+d3u(lv$lCsv znIfe8& z@44vsT|xIeZBeYps2M5Ek;)0wfS~FNvVT2fep6s$A0(0-Z7h0VTWy_Y#6TcDm|K8l077|!>8%9+$Vt}f&3;OoyJ8N%C- z!(8xS+`_e0a_HR4A*gxs=f2tX{DiH|lCUEN>5`2!xA<<+hU$<%)2*qQ zzeymBVpqkQtU7kj$g)W#)KH&fa(;hu1>*vsOhjJHE8UjM$W8%8=29TXF+4f9^pVKR zyZi8lYv<%ae5CNy*#%Ag&oQ^7n~&>=EHJxBBIewTDP)Pah1u|BfoOhQv`v8dR0t;~ z_GjGO?-TU5Ll0*B>-5^YU5Okkk(6<4^b|#&U#ngOW%oN>$o4u|O*G>Tv0I56*iG3~ z@@_#sC+pOP$?8h3HKe>r2dr}i-(oF8|7sO&T*Ty*MVAHhzfyv0%6#QUM&<|uT(t(t zzbVUkHHa%bSZB$Va&YBc(MxX0u%~9KW zHOCa{c9AIMH#BQxahp2k&w$6XWMkQZs55P3i?Y`sZCrU%bt~rl(%4fv(3$b% z2!vir_lly-Ars+DoG*7imeYim(6dqcRZ+RIIVZE-i4s*mU;vOCjWHN%ca3LyoDs$U zmY8FJ*u}pw9RCsiEVR?80bKhjD+$4SVNL2*$&5{lo6I1a7pH@|2fDWp95>>OE;vD9W;OvnIY}Dpr@6ZKdG(|!Zxs0A%P)d|DwHcBf#Kg5u2EX*X; zVQ%&ua~YX>&X)pDS>X4+fdtL6_1pdyCS^#Fs~+AX?{N5iM9A&NIG(Qvxn3T*GBO+x zLa!y84l3iz%Bw0{XO!CO{I3Yf8O)1$b58Q1YRD@LzOC~cRUo?H?chBPQLx7tIO)-B zL48z`jX0ybC)zlm*#Xd0>ndeRE{bw9C3}Xk=nCQ1fc`K8ig+x+yo-8!Z>k7VC|yOYufAzy zs7vK_T(r^C;3ODsryPH|CqV@d45ch^*Jc2HQS?ZB6-?qG27}V%SR59eG`4KM#AMDX zvt&&h+LP|%x^s;W-F%}3T~0tzp01HDSX0D!)w+q{Uv00PX$}t` z78u`hVu7R06tWw!%R#F0-UQ+_7PD$6=!V-vCLtoE)hERW{prCM}H!W@{PfW%PbzVhIaB)%B&7v)m~aLqjLk z$;;A;ra=c08m6Uoy*03Y$i+LK@X|Dc`{6>n%c9NJuz-3qLXEGaTuk%D5}S#~oqc#U zTOp*?SM^Ndb*Sc>=?i%p@E8axZ!!!MAR@3ke+jbR=2p6o-IRJ2Kp-6+FXDN1HeQ-1 zx970CadB|oH7D*xKQCH424s7f;(r7zp+3dE@5Vp4hF#LtC&0)xCm{d={+m(X*8RxN zy}NtwV){S)a@7372oSd#CeNTLk<0}YS)hd437qb2Q~c#(Hc+J+^?5$dvwo;a2y1@XwzHC!Bc* z)Na>LOd3!1kEIFcFGA6Y ztleR-^Q?n#EvveHX_QfY|Q{-%0Y$t_}SVt?hS&di3PZP5L+LvK()L4Y;1e8=|`9 z!;Rq2RaJq^IsQHozodP~W8N;nt2b0@q67(yJaPKJ!dm87pI>t_1?3y43~G3*QK?=c z;5pT&E9SWV-hGZ*xk%jmL(;ylF}k{sR-}& zF-g5Not2riKN;H!Z?-dEvEsOJ<6Xspr{Jge7Z7JB6P2;_DK|uX;cC)mQs%B#59S?* ze2{=?C(6xCWOk^9C`$?|Q3Y2NO|1E~fKh}HW$}N|F9w>1#=Nqd>h$#bj~u>&La8QwV~Y zcf;7~X!MBZTb52bK1kAkU%{T6-J+gfY%DT924)9j5}Ugq5VlxrB@Kgn2g|kisVLn* ztQRvnGq%00Xt4|J$k@WX?8L5i8eGVVC!1Y-6ugr% zi1vdpPvc_YJWPvkS?0|&bE-TH1e=N@(62V260Ez@a<7$*a8ZP4P!J5=D90@v$S^f! ze!I8xQuQSd89txs%O3>EN69zh<1{gkixlovEuPNp65q6)gW9!QQ~(m7haKqR_m>R0 zZ^uZK?T1UV<9z)!&_t&5A9vC4$?XJ{xLM6My#>oN)(*3sl>y`gZ>uRO6WYiT){S*piucIby zvin&)<|+PXW%{1sXaz2|ccTg60?~Wpy`ZxAzTS@L$5|LvZ?Q315L5^BougL6Zk0Zn zJjA3|?Ymy70BoB73#C|B>OgMB)h0@Z1?5eRL&-b1I>gNHMy_dR&ARoH25KJ^or0 zM)Kg32(q(V!oz;R?U9C{T76U=^?Jk$8#oUwuro{6f#*jdR%{k;3RZ(8RWJD)iPD%m zbM*<$3gNMId`YGgOf>rm2Z|xMHzP*x%Zg8l5;TXT0;iZCAlzFkL%99fU=8bNbSRXM zJEQSLk0KER7=nGCu#hY?ENAE1Y=TDPU;`(`S~HSn(b25FueHeVE0s1kpv!NKH!8d_b|u$Xi&R2=kgKTG;l|8Q#<&LjM!otJD%-Qy#}K zN7vLdz6$CyMkO|yi6_D_C!7zf<;v3`wS{N<{~Pq*QHwIEH)g@7ZP`PPSn9!dJ04Ez zSVo#Zi>xJbx1xe*EqzWAsvRWHy|(?K=*O^vnYi{6N2Z|4nJd>>MC?wd5ar9OPx3s(w;a|ar{FYY=WyU%rHsiAqdI-j-5}; zJelpoM-WQAd-^}%w(!np+(Mcl*o0(aDqcTQt3cH!!9}i-hec8hZ}G4oY4tN;@&-e< zyaRv%geSCEF|UwL8XDQ;cmN2vzbLfnZ+A=!JacZ0_otL!U`_FE4NikxW3-`{Gh?`z zb1pFtPPy9|HI1ByjkcsAdl*v@P6u9XBD^BttuEps;I&1jN}IUl&8oFV{eAsb%tRKm zM^ch@$R1Gx@90Lc@nIdEMa@NhYL2T(Cioapn?v26KbtZ26x`cTbad`IaQ$q2{^5!vS zr<|@&f6SW5Eex>OhIgz}+c@%EL`!1!c?Dvf-+4ETb!E1E*8vL$ERqJ;>CV}f&Yuc# zQUwJ09}iK8dC~2y{KU|A_{lx23OX&;#ijN?W;TSXPK&o@KfBT|aFx|^fFC?+!O(Wn zs#0eGLlVpB$4XwjuMrTKhP|U{#*0kKjjamiO&%ZQ75yns`l8b-Cs$Sc+%%s3U!ZV< z=C3t>AEDGy9xI`iZBaWQ``d#odpFGcWfd)edO79p z`DOUj{}YAIG+6{WCt@UD3Po~?jROg zi&X2-(i#)MooqR=BjN$LPsbIPGP7eAM3g$>r$c zIg+p|r!w^(=RO@^Z4albTxPM;=WqTt?x4DegjTtpDqV?e&x8ZwIo@+Z6zg2$_cm6* zy^4!{%IUcCYA50ae;b1TaTh_64HE61=ZNj=%>RF znk{LQdUCSI?sgYFo+lzE_clweW4FOSJ6sR*r9Lv#3GJYbcO`P7IWfEVu863E6~xY% z{-nNzcd*gbHR^H_k#p?|1kXxNg=gE(GuB#I*9#c7#0@y_2SMQCH)!KHroyoeO7fTN*;V5s?#e%~h!r7*V|xHb+oYxOT7Ufp;QF5g3TxF8PNXi20Bj}ukB@}z z28ch3)rhWoBAmpfRqa?^V_k2@ew!-R&5r2YQ6z%*Sz3`tD*^aqU}|7|*=XgT&i4E{ z^HK$_u5Bv)cyjRn?Y(wKnc10g3xkveqPsG4EO+;fMOpmC;tS{)dWt6rZpY^>W#$0= zuc+uNc(>!5JD(mOx0QWX*B!Ya2Z8!h!tvQdZSwEm9`(ms_dE4_vi^p=EfN8h70ue2 zh$iuWWD0Om-Q=S^xDEnR1iUGb5!_D(0qFUceOBRCcLivcTh@!2tOxxqi4yN2oXRud z`42>`POZhRJ3H)UW#p)$_q9hK8(S{~ysYGyyO@j~jtHfzpon|inZGGHSSSX0iT(0(5G=*6oysuB=m6zh8) z#t<=Az&)cy3iGPLietWNc5S$^XeR{aarZ%b5abue z$I4q+*V^Z&JHUS$^k*dk0RLY!!0;u8k{4v4UHo!S5cDc}OMCUDg7z{`y9@PXsnE&x zetdQdXxW1DQOtg$!nBW;Fb*TmR+PUk0+TdQr$}blU15jZ=}@}p#TLrKc$250Ky)K` zjEZyDxxB*#;*U;MYNSaQL^1im4XF<^qEd;KP`|kW`kOUW!6S}S<2){%ski#doEBKc za2*wZHMA83KqnH9v{SxI$B4l*j>&|&+@`FtxoIWLh|wcNQt>n9=%a^9-lmw`iYG@q zUOZzpQ2^C7;gd-}JfY0)jeFJl60^oJC}MtXJ|C>Gr7_uU2U{)2SHE7;Me4sDvhI(h z^nyyag08NUK}{}Glj1qU*pA}NQ=%>_L|9Mo-*Hda96_5Ep|9lvYn{d3r*Wb12#E2p ziDl~ko{uixxAR)DffNuMGz(~A5`#6QVE?K@zx>1!##!_xOgM8!WxZwU?EQ@oxGuZM z=U`KFS;|jrl>_l>7$hBAR=hdIS%O3a!Cvu%FnnsFT3(}}6p^PY4!1Xp%E=H97?l{- z(dy4>hd@pUL!i-zi$lJ|jjt6`+o7YKyxRdZLc@i0c+b|8g>S|e5whp18D_sikOH)^ zJ=UL~ScJU3(GQt?w>W|3CcC*SNV}QayutV>HSPmnpJjpngG?PcZB>}=oqedTyW)4c#!FwnuE!V0SN9b$H^~CEy*jKQwm> zZIal>9t+&CR{P2m$M8&z3CM`pt%? z<@6|>7v8(XglT%;F0YK8zL0sL-5%Wfrq})zt}EBQ`&NPWf2eEjBRqr*@DAoyUBMx8 zu$Lu2&*IM%HPSPMv865u6rc3W&aw$9q;f-uAaW);F!{!{9Uu$}c5;%zaSQ_iFZ0`i zVL&dPF|~2`ZNMnF?7VAhT`bL$=*ftOVrLkhvU=R79FBBy9z&jY{_4_zv2Ml;= zf865Lub)3VR*_WuU%fwuz5qVHXP>~-P;_xdQYxR?UBWe_#ASxKb!qjg;@k!d;Bt!F zJoWOeZj&hWpVNYUbLG=~;^zHHKO4j^&#wKh>a&|&CQ9{k5K8&y4%~EOa=(j1V%jg?>+dq}Li+fAH`RY)A@!QoPq~C3X9T&fySGb*UI2G-72z0j z08%gn^mrl8@+Xr413&|w$=AL(1pML7*DMlc6B!>=^h+q>CLZN9>(IHF7ISTlMiDk% zeF3h{RBxQSM*nETLxw!1lRnwdSeSX|y`&7tm?W-D%XGl8+`O4#~S4KmCgzdBjW8WF73R4Dh;oBh+Jb)W_& zj-bMr9veyzGHU3d0Ho|YakOoy3 zZ0;7=D6#(Oc;WNePCY_}9`?~K&pRl+W`>CO2JM_4dC5?J!`&tvx({uEL6H5*^RYxW z;RM@aVv#`uCfrhr1=)@?{&!ZnjPxephY)^fO9r2T8C?p3JZgD#3YJ$Xv<0}=JYna= z?&@m!-0f)m#qOqoc)F@fy+8=hW@X>IA4Xte&pVwr*w|NClxq5&PDoG;xM5jd_8+~x-Qb4t@DYb{1VG1JYIw)S>~9Sy@$>U!Rko5>cUKtcmqMX7-A%RgP zprzIsIUn3?p7!X2{5)j|b9(F3aELu5!rflKQN8jDxfQ2_QZ@D2qYymC8H$d%^ zwONR@1+VjLdwPq7UM9DBkygOqo#O5&K-Ji5LXrV*r3yRid4{}yJpOK-vD+MH4Fh$oMH;@23No|N_ITZtW>NuKayj0Ct|$Ih zifelKn?q%Y_}erk*_88S&S1{#%|fMhjPOL7Al0UWSTY~&Sr9BuZ~I9&#KU9|7mHfe zaO-Dzg{!O)VO2vRmghE+B#QC`V8|6(Q$Z_A80;*B*J$Q?BZUUDOIwERrOSaLJnJE; z-|kSMX$ zlRv)V;ttz-K81bHng{g>KEBAVT{e7t`FKq~iaPlkFtij*C=fwzi=*Vc(6j8zD|0$s z_B6P)b8R0_@O%|5Z6os^p#ZPlUY)o^KqTU|V{TtGoO zAr-j{BK9!}+I<#|G#PB@e=m%4b51B(7?;eDNGADkX)N0OgVnBRctAUQV$N~mih)fo zXI~(sZ=1cf4YjZu?5uUC%%tH1B=S-MybmCS+b{ZlN0vE0qN4UnlGrzNG^jAH50vB@ z2REK>`48s`3W$MdLazr~Sw#Y&PT7SH4R;@TxF3|LxciqDCGWv|ILOG2luOnW@w5h# zsa-YAM(uwg59)#5Qq$2q5d=iU|L(Uj;NZ-<_fwXu8F0cjF1!yFr_chDN9;sSNe*++ z-+tVjL1ZPt_{V$W#f&}h<@OMsdoQ;Y-=u8$5xpiRj3C0OT4X?1ljJ*#>#^cv@?>Yd ze9Ea5y;0j~MUat}0D;@}!iKNf2I)yVYKt}&*03y3Tlf3MkR5DVMSZLWXrW2S_Md~C zdGgM^(d<_Ri>eu^6%Q2DyJ38u#^+@8Q2ereYepYiq7qFK-FZc$8u1x1bC4MpF*eHE z-JR*Rd@aBY&sQ1Du1#ERiQuhNSDDK-iz$-k%row+Z;frxKd`o+1(FT&#S?30tx*o? z$hFeRKJDEEo>97nKl9z6Lkz#9Uxxe~!x;uq1yW zEByuzV3m=v_LS-(PF1C>lz0LVUMrC&iI4mLIr9ZvaDPI|s`OWyQb7kAL`V>wu#sBb z7UMQtbK{iom-+S^Axwj?4XFoR<&9BHHp$5zUJwd0)0A6f(lEgO@R^BV(CyvH$*0~q zBm=&+Lc!M>lN_o*#FI5Ps5@BiyxbR{tG$QbYK*6AE92jB@J_@%cO=d%Lwp9l-_?GH z#mNquD&B~~B2a7?wgYaK0+1GJ5b=krW~QMRA2wZdQfjU|oGaj340X9RTwe$>BkQm7 zw|v`|ItV`^#`!8al1BB466OZ9)GAhj!$!#(rn(f$5+Iu`;RXYe5qaW0-0U$U_Eg$e z-W!&eK%RGM*4?P(C#=I0-(^RVgs7?Os_y)A_xh<+RZ>>fQye~)@R6Vn)MpZ-&NO-q zn3T}qhrKLk-Q zvBm1Vil_B>6j2pvBrFvk5vqn>g$1e#*g7_vHB`^)B#JnnzX#Z$RO&C%yKLPCCD#ci z!O*kLur<-0bEI~gr@B)m8APp=S4#xH+%XTOrr#bos5&j&3f(I1q9GO@0~~OWv+;gC z(v4VW*#)8?hmC{1WL<0eB;C^x-}A)DUyg9Dw1)inW0(%tM0#lceeVs^)jvv|>fc(fY4((L-~6f#E2~9)7zER~FNI zcfvxP;Z9qwnx1`*cmVb*-C~dE2Zi}39HKbpr$Q8&saivWa*}3Cy6pbJ9oc~JPxQ?}WVJvCP^vvp0%a2~u^XtrJ`dh`C<=YC$yEOU!Ry%92pLa*FR z*lMuh4~T3UgQZSIsW|}G=7qemo1&P?dY6gdZi=Llf%4?f+?DcT6#8Vk7~MI2HO4n9 zI|$h&pMiklJqiP`d%Eb+NjYAUw#VG(+>1|m-xU4FU2l%CW%^j2fB9a<$C;{2HVSG` zSp(O zv<(|_p~Vx5EpvAiE7SkS5;SRS?V^mSwQxLvSLX`p2*+Qu3z`XgBVSH zkdLnmuc|{K2gti-U5sY$e<4rU|3?CPDC4#fd)0(&@odbFv`Mv{vnazCWzX^N;|U>| zyws1b`YP&@LC|acfriKRtzXjr$bl8KYz;u}R_d81empr#*A3QT^?%-z z)pyjV#&TyvVzZD|N^3ELcXEy5qv7Z2Zcuo_Jy4Ls(~6U$1^~8oVp~k)-i`$|6G-ta zV1KVv11ty}tdY9bJn4~gyW-5|c9)ersD=8d@>0x6i|8NSr|CSkxCPhh>+N|q#Eqd- z)eEh6UJkNZ#RN`ElIW>7#15JZtEBjTU)Ud{=mv7yimam5^U)f932Q;W5>dM%vqMlv z2l_q(%6qJz@o0O*M34;e zPGdCfFQ+dWrW6AQJ#0(GNCyY}Vvul5qA(liUm>i^990b2xYHK*kq+x%bP7T>dRCsH z6col2n%?P6RPh@b>H@tEW+l-$^5K6G^X7#{1w~kT1hEYwV7{7&YZ~yB=7_+jB#1Aj z(&|il!2hg347|*<<*#rO%!TSfJx9sTawK#ZK(~<&dyX|odW_@L0S#u&!JWne#8-`j z7XivTwOdsnnf}XTCLSbeaL-^xz}Pnw;GL3Yvs7-^<82j07FR+cz^kBz=bx_#X_gpNS|+fAbfQQhy7O7q)Q)Q!3B99iCNAbJ`@WZ)0-39Q-cbj&y1pC6z2x=RH^Wy?^WIrR#`@Ym)&t2D1^@-6s>PDIB zN1X`^%I`@dh(FH!6M) z9i%|o%oq@f=*KmVfeI9t{eU?@b1SFZSYGIKdocH;Woy7hE7;aK7ju16BKB!j^5$|m zF0~QUd2Z+wWZ|+?4Y&KrDW^8 znFVrS4H^A0xO$Ov4Z@a)H$~gb_nedEqt{ymLKs00oNo02qO_KrABg{Uq>}W*^NWSO z6hv(H_|@>L2n{c@X61bJ)$du07$7Dg*y%+1!oU~w1LDm#S}fSsR}c>`KL7HR+8N24 zSSo7xM5EEO?mP_DI|Mp-tZ2IL0xn-80}Z?y<)+a&M)s;O;pJ`X5+VFpBNOT7Z@eT- z{P%xGywij=yzx5O2az(Tiqu}K{CtXBHE;N(9O4I9OECSrnTCTFSRYqfMxg(*6a^MxtHuSpRr{$jJah0_^hcV3?S^1W!fs~}X_O48 zdb?aMToR@}`uJZ`=cE>%7rq=+y1xFCo&C2)rf0Vw?zSO7!mzI`NSNMde0^e^YAKZr zpWibSn^osOyiM-&yDY)G)Cps7QomW&Rh0lh0sahB%`am5UUld77;)(Ko_oJ0aO++? zAo^T_OwQ(Qd(!nALL2{2DSI47U0O$AVkf9emQL>zL%dI48&A@h`k!&Ol^d1cI*c_q z?^qGlLvd}ns#JB07GfL#;rocqlSJ z9VG9fhkbH5iwGrDHO*FuJ?rOF+96tXqx*#@xa1yT(lue&uO$ig-HJS#ntJH!=fmyI zn3dp5_h%=e5MkkKQfZ*4D5Li75C|btPl36ua@)cChQdam>lW9Y>(sV_)c0y4Q#+d@ zdc4Z55~V4mK4^M=QtNJ^EIj)|$O+DhMHT}>C(4rD>QBmcOu-{>co~*`ujqTP#kJW0 zM?kp0b@qXz8h8A=pKdrDUh+sA&P%=aY}wBU4pOuuMrd%xRVy2Nj^4>$A@?>$Y_lJ; z*BQKAGwxEk@Aq87zjW6Uakk0!?kN#=+?Ksf!8?H@p>c7YH5#8NSaU(l-X~2D{XEz}Lt_%L)(Jys_QbX@dkZT|J!)0xjU?5X+SYye0kM ze9sTqyvhWVZ7rSflDqJQz7)H7H;z=Kc5$~$V$OxMPw{GdEjh@6-0LRP0zQ+l^I$Hy z75aCG^Bc(O<$!*U7X4K@3bS+6Nc6P@=L6pePX&6{^?cRpEIJs8Rx-U^vbK2=z5PFl zOw{sb8OL2e!gV4VdAsq3`SQK_V7H8uNlpyonBF_8pLN9NCP8yf{MFLVgVD*y+lR?s zo3FBef+qv7GnFhca_)wzBqPs+*!e;lVty5QPrJZnzk*b599^8PET$Cqw-{t42mdUq z7hj-7i8RmV;pS3p3L?u@ddJlG87wh{h!*)Uh?HoqO2;JQC4E>BYrkzMf%2Y}F3uRM znUXe)Fg&gZFs#Rj*0WLv2|{~K;ZD~-&wsSD8yJH8e=@Gz>RNB8YnLhd#rNOc59+e3 zDOUOJ7!&0w09Mr%Gi-L7`B*%?3{c+mXt)0VcqQO)J3BsVXf4XKeq;?jYbv<-a@+nd zD#^||9A=3N(C2b08@axwhs^kGnR1ZUdDBBItDsP(R>B5N3H?Q+(~OiV`b=^NGXcqJ zF)uL4;u#Piynj5sY4mo`nOezFf4vmu9zOD6_E-z<&Fjpr$#kJo>u81?Ji&(!ciU0s z`CqnP^zirE1@pPGNi(5UbluR?{wj>6`f01eWmYD^kRT z%q3`)tx4bk6`M-MoFdyhMFZ_xp;|(Nn8r-K6T(2r;H}Jowj(=N6E{1=tNTPYXEelk zujZWP(rzb42FjAaKP$fSo~3%|9DhG0Uw=>no^zrQZfKktT9<;=zYS3%M?TGQd%V}y z12`wVB5XmG^ql#`s<5Q?n8F+9Dg!^y)$`D9lWxp)gIcE3+$E*it7^}4j2sWUvAR5d z?gM=dy$GD0ad~@t*PH?#APoE|1au3vdRb9dFc^MKfe16u4xKT5PJLQSqKNtKZYgA{ zo+fD}1WfVu38c^o+I5hY7fo=HcHOWS&aAFW%e&ahCxn6lhL8+GO6h*dt)yay&vX+# zfyD&v;=3u{4Y!|VX+<|#G@0%^$Gx%mU2i*r&FV*$6_}&s8$Ui-?o!fyN~Q>d5DazI zf2~pScH?%rnn5@&AbvSnRf44WkvlKc1EV~t)IBVksyp->rZlQEIauH3$xY|XyC}H7 zq+OL?8!WCA;zZ+qje6Qt6@e8W@VCJmyQaBwi@JeOnc6@rpI^0JM+C#69thRpq7KZv za*^4J?B^=dA>@ffKhlmE{rs>mKdKEYK7V?hw*{!uQ|?u>RqL2UdhC!R{_CrZJaoe8 z)^L-N=D6Mhi{UX(CjC*wI7=}n5C24w+a7-mRk$2w^Q>hp{XgjV=j(G%L5-rvLch{J zVokan6+F}c<)RtLv{bGHoRtG~E{-4tVl{ELsAt9A?}L{Fo~ekn%x_^IZT&wy{JF+A z*Coy=ZM-*!*b7WZ&g51-k$+|u1U=J{G&gU#VO{hELVKvSW@~uHYLmW)Pd-0Aq=R`gT`kV-U?S1C5!Xnqd$<;6r%BG`df9QYy#8qi0F^6yhB|2k9H3E4B zEn&LHc(g=vicBPv^Y3S6mY7H!rOiLQIrkxnVfDb4rBkab$K(Qo?vU3>6r=#35yQx7 zjSiq4Ed_F|Cw@fz2N2hCu8(LFwbuW=O_Z~jbAyv^G38EMz`K7vg|%S(qSQAVsdm8-;A)N4 z1k*vK2xI`Jhh*vTz3&WhvP2VZMF5(5`o@NsCfqUQo;VIbBHw}*modV5yhbqQqV6n9 z-cuc=RI#%Ht8Qg<8`ev%WxzMyn4~<=qrT&PJCi0tERF z9h&eC_!{HZ4D1=o0;Gt{-aLJ z&aR6Fn1>Ac7$H;qV}njSh4c02H|{f&?|{{S3@C#QKLD&hcPkZ)Rj+kI|5}r^$02;e z(t{LGm^(4)9Fe7TL3lHPD#-tHNA_=_X`Jq@Y|y$I2jDI#f?Y<;=4iHP^a) zO)rGNlr^~)ckY=|>+}Peq|cI4K)uKuu1Gh>(%+}kQW_Z&W%)@{)3*Q{x-{=|m!*e| zReDmYMX_zbb;RpVKvN>Eqs4f-+ZBfqM|YPxtxH5KqsZ)vW46s|Ry6Qqrykd~6k9fM z^=f<@K1<21{SN|3VXHFruMy%J!=Pb6F`TFo`_QUNR0k?(H96OI)63Q!=H(=0wRS@P zC7s=d)~oPy7ZgkUrg@ZRfz;-xJ?#$g8TZl8SfZZ|e40W|{+%uDenz!lsrrv-l6%I8 z2kT8vVeZX`l=cZTP^n{lT#DakQ7@e+G?SKTiL3V>aI7pYSpQVSqp5!=!3u?txMyCj zAPWLqhzQ;aNOFP?1MvtFDYpP{kVe$@$Ea~1Klv5fak6yQ`GCZlkxE`l)xyNZd`HYF zhA{!LwkN{Gi5%QP_V7zMzu8SR`$%=P7n2P4Wp3<^F-~}@Y^Cz+bVt`EZhwIk`c7Id z_oTlyv#WCwxC2NEx>?DEjg#!YTZ}0z+GPXQ3g1C;QIOmN0XhKIe4-wGk;`h7z%kJ1T%d{h5P#29;XEQ z$*;8y84VssIL2(PB=lpx`AwyBI?fKi$FX)}_Mt3Pc>~)~%5U5JlXa}Yw#4cULStqB ztoLOz%C5<|j`Z+lNEl(D-huBdTBJ`2?cf>?hSE2c{d;>*W4D)9370#(b(-Mfmenr_ zQ~^o(cV5?3k-cr33`U=W96p&=5{)4XF@?+`vmevtUsL}Y#>C}Z4J(lpISDDMOtrrD zk_UhBT;)>uB;A0D%%Y$-+0?k4f|61TGo#4=xFGAPjBp>^nd(SAJ${k=0}6^IbDSR{ zTVs8b9_%1#bCqr)t_>ahh!}WrL7RT$Eli4{(N6KT>S#O3js>v>iae*}Yse%B1izf) zJ(P#F?zd;!-8$pU9+`yizc3q)sL3JHlyx?|?0o(`pMng<3Rjc$ zLG2Yd#oHu78Su)?Xvy0q?yAY}k5%LCgzr&XK8T5N_7( z%8Nf9=0$8k97)Q7U71IQPDhTlC{h?ov%TkXP^m5;Gr}ru`9_woK$T~C(zAnh>x>_h z?p8^CaC_{_kF|yU@Q*Wo@Vd87P~iQILS!Y&kUDhLfXRFl`^?kG8z_NuDzQIQ>bpU1 z1j-Z`%Ks0eR}$ideLL8x)=U0#5luj=QAjeQwWYkRZ$R=i{9{$<2(+$R9B(lLLDMU_ zwxDPMzrUq&(hAOK0&rfU65StZWBrn(S_wd3N>Xu;8ERzvd`JD710qpko_U+gVTqe# zpD=bR7A4lVfw%|tv^xk##mXu>hs~u-J1d{gNh6SWMi3K62nio9ban51v@XwhM6iAJ z{3%&WX@Nt|zUZ9@Nkjrx>Sq8_^@nbB4z(U?xIXVLsgAfV;rfuC1m0jls3eRbK`+tt zLmfcANIfTL(hg`TIuMAMS^tkAq|zDzZr-z?4|%Fh6}wyY`?Rm@+++;^-T*zG0TWr* zbtvK9Ry487b1Pjw&{x((`zyW;eoFw$==i|V^b`7u4>XCmGsBppT7>Fb-vO1HXN3z@ zhH&Eu%%g`IFzmm=RRQ#2vw-psoygCN*jRV_+YP@u)F`wmK~`EqgT27`+8sKbXVqJz zG#dAFZWPzLj2X%nM}tB9kv_IYVRJ*$>7W69KCmF8u))g12wMLqrF?DNces9%E}MZlV}PJ0Vg6EoOeXyy zmMpsz4EJ{Ex$tScMyo0O`rm^8>6zH(t(MQ+@{I)vSfS~fn=>rpZi~h6lQW%QN{~nV zl<==zE@wkl5j%=Cdns6Fl-VT`nKo`^=#F;7l=Dj>>b@&IaVrxamo$*{(yZr!>gaLp zyttFh(TVH&lQrd>wkezYTPDDE^ALV8`+Ln`_9Z*-%2$LSfiM1# z1DGZ<;=cS#HEJ$etd?d7FuYps04LwAK*Qd4PiN9Y3>8ok9Z+>8bySbi-avXRf@C^j zFE@BiTX(0k|+Yz~?xQ;S5 z1-q2&igC*w7o!k?LELiM0VN18j(Q`WbvC^^peb093T3D4FCp1m=oANc<;2{vOAwnD z2p(OQP9NtF8ykCG>|y_E#*Pn;x@ZYRQ___~C%Qy!fId%HqT!bgEdaku3G&|l>!VOQF^_|`&cvG^P^@U${FgDryenmu5Dp=f6sS_83 zP!9M7{1s;-A$j?I?2;!{tnhav$oS?a@-p+`@0)KqA`Lv!mLxujS1@oiFv+PY;6Td4 z8V0PqM008>IF^_?1|ocwp!@ zru$bhFPZ{3{)3h?mJhZiP3R0~;L8b zSr}2>C8o>__DTjDq`vty)}srr`mVdy%dr~7r7qNU0b$skhDWzF`e}ovP&IB* zwO-b*LuE(0s`dKTe45ym;NlUCHI0msD3V3*WvBJ|e7%m_^Atb`xj-MKIhg4fvF8K5 zG1C#38rY^cp)gt3wN^24NOVNxKMf~F#O8p1rF?+jAlWC)*=d}R{ckG4`(flj!}xj> zUJ!pjo*@+46JA^mXM!SFbvDThvsEKBtv$j)t$zV1);XZ71oXp19v{Iw?M$_CQqNoc zS3eOMd%0);+741%FibTzf6X_IxGPdv;))a56>Qc=*BS*G@C*p&BT$-Pz@Y<}!&@i! zN5}^%T;C0wAR0OhKvih}Q`nafa|o76-Umt1zoF{Z+XNj;IG9AE06Dk%ER;6V>}c&Q z3olrL#Vbz$tK5kbz(r#^idK67{4UfMkWf>uhuxl9X_r6ZCjo;vlB+cLmzfO~Nzbd- zYvj9IRPr6EMVTHtPhk#@zpg~KO!eRgz7mleBtL+8Ft!DTG$cR&0W zwOI{#OTAu?}7L9ixplNuxtj1TMXP?7?CZ4VB5w4Yw^$q-WII$%RXMr^q zeDAI<&~o4DBrx}gaX_)-9V3883<%3he%aVI&$f1>i6{mp!~YH${UExM?`(*=lkC8# zixCY1>@{_MBbNpDJX87%SMjZd+F}gc{Tu4tud(_Hgoy~E2io;ffZI-<-OamU9D237 zQ?BZ~@I6bT@(SFz_fYQ|{$uJe=hlQ8{W{@OSGkWL^oGhQZKl`rL_v~nxIfvmIB~$! zZl;HxMN7#ZZPDaU`Fl5f$4Omt;3rEvmdcyo1nvZ_)38tmN(l79NL0f1G}rNr-|WqI&~M(Cz;QNSC;f~%20pZZ}VdT|BKPW!!se5!Uu?2y!cLYj!LZ* z&PZ45|LBSvE$rq=I5-9%)&8w}(KOGEF+nGqA2z|f9fCZS;#tU7mteLVBjLcfnR;l_ zq>35b=LcFtZ&n+>DRO|l$hG{oc9a%=i|#F%c#U4SD)yXqh%*e4=W=YmJ1@)289A^| z*_?K&o0LD`J1SV@ni|9FbIK>`A-z;||FyLF%l+#1DoS@Kp2t6F|dM+w)&I}&^L{#hld@lbyohot89 zi%-pn#yCGuF($^B@Sk5bF!QBap6~Gb?=IIU-~0G1(vjQ=GZ0Si+HwJgVqo$(y;SI2 z7xlwZ0?^E>jQ1Qk6twig_(JwYbK<1(0a7e565endqqNo-0cMkdO~*PzD1C0(b0)z| z)r6QuVtj+GQHuxpI8ft+`IKK2e_CFs1AhfnDiUmfq}74JT3@n}mwb}sFB?w3Lq&^7 z7VsovagU3B`S)kkV#hq#APWOm_s@FjpD;DBSwrSdK>ko{l)?t<$d zLKvjaF)m4ix+#7^LwLVK{o;jSsiX9!j0CEfkwu8u%TMGiML0WraoY!dvJXHbKuEuZ z(In_ABif+dxlLkIy55Y5P=bG3 zR{#+xVHP=-s=F#2B9silqnn&y!0SL*{ksq0#Hl+SD{Ukc^o(a|qj5SrxHJ=>%w-M) zNLatBh@xm(GTUqalV;AAAzhB0$B6?9rTuPCF4y{v5J3;lrlBi%bVmcde#{0;22@&; z9?nWV&CEityxv4KNQha(pkmX%gpN>BHn4+U>9r0>bM>!y@VL#e#~k+hV4|j#bUIOa z$3z-96%3+eS{p~ysm=EYtDB3FJ#t*Jirfl44#%NW$GCj!GN|IXmDASto531`_J79- z)P+zDjoVC<%)j6)_#t%V_IX#yL=g;~AqTC{-PDfm>%qa@1lEM8v8L7JyFfaj6E)6J zL+|MHN=G@U$pt)#pB+op6-Wk*?hC0HY|3L^nlQ$^jubYjBMJPWE#T?m`hV`lwhvYe zQQhws4Rbfc3iYz$xDuX+u$Z;{tKH(!ppK@OC$S>L&mJ8GBp9vAK)I>`liuvaCNCCWR z<-R+qlcNnG`eYQUxP)~9CC`_=P*7c}5R#G!)N%mwY`oLnt4Ly7;LyCi+GnS*#OTYT zi!=hT4TbjnHSzh5@Q2aq;c#WQ$HsjkVil@vUT5z@Ce&>_Zy2BCt{;lsEK=7PKN#el6ENJA-kYRbwx$7(& zT9*zzi~R*s`0N_a>liH=;ERuIa|A{5W!?|wWOBea40`+*#08-^{B05FqM2#<2>ll` zeU{rx1vmrUZO`@h~NK6M}xCi46_%2xAy<$1#BJySz; z&{Z3ZyTcElE&F>;68#{H$QyAHanL%Z8ggo)7$@)MpN7$@yEx=}nt2ghzQf~)n^v{y zFBII^8U$VEp+Y?;Y#PBkXGRw448^DAOCtI5cs_>?_uWbf8|Fq-Z&FjQfE_=5+FLBL zIKh>4$9|)|Ry_(Im@HbgRN`2px7?7J6nPOBL0r?}z)fEVx?%H2N1^lT+DL3T^#*Gj z2K6XmKeBvbyYIWHLE`v9xybxIFwx-b>*Y$pdq|hKRJ}kkz1suN{;I1U3b*yEzaGg7 z-A+hgbo~r$WW_O6{(YqPqyja2oFT0{?q^rD`zc@l@UD=7(cD!gkWyW|s!33{6FETmfU1E@vzT(s?Y+W^*-}1>zPNyRq=KR)d@|gY}nE%#0I9yP0pvh?O z)mKJ)HuHUID|sZ*C9C0m!R1VauwAlSOUO?cF<>0W(iiJ=K#>F4WCUUx2h`veV~4B61+C`Ii!@HGNo^v(#k z&b+-N9Hj?@b7)mNni~ih8b(o&5Yr^GZ~iA-uZu;AifZ14DD2s&9+tm!#ED$@YA~vL z3}-@1JvST2>pIXQx}`z*zPIuf*l=swJ^NzdgdXJS)L>MJftDWS^A15zC#Dn} z?ZnKTMKT79L!sf$eN7{zPNr6m_E}b4Lo$lOX@=K0gu}1YJPe6;6bI$Ns;iWXcYQyD zK;$y_MSYul>2mCQTT&VwSH~~M)(RmrPflE**9M=QSuOcY6@;x!N@V#oaYNY0S)AbztClOha}%|? z14IyYDVcoy=i|p9n~S;D6NrKY!r8bv7QpKd&y$B9LTZBJcdnHS1RB< z8U5EI&fN%=Y7;C*U(+4CqvVBjW_K%qW53_kThwl^NpT&8(if0uuM9Z5n>dnGE#LrJ z$j(HE9v;E0ni5mgRqm{wR1x`fkPlj5c8vVsKvN15*1HWcqs+Lqn`HEXgaUc!dPM|9 zxHUo-+k{WwVV67HmSID((cL*Jk`Ixth5@wsS&N=YXuf9W07P`r(xf} zuvscm2i#>gw3q;==5CZ?xy-t|I}Nru`s2{+y#Rk>BxVV43(=hhcRl9qm!U{5bS9}| zbw1y;Gb7KZh2Rx_N7G+8V$!gbBCv8tyP z*I0x3x6>E}-ejL~WUP_JYHy599nhyb5T*P8Hl|%DvOrJg7bVWjRPd*M1O=Un5wl?H z`@kB?v9xa2(o8N~rAR}2WW86C8m|BV$!I4l9}QELn%QZ$WZh@#PPFl)ZVA{jp8PPB z|6K>bV+lk=PfZblGFRQ85HnTaOQO+`MaNRVJVu|tdXZ9tM)t!69xu{SM}rTr2SrfDF_*&5 zU$o?wJhU`1wQJb!B!A~vTpZ29KPGP6xZ?TmF6#6-As&e{?PZYXMkJ_f3t>7$K4F~j zXa3v$iWCZHMfS)Pt4N(-L!Gn^IXmcet5eWh`dQKYmc5|y9X8<{nNdtc31qOmpAMm8 z{$o5R(LeR=!Y*@n@SpDMG-w@VAm4 zt2++sbDoKtrl5l*xsNEBW;>*2tO!PqP{RI2zi#)HAe(Ge)A3^JZCGp*8vQ!*5t&6g z9$tfsC@iLJQAPWVLG)8ERkcLlKIN=QC@29p5Y5XulX{Lg3-hT(hCd@oZ4*;kBrnLc zdw_91fr1_Vf|VnGYm!*6d#{0NpT-4V{&m6!X>2Jqj|+ac4Tg4P=q1Ft3H)0}FaCXK za`1js8-XB6_)Yusl3nM-A5DR0Bw)vG22m=_^?bDrUzsXCHnzbjE9j(VGuRO@@{JNu zd-%Q+=+Bco=@DM^ROft2?c2TNp7djreoOa;Nf1N5Hg|lXoPrbEqHtUM%AF`A!?#LA zDYnmuWq646S(-N>$^X;z2ef!wc0)xs34o;#S?Q}*DmYiY+ruPdRhOMmR#YWAxt5s- z+l&y8JT>Fh+x`{~awI;ZCX?@Ig(_>XZ;d!17#|Ggr zBsw$iKa>;&kIoCQYH7!vP#{vbE=J#(ZsdvkC#H{)whHTD6cR!N%absd>N*q(qiHaM zW?5ZvKj^|DGkOMIW5Ff=aP#845x}v+=f7`Vdaal4E%ft^Nxzcw@OyzyRsV9p9t)rO zB7hjFA9E#5?J%U`qt<4>o0|tSxBps-b_`1S#YC6<=BcO1{KafkJvC8X9>FQ6 z6><|)jAUNY_`d5+D0khkno6R-EzYRQk6f;L8+V;r#<^KxWg6&LFA9i5qx5~`Ix$zB zPwvc(9;z|4_fP>bFKB2HvKdiqbW-bRysqIs!kbxD+WnvBg2Dq6V*#yK$ z54xzVf%*SfNlEp~H&LmpZSHjc%a_pAqc`NTIkN4wU`?ES&{QDbVg1{km}0OWdT8$1 z+FOLAWOW$I>o$S0Ap4DZC1x}p%aQp2zCSCSa2>8d!P$_bA!R)N ze1q!SDBP7DhJkIW%E=1$dsr3KId?1l%#L#A4{@U4{P*!NFhcejQ6Ld#B&Y8-V-~7G zHWyb<=>;}RfbmpiJQ1awn#2C0G){7{Mv8B*jzP^vY&HxST-#?5JBEqSI1)jYiY(s4 zb;x1MJnJ*x=1w5FS&LdGL&qPiv;k7~?{sKOqJDegZg4*n@eLygX$tYX*epq7j9(V2 z>0dCwX>s=1#S~gRK-LQGyZySSs;KnfnPPRQkEcOMOl;Wy=9)xr7$x+wkxMu(iHpwP zGC|a=b$={AfHHfjaHNUwNgLp7JF4gOEw(%SyGa5J(WwVDt7p=44CveOx%QgE*R@t* zWA}w4im1=NLErBRWniz^%w#lRo=8OqC`;n6ZK5#j+R{5y{fl8k@06Pbv{WL(Ia7@B z6jP*njqs6Kc7J|pwEm#4o^kNBZj7Z* z1^F*rS9}G)x)0M)Uye!7Wj1yAKMV8+8E&lGa!k{N-sK&aVm~^#FIF zo&3RG-c~0S4)=9Y6I*!;%K%?`bgLP3Qb(q8Wkk;Eu4aDA26vMY_LbPu{Ti}}zHpVu zkwH{eX4I=r&8cC_zz^M)P*C4JkB$WaV<-skMu(%1EuCFq0`C!c?dwm_=W5y z?uGJy+}!AkdX&S_#{`jg7qSB(-0CNuGvr>$;j@|6gl{5Olrg|`hZtNdw6Gv=EXlLj zJyHFy&0w#X9{}?3^R- zj{_I53BwL_{MlA~sg9nuIC1I);=oiR8LF$hBZXM}O=M&3`%AMK0RGNzsDU@dJk!mu zAC^&K8ZPGH7*2BvM^c0iJSm>DTS>8v>7YNF9C{JL+!$phCz^j?vgS&=d3QPi<|?x! zV>0TJQCbmaMnf?%(%Ym}|9?kuT%hdM@eA866o*XXkYD?E#EkQWYj=|ASeDUGS8R8&s7ZjF`IswCU;NT%$88azT|vp zg0h&Hcu^V0qA|5@+Z|Vj==Ci!-F8SW<|W;!u*5r{P){W!>qEJ8lzGXhXkxQ|tUS_< zk^$Db65+J%n0;)qaRO})BT>-(^wc)}8DY-SxzxPRXrrOs0wsIPj(|s4ATDHsw=49M z!XJlXsR$Bq7xkjD;b4O>M@AH_w}?SGP#zcDdt+l8Sm&G4j1CqV|F`Bu(JXA)pds}C zuw0<#LVVA~I&0e{e0HtDSs5f#NmA6)uefPX_m3#FWi>4Iw`0^lNBv!6{-pn+x`QgZ9tg9%d}@W+$aZ1H&7oC^#MB!1mx|?KsZ;qXfXq|$Gp72Oxe3XPLaTf=Zr$no7 z=$H}!Z`&;-Nme7YJtNS#*MrzDvbAOuLy7N=JgogSNMGR9J@%D>t7_(gwfYugj6Lf# z?FKZ-vXtGmjX+^?9&n+amST%kSdNz*IbO-I+MrE^)-DZ9b*Iyc_!QJpYpdZ15+Rk9K~X1=JBgbGOD2i7@reUB~pc zw2`z(;m7A0HJZvo!HFT#%RjwUq==7EN#BQ6AQ|QB2sW)UU@UGqf_>D3#vTmP)|RjC zDIJeUv|!fKYAE#%unSCqq6q)Z=k06EI_%w`zfNDW>lIW0#K~#$?0ekk`XmJPrW?0i z`(nE{7D^mFirp0>-CE@)-%>0vP4c0BB8&h~+o`<*#qbHXcq{cKPOI*-2CPFP$PiEM zr193-_4G$qgp;oBf*CTY=Oaen4B;7&7h>j*H$CKeP&SzofkuuGfx*GUI*ef@o3cEo zykJG?!~0(KKH&%vk#w{t>}zZ247Az74Oc zwP1hG3}zRQqW(hAzhn?!*(Zwh6NGhZSgkd-Q6X)bCAX^)2Da$35C9KOrPQ)_G?TU~ zp(Hs1(D3|=BZx<21@CY@|IkO=6{e2rMvTld0(h{BFiaQn&T{dxk#S^aJv}SS7}L(W zDQ65IrVWR3P6EV`9dz5s))h$|KEkDgfW4fOH41fCMJ=(_$L56RMEcB%oi}tLcOL~z zo!$*OyrX=xeq>>_z8iWOt_6t<#wzo11dwz8=Kz#~&fHdsii@Dl&JG)>?GTN%T!W^U3# zDwsgmMv<^8%pGs6rt z!GI=$SSs6l1T>0mLNKZQIlKdw7jG%^0>bmvJNvj|Y`mT%hbK3;sx0+U5)`?OJwza~ z;?%uTFj^;^q3is~rx{?9fCBG3B*_vnsTqO6Osn{_y16l;MP zWd-3H*`f7fS&LRlkWwFPNRaVsN`_~L=_AF91cKzK_re@pmp5$^u>3E~&{vTbg1YO! zk{268_NT+HK}ktVwE$&Uvelj!x7Pg;==}G@CXgH)!MuiB1*IyF!InTKl%T-oWcc;Zr^_q{Z zfGd4-_GB1-k`n!G2De)X2R??RX0?&faT?-gZ#Q#c10W)cxIIL%e$OSRJrv5QV44}p z0gfFazpvHE7+Ai1EsMb=`UobGZuCEnT+`*L;`q#dS*`K1mzn07&qTPew0~#dSC{zE z?ynNQRR2WbikIW(C)ob*Q5;h1=-{f|zL%^Wf%-MRUmNo{m-B%juhRABZ^21vwUe_w z*ivsiG&h60cn!J+OW|4(!C_I6I$q;En(0;|J8mU2W0)nq8?0)%xYEgaY+O2 z7?|vJD2Em%0#m#CU*5s6_H-che@$>{Mk_(M1pngoT zpcP8w-CXU;thbV;CGc?H=>uN@z;uPnz>HkGU>|6ZjUh zodU^96>;o^U7>t4e>UcZ*=QOCPSWM+R+sAR7L3V-5QI7`UtHxTjW+1fEdjq*aL5Ek z4W{{r%+tZh5I`q1!Id<{f1B`vi=O}yln~sq67l$(KU3{VxB)+^%nv-WgOX2p3_vW5 z!K?d?nW|acG|~K4IHMYp9PjcVDKv{N==p5z1&=B#Q>&p3fY%FHkcfL9&0DtL@-k5W zQ2*Oj17%Z+o_?g*VeNTgSnzHWpyWalaAjEGV^fN&6?NrU!rXhIq5^R01hr z$Jdm`iS-u@u<(pV;VSA~*K;W8+{U#$_Iz$a+O zPXX0;lkcvU|cs=nr3{8QwhGOxb3wTfPjI9F#Xu}ys{!@7yeh+me4pfwp6K2D3n z_1`4kdjg+#D{@zL83!Z?X>$7g8%W!W)Nt>YDU)Y#lG#J(Kvy7W)s-s~inrhSx(OhOGZuuvsB=;*@Oh~4 zLR)P}!N$}(JseHqHSCf;;0U6~1pY2{3$)BFj3ePQ5gz!fQ!hgfo{FW*hHcC`!yo(K z8{F`&AJ;U%aU1oLM`FH;R%$pr`QphIRqumT-sNueN4;jHRf@X<~SYXYe-<^(QH zo+yuAdYG>LQWcEbPWhGYKx$|u zf{d{IwgzNCj5>-KcCY z9QcH?^5llJxu9DdpDsNQ6{3`$k| zo>TNvx?D|(lotN@W?F2@3PQuhlUN5Vlqr+dJ05(bsPl-|Q_U;Kyqh&6Ms@jQrlnZo zp~GgQjS}~GAEBt^)p#%n8=Ec>0s6THk`$480}|M`ueqn;u?-BGqnUUiQ?VirGtx$` z9@{Rp46GL>+UwIH`oBNnGv0gE0yiV1u-vZ2;8Hso{$iR}U^WOK#ZBY>f>CMw4V$?X z3(D)+6?8V(cL8g>aVTZ0SSkLwNqNq}Wkw1*mPs}uuWs!gvy@kTAZXRQK-lp3rSb4_OirQ;;=TMo6yQV=dsh2! zkh~5IV;~zwrEBvdXBn3x%^V`XP`yQwC(l6u*UKo)Uk8@QISyB-+1?$+1PgtOjZ?_6 zOhf*K-=3R}?gH0Q=pFou$vYb$Hk}u!D>SuV^0-B_j1^kUv|b2z3)4 zYrf_(2U3ervGz(9pGVIkwQ(-(k=9<|yRsI)Nh9sgNO-d0i@fXc%f#Mx7sbE;o%y8` z&X5}#BE)zb%WxOxtS|@acn<{ zFywU!o9sV%eSU4R7Ao+J>+^GOaYuuuwXU)(H}Dd{bc&OcC_w+hg{gq%bV7%w?wKAb zI1&YnOa6>b$a-^?#g8<1003rqf@imnj<+0wrWSgR=$XJCBUe5_6PWI2MN z5Ojtj@2V?Tsnn~wb z>_@!FGkt~oB}Z*n`sBVk2;q26Gl{+k2C4xzX(yjl2FzK_?c3gmd=`zpbQue(Q67^( zy}mlCw~b)g(i`5b$sB+lXrl--weH1E2Bc&6SgyCd#-x-s+Ap2uyymJADO~S<=lN8m z+jlPjnUpU=l8Fq4)I|_I2F8mb7Mq>gX~3|a18XG6 zTjxfU5et>%nIJ9XuGAL*mm00bA;j7>3l0QtT}znMOdizHB;CgNxqm5z2cvI#|B z*^t32JNxiFmv>!qDhEhR(OA}!H@f{^}d$vq@WfxINGv=9r~8exy72I8rY_H70P^!f6S%E70jJQBBR1(Sg9`CEhIWF+450j*#JsWV{uEN_ zqZ)i0Hgb_mOE$s6)qf^x+1gvU2F!!HMv zXLj?v+wp57msH2RnCjh23mw|w;3V)bUPRiw(wIFEMJONg^ zC5jl8lRgBhN`tI}#(c)9B5@p_gbnqJt#LuZsWL5pl-8fU2zvQSC%36RVXOj(4F$+& zS7!EmgA!s%*kzoPy*!mqM&0?@YePlnlNUaCSbn+8jaT1VwN0!_*vAOg*|Swk{$X(? z^-{U$j;STnr;G|KeOW!rQyXGhOJPt*z2z*6HTetlz(YrN)c0JgkIN>X7kFW5gB;Qc z3e&_R!-HK=HX6#l8~$y_5pMa|JlAe%C=g;>66Lo`%qI3LV#h2vumP{$^bB=*+It7# zz71N#GBhzPU$Y#L7SX;fgc_>>?1?_!x7hgIao4cC@p5a`w`#Tmsjuz;fX$8MLMVNH zUN(B1Oz-9@40Wa2e<7EatW`wD(;A^b*bgBQG&&KBg?a;}r?7M@eQ;e~8>?<)nf1>m zref*%R6e{~YQ0oRua1P{6IVNbzRHwFiY!!B_wPVo#*>xrL9lstXCy`n8YPlktGbv? z)`OV{c}2npUCa z{es;G^)_OJb(W1h9fgu$0lEwWQ%T<+!j&PYrEMN51$t6Fce5;}3#)2$jqXGR8m>ZQ zS6s%R$0uC(IP*#gP;?~=jgx{R(K|q30X)k3XLZeH5V-4Aa2<9nn^AUlN-NL#6~<}1 z0%mqqph$LQ7SOTAyP0Z0XazRDk5Z#-py#IEbbCb)`JZ0eLsaBvaN=*w(8Sw=cafq|tR)v?Zq$K@1jb{qnhtoRxZ&pl zZ3aE-2nF{^so#f`0qNM3l*K!{dZX(W*LX|2X)uoNC z%wWCr|1uM(`rbwXF}U|)_UM$CJ4Ke;?t9YcOTMQI){>$IaNExdl>>{g_TK^ z*m>6_`)=G|X&aduj)btjH@;o@H7a-NI&RE!u0=F2f4LY_cn<%?F3PU@pqG9+Ekk?e$++3PBYJbg~%{ zQo1aDRDbsVdGO4lm#VD91WkPu*H>Cz_%fI=T0Yc1vR!tc{1R&GB#Va5RG$U?uoI{n zdW#iabF%e{yAC38pDuEsX4o+v;s9fcxA-V;LQ8K~WQYTo8d&U#((=qzd=my5`Sb1% zPpy&;u`FxKpQY03e|{f2&`&~383;ko>ifoJtbZ0jW*TuV!2@<1 zBM0!gdMNB#{Z8@bnA3Kqp4mn(jSa16e*-)`KgHGG!zGvT4I3x*&|+2F{Qha5F+ib2 zRC+Z=H*&8yj*T_4wrKJ1ahboGjVs8xmQyVWh7mDF9kRG78vf|>wl$+4Og z=-ncNyENlrUHYQUwSE^`>9S|GCBuI;YyFLb^djsQh^-`d}} z7@KcKeE6j6L`<2h3ap2YGI7AR+ftEXQ~PC+r^v^}F8HiWB774^uJ#;K&YxOYe-$)3 z8uozuuw|SCQCyN8+NC`5NvvBV7P!#7H4vplL`t{FQoY5c zMWb8j_}r*C*EtJ1mR%Z6%Fy+5`O(UMCNNXfi|}|4O1|tKqDF%*G~k>XD#T`4(oa%L<(DX7iBI zDOo2&!m%?WhWQbGIKq}!b3i?0F*#n&_i9f^9L@ikMZd(qTT}8-fRS1)-)Hzc?^1{a zb?C7KWK>R6)bzfAZv>vNmQn=bM+v=NXW4bq$~%igBPNkMe_XzsY}@Q%{`rW2Sd>}iJSd++fSuNzAJy53-#!o1 z5Ng51VFPU_F)3gtnf7ueD+~*7)CSnDpe4`u7PhZ8BrxX%trQQY=4Jf7=V=C(qskdl zC!QR`k?cC;ov`^kIn5wgmB&j+1x`l`2GLK(tfxwLx}pFY8>7J;Yv!ASuP_bX(F7YP zmNxX&Q#WyA)i76tqj-z5F*b`=6y$12oSKc?18Y%%NZ{EzO|;=ls)7q<-js}Y99_|O ztd9OsjU8!{zQt=ZDD{+JoD=wpYY=dWgr7q5`v1F@{fOf9d)%YjI_uu?Tjc=KE~{Q5 z2P>UY{#pmzci%|Hu1ijL!C1HNYF=QT5P^fV)gMXsY|e3CUL`rpM1smJ~%J6`%4&?ekp&^S*`C3EzDAIx{JgL zW&YdPSjI_^5V+Em8!{Sz_|BkREwW`C92I2Uj?G$fX}7j4!<~Hl5T<{AKj%!szRB%o ziqcUAHi2xq+)vfn7Oxc^`K`%f6WbY{(Oy5_vlS7XMU8A-{PbL_V0%+ke3a2-t=&2u zKI*fHV57tg^sZ7e#wUvdCufnZvc4eU2bW8Wka^}w5GPqV5Eu7Ff|x9&fz`W)zz6uX zecOk&s^ReUi9n)Y60okl+!F4u&aJTR$^7D*LtvvC!%fJ0V+hvBA}hN{1@ z=Ua97E_DTxX*|0`b6jWp-|Xw*PyONbk#h@t0sTl%lLgFJkV-G@JCM&!M~nzBc~M|-k~Lk{d(h?DwC zAYH$F)qiM=u=8I{k2y4fctQrJ5;j>rf<)Lw7Lbk|V>SQ$vS?|ah3qkyd8MX6d?4tj zdX4f>I=+c==lF_OsE3BTa%-=ko@4r2Rtsy9e_LgMNK)g)txu&JR^nzSDho{pO(=W@ z0GuM^B5*6&71bc)wprwx!~oiVje3crUEl&*2B=?XNMA1GtdO zxtYi+$!n~{%)d|8SjdJ86?z~QQ^Pk&CRYG!oz#5n{e%Pt{rQVdxX#ob;vWj|2|GWH zCio6{k{@v+dEo6*VUbXsWh3_3+ejnJHIp&!Uq`VwuT4sWCpFu*PhDd}PXod?WR=^i z8XGNncEC!E(ud15{!)6}ylzcN{^l8Z;OLrIyLi5m0!FasO}3efkk{ScFDY}JNmWP^ zQFd_aGVj%kt6gL}CpPQMq{Y$@K!F`+lFXb%1KXd?c>?(c)DxhR)nZX9zo3wiD;Mg# z@L&k`&ahN#;8C6lbB*Q%e{G7WYAZ`|J09Xq=I9}e8zOZ49IzM@uxgk?gR1(d$orGv z7Nw?_42Kz7=SJsiZkfy0U{n^TDckhP(ts5`os%ws7&#&snu$0fgh z)u*){_y6U#A_}e&7@}3Wh<*}#%!QVM>&PRtCt)UJ%k+qsYzvfn@ArQVU@sh{>~ zIF1dgr^uGZECHhzW1tEBmCfW>Ul?2OudO2b6X1eLUKRkzpyp!r#M$~>J+wd@?5+Uy zdT}Q%sF_yLnT?)y-_~vpcaeb)@X}q&s-pH!o5IQ#2}{j1_y{B8h_#Q9Q%AHBth`aT zI7|u`gl&2+7`x#eU4QU<1ws``zI!e_T@}Ua%B7vO{o+dRIRML4V3%*eLIew(A*$PC zxzVyBjhdoWt>@p=7CK%}pq7YBT&&%cU`jv`yRPEJqg=pmS&d$;y+ZbapEl9JY*~_M z!`|LoQU`RDeFnH7QB#yOJ*lTtGB;I43XC4&{SPnK_`^GvLPyH&?kLAo5ss^tuq zL3K@uas1ZH7v|ySDHQ>|N>anIRfOKb2 zs9a_J*etCgI)e-uSaMVT>d4vO!Cwo=8X%eA41RG;L>|HeNud~B zCtzknCjrXQNGyLEwl4aB*IMg`cJqKWLAh^)9>hn5;JqaR;xsN&meEEB%Jl!J;(II3 zb^G~?>7x9a#%0LHUDcJR>xBYBKIVEn&%k^BRkYEoStKJhoT^=)Y!gh^qI_i34JPsS z3Zl2P{mZeZu0Dg*zk#~o^V+BW=`8%S?MepgtPmKu|y!%zaYI`N%i za<*(%7kfU!xVP()Z*%d##7;6PO)~cur!K;Q)L)yg0K<=UY`3sc9(R!xE*sjR78dBq zy6g-*nQwTM^j1$a1@=an`zL)00;dhyz)=A#6Kd-hRhP!?Rd~s4<-yaNq-lz1Mf{5s zKAPZodIkcEEV1Dqz-5z^jjuHf!aSu%Xt-e3W(uiv1ds!DO?F2BQ?_z95ep+ptP}m< z9DrT_siEm{9_Rwc#uDhO!mj_PDU60J&lRZ(N(cG6781uf7TErYL*$zjG8m+-DE3%_ zv6wi4+(2YE?$};!vsuIT?LGoDM0$#2`!-qJASyFuiGfbM+W}ccX-itlW&;!XckLN8 zDVwje1g1wp;YCMSq#w_!BiT+Va~HH@`{x@Yh3l-^lW`?Eo%5;qMUo5oQ*>?qp2_(0 zz$3Y#|5{ZBAIJhOyrOm z1MaF2&9vL@ts+;T^}mK|W>*}Phe1#EiE({w?6tU)gdc4s5Ja^S8eo8f% zNFB~mQ%5flt2{ZpMm6gHdw2*dsxF^)c;TXB$7yC1dZo80?xaiXE}G!pHEau9{uHV( z$PZTbAT4;=H3k=F#hL3ddrw?N6Qv4vWtwnh?<6F{doM;n!aEo0WkcbCGZ8tO^k4df zo^jPWRj0<1M5O^;Q}w!PaeUK|RDy!)jM1^Hq^vMwl?`uwXvNZJELK4Uhy;ji00yYs zKG;ACQ{&>7eUGtZp(A8S4j_~_gnRbP8w1_i05)&R@awlXH&)$L8ijVQg{`^#AsncoqP?|F|w@a zd|BjmHU5yGwftEaDq9#V%@sO4;Fzs=F2w6X>eCUb;!6cg|w8RAkDDF-&Iffs43 zRLsjQQoI8Aw+;tE{M(a(O>B_Ptl|Tw(kVx9kXRXC!7-)F+3t>rNx*O;?=@)VWcwgM)lsTvi~s0$C<>vxc2>0mpsY#+c;X*Gs1^2((M$1uoaRz9-_ z1P@b#zLUHcSYNMZ02$i8(f8Nx|NV<_YyW?%q&x4^c74I0MH$vc zYr{y#+cagC=X{(@z8Y#(vW8BtTd=mB+yL-9As(u}b9-FStPQ{X)W9TZ%d~<;zX8IC zC1d8nL)plZ5ZAo^RGTzlmU>;6i~Ctd1c*q@S+ci!l2n}^@`9?Lnb7QW_I}Cg+G(@+ zMcUd=FVTcNq>e!qyOVkG`{DDuR%fvRXi&~c^dp$cy1DWJUA5DtZVuT$Qqk-Y5`v-a}j8ka*)Fp*SPwqRt08z&)U}s%!j>7 z+SfV?Ox-vmwR#x1b_0b3=9P{D>cF?;f6wDfiKi-Ad|WsrAPbX5*z4oVY*wjghK8C> zU~nUMS>bFercSoMw6I=yp0Yo-rsRD|>Sc8&RbUH9mH)8=bX3a6$@9BZ+Kyp7$gTnr z>oLKx-Q}Kv544Y*2AUVoM`J{vA&(Sz|KDL_S8M4^wskKP`n-0NmH4G75J>7kRUv`irx8v%77}bTeeW*v zCUz)~SmmcwtEtgOk#&0`SV%1Z87Jb>Jq=idv( zcLW)R>tuAK?N?AW$1^c}lUUGFOg?xURe~9gC;~_)4eDSrV$FLH1LcIqNnZzdI1ls; zh3=Yr0DjM;7T`}2eH;C<6(2~Q*iniUK?2;>>MhW;LsPIOu!&D?0PqFN2p|dd@&V2} zsBf$gztcuhTarI)eSB~GF2~tev8YY4=gXk16|vlpM#VoV2!EMlcLVP9)`3-q{vVgY zr*P&^o3+m31u-V*P|MD$9Wn*N=CixHt8r7`*0n(l=X@&-vBh~ShS~4*&Z+xWPkqq7 z2uDOXkurC{F8k9T0~05_W4IRJG6e^OfX@l@ocT*LWwtxW=gn^uH9uC^aZ9W_8ecWC)9Gx|-wx6l(iSZQO)6 z8}C2(iBdH|s7uULZ@mv-gl6w3d}9S0;YDH}(o; zGVJ<$c2=z)w)q~NDroUa5hv#k3F@9QR+yhdN#3?)1OnZtqjrO=A^vY>u%13dIJ3u0 zvlz34o4+ABLTM7gV97UVcR&jTjo;<2H&Go@?@9xc1$Rj-J8q!(k%#LooKG)rU4e&h ztElE!nZ|#=X5*(q%-PR$2nmt# zkKEj$QCUo$QZ2`7O%ET@cs%2{~3}((>uJ!;m9egRkuP_#h%E zxlG^N$f=z`Q_~G#uTV)d#I%-QNdXP3&H=6i{u=xqO8WzN5e$V%v@8RVxfIzsqA?Em zfzxJ zb?FmTAGjK3ENnH=%_3yXZba|mzfNG8gP!DY!=DpA8x!)W5$gIolsda>6sG`L;)m#R zv394to7}X#(Nd9S2q}re4HdDq)#8vtH3v#b5S7AP+@4Cuhhf7FcJlVic)69gUL8k> z=R!{6`Y89ZNx5sW4JQo=8be$(zrErpNu#diS*4q`p;HQYN{~M8GOnnfCY&Q7Pn=VIBCi4aDw@s!oF&0`rc}OT0}oZ6$L` z%QVJ$I@6dwNMke9d%X~)D#axS{h8B^q}hyzj*eNcPfyou_o%;sYD-fc3t(YxH2u=D z)Pjl!Sx6(GRsiQKLkRQ6LA)1Hm4pG7T_Gmgn3iPDxHa%Gs`|Bvp&$teQO}B+s6xhJ zip3=&{Dgs6W#@#d1jab@Tf3|Zj>)f0mj}5l%zn^cke-?64S8(Xsx?g^=gUG5*Z03a$!}fM_zN^@htOKu{2n|_!uqZuz{38n&r^Myd{>hm9c3WuJ%hAH*f^znZ z_NhjG8{)58P9|eaj0LYjfwr#ESz;t|h&H$=H{0WvqPCRV08eFm(u$Sxs zS@EgISl~eLdgZQ+weC$4!WR^mSSl(C#9KshiBS@@0$HW|al88;++tuz18DmY{eAr*dr5N7 z*T-%a)#S;}C`mX&!;~Z>a)+n(6%;oR&WVF3nKThGG;u^R8=I~Uc=tIcHOWf@ z+>PpuA(TS&+r$X{_ON}}*xgQ=8*ErM6~p9Fk#53nzP1E?G|UO}c`Jf|SK@v4gT1rO zIj5(voq(qCTlSjqEhJ1WLCZ)7a@Of`-JbW0#OkktZf1-pmDKtaEKfJhSMvBKJ6KW%>FGZkY~&xvwPynQ zQ!dS5Xy{A1RaxFTI1GOe*UTns2`YvfPK1pFCHY}TAIOz&9I7&1Ek~+pUit@X-ZkQ| zKq`p70ed^Q3<0%LahOd-oa;H$jVBoRhj8LGPjxp2Rg^{P8PMBtgNxidqw}wldI1YH zc^5I7NeL(H)%xHbeskE1r_1=iC1WLjR;x0u~Bg^;gX= zi)3xJ8;&tew>FE+C{9HsaDy712)lS_=f3+LV?14buaY}Aryrb(w<+5z)}{4c_3Gsl zrHVQqo#vA}7kXC`wBbb#jHV(CBWA$)W`H1*mzuoik4^exPxs(U`9S1jI(07%mwYEy zHxk;_Z$sx6^)dJ!wN)hIWe8uVWM<_YS3Qpb9_5aEBPzp%ZQSLL11EjIx%Zy1mYD2Y z6XZNEm_{wgf*waS)f$4SCf>?7ptR#_X1sc3aJLZP3?QBn=DFRoaK)1$BaED#JVA+) zp)Gty&}v8*3L?UL(a9f?T0G`JWnyNDPm;5MIPYg|**}!W>c}7%rUqeQ_dsI!O61{- zhKTo|szBpAW;PH+_t+uu#O*z3IM&%sUZWMq7MHKmI#LyvYw?&&N(QLU&bpM`DTR)x z&;Wq)$)sBBofP8+r zHT@TOi4INsJJxhk26U)cswu%{%D$g;w!Udh~`(KBgn ze2Ub+-H>M-IPD{K0}jhjzn}LU*$Oe8)5>hEX)qL+frqwt%PqF~z-FM~VW2#9{y%U` zBN~qoaMcNO1;48#N6Q0}<8`5zm&K9}AymBm?@63EqqUQ~(Mg)=v|Ji0;3R#2m<7mH zI`_)zjFaK5oVA&n6QC3su&Jvct{;%sV5Azo86L>>FG_zQzpf^8Dg$EY4?j6A?a8&A z-Op`aq7>W84_3usYHoZ8Zs;^^eF;~EdRD}1?qZC??w%eyJi8aqWFSmWjlr{;3P zUN9brfggkPZj`PWnbKsP8&-GLn4to><>*wQ{oQaCyraUl-#U*hN@F+uhtSez+sS?} zAlm;<V~*I#`^oF_|hL` zkDkBmu&6Q@3pqFv>#gX8d{?~D8|yF7eItvN4I+DIj7~&E#_-alC1wx(Nm$|~ zEb=RFoUAy|2fX?uyl|1@ODj{{d>gY@9s!UR?X-8slVM#XT`=f4Jt-@t?H<3aE(>Yk z2IIK#i>|&(e}L)zn!92nfX3{QDj5grgKUzXEjhz@JMw1cCHT!y(1HT04M|RU)cp*y z1nY#GqJc|bokcRdw#ahq&y$mS6?{T z)nwM}=3fIxo^gBY`aDR(oA?liThT)kv^XjG5}Zm73Wdd6o~wx{Y;BY`KDr}<5cpqF zL6us?9Tp%GX7>U3ZNCb|HX`>2g>tpUl54^tyW@x&T>jYVWKB0h(kZ=~%qM|_LcyR6 zPZ^Adun__pHvJuTN^!2Fi*}>D>-gvhfpsA`67+b5t$SrQ&a6j9oJCE9q^ImxFe~n{ zqOVS2W;kf&27ooGHsL_&#%}Gfny3;h zCpxRCihsJ+VM{Z|d_zafl?j`uE%k}+9x~;UOcVw@+Th9lcd5=perfc5>m5nI17ZaY z_B#&+!8!a{OkKJuAxvmWSMBEE(zG)-$?`geU&thBL>mY95xux&R!Zz`z&Q@)3$T}g zX4Ft0Bxg(ke~uSzX?n#NXYX@y+jppl7p8}IsLW=ImmFzEIZvj`tB_oB1^Igr-oX$a z&pErc5aAx3z!i}4Kc0!t8jm%YabfKSLgOkgWm0>HU#DTTVg)R(q%i$<6ta9G zZ4`bk8$52OdKN383FgCutSz`%vU(@xJ8e|$`=BgzBy9YiEDivq^r|p?tVK;13kk0H z6}+->l9iu9r@JGZ$PU>5rcQYN3m{|cV528@TnJsbsSHHF><*IZ9Of5ty;wK!08c{Z z;o?h>;a9#EdiUv&OyIx*4t4ptRKkphn-Ba|-}zGS5f4(s=_diS2zslc#h?4(Qa=Y1 zCX1zqSP5^N^&wP&g6Y*Jg|=w`!Ec$h)tgg(<9F*)Kjx2x=dhg5Up>UL)la?U;>+Mr zz>sFO)CskkrWnrLuvOgCOT9h0bM72>r^rqyJT0VnwdX>Xd+m2pfLPqPCA@~9KXMj~ zI8t0@VjbD~fN;KCJw_rLrOGUdNbqIh3DeB%VrSi5(*OXt*=nb&k0f_x{ z^@of9JTo>8dTa=NWhc- z77J?+L|Ym2|6vAfbPg<(%D|-A+U@3DXO#=409No<(wbV1MxNu$Wkmb7_#GO850yMuzq^m(tL>hc6A=dgN+hx#GmWliLPO@1b6v zKaLnCRl&~$wH}VP&#Rll=SlKe(=H@>BPYponujK;U2(+pVr*gw@iB|K1y7ndYYAcS z0r}nmWQe6U=R*$=xCE7)WsF|v?#u_Lf!HQXb-aqrk#ze8;IK@)G$!8%w-W+ne6X0R z8_7Z37XnJI6sa0zTWp}l&2Hc@!S|1Uj%AdyT7*>0a!qK~MpL0%?#~|)AjVN+O-r%G z=JB@Ywfw@61^=}1vF6x9Ukn;-iRM}`B@mcT-)Km4AiuHc&8NjtaqXyW1f_DIgGwwU z?s8m2Yc*EZ4z16w<@~mv7gu{hr547f(X4vCO)1edvzOzFQr6%=MFX;5^J@&&`Ix}sdP}BIH}eL%XzX+6A-C!b z^vlG8wtdm^T)z=QRKo**2!VJY9u3sIb}Xo zxra4gM#h`@y+lY^1YB!hg_P}Du_mC`j#@bs$+$sBNc~#_qKFHLXHa)-xEOKBay1^*{HL3F}x)vlLDMDwCC?0`DjxnMY7ch?Onx z@JcOOcyk)X^=SWQ0L~oPsS7UIz{y9w%u`{5h}tmGNXP1zmEPgIkrO_Ytz7&(9lgs@ zarcSS(8uOyuYKY}$E^T1p#UO?*&~#42V&Qw;3CnsX8pj75_+YBsCFw-vtQ}4rpl!l ze4TZ%xsXhn9y1 zSZP;2> z>_>M3L>P4@p|>SCO_E`1{!CCd{9Tb>Ho1&(MEeAWapn(x4!zXTY}O6+#v8AUuVhP$ zzhuNh7OHf zFJ1`fy01sv2OwNqiVZh!onJ4%tC(aFMnihc`QtvXhgqmf*=sE3V`iK)X;Ls(v$n#Z z!ct@V{~{dTHOgF+b!>I^7-K_NC1~+KLVx{!esSHN(BpcvzRGGYBCPNUcKuhE8R>_D25ohvXD6Ul4=ENplg%Tfw9`-Byc&BgO zps4nM)huua`Vnr|ds8x>S^sODIO9st>}&zu<{-MRt{A;HU6^^GF8P)NJ5FC$fsBj( zJ%u49hbmo1QzYBXSKlu3wNP9RWrQQRg2qXJFN3 zXW%s&nbRM3 zTf~c=I5ArG5oCQ-R0RsGhTQPEnaucy#J6e@044X+&gu0W%`g}%93LO&d3uJ;jzLqJ zbEoQ<_1%^3SOTY$sLt!x*P0a}?S0iSYaeRXxdgLwnqST38GYiXFn`TK(=?&G)!OYAmnTDI{1ChINT(_gG)k6ua;C04 zfMs(_!0^=By-YaLa{{2~z2wZwT&@rC9f=IUvRoBuJm(PR;LhD-Ebk=mrV(|ap5SD# zO2|8;iL_R~+!?fC#|*;A42X6|s>Q}qR~muyI5|NcgD47Cj^@J4fiw3Zpc7uwlQ~%U z;rE(N1~W|idZcW4-9FpO0;tqM-(2o5#~~cp>(Q-~3#JO9CAofDQlB4rRN-}> z2u6|fX~nNiIv=%01$^KBCz1Z^#ONiU-Zr7d>#6oXq_CdeUga3|H*9&(R!QUSf);{1 zSYJ#K3LDrO;s3TH7s|JRVgmIXUPDxC^eRIWpbkzOAK#25`7`TT+!2DvLICLFy{W)# z>5F{dDdcW@2>=V0RxMB*K2OF$IMtR9F6vEE4u zc-3P^zsY3?9Cb{=(6tZ^M*yUQ9|BGlBCNc<6Y|P*)GBfbF^bl^dmyOFltI3t36bXc zF3N}J5S0KF$I$iPkVVFMO}14($8Lfr^ZI(l4MJewOm!~C!GipI?VhT(HxRs!Qh5rNvP3OxE5yDsDbUnVr5c+&DjYEijO8AxeeS6TS)vdtMc@%dN*%n7KKRMc}sBh@1yPYcyzaz=skkg@^yE@Yy#LObbC?LM2j6Z7Rc#M1gd)*KI0 z#No1v%Nn^VmVuEb`|c#0hKD|f*YSA}2o&>XDJ&No<*9$hh!@9VkNwpI;R~uTifTlS zf*!7stQ-MMr{eNKeydqc&_$2AUSNW4O6@sxk#C%i{qCYUQ}WSfCPQ4lpSG}Ht0K-6 zhVb}6Gz_+Ft5Z_fP}Jv*iL((z%MtDou=My6+JqDWEo!dd_=@Qx2>t#8gL%TLmE9by022O9=Er1ibgdz=>{ z=kja8;~e_n|H}PCVrd2nYUSGSLyeI4$Fe)J!dhw7rjU!47Pe3|80ZR3zG^D$yqH$; zu3mT4me?9eFLV)G^o_H_eVnS?K~r>C6kmxJi#5ei2IA^nKiiCK)yJ*P6`;dDPZ*q9r^@&#A1~pjHI}TF>ba9n%BPAab|#1>OD?!@5vR}g?VM6m6dFd z9-X>5ieb>%B2wM7%|;yW9p;<{ZQ%ja1Cv*=SEzLUTM|ctFcg(OB##uy+0#HDwmg7T zTD{@~j>Gf^hx>8VX@4rbzo3(g8dZGL%&)viiZcB|v#nD^=y&XvMo0N60v>0p$0wTC zGf4__ri5XE=)tP%KxNumKH0kYxQzRYWUY-0GK`M-@qNZs-~n&3k|w3vp{R_QZ#fY8kw^vVoO3R)HPf-^>dq*Jp+FCY#Dj<_MJXKs&UQ`qHh9D z7FV%$pK>!1f#jt*=e~NN&{D^Fxb2;?$BeA#A)c^gSg-BK6J-}l%{n||em&WVOKrO; z+ov#^hxtE4{q#kMr0gMzKGZ)V%GyFDK>}`EZix3~=5MFzqbNIF(gyi4{!P?TnTc}0 z>qWF1!HSNcrXfOPftM7>to#7I^)8Rj_v`?m#2xDJ>2vquhkUte9=&wYxP-{71X+k{ z!ewD@ha8qSe$N)uV#SQju{wFGqLPuCTh5yUK?vcYopH+hQ_`PiRB(y*1;#+IwsA4-qt4>jln&sK@K zRwCEYF*sB;Zj%g;BERO_vc<|Y{?J6lV2O-T zdT-yJ48Id8!YtgLx;lU6wE&9+Rc8Raxmx3VC{7BhmShM}ytLmhrR15>@z|;2mF&N_ zxq%8OC1=mAf^o%<3+TW+(cVse<%G$_kkMBS@@qO!o6)8qBzDnSr(q64!T(e~Qz|0i z+6WaX_FTII(O**N-rC>{9}u8Gx4WuOPujw-)aWX&V&pQ{*@Cw9gD`)Z{BsDDglA?_ zqIQJFR8ii*$4x8e<1U9)OIwZY2QC+7!!F`o)u2(KNngFB59C@FT=7iFB)3BH!^STi z&I4jQ+@+c`alTkasbCyGMs#Xr(_;f-dvo59Xs@N6EjHyhU`hP?XDc?wXyP`x1|m_m zQYoR+db+7#q;6vAL2-;pZ!pgmQZ?${ll@d_uMf`L-T44*{|Xm=P8D~n3B{JItQShT zB-_KBHvbuvLG$G&DM6A-1A2}Gl|?xJ7ZcF6&F9*SwCY(B$oY4Ixdnn_KwrpRjXI>i z2q!5&iLrJEBkV{_a%{f3F1W0|e_9dy)sVLDlI1}##PFE``o%aDJfFkVz1tcg!UyzJ z?%fOGE($ZrX;6^GkjwcDh~J<-_gV@V6FSU>v@BV=;j<9a4KdU zA&6}E%S~HAQ)YF#E=kx<0(Q$kePQNwhZHC7nZcv+Nx%KrTG_scC?jbl5m0~J2ArtO zf4mGci+V;ws!ItCEbBGMOZ9*S?=CfW0B)X!7^sUFYQLu9?nQ#KELNUxAem%dm{9g2 zy%X~R`(7mP53h6T{PV5>4>_&!r zH@O~EMM<%{a+Y5oJ+HMWSLg}{ghvsH_?2f9028+>*j@>hqh-5|UzOPE}!p*z}X7xI{n{=9}racy1kANq)H;UNlx? z2{}sDM|^Uu%{_D!Cdp>Ll(=cmMeO1!169VeIM}bxJN*hkAWWA#)|Pu%puwg9dF3Nuoiuhl4EUE~$Zm*0o!U8*)jjsR z0GFW~_lQf1%8e%0j*Jxnw`$PN9^gqJTJHNDK(>ZUjATm&XpMeGmJt2ijyE|Kt}O9h zIJ5$GoGVb`t21py-QF2QCxBbcqZ5M#A=%m#jrH%n0mak-=QaD9FGzdl>y&}%2d4d? z&HbBKf1dwL`dqP0Jr$UN%71ykl0NSrMsU)a>L(+ZXO#Fl@op(!7ai4<_#u=m;fbYS z-e7h#XRl-9WA#+=2$x|vJnXYliwxRtK=++&U zwF&<}H83Y*Yw)ZFPxsBQ#~*Ah&X(T$quJ}W-Oy8+5taUt;%3>tlRV(wP*DWj|6mV6 z+U0ouK}ooRI8YrUUgPUiy(p*qW@ZlFSAbfgYlZE=;a+A z{cj+)$bV?W!^u2+tK2BLw$WZ*rP>cE6XTwv_Ev870sAoC1A0sfLTXm`PK`@wqO-s? z1*QPH`>O3W=j5!4jU}+&pizhtxi|z{qBMXB$$=p&MHO!Qb_yg$ffHLA6E1tZsQ86m zBuM@RxR-?jw?RaekCw`Cc0JVM#Udhr^T{Swpz0nqnbWpGdGcyB6>~jq(68~bA4Yp` z37QF`x`swqt_*M`F-jSjh2OQJ34v9+3DPi?b9)Hvu_J(yw{hVd3r`~k*J+87R-2^Z z#~~#4Tj?8mTvjj$YsJ@syR+W(4h&A@o@?IbpGTge!iPKx0B{)vY`%xm=b}+F`Wbn} zQ3_9xO-NLfGJBE|jQ=}z4TH@TO}#nVA_+=ov(`hD8RpNOX8ASC1~J@!+f3gfKKtBX++j00lBc zDsUgY9g}as0u|FJGGwRKd-eVXFxK_ensc#^Y8;{IBp9V zc!fTE2d5^Uu7X>>c^7Q-tkQ4)N`_E+*aXw<9zt_`?O{oF zy?{nwIyWhj0}8iWD%v0>I-pD!=8@?`5V-Nz2Pk=d1}Fv zPAxLlaAoor$_hAO$<4jvo02_OFB+03esGlp1{^S?U2(;BN5xz7+YD$pL5d>9Le|q| zh7E{~#K!V%iX@4mxlY~iaI>5IA`cK+Q+j6wlI$a1k^#~UcJ+RvpI0&G?;R@>7n#Hzr|R_i|4jv^+YJcvTq*I`7Tb|4^~czEXRf4DOJ zav|k7V!NKDIX4we{&ypp)jx)R#u)KEkeqb7_cUHAX5fpmG>}O8Gg{VEd4sxVsv*Jw zz0x#F2INlB=JWeSvaADDJ52WQu7Fo%YI2_DV}_gpEx;1+Xi#qW{+iwpJk-ovUr&wS z=@wVojPd(IZ_kyBJ)_OI@&%6NCbYugiWm_YmNeeZ?x0|K!yn-AxI3@ITwsbQq+}$zr=~i+?^gSJ75TH=6lR;AYh2!!CviV4 z!Mm2iFdXzYroQ`Knm~hs0+3ok-rOoWsRv(`<|=%e_&dMaO2<$t;uw|gv{<3tMgDtD zt)>=Hs19^HNLfb2WB)ylMXJ;bP2_CwxLGjUlA{DU~_sX z)&byAM-LF>a{fTM9h*iVqg5$2Jfjz365%rnch3+L(%PF_i00PK=OYw2F(a3r^M~>%}e7XAcV^f11MJ)I4GuQ7>^mn~cSsxfLYJ z+Tl}xD0iRQpH!B^uMoIIe&-uhO?L&mK`Ff{U3bgvFW@b_BZki}2t2zkz$83rqah1` zLW?My#^+FV);GS;(dl)xHTDb6@M#*Uh$8%EaDBW*o9I9ElQH%tEz2FJ?(tlBwKZ_ape&)GR9^VNfyViQs2fMX6C=l7xVaYf^mbhjlMLIlf zHZU-jn92COQlP!e+r>(CT>6jor|T&U_h=5x6J>>`rHSj}zZrYZP0^m;;59;yodocn zd92aX>Bga`=aNJfaG7k6!?$oO0$zTlh^ngf=Zit9MNoFhFUOVAdf+cUca9jv*(Z0F zp1L4*eudr;0q+{_n_!xieR8S)TviKrHgAGywb>AkL^XFgQ;V8bL^i{0VbV=138GKd3OsQK%?uoa@_!+uIYJb za2vp>acM@Js#Ap&cqr_>Md~2{qhfqREoYQo>sIf&*YCanmYCP3{icR32=I7cf?Awx zuAUIW=z8zSKOjrzfd~HCQ@_8p&pf7V4`HNsyk>c*r-9Jfx6yGw-dt=dVJG^oB)tm* zG6q>?=L3UTN&O6+4T9N=CFlDh?zJufImXq@X=?ik-HUo!yUd5<_V*&Uc71*Qva8u@ z=6**gLHq?rBhtXT`x$bQ`lZ!(_g0|PAo(9Mex?;0i3VlfbOR1$H0SChy~if?1!shU z=8|@~OErSl1~wGCFeJw7Xm*|gKBUReqt?c1o|)tD#G(ybEu4(PuMmK2XMxeFfzTxy zOA{|WZx<@|$aX4X8ipd{d$d6I)0xQu5qeTxGaJ9JdEN?oGP0x#i1i)`kLZA_p%#3{ z&_;k7PZQ;`QDATj-Jw`GEuus?KW}82)pkm`GpmnE_{_}AgLG>5-z{~&^gsyr7WkjV zkFL(Cac&elB%wpM04xI?hb@lGP#75@tu67~Ar!U07kz9C?S+P>@|EjM>5+nbM+X;< zx4aMnT#Yy6f~s#mC9i_a*aS`f8^T*X7e~r;C;BdX9d-lvXY1IBbg_TOA+4r~#4~B= zYT>jv4ue|<2>UH+@eS!)pO1r=BEqc|AFIVPENX?5wlwgl%a#X4zYTuLDPc~V$~E(# zSK%o&qGIrH%KzL?IlfM=Kdm?c`ZlHw`aV7u2DXM+8$@WjY*tsv*Ecm)?XeK7rJ7Hq zX=m*GNuZ=DFGP|_U-*Y^%>R_%+%)Gy<4OZl4@P*1ahkZ=wRZX|Nf@q55-@8H(wp_uke$1JQp6*{q849rEv*;VBgwRE z&*+YTNxh`g-v2nrBc0ExB5s{^=qCDqnY!rY%1DtcY-g?!pha_G~1_xy;lp2G)+jG=X zd?K}D0evnM*C!(rL-u0pD!fj3WgF?N=5zuOQhCn{4Dm~2VSY(u&8^8%sg2tYsBR4f z@JNZ9#O=z`4DnvSrycqHrGfc>3nQ&LVqi2AWC>gBKI5*~5d@-wCX~fS3JNBHIVrkB z?;Gm&7yme=!Gm~A-0QC%;k3k53)#%URF@F`&<5ohwmtF{%wt3JFLy)1#-y9QMe6sjsZj3J zKgxH-ipsKIm9`(oA7f#gd`W3HKFeEoS3+Y(FW2?yi`9OokY@_QMO;Rvz%=PkDYQj7 zn5+gueUA_wbK3!%tF{?3Ua;NwJY#hOLL0!9Fr9~{-Tm{T5ohdOxHvtg1;NQ2#KN( z7xA)rc?(56dZsc%gHQIFZcRhjD)qTdimQR27KcB}m#Tv+KUjt#_rclUWM<~U zI^hYQ<%4|BqF|(Bb!~pwiu9AF$AeM=B7&`hKVzfLwVEUq=hosf-5Z<@H4t@HJy6A7 z4PsIpAqJ574^BIW?ffkh{b^)BRa=~YYLz8ikH(Z+I{+&)bAr&6l63|MCsKk$+l z+d@^kDG9#ykmyh=6fL^}gav8g*Pzp;S{4iC&hg)4$d+ggaN{gG=KngBSC4_?^NC#F zk4i_`fJ-~T?2{M@!YmbySoj#f);L_A($2-A^FIi7(8)#0-&9YEMXhP)rlvI@)Gnmk zcC+!$6M&=mNt@)!Yo`YrW>M-ZyaoVrb#r-i1(Ej&=TDL+dVil(adjQVr7}(>+CunA z&640kv!k;Ujg{Bw3t)jH6XQYdbHk-F65Q#Kb-lgw5iADeG+w-CthlYj#p))S|Voo-yv0uxxn?|TMy_|52ye)J~9yp6|hcANcfRqPKV znc7Sz$XBJ#p0*_doU8^I(0Tbx;-6+_H|ddnQ4ZHvgc+;mfFg_RNTykc#nf{G!nqUD zABR4)HcP?~K=0rLW9yODoy_XI1FD2# z6%65D_Wm(}TiDO?xb{BvZ95@o#iq?P1f_s^f-I3o7LA<9&X8w|``If&;dMu!TTcM3Rk@0SxwxnFDJklXV?2+6*nG4?`Mj0-@SU~`Exu_gYs9QvSBt3u0eAZ&8 z$f9lNX9%_trNYk3_6sLVW zxZZ5=kQj<2Jj3&bi8I7{z;%M@zEJJ6Vj+>$Dah!wWGQ19MW@@CdTKHc^>8j2g{9p- zS4G^H{ZdL>*vTW%L6^g{(VrmSM{MDH>*AdX5>AsnvNI4a9>jODL9;;7x`P?h^EZ;# zqj`(bmXRg^k(ViG&9ACDRAa~NZZ>=#)s#mv#DQ zV1c71o>+tI;F|{bk^{-C!kr`w^-igij)5T$a8O}XJYf_hG`@uRr9&|)k}KGn+Ifiu z*5$bgrRF^Khy*s92Aw1(v$^~HZ7S&uO;UdXrpTq=*+67LGG~gg^N`NWBK2wtOYz>U5QH%3fTJ$qEWWN0jup4(CdC~i) zpDR8J4WCRveOTX+K49u{9M)V6E0hVP5Ys^MGzXOWZc7^U zwH*HR5qSidW4AN*Z8!uDnK18T#ruCzs0{1c%5-1hA%J+oTw9&l%{np3Gef|fwJ8Sp zfJ5HT+8m^C6ppT6`@{7V!zkP{vZ;{)+b#duQ9^3n8Jw)zW5)IVn!%|d6!6ZE4(Yk2 zEZw|qs_C{Dj*Y#nKtl1rZe|R^gPzMK&&RnV9w%YI!Ex?J5TokklS5F^dVPl$u>wvd z`#Sp4mQJIca3prce+M;JU75i>C|fqvB7l*FFbALjK`FzJSkO~FT8?KY!RYVDSuw6g z;3{;`=g5`_l%pXt?9sey)}2IqidlU>_>R8deea4zg`8}(Ou9{zp?rOQAgG}5i&OK& zS|_10T@@zhCOQEZB62|8@(DNF)it!^K3t1FYK$3xOG|y$g;3G-7z#gEFV^vd*6sDK z25TF!;6;;DMZdJQGGzU$Yrl0Ao!tbCwR;(2=Zy@j!4xmNc6?Cm)W+(PtU^b5!U^$SiL^w7Rw-w# z+)V&A!*O;F)oUilEKNA7fuEitvSi0`MWx)wk0f?fg>@5nqK0X^fBE+neZ9a=F@8RygPC{bt@hQ@Zs zhG>LNlxhA+Tz){b36v{0B4K8)WiCLZEzdssL)9+bBJ9|@>JndBAqvrET#i&2v3YN;eMaJ%1se>&Is}Egrlq(_bUeC5_tnSST7ix4AXcw(9p@-4>A% zzQoq-|JDNya4g%~7hJaiGWLDut8ciiWfM&p+Chub2I;#wRWv|J03n^b;p8=-6eN&m zK42Nu`+G7<+ob8wQ}=J`CvDv*wzQ+Kd3FEpMFcge396W^Udc$+5^Bv)A|T!`pujbH zvLz}7A8O~_9L!|9je&ytDMErQ1dn}ZOHG3aVzcuiJa0r3&5dfE0bbU5H^2yl0I?b`%PTbW&i_N1vG_B-|wsqGa7Rxt7PQc)j`R;Y=F*d+s0Ny-G4=XhEjK>y3fIKDQ5bx6C?G7?ec7~ZXhcin9xHZ zz_}#dX}GthJ-AaiegCdydLYb%7WwB&$`x||rsx#lL&D{(PYUUjPC{Fp$rjsyi(0Q}h@3ypJYA5L`apZBjb}L&-y#zbaArzk`T3Jy#fj;P5I08+ zI=s#Xi*m5_1kc;3$$vmX!+WcC5r4p6GX8imAs1n>`w?KuA4{~``PH@y4b%j+&hBzg;e(J_fbWgNBd?V%zR~GZA&@vZ3tAX zgd8x`A(PM4u_4MIx6k6VY_U85R(NY6nb#Y>Y_ox6dz7~JY-HDYdmlC+76@3U2Uz_D z2W;Yxq{-piU*~VxTyL7{&XRf*LOAl}p+D9dnfnm!=h_O1WU#S>J7mUrq=gF3XPK%60hYftPF_8MntQhZK>daF2=)3Mt(J_?Or`7Kq|5taZ)wf6CMVMCv0&Y=>eD-Vtk#$+{PGE+9bpx&#Np=aI>Lf6vd~0@Kc~E zc>_pP+o|@SSs&!V;SY2>8&6eFuSer6IdB~SYgCl;eiIJB_i&6pN_sfr4MRr?=JocK zntjVSc&Fpu`FA?EY-3~cTl>Nu()~8C$J7J97xKpGb=G$SNheJD&ol_hVo?yFZ4uu} z=!6jTtGL3sF(a2$J`?&oZL;vWs5+*c%_2s^iAy}hscbnxL8MMon4ZR)PrAvE}}BD8)+s zoa)J6!r;nB^E`*FfxsBLl(tp;7oNndl7w~$o=T#vLd_Eg~6`A=I z0z$1&tO7H1hLBs3xnySiv>%q#YmA+R>P#hHkh{uSXSl?sj}RBS$Es)Xu9H25l1pTd zxMgO+r9Flv3(l&fG~UMb zdH>9kcf4=TDy2aVou0;A#24mi*59$owwn^cqgqYButTy20Ixbvuz4JDN7O+7o+q(?(^nMP>VtR4d*>!&kFf5m{ySue*V%7{UPjFDzb7>xT>fOe%Mo?t|igB_KC~ z%jJ%L3*jtgi^$w{F<5A~c#tr?EWaA?Lwv2iaqX4*)jENtpP-5$@I>d}o!$L(C9R}8 zIa)|I7pmX3jm-2qblEZ(5$hbrFvkM-mr1o}HMb;PMucnbB5H!UiCjy7TBQOV74^=O zV}U{4O=EYWLsP%Z*Xjz$Zn6n@Z22NEhD^g3V)?v0>vy)su4kLOv3>jQO@8Emm!=B= z{5|cvGklka?zPRErl0)5@VCGc3MIdY@b!*ZYgYaAa4sARUOk`x=jQZ_>OTm({ti_P zboZvjCEJd?>WA0qQzO)4 z4<+xIsA^(zn#Kp6=%E=oz6pc4%a)%@F&v-;We}s| z!RGKMoL(B8i$VMg6Z~>|X9;ElIps}P@u;;Tu^qG0?75$Bv%TEIV!c95tQpGd@HKFj z(Tm>G1h1p19}T>S=n8N25LexUs~Q41N7`#uEVyzD#m*J(3QAmN-^aQRC8qBxHR_wt zBd2KWkPn{GeCbsyX+8RvGx@K`yt^(+ZTZY61SNM!Iv;cn3uD%DG-_1BuG=Qap~6pG z0TxCIL?ZT&U(Tpa335;Iu~me=_)`GBGC>hO2jyQDzEN_w1b*e&ja^ zI{=8lJt?0thjVe`dpaAEW{?TLI~pov4X$k*NjamongTBxp*6v&4|VVEe9%)El;eh>e`NtfpdTz!l=X&aJ@%0BNr@5Fgnjhs_MY| z@|!C=kO@KY)1Ce=6ye-AqZJECNfFTrl~&vfS^?g z(gwSOe-}7Bx@|P@qfdWRU0Ab4*tmkHI-<_uZ6dJ19;0fC)S_tWmak`{9*Rn1TfJ=5 zD0Ua_BR9{DzXGlC76tRpeRZkNkO8ie|6F6Hh{%!9pjs4sq%pM`6u+=UOV-^x>F3YW z)?*bjevuywO;BktMRV{@&{N94Dd`lln8PoI@-g0o+wYe>GIc3lM&-#Gqq_gxa7wS4GT;fF!4({^ZAdYkS)IE z*;@E4y@fs+Wx!L$_>lRa$UT-4lagI$kjr-aQXChsD>Y+9?nDGKr$&7WR&%TAYY!uv zq0WQ4tGT+mi?+gW7ZLt_CjArZP2i5?!XmZ`fQFZ@032ISXEO)Sr4R^n+%M=@_T0cG zxgF%FshqDX8a}dXs-4){-mMlwMjn0j)goVWSfLT(LsimkQ62INu{G40_;aZG&(mmJ zh#0V)^9`SKAWy@Q0uc@f=RB2I^atMBVqHBUfR-e#3H(Ouw{wA7g*oHqe@y#ae4pFhd$nrVsT$@w0}sANvGg*63PwR*?U)ccf(4aE|7 zxIaa`PU}iesrXcfg^*eSo7ec1W$0P?;@5e6h9yO&TMTQFY9X#?Ai0j8We%dqK@B`c zuDJb2s5p~?eun~$&5K7dupmkxj@4QTle8G2pdNi|a)X%ZOKPNy40U<`xat{RPNo#x zi~+6*5X7E2RuOmEBUv_~)CDOpGpZ;*J8|4g3f#p?YXsbEB@8>kdnwL9rZB%3I6MWN zZT$XTzs6r1&wG`U$x$JAhY#!2kuBT2dH=BYNweRM{%+uS?s#->J{+?d8ADzIROCL? zh8-Cc+IU`T6X5H#z>X9jkL-~4-)@__(eCr+^dlk9V`(kl&Q{eY%s$!=Vh9>SkOUa^ zo4ZkDLQR1tUgb?opiL&?3D?p(t2hpjyd?XKDC6wz@gc(@5h;?(;Bxpsg_ z`V4I5Y+2)iS$=3cV%TSCS&!s^W5VJ}muTO0p@W8&b%QtUYQ~Z#NjyA#Khs;OY6`8K ztQcb}5Ts2f7?m`Efdn)O5*MA!mM(Keb7)q#+*K!yO|9(!z>ilV$B+P-+-QMB?_gXU zxcp^{WK*(PSyGY9J>Oi+Mj_54AC#j68sn&hJ))sVH+X#zJM(PIMedoTu7RH%jw`+C zV&zkABJ;NvIc%-SDb`W^o!evdD#NC&3^G(t5dI2t|J@bXpp)xhH0CXOn+#nI4**_a zh{$2TFgG+%&LAj4>D%d?YLjwU$hluTnYL%aDjc@z58vAsCX4)T6BIcf7g?XcV#Fei z!vFa{%3USEsZ27gLnLf#0YY?h+7kMRlkrq=M=9-vg@7^J?J#ZCUN z^~d>CtvUIw1$aGwf>|I(HF*N$qi^{Xt3mr8vpKZI5F+cAJKWyekrZ9 zGu+_ZxjcihHA2H!w;L;(L_zS)^(g;?Pc=0q@O4uaeaWyBJH(^RIyb=g{KzHxJ}r+~ zMTB56^TO}*(f6_&I6Q-eY|%X`iiK|^&PJ=LWmA8f&z?T_0}K1YCR4*AdgSq-VD$}E zQmf!j{k6R+*Z6TL!34mI@qZ{@Fhx(u7dpF{!>lJmVQnqrR9!O8A*NLLEr4Qg7D69{ za>J`WYiDPOTho&-(KJF@lk~dv6c_W*GG~LE7FR}i3oyH5vdn=KeNEtDFI1bJvg)+U z{99uz+pi^bD2m?gXh?Bfl8txX+cRJ}4Z23~RNRI40L71BMYpXtf+!eu*~24R61&XY z5#NiSy@oIl3&8x-Nt8ID8v)Do@Rsn3#N6&QlY#AWd0^lPrh*B+8n(ECeIPQrADS@P z?Oe^cBVM`SfdNb_T}sbm;@t-EKC=EjF**DBZu|f{2f$#;9A|bxu{> zr6LT(U!~XEx6RyU1?BtsD4JIt5{B8qJ>T&Hb3E=uBm7EIwn*`}&;=kPl-zr0RzmsU z3lFwZcW>H($04aW$Nq6=OGRO)F`;gqTs47Z3q%1>sVCX-&ADeii_rEb)cjG;3g#*u zeZgZ^(wLjA`5{+hyGPMw$QPwHrKrICOVw$$Iw>w&Djt02bDh*}crO2QV6$S)&!-`U zjzn|kK|oOZT1uW+)}(Aq?OQeSPgaD+Y3lV}6TDCvYoGFOqLIWB+gtb8)OnqLR88-})RH%Ho^-w86q!OEyjqD=hpt1mmK%gsw=rqt|Mi zP78h>lt%ZRI7w`Je;PUaIxVzqc}`pGyu+MyxQz-V{PU=1-{{^uiQevabce@|6y$;$ z_|>D@MNjgeNR--68gQl(efHxQfF6mCGvCZ1G|z@(IHP!#fNtn@#emm$?PS1y#L<_~ zr(BYztQ7xke2no^^9aIT3V@NjHVRu-+wyLFpmtGuBpZCSxwOp@NBoq{y)}=@oLrEE zvvJOzG9@;W59|NgcR#WKD0csw%4)?Qb$I_wXIK4G(UJY# zWuNaisM3pf3&HGHa`~AaNAG=(!Hm8_pe_`*Qs0-9$61~H6ZNaxs6R3rZ=Qq^7_0Ri z`cC%r0By*hs;JoQxI_*1U%Q)D^24Y=(>QT2$3RFLH1@2?{c7Xl&5wq+dP# z$b!))HPyZ=~hvVvn)c8hQ%_GZUTh0mj^M$uHExT+qUY=8kvi zD{P1K*r^@e-&dH_wA{NT+RC_5LTg6CMyBt2WjMu&L$_MoosD}8{;M^%88Jh!zQK9Qm&#S*imQm4RwLYr@-g(h4E>m{khZJ{27Pg6d1{26y8h7wds20Fu;{e(YuIxI&qTA>4eAKD!CLzYf+*cj*N5d?|Ar^vW+l4#GGvwPD{r z?DjHem-7dfw~I$@*Vv0HZ5!Wj(uWi4;l>3tXITp!NY19A=5M~2twy%ON@6uLhJNq^ zQy>=%gqdZZkAs}oESan0sxTq{vf;EwQIPvag-V!F5h~@xMb@gZ&9a*DACk020)Tpb=TQPAB!_vJ|9kuBX!q{G+E zUmxLZ1G!wh(1S18FFqOeoU@L6Y(HREfsTpHQ7)sF<;IMn)3Sd&Wi_2xo8}3W*K!!T z>CYR#8c4}fKyW$zULs;Apvr(^eRkY+74;#AzncW&w6n+v$FzULwU=`h!MMA{;oEn= zmO%+O<)p7tXlfvdN&RtKPIKm9R#C?nPZke@*xgcu2E4r7^GEbI@NvdZ(=K~DcViqJ zK>eFWkFu);Fjxh0(C|wfQ@3C+C`CkvlP`Bqja$YQw7AJ2rn9T1Rb#8cYGNaohOhB z37p!wsPJUBD=Zc-Ai@)qutm;YDjfnHo*T~TMP|*!Q2_8OR509_j7nhOjLKv)gdx7j zZ_{ffuoO3Z2+%}16|ZJ zY~r`$BgQiEyWsW=qsTy8WWIh6a(9PC)4#O6tfCM+P1nLW4#BXKtF89@wP<0H$TDBv zq4s8g+;Rt%eBrpOd?^XiU2zi|%W74Ga4#nCBs&!4H%R6E#wg7Wn`;_hDp&gLs25&f z$JNhUYm;#i-$A)8Y56!DYHR&m4hcNu6hEoVjyxjZrax4#iCdo6`%v^TrWr7izqWFU zqYA-D3f!;77YROkutG+c2u{tkcngrr zJNGz5LIfk&FVD~|v*Lp7PJew!F0lM^w-# zX9jv3Xi8*(KF1EU<-rimc6V6QOua}-D1DYBR2^BjWBR|xR6qWqwptvH+G&Dzu$sE{ z&VtO8!WBEfNy&F-sXY@}(<%N8Q;lc>MN!q;HQxfTv{k?P5}J7SDSCgY@>IH%OTs;y z%6maz6Y*C>be^R9J=u-?`je|V@3D$3}-rl^7z}hZ!dX4V~oeF z{`QkV_-LtK7UuCEZLVf|Ahv9Imq3%X;>;i&&wo39=A0svatIh&xmK>UB(lgA@GX?I z!8Z*<`Nbqt1c9rHNV@_qq7UZI@dM5P2(OdY{pcYiWX&%)6A|2_YxfdejlGXT=NrG% zT;))dp45guRYFX?&hhNE+kY9W;_O0yASo>P8ChW`pG{?mN4^lnVCLufUpS2b0tZDQk7S6`P*Ho202SFt8rfVf=DIjP7igq?>0b#eQwglYO_3Z*Z?2I`5Ko$lh#kF{dY;*1`4K2 zT`CzpDX-fQP$RXTq1H9um!AX9%#g=rDvO4wG>;4`JDoTSC+g-UnefByPV9 z(g&X5@jNhC7WHno$C`|vAL=+27Mu+Ywq$6*xbVQ7oz)c%=zv0AfoO54LGag_{eqzj zh0nDrB+n?s>f1o~9dsHL=CO&JH>#n3k;DgkZv?9{Ii^eVpeSq8UC|04MTG-fT*^l2 zbfYB|SZ&0WH)3Y~k#87gTPo}`bFTJQKp7}MgzY5Odi8J$vhr}Y*j;#5^JV$FFSyXq zGcMuO%_r^BXjXB8KwTL<74**@ESEV`XU+uZ`6t`Q4zL>?k4P2Ccy3N-z@$qd=|ySf zSK6zsn+imRjt_?pn~4&?Bk|_@rZaO%R%l^r8WJ;qQ|*o*r`nyZ7&_GJj9 zIoftzC2cw7X=fb^QNisFfM>7p+ zkx5sBl%YGhRdL>;YVfmjMOIY-_kGNFzSG9YdAk^vUP_*7Zd^A+J7r40xcflpMH)5d_wIV+u2hKJUJUK9^W_f`O-Jo$^~u+oUG3-z~T1%tIugdSQa$Oijl zo5@0TBj#C;WQc+uk+&Ov3xtR++)NR~+Y;PdelALg z9-DBEyA+_I4ghqOW(uJ8$jMPkb>OCXsQJk_CYsjLep+jwm3A)c*#4~i;mKfS&0TC9 z(Z~QwSXb%3sWYVpX{Zk&Cw7!UWUc-DoGB(tdQQ(e)OIf3Wex*&Ovc#|wsgtE608b$ z5GooohmS$&t1aZO?p5wNJh;3kwJz6Q*bOyYoaWp9>B$>EB3FhNW%)MCfrh#oU;*B- zS9~}RqnQ!yI|G$;TyokG43o+OplVcgC=ViGoGV^~%3=Lg=WArGhzkTQne- z_gxkE=nE_14AGXuu4p4hluQptl#y4md73kKJ1?W<#|Q2v1BnH|+?gRU zRIn>}p5@D7;$+Pm0t}8@HMqPE#w4U9(3G4l@V6Yw8~?wjGoR(m6X5!feZM+%UIuo~ zRqva*H#CR&4`Pm(!63nGDvlao00O`GW*+bbCJ1yAu0*-bAi;!1g2Kl`sfh)!p~!Bz z0HGD#x4US+D`EwJTfXV5FJ%OCqHP$dgHt3J6m))&jZ*)YB=U$7kk)d6V4K2G8mpjAT4WROwL7FZpQczqvwf89U;?i zxfew%wM(<>1A2|1ONd|q+;E*i0bz#lqBTs4a0$N!s3?;?7cjqk7Ho(4RUuNe6qs}m zr@Pg*&RimnVvuJTVT~D1|9dzX!tSE_Zpl*DmXdri`C&=go#}gMd!6^og+LIl2Zuox zxxk3^@utrT)2a|C>j$dS?5&tecN!&ssW~f{8`PeC6mi#>BpWSG{yAmi?j?i;KEN;F zr%pQ))*%H&vmsEfO0dS-0S)n<&shx2?w z`M`qdHB4x?dM*XhS{#jHYtr(%Bo}D`XcKMEx%kE;-GK#o2@hoiy=r7x!p#YE6%<{y zi6|=OA#Qrj6z2tV-oTHU#*r1Nf1K9L)ry&31$lyaX=kMOQ0}ExbyBe_uhXBQPE5Y^wSSw?*6^xRs=C_0>?j2x7JqVK3=HU0v-wLk} zX7QUQ80|F22f}vZ^~bYvN+cc>ZE_KyIzh=0<48TTSTF$4ncf-TU?xa+hHNdec-R!R zijEvt3TAAX)poKt2SM_@4=GwAduyiLx=06Ad>H9tDIBx5-Rss%-Wy2KRp~Z^F3$ba3F8 z%5Kl>n$`Ij1R2b`nY0l$Fg}_oX$SF5;)(+5n-ek@cVOLRV=)IzU19Fgr48xlAO*OryPlD6Oyz?b8s%)n zG)EO6<<;(vNJGuiaiwpevkvX{2EVR$c2=@qrh`va7MTtvWilaGiYMX*`{h%=F5y=7 z?P49mM;&Dre_lF^#B~mEl8;Dyw9;!4b$>l@EZ+wl3LZfxOdNcUBldZV8ZYy}I95{f zlIzs?lk-Bd1W46Fm%}sRL0&zQS!%I%(Bnd1*w%_i4!!Rys#DdD;CJ<7wchn`yRqKe z2xf!NEpk@0yD0Nyl_OP3fk=e%jJAE3!L3qjcf^})@ z9dThm`R4Yz)Z2WS$8En@yh}4ezL*VF)l?f-QO2@+G0O5f!z-@tCM0q#FQ|`_u3a&u zRld2`Za34{T_|3tdC7TDa1N?NSsp-!rqnd4>f|D%^Qj7iEfrVoaVxXxA`_ZSMq#Gf zecn$;a6X|8=9Bj0Q9B`_5TOvq)AwVCrZ)|)x8nC(ZjSaYYBvMgT;F&BL6?6eR6QL; z_KgF@&lN-$)JQ-Wa+@x%dmNSJG~{*7N|Z|~;y;KSADN0rO=M~OJ)9h2g=S+XvwOjC zdvalcLkp^f3*ePVk+Cuj7IVWI z8f&NGNYILqyo$F_9=i@pk2u5777ov}0+A_5`EVe&W@eCquEr}3e+j@3 z&jn(5 zF!kghBGWU6*CLum8HWo4WFVJD#BYiWKP9$ZT=ZiAM$w=3la--_L2SFtgcha7g^Z&G zfsfe58_^2DmlAznDxT30VKm=AA;hAwe;9tPH@4BpR0*9iXl3wb#M7Z@44$fot}~Hv z^Gcl5PR!_4!O>p$n3CS--WNOvC@l0c8TO)spwbFawa}G(j#)SZjd@eWqQGTYdV$TZ zE7^Ai0uXK;oOEXQNQlu4%Iz7G-?F$~1EUd{o=3WXOMRXpZLl@%&f_j8{F>w|C4cZq z9maE3&$TPl#$@7D+lq4O{dB7e{m%l;2dvHi>T6b0FIFAGXhi!g+v-8F{t2yzj-mZv zi*Rt?4OJL=CjNxX{4wqe44Qn1Lx3qJ)5LDG4s4YRa@JYd9f>iRy@g)%Kd_lq8&C0L zbNa8l9U)#;6T<}{;O_z^k7TyLoXC{Zig5Q+uVc0T#f(SZQ=n{qA#UI0f)#?YHWBd% z&Iy zAlw)K-=71u#zk(!>m;F*mx2ciy$*x~D z9TwCw$+Lc$hefeoOamcC_d|dcJofTdz?Zv>iHBTQUyCc<@1wKp-Ji0^i3re+jK1=U z>z+We;-hH||DCP;s%PYNdpzBE-X-%8Xh0gtX~X-yrE<=M1F^Ch5a)H=>r9TTTsIXx zbu3BgjKovoO`lBw00QLX)3F>Pd8M9`h9z_+FK_Kcb3BjH)V-WAJF+lOkmBFk5;t(A zZ7E#rsZ+A{_h@sw^EK;qqe*d`zz(m27E|D0x-?M8W>9iy$vB$veyMH|>shq!L^-mp z<;1&Kmf)2}3{EJA5BTM)imWp&OFLKpK6#wk>xC<^jwG2cj@ljip8C2ewUk=F##JT5 z>BCf$`mSVE44{LjaV5xLyk9^apnGTkC<8|GnSS6qdn}=FaapGf&&LLKDGJA#p3 z@y8C<{8kZ#3LF9{EI@3pgS(ij2UD%e-c0F1fzJ_h>O=9lIP~216uN<XTr6c(U(3<$9sXlm!Ai9;!)MC$Nf zhz3IeNqBSTLd2w0A^4Ne-iI&k5?Cd&&VFFp)0gXh{{5fra*%zsrbV))WZgkx@e&2N zp-fetUdqq>AFlk@6iHK}IV2XyPMh3#Z|~iL{+>jrn`j=$q;YcEi&fSJub&=TKl-5=3h9x%zVjKPma#v5>(oQG}?e9 zK4jU?bbrTcxgfbzn*P)i)wqV6(Gyo-ugB_gM* z;w9$S=2%<;B86mp%rKr;-ya`|TVz@v?!v>3~e{kFz#XwA>}zf-628MJn#M8K({c(RLdusjimnA3OKP8WIdej=;^{ z1dTH{5DZ%~BF8oIX)%Cvpw(cM>$r1Bm}!?yD0vSXc`u}mk*vzpdP!#LY1X2jH5EFV zQ9!?Bf~NA?V4`?r_#md~ZdHoSungrD)91;wpm*7O7Z%N!hOEdh8l#9nWx?2MdLRl{ z>uAN~Nb_e7Xo?6xgUgsq$nuu1%gWifNdO=Dc04A(#2YiJ8e4=A-Tkzszr=QEU(X@U zNjQFUB&^!m(pdXR*<5nBZ|LkPGNdDS$1Cr+Khs>H(V%mi6ZKGLB?hFwT%~zm;~kP* z|5IQy7!87f(aL5O(>&rNcOi#|ud9~9m$4=&F)^E|lSt+LOzBy|E+)`PIK7%CtwmsC zVCVMjEMCbkn*#=G&T|aMN+^fjC>SXe2~paAvt~^AJ|U4aVy;Xg?i$+7g2o=fqA9>P zKGBIHw^X122CJ3e27u%y-tbrxV!fT>cZ5aU;-lGM+`jgwT(v57)T!03sm>uFZ0P*z zB>7GDaA^FvXMnMi`WM?aIK-oUFo~e`mUNNr`p*($GVQ0l@tyX`6euJS?C*@q*P}Cb z#7?4(9P>CComAD`$r=$BZtE*jvYR zzlM51{rRFpVC?1~HxLN{Ja%(Z1Uru@H|xJ#%YV&Kk}X?1&wJ`ED2}-Ptv*pA5-|}G zaB3W+PNmSq?Sz36e#wzl7*NPQ@Ttj+|1%5EpA@*}Yc>F%jSLuBe{z9HZ|c$r2hlQ9 zyXy6uPo_P=uZEwQYKpx|J%VI9PYF-0U!la>8-V8%BpPYvqm!T$gbxZ$E`zo}c2t0z zQUYE7#;(u3y+M^K2T(frx-g^>gT(bD?4rI#@ZF6&`eP1t-c8W#AxYH?oph+p9R z{K8>P`bIXe*Qah9e)V~t>GS$>`2w?Yz1GI2Ih;Bo3%+t>jf-}rD#3#(Z_pmk(8wN% zEj1CPJ7-Qsf4i~A`|M#pw)Q}UO?R2K>k8%cG!r8>(4$KazVo=sR1KP~jGz@h1d z$8JN4Sdz^d9n6GZrIGv#NxU6xN6i?UF*qS%hGg8qdpSgD&2;T*@68~Q=;_rW$>hd+$ot*P16iH)RI(n+I{o1kZ=ROQ>y3Ka-4vqoc}zHmU_l67;Zr)42a z41;)L>*7)Flv%Wy*k}jh<`jf3FxQ!*2HHy~pKtOLc&6xeX_7}u?oV(jMW;#N$a!yx z==f#B1j+~aybwZ5#hpyIJU(=&E{0nqQ(&RZcKX=_Q21wW=`ud_1B z^m4IkBz6AWXn=D1X5fZ#Is3iZ{|{iV9vQ|`Mv%`#5?0fU=y#0GM|y=A1;I@wTF}OamMO z!Q$1z44J<9mS?>Ld8N=JLBH9kzi)DoS>0y!`dO?Y=sQ;cmeFIo>XakYK_Vlf7@#BL3^{kACo&}hK}!Z#B1kClcHN<%!kcg z^kApUa@ZE6d@4T1^`ARzasJwbp4YN<6Y@VkMf0&4;#F{3%aH40)ug!B?HqCG&#b0f zqM?I!e=x$7qq3L0Q0Lt{V=8CIMUGijK7LCA4di19G1qa*=I%A zwF98>J*FAMBrxeZ-@I4u`nOTwv!3&b`}(0{#sW~1;Yh0 zH42((LBVPC0K3=6|3eHocq&6=CXUpTDRE_ZJJe&LK-5cth7+u$tg7ALNneG1y0 zx$lfS^_F7f>`O8Sjgdgn6InJ{4=9K-zd0O}{v^vRX7v|p^E5SnQ>gDT=1$}h!^B|e zs@(}TOAxH{JLOKK$fPkfrbeU{yaXOU8J`O4vq@n&h{z$J`xknAo&z99^5{=r9S}Pe zbbpe@L0(BG!6y}Gk0DF+9nqeHpX~mvE}`+~xF#`EAd3+5AAJZrtZ**36=7}^F1`=# zhf2>WN>C|e$%L1!wgcMm5IY>@MIabp=M%YIyW&YsU%?5lkqPOsX12CF@GRKX&1Z4u zp2N^iM{x$0|u_v%n=@!JihzRAk(ju-p38U2_+y2H@GO0g}Ij5tikwS1zb5&IzR1!z5+J8Yn?bk1|vsh$9GwI=k(&^&TRK^LmazG_OuC z#zjpiF+I2=&T0=dx7BNz1$Wz3>*VX}KE;Tc&y`6X^}IO&0|-n!>lQXfxr%~1LkaQG zJqgO(4<9EXNo0i>)VhqpBah!-7?IpX!T>jyK>Z*?WuvIORF9zNG!WbwxCNyVu0(>? zno!y->?Sopl?^mar&T6o%{_s6=LnW?kRnn_+1%7&%@5nvLooy~tH1@0 zHe)cfG9ZT-Dsx0ohgpNPIgl`41Y3ST^5INE*p`7*+mpx0C+$Z1Bi#1ZTYr1XkEf(* zPeO4?w3Z_KO$=lg+Y5x@y>bF(mPfnsn%74UylFkiBk|*J__+GGrnHB~6iZBz3he0% zh5k}}#nc`ezoaG~DG7rv<^-WnFuJEQa+-Zo8COyV8`}$lcXT|sCW|f{8tA66H>|}z zUx&!OGc`ix#goh4Q0Rtd$nUj<3yJ!9wWygrKPW($Cfqao{H?r_{~rzYrUuDb2DFh} z;t#zeQ3N+(X`B$i%R3Xe;2tw`=p*qtb>H24K=TBCWv_%T4zCT6z0yKCpNd0BW7`+@ z4?`cmgyTmR%6G5T*oiHk>9h%6QaD8JPH>uAKk5^PufXhqo4T*h0n?i;}eq+$enM@3~v(#sxHysZFAr!?OU>-{~3eq`O4>YGK zeY#q`DO+1&bvkV;xJKu^npm z<~xq)wMV<9IO0qigJqC7fWPuYXp*uVKO7KYnAEClyh0wfZ;vIX660bCg(T3P<9G`RQx>c@{v% zbJuJLe`%fKQK8_OFccXZCaMKRi&#;;oS+{E{eX2M?xoqfk>aH!iHS<2%}aJ>TtA|m z^zlCH&hK0mc3PW)lx4b}<1Wzlz1u*r7(V@GKCDyMuO6wA-Pod?M zWo2UbqMngQ)nlyXCv=$-i-f_O|9-0U=MEAFEm#73#)J(0@b?y;ETf>PqY+N6=z)z{ zxLyT~uzl&v(&q9Il`xT|mhrp)MPQkEE^w@o-}oL`HDnEZG>*#&%h!)vFo1Cb;h_U^ z`OioM*2)S7b=--6Ncbft7E#%)LZuykb%3`saE%VbfM}(AhrzDN( zh?=b3gW0Nr(9_8TfPgt*10zf9LHQ0zo>#00@pv?h*T=UhW#Cy~ED8%znZZ~TB^vnj z3fy(?cjFd-*8Gx&!)hK;VIY^mvb|f2psJzEp(T~LVmSpNPS;~tPg+<_TUldPFT3i1 z)ZoV6)MoQ)OVGC3BWb5ljvIlB(+=yB99xY=NH%knGEHJJRPG6Yi}3)P?Kg_v?X@K{t~Wlrl!Q`B6FkLSQfl=8k!u^3~gd1eCoqV!V`5R zoWSg}!JkRyFYkZgjD7Exght&n5CG=0J*Mg;m6or<)3J~B=ODVT7+`P|l=iKT`_^y`x9!0~J2 zEV9C1n&^opsJF=HaGE-a;bT;Ry=+?dY8d=?KWF)*B=?#;Y>MIvvHL1PTVE^A0HuXi zCf62b9fdVFooEuz(eI1c;IP$1_3vl(p#9k0_@4~{{Gf!133c!HntyB9ACDP^=`UQXFl@Nz!NC%p(T3|q z-9L<7h^i2{bFfQ4#s5ZAFoIrCy}!;p$`Il{01eR0u)_xK)%ODNB9O5BcrR|;ZFGy; zzLrcC3oX!qBt#D;5RNvokAFY&&3yTRC=qt{$CHh*9x(}}N|eEKjj=2ii5IAN>bUTd z8lAcw$?^`>I>;`uN6rvFU$U-rllVM2>%z z9*oapM~w&We)aL_!6_r_|1~I?;(L>ma4%vxqsXKA*@{7u-54${d~M>;I_5V;j|DgF z=oQOc3wld)0ajBR+>fTl9&JCNCB)vUza-Fj^J!jG{f)%sb5;&@HmAnGP4ZtMZS0)j^zeZZ;$ zk*zPZXs%@FlgLS44ol9-BxH>T$s}?mxhf&Ox1M;F(cIlOLV*VNIdR$ZYxZ_=JcfpN zsRHWgMw4D%G4nW1)zQLbS?Ksz6_ZIyXTv!)_#N39@CN&ZlO@m(H5thZ+<4>tdPuTz z@m+ZJ*Ls&c09FQf&$&?Mc0F5`L}H)A){Hk;AX57``~#&$ALQ})q4f7kKP7fCLM^Zj zhV&Aw$^`)dbTK}ei_k$KpVHIaPri;xZt?UDjk#kcS9e%Q<39-o?rl6D0~LyhIEd9& zj`yl3UYT&_|88CNx#TY&_>+Jd^^2i!MV5Lc_&W1lpoPP!I`!E^vf#B^DY9dv~D@x8;RJ4b6JJU3HmF+?5UFp)0F(h_F(I!|e#FbigBj#P--P?fxKUo1MTP#CXmHR__P}R62I* zG2(0Rhz9)wC0g|)@cas-8E>E)vG#xt1=S2qAX{_c%rO0;@Cx9gM78PhH=or2EHG~^ zYR81YX;TwRJO1pVB~G(V%eID|JaLYW@OL!-)T&42QuPj zAInW0yQYA(zPGtRA~MREYN`N1KwBoH8-S{Q&zf29|7VuLZ{Ru{t8Aph%r!t}f2m}Q zQcFZQt-vO!`toD+hur}wwWcO2QgC7_8nyl-!s1U)BbT9TZ*kl~^oa~)^ojMe4(1Z= zjmTvQunIu(1K5Hkk*_JDf_)bhmF%mOR$*ZG?<z@?cv0E%?$my^y|pRkw0_TI1-ixLJQ5 zLI%U5!CB6h_c&hHDeqfa_v^2%uoM0Bges$3UL-T3H&+2%7dM+)>1tv*@u|8%%5(+< zPYEC^gA8Gf`%l@g{SBb5!LiEL<1G21X_i_&y~h5*b7R&E3=Z7gHCL0i7AP*&^maio zwy#WSl9lyDhlGN(oI8|<9TgS{RXOgy}TUFi4!DswQ=3nGgV(C+drlPwA|qG*tp>kzOqZMTUrb6yh$Dj#V02Ea35^ ztdBRt0+Pny2q{`#H*I$(DMnG&@yjg*n&f}h28ltq5!5WznD z+MWS&%9I+%70 zcr+--U+}#}WimQPHUj3v$U)g@PYyOzlD^^~2j3Mj9>EGzZ+HkXkmaBd<6&xilsG#M zG+~Ndd8B43!N{mz%y%-67)^|Cr?mu}zGmhU3KcNnY5vaH@riVkonr}`J#3QgIP{aJ zBV%O|-c0@$;d|102FP3{*}*a=cs;|jUF)n2{_)ad(J3>Iw>_H-I7o9W=z+~} zly^D~_*Vw4AH)4<@?#F_X7V;~BGV*H3_m()kv&Jh+B?TsJxF~BW|Nx11*HZxI=sij zUsK=|Rwu?R!C#Jiy@5ce{}%3`^iSH?I|-UD)fQP{u;_t0xstjI|Buhz>KSULcXMj-(ul=cf6Mhw28%u~x1#;scU zKv&zAsx>I~ZLekT?SZRo3~qM@ruUg3aMCHv##6FtoS{Sc;uOLF;=;6x zaQHBh@|IftCG~3sgE*pHle^VLHv_cdM*4V+2AN3jIR(4Paxh)%leGB#Qoqfu9)qr6 zBJO#a8B?Yu^Y|mB)dkF({WS_q@i1?0ZT1J37*X(<7etq14H8%b zH5dQMRvpxWiFU06)e(=X#PLg#47N#9TekfItrcR*pME*9%r>?SrP%04?hAxZ_q*5= zI_xQN7s5G;OXTV*rCeaiXh|q%CtZ=N&H7|tnn1Jf8r$CteN-Ah(t9%6sXPE8s>!1$ zy%xMI1$ofzJky4Vhy}RqT{`tVq3M(DmhRL!Z88H^O}yv6J){r1PD4+4+#xCPSxE$> z#ZqDV2ERmZ&+@bD#fex?VYn6|SIwkY-Co3*YCVGnOEo*M10q@eXet=+_L%9(kcsun z-cjecaFTNVO`ck|j6(ES#0WY)Wj2Joj|0ThcxQvnF1t&Kthx80aKlDTxtNutcv8sY*LU z6=`v?>7~btQVw;G8-1QZHPd+t8CN@f%fFIKCy^;3H{f6@=faX6T1x^2Sx9VOaBO8~ z0(8WqR8(UL`A(K^Ky#I`GNZUS>feD$Km=Hr^7RxTFt&8<2bo~F5og%e=tFrfEND}LTkC8p*aL( zjt*7_vy<$`w<@Id9vanJ-!#f&TL03Flj0N;G6F*ft5cMH<>B8fc(L*pr6bC?YUvn< zai;cr9~THP*Slx50HZFWGaLBXPZxPW2i?(QxA@!Lavk(`jx(BVH7S0fjd%v2m?&Bf ziUA+NiIGTI$GiH*|M@lb=PgHkdZMnyDdi|BLAzE|u>RjIIyB?ne0hv5v2Px&N#}7J zXj{XqBCp;dx0k_!PUe~YCN${Z)E9YSNR=_4rO^fMu%$(+kN%EowVWmGeFWU8ASlpR44>O`uAU!^axqv6}`7?i-xw7~s z0TSsZa0KkS-&j-`9tevmi3m`YawHEh`g=EYR zex>Z^y`2Fq9Y|9`rW0!DWvOx|@D-aFnAd>LE!(Vvb3j0xV9J(T0g&5|ysB76JL zrEL-`6ZfnY3Aeph7LF$giw(px(j`^_$#R#>8m082ILA_Qt#UBA zk_2H|l1?su5tavBA57oQNhHFCFh;(68>?O)3uTj7U0_Z5bfO#n{{v7KFKh@0#xy>= z@9?NYgHH5_qWZkUb*LInZgN$qs}9jt$Un*dJhhvv3U(K)zP6cT9>7^stZ{mc?aDC# z?L$zGL8H;t(Lji&72hW27+Ur*BX}ia@Bn0NUyW>QvT9$9exS)O+kl^m=;Z&I^&xwC z6ZoI*jp=aO?JpL9XXDStIuehnXG}In&>$-4_W=jOs}{#Q$CovnA@5!v=aC;C9%a?@ z3G)yF1=LX^EHb+>8Olcdt%OK&1Pg#_5vcI3?A1(##b&0#J%B=B5#~uwsNH8O;fapH zU@h%1>j6=FI$sO>DbfdKOgBZK8k1~y6YgNvW(*F{vJMQS^WW2XalyA*${o5Tl^&16 zobwCS1tXvPFY4^Sfs0WK_XqpI5W?+G<_|9EXp}2}eL|93AJv}!|8&4C9va}WF4G>+ z*nP^&HlviME zToM+Eh-wXi0d+UAwzSJRL;0Kt9D{~b z42fRQY}XmJ0w%4`t_36VMR0yNA9BPhR1r8A{Ob=>`y4{*TL%TYCg2|l^fl)sv9t*juaUW;G;rHz@pqX6On^amxwc^QH4_>eX){!s* z>WkwmUh3PKS8|4Zk^Kzim}Y|+e8_r3wk5}&-OJo8zsA#zXIN`tCEcaPjIt-Wj4{*! zYqkXy)MsSo=TVr0$inAob|FL3)F3A)^jP{OuRlL^BP<-Q&ofreQ+ZpNfCDHs=l#OV z4yAV;vQNxOTaI})j^^QMj|*Xe4_;aF3)QJJ#4k4%0K5qo+VVB>^s~6w@^+?*ePKCu z9tWf9%Ar`90(Qy;a@`8x^4|rpJF$txc26gcx~6c5;~Y8KK`S@R-vw)$dbfHp)uIe| z!oh8OI^-Hk`=~UQc7{IdA9eZx9qLesEsHdiyHUrc{Qta|0Z0e}lPLXLIX1Ydw`0f;w>}oKJPqG%XeVieqQ)WkHrN1S+kdNw zncv0}ZP(AAg&3^z@XZC!F$4uiSJtDUAJ7c&Pp&aI+&LyACamtIE%{sd_gR`M7xaL5 zDW-Wc6Ae`e-)k84H%4)WrzdC90n!fuygCTB4&uuod#d2aozPyXYwQO7j*j}34m zcJn*!9kw3z&8Hj;dSyRZV%$%F{C7(gB>cf`L~n`^_@-hxl#`Lq9s;1a*qcckolpaT z=OdzaZ5`(?vb$Ql26MA83w;L4^^yGV!|Nq-$k2rzBDZm)mNVM7ayb?Xj6bZ|3Wp(* zX@vA7w2CPWJf+0vM14;;G|_R5m5SYIZ$&kv z$htlqaL_hOGM0`ClHByw+FFJqAMy*C^x$xqV-hnsCxZ*A%jK{Zawwklmy=#-;_k>i zGKb7~Psz%lunb4^^1NEbQ>{cndNlRKMRL+lTIw+8(Y_&7 zYU~qYhJ-|FO`9a?^gKn^bi_}Sr;<3Hu;|fzbV~M1kb0=nxe82t>mGKgMSZAeADuK3A|u z7v2f0{@!bQ6bp&_dzc4yv#OoJym4=vOZyNRUlc)=wYk!Q!;|A)1~8-n@KX-d0E*2# zJpqtjSx%4O7$KaTZ(?N2mW}27iIFKWi&-GXDPoP*@xClotM3(*?F8Pu!s~199ZYNV z(A_K`rv!BR@f#QRax?I|&rukQ4(+kwt&#n@CfL=}4KH&mXX2Ix-k0Gr-jmFVr5HNq zWEo0x+Q3f&q5(-TYMO~K?Dk~RO?R^W(=rkl#mn?V<9iB(XDR5XdW5*hhLv&`j17X`Es@?=5&RL#M914c?**QNcIJ;egHC$mLZe5c~1)2yC@KWTrnP!8+2nwp$)9$JJy&}|LZ*B^3bPSSj?2+$UUaU zn$LCzwjGqfr1HbM_>i!okhjzT*_cf#H>DMekiPRBCcaEURU6L`w!dbUWH1NlKU2Vv zUy>u}C`PA!@r&e!H-uLe4@EQ9olEo^xSteKvk@oq3$;!R)=;5T40^t(OE=8%HMKq^ zlCw?-_2Nmx`VgslQ}vD>0V=t6k;`{#JD|b-Xh(f{4$9Jc7N0u#fS18lVtLFohL0RQ zG9;6&7b)EUmaE-m_}^aDOMQePqF@9oYrbf)Jh*po01$Iqi7`%)+nBA!$#vCU><@}^ zaU7p8FkDPbklZ5E_>dN zx!s?qqB@t1lyfTNYD8HK&Z}U(tQ#?;`N$cfFs`e~zAO@mmfJsFw6u`iTB9(SYAa6R z$tF1kj33{Uh9APm$`K%MZT`H9+?XEt!H$fpZlg ziBR140r-=>kxY+rE?EbN46jbrT1yn;{?mM68EHTgd79MV?=%cFq9Y{zynKLQOTe1@ zO^r;+RL7XjQ2sy55;og*RtapDjNvD>`Z9Sw)0EszV#+IPP`a2z-ZLSH(OnYydu3eO zQjiV3FY53stA!->4h!R*a$$qd5P_=RaU>B+(rQGMpf&Iuf)&&5{zGx^>`9|7dDWqv zoHL&FKp%3O{a$7GHgcsMZxzCSmayyBF;J=oJ)zuFgyhNB5z--H#?dD|s=D~0)swyw z0z!^4@qnY(y=h_~_&e+z#b9zk%ANutErx*T-nN{V`JM8;_kWr1mUuXYNzM?i%xOm<@n&$c;gCc(9=z~rg0n~~{B{D9(8j)H3H;_z{iJZ_lKC+o zK&JM6Fbvz8$^9tA{>~Z&oNChCRY%ifaw=J{3228vB<8;uwpx)5O}Zo^<^SO$Q@~vt zGAYyVugS-r>EttV_w!@Z)6W4Z_CvSsj}RbVm4D7VmCrOLbOPlNi>^}n*m^jD2F^Hz zu~*cpl;SL*atOn^>I`P)h?GQxo5HGHgg|8$tn<|b%ZHCjqa6eE5XBrJC!F69mSwq1 z9rR;C0p52#Rt0d0#FI3gsc-v2bBnxPkLJauhn-tes=0x)CTluIU3N=8rn>k1KR&L? zy6hY5V~#SAutB-8F8&0HF*tPhYa!uM?uNwn^q~A;kh{F^%*&De>b!+E)Idg!5kIs) zG7c+HuLcm~Q;D@sqr-M702{5ONfz;K-}NOBH3;ydAA?H+y2anO(z9~q4k2wjBo3sS zznmuETFS6@0D=m_K#LaPZZ`_>1DGKL!BFDEvWFOtlG>%P>J_)t;J{*N4SEk%7oRG5mzA7eG!)6w zb?{ujrfYEV=8_ezQc$N~FEgxC4!H(aR9bSn5WIyR$@SRX!jS}K*0iy{cV8kS0zZ6V zH$+$n0RxN=T6KN^GxOR`%d`pK_LnFy#OTQ{usS|OAzw?AWv!uykj4^@3;$d6_}N8Z zQ?KrMV;$YD#Oh$|yR^*BIAWVzJY0bXWp0b#E%wVDMXn}MStj>bhD{Rr8wJyLj`YtW z(Qw0r^iaX!uzF)vY4s85??xbsF+~ivtWqd^(9kQi^?fwQAXViV@P55C;frfNA&Iah zXT8icUXkF!&zDER0Ik!4^wEaA)(4ApG0tYd3AJ=3zwaeD@r9N5aexsg0GMjCjIF!Q z_$+`j%r71qghtW4c927mk`&e9*(U)r^ou33Rht zP=8fy3Ndyq4r|yGC&a3+vlfFvEJvj<^nlK%5BZ2Z$L7nA9P% zLd>$AVa;9%IV-lnwMp`I2?OX?^vXE+RF`Z_$>3%Un!e`IY0rK{oCF`;?04hczo{vu zE@$^u>IdkO+VY(c{g)m(lRi1PMSuffzn>hv^U{ZZDwP3=o!!v0_^PkhYoO{A!W8L| zE>i83;(}?@145@kXKVUU^Os7-xhEn_SzPAVRu7C8+k2{+^!zlTC=Y4(mM55>fp9yh z8OFVp-`-XSwBLAf5Y-1WjisCgyPWT@!U2-9u4WE#w(gB@$FF!W_*PRNNmMqL%=s3v zckJlmlSQEMMnS#dwF8j0ZZ&;~yd@aw%$aS{>?qgP#mH6OE7_@3kfR%W>$Epe4sApo ziA6#pXwDdMm8xGk@EOful$|Rf$>;D?Xn!}X#zgr)XI%#5%!|8jD8Eff2MksAxBC#& zep99id@v4MGxBVOJrzuuvk?XuZ%F#_FLn)S5D-RkX&ro$oJ2KZi+c{+O`EXUxyRq} z4d1NAa&K-iE*;}pnFk7m)<9Tc(z3K5B8!B+FjF&!r@4!RPCh24LOO9KXWi={=6F$5 z>gI)^!qvee*NtmFGxdoK0{wg+fMRi}B<N(CJE2)^=w-QiB+{FlyPp=%HEdE+R9(wUP{MuuUrL@ghzO3Vb{ppM}PLz@5 zQ}U38Bx75ojDlL60fpBtj>TPtC^5MsMjhb<)iBD=hEY8m>mL0y5@W@x6 zNGKO){Q`rxWaih>A)uS*v4lzz3e*WOue|1=!y7>;gP|Q>dvCg1)c=^$HLND zIsm)wMRzt9)|SLgbabAlz?nb}0&I{c^IzR%|H!v)_jX}eoB{;U(TD$3o{aDXBzC8~ zq){CFsyZLRlTT7rilZ}{+4RxIqFp?^TR1tQ2yj2}Z=LZi4+)O`*Y#UcV}7TUW=wS4 z_A*H9UX6Mfl;byPswx8hMIVGynP17%Z>lgNcH$8!B*Jl7F~<5WZ#sgA;VbF4#69hJ z7PHJP=Ik`Kj%#3RkFV%T6LSi2-f-9fTqq$9jK&jzi7^fv;d^Y3g+GilzVT%*=iD-J z!0Hk)*;hGs$wv&VZ)(u_@^QoYKN%aq;UzckzF5^LZbIo4c}%1x?ljS@0}uPY=*-b> zyf^$+SQ%UGUWABTbxE?<;ay7lKGk7`_@z>GDVj5?!!A?GFm}q8K(6`6D3-n1u0&v9 z4le&L^}X~OJ*W?3-CB{$BP(JR|MS}i%U<+NjrcO1LR=#T4Xo3eiZF-E@L-1*x z2P_3zlq=6LX|5Dk1X726V>PR!C(*wf7DrbZuR)c0b07FEX5a*k`q6{LK*2y6!jCs- zt-n}%pkl+Ysq=9NBXZcrqVWe+htf_*76DeUU$tlf)orFw4Md-%%QjJhla4>MGQVJN z{66j*CWhMuV>rZIRh$`J@{%GKaz!$<<*J$9I|W|tOH&mGw!-wsZvl+~F-w~L2_z*} zO>JEuEM1*@$KC6BK=7WJ8cG7b-J=~ur^AP6TC4K&%?gO==yH_Pt{N}2`US=Lg=Y`= zqW1WTnNFAwi)zIAtsT#zPlNgF>ktFE{^!9aq8{DlcZ!wNOtCsSK3B~Q3Jk_{Bim)s zK$&d1r_})n$17$3WIg0yVp-Xp^SSY+UplOzAF;J!eS_;1I0 z?V7utG=VrlR>%wh^sDw_iM20GwU2{& zQS`i)P+<}TqXCx_XzW){tm<;bdSo4m4+_%GVl_jgu*Gga`m_b+??BF25NZYI65v@T zWDtOTYz+u6l)-~h3(ZOR19Gpt(*|dx24~85XBxSD;zuEzg1P_~ihv{^6{|FA#*;$Z zxV709Kv^y|-Pw0=GtGUM?DksXrRMl`aM`P?u9IynksN#@*d?Cl66^bLLwUCqL2QsG zk~2kK$(bkinBZTZb6=8l`WPLCus73MVT_Zx8?fxJg#oPEy3K(P(m&15Di;1_X7O09 zk_vv5U^|V!aA%H3G681Th@nf&^_4iAPSSAOABY$PvmTgrxVS8+5(y(r4XkxiLz&;x z2rlv62g)jElH3V$v#KtaXE1QKkoPe z&ncp1F03}qiDnWUYAiE z3=n;GEBg*oN0KIn%Gs_LNJX?D_1CDyJeHm~Zy$pHXA^oI#Q$|s)q05myaNPlx%pp# z!gK<+iLo)QpVYiZbEv9dA;DhYvc)nYB}F<8hxPDDV9K1>wSnlUv6(Fu;uIVOrn&MU zD33*uk1Zvw6oA$iMKXc)8YKSxZ$LJ5f~~Y6_{TRK%JNV^I%Etvrg?tlpwE{j)#-cT zW?Nm6FC?rx*}*2nwwsFeT7?xZ?enml^IvYrj8R-BdUt+RrmfI&x4|I1u?76Y5jJpy#dv|e#t!B^ID>K#~Phbn;Nkd2aa=x-iG{g1#?P`3@+Jn zm@tD~rm2_6m-w|DOX~32% zkbm={%JO@n{xP)Rs~m8*JBR-%44SP;hIS2SG>6 zMEmO}ObGn-hhtFpUKcHjc2HRIt$RvJlztZZ+r!$K4->@i z&@d2T@p4RrsIaT>GB3GEOE3rLJi1vdU<5YQ#;<#MHBxJt+_JRbkvdh{vse$QCaCfd z`>6l-uX=Ku$6wm=%j}E>hF8?s%v5~s_iJ6V-DX+^Sd!t*_Q?451(DqzVYy*Rk}<<$ z`q1sMedn&w4BtOn|AyS-B8*D)y@Vvg+nDQ^fgWT;AMoo6u;I>k)>b zHp{8`B4)67_RqSRvu-KMsnt4k`U?bMDkLC=!_*8r%fyDa1F44^{`Lv$kBf zECz7r7q5;&4@x^KeEE#w|8-GcvyceiAFOres!+hyA(DV4p8c{1lv~dlVBKx*GMhTQ z0}1ENGLa8N>n2&DjD3*E`&FedS)9Wk;hq}^%sl&5iqQG8IgI(#wi2cC**nzkq(gc+ zx}Uh#*=!Z&T9vlFN$5a@ehp!`Q0sITtBQ~L%q6lp?z`+`NV9BnSVwrs@S+QH9@iuRTa|@CgeUr z4SzI3;3RHyeLSH^%H-I3k`zhyD=Ir)|kPJt0zP#=U{oYq@Ltxrgp;Cd8v; zPCzcS+~%$d2nN5Px{F`&j)ilOJDx!QRd{MnUN2I zkPLzNp;MsapfA!iVwcMm=D{JE=Du!pT)&wgcgsxE>;;qQq`k*MOS9Mt@`U|q0ChcF z@HmcqZQCXFr@iRG%D6OKv?Xz(>ee}n)jwapVZube#rCE z?T8}|Z0shHy{MKL&qEKun}58P>wGxhD@4Tbz-)QvThfzYEOy&rvaJ^&_5YIx?S{;R zC;3L@=$q2&m5x+{fYcj2JC6hWNJ>Bvy@aJsIO=oh{~u*gNa+fUsc5DbAfva@^xP^# zwJrwSADbcYPKA= zZ{NSo9D>pm*_KN_nxcKU-N$I&$3pBZ-=PEAe5tSK@y3So1RQ86ofx_60j~iE0NYlI zu#N&T)Fu7#J}87m2Tvrm`{wY@E$;E*Wm+fiKJIYc1UadEn~cvhvrW(fRZUnQ%O%qHGtO;Z@r4(d$bSWAV(~mS}1)E{fM=4ya!Ba^&^6FEA{ca2RU2y*J z?)b!0ntReZ1pq`)%Y5oYeo*2nBsN9f*EJa^4UUkQDM{==(K&adxGO`)Q3Fo((X8th zlfVV{(&nWWS9uGPWqGizWS&F_#gGfNhNqbY+o9@t2RH@(TBw;(cuD(Yk#A*cE+y6} z=L<7i(;j?aVP=;ouRmHFyR&*e5n85A>({qHFU6Iu@p_I|KAu^{jjU%`@a9%<&%qh- z5Zv3vIs6Pp)+Omqa7;yMZX(Z6D~I{0V5iNwBalwyuE~SUaO70Rn0l#g!pc~~dXQ9NAZxXyf}@uOZNhFwy|n#s_$0DIKd<8DF<;T0RRfvCZ`&y;ROUp3j!EB%4z zslr85l;1gn`D^1VyB;SY^(Q)ukmUk5A6)NJP$5c}xhAQL1bkIh6HVhzX01uZfBWQJ z(AF?>xX5b$Ay8=a9&0%`w=&jy?8R740M`(5xcen!h-)%~+_#?5@XBW*wvJyF>|@f) zL*jb!>H-MGlmO#PNIQsZZm^q+3w^nqE)aRs)Ql7&CV7jZv=j2%JPj!>w(dlH?iX|k z%b8rw1knBVmnL&Z97$OOQ1_Eb@v;Z3aW78!>E%auBbjIuq?%e35~v&qd|%jc>No_0 zas;$wbkX`|*otpoa3=QSfEK>4)kt|z_A4B`L9P4!_(WP6I~2pQ=l^a(N-PiUI=ySY zlYQL@g;=r&q22>WHI$?}eNx18pPuc))~#3W13ZovT_FSp_XCGJ>dz3UKJNV4nC}n3 z@6Qv2owFW-N9Ud}sIxH}G!O13!bLJ~rCu4#X9R$&DwKZlp-?P=7vBZaR1R_`M=TG7 zUOW~-_ttj2(Xx#8k#+1PqgmG94PIX>wr=h*re;zEk2)?*7h5fbhs)DE*R7oOx-&&> zMtI<0`S2LA85P{0{F|WVseqU=Su-^mNMr4%uWb@M5A^T$NMc-}15B$_yx|_?@Z%m# zGK9#>8;**RDhn)UWu7~G&Z{_G9`o$5pk&7WQnHky$it;f349Ua$aR6_1+=fH$7ZH~ zsJWF$f-?L*i|*#okr-dF0p2Lwhck{cCj`^!FU5~p(`8Ie_U>iMP9kzH-mk)(pax_4 zXDvGkABXGBbYqvDJ+zg?z}kD-0>Go#M|>BBOj#k2(c67OJ$Wd7GR-$_Y?z>;BMg?h z$VNO|f9;DsH1VDalX%n(XP6u{gSc%>g|&g^ueChcLjfX*TCh#pQLxhnogEv+kyE0D zKY_NU@anWgaMSMJtCMO}iKiIlKUR9E#bqSDIW5Rwfai39TpaxCqi6-kksr zt{x+pr2E80`L1h3V6G==(a>2WLR7(L(NQmGr2nJ4&~$dzpv;c{Ku5m8Z^MxD#hC(O zA-gvxxW{I&qlfS7O8Doml?=kQn8qCvsPS6U`7>T3as!ftl+4pI+Xux-3knwQB{Q}# ztQc_;65zTJagH5~e{B(0`n2MdpL+VP2H3MO#=Svhp|!w8KeY3z zbG$d5;ah)oa~bi{^`#%v%Q^k=*}OA@n(?-tvGfk807$GY#*bl-)!+RW9lbfi`#GRzL(bXki(C#=Y-O_}?aht* z;-G@b`T$ZkkA${IATKxCfrNFgeaP0dgS*1bgrwxY+Ip5u1RJa`iw|4p-;k!2KqSh0 z+e4ajWo=d2W1Htkq=Gi}B5GojZ>2B&qm*UHk4^73sY@ZHfkZ}pex4+-6!zahI^3z^ z0PdcmU#caJOrM>qqr#`9F-(UwE{nGTZw?9*O+_Qa{J*!D0;iIr53ut zcoR02R&)xXe{(EI#B+1ydv_Q#tNKZ*XF2JDfj&XQL}UA+7Y(g}!pqZ@cmNtLTd?4-N^%G! zAhQU+*yr6S=V#g)1bt-k#@{T&YrQXyH)mk>Gir%Ik+odT{$wk3Y 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But first, please read -. diff --git a/firmware/ChibiOS_16/os/common/ports/ARM/compilers/GCC/crt0.s b/firmware/ChibiOS_16/os/common/ports/ARM/compilers/GCC/crt0.s deleted file mode 100644 index 8b4e3c0946..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARM/compilers/GCC/crt0.s +++ /dev/null @@ -1,152 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file crt0.s - * @brief Generic ARM startup file. - * - * @addtogroup ARM_GCC_STARTUP - * @{ - */ - -#if !defined(__DOXYGEN__) - - .set MODE_USR, 0x10 - .set MODE_FIQ, 0x11 - .set MODE_IRQ, 0x12 - .set MODE_SVC, 0x13 - .set MODE_ABT, 0x17 - .set MODE_UND, 0x1B - .set MODE_SYS, 0x1F - - .set I_BIT, 0x80 - .set F_BIT, 0x40 - - .text - .code 32 - .balign 4 - -/* - * Reset handler. - */ - .global Reset_Handler -Reset_Handler: - /* - * Stack pointers initialization. - */ - ldr r0, =__stacks_end__ - /* Undefined */ - msr CPSR_c, #MODE_UND | I_BIT | F_BIT - mov sp, r0 - ldr r1, =__und_stack_size__ - sub r0, r0, r1 - /* Abort */ - msr CPSR_c, #MODE_ABT | I_BIT | F_BIT - mov sp, r0 - ldr r1, =__abt_stack_size__ - sub r0, r0, r1 - /* FIQ */ - msr CPSR_c, #MODE_FIQ | I_BIT | F_BIT - mov sp, r0 - ldr r1, =__fiq_stack_size__ - sub r0, r0, r1 - /* IRQ */ - msr CPSR_c, #MODE_IRQ | I_BIT | F_BIT - mov sp, r0 - ldr r1, =__irq_stack_size__ - sub r0, r0, r1 - /* Supervisor */ - msr CPSR_c, #MODE_SVC | I_BIT | F_BIT - mov sp, r0 - ldr r1, =__svc_stack_size__ - sub r0, r0, r1 - /* System */ - msr CPSR_c, #MODE_SYS | I_BIT | F_BIT - mov sp, r0 -// ldr r1, =__sys_stack_size__ -// sub r0, r0, r1 - /* - * Early initialization. - */ -#if !defined(THUMB_NO_INTERWORKING) - bl __early_init -#else /* defined(THUMB_NO_INTERWORKING) */ - add r0, pc, #1 - bx r0 - .code 16 - bl __early_init - mov r0, pc - bx r0 - .code 32 -#endif /* defined(THUMB_NO_INTERWORKING) */ - - /* - * Data initialization. - * NOTE: It assumes that the DATA size is a multiple of 4. - */ - ldr r1, =_textdata - ldr r2, =_data - ldr r3, =_edata -dataloop: - cmp r2, r3 - ldrlo r0, [r1], #4 - strlo r0, [r2], #4 - blo dataloop - /* - * BSS initialization. - * NOTE: It assumes that the BSS size is a multiple of 4. - */ - mov r0, #0 - ldr r1, =_bss_start - ldr r2, =_bss_end -bssloop: - cmp r1, r2 - strlo r0, [r1], #4 - blo bssloop - /* - * Late initialization. - */ -#if !defined(THUMB_NO_INTERWORKING) - bl __late_init -#else /* defined(THUMB_NO_INTERWORKING) */ - add r0, pc, #1 - bx r0 - .code 16 - bl __late_init - mov r0, pc - bx r0 - .code 32 -#endif /* defined(THUMB_NO_INTERWORKING) */ - - /* - * Main program invocation. - */ -#if defined(THUMB_NO_INTERWORKING) - add r0, pc, #1 - bx r0 - .code 16 - bl main - ldr r1, =__default_exit - bx r1 - .code 32 -#else /* !defined(THUMB_NO_INTERWORKING) */ - bl main - b __default_exit -#endif /* !defined(THUMB_NO_INTERWORKING) */ - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/ARM/compilers/GCC/crt1.c b/firmware/ChibiOS_16/os/common/ports/ARM/compilers/GCC/crt1.c deleted file mode 100644 index 23c1b37244..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARM/compilers/GCC/crt1.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file ARMCMx/compilers/GCC/crt1.c - * @brief Startup stub functions. - * - * @addtogroup ARMCMx_GCC_STARTUP - * @{ - */ - -#include - -/** - * @brief Early initialization. - * @details This hook is invoked immediately after the stack initialization - * and before the DATA and BSS segments initialization. The - * default behavior is to do nothing. - * @note This function is a weak symbol. - */ -#if !defined(__DOXYGEN__) -__attribute__((weak)) -#endif -/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/ -void __early_init(void) {} -/*lint -restore*/ - -/** - * @brief Late initialization. - * @details This hook is invoked after the DATA and BSS segments - * initialization and before any static constructor. The - * default behavior is to do nothing. - * @note This function is a weak symbol. - */ -#if !defined(__DOXYGEN__) -__attribute__((weak)) -#endif -/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/ -void __late_init(void) {} -/*lint -restore*/ - -/** - * @brief Default @p main() function exit handler. - * @details This handler is invoked or the @p main() function exit. The - * default behavior is to enter an infinite loop. - * @note This function is a weak symbol. - */ -#if !defined(__DOXYGEN__) -__attribute__((noreturn, weak)) -#endif -/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/ -void __default_exit(void) { -/*lint -restore*/ - - while (true) { - } -} - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/ARM/compilers/GCC/ld/LPC2148.ld b/firmware/ChibiOS_16/os/common/ports/ARM/compilers/GCC/ld/LPC2148.ld deleted file mode 100644 index e17a66f025..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARM/compilers/GCC/ld/LPC2148.ld +++ /dev/null @@ -1,43 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * LPC2148 memory setup. - */ -MEMORY -{ - flash : org = 0x00000000, len = 512k - 12k - ram0 : org = 0x40000200, len = 32k - 0x200 - 288 - ram1 : org = 0x00000000, len = 0 - ram2 : org = 0x00000000, len = 0 - ram3 : org = 0x00000000, len = 0 - ram4 : org = 0x00000000, len = 0 - ram5 : org = 0x00000000, len = 0 - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* RAM region to be used for stacks. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("STACKS_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -INCLUDE rules.ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARM/compilers/GCC/mk/startup_lpc214x.mk b/firmware/ChibiOS_16/os/common/ports/ARM/compilers/GCC/mk/startup_lpc214x.mk deleted file mode 100644 index 3ab99b73ce..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARM/compilers/GCC/mk/startup_lpc214x.mk +++ /dev/null @@ -1,9 +0,0 @@ -# List of the ChibiOS generic LPC214x file. -STARTUPSRC = $(CHIBIOS)/os/common/ports/ARM/compilers/GCC/crt1.c - -STARTUPASM = $(CHIBIOS)/os/common/ports/ARM/compilers/GCC/vectors.s \ - $(CHIBIOS)/os/common/ports/ARM/compilers/GCC/crt0.s - -STARTUPINC = ${CHIBIOS}/os/common/ports/ARM/devices/LPC214x - -STARTUPLD = ${CHIBIOS}/os/common/ports/ARM/compilers/GCC/ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARM/compilers/GCC/rules.ld b/firmware/ChibiOS_16/os/common/ports/ARM/compilers/GCC/rules.ld deleted file mode 100644 index f3b5f51bf4..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARM/compilers/GCC/rules.ld +++ /dev/null @@ -1,221 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -__stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__; - -__ram0_start__ = ORIGIN(ram0); -__ram0_size__ = LENGTH(ram0); -__ram0_end__ = __ram0_start__ + __ram0_size__; -__ram1_start__ = ORIGIN(ram1); -__ram1_size__ = LENGTH(ram1); -__ram1_end__ = __ram1_start__ + __ram1_size__; -__ram2_start__ = ORIGIN(ram2); -__ram2_size__ = LENGTH(ram2); -__ram2_end__ = __ram2_start__ + __ram2_size__; -__ram3_start__ = ORIGIN(ram3); -__ram3_size__ = LENGTH(ram3); -__ram3_end__ = __ram3_start__ + __ram3_size__; -__ram4_start__ = ORIGIN(ram4); -__ram4_size__ = LENGTH(ram4); -__ram4_end__ = __ram4_start__ + __ram4_size__; -__ram5_start__ = ORIGIN(ram5); -__ram5_size__ = LENGTH(ram5); -__ram5_end__ = __ram5_start__ + __ram5_size__; -__ram6_start__ = ORIGIN(ram6); -__ram6_size__ = LENGTH(ram6); -__ram6_end__ = __ram6_start__ + __ram6_size__; -__ram7_start__ = ORIGIN(ram7); -__ram7_size__ = LENGTH(ram7); -__ram7_end__ = __ram7_start__ + __ram7_size__; - -ENTRY(Reset_Handler) - -SECTIONS -{ - . = 0; - _text = .; - - startup : ALIGN(16) SUBALIGN(16) - { - KEEP(*(.vectors)) - } > flash - - constructors : ALIGN(4) SUBALIGN(4) - { - PROVIDE(__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - } > flash - - destructors : ALIGN(4) SUBALIGN(4) - { - PROVIDE(__fini_array_start = .); - KEEP(*(.fini_array)) - KEEP(*(SORT(.fini_array.*))) - PROVIDE(__fini_array_end = .); - } > flash - - .text : ALIGN(16) SUBALIGN(16) - { - *(.text) - *(.text.*) - *(.rodata) - *(.rodata.*) - *(.glue_7t) - *(.glue_7) - *(.gcc*) - } > flash - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > flash - - .ARM.exidx : { - PROVIDE(__exidx_start = .); - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - PROVIDE(__exidx_end = .); - } > flash - - .eh_frame_hdr : - { - *(.eh_frame_hdr) - } > flash - - .eh_frame : ONLY_IF_RO - { - *(.eh_frame) - } > flash - - .textalign : ONLY_IF_RO - { - . = ALIGN(8); - } > flash - - . = ALIGN(4); - _etext = .; - _textdata = _etext; - - .stacks : - { - . = ALIGN(8); - __stacks_base__ = .; - . += __stacks_total_size__; - . = ALIGN(8); - __stacks_end__ = .; - } > STACKS_RAM - - .data : ALIGN(4) - { - . = ALIGN(4); - PROVIDE(_data = .); - *(.data) - *(.data.*) - *(.ramtext) - . = ALIGN(4); - PROVIDE(_edata = .); - } > DATA_RAM AT > flash - - .bss : ALIGN(4) - { - . = ALIGN(4); - PROVIDE(_bss_start = .); - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - PROVIDE(_bss_end = .); - PROVIDE(end = .); - } > BSS_RAM - - .ram0 (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - *(.ram0) - *(.ram0.*) - . = ALIGN(4); - __ram0_free__ = .; - } > ram0 - - .ram1 (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - *(.ram1) - *(.ram1.*) - . = ALIGN(4); - __ram1_free__ = .; - } > ram1 - - .ram2 (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - *(.ram2) - *(.ram2.*) - . = ALIGN(4); - __ram2_free__ = .; - } > ram2 - - .ram3 (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - *(.ram3) - *(.ram3.*) - . = ALIGN(4); - __ram3_free__ = .; - } > ram3 - - .ram4 (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - *(.ram4) - *(.ram4.*) - . = ALIGN(4); - __ram4_free__ = .; - } > ram4 - - .ram5 (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - *(.ram5) - *(.ram5.*) - . = ALIGN(4); - __ram5_free__ = .; - } > ram5 - - .ram6 (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - *(.ram6) - *(.ram6.*) - . = ALIGN(4); - __ram6_free__ = .; - } > ram6 - - .ram7 (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - *(.ram7) - *(.ram7.*) - . = ALIGN(4); - __ram7_free__ = .; - } > ram7 -} - -/* Heap default boundaries, it is defaulted to be the non-used part - of ram0 region.*/ -__heap_base__ = __ram0_free__; -__heap_end__ = __ram0_end__; diff --git a/firmware/ChibiOS_16/os/common/ports/ARM/compilers/GCC/rules.mk b/firmware/ChibiOS_16/os/common/ports/ARM/compilers/GCC/rules.mk deleted file mode 100644 index d77d730d19..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARM/compilers/GCC/rules.mk +++ /dev/null @@ -1,312 +0,0 @@ -# ARM Cortex-Mx common makefile scripts and rules. - -############################################################################## -# Processing options coming from the upper Makefile. -# - -# Compiler options -OPT = $(USE_OPT) -COPT = $(USE_COPT) -CPPOPT = $(USE_CPPOPT) - -# Garbage collection -ifeq ($(USE_LINK_GC),yes) - OPT += -ffunction-sections -fdata-sections -fno-common - LDOPT := ,--gc-sections -else - LDOPT := -endif - -# Linker extra options -ifneq ($(USE_LDOPT),) - LDOPT := $(LDOPT),$(USE_LDOPT) -endif - -# Link time optimizations -ifeq ($(USE_LTO),yes) - OPT += -flto -endif - -# Undefined state stack size -ifeq ($(USE_UND_STACKSIZE),) - LDOPT := $(LDOPT),--defsym=__und_stack_size__=8 -else - LDOPT := $(LDOPT),--defsym=__und_stack_size__=$(USE_UND_STACKSIZE) -endif - -# Abort stack size -ifeq ($(USE_ABT_STACKSIZE),) - LDOPT := $(LDOPT),--defsym=__abt_stack_size__=8 -else - LDOPT := $(LDOPT),--defsym=__abt_stack_size__=$(USE_ABT_STACKSIZE) -endif - -# FIQ stack size -ifeq ($(USE_FIQ_STACKSIZE),) - LDOPT := $(LDOPT),--defsym=__fiq_stack_size__=64 -else - LDOPT := $(LDOPT),--defsym=__fiq_stack_size__=$(USE_FIQ_STACKSIZE) -endif - -# IRQ stack size -ifeq ($(USE_IRQ_STACKSIZE),) - LDOPT := $(LDOPT),--defsym=__irq_stack_size__=0x400 -else - LDOPT := $(LDOPT),--defsym=__irq_stack_size__=$(USE_IRQ_STACKSIZE) -endif - -# Supervisor stack size -ifeq ($(USE_SUPERVISOR_STACKSIZE),) - LDOPT := $(LDOPT),--defsym=__svc_stack_size__=8 -else - LDOPT := $(LDOPT),--defsym=__svc_stack_size__=$(USE_SUPERVISOR_STACKSIZE) -endif - -# System stack size -ifeq ($(USE_SYSTEM_STACKSIZE),) - LDOPT := $(LDOPT),--defsym=__sys_stack_size__=0x400 -else - LDOPT := $(LDOPT),--defsym=__sys_stack_size__=$(USE_SYSTEM_STACKSIZE) -endif - -# Output directory and files -ifeq ($(BUILDDIR),) - BUILDDIR = build -endif -ifeq ($(BUILDDIR),.) - BUILDDIR = build -endif -OUTFILES = $(BUILDDIR)/$(PROJECT).elf $(BUILDDIR)/$(PROJECT).hex \ - $(BUILDDIR)/$(PROJECT).bin $(BUILDDIR)/$(PROJECT).dmp \ - $(BUILDDIR)/$(PROJECT).list - - -# Source files groups and paths -ifeq ($(USE_THUMB),yes) - TCSRC += $(CSRC) - TCPPSRC += $(CPPSRC) -else - ACSRC += $(CSRC) - ACPPSRC += $(CPPSRC) -endif -ASRC = $(ACSRC) $(ACPPSRC) -TSRC = $(TCSRC) $(TCPPSRC) -SRCPATHS = $(sort $(dir $(ASMXSRC)) $(dir $(ASMSRC)) $(dir $(ASRC)) $(dir $(TSRC))) - -# Various directories -OBJDIR = $(BUILDDIR)/obj -LSTDIR = $(BUILDDIR)/lst - -# Object files groups -ACOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ACSRC:.c=.o))) -ACPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ACPPSRC:.cpp=.o))) -TCOBJS = $(addprefix $(OBJDIR)/, $(notdir $(TCSRC:.c=.o))) -TCPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(TCPPSRC:.cpp=.o))) -ASMOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMSRC:.s=.o))) -ASMXOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMXSRC:.S=.o))) -OBJS = $(ASMXOBJS) $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS) - -# Paths -IINCDIR = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR)) -LLIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) - -# Macros -DEFS = $(DDEFS) $(UDEFS) -ADEFS = $(DADEFS) $(UADEFS) - -# Libs -LIBS = $(DLIBS) $(ULIBS) - -# Various settings -MCFLAGS = -mcpu=$(MCU) -ODFLAGS = -x --syms -ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS) -ASXFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS) -CFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS) -CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS) -LDFLAGS = $(MCFLAGS) $(OPT) -nostartfiles $(LLIBDIR) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--library-path=$(RULESPATH),--script=$(LDSCRIPT)$(LDOPT) - -# Thumb interwork enabled only if needed because it kills performance. -ifneq ($(strip $(TSRC)),) - CFLAGS += -DTHUMB_PRESENT - CPPFLAGS += -DTHUMB_PRESENT - ASFLAGS += -DTHUMB_PRESENT - ASXFLAGS += -DTHUMB_PRESENT - ifneq ($(strip $(ASRC)),) - # Mixed ARM and THUMB mode. - CFLAGS += -mthumb-interwork - CPPFLAGS += -mthumb-interwork - ASFLAGS += -mthumb-interwork - ASXFLAGS += -mthumb-interwork - LDFLAGS += -mthumb-interwork - else - # Pure THUMB mode, THUMB C code cannot be called by ARM asm code directly. - CFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING - CPPFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING - ASFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -mthumb - ASXFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -mthumb - LDFLAGS += -mno-thumb-interwork -mthumb - endif -else - # Pure ARM mode - CFLAGS += -mno-thumb-interwork - CPPFLAGS += -mno-thumb-interwork - ASFLAGS += -mno-thumb-interwork - ASXFLAGS += -mno-thumb-interwork - LDFLAGS += -mno-thumb-interwork -endif - -# Generate dependency information -ASFLAGS += -MD -MP -MF .dep/$(@F).d -ASXFLAGS += -MD -MP -MF .dep/$(@F).d -CFLAGS += -MD -MP -MF .dep/$(@F).d -CPPFLAGS += -MD -MP -MF .dep/$(@F).d - -# Paths where to search for sources -VPATH = $(SRCPATHS) - -# -# Makefile rules -# - -all: PRE_MAKE_ALL_RULE_HOOK $(OBJS) $(OUTFILES) POST_MAKE_ALL_RULE_HOOK - -PRE_MAKE_ALL_RULE_HOOK: - -POST_MAKE_ALL_RULE_HOOK: - -$(OBJS): | $(BUILDDIR) $(OBJDIR) $(LSTDIR) - -$(BUILDDIR): -ifneq ($(USE_VERBOSE_COMPILE),yes) - @echo Compiler Options - @echo $(CC) -c $(CFLAGS) -I. $(IINCDIR) main.c -o main.o - @echo -endif - @mkdir -p $(BUILDDIR) - -$(OBJDIR): - @mkdir -p $(OBJDIR) - -$(LSTDIR): - @mkdir -p $(LSTDIR) - -$(ACPPOBJS) : $(OBJDIR)/%.o : %.cpp Makefile -ifeq ($(USE_VERBOSE_COMPILE),yes) - @echo - $(CPPC) -c $(CPPFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@ -else - @echo Compiling $( $@ - $(SZ) $< -else - @echo Creating $@ - @$(OD) $(ODFLAGS) $< > $@ - @echo - @$(SZ) $< -endif - -%.list: %.elf -ifeq ($(USE_VERBOSE_COMPILE),yes) - $(OD) -S $< > $@ -else - @echo Creating $@ - @$(OD) -S $< > $@ - @echo - @echo Done -endif - -lib: $(OBJS) $(BUILDDIR)/lib$(PROJECT).a - -$(BUILDDIR)/lib$(PROJECT).a: $(OBJS) - @$(AR) -r $@ $^ - @echo - @echo Done - -clean: - @echo Cleaning - -rm -fR .dep $(BUILDDIR) - @echo - @echo Done - -# -# Include the dependency files, should be the last of the makefile -# --include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) - -# *** EOF *** diff --git a/firmware/ChibiOS_16/os/common/ports/ARM/compilers/GCC/vectors.s b/firmware/ChibiOS_16/os/common/ports/ARM/compilers/GCC/vectors.s deleted file mode 100644 index 7ca71e0131..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARM/compilers/GCC/vectors.s +++ /dev/null @@ -1,98 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file ARM/compilers/GCC/vectors.s - * @brief Interrupt vectors for ARM devices. - * - * @defgroup ARM_VECTORS ARM Exception Vectors - * @{ - */ - -#if defined(__DOXYGEN__) -/** - * @brief Unhandled exceptions handler. - * @details Any undefined exception vector points to this function by default. - * This function simply stops the system into an infinite loop. - * @note The default implementation is a weak symbol, the application - * can override the default implementation. - * - * @notapi - */ -void _unhandled_exception(void) {} -#endif - -#if !defined(__DOXYGEN__) - - .section .vectors, "ax" - .code 32 - .balign 4 - -/* - * System entry points. - */ - .global _start -_start: - ldr pc, _reset - ldr pc, _undefined - ldr pc, _swi - ldr pc, _prefetch - ldr pc, _abort - nop - ldr pc, _irq - ldr pc, _fiq - -_reset: - .word Reset_Handler -_undefined: - .word Und_Handler -_swi: - .word Swi_Handler -_prefetch: - .word Prefetch_Handler -_abort: - .word Abort_Handler -_fiq: - .word Fiq_Handler -_irq: - .word Irq_Handler - -/* - * Default exceptions handlers. The handlers are declared weak in order to be - * replaced by the real handling code. Everything is defaulted to an infinite - * loop. - */ - .weak Reset_Handler -Reset_Handler: - .weak Und_Handler -Und_Handler: - .weak Swi_Handler -Swi_Handler: - .weak Prefetch_Handler -Prefetch_Handler: - .weak Abort_Handler -Abort_Handler: - .weak Fiq_Handler -Fiq_Handler: - .weak Irq_Handler -Irq_Handler: - .weak _unhandled_exception -_unhandled_exception: - b _unhandled_exception - -#endif - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/ARM/devices/LPC214x/armparams.h b/firmware/ChibiOS_16/os/common/ports/ARM/devices/LPC214x/armparams.h deleted file mode 100644 index 9ee46ce6af..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARM/devices/LPC214x/armparams.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file armparams.h - * @brief ARM parameters for the LPC214x. - * - * @defgroup ARM_LPC214x LPC214x Specific Parameters - * @ingroup ARM_SPECIFIC - * @details This file contains the ARM specific parameters for the - * LPC214x platform. - * @{ - */ - -#ifndef _ARMPARAMS_H_ -#define _ARMPARAMS_H_ - -/** - * @brief ARM core model. - */ -#define ARM_CORE ARM_CORE_ARM7TDMI - -/** - * @brief Thumb-capable. - */ -#define ARM_SUPPORTS_THUMB 1 - -/** - * @brief Thumb2-capable. - */ -#define ARM_SUPPORTS_THUMB2 0 - -/** - * @brief Implementation of the wait-for-interrupt state enter. - */ -#define ARM_WFI_IMPL (PCON = 1) - -#if !defined(_FROM_ASM_) || defined(__DOXYGEN__) -/** - * @brief Address of the IRQ vector register in the interrupt controller. - */ -#define ARM_IRQ_VECTOR_REG 0xFFFFF030U -#else -#define ARM_IRQ_VECTOR_REG 0xFFFFF030 -#endif - -#endif /* _ARMPARAMS_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/ARM/devices/LPC214x/lpc214x.h b/firmware/ChibiOS_16/os/common/ports/ARM/devices/LPC214x/lpc214x.h deleted file mode 100644 index fc127c5897..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARM/devices/LPC214x/lpc214x.h +++ /dev/null @@ -1,523 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file lpc214x.h - * @brief LPC214x register definitions. - */ - -#ifndef _LPC214X_H_ -#define _LPC214X_H_ - -typedef volatile uint8_t IOREG8; -typedef volatile uint16_t IOREG16; -typedef volatile uint32_t IOREG32; - -/* - * System. - */ -#define MEMMAP (*((IOREG32 *)0xE01FC040)) -#define PCON (*((IOREG32 *)0xE01FC0C0)) -#define PCONP (*((IOREG32 *)0xE01FC0C4)) -#define VPBDIV (*((IOREG32 *)0xE01FC100)) -#define EXTINT (*((IOREG32 *)0xE01FC140)) -#define INTWAKE (*((IOREG32 *)0xE01FC144)) -#define EXTMODE (*((IOREG32 *)0xE01FC148)) -#define EXTPOLAR (*((IOREG32 *)0xE01FC14C)) -#define RSID (*((IOREG32 *)0xE01FC180)) -#define CSPR (*((IOREG32 *)0xE01FC184)) -#define SCS (*((IOREG32 *)0xE01FC1A0)) - -#define VPD_D4 0 -#define VPD_D1 1 -#define VPD_D2 2 -#define VPD_RESERVED 3 - -#define PCTIM0 (1 << 1) -#define PCTIM1 (1 << 2) -#define PCUART0 (1 << 3) -#define PCUART1 (1 << 4) -#define PCPWM0 (1 << 5) -#define PCI2C0 (1 << 7) -#define PCSPI0 (1 << 8) -#define PCRTC (1 << 9) -#define PCSPI1 (1 << 10) -#define PCAD0 (1 << 12) -#define PCI2C1 (1 << 19) -#define PCAD1 (1 << 20) -#define PCUSB (1 << 31) -#define PCALL (PCTIM0 | PCTIM1 | PCUART0 | PCUART1 | \ - PCPWM0 | PCI2C0 | PCSPI0 | PCRTC | PCSPI1 | \ - PCAD0 | PCI2C1 | PCAD1 | PCUSB) - -#define EINT0 1 -#define EINT1 2 -#define EINT2 4 -#define EINT3 8 - -#define EXTWAKE0 1 -#define EXTWAKE1 2 -#define EXTWAKE2 4 -#define EXTWAKE3 8 -#define USBWAKE 0x20 -#define BODWAKE 0x4000 -#define RTCWAKE 0x8000 - -#define EXTMODE0 1 -#define EXTMODE1 2 -#define EXTMODE2 4 -#define EXTMODE3 8 - -#define EXTPOLAR0 1 -#define EXTPOLAR1 2 -#define EXTPOLAR2 4 -#define EXTPOLAR3 8 - -typedef struct { - IOREG32 PLL_CON; - IOREG32 PLL_CFG; - IOREG32 PLL_STAT; - IOREG32 PLL_FEED; -} PLL; - -#define PLL0Base ((PLL *)0xE01FC080) -#define PLL1Base ((PLL *)0xE01FC0A0) -#define PLL0CON (PLL0Base->PLL_CON) -#define PLL0CFG (PLL0Base->PLL_CFG) -#define PLL0STAT (PLL0Base->PLL_STAT) -#define PLL0FEED (PLL0Base->PLL_FEED) -#define PLL1CON (PLL1Base->PLL_CON) -#define PLL1CFG (PLL1Base->PLL_CFG) -#define PLL1STAT (PLL1Base->PLL_STAT) -#define PLL1FEED (PLL1Base->PLL_FEED) - -/* - * Pins. - */ -typedef struct { - IOREG32 PS_SEL0; - IOREG32 PS_SEL1; - IOREG32 _dummy[3]; - IOREG32 PS_SEL2; -} PS; - -#define PSBase ((PS *)0xE002C000) -#define PINSEL0 (PSBase->PS_SEL0) -#define PINSEL1 (PSBase->PS_SEL1) -#define PINSEL2 (PSBase->PS_SEL2) - -/* - * VIC - */ -#define SOURCE_WDT 0 -#define SOURCE_ARMCore0 2 -#define SOURCE_ARMCore1 3 -#define SOURCE_Timer0 4 -#define SOURCE_Timer1 5 -#define SOURCE_UART0 6 -#define SOURCE_UART1 7 -#define SOURCE_PWM0 8 -#define SOURCE_I2C0 9 -#define SOURCE_SPI0 10 -#define SOURCE_SPI1 11 -#define SOURCE_PLL 12 -#define SOURCE_RTC 13 -#define SOURCE_EINT0 14 -#define SOURCE_EINT1 15 -#define SOURCE_EINT2 16 -#define SOURCE_EINT3 17 -#define SOURCE_ADC0 18 -#define SOURCE_I2C1 19 -#define SOURCE_BOD 20 -#define SOURCE_ADC1 21 -#define SOURCE_USB 22 - -#define INTMASK(n) (1 << (n)) -#define ALLINTMASK (INTMASK(SOURCE_WDT) | INTMASK(SOURCE_ARMCore0) | \ - INTMASK(SOURCE_ARMCore1) | INTMASK(SOURCE_Timer0) | \ - INTMASK(SOURCE_Timer1) | INTMASK(SOURCE_UART0) | \ - INTMASK(SOURCE_UART1) | INTMASK(SOURCE_PWM0) | \ - INTMASK(SOURCE_I2C0) | INTMASK(SOURCE_SPI0) | \ - INTMASK(SOURCE_SPI1) | INTMASK(SOURCE_PLL) | \ - INTMASK(SOURCE_RTC) | INTMASK(SOURCE_EINT0) | \ - INTMASK(SOURCE_EINT1) | INTMASK(SOURCE_EINT2) | \ - INTMASK(SOURCE_EINT3) | INTMASK(SOURCE_ADC0) | \ - INTMASK(SOURCE_I2C1) | INTMASK(SOURCE_BOD) | \ - INTMASK(SOURCE_ADC1) | INTMASK(SOURCE_USB)) - -typedef struct { - IOREG32 VIC_IRQStatus; - IOREG32 VIC_FIQStatus; - IOREG32 VIC_RawIntr; - IOREG32 VIC_IntSelect; - IOREG32 VIC_IntEnable; - IOREG32 VIC_IntEnClear; - IOREG32 VIC_SoftInt; - IOREG32 VIC_SoftIntClear; - IOREG32 VIC_Protection; - IOREG32 unused1[3]; - IOREG32 VIC_VectAddr; - IOREG32 VIC_DefVectAddr; - IOREG32 unused2[50]; - IOREG32 VIC_VectAddrs[16]; - IOREG32 unused3[48]; - IOREG32 VIC_VectCntls[16]; -} VIC; - -#define VICBase ((VIC *)0xFFFFF000) -#define VICVectorsBase ((IOREG32 *)0xFFFFF100) -#define VICControlsBase ((IOREG32 *)0xFFFFF200) - -#define VICIRQStatus (VICBase->VIC_IRQStatus) -#define VICFIQStatus (VICBase->VIC_FIQStatus) -#define VICRawIntr (VICBase->VIC_RawIntr) -#define VICIntSelect (VICBase->VIC_IntSelect) -#define VICIntEnable (VICBase->VIC_IntEnable) -#define VICIntEnClear (VICBase->VIC_IntEnClear) -#define VICSoftInt (VICBase->VIC_SoftInt) -#define VICSoftIntClear (VICBase->VIC_SoftIntClear) -#define VICProtection (VICBase->VIC_Protection) -#define VICVectAddr (VICBase->VIC_VectAddr) -#define VICDefVectAddr (VICBase->VIC_DefVectAddr) - -#define VICVectAddrs(n) (VICBase->VIC_VectAddrs[n]) -#define VICVectCntls(n) (VICBase->VIC_VectCntls[n]) - -/* - * MAM. - */ -typedef struct { - IOREG32 MAM_Control; - IOREG32 MAM_Timing; -} MAM; - -#define MAMBase ((MAM *)0xE01FC000) -#define MAMCR (MAMBase->MAM_Control) -#define MAMTIM (MAMBase->MAM_Timing) - -/* - * GPIO - FIO. - */ -typedef struct { - IOREG32 IO_PIN; - IOREG32 IO_SET; - IOREG32 IO_DIR; - IOREG32 IO_CLR; -} GPIO; - -#define GPIO0Base ((GPIO *)0xE0028000) -#define IO0PIN (GPIO0Base->IO_PIN) -#define IO0SET (GPIO0Base->IO_SET) -#define IO0DIR (GPIO0Base->IO_DIR) -#define IO0CLR (GPIO0Base->IO_CLR) - -#define GPIO1Base ((GPIO *)0xE0028010) -#define IO1PIN (GPIO1Base->IO_PIN) -#define IO1SET (GPIO1Base->IO_SET) -#define IO1DIR (GPIO1Base->IO_DIR) -#define IO1CLR (GPIO1Base->IO_CLR) - -typedef struct { - IOREG32 FIO_DIR; - IOREG32 unused1; - IOREG32 unused2; - IOREG32 unused3; - IOREG32 FIO_MASK; - IOREG32 FIO_PIN; - IOREG32 FIO_SET; - IOREG32 FIO_CLR; -} FIO; - -#define FIO0Base ((FIO *)0x3FFFC000) -#define FIO0DIR (FIO0Base->FIO_DIR) -#define FIO0MASK (FIO0Base->FIO_MASK) -#define FIO0PIN (FIO0Base->FIO_PIN) -#define FIO0SET (FIO0Base->FIO_SET) -#define FIO0CLR (FIO0Base->FIO_CLR) - -#define FIO1Base ((FIO *)0x3FFFC020) -#define FIO1DIR (FIO1Base->FIO_DIR) -#define FIO1MASK (FIO1Base->FIO_MASK) -#define FIO1PIN (FIO1Base->FIO_PIN) -#define FIO1SET (FIO1Base->FIO_SET) -#define FIO1CLR (FIO1Base->FIO_CLR) - -/* - * UART. - */ -typedef struct { - union { - IOREG32 UART_RBR; - IOREG32 UART_THR; - IOREG32 UART_DLL; - }; - union { - IOREG32 UART_IER; - IOREG32 UART_DLM; - }; - union { - IOREG32 UART_IIR; - IOREG32 UART_FCR; - }; - IOREG32 UART_LCR; - IOREG32 UART_MCR; - IOREG32 UART_LSR; - IOREG32 unused18; - IOREG32 UART_SCR; - IOREG32 UART_ACR; - IOREG32 unused24; - IOREG32 UART_FDR; - IOREG32 unused2C; - IOREG32 UART_TER; -} UART; - -#define U0Base ((UART *)0xE000C000) -#define U0RBR (U0Base->UART_RBR) -#define U0THR (U0Base->UART_THR) -#define U0DLL (U0Base->UART_DLL) -#define U0IER (U0Base->UART_IER) -#define U0DLM (U0Base->UART_DLM) -#define U0IIR (U0Base->UART_IIR) -#define U0FCR (U0Base->UART_FCR) -#define U0LCR (U0Base->UART_LCR) -#define U0LSR (U0Base->UART_LSR) -#define U0SCR (U0Base->UART_SCR) -#define U0ACR (U0Base->UART_ACR) -#define U0FDR (U0Base->UART_FDR) -#define U0TER (U0Base->UART_TER) - -#define U1Base ((UART *)0xE0010000) -#define U1RBR (U1Base->UART_RBR) -#define U1THR (U1Base->UART_THR) -#define U1DLL (U1Base->UART_DLL) -#define U1IER (U1Base->UART_IER) -#define U1DLM (U1Base->UART_DLM) -#define U1IIR (U1Base->UART_IIR) -#define U1FCR (U1Base->UART_FCR) -#define U1MCR (U1Base->UART_MCR) -#define U1LCR (U1Base->UART_LCR) -#define U1LSR (U1Base->UART_LSR) -#define U1SCR (U1Base->UART_SCR) -#define U1ACR (U1Base->UART_ACR) -#define U1FDR (U1Base->UART_FDR) -#define U1TER (U1Base->UART_TER) - -#define IIR_SRC_MASK 0x0F -#define IIR_SRC_NONE 0x01 -#define IIR_SRC_TX 0x02 -#define IIR_SRC_RX 0x04 -#define IIR_SRC_ERROR 0x06 -#define IIR_SRC_TIMEOUT 0x0C - -#define IER_RBR 1 -#define IER_THRE 2 -#define IER_STATUS 4 - -#define IIR_INT_PENDING 1 - -#define LCR_WL5 0 -#define LCR_WL6 1 -#define LCR_WL7 2 -#define LCR_WL8 3 -#define LCR_STOP1 0 -#define LCR_STOP2 4 -#define LCR_NOPARITY 0 -#define LCR_PARITYODD 0x08 -#define LCR_PARITYEVEN 0x18 -#define LCR_PARITYONE 0x28 -#define LCR_PARITYZERO 0x38 -#define LCR_BREAK_ON 0x40 -#define LCR_DLAB 0x80 - -#define FCR_ENABLE 1 -#define FCR_RXRESET 2 -#define FCR_TXRESET 4 -#define FCR_TRIGGER0 0 -#define FCR_TRIGGER1 0x40 -#define FCR_TRIGGER2 0x80 -#define FCR_TRIGGER3 0xC0 - -#define LSR_RBR_FULL 1 -#define LSR_OVERRUN 2 -#define LSR_PARITY 4 -#define LSR_FRAMING 8 -#define LSR_BREAK 0x10 -#define LSR_THRE 0x20 -#define LSR_TEMT 0x40 -#define LSR_RXFE 0x80 - -#define TER_ENABLE 0x80 - -/* - * SSP. - */ -typedef struct { - IOREG32 SSP_CR0; - IOREG32 SSP_CR1; - IOREG32 SSP_DR; - IOREG32 SSP_SR; - IOREG32 SSP_CPSR; - IOREG32 SSP_IMSC; - IOREG32 SSP_RIS; - IOREG32 SSP_MIS; - IOREG32 SSP_ICR; -} SSP; - -#define SSPBase ((SSP *)0xE0068000) -#define SSPCR0 (SSPBase->SSP_CR0) -#define SSPCR1 (SSPBase->SSP_CR1) -#define SSPDR (SSPBase->SSP_DR) -#define SSPSR (SSPBase->SSP_SR) -#define SSPCPSR (SSPBase->SSP_CPSR) -#define SSPIMSC (SSPBase->SSP_IMSC) -#define SSPRIS (SSPBase->SSP_RIS) -#define SSPMIS (SSPBase->SSP_MIS) -#define SSPICR (SSPBase->SSP_ICR) - -#define CR0_DSSMASK 0x0F -#define CR0_DSS4BIT 3 -#define CR0_DSS5BIT 4 -#define CR0_DSS6BIT 5 -#define CR0_DSS7BIT 6 -#define CR0_DSS8BIT 7 -#define CR0_DSS9BIT 8 -#define CR0_DSS10BIT 9 -#define CR0_DSS11BIT 0xA -#define CR0_DSS12BIT 0xB -#define CR0_DSS13BIT 0xC -#define CR0_DSS14BIT 0xD -#define CR0_DSS15BIT 0xE -#define CR0_DSS16BIT 0xF -#define CR0_FRFSPI 0 -#define CR0_FRFSSI 0x10 -#define CR0_FRFMW 0x20 -#define CR0_CPOL 0x40 -#define CR0_CPHA 0x80 -#define CR0_CLOCKRATE(n) ((n) << 8) - -#define CR1_LBM 1 -#define CR1_SSE 2 -#define CR1_MS 4 -#define CR1_SOD 8 - -#define SR_TFE 1 -#define SR_TNF 2 -#define SR_RNE 4 -#define SR_RFF 8 -#define SR_BSY 0x10 - -#define IMSC_ROR 1 -#define IMSC_RT 2 -#define IMSC_RX 4 -#define IMSC_TX 8 - -#define RIS_ROR 1 -#define RIS_RT 2 -#define RIS_RX 4 -#define RIS_TX 8 - -#define MIS_ROR 1 -#define MIS_RT 2 -#define MIS_RX 4 -#define MIS_TX 8 - -#define ICR_ROR 1 -#define ICR_RT 2 - -/* - * Timers/Counters. - */ -typedef struct { - IOREG32 TC_IR; - IOREG32 TC_TCR; - IOREG32 TC_TC; - IOREG32 TC_PR; - IOREG32 TC_PC; - IOREG32 TC_MCR; - IOREG32 TC_MR0; - IOREG32 TC_MR1; - IOREG32 TC_MR2; - IOREG32 TC_MR3; - IOREG32 TC_CCR; - IOREG32 TC_CR0; - IOREG32 TC_CR1; - IOREG32 TC_CR2; - IOREG32 TC_CR3; - IOREG32 TC_EMR; - IOREG32 TC_CTCR; -} TC; - -#define T0Base ((TC *)0xE0004000) -#define T0IR (T0Base->TC_IR) -#define T0TCR (T0Base->TC_TCR) -#define T0TC (T0Base->TC_TC) -#define T0PR (T0Base->TC_PR) -#define T0PC (T0Base->TC_PC) -#define T0MCR (T0Base->TC_MCR) -#define T0MR0 (T0Base->TC_MR0) -#define T0MR1 (T0Base->TC_MR1) -#define T0MR2 (T0Base->TC_MR2) -#define T0MR3 (T0Base->TC_MR3) -#define T0CCR (T0Base->TC_CCR) -#define T0CR0 (T0Base->TC_CR0) -#define T0CR1 (T0Base->TC_CR1) -#define T0CR2 (T0Base->TC_CR2) -#define T0CR3 (T0Base->TC_CR3) -#define T0EMR (T0Base->TC_EMR) -#define T0CTCR (T0Base->TC_CTCR) - -#define T1Base ((TC *)0xE0008000) -#define T1IR (T1Base->TC_IR) -#define T1TCR (T1Base->TC_TCR) -#define T1TC (T1Base->TC_TC) -#define T1PR (T1Base->TC_PR) -#define T1PC (T1Base->TC_PC) -#define T1MCR (T1Base->TC_MCR) -#define T1MR0 (T1Base->TC_MR0) -#define T1MR1 (T1Base->TC_MR1) -#define T1MR2 (T1Base->TC_MR2) -#define T1MR3 (T1Base->TC_MR3) -#define T1CCR (T1Base->TC_CCR) -#define T1CR0 (T1Base->TC_CR0) -#define T1CR1 (T1Base->TC_CR1) -#define T1CR2 (T1Base->TC_CR2) -#define T1CR3 (T1Base->TC_CR3) -#define T1EMR (T1Base->TC_EMR) -#define T1CTCR (T1Base->TC_CTCR) - -/* - * Watchdog. - */ -typedef struct { - IOREG32 WD_MOD; - IOREG32 WD_TC; - IOREG32 WD_FEED; - IOREG32 WD_TV; -} WD; - -#define WDBase ((WD *)0xE0000000) -#define WDMOD (WDBase->WD_MOD) -#define WDTC (WDBase->WD_TC) -#define WDFEED (WDBase->WD_FEED) -#define WDTV (WDBase->WD_TV) - -/* - * DAC. - */ -#define DACR (*((IOREG32 *)0xE006C000)) - -#endif /* _LPC214X_H_ */ - diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/crt0_v6m.s b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/crt0_v6m.s deleted file mode 100644 index 5fabb73817..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/crt0_v6m.s +++ /dev/null @@ -1,256 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file crt0_v6m.s - * @brief Generic ARMv6-M (Cortex-M0/M1) startup file for ChibiOS. - * - * @addtogroup ARMCMx_GCC_STARTUP_V6M - * @{ - */ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -#if !defined(FALSE) || defined(__DOXYGEN__) -#define FALSE 0 -#endif - -#if !defined(TRUE) || defined(__DOXYGEN__) -#define TRUE 1 -#endif - -#define CONTROL_MODE_PRIVILEGED 0 -#define CONTROL_MODE_UNPRIVILEGED 1 -#define CONTROL_USE_MSP 0 -#define CONTROL_USE_PSP 2 - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Control special register initialization value. - * @details The system is setup to run in privileged mode using the PSP - * stack (dual stack mode). - */ -#if !defined(CRT0_CONTROL_INIT) || defined(__DOXYGEN__) -#define CRT0_CONTROL_INIT (CONTROL_USE_PSP | \ - CONTROL_MODE_PRIVILEGED) -#endif - -/** - * @brief Core initialization switch. - */ -#if !defined(CRT0_INIT_CORE) || defined(__DOXYGEN__) -#define CRT0_INIT_CORE TRUE -#endif - -/** - * @brief Stack segments initialization switch. - */ -#if !defined(CRT0_STACKS_FILL_PATTERN) || defined(__DOXYGEN__) -#define CRT0_STACKS_FILL_PATTERN 0x55555555 -#endif - -/** - * @brief Stack segments initialization switch. - */ -#if !defined(CRT0_INIT_STACKS) || defined(__DOXYGEN__) -#define CRT0_INIT_STACKS TRUE -#endif - -/** - * @brief DATA segment initialization switch. - */ -#if !defined(CRT0_INIT_DATA) || defined(__DOXYGEN__) -#define CRT0_INIT_DATA TRUE -#endif - -/** - * @brief BSS segment initialization switch. - */ -#if !defined(CRT0_INIT_BSS) || defined(__DOXYGEN__) -#define CRT0_INIT_BSS TRUE -#endif - -/** - * @brief RAM areas initialization switch. - */ -#if !defined(CRT0_INIT_RAM_AREAS) || defined(__DOXYGEN__) -#define CRT0_INIT_RAM_AREAS TRUE -#endif - -/** - * @brief Constructors invocation switch. - */ -#if !defined(CRT0_CALL_CONSTRUCTORS) || defined(__DOXYGEN__) -#define CRT0_CALL_CONSTRUCTORS TRUE -#endif - -/** - * @brief Destructors invocation switch. - */ -#if !defined(CRT0_CALL_DESTRUCTORS) || defined(__DOXYGEN__) -#define CRT0_CALL_DESTRUCTORS TRUE -#endif - -/*===========================================================================*/ -/* Code section. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) - - .cpu cortex-m0 - .fpu softvfp - - .thumb - .text - -/* - * Reset handler. - */ - .align 2 - .thumb_func - .global Reset_Handler -Reset_Handler: - /* Interrupts are globally masked initially.*/ - cpsid i - - /* PSP stack pointers initialization.*/ - ldr r0, =__process_stack_end__ - msr PSP, r0 - - /* CPU mode initialization as configured.*/ - movs r0, #CRT0_CONTROL_INIT - msr CONTROL, r0 - isb - -#if CRT0_INIT_CORE == TRUE - /* Core initialization.*/ - bl __core_init -#endif - - /* Early initialization..*/ - bl __early_init - -#if CRT0_INIT_STACKS == TRUE - ldr r0, =CRT0_STACKS_FILL_PATTERN - /* Main Stack initialization. Note, it assumes that the - stack size is a multiple of 4 so the linker file must - ensure this.*/ - ldr r1, =__main_stack_base__ - ldr r2, =__main_stack_end__ -msloop: - cmp r1, r2 - bge endmsloop - str r0, [r1] - add r1, r1, #4 - b msloop -endmsloop: - /* Process Stack initialization. Note, it assumes that the - stack size is a multiple of 4 so the linker file must - ensure this.*/ - ldr r1, =__process_stack_base__ - ldr r2, =__process_stack_end__ -psloop: - cmp r1, r2 - bge endpsloop - str r0, [r1] - add r1, r1, #4 - b psloop -endpsloop: -#endif - -#if CRT0_INIT_DATA == TRUE - /* Data initialization. Note, it assumes that the DATA size - is a multiple of 4 so the linker file must ensure this.*/ - ldr r1, =_textdata - ldr r2, =_data - ldr r3, =_edata -dloop: - cmp r2, r3 - bge enddloop - ldr r0, [r1] - str r0, [r2] - add r1, r1, #4 - add r2, r2, #4 - b dloop -enddloop: -#endif - -#if CRT0_INIT_BSS == TRUE - /* BSS initialization. Note, it assumes that the DATA size - is a multiple of 4 so the linker file must ensure this.*/ - movs r0, #0 - ldr r1, =_bss_start - ldr r2, =_bss_end -bloop: - cmp r1, r2 - bge endbloop - str r0, [r1] - add r1, r1, #4 - b bloop -endbloop: -#endif - -#if CRT0_INIT_RAM_AREAS == TRUE - /* RAM areas initialization.*/ - bl __init_ram_areas -#endif - - /* Late initialization..*/ - bl __late_init - -#if CRT0_CALL_CONSTRUCTORS == TRUE - /* Constructors invocation.*/ - ldr r4, =__init_array_start - ldr r5, =__init_array_end -initloop: - cmp r4, r5 - bge endinitloop - ldr r1, [r4] - blx r1 - add r4, r4, #4 - b initloop -endinitloop: -#endif - - /* Main program invocation, r0 contains the returned value.*/ - bl main - -#if CRT0_CALL_DESTRUCTORS == TRUE - /* Destructors invocation.*/ - ldr r4, =__fini_array_start - ldr r5, =__fini_array_end -finiloop: - cmp r4, r5 - bge endfiniloop - ldr r1, [r4] - blx r1 - add r4, r4, #4 - b finiloop -endfiniloop: -#endif - - /* Branching to the defined exit handler.*/ - ldr r1, =__default_exit - bx r1 - -#endif - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/crt0_v7m.s b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/crt0_v7m.s deleted file mode 100644 index 63c3ba754f..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/crt0_v7m.s +++ /dev/null @@ -1,319 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file crt0_v7m.s - * @brief Generic ARMv7-M (Cortex-M3/M4/M7) startup file for ChibiOS. - * - * @addtogroup ARMCMx_GCC_STARTUP_V7M - * @{ - */ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -#if !defined(FALSE) || defined(__DOXYGEN__) -#define FALSE 0 -#endif - -#if !defined(TRUE) || defined(__DOXYGEN__) -#define TRUE 1 -#endif - -#define CONTROL_MODE_PRIVILEGED 0 -#define CONTROL_MODE_UNPRIVILEGED 1 -#define CONTROL_USE_MSP 0 -#define CONTROL_USE_PSP 2 -#define CONTROL_FPCA 4 - -#define FPCCR_ASPEN (1 << 31) -#define FPCCR_LSPEN (1 << 30) - -#define SCB_CPACR 0xE000ED88 -#define SCB_FPCCR 0xE000EF34 -#define SCB_FPDSCR 0xE000EF3C - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief FPU initialization switch. - */ -#if !defined(CRT0_INIT_FPU) || defined(__DOXYGEN__) -#if defined(CORTEX_USE_FPU) || defined(__DOXYGEN__) -#define CRT0_INIT_FPU CORTEX_USE_FPU -#else -#define CRT0_INIT_FPU FALSE -#endif -#endif - -/** - * @brief Control special register initialization value. - * @details The system is setup to run in privileged mode using the PSP - * stack (dual stack mode). - */ -#if !defined(CRT0_CONTROL_INIT) || defined(__DOXYGEN__) -#define CRT0_CONTROL_INIT (CONTROL_USE_PSP | \ - CONTROL_MODE_PRIVILEGED) -#endif - -/** - * @brief Core initialization switch. - */ -#if !defined(CRT0_INIT_CORE) || defined(__DOXYGEN__) -#define CRT0_INIT_CORE TRUE -#endif - -/** - * @brief Stack segments initialization switch. - */ -#if !defined(CRT0_STACKS_FILL_PATTERN) || defined(__DOXYGEN__) -#define CRT0_STACKS_FILL_PATTERN 0x55555555 -#endif - -/** - * @brief Stack segments initialization switch. - */ -#if !defined(CRT0_INIT_STACKS) || defined(__DOXYGEN__) -#define CRT0_INIT_STACKS TRUE -#endif - -/** - * @brief DATA segment initialization switch. - */ -#if !defined(CRT0_INIT_DATA) || defined(__DOXYGEN__) -#define CRT0_INIT_DATA TRUE -#endif - -/** - * @brief BSS segment initialization switch. - */ -#if !defined(CRT0_INIT_BSS) || defined(__DOXYGEN__) -#define CRT0_INIT_BSS TRUE -#endif - -/** - * @brief RAM areas initialization switch. - */ -#if !defined(CRT0_INIT_RAM_AREAS) || defined(__DOXYGEN__) -#define CRT0_INIT_RAM_AREAS TRUE -#endif - -/** - * @brief Constructors invocation switch. - */ -#if !defined(CRT0_CALL_CONSTRUCTORS) || defined(__DOXYGEN__) -#define CRT0_CALL_CONSTRUCTORS TRUE -#endif - -/** - * @brief Destructors invocation switch. - */ -#if !defined(CRT0_CALL_DESTRUCTORS) || defined(__DOXYGEN__) -#define CRT0_CALL_DESTRUCTORS TRUE -#endif - -/** - * @brief FPU FPCCR register initialization value. - * @note Only used if @p CRT0_INIT_FPU is equal to @p TRUE. - */ -#if !defined(CRT0_FPCCR_INIT) || defined(__DOXYGEN__) -#define CRT0_FPCCR_INIT (FPCCR_ASPEN | FPCCR_LSPEN) -#endif - -/** - * @brief CPACR register initialization value. - * @note Only used if @p CRT0_INIT_FPU is equal to @p TRUE. - */ -#if !defined(CRT0_CPACR_INIT) || defined(__DOXYGEN__) -#define CRT0_CPACR_INIT 0x00F00000 -#endif - -/*===========================================================================*/ -/* Code section. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) - - .syntax unified - .cpu cortex-m3 -#if CRT0_INIT_FPU == TRUE - .fpu fpv4-sp-d16 -#else - .fpu softvfp -#endif - - .thumb - .text - -/* - * Reset handler. - */ - .align 2 - .thumb_func - .global Reset_Handler -Reset_Handler: - /* Interrupts are globally masked initially.*/ - cpsid i - - /* PSP stack pointers initialization.*/ - ldr r0, =__process_stack_end__ - msr PSP, r0 - -#if CRT0_INIT_FPU == TRUE - /* FPU FPCCR initialization.*/ - movw r0, #CRT0_FPCCR_INIT & 0xFFFF - movt r0, #CRT0_FPCCR_INIT >> 16 - movw r1, #SCB_FPCCR & 0xFFFF - movt r1, #SCB_FPCCR >> 16 - str r0, [r1] - dsb - isb - - /* CPACR initialization.*/ - movw r0, #CRT0_CPACR_INIT & 0xFFFF - movt r0, #CRT0_CPACR_INIT >> 16 - movw r1, #SCB_CPACR & 0xFFFF - movt r1, #SCB_CPACR >> 16 - str r0, [r1] - dsb - isb - - /* FPU FPSCR initially cleared.*/ - mov r0, #0 - vmsr FPSCR, r0 - - /* FPU FPDSCR initially cleared.*/ - movw r1, #SCB_FPDSCR & 0xFFFF - movt r1, #SCB_FPDSCR >> 16 - str r0, [r1] - - /* Enforcing FPCA bit in the CONTROL register.*/ - movs r0, #CRT0_CONTROL_INIT | CONTROL_FPCA - -#else - movs r0, #CRT0_CONTROL_INIT -#endif - - /* CONTROL register initialization as configured.*/ - msr CONTROL, r0 - isb - -#if CRT0_INIT_CORE == TRUE - /* Core initialization.*/ - bl __core_init -#endif - - /* Early initialization.*/ - bl __early_init - -#if CRT0_INIT_STACKS == TRUE - ldr r0, =CRT0_STACKS_FILL_PATTERN - /* Main Stack initialization. Note, it assumes that the - stack size is a multiple of 4 so the linker file must - ensure this.*/ - ldr r1, =__main_stack_base__ - ldr r2, =__main_stack_end__ -msloop: - cmp r1, r2 - itt lo - strlo r0, [r1], #4 - blo msloop - - /* Process Stack initialization. Note, it assumes that the - stack size is a multiple of 4 so the linker file must - ensure this.*/ - ldr r1, =__process_stack_base__ - ldr r2, =__process_stack_end__ -psloop: - cmp r1, r2 - itt lo - strlo r0, [r1], #4 - blo psloop -#endif - -#if CRT0_INIT_DATA == TRUE - /* Data initialization. Note, it assumes that the DATA size - is a multiple of 4 so the linker file must ensure this.*/ - ldr r1, =_textdata_start - ldr r2, =_data_start - ldr r3, =_data_end -dloop: - cmp r2, r3 - ittt lo - ldrlo r0, [r1], #4 - strlo r0, [r2], #4 - blo dloop -#endif - -#if CRT0_INIT_BSS == TRUE - /* BSS initialization. Note, it assumes that the DATA size - is a multiple of 4 so the linker file must ensure this.*/ - movs r0, #0 - ldr r1, =_bss_start - ldr r2, =_bss_end -bloop: - cmp r1, r2 - itt lo - strlo r0, [r1], #4 - blo bloop -#endif - -#if CRT0_INIT_RAM_AREAS == TRUE - /* RAM areas initialization.*/ - bl __init_ram_areas -#endif - - /* Late initialization..*/ - bl __late_init - -#if CRT0_CALL_CONSTRUCTORS == TRUE - /* Constructors invocation.*/ - ldr r4, =__init_array_start - ldr r5, =__init_array_end -initloop: - cmp r4, r5 - bge endinitloop - ldr r1, [r4], #4 - blx r1 - b initloop -endinitloop: -#endif - - /* Main program invocation, r0 contains the returned value.*/ - bl main - -#if CRT0_CALL_DESTRUCTORS == TRUE - /* Destructors invocation.*/ - ldr r4, =__fini_array_start - ldr r5, =__fini_array_end -finiloop: - cmp r4, r5 - bge endfiniloop - ldr r1, [r4], #4 - blx r1 - b finiloop -endfiniloop: -#endif - - /* Branching to the defined exit handler.*/ - b __default_exit - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/crt1.c b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/crt1.c deleted file mode 100644 index 24bf30bdd5..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/crt1.c +++ /dev/null @@ -1,218 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file ARMCMx/compilers/GCC/crt1.c - * @brief Startup stub functions. - * - * @addtogroup ARMCMx_GCC_STARTUP - * @{ - */ - -#include - -#include "cmparams.h" - -/*===========================================================================*/ -/* Module local definitions. */ -/*===========================================================================*/ - -#if !defined(CRT1_AREAS_NUMBER) || defined(__DOXYGEN__) -#define CRT1_AREAS_NUMBER 8 -#endif - -#if (CRT1_AREAS_NUMBER < 0) || (CRT1_AREAS_NUMBER > 8) -#error "CRT1_AREAS_NUMBER must be within 0 and 8" -#endif - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/** - * @brief Type of an area to be initialized. - */ -typedef struct { - uint32_t *init_text_area; - uint32_t *init_area; - uint32_t *clear_area; - uint32_t *no_init_area; -} ram_init_area_t; - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -#if (CRT1_AREAS_NUMBER > 0) || defined(__DOXYGEN__) -extern uint32_t __ram0_init_text__, __ram0_init__, __ram0_clear__, __ram0_noinit__; -#endif -#if (CRT1_AREAS_NUMBER > 1) || defined(__DOXYGEN__) -extern uint32_t __ram1_init_text__, __ram1_init__, __ram1_clear__, __ram1_noinit__; -#endif -#if (CRT1_AREAS_NUMBER > 2) || defined(__DOXYGEN__) -extern uint32_t __ram2_init_text__, __ram2_init__, __ram2_clear__, __ram2_noinit__; -#endif -#if (CRT1_AREAS_NUMBER > 3) || defined(__DOXYGEN__) -extern uint32_t __ram3_init_text__, __ram3_init__, __ram3_clear__, __ram3_noinit__; -#endif -#if (CRT1_AREAS_NUMBER > 4) || defined(__DOXYGEN__) -extern uint32_t __ram4_init_text__, __ram4_init__, __ram4_clear__, __ram4_noinit__; -#endif -#if (CRT1_AREAS_NUMBER > 5) || defined(__DOXYGEN__) -extern uint32_t __ram5_init_text__, __ram5_init__, __ram5_clear__, __ram5_noinit__; -#endif -#if (CRT1_AREAS_NUMBER > 6) || defined(__DOXYGEN__) -extern uint32_t __ram6_init_text__, __ram6_init__, __ram6_clear__, __ram6_noinit__; -#endif -#if (CRT1_AREAS_NUMBER > 7) || defined(__DOXYGEN__) -extern uint32_t __ram7_init_text__, __ram7_init__, __ram7_clear__, __ram7_noinit__; -#endif - -/** - * @brief Static table of areas to be initialized. - */ -#if (CRT1_AREAS_NUMBER > 0) || defined(__DOXYGEN__) -static const ram_init_area_t ram_areas[CRT1_AREAS_NUMBER] = { - {&__ram0_init_text__, &__ram0_init__, &__ram0_clear__, &__ram0_noinit__}, -#if (CRT1_AREAS_NUMBER > 1) || defined(__DOXYGEN__) - {&__ram1_init_text__, &__ram1_init__, &__ram1_clear__, &__ram1_noinit__}, -#endif -#if (CRT1_AREAS_NUMBER > 2) || defined(__DOXYGEN__) - {&__ram2_init_text__, &__ram2_init__, &__ram2_clear__, &__ram2_noinit__}, -#endif -#if (CRT1_AREAS_NUMBER > 3) || defined(__DOXYGEN__) - {&__ram3_init_text__, &__ram3_init__, &__ram3_clear__, &__ram3_noinit__}, -#endif -#if (CRT1_AREAS_NUMBER > 4) || defined(__DOXYGEN__) - {&__ram4_init_text__, &__ram4_init__, &__ram4_clear__, &__ram4_noinit__}, -#endif -#if (CRT1_AREAS_NUMBER > 5) || defined(__DOXYGEN__) - {&__ram5_init_text__, &__ram5_init__, &__ram5_clear__, &__ram5_noinit__}, -#endif -#if (CRT1_AREAS_NUMBER > 6) || defined(__DOXYGEN__) - {&__ram6_init_text__, &__ram6_init__, &__ram6_clear__, &__ram6_noinit__}, -#endif -#if (CRT1_AREAS_NUMBER > 7) || defined(__DOXYGEN__) - {&__ram7_init_text__, &__ram7_init__, &__ram7_clear__, &__ram7_noinit__}, -#endif -}; -#endif - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -/** - * @brief Architecture-dependent core initialization. - * @details This hook is invoked immediately after the stack initialization - * and before the DATA and BSS segments initialization. - * @note This function is a weak symbol. - */ -#if !defined(__DOXYGEN__) -__attribute__((weak)) -#endif -/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/ -void __core_init(void) { - -#if __CORTEX_M == 7 - SCB_EnableICache(); - SCB_EnableDCache(); -#endif -} - -/** - * @brief Early initialization. - * @details This hook is invoked immediately after the stack and core - * initialization and before the DATA and BSS segments - * initialization. - * @note This function is a weak symbol. - */ -#if !defined(__DOXYGEN__) -__attribute__((weak)) -#endif -/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/ -void __early_init(void) {} -/*lint -restore*/ - -/** - * @brief Late initialization. - * @details This hook is invoked after the DATA and BSS segments - * initialization and before any static constructor. The - * default behavior is to do nothing. - * @note This function is a weak symbol. - */ -#if !defined(__DOXYGEN__) -__attribute__((weak)) -#endif -/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/ -void __late_init(void) {} -/*lint -restore*/ - -/** - * @brief Default @p main() function exit handler. - * @details This handler is invoked or the @p main() function exit. The - * default behavior is to enter an infinite loop. - * @note This function is a weak symbol. - */ -#if !defined(__DOXYGEN__) -__attribute__((noreturn, weak)) -#endif -/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/ -void __default_exit(void) { -/*lint -restore*/ - - while (true) { - } -} - -/** - * @brief Performs the initialization of the various RAM areas. - */ -void __init_ram_areas(void) { -#if CRT1_AREAS_NUMBER > 0 - const ram_init_area_t *rap = ram_areas; - - do { - uint32_t *tp = rap->init_text_area; - uint32_t *p = rap->init_area; - - /* Copying initialization data.*/ - while (p < rap->clear_area) { - *p = *tp; - p++; - tp++; - } - - /* Zeroing clear area.*/ - while (p < rap->no_init_area) { - *p = 0; - p++; - } - rap++; - } - while (rap < &ram_areas[CRT1_AREAS_NUMBER]); -#endif -} - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/KL25Z128.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/KL25Z128.ld deleted file mode 100644 index ed38a46e64..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/KL25Z128.ld +++ /dev/null @@ -1,389 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * KL25Z128 memory setup. - */ -MEMORY -{ - flash0 : org = 0x00000000, len = 0x100 - flashcfg : org = 0x00000400, len = 0x10 - flash : org = 0x00000410, len = 128k - 0x410 - ram0 : org = 0x1FFFF000, len = 16k - ram1 : org = 0x00000000, len = 0 - ram2 : org = 0x00000000, len = 0 - ram3 : org = 0x00000000, len = 0 - ram4 : org = 0x00000000, len = 0 - ram5 : org = 0x00000000, len = 0 - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -REGION_ALIAS("MAIN_STACK_RAM", ram0); -REGION_ALIAS("PROCESS_STACK_RAM", ram0); -REGION_ALIAS("DATA_RAM", ram0); -REGION_ALIAS("BSS_RAM", ram0); -REGION_ALIAS("HEAP_RAM", ram0); - -__ram0_start__ = ORIGIN(ram0); -__ram0_size__ = LENGTH(ram0); -__ram0_end__ = __ram0_start__ + __ram0_size__; -__ram1_start__ = ORIGIN(ram1); -__ram1_size__ = LENGTH(ram1); -__ram1_end__ = __ram1_start__ + __ram1_size__; -__ram2_start__ = ORIGIN(ram2); -__ram2_size__ = LENGTH(ram2); -__ram2_end__ = __ram2_start__ + __ram2_size__; -__ram3_start__ = ORIGIN(ram3); -__ram3_size__ = LENGTH(ram3); -__ram3_end__ = __ram3_start__ + __ram3_size__; -__ram4_start__ = ORIGIN(ram4); -__ram4_size__ = LENGTH(ram4); -__ram4_end__ = __ram4_start__ + __ram4_size__; -__ram5_start__ = ORIGIN(ram5); -__ram5_size__ = LENGTH(ram5); -__ram5_end__ = __ram5_start__ + __ram5_size__; -__ram6_start__ = ORIGIN(ram6); -__ram6_size__ = LENGTH(ram6); -__ram6_end__ = __ram6_start__ + __ram6_size__; -__ram7_start__ = ORIGIN(ram7); -__ram7_size__ = LENGTH(ram7); -__ram7_end__ = __ram7_start__ + __ram7_size__; - -ENTRY(Reset_Handler) - -SECTIONS -{ - . = 0; - - startup : ALIGN(16) SUBALIGN(16) - { - KEEP(*(.vectors)) - } > flash0 - - .cfmprotect : ALIGN(4) SUBALIGN(4) - { - KEEP(*(.cfmconfig)) - } > flashcfg - - _text = .; - - constructors : ALIGN(4) SUBALIGN(4) - { - __init_array_start = .; - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - __init_array_end = .; - } > flash - - destructors : ALIGN(4) SUBALIGN(4) - { - __fini_array_start = .; - KEEP(*(.fini_array)) - KEEP(*(SORT(.fini_array.*))) - __fini_array_end = .; - } > flash - - .text : ALIGN(16) SUBALIGN(16) - { - *(.text) - *(.text.*) - *(.rodata) - *(.rodata.*) - *(.glue_7t) - *(.glue_7) - *(.gcc*) - } > flash - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > flash - - .ARM.exidx : { - __exidx_start = .; - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - __exidx_end = .; - } > flash - - .eh_frame_hdr : - { - *(.eh_frame_hdr) - } > flash - - .eh_frame : ONLY_IF_RO - { - *(.eh_frame) - } > flash - - .textalign : ONLY_IF_RO - { - . = ALIGN(8); - } > flash - - /* Legacy symbol, not used anywhere.*/ - . = ALIGN(4); - PROVIDE(_etext = .); - - /* Special section for exceptions stack.*/ - .mstack : - { - . = ALIGN(8); - __main_stack_base__ = .; - . += __main_stack_size__; - . = ALIGN(8); - __main_stack_end__ = .; - } > MAIN_STACK_RAM - - /* Special section for process stack.*/ - .pstack : - { - __process_stack_base__ = .; - __main_thread_stack_base__ = .; - . += __process_stack_size__; - . = ALIGN(8); - __process_stack_end__ = .; - __main_thread_stack_end__ = .; - } > PROCESS_STACK_RAM - - .data : ALIGN(4) - { - . = ALIGN(4); - PROVIDE(_textdata = LOADADDR(.data)); - PROVIDE(_data = .); - _textdata_start = LOADADDR(.data); - _data_start = .; - *(.data) - *(.data.*) - *(.ramtext) - . = ALIGN(4); - PROVIDE(_edata = .); - _data_end = .; - } > DATA_RAM AT > flash - - .bss (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - _bss_start = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - _bss_end = .; - PROVIDE(end = .); - } > BSS_RAM - - .ram0_init : ALIGN(4) - { - . = ALIGN(4); - __ram0_init_text__ = LOADADDR(.ram0_init); - __ram0_init__ = .; - *(.ram0_init) - *(.ram0_init.*) - . = ALIGN(4); - } > ram0 AT > flash - - .ram0 (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - __ram0_clear__ = .; - *(.ram0_clear) - *(.ram0_clear.*) - . = ALIGN(4); - __ram0_noinit__ = .; - *(.ram0) - *(.ram0.*) - . = ALIGN(4); - __ram0_free__ = .; - } > ram0 - - .ram1_init : ALIGN(4) - { - . = ALIGN(4); - __ram1_init_text__ = LOADADDR(.ram1_init); - __ram1_init__ = .; - *(.ram1_init) - *(.ram1_init.*) - . = ALIGN(4); - } > ram1 AT > flash - - .ram1 (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - __ram1_clear__ = .; - *(.ram1_clear) - *(.ram1_clear.*) - . = ALIGN(4); - __ram1_noinit__ = .; - *(.ram1) - *(.ram1.*) - . = ALIGN(4); - __ram1_free__ = .; - } > ram1 - - .ram2_init : ALIGN(4) - { - . = ALIGN(4); - __ram2_init_text__ = LOADADDR(.ram2_init); - __ram2_init__ = .; - *(.ram2_init) - *(.ram2_init.*) - . = ALIGN(4); - } > ram2 AT > flash - - .ram2 (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - __ram2_clear__ = .; - *(.ram2_clear) - *(.ram2_clear.*) - . = ALIGN(4); - __ram2_noinit__ = .; - *(.ram2) - *(.ram2.*) - . = ALIGN(4); - __ram2_free__ = .; - } > ram2 - - .ram3_init : ALIGN(4) - { - . = ALIGN(4); - __ram3_init_text__ = LOADADDR(.ram3_init); - __ram3_init__ = .; - *(.ram3_init) - *(.ram3_init.*) - . = ALIGN(4); - } > ram3 AT > flash - - .ram3 (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - __ram3_clear__ = .; - *(.ram3_clear) - *(.ram3_clear.*) - . = ALIGN(4); - __ram3_noinit__ = .; - *(.ram3) - *(.ram3.*) - . = ALIGN(4); - __ram3_free__ = .; - } > ram3 - - .ram4_init : ALIGN(4) - { - . = ALIGN(4); - __ram4_init_text__ = LOADADDR(.ram4_init); - __ram4_init__ = .; - *(.ram4_init) - *(.ram4_init.*) - . = ALIGN(4); - } > ram4 AT > flash - - .ram4 (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - __ram4_clear__ = .; - *(.ram4_clear) - *(.ram4_clear.*) - . = ALIGN(4); - __ram4_noinit__ = .; - *(.ram4) - *(.ram4.*) - . = ALIGN(4); - __ram4_free__ = .; - } > ram4 - - .ram5_init : ALIGN(4) - { - . = ALIGN(4); - __ram5_init_text__ = LOADADDR(.ram5_init); - __ram5_init__ = .; - *(.ram5_init) - *(.ram5_init.*) - . = ALIGN(4); - } > ram5 AT > flash - - .ram5 (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - __ram5_clear__ = .; - *(.ram5_clear) - *(.ram5_clear.*) - . = ALIGN(4); - __ram5_noinit__ = .; - *(.ram5) - *(.ram5.*) - . = ALIGN(4); - __ram5_free__ = .; - } > ram5 - - .ram6_init : ALIGN(4) - { - . = ALIGN(4); - __ram6_init_text__ = LOADADDR(.ram6_init); - __ram6_init__ = .; - *(.ram6_init) - *(.ram6_init.*) - . = ALIGN(4); - } > ram6 AT > flash - - .ram6 (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - __ram6_clear__ = .; - *(.ram6_clear) - *(.ram6_clear.*) - . = ALIGN(4); - __ram6_noinit__ = .; - *(.ram6) - *(.ram6.*) - . = ALIGN(4); - __ram6_free__ = .; - } > ram6 - - .ram7_init : ALIGN(4) - { - . = ALIGN(4); - __ram7_init_text__ = LOADADDR(.ram7_init); - __ram7_init__ = .; - *(.ram7_init) - *(.ram7_init.*) - . = ALIGN(4); - } > ram7 AT > flash - - .ram7 (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - __ram7_clear__ = .; - *(.ram7_clear) - *(.ram7_clear.*) - . = ALIGN(4); - __ram7_noinit__ = .; - *(.ram7) - *(.ram7.*) - . = ALIGN(4); - __ram7_free__ = .; - } > ram7 - - /* The default heap uses the (statically) unused part of a RAM section.*/ - .heap (NOLOAD) : - { - . = ALIGN(8); - __heap_base__ = .; - . = ORIGIN(HEAP_RAM) + LENGTH(HEAP_RAM); - __heap_end__ = .; - } > HEAP_RAM -} diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/MK20DX128.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/MK20DX128.ld deleted file mode 100644 index 58ed66cfe3..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/MK20DX128.ld +++ /dev/null @@ -1,389 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * MK20DX128 memory setup. - */ -MEMORY -{ - flash0 : org = 0x00000000, len = 0x100 - flashcfg : org = 0x00000400, len = 0x10 - flash : org = 0x00000410, len = 128k - 0x410 - ram0 : org = 0x1fffe000, len = 16k - ram1 : org = 0x00000000, len = 0 - ram2 : org = 0x00000000, len = 0 - ram3 : org = 0x00000000, len = 0 - ram4 : org = 0x00000000, len = 0 - ram5 : org = 0x00000000, len = 0 - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -REGION_ALIAS("MAIN_STACK_RAM", ram0); -REGION_ALIAS("PROCESS_STACK_RAM", ram0); -REGION_ALIAS("DATA_RAM", ram0); -REGION_ALIAS("BSS_RAM", ram0); -REGION_ALIAS("HEAP_RAM", ram0); - -__ram0_start__ = ORIGIN(ram0); -__ram0_size__ = LENGTH(ram0); -__ram0_end__ = __ram0_start__ + __ram0_size__; -__ram1_start__ = ORIGIN(ram1); -__ram1_size__ = LENGTH(ram1); -__ram1_end__ = __ram1_start__ + __ram1_size__; -__ram2_start__ = ORIGIN(ram2); -__ram2_size__ = LENGTH(ram2); -__ram2_end__ = __ram2_start__ + __ram2_size__; -__ram3_start__ = ORIGIN(ram3); -__ram3_size__ = LENGTH(ram3); -__ram3_end__ = __ram3_start__ + __ram3_size__; -__ram4_start__ = ORIGIN(ram4); -__ram4_size__ = LENGTH(ram4); -__ram4_end__ = __ram4_start__ + __ram4_size__; -__ram5_start__ = ORIGIN(ram5); -__ram5_size__ = LENGTH(ram5); -__ram5_end__ = __ram5_start__ + __ram5_size__; -__ram6_start__ = ORIGIN(ram6); -__ram6_size__ = LENGTH(ram6); -__ram6_end__ = __ram6_start__ + __ram6_size__; -__ram7_start__ = ORIGIN(ram7); -__ram7_size__ = LENGTH(ram7); -__ram7_end__ = __ram7_start__ + __ram7_size__; - -ENTRY(Reset_Handler) - -SECTIONS -{ - . = 0; - - startup : ALIGN(16) SUBALIGN(16) - { - KEEP(*(.vectors)) - } > flash0 - - .cfmprotect : ALIGN(4) SUBALIGN(4) - { - KEEP(*(.cfmconfig)) - } > flashcfg - - _text = .; - - constructors : ALIGN(4) SUBALIGN(4) - { - __init_array_start = .; - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - __init_array_end = .; - } > flash - - destructors : ALIGN(4) SUBALIGN(4) - { - __fini_array_start = .; - KEEP(*(.fini_array)) - KEEP(*(SORT(.fini_array.*))) - __fini_array_end = .; - } > flash - - .text : ALIGN(16) SUBALIGN(16) - { - *(.text) - *(.text.*) - *(.rodata) - *(.rodata.*) - *(.glue_7t) - *(.glue_7) - *(.gcc*) - } > flash - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > flash - - .ARM.exidx : { - __exidx_start = .; - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - __exidx_end = .; - } > flash - - .eh_frame_hdr : - { - *(.eh_frame_hdr) - } > flash - - .eh_frame : ONLY_IF_RO - { - *(.eh_frame) - } > flash - - .textalign : ONLY_IF_RO - { - . = ALIGN(8); - } > flash - - /* Legacy symbol, not used anywhere.*/ - . = ALIGN(4); - PROVIDE(_etext = .); - - /* Special section for exceptions stack.*/ - .mstack : - { - . = ALIGN(8); - __main_stack_base__ = .; - . += __main_stack_size__; - . = ALIGN(8); - __main_stack_end__ = .; - } > MAIN_STACK_RAM - - /* Special section for process stack.*/ - .pstack : - { - __process_stack_base__ = .; - __main_thread_stack_base__ = .; - . += __process_stack_size__; - . = ALIGN(8); - __process_stack_end__ = .; - __main_thread_stack_end__ = .; - } > PROCESS_STACK_RAM - - .data : ALIGN(4) - { - . = ALIGN(4); - PROVIDE(_textdata = LOADADDR(.data)); - PROVIDE(_data = .); - _textdata_start = LOADADDR(.data); - _data_start = .; - *(.data) - *(.data.*) - *(.ramtext) - . = ALIGN(4); - PROVIDE(_edata = .); - _data_end = .; - } > DATA_RAM AT > flash - - .bss (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - _bss_start = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - _bss_end = .; - PROVIDE(end = .); - } > BSS_RAM - - .ram0_init : ALIGN(4) - { - . = ALIGN(4); - __ram0_init_text__ = LOADADDR(.ram0_init); - __ram0_init__ = .; - *(.ram0_init) - *(.ram0_init.*) - . = ALIGN(4); - } > ram0 AT > flash - - .ram0 (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - __ram0_clear__ = .; - *(.ram0_clear) - *(.ram0_clear.*) - . = ALIGN(4); - __ram0_noinit__ = .; - *(.ram0) - *(.ram0.*) - . = ALIGN(4); - __ram0_free__ = .; - } > ram0 - - .ram1_init : ALIGN(4) - { - . = ALIGN(4); - __ram1_init_text__ = LOADADDR(.ram1_init); - __ram1_init__ = .; - *(.ram1_init) - *(.ram1_init.*) - . = ALIGN(4); - } > ram1 AT > flash - - .ram1 (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - __ram1_clear__ = .; - *(.ram1_clear) - *(.ram1_clear.*) - . = ALIGN(4); - __ram1_noinit__ = .; - *(.ram1) - *(.ram1.*) - . = ALIGN(4); - __ram1_free__ = .; - } > ram1 - - .ram2_init : ALIGN(4) - { - . = ALIGN(4); - __ram2_init_text__ = LOADADDR(.ram2_init); - __ram2_init__ = .; - *(.ram2_init) - *(.ram2_init.*) - . = ALIGN(4); - } > ram2 AT > flash - - .ram2 (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - __ram2_clear__ = .; - *(.ram2_clear) - *(.ram2_clear.*) - . = ALIGN(4); - __ram2_noinit__ = .; - *(.ram2) - *(.ram2.*) - . = ALIGN(4); - __ram2_free__ = .; - } > ram2 - - .ram3_init : ALIGN(4) - { - . = ALIGN(4); - __ram3_init_text__ = LOADADDR(.ram3_init); - __ram3_init__ = .; - *(.ram3_init) - *(.ram3_init.*) - . = ALIGN(4); - } > ram3 AT > flash - - .ram3 (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - __ram3_clear__ = .; - *(.ram3_clear) - *(.ram3_clear.*) - . = ALIGN(4); - __ram3_noinit__ = .; - *(.ram3) - *(.ram3.*) - . = ALIGN(4); - __ram3_free__ = .; - } > ram3 - - .ram4_init : ALIGN(4) - { - . = ALIGN(4); - __ram4_init_text__ = LOADADDR(.ram4_init); - __ram4_init__ = .; - *(.ram4_init) - *(.ram4_init.*) - . = ALIGN(4); - } > ram4 AT > flash - - .ram4 (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - __ram4_clear__ = .; - *(.ram4_clear) - *(.ram4_clear.*) - . = ALIGN(4); - __ram4_noinit__ = .; - *(.ram4) - *(.ram4.*) - . = ALIGN(4); - __ram4_free__ = .; - } > ram4 - - .ram5_init : ALIGN(4) - { - . = ALIGN(4); - __ram5_init_text__ = LOADADDR(.ram5_init); - __ram5_init__ = .; - *(.ram5_init) - *(.ram5_init.*) - . = ALIGN(4); - } > ram5 AT > flash - - .ram5 (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - __ram5_clear__ = .; - *(.ram5_clear) - *(.ram5_clear.*) - . = ALIGN(4); - __ram5_noinit__ = .; - *(.ram5) - *(.ram5.*) - . = ALIGN(4); - __ram5_free__ = .; - } > ram5 - - .ram6_init : ALIGN(4) - { - . = ALIGN(4); - __ram6_init_text__ = LOADADDR(.ram6_init); - __ram6_init__ = .; - *(.ram6_init) - *(.ram6_init.*) - . = ALIGN(4); - } > ram6 AT > flash - - .ram6 (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - __ram6_clear__ = .; - *(.ram6_clear) - *(.ram6_clear.*) - . = ALIGN(4); - __ram6_noinit__ = .; - *(.ram6) - *(.ram6.*) - . = ALIGN(4); - __ram6_free__ = .; - } > ram6 - - .ram7_init : ALIGN(4) - { - . = ALIGN(4); - __ram7_init_text__ = LOADADDR(.ram7_init); - __ram7_init__ = .; - *(.ram7_init) - *(.ram7_init.*) - . = ALIGN(4); - } > ram7 AT > flash - - .ram7 (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - __ram7_clear__ = .; - *(.ram7_clear) - *(.ram7_clear.*) - . = ALIGN(4); - __ram7_noinit__ = .; - *(.ram7) - *(.ram7.*) - . = ALIGN(4); - __ram7_free__ = .; - } > ram7 - - /* The default heap uses the (statically) unused part of a RAM section.*/ - .heap (NOLOAD) : - { - . = ALIGN(8); - __heap_base__ = .; - . = ORIGIN(HEAP_RAM) + LENGTH(HEAP_RAM); - __heap_end__ = .; - } > HEAP_RAM -} diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F030x4.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F030x4.ld deleted file mode 100644 index b4b7c98900..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F030x4.ld +++ /dev/null @@ -1,50 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * STM32F030x4 memory setup. - */ -MEMORY -{ - flash : org = 0x08000000, len = 16k - ram0 : org = 0x20000000, len = 4k - ram1 : org = 0x00000000, len = 0 - ram2 : org = 0x00000000, len = 0 - ram3 : org = 0x00000000, len = 0 - ram4 : org = 0x00000000, len = 0 - ram5 : org = 0x00000000, len = 0 - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -INCLUDE rules.ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F030x6.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F030x6.ld deleted file mode 100644 index 79a4f2a44e..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F030x6.ld +++ /dev/null @@ -1,50 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * STM32F030x6 memory setup. - */ -MEMORY -{ - flash : org = 0x08000000, len = 32k - ram0 : org = 0x20000000, len = 4k - ram1 : org = 0x00000000, len = 0 - ram2 : org = 0x00000000, len = 0 - ram3 : org = 0x00000000, len = 0 - ram4 : org = 0x00000000, len = 0 - ram5 : org = 0x00000000, len = 0 - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -INCLUDE rules.ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F030x8.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F030x8.ld deleted file mode 100644 index 24386eb762..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F030x8.ld +++ /dev/null @@ -1,50 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * STM32F030x8 memory setup. - */ -MEMORY -{ - flash : org = 0x08000000, len = 64k - ram0 : org = 0x20000000, len = 8k - ram1 : org = 0x00000000, len = 0 - ram2 : org = 0x00000000, len = 0 - ram3 : org = 0x00000000, len = 0 - ram4 : org = 0x00000000, len = 0 - ram5 : org = 0x00000000, len = 0 - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -INCLUDE rules.ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F031x6.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F031x6.ld deleted file mode 100644 index b18e6285c6..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F031x6.ld +++ /dev/null @@ -1,50 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * STM32F031x6 memory setup. - */ -MEMORY -{ - flash : org = 0x08000000, len = 32k - ram0 : org = 0x20000000, len = 4k - ram1 : org = 0x00000000, len = 0 - ram2 : org = 0x00000000, len = 0 - ram3 : org = 0x00000000, len = 0 - ram4 : org = 0x00000000, len = 0 - ram5 : org = 0x00000000, len = 0 - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -INCLUDE rules.ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F042x6.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F042x6.ld deleted file mode 100644 index e44a190d38..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F042x6.ld +++ /dev/null @@ -1,50 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * STM32F042x6 memory setup. - */ -MEMORY -{ - flash : org = 0x08000000, len = 32k - ram0 : org = 0x20000000, len = 6k - ram1 : org = 0x00000000, len = 0 - ram2 : org = 0x00000000, len = 0 - ram3 : org = 0x00000000, len = 0 - ram4 : org = 0x00000000, len = 0 - ram5 : org = 0x00000000, len = 0 - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -INCLUDE rules.ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F051x8.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F051x8.ld deleted file mode 100644 index 36e32edffe..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F051x8.ld +++ /dev/null @@ -1,50 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * STM32F051x8 memory setup. - */ -MEMORY -{ - flash : org = 0x08000000, len = 64k - ram0 : org = 0x20000000, len = 8k - ram1 : org = 0x00000000, len = 0 - ram2 : org = 0x00000000, len = 0 - ram3 : org = 0x00000000, len = 0 - ram4 : org = 0x00000000, len = 0 - ram5 : org = 0x00000000, len = 0 - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -INCLUDE rules.ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F072xB.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F072xB.ld deleted file mode 100644 index 9abd3db4ae..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F072xB.ld +++ /dev/null @@ -1,50 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * STM32F072xB memory setup. - */ -MEMORY -{ - flash : org = 0x08000000, len = 128k - ram0 : org = 0x20000000, len = 16k - ram1 : org = 0x00000000, len = 0 - ram2 : org = 0x00000000, len = 0 - ram3 : org = 0x00000000, len = 0 - ram4 : org = 0x00000000, len = 0 - ram5 : org = 0x00000000, len = 0 - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -INCLUDE rules.ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F091xC.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F091xC.ld deleted file mode 100644 index e82bf9795f..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F091xC.ld +++ /dev/null @@ -1,50 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * STM32F091xC memory setup. - */ -MEMORY -{ - flash : org = 0x08000000, len = 256k - ram0 : org = 0x20000000, len = 32k - ram1 : org = 0x00000000, len = 0 - ram2 : org = 0x00000000, len = 0 - ram3 : org = 0x00000000, len = 0 - ram4 : org = 0x00000000, len = 0 - ram5 : org = 0x00000000, len = 0 - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -INCLUDE rules.ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F100xB.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F100xB.ld deleted file mode 100644 index 980905b61a..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F100xB.ld +++ /dev/null @@ -1,50 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * ST32F100xB memory setup. - */ -MEMORY -{ - flash : org = 0x08000000, len = 128k - ram0 : org = 0x20000000, len = 8k - ram1 : org = 0x00000000, len = 0 - ram2 : org = 0x00000000, len = 0 - ram3 : org = 0x00000000, len = 0 - ram4 : org = 0x00000000, len = 0 - ram5 : org = 0x00000000, len = 0 - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -INCLUDE rules.ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103x8.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103x8.ld deleted file mode 100644 index 66288a2012..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103x8.ld +++ /dev/null @@ -1,50 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * ST32F103x8 memory setup. - */ -MEMORY -{ - flash : org = 0x08000000, len = 64k - ram0 : org = 0x20000000, len = 20k - ram1 : org = 0x00000000, len = 0 - ram2 : org = 0x00000000, len = 0 - ram3 : org = 0x00000000, len = 0 - ram4 : org = 0x00000000, len = 0 - ram5 : org = 0x00000000, len = 0 - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -INCLUDE rules.ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xB.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xB.ld deleted file mode 100644 index 8ec861b8d5..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xB.ld +++ /dev/null @@ -1,50 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * ST32F103xB memory setup. - */ -MEMORY -{ - flash : org = 0x08000000, len = 128k - ram0 : org = 0x20000000, len = 20k - ram1 : org = 0x00000000, len = 0 - ram2 : org = 0x00000000, len = 0 - ram3 : org = 0x00000000, len = 0 - ram4 : org = 0x00000000, len = 0 - ram5 : org = 0x00000000, len = 0 - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -INCLUDE rules.ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xD.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xD.ld deleted file mode 100644 index f1e906d26d..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xD.ld +++ /dev/null @@ -1,50 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * ST32F103xE memory setup. - */ -MEMORY -{ - flash : org = 0x08000000, len = 384k - ram0 : org = 0x20000000, len = 64k - ram1 : org = 0x00000000, len = 0 - ram2 : org = 0x00000000, len = 0 - ram3 : org = 0x00000000, len = 0 - ram4 : org = 0x00000000, len = 0 - ram5 : org = 0x00000000, len = 0 - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -INCLUDE rules.ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xE.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xE.ld deleted file mode 100644 index e7ec5681ea..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xE.ld +++ /dev/null @@ -1,50 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * ST32F103xE memory setup. - */ -MEMORY -{ - flash : org = 0x08000000, len = 512k - ram0 : org = 0x20000000, len = 64k - ram1 : org = 0x00000000, len = 0 - ram2 : org = 0x00000000, len = 0 - ram3 : org = 0x00000000, len = 0 - ram4 : org = 0x00000000, len = 0 - ram5 : org = 0x00000000, len = 0 - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -INCLUDE rules.ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xE_maplemini_bootloader.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xE_maplemini_bootloader.ld deleted file mode 100644 index f9378ad80e..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xE_maplemini_bootloader.ld +++ /dev/null @@ -1,53 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * ST32F103xE memory setup for use with the maplemini bootloader. - * You will have to - * #define CORTEX_VTOR_INIT 0x5000 - * in your projects chconf.h - */ -MEMORY -{ - flash : org = 0x08005000, len = 512k - 0x5000 - ram0 : org = 0x20000C00, len = 64k - 0xC00 - ram1 : org = 0x00000000, len = 0 - ram2 : org = 0x00000000, len = 0 - ram3 : org = 0x00000000, len = 0 - ram4 : org = 0x00000000, len = 0 - ram5 : org = 0x00000000, len = 0 - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -INCLUDE rules.ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xG.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xG.ld deleted file mode 100644 index ed0c2e5d3c..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xG.ld +++ /dev/null @@ -1,50 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * ST32F103xG memory setup. - */ -MEMORY -{ - flash : org = 0x08000000, len = 1m - ram0 : org = 0x20000000, len = 96k - ram1 : org = 0x00000000, len = 0 - ram2 : org = 0x00000000, len = 0 - ram3 : org = 0x00000000, len = 0 - ram4 : org = 0x00000000, len = 0 - ram5 : org = 0x00000000, len = 0 - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -INCLUDE rules.ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F107xC.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F107xC.ld deleted file mode 100644 index 3d5e06b992..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F107xC.ld +++ /dev/null @@ -1,50 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * ST32F107xC memory setup. - */ -MEMORY -{ - flash : org = 0x08000000, len = 256k - ram0 : org = 0x20000000, len = 64k - ram1 : org = 0x00000000, len = 0 - ram2 : org = 0x00000000, len = 0 - ram3 : org = 0x00000000, len = 0 - ram4 : org = 0x00000000, len = 0 - ram5 : org = 0x00000000, len = 0 - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -INCLUDE rules.ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F207xG.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F207xG.ld deleted file mode 100644 index 5dfef0d562..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F207xG.ld +++ /dev/null @@ -1,51 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * STM32F207xG memory setup. - * Note: Use of ram1 and ram2 is mutually exclusive with use of ram0. - */ -MEMORY -{ - flash : org = 0x08000000, len = 1M - ram0 : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */ - ram1 : org = 0x20000000, len = 112k /* SRAM1 */ - ram2 : org = 0x2001C000, len = 16k /* SRAM2 */ - ram3 : org = 0x00000000, len = 0 - ram4 : org = 0x10000000, len = 64k /* CCM SRAM */ - ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -INCLUDE rules.ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F302x8.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F302x8.ld deleted file mode 100644 index 78fa31bb97..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F302x8.ld +++ /dev/null @@ -1,50 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * STM32F302x8 memory setup. - */ -MEMORY -{ - flash : org = 0x08000000, len = 64k - ram0 : org = 0x20000000, len = 16k - ram1 : org = 0x00000000, len = 0 - ram2 : org = 0x00000000, len = 0 - ram3 : org = 0x00000000, len = 0 - ram4 : org = 0x00000000, len = 0 - ram5 : org = 0x00000000, len = 0 - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -INCLUDE rules.ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F303x8.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F303x8.ld deleted file mode 100644 index 3bce18ec69..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F303x8.ld +++ /dev/null @@ -1,50 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * STM32F303x8 memory setup. - */ -MEMORY -{ - flash : org = 0x08000000, len = 64k - ram0 : org = 0x20000000, len = 12k - ram1 : org = 0x00000000, len = 0 - ram2 : org = 0x00000000, len = 0 - ram3 : org = 0x00000000, len = 0 - ram4 : org = 0x10000000, len = 4k - ram5 : org = 0x00000000, len = 0 - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -INCLUDE rules.ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F303xC.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F303xC.ld deleted file mode 100644 index ab03761223..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F303xC.ld +++ /dev/null @@ -1,50 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * STM32F303xC memory setup. - */ -MEMORY -{ - flash : org = 0x08000000, len = 256k - ram0 : org = 0x20000000, len = 40k - ram1 : org = 0x00000000, len = 0 - ram2 : org = 0x00000000, len = 0 - ram3 : org = 0x00000000, len = 0 - ram4 : org = 0x10000000, len = 8k - ram5 : org = 0x00000000, len = 0 - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -INCLUDE rules.ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F334x8.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F334x8.ld deleted file mode 100644 index 89fb9fcfe5..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F334x8.ld +++ /dev/null @@ -1,50 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * STM32F3334x8 memory setup. - */ -MEMORY -{ - flash : org = 0x08000000, len = 64k - ram0 : org = 0x20000000, len = 12k - ram1 : org = 0x00000000, len = 0 - ram2 : org = 0x00000000, len = 0 - ram3 : org = 0x00000000, len = 0 - ram4 : org = 0x10000000, len = 4k - ram5 : org = 0x00000000, len = 0 - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -INCLUDE rules.ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F373xC.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F373xC.ld deleted file mode 100644 index b94b8e0747..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F373xC.ld +++ /dev/null @@ -1,50 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * STM32F373xC memory setup. - */ -MEMORY -{ - flash : org = 0x08000000, len = 256k - ram0 : org = 0x20000000, len = 32k - ram1 : org = 0x00000000, len = 0 - ram2 : org = 0x00000000, len = 0 - ram3 : org = 0x00000000, len = 0 - ram4 : org = 0x00000000, len = 0 - ram5 : org = 0x00000000, len = 0 - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -INCLUDE rules.ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F401xC.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F401xC.ld deleted file mode 100644 index 54db265f5e..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F401xC.ld +++ /dev/null @@ -1,50 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * STM32F401xC memory setup. - */ -MEMORY -{ - flash : org = 0x08000000, len = 256k - ram0 : org = 0x20000000, len = 64k - ram1 : org = 0x00000000, len = 0 - ram2 : org = 0x00000000, len = 0 - ram3 : org = 0x00000000, len = 0 - ram4 : org = 0x00000000, len = 0 - ram5 : org = 0x00000000, len = 0 - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -INCLUDE rules.ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F401xE.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F401xE.ld deleted file mode 100644 index 103238fe49..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F401xE.ld +++ /dev/null @@ -1,50 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * STM32F401xE memory setup. - */ -MEMORY -{ - flash : org = 0x08000000, len = 512k - ram0 : org = 0x20000000, len = 96k - ram1 : org = 0x00000000, len = 0 - ram2 : org = 0x00000000, len = 0 - ram3 : org = 0x00000000, len = 0 - ram4 : org = 0x00000000, len = 0 - ram5 : org = 0x00000000, len = 0 - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -INCLUDE rules.ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F405xG.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F405xG.ld deleted file mode 100644 index 83dffac690..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F405xG.ld +++ /dev/null @@ -1,50 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * STM32F405xG memory setup. - */ -MEMORY -{ - flash : org = 0x08000000, len = 1M - ram0 : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */ - ram1 : org = 0x20000000, len = 112k /* SRAM1 */ - ram2 : org = 0x2001C000, len = 16k /* SRAM2 */ - ram3 : org = 0x00000000, len = 0 - ram4 : org = 0x10000000, len = 64k /* CCM SRAM */ - ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -INCLUDE rules.ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F407xG.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F407xG.ld deleted file mode 100644 index dc92cea9e4..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F407xG.ld +++ /dev/null @@ -1,51 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * STM32F407xG memory setup. - * Note: Use of ram1 and ram2 is mutually exclusive with use of ram0. - */ -MEMORY -{ - flash : org = 0x08000000, len = 1M - ram0 : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */ - ram1 : org = 0x20000000, len = 112k /* SRAM1 */ - ram2 : org = 0x2001C000, len = 16k /* SRAM2 */ - ram3 : org = 0x00000000, len = 0 - ram4 : org = 0x10000000, len = 64k /* CCM SRAM */ - ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -INCLUDE rules.ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F411xC.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F411xC.ld deleted file mode 100644 index eb00b34d6c..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F411xC.ld +++ /dev/null @@ -1,50 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * STM32F411xC memory setup. - */ -MEMORY -{ - flash : org = 0x08000000, len = 256k - ram0 : org = 0x20000000, len = 128k /* SRAM1 */ - ram1 : org = 0x00000000, len = 0 - ram2 : org = 0x00000000, len = 0 - ram3 : org = 0x00000000, len = 0 - ram4 : org = 0x00000000, len = 0 - ram5 : org = 0x00000000, len = 0 - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -INCLUDE rules.ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F411xE.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F411xE.ld deleted file mode 100644 index 411f1d4f87..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F411xE.ld +++ /dev/null @@ -1,50 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * STM32F411xE memory setup. - */ -MEMORY -{ - flash : org = 0x08000000, len = 512k - ram0 : org = 0x20000000, len = 128k - ram1 : org = 0x00000000, len = 0 - ram2 : org = 0x00000000, len = 0 - ram3 : org = 0x00000000, len = 0 - ram4 : org = 0x00000000, len = 0 - ram5 : org = 0x00000000, len = 0 - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -INCLUDE rules.ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F429xI.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F429xI.ld deleted file mode 100644 index 8d2beff546..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F429xI.ld +++ /dev/null @@ -1,51 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * ST32F429xI memory setup. - * Note: Use of ram1, ram2 and ram3 is mutually exclusive with use of ram0. - */ -MEMORY -{ - flash : org = 0x08000000, len = 2M - ram0 : org = 0x20000000, len = 192k /* SRAM1 + SRAM2 + SRAM3 */ - ram1 : org = 0x20000000, len = 112k /* SRAM1 */ - ram2 : org = 0x2001C000, len = 16k /* SRAM2 */ - ram3 : org = 0x20020000, len = 64k /* SRAM3 */ - ram4 : org = 0x10000000, len = 64k /* CCM SRAM */ - ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -INCLUDE rules.ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG.ld deleted file mode 100644 index 2fb3f4c3a5..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG.ld +++ /dev/null @@ -1,63 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * ST32F746xG generic setup. - * - * RAM0 - Data, Heap. - * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH. - * - * Notes: - * BSS is placed in DTCM RAM in order to simplify DMA buffers management. - */ -MEMORY -{ - flash : org = 0x08000000, len = 1M - flash_itcm : org = 0x00200000, len = 1M - ram0 : org = 0x20010000, len = 256k /* SRAM1 + SRAM2 */ - ram1 : org = 0x20010000, len = 240k /* SRAM1 */ - ram2 : org = 0x2004C000, len = 16k /* SRAM2 */ - ram3 : org = 0x20000000, len = 64k /* DTCM-RAM */ - ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */ - ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("MAIN_STACK_RAM", ram3); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram3); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram3); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -/* RAM region to be used for nocache segment.*/ -REGION_ALIAS("NOCACHE_RAM", ram3); - -/* RAM region to be used for eth segment.*/ -REGION_ALIAS("ETH_RAM", ram3); - -INCLUDE ld/rules_STM32F7xx.ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG_ETH.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG_ETH.ld deleted file mode 100644 index bd69c398c2..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG_ETH.ld +++ /dev/null @@ -1,63 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * ST32F746xG Ethernet setup. - * - * RAM1 - Data, Heap. - * RAM2 - ETH. - * RAM3 - Main Stack, Process Stack, BSS, NOCACHE. - * - * Notes: - * BSS is placed in DTCM RAM in order to simplify DMA buffers management. - */ -MEMORY -{ - flash : org = 0x08000000, len = 1M - ram0 : org = 0x20010000, len = 256k /* SRAM1 + SRAM2 */ - ram1 : org = 0x20010000, len = 240k /* SRAM1 */ - ram2 : org = 0x2004C000, len = 16k /* SRAM2 */ - ram3 : org = 0x20000000, len = 64k /* DTCM-RAM */ - ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */ - ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("MAIN_STACK_RAM", ram3); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram3); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram1); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram3); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram1); - -/* RAM region to be used for nocache segment.*/ -REGION_ALIAS("NOCACHE_RAM", ram3); - -/* RAM region to be used for eth segment.*/ -REGION_ALIAS("ETH_RAM", ram2); - -INCLUDE rules_dma.ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG_MAX.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG_MAX.ld deleted file mode 100644 index cde9e817eb..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG_MAX.ld +++ /dev/null @@ -1,65 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * ST32F746xG maximum RAM setup. - * - * RAM0 - Data, BSS, Heap. - * RAM3 - Main Stack, Process Stack, NOCACHE, ETH. - * - * Notes: - * BSS is placed in cached RAM, DMA buffers management is delegated to the - * application code. This setup maximizes the linear RAM available to BSS and - * Heap. - */ -MEMORY -{ - flash : org = 0x08000000, len = 1M - flash_itcm : org = 0x00200000, len = 1M - ram0 : org = 0x20010000, len = 256k /* SRAM1 + SRAM2 */ - ram1 : org = 0x20010000, len = 240k /* SRAM1 */ - ram2 : org = 0x2004C000, len = 16k /* SRAM2 */ - ram3 : org = 0x20000000, len = 64k /* DTCM-RAM */ - ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */ - ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("MAIN_STACK_RAM", ram3); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram3); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -/* RAM region to be used for nocache segment.*/ -REGION_ALIAS("NOCACHE_RAM", ram3); - -/* RAM region to be used for eth segment.*/ -REGION_ALIAS("ETH_RAM", ram3); - -INCLUDE ld/rules_STM32F7xx.ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32L052x6.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32L052x6.ld deleted file mode 100644 index bf754152e3..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32L052x6.ld +++ /dev/null @@ -1,50 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * STM32L052x8 memory setup. - */ -MEMORY -{ - flash : org = 0x08000000, len = 16k - ram0 : org = 0x20000000, len = 8k - ram1 : org = 0x00000000, len = 0 - ram2 : org = 0x00000000, len = 0 - ram3 : org = 0x00000000, len = 0 - ram4 : org = 0x00000000, len = 0 - ram5 : org = 0x00000000, len = 0 - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -INCLUDE rules.ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32L052x8.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32L052x8.ld deleted file mode 100644 index 0ca8932f6d..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32L052x8.ld +++ /dev/null @@ -1,50 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * STM32L052x8 memory setup. - */ -MEMORY -{ - flash : org = 0x08000000, len = 64k - ram0 : org = 0x20000000, len = 8k - ram1 : org = 0x00000000, len = 0 - ram2 : org = 0x00000000, len = 0 - ram3 : org = 0x00000000, len = 0 - ram4 : org = 0x00000000, len = 0 - ram5 : org = 0x00000000, len = 0 - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -INCLUDE rules.ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32L053x8.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32L053x8.ld deleted file mode 100644 index 30bbba080f..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32L053x8.ld +++ /dev/null @@ -1,50 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * STM32L053x8 memory setup. - */ -MEMORY -{ - flash : org = 0x08000000, len = 64k - ram0 : org = 0x20000000, len = 8k - ram1 : org = 0x00000000, len = 0 - ram2 : org = 0x00000000, len = 0 - ram3 : org = 0x00000000, len = 0 - ram4 : org = 0x00000000, len = 0 - ram5 : org = 0x00000000, len = 0 - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -INCLUDE rules.ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32L151x6.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32L151x6.ld deleted file mode 100644 index 88fe0b4f36..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32L151x6.ld +++ /dev/null @@ -1,50 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * STM32L151x6 memory setup. - */ -MEMORY -{ - flash : org = 0x08000000, len = 32k - ram0 : org = 0x20000000, len = 10k - ram1 : org = 0x00000000, len = 0 - ram2 : org = 0x00000000, len = 0 - ram3 : org = 0x00000000, len = 0 - ram4 : org = 0x00000000, len = 0 - ram5 : org = 0x00000000, len = 0 - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -INCLUDE rules.ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32L152xB.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32L152xB.ld deleted file mode 100644 index d84ad29179..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32L152xB.ld +++ /dev/null @@ -1,50 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * STM32L152xB memory setup. - */ -MEMORY -{ - flash : org = 0x08000000, len = 128k - ram0 : org = 0x20000000, len = 16k - ram1 : org = 0x00000000, len = 0 - ram2 : org = 0x00000000, len = 0 - ram3 : org = 0x00000000, len = 0 - ram4 : org = 0x00000000, len = 0 - ram5 : org = 0x00000000, len = 0 - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -INCLUDE rules.ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32L152xE.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32L152xE.ld deleted file mode 100644 index 7446a85e64..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32L152xE.ld +++ /dev/null @@ -1,50 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * STM32L152xB memory setup. - */ -MEMORY -{ - flash : org = 0x08000000, len = 512k - ram0 : org = 0x20000000, len = 80k - ram1 : org = 0x00000000, len = 0 - ram2 : org = 0x00000000, len = 0 - ram3 : org = 0x00000000, len = 0 - ram4 : org = 0x00000000, len = 0 - ram5 : org = 0x00000000, len = 0 - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -INCLUDE rules.ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32L476xG.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32L476xG.ld deleted file mode 100644 index 79126f2fce..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/STM32L476xG.ld +++ /dev/null @@ -1,50 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * STM32F303xC memory setup. - */ -MEMORY -{ - flash : org = 0x08000000, len = 1M - ram0 : org = 0x20000000, len = 96k - ram1 : org = 0x00000000, len = 0 - ram2 : org = 0x00000000, len = 0 - ram3 : org = 0x00000000, len = 0 - ram4 : org = 0x10000000, len = 32k - ram5 : org = 0x00000000, len = 0 - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -INCLUDE rules.ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/rules_STM32F7xx.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/rules_STM32F7xx.ld deleted file mode 100644 index 522b07d7fa..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/ld/rules_STM32F7xx.ld +++ /dev/null @@ -1,391 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -__ram0_start__ = ORIGIN(ram0); -__ram0_size__ = LENGTH(ram0); -__ram0_end__ = __ram0_start__ + __ram0_size__; -__ram1_start__ = ORIGIN(ram1); -__ram1_size__ = LENGTH(ram1); -__ram1_end__ = __ram1_start__ + __ram1_size__; -__ram2_start__ = ORIGIN(ram2); -__ram2_size__ = LENGTH(ram2); -__ram2_end__ = __ram2_start__ + __ram2_size__; -__ram3_start__ = ORIGIN(ram3); -__ram3_size__ = LENGTH(ram3); -__ram3_end__ = __ram3_start__ + __ram3_size__; -__ram4_start__ = ORIGIN(ram4); -__ram4_size__ = LENGTH(ram4); -__ram4_end__ = __ram4_start__ + __ram4_size__; -__ram5_start__ = ORIGIN(ram5); -__ram5_size__ = LENGTH(ram5); -__ram5_end__ = __ram5_start__ + __ram5_size__; -__ram6_start__ = ORIGIN(ram6); -__ram6_size__ = LENGTH(ram6); -__ram6_end__ = __ram6_start__ + __ram6_size__; -__ram7_start__ = ORIGIN(ram7); -__ram7_size__ = LENGTH(ram7); -__ram7_end__ = __ram7_start__ + __ram7_size__; - -ENTRY(Reset_Handler) - -SECTIONS -{ - . = 0; - _text = .; - - startup : ALIGN(16) SUBALIGN(16) - { - KEEP(*(.vectors)) - } > flash_itcm AT > flash - - constructors : ALIGN(4) SUBALIGN(4) - { - __init_array_start = .; - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - __init_array_end = .; - } > flash_itcm AT > flash - - destructors : ALIGN(4) SUBALIGN(4) - { - __fini_array_start = .; - KEEP(*(.fini_array)) - KEEP(*(SORT(.fini_array.*))) - __fini_array_end = .; - } > flash_itcm AT > flash - - .text : ALIGN(16) SUBALIGN(16) - { - *(.text) - *(.text.*) - *(.glue_7t) - *(.glue_7) - *(.gcc*) - } > flash_itcm AT > flash - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > flash_itcm AT > flash - - .ARM.exidx : { - __exidx_start = .; - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - __exidx_end = .; - } > flash_itcm AT > flash - - .eh_frame_hdr : - { - *(.eh_frame_hdr) - } > flash_itcm AT > flash - - .eh_frame : ONLY_IF_RO - { - *(.eh_frame) - } > flash_itcm AT > flash - - .textalign : ONLY_IF_RO - { - . = ALIGN(8); - } > flash_itcm AT > flash - - /* Constants are placed in the normal flash (non-ITCM) region because it - is desirable to make them DMA-accessible.*/ - .rodata : ALIGN(4) - { - . = ALIGN(4); - __rodata_base__ = .; - *(.rodata) - *(.rodata.*) - . = ALIGN(4); - __rodata_end__ = .; - } > flash - - /* Legacy symbol, not used anywhere.*/ - . = ALIGN(4); - PROVIDE(_etext = .); - - /* Special section for exceptions stack.*/ - .mstack : - { - . = ALIGN(8); - __main_stack_base__ = .; - . += __main_stack_size__; - . = ALIGN(8); - __main_stack_end__ = .; - } > MAIN_STACK_RAM - - /* Special section for process stack.*/ - .pstack : - { - __process_stack_base__ = .; - __main_thread_stack_base__ = .; - . += __process_stack_size__; - . = ALIGN(8); - __process_stack_end__ = .; - __main_thread_stack_end__ = .; - } > PROCESS_STACK_RAM - - /* Special section for non cache-able areas.*/ - .nocache (NOLOAD) : ALIGN(4) - { - __nocache_base__ = .; - *(.nocache) - *(.nocache.*) - *(.bss.__nocache_*) - . = ALIGN(4); - __nocache_end__ = .; - } > NOCACHE_RAM - - /* Special section for Ethernet DMA non cache-able areas.*/ - .eth (NOLOAD) : ALIGN(4) - { - __eth_base__ = .; - *(.eth) - *(.eth.*) - *(.bss.__eth_*) - . = ALIGN(4); - __eth_end__ = .; - } > ETH_RAM - - .data : ALIGN(4) - { - . = ALIGN(4); - PROVIDE(_textdata = LOADADDR(.data)); - PROVIDE(_data = .); - _textdata_start = LOADADDR(.data); - _data_start = .; - *(.data) - *(.data.*) - *(.ramtext) - . = ALIGN(4); - PROVIDE(_edata = .); - _data_end = .; - } > DATA_RAM AT > flash - - .bss (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - _bss_start = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - _bss_end = .; - PROVIDE(end = .); - } > BSS_RAM - - .ram0_init : ALIGN(4) - { - . = ALIGN(4); - __ram0_init_text__ = LOADADDR(.ram0_init); - __ram0_init__ = .; - *(.ram0_init) - *(.ram0_init.*) - . = ALIGN(4); - } > ram0 AT > flash - - .ram0 (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - __ram0_clear__ = .; - *(.ram0_clear) - *(.ram0_clear.*) - . = ALIGN(4); - __ram0_noinit__ = .; - *(.ram0) - *(.ram0.*) - . = ALIGN(4); - __ram0_free__ = .; - } > ram0 - - .ram1_init : ALIGN(4) - { - . = ALIGN(4); - __ram1_init_text__ = LOADADDR(.ram1_init); - __ram1_init__ = .; - *(.ram1_init) - *(.ram1_init.*) - . = ALIGN(4); - } > ram1 AT > flash - - .ram1 (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - __ram1_clear__ = .; - *(.ram1_clear) - *(.ram1_clear.*) - . = ALIGN(4); - __ram1_noinit__ = .; - *(.ram1) - *(.ram1.*) - . = ALIGN(4); - __ram1_free__ = .; - } > ram1 - - .ram2_init : ALIGN(4) - { - . = ALIGN(4); - __ram2_init_text__ = LOADADDR(.ram2_init); - __ram2_init__ = .; - *(.ram2_init) - *(.ram2_init.*) - . = ALIGN(4); - } > ram2 AT > flash - - .ram2 (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - __ram2_clear__ = .; - *(.ram2_clear) - *(.ram2_clear.*) - . = ALIGN(4); - __ram2_noinit__ = .; - *(.ram2) - *(.ram2.*) - . = ALIGN(4); - __ram2_free__ = .; - } > ram2 - - .ram3_init : ALIGN(4) - { - . = ALIGN(4); - __ram3_init_text__ = LOADADDR(.ram3_init); - __ram3_init__ = .; - *(.ram3_init) - *(.ram3_init.*) - . = ALIGN(4); - } > ram3 AT > flash - - .ram3 (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - __ram3_clear__ = .; - *(.ram3_clear) - *(.ram3_clear.*) - . = ALIGN(4); - __ram3_noinit__ = .; - *(.ram3) - *(.ram3.*) - . = ALIGN(4); - __ram3_free__ = .; - } > ram3 - - .ram4_init : ALIGN(4) - { - . = ALIGN(4); - __ram4_init_text__ = LOADADDR(.ram4_init); - __ram4_init__ = .; - *(.ram4_init) - *(.ram4_init.*) - . = ALIGN(4); - } > ram4 AT > flash - - .ram4 (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - __ram4_clear__ = .; - *(.ram4_clear) - *(.ram4_clear.*) - . = ALIGN(4); - __ram4_noinit__ = .; - *(.ram4) - *(.ram4.*) - . = ALIGN(4); - __ram4_free__ = .; - } > ram4 - - .ram5_init : ALIGN(4) - { - . = ALIGN(4); - __ram5_init_text__ = LOADADDR(.ram5_init); - __ram5_init__ = .; - *(.ram5_init) - *(.ram5_init.*) - . = ALIGN(4); - } > ram5 AT > flash - - .ram5 (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - __ram5_clear__ = .; - *(.ram5_clear) - *(.ram5_clear.*) - . = ALIGN(4); - __ram5_noinit__ = .; - *(.ram5) - *(.ram5.*) - . = ALIGN(4); - __ram5_free__ = .; - } > ram5 - - .ram6_init : ALIGN(4) - { - . = ALIGN(4); - __ram6_init_text__ = LOADADDR(.ram6_init); - __ram6_init__ = .; - *(.ram6_init) - *(.ram6_init.*) - . = ALIGN(4); - } > ram6 AT > flash - - .ram6 (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - __ram6_clear__ = .; - *(.ram6_clear) - *(.ram6_clear.*) - . = ALIGN(4); - __ram6_noinit__ = .; - *(.ram6) - *(.ram6.*) - . = ALIGN(4); - __ram6_free__ = .; - } > ram6 - - .ram7_init : ALIGN(4) - { - . = ALIGN(4); - __ram7_init_text__ = LOADADDR(.ram7_init); - __ram7_init__ = .; - *(.ram7_init) - *(.ram7_init.*) - . = ALIGN(4); - } > ram7 AT > flash - - .ram7 (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - __ram7_clear__ = .; - *(.ram7_clear) - *(.ram7_clear.*) - . = ALIGN(4); - __ram7_noinit__ = .; - *(.ram7) - *(.ram7.*) - . = ALIGN(4); - __ram7_free__ = .; - } > ram7 - - /* The default heap uses the (statically) unused part of a RAM section.*/ - .heap (NOLOAD) : - { - . = ALIGN(8); - __heap_base__ = .; - . = ORIGIN(HEAP_RAM) + LENGTH(HEAP_RAM); - __heap_end__ = .; - } > HEAP_RAM -} diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/mk/startup_k20x.mk b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/mk/startup_k20x.mk deleted file mode 100644 index 5f9ad87658..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/mk/startup_k20x.mk +++ /dev/null @@ -1,12 +0,0 @@ -# List of the ChibiOS generic K20x startup and CMSIS files. -STARTUPSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt1.c \ - $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c - -STARTUPASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0_v7m.s - -STARTUPINC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC \ - $(CHIBIOS)/os/common/ports/ARMCMx/devices/K20x \ - $(CHIBIOS)/os/ext/CMSIS/include \ - $(CHIBIOS)/os/ext/CMSIS/KINETIS - -STARTUPLD = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/mk/startup_kl2x.mk b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/mk/startup_kl2x.mk deleted file mode 100644 index 30014a3dd4..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/mk/startup_kl2x.mk +++ /dev/null @@ -1,12 +0,0 @@ -# List of the ChibiOS generic KL2x startup and CMSIS files. -STARTUPSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt1.c \ - $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c - -STARTUPASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0_v6m.s - -STARTUPINC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC \ - $(CHIBIOS)/os/common/ports/ARMCMx/devices/KL2x \ - $(CHIBIOS)/os/ext/CMSIS/include \ - $(CHIBIOS)/os/ext/CMSIS/KINETIS - -STARTUPLD = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32f0xx.mk b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32f0xx.mk deleted file mode 100644 index bd94d87061..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32f0xx.mk +++ /dev/null @@ -1,12 +0,0 @@ -# List of the ChibiOS generic STM32F0xx startup and CMSIS files. -STARTUPSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt1.c \ - $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c - -STARTUPASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0_v6m.s - -STARTUPINC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC \ - $(CHIBIOS)/os/common/ports/ARMCMx/devices/STM32F0xx \ - $(CHIBIOS)/os/ext/CMSIS/include \ - $(CHIBIOS)/os/ext/CMSIS/ST/STM32F0xx - -STARTUPLD = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32f1xx.mk b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32f1xx.mk deleted file mode 100644 index b226b2bd25..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32f1xx.mk +++ /dev/null @@ -1,12 +0,0 @@ -# List of the ChibiOS generic STM32F1xx startup and CMSIS files. -STARTUPSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt1.c \ - $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c - -STARTUPASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0_v7m.s - -STARTUPINC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC \ - $(CHIBIOS)/os/common/ports/ARMCMx/devices/STM32F1xx \ - $(CHIBIOS)/os/ext/CMSIS/include \ - $(CHIBIOS)/os/ext/CMSIS/ST/STM32F1xx - -STARTUPLD = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32f2xx.mk b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32f2xx.mk deleted file mode 100644 index a901660947..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32f2xx.mk +++ /dev/null @@ -1,12 +0,0 @@ -# List of the ChibiOS generic STM32F2xx startup and CMSIS files. -STARTUPSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt1.c \ - $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c - -STARTUPASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0_v7m.s - -STARTUPINC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC \ - $(CHIBIOS)/os/common/ports/ARMCMx/devices/STM32F2xx \ - $(CHIBIOS)/os/ext/CMSIS/include \ - $(CHIBIOS)/os/ext/CMSIS/ST/STM32F2xx - -STARTUPLD = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32f3xx.mk b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32f3xx.mk deleted file mode 100644 index 8a6af7b508..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32f3xx.mk +++ /dev/null @@ -1,12 +0,0 @@ -# List of the ChibiOS generic STM32F3xx startup and CMSIS files. -STARTUPSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt1.c \ - $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c - -STARTUPASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0_v7m.s - -STARTUPINC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC \ - $(CHIBIOS)/os/common/ports/ARMCMx/devices/STM32F3xx \ - $(CHIBIOS)/os/ext/CMSIS/include \ - $(CHIBIOS)/os/ext/CMSIS/ST/STM32F3xx - -STARTUPLD = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk deleted file mode 100644 index c01ed0154f..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk +++ /dev/null @@ -1,12 +0,0 @@ -# List of the ChibiOS generic STM32F4xx startup and CMSIS files. -STARTUPSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt1.c \ - $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c - -STARTUPASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0_v7m.s - -STARTUPINC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC \ - $(CHIBIOS)/os/common/ports/ARMCMx/devices/STM32F4xx \ - $(CHIBIOS)/os/ext/CMSIS/include \ - $(CHIBIOS)/os/ext/CMSIS/ST/STM32F4xx - -STARTUPLD = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32f7xx.mk b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32f7xx.mk deleted file mode 100644 index 5527f03dcf..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32f7xx.mk +++ /dev/null @@ -1,12 +0,0 @@ -# List of the ChibiOS generic STM32F7xx startup and CMSIS files. -STARTUPSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt1.c \ - $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c - -STARTUPASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0_v7m.s - -STARTUPINC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC \ - $(CHIBIOS)/os/common/ports/ARMCMx/devices/STM32F7xx \ - $(CHIBIOS)/os/ext/CMSIS/include \ - $(CHIBIOS)/os/ext/CMSIS/ST/STM32F7xx - -STARTUPLD = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32l0xx.mk b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32l0xx.mk deleted file mode 100644 index 46524c8d0a..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32l0xx.mk +++ /dev/null @@ -1,12 +0,0 @@ -# List of the ChibiOS generic STM32L0xx startup and CMSIS files. -STARTUPSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt1.c \ - $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c - -STARTUPASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0_v6m.s - -STARTUPINC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC \ - $(CHIBIOS)/os/common/ports/ARMCMx/devices/STM32L0xx \ - $(CHIBIOS)/os/ext/CMSIS/include \ - $(CHIBIOS)/os/ext/CMSIS/ST/STM32L0xx - -STARTUPLD = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32l1xx.mk b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32l1xx.mk deleted file mode 100644 index 9f275aa318..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32l1xx.mk +++ /dev/null @@ -1,12 +0,0 @@ -# List of the ChibiOS generic STM32L1xx startup and CMSIS files. -STARTUPSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt1.c \ - $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c - -STARTUPASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0_v7m.s - -STARTUPINC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC \ - $(CHIBIOS)/os/common/ports/ARMCMx/devices/STM32L1xx \ - $(CHIBIOS)/os/ext/CMSIS/include \ - $(CHIBIOS)/os/ext/CMSIS/ST/STM32L1xx - -STARTUPLD = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32l4xx.mk b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32l4xx.mk deleted file mode 100644 index 4f1fd19b79..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32l4xx.mk +++ /dev/null @@ -1,12 +0,0 @@ -# List of the ChibiOS generic STM32L4xx startup and CMSIS files. -STARTUPSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt1.c \ - $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c - -STARTUPASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0_v7m.s - -STARTUPINC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC \ - $(CHIBIOS)/os/common/ports/ARMCMx/devices/STM32L4xx \ - $(CHIBIOS)/os/ext/CMSIS/include \ - $(CHIBIOS)/os/ext/CMSIS/ST/STM32L4xx - -STARTUPLD = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/ld diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/rules.ld b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/rules.ld deleted file mode 100644 index 4d842e7377..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/rules.ld +++ /dev/null @@ -1,359 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -__ram0_start__ = ORIGIN(ram0); -__ram0_size__ = LENGTH(ram0); -__ram0_end__ = __ram0_start__ + __ram0_size__; -__ram1_start__ = ORIGIN(ram1); -__ram1_size__ = LENGTH(ram1); -__ram1_end__ = __ram1_start__ + __ram1_size__; -__ram2_start__ = ORIGIN(ram2); -__ram2_size__ = LENGTH(ram2); -__ram2_end__ = __ram2_start__ + __ram2_size__; -__ram3_start__ = ORIGIN(ram3); -__ram3_size__ = LENGTH(ram3); -__ram3_end__ = __ram3_start__ + __ram3_size__; -__ram4_start__ = ORIGIN(ram4); -__ram4_size__ = LENGTH(ram4); -__ram4_end__ = __ram4_start__ + __ram4_size__; -__ram5_start__ = ORIGIN(ram5); -__ram5_size__ = LENGTH(ram5); -__ram5_end__ = __ram5_start__ + __ram5_size__; -__ram6_start__ = ORIGIN(ram6); -__ram6_size__ = LENGTH(ram6); -__ram6_end__ = __ram6_start__ + __ram6_size__; -__ram7_start__ = ORIGIN(ram7); -__ram7_size__ = LENGTH(ram7); -__ram7_end__ = __ram7_start__ + __ram7_size__; - -ENTRY(Reset_Handler) - -SECTIONS -{ - . = 0; - _text = .; - - startup : ALIGN(16) SUBALIGN(16) - { - KEEP(*(.vectors)) - } > flash - - constructors : ALIGN(4) SUBALIGN(4) - { - __init_array_start = .; - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - __init_array_end = .; - } > flash - - destructors : ALIGN(4) SUBALIGN(4) - { - __fini_array_start = .; - KEEP(*(.fini_array)) - KEEP(*(SORT(.fini_array.*))) - __fini_array_end = .; - } > flash - - .text : ALIGN(16) SUBALIGN(16) - { - *(.text) - *(.text.*) - *(.rodata) - *(.rodata.*) - *(.glue_7t) - *(.glue_7) - *(.gcc*) - } > flash - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > flash - - .ARM.exidx : { - __exidx_start = .; - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - __exidx_end = .; - } > flash - - .eh_frame_hdr : - { - *(.eh_frame_hdr) - } > flash - - .eh_frame : ONLY_IF_RO - { - *(.eh_frame) - } > flash - - .textalign : ONLY_IF_RO - { - . = ALIGN(8); - } > flash - - /* Legacy symbol, not used anywhere.*/ - . = ALIGN(4); - PROVIDE(_etext = .); - - /* Special section for exceptions stack.*/ - .mstack : - { - . = ALIGN(8); - __main_stack_base__ = .; - . += __main_stack_size__; - . = ALIGN(8); - __main_stack_end__ = .; - } > MAIN_STACK_RAM - - /* Special section for process stack.*/ - .pstack : - { - __process_stack_base__ = .; - __main_thread_stack_base__ = .; - . += __process_stack_size__; - . = ALIGN(8); - __process_stack_end__ = .; - __main_thread_stack_end__ = .; - } > PROCESS_STACK_RAM - - .data : ALIGN(4) - { - . = ALIGN(4); - PROVIDE(_textdata = LOADADDR(.data)); - PROVIDE(_data = .); - _textdata_start = LOADADDR(.data); - _data_start = .; - *(.data) - *(.data.*) - *(.ramtext) - . = ALIGN(4); - PROVIDE(_edata = .); - _data_end = .; - } > DATA_RAM AT > flash - - .bss (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - _bss_start = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - _bss_end = .; - PROVIDE(end = .); - } > BSS_RAM - - .ram0_init : ALIGN(4) - { - . = ALIGN(4); - __ram0_init_text__ = LOADADDR(.ram0_init); - __ram0_init__ = .; - *(.ram0_init) - *(.ram0_init.*) - . = ALIGN(4); - } > ram0 AT > flash - - .ram0 (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - __ram0_clear__ = .; - *(.ram0_clear) - *(.ram0_clear.*) - . = ALIGN(4); - __ram0_noinit__ = .; - *(.ram0) - *(.ram0.*) - . = ALIGN(4); - __ram0_free__ = .; - } > ram0 - - .ram1_init : ALIGN(4) - { - . = ALIGN(4); - __ram1_init_text__ = LOADADDR(.ram1_init); - __ram1_init__ = .; - *(.ram1_init) - *(.ram1_init.*) - . = ALIGN(4); - } > ram1 AT > flash - - .ram1 (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - __ram1_clear__ = .; - *(.ram1_clear) - *(.ram1_clear.*) - . = ALIGN(4); - __ram1_noinit__ = .; - *(.ram1) - *(.ram1.*) - . = ALIGN(4); - __ram1_free__ = .; - } > ram1 - - .ram2_init : ALIGN(4) - { - . = ALIGN(4); - __ram2_init_text__ = LOADADDR(.ram2_init); - __ram2_init__ = .; - *(.ram2_init) - *(.ram2_init.*) - . = ALIGN(4); - } > ram2 AT > flash - - .ram2 (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - __ram2_clear__ = .; - *(.ram2_clear) - *(.ram2_clear.*) - . = ALIGN(4); - __ram2_noinit__ = .; - *(.ram2) - *(.ram2.*) - . = ALIGN(4); - __ram2_free__ = .; - } > ram2 - - .ram3_init : ALIGN(4) - { - . = ALIGN(4); - __ram3_init_text__ = LOADADDR(.ram3_init); - __ram3_init__ = .; - *(.ram3_init) - *(.ram3_init.*) - . = ALIGN(4); - } > ram3 AT > flash - - .ram3 (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - __ram3_clear__ = .; - *(.ram3_clear) - *(.ram3_clear.*) - . = ALIGN(4); - __ram3_noinit__ = .; - *(.ram3) - *(.ram3.*) - . = ALIGN(4); - __ram3_free__ = .; - } > ram3 - - .ram4_init : ALIGN(4) - { - . = ALIGN(4); - __ram4_init_text__ = LOADADDR(.ram4_init); - __ram4_init__ = .; - *(.ram4_init) - *(.ram4_init.*) - . = ALIGN(4); - } > ram4 AT > flash - - .ram4 (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - __ram4_clear__ = .; - *(.ram4_clear) - *(.ram4_clear.*) - . = ALIGN(4); - __ram4_noinit__ = .; - *(.ram4) - *(.ram4.*) - . = ALIGN(4); - __ram4_free__ = .; - } > ram4 - - .ram5_init : ALIGN(4) - { - . = ALIGN(4); - __ram5_init_text__ = LOADADDR(.ram5_init); - __ram5_init__ = .; - *(.ram5_init) - *(.ram5_init.*) - . = ALIGN(4); - } > ram5 AT > flash - - .ram5 (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - __ram5_clear__ = .; - *(.ram5_clear) - *(.ram5_clear.*) - . = ALIGN(4); - __ram5_noinit__ = .; - *(.ram5) - *(.ram5.*) - . = ALIGN(4); - __ram5_free__ = .; - } > ram5 - - .ram6_init : ALIGN(4) - { - . = ALIGN(4); - __ram6_init_text__ = LOADADDR(.ram6_init); - __ram6_init__ = .; - *(.ram6_init) - *(.ram6_init.*) - . = ALIGN(4); - } > ram6 AT > flash - - .ram6 (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - __ram6_clear__ = .; - *(.ram6_clear) - *(.ram6_clear.*) - . = ALIGN(4); - __ram6_noinit__ = .; - *(.ram6) - *(.ram6.*) - . = ALIGN(4); - __ram6_free__ = .; - } > ram6 - - .ram7_init : ALIGN(4) - { - . = ALIGN(4); - __ram7_init_text__ = LOADADDR(.ram7_init); - __ram7_init__ = .; - *(.ram7_init) - *(.ram7_init.*) - . = ALIGN(4); - } > ram7 AT > flash - - .ram7 (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - __ram7_clear__ = .; - *(.ram7_clear) - *(.ram7_clear.*) - . = ALIGN(4); - __ram7_noinit__ = .; - *(.ram7) - *(.ram7.*) - . = ALIGN(4); - __ram7_free__ = .; - } > ram7 - - /* The default heap uses the (statically) unused part of a RAM section.*/ - .heap (NOLOAD) : - { - . = ALIGN(8); - __heap_base__ = .; - . = ORIGIN(HEAP_RAM) + LENGTH(HEAP_RAM); - __heap_end__ = .; - } > HEAP_RAM -} diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/rules.mk b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/rules.mk deleted file mode 100644 index 72e5801d38..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/rules.mk +++ /dev/null @@ -1,312 +0,0 @@ -# ARM Cortex-Mx common makefile scripts and rules. - -############################################################################## -# Processing options coming from the upper Makefile. -# - -# Compiler options -OPT := $(USE_OPT) -COPT := $(USE_COPT) -CPPOPT := $(USE_CPPOPT) - -# Garbage collection -ifeq ($(USE_LINK_GC),yes) - OPT += -ffunction-sections -fdata-sections -fno-common - LDOPT := ,--gc-sections -else - LDOPT := -endif - -# Linker extra options -ifneq ($(USE_LDOPT),) - LDOPT := $(LDOPT),$(USE_LDOPT) -endif - -# Link time optimizations -ifeq ($(USE_LTO),yes) - OPT += -flto -endif - -# FPU-related options -ifeq ($(USE_FPU),) - USE_FPU = no -endif -ifneq ($(USE_FPU),no) - OPT += -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 -fsingle-precision-constant - DDEFS += -DCORTEX_USE_FPU=TRUE - DADEFS += -DCORTEX_USE_FPU=TRUE -else - DDEFS += -DCORTEX_USE_FPU=FALSE - DADEFS += -DCORTEX_USE_FPU=FALSE -endif - -# Process stack size -ifeq ($(USE_PROCESS_STACKSIZE),) - LDOPT := $(LDOPT),--defsym=__process_stack_size__=0x400 -else - LDOPT := $(LDOPT),--defsym=__process_stack_size__=$(USE_PROCESS_STACKSIZE) -endif - -# Exceptions stack size -ifeq ($(USE_EXCEPTIONS_STACKSIZE),) - LDOPT := $(LDOPT),--defsym=__main_stack_size__=0x400 -else - LDOPT := $(LDOPT),--defsym=__main_stack_size__=$(USE_EXCEPTIONS_STACKSIZE) -endif - -# Output directory and files -ifeq ($(BUILDDIR),) - BUILDDIR = build -endif -ifeq ($(BUILDDIR),.) - BUILDDIR = build -endif -OUTFILES := $(BUILDDIR)/$(PROJECT).elf \ - $(BUILDDIR)/$(PROJECT).hex \ - $(BUILDDIR)/$(PROJECT).bin \ - $(BUILDDIR)/$(PROJECT).dmp \ - $(BUILDDIR)/$(PROJECT).list - -ifdef SREC - OUTFILES += $(BUILDDIR)/$(PROJECT).srec -endif - -# Source files groups and paths -ifeq ($(USE_THUMB),yes) - TCSRC += $(CSRC) - TCPPSRC += $(CPPSRC) -else - ACSRC += $(CSRC) - ACPPSRC += $(CPPSRC) -endif -ASRC := $(ACSRC) $(ACPPSRC) -TSRC := $(TCSRC) $(TCPPSRC) -SRCPATHS := $(sort $(dir $(ASMXSRC)) $(dir $(ASMSRC)) $(dir $(ASRC)) $(dir $(TSRC))) - -# Various directories -OBJDIR := $(BUILDDIR)/obj -LSTDIR := $(BUILDDIR)/lst - -# Object files groups -ACOBJS := $(addprefix $(OBJDIR)/, $(notdir $(ACSRC:.c=.o))) -ACPPOBJS := $(addprefix $(OBJDIR)/, $(notdir $(ACPPSRC:.cpp=.o))) -TCOBJS := $(addprefix $(OBJDIR)/, $(notdir $(TCSRC:.c=.o))) -TCPPOBJS := $(addprefix $(OBJDIR)/, $(notdir $(TCPPSRC:.cpp=.o))) -ASMOBJS := $(addprefix $(OBJDIR)/, $(notdir $(ASMSRC:.s=.o))) -ASMXOBJS := $(addprefix $(OBJDIR)/, $(notdir $(ASMXSRC:.S=.o))) -OBJS := $(ASMXOBJS) $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS) - -# Paths -IINCDIR := $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR)) -LLIBDIR := $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) - -# Macros -DEFS := $(DDEFS) $(UDEFS) -ADEFS := $(DADEFS) $(UADEFS) - -# Libs -LIBS := $(DLIBS) $(ULIBS) - -# Various settings -MCFLAGS := -mcpu=$(MCU) -ODFLAGS = -x --syms -ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS) -ASXFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS) -CFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS) -CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS) -LDFLAGS = $(MCFLAGS) $(OPT) -nostartfiles $(LLIBDIR) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--library-path=$(RULESPATH),--script=$(LDSCRIPT)$(LDOPT) - -# Thumb interwork enabled only if needed because it kills performance. -ifneq ($(strip $(TSRC)),) - CFLAGS += -DTHUMB_PRESENT - CPPFLAGS += -DTHUMB_PRESENT - ASFLAGS += -DTHUMB_PRESENT - ASXFLAGS += -DTHUMB_PRESENT - ifneq ($(strip $(ASRC)),) - # Mixed ARM and THUMB mode. - CFLAGS += -mthumb-interwork - CPPFLAGS += -mthumb-interwork - ASFLAGS += -mthumb-interwork - ASXFLAGS += -mthumb-interwork - LDFLAGS += -mthumb-interwork - else - # Pure THUMB mode, THUMB C code cannot be called by ARM asm code directly. - CFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING - CPPFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING - ASFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -mthumb - ASXFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -mthumb - LDFLAGS += -mno-thumb-interwork -mthumb - endif -else - # Pure ARM mode - CFLAGS += -mno-thumb-interwork - CPPFLAGS += -mno-thumb-interwork - ASFLAGS += -mno-thumb-interwork - ASXFLAGS += -mno-thumb-interwork - LDFLAGS += -mno-thumb-interwork -endif - -# Generate dependency information -ASFLAGS += -MD -MP -MF .dep/$(@F).d -ASXFLAGS += -MD -MP -MF .dep/$(@F).d -CFLAGS += -MD -MP -MF .dep/$(@F).d -CPPFLAGS += -MD -MP -MF .dep/$(@F).d - -# Paths where to search for sources -VPATH = $(SRCPATHS) - -# -# Makefile rules -# - -all: PRE_MAKE_ALL_RULE_HOOK $(OBJS) $(OUTFILES) POST_MAKE_ALL_RULE_HOOK - -PRE_MAKE_ALL_RULE_HOOK: - -POST_MAKE_ALL_RULE_HOOK: - -$(OBJS): | $(BUILDDIR) $(OBJDIR) $(LSTDIR) - -$(BUILDDIR): -ifneq ($(USE_VERBOSE_COMPILE),yes) - @echo Compiler Options - @echo $(CC) -c $(CFLAGS) -I. $(IINCDIR) main.c -o main.o - @echo -endif - @mkdir -p $(BUILDDIR) - -$(OBJDIR): - @mkdir -p $(OBJDIR) - -$(LSTDIR): - @mkdir -p $(LSTDIR) - -$(ACPPOBJS) : $(OBJDIR)/%.o : %.cpp Makefile -ifeq ($(USE_VERBOSE_COMPILE),yes) - @echo - $(CPPC) -c $(CPPFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@ -else - @echo Compiling $( $@ - $(SZ) $< -else - @echo Creating $@ - @$(OD) $(ODFLAGS) $< > $@ - @echo - @$(SZ) $< -endif - -%.list: %.elf -ifeq ($(USE_VERBOSE_COMPILE),yes) - $(OD) -S $< > $@ -else - @echo Creating $@ - @$(OD) -S $< > $@ - @echo - @echo Done -endif - -lib: $(OBJS) $(BUILDDIR)/lib$(PROJECT).a - -$(BUILDDIR)/lib$(PROJECT).a: $(OBJS) - @$(AR) -r $@ $^ - @echo - @echo Done - -clean: - @echo Cleaning - -rm -fR .dep $(BUILDDIR) - @echo - @echo Done - -# -# Include the dependency files, should be the last of the makefile -# --include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) - -# *** EOF *** diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/vectors.c b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/vectors.c deleted file mode 100644 index e9bb50f83c..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/vectors.c +++ /dev/null @@ -1,629 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file ARMCMx/compilers/GCC/vectors.c - * @brief Interrupt vectors for Cortex-Mx devices. - * - * @defgroup ARMCMx_VECTORS Cortex-Mx Interrupt Vectors - * @{ - */ - -#include -#include - -#include "vectors.h" - -#if (CORTEX_NUM_VECTORS % 8) != 0 -#error "the constant CORTEX_NUM_VECTORS must be a multiple of 8" -#endif - -#if (CORTEX_NUM_VECTORS < 8) || (CORTEX_NUM_VECTORS > 240) -#error "the constant CORTEX_NUM_VECTORS must be between 8 and 240 inclusive" -#endif - -/** - * @brief Unhandled exceptions handler. - * @details Any undefined exception vector points to this function by default. - * This function simply stops the system into an infinite loop. - * - * @notapi - */ -/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/ -void _unhandled_exception(void) { -/*lint -restore*/ - - while (true) { - } -} - -#if !defined(__DOXYGEN__) -extern uint32_t __main_stack_end__; -void Reset_Handler(void); -void NMI_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); -void HardFault_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); -void MemManage_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); -void BusFault_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); -void UsageFault_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector1C(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector20(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector24(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector28(void) __attribute__((weak, alias("_unhandled_exception"))); -void SVC_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); -void DebugMon_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector34(void) __attribute__((weak, alias("_unhandled_exception"))); -void PendSV_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); -void SysTick_Handler(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector40(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector44(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector48(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector4C(void) __attribute__((weak, alias("_unhandled_exception"))); -#if CORTEX_NUM_VECTORS > 4 -void Vector50(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector54(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector58(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector5C(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 8 -void Vector60(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector64(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector68(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector6C(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 12 -void Vector70(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector74(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector78(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector7C(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 16 -void Vector80(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector84(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector88(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector8C(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 20 -void Vector90(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector94(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector98(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector9C(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 24 -void VectorA0(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorA4(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorA8(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorAC(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 28 -void VectorB0(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorB4(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorB8(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorBC(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 32 -void VectorC0(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorC4(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorC8(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorCC(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 36 -void VectorD0(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorD4(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorD8(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorDC(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 40 -void VectorE0(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorE4(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorE8(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorEC(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 44 -void VectorF0(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorF4(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorF8(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorFC(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 48 -void Vector100(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector104(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector108(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector10C(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 52 -void Vector110(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector114(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector118(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector11C(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 56 -void Vector120(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector124(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector128(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector12C(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 60 -void Vector130(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector134(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector138(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector13C(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 64 -void Vector140(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector144(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector148(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector14C(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 68 -void Vector150(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector154(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector158(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector15C(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 72 -void Vector160(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector164(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector168(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector16C(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 76 -void Vector170(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector174(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector178(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector17C(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 80 -void Vector180(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector184(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector188(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector18C(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 84 -void Vector190(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector194(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector198(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector19C(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 88 -void Vector1A0(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector1A4(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector1A8(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector1AC(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 92 -void Vector1B0(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector1B4(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector1B8(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector1BC(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 96 -void Vector1C0(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector1C4(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector1C8(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector1CC(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 100 -void Vector1D0(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector1D4(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector1D8(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector1DC(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 104 -void Vector1E0(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector1E4(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector1E8(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector1EC(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 108 -void Vector1F0(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector1F4(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector1F8(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector1FC(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 112 -void Vector200(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector204(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector208(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector20C(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 116 -void Vector210(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector214(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector218(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector21C(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 120 -void Vector220(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector224(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector228(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector22C(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 124 -void Vector230(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector234(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector238(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector23C(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 128 -void Vector240(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector244(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector248(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector24C(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 132 -void Vector250(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector254(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector258(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector25C(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 136 -void Vector260(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector264(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector268(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector26C(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 140 -void Vector270(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector274(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector278(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector27C(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 144 -void Vector280(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector284(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector288(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector28C(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 148 -void Vector290(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector294(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector298(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector29C(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 152 -void Vector2A0(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector2A4(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector2A8(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector2AC(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 156 -void Vector2B0(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector2B4(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector2B8(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector2BC(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 160 -void Vector2C0(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector2C4(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector2C8(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector2CC(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 164 -void Vector2D0(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector2D4(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector2D8(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector2DC(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 168 -void Vector2E0(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector2E4(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector2E8(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector2EC(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 172 -void Vector2F0(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector2F4(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector2F8(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector2FC(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 176 -void Vector300(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector304(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector308(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector30C(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 180 -void Vector310(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector314(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector318(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector31C(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 184 -void Vector320(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector324(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector328(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector32C(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 188 -void Vector330(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector334(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector338(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector33C(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 192 -void Vector340(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector344(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector348(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector34C(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 196 -void Vector350(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector354(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector358(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector35C(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 200 -void Vector360(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector364(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector368(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector36C(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 204 -void Vector370(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector374(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector378(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector37C(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 208 -void Vector380(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector384(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector388(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector38C(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 212 -void Vector390(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector394(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector398(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector39C(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 216 -void Vector3A0(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector3A4(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector3A8(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector3AC(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 220 -void Vector3B0(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector3B4(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector3B8(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector3BC(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 224 -void Vector3C0(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector3C4(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector3C8(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector3CC(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 228 -void Vector3D0(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector3D4(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector3D8(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector3DC(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 232 -void Vector3E0(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector3E4(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector3E8(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector3EC(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if CORTEX_NUM_VECTORS > 236 -void Vector3F0(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector3F4(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector3F8(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector3FC(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#endif /* !defined(__DOXYGEN__) */ - -/** - * @brief STM32 vectors table. - */ -#if !defined(__DOXYGEN__) -#if !defined(VECTORS_SECTION) -__attribute__ ((used, aligned(128), section(".vectors"))) -#else -__attribute__ ((used, aligned(128), section(VECTORS_SECTION))) -#endif -#endif -/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/ -vectors_t _vectors = { -/*lint -restore*/ - &__main_stack_end__,Reset_Handler, NMI_Handler, HardFault_Handler, - MemManage_Handler, BusFault_Handler, UsageFault_Handler, Vector1C, - Vector20, Vector24, Vector28, SVC_Handler, - DebugMon_Handler, Vector34, PendSV_Handler, SysTick_Handler, - { - Vector40, Vector44, Vector48, Vector4C, -#if CORTEX_NUM_VECTORS > 4 - Vector50, Vector54, Vector58, Vector5C, -#endif -#if CORTEX_NUM_VECTORS > 8 - Vector60, Vector64, Vector68, Vector6C, -#endif -#if CORTEX_NUM_VECTORS > 12 - Vector70, Vector74, Vector78, Vector7C, -#endif -#if CORTEX_NUM_VECTORS > 16 - Vector80, Vector84, Vector88, Vector8C, -#endif -#if CORTEX_NUM_VECTORS > 20 - Vector90, Vector94, Vector98, Vector9C, -#endif -#if CORTEX_NUM_VECTORS > 24 - VectorA0, VectorA4, VectorA8, VectorAC, -#endif -#if CORTEX_NUM_VECTORS > 28 - VectorB0, VectorB4, VectorB8, VectorBC, -#endif -#if CORTEX_NUM_VECTORS > 32 - VectorC0, VectorC4, VectorC8, VectorCC, -#endif -#if CORTEX_NUM_VECTORS > 36 - VectorD0, VectorD4, VectorD8, VectorDC, -#endif -#if CORTEX_NUM_VECTORS > 40 - VectorE0, VectorE4, VectorE8, VectorEC, -#endif -#if CORTEX_NUM_VECTORS > 44 - VectorF0, VectorF4, VectorF8, VectorFC, -#endif -#if CORTEX_NUM_VECTORS > 48 - Vector100, Vector104, Vector108, Vector10C, -#endif -#if CORTEX_NUM_VECTORS > 52 - Vector110, Vector114, Vector118, Vector11C, -#endif -#if CORTEX_NUM_VECTORS > 56 - Vector120, Vector124, Vector128, Vector12C, -#endif -#if CORTEX_NUM_VECTORS > 60 - Vector130, Vector134, Vector138, Vector13C, -#endif -#if CORTEX_NUM_VECTORS > 64 - Vector140, Vector144, Vector148, Vector14C, -#endif -#if CORTEX_NUM_VECTORS > 68 - Vector150, Vector154, Vector158, Vector15C, -#endif -#if CORTEX_NUM_VECTORS > 72 - Vector160, Vector164, Vector168, Vector16C, -#endif -#if CORTEX_NUM_VECTORS > 76 - Vector170, Vector174, Vector178, Vector17C, -#endif -#if CORTEX_NUM_VECTORS > 80 - Vector180, Vector184, Vector188, Vector18C, -#endif -#if CORTEX_NUM_VECTORS > 84 - Vector190, Vector194, Vector198, Vector19C, -#endif -#if CORTEX_NUM_VECTORS > 88 - Vector1A0, Vector1A4, Vector1A8, Vector1AC, -#endif -#if CORTEX_NUM_VECTORS > 92 - Vector1B0, Vector1B4, Vector1B8, Vector1BC, -#endif -#if CORTEX_NUM_VECTORS > 96 - Vector1C0, Vector1C4, Vector1C8, Vector1CC, -#endif -#if CORTEX_NUM_VECTORS > 100 - Vector1D0, Vector1D4, Vector1D8, Vector1DC, -#endif -#if CORTEX_NUM_VECTORS > 104 - Vector1E0, Vector1E4, Vector1E8, Vector1EC, -#endif -#if CORTEX_NUM_VECTORS > 108 - Vector1F0, Vector1F4, Vector1F8, Vector1FC, -#endif -#if CORTEX_NUM_VECTORS > 112 - Vector200, Vector204, Vector208, Vector20C, -#endif -#if CORTEX_NUM_VECTORS > 116 - Vector210, Vector214, Vector218, Vector21C, -#endif -#if CORTEX_NUM_VECTORS > 120 - Vector220, Vector224, Vector228, Vector22C, -#endif -#if CORTEX_NUM_VECTORS > 124 - Vector230, Vector234, Vector238, Vector23C, -#endif -#if CORTEX_NUM_VECTORS > 128 - Vector240, Vector244, Vector248, Vector24C, -#endif -#if CORTEX_NUM_VECTORS > 132 - Vector250, Vector254, Vector258, Vector25C, -#endif -#if CORTEX_NUM_VECTORS > 136 - Vector260, Vector264, Vector268, Vector26C, -#endif -#if CORTEX_NUM_VECTORS > 140 - Vector270, Vector274, Vector278, Vector27C, -#endif -#if CORTEX_NUM_VECTORS > 144 - Vector280, Vector284, Vector288, Vector28C, -#endif -#if CORTEX_NUM_VECTORS > 148 - Vector290, Vector294, Vector298, Vector29C, -#endif -#if CORTEX_NUM_VECTORS > 152 - Vector2A0, Vector2A4, Vector2A8, Vector2AC, -#endif -#if CORTEX_NUM_VECTORS > 156 - Vector2B0, Vector2B4, Vector2B8, Vector2BC, -#endif -#if CORTEX_NUM_VECTORS > 160 - Vector2C0, Vector2C4, Vector2C8, Vector2CC, -#endif -#if CORTEX_NUM_VECTORS > 164 - Vector2D0, Vector2D4, Vector2D8, Vector2DC, -#endif -#if CORTEX_NUM_VECTORS > 168 - Vector2E0, Vector2E4, Vector2E8, Vector2EC, -#endif -#if CORTEX_NUM_VECTORS > 172 - Vector2F0, Vector2F4, Vector2F8, Vector2FC, -#endif -#if CORTEX_NUM_VECTORS > 176 - Vector300, Vector304, Vector308, Vector30C, -#endif -#if CORTEX_NUM_VECTORS > 180 - Vector310, Vector314, Vector318, Vector31C, -#endif -#if CORTEX_NUM_VECTORS > 184 - Vector320, Vector324, Vector328, Vector32C, -#endif -#if CORTEX_NUM_VECTORS > 188 - Vector330, Vector334, Vector338, Vector33C, -#endif -#if CORTEX_NUM_VECTORS > 192 - Vector340, Vector344, Vector348, Vector34C, -#endif -#if CORTEX_NUM_VECTORS > 196 - Vector350, Vector354, Vector358, Vector35C, -#endif -#if CORTEX_NUM_VECTORS > 200 - Vector360, Vector364, Vector368, Vector36C, -#endif -#if CORTEX_NUM_VECTORS > 204 - Vector370, Vector374, Vector378, Vector37C, -#endif -#if CORTEX_NUM_VECTORS > 208 - Vector380, Vector384, Vector388, Vector38C, -#endif -#if CORTEX_NUM_VECTORS > 212 - Vector390, Vector394, Vector398, Vector39C, -#endif -#if CORTEX_NUM_VECTORS > 216 - Vector3A0, Vector3A4, Vector3A8, Vector3AC, -#endif -#if CORTEX_NUM_VECTORS > 220 - Vector3B0, Vector3B4, Vector3B8, Vector3BC, -#endif -#if CORTEX_NUM_VECTORS > 224 - Vector3C0, Vector3C4, Vector3C8, Vector3CC, -#endif -#if CORTEX_NUM_VECTORS > 228 - Vector3D0, Vector3D4, Vector3D8, Vector3DC -#endif -#if CORTEX_NUM_VECTORS > 232 - Vector3E0, Vector3E4, Vector3E8, Vector3EC -#endif -#if CORTEX_NUM_VECTORS > 236 - Vector3F0, Vector3F4, Vector3F8, Vector3FC -#endif - } -}; - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/vectors.h b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/vectors.h deleted file mode 100644 index 2107063f2b..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/GCC/vectors.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file ARMCMx/compilers/GCC/vectors.h - * @brief Interrupt vectors for Cortex-Mx devices. - * - * @defgroup ARMCMx_VECTORS Cortex-Mx Interrupt Vectors - * @{ - */ - -#ifndef _VECTORS_H_ -#define _VECTORS_H_ - -#include "cmparams.h" - -/* This inclusion can be used to remap vectors using different names. - * Example: - * #define Vector7C UartRX_Handler - * This can be useful when using 3rd part libraries that assume specific - * vector names. - */ -#if defined(VECTORS_USE_CONF) -#include "vectorsconf.h" -#endif - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -#if !defined(_FROM_ASM_) -/** - * @brief Type of an IRQ vector. - */ -typedef void (*irq_vector_t)(void); - -/** - * @brief Type of a structure representing the whole vectors table. - */ -typedef struct { - uint32_t *init_stack; - irq_vector_t reset_handler; - irq_vector_t nmi_handler; - irq_vector_t hardfault_handler; - irq_vector_t memmanage_handler; - irq_vector_t busfault_handler; - irq_vector_t usagefault_handler; - irq_vector_t vector1c; - irq_vector_t vector20; - irq_vector_t vector24; - irq_vector_t vector28; - irq_vector_t svc_handler; - irq_vector_t debugmonitor_handler; - irq_vector_t vector34; - irq_vector_t pendsv_handler; - irq_vector_t systick_handler; - irq_vector_t vectors[CORTEX_NUM_VECTORS]; -} vectors_t; -#endif /* !defined(_FROM_ASM_) */ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(_FROM_ASM_) -extern vectors_t _vectors; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -#endif /* _VECTORS_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/IAR/cstartup.s b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/IAR/cstartup.s deleted file mode 100644 index 04d8922b9e..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/IAR/cstartup.s +++ /dev/null @@ -1,79 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file ARMCMx/IAR/cstartup.s - * @brief Generic IAR Cortex-Mx startup file. - * - * @addtogroup ARMCMx_IAR_STARTUP - * @{ - */ - -#if !defined(__DOXYGEN__) - - MODULE ?cstartup - -CONTROL_MODE_PRIVILEGED SET 0 -CONTROL_MODE_UNPRIVILEGED SET 1 -CONTROL_USE_MSP SET 0 -CONTROL_USE_PSP SET 2 - - AAPCS INTERWORK, VFP_COMPATIBLE, ROPI - PRESERVE8 - - SECTION .intvec:CODE:NOROOT(3) - - SECTION CSTACK:DATA:NOROOT(3) - PUBLIC __main_thread_stack_base__ -__main_thread_stack_base__: - PUBLIC __heap_end__ -__heap_end__: - - SECTION SYSHEAP:DATA:NOROOT(3) - PUBLIC __heap_base__ -__heap_base__: - - PUBLIC __iar_program_start - EXTERN __vector_table - EXTWEAK __iar_init_core - EXTWEAK __iar_init_vfp - EXTERN __cmain - - SECTION .text:CODE:REORDER(2) - REQUIRE __vector_table - THUMB -__iar_program_start: - cpsid i - ldr r0, =SFE(CSTACK) - msr PSP, r0 - movs r0, #CONTROL_MODE_PRIVILEGED | CONTROL_USE_PSP - msr CONTROL, r0 - isb - bl __early_init - bl __iar_init_core - bl __iar_init_vfp - b __cmain - - SECTION .text:CODE:NOROOT:REORDER(2) - PUBWEAK __early_init -__early_init: - bx lr - - END - -#endif /* !defined(__DOXYGEN__) */ - -/**< @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/IAR/vectors.s b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/IAR/vectors.s deleted file mode 100644 index e8bcd93eb7..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/IAR/vectors.s +++ /dev/null @@ -1,1006 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file ARMCMx/IAR/vectors.c - * @brief Interrupt vectors for Cortex-Mx devices. - * - * @defgroup ARMCMx_IAR_VECTORS Cortex-Mx Interrupt Vectors - * @{ - */ - -#define _FROM_ASM_ -#include "cmparams.h" - -#if !defined(__DOXYGEN__) - -#if (CORTEX_NUM_VECTORS & 7) != 0 -#error "the constant CORTEX_NUM_VECTORS must be a multiple of 8" -#endif - -#if (CORTEX_NUM_VECTORS < 8) || (CORTEX_NUM_VECTORS > 240) -#error "the constant CORTEX_NUM_VECTORS must be between 8 and 240 inclusive" -#endif - - MODULE ?vectors - - AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE - PRESERVE8 - - SECTION IRQSTACK:DATA:NOROOT(3) - SECTION .intvec:CODE:NOROOT(3) - - EXTERN __iar_program_start - PUBLIC __vector_table - - DATA - -__vector_table: - DCD SFE(IRQSTACK) - DCD __iar_program_start - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler - DCD Vector1C - DCD Vector20 - DCD Vector24 - DCD Vector28 - DCD SVC_Handler - DCD DebugMon_Handler - DCD Vector34 - DCD PendSV_Handler - DCD SysTick_Handler - DCD Vector40 - DCD Vector44 - DCD Vector48 - DCD Vector4C - DCD Vector50 - DCD Vector54 - DCD Vector58 - DCD Vector5C -#if CORTEX_NUM_VECTORS > 8 - DCD Vector60 - DCD Vector64 - DCD Vector68 - DCD Vector6C - DCD Vector70 - DCD Vector74 - DCD Vector78 - DCD Vector7C -#endif -#if CORTEX_NUM_VECTORS > 16 - DCD Vector80 - DCD Vector84 - DCD Vector88 - DCD Vector8C - DCD Vector90 - DCD Vector94 - DCD Vector98 - DCD Vector9C -#endif -#if CORTEX_NUM_VECTORS > 24 - DCD VectorA0 - DCD VectorA4 - DCD VectorA8 - DCD VectorAC - DCD VectorB0 - DCD VectorB4 - DCD VectorB8 - DCD VectorBC -#endif -#if CORTEX_NUM_VECTORS > 32 - DCD VectorC0 - DCD VectorC4 - DCD VectorC8 - DCD VectorCC - DCD VectorD0 - DCD VectorD4 - DCD VectorD8 - DCD VectorDC -#endif -#if CORTEX_NUM_VECTORS > 40 - DCD VectorE0 - DCD VectorE4 - DCD VectorE8 - DCD VectorEC - DCD VectorF0 - DCD VectorF4 - DCD VectorF8 - DCD VectorFC -#endif -#if CORTEX_NUM_VECTORS > 48 - DCD Vector100 - DCD Vector104 - DCD Vector108 - DCD Vector10C - DCD Vector110 - DCD Vector114 - DCD Vector118 - DCD Vector11C -#endif -#if CORTEX_NUM_VECTORS > 56 - DCD Vector120 - DCD Vector124 - DCD Vector128 - DCD Vector12C - DCD Vector130 - DCD Vector134 - DCD Vector138 - DCD Vector13C -#endif -#if CORTEX_NUM_VECTORS > 64 - DCD Vector140 - DCD Vector144 - DCD Vector148 - DCD Vector14C - DCD Vector150 - DCD Vector154 - DCD Vector158 - DCD Vector15C -#endif -#if CORTEX_NUM_VECTORS > 72 - DCD Vector160 - DCD Vector164 - DCD Vector168 - DCD Vector16C - DCD Vector170 - DCD Vector174 - DCD Vector178 - DCD Vector17C -#endif -#if CORTEX_NUM_VECTORS > 80 - DCD Vector180 - DCD Vector184 - DCD Vector188 - DCD Vector18C - DCD Vector190 - DCD Vector194 - DCD Vector198 - DCD Vector19C -#endif -#if CORTEX_NUM_VECTORS > 88 - DCD Vector1A0 - DCD Vector1A4 - DCD Vector1A8 - DCD Vector1AC - DCD Vector1B0 - DCD Vector1B4 - DCD Vector1B8 - DCD Vector1BC -#endif -#if CORTEX_NUM_VECTORS > 96 - DCD Vector1C0 - DCD Vector1C4 - DCD Vector1C8 - DCD Vector1CC - DCD Vector1D0 - DCD Vector1D4 - DCD Vector1D8 - DCD Vector1DC -#endif -#if CORTEX_NUM_VECTORS > 104 - DCD Vector1E0 - DCD Vector1E4 - DCD Vector1E8 - DCD Vector1EC - DCD Vector1F0 - DCD Vector1F4 - DCD Vector1F8 - DCD Vector1FC -#endif -#if CORTEX_NUM_VECTORS > 112 - DCD Vector200 - DCD Vector204 - DCD Vector208 - DCD Vector20C - DCD Vector210 - DCD Vector214 - DCD Vector218 - DCD Vector21C -#endif -#if CORTEX_NUM_VECTORS > 120 - DCD Vector220 - DCD Vector224 - DCD Vector228 - DCD Vector22C - DCD Vector230 - DCD Vector234 - DCD Vector238 - DCD Vector23C -#endif -#if CORTEX_NUM_VECTORS > 128 - DCD Vector240 - DCD Vector244 - DCD Vector248 - DCD Vector24C - DCD Vector250 - DCD Vector254 - DCD Vector258 - DCD Vector25C -#endif -#if CORTEX_NUM_VECTORS > 136 - DCD Vector260 - DCD Vector264 - DCD Vector268 - DCD Vector26C - DCD Vector270 - DCD Vector274 - DCD Vector278 - DCD Vector27C -#endif -#if CORTEX_NUM_VECTORS > 144 - DCD Vector280 - DCD Vector284 - DCD Vector288 - DCD Vector28C - DCD Vector290 - DCD Vector294 - DCD Vector298 - DCD Vector29C -#endif -#if CORTEX_NUM_VECTORS > 152 - DCD Vector2A0 - DCD Vector2A4 - DCD Vector2A8 - DCD Vector2AC - DCD Vector2B0 - DCD Vector2B4 - DCD Vector2B8 - DCD Vector2BC -#endif -#if CORTEX_NUM_VECTORS > 160 - DCD Vector2C0 - DCD Vector2C4 - DCD Vector2C8 - DCD Vector2CC - DCD Vector2D0 - DCD Vector2D4 - DCD Vector2D8 - DCD Vector2DC -#endif -#if CORTEX_NUM_VECTORS > 168 - DCD Vector2E0 - DCD Vector2E4 - DCD Vector2E8 - DCD Vector2EC - DCD Vector2F0 - DCD Vector2F4 - DCD Vector2F8 - DCD Vector2FC -#endif -#if CORTEX_NUM_VECTORS > 176 - DCD Vector300 - DCD Vector304 - DCD Vector308 - DCD Vector30C - DCD Vector310 - DCD Vector314 - DCD Vector318 - DCD Vector31C -#endif -#if CORTEX_NUM_VECTORS > 184 - DCD Vector320 - DCD Vector324 - DCD Vector328 - DCD Vector32C - DCD Vector330 - DCD Vector334 - DCD Vector338 - DCD Vector33C -#endif -#if CORTEX_NUM_VECTORS > 192 - DCD Vector340 - DCD Vector344 - DCD Vector348 - DCD Vector34C - DCD Vector350 - DCD Vector354 - DCD Vector358 - DCD Vector35C -#endif -#if CORTEX_NUM_VECTORS > 200 - DCD Vector360 - DCD Vector364 - DCD Vector368 - DCD Vector36C - DCD Vector370 - DCD Vector374 - DCD Vector378 - DCD Vector37C -#endif -#if CORTEX_NUM_VECTORS > 208 - DCD Vector380 - DCD Vector384 - DCD Vector388 - DCD Vector38C - DCD Vector390 - DCD Vector394 - DCD Vector398 - DCD Vector39C -#endif -#if CORTEX_NUM_VECTORS > 216 - DCD Vector3A0 - DCD Vector3A4 - DCD Vector3A8 - DCD Vector3AC - DCD Vector3B0 - DCD Vector3B4 - DCD Vector3B8 - DCD Vector3BC -#endif -#if CORTEX_NUM_VECTORS > 224 - DCD Vector3C0 - DCD Vector3C4 - DCD Vector3C8 - DCD Vector3CC - DCD Vector3D0 - DCD Vector3D4 - DCD Vector3D8 - DCD Vector3DC -#endif -#if CORTEX_NUM_VECTORS > 232 - DCD Vector3E0 - DCD Vector3E4 - DCD Vector3E8 - DCD Vector3EC - DCD Vector3F0 - DCD Vector3F4 - DCD Vector3F8 - DCD Vector3FC -#endif - -/* - * Default interrupt handlers. - */ - PUBWEAK NMI_Handler - PUBWEAK HardFault_Handler - PUBWEAK MemManage_Handler - PUBWEAK BusFault_Handler - PUBWEAK UsageFault_Handler - PUBWEAK Vector1C - PUBWEAK Vector20 - PUBWEAK Vector24 - PUBWEAK Vector28 - PUBWEAK SVC_Handler - PUBWEAK DebugMon_Handler - PUBWEAK Vector34 - PUBWEAK PendSV_Handler - PUBWEAK SysTick_Handler - PUBWEAK Vector40 - PUBWEAK Vector44 - PUBWEAK Vector48 - PUBWEAK Vector4C - PUBWEAK Vector50 - PUBWEAK Vector54 - PUBWEAK Vector58 - PUBWEAK Vector5C -#if CORTEX_NUM_VECTORS > 8 - PUBWEAK Vector60 - PUBWEAK Vector64 - PUBWEAK Vector68 - PUBWEAK Vector6C - PUBWEAK Vector70 - PUBWEAK Vector74 - PUBWEAK Vector78 - PUBWEAK Vector7C -#endif -#if CORTEX_NUM_VECTORS > 16 - PUBWEAK Vector80 - PUBWEAK Vector84 - PUBWEAK Vector88 - PUBWEAK Vector8C - PUBWEAK Vector90 - PUBWEAK Vector94 - PUBWEAK Vector98 - PUBWEAK Vector9C -#endif -#if CORTEX_NUM_VECTORS > 24 - PUBWEAK VectorA0 - PUBWEAK VectorA4 - PUBWEAK VectorA8 - PUBWEAK VectorAC - PUBWEAK VectorB0 - PUBWEAK VectorB4 - PUBWEAK VectorB8 - PUBWEAK VectorBC -#endif -#if CORTEX_NUM_VECTORS > 32 - PUBWEAK VectorC0 - PUBWEAK VectorC4 - PUBWEAK VectorC8 - PUBWEAK VectorCC - PUBWEAK VectorD0 - PUBWEAK VectorD4 - PUBWEAK VectorD8 - PUBWEAK VectorDC -#endif -#if CORTEX_NUM_VECTORS > 40 - PUBWEAK VectorE0 - PUBWEAK VectorE4 - PUBWEAK VectorE8 - PUBWEAK VectorEC - PUBWEAK VectorF0 - PUBWEAK VectorF4 - PUBWEAK VectorF8 - PUBWEAK VectorFC -#endif -#if CORTEX_NUM_VECTORS > 48 - PUBWEAK Vector100 - PUBWEAK Vector104 - PUBWEAK Vector108 - PUBWEAK Vector10C - PUBWEAK Vector110 - PUBWEAK Vector114 - PUBWEAK Vector118 - PUBWEAK Vector11C -#endif -#if CORTEX_NUM_VECTORS > 56 - PUBWEAK Vector120 - PUBWEAK Vector124 - PUBWEAK Vector128 - PUBWEAK Vector12C - PUBWEAK Vector130 - PUBWEAK Vector134 - PUBWEAK Vector138 - PUBWEAK Vector13C -#endif -#if CORTEX_NUM_VECTORS > 64 - PUBWEAK Vector140 - PUBWEAK Vector144 - PUBWEAK Vector148 - PUBWEAK Vector14C - PUBWEAK Vector150 - PUBWEAK Vector154 - PUBWEAK Vector158 - PUBWEAK Vector15C -#endif -#if CORTEX_NUM_VECTORS > 72 - PUBWEAK Vector160 - PUBWEAK Vector164 - PUBWEAK Vector168 - PUBWEAK Vector16C - PUBWEAK Vector170 - PUBWEAK Vector174 - PUBWEAK Vector178 - PUBWEAK Vector17C -#endif -#if CORTEX_NUM_VECTORS > 80 - PUBWEAK Vector180 - PUBWEAK Vector184 - PUBWEAK Vector188 - PUBWEAK Vector18C - PUBWEAK Vector190 - PUBWEAK Vector194 - PUBWEAK Vector198 - PUBWEAK Vector19C -#endif -#if CORTEX_NUM_VECTORS > 88 - PUBWEAK Vector1A0 - PUBWEAK Vector1A4 - PUBWEAK Vector1A8 - PUBWEAK Vector1AC - PUBWEAK Vector1B0 - PUBWEAK Vector1B4 - PUBWEAK Vector1B8 - PUBWEAK Vector1BC -#endif -#if CORTEX_NUM_VECTORS > 96 - PUBWEAK Vector1C0 - PUBWEAK Vector1C4 - PUBWEAK Vector1C8 - PUBWEAK Vector1CC - PUBWEAK Vector1D0 - PUBWEAK Vector1D4 - PUBWEAK Vector1D8 - PUBWEAK Vector1DC -#endif -#if CORTEX_NUM_VECTORS > 104 - PUBWEAK Vector1E0 - PUBWEAK Vector1E4 - PUBWEAK Vector1E8 - PUBWEAK Vector1EC - PUBWEAK Vector1F0 - PUBWEAK Vector1F4 - PUBWEAK Vector1F8 - PUBWEAK Vector1FC -#endif -#if CORTEX_NUM_VECTORS > 112 - PUBWEAK Vector200 - PUBWEAK Vector204 - PUBWEAK Vector208 - PUBWEAK Vector20C - PUBWEAK Vector210 - PUBWEAK Vector214 - PUBWEAK Vector218 - PUBWEAK Vector21C -#endif -#if CORTEX_NUM_VECTORS > 120 - PUBWEAK Vector220 - PUBWEAK Vector224 - PUBWEAK Vector228 - PUBWEAK Vector22C - PUBWEAK Vector230 - PUBWEAK Vector234 - PUBWEAK Vector238 - PUBWEAK Vector23C -#endif -#if CORTEX_NUM_VECTORS > 128 - PUBWEAK Vector240 - PUBWEAK Vector244 - PUBWEAK Vector248 - PUBWEAK Vector24C - PUBWEAK Vector250 - PUBWEAK Vector254 - PUBWEAK Vector258 - PUBWEAK Vector25C -#endif -#if CORTEX_NUM_VECTORS > 136 - PUBWEAK Vector260 - PUBWEAK Vector264 - PUBWEAK Vector268 - PUBWEAK Vector26C - PUBWEAK Vector270 - PUBWEAK Vector274 - PUBWEAK Vector278 - PUBWEAK Vector27C -#endif -#if CORTEX_NUM_VECTORS > 144 - PUBWEAK Vector280 - PUBWEAK Vector284 - PUBWEAK Vector288 - PUBWEAK Vector28C - PUBWEAK Vector290 - PUBWEAK Vector294 - PUBWEAK Vector298 - PUBWEAK Vector29C -#endif -#if CORTEX_NUM_VECTORS > 152 - PUBWEAK Vector2A0 - PUBWEAK Vector2A4 - PUBWEAK Vector2A8 - PUBWEAK Vector2AC - PUBWEAK Vector2B0 - PUBWEAK Vector2B4 - PUBWEAK Vector2B8 - PUBWEAK Vector2BC -#endif -#if CORTEX_NUM_VECTORS > 160 - PUBWEAK Vector2C0 - PUBWEAK Vector2C4 - PUBWEAK Vector2C8 - PUBWEAK Vector2CC - PUBWEAK Vector2D0 - PUBWEAK Vector2D4 - PUBWEAK Vector2D8 - PUBWEAK Vector2DC -#endif -#if CORTEX_NUM_VECTORS > 168 - PUBWEAK Vector2E0 - PUBWEAK Vector2E4 - PUBWEAK Vector2E8 - PUBWEAK Vector2EC - PUBWEAK Vector2F0 - PUBWEAK Vector2F4 - PUBWEAK Vector2F8 - PUBWEAK Vector2FC -#endif -#if CORTEX_NUM_VECTORS > 176 - PUBWEAK Vector300 - PUBWEAK Vector304 - PUBWEAK Vector308 - PUBWEAK Vector30C - PUBWEAK Vector310 - PUBWEAK Vector314 - PUBWEAK Vector318 - PUBWEAK Vector31C -#endif -#if CORTEX_NUM_VECTORS > 184 - PUBWEAK Vector320 - PUBWEAK Vector324 - PUBWEAK Vector328 - PUBWEAK Vector32C - PUBWEAK Vector330 - PUBWEAK Vector334 - PUBWEAK Vector338 - PUBWEAK Vector33C -#endif -#if CORTEX_NUM_VECTORS > 192 - PUBWEAK Vector340 - PUBWEAK Vector344 - PUBWEAK Vector348 - PUBWEAK Vector34C - PUBWEAK Vector350 - PUBWEAK Vector354 - PUBWEAK Vector358 - PUBWEAK Vector35C -#endif -#if CORTEX_NUM_VECTORS > 200 - PUBWEAK Vector360 - PUBWEAK Vector364 - PUBWEAK Vector368 - PUBWEAK Vector36C - PUBWEAK Vector370 - PUBWEAK Vector374 - PUBWEAK Vector378 - PUBWEAK Vector37C -#endif -#if CORTEX_NUM_VECTORS > 208 - PUBWEAK Vector380 - PUBWEAK Vector384 - PUBWEAK Vector388 - PUBWEAK Vector38C - PUBWEAK Vector390 - PUBWEAK Vector394 - PUBWEAK Vector398 - PUBWEAK Vector39C -#endif -#if CORTEX_NUM_VECTORS > 216 - PUBWEAK Vector3A0 - PUBWEAK Vector3A4 - PUBWEAK Vector3A8 - PUBWEAK Vector3AC - PUBWEAK Vector3B0 - PUBWEAK Vector3B4 - PUBWEAK Vector3B8 - PUBWEAK Vector3BC -#endif -#if CORTEX_NUM_VECTORS > 224 - PUBWEAK Vector3C0 - PUBWEAK Vector3C4 - PUBWEAK Vector3C8 - PUBWEAK Vector3CC - PUBWEAK Vector3D0 - PUBWEAK Vector3D4 - PUBWEAK Vector3D8 - PUBWEAK Vector3DC -#endif -#if CORTEX_NUM_VECTORS > 232 - PUBWEAK Vector3E0 - PUBWEAK Vector3E4 - PUBWEAK Vector3E8 - PUBWEAK Vector3EC - PUBWEAK Vector3F0 - PUBWEAK Vector3F4 - PUBWEAK Vector3F8 - PUBWEAK Vector3FC -#endif - PUBLIC _unhandled_exception - - SECTION .text:CODE:NOROOT:REORDER(1) - THUMB - -NMI_Handler -HardFault_Handler -MemManage_Handler -BusFault_Handler -UsageFault_Handler -Vector1C -Vector20 -Vector24 -Vector28 -SVC_Handler -DebugMon_Handler -Vector34 -PendSV_Handler -SysTick_Handler -Vector40 -Vector44 -Vector48 -Vector4C -Vector50 -Vector54 -Vector58 -Vector5C -#if CORTEX_NUM_VECTORS > 8 -Vector60 -Vector64 -Vector68 -Vector6C -Vector70 -Vector74 -Vector78 -Vector7C -#endif -#if CORTEX_NUM_VECTORS > 16 -Vector80 -Vector84 -Vector88 -Vector8C -Vector90 -Vector94 -Vector98 -Vector9C -#endif -#if CORTEX_NUM_VECTORS > 24 -VectorA0 -VectorA4 -VectorA8 -VectorAC -VectorB0 -VectorB4 -VectorB8 -VectorBC -#endif -#if CORTEX_NUM_VECTORS > 32 -VectorC0 -VectorC4 -VectorC8 -VectorCC -VectorD0 -VectorD4 -VectorD8 -VectorDC -#endif -#if CORTEX_NUM_VECTORS > 40 -VectorE0 -VectorE4 -VectorE8 -VectorEC -VectorF0 -VectorF4 -VectorF8 -VectorFC -#endif -#if CORTEX_NUM_VECTORS > 48 -Vector100 -Vector104 -Vector108 -Vector10C -Vector110 -Vector114 -Vector118 -Vector11C -#endif -#if CORTEX_NUM_VECTORS > 56 -Vector120 -Vector124 -Vector128 -Vector12C -Vector130 -Vector134 -Vector138 -Vector13C -#endif -#if CORTEX_NUM_VECTORS > 64 -Vector140 -Vector144 -Vector148 -Vector14C -Vector150 -Vector154 -Vector158 -Vector15C -#endif -#if CORTEX_NUM_VECTORS > 72 -Vector160 -Vector164 -Vector168 -Vector16C -Vector170 -Vector174 -Vector178 -Vector17C -#endif -#if CORTEX_NUM_VECTORS > 80 -Vector180 -Vector184 -Vector188 -Vector18C -Vector190 -Vector194 -Vector198 -Vector19C -#endif -#if CORTEX_NUM_VECTORS > 88 -Vector1A0 -Vector1A4 -Vector1A8 -Vector1AC -Vector1B0 -Vector1B4 -Vector1B8 -Vector1BC -#endif -#if CORTEX_NUM_VECTORS > 96 -Vector1C0 -Vector1C4 -Vector1C8 -Vector1CC -Vector1D0 -Vector1D4 -Vector1D8 -Vector1DC -#endif -#if CORTEX_NUM_VECTORS > 104 -Vector1E0 -Vector1E4 -Vector1E8 -Vector1EC -Vector1F0 -Vector1F4 -Vector1F8 -Vector1FC -#endif -#if CORTEX_NUM_VECTORS > 112 -Vector200 -Vector204 -Vector208 -Vector20C -Vector210 -Vector214 -Vector218 -Vector21C -#endif -#if CORTEX_NUM_VECTORS > 120 -Vector220 -Vector224 -Vector228 -Vector22C -Vector230 -Vector234 -Vector238 -Vector23C -#endif -#if CORTEX_NUM_VECTORS > 128 -Vector240 -Vector244 -Vector248 -Vector24C -Vector250 -Vector254 -Vector258 -Vector25C -#endif -#if CORTEX_NUM_VECTORS > 136 -Vector260 -Vector264 -Vector268 -Vector26C -Vector270 -Vector274 -Vector278 -Vector27C -#endif -#if CORTEX_NUM_VECTORS > 144 -Vector280 -Vector284 -Vector288 -Vector28C -Vector290 -Vector294 -Vector298 -Vector29C -#endif -#if CORTEX_NUM_VECTORS > 152 -Vector2A0 -Vector2A4 -Vector2A8 -Vector2AC -Vector2B0 -Vector2B4 -Vector2B8 -Vector2BC -#endif -#if CORTEX_NUM_VECTORS > 160 -Vector2C0 -Vector2C4 -Vector2C8 -Vector2CC -Vector2D0 -Vector2D4 -Vector2D8 -Vector2DC -#endif -#if CORTEX_NUM_VECTORS > 168 -Vector2E0 -Vector2E4 -Vector2E8 -Vector2EC -Vector2F0 -Vector2F4 -Vector2F8 -Vector2FC -#endif -#if CORTEX_NUM_VECTORS > 176 -Vector300 -Vector304 -Vector308 -Vector30C -Vector310 -Vector314 -Vector318 -Vector31C -#endif -#if CORTEX_NUM_VECTORS > 184 -Vector320 -Vector324 -Vector328 -Vector32C -Vector330 -Vector334 -Vector338 -Vector33C -#endif -#if CORTEX_NUM_VECTORS > 192 -Vector340 -Vector344 -Vector348 -Vector34C -Vector350 -Vector354 -Vector358 -Vector35C -#endif -#if CORTEX_NUM_VECTORS > 200 -Vector360 -Vector364 -Vector368 -Vector36C -Vector370 -Vector374 -Vector378 -Vector37C -#endif -#if CORTEX_NUM_VECTORS > 208 -Vector380 -Vector384 -Vector388 -Vector38C -Vector390 -Vector394 -Vector398 -Vector39C -#endif -#if CORTEX_NUM_VECTORS > 216 -Vector3A0 -Vector3A4 -Vector3A8 -Vector3AC -Vector3B0 -Vector3B4 -Vector3B8 -Vector3BC -#endif -#if CORTEX_NUM_VECTORS > 224 -Vector3C0 -Vector3C4 -Vector3C8 -Vector3CC -Vector3D0 -Vector3D4 -Vector3D8 -Vector3DC -#endif -#if CORTEX_NUM_VECTORS > 232 -Vector3E0 -Vector3E4 -Vector3E8 -Vector3EC -Vector3F0 -Vector3F4 -Vector3F8 -Vector3FC -#endif -_unhandled_exception - b _unhandled_exception - - END - -#endif /* !defined(__DOXYGEN__) */ - -/**< @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/RVCT/cstartup.s b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/RVCT/cstartup.s deleted file mode 100644 index 8726254378..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/RVCT/cstartup.s +++ /dev/null @@ -1,131 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file ARMCMx/RVCT/cstartup.s - * @brief Generic RVCT Cortex-Mx startup file. - * - * @addtogroup ARMCMx_RVCT_STARTUP - * @{ - */ - -#if !defined(__DOXYGEN__) - -;/* <<< Use Configuration Wizard in Context Menu >>> */ - -;// Main Stack Configuration (IRQ Stack) -;// Main Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -;// -main_stack_size EQU 0x00000400 - -;// Process Stack Configuration -;// Process Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -;// -proc_stack_size EQU 0x00000400 - -;// C-runtime heap size -;// C-runtime heap size (in Bytes) <0x0-0xFFFFFFFF:8> -;// -heap_size EQU 0x00000400 - - AREA MSTACK, NOINIT, READWRITE, ALIGN=3 -main_stack_mem SPACE main_stack_size - EXPORT __initial_msp -__initial_msp - - AREA CSTACK, NOINIT, READWRITE, ALIGN=3 -__main_thread_stack_base__ - EXPORT __main_thread_stack_base__ -proc_stack_mem SPACE proc_stack_size - EXPORT __initial_sp -__initial_sp - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE heap_size -__heap_limit - -CONTROL_MODE_PRIVILEGED EQU 0 -CONTROL_MODE_UNPRIVILEGED EQU 1 -CONTROL_USE_MSP EQU 0 -CONTROL_USE_PSP EQU 2 - - PRESERVE8 - THUMB - - AREA |.text|, CODE, READONLY - -/* - * Reset handler. - */ - IMPORT __main - EXPORT Reset_Handler -Reset_Handler PROC - cpsid i - ldr r0, =__initial_sp - msr PSP, r0 - movs r0, #CONTROL_MODE_PRIVILEGED :OR: CONTROL_USE_PSP - msr CONTROL, r0 - isb - bl __early_init - - IF {CPU} = "Cortex-M4.fp" - LDR R0, =0xE000ED88 ; Enable CP10,CP11 - LDR R1, [R0] - ORR R1, R1, #(0xF << 20) - STR R1, [R0] - ENDIF - - ldr r0, =__main - bx r0 - ENDP - -__early_init PROC - EXPORT __early_init [WEAK] - bx lr - ENDP - - ALIGN - -/* - * User Initial Stack & Heap. - */ - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - ldr r0, =Heap_Mem - ldr r1, =(proc_stack_mem + proc_stack_size) - ldr r2, =(Heap_Mem + heap_size) - ldr r3, =proc_stack_mem - bx lr - - ALIGN - - ENDIF - - END - -#endif /* !defined(__DOXYGEN__) */ - -/**< @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/RVCT/vectors.s b/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/RVCT/vectors.s deleted file mode 100644 index ec882ad24b..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/compilers/RVCT/vectors.s +++ /dev/null @@ -1,1002 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file ARMCMx/RVCT/vectors.c - * @brief Interrupt vectors for Cortex-Mx devices. - * - * @defgroup ARMCMx_RVCT_VECTORS Cortex-Mx Interrupt Vectors - * @{ - */ - -#define _FROM_ASM_ -#include "cmparams.h" - -#if !defined(__DOXYGEN__) - -#if (CORTEX_NUM_VECTORS & 7) != 0 -#error "the constant CORTEX_NUM_VECTORS must be a multiple of 8" -#endif - -#if (CORTEX_NUM_VECTORS < 8) || (CORTEX_NUM_VECTORS > 240) -#error "the constant CORTEX_NUM_VECTORS must be between 8 and 240 inclusive" -#endif - - PRESERVE8 - - AREA RESET, DATA, READONLY - - IMPORT __initial_msp - IMPORT Reset_Handler - EXPORT __Vectors - -__Vectors - DCD __initial_msp - DCD Reset_Handler - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler - DCD Vector1C - DCD Vector20 - DCD Vector24 - DCD Vector28 - DCD SVC_Handler - DCD DebugMon_Handler - DCD Vector34 - DCD PendSV_Handler - DCD SysTick_Handler - DCD Vector40 - DCD Vector44 - DCD Vector48 - DCD Vector4C - DCD Vector50 - DCD Vector54 - DCD Vector58 - DCD Vector5C -#if CORTEX_NUM_VECTORS > 8 - DCD Vector60 - DCD Vector64 - DCD Vector68 - DCD Vector6C - DCD Vector70 - DCD Vector74 - DCD Vector78 - DCD Vector7C -#endif -#if CORTEX_NUM_VECTORS > 16 - DCD Vector80 - DCD Vector84 - DCD Vector88 - DCD Vector8C - DCD Vector90 - DCD Vector94 - DCD Vector98 - DCD Vector9C -#endif -#if CORTEX_NUM_VECTORS > 24 - DCD VectorA0 - DCD VectorA4 - DCD VectorA8 - DCD VectorAC - DCD VectorB0 - DCD VectorB4 - DCD VectorB8 - DCD VectorBC -#endif -#if CORTEX_NUM_VECTORS > 32 - DCD VectorC0 - DCD VectorC4 - DCD VectorC8 - DCD VectorCC - DCD VectorD0 - DCD VectorD4 - DCD VectorD8 - DCD VectorDC -#endif -#if CORTEX_NUM_VECTORS > 40 - DCD VectorE0 - DCD VectorE4 - DCD VectorE8 - DCD VectorEC - DCD VectorF0 - DCD VectorF4 - DCD VectorF8 - DCD VectorFC -#endif -#if CORTEX_NUM_VECTORS > 48 - DCD Vector100 - DCD Vector104 - DCD Vector108 - DCD Vector10C - DCD Vector110 - DCD Vector114 - DCD Vector118 - DCD Vector11C -#endif -#if CORTEX_NUM_VECTORS > 56 - DCD Vector120 - DCD Vector124 - DCD Vector128 - DCD Vector12C - DCD Vector130 - DCD Vector134 - DCD Vector138 - DCD Vector13C -#endif -#if CORTEX_NUM_VECTORS > 64 - DCD Vector140 - DCD Vector144 - DCD Vector148 - DCD Vector14C - DCD Vector150 - DCD Vector154 - DCD Vector158 - DCD Vector15C -#endif -#if CORTEX_NUM_VECTORS > 72 - DCD Vector160 - DCD Vector164 - DCD Vector168 - DCD Vector16C - DCD Vector170 - DCD Vector174 - DCD Vector178 - DCD Vector17C -#endif -#if CORTEX_NUM_VECTORS > 80 - DCD Vector180 - DCD Vector184 - DCD Vector188 - DCD Vector18C - DCD Vector190 - DCD Vector194 - DCD Vector198 - DCD Vector19C -#endif -#if CORTEX_NUM_VECTORS > 88 - DCD Vector1A0 - DCD Vector1A4 - DCD Vector1A8 - DCD Vector1AC - DCD Vector1B0 - DCD Vector1B4 - DCD Vector1B8 - DCD Vector1BC -#endif -#if CORTEX_NUM_VECTORS > 96 - DCD Vector1C0 - DCD Vector1C4 - DCD Vector1C8 - DCD Vector1CC - DCD Vector1D0 - DCD Vector1D4 - DCD Vector1D8 - DCD Vector1DC -#endif -#if CORTEX_NUM_VECTORS > 104 - DCD Vector1E0 - DCD Vector1E4 - DCD Vector1E8 - DCD Vector1EC - DCD Vector1F0 - DCD Vector1F4 - DCD Vector1F8 - DCD Vector1FC -#endif -#if CORTEX_NUM_VECTORS > 112 - DCD Vector200 - DCD Vector204 - DCD Vector208 - DCD Vector20C - DCD Vector210 - DCD Vector214 - DCD Vector218 - DCD Vector21C -#endif -#if CORTEX_NUM_VECTORS > 120 - DCD Vector220 - DCD Vector224 - DCD Vector228 - DCD Vector22C - DCD Vector230 - DCD Vector234 - DCD Vector238 - DCD Vector23C -#endif -#if CORTEX_NUM_VECTORS > 128 - DCD Vector240 - DCD Vector244 - DCD Vector248 - DCD Vector24C - DCD Vector250 - DCD Vector254 - DCD Vector258 - DCD Vector25C -#endif -#if CORTEX_NUM_VECTORS > 136 - DCD Vector260 - DCD Vector264 - DCD Vector268 - DCD Vector26C - DCD Vector270 - DCD Vector274 - DCD Vector278 - DCD Vector27C -#endif -#if CORTEX_NUM_VECTORS > 144 - DCD Vector280 - DCD Vector284 - DCD Vector288 - DCD Vector28C - DCD Vector290 - DCD Vector294 - DCD Vector298 - DCD Vector29C -#endif -#if CORTEX_NUM_VECTORS > 152 - DCD Vector2A0 - DCD Vector2A4 - DCD Vector2A8 - DCD Vector2AC - DCD Vector2B0 - DCD Vector2B4 - DCD Vector2B8 - DCD Vector2BC -#endif -#if CORTEX_NUM_VECTORS > 160 - DCD Vector2C0 - DCD Vector2C4 - DCD Vector2C8 - DCD Vector2CC - DCD Vector2D0 - DCD Vector2D4 - DCD Vector2D8 - DCD Vector2DC -#endif -#if CORTEX_NUM_VECTORS > 168 - DCD Vector2E0 - DCD Vector2E4 - DCD Vector2E8 - DCD Vector2EC - DCD Vector2F0 - DCD Vector2F4 - DCD Vector2F8 - DCD Vector2FC -#endif -#if CORTEX_NUM_VECTORS > 176 - DCD Vector300 - DCD Vector304 - DCD Vector308 - DCD Vector30C - DCD Vector310 - DCD Vector314 - DCD Vector318 - DCD Vector31C -#endif -#if CORTEX_NUM_VECTORS > 184 - DCD Vector320 - DCD Vector324 - DCD Vector328 - DCD Vector32C - DCD Vector330 - DCD Vector334 - DCD Vector338 - DCD Vector33C -#endif -#if CORTEX_NUM_VECTORS > 192 - DCD Vector340 - DCD Vector344 - DCD Vector348 - DCD Vector34C - DCD Vector350 - DCD Vector354 - DCD Vector358 - DCD Vector35C -#endif -#if CORTEX_NUM_VECTORS > 200 - DCD Vector360 - DCD Vector364 - DCD Vector368 - DCD Vector36C - DCD Vector370 - DCD Vector374 - DCD Vector378 - DCD Vector37C -#endif -#if CORTEX_NUM_VECTORS > 208 - DCD Vector380 - DCD Vector384 - DCD Vector388 - DCD Vector38C - DCD Vector390 - DCD Vector394 - DCD Vector398 - DCD Vector39C -#endif -#if CORTEX_NUM_VECTORS > 216 - DCD Vector3A0 - DCD Vector3A4 - DCD Vector3A8 - DCD Vector3AC - DCD Vector3B0 - DCD Vector3B4 - DCD Vector3B8 - DCD Vector3BC -#endif -#if CORTEX_NUM_VECTORS > 224 - DCD Vector3C0 - DCD Vector3C4 - DCD Vector3C8 - DCD Vector3CC - DCD Vector3D0 - DCD Vector3D4 - DCD Vector3D8 - DCD Vector3DC -#endif -#if CORTEX_NUM_VECTORS > 232 - DCD Vector3E0 - DCD Vector3E4 - DCD Vector3E8 - DCD Vector3EC - DCD Vector3F0 - DCD Vector3F4 - DCD Vector3F8 - DCD Vector3FC -#endif - - AREA |.text|, CODE, READONLY - THUMB - -/* - * Default interrupt handlers. - */ - EXPORT _unhandled_exception -_unhandled_exception PROC - EXPORT NMI_Handler [WEAK] - EXPORT HardFault_Handler [WEAK] - EXPORT MemManage_Handler [WEAK] - EXPORT BusFault_Handler [WEAK] - EXPORT UsageFault_Handler [WEAK] - EXPORT Vector1C [WEAK] - EXPORT Vector20 [WEAK] - EXPORT Vector24 [WEAK] - EXPORT Vector28 [WEAK] - EXPORT SVC_Handler [WEAK] - EXPORT DebugMon_Handler [WEAK] - EXPORT Vector34 [WEAK] - EXPORT PendSV_Handler [WEAK] - EXPORT SysTick_Handler [WEAK] - EXPORT Vector40 [WEAK] - EXPORT Vector44 [WEAK] - EXPORT Vector48 [WEAK] - EXPORT Vector4C [WEAK] - EXPORT Vector50 [WEAK] - EXPORT Vector54 [WEAK] - EXPORT Vector58 [WEAK] - EXPORT Vector5C [WEAK] -#if CORTEX_NUM_VECTORS > 8 - EXPORT Vector60 [WEAK] - EXPORT Vector64 [WEAK] - EXPORT Vector68 [WEAK] - EXPORT Vector6C [WEAK] - EXPORT Vector70 [WEAK] - EXPORT Vector74 [WEAK] - EXPORT Vector78 [WEAK] - EXPORT Vector7C [WEAK] -#endif -#if CORTEX_NUM_VECTORS > 16 - EXPORT Vector80 [WEAK] - EXPORT Vector84 [WEAK] - EXPORT Vector88 [WEAK] - EXPORT Vector8C [WEAK] - EXPORT Vector90 [WEAK] - EXPORT Vector94 [WEAK] - EXPORT Vector98 [WEAK] - EXPORT Vector9C [WEAK] -#endif -#if CORTEX_NUM_VECTORS > 24 - EXPORT VectorA0 [WEAK] - EXPORT VectorA4 [WEAK] - EXPORT VectorA8 [WEAK] - EXPORT VectorAC [WEAK] - EXPORT VectorB0 [WEAK] - EXPORT VectorB4 [WEAK] - EXPORT VectorB8 [WEAK] - EXPORT VectorBC [WEAK] -#endif -#if CORTEX_NUM_VECTORS > 32 - EXPORT VectorC0 [WEAK] - EXPORT VectorC4 [WEAK] - EXPORT VectorC8 [WEAK] - EXPORT VectorCC [WEAK] - EXPORT VectorD0 [WEAK] - EXPORT VectorD4 [WEAK] - EXPORT VectorD8 [WEAK] - EXPORT VectorDC [WEAK] -#endif -#if CORTEX_NUM_VECTORS > 40 - EXPORT VectorE0 [WEAK] - EXPORT VectorE4 [WEAK] - EXPORT VectorE8 [WEAK] - EXPORT VectorEC [WEAK] - EXPORT VectorF0 [WEAK] - EXPORT VectorF4 [WEAK] - EXPORT VectorF8 [WEAK] - EXPORT VectorFC [WEAK] -#endif -#if CORTEX_NUM_VECTORS > 48 - EXPORT Vector100 [WEAK] - EXPORT Vector104 [WEAK] - EXPORT Vector108 [WEAK] - EXPORT Vector10C [WEAK] - EXPORT Vector110 [WEAK] - EXPORT Vector114 [WEAK] - EXPORT Vector118 [WEAK] - EXPORT Vector11C [WEAK] -#endif -#if CORTEX_NUM_VECTORS > 56 - EXPORT Vector120 [WEAK] - EXPORT Vector124 [WEAK] - EXPORT Vector128 [WEAK] - EXPORT Vector12C [WEAK] - EXPORT Vector130 [WEAK] - EXPORT Vector134 [WEAK] - EXPORT Vector138 [WEAK] - EXPORT Vector13C [WEAK] -#endif -#if CORTEX_NUM_VECTORS > 64 - EXPORT Vector140 [WEAK] - EXPORT Vector144 [WEAK] - EXPORT Vector148 [WEAK] - EXPORT Vector14C [WEAK] - EXPORT Vector150 [WEAK] - EXPORT Vector154 [WEAK] - EXPORT Vector158 [WEAK] - EXPORT Vector15C [WEAK] -#endif -#if CORTEX_NUM_VECTORS > 72 - EXPORT Vector160 [WEAK] - EXPORT Vector164 [WEAK] - EXPORT Vector168 [WEAK] - EXPORT Vector16C [WEAK] - EXPORT Vector170 [WEAK] - EXPORT Vector174 [WEAK] - EXPORT Vector178 [WEAK] - EXPORT Vector17C [WEAK] -#endif -#if CORTEX_NUM_VECTORS > 80 - EXPORT Vector180 [WEAK] - EXPORT Vector184 [WEAK] - EXPORT Vector188 [WEAK] - EXPORT Vector18C [WEAK] - EXPORT Vector190 [WEAK] - EXPORT Vector194 [WEAK] - EXPORT Vector198 [WEAK] - EXPORT Vector19C [WEAK] -#endif -#if CORTEX_NUM_VECTORS > 88 - EXPORT Vector1A0 [WEAK] - EXPORT Vector1A4 [WEAK] - EXPORT Vector1A8 [WEAK] - EXPORT Vector1AC [WEAK] - EXPORT Vector1B0 [WEAK] - EXPORT Vector1B4 [WEAK] - EXPORT Vector1B8 [WEAK] - EXPORT Vector1BC [WEAK] -#endif -#if CORTEX_NUM_VECTORS > 96 - EXPORT Vector1C0 [WEAK] - EXPORT Vector1C4 [WEAK] - EXPORT Vector1C8 [WEAK] - EXPORT Vector1CC [WEAK] - EXPORT Vector1D0 [WEAK] - EXPORT Vector1D4 [WEAK] - EXPORT Vector1D8 [WEAK] - EXPORT Vector1DC [WEAK] -#endif -#if CORTEX_NUM_VECTORS > 104 - EXPORT Vector1E0 [WEAK] - EXPORT Vector1E4 [WEAK] - EXPORT Vector1E8 [WEAK] - EXPORT Vector1EC [WEAK] - EXPORT Vector1F0 [WEAK] - EXPORT Vector1F4 [WEAK] - EXPORT Vector1F8 [WEAK] - EXPORT Vector1FC [WEAK] -#endif -#if CORTEX_NUM_VECTORS > 112 - EXPORT Vector200 [WEAK] - EXPORT Vector204 [WEAK] - EXPORT Vector208 [WEAK] - EXPORT Vector20C [WEAK] - EXPORT Vector210 [WEAK] - EXPORT Vector214 [WEAK] - EXPORT Vector218 [WEAK] - EXPORT Vector21C [WEAK] -#endif -#if CORTEX_NUM_VECTORS > 120 - EXPORT Vector220 [WEAK] - EXPORT Vector224 [WEAK] - EXPORT Vector228 [WEAK] - EXPORT Vector22C [WEAK] - EXPORT Vector230 [WEAK] - EXPORT Vector234 [WEAK] - EXPORT Vector238 [WEAK] - EXPORT Vector23C [WEAK] -#endif -#if CORTEX_NUM_VECTORS > 128 - EXPORT Vector240 [WEAK] - EXPORT Vector244 [WEAK] - EXPORT Vector248 [WEAK] - EXPORT Vector24C [WEAK] - EXPORT Vector250 [WEAK] - EXPORT Vector254 [WEAK] - EXPORT Vector258 [WEAK] - EXPORT Vector25C [WEAK] -#endif -#if CORTEX_NUM_VECTORS > 136 - EXPORT Vector260 [WEAK] - EXPORT Vector264 [WEAK] - EXPORT Vector268 [WEAK] - EXPORT Vector26C [WEAK] - EXPORT Vector270 [WEAK] - EXPORT Vector274 [WEAK] - EXPORT Vector278 [WEAK] - EXPORT Vector27C [WEAK] -#endif -#if CORTEX_NUM_VECTORS > 144 - EXPORT Vector280 [WEAK] - EXPORT Vector284 [WEAK] - EXPORT Vector288 [WEAK] - EXPORT Vector28C [WEAK] - EXPORT Vector290 [WEAK] - EXPORT Vector294 [WEAK] - EXPORT Vector298 [WEAK] - EXPORT Vector29C [WEAK] -#endif -#if CORTEX_NUM_VECTORS > 152 - EXPORT Vector2A0 [WEAK] - EXPORT Vector2A4 [WEAK] - EXPORT Vector2A8 [WEAK] - EXPORT Vector2AC [WEAK] - EXPORT Vector2B0 [WEAK] - EXPORT Vector2B4 [WEAK] - EXPORT Vector2B8 [WEAK] - EXPORT Vector2BC [WEAK] -#endif -#if CORTEX_NUM_VECTORS > 160 - EXPORT Vector2C0 [WEAK] - EXPORT Vector2C4 [WEAK] - EXPORT Vector2C8 [WEAK] - EXPORT Vector2CC [WEAK] - EXPORT Vector2D0 [WEAK] - EXPORT Vector2D4 [WEAK] - EXPORT Vector2D8 [WEAK] - EXPORT Vector2DC [WEAK] -#endif -#if CORTEX_NUM_VECTORS > 168 - EXPORT Vector2E0 [WEAK] - EXPORT Vector2E4 [WEAK] - EXPORT Vector2E8 [WEAK] - EXPORT Vector2EC [WEAK] - EXPORT Vector2F0 [WEAK] - EXPORT Vector2F4 [WEAK] - EXPORT Vector2F8 [WEAK] - EXPORT Vector2FC [WEAK] -#endif -#if CORTEX_NUM_VECTORS > 176 - EXPORT Vector300 [WEAK] - EXPORT Vector304 [WEAK] - EXPORT Vector308 [WEAK] - EXPORT Vector30C [WEAK] - EXPORT Vector310 [WEAK] - EXPORT Vector314 [WEAK] - EXPORT Vector318 [WEAK] - EXPORT Vector31C [WEAK] -#endif -#if CORTEX_NUM_VECTORS > 184 - EXPORT Vector320 [WEAK] - EXPORT Vector324 [WEAK] - EXPORT Vector328 [WEAK] - EXPORT Vector32C [WEAK] - EXPORT Vector330 [WEAK] - EXPORT Vector334 [WEAK] - EXPORT Vector338 [WEAK] - EXPORT Vector33C [WEAK] -#endif -#if CORTEX_NUM_VECTORS > 192 - EXPORT Vector340 [WEAK] - EXPORT Vector344 [WEAK] - EXPORT Vector348 [WEAK] - EXPORT Vector34C [WEAK] - EXPORT Vector350 [WEAK] - EXPORT Vector354 [WEAK] - EXPORT Vector358 [WEAK] - EXPORT Vector35C [WEAK] -#endif -#if CORTEX_NUM_VECTORS > 200 - EXPORT Vector360 [WEAK] - EXPORT Vector364 [WEAK] - EXPORT Vector368 [WEAK] - EXPORT Vector36C [WEAK] - EXPORT Vector370 [WEAK] - EXPORT Vector374 [WEAK] - EXPORT Vector378 [WEAK] - EXPORT Vector37C [WEAK] -#endif -#if CORTEX_NUM_VECTORS > 208 - EXPORT Vector380 [WEAK] - EXPORT Vector384 [WEAK] - EXPORT Vector388 [WEAK] - EXPORT Vector38C [WEAK] - EXPORT Vector390 [WEAK] - EXPORT Vector394 [WEAK] - EXPORT Vector398 [WEAK] - EXPORT Vector39C [WEAK] -#endif -#if CORTEX_NUM_VECTORS > 216 - EXPORT Vector3A0 [WEAK] - EXPORT Vector3A4 [WEAK] - EXPORT Vector3A8 [WEAK] - EXPORT Vector3AC [WEAK] - EXPORT Vector3B0 [WEAK] - EXPORT Vector3B4 [WEAK] - EXPORT Vector3B8 [WEAK] - EXPORT Vector3BC [WEAK] -#endif -#if CORTEX_NUM_VECTORS > 224 - EXPORT Vector3C0 [WEAK] - EXPORT Vector3C4 [WEAK] - EXPORT Vector3C8 [WEAK] - EXPORT Vector3CC [WEAK] - EXPORT Vector3D0 [WEAK] - EXPORT Vector3D4 [WEAK] - EXPORT Vector3D8 [WEAK] - EXPORT Vector3DC [WEAK] -#endif -#if CORTEX_NUM_VECTORS > 232 - EXPORT Vector3E0 [WEAK] - EXPORT Vector3E4 [WEAK] - EXPORT Vector3E8 [WEAK] - EXPORT Vector3EC [WEAK] - EXPORT Vector3F0 [WEAK] - EXPORT Vector3F4 [WEAK] - EXPORT Vector3F8 [WEAK] - EXPORT Vector3FC [WEAK] -#endif - -NMI_Handler -HardFault_Handler -MemManage_Handler -BusFault_Handler -UsageFault_Handler -Vector1C -Vector20 -Vector24 -Vector28 -SVC_Handler -DebugMon_Handler -Vector34 -PendSV_Handler -SysTick_Handler -Vector40 -Vector44 -Vector48 -Vector4C -Vector50 -Vector54 -Vector58 -Vector5C -#if CORTEX_NUM_VECTORS > 8 -Vector60 -Vector64 -Vector68 -Vector6C -Vector70 -Vector74 -Vector78 -Vector7C -#endif -#if CORTEX_NUM_VECTORS > 16 -Vector80 -Vector84 -Vector88 -Vector8C -Vector90 -Vector94 -Vector98 -Vector9C -#endif -#if CORTEX_NUM_VECTORS > 24 -VectorA0 -VectorA4 -VectorA8 -VectorAC -VectorB0 -VectorB4 -VectorB8 -VectorBC -#endif -#if CORTEX_NUM_VECTORS > 32 -VectorC0 -VectorC4 -VectorC8 -VectorCC -VectorD0 -VectorD4 -VectorD8 -VectorDC -#endif -#if CORTEX_NUM_VECTORS > 40 -VectorE0 -VectorE4 -VectorE8 -VectorEC -VectorF0 -VectorF4 -VectorF8 -VectorFC -#endif -#if CORTEX_NUM_VECTORS > 48 -Vector100 -Vector104 -Vector108 -Vector10C -Vector110 -Vector114 -Vector118 -Vector11C -#endif -#if CORTEX_NUM_VECTORS > 56 -Vector120 -Vector124 -Vector128 -Vector12C -Vector130 -Vector134 -Vector138 -Vector13C -#endif -#if CORTEX_NUM_VECTORS > 64 -Vector140 -Vector144 -Vector148 -Vector14C -Vector150 -Vector154 -Vector158 -Vector15C -#endif -#if CORTEX_NUM_VECTORS > 72 -Vector160 -Vector164 -Vector168 -Vector16C -Vector170 -Vector174 -Vector178 -Vector17C -#endif -#if CORTEX_NUM_VECTORS > 80 -Vector180 -Vector184 -Vector188 -Vector18C -Vector190 -Vector194 -Vector198 -Vector19C -#endif -#if CORTEX_NUM_VECTORS > 88 -Vector1A0 -Vector1A4 -Vector1A8 -Vector1AC -Vector1B0 -Vector1B4 -Vector1B8 -Vector1BC -#endif -#if CORTEX_NUM_VECTORS > 96 -Vector1C0 -Vector1C4 -Vector1C8 -Vector1CC -Vector1D0 -Vector1D4 -Vector1D8 -Vector1DC -#endif -#if CORTEX_NUM_VECTORS > 104 -Vector1E0 -Vector1E4 -Vector1E8 -Vector1EC -Vector1F0 -Vector1F4 -Vector1F8 -Vector1FC -#endif -#if CORTEX_NUM_VECTORS > 112 -Vector200 -Vector204 -Vector208 -Vector20C -Vector210 -Vector214 -Vector218 -Vector21C -#endif -#if CORTEX_NUM_VECTORS > 120 -Vector220 -Vector224 -Vector228 -Vector22C -Vector230 -Vector234 -Vector238 -Vector23C -#endif -#if CORTEX_NUM_VECTORS > 128 -Vector240 -Vector244 -Vector248 -Vector24C -Vector250 -Vector254 -Vector258 -Vector25C -#endif -#if CORTEX_NUM_VECTORS > 136 -Vector260 -Vector264 -Vector268 -Vector26C -Vector270 -Vector274 -Vector278 -Vector27C -#endif -#if CORTEX_NUM_VECTORS > 144 -Vector280 -Vector284 -Vector288 -Vector28C -Vector290 -Vector294 -Vector298 -Vector29C -#endif -#if CORTEX_NUM_VECTORS > 152 -Vector2A0 -Vector2A4 -Vector2A8 -Vector2AC -Vector2B0 -Vector2B4 -Vector2B8 -Vector2BC -#endif -#if CORTEX_NUM_VECTORS > 160 -Vector2C0 -Vector2C4 -Vector2C8 -Vector2CC -Vector2D0 -Vector2D4 -Vector2D8 -Vector2DC -#endif -#if CORTEX_NUM_VECTORS > 168 -Vector2E0 -Vector2E4 -Vector2E8 -Vector2EC -Vector2F0 -Vector2F4 -Vector2F8 -Vector2FC -#endif -#if CORTEX_NUM_VECTORS > 176 -Vector300 -Vector304 -Vector308 -Vector30C -Vector310 -Vector314 -Vector318 -Vector31C -#endif -#if CORTEX_NUM_VECTORS > 184 -Vector320 -Vector324 -Vector328 -Vector32C -Vector330 -Vector334 -Vector338 -Vector33C -#endif -#if CORTEX_NUM_VECTORS > 192 -Vector340 -Vector344 -Vector348 -Vector34C -Vector350 -Vector354 -Vector358 -Vector35C -#endif -#if CORTEX_NUM_VECTORS > 200 -Vector360 -Vector364 -Vector368 -Vector36C -Vector370 -Vector374 -Vector378 -Vector37C -#endif -#if CORTEX_NUM_VECTORS > 208 -Vector380 -Vector384 -Vector388 -Vector38C -Vector390 -Vector394 -Vector398 -Vector39C -#endif -#if CORTEX_NUM_VECTORS > 216 -Vector3A0 -Vector3A4 -Vector3A8 -Vector3AC -Vector3B0 -Vector3B4 -Vector3B8 -Vector3BC -#endif -#if CORTEX_NUM_VECTORS > 224 -Vector3C0 -Vector3C4 -Vector3C8 -Vector3CC -Vector3D0 -Vector3D4 -Vector3D8 -Vector3DC -#endif -#if CORTEX_NUM_VECTORS > 232 -Vector3E0 -Vector3E4 -Vector3E8 -Vector3EC -Vector3F0 -Vector3F4 -Vector3F8 -Vector3FC -#endif - b _unhandled_exception - ENDP - - END - -#endif /* !defined(__DOXYGEN__) */ - -/**< @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/devices/K20x/cmparams.h b/firmware/ChibiOS_16/os/common/ports/ARMCMx/devices/K20x/cmparams.h deleted file mode 100644 index 5bcde6e22c..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/devices/K20x/cmparams.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file GCC/ARMCMx/MK20Dx/cmparams.h - * @brief ARM Cortex-M4 parameters for the Kinetis MK20Dx. - * - * @defgroup ARMCMx_MK20Dx Kinetis MK20Dx Specific Parameters - * @ingroup ARMCMx_SPECIFIC - * @details This file contains the Cortex-M4 specific parameters for the - * Kinetis MK20Dx platform. - * @{ - */ - -#ifndef _CMPARAMS_H_ -#define _CMPARAMS_H_ - -/** - * @brief Cortex core model. - */ -#define CORTEX_MODEL 4 - -/** - * @brief Systick unit presence. - */ -#define CORTEX_HAS_ST TRUE - -/** - * @brief Floating Point unit presence. - */ -#define CORTEX_HAS_FPU FALSE - -/** - * @brief Number of bits in priority masks. - */ -#define CORTEX_PRIORITY_BITS 4 - -/** - * @brief Number of interrupt vectors. - * @note This number does not include the 16 system vectors and must be - * rounded to a multiple of 8. - */ -#define CORTEX_NUM_VECTORS 48 - -/* The following code is not processed when the file is included from an - asm module.*/ -#if !defined(_FROM_ASM_) - -/* Including the device CMSIS header. Note, we are not using the definitions - from this header because we need this file to be usable also from - assembler source files. We verify that the info matches instead.*/ -#include "mk20d5.h" - -#if CORTEX_MODEL != __CORTEX_M -#error "CMSIS __CORTEX_M mismatch" -#endif - -#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS -#error "CMSIS __NVIC_PRIO_BITS mismatch" -#endif - -#endif /* !defined(_FROM_ASM_) */ - -#endif /* _CMPARAMS_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/devices/KL2x/cmparams.h b/firmware/ChibiOS_16/os/common/ports/ARMCMx/devices/KL2x/cmparams.h deleted file mode 100644 index f8e21175c4..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/devices/KL2x/cmparams.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file KL2x/cmparams.h - * @brief ARM Cortex-M0+ parameters for the Kinetis KL2x family. - * - * @defgroup ARMCMx_KL2x Kinetis KL2x Specific Parameters - * @ingroup ARMCMx_SPECIFIC - * @details This file contains the Cortex-M0+ specific parameters for the - * Kinetis KL2x platform. - * @{ - */ - -#ifndef _CMPARAMS_H_ -#define _CMPARAMS_H_ - -/** - * @brief Cortex core model. - */ -#define CORTEX_MODEL 0 - -/** - * @brief Systick unit presence. - */ -#define CORTEX_HAS_ST TRUE - -/** - * @brief Floating Point unit presence. - */ -#define CORTEX_HAS_FPU FALSE - -/** - * @brief Number of bits in priority masks. - */ -#define CORTEX_PRIORITY_BITS 2 - -/** - * @brief Number of interrupt vectors. - * @note This number does not include the 16 system vectors and must be - * rounded to a multiple of 8. - */ -#define CORTEX_NUM_VECTORS 32 - -/* The following code is not processed when the file is included from an - asm module.*/ -#if !defined(_FROM_ASM_) - -/* Including the device CMSIS header. Note, we are not using the definitions - from this header because we need this file to be usable also from - assembler source files. We verify that the info matches instead.*/ -#include "kl25z.h" - -#if CORTEX_MODEL != __CORTEX_M -#error "CMSIS __CORTEX_M mismatch" -#endif - -#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS -#error "CMSIS __NVIC_PRIO_BITS mismatch" -#endif - -#endif /* !defined(_FROM_ASM_) */ - -#endif /* _CMPARAMS_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/devices/STM32F0xx/cmparams.h b/firmware/ChibiOS_16/os/common/ports/ARMCMx/devices/STM32F0xx/cmparams.h deleted file mode 100644 index 84414bd9c7..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/devices/STM32F0xx/cmparams.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F0xx/cmparams.h - * @brief ARM Cortex-M0 parameters for the STM32F0xx. - * - * @defgroup ARMCMx_STM32F0xx STM32F0xx Specific Parameters - * @ingroup ARMCMx_SPECIFIC - * @details This file contains the Cortex-M0 specific parameters for the - * STM32F0xx platform. - * @{ - */ - -#ifndef _CMPARAMS_H_ -#define _CMPARAMS_H_ - -/** - * @brief Cortex core model. - */ -#define CORTEX_MODEL 0 - -/** - * @brief Floating Point unit presence. - */ -#define CORTEX_HAS_FPU 0 - -/** - * @brief Number of bits in priority masks. - */ -#define CORTEX_PRIORITY_BITS 2 - -/** - * @brief Number of interrupt vectors. - * @note This number does not include the 16 system vectors and must be - * rounded to a multiple of 8. - */ -#define CORTEX_NUM_VECTORS 32 - -/* The following code is not processed when the file is included from an - asm module.*/ -#if !defined(_FROM_ASM_) - -/* If the device type is not externally defined, for example from the Makefile, - then a file named board.h is included. This file must contain a device - definition compatible with the vendor include file.*/ -#if !defined (STM32F030x6) && !defined (STM32F030x8) && \ - !defined (STM32F031x6) && !defined (STM32F038xx) && \ - !defined (STM32F042x6) && !defined (STM32F048xx) && \ - !defined (STM32F051x8) && !defined (STM32F058xx) && \ - !defined (STM32F071xB) && !defined (STM32F072xB) && \ - !defined (STM32F078xx) -#include "board.h" -#endif - -/* Including the device CMSIS header. Note, we are not using the definitions - from this header because we need this file to be usable also from - assembler source files. We verify that the info matches instead.*/ -#include "stm32f0xx.h" - -#if CORTEX_MODEL != __CORTEX_M -#error "CMSIS __CORTEX_M mismatch" -#endif - -#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS -#error "CMSIS __NVIC_PRIO_BITS mismatch" -#endif - -#endif /* !defined(_FROM_ASM_) */ - -#endif /* _CMPARAMS_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/devices/STM32F1xx/cmparams.h b/firmware/ChibiOS_16/os/common/ports/ARMCMx/devices/STM32F1xx/cmparams.h deleted file mode 100644 index 00bf9e0973..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/devices/STM32F1xx/cmparams.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F1xx/cmparams.h - * @brief ARM Cortex-M3 parameters for the STM32F1xx. - * - * @defgroup ARMCMx_STM32F1xx STM32F1xx Specific Parameters - * @ingroup ARMCMx_SPECIFIC - * @details This file contains the Cortex-M4 specific parameters for the - * STM32F1xx platform. - * @{ - */ - -#ifndef _CMPARAMS_H_ -#define _CMPARAMS_H_ - -/** - * @brief Cortex core model. - */ -#define CORTEX_MODEL 3 - -/** - * @brief Floating Point unit presence. - */ -#define CORTEX_HAS_FPU 0 - -/** - * @brief Number of bits in priority masks. - */ -#define CORTEX_PRIORITY_BITS 4 - -/** - * @brief Number of interrupt vectors. - * @note This number does not include the 16 system vectors and must be - * rounded to a multiple of 8. - */ -#define CORTEX_NUM_VECTORS 72 - -/* The following code is not processed when the file is included from an - asm module.*/ -#if !defined(_FROM_ASM_) - -/* If the device type is not externally defined, for example from the Makefile, - then a file named board.h is included. This file must contain a device - definition compatible with the vendor include file.*/ -#if !defined(STM32F100xB) && !defined(STM32F100xE) && \ - !defined(STM32F101x6) && !defined(STM32F101xB) && \ - !defined(STM32F101xE) && !defined(STM32F101xG) && \ - !defined(STM32F102x6) && !defined(STM32F102xB) && \ - !defined(STM32F103x6) && !defined(STM32F103xB) && \ - !defined(STM32F103xE) && !defined(STM32F103xG) && \ - !defined(STM32F105xC) && !defined(STM32F107xC) -#include "board.h" -#endif - -/* Including the device CMSIS header. Note, we are not using the definitions - from this header because we need this file to be usable also from - assembler source files. We verify that the info matches instead.*/ -#include "stm32f1xx.h" - -#if CORTEX_MODEL != __CORTEX_M -#error "CMSIS __CORTEX_M mismatch" -#endif - -#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS -#error "CMSIS __NVIC_PRIO_BITS mismatch" -#endif - -#endif /* !defined(_FROM_ASM_) */ - -#endif /* _CMPARAMS_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/devices/STM32F2xx/cmparams.h b/firmware/ChibiOS_16/os/common/ports/ARMCMx/devices/STM32F2xx/cmparams.h deleted file mode 100644 index c56d5045f5..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/devices/STM32F2xx/cmparams.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F2xx/cmparams.h - * @brief ARM Cortex-M3 parameters for the STM32F2xx. - * - * @defgroup ARMCMx_STM32F2xx STM32F2xx Specific Parameters - * @ingroup ARMCMx_SPECIFIC - * @details This file contains the Cortex-M3 specific parameters for the - * STM32F2xx platform. - * @{ - */ - -#ifndef _CMPARAMS_H_ -#define _CMPARAMS_H_ - -/** - * @brief Cortex core model. - */ -#define CORTEX_MODEL 3 - -/** - * @brief Floating Point unit presence. - */ -#define CORTEX_HAS_FPU 0 - -/** - * @brief Number of bits in priority masks. - */ -#define CORTEX_PRIORITY_BITS 4 - -/** - * @brief Number of interrupt vectors. - * @note This number does not include the 16 system vectors and must be - * rounded to a multiple of 8. - */ -#define CORTEX_NUM_VECTORS 96 - -/* The following code is not processed when the file is included from an - asm module.*/ -#if !defined(_FROM_ASM_) - -/* If the device type is not externally defined, for example from the Makefile, - then a file named board.h is included. This file must contain a device - definition compatible with the vendor include file.*/ -#if !defined(STM32F2XX) -#include "board.h" -#endif - -/* Including the device CMSIS header. Note, we are not using the definitions - from this header because we need this file to be usable also from - assembler source files. We verify that the info matches instead.*/ -#include "stm32f2xx.h" - -#if CORTEX_MODEL != __CORTEX_M -#error "CMSIS __CORTEX_M mismatch" -#endif - -#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS -#error "CMSIS __NVIC_PRIO_BITS mismatch" -#endif - -#endif /* !defined(_FROM_ASM_) */ - -#endif /* _CMPARAMS_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/devices/STM32F3xx/cmparams.h b/firmware/ChibiOS_16/os/common/ports/ARMCMx/devices/STM32F3xx/cmparams.h deleted file mode 100644 index 64c3a930fc..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/devices/STM32F3xx/cmparams.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F3xx/cmparams.h - * @brief ARM Cortex-M4 parameters for the STM32F3xx. - * - * @defgroup ARMCMx_STM32F3xx STM32F3xx Specific Parameters - * @ingroup ARMCMx_SPECIFIC - * @details This file contains the Cortex-M4 specific parameters for the - * STM32F3xx platform. - * @{ - */ - -#ifndef _CMPARAMS_H_ -#define _CMPARAMS_H_ - -/** - * @brief Cortex core model. - */ -#define CORTEX_MODEL 4 - -/** - * @brief Floating Point unit presence. - */ -#define CORTEX_HAS_FPU 1 - -/** - * @brief Number of bits in priority masks. - */ -#define CORTEX_PRIORITY_BITS 4 - -/** - * @brief Number of interrupt vectors. - * @note This number does not include the 16 system vectors and must be - * rounded to a multiple of 8. - */ -#define CORTEX_NUM_VECTORS 88 - -/* The following code is not processed when the file is included from an - asm module.*/ -#if !defined(_FROM_ASM_) - -/* If the device type is not externally defined, for example from the Makefile, - then a file named board.h is included. This file must contain a device - definition compatible with the vendor include file.*/ -#if !defined (STM32F301x8) && !defined (STM32F318xx) && \ - !defined (STM32F302x8) && !defined (STM32F302xC) && \ - !defined (STM32F303x8) && !defined (STM32F303xC) && \ - !defined (STM32F358xx) && !defined (STM32F334x8) && \ - !defined (STM32F328xx) && \ - !defined (STM32F373xC) && !defined (STM32F378xx) -#include "board.h" -#endif - -/* Including the device CMSIS header. Note, we are not using the definitions - from this header because we need this file to be usable also from - assembler source files. We verify that the info matches instead.*/ -#include "stm32f3xx.h" - -#if CORTEX_MODEL != __CORTEX_M -#error "CMSIS __CORTEX_M mismatch" -#endif - -#if CORTEX_HAS_FPU != __FPU_PRESENT -#error "CMSIS __FPU_PRESENT mismatch" -#endif - -#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS -#error "CMSIS __NVIC_PRIO_BITS mismatch" -#endif - -#endif /* !defined(_FROM_ASM_) */ - -#endif /* _CMPARAMS_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/devices/STM32F4xx/cmparams.h b/firmware/ChibiOS_16/os/common/ports/ARMCMx/devices/STM32F4xx/cmparams.h deleted file mode 100644 index a57b11bdef..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/devices/STM32F4xx/cmparams.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F4xx/cmparams.h - * @brief ARM Cortex-M4 parameters for the STM32F4xx. - * - * @defgroup ARMCMx_STM32F4xx STM32F4xx Specific Parameters - * @ingroup ARMCMx_SPECIFIC - * @details This file contains the Cortex-M4 specific parameters for the - * STM32F4xx platform. - * @{ - */ - -#ifndef _CMPARAMS_H_ -#define _CMPARAMS_H_ - -/** - * @brief Cortex core model. - */ -#define CORTEX_MODEL 4 - -/** - * @brief Floating Point unit presence. - */ -#define CORTEX_HAS_FPU 1 - -/** - * @brief Number of bits in priority masks. - */ -#define CORTEX_PRIORITY_BITS 4 - -/** - * @brief Number of interrupt vectors. - * @note This number does not include the 16 system vectors and must be - * rounded to a multiple of 8. - */ -#define CORTEX_NUM_VECTORS 96 - -/* The following code is not processed when the file is included from an - asm module.*/ -#if !defined(_FROM_ASM_) - -/* If the device type is not externally defined, for example from the Makefile, - then a file named board.h is included. This file must contain a device - definition compatible with the vendor include file.*/ -#if !defined(STM32F405xx) && !defined(STM32F415xx) && \ - !defined(STM32F407xx) && !defined(STM32F417xx) && \ - !defined(STM32F427xx) && !defined(STM32F437xx) && \ - !defined(STM32F429xx) && !defined(STM32F439xx) && \ - !defined(STM32F401xC) && !defined(STM32F401xE) && \ - !defined(STM32F411xE) -#include "board.h" -#endif - -/* Including the device CMSIS header. Note, we are not using the definitions - from this header because we need this file to be usable also from - assembler source files. We verify that the info matches instead.*/ -#include "stm32f4xx.h" - -#if CORTEX_MODEL != __CORTEX_M -#error "CMSIS __CORTEX_M mismatch" -#endif - -#if CORTEX_HAS_FPU != __FPU_PRESENT -#error "CMSIS __FPU_PRESENT mismatch" -#endif - -#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS -#error "CMSIS __NVIC_PRIO_BITS mismatch" -#endif - -#endif /* !defined(_FROM_ASM_) */ - -#endif /* _CMPARAMS_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/devices/STM32F7xx/cmparams.h b/firmware/ChibiOS_16/os/common/ports/ARMCMx/devices/STM32F7xx/cmparams.h deleted file mode 100644 index ae98bdff2d..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/devices/STM32F7xx/cmparams.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F7xx/cmparams.h - * @brief ARM Cortex-M7 parameters for the STM32F4xx. - * - * @defgroup ARMCMx_STM32F7xx STM32F7xx Specific Parameters - * @ingroup ARMCMx_SPECIFIC - * @details This file contains the Cortex-M7 specific parameters for the - * STM32F7xx platform. - * @{ - */ - -#ifndef _CMPARAMS_H_ -#define _CMPARAMS_H_ - -/** - * @brief Cortex core model. - */ -#define CORTEX_MODEL 7 - -/** - * @brief Floating Point unit presence. - */ -#define CORTEX_HAS_FPU 1 - -/** - * @brief Number of bits in priority masks. - */ -#define CORTEX_PRIORITY_BITS 4 - -/** - * @brief Number of interrupt vectors. - * @note This number does not include the 16 system vectors and must be - * rounded to a multiple of 8. - */ -#define CORTEX_NUM_VECTORS 112 - -/* The following code is not processed when the file is included from an - asm module.*/ -#if !defined(_FROM_ASM_) - -/* If the device type is not externally defined, for example from the Makefile, - then a file named board.h is included. This file must contain a device - definition compatible with the vendor include file.*/ -#if !defined(STM32F745xx) && !defined(STM32F746xx) && !defined(STM32F756xx) -#include "board.h" -#endif - -/* Including the device CMSIS header. Note, we are not using the definitions - from this header because we need this file to be usable also from - assembler source files. We verify that the info matches instead.*/ -#include "stm32f7xx.h" - -#if CORTEX_MODEL != __CORTEX_M -#error "CMSIS __CORTEX_M mismatch" -#endif - -#if CORTEX_HAS_FPU != __FPU_PRESENT -#error "CMSIS __FPU_PRESENT mismatch" -#endif - -#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS -#error "CMSIS __NVIC_PRIO_BITS mismatch" -#endif - -#endif /* !defined(_FROM_ASM_) */ - -#endif /* _CMPARAMS_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/devices/STM32L0xx/cmparams.h b/firmware/ChibiOS_16/os/common/ports/ARMCMx/devices/STM32L0xx/cmparams.h deleted file mode 100644 index 066d66043f..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/devices/STM32L0xx/cmparams.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32L0xx/cmparams.h - * @brief ARM Cortex-M0+ parameters for the STM32L0xx. - * - * @defgroup ARMCMx_STM32L0xx STM32L0xx Specific Parameters - * @ingroup ARMCMx_SPECIFIC - * @details This file contains the Cortex-M0 specific parameters for the - * STM32L0xx platform. - * @{ - */ - -#ifndef _CMPARAMS_H_ -#define _CMPARAMS_H_ - -/** - * @brief Cortex core model. - */ -#define CORTEX_MODEL 0 - -/** - * @brief Floating Point unit presence. - */ -#define CORTEX_HAS_FPU 0 - -/** - * @brief Number of bits in priority masks. - */ -#define CORTEX_PRIORITY_BITS 2 - -/** - * @brief Number of interrupt vectors. - * @note This number does not include the 16 system vectors and must be - * rounded to a multiple of 8. - */ -#define CORTEX_NUM_VECTORS 32 - -/* The following code is not processed when the file is included from an - asm module.*/ -#if !defined(_FROM_ASM_) - -/* If the device type is not externally defined, for example from the Makefile, - then a file named board.h is included. This file must contain a device - definition compatible with the vendor include file.*/ -#if !defined(STM32L051xx) && !defined(STM32L052xx) && \ - !defined(STM32L053xx) && !defined(STM32L062xx) && \ - !defined(STM32L063xx) && !defined(STM32L061xx) -#include "board.h" -#endif - -/* Including the device CMSIS header. Note, we are not using the definitions - from this header because we need this file to be usable also from - assembler source files. We verify that the info matches instead.*/ -#include "stm32l0xx.h" - -#if CORTEX_MODEL != __CORTEX_M -#error "CMSIS __CORTEX_M mismatch" -#endif - -#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS -#error "CMSIS __NVIC_PRIO_BITS mismatch" -#endif - -#endif /* !defined(_FROM_ASM_) */ - -#endif /* _CMPARAMS_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/devices/STM32L1xx/cmparams.h b/firmware/ChibiOS_16/os/common/ports/ARMCMx/devices/STM32L1xx/cmparams.h deleted file mode 100644 index 8c92b11ee0..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/devices/STM32L1xx/cmparams.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32L1xx/cmparams.h - * @brief ARM Cortex-M3 parameters for the STM32L1xx. - * - * @defgroup ARMCMx_STM32L1xx STM32L1xx Specific Parameters - * @ingroup ARMCMx_SPECIFIC - * @details This file contains the Cortex-M3 specific parameters for the - * STM32L1xx platform. - * @{ - */ - -#ifndef _CMPARAMS_H_ -#define _CMPARAMS_H_ - -/** - * @brief Cortex core model. - */ -#define CORTEX_MODEL 3 - -/** - * @brief Floating Point unit presence. - */ -#define CORTEX_HAS_FPU 0 - -/** - * @brief Number of bits in priority masks. - */ -#define CORTEX_PRIORITY_BITS 4 - -/** - * @brief Number of interrupt vectors. - * @note This number does not include the 16 system vectors and must be - * rounded to a multiple of 8. - */ -#define CORTEX_NUM_VECTORS 64 - -/* The following code is not processed when the file is included from an - asm module.*/ -#if !defined(_FROM_ASM_) - -/* If the device type is not externally defined, for example from the Makefile, - then a file named board.h is included. This file must contain a device - definition compatible with the vendor include file.*/ -#if !defined(STM32L100xB) && !defined(STM32L100xBA) && \ - !defined(STM32L100xC) && !defined(STM32L151xB) && \ - !defined(STM32L151xBA) && !defined(STM32L151xC) && \ - !defined(STM32L151xCA) && !defined(STM32L151xD) && \ - !defined(STM32L151xDX) && !defined(STM32L151xE) && \ - !defined(STM32L152xB) && !defined(STM32L152xBA) && \ - !defined(STM32L152xC) && !defined(STM32L152xCA) && \ - !defined(STM32L152xD) && !defined(STM32L152xDX) && \ - !defined(STM32L152xE) && !defined(STM32L162xC) && \ - !defined(STM32L162xCA) && !defined(STM32L162xD) && \ - !defined(STM32L162xDX) && !defined(STM32L162xE) -#include "board.h" -#endif - -/* Including the device CMSIS header. Note, we are not using the definitions - from this header because we need this file to be usable also from - assembler source files. We verify that the info matches instead.*/ -#include "stm32l1xx.h" - -#if CORTEX_MODEL != __CORTEX_M -#error "CMSIS __CORTEX_M mismatch" -#endif - -#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS -#error "CMSIS __NVIC_PRIO_BITS mismatch" -#endif - -/* Fix for yet another consistency error in ST headers.*/ -#define SVCall_IRQn SVC_IRQn - -#endif /* !defined(_FROM_ASM_) */ - -#endif /* _CMPARAMS_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/ARMCMx/devices/STM32L4xx/cmparams.h b/firmware/ChibiOS_16/os/common/ports/ARMCMx/devices/STM32L4xx/cmparams.h deleted file mode 100644 index 9bf811c08f..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/ARMCMx/devices/STM32L4xx/cmparams.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F4xx/cmparams.h - * @brief ARM Cortex-M4 parameters for the STM32F4xx. - * - * @defgroup ARMCMx_STM32L$xx STM32L4xx Specific Parameters - * @ingroup ARMCMx_SPECIFIC - * @details This file contains the Cortex-M4 specific parameters for the - * STM32L4xx platform. - * @{ - */ - -#ifndef _CMPARAMS_H_ -#define _CMPARAMS_H_ - -/** - * @brief Cortex core model. - */ -#define CORTEX_MODEL 4 - -/** - * @brief Floating Point unit presence. - */ -#define CORTEX_HAS_FPU 1 - -/** - * @brief Number of bits in priority masks. - */ -#define CORTEX_PRIORITY_BITS 4 - -/** - * @brief Number of interrupt vectors. - * @note This number does not include the 16 system vectors and must be - * rounded to a multiple of 8. - */ -#define CORTEX_NUM_VECTORS 88 - -/* The following code is not processed when the file is included from an - asm module.*/ -#if !defined(_FROM_ASM_) - -/* If the device type is not externally defined, for example from the Makefile, - then a file named board.h is included. This file must contain a device - definition compatible with the vendor include file.*/ -#if !defined(STM32L471xx) && !defined(STM32L475xx) && \ - !defined(STM32L476xx) && !defined(STM32L485xx) && \ - !defined (STM32L486xx) -#include "board.h" -#endif - -/* Including the device CMSIS header. Note, we are not using the definitions - from this header because we need this file to be usable also from - assembler source files. We verify that the info matches instead.*/ -#include "stm32l4xx.h" - -#if CORTEX_MODEL != __CORTEX_M -#error "CMSIS __CORTEX_M mismatch" -#endif - -#if CORTEX_HAS_FPU != __FPU_PRESENT -#error "CMSIS __FPU_PRESENT mismatch" -#endif - -#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS -#error "CMSIS __NVIC_PRIO_BITS mismatch" -#endif - -#endif /* !defined(_FROM_ASM_) */ - -#endif /* _CMPARAMS_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/compilers/CW/crt0.s b/firmware/ChibiOS_16/os/common/ports/e200/compilers/CW/crt0.s deleted file mode 100644 index 30a8e8af91..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/compilers/CW/crt0.s +++ /dev/null @@ -1,258 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file CW/crt0.s - * @brief Generic PowerPC startup file for CodeWarrior. - * - * @addtogroup PPC_CW_CORE - * @{ - */ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -#if !defined(FALSE) || defined(__DOXYGEN__) -#define FALSE 0 -#endif - -#if !defined(TRUE) || defined(__DOXYGEN__) -#define TRUE 1 -#endif - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Stack segments initialization switch. - */ -#if !defined(CRT0_STACKS_FILL_PATTERN) || defined(__DOXYGEN__) -#define CRT0_STACKS_FILL_PATTERN 0x55555555 -#endif - -/** - * @brief Stack segments initialization switch. - */ -#if !defined(CRT0_INIT_STACKS) || defined(__DOXYGEN__) -#define CRT0_INIT_STACKS TRUE -#endif - -/** - * @brief DATA segment initialization switch. - */ -#if !defined(CRT0_INIT_DATA) || defined(__DOXYGEN__) -#define CRT0_INIT_DATA TRUE -#endif - -/** - * @brief BSS segment initialization switch. - */ -#if !defined(CRT0_INIT_BSS) || defined(__DOXYGEN__) -#define CRT0_INIT_BSS TRUE -#endif - -/** - * @brief Constructors invocation switch. - */ -#if !defined(CRT0_CALL_CONSTRUCTORS) || defined(__DOXYGEN__) -#define CRT0_CALL_CONSTRUCTORS FALSE -#endif - -/** - * @brief Destructors invocation switch. - */ -#if !defined(CRT0_CALL_DESTRUCTORS) || defined(__DOXYGEN__) -#define CRT0_CALL_DESTRUCTORS FALSE -#endif - -/*===========================================================================*/ -/* Code section. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) - .extern __sdata2_start__ - .extern __sdata_start__ - .extern __bss_start__ - .extern __bss_end__ - .extern __irq_stack_base__ - .extern __irq_stack_end__ - .extern __process_stack_end__ - .extern __process_stack_base__ - .extern __romdata_start__ - .extern __data_start__ - .extern __data_end__ - .extern __init_array_start - .extern __init_array_end - .extern __fini_array_start - .extern __fini_array_end - - .extern main - - .section .crt0, text_vle - .align 16 - .globl _boot_address - .type _boot_address, @function -_boot_address: - /* Stack setup.*/ - e_lis r1, __process_stack_end__@h - e_or2i r1, __process_stack_end__@l - se_li r0, 0 - e_stwu r0, -8(r1) - - /* Small sections registers initialization.*/ - e_lis r2, __sdata2_start__@h - e_or2i r2, __sdata2_start__@l - e_lis r13, __sdata_start__@h - e_or2i r13, __sdata_start__@l - - /* Early initialization.*/ - e_bl __early_init - -#if CRT0_INIT_STACKS == TRUE - /* Stacks fill pattern.*/ - e_lis r7, CRT0_STACKS_FILL_PATTERN@h - e_or2i r7, CRT0_STACKS_FILL_PATTERN@l - - /* IRQ Stack initialization. Note, the architecture does not use this - stack, the size is usually zero. An OS can have special SW handling - and require this. A 4 bytes alignment is assumed and required.*/ - e_lis r4, __irq_stack_base__@h - e_or2i r4, __irq_stack_base__@l - e_lis r5, __irq_stack_end__@h - e_or2i r5, __irq_stack_end__@l -.irqsloop: - se_cmpl r4, r5 - se_bge .irqsend - se_stw r7, 0(r4) - se_addi r4, 4 - se_b .irqsloop -.irqsend: - - /* Process Stack initialization. Note, does not overwrite the already - written EABI frame. A 4 bytes alignment is assumed and required.*/ - e_lis r4, __process_stack_base__@h - e_or2i r4, __process_stack_base__@l - e_lis r5, (__process_stack_end__ - 8)@h - e_or2i r5, (__process_stack_end__ - 8)@l -.prcsloop: - se_cmpl r4, r5 - se_bge .prcsend - se_stw r7, 0(r4) - se_addi r4, 4 - se_b .prcsloop -.prcsend: -#endif - -#if CRT0_INIT_BSS == TRUE - /* BSS clearing.*/ - e_lis r4, __bss_start__@h - e_or2i r4, __bss_start__@l - e_lis r5, __bss_end__@h - e_or2i r5, __bss_end__@l - se_li r7, 0 -.bssloop: - se_cmpl r4, r5 - se_bge .bssend - se_stw r7, 0(r4) - se_addi r4, 4 - se_b .bssloop -.bssend: -#endif - -#if CRT0_INIT_DATA == TRUE - /* DATA initialization.*/ - e_lis r4, __romdata_start__@h - e_or2i r4, __romdata_start__@l - e_lis r5, __data_start__@h - e_or2i r5, __data_start__@l - e_lis r6, __data_end__@h - e_or2i r6, __data_end__@l -.dataloop: - se_cmpl r5, r6 - se_bge .dataend - se_lwz r7, 0(r4) - se_addi r4, 4 - se_stw r7, 0(r5) - se_addi r5, 4 - se_b .dataloop -.dataend: -#endif - - /* Late initialization.*/ - e_bl __late_init - -#if CRT0_CALL_CONSTRUCTORS == TRUE - /* Constructors invocation.*/ - e_lis r4, __init_array_start@h - e_or2i r4, __init_array_start@l - e_lis r5, __init_array_end@h - e_or2i r5, __init_array_end@l -.iniloop: - se_cmpl r4, r5 - se_bge .iniend - se_lwz r6, 0(r4) - se_mtctr r6 - se_addi r4, 4 - se_bctrl - se_b .iniloop -.iniend: -#endif - - /* Main program invocation.*/ - e_bl main - -#if CRT0_CALL_DESTRUCTORS == TRUE - /* Destructors invocation.*/ - e_lis r4, __fini_array_start@h - e_or2i r4, __fini_array_start@l - e_lis r5, __fini_array_end@h - e_or2i r5, __fini_array_end@l -.finiloop: - se_cmpl r4, r5 - se_bge .finiend - se_lwz r6, 0(r4) - se_mtctr r6 - se_addi r4, 4 - se_bctrl - se_b .finiloop -.finiend: -#endif - - /* Branching to the defined exit handler.*/ - e_b __default_exit - -#endif /* !defined(__DOXYGEN__) */ - - .section .text_vle - .align 4 - - /* Default main exit code, infinite loop.*/ - .weak __default_exit -__default_exit: - e_b __default_exit - - /* Default early initialization code, none.*/ - .weak __early_init - se_blr - - /* Default late initialization code, none.*/ - .weak __late_init -__late_init: - se_blr - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/compilers/CW/unhandled.s b/firmware/ChibiOS_16/os/common/ports/e200/compilers/CW/unhandled.s deleted file mode 100644 index ef5cfbc4cd..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/compilers/CW/unhandled.s +++ /dev/null @@ -1,1858 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file weak.s - * @brief Unhandled IRQs. - * - * @addtogroup PPC_CW_CORE - * @{ - */ - -#define _FROM_ASM_ -#include "ppcparams.h" - -#if defined(VECTORS_RENAMING) -#include "isrs.h" -#endif - -#if !defined(__DOXYGEN__) - - .section .text_vle - .align 4 - - .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5 - .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11 - .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15 -_IVOR0: -_IVOR1: -_IVOR2: -_IVOR3: -_IVOR4: -_IVOR5: -_IVOR6: -_IVOR7: -_IVOR8: -_IVOR9: -_IVOR10: -_IVOR11: -_IVOR12: -_IVOR13: -_IVOR14: -_IVOR15: - .global _unhandled_exception -_unhandled_exception: - se_b _unhandled_exception - - .weak vector0, vector1, vector2, vector3 -#if PPC_NUM_VECTORS > 4 - .weak vector4, vector5, vector6, vector7 -#endif -#if PPC_NUM_VECTORS > 8 - .weak vector8, vector9, vector10, vector11 -#endif -#if PPC_NUM_VECTORS > 12 - .weak vector12, vector13, vector14, vector15 -#endif -#if PPC_NUM_VECTORS > 16 - .weak vector16, vector17, vector18, vector19 -#endif -#if PPC_NUM_VECTORS > 20 - .weak vector20, vector21, vector22, vector23 -#endif -#if PPC_NUM_VECTORS > 24 - .weak vector24, vector25, vector26, vector27 -#endif -#if PPC_NUM_VECTORS > 28 - .weak vector28, vector29, vector30, vector31 -#endif -#if PPC_NUM_VECTORS > 32 - .weak vector32, vector33, vector34, vector35 -#endif -#if PPC_NUM_VECTORS > 36 - .weak vector36, vector37, vector38, vector39 -#endif -#if PPC_NUM_VECTORS > 40 - .weak vector40, vector41, vector42, vector43 -#endif -#if PPC_NUM_VECTORS > 44 - .weak vector44, vector45, vector46, vector47 -#endif -#if PPC_NUM_VECTORS > 48 - .weak vector48, vector49, vector50, vector51 -#endif -#if PPC_NUM_VECTORS > 52 - .weak vector52, vector53, vector54, vector55 -#endif -#if PPC_NUM_VECTORS > 56 - .weak vector56, vector57, vector58, vector59 -#endif -#if PPC_NUM_VECTORS > 60 - .weak vector60, vector61, vector62, vector63 -#endif -#if PPC_NUM_VECTORS > 64 - .weak vector64, vector65, vector66, vector67 -#endif -#if PPC_NUM_VECTORS > 68 - .weak vector68, vector69, vector70, vector71 -#endif -#if PPC_NUM_VECTORS > 72 - .weak vector72, vector73, vector74, vector75 -#endif -#if PPC_NUM_VECTORS > 76 - .weak vector76, vector77, vector78, vector79 -#endif -#if PPC_NUM_VECTORS > 80 - .weak vector80, vector81, vector82, vector83 -#endif -#if PPC_NUM_VECTORS > 84 - .weak vector84, vector85, vector86, vector87 -#endif -#if PPC_NUM_VECTORS > 88 - .weak vector88, vector89, vector90, vector91 -#endif -#if PPC_NUM_VECTORS > 92 - .weak vector92, vector93, vector94, vector95 -#endif -#if PPC_NUM_VECTORS > 96 - .weak vector96, vector97, vector98, vector99 -#endif -#if PPC_NUM_VECTORS > 100 - .weak vector100, vector101, vector102, vector103 -#endif -#if PPC_NUM_VECTORS > 104 - .weak vector104, vector105, vector106, vector107 -#endif -#if PPC_NUM_VECTORS > 108 - .weak vector108, vector109, vector110, vector111 -#endif -#if PPC_NUM_VECTORS > 112 - .weak vector112, vector113, vector114, vector115 -#endif -#if PPC_NUM_VECTORS > 116 - .weak vector116, vector117, vector118, vector119 -#endif -#if PPC_NUM_VECTORS > 120 - .weak vector120, vector121, vector122, vector123 -#endif -#if PPC_NUM_VECTORS > 124 - .weak vector124, vector125, vector126, vector127 -#endif -#if PPC_NUM_VECTORS > 128 - .weak vector128, vector129, vector130, vector131 -#endif -#if PPC_NUM_VECTORS > 132 - .weak vector132, vector133, vector134, vector135 -#endif -#if PPC_NUM_VECTORS > 136 - .weak vector136, vector137, vector138, vector139 -#endif -#if PPC_NUM_VECTORS > 140 - .weak vector140, vector141, vector142, vector143 -#endif -#if PPC_NUM_VECTORS > 144 - .weak vector144, vector145, vector146, vector147 -#endif -#if PPC_NUM_VECTORS > 148 - .weak vector148, vector149, vector150, vector151 -#endif -#if PPC_NUM_VECTORS > 152 - .weak vector152, vector153, vector154, vector155 -#endif -#if PPC_NUM_VECTORS > 156 - .weak vector156, vector157, vector158, vector159 -#endif -#if PPC_NUM_VECTORS > 160 - .weak vector160, vector161, vector162, vector163 -#endif -#if PPC_NUM_VECTORS > 164 - .weak vector164, vector165, vector166, vector167 -#endif -#if PPC_NUM_VECTORS > 168 - .weak vector168, vector169, vector170, vector171 -#endif -#if PPC_NUM_VECTORS > 172 - .weak vector172, vector173, vector174, vector175 -#endif -#if PPC_NUM_VECTORS > 176 - .weak vector176, vector177, vector178, vector179 -#endif -#if PPC_NUM_VECTORS > 180 - .weak vector180, vector181, vector182, vector183 -#endif -#if PPC_NUM_VECTORS > 184 - .weak vector184, vector185, vector186, vector187 -#endif -#if PPC_NUM_VECTORS > 188 - .weak vector188, vector189, vector190, vector191 -#endif -#if PPC_NUM_VECTORS > 192 - .weak vector192, vector193, vector194, vector195 -#endif -#if PPC_NUM_VECTORS > 196 - .weak vector196, vector197, vector198, vector199 -#endif -#if PPC_NUM_VECTORS > 200 - .weak vector200, vector201, vector202, vector203 -#endif -#if PPC_NUM_VECTORS > 204 - .weak vector204, vector205, vector206, vector207 -#endif -#if PPC_NUM_VECTORS > 208 - .weak vector208, vector209, vector210, vector211 -#endif -#if PPC_NUM_VECTORS > 212 - .weak vector212, vector213, vector214, vector215 -#endif -#if PPC_NUM_VECTORS > 216 - .weak vector216, vector217, vector218, vector219 -#endif -#if PPC_NUM_VECTORS > 220 - .weak vector220, vector221, vector222, vector223 -#endif -#if PPC_NUM_VECTORS > 224 - .weak vector224, vector225, vector226, vector227 -#endif -#if PPC_NUM_VECTORS > 228 - .weak vector228, vector229, vector230, vector231 -#endif -#if PPC_NUM_VECTORS > 232 - .weak vector232, vector233, vector234, vector235 -#endif -#if PPC_NUM_VECTORS > 236 - .weak vector236, vector237, vector238, vector239 -#endif -#if PPC_NUM_VECTORS > 240 - .weak vector240, vector241, vector242, vector243 -#endif -#if PPC_NUM_VECTORS > 244 - .weak vector244, vector245, vector246, vector247 -#endif -#if PPC_NUM_VECTORS > 248 - .weak vector248, vector249, vector250, vector251 -#endif -#if PPC_NUM_VECTORS > 252 - .weak vector252, vector253, vector254, vector255 -#endif -#if PPC_NUM_VECTORS > 256 - .weak vector256, vector257, vector258, vector259 -#endif -#if PPC_NUM_VECTORS > 260 - .weak vector260, vector261, vector262, vector263 -#endif -#if PPC_NUM_VECTORS > 264 - .weak vector264, vector265, vector266, vector267 -#endif -#if PPC_NUM_VECTORS > 268 - .weak vector268, vector269, vector270, vector271 -#endif -#if PPC_NUM_VECTORS > 272 - .weak vector272, vector273, vector274, vector275 -#endif -#if PPC_NUM_VECTORS > 276 - .weak vector276, vector277, vector278, vector279 -#endif -#if PPC_NUM_VECTORS > 280 - .weak vector280, vector281, vector282, vector283 -#endif -#if PPC_NUM_VECTORS > 284 - .weak vector284, vector285, vector286, vector287 -#endif -#if PPC_NUM_VECTORS > 288 - .weak vector288, vector289, vector290, vector291 -#endif -#if PPC_NUM_VECTORS > 292 - .weak vector292, vector293, vector294, vector295 -#endif -#if PPC_NUM_VECTORS > 296 - .weak vector296, vector297, vector298, vector299 -#endif -#if PPC_NUM_VECTORS > 300 - .weak vector300, vector301, vector302, vector303 -#endif -#if PPC_NUM_VECTORS > 304 - .weak vector304, vector305, vector306, vector307 -#endif -#if PPC_NUM_VECTORS > 308 - .weak vector308, vector309, vector310, vector311 -#endif -#if PPC_NUM_VECTORS > 312 - .weak vector312, vector313, vector314, vector315 -#endif -#if PPC_NUM_VECTORS > 316 - .weak vector316, vector317, vector318, vector319 -#endif -#if PPC_NUM_VECTORS > 320 - .weak vector320, vector321, vector322, vector323 -#endif -#if PPC_NUM_VECTORS > 324 - .weak vector324, vector325, vector326, vector327 -#endif -#if PPC_NUM_VECTORS > 328 - .weak vector328, vector329, vector330, vector331 -#endif -#if PPC_NUM_VECTORS > 332 - .weak vector332, vector333, vector334, vector335 -#endif -#if PPC_NUM_VECTORS > 336 - .weak vector336, vector337, vector338, vector339 -#endif -#if PPC_NUM_VECTORS > 340 - .weak vector340, vector341, vector342, vector343 -#endif -#if PPC_NUM_VECTORS > 344 - .weak vector344, vector345, vector346, vector347 -#endif -#if PPC_NUM_VECTORS > 348 - .weak vector348, vector349, vector350, vector351 -#endif -#if PPC_NUM_VECTORS > 352 - .weak vector352, vector353, vector354, vector355 -#endif -#if PPC_NUM_VECTORS > 356 - .weak vector356, vector357, vector358, vector359 -#endif -#if PPC_NUM_VECTORS > 360 - .weak vector360, vector361, vector362, vector363 -#endif -#if PPC_NUM_VECTORS > 364 - .weak vector364, vector365, vector366, vector367 -#endif -#if PPC_NUM_VECTORS > 368 - .weak vector368, vector369, vector370, vector371 -#endif -#if PPC_NUM_VECTORS > 372 - .weak vector372, vector373, vector374, vector375 -#endif -#if PPC_NUM_VECTORS > 376 - .weak vector376, vector377, vector378, vector379 -#endif -#if PPC_NUM_VECTORS > 380 - .weak vector380, vector381, vector382, vector383 -#endif -#if PPC_NUM_VECTORS > 384 - .weak vector384, vector385, vector386, vector387 -#endif -#if PPC_NUM_VECTORS > 388 - .weak vector388, vector389, vector390, vector391 -#endif -#if PPC_NUM_VECTORS > 392 - .weak vector392, vector393, vector394, vector395 -#endif -#if PPC_NUM_VECTORS > 396 - .weak vector396, vector397, vector398, vector399 -#endif -#if PPC_NUM_VECTORS > 400 - .weak vector400, vector401, vector402, vector403 -#endif -#if PPC_NUM_VECTORS > 404 - .weak vector404, vector405, vector406, vector407 -#endif -#if PPC_NUM_VECTORS > 408 - .weak vector408, vector409, vector410, vector411 -#endif -#if PPC_NUM_VECTORS > 412 - .weak vector412, vector413, vector414, vector415 -#endif -#if PPC_NUM_VECTORS > 416 - .weak vector416, vector417, vector418, vector419 -#endif -#if PPC_NUM_VECTORS > 420 - .weak vector420, vector421, vector422, vector423 -#endif -#if PPC_NUM_VECTORS > 424 - .weak vector424, vector425, vector426, vector427 -#endif -#if PPC_NUM_VECTORS > 428 - .weak vector428, vector429, vector430, vector431 -#endif -#if PPC_NUM_VECTORS > 432 - .weak vector432, vector433, vector434, vector435 -#endif -#if PPC_NUM_VECTORS > 436 - .weak vector436, vector437, vector438, vector439 -#endif -#if PPC_NUM_VECTORS > 440 - .weak vector440, vector441, vector442, vector443 -#endif -#if PPC_NUM_VECTORS > 444 - .weak vector444, vector445, vector446, vector447 -#endif -#if PPC_NUM_VECTORS > 448 - .weak vector448, vector449, vector450, vector451 -#endif -#if PPC_NUM_VECTORS > 452 - .weak vector452, vector453, vector454, vector455 -#endif -#if PPC_NUM_VECTORS > 456 - .weak vector456, vector457, vector458, vector459 -#endif -#if PPC_NUM_VECTORS > 460 - .weak vector460, vector461, vector462, vector463 -#endif -#if PPC_NUM_VECTORS > 464 - .weak vector464, vector465, vector466, vector467 -#endif -#if PPC_NUM_VECTORS > 468 - .weak vector468, vector469, vector470, vector471 -#endif -#if PPC_NUM_VECTORS > 472 - .weak vector472, vector473, vector474, vector475 -#endif -#if PPC_NUM_VECTORS > 476 - .weak vector476, vector477, vector478, vector479 -#endif -#if PPC_NUM_VECTORS > 480 - .weak vector480, vector481, vector482, vector483 -#endif -#if PPC_NUM_VECTORS > 484 - .weak vector484, vector485, vector486, vector487 -#endif -#if PPC_NUM_VECTORS > 488 - .weak vector488, vector489, vector490, vector491 -#endif -#if PPC_NUM_VECTORS > 492 - .weak vector492, vector493, vector494, vector495 -#endif -#if PPC_NUM_VECTORS > 496 - .weak vector496, vector497, vector498, vector499 -#endif -#if PPC_NUM_VECTORS > 500 - .weak vector500, vector501, vector502, vector503 -#endif -#if PPC_NUM_VECTORS > 504 - .weak vector504, vector505, vector506, vector507 -#endif -#if PPC_NUM_VECTORS > 508 - .weak vector508, vector509, vector510, vector511 -#endif -#if PPC_NUM_VECTORS > 512 - .weak vector512, vector513, vector514, vector515 -#endif -#if PPC_NUM_VECTORS > 516 - .weak vector516, vector517, vector518, vector519 -#endif -#if PPC_NUM_VECTORS > 520 - .weak vector520, vector521, vector522, vector523 -#endif -#if PPC_NUM_VECTORS > 524 - .weak vector524, vector525, vector526, vector527 -#endif -#if PPC_NUM_VECTORS > 528 - .weak vector528, vector529, vector530, vector531 -#endif -#if PPC_NUM_VECTORS > 532 - .weak vector532, vector533, vector534, vector535 -#endif -#if PPC_NUM_VECTORS > 536 - .weak vector536, vector537, vector538, vector539 -#endif -#if PPC_NUM_VECTORS > 540 - .weak vector540, vector541, vector542, vector543 -#endif -#if PPC_NUM_VECTORS > 544 - .weak vector544, vector545, vector546, vector547 -#endif -#if PPC_NUM_VECTORS > 548 - .weak vector548, vector549, vector550, vector551 -#endif -#if PPC_NUM_VECTORS > 552 - .weak vector552, vector553, vector554, vector555 -#endif -#if PPC_NUM_VECTORS > 556 - .weak vector556, vector557, vector558, vector559 -#endif -#if PPC_NUM_VECTORS > 560 - .weak vector560, vector561, vector562, vector563 -#endif -#if PPC_NUM_VECTORS > 564 - .weak vector564, vector565, vector566, vector567 -#endif -#if PPC_NUM_VECTORS > 568 - .weak vector568, vector569, vector570, vector571 -#endif -#if PPC_NUM_VECTORS > 572 - .weak vector572, vector573, vector574, vector575 -#endif -#if PPC_NUM_VECTORS > 576 - .weak vector576, vector577, vector578, vector579 -#endif -#if PPC_NUM_VECTORS > 580 - .weak vector580, vector581, vector582, vector583 -#endif -#if PPC_NUM_VECTORS > 584 - .weak vector584, vector585, vector586, vector587 -#endif -#if PPC_NUM_VECTORS > 588 - .weak vector588, vector589, vector590, vector591 -#endif -#if PPC_NUM_VECTORS > 592 - .weak vector592, vector593, vector594, vector595 -#endif -#if PPC_NUM_VECTORS > 596 - .weak vector596, vector597, vector598, vector599 -#endif -#if PPC_NUM_VECTORS > 600 - .weak vector600, vector601, vector602, vector603 -#endif -#if PPC_NUM_VECTORS > 604 - .weak vector604, vector605, vector606, vector607 -#endif -#if PPC_NUM_VECTORS > 608 - .weak vector608, vector609, vector610, vector611 -#endif -#if PPC_NUM_VECTORS > 612 - .weak vector612, vector613, vector614, vector615 -#endif -#if PPC_NUM_VECTORS > 616 - .weak vector616, vector617, vector618, vector619 -#endif -#if PPC_NUM_VECTORS > 620 - .weak vector620, vector621, vector622, vector623 -#endif -#if PPC_NUM_VECTORS > 624 - .weak vector624, vector625, vector626, vector627 -#endif -#if PPC_NUM_VECTORS > 628 - .weak vector628, vector629, vector630, vector631 -#endif -#if PPC_NUM_VECTORS > 632 - .weak vector632, vector633, vector634, vector635 -#endif -#if PPC_NUM_VECTORS > 636 - .weak vector636, vector637, vector638, vector639 -#endif -#if PPC_NUM_VECTORS > 640 - .weak vector640, vector641, vector642, vector643 -#endif -#if PPC_NUM_VECTORS > 644 - .weak vector644, vector645, vector646, vector647 -#endif -#if PPC_NUM_VECTORS > 648 - .weak vector648, vector649, vector650, vector651 -#endif -#if PPC_NUM_VECTORS > 652 - .weak vector652, vector653, vector654, vector655 -#endif -#if PPC_NUM_VECTORS > 656 - .weak vector656, vector657, vector658, vector659 -#endif -#if PPC_NUM_VECTORS > 660 - .weak vector660, vector661, vector662, vector663 -#endif -#if PPC_NUM_VECTORS > 664 - .weak vector664, vector665, vector666, vector667 -#endif -#if PPC_NUM_VECTORS > 668 - .weak vector668, vector669, vector670, vector671 -#endif -#if PPC_NUM_VECTORS > 672 - .weak vector672, vector673, vector674, vector675 -#endif -#if PPC_NUM_VECTORS > 676 - .weak vector676, vector677, vector678, vector679 -#endif -#if PPC_NUM_VECTORS > 680 - .weak vector680, vector681, vector682, vector683 -#endif -#if PPC_NUM_VECTORS > 684 - .weak vector684, vector685, vector686, vector687 -#endif -#if PPC_NUM_VECTORS > 688 - .weak vector688, vector689, vector690, vector691 -#endif -#if PPC_NUM_VECTORS > 692 - .weak vector692, vector693, vector694, vector695 -#endif -#if PPC_NUM_VECTORS > 696 - .weak vector696, vector697, vector698, vector699 -#endif -#if PPC_NUM_VECTORS > 700 - .weak vector700, vector701, vector702, vector703 -#endif -#if PPC_NUM_VECTORS > 704 - .weak vector704, vector705, vector706, vector707 -#endif -#if PPC_NUM_VECTORS > 708 - .weak vector708, vector709, vector710, vector711 -#endif -#if PPC_NUM_VECTORS > 712 - .weak vector712, vector713, vector714, vector715 -#endif -#if PPC_NUM_VECTORS > 716 - .weak vector716, vector717, vector718, vector719 -#endif -#if PPC_NUM_VECTORS > 720 - .weak vector720, vector721, vector722, vector723 -#endif -#if PPC_NUM_VECTORS > 724 - .weak vector724, vector725, vector726, vector727 -#endif -#if PPC_NUM_VECTORS > 728 - .weak vector728, vector729, vector730, vector731 -#endif -#if PPC_NUM_VECTORS > 732 - .weak vector732, vector733, vector734, vector735 -#endif -#if PPC_NUM_VECTORS > 736 - .weak vector736, vector737, vector738, vector739 -#endif -#if PPC_NUM_VECTORS > 740 - .weak vector740, vector741, vector742, vector743 -#endif -#if PPC_NUM_VECTORS > 744 - .weak vector744, vector745, vector746, vector747 -#endif -#if PPC_NUM_VECTORS > 748 - .weak vector748, vector749, vector750, vector751 -#endif -#if PPC_NUM_VECTORS > 752 - .weak vector752, vector753, vector754, vector755 -#endif -#if PPC_NUM_VECTORS > 756 - .weak vector756, vector757, vector758, vector759 -#endif -#if PPC_NUM_VECTORS > 760 - .weak vector760, vector761, vector762, vector763 -#endif -#if PPC_NUM_VECTORS > 764 - .weak vector764, vector765, vector766, vector767 -#endif -#if PPC_NUM_VECTORS > 768 - .weak vector768, vector769, vector770, vector771 -#endif -#if PPC_NUM_VECTORS > 772 - .weak vector772, vector773, vector774, vector775 -#endif -#if PPC_NUM_VECTORS > 776 - .weak vector776, vector777, vector778, vector779 -#endif -#if PPC_NUM_VECTORS > 780 - .weak vector780, vector781, vector782, vector783 -#endif -#if PPC_NUM_VECTORS > 784 - .weak vector784, vector785, vector786, vector787 -#endif -#if PPC_NUM_VECTORS > 788 - .weak vector788, vector789, vector790, vector791 -#endif -#if PPC_NUM_VECTORS > 792 - .weak vector792, vector793, vector794, vector795 -#endif -#if PPC_NUM_VECTORS > 796 - .weak vector796, vector797, vector798, vector799 -#endif -#if PPC_NUM_VECTORS > 800 - .weak vector800, vector801, vector802, vector803 -#endif -#if PPC_NUM_VECTORS > 804 - .weak vector804, vector805, vector806, vector807 -#endif -#if PPC_NUM_VECTORS > 808 - .weak vector808, vector809, vector810, vector811 -#endif -#if PPC_NUM_VECTORS > 812 - .weak vector812, vector813, vector814, vector815 -#endif -#if PPC_NUM_VECTORS > 816 - .weak vector816, vector817, vector818, vector819 -#endif -#if PPC_NUM_VECTORS > 820 - .weak vector820, vector821, vector822, vector823 -#endif -#if PPC_NUM_VECTORS > 824 - .weak vector824, vector825, vector826, vector827 -#endif -#if PPC_NUM_VECTORS > 828 - .weak vector828, vector829, vector830, vector831 -#endif -#if PPC_NUM_VECTORS > 832 - .weak vector832, vector833, vector834, vector835 -#endif -#if PPC_NUM_VECTORS > 836 - .weak vector836, vector837, vector838, vector839 -#endif -#if PPC_NUM_VECTORS > 840 - .weak vector840, vector841, vector842, vector843 -#endif -#if PPC_NUM_VECTORS > 844 - .weak vector844, vector845, vector846, vector847 -#endif -#if PPC_NUM_VECTORS > 848 - .weak vector848, vector849, vector850, vector851 -#endif -#if PPC_NUM_VECTORS > 852 - .weak vector852, vector853, vector854, vector855 -#endif -#if PPC_NUM_VECTORS > 856 - .weak vector856, vector857, vector858, vector859 -#endif -#if PPC_NUM_VECTORS > 860 - .weak vector860, vector861, vector862, vector863 -#endif -#if PPC_NUM_VECTORS > 864 - .weak vector864, vector865, vector866, vector867 -#endif -#if PPC_NUM_VECTORS > 868 - .weak vector868, vector869, vector870, vector871 -#endif -#if PPC_NUM_VECTORS > 872 - .weak vector872, vector873, vector874, vector875 -#endif -#if PPC_NUM_VECTORS > 876 - .weak vector876, vector877, vector878, vector879 -#endif -#if PPC_NUM_VECTORS > 880 - .weak vector880, vector881, vector882, vector883 -#endif -#if PPC_NUM_VECTORS > 884 - .weak vector884, vector885, vector886, vector887 -#endif -#if PPC_NUM_VECTORS > 888 - .weak vector888, vector889, vector890, vector891 -#endif -#if PPC_NUM_VECTORS > 892 - .weak vector892, vector893, vector894, vector895 -#endif -#if PPC_NUM_VECTORS > 896 - .weak vector896, vector897, vector898, vector899 -#endif -#if PPC_NUM_VECTORS > 900 - .weak vector900, vector901, vector902, vector903 -#endif -#if PPC_NUM_VECTORS > 904 - .weak vector904, vector905, vector906, vector907 -#endif -#if PPC_NUM_VECTORS > 908 - .weak vector908, vector909, vector910, vector911 -#endif -#if PPC_NUM_VECTORS > 912 - .weak vector912, vector913, vector914, vector915 -#endif -#if PPC_NUM_VECTORS > 916 - .weak vector916, vector917, vector918, vector919 -#endif -#if PPC_NUM_VECTORS > 920 - .weak vector920, vector921, vector922, vector923 -#endif -#if PPC_NUM_VECTORS > 924 - .weak vector924, vector925, vector926, vector927 -#endif -#if PPC_NUM_VECTORS > 928 - .weak vector928, vector929, vector930, vector931 -#endif -#if PPC_NUM_VECTORS > 932 - .weak vector932, vector933, vector934, vector935 -#endif -#if PPC_NUM_VECTORS > 936 - .weak vector936, vector937, vector938, vector939 -#endif -#if PPC_NUM_VECTORS > 940 - .weak vector940, vector941, vector942, vector943 -#endif -#if PPC_NUM_VECTORS > 944 - .weak vector944, vector945, vector946, vector947 -#endif -#if PPC_NUM_VECTORS > 948 - .weak vector948, vector949, vector950, vector951 -#endif -#if PPC_NUM_VECTORS > 952 - .weak vector952, vector953, vector954, vector955 -#endif -#if PPC_NUM_VECTORS > 956 - .weak vector956, vector957, vector958, vector959 -#endif -#if PPC_NUM_VECTORS > 960 - .weak vector960, vector961, vector962, vector963 -#endif -#if PPC_NUM_VECTORS > 964 - .weak vector964, vector965, vector966, vector967 -#endif -#if PPC_NUM_VECTORS > 968 - .weak vector968, vector969, vector970, vector971 -#endif -#if PPC_NUM_VECTORS > 972 - .weak vector972, vector973, vector974, vector975 -#endif -#if PPC_NUM_VECTORS > 976 - .weak vector976, vector977, vector978, vector979 -#endif -#if PPC_NUM_VECTORS > 980 - .weak vector980, vector981, vector982, vector983 -#endif -#if PPC_NUM_VECTORS > 984 - .weak vector984, vector985, vector986, vector987 -#endif -#if PPC_NUM_VECTORS > 988 - .weak vector988, vector989, vector990, vector991 -#endif -#if PPC_NUM_VECTORS > 992 - .weak vector992, vector993, vector994, vector995 -#endif -#if PPC_NUM_VECTORS > 996 - .weak vector996, vector997, vector998, vector999 -#endif -#if PPC_NUM_VECTORS > 1000 - .weak vector1000, vector1001, vector1002, vector1003 -#endif -#if PPC_NUM_VECTORS > 1004 - .weak vector1004, vector1005, vector1006, vector1007 -#endif -#if PPC_NUM_VECTORS > 1008 - .weak vector1008, vector1009, vector1010, vector1011 -#endif -#if PPC_NUM_VECTORS > 1012 - .weak vector1012, vector1013, vector1014, vector1015 -#endif -#if PPC_NUM_VECTORS > 1016 - .weak vector1016, vector1017, vector1018, vector1019 -#endif -#if PPC_NUM_VECTORS > 1020 - .weak vector1020, vector1021, vector1022, vector1023 -#endif - -vector0: -vector1: -vector2: -vector3: -vector4: -vector5: -vector6: -vector7: -vector8: -vector9: -vector10: -vector11: -vector12: -vector13: -vector14: -vector15: -vector16: -vector17: -vector18: -vector19: -vector20: -vector21: -vector22: -vector23: -vector24: -vector25: -vector26: -vector27: -vector28: -vector29: -vector30: -vector31: -vector32: -vector33: -vector34: -vector35: -vector36: -vector37: -vector38: -vector39: -vector40: -vector41: -vector42: -vector43: -vector44: -vector45: -vector46: -vector47: -vector48: -vector49: -vector50: -vector51: -vector52: -vector53: -vector54: -vector55: -vector56: -vector57: -vector58: -vector59: -vector60: -vector61: -vector62: -vector63: -vector64: -vector65: -vector66: -vector67: -vector68: -vector69: -vector70: -vector71: -vector72: -vector73: -vector74: -vector75: -vector76: -vector77: -vector78: -vector79: -vector80: -vector81: -vector82: -vector83: -vector84: -vector85: -vector86: -vector87: -vector88: -vector89: -vector90: -vector91: -vector92: -vector93: -vector94: -vector95: -vector96: -vector97: -vector98: -vector99: -vector100: -vector101: -vector102: -vector103: -vector104: -vector105: -vector106: -vector107: -vector108: -vector109: -vector110: -vector111: -vector112: -vector113: -vector114: -vector115: -vector116: -vector117: -vector118: -vector119: -vector120: -vector121: -vector122: -vector123: -vector124: -vector125: -vector126: -vector127: -vector128: -vector129: -vector130: -vector131: -vector132: -vector133: -vector134: -vector135: -vector136: -vector137: -vector138: -vector139: -vector140: -vector141: -vector142: -vector143: -vector144: -vector145: -vector146: -vector147: -vector148: -vector149: -vector150: -vector151: -vector152: -vector153: -vector154: -vector155: -vector156: -vector157: -vector158: -vector159: -vector160: -vector161: -vector162: -vector163: -vector164: -vector165: -vector166: -vector167: -vector168: -vector169: -vector170: -vector171: -vector172: -vector173: -vector174: -vector175: -vector176: -vector177: -vector178: -vector179: -vector180: -vector181: -vector182: -vector183: -vector184: -vector185: -vector186: -vector187: -vector188: -vector189: -vector190: -vector191: -vector192: -vector193: -vector194: -vector195: -vector196: -vector197: -vector198: -vector199: -vector200: -vector201: -vector202: -vector203: -vector204: -vector205: -vector206: -vector207: -vector208: -vector209: -vector210: -vector211: -vector212: -vector213: -vector214: -vector215: -vector216: -vector217: -vector218: -vector219: -vector220: -vector221: -vector222: -vector223: -vector224: -vector225: -vector226: -vector227: -vector228: -vector229: -vector230: -vector231: -vector232: -vector233: -vector234: -vector235: -vector236: -vector237: -vector238: -vector239: -vector240: -vector241: -vector242: -vector243: -vector244: -vector245: -vector246: -vector247: -vector248: -vector249: -vector250: -vector251: -vector252: -vector253: -vector254: -vector255: -vector256: -vector257: -vector258: -vector259: -vector260: -vector261: -vector262: -vector263: -vector264: -vector265: -vector266: -vector267: -vector268: -vector269: -vector270: -vector271: -vector272: -vector273: -vector274: -vector275: -vector276: -vector277: -vector278: -vector279: -vector280: -vector281: -vector282: -vector283: -vector284: -vector285: -vector286: -vector287: -vector288: -vector289: -vector290: -vector291: -vector292: -vector293: -vector294: -vector295: -vector296: -vector297: -vector298: -vector299: -vector300: -vector301: -vector302: -vector303: -vector304: -vector305: -vector306: -vector307: -vector308: -vector309: -vector310: -vector311: -vector312: -vector313: -vector314: -vector315: -vector316: -vector317: -vector318: -vector319: -vector320: -vector321: -vector322: -vector323: -vector324: -vector325: -vector326: -vector327: -vector328: -vector329: -vector330: -vector331: -vector332: -vector333: -vector334: -vector335: -vector336: -vector337: -vector338: -vector339: -vector340: -vector341: -vector342: -vector343: -vector344: -vector345: -vector346: -vector347: -vector348: -vector349: -vector350: -vector351: -vector352: -vector353: -vector354: -vector355: -vector356: -vector357: -vector358: -vector359: -vector360: -vector361: -vector362: -vector363: -vector364: -vector365: -vector366: -vector367: -vector368: -vector369: -vector370: -vector371: -vector372: -vector373: -vector374: -vector375: -vector376: -vector377: -vector378: -vector379: -vector380: -vector381: -vector382: -vector383: -vector384: -vector385: -vector386: -vector387: -vector388: -vector389: -vector390: -vector391: -vector392: -vector393: -vector394: -vector395: -vector396: -vector397: -vector398: -vector399: -vector400: -vector401: -vector402: -vector403: -vector404: -vector405: -vector406: -vector407: -vector408: -vector409: -vector410: -vector411: -vector412: -vector413: -vector414: -vector415: -vector416: -vector417: -vector418: -vector419: -vector420: -vector421: -vector422: -vector423: -vector424: -vector425: -vector426: -vector427: -vector428: -vector429: -vector430: -vector431: -vector432: -vector433: -vector434: -vector435: -vector436: -vector437: -vector438: -vector439: -vector440: -vector441: -vector442: -vector443: -vector444: -vector445: -vector446: -vector447: -vector448: -vector449: -vector450: -vector451: -vector452: -vector453: -vector454: -vector455: -vector456: -vector457: -vector458: -vector459: -vector460: -vector461: -vector462: -vector463: -vector464: -vector465: -vector466: -vector467: -vector468: -vector469: -vector470: -vector471: -vector472: -vector473: -vector474: -vector475: -vector476: -vector477: -vector478: -vector479: -vector480: -vector481: -vector482: -vector483: -vector484: -vector485: -vector486: -vector487: -vector488: -vector489: -vector490: -vector491: -vector492: -vector493: -vector494: -vector495: -vector496: -vector497: -vector498: -vector499: -vector500: -vector501: -vector502: -vector503: -vector504: -vector505: -vector506: -vector507: -vector508: -vector509: -vector510: -vector511: -vector512: -vector513: -vector514: -vector515: -vector516: -vector517: -vector518: -vector519: -vector520: -vector521: -vector522: -vector523: -vector524: -vector525: -vector526: -vector527: -vector528: -vector529: -vector530: -vector531: -vector532: -vector533: -vector534: -vector535: -vector536: -vector537: -vector538: -vector539: -vector540: -vector541: -vector542: -vector543: -vector544: -vector545: -vector546: -vector547: -vector548: -vector549: -vector550: -vector551: -vector552: -vector553: -vector554: -vector555: -vector556: -vector557: -vector558: -vector559: -vector560: -vector561: -vector562: -vector563: -vector564: -vector565: -vector566: -vector567: -vector568: -vector569: -vector570: -vector571: -vector572: -vector573: -vector574: -vector575: -vector576: -vector577: -vector578: -vector579: -vector580: -vector581: -vector582: -vector583: -vector584: -vector585: -vector586: -vector587: -vector588: -vector589: -vector590: -vector591: -vector592: -vector593: -vector594: -vector595: -vector596: -vector597: -vector598: -vector599: -vector600: -vector601: -vector602: -vector603: -vector604: -vector605: -vector606: -vector607: -vector608: -vector609: -vector610: -vector611: -vector612: -vector613: -vector614: -vector615: -vector616: -vector617: -vector618: -vector619: -vector620: -vector621: -vector622: -vector623: -vector624: -vector625: -vector626: -vector627: -vector628: -vector629: -vector630: -vector631: -vector632: -vector633: -vector634: -vector635: -vector636: -vector637: -vector638: -vector639: -vector640: -vector641: -vector642: -vector643: -vector644: -vector645: -vector646: -vector647: -vector648: -vector649: -vector650: -vector651: -vector652: -vector653: -vector654: -vector655: -vector656: -vector657: -vector658: -vector659: -vector660: -vector661: -vector662: -vector663: -vector664: -vector665: -vector666: -vector667: -vector668: -vector669: -vector670: -vector671: -vector672: -vector673: -vector674: -vector675: -vector676: -vector677: -vector678: -vector679: -vector680: -vector681: -vector682: -vector683: -vector684: -vector685: -vector686: -vector687: -vector688: -vector689: -vector690: -vector691: -vector692: -vector693: -vector694: -vector695: -vector696: -vector697: -vector698: -vector699: -vector700: -vector701: -vector702: -vector703: -vector704: -vector705: -vector706: -vector707: -vector708: -vector709: -vector710: -vector711: -vector712: -vector713: -vector714: -vector715: -vector716: -vector717: -vector718: -vector719: -vector720: -vector721: -vector722: -vector723: -vector724: -vector725: -vector726: -vector727: -vector728: -vector729: -vector730: -vector731: -vector732: -vector733: -vector734: -vector735: -vector736: -vector737: -vector738: -vector739: -vector740: -vector741: -vector742: -vector743: -vector744: -vector745: -vector746: -vector747: -vector748: -vector749: -vector750: -vector751: -vector752: -vector753: -vector754: -vector755: -vector756: -vector757: -vector758: -vector759: -vector760: -vector761: -vector762: -vector763: -vector764: -vector765: -vector766: -vector767: -vector768: -vector769: -vector770: -vector771: -vector772: -vector773: -vector774: -vector775: -vector776: -vector777: -vector778: -vector779: -vector780: -vector781: -vector782: -vector783: -vector784: -vector785: -vector786: -vector787: -vector788: -vector789: -vector790: -vector791: -vector792: -vector793: -vector794: -vector795: -vector796: -vector797: -vector798: -vector799: -vector800: -vector801: -vector802: -vector803: -vector804: -vector805: -vector806: -vector807: -vector808: -vector809: -vector810: -vector811: -vector812: -vector813: -vector814: -vector815: -vector816: -vector817: -vector818: -vector819: -vector820: -vector821: -vector822: -vector823: -vector824: -vector825: -vector826: -vector827: -vector828: -vector829: -vector830: -vector831: -vector832: -vector833: -vector834: -vector835: -vector836: -vector837: -vector838: -vector839: -vector840: -vector841: -vector842: -vector843: -vector844: -vector845: -vector846: -vector847: -vector848: -vector849: -vector850: -vector851: -vector852: -vector853: -vector854: -vector855: -vector856: -vector857: -vector858: -vector859: -vector860: -vector861: -vector862: -vector863: -vector864: -vector865: -vector866: -vector867: -vector868: -vector869: -vector870: -vector871: -vector872: -vector873: -vector874: -vector875: -vector876: -vector877: -vector878: -vector879: -vector880: -vector881: -vector882: -vector883: -vector884: -vector885: -vector886: -vector887: -vector888: -vector889: -vector890: -vector891: -vector892: -vector893: -vector894: -vector895: -vector896: -vector897: -vector898: -vector899: -vector900: -vector901: -vector902: -vector903: -vector904: -vector905: -vector906: -vector907: -vector908: -vector909: -vector910: -vector911: -vector912: -vector913: -vector914: -vector915: -vector916: -vector917: -vector918: -vector919: -vector920: -vector921: -vector922: -vector923: -vector924: -vector925: -vector926: -vector927: -vector928: -vector929: -vector930: -vector931: -vector932: -vector933: -vector934: -vector935: -vector936: -vector937: -vector938: -vector939: -vector940: -vector941: -vector942: -vector943: -vector944: -vector945: -vector946: -vector947: -vector948: -vector949: -vector950: -vector951: -vector952: -vector953: -vector954: -vector955: -vector956: -vector957: -vector958: -vector959: -vector960: -vector961: -vector962: -vector963: -vector964: -vector965: -vector966: -vector967: -vector968: -vector969: -vector970: -vector971: -vector972: -vector973: -vector974: -vector975: -vector976: -vector977: -vector978: -vector979: -vector980: -vector981: -vector982: -vector983: -vector984: -vector985: -vector986: -vector987: -vector988: -vector989: -vector990: -vector991: -vector992: -vector993: -vector994: -vector995: -vector996: -vector997: -vector998: -vector999: -vector1000: -vector1001: -vector1002: -vector1003: -vector1004: -vector1005: -vector1006: -vector1007: -vector1008: -vector1009: -vector1010: -vector1011: -vector1012: -vector1013: -vector1014: -vector1015: -vector1016: -vector1017: -vector1018: -vector1019: -vector1020: -vector1021: -vector1022: -vector1023: - - .global _unhandled_irq -_unhandled_irq: - se_b _unhandled_irq - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/compilers/CW/vectors.h b/firmware/ChibiOS_16/os/common/ports/e200/compilers/CW/vectors.h deleted file mode 100644 index 414ad415d1..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/compilers/CW/vectors.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file vectors.h - * @brief ISR vector module header. - * - * @addtogroup PPC_CW_CORE - * @{ - */ - -#ifndef _VECTORS_H_ -#define _VECTORS_H_ - -#include "ppcparams.h" - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/* The following code is not processed when the file is included from an - asm module.*/ -#if !defined(_FROM_ASM_) - -#if !defined(__DOXYGEN__) -extern uint32_t _vectors[PPC_NUM_VECTORS]; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void _unhandled_irq(void); -#ifdef __cplusplus -} -#endif - -#endif /* !defined(_FROM_ASM_) */ - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -#endif /* _VECTORS_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/compilers/CW/vectors.s b/firmware/ChibiOS_16/os/common/ports/e200/compilers/CW/vectors.s deleted file mode 100644 index 3850446718..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/compilers/CW/vectors.s +++ /dev/null @@ -1,1577 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file vectors.s - * @brief SPC56x vectors table. - * - * @addtogroup PPC_CW_CORE - * @{ - */ - -#define _FROM_ASM_ -#include "ppcparams.h" - -#if defined(VECTORS_RENAMING) -#include "isrs.h" -#endif - -#if !defined(__DOXYGEN__) - - .global vector0, vector1, vector2, vector3 -#if PPC_NUM_VECTORS > 4 - .global vector4, vector5, vector6, vector7 -#endif -#if PPC_NUM_VECTORS > 8 - .global vector8, vector9, vector10, vector11 -#endif -#if PPC_NUM_VECTORS > 12 - .global vector12, vector13, vector14, vector15 -#endif -#if PPC_NUM_VECTORS > 16 - .global vector16, vector17, vector18, vector19 -#endif -#if PPC_NUM_VECTORS > 20 - .global vector20, vector21, vector22, vector23 -#endif -#if PPC_NUM_VECTORS > 24 - .global vector24, vector25, vector26, vector27 -#endif -#if PPC_NUM_VECTORS > 28 - .global vector28, vector29, vector30, vector31 -#endif -#if PPC_NUM_VECTORS > 32 - .global vector32, vector33, vector34, vector35 -#endif -#if PPC_NUM_VECTORS > 36 - .global vector36, vector37, vector38, vector39 -#endif -#if PPC_NUM_VECTORS > 40 - .global vector40, vector41, vector42, vector43 -#endif -#if PPC_NUM_VECTORS > 44 - .global vector44, vector45, vector46, vector47 -#endif -#if PPC_NUM_VECTORS > 48 - .global vector48, vector49, vector50, vector51 -#endif -#if PPC_NUM_VECTORS > 52 - .global vector52, vector53, vector54, vector55 -#endif -#if PPC_NUM_VECTORS > 56 - .global vector56, vector57, vector58, vector59 -#endif -#if PPC_NUM_VECTORS > 60 - .global vector60, vector61, vector62, vector63 -#endif -#if PPC_NUM_VECTORS > 64 - .global vector64, vector65, vector66, vector67 -#endif -#if PPC_NUM_VECTORS > 68 - .global vector68, vector69, vector70, vector71 -#endif -#if PPC_NUM_VECTORS > 72 - .global vector72, vector73, vector74, vector75 -#endif -#if PPC_NUM_VECTORS > 76 - .global vector76, vector77, vector78, vector79 -#endif -#if PPC_NUM_VECTORS > 80 - .global vector80, vector81, vector82, vector83 -#endif -#if PPC_NUM_VECTORS > 84 - .global vector84, vector85, vector86, vector87 -#endif -#if PPC_NUM_VECTORS > 88 - .global vector88, vector89, vector90, vector91 -#endif -#if PPC_NUM_VECTORS > 92 - .global vector92, vector93, vector94, vector95 -#endif -#if PPC_NUM_VECTORS > 96 - .global vector96, vector97, vector98, vector99 -#endif -#if PPC_NUM_VECTORS > 100 - .global vector100, vector101, vector102, vector103 -#endif -#if PPC_NUM_VECTORS > 104 - .global vector104, vector105, vector106, vector107 -#endif -#if PPC_NUM_VECTORS > 108 - .global vector108, vector109, vector110, vector111 -#endif -#if PPC_NUM_VECTORS > 112 - .global vector112, vector113, vector114, vector115 -#endif -#if PPC_NUM_VECTORS > 116 - .global vector116, vector117, vector118, vector119 -#endif -#if PPC_NUM_VECTORS > 120 - .global vector120, vector121, vector122, vector123 -#endif -#if PPC_NUM_VECTORS > 124 - .global vector124, vector125, vector126, vector127 -#endif -#if PPC_NUM_VECTORS > 128 - .global vector128, vector129, vector130, vector131 -#endif -#if PPC_NUM_VECTORS > 132 - .global vector132, vector133, vector134, vector135 -#endif -#if PPC_NUM_VECTORS > 136 - .global vector136, vector137, vector138, vector139 -#endif -#if PPC_NUM_VECTORS > 140 - .global vector140, vector141, vector142, vector143 -#endif -#if PPC_NUM_VECTORS > 144 - .global vector144, vector145, vector146, vector147 -#endif -#if PPC_NUM_VECTORS > 148 - .global vector148, vector149, vector150, vector151 -#endif -#if PPC_NUM_VECTORS > 152 - .global vector152, vector153, vector154, vector155 -#endif -#if PPC_NUM_VECTORS > 156 - .global vector156, vector157, vector158, vector159 -#endif -#if PPC_NUM_VECTORS > 160 - .global vector160, vector161, vector162, vector163 -#endif -#if PPC_NUM_VECTORS > 164 - .global vector164, vector165, vector166, vector167 -#endif -#if PPC_NUM_VECTORS > 168 - .global vector168, vector169, vector170, vector171 -#endif -#if PPC_NUM_VECTORS > 172 - .global vector172, vector173, vector174, vector175 -#endif -#if PPC_NUM_VECTORS > 176 - .global vector176, vector177, vector178, vector179 -#endif -#if PPC_NUM_VECTORS > 180 - .global vector180, vector181, vector182, vector183 -#endif -#if PPC_NUM_VECTORS > 184 - .global vector184, vector185, vector186, vector187 -#endif -#if PPC_NUM_VECTORS > 188 - .global vector188, vector189, vector190, vector191 -#endif -#if PPC_NUM_VECTORS > 192 - .global vector192, vector193, vector194, vector195 -#endif -#if PPC_NUM_VECTORS > 196 - .global vector196, vector197, vector198, vector199 -#endif -#if PPC_NUM_VECTORS > 200 - .global vector200, vector201, vector202, vector203 -#endif -#if PPC_NUM_VECTORS > 204 - .global vector204, vector205, vector206, vector207 -#endif -#if PPC_NUM_VECTORS > 208 - .global vector208, vector209, vector210, vector211 -#endif -#if PPC_NUM_VECTORS > 212 - .global vector212, vector213, vector214, vector215 -#endif -#if PPC_NUM_VECTORS > 216 - .global vector216, vector217, vector218, vector219 -#endif -#if PPC_NUM_VECTORS > 220 - .global vector220, vector221, vector222, vector223 -#endif -#if PPC_NUM_VECTORS > 224 - .global vector224, vector225, vector226, vector227 -#endif -#if PPC_NUM_VECTORS > 228 - .global vector228, vector229, vector230, vector231 -#endif -#if PPC_NUM_VECTORS > 232 - .global vector232, vector233, vector234, vector235 -#endif -#if PPC_NUM_VECTORS > 236 - .global vector236, vector237, vector238, vector239 -#endif -#if PPC_NUM_VECTORS > 240 - .global vector240, vector241, vector242, vector243 -#endif -#if PPC_NUM_VECTORS > 244 - .global vector244, vector245, vector246, vector247 -#endif -#if PPC_NUM_VECTORS > 248 - .global vector248, vector249, vector250, vector251 -#endif -#if PPC_NUM_VECTORS > 252 - .global vector252, vector253, vector254, vector255 -#endif -#if PPC_NUM_VECTORS > 256 - .global vector256, vector257, vector258, vector259 -#endif -#if PPC_NUM_VECTORS > 260 - .global vector260, vector261, vector262, vector263 -#endif -#if PPC_NUM_VECTORS > 264 - .global vector264, vector265, vector266, vector267 -#endif -#if PPC_NUM_VECTORS > 268 - .global vector268, vector269, vector270, vector271 -#endif -#if PPC_NUM_VECTORS > 272 - .global vector272, vector273, vector274, vector275 -#endif -#if PPC_NUM_VECTORS > 276 - .global vector276, vector277, vector278, vector279 -#endif -#if PPC_NUM_VECTORS > 280 - .global vector280, vector281, vector282, vector283 -#endif -#if PPC_NUM_VECTORS > 284 - .global vector284, vector285, vector286, vector287 -#endif -#if PPC_NUM_VECTORS > 288 - .global vector288, vector289, vector290, vector291 -#endif -#if PPC_NUM_VECTORS > 292 - .global vector292, vector293, vector294, vector295 -#endif -#if PPC_NUM_VECTORS > 296 - .global vector296, vector297, vector298, vector299 -#endif -#if PPC_NUM_VECTORS > 300 - .global vector300, vector301, vector302, vector303 -#endif -#if PPC_NUM_VECTORS > 304 - .global vector304, vector305, vector306, vector307 -#endif -#if PPC_NUM_VECTORS > 308 - .global vector308, vector309, vector310, vector311 -#endif -#if PPC_NUM_VECTORS > 312 - .global vector312, vector313, vector314, vector315 -#endif -#if PPC_NUM_VECTORS > 316 - .global vector316, vector317, vector318, vector319 -#endif -#if PPC_NUM_VECTORS > 320 - .global vector320, vector321, vector322, vector323 -#endif -#if PPC_NUM_VECTORS > 324 - .global vector324, vector325, vector326, vector327 -#endif -#if PPC_NUM_VECTORS > 328 - .global vector328, vector329, vector330, vector331 -#endif -#if PPC_NUM_VECTORS > 332 - .global vector332, vector333, vector334, vector335 -#endif -#if PPC_NUM_VECTORS > 336 - .global vector336, vector337, vector338, vector339 -#endif -#if PPC_NUM_VECTORS > 340 - .global vector340, vector341, vector342, vector343 -#endif -#if PPC_NUM_VECTORS > 344 - .global vector344, vector345, vector346, vector347 -#endif -#if PPC_NUM_VECTORS > 348 - .global vector348, vector349, vector350, vector351 -#endif -#if PPC_NUM_VECTORS > 352 - .global vector352, vector353, vector354, vector355 -#endif -#if PPC_NUM_VECTORS > 356 - .global vector356, vector357, vector358, vector359 -#endif -#if PPC_NUM_VECTORS > 360 - .global vector360, vector361, vector362, vector363 -#endif -#if PPC_NUM_VECTORS > 364 - .global vector364, vector365, vector366, vector367 -#endif -#if PPC_NUM_VECTORS > 368 - .global vector368, vector369, vector370, vector371 -#endif -#if PPC_NUM_VECTORS > 372 - .global vector372, vector373, vector374, vector375 -#endif -#if PPC_NUM_VECTORS > 376 - .global vector376, vector377, vector378, vector379 -#endif -#if PPC_NUM_VECTORS > 380 - .global vector380, vector381, vector382, vector383 -#endif -#if PPC_NUM_VECTORS > 384 - .global vector384, vector385, vector386, vector387 -#endif -#if PPC_NUM_VECTORS > 388 - .global vector388, vector389, vector390, vector391 -#endif -#if PPC_NUM_VECTORS > 392 - .global vector392, vector393, vector394, vector395 -#endif -#if PPC_NUM_VECTORS > 396 - .global vector396, vector397, vector398, vector399 -#endif -#if PPC_NUM_VECTORS > 400 - .global vector400, vector401, vector402, vector403 -#endif -#if PPC_NUM_VECTORS > 404 - .global vector404, vector405, vector406, vector407 -#endif -#if PPC_NUM_VECTORS > 408 - .global vector408, vector409, vector410, vector411 -#endif -#if PPC_NUM_VECTORS > 412 - .global vector412, vector413, vector414, vector415 -#endif -#if PPC_NUM_VECTORS > 416 - .global vector416, vector417, vector418, vector419 -#endif -#if PPC_NUM_VECTORS > 420 - .global vector420, vector421, vector422, vector423 -#endif -#if PPC_NUM_VECTORS > 424 - .global vector424, vector425, vector426, vector427 -#endif -#if PPC_NUM_VECTORS > 428 - .global vector428, vector429, vector430, vector431 -#endif -#if PPC_NUM_VECTORS > 432 - .global vector432, vector433, vector434, vector435 -#endif -#if PPC_NUM_VECTORS > 436 - .global vector436, vector437, vector438, vector439 -#endif -#if PPC_NUM_VECTORS > 440 - .global vector440, vector441, vector442, vector443 -#endif -#if PPC_NUM_VECTORS > 444 - .global vector444, vector445, vector446, vector447 -#endif -#if PPC_NUM_VECTORS > 448 - .global vector448, vector449, vector450, vector451 -#endif -#if PPC_NUM_VECTORS > 452 - .global vector452, vector453, vector454, vector455 -#endif -#if PPC_NUM_VECTORS > 456 - .global vector456, vector457, vector458, vector459 -#endif -#if PPC_NUM_VECTORS > 460 - .global vector460, vector461, vector462, vector463 -#endif -#if PPC_NUM_VECTORS > 464 - .global vector464, vector465, vector466, vector467 -#endif -#if PPC_NUM_VECTORS > 468 - .global vector468, vector469, vector470, vector471 -#endif -#if PPC_NUM_VECTORS > 472 - .global vector472, vector473, vector474, vector475 -#endif -#if PPC_NUM_VECTORS > 476 - .global vector476, vector477, vector478, vector479 -#endif -#if PPC_NUM_VECTORS > 480 - .global vector480, vector481, vector482, vector483 -#endif -#if PPC_NUM_VECTORS > 484 - .global vector484, vector485, vector486, vector487 -#endif -#if PPC_NUM_VECTORS > 488 - .global vector488, vector489, vector490, vector491 -#endif -#if PPC_NUM_VECTORS > 492 - .global vector492, vector493, vector494, vector495 -#endif -#if PPC_NUM_VECTORS > 496 - .global vector496, vector497, vector498, vector499 -#endif -#if PPC_NUM_VECTORS > 500 - .global vector500, vector501, vector502, vector503 -#endif -#if PPC_NUM_VECTORS > 504 - .global vector504, vector505, vector506, vector507 -#endif -#if PPC_NUM_VECTORS > 508 - .global vector508, vector509, vector510, vector511 -#endif -#if PPC_NUM_VECTORS > 512 - .global vector512, vector513, vector514, vector515 -#endif -#if PPC_NUM_VECTORS > 516 - .global vector516, vector517, vector518, vector519 -#endif -#if PPC_NUM_VECTORS > 520 - .global vector520, vector521, vector522, vector523 -#endif -#if PPC_NUM_VECTORS > 524 - .global vector524, vector525, vector526, vector527 -#endif -#if PPC_NUM_VECTORS > 528 - .global vector528, vector529, vector530, vector531 -#endif -#if PPC_NUM_VECTORS > 532 - .global vector532, vector533, vector534, vector535 -#endif -#if PPC_NUM_VECTORS > 536 - .global vector536, vector537, vector538, vector539 -#endif -#if PPC_NUM_VECTORS > 540 - .global vector540, vector541, vector542, vector543 -#endif -#if PPC_NUM_VECTORS > 544 - .global vector544, vector545, vector546, vector547 -#endif -#if PPC_NUM_VECTORS > 548 - .global vector548, vector549, vector550, vector551 -#endif -#if PPC_NUM_VECTORS > 552 - .global vector552, vector553, vector554, vector555 -#endif -#if PPC_NUM_VECTORS > 556 - .global vector556, vector557, vector558, vector559 -#endif -#if PPC_NUM_VECTORS > 560 - .global vector560, vector561, vector562, vector563 -#endif -#if PPC_NUM_VECTORS > 564 - .global vector564, vector565, vector566, vector567 -#endif -#if PPC_NUM_VECTORS > 568 - .global vector568, vector569, vector570, vector571 -#endif -#if PPC_NUM_VECTORS > 572 - .global vector572, vector573, vector574, vector575 -#endif -#if PPC_NUM_VECTORS > 576 - .global vector576, vector577, vector578, vector579 -#endif -#if PPC_NUM_VECTORS > 580 - .global vector580, vector581, vector582, vector583 -#endif -#if PPC_NUM_VECTORS > 584 - .global vector584, vector585, vector586, vector587 -#endif -#if PPC_NUM_VECTORS > 588 - .global vector588, vector589, vector590, vector591 -#endif -#if PPC_NUM_VECTORS > 592 - .global vector592, vector593, vector594, vector595 -#endif -#if PPC_NUM_VECTORS > 596 - .global vector596, vector597, vector598, vector599 -#endif -#if PPC_NUM_VECTORS > 600 - .global vector600, vector601, vector602, vector603 -#endif -#if PPC_NUM_VECTORS > 604 - .global vector604, vector605, vector606, vector607 -#endif -#if PPC_NUM_VECTORS > 608 - .global vector608, vector609, vector610, vector611 -#endif -#if PPC_NUM_VECTORS > 612 - .global vector612, vector613, vector614, vector615 -#endif -#if PPC_NUM_VECTORS > 616 - .global vector616, vector617, vector618, vector619 -#endif -#if PPC_NUM_VECTORS > 620 - .global vector620, vector621, vector622, vector623 -#endif -#if PPC_NUM_VECTORS > 624 - .global vector624, vector625, vector626, vector627 -#endif -#if PPC_NUM_VECTORS > 628 - .global vector628, vector629, vector630, vector631 -#endif -#if PPC_NUM_VECTORS > 632 - .global vector632, vector633, vector634, vector635 -#endif -#if PPC_NUM_VECTORS > 636 - .global vector636, vector637, vector638, vector639 -#endif -#if PPC_NUM_VECTORS > 640 - .global vector640, vector641, vector642, vector643 -#endif -#if PPC_NUM_VECTORS > 644 - .global vector644, vector645, vector646, vector647 -#endif -#if PPC_NUM_VECTORS > 648 - .global vector648, vector649, vector650, vector651 -#endif -#if PPC_NUM_VECTORS > 652 - .global vector652, vector653, vector654, vector655 -#endif -#if PPC_NUM_VECTORS > 656 - .global vector656, vector657, vector658, vector659 -#endif -#if PPC_NUM_VECTORS > 660 - .global vector660, vector661, vector662, vector663 -#endif -#if PPC_NUM_VECTORS > 664 - .global vector664, vector665, vector666, vector667 -#endif -#if PPC_NUM_VECTORS > 668 - .global vector668, vector669, vector670, vector671 -#endif -#if PPC_NUM_VECTORS > 672 - .global vector672, vector673, vector674, vector675 -#endif -#if PPC_NUM_VECTORS > 676 - .global vector676, vector677, vector678, vector679 -#endif -#if PPC_NUM_VECTORS > 680 - .global vector680, vector681, vector682, vector683 -#endif -#if PPC_NUM_VECTORS > 684 - .global vector684, vector685, vector686, vector687 -#endif -#if PPC_NUM_VECTORS > 688 - .global vector688, vector689, vector690, vector691 -#endif -#if PPC_NUM_VECTORS > 692 - .global vector692, vector693, vector694, vector695 -#endif -#if PPC_NUM_VECTORS > 696 - .global vector696, vector697, vector698, vector699 -#endif -#if PPC_NUM_VECTORS > 700 - .global vector700, vector701, vector702, vector703 -#endif -#if PPC_NUM_VECTORS > 704 - .global vector704, vector705, vector706, vector707 -#endif -#if PPC_NUM_VECTORS > 708 - .global vector708, vector709, vector710, vector711 -#endif -#if PPC_NUM_VECTORS > 712 - .global vector712, vector713, vector714, vector715 -#endif -#if PPC_NUM_VECTORS > 716 - .global vector716, vector717, vector718, vector719 -#endif -#if PPC_NUM_VECTORS > 720 - .global vector720, vector721, vector722, vector723 -#endif -#if PPC_NUM_VECTORS > 724 - .global vector724, vector725, vector726, vector727 -#endif -#if PPC_NUM_VECTORS > 728 - .global vector728, vector729, vector730, vector731 -#endif -#if PPC_NUM_VECTORS > 732 - .global vector732, vector733, vector734, vector735 -#endif -#if PPC_NUM_VECTORS > 736 - .global vector736, vector737, vector738, vector739 -#endif -#if PPC_NUM_VECTORS > 740 - .global vector740, vector741, vector742, vector743 -#endif -#if PPC_NUM_VECTORS > 744 - .global vector744, vector745, vector746, vector747 -#endif -#if PPC_NUM_VECTORS > 748 - .global vector748, vector749, vector750, vector751 -#endif -#if PPC_NUM_VECTORS > 752 - .global vector752, vector753, vector754, vector755 -#endif -#if PPC_NUM_VECTORS > 756 - .global vector756, vector757, vector758, vector759 -#endif -#if PPC_NUM_VECTORS > 760 - .global vector760, vector761, vector762, vector763 -#endif -#if PPC_NUM_VECTORS > 764 - .global vector764, vector765, vector766, vector767 -#endif -#if PPC_NUM_VECTORS > 768 - .global vector768, vector769, vector770, vector771 -#endif -#if PPC_NUM_VECTORS > 772 - .global vector772, vector773, vector774, vector775 -#endif -#if PPC_NUM_VECTORS > 776 - .global vector776, vector777, vector778, vector779 -#endif -#if PPC_NUM_VECTORS > 780 - .global vector780, vector781, vector782, vector783 -#endif -#if PPC_NUM_VECTORS > 784 - .global vector784, vector785, vector786, vector787 -#endif -#if PPC_NUM_VECTORS > 788 - .global vector788, vector789, vector790, vector791 -#endif -#if PPC_NUM_VECTORS > 792 - .global vector792, vector793, vector794, vector795 -#endif -#if PPC_NUM_VECTORS > 796 - .global vector796, vector797, vector798, vector799 -#endif -#if PPC_NUM_VECTORS > 800 - .global vector800, vector801, vector802, vector803 -#endif -#if PPC_NUM_VECTORS > 804 - .global vector804, vector805, vector806, vector807 -#endif -#if PPC_NUM_VECTORS > 808 - .global vector808, vector809, vector810, vector811 -#endif -#if PPC_NUM_VECTORS > 812 - .global vector812, vector813, vector814, vector815 -#endif -#if PPC_NUM_VECTORS > 816 - .global vector816, vector817, vector818, vector819 -#endif -#if PPC_NUM_VECTORS > 820 - .global vector820, vector821, vector822, vector823 -#endif -#if PPC_NUM_VECTORS > 824 - .global vector824, vector825, vector826, vector827 -#endif -#if PPC_NUM_VECTORS > 828 - .global vector828, vector829, vector830, vector831 -#endif -#if PPC_NUM_VECTORS > 832 - .global vector832, vector833, vector834, vector835 -#endif -#if PPC_NUM_VECTORS > 836 - .global vector836, vector837, vector838, vector839 -#endif -#if PPC_NUM_VECTORS > 840 - .global vector840, vector841, vector842, vector843 -#endif -#if PPC_NUM_VECTORS > 844 - .global vector844, vector845, vector846, vector847 -#endif -#if PPC_NUM_VECTORS > 848 - .global vector848, vector849, vector850, vector851 -#endif -#if PPC_NUM_VECTORS > 852 - .global vector852, vector853, vector854, vector855 -#endif -#if PPC_NUM_VECTORS > 856 - .global vector856, vector857, vector858, vector859 -#endif -#if PPC_NUM_VECTORS > 860 - .global vector860, vector861, vector862, vector863 -#endif -#if PPC_NUM_VECTORS > 864 - .global vector864, vector865, vector866, vector867 -#endif -#if PPC_NUM_VECTORS > 868 - .global vector868, vector869, vector870, vector871 -#endif -#if PPC_NUM_VECTORS > 872 - .global vector872, vector873, vector874, vector875 -#endif -#if PPC_NUM_VECTORS > 876 - .global vector876, vector877, vector878, vector879 -#endif -#if PPC_NUM_VECTORS > 880 - .global vector880, vector881, vector882, vector883 -#endif -#if PPC_NUM_VECTORS > 884 - .global vector884, vector885, vector886, vector887 -#endif -#if PPC_NUM_VECTORS > 888 - .global vector888, vector889, vector890, vector891 -#endif -#if PPC_NUM_VECTORS > 892 - .global vector892, vector893, vector894, vector895 -#endif -#if PPC_NUM_VECTORS > 896 - .global vector896, vector897, vector898, vector899 -#endif -#if PPC_NUM_VECTORS > 900 - .global vector900, vector901, vector902, vector903 -#endif -#if PPC_NUM_VECTORS > 904 - .global vector904, vector905, vector906, vector907 -#endif -#if PPC_NUM_VECTORS > 908 - .global vector908, vector909, vector910, vector911 -#endif -#if PPC_NUM_VECTORS > 912 - .global vector912, vector913, vector914, vector915 -#endif -#if PPC_NUM_VECTORS > 916 - .global vector916, vector917, vector918, vector919 -#endif -#if PPC_NUM_VECTORS > 920 - .global vector920, vector921, vector922, vector923 -#endif -#if PPC_NUM_VECTORS > 924 - .global vector924, vector925, vector926, vector927 -#endif -#if PPC_NUM_VECTORS > 928 - .global vector928, vector929, vector930, vector931 -#endif -#if PPC_NUM_VECTORS > 932 - .global vector932, vector933, vector934, vector935 -#endif -#if PPC_NUM_VECTORS > 936 - .global vector936, vector937, vector938, vector939 -#endif -#if PPC_NUM_VECTORS > 940 - .global vector940, vector941, vector942, vector943 -#endif -#if PPC_NUM_VECTORS > 944 - .global vector944, vector945, vector946, vector947 -#endif -#if PPC_NUM_VECTORS > 948 - .global vector948, vector949, vector950, vector951 -#endif -#if PPC_NUM_VECTORS > 952 - .global vector952, vector953, vector954, vector955 -#endif -#if PPC_NUM_VECTORS > 956 - .global vector956, vector957, vector958, vector959 -#endif -#if PPC_NUM_VECTORS > 960 - .global vector960, vector961, vector962, vector963 -#endif -#if PPC_NUM_VECTORS > 964 - .global vector964, vector965, vector966, vector967 -#endif -#if PPC_NUM_VECTORS > 968 - .global vector968, vector969, vector970, vector971 -#endif -#if PPC_NUM_VECTORS > 972 - .global vector972, vector973, vector974, vector975 -#endif -#if PPC_NUM_VECTORS > 976 - .global vector976, vector977, vector978, vector979 -#endif -#if PPC_NUM_VECTORS > 980 - .global vector980, vector981, vector982, vector983 -#endif -#if PPC_NUM_VECTORS > 984 - .global vector984, vector985, vector986, vector987 -#endif -#if PPC_NUM_VECTORS > 988 - .global vector988, vector989, vector990, vector991 -#endif -#if PPC_NUM_VECTORS > 992 - .global vector992, vector993, vector994, vector995 -#endif -#if PPC_NUM_VECTORS > 996 - .global vector996, vector997, vector998, vector999 -#endif -#if PPC_NUM_VECTORS > 1000 - .global vector1000, vector1001, vector1002, vector1003 -#endif -#if PPC_NUM_VECTORS > 1004 - .global vector1004, vector1005, vector1006, vector1007 -#endif -#if PPC_NUM_VECTORS > 1008 - .global vector1008, vector1009, vector1010, vector1011 -#endif -#if PPC_NUM_VECTORS > 1012 - .global vector1012, vector1013, vector1014, vector1015 -#endif -#if PPC_NUM_VECTORS > 1016 - .global vector1016, vector1017, vector1018, vector1019 -#endif -#if PPC_NUM_VECTORS > 1020 - .global vector1020, vector1021, vector1022, vector1023 -#endif - - /* Software vectors table. The vectors are accessed from the IVOR4 - handler only. In order to declare an interrupt handler just create - a function withe the same name of a vector, the symbol will - override the weak symbol declared here.*/ - .section .vectors - .globl _vectors -_vectors: - .long vector0, vector1, vector2, vector3 -#if PPC_NUM_VECTORS > 4 - .long vector4, vector5, vector6, vector7 -#endif -#if PPC_NUM_VECTORS > 8 - .long vector8, vector9, vector10, vector11 -#endif -#if PPC_NUM_VECTORS > 12 - .long vector12, vector13, vector14, vector15 -#endif -#if PPC_NUM_VECTORS > 16 - .long vector16, vector17, vector18, vector19 -#endif -#if PPC_NUM_VECTORS > 20 - .long vector20, vector21, vector22, vector23 -#endif -#if PPC_NUM_VECTORS > 24 - .long vector24, vector25, vector26, vector27 -#endif -#if PPC_NUM_VECTORS > 28 - .long vector28, vector29, vector30, vector31 -#endif -#if PPC_NUM_VECTORS > 32 - .long vector32, vector33, vector34, vector35 -#endif -#if PPC_NUM_VECTORS > 36 - .long vector36, vector37, vector38, vector39 -#endif -#if PPC_NUM_VECTORS > 40 - .long vector40, vector41, vector42, vector43 -#endif -#if PPC_NUM_VECTORS > 44 - .long vector44, vector45, vector46, vector47 -#endif -#if PPC_NUM_VECTORS > 48 - .long vector48, vector49, vector50, vector51 -#endif -#if PPC_NUM_VECTORS > 52 - .long vector52, vector53, vector54, vector55 -#endif -#if PPC_NUM_VECTORS > 56 - .long vector56, vector57, vector58, vector59 -#endif -#if PPC_NUM_VECTORS > 60 - .long vector60, vector61, vector62, vector63 -#endif -#if PPC_NUM_VECTORS > 64 - .long vector64, vector65, vector66, vector67 -#endif -#if PPC_NUM_VECTORS > 68 - .long vector68, vector69, vector70, vector71 -#endif -#if PPC_NUM_VECTORS > 72 - .long vector72, vector73, vector74, vector75 -#endif -#if PPC_NUM_VECTORS > 76 - .long vector76, vector77, vector78, vector79 -#endif -#if PPC_NUM_VECTORS > 80 - .long vector80, vector81, vector82, vector83 -#endif -#if PPC_NUM_VECTORS > 84 - .long vector84, vector85, vector86, vector87 -#endif -#if PPC_NUM_VECTORS > 88 - .long vector88, vector89, vector90, vector91 -#endif -#if PPC_NUM_VECTORS > 92 - .long vector92, vector93, vector94, vector95 -#endif -#if PPC_NUM_VECTORS > 96 - .long vector96, vector97, vector98, vector99 -#endif -#if PPC_NUM_VECTORS > 100 - .long vector100, vector101, vector102, vector103 -#endif -#if PPC_NUM_VECTORS > 104 - .long vector104, vector105, vector106, vector107 -#endif -#if PPC_NUM_VECTORS > 108 - .long vector108, vector109, vector110, vector111 -#endif -#if PPC_NUM_VECTORS > 112 - .long vector112, vector113, vector114, vector115 -#endif -#if PPC_NUM_VECTORS > 116 - .long vector116, vector117, vector118, vector119 -#endif -#if PPC_NUM_VECTORS > 120 - .long vector120, vector121, vector122, vector123 -#endif -#if PPC_NUM_VECTORS > 124 - .long vector124, vector125, vector126, vector127 -#endif -#if PPC_NUM_VECTORS > 128 - .long vector128, vector129, vector130, vector131 -#endif -#if PPC_NUM_VECTORS > 132 - .long vector132, vector133, vector134, vector135 -#endif -#if PPC_NUM_VECTORS > 136 - .long vector136, vector137, vector138, vector139 -#endif -#if PPC_NUM_VECTORS > 140 - .long vector140, vector141, vector142, vector143 -#endif -#if PPC_NUM_VECTORS > 144 - .long vector144, vector145, vector146, vector147 -#endif -#if PPC_NUM_VECTORS > 148 - .long vector148, vector149, vector150, vector151 -#endif -#if PPC_NUM_VECTORS > 152 - .long vector152, vector153, vector154, vector155 -#endif -#if PPC_NUM_VECTORS > 156 - .long vector156, vector157, vector158, vector159 -#endif -#if PPC_NUM_VECTORS > 160 - .long vector160, vector161, vector162, vector163 -#endif -#if PPC_NUM_VECTORS > 164 - .long vector164, vector165, vector166, vector167 -#endif -#if PPC_NUM_VECTORS > 168 - .long vector168, vector169, vector170, vector171 -#endif -#if PPC_NUM_VECTORS > 172 - .long vector172, vector173, vector174, vector175 -#endif -#if PPC_NUM_VECTORS > 176 - .long vector176, vector177, vector178, vector179 -#endif -#if PPC_NUM_VECTORS > 180 - .long vector180, vector181, vector182, vector183 -#endif -#if PPC_NUM_VECTORS > 184 - .long vector184, vector185, vector186, vector187 -#endif -#if PPC_NUM_VECTORS > 188 - .long vector188, vector189, vector190, vector191 -#endif -#if PPC_NUM_VECTORS > 192 - .long vector192, vector193, vector194, vector195 -#endif -#if PPC_NUM_VECTORS > 196 - .long vector196, vector197, vector198, vector199 -#endif -#if PPC_NUM_VECTORS > 200 - .long vector200, vector201, vector202, vector203 -#endif -#if PPC_NUM_VECTORS > 204 - .long vector204, vector205, vector206, vector207 -#endif -#if PPC_NUM_VECTORS > 208 - .long vector208, vector209, vector210, vector211 -#endif -#if PPC_NUM_VECTORS > 212 - .long vector212, vector213, vector214, vector215 -#endif -#if PPC_NUM_VECTORS > 216 - .long vector216, vector217, vector218, vector219 -#endif -#if PPC_NUM_VECTORS > 220 - .long vector220, vector221, vector222, vector223 -#endif -#if PPC_NUM_VECTORS > 224 - .long vector224, vector225, vector226, vector227 -#endif -#if PPC_NUM_VECTORS > 228 - .long vector228, vector229, vector230, vector231 -#endif -#if PPC_NUM_VECTORS > 232 - .long vector232, vector233, vector234, vector235 -#endif -#if PPC_NUM_VECTORS > 236 - .long vector236, vector237, vector238, vector239 -#endif -#if PPC_NUM_VECTORS > 240 - .long vector240, vector241, vector242, vector243 -#endif -#if PPC_NUM_VECTORS > 244 - .long vector244, vector245, vector246, vector247 -#endif -#if PPC_NUM_VECTORS > 248 - .long vector248, vector249, vector250, vector251 -#endif -#if PPC_NUM_VECTORS > 252 - .long vector252, vector253, vector254, vector255 -#endif -#if PPC_NUM_VECTORS > 256 - .long vector256, vector257, vector258, vector259 -#endif -#if PPC_NUM_VECTORS > 260 - .long vector260, vector261, vector262, vector263 -#endif -#if PPC_NUM_VECTORS > 264 - .long vector264, vector265, vector266, vector267 -#endif -#if PPC_NUM_VECTORS > 268 - .long vector268, vector269, vector270, vector271 -#endif -#if PPC_NUM_VECTORS > 272 - .long vector272, vector273, vector274, vector275 -#endif -#if PPC_NUM_VECTORS > 276 - .long vector276, vector277, vector278, vector279 -#endif -#if PPC_NUM_VECTORS > 280 - .long vector280, vector281, vector282, vector283 -#endif -#if PPC_NUM_VECTORS > 284 - .long vector284, vector285, vector286, vector287 -#endif -#if PPC_NUM_VECTORS > 288 - .long vector288, vector289, vector290, vector291 -#endif -#if PPC_NUM_VECTORS > 292 - .long vector292, vector293, vector294, vector295 -#endif -#if PPC_NUM_VECTORS > 296 - .long vector296, vector297, vector298, vector299 -#endif -#if PPC_NUM_VECTORS > 300 - .long vector300, vector301, vector302, vector303 -#endif -#if PPC_NUM_VECTORS > 304 - .long vector304, vector305, vector306, vector307 -#endif -#if PPC_NUM_VECTORS > 308 - .long vector308, vector309, vector310, vector311 -#endif -#if PPC_NUM_VECTORS > 312 - .long vector312, vector313, vector314, vector315 -#endif -#if PPC_NUM_VECTORS > 316 - .long vector316, vector317, vector318, vector319 -#endif -#if PPC_NUM_VECTORS > 320 - .long vector320, vector321, vector322, vector323 -#endif -#if PPC_NUM_VECTORS > 324 - .long vector324, vector325, vector326, vector327 -#endif -#if PPC_NUM_VECTORS > 328 - .long vector328, vector329, vector330, vector331 -#endif -#if PPC_NUM_VECTORS > 332 - .long vector332, vector333, vector334, vector335 -#endif -#if PPC_NUM_VECTORS > 336 - .long vector336, vector337, vector338, vector339 -#endif -#if PPC_NUM_VECTORS > 340 - .long vector340, vector341, vector342, vector343 -#endif -#if PPC_NUM_VECTORS > 344 - .long vector344, vector345, vector346, vector347 -#endif -#if PPC_NUM_VECTORS > 348 - .long vector348, vector349, vector350, vector351 -#endif -#if PPC_NUM_VECTORS > 352 - .long vector352, vector353, vector354, vector355 -#endif -#if PPC_NUM_VECTORS > 356 - .long vector356, vector357, vector358, vector359 -#endif -#if PPC_NUM_VECTORS > 360 - .long vector360, vector361, vector362, vector363 -#endif -#if PPC_NUM_VECTORS > 364 - .long vector364, vector365, vector366, vector367 -#endif -#if PPC_NUM_VECTORS > 368 - .long vector368, vector369, vector370, vector371 -#endif -#if PPC_NUM_VECTORS > 372 - .long vector372, vector373, vector374, vector375 -#endif -#if PPC_NUM_VECTORS > 376 - .long vector376, vector377, vector378, vector379 -#endif -#if PPC_NUM_VECTORS > 380 - .long vector380, vector381, vector382, vector383 -#endif -#if PPC_NUM_VECTORS > 384 - .long vector384, vector385, vector386, vector387 -#endif -#if PPC_NUM_VECTORS > 388 - .long vector388, vector389, vector390, vector391 -#endif -#if PPC_NUM_VECTORS > 392 - .long vector392, vector393, vector394, vector395 -#endif -#if PPC_NUM_VECTORS > 396 - .long vector396, vector397, vector398, vector399 -#endif -#if PPC_NUM_VECTORS > 400 - .long vector400, vector401, vector402, vector403 -#endif -#if PPC_NUM_VECTORS > 404 - .long vector404, vector405, vector406, vector407 -#endif -#if PPC_NUM_VECTORS > 408 - .long vector408, vector409, vector410, vector411 -#endif -#if PPC_NUM_VECTORS > 412 - .long vector412, vector413, vector414, vector415 -#endif -#if PPC_NUM_VECTORS > 416 - .long vector416, vector417, vector418, vector419 -#endif -#if PPC_NUM_VECTORS > 420 - .long vector420, vector421, vector422, vector423 -#endif -#if PPC_NUM_VECTORS > 424 - .long vector424, vector425, vector426, vector427 -#endif -#if PPC_NUM_VECTORS > 428 - .long vector428, vector429, vector430, vector431 -#endif -#if PPC_NUM_VECTORS > 432 - .long vector432, vector433, vector434, vector435 -#endif -#if PPC_NUM_VECTORS > 436 - .long vector436, vector437, vector438, vector439 -#endif -#if PPC_NUM_VECTORS > 440 - .long vector440, vector441, vector442, vector443 -#endif -#if PPC_NUM_VECTORS > 444 - .long vector444, vector445, vector446, vector447 -#endif -#if PPC_NUM_VECTORS > 448 - .long vector448, vector449, vector450, vector451 -#endif -#if PPC_NUM_VECTORS > 452 - .long vector452, vector453, vector454, vector455 -#endif -#if PPC_NUM_VECTORS > 456 - .long vector456, vector457, vector458, vector459 -#endif -#if PPC_NUM_VECTORS > 460 - .long vector460, vector461, vector462, vector463 -#endif -#if PPC_NUM_VECTORS > 464 - .long vector464, vector465, vector466, vector467 -#endif -#if PPC_NUM_VECTORS > 468 - .long vector468, vector469, vector470, vector471 -#endif -#if PPC_NUM_VECTORS > 472 - .long vector472, vector473, vector474, vector475 -#endif -#if PPC_NUM_VECTORS > 476 - .long vector476, vector477, vector478, vector479 -#endif -#if PPC_NUM_VECTORS > 480 - .long vector480, vector481, vector482, vector483 -#endif -#if PPC_NUM_VECTORS > 484 - .long vector484, vector485, vector486, vector487 -#endif -#if PPC_NUM_VECTORS > 488 - .long vector488, vector489, vector490, vector491 -#endif -#if PPC_NUM_VECTORS > 492 - .long vector492, vector493, vector494, vector495 -#endif -#if PPC_NUM_VECTORS > 496 - .long vector496, vector497, vector498, vector499 -#endif -#if PPC_NUM_VECTORS > 500 - .long vector500, vector501, vector502, vector503 -#endif -#if PPC_NUM_VECTORS > 504 - .long vector504, vector505, vector506, vector507 -#endif -#if PPC_NUM_VECTORS > 508 - .long vector508, vector509, vector510, vector511 -#endif -#if PPC_NUM_VECTORS > 512 - .long vector512, vector513, vector514, vector515 -#endif -#if PPC_NUM_VECTORS > 516 - .long vector516, vector517, vector518, vector519 -#endif -#if PPC_NUM_VECTORS > 520 - .long vector520, vector521, vector522, vector523 -#endif -#if PPC_NUM_VECTORS > 524 - .long vector524, vector525, vector526, vector527 -#endif -#if PPC_NUM_VECTORS > 528 - .long vector528, vector529, vector530, vector531 -#endif -#if PPC_NUM_VECTORS > 532 - .long vector532, vector533, vector534, vector535 -#endif -#if PPC_NUM_VECTORS > 536 - .long vector536, vector537, vector538, vector539 -#endif -#if PPC_NUM_VECTORS > 540 - .long vector540, vector541, vector542, vector543 -#endif -#if PPC_NUM_VECTORS > 544 - .long vector544, vector545, vector546, vector547 -#endif -#if PPC_NUM_VECTORS > 548 - .long vector548, vector549, vector550, vector551 -#endif -#if PPC_NUM_VECTORS > 552 - .long vector552, vector553, vector554, vector555 -#endif -#if PPC_NUM_VECTORS > 556 - .long vector556, vector557, vector558, vector559 -#endif -#if PPC_NUM_VECTORS > 560 - .long vector560, vector561, vector562, vector563 -#endif -#if PPC_NUM_VECTORS > 564 - .long vector564, vector565, vector566, vector567 -#endif -#if PPC_NUM_VECTORS > 568 - .long vector568, vector569, vector570, vector571 -#endif -#if PPC_NUM_VECTORS > 572 - .long vector572, vector573, vector574, vector575 -#endif -#if PPC_NUM_VECTORS > 576 - .long vector576, vector577, vector578, vector579 -#endif -#if PPC_NUM_VECTORS > 580 - .long vector580, vector581, vector582, vector583 -#endif -#if PPC_NUM_VECTORS > 584 - .long vector584, vector585, vector586, vector587 -#endif -#if PPC_NUM_VECTORS > 588 - .long vector588, vector589, vector590, vector591 -#endif -#if PPC_NUM_VECTORS > 592 - .long vector592, vector593, vector594, vector595 -#endif -#if PPC_NUM_VECTORS > 596 - .long vector596, vector597, vector598, vector599 -#endif -#if PPC_NUM_VECTORS > 600 - .long vector600, vector601, vector602, vector603 -#endif -#if PPC_NUM_VECTORS > 604 - .long vector604, vector605, vector606, vector607 -#endif -#if PPC_NUM_VECTORS > 608 - .long vector608, vector609, vector610, vector611 -#endif -#if PPC_NUM_VECTORS > 612 - .long vector612, vector613, vector614, vector615 -#endif -#if PPC_NUM_VECTORS > 616 - .long vector616, vector617, vector618, vector619 -#endif -#if PPC_NUM_VECTORS > 620 - .long vector620, vector621, vector622, vector623 -#endif -#if PPC_NUM_VECTORS > 624 - .long vector624, vector625, vector626, vector627 -#endif -#if PPC_NUM_VECTORS > 628 - .long vector628, vector629, vector630, vector631 -#endif -#if PPC_NUM_VECTORS > 632 - .long vector632, vector633, vector634, vector635 -#endif -#if PPC_NUM_VECTORS > 636 - .long vector636, vector637, vector638, vector639 -#endif -#if PPC_NUM_VECTORS > 640 - .long vector640, vector641, vector642, vector643 -#endif -#if PPC_NUM_VECTORS > 644 - .long vector644, vector645, vector646, vector647 -#endif -#if PPC_NUM_VECTORS > 648 - .long vector648, vector649, vector650, vector651 -#endif -#if PPC_NUM_VECTORS > 652 - .long vector652, vector653, vector654, vector655 -#endif -#if PPC_NUM_VECTORS > 656 - .long vector656, vector657, vector658, vector659 -#endif -#if PPC_NUM_VECTORS > 660 - .long vector660, vector661, vector662, vector663 -#endif -#if PPC_NUM_VECTORS > 664 - .long vector664, vector665, vector666, vector667 -#endif -#if PPC_NUM_VECTORS > 668 - .long vector668, vector669, vector670, vector671 -#endif -#if PPC_NUM_VECTORS > 672 - .long vector672, vector673, vector674, vector675 -#endif -#if PPC_NUM_VECTORS > 676 - .long vector676, vector677, vector678, vector679 -#endif -#if PPC_NUM_VECTORS > 680 - .long vector680, vector681, vector682, vector683 -#endif -#if PPC_NUM_VECTORS > 684 - .long vector684, vector685, vector686, vector687 -#endif -#if PPC_NUM_VECTORS > 688 - .long vector688, vector689, vector690, vector691 -#endif -#if PPC_NUM_VECTORS > 692 - .long vector692, vector693, vector694, vector695 -#endif -#if PPC_NUM_VECTORS > 696 - .long vector696, vector697, vector698, vector699 -#endif -#if PPC_NUM_VECTORS > 700 - .long vector700, vector701, vector702, vector703 -#endif -#if PPC_NUM_VECTORS > 704 - .long vector704, vector705, vector706, vector707 -#endif -#if PPC_NUM_VECTORS > 708 - .long vector708, vector709, vector710, vector711 -#endif -#if PPC_NUM_VECTORS > 712 - .long vector712, vector713, vector714, vector715 -#endif -#if PPC_NUM_VECTORS > 716 - .long vector716, vector717, vector718, vector719 -#endif -#if PPC_NUM_VECTORS > 720 - .long vector720, vector721, vector722, vector723 -#endif -#if PPC_NUM_VECTORS > 724 - .long vector724, vector725, vector726, vector727 -#endif -#if PPC_NUM_VECTORS > 728 - .long vector728, vector729, vector730, vector731 -#endif -#if PPC_NUM_VECTORS > 732 - .long vector732, vector733, vector734, vector735 -#endif -#if PPC_NUM_VECTORS > 736 - .long vector736, vector737, vector738, vector739 -#endif -#if PPC_NUM_VECTORS > 740 - .long vector740, vector741, vector742, vector743 -#endif -#if PPC_NUM_VECTORS > 744 - .long vector744, vector745, vector746, vector747 -#endif -#if PPC_NUM_VECTORS > 748 - .long vector748, vector749, vector750, vector751 -#endif -#if PPC_NUM_VECTORS > 752 - .long vector752, vector753, vector754, vector755 -#endif -#if PPC_NUM_VECTORS > 756 - .long vector756, vector757, vector758, vector759 -#endif -#if PPC_NUM_VECTORS > 760 - .long vector760, vector761, vector762, vector763 -#endif -#if PPC_NUM_VECTORS > 764 - .long vector764, vector765, vector766, vector767 -#endif -#if PPC_NUM_VECTORS > 768 - .long vector768, vector769, vector770, vector771 -#endif -#if PPC_NUM_VECTORS > 772 - .long vector772, vector773, vector774, vector775 -#endif -#if PPC_NUM_VECTORS > 776 - .long vector776, vector777, vector778, vector779 -#endif -#if PPC_NUM_VECTORS > 780 - .long vector780, vector781, vector782, vector783 -#endif -#if PPC_NUM_VECTORS > 784 - .long vector784, vector785, vector786, vector787 -#endif -#if PPC_NUM_VECTORS > 788 - .long vector788, vector789, vector790, vector791 -#endif -#if PPC_NUM_VECTORS > 792 - .long vector792, vector793, vector794, vector795 -#endif -#if PPC_NUM_VECTORS > 796 - .long vector796, vector797, vector798, vector799 -#endif -#if PPC_NUM_VECTORS > 800 - .long vector800, vector801, vector802, vector803 -#endif -#if PPC_NUM_VECTORS > 804 - .long vector804, vector805, vector806, vector807 -#endif -#if PPC_NUM_VECTORS > 808 - .long vector808, vector809, vector810, vector811 -#endif -#if PPC_NUM_VECTORS > 812 - .long vector812, vector813, vector814, vector815 -#endif -#if PPC_NUM_VECTORS > 816 - .long vector816, vector817, vector818, vector819 -#endif -#if PPC_NUM_VECTORS > 820 - .long vector820, vector821, vector822, vector823 -#endif -#if PPC_NUM_VECTORS > 824 - .long vector824, vector825, vector826, vector827 -#endif -#if PPC_NUM_VECTORS > 828 - .long vector828, vector829, vector830, vector831 -#endif -#if PPC_NUM_VECTORS > 832 - .long vector832, vector833, vector834, vector835 -#endif -#if PPC_NUM_VECTORS > 836 - .long vector836, vector837, vector838, vector839 -#endif -#if PPC_NUM_VECTORS > 840 - .long vector840, vector841, vector842, vector843 -#endif -#if PPC_NUM_VECTORS > 844 - .long vector844, vector845, vector846, vector847 -#endif -#if PPC_NUM_VECTORS > 848 - .long vector848, vector849, vector850, vector851 -#endif -#if PPC_NUM_VECTORS > 852 - .long vector852, vector853, vector854, vector855 -#endif -#if PPC_NUM_VECTORS > 856 - .long vector856, vector857, vector858, vector859 -#endif -#if PPC_NUM_VECTORS > 860 - .long vector860, vector861, vector862, vector863 -#endif -#if PPC_NUM_VECTORS > 864 - .long vector864, vector865, vector866, vector867 -#endif -#if PPC_NUM_VECTORS > 868 - .long vector868, vector869, vector870, vector871 -#endif -#if PPC_NUM_VECTORS > 872 - .long vector872, vector873, vector874, vector875 -#endif -#if PPC_NUM_VECTORS > 876 - .long vector876, vector877, vector878, vector879 -#endif -#if PPC_NUM_VECTORS > 880 - .long vector880, vector881, vector882, vector883 -#endif -#if PPC_NUM_VECTORS > 884 - .long vector884, vector885, vector886, vector887 -#endif -#if PPC_NUM_VECTORS > 888 - .long vector888, vector889, vector890, vector891 -#endif -#if PPC_NUM_VECTORS > 892 - .long vector892, vector893, vector894, vector895 -#endif -#if PPC_NUM_VECTORS > 896 - .long vector896, vector897, vector898, vector899 -#endif -#if PPC_NUM_VECTORS > 900 - .long vector900, vector901, vector902, vector903 -#endif -#if PPC_NUM_VECTORS > 904 - .long vector904, vector905, vector906, vector907 -#endif -#if PPC_NUM_VECTORS > 908 - .long vector908, vector909, vector910, vector911 -#endif -#if PPC_NUM_VECTORS > 912 - .long vector912, vector913, vector914, vector915 -#endif -#if PPC_NUM_VECTORS > 916 - .long vector916, vector917, vector918, vector919 -#endif -#if PPC_NUM_VECTORS > 920 - .long vector920, vector921, vector922, vector923 -#endif -#if PPC_NUM_VECTORS > 924 - .long vector924, vector925, vector926, vector927 -#endif -#if PPC_NUM_VECTORS > 928 - .long vector928, vector929, vector930, vector931 -#endif -#if PPC_NUM_VECTORS > 932 - .long vector932, vector933, vector934, vector935 -#endif -#if PPC_NUM_VECTORS > 936 - .long vector936, vector937, vector938, vector939 -#endif -#if PPC_NUM_VECTORS > 940 - .long vector940, vector941, vector942, vector943 -#endif -#if PPC_NUM_VECTORS > 944 - .long vector944, vector945, vector946, vector947 -#endif -#if PPC_NUM_VECTORS > 948 - .long vector948, vector949, vector950, vector951 -#endif -#if PPC_NUM_VECTORS > 952 - .long vector952, vector953, vector954, vector955 -#endif -#if PPC_NUM_VECTORS > 956 - .long vector956, vector957, vector958, vector959 -#endif -#if PPC_NUM_VECTORS > 960 - .long vector960, vector961, vector962, vector963 -#endif -#if PPC_NUM_VECTORS > 964 - .long vector964, vector965, vector966, vector967 -#endif -#if PPC_NUM_VECTORS > 968 - .long vector968, vector969, vector970, vector971 -#endif -#if PPC_NUM_VECTORS > 972 - .long vector972, vector973, vector974, vector975 -#endif -#if PPC_NUM_VECTORS > 976 - .long vector976, vector977, vector978, vector979 -#endif -#if PPC_NUM_VECTORS > 980 - .long vector980, vector981, vector982, vector983 -#endif -#if PPC_NUM_VECTORS > 984 - .long vector984, vector985, vector986, vector987 -#endif -#if PPC_NUM_VECTORS > 988 - .long vector988, vector989, vector990, vector991 -#endif -#if PPC_NUM_VECTORS > 992 - .long vector992, vector993, vector994, vector995 -#endif -#if PPC_NUM_VECTORS > 996 - .long vector996, vector997, vector998, vector999 -#endif -#if PPC_NUM_VECTORS > 1000 - .long vector1000, vector1001, vector1002, vector1003 -#endif -#if PPC_NUM_VECTORS > 1004 - .long vector1004, vector1005, vector1006, vector1007 -#endif -#if PPC_NUM_VECTORS > 1008 - .long vector1008, vector1009, vector1010, vector1011 -#endif -#if PPC_NUM_VECTORS > 1012 - .long vector1012, vector1013, vector1014, vector1015 -#endif -#if PPC_NUM_VECTORS > 1016 - .long vector1016, vector1017, vector1018, vector1019 -#endif -#if PPC_NUM_VECTORS > 1020 - .long vector1020, vector1021, vector1022, vector1023 -#endif - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/crt0.s b/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/crt0.s deleted file mode 100644 index 1201beb20e..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/crt0.s +++ /dev/null @@ -1,242 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file GCC/crt0.s - * @brief Generic PowerPC startup file for GCC. - * - * @addtogroup PPC_GCC_CORE - * @{ - */ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -#if !defined(FALSE) || defined(__DOXYGEN__) -#define FALSE 0 -#endif - -#if !defined(TRUE) || defined(__DOXYGEN__) -#define TRUE 1 -#endif - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Stack segments initialization switch. - */ -#if !defined(CRT0_STACKS_FILL_PATTERN) || defined(__DOXYGEN__) -#define CRT0_STACKS_FILL_PATTERN 0x55555555 -#endif - -/** - * @brief Stack segments initialization switch. - */ -#if !defined(CRT0_INIT_STACKS) || defined(__DOXYGEN__) -#define CRT0_INIT_STACKS TRUE -#endif - -/** - * @brief DATA segment initialization switch. - */ -#if !defined(CRT0_INIT_DATA) || defined(__DOXYGEN__) -#define CRT0_INIT_DATA TRUE -#endif - -/** - * @brief BSS segment initialization switch. - */ -#if !defined(CRT0_INIT_BSS) || defined(__DOXYGEN__) -#define CRT0_INIT_BSS TRUE -#endif - -/** - * @brief Constructors invocation switch. - */ -#if !defined(CRT0_CALL_CONSTRUCTORS) || defined(__DOXYGEN__) -#define CRT0_CALL_CONSTRUCTORS TRUE -#endif - -/** - * @brief Destructors invocation switch. - */ -#if !defined(CRT0_CALL_DESTRUCTORS) || defined(__DOXYGEN__) -#define CRT0_CALL_DESTRUCTORS TRUE -#endif - -/*===========================================================================*/ -/* Code section. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) - - .section .crt0, "ax" - .align 2 - .globl _boot_address - .type _boot_address, @function -_boot_address: - /* Stack setup.*/ - lis %r1, __process_stack_end__@h - ori %r1, %r1, __process_stack_end__@l - li %r0, 0 - stwu %r0, -8(%r1) - - /* Small sections registers initialization.*/ - lis %r2, __sdata2_start__@h - ori %r2, %r2, __sdata2_start__@l - lis %r13, __sdata_start__@h - ori %r13, %r13, __sdata_start__@l - - /* Early initialization.*/ - bl __early_init - -#if CRT0_INIT_STACKS == TRUE - /* Stacks fill pattern.*/ - lis %r7, CRT0_STACKS_FILL_PATTERN@h - ori %r7, %r7, CRT0_STACKS_FILL_PATTERN@l - - /* IRQ Stack initialization. Note, the architecture does not use this - stack, the size is usually zero. An OS can have special SW handling - and require this. A 4 bytes alignment is assmend and required.*/ - lis %r4, __irq_stack_base__@h - ori %r4, %r4, __irq_stack_base__@l - lis %r5, __irq_stack_end__@h - ori %r5, %r5, __irq_stack_end__@l -.irqsloop: - cmpl cr0, %r4, %r5 - bge cr0, .irqsend - stw %r7, 0(%r4) - addi %r4, %r4, 4 - b .irqsloop -.irqsend: - - /* Process Stack initialization. Note, does not overwrite the already - written EABI frame. A 4 bytes alignment is assmend and required.*/ - lis %r4, __process_stack_base__@h - ori %r4, %r4, __process_stack_base__@l - lis %r5, (__process_stack_end__ - 8)@h - ori %r5, %r5, (__process_stack_end__ - 8)@l -.prcsloop: - cmpl cr0, %r4, %r5 - bge cr0, .prcsend - stw %r7, 0(%r4) - addi %r4, %r4, 4 - b .prcsloop -.prcsend: -#endif - -#if CRT0_INIT_BSS == TRUE - /* BSS clearing.*/ - lis %r4, __bss_start__@h - ori %r4, %r4, __bss_start__@l - lis %r5, __bss_end__@h - ori %r5, %r5, __bss_end__@l - li %r7, 0 -.bssloop: - cmpl cr0, %r4, %r5 - bge cr0, .bssend - stw %r7, 0(%r4) - addi %r4, %r4, 4 - b .bssloop -.bssend: -#endif - -#if CRT0_INIT_DATA == TRUE - /* DATA initialization.*/ - lis %r4, __romdata_start__@h - ori %r4, %r4, __romdata_start__@l - lis %r5, __data_start__@h - ori %r5, %r5, __data_start__@l - lis %r6, __data_end__@h - ori %r6, %r6, __data_end__@l -.dataloop: - cmpl cr0, %r5, %r6 - bge cr0, .dataend - lwz %r7, 0(%r4) - addi %r4, %r4, 4 - stw %r7, 0(%r5) - addi %r5, %r5, 4 - b .dataloop -.dataend: -#endif - - /* Late initialization.*/ - bl __late_init - -#if CRT0_CALL_CONSTRUCTORS == TRUE - /* Constructors invocation.*/ - lis %r4, __init_array_start@h - ori %r4, %r4, __init_array_start@l - lis %r5, __init_array_end@h - ori %r5, %r5, __init_array_end@l -.iniloop: - cmplw %cr0, %r4, %r5 - bge %cr0, .iniend - lwz %r6, 0(%r4) - mtctr %r6 - addi %r4, %r4, 4 - bctrl - b .iniloop -.iniend: -#endif - - /* Main program invocation.*/ - bl main - -#if CRT0_CALL_DESTRUCTORS == TRUE - /* Destructors invocation.*/ - lis %r4, __fini_array_start@h - ori %r4, %r4, __fini_array_start@l - lis %r5, __fini_array_end@h - ori %r5, %r5, __fini_array_end@l -.finiloop: - cmplw %cr0, %r4, %r5 - bge %cr0, .finiend - lwz %r6, 0(%r4) - mtctr %r6 - addi %r4, %r4, 4 - bctrl - b .finiloop -.finiend: -#endif - - /* Branching to the defined exit handler.*/ - b __default_exit - - /* Default main exit code, infinite loop.*/ - .weak __default_exit - .type __default_exit, @function -__default_exit: - b __default_exit - - /* Default early initialization code, none.*/ - .weak __early_init - .type __early_init, @function -__early_init: - blr - - /* Default late initialization code, none.*/ - .weak __late_init - .type __late_init, @function -__late_init: - blr - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/ld/SPC560B50.ld b/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/ld/SPC560B50.ld deleted file mode 100644 index 1303cc1530..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/ld/SPC560B50.ld +++ /dev/null @@ -1,27 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * SPC560B50 memory setup. - */ -MEMORY -{ - flash : org = 0x00000000, len = 512k - dataflash : org = 0x00800000, len = 64k - ram : org = 0x40000000, len = 32k -} - -INCLUDE rules_z0.ld diff --git a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/ld/SPC560B60.ld b/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/ld/SPC560B60.ld deleted file mode 100644 index 49b63c243f..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/ld/SPC560B60.ld +++ /dev/null @@ -1,27 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * SPC560B60 memory setup. - */ -MEMORY -{ - flash : org = 0x00000000, len = 1024k - dataflash : org = 0x00800000, len = 64k - ram : org = 0x40000000, len = 80k -} - -INCLUDE rules_z0.ld diff --git a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/ld/SPC560B64.ld b/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/ld/SPC560B64.ld deleted file mode 100644 index d81b122d17..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/ld/SPC560B64.ld +++ /dev/null @@ -1,27 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * SPC560B64 memory setup. - */ -MEMORY -{ - flash : org = 0x00000000, len = 1536k - dataflash : org = 0x00800000, len = 64k - ram : org = 0x40000000, len = 96k -} - -INCLUDE rules_z0.ld diff --git a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/ld/SPC560D40.ld b/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/ld/SPC560D40.ld deleted file mode 100644 index a5972851a6..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/ld/SPC560D40.ld +++ /dev/null @@ -1,27 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * SPC560D40 memory setup. - */ -MEMORY -{ - flash : org = 0x00000000, len = 256k - dataflash : org = 0x00800000, len = 64k - ram : org = 0x40000000, len = 16k -} - -INCLUDE rules_z0.ld diff --git a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/ld/SPC560P50.ld b/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/ld/SPC560P50.ld deleted file mode 100644 index 574580f243..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/ld/SPC560P50.ld +++ /dev/null @@ -1,27 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * SPC560P50 memory setup. - */ -MEMORY -{ - flash : org = 0x00000000, len = 512k - dataflash : org = 0x00800000, len = 64k - ram : org = 0x40000000, len = 40k -} - -INCLUDE rules_z0.ld diff --git a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/ld/SPC563M64.ld b/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/ld/SPC563M64.ld deleted file mode 100644 index c3bcb8a2f4..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/ld/SPC563M64.ld +++ /dev/null @@ -1,26 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * SPC563M64 memory setup. - */ -MEMORY -{ - flash : org = 0x00000000, len = 1536k - ram : org = 0x40000000, len = 94k -} - -INCLUDE rules_z3.ld diff --git a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/ld/SPC564A70.ld b/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/ld/SPC564A70.ld deleted file mode 100644 index cb4c8ebea5..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/ld/SPC564A70.ld +++ /dev/null @@ -1,26 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * SPC563A70 memory setup. - */ -MEMORY -{ - flash : org = 0x00000000, len = 2M - ram : org = 0x40000000, len = 128k -} - -INCLUDE rules_z4.ld diff --git a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/ld/SPC564A80.ld b/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/ld/SPC564A80.ld deleted file mode 100644 index cc4c0ad926..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/ld/SPC564A80.ld +++ /dev/null @@ -1,26 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * SPC563A80 memory setup. - */ -MEMORY -{ - flash : org = 0x00000000, len = 4M - ram : org = 0x40000000, len = 192k -} - -INCLUDE rules_z4.ld diff --git a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/ld/SPC56EC74.ld b/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/ld/SPC56EC74.ld deleted file mode 100644 index 65e4dfae36..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/ld/SPC56EC74.ld +++ /dev/null @@ -1,27 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * SPC56EC74 memory setup. - */ -MEMORY -{ - flash : org = 0x00000000, len = 3M - dataflash : org = 0x00800000, len = 64k - ram : org = 0x40000000, len = 256k -} - -INCLUDE rules_z4.ld diff --git a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/ld/SPC56EL54_LSM.ld b/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/ld/SPC56EL54_LSM.ld deleted file mode 100644 index 58ec992383..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/ld/SPC56EL54_LSM.ld +++ /dev/null @@ -1,26 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * SPC56EL54 memory setup in LSM mode. - */ -MEMORY -{ - flash : org = 0x00000000, len = 768k - ram : org = 0x40000000, len = 128k -} - -INCLUDE rules_z4.ld diff --git a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/ld/SPC56EL60_LSM.ld b/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/ld/SPC56EL60_LSM.ld deleted file mode 100644 index 4d211bcd36..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/ld/SPC56EL60_LSM.ld +++ /dev/null @@ -1,26 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * SPC56EL60 memory setup in LSM mode. - */ -MEMORY -{ - flash : org = 0x00000000, len = 1M - ram : org = 0x40000000, len = 128k -} - -INCLUDE rules_z4.ld diff --git a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/ld/SPC56EL70_LSM.ld b/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/ld/SPC56EL70_LSM.ld deleted file mode 100644 index d299b9cf29..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/ld/SPC56EL70_LSM.ld +++ /dev/null @@ -1,26 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * SPC56EL70 memory setup in LSM mode. - */ -MEMORY -{ - flash : org = 0x00000000, len = 2M - ram : org = 0x40000000, len = 192k -} - -INCLUDE rules_z4.ld diff --git a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/ld/SPC57EM80_HSM.ld b/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/ld/SPC57EM80_HSM.ld deleted file mode 100644 index 52b36f8eb5..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/ld/SPC57EM80_HSM.ld +++ /dev/null @@ -1,28 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * SPC57EM80-HSM memory setup. - */ -MEMORY -{ - flash : org = 0x0060C000, len = 144k - dflash0 : org = 0x00680000, len = 16k - dflash1 : org = 0x00684000, len = 16k - ram : org = 0xA0000000, len = 40k -} - -INCLUDE rules_z0.ld diff --git a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/mk/startup_spc560bcxx.mk b/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/mk/startup_spc560bcxx.mk deleted file mode 100644 index c7e128fccb..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/mk/startup_spc560bcxx.mk +++ /dev/null @@ -1,11 +0,0 @@ -# List of the ChibiOS e200z0 SPC560BCxx startup files. -STARTUPSRC = - -STARTUPASM = $(CHIBIOS)/os/common/ports/e200/devices/SPC560BCxx/boot.s \ - $(CHIBIOS)/os/common/ports/e200/compilers/GCC/vectors.s \ - $(CHIBIOS)/os/common/ports/e200/compilers/GCC/crt0.s - -STARTUPINC = ${CHIBIOS}/os/common/ports/e200/compilers/GCC \ - ${CHIBIOS}/os/common/ports/e200/devices/SPC560BCxx - -STARTUPLD = ${CHIBIOS}/os/common/ports/e200/compilers/GCC/ld diff --git a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/mk/startup_spc560bxx.mk b/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/mk/startup_spc560bxx.mk deleted file mode 100644 index 5718ce6dbc..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/mk/startup_spc560bxx.mk +++ /dev/null @@ -1,11 +0,0 @@ -# List of the ChibiOS e200z0 SPC560Bxx startup files. -STARTUPSRC = - -STARTUPASM = $(CHIBIOS)/os/common/ports/e200/devices/SPC560Bxx/boot.s \ - $(CHIBIOS)/os/common/ports/e200/compilers/GCC/vectors.s \ - $(CHIBIOS)/os/common/ports/e200/compilers/GCC/crt0.s - -STARTUPINC = ${CHIBIOS}/os/common/ports/e200/compilers/GCC \ - ${CHIBIOS}/os/common/ports/e200/devices/SPC560Bxx - -STARTUPLD = ${CHIBIOS}/os/common/ports/e200/compilers/GCC/ld diff --git a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/mk/startup_spc560dxx.mk b/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/mk/startup_spc560dxx.mk deleted file mode 100644 index 18f487cb05..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/mk/startup_spc560dxx.mk +++ /dev/null @@ -1,11 +0,0 @@ -# List of the ChibiOS e200z0 SPC560Dxx startup files. -STARTUPSRC = - -STARTUPASM = $(CHIBIOS)/os/common/ports/e200/devices/SPC560Dxx/boot.s \ - $(CHIBIOS)/os/common/ports/e200/compilers/GCC/vectors.s \ - $(CHIBIOS)/os/common/ports/e200/compilers/GCC/crt0.s - -STARTUPINC = ${CHIBIOS}/os/common/ports/e200/compilers/GCC \ - ${CHIBIOS}/os/common/ports/e200/devices/SPC560Dxx - -STARTUPLD = ${CHIBIOS}/os/common/ports/e200/compilers/GCC/ld diff --git a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/mk/startup_spc560pxx.mk b/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/mk/startup_spc560pxx.mk deleted file mode 100644 index ac182fa27f..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/mk/startup_spc560pxx.mk +++ /dev/null @@ -1,11 +0,0 @@ -# List of the ChibiOS e200z0 SPC560Pxx startup files. -STARTUPSRC = - -STARTUPASM = $(CHIBIOS)/os/common/ports/e200/devices/SPC560Pxx/boot.s \ - $(CHIBIOS)/os/common/ports/e200/compilers/GCC/vectors.s \ - $(CHIBIOS)/os/common/ports/e200/compilers/GCC/crt0.s - -STARTUPINC = ${CHIBIOS}/os/common/ports/e200/compilers/GCC \ - ${CHIBIOS}/os/common/ports/e200/devices/SPC560Pxx - -STARTUPLD = ${CHIBIOS}/os/common/ports/e200/compilers/GCC/ld diff --git a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/mk/startup_spc563mxx.mk b/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/mk/startup_spc563mxx.mk deleted file mode 100644 index 56a6bb7d43..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/mk/startup_spc563mxx.mk +++ /dev/null @@ -1,11 +0,0 @@ -# List of the ChibiOS e200z3 SPC563Mxx startup files. -STARTUPSRC = - -STARTUPASM = $(CHIBIOS)/os/common/ports/e200/devices/SPC563Mxx/boot.s \ - $(CHIBIOS)/os/common/ports/e200/compilers/GCC/vectors.s \ - $(CHIBIOS)/os/common/ports/e200/compilers/GCC/crt0.s - -STARTUPINC = ${CHIBIOS}/os/common/ports/e200/compilers/GCC \ - ${CHIBIOS}/os/common/ports/e200/devices/SPC563Mxx - -STARTUPLD = ${CHIBIOS}/os/common/ports/e200/compilers/GCC/ld diff --git a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/mk/startup_spc564axx.mk b/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/mk/startup_spc564axx.mk deleted file mode 100644 index d21c1204ec..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/mk/startup_spc564axx.mk +++ /dev/null @@ -1,11 +0,0 @@ -# List of the ChibiOS e200z4 SPC564Axx startup files. -STARTUPSRC = - -STARTUPASM = $(CHIBIOS)/os/common/ports/e200/devices/SPC564Axx/boot.s \ - $(CHIBIOS)/os/common/ports/e200/compilers/GCC/vectors.s \ - $(CHIBIOS)/os/common/ports/e200/compilers/GCC/crt0.s - -STARTUPINC = ${CHIBIOS}/os/common/ports/e200/compilers/GCC \ - ${CHIBIOS}/os/common/ports/e200/devices/SPC564Axx - -STARTUPLD = ${CHIBIOS}/os/common/ports/e200/compilers/GCC/ld diff --git a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/mk/startup_spc56ecxx.mk b/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/mk/startup_spc56ecxx.mk deleted file mode 100644 index ff295cca5e..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/mk/startup_spc56ecxx.mk +++ /dev/null @@ -1,11 +0,0 @@ -# List of the ChibiOS e200z4 SPC56ECxx startup files. -STARTUPSRC = - -STARTUPASM = $(CHIBIOS)/os/common/ports/e200/devices/SPC56ECxx/boot.s \ - $(CHIBIOS)/os/common/ports/e200/compilers/GCC/vectors.s \ - $(CHIBIOS)/os/common/ports/e200/compilers/GCC/crt0.s - -STARTUPINC = ${CHIBIOS}/os/common/ports/e200/compilers/GCC \ - ${CHIBIOS}/os/common/ports/e200/devices/SPC56ECxx - -STARTUPLD = ${CHIBIOS}/os/common/ports/e200/compilers/GCC/ld diff --git a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/mk/startup_spc56elxx.mk b/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/mk/startup_spc56elxx.mk deleted file mode 100644 index 13cf8c509a..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/mk/startup_spc56elxx.mk +++ /dev/null @@ -1,11 +0,0 @@ -# List of the ChibiOS e200z4 SPC56ELxx startup files. -STARTUPSRC = - -STARTUPASM = $(CHIBIOS)/os/common/ports/e200/devices/SPC56ELxx/boot.s \ - $(CHIBIOS)/os/common/ports/e200/compilers/GCC/vectors.s \ - $(CHIBIOS)/os/common/ports/e200/compilers/GCC/crt0.s - -STARTUPINC = ${CHIBIOS}/os/common/ports/e200/compilers/GCC \ - ${CHIBIOS}/os/common/ports/e200/devices/SPC56ELxx - -STARTUPLD = ${CHIBIOS}/os/common/ports/e200/compilers/GCC/ld diff --git a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/rules.mk b/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/rules.mk deleted file mode 100644 index cee4eeddc0..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/rules.mk +++ /dev/null @@ -1,243 +0,0 @@ -# e200z common makefile scripts and rules. - -############################################################################## -# Processing options coming from the upper Makefile. -# - -# Compiler options -OPT = $(USE_OPT) -COPT = $(USE_COPT) -CPPOPT = $(USE_CPPOPT) - -# Garbage collection -ifeq ($(USE_LINK_GC),yes) - OPT += -ffunction-sections -fdata-sections -fno-common - LDOPT := --gc-sections -else - LDOPT := --no-gc-sections -endif - -# Linker extra options -ifneq ($(USE_LDOPT),) - LDOPT := $(LDOPT),$(USE_LDOPT) -endif - -# Link time optimizations -ifeq ($(USE_LTO),yes) - OPT += -flto -endif - -# VLE option handling. -ifeq ($(USE_VLE),yes) - DDEFS += -DPPC_USE_VLE=1 - DADEFS += -DPPC_USE_VLE=1 - MCU += -mvle -else - DDEFS += -DPPC_USE_VLE=0 - DADEFS += -DPPC_USE_VLE=0 -endif - -# Process stack size -ifeq ($(USE_PROCESS_STACKSIZE),) - LDOPT := $(LDOPT),--defsym=__process_stack_size__=0x400 -else - LDOPT := $(LDOPT),--defsym=__process_stack_size__=$(USE_PROCESS_STACKSIZE) -endif - -# Exceptions stack size -ifeq ($(USE_EXCEPTIONS_STACKSIZE),) - LDOPT := $(LDOPT),--defsym=__irq_stack_size__=0x400 -else - LDOPT := $(LDOPT),--defsym=__irq_stack_size__=$(USE_EXCEPTIONS_STACKSIZE) -endif - -# Output directory and files -ifeq ($(BUILDDIR),) - BUILDDIR = build -endif -ifeq ($(BUILDDIR),.) - BUILDDIR = build -endif -OUTFILES = $(BUILDDIR)/$(PROJECT).elf $(BUILDDIR)/$(PROJECT).hex \ - $(BUILDDIR)/$(PROJECT).mot $(BUILDDIR)/$(PROJECT).bin \ - $(BUILDDIR)/$(PROJECT).dmp $(BUILDDIR)/$(PROJECT).list - - -# Source files groups and paths -SRC = $(CSRC)$(CPPSRC) -SRCPATHS = $(sort $(dir $(ASMXSRC)) $(dir $(ASMSRC)) $(dir $(SRC))) - -# Various directories -OBJDIR = $(BUILDDIR)/obj -LSTDIR = $(BUILDDIR)/lst - -# Object files groups -COBJS = $(addprefix $(OBJDIR)/, $(notdir $(CSRC:.c=.o))) -CPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(CPPSRC:.cpp=.o))) -ASMOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMSRC:.s=.o))) -ASMXOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMXSRC:.S=.o))) -OBJS = $(ASMXOBJS) $(ASMOBJS) $(COBJS) $(CPPOBJS) - -# Paths -IINCDIR = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR)) -LLIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) - -# Macros -DEFS = $(DDEFS) $(UDEFS) -ADEFS = $(DADEFS) $(UADEFS) - -# Libs -LIBS = $(DLIBS) $(ULIBS) - -# Various settings -MCFLAGS = -mcpu=$(MCU) -ODFLAGS = -x --syms -ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS) -ASXFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS) -CFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS) -CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS) -LDFLAGS = $(MCFLAGS) $(OPT) -nostartfiles $(LLIBDIR) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--library-path=$(RULESPATH),$(LDOPT),--script=$(LDSCRIPT) - -# Generate dependency information -ASFLAGS += -MD -MP -MF .dep/$(@F).d -ASXFLAGS += -MD -MP -MF .dep/$(@F).d -CFLAGS += -MD -MP -MF .dep/$(@F).d -CPPFLAGS += -MD -MP -MF .dep/$(@F).d - -# Paths where to search for sources -VPATH = $(SRCPATHS) - -# -# Makefile rules -# - -all: PRE_MAKE_ALL_RULE_HOOK $(OBJS) $(OUTFILES) POST_MAKE_ALL_RULE_HOOK - -PRE_MAKE_ALL_RULE_HOOK: - -POST_MAKE_ALL_RULE_HOOK: - -$(OBJS): | $(BUILDDIR) $(OBJDIR) $(LSTDIR) - -$(BUILDDIR): -ifneq ($(USE_VERBOSE_COMPILE),yes) - @echo Compiler Options - @echo $(CC) -c $(CFLAGS) -I. $(IINCDIR) main.c -o main.o - @echo -endif - @mkdir -p $(BUILDDIR) - -$(OBJDIR): - @mkdir -p $(OBJDIR) - -$(LSTDIR): - @mkdir -p $(LSTDIR) - -$(CPPOBJS) : $(OBJDIR)/%.o : %.cpp Makefile -ifeq ($(USE_VERBOSE_COMPILE),yes) - @echo - $(CPPC) -c $(CPPFLAGS) -I. $(IINCDIR) $< -o $@ -else - @echo Compiling $( $@ - $(SZ) $< -else - @echo Creating $@ - @$(OD) $(ODFLAGS) $< > $@ - @echo - @$(SZ) $< -endif - -%.list: %.elf $(LDSCRIPT) -ifeq ($(USE_VERBOSE_COMPILE),yes) - $(OD) -S $< > $@ -else - @echo Creating $@ - @$(OD) -S $< > $@ - @echo Done -endif - -lib: $(OBJS) $(BUILDDIR)/lib$(PROJECT).a - -$(BUILDDIR)/lib$(PROJECT).a: $(OBJS) - @$(AR) -r $@ $^ - @echo - @echo Done - -clean: - @echo Cleaning - -rm -fR .dep $(BUILDDIR) - @echo - @echo Done - -# -# Include the dependency files, should be the last of the makefile -# --include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) - -# *** EOF *** diff --git a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/rules_z0.ld b/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/rules_z0.ld deleted file mode 100644 index c31de7e7f1..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/rules_z0.ld +++ /dev/null @@ -1,159 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -__ram_size__ = LENGTH(ram); -__ram_start__ = ORIGIN(ram); -__ram_end__ = ORIGIN(ram) + LENGTH(ram); - -ENTRY(_reset_address) - -SECTIONS -{ - . = ORIGIN(flash); - .boot0 : ALIGN(16) SUBALIGN(16) - { - KEEP(*(.boot)) - } > flash - - .boot1 : ALIGN(16) SUBALIGN(16) - { - KEEP(*(.handlers)) - KEEP(*(.crt0)) - /* The vectors table requires a 2kB alignment.*/ - . = ALIGN(0x800); - KEEP(*(.vectors)) - /* The IVPR register requires a 4kB alignment.*/ - . = ALIGN(0x1000); - __ivpr_base__ = .; - KEEP(*(.ivors)) - } > flash - - constructors : ALIGN(4) SUBALIGN(4) - { - PROVIDE(__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - } > flash - - destructors : ALIGN(4) SUBALIGN(4) - { - PROVIDE(__fini_array_start = .); - KEEP(*(.fini_array)) - KEEP(*(SORT(.fini_array.*))) - PROVIDE(__fini_array_end = .); - } > flash - - .text_vle : ALIGN(16) SUBALIGN(16) - { - *(.text_vle) - *(.text_vle.*) - *(.gnu.linkonce.t_vle.*) - } > flash - - .text : ALIGN(16) SUBALIGN(16) - { - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - } > flash - - .rodata : ALIGN(16) SUBALIGN(16) - { - *(.glue_7t) - *(.glue_7) - *(.gcc*) - *(.rodata) - *(.rodata.*) - *(.rodata1) - } > flash - - .sdata2 : ALIGN(16) SUBALIGN(16) - { - __sdata2_start__ = . + 0x8000; - *(.sdata2) - *(.sdata2.*) - *(.gnu.linkonce.s2.*) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - } > flash - - .eh_frame_hdr : - { - *(.eh_frame_hdr) - } > flash - - .eh_frame : ONLY_IF_RO - { - *(.eh_frame) - } > flash - - .romdata : ALIGN(16) SUBALIGN(16) - { - __romdata_start__ = .; - } > flash - - .stacks : ALIGN(16) SUBALIGN(16) - { - . = ALIGN(8); - __irq_stack_base__ = .; - . += __irq_stack_size__; - . = ALIGN(8); - __irq_stack_end__ = .; - __process_stack_base__ = .; - __main_thread_stack_base__ = .; - . += __process_stack_size__; - . = ALIGN(8); - __process_stack_end__ = .; - __main_thread_stack_end__ = .; - } > ram - - .data : AT(__romdata_start__) - { - . = ALIGN(4); - __data_start__ = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - __sdata_start__ = . + 0x8000; - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - __data_end__ = .; - } > ram - - .sbss : - { - __bss_start__ = .; - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - } > ram - - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - __bss_end__ = .; - } > ram - - __heap_base__ = __bss_end__; - __heap_end__ = __ram_end__; -} diff --git a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/rules_z3.ld b/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/rules_z3.ld deleted file mode 100644 index 499516bf0d..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/rules_z3.ld +++ /dev/null @@ -1,156 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -__ram_size__ = LENGTH(ram); -__ram_start__ = ORIGIN(ram); -__ram_end__ = ORIGIN(ram) + LENGTH(ram); - -ENTRY(_reset_address) - -SECTIONS -{ - . = ORIGIN(flash); - .boot0 : ALIGN(16) SUBALIGN(16) - { - __ivpr_base__ = .; - KEEP(*(.boot)) - } > flash - - .boot1 : ALIGN(16) SUBALIGN(16) - { - KEEP(*(.handlers)) - KEEP(*(.crt0)) - /* The vectors table requires a 2kB alignment.*/ - . = ALIGN(0x800); - KEEP(*(.vectors)) - } > flash - - constructors : ALIGN(4) SUBALIGN(4) - { - PROVIDE(__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - } > flash - - destructors : ALIGN(4) SUBALIGN(4) - { - PROVIDE(__fini_array_start = .); - KEEP(*(.fini_array)) - KEEP(*(SORT(.fini_array.*))) - PROVIDE(__fini_array_end = .); - } > flash - - .text_vle : ALIGN(16) SUBALIGN(16) - { - *(.text_vle) - *(.text_vle.*) - *(.gnu.linkonce.t_vle.*) - } > flash - - .text : ALIGN(16) SUBALIGN(16) - { - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - } > flash - - .rodata : ALIGN(16) SUBALIGN(16) - { - *(.glue_7t) - *(.glue_7) - *(.gcc*) - *(.rodata) - *(.rodata.*) - *(.rodata1) - } > flash - - .sdata2 : ALIGN(16) SUBALIGN(16) - { - __sdata2_start__ = . + 0x8000; - *(.sdata2) - *(.sdata2.*) - *(.gnu.linkonce.s2.*) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - } > flash - - .eh_frame_hdr : - { - *(.eh_frame_hdr) - } > flash - - .eh_frame : ONLY_IF_RO - { - *(.eh_frame) - } > flash - - .romdata : ALIGN(16) SUBALIGN(16) - { - __romdata_start__ = .; - } > flash - - .stacks : ALIGN(16) SUBALIGN(16) - { - . = ALIGN(8); - __irq_stack_base__ = .; - . += __irq_stack_size__; - . = ALIGN(8); - __irq_stack_end__ = .; - __process_stack_base__ = .; - __main_thread_stack_base__ = .; - . += __process_stack_size__; - . = ALIGN(8); - __process_stack_end__ = .; - __main_thread_stack_end__ = .; - } > ram - - .data : AT(__romdata_start__) - { - . = ALIGN(4); - __data_start__ = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - __sdata_start__ = . + 0x8000; - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - __data_end__ = .; - } > ram - - .sbss : - { - __bss_start__ = .; - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - } > ram - - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - __bss_end__ = .; - } > ram - - __heap_base__ = __bss_end__; - __heap_end__ = __ram_end__; -} diff --git a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/rules_z4.ld b/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/rules_z4.ld deleted file mode 100644 index 499516bf0d..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/rules_z4.ld +++ /dev/null @@ -1,156 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -__ram_size__ = LENGTH(ram); -__ram_start__ = ORIGIN(ram); -__ram_end__ = ORIGIN(ram) + LENGTH(ram); - -ENTRY(_reset_address) - -SECTIONS -{ - . = ORIGIN(flash); - .boot0 : ALIGN(16) SUBALIGN(16) - { - __ivpr_base__ = .; - KEEP(*(.boot)) - } > flash - - .boot1 : ALIGN(16) SUBALIGN(16) - { - KEEP(*(.handlers)) - KEEP(*(.crt0)) - /* The vectors table requires a 2kB alignment.*/ - . = ALIGN(0x800); - KEEP(*(.vectors)) - } > flash - - constructors : ALIGN(4) SUBALIGN(4) - { - PROVIDE(__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - } > flash - - destructors : ALIGN(4) SUBALIGN(4) - { - PROVIDE(__fini_array_start = .); - KEEP(*(.fini_array)) - KEEP(*(SORT(.fini_array.*))) - PROVIDE(__fini_array_end = .); - } > flash - - .text_vle : ALIGN(16) SUBALIGN(16) - { - *(.text_vle) - *(.text_vle.*) - *(.gnu.linkonce.t_vle.*) - } > flash - - .text : ALIGN(16) SUBALIGN(16) - { - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - } > flash - - .rodata : ALIGN(16) SUBALIGN(16) - { - *(.glue_7t) - *(.glue_7) - *(.gcc*) - *(.rodata) - *(.rodata.*) - *(.rodata1) - } > flash - - .sdata2 : ALIGN(16) SUBALIGN(16) - { - __sdata2_start__ = . + 0x8000; - *(.sdata2) - *(.sdata2.*) - *(.gnu.linkonce.s2.*) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - } > flash - - .eh_frame_hdr : - { - *(.eh_frame_hdr) - } > flash - - .eh_frame : ONLY_IF_RO - { - *(.eh_frame) - } > flash - - .romdata : ALIGN(16) SUBALIGN(16) - { - __romdata_start__ = .; - } > flash - - .stacks : ALIGN(16) SUBALIGN(16) - { - . = ALIGN(8); - __irq_stack_base__ = .; - . += __irq_stack_size__; - . = ALIGN(8); - __irq_stack_end__ = .; - __process_stack_base__ = .; - __main_thread_stack_base__ = .; - . += __process_stack_size__; - . = ALIGN(8); - __process_stack_end__ = .; - __main_thread_stack_end__ = .; - } > ram - - .data : AT(__romdata_start__) - { - . = ALIGN(4); - __data_start__ = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - __sdata_start__ = . + 0x8000; - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - __data_end__ = .; - } > ram - - .sbss : - { - __bss_start__ = .; - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - } > ram - - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - __bss_end__ = .; - } > ram - - __heap_base__ = __bss_end__; - __heap_end__ = __ram_end__; -} diff --git a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/vectors.h b/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/vectors.h deleted file mode 100644 index 367a257116..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/vectors.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file vectors.h - * @brief ISR vector module header. - * - * @addtogroup PPC_GCC_CORE - * @{ - */ - -#ifndef _VECTORS_H_ -#define _VECTORS_H_ - -#include "ppcparams.h" - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/* The following code is not processed when the file is included from an - asm module.*/ -#if !defined(_FROM_ASM_) - -#if !defined(__DOXYGEN__) -extern uint32_t _vectors[PPC_NUM_VECTORS]; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void _unhandled_irq(void); -#ifdef __cplusplus -} -#endif - -#endif /* !defined(_FROM_ASM_) */ - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -#endif /* _VECTORS_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/vectors.s b/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/vectors.s deleted file mode 100644 index 22ca19df74..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/compilers/GCC/vectors.s +++ /dev/null @@ -1,2612 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file vectors.s - * @brief SPC56x vectors table. - * - * @addtogroup PPC_GCC_CORE - * @{ - */ - -#define _FROM_ASM_ -#include "ppcparams.h" - -#if defined(VECTORS_RENAMING) -#include "isrs.h" -#endif - -#if !defined(__DOXYGEN__) - - /* Software vectors table. The vectors are accessed from the IVOR4 - handler only. In order to declare an interrupt handler just create - a function withe the same name of a vector, the symbol will - override the weak symbol declared here.*/ - .section .vectors, "ax" - .align 4 - .globl _vectors -_vectors: - .long vector0, vector1, vector2, vector3 -#if PPC_NUM_VECTORS > 4 - .long vector4, vector5, vector6, vector7 -#endif -#if PPC_NUM_VECTORS > 8 - .long vector8, vector9, vector10, vector11 -#endif -#if PPC_NUM_VECTORS > 12 - .long vector12, vector13, vector14, vector15 -#endif -#if PPC_NUM_VECTORS > 16 - .long vector16, vector17, vector18, vector19 -#endif -#if PPC_NUM_VECTORS > 20 - .long vector20, vector21, vector22, vector23 -#endif -#if PPC_NUM_VECTORS > 24 - .long vector24, vector25, vector26, vector27 -#endif -#if PPC_NUM_VECTORS > 28 - .long vector28, vector29, vector30, vector31 -#endif -#if PPC_NUM_VECTORS > 32 - .long vector32, vector33, vector34, vector35 -#endif -#if PPC_NUM_VECTORS > 36 - .long vector36, vector37, vector38, vector39 -#endif -#if PPC_NUM_VECTORS > 40 - .long vector40, vector41, vector42, vector43 -#endif -#if PPC_NUM_VECTORS > 44 - .long vector44, vector45, vector46, vector47 -#endif -#if PPC_NUM_VECTORS > 48 - .long vector48, vector49, vector50, vector51 -#endif -#if PPC_NUM_VECTORS > 52 - .long vector52, vector53, vector54, vector55 -#endif -#if PPC_NUM_VECTORS > 56 - .long vector56, vector57, vector58, vector59 -#endif -#if PPC_NUM_VECTORS > 60 - .long vector60, vector61, vector62, vector63 -#endif -#if PPC_NUM_VECTORS > 64 - .long vector64, vector65, vector66, vector67 -#endif -#if PPC_NUM_VECTORS > 68 - .long vector68, vector69, vector70, vector71 -#endif -#if PPC_NUM_VECTORS > 72 - .long vector72, vector73, vector74, vector75 -#endif -#if PPC_NUM_VECTORS > 76 - .long vector76, vector77, vector78, vector79 -#endif -#if PPC_NUM_VECTORS > 80 - .long vector80, vector81, vector82, vector83 -#endif -#if PPC_NUM_VECTORS > 84 - .long vector84, vector85, vector86, vector87 -#endif -#if PPC_NUM_VECTORS > 88 - .long vector88, vector89, vector90, vector91 -#endif -#if PPC_NUM_VECTORS > 92 - .long vector92, vector93, vector94, vector95 -#endif -#if PPC_NUM_VECTORS > 96 - .long vector96, vector97, vector98, vector99 -#endif -#if PPC_NUM_VECTORS > 100 - .long vector100, vector101, vector102, vector103 -#endif -#if PPC_NUM_VECTORS > 104 - .long vector104, vector105, vector106, vector107 -#endif -#if PPC_NUM_VECTORS > 108 - .long vector108, vector109, vector110, vector111 -#endif -#if PPC_NUM_VECTORS > 112 - .long vector112, vector113, vector114, vector115 -#endif -#if PPC_NUM_VECTORS > 116 - .long vector116, vector117, vector118, vector119 -#endif -#if PPC_NUM_VECTORS > 120 - .long vector120, vector121, vector122, vector123 -#endif -#if PPC_NUM_VECTORS > 124 - .long vector124, vector125, vector126, vector127 -#endif -#if PPC_NUM_VECTORS > 128 - .long vector128, vector129, vector130, vector131 -#endif -#if PPC_NUM_VECTORS > 132 - .long vector132, vector133, vector134, vector135 -#endif -#if PPC_NUM_VECTORS > 136 - .long vector136, vector137, vector138, vector139 -#endif -#if PPC_NUM_VECTORS > 140 - .long vector140, vector141, vector142, vector143 -#endif -#if PPC_NUM_VECTORS > 144 - .long vector144, vector145, vector146, vector147 -#endif -#if PPC_NUM_VECTORS > 148 - .long vector148, vector149, vector150, vector151 -#endif -#if PPC_NUM_VECTORS > 152 - .long vector152, vector153, vector154, vector155 -#endif -#if PPC_NUM_VECTORS > 156 - .long vector156, vector157, vector158, vector159 -#endif -#if PPC_NUM_VECTORS > 160 - .long vector160, vector161, vector162, vector163 -#endif -#if PPC_NUM_VECTORS > 164 - .long vector164, vector165, vector166, vector167 -#endif -#if PPC_NUM_VECTORS > 168 - .long vector168, vector169, vector170, vector171 -#endif -#if PPC_NUM_VECTORS > 172 - .long vector172, vector173, vector174, vector175 -#endif -#if PPC_NUM_VECTORS > 176 - .long vector176, vector177, vector178, vector179 -#endif -#if PPC_NUM_VECTORS > 180 - .long vector180, vector181, vector182, vector183 -#endif -#if PPC_NUM_VECTORS > 184 - .long vector184, vector185, vector186, vector187 -#endif -#if PPC_NUM_VECTORS > 188 - .long vector188, vector189, vector190, vector191 -#endif -#if PPC_NUM_VECTORS > 192 - .long vector192, vector193, vector194, vector195 -#endif -#if PPC_NUM_VECTORS > 196 - .long vector196, vector197, vector198, vector199 -#endif -#if PPC_NUM_VECTORS > 200 - .long vector200, vector201, vector202, vector203 -#endif -#if PPC_NUM_VECTORS > 204 - .long vector204, vector205, vector206, vector207 -#endif -#if PPC_NUM_VECTORS > 208 - .long vector208, vector209, vector210, vector211 -#endif -#if PPC_NUM_VECTORS > 212 - .long vector212, vector213, vector214, vector215 -#endif -#if PPC_NUM_VECTORS > 216 - .long vector216, vector217, vector218, vector219 -#endif -#if PPC_NUM_VECTORS > 220 - .long vector220, vector221, vector222, vector223 -#endif -#if PPC_NUM_VECTORS > 224 - .long vector224, vector225, vector226, vector227 -#endif -#if PPC_NUM_VECTORS > 228 - .long vector228, vector229, vector230, vector231 -#endif -#if PPC_NUM_VECTORS > 232 - .long vector232, vector233, vector234, vector235 -#endif -#if PPC_NUM_VECTORS > 236 - .long vector236, vector237, vector238, vector239 -#endif -#if PPC_NUM_VECTORS > 240 - .long vector240, vector241, vector242, vector243 -#endif -#if PPC_NUM_VECTORS > 244 - .long vector244, vector245, vector246, vector247 -#endif -#if PPC_NUM_VECTORS > 248 - .long vector248, vector249, vector250, vector251 -#endif -#if PPC_NUM_VECTORS > 252 - .long vector252, vector253, vector254, vector255 -#endif -#if PPC_NUM_VECTORS > 256 - .long vector256, vector257, vector258, vector259 -#endif -#if PPC_NUM_VECTORS > 260 - .long vector260, vector261, vector262, vector263 -#endif -#if PPC_NUM_VECTORS > 264 - .long vector264, vector265, vector266, vector267 -#endif -#if PPC_NUM_VECTORS > 268 - .long vector268, vector269, vector270, vector271 -#endif -#if PPC_NUM_VECTORS > 272 - .long vector272, vector273, vector274, vector275 -#endif -#if PPC_NUM_VECTORS > 276 - .long vector276, vector277, vector278, vector279 -#endif -#if PPC_NUM_VECTORS > 280 - .long vector280, vector281, vector282, vector283 -#endif -#if PPC_NUM_VECTORS > 284 - .long vector284, vector285, vector286, vector287 -#endif -#if PPC_NUM_VECTORS > 288 - .long vector288, vector289, vector290, vector291 -#endif -#if PPC_NUM_VECTORS > 292 - .long vector292, vector293, vector294, vector295 -#endif -#if PPC_NUM_VECTORS > 296 - .long vector296, vector297, vector298, vector299 -#endif -#if PPC_NUM_VECTORS > 300 - .long vector300, vector301, vector302, vector303 -#endif -#if PPC_NUM_VECTORS > 304 - .long vector304, vector305, vector306, vector307 -#endif -#if PPC_NUM_VECTORS > 308 - .long vector308, vector309, vector310, vector311 -#endif -#if PPC_NUM_VECTORS > 312 - .long vector312, vector313, vector314, vector315 -#endif -#if PPC_NUM_VECTORS > 316 - .long vector316, vector317, vector318, vector319 -#endif -#if PPC_NUM_VECTORS > 320 - .long vector320, vector321, vector322, vector323 -#endif -#if PPC_NUM_VECTORS > 324 - .long vector324, vector325, vector326, vector327 -#endif -#if PPC_NUM_VECTORS > 328 - .long vector328, vector329, vector330, vector331 -#endif -#if PPC_NUM_VECTORS > 332 - .long vector332, vector333, vector334, vector335 -#endif -#if PPC_NUM_VECTORS > 336 - .long vector336, vector337, vector338, vector339 -#endif -#if PPC_NUM_VECTORS > 340 - .long vector340, vector341, vector342, vector343 -#endif -#if PPC_NUM_VECTORS > 344 - .long vector344, vector345, vector346, vector347 -#endif -#if PPC_NUM_VECTORS > 348 - .long vector348, vector349, vector350, vector351 -#endif -#if PPC_NUM_VECTORS > 352 - .long vector352, vector353, vector354, vector355 -#endif -#if PPC_NUM_VECTORS > 356 - .long vector356, vector357, vector358, vector359 -#endif -#if PPC_NUM_VECTORS > 360 - .long vector360, vector361, vector362, vector363 -#endif -#if PPC_NUM_VECTORS > 364 - .long vector364, vector365, vector366, vector367 -#endif -#if PPC_NUM_VECTORS > 368 - .long vector368, vector369, vector370, vector371 -#endif -#if PPC_NUM_VECTORS > 372 - .long vector372, vector373, vector374, vector375 -#endif -#if PPC_NUM_VECTORS > 376 - .long vector376, vector377, vector378, vector379 -#endif -#if PPC_NUM_VECTORS > 380 - .long vector380, vector381, vector382, vector383 -#endif -#if PPC_NUM_VECTORS > 384 - .long vector384, vector385, vector386, vector387 -#endif -#if PPC_NUM_VECTORS > 388 - .long vector388, vector389, vector390, vector391 -#endif -#if PPC_NUM_VECTORS > 392 - .long vector392, vector393, vector394, vector395 -#endif -#if PPC_NUM_VECTORS > 396 - .long vector396, vector397, vector398, vector399 -#endif -#if PPC_NUM_VECTORS > 400 - .long vector400, vector401, vector402, vector403 -#endif -#if PPC_NUM_VECTORS > 404 - .long vector404, vector405, vector406, vector407 -#endif -#if PPC_NUM_VECTORS > 408 - .long vector408, vector409, vector410, vector411 -#endif -#if PPC_NUM_VECTORS > 412 - .long vector412, vector413, vector414, vector415 -#endif -#if PPC_NUM_VECTORS > 416 - .long vector416, vector417, vector418, vector419 -#endif -#if PPC_NUM_VECTORS > 420 - .long vector420, vector421, vector422, vector423 -#endif -#if PPC_NUM_VECTORS > 424 - .long vector424, vector425, vector426, vector427 -#endif -#if PPC_NUM_VECTORS > 428 - .long vector428, vector429, vector430, vector431 -#endif -#if PPC_NUM_VECTORS > 432 - .long vector432, vector433, vector434, vector435 -#endif -#if PPC_NUM_VECTORS > 436 - .long vector436, vector437, vector438, vector439 -#endif -#if PPC_NUM_VECTORS > 440 - .long vector440, vector441, vector442, vector443 -#endif -#if PPC_NUM_VECTORS > 444 - .long vector444, vector445, vector446, vector447 -#endif -#if PPC_NUM_VECTORS > 448 - .long vector448, vector449, vector450, vector451 -#endif -#if PPC_NUM_VECTORS > 452 - .long vector452, vector453, vector454, vector455 -#endif -#if PPC_NUM_VECTORS > 456 - .long vector456, vector457, vector458, vector459 -#endif -#if PPC_NUM_VECTORS > 460 - .long vector460, vector461, vector462, vector463 -#endif -#if PPC_NUM_VECTORS > 464 - .long vector464, vector465, vector466, vector467 -#endif -#if PPC_NUM_VECTORS > 468 - .long vector468, vector469, vector470, vector471 -#endif -#if PPC_NUM_VECTORS > 472 - .long vector472, vector473, vector474, vector475 -#endif -#if PPC_NUM_VECTORS > 476 - .long vector476, vector477, vector478, vector479 -#endif -#if PPC_NUM_VECTORS > 480 - .long vector480, vector481, vector482, vector483 -#endif -#if PPC_NUM_VECTORS > 484 - .long vector484, vector485, vector486, vector487 -#endif -#if PPC_NUM_VECTORS > 488 - .long vector488, vector489, vector490, vector491 -#endif -#if PPC_NUM_VECTORS > 492 - .long vector492, vector493, vector494, vector495 -#endif -#if PPC_NUM_VECTORS > 496 - .long vector496, vector497, vector498, vector499 -#endif -#if PPC_NUM_VECTORS > 500 - .long vector500, vector501, vector502, vector503 -#endif -#if PPC_NUM_VECTORS > 504 - .long vector504, vector505, vector506, vector507 -#endif -#if PPC_NUM_VECTORS > 508 - .long vector508, vector509, vector510, vector511 -#endif -#if PPC_NUM_VECTORS > 512 - .long vector512, vector513, vector514, vector515 -#endif -#if PPC_NUM_VECTORS > 516 - .long vector516, vector517, vector518, vector519 -#endif -#if PPC_NUM_VECTORS > 520 - .long vector520, vector521, vector522, vector523 -#endif -#if PPC_NUM_VECTORS > 524 - .long vector524, vector525, vector526, vector527 -#endif -#if PPC_NUM_VECTORS > 528 - .long vector528, vector529, vector530, vector531 -#endif -#if PPC_NUM_VECTORS > 532 - .long vector532, vector533, vector534, vector535 -#endif -#if PPC_NUM_VECTORS > 536 - .long vector536, vector537, vector538, vector539 -#endif -#if PPC_NUM_VECTORS > 540 - .long vector540, vector541, vector542, vector543 -#endif -#if PPC_NUM_VECTORS > 544 - .long vector544, vector545, vector546, vector547 -#endif -#if PPC_NUM_VECTORS > 548 - .long vector548, vector549, vector550, vector551 -#endif -#if PPC_NUM_VECTORS > 552 - .long vector552, vector553, vector554, vector555 -#endif -#if PPC_NUM_VECTORS > 556 - .long vector556, vector557, vector558, vector559 -#endif -#if PPC_NUM_VECTORS > 560 - .long vector560, vector561, vector562, vector563 -#endif -#if PPC_NUM_VECTORS > 564 - .long vector564, vector565, vector566, vector567 -#endif -#if PPC_NUM_VECTORS > 568 - .long vector568, vector569, vector570, vector571 -#endif -#if PPC_NUM_VECTORS > 572 - .long vector572, vector573, vector574, vector575 -#endif -#if PPC_NUM_VECTORS > 576 - .long vector576, vector577, vector578, vector579 -#endif -#if PPC_NUM_VECTORS > 580 - .long vector580, vector581, vector582, vector583 -#endif -#if PPC_NUM_VECTORS > 584 - .long vector584, vector585, vector586, vector587 -#endif -#if PPC_NUM_VECTORS > 588 - .long vector588, vector589, vector590, vector591 -#endif -#if PPC_NUM_VECTORS > 592 - .long vector592, vector593, vector594, vector595 -#endif -#if PPC_NUM_VECTORS > 596 - .long vector596, vector597, vector598, vector599 -#endif -#if PPC_NUM_VECTORS > 600 - .long vector600, vector601, vector602, vector603 -#endif -#if PPC_NUM_VECTORS > 604 - .long vector604, vector605, vector606, vector607 -#endif -#if PPC_NUM_VECTORS > 608 - .long vector608, vector609, vector610, vector611 -#endif -#if PPC_NUM_VECTORS > 612 - .long vector612, vector613, vector614, vector615 -#endif -#if PPC_NUM_VECTORS > 616 - .long vector616, vector617, vector618, vector619 -#endif -#if PPC_NUM_VECTORS > 620 - .long vector620, vector621, vector622, vector623 -#endif -#if PPC_NUM_VECTORS > 624 - .long vector624, vector625, vector626, vector627 -#endif -#if PPC_NUM_VECTORS > 628 - .long vector628, vector629, vector630, vector631 -#endif -#if PPC_NUM_VECTORS > 632 - .long vector632, vector633, vector634, vector635 -#endif -#if PPC_NUM_VECTORS > 636 - .long vector636, vector637, vector638, vector639 -#endif -#if PPC_NUM_VECTORS > 640 - .long vector640, vector641, vector642, vector643 -#endif -#if PPC_NUM_VECTORS > 644 - .long vector644, vector645, vector646, vector647 -#endif -#if PPC_NUM_VECTORS > 648 - .long vector648, vector649, vector650, vector651 -#endif -#if PPC_NUM_VECTORS > 652 - .long vector652, vector653, vector654, vector655 -#endif -#if PPC_NUM_VECTORS > 656 - .long vector656, vector657, vector658, vector659 -#endif -#if PPC_NUM_VECTORS > 660 - .long vector660, vector661, vector662, vector663 -#endif -#if PPC_NUM_VECTORS > 664 - .long vector664, vector665, vector666, vector667 -#endif -#if PPC_NUM_VECTORS > 668 - .long vector668, vector669, vector670, vector671 -#endif -#if PPC_NUM_VECTORS > 672 - .long vector672, vector673, vector674, vector675 -#endif -#if PPC_NUM_VECTORS > 676 - .long vector676, vector677, vector678, vector679 -#endif -#if PPC_NUM_VECTORS > 680 - .long vector680, vector681, vector682, vector683 -#endif -#if PPC_NUM_VECTORS > 684 - .long vector684, vector685, vector686, vector687 -#endif -#if PPC_NUM_VECTORS > 688 - .long vector688, vector689, vector690, vector691 -#endif -#if PPC_NUM_VECTORS > 692 - .long vector692, vector693, vector694, vector695 -#endif -#if PPC_NUM_VECTORS > 696 - .long vector696, vector697, vector698, vector699 -#endif -#if PPC_NUM_VECTORS > 700 - .long vector700, vector701, vector702, vector703 -#endif -#if PPC_NUM_VECTORS > 704 - .long vector704, vector705, vector706, vector707 -#endif -#if PPC_NUM_VECTORS > 708 - .long vector708, vector709, vector710, vector711 -#endif -#if PPC_NUM_VECTORS > 712 - .long vector712, vector713, vector714, vector715 -#endif -#if PPC_NUM_VECTORS > 716 - .long vector716, vector717, vector718, vector719 -#endif -#if PPC_NUM_VECTORS > 720 - .long vector720, vector721, vector722, vector723 -#endif -#if PPC_NUM_VECTORS > 724 - .long vector724, vector725, vector726, vector727 -#endif -#if PPC_NUM_VECTORS > 728 - .long vector728, vector729, vector730, vector731 -#endif -#if PPC_NUM_VECTORS > 732 - .long vector732, vector733, vector734, vector735 -#endif -#if PPC_NUM_VECTORS > 736 - .long vector736, vector737, vector738, vector739 -#endif -#if PPC_NUM_VECTORS > 740 - .long vector740, vector741, vector742, vector743 -#endif -#if PPC_NUM_VECTORS > 744 - .long vector744, vector745, vector746, vector747 -#endif -#if PPC_NUM_VECTORS > 748 - .long vector748, vector749, vector750, vector751 -#endif -#if PPC_NUM_VECTORS > 752 - .long vector752, vector753, vector754, vector755 -#endif -#if PPC_NUM_VECTORS > 756 - .long vector756, vector757, vector758, vector759 -#endif -#if PPC_NUM_VECTORS > 760 - .long vector760, vector761, vector762, vector763 -#endif -#if PPC_NUM_VECTORS > 764 - .long vector764, vector765, vector766, vector767 -#endif -#if PPC_NUM_VECTORS > 768 - .long vector768, vector769, vector770, vector771 -#endif -#if PPC_NUM_VECTORS > 772 - .long vector772, vector773, vector774, vector775 -#endif -#if PPC_NUM_VECTORS > 776 - .long vector776, vector777, vector778, vector779 -#endif -#if PPC_NUM_VECTORS > 780 - .long vector780, vector781, vector782, vector783 -#endif -#if PPC_NUM_VECTORS > 784 - .long vector784, vector785, vector786, vector787 -#endif -#if PPC_NUM_VECTORS > 788 - .long vector788, vector789, vector790, vector791 -#endif -#if PPC_NUM_VECTORS > 792 - .long vector792, vector793, vector794, vector795 -#endif -#if PPC_NUM_VECTORS > 796 - .long vector796, vector797, vector798, vector799 -#endif -#if PPC_NUM_VECTORS > 800 - .long vector800, vector801, vector802, vector803 -#endif -#if PPC_NUM_VECTORS > 804 - .long vector804, vector805, vector806, vector807 -#endif -#if PPC_NUM_VECTORS > 808 - .long vector808, vector809, vector810, vector811 -#endif -#if PPC_NUM_VECTORS > 812 - .long vector812, vector813, vector814, vector815 -#endif -#if PPC_NUM_VECTORS > 816 - .long vector816, vector817, vector818, vector819 -#endif -#if PPC_NUM_VECTORS > 820 - .long vector820, vector821, vector822, vector823 -#endif -#if PPC_NUM_VECTORS > 824 - .long vector824, vector825, vector826, vector827 -#endif -#if PPC_NUM_VECTORS > 828 - .long vector828, vector829, vector830, vector831 -#endif -#if PPC_NUM_VECTORS > 832 - .long vector832, vector833, vector834, vector835 -#endif -#if PPC_NUM_VECTORS > 836 - .long vector836, vector837, vector838, vector839 -#endif -#if PPC_NUM_VECTORS > 840 - .long vector840, vector841, vector842, vector843 -#endif -#if PPC_NUM_VECTORS > 844 - .long vector844, vector845, vector846, vector847 -#endif -#if PPC_NUM_VECTORS > 848 - .long vector848, vector849, vector850, vector851 -#endif -#if PPC_NUM_VECTORS > 852 - .long vector852, vector853, vector854, vector855 -#endif -#if PPC_NUM_VECTORS > 856 - .long vector856, vector857, vector858, vector859 -#endif -#if PPC_NUM_VECTORS > 860 - .long vector860, vector861, vector862, vector863 -#endif -#if PPC_NUM_VECTORS > 864 - .long vector864, vector865, vector866, vector867 -#endif -#if PPC_NUM_VECTORS > 868 - .long vector868, vector869, vector870, vector871 -#endif -#if PPC_NUM_VECTORS > 872 - .long vector872, vector873, vector874, vector875 -#endif -#if PPC_NUM_VECTORS > 876 - .long vector876, vector877, vector878, vector879 -#endif -#if PPC_NUM_VECTORS > 880 - .long vector880, vector881, vector882, vector883 -#endif -#if PPC_NUM_VECTORS > 884 - .long vector884, vector885, vector886, vector887 -#endif -#if PPC_NUM_VECTORS > 888 - .long vector888, vector889, vector890, vector891 -#endif -#if PPC_NUM_VECTORS > 892 - .long vector892, vector893, vector894, vector895 -#endif -#if PPC_NUM_VECTORS > 896 - .long vector896, vector897, vector898, vector899 -#endif -#if PPC_NUM_VECTORS > 900 - .long vector900, vector901, vector902, vector903 -#endif -#if PPC_NUM_VECTORS > 904 - .long vector904, vector905, vector906, vector907 -#endif -#if PPC_NUM_VECTORS > 908 - .long vector908, vector909, vector910, vector911 -#endif -#if PPC_NUM_VECTORS > 912 - .long vector912, vector913, vector914, vector915 -#endif -#if PPC_NUM_VECTORS > 916 - .long vector916, vector917, vector918, vector919 -#endif -#if PPC_NUM_VECTORS > 920 - .long vector920, vector921, vector922, vector923 -#endif -#if PPC_NUM_VECTORS > 924 - .long vector924, vector925, vector926, vector927 -#endif -#if PPC_NUM_VECTORS > 928 - .long vector928, vector929, vector930, vector931 -#endif -#if PPC_NUM_VECTORS > 932 - .long vector932, vector933, vector934, vector935 -#endif -#if PPC_NUM_VECTORS > 936 - .long vector936, vector937, vector938, vector939 -#endif -#if PPC_NUM_VECTORS > 940 - .long vector940, vector941, vector942, vector943 -#endif -#if PPC_NUM_VECTORS > 944 - .long vector944, vector945, vector946, vector947 -#endif -#if PPC_NUM_VECTORS > 948 - .long vector948, vector949, vector950, vector951 -#endif -#if PPC_NUM_VECTORS > 952 - .long vector952, vector953, vector954, vector955 -#endif -#if PPC_NUM_VECTORS > 956 - .long vector956, vector957, vector958, vector959 -#endif -#if PPC_NUM_VECTORS > 960 - .long vector960, vector961, vector962, vector963 -#endif -#if PPC_NUM_VECTORS > 964 - .long vector964, vector965, vector966, vector967 -#endif -#if PPC_NUM_VECTORS > 968 - .long vector968, vector969, vector970, vector971 -#endif -#if PPC_NUM_VECTORS > 972 - .long vector972, vector973, vector974, vector975 -#endif -#if PPC_NUM_VECTORS > 976 - .long vector976, vector977, vector978, vector979 -#endif -#if PPC_NUM_VECTORS > 980 - .long vector980, vector981, vector982, vector983 -#endif -#if PPC_NUM_VECTORS > 984 - .long vector984, vector985, vector986, vector987 -#endif -#if PPC_NUM_VECTORS > 988 - .long vector988, vector989, vector990, vector991 -#endif -#if PPC_NUM_VECTORS > 992 - .long vector992, vector993, vector994, vector995 -#endif -#if PPC_NUM_VECTORS > 996 - .long vector996, vector997, vector998, vector999 -#endif -#if PPC_NUM_VECTORS > 1000 - .long vector1000, vector1001, vector1002, vector1003 -#endif -#if PPC_NUM_VECTORS > 1004 - .long vector1004, vector1005, vector1006, vector1007 -#endif -#if PPC_NUM_VECTORS > 1008 - .long vector1008, vector1009, vector1010, vector1011 -#endif -#if PPC_NUM_VECTORS > 1012 - .long vector1012, vector1013, vector1014, vector1015 -#endif -#if PPC_NUM_VECTORS > 1016 - .long vector1016, vector1017, vector1018, vector1019 -#endif -#if PPC_NUM_VECTORS > 1020 - .long vector1020, vector1021, vector1022, vector1023 -#endif - - .text - .align 2 - - .weak vector0, vector1, vector2, vector3 -#if PPC_NUM_VECTORS > 4 - .weak vector4, vector5, vector6, vector7 -#endif -#if PPC_NUM_VECTORS > 8 - .weak vector8, vector9, vector10, vector11 -#endif -#if PPC_NUM_VECTORS > 12 - .weak vector12, vector13, vector14, vector15 -#endif -#if PPC_NUM_VECTORS > 16 - .weak vector16, vector17, vector18, vector19 -#endif -#if PPC_NUM_VECTORS > 20 - .weak vector20, vector21, vector22, vector23 -#endif -#if PPC_NUM_VECTORS > 24 - .weak vector24, vector25, vector26, vector27 -#endif -#if PPC_NUM_VECTORS > 28 - .weak vector28, vector29, vector30, vector31 -#endif -#if PPC_NUM_VECTORS > 32 - .weak vector32, vector33, vector34, vector35 -#endif -#if PPC_NUM_VECTORS > 36 - .weak vector36, vector37, vector38, vector39 -#endif -#if PPC_NUM_VECTORS > 40 - .weak vector40, vector41, vector42, vector43 -#endif -#if PPC_NUM_VECTORS > 44 - .weak vector44, vector45, vector46, vector47 -#endif -#if PPC_NUM_VECTORS > 48 - .weak vector48, vector49, vector50, vector51 -#endif -#if PPC_NUM_VECTORS > 52 - .weak vector52, vector53, vector54, vector55 -#endif -#if PPC_NUM_VECTORS > 56 - .weak vector56, vector57, vector58, vector59 -#endif -#if PPC_NUM_VECTORS > 60 - .weak vector60, vector61, vector62, vector63 -#endif -#if PPC_NUM_VECTORS > 64 - .weak vector64, vector65, vector66, vector67 -#endif -#if PPC_NUM_VECTORS > 68 - .weak vector68, vector69, vector70, vector71 -#endif -#if PPC_NUM_VECTORS > 72 - .weak vector72, vector73, vector74, vector75 -#endif -#if PPC_NUM_VECTORS > 76 - .weak vector76, vector77, vector78, vector79 -#endif -#if PPC_NUM_VECTORS > 80 - .weak vector80, vector81, vector82, vector83 -#endif -#if PPC_NUM_VECTORS > 84 - .weak vector84, vector85, vector86, vector87 -#endif -#if PPC_NUM_VECTORS > 88 - .weak vector88, vector89, vector90, vector91 -#endif -#if PPC_NUM_VECTORS > 92 - .weak vector92, vector93, vector94, vector95 -#endif -#if PPC_NUM_VECTORS > 96 - .weak vector96, vector97, vector98, vector99 -#endif -#if PPC_NUM_VECTORS > 100 - .weak vector100, vector101, vector102, vector103 -#endif -#if PPC_NUM_VECTORS > 104 - .weak vector104, vector105, vector106, vector107 -#endif -#if PPC_NUM_VECTORS > 108 - .weak vector108, vector109, vector110, vector111 -#endif -#if PPC_NUM_VECTORS > 112 - .weak vector112, vector113, vector114, vector115 -#endif -#if PPC_NUM_VECTORS > 116 - .weak vector116, vector117, vector118, vector119 -#endif -#if PPC_NUM_VECTORS > 120 - .weak vector120, vector121, vector122, vector123 -#endif -#if PPC_NUM_VECTORS > 124 - .weak vector124, vector125, vector126, vector127 -#endif -#if PPC_NUM_VECTORS > 128 - .weak vector128, vector129, vector130, vector131 -#endif -#if PPC_NUM_VECTORS > 132 - .weak vector132, vector133, vector134, vector135 -#endif -#if PPC_NUM_VECTORS > 136 - .weak vector136, vector137, vector138, vector139 -#endif -#if PPC_NUM_VECTORS > 140 - .weak vector140, vector141, vector142, vector143 -#endif -#if PPC_NUM_VECTORS > 144 - .weak vector144, vector145, vector146, vector147 -#endif -#if PPC_NUM_VECTORS > 148 - .weak vector148, vector149, vector150, vector151 -#endif -#if PPC_NUM_VECTORS > 152 - .weak vector152, vector153, vector154, vector155 -#endif -#if PPC_NUM_VECTORS > 156 - .weak vector156, vector157, vector158, vector159 -#endif -#if PPC_NUM_VECTORS > 160 - .weak vector160, vector161, vector162, vector163 -#endif -#if PPC_NUM_VECTORS > 164 - .weak vector164, vector165, vector166, vector167 -#endif -#if PPC_NUM_VECTORS > 168 - .weak vector168, vector169, vector170, vector171 -#endif -#if PPC_NUM_VECTORS > 172 - .weak vector172, vector173, vector174, vector175 -#endif -#if PPC_NUM_VECTORS > 176 - .weak vector176, vector177, vector178, vector179 -#endif -#if PPC_NUM_VECTORS > 180 - .weak vector180, vector181, vector182, vector183 -#endif -#if PPC_NUM_VECTORS > 184 - .weak vector184, vector185, vector186, vector187 -#endif -#if PPC_NUM_VECTORS > 188 - .weak vector188, vector189, vector190, vector191 -#endif -#if PPC_NUM_VECTORS > 192 - .weak vector192, vector193, vector194, vector195 -#endif -#if PPC_NUM_VECTORS > 196 - .weak vector196, vector197, vector198, vector199 -#endif -#if PPC_NUM_VECTORS > 200 - .weak vector200, vector201, vector202, vector203 -#endif -#if PPC_NUM_VECTORS > 204 - .weak vector204, vector205, vector206, vector207 -#endif -#if PPC_NUM_VECTORS > 208 - .weak vector208, vector209, vector210, vector211 -#endif -#if PPC_NUM_VECTORS > 212 - .weak vector212, vector213, vector214, vector215 -#endif -#if PPC_NUM_VECTORS > 216 - .weak vector216, vector217, vector218, vector219 -#endif -#if PPC_NUM_VECTORS > 220 - .weak vector220, vector221, vector222, vector223 -#endif -#if PPC_NUM_VECTORS > 224 - .weak vector224, vector225, vector226, vector227 -#endif -#if PPC_NUM_VECTORS > 228 - .weak vector228, vector229, vector230, vector231 -#endif -#if PPC_NUM_VECTORS > 232 - .weak vector232, vector233, vector234, vector235 -#endif -#if PPC_NUM_VECTORS > 236 - .weak vector236, vector237, vector238, vector239 -#endif -#if PPC_NUM_VECTORS > 240 - .weak vector240, vector241, vector242, vector243 -#endif -#if PPC_NUM_VECTORS > 244 - .weak vector244, vector245, vector246, vector247 -#endif -#if PPC_NUM_VECTORS > 248 - .weak vector248, vector249, vector250, vector251 -#endif -#if PPC_NUM_VECTORS > 252 - .weak vector252, vector253, vector254, vector255 -#endif -#if PPC_NUM_VECTORS > 256 - .weak vector256, vector257, vector258, vector259 -#endif -#if PPC_NUM_VECTORS > 260 - .weak vector260, vector261, vector262, vector263 -#endif -#if PPC_NUM_VECTORS > 264 - .weak vector264, vector265, vector266, vector267 -#endif -#if PPC_NUM_VECTORS > 268 - .weak vector268, vector269, vector270, vector271 -#endif -#if PPC_NUM_VECTORS > 272 - .weak vector272, vector273, vector274, vector275 -#endif -#if PPC_NUM_VECTORS > 276 - .weak vector276, vector277, vector278, vector279 -#endif -#if PPC_NUM_VECTORS > 280 - .weak vector280, vector281, vector282, vector283 -#endif -#if PPC_NUM_VECTORS > 284 - .weak vector284, vector285, vector286, vector287 -#endif -#if PPC_NUM_VECTORS > 288 - .weak vector288, vector289, vector290, vector291 -#endif -#if PPC_NUM_VECTORS > 292 - .weak vector292, vector293, vector294, vector295 -#endif -#if PPC_NUM_VECTORS > 296 - .weak vector296, vector297, vector298, vector299 -#endif -#if PPC_NUM_VECTORS > 300 - .weak vector300, vector301, vector302, vector303 -#endif -#if PPC_NUM_VECTORS > 304 - .weak vector304, vector305, vector306, vector307 -#endif -#if PPC_NUM_VECTORS > 308 - .weak vector308, vector309, vector310, vector311 -#endif -#if PPC_NUM_VECTORS > 312 - .weak vector312, vector313, vector314, vector315 -#endif -#if PPC_NUM_VECTORS > 316 - .weak vector316, vector317, vector318, vector319 -#endif -#if PPC_NUM_VECTORS > 320 - .weak vector320, vector321, vector322, vector323 -#endif -#if PPC_NUM_VECTORS > 324 - .weak vector324, vector325, vector326, vector327 -#endif -#if PPC_NUM_VECTORS > 328 - .weak vector328, vector329, vector330, vector331 -#endif -#if PPC_NUM_VECTORS > 332 - .weak vector332, vector333, vector334, vector335 -#endif -#if PPC_NUM_VECTORS > 336 - .weak vector336, vector337, vector338, vector339 -#endif -#if PPC_NUM_VECTORS > 340 - .weak vector340, vector341, vector342, vector343 -#endif -#if PPC_NUM_VECTORS > 344 - .weak vector344, vector345, vector346, vector347 -#endif -#if PPC_NUM_VECTORS > 348 - .weak vector348, vector349, vector350, vector351 -#endif -#if PPC_NUM_VECTORS > 352 - .weak vector352, vector353, vector354, vector355 -#endif -#if PPC_NUM_VECTORS > 356 - .weak vector356, vector357, vector358, vector359 -#endif -#if PPC_NUM_VECTORS > 360 - .weak vector360, vector361, vector362, vector363 -#endif -#if PPC_NUM_VECTORS > 364 - .weak vector364, vector365, vector366, vector367 -#endif -#if PPC_NUM_VECTORS > 368 - .weak vector368, vector369, vector370, vector371 -#endif -#if PPC_NUM_VECTORS > 372 - .weak vector372, vector373, vector374, vector375 -#endif -#if PPC_NUM_VECTORS > 376 - .weak vector376, vector377, vector378, vector379 -#endif -#if PPC_NUM_VECTORS > 380 - .weak vector380, vector381, vector382, vector383 -#endif -#if PPC_NUM_VECTORS > 384 - .weak vector384, vector385, vector386, vector387 -#endif -#if PPC_NUM_VECTORS > 388 - .weak vector388, vector389, vector390, vector391 -#endif -#if PPC_NUM_VECTORS > 392 - .weak vector392, vector393, vector394, vector395 -#endif -#if PPC_NUM_VECTORS > 396 - .weak vector396, vector397, vector398, vector399 -#endif -#if PPC_NUM_VECTORS > 400 - .weak vector400, vector401, vector402, vector403 -#endif -#if PPC_NUM_VECTORS > 404 - .weak vector404, vector405, vector406, vector407 -#endif -#if PPC_NUM_VECTORS > 408 - .weak vector408, vector409, vector410, vector411 -#endif -#if PPC_NUM_VECTORS > 412 - .weak vector412, vector413, vector414, vector415 -#endif -#if PPC_NUM_VECTORS > 416 - .weak vector416, vector417, vector418, vector419 -#endif -#if PPC_NUM_VECTORS > 420 - .weak vector420, vector421, vector422, vector423 -#endif -#if PPC_NUM_VECTORS > 424 - .weak vector424, vector425, vector426, vector427 -#endif -#if PPC_NUM_VECTORS > 428 - .weak vector428, vector429, vector430, vector431 -#endif -#if PPC_NUM_VECTORS > 432 - .weak vector432, vector433, vector434, vector435 -#endif -#if PPC_NUM_VECTORS > 436 - .weak vector436, vector437, vector438, vector439 -#endif -#if PPC_NUM_VECTORS > 440 - .weak vector440, vector441, vector442, vector443 -#endif -#if PPC_NUM_VECTORS > 444 - .weak vector444, vector445, vector446, vector447 -#endif -#if PPC_NUM_VECTORS > 448 - .weak vector448, vector449, vector450, vector451 -#endif -#if PPC_NUM_VECTORS > 452 - .weak vector452, vector453, vector454, vector455 -#endif -#if PPC_NUM_VECTORS > 456 - .weak vector456, vector457, vector458, vector459 -#endif -#if PPC_NUM_VECTORS > 460 - .weak vector460, vector461, vector462, vector463 -#endif -#if PPC_NUM_VECTORS > 464 - .weak vector464, vector465, vector466, vector467 -#endif -#if PPC_NUM_VECTORS > 468 - .weak vector468, vector469, vector470, vector471 -#endif -#if PPC_NUM_VECTORS > 472 - .weak vector472, vector473, vector474, vector475 -#endif -#if PPC_NUM_VECTORS > 476 - .weak vector476, vector477, vector478, vector479 -#endif -#if PPC_NUM_VECTORS > 480 - .weak vector480, vector481, vector482, vector483 -#endif -#if PPC_NUM_VECTORS > 484 - .weak vector484, vector485, vector486, vector487 -#endif -#if PPC_NUM_VECTORS > 488 - .weak vector488, vector489, vector490, vector491 -#endif -#if PPC_NUM_VECTORS > 492 - .weak vector492, vector493, vector494, vector495 -#endif -#if PPC_NUM_VECTORS > 496 - .weak vector496, vector497, vector498, vector499 -#endif -#if PPC_NUM_VECTORS > 500 - .weak vector500, vector501, vector502, vector503 -#endif -#if PPC_NUM_VECTORS > 504 - .weak vector504, vector505, vector506, vector507 -#endif -#if PPC_NUM_VECTORS > 508 - .weak vector508, vector509, vector510, vector511 -#endif -#if PPC_NUM_VECTORS > 512 - .weak vector512, vector513, vector514, vector515 -#endif -#if PPC_NUM_VECTORS > 516 - .weak vector516, vector517, vector518, vector519 -#endif -#if PPC_NUM_VECTORS > 520 - .weak vector520, vector521, vector522, vector523 -#endif -#if PPC_NUM_VECTORS > 524 - .weak vector524, vector525, vector526, vector527 -#endif -#if PPC_NUM_VECTORS > 528 - .weak vector528, vector529, vector530, vector531 -#endif -#if PPC_NUM_VECTORS > 532 - .weak vector532, vector533, vector534, vector535 -#endif -#if PPC_NUM_VECTORS > 536 - .weak vector536, vector537, vector538, vector539 -#endif -#if PPC_NUM_VECTORS > 540 - .weak vector540, vector541, vector542, vector543 -#endif -#if PPC_NUM_VECTORS > 544 - .weak vector544, vector545, vector546, vector547 -#endif -#if PPC_NUM_VECTORS > 548 - .weak vector548, vector549, vector550, vector551 -#endif -#if PPC_NUM_VECTORS > 552 - .weak vector552, vector553, vector554, vector555 -#endif -#if PPC_NUM_VECTORS > 556 - .weak vector556, vector557, vector558, vector559 -#endif -#if PPC_NUM_VECTORS > 560 - .weak vector560, vector561, vector562, vector563 -#endif -#if PPC_NUM_VECTORS > 564 - .weak vector564, vector565, vector566, vector567 -#endif -#if PPC_NUM_VECTORS > 568 - .weak vector568, vector569, vector570, vector571 -#endif -#if PPC_NUM_VECTORS > 572 - .weak vector572, vector573, vector574, vector575 -#endif -#if PPC_NUM_VECTORS > 576 - .weak vector576, vector577, vector578, vector579 -#endif -#if PPC_NUM_VECTORS > 580 - .weak vector580, vector581, vector582, vector583 -#endif -#if PPC_NUM_VECTORS > 584 - .weak vector584, vector585, vector586, vector587 -#endif -#if PPC_NUM_VECTORS > 588 - .weak vector588, vector589, vector590, vector591 -#endif -#if PPC_NUM_VECTORS > 592 - .weak vector592, vector593, vector594, vector595 -#endif -#if PPC_NUM_VECTORS > 596 - .weak vector596, vector597, vector598, vector599 -#endif -#if PPC_NUM_VECTORS > 600 - .weak vector600, vector601, vector602, vector603 -#endif -#if PPC_NUM_VECTORS > 604 - .weak vector604, vector605, vector606, vector607 -#endif -#if PPC_NUM_VECTORS > 608 - .weak vector608, vector609, vector610, vector611 -#endif -#if PPC_NUM_VECTORS > 612 - .weak vector612, vector613, vector614, vector615 -#endif -#if PPC_NUM_VECTORS > 616 - .weak vector616, vector617, vector618, vector619 -#endif -#if PPC_NUM_VECTORS > 620 - .weak vector620, vector621, vector622, vector623 -#endif -#if PPC_NUM_VECTORS > 624 - .weak vector624, vector625, vector626, vector627 -#endif -#if PPC_NUM_VECTORS > 628 - .weak vector628, vector629, vector630, vector631 -#endif -#if PPC_NUM_VECTORS > 632 - .weak vector632, vector633, vector634, vector635 -#endif -#if PPC_NUM_VECTORS > 636 - .weak vector636, vector637, vector638, vector639 -#endif -#if PPC_NUM_VECTORS > 640 - .weak vector640, vector641, vector642, vector643 -#endif -#if PPC_NUM_VECTORS > 644 - .weak vector644, vector645, vector646, vector647 -#endif -#if PPC_NUM_VECTORS > 648 - .weak vector648, vector649, vector650, vector651 -#endif -#if PPC_NUM_VECTORS > 652 - .weak vector652, vector653, vector654, vector655 -#endif -#if PPC_NUM_VECTORS > 656 - .weak vector656, vector657, vector658, vector659 -#endif -#if PPC_NUM_VECTORS > 660 - .weak vector660, vector661, vector662, vector663 -#endif -#if PPC_NUM_VECTORS > 664 - .weak vector664, vector665, vector666, vector667 -#endif -#if PPC_NUM_VECTORS > 668 - .weak vector668, vector669, vector670, vector671 -#endif -#if PPC_NUM_VECTORS > 672 - .weak vector672, vector673, vector674, vector675 -#endif -#if PPC_NUM_VECTORS > 676 - .weak vector676, vector677, vector678, vector679 -#endif -#if PPC_NUM_VECTORS > 680 - .weak vector680, vector681, vector682, vector683 -#endif -#if PPC_NUM_VECTORS > 684 - .weak vector684, vector685, vector686, vector687 -#endif -#if PPC_NUM_VECTORS > 688 - .weak vector688, vector689, vector690, vector691 -#endif -#if PPC_NUM_VECTORS > 692 - .weak vector692, vector693, vector694, vector695 -#endif -#if PPC_NUM_VECTORS > 696 - .weak vector696, vector697, vector698, vector699 -#endif -#if PPC_NUM_VECTORS > 700 - .weak vector700, vector701, vector702, vector703 -#endif -#if PPC_NUM_VECTORS > 704 - .weak vector704, vector705, vector706, vector707 -#endif -#if PPC_NUM_VECTORS > 708 - .weak vector708, vector709, vector710, vector711 -#endif -#if PPC_NUM_VECTORS > 712 - .weak vector712, vector713, vector714, vector715 -#endif -#if PPC_NUM_VECTORS > 716 - .weak vector716, vector717, vector718, vector719 -#endif -#if PPC_NUM_VECTORS > 720 - .weak vector720, vector721, vector722, vector723 -#endif -#if PPC_NUM_VECTORS > 724 - .weak vector724, vector725, vector726, vector727 -#endif -#if PPC_NUM_VECTORS > 728 - .weak vector728, vector729, vector730, vector731 -#endif -#if PPC_NUM_VECTORS > 732 - .weak vector732, vector733, vector734, vector735 -#endif -#if PPC_NUM_VECTORS > 736 - .weak vector736, vector737, vector738, vector739 -#endif -#if PPC_NUM_VECTORS > 740 - .weak vector740, vector741, vector742, vector743 -#endif -#if PPC_NUM_VECTORS > 744 - .weak vector744, vector745, vector746, vector747 -#endif -#if PPC_NUM_VECTORS > 748 - .weak vector748, vector749, vector750, vector751 -#endif -#if PPC_NUM_VECTORS > 752 - .weak vector752, vector753, vector754, vector755 -#endif -#if PPC_NUM_VECTORS > 756 - .weak vector756, vector757, vector758, vector759 -#endif -#if PPC_NUM_VECTORS > 760 - .weak vector760, vector761, vector762, vector763 -#endif -#if PPC_NUM_VECTORS > 764 - .weak vector764, vector765, vector766, vector767 -#endif -#if PPC_NUM_VECTORS > 768 - .weak vector768, vector769, vector770, vector771 -#endif -#if PPC_NUM_VECTORS > 772 - .weak vector772, vector773, vector774, vector775 -#endif -#if PPC_NUM_VECTORS > 776 - .weak vector776, vector777, vector778, vector779 -#endif -#if PPC_NUM_VECTORS > 780 - .weak vector780, vector781, vector782, vector783 -#endif -#if PPC_NUM_VECTORS > 784 - .weak vector784, vector785, vector786, vector787 -#endif -#if PPC_NUM_VECTORS > 788 - .weak vector788, vector789, vector790, vector791 -#endif -#if PPC_NUM_VECTORS > 792 - .weak vector792, vector793, vector794, vector795 -#endif -#if PPC_NUM_VECTORS > 796 - .weak vector796, vector797, vector798, vector799 -#endif -#if PPC_NUM_VECTORS > 800 - .weak vector800, vector801, vector802, vector803 -#endif -#if PPC_NUM_VECTORS > 804 - .weak vector804, vector805, vector806, vector807 -#endif -#if PPC_NUM_VECTORS > 808 - .weak vector808, vector809, vector810, vector811 -#endif -#if PPC_NUM_VECTORS > 812 - .weak vector812, vector813, vector814, vector815 -#endif -#if PPC_NUM_VECTORS > 816 - .weak vector816, vector817, vector818, vector819 -#endif -#if PPC_NUM_VECTORS > 820 - .weak vector820, vector821, vector822, vector823 -#endif -#if PPC_NUM_VECTORS > 824 - .weak vector824, vector825, vector826, vector827 -#endif -#if PPC_NUM_VECTORS > 828 - .weak vector828, vector829, vector830, vector831 -#endif -#if PPC_NUM_VECTORS > 832 - .weak vector832, vector833, vector834, vector835 -#endif -#if PPC_NUM_VECTORS > 836 - .weak vector836, vector837, vector838, vector839 -#endif -#if PPC_NUM_VECTORS > 840 - .weak vector840, vector841, vector842, vector843 -#endif -#if PPC_NUM_VECTORS > 844 - .weak vector844, vector845, vector846, vector847 -#endif -#if PPC_NUM_VECTORS > 848 - .weak vector848, vector849, vector850, vector851 -#endif -#if PPC_NUM_VECTORS > 852 - .weak vector852, vector853, vector854, vector855 -#endif -#if PPC_NUM_VECTORS > 856 - .weak vector856, vector857, vector858, vector859 -#endif -#if PPC_NUM_VECTORS > 860 - .weak vector860, vector861, vector862, vector863 -#endif -#if PPC_NUM_VECTORS > 864 - .weak vector864, vector865, vector866, vector867 -#endif -#if PPC_NUM_VECTORS > 868 - .weak vector868, vector869, vector870, vector871 -#endif -#if PPC_NUM_VECTORS > 872 - .weak vector872, vector873, vector874, vector875 -#endif -#if PPC_NUM_VECTORS > 876 - .weak vector876, vector877, vector878, vector879 -#endif -#if PPC_NUM_VECTORS > 880 - .weak vector880, vector881, vector882, vector883 -#endif -#if PPC_NUM_VECTORS > 884 - .weak vector884, vector885, vector886, vector887 -#endif -#if PPC_NUM_VECTORS > 888 - .weak vector888, vector889, vector890, vector891 -#endif -#if PPC_NUM_VECTORS > 892 - .weak vector892, vector893, vector894, vector895 -#endif -#if PPC_NUM_VECTORS > 896 - .weak vector896, vector897, vector898, vector899 -#endif -#if PPC_NUM_VECTORS > 900 - .weak vector900, vector901, vector902, vector903 -#endif -#if PPC_NUM_VECTORS > 904 - .weak vector904, vector905, vector906, vector907 -#endif -#if PPC_NUM_VECTORS > 908 - .weak vector908, vector909, vector910, vector911 -#endif -#if PPC_NUM_VECTORS > 912 - .weak vector912, vector913, vector914, vector915 -#endif -#if PPC_NUM_VECTORS > 916 - .weak vector916, vector917, vector918, vector919 -#endif -#if PPC_NUM_VECTORS > 920 - .weak vector920, vector921, vector922, vector923 -#endif -#if PPC_NUM_VECTORS > 924 - .weak vector924, vector925, vector926, vector927 -#endif -#if PPC_NUM_VECTORS > 928 - .weak vector928, vector929, vector930, vector931 -#endif -#if PPC_NUM_VECTORS > 932 - .weak vector932, vector933, vector934, vector935 -#endif -#if PPC_NUM_VECTORS > 936 - .weak vector936, vector937, vector938, vector939 -#endif -#if PPC_NUM_VECTORS > 940 - .weak vector940, vector941, vector942, vector943 -#endif -#if PPC_NUM_VECTORS > 944 - .weak vector944, vector945, vector946, vector947 -#endif -#if PPC_NUM_VECTORS > 948 - .weak vector948, vector949, vector950, vector951 -#endif -#if PPC_NUM_VECTORS > 952 - .weak vector952, vector953, vector954, vector955 -#endif -#if PPC_NUM_VECTORS > 956 - .weak vector956, vector957, vector958, vector959 -#endif -#if PPC_NUM_VECTORS > 960 - .weak vector960, vector961, vector962, vector963 -#endif -#if PPC_NUM_VECTORS > 964 - .weak vector964, vector965, vector966, vector967 -#endif -#if PPC_NUM_VECTORS > 968 - .weak vector968, vector969, vector970, vector971 -#endif -#if PPC_NUM_VECTORS > 972 - .weak vector972, vector973, vector974, vector975 -#endif -#if PPC_NUM_VECTORS > 976 - .weak vector976, vector977, vector978, vector979 -#endif -#if PPC_NUM_VECTORS > 980 - .weak vector980, vector981, vector982, vector983 -#endif -#if PPC_NUM_VECTORS > 984 - .weak vector984, vector985, vector986, vector987 -#endif -#if PPC_NUM_VECTORS > 988 - .weak vector988, vector989, vector990, vector991 -#endif -#if PPC_NUM_VECTORS > 992 - .weak vector992, vector993, vector994, vector995 -#endif -#if PPC_NUM_VECTORS > 996 - .weak vector996, vector997, vector998, vector999 -#endif -#if PPC_NUM_VECTORS > 1000 - .weak vector1000, vector1001, vector1002, vector1003 -#endif -#if PPC_NUM_VECTORS > 1004 - .weak vector1004, vector1005, vector1006, vector1007 -#endif -#if PPC_NUM_VECTORS > 1008 - .weak vector1008, vector1009, vector1010, vector1011 -#endif -#if PPC_NUM_VECTORS > 1012 - .weak vector1012, vector1013, vector1014, vector1015 -#endif -#if PPC_NUM_VECTORS > 1016 - .weak vector1016, vector1017, vector1018, vector1019 -#endif -#if PPC_NUM_VECTORS > 1020 - .weak vector1020, vector1021, vector1022, vector1023 -#endif - -vector0: -vector1: -vector2: -vector3: -vector4: -vector5: -vector6: -vector7: -vector8: -vector9: -vector10: -vector11: -vector12: -vector13: -vector14: -vector15: -vector16: -vector17: -vector18: -vector19: -vector20: -vector21: -vector22: -vector23: -vector24: -vector25: -vector26: -vector27: -vector28: -vector29: -vector30: -vector31: -vector32: -vector33: -vector34: -vector35: -vector36: -vector37: -vector38: -vector39: -vector40: -vector41: -vector42: -vector43: -vector44: -vector45: -vector46: -vector47: -vector48: -vector49: -vector50: -vector51: -vector52: -vector53: -vector54: -vector55: -vector56: -vector57: -vector58: -vector59: -vector60: -vector61: -vector62: -vector63: -vector64: -vector65: -vector66: -vector67: -vector68: -vector69: -vector70: -vector71: -vector72: -vector73: -vector74: -vector75: -vector76: -vector77: -vector78: -vector79: -vector80: -vector81: -vector82: -vector83: -vector84: -vector85: -vector86: -vector87: -vector88: -vector89: -vector90: -vector91: -vector92: -vector93: -vector94: -vector95: -vector96: -vector97: -vector98: -vector99: -vector100: -vector101: -vector102: -vector103: -vector104: -vector105: -vector106: -vector107: -vector108: -vector109: -vector110: -vector111: -vector112: -vector113: -vector114: -vector115: -vector116: -vector117: -vector118: -vector119: -vector120: -vector121: -vector122: -vector123: -vector124: -vector125: -vector126: -vector127: -vector128: -vector129: -vector130: -vector131: -vector132: -vector133: -vector134: -vector135: -vector136: -vector137: -vector138: -vector139: -vector140: -vector141: -vector142: -vector143: -vector144: -vector145: -vector146: -vector147: -vector148: -vector149: -vector150: -vector151: -vector152: -vector153: -vector154: -vector155: -vector156: -vector157: -vector158: -vector159: -vector160: -vector161: -vector162: -vector163: -vector164: -vector165: -vector166: -vector167: -vector168: -vector169: -vector170: -vector171: -vector172: -vector173: -vector174: -vector175: -vector176: -vector177: -vector178: -vector179: -vector180: -vector181: -vector182: -vector183: -vector184: -vector185: -vector186: -vector187: -vector188: -vector189: -vector190: -vector191: -vector192: -vector193: -vector194: -vector195: -vector196: -vector197: -vector198: -vector199: -vector200: -vector201: -vector202: -vector203: -vector204: -vector205: -vector206: -vector207: -vector208: -vector209: -vector210: -vector211: -vector212: -vector213: -vector214: -vector215: -vector216: -vector217: -vector218: -vector219: -vector220: -vector221: -vector222: -vector223: -vector224: -vector225: -vector226: -vector227: -vector228: -vector229: -vector230: -vector231: -vector232: -vector233: -vector234: -vector235: -vector236: -vector237: -vector238: -vector239: -vector240: -vector241: -vector242: -vector243: -vector244: -vector245: -vector246: -vector247: -vector248: -vector249: -vector250: -vector251: -vector252: -vector253: -vector254: -vector255: -vector256: -vector257: -vector258: -vector259: -vector260: -vector261: -vector262: -vector263: -vector264: -vector265: -vector266: -vector267: -vector268: -vector269: -vector270: -vector271: -vector272: -vector273: -vector274: -vector275: -vector276: -vector277: -vector278: -vector279: -vector280: -vector281: -vector282: -vector283: -vector284: -vector285: -vector286: -vector287: -vector288: -vector289: -vector290: -vector291: -vector292: -vector293: -vector294: -vector295: -vector296: -vector297: -vector298: -vector299: -vector300: -vector301: -vector302: -vector303: -vector304: -vector305: -vector306: -vector307: -vector308: -vector309: -vector310: -vector311: -vector312: -vector313: -vector314: -vector315: -vector316: -vector317: -vector318: -vector319: -vector320: -vector321: -vector322: -vector323: -vector324: -vector325: -vector326: -vector327: -vector328: -vector329: -vector330: -vector331: -vector332: -vector333: -vector334: -vector335: -vector336: -vector337: -vector338: -vector339: -vector340: -vector341: -vector342: -vector343: -vector344: -vector345: -vector346: -vector347: -vector348: -vector349: -vector350: -vector351: -vector352: -vector353: -vector354: -vector355: -vector356: -vector357: -vector358: -vector359: -vector360: -vector361: -vector362: -vector363: -vector364: -vector365: -vector366: -vector367: -vector368: -vector369: -vector370: -vector371: -vector372: -vector373: -vector374: -vector375: -vector376: -vector377: -vector378: -vector379: -vector380: -vector381: -vector382: -vector383: -vector384: -vector385: -vector386: -vector387: -vector388: -vector389: -vector390: -vector391: -vector392: -vector393: -vector394: -vector395: -vector396: -vector397: -vector398: -vector399: -vector400: -vector401: -vector402: -vector403: -vector404: -vector405: -vector406: -vector407: -vector408: -vector409: -vector410: -vector411: -vector412: -vector413: -vector414: -vector415: -vector416: -vector417: -vector418: -vector419: -vector420: -vector421: -vector422: -vector423: -vector424: -vector425: -vector426: -vector427: -vector428: -vector429: -vector430: -vector431: -vector432: -vector433: -vector434: -vector435: -vector436: -vector437: -vector438: -vector439: -vector440: -vector441: -vector442: -vector443: -vector444: -vector445: -vector446: -vector447: -vector448: -vector449: -vector450: -vector451: -vector452: -vector453: -vector454: -vector455: -vector456: -vector457: -vector458: -vector459: -vector460: -vector461: -vector462: -vector463: -vector464: -vector465: -vector466: -vector467: -vector468: -vector469: -vector470: -vector471: -vector472: -vector473: -vector474: -vector475: -vector476: -vector477: -vector478: -vector479: -vector480: -vector481: -vector482: -vector483: -vector484: -vector485: -vector486: -vector487: -vector488: -vector489: -vector490: -vector491: -vector492: -vector493: -vector494: -vector495: -vector496: -vector497: -vector498: -vector499: -vector500: -vector501: -vector502: -vector503: -vector504: -vector505: -vector506: -vector507: -vector508: -vector509: -vector510: -vector511: -vector512: -vector513: -vector514: -vector515: -vector516: -vector517: -vector518: -vector519: -vector520: -vector521: -vector522: -vector523: -vector524: -vector525: -vector526: -vector527: -vector528: -vector529: -vector530: -vector531: -vector532: -vector533: -vector534: -vector535: -vector536: -vector537: -vector538: -vector539: -vector540: -vector541: -vector542: -vector543: -vector544: -vector545: -vector546: -vector547: -vector548: -vector549: -vector550: -vector551: -vector552: -vector553: -vector554: -vector555: -vector556: -vector557: -vector558: -vector559: -vector560: -vector561: -vector562: -vector563: -vector564: -vector565: -vector566: -vector567: -vector568: -vector569: -vector570: -vector571: -vector572: -vector573: -vector574: -vector575: -vector576: -vector577: -vector578: -vector579: -vector580: -vector581: -vector582: -vector583: -vector584: -vector585: -vector586: -vector587: -vector588: -vector589: -vector590: -vector591: -vector592: -vector593: -vector594: -vector595: -vector596: -vector597: -vector598: -vector599: -vector600: -vector601: -vector602: -vector603: -vector604: -vector605: -vector606: -vector607: -vector608: -vector609: -vector610: -vector611: -vector612: -vector613: -vector614: -vector615: -vector616: -vector617: -vector618: -vector619: -vector620: -vector621: -vector622: -vector623: -vector624: -vector625: -vector626: -vector627: -vector628: -vector629: -vector630: -vector631: -vector632: -vector633: -vector634: -vector635: -vector636: -vector637: -vector638: -vector639: -vector640: -vector641: -vector642: -vector643: -vector644: -vector645: -vector646: -vector647: -vector648: -vector649: -vector650: -vector651: -vector652: -vector653: -vector654: -vector655: -vector656: -vector657: -vector658: -vector659: -vector660: -vector661: -vector662: -vector663: -vector664: -vector665: -vector666: -vector667: -vector668: -vector669: -vector670: -vector671: -vector672: -vector673: -vector674: -vector675: -vector676: -vector677: -vector678: -vector679: -vector680: -vector681: -vector682: -vector683: -vector684: -vector685: -vector686: -vector687: -vector688: -vector689: -vector690: -vector691: -vector692: -vector693: -vector694: -vector695: -vector696: -vector697: -vector698: -vector699: -vector700: -vector701: -vector702: -vector703: -vector704: -vector705: -vector706: -vector707: -vector708: -vector709: -vector710: -vector711: -vector712: -vector713: -vector714: -vector715: -vector716: -vector717: -vector718: -vector719: -vector720: -vector721: -vector722: -vector723: -vector724: -vector725: -vector726: -vector727: -vector728: -vector729: -vector730: -vector731: -vector732: -vector733: -vector734: -vector735: -vector736: -vector737: -vector738: -vector739: -vector740: -vector741: -vector742: -vector743: -vector744: -vector745: -vector746: -vector747: -vector748: -vector749: -vector750: -vector751: -vector752: -vector753: -vector754: -vector755: -vector756: -vector757: -vector758: -vector759: -vector760: -vector761: -vector762: -vector763: -vector764: -vector765: -vector766: -vector767: -vector768: -vector769: -vector770: -vector771: -vector772: -vector773: -vector774: -vector775: -vector776: -vector777: -vector778: -vector779: -vector780: -vector781: -vector782: -vector783: -vector784: -vector785: -vector786: -vector787: -vector788: -vector789: -vector790: -vector791: -vector792: -vector793: -vector794: -vector795: -vector796: -vector797: -vector798: -vector799: -vector800: -vector801: -vector802: -vector803: -vector804: -vector805: -vector806: -vector807: -vector808: -vector809: -vector810: -vector811: -vector812: -vector813: -vector814: -vector815: -vector816: -vector817: -vector818: -vector819: -vector820: -vector821: -vector822: -vector823: -vector824: -vector825: -vector826: -vector827: -vector828: -vector829: -vector830: -vector831: -vector832: -vector833: -vector834: -vector835: -vector836: -vector837: -vector838: -vector839: -vector840: -vector841: -vector842: -vector843: -vector844: -vector845: -vector846: -vector847: -vector848: -vector849: -vector850: -vector851: -vector852: -vector853: -vector854: -vector855: -vector856: -vector857: -vector858: -vector859: -vector860: -vector861: -vector862: -vector863: -vector864: -vector865: -vector866: -vector867: -vector868: -vector869: -vector870: -vector871: -vector872: -vector873: -vector874: -vector875: -vector876: -vector877: -vector878: -vector879: -vector880: -vector881: -vector882: -vector883: -vector884: -vector885: -vector886: -vector887: -vector888: -vector889: -vector890: -vector891: -vector892: -vector893: -vector894: -vector895: -vector896: -vector897: -vector898: -vector899: -vector900: -vector901: -vector902: -vector903: -vector904: -vector905: -vector906: -vector907: -vector908: -vector909: -vector910: -vector911: -vector912: -vector913: -vector914: -vector915: -vector916: -vector917: -vector918: -vector919: -vector920: -vector921: -vector922: -vector923: -vector924: -vector925: -vector926: -vector927: -vector928: -vector929: -vector930: -vector931: -vector932: -vector933: -vector934: -vector935: -vector936: -vector937: -vector938: -vector939: -vector940: -vector941: -vector942: -vector943: -vector944: -vector945: -vector946: -vector947: -vector948: -vector949: -vector950: -vector951: -vector952: -vector953: -vector954: -vector955: -vector956: -vector957: -vector958: -vector959: -vector960: -vector961: -vector962: -vector963: -vector964: -vector965: -vector966: -vector967: -vector968: -vector969: -vector970: -vector971: -vector972: -vector973: -vector974: -vector975: -vector976: -vector977: -vector978: -vector979: -vector980: -vector981: -vector982: -vector983: -vector984: -vector985: -vector986: -vector987: -vector988: -vector989: -vector990: -vector991: -vector992: -vector993: -vector994: -vector995: -vector996: -vector997: -vector998: -vector999: -vector1000: -vector1001: -vector1002: -vector1003: -vector1004: -vector1005: -vector1006: -vector1007: -vector1008: -vector1009: -vector1010: -vector1011: -vector1012: -vector1013: -vector1014: -vector1015: -vector1016: -vector1017: -vector1018: -vector1019: -vector1020: -vector1021: -vector1022: -vector1023: - b _unhandled_irq - - .weak _unhandled_irq - .type _unhandled_irq, @function -_unhandled_irq: - b _unhandled_irq - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560BCxx/boot.h b/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560BCxx/boot.h deleted file mode 100644 index 9dc4a8a42e..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560BCxx/boot.h +++ /dev/null @@ -1,114 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file boot.h - * @brief Boot parameters for the SPC560BCxx. - * @{ - */ - -#ifndef _BOOT_H_ -#define _BOOT_H_ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @name BUCSR registers definitions - * @{ - */ -#define BUCSR_BPEN 0x00000001 -#define BUCSR_BALLOC_BFI 0x00000200 -/** @} */ - -/** - * @name MSR register definitions - * @{ - */ -#define MSR_WE 0x00040000 -#define MSR_CE 0x00020000 -#define MSR_EE 0x00008000 -#define MSR_PR 0x00004000 -#define MSR_ME 0x00001000 -#define MSR_DE 0x00000200 -#define MSR_IS 0x00000020 -#define MSR_DS 0x00000010 -#define MSR_RI 0x00000002 -/** @} */ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/* - * BUCSR default settings. - */ -#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__) -#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI) -#endif - -/* - * MSR default settings. - */ -#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__) -#define BOOT_MSR_DEFAULT (MSR_WE | MSR_CE | MSR_ME) -#endif - -/* - * Boot default settings. - */ -#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__) -#define BOOT_PERFORM_CORE_INIT 1 -#endif - -/* - * VLE mode default settings. - */ -#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__) -#define BOOT_USE_VLE 1 -#endif - -/* - * RAM relocation flag. - */ -#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__) -#define BOOT_RELOCATE_IN_RAM 0 -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -#endif /* _BOOT_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560BCxx/boot.s b/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560BCxx/boot.s deleted file mode 100644 index 3586a38636..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560BCxx/boot.s +++ /dev/null @@ -1,214 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SPC560BCxx/boot.s - * @brief SPC560BCxx boot-related code. - * - * @addtogroup PPC_BOOT - * @{ - */ - -#include "boot.h" - -#if !defined(__DOXYGEN__) - - /* BAM record.*/ - .section .boot, "ax" - - .long 0x015A0000 - .long _reset_address - - .align 2 - .globl _reset_address - .type _reset_address, @function -_reset_address: -#if BOOT_PERFORM_CORE_INIT - bl _coreinit -#endif - bl _ivinit - -#if BOOT_RELOCATE_IN_RAM - /* - * Image relocation in RAM. - */ - lis %r4, __ram_reloc_start__@h - ori %r4, %r4, __ram_reloc_start__@l - lis %r5, __ram_reloc_dest__@h - ori %r5, %r5, __ram_reloc_dest__@l - lis %r6, __ram_reloc_end__@h - ori %r6, %r6, __ram_reloc_end__@l -.relloop: - cmpl cr0, %r4, %r6 - bge cr0, .relend - lwz %r7, 0(%r4) - addi %r4, %r4, 4 - stw %r7, 0(%r5) - addi %r5, %r5, 4 - b .relloop -.relend: - lis %r3, _boot_address@h - ori %r3, %r3, _boot_address@l - mtctr %r3 - bctrl -#else - b _boot_address -#endif - -#if BOOT_PERFORM_CORE_INIT - .align 2 -_coreinit: - /* - * RAM clearing, this device requires a write to all RAM location in - * order to initialize the ECC detection hardware, this is going to - * slow down the startup but there is no way around. - */ - xor %r0, %r0, %r0 - xor %r1, %r1, %r1 - xor %r2, %r2, %r2 - xor %r3, %r3, %r3 - xor %r4, %r4, %r4 - xor %r5, %r5, %r5 - xor %r6, %r6, %r6 - xor %r7, %r7, %r7 - xor %r8, %r8, %r8 - xor %r9, %r9, %r9 - xor %r10, %r10, %r10 - xor %r11, %r11, %r11 - xor %r12, %r12, %r12 - xor %r13, %r13, %r13 - xor %r14, %r14, %r14 - xor %r15, %r15, %r15 - xor %r16, %r16, %r16 - xor %r17, %r17, %r17 - xor %r18, %r18, %r18 - xor %r19, %r19, %r19 - xor %r20, %r20, %r20 - xor %r21, %r21, %r21 - xor %r22, %r22, %r22 - xor %r23, %r23, %r23 - xor %r24, %r24, %r24 - xor %r25, %r25, %r25 - xor %r26, %r26, %r26 - xor %r27, %r27, %r27 - xor %r28, %r28, %r28 - xor %r29, %r29, %r29 - xor %r30, %r30, %r30 - xor %r31, %r31, %r31 - lis %r4, __ram_start__@h - ori %r4, %r4, __ram_start__@l - lis %r5, __ram_end__@h - ori %r5, %r5, __ram_end__@l -.cleareccloop: - cmpl %cr0, %r4, %r5 - bge %cr0, .cleareccend - stmw %r16, 0(%r4) - addi %r4, %r4, 64 - b .cleareccloop -.cleareccend: - - /* - * Branch prediction enabled. - */ - li %r3, BOOT_BUCSR_DEFAULT - mtspr 1013, %r3 /* BUCSR */ - - blr -#endif /* BOOT_PERFORM_CORE_INIT */ - - /* - * Exception vectors initialization. - */ - .align 2 -_ivinit: - /* MSR initialization.*/ - lis %r3, BOOT_MSR_DEFAULT@h - ori %r3, %r3, BOOT_MSR_DEFAULT@l - mtMSR %r3 - - /* IVPR initialization.*/ - lis %r3, __ivpr_base__@h - ori %r3, %r3, __ivpr_base__@l - mtIVPR %r3 - - blr - - .section .ivors, "ax" - - .globl IVORS -IVORS: - b _IVOR0 - .align 4 - b _IVOR1 - .align 4 - b _IVOR2 - .align 4 - b _IVOR3 - .align 4 - b _IVOR4 - .align 4 - b _IVOR5 - .align 4 - b _IVOR6 - .align 4 - b _IVOR7 - .align 4 - b _IVOR8 - .align 4 - b _IVOR9 - .align 4 - b _IVOR10 - .align 4 - b _IVOR11 - .align 4 - b _IVOR12 - .align 4 - b _IVOR13 - .align 4 - b _IVOR14 - .align 4 - b _IVOR15 - - .section .handlers, "ax" - - /* - * Default IVOR handlers. - */ - .align 2 - .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5 - .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11 - .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15 -_IVOR0: -_IVOR1: -_IVOR2: -_IVOR3: -_IVOR5: -_IVOR6: -_IVOR7: -_IVOR8: -_IVOR9: -_IVOR11: -_IVOR12: -_IVOR13: -_IVOR14: -_IVOR15: - .global _unhandled_exception -_unhandled_exception: - b _unhandled_exception - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560BCxx/intc.h b/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560BCxx/intc.h deleted file mode 100644 index ad6f04568c..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560BCxx/intc.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SPC560BCxx/intc.h - * @brief SPC560BCxx INTC module header. - * - * @addtogroup INTC - * @{ - */ - -#ifndef _INTC_H_ -#define _INTC_H_ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @name INTC addresses - * @{ - */ -#define INTC_BASE 0xFFF48000 -#define INTC_IACKR_ADDR (INTC_BASE + 0x10) -#define INTC_EOIR_ADDR (INTC_BASE + 0x18) -/** @} */ - -/** - * @brief INTC priority levels. - */ -#define INTC_PRIORITY_LEVELS 16U - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @name INTC-related macros - * @{ - */ -#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0))) -#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t))))) -#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t))))) -#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t))))) -#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t))))) -/** @} */ - -/** - * @brief Core selection macros for PSR register. - */ -#define INTC_PSR_CORE0 0x00 - -/** - * @brief PSR register content helper - */ -#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -#endif /* _INTC_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560BCxx/ppcparams.h b/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560BCxx/ppcparams.h deleted file mode 100644 index a3b15d2276..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560BCxx/ppcparams.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SPC560BCxx/ppcparams.h - * @brief PowerPC parameters for the SPC560BCxx. - * - * @defgroup PPC_SPC560BCxx SPC560BCxx Specific Parameters - * @ingroup PPC_SPECIFIC - * @details This file contains the PowerPC specific parameters for the - * SPC560BCxx platform. - * @{ - */ - -#ifndef _PPCPARAMS_H_ -#define _PPCPARAMS_H_ - -/** - * @brief Family identification macro. - */ -#define PPC_SPC560BCxx - -/** - * @brief PPC core model. - */ -#define PPC_VARIANT PPC_VARIANT_e200z0 - -/** - * @brief Number of cores. - */ -#define PPC_CORE_NUMBER 1 - -/** - * @brief Number of writable bits in IVPR register. - */ -#define PPC_IVPR_BITS 20 - -/** - * @brief IVORx registers support. - */ -#define PPC_SUPPORTS_IVORS FALSE - -/** - * @brief Book E instruction set support. - */ -#define PPC_SUPPORTS_BOOKE FALSE - -/** - * @brief VLE instruction set support. - */ -#define PPC_SUPPORTS_VLE TRUE - -/** - * @brief Supports VLS Load/Store Multiple Volatile instructions. - */ -#define PPC_SUPPORTS_VLE_MULTI TRUE - -/** - * @brief Supports the decrementer timer. - */ -#define PPC_SUPPORTS_DECREMENTER FALSE - -/** - * @brief Number of interrupt sources. - */ -#define PPC_NUM_VECTORS 217 - -#endif /* _PPCPARAMS_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560Bxx/boot.h b/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560Bxx/boot.h deleted file mode 100644 index 509600a50d..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560Bxx/boot.h +++ /dev/null @@ -1,114 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file boot.h - * @brief Boot parameters for the SPC560Bxx. - * @{ - */ - -#ifndef _BOOT_H_ -#define _BOOT_H_ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @name BUCSR registers definitions - * @{ - */ -#define BUCSR_BPEN 0x00000001 -#define BUCSR_BALLOC_BFI 0x00000200 -/** @} */ - -/** - * @name MSR register definitions - * @{ - */ -#define MSR_WE 0x00040000 -#define MSR_CE 0x00020000 -#define MSR_EE 0x00008000 -#define MSR_PR 0x00004000 -#define MSR_ME 0x00001000 -#define MSR_DE 0x00000200 -#define MSR_IS 0x00000020 -#define MSR_DS 0x00000010 -#define MSR_RI 0x00000002 -/** @} */ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/* - * BUCSR default settings. - */ -#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__) -#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI) -#endif - -/* - * MSR default settings. - */ -#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__) -#define BOOT_MSR_DEFAULT (MSR_WE | MSR_CE | MSR_ME) -#endif - -/* - * Boot default settings. - */ -#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__) -#define BOOT_PERFORM_CORE_INIT 1 -#endif - -/* - * VLE mode default settings. - */ -#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__) -#define BOOT_USE_VLE 1 -#endif - -/* - * RAM relocation flag. - */ -#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__) -#define BOOT_RELOCATE_IN_RAM 0 -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -#endif /* _BOOT_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560Bxx/boot.s b/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560Bxx/boot.s deleted file mode 100644 index 6566b51c0b..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560Bxx/boot.s +++ /dev/null @@ -1,214 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SPC560Bxx/boot.s - * @brief SPC560Bxx boot-related code. - * - * @addtogroup PPC_BOOT - * @{ - */ - -#include "boot.h" - -#if !defined(__DOXYGEN__) - - /* BAM record.*/ - .section .boot, "ax" - - .long 0x015A0000 - .long _reset_address - - .align 2 - .globl _reset_address - .type _reset_address, @function -_reset_address: -#if BOOT_PERFORM_CORE_INIT - bl _coreinit -#endif - bl _ivinit - -#if BOOT_RELOCATE_IN_RAM - /* - * Image relocation in RAM. - */ - lis %r4, __ram_reloc_start__@h - ori %r4, %r4, __ram_reloc_start__@l - lis %r5, __ram_reloc_dest__@h - ori %r5, %r5, __ram_reloc_dest__@l - lis %r6, __ram_reloc_end__@h - ori %r6, %r6, __ram_reloc_end__@l -.relloop: - cmpl cr0, %r4, %r6 - bge cr0, .relend - lwz %r7, 0(%r4) - addi %r4, %r4, 4 - stw %r7, 0(%r5) - addi %r5, %r5, 4 - b .relloop -.relend: - lis %r3, _boot_address@h - ori %r3, %r3, _boot_address@l - mtctr %r3 - bctrl -#else - b _boot_address -#endif - -#if BOOT_PERFORM_CORE_INIT - .align 2 -_coreinit: - /* - * RAM clearing, this device requires a write to all RAM location in - * order to initialize the ECC detection hardware, this is going to - * slow down the startup but there is no way around. - */ - xor %r0, %r0, %r0 - xor %r1, %r1, %r1 - xor %r2, %r2, %r2 - xor %r3, %r3, %r3 - xor %r4, %r4, %r4 - xor %r5, %r5, %r5 - xor %r6, %r6, %r6 - xor %r7, %r7, %r7 - xor %r8, %r8, %r8 - xor %r9, %r9, %r9 - xor %r10, %r10, %r10 - xor %r11, %r11, %r11 - xor %r12, %r12, %r12 - xor %r13, %r13, %r13 - xor %r14, %r14, %r14 - xor %r15, %r15, %r15 - xor %r16, %r16, %r16 - xor %r17, %r17, %r17 - xor %r18, %r18, %r18 - xor %r19, %r19, %r19 - xor %r20, %r20, %r20 - xor %r21, %r21, %r21 - xor %r22, %r22, %r22 - xor %r23, %r23, %r23 - xor %r24, %r24, %r24 - xor %r25, %r25, %r25 - xor %r26, %r26, %r26 - xor %r27, %r27, %r27 - xor %r28, %r28, %r28 - xor %r29, %r29, %r29 - xor %r30, %r30, %r30 - xor %r31, %r31, %r31 - lis %r4, __ram_start__@h - ori %r4, %r4, __ram_start__@l - lis %r5, __ram_end__@h - ori %r5, %r5, __ram_end__@l -.cleareccloop: - cmpl %cr0, %r4, %r5 - bge %cr0, .cleareccend - stmw %r16, 0(%r4) - addi %r4, %r4, 64 - b .cleareccloop -.cleareccend: - - /* - * Branch prediction enabled. - */ - li %r3, BOOT_BUCSR_DEFAULT - mtspr 1013, %r3 /* BUCSR */ - - blr -#endif /* BOOT_PERFORM_CORE_INIT */ - - /* - * Exception vectors initialization. - */ - .align 2 -_ivinit: - /* MSR initialization.*/ - lis %r3, BOOT_MSR_DEFAULT@h - ori %r3, %r3, BOOT_MSR_DEFAULT@l - mtMSR %r3 - - /* IVPR initialization.*/ - lis %r3, __ivpr_base__@h - ori %r3, %r3, __ivpr_base__@l - mtIVPR %r3 - - blr - - .section .ivors, "ax" - - .globl IVORS -IVORS: - b _IVOR0 - .align 4 - b _IVOR1 - .align 4 - b _IVOR2 - .align 4 - b _IVOR3 - .align 4 - b _IVOR4 - .align 4 - b _IVOR5 - .align 4 - b _IVOR6 - .align 4 - b _IVOR7 - .align 4 - b _IVOR8 - .align 4 - b _IVOR9 - .align 4 - b _IVOR10 - .align 4 - b _IVOR11 - .align 4 - b _IVOR12 - .align 4 - b _IVOR13 - .align 4 - b _IVOR14 - .align 4 - b _IVOR15 - - .section .handlers, "ax" - - /* - * Default IVOR handlers. - */ - .align 2 - .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5 - .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11 - .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15 -_IVOR0: -_IVOR1: -_IVOR2: -_IVOR3: -_IVOR5: -_IVOR6: -_IVOR7: -_IVOR8: -_IVOR9: -_IVOR11: -_IVOR12: -_IVOR13: -_IVOR14: -_IVOR15: - .global _unhandled_exception -_unhandled_exception: - b _unhandled_exception - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560Bxx/intc.h b/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560Bxx/intc.h deleted file mode 100644 index f53ca709a3..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560Bxx/intc.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SPC560Bxx/intc.h - * @brief SPC560Bxx INTC module header. - * - * @addtogroup INTC - * @{ - */ - -#ifndef _INTC_H_ -#define _INTC_H_ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @name INTC addresses - * @{ - */ -#define INTC_BASE 0xFFF48000 -#define INTC_IACKR_ADDR (INTC_BASE + 0x10) -#define INTC_EOIR_ADDR (INTC_BASE + 0x18) -/** @} */ - -/** - * @brief INTC priority levels. - */ -#define INTC_PRIORITY_LEVELS 16U - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @name INTC-related macros - * @{ - */ -#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0))) -#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t))))) -#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t))))) -#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t))))) -#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t))))) -/** @} */ - -/** - * @brief Core selection macros for PSR register. - */ -#define INTC_PSR_CORE0 0x00 - -/** - * @brief PSR register content helper - */ -#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -#endif /* _INTC_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560Bxx/ppcparams.h b/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560Bxx/ppcparams.h deleted file mode 100644 index 8067f4b7cc..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560Bxx/ppcparams.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SPC560Bxx/ppcparams.h - * @brief PowerPC parameters for the SPC560Bxx. - * - * @defgroup PPC_SPC560Bxx SPC560Bxx Specific Parameters - * @ingroup PPC_SPECIFIC - * @details This file contains the PowerPC specific parameters for the - * SPC560Bxx platform. - * @{ - */ - -#ifndef _PPCPARAMS_H_ -#define _PPCPARAMS_H_ - -/** - * @brief Family identification macro. - */ -#define PPC_SPC560Bxx - -/** - * @brief PPC core model. - */ -#define PPC_VARIANT PPC_VARIANT_e200z0 - -/** - * @brief Number of cores. - */ -#define PPC_CORE_NUMBER 1 - -/** - * @brief Number of writable bits in IVPR register. - */ -#define PPC_IVPR_BITS 20 - -/** - * @brief IVORx registers support. - */ -#define PPC_SUPPORTS_IVORS FALSE - -/** - * @brief Book E instruction set support. - */ -#define PPC_SUPPORTS_BOOKE FALSE - -/** - * @brief VLE instruction set support. - */ -#define PPC_SUPPORTS_VLE TRUE - -/** - * @brief Supports VLS Load/Store Multiple Volatile instructions. - */ -#define PPC_SUPPORTS_VLE_MULTI TRUE - -/** - * @brief Supports the decrementer timer. - */ -#define PPC_SUPPORTS_DECREMENTER FALSE - -/** - * @brief Number of interrupt sources. - */ -#define PPC_NUM_VECTORS 234 - -#endif /* _PPCPARAMS_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560Dxx/boot.h b/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560Dxx/boot.h deleted file mode 100644 index 20964da7f4..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560Dxx/boot.h +++ /dev/null @@ -1,114 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file boot.h - * @brief Boot parameters for the SPC560Dxx. - * @{ - */ - -#ifndef _BOOT_H_ -#define _BOOT_H_ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @name BUCSR registers definitions - * @{ - */ -#define BUCSR_BPEN 0x00000001 -#define BUCSR_BALLOC_BFI 0x00000200 -/** @} */ - -/** - * @name MSR register definitions - * @{ - */ -#define MSR_WE 0x00040000 -#define MSR_CE 0x00020000 -#define MSR_EE 0x00008000 -#define MSR_PR 0x00004000 -#define MSR_ME 0x00001000 -#define MSR_DE 0x00000200 -#define MSR_IS 0x00000020 -#define MSR_DS 0x00000010 -#define MSR_RI 0x00000002 -/** @} */ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/* - * BUCSR default settings. - */ -#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__) -#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI) -#endif - -/* - * MSR default settings. - */ -#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__) -#define BOOT_MSR_DEFAULT (MSR_WE | MSR_CE | MSR_ME) -#endif - -/* - * Boot default settings. - */ -#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__) -#define BOOT_PERFORM_CORE_INIT 1 -#endif - -/* - * VLE mode default settings. - */ -#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__) -#define BOOT_USE_VLE 1 -#endif - -/* - * RAM relocation flag. - */ -#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__) -#define BOOT_RELOCATE_IN_RAM 0 -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -#endif /* _BOOT_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560Dxx/boot.s b/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560Dxx/boot.s deleted file mode 100644 index a1ee9c9749..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560Dxx/boot.s +++ /dev/null @@ -1,214 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SPC560Dxx/boot.s - * @brief SPC560Dxx boot-related code. - * - * @addtogroup PPC_BOOT - * @{ - */ - -#include "boot.h" - -#if !defined(__DOXYGEN__) - - /* BAM record.*/ - .section .boot, "ax" - - .long 0x015A0000 - .long _reset_address - - .align 2 - .globl _reset_address - .type _reset_address, @function -_reset_address: -#if BOOT_PERFORM_CORE_INIT - bl _coreinit -#endif - bl _ivinit - -#if BOOT_RELOCATE_IN_RAM - /* - * Image relocation in RAM. - */ - lis r4, __ram_reloc_start__@h - ori r4, r4, __ram_reloc_start__@l - lis r5, __ram_reloc_dest__@h - ori r5, r5, __ram_reloc_dest__@l - lis r6, __ram_reloc_end__@h - ori r6, r6, __ram_reloc_end__@l -.relloop: - cmpl cr0, r4, r6 - bge cr0, .relend - lwz r7, 0(r4) - addi r4, r4, 4 - stw r7, 0(r5) - addi r5, r5, 4 - b .relloop -.relend: - lis r3, _boot_address@h - ori r3, r3, _boot_address@l - mtctr r3 - bctrl -#else - b _boot_address -#endif - -#if BOOT_PERFORM_CORE_INIT - .align 2 -_coreinit: - /* - * RAM clearing, this device requires a write to all RAM location in - * order to initialize the ECC detection hardware, this is going to - * slow down the startup but there is no way around. - */ - xor r0, r0, r0 - xor r1, r1, r1 - xor r2, r2, r2 - xor r3, r3, r3 - xor r4, r4, r4 - xor r5, r5, r5 - xor r6, r6, r6 - xor r7, r7, r7 - xor r8, r8, r8 - xor r9, r9, r9 - xor r10, r10, r10 - xor r11, r11, r11 - xor r12, r12, r12 - xor r13, r13, r13 - xor r14, r14, r14 - xor r15, r15, r15 - xor r16, r16, r16 - xor r17, r17, r17 - xor r18, r18, r18 - xor r19, r19, r19 - xor r20, r20, r20 - xor r21, r21, r21 - xor r22, r22, r22 - xor r23, r23, r23 - xor r24, r24, r24 - xor r25, r25, r25 - xor r26, r26, r26 - xor r27, r27, r27 - xor r28, r28, r28 - xor r29, r29, r29 - xor r30, r30, r30 - xor r31, r31, r31 - lis r4, __ram_start__@h - ori r4, r4, __ram_start__@l - lis r5, __ram_end__@h - ori r5, r5, __ram_end__@l -.cleareccloop: - cmpl cr0, r4, r5 - bge cr0, .cleareccend - stmw r16, 0(r4) - addi r4, r4, 64 - b .cleareccloop -.cleareccend: - - /* - * Branch prediction enabled. - */ - li r3, BOOT_BUCSR_DEFAULT - mtspr 1013, r3 /* BUCSR */ - - blr -#endif /* BOOT_PERFORM_CORE_INIT */ - - /* - * Exception vectors initialization. - */ - .align 2 -_ivinit: - /* MSR initialization.*/ - lis r3, BOOT_MSR_DEFAULT@h - ori r3, r3, BOOT_MSR_DEFAULT@l - mtMSR r3 - - /* IVPR initialization.*/ - lis r3, __ivpr_base__@h - ori r3, r3, __ivpr_base__@l - mtIVPR r3 - - blr - - .section .ivors, "ax" - - .globl IVORS -IVORS: - b _IVOR0 - .align 4 - b _IVOR1 - .align 4 - b _IVOR2 - .align 4 - b _IVOR3 - .align 4 - b _IVOR4 - .align 4 - b _IVOR5 - .align 4 - b _IVOR6 - .align 4 - b _IVOR7 - .align 4 - b _IVOR8 - .align 4 - b _IVOR9 - .align 4 - b _IVOR10 - .align 4 - b _IVOR11 - .align 4 - b _IVOR12 - .align 4 - b _IVOR13 - .align 4 - b _IVOR14 - .align 4 - b _IVOR15 - - .section .handlers, "ax" - - /* - * Default IVOR handlers. - */ - .align 2 - .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5 - .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11 - .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15 -_IVOR0: -_IVOR1: -_IVOR2: -_IVOR3: -_IVOR5: -_IVOR6: -_IVOR7: -_IVOR8: -_IVOR9: -_IVOR11: -_IVOR12: -_IVOR13: -_IVOR14: -_IVOR15: - .global _unhandled_exception -_unhandled_exception: - b _unhandled_exception - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560Dxx/boot_cw.s b/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560Dxx/boot_cw.s deleted file mode 100644 index b2e5894b29..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560Dxx/boot_cw.s +++ /dev/null @@ -1,200 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SPC560Dxx/boot.s - * @brief SPC560Dxx boot-related code. - * - * @addtogroup PPC_BOOT - * @{ - */ - -#include "boot.h" - -#if !defined(__DOXYGEN__) - - .extern _boot_address - .extern __ram_start__ - .extern __ram_end__ - .extern __ivpr_base__ - - .extern _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5 - .extern _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11 - .extern _IVOR12, _IVOR13, _IVOR14, _IVOR15 - - /* BAM record.*/ - .section .boot, 16 - - .long 0x015A0000 - .long _reset_address - - .align 4 - .globl _reset_address - .type _reset_address, @function -_reset_address: -#if BOOT_PERFORM_CORE_INIT - se_bl _coreinit -#endif - se_bl _ivinit - -#if BOOT_RELOCATE_IN_RAM - /* - * Image relocation in RAM. - */ - e_lis r4, __ram_reloc_start__@h - e_or2i r4, r4, __ram_reloc_start__@l - e_lis r5, __ram_reloc_dest__@h - e_or2i r5, r5, __ram_reloc_dest__@l - e_lis r6, __ram_reloc_end__@h - e_or2i r6, r6, __ram_reloc_end__@l -.relloop: - se_cmpl r4, r6 - se_bge .relend - se_lwz r7, 0(r4) - se_addi r4, 4 - se_stw r7, 0(r5) - se_addi r5, 4 - se_b .relloop -.relend: - e_lis r3, _boot_address@h - e_or2i r3, _boot_address@l - mtctr r3 - se_bctrl -#else - e_b _boot_address -#endif - -#if BOOT_PERFORM_CORE_INIT - .align 4 -_coreinit: - /* - * RAM clearing, this device requires a write to all RAM location in - * order to initialize the ECC detection hardware, this is going to - * slow down the startup but there is no way around. - */ - xor r0, r0, r0 - xor r1, r1, r1 - xor r2, r2, r2 - xor r3, r3, r3 - xor r4, r4, r4 - xor r5, r5, r5 - xor r6, r6, r6 - xor r7, r7, r7 - xor r8, r8, r8 - xor r9, r9, r9 - xor r10, r10, r10 - xor r11, r11, r11 - xor r12, r12, r12 - xor r13, r13, r13 - xor r14, r14, r14 - xor r15, r15, r15 - xor r16, r16, r16 - xor r17, r17, r17 - xor r18, r18, r18 - xor r19, r19, r19 - xor r20, r20, r20 - xor r21, r21, r21 - xor r22, r22, r22 - xor r23, r23, r23 - xor r24, r24, r24 - xor r25, r25, r25 - xor r26, r26, r26 - xor r27, r27, r27 - xor r28, r28, r28 - xor r29, r29, r29 - xor r30, r30, r30 - xor r31, r31, r31 - e_lis r4, __ram_start__@h - e_or2i r4, __ram_start__@l - e_lis r5, __ram_end__@h - e_or2i r5, __ram_end__@l -.cleareccloop: - se_cmpl r4, r5 - se_bge .cleareccend - e_stmw r16, 0(r4) - e_addi r4, r4, 64 - se_b .cleareccloop -.cleareccend: - - /* - * Branch prediction enabled. - */ - e_li r3, BOOT_BUCSR_DEFAULT - mtspr 1013, r3 /* BUCSR */ - - se_blr -#endif /* BOOT_PERFORM_CORE_INIT */ - - /* - * Exception vectors initialization. - */ - .align 4 -_ivinit: - /* MSR initialization.*/ - e_lis r3, BOOT_MSR_DEFAULT@h - e_ori r3, r3, BOOT_MSR_DEFAULT@l - mtMSR r3 - - /* IVPR initialization.*/ - e_lis r3, __ivpr_base__@h - e_or2i r3, __ivpr_base__@l - mtIVPR r3 - - se_blr - - .section .ivors, text_vle - .align 16 - .globl IVORS -IVORS: - e_b _IVOR0 - .align 16 - e_b _IVOR1 - .align 16 - e_b _IVOR2 - .align 16 - e_b _IVOR3 - .align 16 - e_b _IVOR4 - .align 16 - e_b _IVOR5 - .align 16 - e_b _IVOR6 - .align 16 - e_b _IVOR7 - .align 16 - e_b _IVOR8 - .align 16 - e_b _IVOR9 - .align 16 - e_b _IVOR10 - .align 16 - e_b _IVOR11 - .align 16 - e_b _IVOR12 - .align 16 - e_b _IVOR13 - .align 16 - e_b _IVOR14 - .align 16 - e_b _IVOR15 - - .section .handlers, text_vle - .align 16 - - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560Dxx/intc.h b/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560Dxx/intc.h deleted file mode 100644 index 1a19d0455b..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560Dxx/intc.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SPC560Dxx/intc.h - * @brief SPC560Dxx INTC module header. - * - * @addtogroup INTC - * @{ - */ - -#ifndef _INTC_H_ -#define _INTC_H_ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @name INTC addresses - * @{ - */ -#define INTC_BASE 0xFFF48000 -#define INTC_IACKR_ADDR (INTC_BASE + 0x10) -#define INTC_EOIR_ADDR (INTC_BASE + 0x18) -/** @} */ - -/** - * @brief INTC priority levels. - */ -#define INTC_PRIORITY_LEVELS 16U - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @name INTC-related macros - * @{ - */ -#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0))) -#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t))))) -#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t))))) -#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t))))) -#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t))))) -/** @} */ - -/** - * @brief Core selection macros for PSR register. - */ -#define INTC_PSR_CORE0 0x00 - -/** - * @brief PSR register content helper - */ -#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -#endif /* _INTC_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560Dxx/ppcparams.h b/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560Dxx/ppcparams.h deleted file mode 100644 index 2e4c38f2bf..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560Dxx/ppcparams.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SPC560Dxx/ppcparams.h - * @brief PowerPC parameters for the SPC560Dxx. - * - * @defgroup PPC_SPC560Dxx SPC560Dxx Specific Parameters - * @ingroup PPC_SPECIFIC - * @details This file contains the PowerPC specific parameters for the - * SPC560Dxx platform. - * @{ - */ - -#ifndef _PPCPARAMS_H_ -#define _PPCPARAMS_H_ - -/** - * @brief Family identification macro. - */ -#define PPC_SPC560Dxx - -/** - * @brief PPC core model. - */ -#define PPC_VARIANT PPC_VARIANT_e200z0 - -/** - * @brief Number of cores. - */ -#define PPC_CORE_NUMBER 1 - -/** - * @brief Number of writable bits in IVPR register. - */ -#define PPC_IVPR_BITS 20 - -/** - * @brief IVORx registers support. - */ -#define PPC_SUPPORTS_IVORS FALSE - -/** - * @brief Book E instruction set support. - */ -#define PPC_SUPPORTS_BOOKE FALSE - -/** - * @brief VLE instruction set support. - */ -#define PPC_SUPPORTS_VLE TRUE - -/** - * @brief Supports VLS Load/Store Multiple Volatile instructions. - */ -#define PPC_SUPPORTS_VLE_MULTI TRUE - -/** - * @brief Supports the decrementer timer. - */ -#define PPC_SUPPORTS_DECREMENTER FALSE - -/** - * @brief Number of interrupt sources. - */ -#define PPC_NUM_VECTORS 155 - -#endif /* _PPCPARAMS_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560Pxx/boot.h b/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560Pxx/boot.h deleted file mode 100644 index ad945be86f..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560Pxx/boot.h +++ /dev/null @@ -1,114 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file boot.h - * @brief Boot parameters for the SPC560Pxx. - * @{ - */ - -#ifndef _BOOT_H_ -#define _BOOT_H_ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @name BUCSR registers definitions - * @{ - */ -#define BUCSR_BPEN 0x00000001 -#define BUCSR_BALLOC_BFI 0x00000200 -/** @} */ - -/** - * @name MSR register definitions - * @{ - */ -#define MSR_WE 0x00040000 -#define MSR_CE 0x00020000 -#define MSR_EE 0x00008000 -#define MSR_PR 0x00004000 -#define MSR_ME 0x00001000 -#define MSR_DE 0x00000200 -#define MSR_IS 0x00000020 -#define MSR_DS 0x00000010 -#define MSR_RI 0x00000002 -/** @} */ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/* - * BUCSR default settings. - */ -#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__) -#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI) -#endif - -/* - * MSR default settings. - */ -#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__) -#define BOOT_MSR_DEFAULT (MSR_WE | MSR_CE | MSR_ME) -#endif - -/* - * Boot default settings. - */ -#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__) -#define BOOT_PERFORM_CORE_INIT 1 -#endif - -/* - * VLE mode default settings. - */ -#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__) -#define BOOT_USE_VLE 1 -#endif - -/* - * RAM relocation flag. - */ -#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__) -#define BOOT_RELOCATE_IN_RAM 0 -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -#endif /* _BOOT_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560Pxx/boot.s b/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560Pxx/boot.s deleted file mode 100644 index 9904dd0be0..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560Pxx/boot.s +++ /dev/null @@ -1,214 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SPC560Pxx/boot.s - * @brief SPC560Pxx boot-related code. - * - * @addtogroup PPC_BOOT - * @{ - */ - -#include "boot.h" - -#if !defined(__DOXYGEN__) - - /* BAM record.*/ - .section .boot, "ax" - - .long 0x015A0000 - .long _reset_address - - .align 2 - .globl _reset_address - .type _reset_address, @function -_reset_address: -#if BOOT_PERFORM_CORE_INIT - bl _coreinit -#endif - bl _ivinit - -#if BOOT_RELOCATE_IN_RAM - /* - * Image relocation in RAM. - */ - lis %r4, __ram_reloc_start__@h - ori %r4, %r4, __ram_reloc_start__@l - lis %r5, __ram_reloc_dest__@h - ori %r5, %r5, __ram_reloc_dest__@l - lis %r6, __ram_reloc_end__@h - ori %r6, %r6, __ram_reloc_end__@l -.relloop: - cmpl cr0, %r4, %r6 - bge cr0, .relend - lwz %r7, 0(%r4) - addi %r4, %r4, 4 - stw %r7, 0(%r5) - addi %r5, %r5, 4 - b .relloop -.relend: - lis %r3, _boot_address@h - ori %r3, %r3, _boot_address@l - mtctr %r3 - bctrl -#else - b _boot_address -#endif - -#if BOOT_PERFORM_CORE_INIT - .align 2 -_coreinit: - /* - * RAM clearing, this device requires a write to all RAM location in - * order to initialize the ECC detection hardware, this is going to - * slow down the startup but there is no way around. - */ - xor %r0, %r0, %r0 - xor %r1, %r1, %r1 - xor %r2, %r2, %r2 - xor %r3, %r3, %r3 - xor %r4, %r4, %r4 - xor %r5, %r5, %r5 - xor %r6, %r6, %r6 - xor %r7, %r7, %r7 - xor %r8, %r8, %r8 - xor %r9, %r9, %r9 - xor %r10, %r10, %r10 - xor %r11, %r11, %r11 - xor %r12, %r12, %r12 - xor %r13, %r13, %r13 - xor %r14, %r14, %r14 - xor %r15, %r15, %r15 - xor %r16, %r16, %r16 - xor %r17, %r17, %r17 - xor %r18, %r18, %r18 - xor %r19, %r19, %r19 - xor %r20, %r20, %r20 - xor %r21, %r21, %r21 - xor %r22, %r22, %r22 - xor %r23, %r23, %r23 - xor %r24, %r24, %r24 - xor %r25, %r25, %r25 - xor %r26, %r26, %r26 - xor %r27, %r27, %r27 - xor %r28, %r28, %r28 - xor %r29, %r29, %r29 - xor %r30, %r30, %r30 - xor %r31, %r31, %r31 - lis %r4, __ram_start__@h - ori %r4, %r4, __ram_start__@l - lis %r5, __ram_end__@h - ori %r5, %r5, __ram_end__@l -.cleareccloop: - cmpl %cr0, %r4, %r5 - bge %cr0, .cleareccend - stmw %r16, 0(%r4) - addi %r4, %r4, 64 - b .cleareccloop -.cleareccend: - - /* - * Branch prediction enabled. - */ - li %r3, BOOT_BUCSR_DEFAULT - mtspr 1013, %r3 /* BUCSR */ - - blr -#endif /* BOOT_PERFORM_CORE_INIT */ - - /* - * Exception vectors initialization. - */ - .align 2 -_ivinit: - /* MSR initialization.*/ - lis %r3, BOOT_MSR_DEFAULT@h - ori %r3, %r3, BOOT_MSR_DEFAULT@l - mtMSR %r3 - - /* IVPR initialization.*/ - lis %r3, __ivpr_base__@h - ori %r3, %r3, __ivpr_base__@l - mtIVPR %r3 - - blr - - .section .ivors, "ax" - - .globl IVORS -IVORS: - b _IVOR0 - .align 4 - b _IVOR1 - .align 4 - b _IVOR2 - .align 4 - b _IVOR3 - .align 4 - b _IVOR4 - .align 4 - b _IVOR5 - .align 4 - b _IVOR6 - .align 4 - b _IVOR7 - .align 4 - b _IVOR8 - .align 4 - b _IVOR9 - .align 4 - b _IVOR10 - .align 4 - b _IVOR11 - .align 4 - b _IVOR12 - .align 4 - b _IVOR13 - .align 4 - b _IVOR14 - .align 4 - b _IVOR15 - - .section .handlers, "ax" - - /* - * Default IVOR handlers. - */ - .align 2 - .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5 - .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11 - .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15 -_IVOR0: -_IVOR1: -_IVOR2: -_IVOR3: -_IVOR5: -_IVOR6: -_IVOR7: -_IVOR8: -_IVOR9: -_IVOR11: -_IVOR12: -_IVOR13: -_IVOR14: -_IVOR15: - .global _unhandled_exception -_unhandled_exception: - b _unhandled_exception - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560Pxx/intc.h b/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560Pxx/intc.h deleted file mode 100644 index c33b6f2693..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560Pxx/intc.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SPC560Pxx/intc.h - * @brief SPC560Pxx INTC module header. - * - * @addtogroup INTC - * @{ - */ - -#ifndef _INTC_H_ -#define _INTC_H_ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @name INTC addresses - * @{ - */ -#define INTC_BASE 0xFFF48000 -#define INTC_IACKR_ADDR (INTC_BASE + 0x10) -#define INTC_EOIR_ADDR (INTC_BASE + 0x18) -/** @} */ - -/** - * @brief INTC priority levels. - */ -#define INTC_PRIORITY_LEVELS 16U - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @name INTC-related macros - * @{ - */ -#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0))) -#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t))))) -#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t))))) -#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t))))) -#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t))))) -/** @} */ - -/** - * @brief Core selection macros for PSR register. - */ -#define INTC_PSR_CORE0 0x00 - -/** - * @brief PSR register content helper - */ -#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -#endif /* _INTC_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560Pxx/ppcparams.h b/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560Pxx/ppcparams.h deleted file mode 100644 index f2b14f6dc5..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC560Pxx/ppcparams.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SPC560Pxx/ppcparams.h - * @brief PowerPC parameters for the SPC560Pxx. - * - * @defgroup PPC_SPC560Pxx SPC560Pxx Specific Parameters - * @ingroup PPC_SPECIFIC - * @details This file contains the PowerPC specific parameters for the - * SPC560Pxx platform. - * @{ - */ - -#ifndef _PPCPARAMS_H_ -#define _PPCPARAMS_H_ - -/** - * @brief Family identification macro. - */ -#define PPC_SPC560Pxx - -/** - * @brief PPC core model. - */ -#define PPC_VARIANT PPC_VARIANT_e200z0 - -/** - * @brief Number of cores. - */ -#define PPC_CORE_NUMBER 1 - -/** - * @brief Number of writable bits in IVPR register. - */ -#define PPC_IVPR_BITS 20 - -/** - * @brief IVORx registers support. - */ -#define PPC_SUPPORTS_IVORS FALSE - -/** - * @brief Book E instruction set support. - */ -#define PPC_SUPPORTS_BOOKE FALSE - -/** - * @brief VLE instruction set support. - */ -#define PPC_SUPPORTS_VLE TRUE - -/** - * @brief Supports VLS Load/Store Multiple Volatile instructions. - */ -#define PPC_SUPPORTS_VLE_MULTI TRUE - -/** - * @brief Supports the decrementer timer. - */ -#define PPC_SUPPORTS_DECREMENTER FALSE - -/** - * @brief Number of interrupt sources. - */ -#define PPC_NUM_VECTORS 261 - -#endif /* _PPCPARAMS_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC563Mxx/boot.h b/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC563Mxx/boot.h deleted file mode 100644 index 3a2a0a5162..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC563Mxx/boot.h +++ /dev/null @@ -1,119 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file boot.h - * @brief Boot parameters for the SPC563Mxx. - * @{ - */ - -#ifndef _BOOT_H_ -#define _BOOT_H_ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @name BUCSR registers definitions - * @{ - */ -#define BUCSR_BPEN 0x00000001 -#define BUCSR_BALLOC_BFI 0x00000200 -/** @} */ - -/** - * @name MSR register definitions - * @{ - */ -#define MSR_UCLE 0x04000000 -#define MSR_SPE 0x02000000 -#define MSR_WE 0x00040000 -#define MSR_CE 0x00020000 -#define MSR_EE 0x00008000 -#define MSR_PR 0x00004000 -#define MSR_FP 0x00002000 -#define MSR_ME 0x00001000 -#define MSR_FE0 0x00000800 -#define MSR_DE 0x00000200 -#define MSR_FE1 0x00000100 -#define MSR_IS 0x00000020 -#define MSR_DS 0x00000010 -#define MSR_RI 0x00000002 -/** @} */ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/* - * BUCSR default settings. - */ -#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__) -#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI) -#endif - -/* - * MSR default settings. - */ -#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__) -#define BOOT_MSR_DEFAULT (MSR_SPE | MSR_WE | MSR_CE | MSR_ME) -#endif - -/* - * Boot default settings. - */ -#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__) -#define BOOT_PERFORM_CORE_INIT 1 -#endif - -/* - * VLE mode default settings. - */ -#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__) -#define BOOT_USE_VLE 1 -#endif - -/* - * RAM relocation flag. - */ -#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__) -#define BOOT_RELOCATE_IN_RAM 0 -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -#endif /* _BOOT_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC563Mxx/boot.s b/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC563Mxx/boot.s deleted file mode 100644 index da34b2d4a8..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC563Mxx/boot.s +++ /dev/null @@ -1,188 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SPC563Mxx/boot.s - * @brief SPC563Mxx boot-related code. - * - * @addtogroup PPC_BOOT - * @{ - */ - -#include "boot.h" - -#if !defined(__DOXYGEN__) - - /* BAM record.*/ - .section .boot, "ax" - -#if BOOT_USE_VLE - .long 0x015A0000 -#else - .long 0x005A0000 -#endif - .long _reset_address - - .align 2 - .globl _reset_address - .type _reset_address, @function -_reset_address: -#if BOOT_PERFORM_CORE_INIT - bl _coreinit -#endif - bl _ivinit - -#if BOOT_RELOCATE_IN_RAM - /* - * Image relocation in RAM. - */ - lis %r4, __ram_reloc_start__@h - ori %r4, %r4, __ram_reloc_start__@l - lis %r5, __ram_reloc_dest__@h - ori %r5, %r5, __ram_reloc_dest__@l - lis %r6, __ram_reloc_end__@h - ori %r6, %r6, __ram_reloc_end__@l -.relloop: - cmpl cr0, %r4, %r6 - bge cr0, .relend - lwz %r7, 0(%r4) - addi %r4, %r4, 4 - stw %r7, 0(%r5) - addi %r5, %r5, 4 - b .relloop -.relend: - lis %r3, _boot_address@h - ori %r3, %r3, _boot_address@l - mtctr %r3 - bctrl -#else - b _boot_address -#endif - -#if BOOT_PERFORM_CORE_INIT - .align 2 -_coreinit: - /* - * RAM clearing, this device requires a write to all RAM location in - * order to initialize the ECC detection hardware, this is going to - * slow down the startup but there is no way around. - */ - xor %r0, %r0, %r0 - xor %r1, %r1, %r1 - xor %r2, %r2, %r2 - xor %r3, %r3, %r3 - xor %r4, %r4, %r4 - xor %r5, %r5, %r5 - xor %r6, %r6, %r6 - xor %r7, %r7, %r7 - xor %r8, %r8, %r8 - xor %r9, %r9, %r9 - xor %r10, %r10, %r10 - xor %r11, %r11, %r11 - xor %r12, %r12, %r12 - xor %r13, %r13, %r13 - xor %r14, %r14, %r14 - xor %r15, %r15, %r15 - xor %r16, %r16, %r16 - xor %r17, %r17, %r17 - xor %r18, %r18, %r18 - xor %r19, %r19, %r19 - xor %r20, %r20, %r20 - xor %r21, %r21, %r21 - xor %r22, %r22, %r22 - xor %r23, %r23, %r23 - xor %r24, %r24, %r24 - xor %r25, %r25, %r25 - xor %r26, %r26, %r26 - xor %r27, %r27, %r27 - xor %r28, %r28, %r28 - xor %r29, %r29, %r29 - xor %r30, %r30, %r30 - xor %r31, %r31, %r31 - lis %r4, __ram_start__@h - ori %r4, %r4, __ram_start__@l - lis %r5, __ram_end__@h - ori %r5, %r5, __ram_end__@l -.cleareccloop: - cmpl %cr0, %r4, %r5 - bge %cr0, .cleareccend - stmw %r16, 0(%r4) - addi %r4, %r4, 64 - b .cleareccloop -.cleareccend: - - /* - * Branch prediction enabled. - */ - li %r3, BOOT_BUCSR_DEFAULT - mtspr 1013, %r3 /* BUCSR */ - - blr -#endif /* BOOT_PERFORM_CORE_INIT */ - - /* - * Exception vectors initialization. - */ -_ivinit: - /* MSR initialization.*/ - lis %r3, BOOT_MSR_DEFAULT@h - ori %r3, %r3, BOOT_MSR_DEFAULT@l - mtMSR %r3 - - /* IVPR initialization.*/ - lis %r3, __ivpr_base__@h - ori %r3, %r3, __ivpr_base__@l - mtIVPR %r3 - - /* IVORs initialization.*/ - lis %r3, _unhandled_exception@h - ori %r3, %r3, _unhandled_exception@l - - mtspr 400, %r3 /* IVOR0-15 */ - mtspr 401, %r3 - mtspr 402, %r3 - mtspr 403, %r3 - mtspr 404, %r3 - mtspr 405, %r3 - mtspr 406, %r3 - mtspr 407, %r3 - mtspr 408, %r3 - mtspr 409, %r3 - mtspr 410, %r3 - mtspr 411, %r3 - mtspr 412, %r3 - mtspr 413, %r3 - mtspr 414, %r3 - mtspr 415, %r3 - mtspr 528, %r3 /* IVOR32-34 */ - mtspr 529, %r3 - mtspr 530, %r3 - - blr - - .section .handlers, "ax" - - /* - * Unhandled exceptions handler. - */ - .weak _unhandled_exception - .type _unhandled_exception, @function -_unhandled_exception: - b _unhandled_exception - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC563Mxx/intc.h b/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC563Mxx/intc.h deleted file mode 100644 index fc37ab2b40..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC563Mxx/intc.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SPC563Mxx/intc.h - * @brief SPC563Mxx INTC module header. - * - * @addtogroup INTC - * @{ - */ - -#ifndef _INTC_H_ -#define _INTC_H_ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @name INTC addresses - * @{ - */ -#define INTC_BASE 0xFFF48000 -#define INTC_IACKR_ADDR (INTC_BASE + 0x10) -#define INTC_EOIR_ADDR (INTC_BASE + 0x18) -/** @} */ - -/** - * @brief INTC priority levels. - */ -#define INTC_PRIORITY_LEVELS 16U - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @name INTC-related macros - * @{ - */ -#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0))) -#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t))))) -#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t))))) -#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t))))) -#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t))))) -/** @} */ - -/** - * @brief Core selection macros for PSR register. - */ -#define INTC_PSR_CORE0 0x00 - -/** - * @brief PSR register content helper - */ -#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -#endif /* _INTC_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC563Mxx/ppcparams.h b/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC563Mxx/ppcparams.h deleted file mode 100644 index 226a53cc64..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC563Mxx/ppcparams.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SPC563Mxx/ppcparams.h - * @brief PowerPC parameters for the SPC563Mxx. - * - * @defgroup PPC_SPC563Mxx SPC563Mxx Specific Parameters - * @ingroup PPC_SPECIFIC - * @details This file contains the PowerPC specific parameters for the - * SPC563Mxx platform. - * @{ - */ - -#ifndef _PPCPARAMS_H_ -#define _PPCPARAMS_H_ - -/** - * @brief Family identification macro. - */ -#define PPC_SPC563Mxx - -/** - * @brief PPC core model. - */ -#define PPC_VARIANT PPC_VARIANT_e200z3 - -/** - * @brief Number of cores. - */ -#define PPC_CORE_NUMBER 1 - -/** - * @brief Number of writable bits in IVPR register. - */ -#define PPC_IVPR_BITS 16 - -/** - * @brief IVORx registers support. - */ -#define PPC_SUPPORTS_IVORS TRUE - -/** - * @brief Book E instruction set support. - */ -#define PPC_SUPPORTS_BOOKE TRUE - -/** - * @brief VLE instruction set support. - */ -#define PPC_SUPPORTS_VLE TRUE - -/** - * @brief Supports VLS Load/Store Multiple Volatile instructions. - */ -#define PPC_SUPPORTS_VLE_MULTI TRUE - -/** - * @brief Supports the decrementer timer. - */ -#define PPC_SUPPORTS_DECREMENTER TRUE - -/** - * @brief Number of interrupt sources. - */ -#define PPC_NUM_VECTORS 360 - -#endif /* _PPCPARAMS_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC564Axx/boot.h b/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC564Axx/boot.h deleted file mode 100644 index 2f4aca4dab..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC564Axx/boot.h +++ /dev/null @@ -1,242 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file boot.h - * @brief Boot parameters for the SPC564Axx. - * @{ - */ - -#ifndef _BOOT_H_ -#define _BOOT_H_ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @name MASx registers definitions - * @{ - */ -#define MAS0_TBLMAS_TBL 0x10000000 -#define MAS0_ESEL_MASK 0x000F0000 -#define MAS0_ESEL(n) ((n) << 16) - -#define MAS1_VALID 0x80000000 -#define MAS1_IPROT 0x40000000 -#define MAS1_TID_MASK 0x00FF0000 -#define MAS1_TS 0x00001000 -#define MAS1_TSISE_MASK 0x00000F80 -#define MAS1_TSISE_1K 0x00000000 -#define MAS1_TSISE_2K 0x00000080 -#define MAS1_TSISE_4K 0x00000100 -#define MAS1_TSISE_8K 0x00000180 -#define MAS1_TSISE_16K 0x00000200 -#define MAS1_TSISE_32K 0x00000280 -#define MAS1_TSISE_64K 0x00000300 -#define MAS1_TSISE_128K 0x00000380 -#define MAS1_TSISE_256K 0x00000400 -#define MAS1_TSISE_512K 0x00000480 -#define MAS1_TSISE_1M 0x00000500 -#define MAS1_TSISE_2M 0x00000580 -#define MAS1_TSISE_4M 0x00000600 -#define MAS1_TSISE_8M 0x00000680 -#define MAS1_TSISE_16M 0x00000700 -#define MAS1_TSISE_32M 0x00000780 -#define MAS1_TSISE_64M 0x00000800 -#define MAS1_TSISE_128M 0x00000880 -#define MAS1_TSISE_256M 0x00000900 -#define MAS1_TSISE_512M 0x00000980 -#define MAS1_TSISE_1G 0x00000A00 -#define MAS1_TSISE_2G 0x00000A80 -#define MAS1_TSISE_4G 0x00000B00 - -#define MAS2_EPN_MASK 0xFFFFFC00 -#define MAS2_EPN(n) ((n) & MAS2_EPN_MASK) -#define MAS2_EBOOK 0x00000000 -#define MAS2_VLE 0x00000020 -#define MAS2_W 0x00000010 -#define MAS2_I 0x00000008 -#define MAS2_M 0x00000004 -#define MAS2_G 0x00000002 -#define MAS2_E 0x00000001 - -#define MAS3_RPN_MASK 0xFFFFFC00 -#define MAS3_RPN(n) ((n) & MAS3_RPN_MASK) -#define MAS3_U0 0x00000200 -#define MAS3_U1 0x00000100 -#define MAS3_U2 0x00000080 -#define MAS3_U3 0x00000040 -#define MAS3_UX 0x00000020 -#define MAS3_SX 0x00000010 -#define MAS3_UW 0x00000008 -#define MAS3_SW 0x00000004 -#define MAS3_UR 0x00000002 -#define MAS3_SR 0x00000001 -/** @} */ - -/** - * @name BUCSR registers definitions - * @{ - */ -#define BUCSR_BPEN 0x00000001 -#define BUCSR_BPRED_MASK 0x00000006 -#define BUCSR_BPRED_0 0x00000000 -#define BUCSR_BPRED_1 0x00000002 -#define BUCSR_BPRED_2 0x00000004 -#define BUCSR_BPRED_3 0x00000006 -#define BUCSR_BALLOC_MASK 0x00000030 -#define BUCSR_BALLOC_0 0x00000000 -#define BUCSR_BALLOC_1 0x00000010 -#define BUCSR_BALLOC_2 0x00000020 -#define BUCSR_BALLOC_3 0x00000030 -#define BUCSR_BALLOC_BFI 0x00000200 -/** @} */ - -/** - * @name LICSR1 registers definitions - * @{ - */ -#define LICSR1_ICE 0x00000001 -#define LICSR1_ICINV 0x00000002 -#define LICSR1_ICORG 0x00000010 -/** @} */ - -/** - * @name MSR register definitions - * @{ - */ -#define MSR_UCLE 0x04000000 -#define MSR_SPE 0x02000000 -#define MSR_WE 0x00040000 -#define MSR_CE 0x00020000 -#define MSR_EE 0x00008000 -#define MSR_PR 0x00004000 -#define MSR_FP 0x00002000 -#define MSR_ME 0x00001000 -#define MSR_FE0 0x00000800 -#define MSR_DE 0x00000200 -#define MSR_FE1 0x00000100 -#define MSR_IS 0x00000020 -#define MSR_DS 0x00000010 -#define MSR_RI 0x00000002 -/** @} */ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/* - * TLB default settings. - */ -#define TLB0_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(0)) -#define TLB0_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_256K) -#define TLB0_MAS2 (MAS2_EPN(0x40000000) | MAS2_VLE) -#define TLB0_MAS3 (MAS3_RPN(0x40000000) | \ - MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \ - MAS3_UR | MAS3_SR) - -#define TLB1_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(1)) -#define TLB1_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_4M) -#define TLB1_MAS2 (MAS2_EPN(0x00000000) | MAS2_VLE) -#define TLB1_MAS3 (MAS3_RPN(0x00000000) | \ - MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \ - MAS3_UR | MAS3_SR) - -#define TLB2_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(2)) -#define TLB2_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M) -#define TLB2_MAS2 (MAS2_EPN(0xC3F00000) | MAS2_I) -#define TLB2_MAS3 (MAS3_RPN(0xC3F00000) | \ - MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR) - -#define TLB3_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(3)) -#define TLB3_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M) -#define TLB3_MAS2 (MAS2_EPN(0xFFE00000) | MAS2_I) -#define TLB3_MAS3 (MAS3_RPN(0xFFE00000) | \ - MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR) - -#define TLB4_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(4)) -#define TLB4_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M) -#define TLB4_MAS2 (MAS2_EPN(0xFFF00000) | MAS2_I) -#define TLB4_MAS3 (MAS3_RPN(0xFFF00000) | \ - MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR) - -/* - * BUCSR default settings. - */ -#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__) -#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BPRED_0 | \ - BUCSR_BALLOC_0 | BUCSR_BALLOC_BFI) -#endif - -/* - * LICSR1 default settings. - */ -#if !defined(BOOT_LICSR1_DEFAULT) || defined(__DOXYGEN__) -#define BOOT_LICSR1_DEFAULT (LICSR1_ICE | LICSR1_ICORG) -#endif - -/* - * MSR default settings. - */ -#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__) -#define BOOT_MSR_DEFAULT (MSR_SPE | MSR_WE | MSR_CE | MSR_ME) -#endif - -/* - * Boot default settings. - */ -#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__) -#define BOOT_PERFORM_CORE_INIT 1 -#endif - -/* - * VLE mode default settings. - */ -#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__) -#define BOOT_USE_VLE 1 -#endif - -/* - * RAM relocation flag. - */ -#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__) -#define BOOT_RELOCATE_IN_RAM 0 -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -#endif /* _BOOT_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC564Axx/boot.s b/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC564Axx/boot.s deleted file mode 100644 index fa6ff62015..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC564Axx/boot.s +++ /dev/null @@ -1,353 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SPC564Axx/boot.s - * @brief SPC564Axx boot-related code. - * - * @addtogroup PPC_BOOT - * @{ - */ - -#include "boot.h" - -#if !defined(__DOXYGEN__) - - /* BAM record.*/ - .section .boot, "ax" - -#if BOOT_USE_VLE - .long 0x015A0000 -#else - .long 0x005A0000 -#endif - .long _reset_address - - .align 2 - .globl _reset_address - .type _reset_address, @function -_reset_address: -#if BOOT_PERFORM_CORE_INIT - bl _coreinit -#endif - bl _ivinit - -#if BOOT_RELOCATE_IN_RAM - /* - * Image relocation in RAM. - */ - lis %r4, __ram_reloc_start__@h - ori %r4, %r4, __ram_reloc_start__@l - lis %r5, __ram_reloc_dest__@h - ori %r5, %r5, __ram_reloc_dest__@l - lis %r6, __ram_reloc_end__@h - ori %r6, %r6, __ram_reloc_end__@l -.relloop: - cmpl cr0, %r4, %r6 - bge cr0, .relend - lwz %r7, 0(%r4) - addi %r4, %r4, 4 - stw %r7, 0(%r5) - addi %r5, %r5, 4 - b .relloop -.relend: - lis %r3, _boot_address@h - ori %r3, %r3, _boot_address@l - mtctr %r3 - bctrl -#else - b _boot_address -#endif - -#if BOOT_PERFORM_CORE_INIT - .align 2 -_ramcode: - tlbwe - isync - blr - - .align 2 -_coreinit: - /* - * Invalidating all TLBs except TLB1. - */ - lis %r3, 0 - mtspr 625, %r3 /* MAS1 */ - mtspr 626, %r3 /* MAS2 */ - mtspr 627, %r3 /* MAS3 */ - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(0))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - - /* - * TLB0 allocated to internal RAM. - */ - lis %r3, TLB0_MAS0@h - mtspr 624, %r3 /* MAS0 */ - lis %r3, TLB0_MAS1@h - ori %r3, %r3, TLB0_MAS1@l - mtspr 625, %r3 /* MAS1 */ - lis %r3, TLB0_MAS2@h - ori %r3, %r3, TLB0_MAS2@l - mtspr 626, %r3 /* MAS2 */ - lis %r3, TLB0_MAS3@h - ori %r3, %r3, TLB0_MAS3@l - mtspr 627, %r3 /* MAS3 */ - tlbwe - - /* - * TLB2 allocated to internal Peripherals Bridge A. - */ - lis %r3, TLB2_MAS0@h - mtspr 624, %r3 /* MAS0 */ - lis %r3, TLB2_MAS1@h - ori %r3, %r3, TLB2_MAS1@l - mtspr 625, %r3 /* MAS1 */ - lis %r3, TLB2_MAS2@h - ori %r3, %r3, TLB2_MAS2@l - mtspr 626, %r3 /* MAS2 */ - lis %r3, TLB2_MAS3@h - ori %r3, %r3, TLB2_MAS3@l - mtspr 627, %r3 /* MAS3 */ - tlbwe - - /* - * TLB3 allocated to internal Peripherals Bridge B. - */ - lis %r3, TLB3_MAS0@h - mtspr 624, %r3 /* MAS0 */ - lis %r3, TLB3_MAS1@h - ori %r3, %r3, TLB3_MAS1@l - mtspr 625, %r3 /* MAS1 */ - lis %r3, TLB3_MAS2@h - ori %r3, %r3, TLB3_MAS2@l - mtspr 626, %r3 /* MAS2 */ - lis %r3, TLB3_MAS3@h - ori %r3, %r3, TLB3_MAS3@l - mtspr 627, %r3 /* MAS3 */ - tlbwe - - /* - * TLB4 allocated to on-platform peripherals. - */ - lis %r3, TLB4_MAS0@h - mtspr 624, %r3 /* MAS0 */ - lis %r3, TLB4_MAS1@h - ori %r3, %r3, TLB4_MAS1@l - mtspr 625, %r3 /* MAS1 */ - lis %r3, TLB4_MAS2@h - ori %r3, %r3, TLB4_MAS2@l - mtspr 626, %r3 /* MAS2 */ - lis %r3, TLB4_MAS3@h - ori %r3, %r3, TLB4_MAS3@l - mtspr 627, %r3 /* MAS3 */ - tlbwe - - /* - * RAM clearing, this device requires a write to all RAM location in - * order to initialize the ECC detection hardware, this is going to - * slow down the startup but there is no way around. - */ - xor %r0, %r0, %r0 - xor %r1, %r1, %r1 - xor %r2, %r2, %r2 - xor %r3, %r3, %r3 - xor %r4, %r4, %r4 - xor %r5, %r5, %r5 - xor %r6, %r6, %r6 - xor %r7, %r7, %r7 - xor %r8, %r8, %r8 - xor %r9, %r9, %r9 - xor %r10, %r10, %r10 - xor %r11, %r11, %r11 - xor %r12, %r12, %r12 - xor %r13, %r13, %r13 - xor %r14, %r14, %r14 - xor %r15, %r15, %r15 - xor %r16, %r16, %r16 - xor %r17, %r17, %r17 - xor %r18, %r18, %r18 - xor %r19, %r19, %r19 - xor %r20, %r20, %r20 - xor %r21, %r21, %r21 - xor %r22, %r22, %r22 - xor %r23, %r23, %r23 - xor %r24, %r24, %r24 - xor %r25, %r25, %r25 - xor %r26, %r26, %r26 - xor %r27, %r27, %r27 - xor %r28, %r28, %r28 - xor %r29, %r29, %r29 - xor %r30, %r30, %r30 - xor %r31, %r31, %r31 - lis %r4, __ram_start__@h - ori %r4, %r4, __ram_start__@l - lis %r5, __ram_end__@h - ori %r5, %r5, __ram_end__@l -.cleareccloop: - cmpl %cr0, %r4, %r5 - bge %cr0, .cleareccend - stmw %r16, 0(%r4) - addi %r4, %r4, 64 - b .cleareccloop -.cleareccend: - - /* - * *Finally* the TLB1 is re-allocated to flash, note, the final phase - * is executed from RAM. - */ - lis %r3, TLB1_MAS0@h - mtspr 624, %r3 /* MAS0 */ - lis %r3, TLB1_MAS1@h - ori %r3, %r3, TLB1_MAS1@l - mtspr 625, %r3 /* MAS1 */ - lis %r3, TLB1_MAS2@h - ori %r3, %r3, TLB1_MAS2@l - mtspr 626, %r3 /* MAS2 */ - lis %r3, TLB1_MAS3@h - ori %r3, %r3, TLB1_MAS3@l - mtspr 627, %r3 /* MAS3 */ - mflr %r4 - lis %r6, _ramcode@h - ori %r6, %r6, _ramcode@l - lis %r7, 0x40010000@h - mtctr %r7 - lwz %r3, 0(%r6) - stw %r3, 0(%r7) - lwz %r3, 4(%r6) - stw %r3, 4(%r7) - lwz %r3, 8(%r6) - stw %r3, 8(%r7) - bctrl - mtlr %r4 - - /* - * Branch prediction enabled. - */ - li %r3, BOOT_BUCSR_DEFAULT - mtspr 1013, %r3 /* BUCSR */ - - /* - * Cache invalidated and then enabled. - */ - li %r3, LICSR1_ICINV - mtspr 1011, %r3 /* LICSR1 */ -.inv: mfspr %r3, 1011 /* LICSR1 */ - andi. %r3, %r3, LICSR1_ICINV - bne .inv - lis %r3, BOOT_LICSR1_DEFAULT@h - ori %r3, %r3, BOOT_LICSR1_DEFAULT@l - mtspr 1011, %r3 /* LICSR1 */ - - blr -#endif /* BOOT_PERFORM_CORE_INIT */ - - /* - * Exception vectors initialization. - */ - .align 2 -_ivinit: - /* MSR initialization.*/ - lis %r3, BOOT_MSR_DEFAULT@h - ori %r3, %r3, BOOT_MSR_DEFAULT@l - mtMSR %r3 - - /* IVPR initialization.*/ - lis %r3, __ivpr_base__@h - ori %r3, %r3, __ivpr_base__@l - mtIVPR %r3 - - /* IVORs initialization.*/ - lis %r3, _unhandled_exception@h - ori %r3, %r3, _unhandled_exception@l - - mtspr 400, %r3 /* IVOR0-15 */ - mtspr 401, %r3 - mtspr 402, %r3 - mtspr 403, %r3 - mtspr 404, %r3 - mtspr 405, %r3 - mtspr 406, %r3 - mtspr 407, %r3 - mtspr 408, %r3 - mtspr 409, %r3 - mtspr 410, %r3 - mtspr 411, %r3 - mtspr 412, %r3 - mtspr 413, %r3 - mtspr 414, %r3 - mtspr 415, %r3 - mtspr 528, %r3 /* IVOR32-34 */ - mtspr 529, %r3 - mtspr 530, %r3 - - blr - - .section .handlers, "ax" - - /* - * Unhandled exceptions handler. - */ - .weak _unhandled_exception - .type _unhandled_exception, @function -_unhandled_exception: - b _unhandled_exception - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC564Axx/intc.h b/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC564Axx/intc.h deleted file mode 100644 index fc52a96996..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC564Axx/intc.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SPC564Axx/intc.h - * @brief SPC564Axx INTC module header. - * - * @addtogroup INTC - * @{ - */ - -#ifndef _INTC_H_ -#define _INTC_H_ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @name INTC addresses - * @{ - */ -#define INTC_BASE 0xFFF48000 -#define INTC_IACKR_ADDR (INTC_BASE + 0x10) -#define INTC_EOIR_ADDR (INTC_BASE + 0x18) -/** @} */ - -/** - * @brief INTC priority levels. - */ -#define INTC_PRIORITY_LEVELS 16U - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @name INTC-related macros - * @{ - */ -#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0))) -#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t))))) -#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t))))) -#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t))))) -#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t))))) -/** @} */ - -/** - * @brief Core selection macros for PSR register. - */ -#define INTC_PSR_CORE0 0x00 - -/** - * @brief PSR register content helper - */ -#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -#endif /* _INTC_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC564Axx/ppcparams.h b/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC564Axx/ppcparams.h deleted file mode 100644 index 28cdf25110..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC564Axx/ppcparams.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SPC564Axx/ppcparams.h - * @brief PowerPC parameters for the SPC564Axx. - * - * @defgroup PPC_SPC564Axx SPC564Axx Specific Parameters - * @ingroup PPC_SPECIFIC - * @details This file contains the PowerPC specific parameters for the - * SPC564Axx platform. - * @{ - */ - -#ifndef _PPCPARAMS_H_ -#define _PPCPARAMS_H_ - -/** - * @brief Family identification macro. - */ -#define PPC_SPC564Axx - -/** - * @brief PPC core model. - */ -#define PPC_VARIANT PPC_VARIANT_e200z4 - -/** - * @brief Number of cores. - */ -#define PPC_CORE_NUMBER 1 - -/** - * @brief Number of writable bits in IVPR register. - */ -#define PPC_IVPR_BITS 16 - -/** - * @brief IVORx registers support. - */ -#define PPC_SUPPORTS_IVORS TRUE - -/** - * @brief Book E instruction set support. - */ -#define PPC_SUPPORTS_BOOKE TRUE - -/** - * @brief VLE instruction set support. - */ -#define PPC_SUPPORTS_VLE TRUE - -/** - * @brief Supports VLS Load/Store Multiple Volatile instructions. - */ -#define PPC_SUPPORTS_VLE_MULTI TRUE - -/** - * @brief Supports the decrementer timer. - */ -#define PPC_SUPPORTS_DECREMENTER TRUE - -/** - * @brief Number of interrupt sources. - */ -#define PPC_NUM_VECTORS 486 - -#endif /* _PPCPARAMS_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC56ECxx/boot.h b/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC56ECxx/boot.h deleted file mode 100644 index 3b4c4bb71b..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC56ECxx/boot.h +++ /dev/null @@ -1,248 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file boot.h - * @brief Boot parameters for the SPC56ECxx. - * @{ - */ - -#ifndef _BOOT_H_ -#define _BOOT_H_ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @name MASx registers definitions - * @{ - */ -#define MAS0_TBLMAS_TBL 0x10000000 -#define MAS0_ESEL_MASK 0x000F0000 -#define MAS0_ESEL(n) ((n) << 16) - -#define MAS1_VALID 0x80000000 -#define MAS1_IPROT 0x40000000 -#define MAS1_TID_MASK 0x00FF0000 -#define MAS1_TS 0x00001000 -#define MAS1_TSISE_MASK 0x00000F80 -#define MAS1_TSISE_1K 0x00000000 -#define MAS1_TSISE_2K 0x00000080 -#define MAS1_TSISE_4K 0x00000100 -#define MAS1_TSISE_8K 0x00000180 -#define MAS1_TSISE_16K 0x00000200 -#define MAS1_TSISE_32K 0x00000280 -#define MAS1_TSISE_64K 0x00000300 -#define MAS1_TSISE_128K 0x00000380 -#define MAS1_TSISE_256K 0x00000400 -#define MAS1_TSISE_512K 0x00000480 -#define MAS1_TSISE_1M 0x00000500 -#define MAS1_TSISE_2M 0x00000580 -#define MAS1_TSISE_4M 0x00000600 -#define MAS1_TSISE_8M 0x00000680 -#define MAS1_TSISE_16M 0x00000700 -#define MAS1_TSISE_32M 0x00000780 -#define MAS1_TSISE_64M 0x00000800 -#define MAS1_TSISE_128M 0x00000880 -#define MAS1_TSISE_256M 0x00000900 -#define MAS1_TSISE_512M 0x00000980 -#define MAS1_TSISE_1G 0x00000A00 -#define MAS1_TSISE_2G 0x00000A80 -#define MAS1_TSISE_4G 0x00000B00 - -#define MAS2_EPN_MASK 0xFFFFFC00 -#define MAS2_EPN(n) ((n) & MAS2_EPN_MASK) -#define MAS2_EBOOK 0x00000000 -#define MAS2_VLE 0x00000020 -#define MAS2_W 0x00000010 -#define MAS2_I 0x00000008 -#define MAS2_M 0x00000004 -#define MAS2_G 0x00000002 -#define MAS2_E 0x00000001 - -#define MAS3_RPN_MASK 0xFFFFFC00 -#define MAS3_RPN(n) ((n) & MAS3_RPN_MASK) -#define MAS3_U0 0x00000200 -#define MAS3_U1 0x00000100 -#define MAS3_U2 0x00000080 -#define MAS3_U3 0x00000040 -#define MAS3_UX 0x00000020 -#define MAS3_SX 0x00000010 -#define MAS3_UW 0x00000008 -#define MAS3_SW 0x00000004 -#define MAS3_UR 0x00000002 -#define MAS3_SR 0x00000001 -/** @} */ - -/** - * @name BUCSR registers definitions - * @{ - */ -#define BUCSR_BPEN 0x00000001 -#define BUCSR_BPRED_MASK 0x00000006 -#define BUCSR_BPRED_0 0x00000000 -#define BUCSR_BPRED_1 0x00000002 -#define BUCSR_BPRED_2 0x00000004 -#define BUCSR_BPRED_3 0x00000006 -#define BUCSR_BALLOC_MASK 0x00000030 -#define BUCSR_BALLOC_0 0x00000000 -#define BUCSR_BALLOC_1 0x00000010 -#define BUCSR_BALLOC_2 0x00000020 -#define BUCSR_BALLOC_3 0x00000030 -#define BUCSR_BALLOC_BFI 0x00000200 -/** @} */ - -/** - * @name LICSR1 registers definitions - * @{ - */ -#define LICSR1_ICE 0x00000001 -#define LICSR1_ICINV 0x00000002 -#define LICSR1_ICORG 0x00000010 -/** @} */ - -/** - * @name MSR register definitions - * @{ - */ -#define MSR_UCLE 0x04000000 -#define MSR_SPE 0x02000000 -#define MSR_WE 0x00040000 -#define MSR_CE 0x00020000 -#define MSR_EE 0x00008000 -#define MSR_PR 0x00004000 -#define MSR_FP 0x00002000 -#define MSR_ME 0x00001000 -#define MSR_FE0 0x00000800 -#define MSR_DE 0x00000200 -#define MSR_FE1 0x00000100 -#define MSR_IS 0x00000020 -#define MSR_DS 0x00000010 -#define MSR_RI 0x00000002 -/** @} */ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/* - * TLB default settings. - */ -#define TLB0_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(0)) -#define TLB0_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_4M) -#define TLB0_MAS2 (MAS2_EPN(0x00000000) | MAS2_VLE) -#define TLB0_MAS3 (MAS3_RPN(0x00000000) | \ - MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \ - MAS3_UR | MAS3_SR) - -#define TLB1_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(1)) -#define TLB1_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_256K) -#define TLB1_MAS2 (MAS2_EPN(0x40000000) | MAS2_VLE) -#define TLB1_MAS3 (MAS3_RPN(0x40000000) | \ - MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \ - MAS3_UR | MAS3_SR) - -#define TLB2_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(2)) -#define TLB2_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M) -#define TLB2_MAS2 (MAS2_EPN(0xC3F00000) | MAS2_I) -#define TLB2_MAS3 (MAS3_RPN(0xC3F00000) | \ - MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR) - -#define TLB3_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(3)) -#define TLB3_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M) -#define TLB3_MAS2 (MAS2_EPN(0xFFE00000) | MAS2_I) -#define TLB3_MAS3 (MAS3_RPN(0xFFE00000) | \ - MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR) - -#define TLB4_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(4)) -#define TLB4_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M) -#define TLB4_MAS2 (MAS2_EPN(0x8FF00000) | MAS2_I) -#define TLB4_MAS3 (MAS3_RPN(0x8FF00000) | \ - MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR) - -#define TLB5_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(5)) -#define TLB5_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M) -#define TLB5_MAS2 (MAS2_EPN(0xFFF00000) | MAS2_I) -#define TLB5_MAS3 (MAS3_RPN(0xFFF00000) | \ - MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR) - -/* - * BUCSR default settings. - */ -#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__) -#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BPRED_0 | \ - BUCSR_BALLOC_0 | BUCSR_BALLOC_BFI) -#endif - -/* - * LICSR1 default settings. - */ -#if !defined(BOOT_LICSR1_DEFAULT) || defined(__DOXYGEN__) -#define BOOT_LICSR1_DEFAULT (LICSR1_ICE | LICSR1_ICORG) -#endif - -/* - * MSR default settings. - */ -#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__) -#define BOOT_MSR_DEFAULT (MSR_SPE | MSR_WE | MSR_CE | MSR_ME) -#endif - -/* - * Boot default settings. - */ -#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__) -#define BOOT_PERFORM_CORE_INIT 1 -#endif - -/* - * VLE mode default settings. - */ -#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__) -#define BOOT_USE_VLE 1 -#endif - -/* - * RAM relocation flag. - */ -#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__) -#define BOOT_RELOCATE_IN_RAM 0 -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -#endif /* _BOOT_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC56ECxx/boot.s b/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC56ECxx/boot.s deleted file mode 100644 index 5e59bb80b1..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC56ECxx/boot.s +++ /dev/null @@ -1,403 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SPC56ECxx/boot.s - * @brief SPC56ECxx boot-related code. - * - * @addtogroup PPC_BOOT - * @{ - */ - -#include "boot.h" - -#if !defined(__DOXYGEN__) - - /* BAM record.*/ - .section .boot, "ax" - -#if BOOT_USE_VLE - .long 0x015A0000 -#else - .long 0x005A0000 -#endif - .long _reset_address - - .align 2 - .globl _reset_address - .type _reset_address, @function -_reset_address: -#if BOOT_PERFORM_CORE_INIT - bl _coreinit -#endif - bl _ivinit - -#if BOOT_RELOCATE_IN_RAM - /* - * Image relocation in RAM. - */ - lis %r4, __ram_reloc_start__@h - ori %r4, %r4, __ram_reloc_start__@l - lis %r5, __ram_reloc_dest__@h - ori %r5, %r5, __ram_reloc_dest__@l - lis %r6, __ram_reloc_end__@h - ori %r6, %r6, __ram_reloc_end__@l -.relloop: - cmpl cr0, %r4, %r6 - bge cr0, .relend - lwz %r7, 0(%r4) - addi %r4, %r4, 4 - stw %r7, 0(%r5) - addi %r5, %r5, 4 - b .relloop -.relend: - lis %r3, _boot_address@h - ori %r3, %r3, _boot_address@l - mtctr %r3 - bctrl -#else - b _boot_address -#endif - -#if BOOT_PERFORM_CORE_INIT - .align 2 -_ramcode: - tlbwe - isync - blr - - .align 2 -_coreinit: - /* - * Invalidating all TLBs except TLB0. - */ - lis %r3, 0 - mtspr 625, %r3 /* MAS1 */ - mtspr 626, %r3 /* MAS2 */ - mtspr 627, %r3 /* MAS3 */ - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(1))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - - /* - * TLB1 allocated to internal RAM. - */ - lis %r3, TLB1_MAS0@h - mtspr 624, %r3 /* MAS0 */ - lis %r3, TLB1_MAS1@h - ori %r3, %r3, TLB1_MAS1@l - mtspr 625, %r3 /* MAS1 */ - lis %r3, TLB1_MAS2@h - ori %r3, %r3, TLB1_MAS2@l - mtspr 626, %r3 /* MAS2 */ - lis %r3, TLB1_MAS3@h - ori %r3, %r3, TLB1_MAS3@l - mtspr 627, %r3 /* MAS3 */ - tlbwe - - /* - * TLB2 allocated to internal Peripherals Bridge A. - */ - lis %r3, TLB2_MAS0@h - mtspr 624, %r3 /* MAS0 */ - lis %r3, TLB2_MAS1@h - ori %r3, %r3, TLB2_MAS1@l - mtspr 625, %r3 /* MAS1 */ - lis %r3, TLB2_MAS2@h - ori %r3, %r3, TLB2_MAS2@l - mtspr 626, %r3 /* MAS2 */ - lis %r3, TLB2_MAS3@h - ori %r3, %r3, TLB2_MAS3@l - mtspr 627, %r3 /* MAS3 */ - tlbwe - - /* - * TLB3 allocated to internal Peripherals Bridge B. - */ - lis %r3, TLB3_MAS0@h - mtspr 624, %r3 /* MAS0 */ - lis %r3, TLB3_MAS1@h - ori %r3, %r3, TLB3_MAS1@l - mtspr 625, %r3 /* MAS1 */ - lis %r3, TLB3_MAS2@h - ori %r3, %r3, TLB3_MAS2@l - mtspr 626, %r3 /* MAS2 */ - lis %r3, TLB3_MAS3@h - ori %r3, %r3, TLB3_MAS3@l - mtspr 627, %r3 /* MAS3 */ - tlbwe - - /* - * TLB4 allocated to on-platform peripherals. - */ - lis %r3, TLB4_MAS0@h - mtspr 624, %r3 /* MAS0 */ - lis %r3, TLB4_MAS1@h - ori %r3, %r3, TLB4_MAS1@l - mtspr 625, %r3 /* MAS1 */ - lis %r3, TLB4_MAS2@h - ori %r3, %r3, TLB4_MAS2@l - mtspr 626, %r3 /* MAS2 */ - lis %r3, TLB4_MAS3@h - ori %r3, %r3, TLB4_MAS3@l - mtspr 627, %r3 /* MAS3 */ - tlbwe - - /* - * TLB5 allocated to on-platform peripherals. - */ - lis %r3, TLB5_MAS0@h - mtspr 624, %r3 /* MAS0 */ - lis %r3, TLB5_MAS1@h - ori %r3, %r3, TLB5_MAS1@l - mtspr 625, %r3 /* MAS1 */ - lis %r3, TLB5_MAS2@h - ori %r3, %r3, TLB5_MAS2@l - mtspr 626, %r3 /* MAS2 */ - lis %r3, TLB5_MAS3@h - ori %r3, %r3, TLB5_MAS3@l - mtspr 627, %r3 /* MAS3 */ - tlbwe - - /* - * RAM clearing, this device requires a write to all RAM location in - * order to initialize the ECC detection hardware, this is going to - * slow down the startup but there is no way around. - */ - xor %r0, %r0, %r0 - xor %r1, %r1, %r1 - xor %r2, %r2, %r2 - xor %r3, %r3, %r3 - xor %r4, %r4, %r4 - xor %r5, %r5, %r5 - xor %r6, %r6, %r6 - xor %r7, %r7, %r7 - xor %r8, %r8, %r8 - xor %r9, %r9, %r9 - xor %r10, %r10, %r10 - xor %r11, %r11, %r11 - xor %r12, %r12, %r12 - xor %r13, %r13, %r13 - xor %r14, %r14, %r14 - xor %r15, %r15, %r15 - xor %r16, %r16, %r16 - xor %r17, %r17, %r17 - xor %r18, %r18, %r18 - xor %r19, %r19, %r19 - xor %r20, %r20, %r20 - xor %r21, %r21, %r21 - xor %r22, %r22, %r22 - xor %r23, %r23, %r23 - xor %r24, %r24, %r24 - xor %r25, %r25, %r25 - xor %r26, %r26, %r26 - xor %r27, %r27, %r27 - xor %r28, %r28, %r28 - xor %r29, %r29, %r29 - xor %r30, %r30, %r30 - xor %r31, %r31, %r31 - lis %r4, __ram_start__@h - ori %r4, %r4, __ram_start__@l - lis %r5, __ram_end__@h - ori %r5, %r5, __ram_end__@l -.cleareccloop: - cmpl %cr0, %r4, %r5 - bge %cr0, .cleareccend - stmw %r16, 0(%r4) - addi %r4, %r4, 64 - b .cleareccloop -.cleareccend: - - /* - * Special function registers clearing, required in order to avoid - * possible problems with lockstep mode. - */ - mtcrf 0xFF, %r31 - mtspr 9, %r31 /* CTR */ - mtspr 22, %r31 /* DEC */ - mtspr 26, %r31 /* SRR0-1 */ - mtspr 27, %r31 - mtspr 54, %r31 /* DECAR */ - mtspr 58, %r31 /* CSRR0-1 */ - mtspr 59, %r31 - mtspr 61, %r31 /* DEAR */ - mtspr 256, %r31 /* USPRG0 */ - mtspr 272, %r31 /* SPRG1-7 */ - mtspr 273, %r31 - mtspr 274, %r31 - mtspr 275, %r31 - mtspr 276, %r31 - mtspr 277, %r31 - mtspr 278, %r31 - mtspr 279, %r31 - mtspr 285, %r31 /* TBU */ - mtspr 284, %r31 /* TBL */ -#if 0 - mtspr 318, %r31 /* DVC1-2 */ - mtspr 319, %r31 -#endif - mtspr 562, %r31 /* DBCNT */ - mtspr 570, %r31 /* MCSRR0 */ - mtspr 571, %r31 /* MCSRR1 */ - mtspr 604, %r31 /* SPRG8-9 */ - mtspr 605, %r31 - - /* - * *Finally* the TLB0 is re-allocated to flash, note, the final phase - * is executed from RAM. - */ - lis %r3, TLB0_MAS0@h - mtspr 624, %r3 /* MAS0 */ - lis %r3, TLB0_MAS1@h - ori %r3, %r3, TLB0_MAS1@l - mtspr 625, %r3 /* MAS1 */ - lis %r3, TLB0_MAS2@h - ori %r3, %r3, TLB0_MAS2@l - mtspr 626, %r3 /* MAS2 */ - lis %r3, TLB0_MAS3@h - ori %r3, %r3, TLB0_MAS3@l - mtspr 627, %r3 /* MAS3 */ - mflr %r4 - lis %r6, _ramcode@h - ori %r6, %r6, _ramcode@l - lis %r7, 0x40010000@h - mtctr %r7 - lwz %r3, 0(%r6) - stw %r3, 0(%r7) - lwz %r3, 4(%r6) - stw %r3, 4(%r7) - lwz %r3, 8(%r6) - stw %r3, 8(%r7) - bctrl - mtlr %r4 - - /* - * Branch prediction enabled. - */ - li %r3, BOOT_BUCSR_DEFAULT - mtspr 1013, %r3 /* BUCSR */ - - /* - * Cache invalidated and then enabled. - */ - li %r3, LICSR1_ICINV - mtspr 1011, %r3 /* LICSR1 */ -.inv: mfspr %r3, 1011 /* LICSR1 */ - andi. %r3, %r3, LICSR1_ICINV - bne .inv - lis %r3, BOOT_LICSR1_DEFAULT@h - ori %r3, %r3, BOOT_LICSR1_DEFAULT@l - mtspr 1011, %r3 /* LICSR1 */ - - blr -#endif /* BOOT_PERFORM_CORE_INIT */ - - /* - * Exception vectors initialization. - */ - .align 2 -_ivinit: - /* MSR initialization.*/ - lis %r3, BOOT_MSR_DEFAULT@h - ori %r3, %r3, BOOT_MSR_DEFAULT@l - mtMSR %r3 - - /* IVPR initialization.*/ - lis %r3, __ivpr_base__@h - ori %r3, %r3, __ivpr_base__@l - mtIVPR %r3 - - /* IVORs initialization.*/ - lis %r3, _unhandled_exception@h - ori %r3, %r3, _unhandled_exception@l - - mtspr 400, %r3 /* IVOR0-15 */ - mtspr 401, %r3 - mtspr 402, %r3 - mtspr 403, %r3 - mtspr 404, %r3 - mtspr 405, %r3 - mtspr 406, %r3 - mtspr 407, %r3 - mtspr 408, %r3 - mtspr 409, %r3 - mtspr 410, %r3 - mtspr 411, %r3 - mtspr 412, %r3 - mtspr 413, %r3 - mtspr 414, %r3 - mtspr 415, %r3 - mtspr 528, %r3 /* IVOR32-34 */ - mtspr 529, %r3 - mtspr 530, %r3 - - blr - - .section .handlers, "ax" - - /* - * Unhandled exceptions handler. - */ - .weak _unhandled_exception - .type _unhandled_exception, @function -_unhandled_exception: - b _unhandled_exception - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC56ECxx/boot_cw.s b/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC56ECxx/boot_cw.s deleted file mode 100644 index ec0ffdb0f0..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC56ECxx/boot_cw.s +++ /dev/null @@ -1,400 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SPC56ECxx/boot.s - * @brief SPC56ECxx boot-related code. - * - * @addtogroup PPC_BOOT - * @{ - */ - -#include "boot.h" - -#if !defined(__DOXYGEN__) - - .extern _boot_address - .extern __ram_start__ - .extern __ram_end__ - .extern __ivpr_base__ - - .extern _unhandled_exception - - /* BAM record.*/ - .section .boot, 16 - -#if BOOT_USE_VLE - .long 0x015A0000 -#else - .long 0x005A0000 -#endif - .long _reset_address - - .align 4 - .globl _reset_address - .type _reset_address, @function -_reset_address: -#if BOOT_PERFORM_CORE_INIT - e_bl _coreinit -#endif - e_bl _ivinit - -#if BOOT_RELOCATE_IN_RAM - /* - * Image relocation in RAM. - */ - e_lis r4, __ram_reloc_start__@h - e_or2i r4, r4, __ram_reloc_start__@l - e_lis r5, __ram_reloc_dest__@h - e_or2i r5, r5, __ram_reloc_dest__@l - e_lis r6, __ram_reloc_end__@h - e_or2i r6, r6, __ram_reloc_end__@l -.relloop: - se_cmpl r4, r6 - se_bge .relend - se_lwz r7, 0(r4) - se_addi r4, 4 - se_stw r7, 0(r5) - se_addi r5, 4 - se_b .relloop -.relend: - e_lis r3, _boot_address@h - e_or2i r3, _boot_address@l - mtctr r3 - se_bctrl -#else - e_b _boot_address -#endif - -#if BOOT_PERFORM_CORE_INIT - .align 4 -_ramcode: - tlbwe - se_isync - se_blr - - .align 2 -_coreinit: - /* - * Invalidating all TLBs except TLB0. - */ - e_lis r3, 0 - mtspr 625, r3 /* MAS1 */ - mtspr 626, r3 /* MAS2 */ - mtspr 627, r3 /* MAS3 */ - e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(1))@h - mtspr 624, r3 /* MAS0 */ - tlbwe - e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h - mtspr 624, r3 /* MAS0 */ - tlbwe - e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h - mtspr 624, r3 /* MAS0 */ - tlbwe - e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h - mtspr 624, r3 /* MAS0 */ - tlbwe - e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h - mtspr 624, r3 /* MAS0 */ - tlbwe - e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h - mtspr 624, r3 /* MAS0 */ - tlbwe - e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h - mtspr 624, r3 /* MAS0 */ - tlbwe - e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h - mtspr 624, r3 /* MAS0 */ - tlbwe - e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h - mtspr 624, r3 /* MAS0 */ - tlbwe - e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h - mtspr 624, r3 /* MAS0 */ - tlbwe - e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h - mtspr 624, r3 /* MAS0 */ - tlbwe - e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h - mtspr 624, r3 /* MAS0 */ - tlbwe - e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h - mtspr 624, r3 /* MAS0 */ - tlbwe - e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h - mtspr 624, r3 /* MAS0 */ - tlbwe - e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h - mtspr 624, r3 /* MAS0 */ - tlbwe - - /* - * TLB1 allocated to internal RAM. - */ - e_lis r3, TLB1_MAS0@h - mtspr 624, r3 /* MAS0 */ - e_lis r3, TLB1_MAS1@h - e_or2i r3, TLB1_MAS1@l - mtspr 625, r3 /* MAS1 */ - e_lis r3, TLB1_MAS2@h - e_or2i r3, TLB1_MAS2@l - mtspr 626, r3 /* MAS2 */ - e_lis r3, TLB1_MAS3@h - e_or2i r3, TLB1_MAS3@l - mtspr 627, r3 /* MAS3 */ - tlbwe - - /* - * TLB2 allocated to internal Peripherals Bridge A. - */ - e_lis r3, TLB2_MAS0@h - mtspr 624, r3 /* MAS0 */ - e_lis r3, TLB2_MAS1@h - e_or2i r3, TLB2_MAS1@l - mtspr 625, r3 /* MAS1 */ - e_lis r3, TLB2_MAS2@h - e_or2i r3, TLB2_MAS2@l - mtspr 626, r3 /* MAS2 */ - e_lis r3, TLB2_MAS3@h - e_or2i r3, TLB2_MAS3@l - mtspr 627, r3 /* MAS3 */ - tlbwe - - /* - * TLB3 allocated to internal Peripherals Bridge B. - */ - e_lis r3, TLB3_MAS0@h - mtspr 624, r3 /* MAS0 */ - e_lis r3, TLB3_MAS1@h - e_or2i r3, TLB3_MAS1@l - mtspr 625, r3 /* MAS1 */ - e_lis r3, TLB3_MAS2@h - e_or2i r3, TLB3_MAS2@l - mtspr 626, r3 /* MAS2 */ - e_lis r3, TLB3_MAS3@h - e_or2i r3, TLB3_MAS3@l - mtspr 627, r3 /* MAS3 */ - tlbwe - - /* - * TLB4 allocated to on-platform peripherals. - */ - e_lis r3, TLB4_MAS0@h - mtspr 624, r3 /* MAS0 */ - e_lis r3, TLB4_MAS1@h - e_or2i r3, TLB4_MAS1@l - mtspr 625, r3 /* MAS1 */ - e_lis r3, TLB4_MAS2@h - e_or2i r3, TLB4_MAS2@l - mtspr 626, r3 /* MAS2 */ - e_lis r3, TLB4_MAS3@h - e_or2i r3, TLB4_MAS3@l - mtspr 627, r3 /* MAS3 */ - tlbwe - - /* - * TLB5 allocated to on-platform peripherals. - */ - e_lis r3, TLB5_MAS0@h - mtspr 624, r3 /* MAS0 */ - e_lis r3, TLB5_MAS1@h - e_or2i r3, TLB5_MAS1@l - mtspr 625, r3 /* MAS1 */ - e_lis r3, TLB5_MAS2@h - e_or2i r3, TLB5_MAS2@l - mtspr 626, r3 /* MAS2 */ - e_lis r3, TLB5_MAS3@h - e_or2i r3, TLB5_MAS3@l - mtspr 627, r3 /* MAS3 */ - tlbwe - - /* - * RAM clearing, this device requires a write to all RAM location in - * order to initialize the ECC detection hardware, this is going to - * slow down the startup but there is no way around. - */ - xor r0, r0, r0 - xor r1, r1, r1 - xor r2, r2, r2 - xor r3, r3, r3 - xor r4, r4, r4 - xor r5, r5, r5 - xor r6, r6, r6 - xor r7, r7, r7 - xor r8, r8, r8 - xor r9, r9, r9 - xor r10, r10, r10 - xor r11, r11, r11 - xor r12, r12, r12 - xor r13, r13, r13 - xor r14, r14, r14 - xor r15, r15, r15 - xor r16, r16, r16 - xor r17, r17, r17 - xor r18, r18, r18 - xor r19, r19, r19 - xor r20, r20, r20 - xor r21, r21, r21 - xor r22, r22, r22 - xor r23, r23, r23 - xor r24, r24, r24 - xor r25, r25, r25 - xor r26, r26, r26 - xor r27, r27, r27 - xor r28, r28, r28 - xor r29, r29, r29 - xor r30, r30, r30 - xor r31, r31, r31 - e_lis r4, __ram_start__@h - e_or2i r4, __ram_start__@l - e_lis r5, __ram_end__@h - e_or2i r5, __ram_end__@l -.cleareccloop: - se_cmpl r4, r5 - se_bge .cleareccend - e_stmw r16, 0(r4) - e_addi r4, r4, 64 - se_b .cleareccloop -.cleareccend: - - /* - * Special function registers clearing, required in order to avoid - * possible problems with lockstep mode. - */ - mtcrf 0xFF, r31 - mtspr 9, r31 /* CTR */ - mtspr 22, r31 /* DEC */ - mtspr 26, r31 /* SRR0-1 */ - mtspr 27, r31 - mtspr 54, r31 /* DECAR */ - mtspr 58, r31 /* CSRR0-1 */ - mtspr 59, r31 - mtspr 61, r31 /* DEAR */ - mtspr 256, r31 /* USPRG0 */ - mtspr 272, r31 /* SPRG1-7 */ - mtspr 273, r31 - mtspr 274, r31 - mtspr 275, r31 - mtspr 276, r31 - mtspr 277, r31 - mtspr 278, r31 - mtspr 279, r31 - mtspr 285, r31 /* TBU */ - mtspr 284, r31 /* TBL */ -#if 0 - mtspr 318, r31 /* DVC1-2 */ - mtspr 319, r31 -#endif - mtspr 562, r31 /* DBCNT */ - mtspr 570, r31 /* MCSRR0 */ - mtspr 571, r31 /* MCSRR1 */ - mtspr 604, r31 /* SPRG8-9 */ - mtspr 605, r31 - - /* - * *Finally* the TLB0 is re-allocated to flash, note, the final phase - * is executed from RAM. - */ - e_lis r3, TLB0_MAS0@h - mtspr 624, r3 /* MAS0 */ - e_lis r3, TLB0_MAS1@h - e_or2i r3, TLB0_MAS1@l - mtspr 625, r3 /* MAS1 */ - e_lis r3, TLB0_MAS2@h - e_or2i r3, TLB0_MAS2@l - mtspr 626, r3 /* MAS2 */ - e_lis r3, TLB0_MAS3@h - e_or2i r3, TLB0_MAS3@l - mtspr 627, r3 /* MAS3 */ - se_mflr r4 - e_lis r6, _ramcode@h - e_or2i r6, _ramcode@l - e_lis r7, 0x40010000@h - mtctr r7 - se_lwz r3, 0(r6) - se_stw r3, 0(r7) - se_lwz r3, 4(r6) - se_stw r3, 4(r7) - se_lwz r3, 8(r6) - se_stw r3, 8(r7) - se_bctrl - mtlr r4 - - /* - * Branch prediction enabled. - */ - e_li r3, BOOT_BUCSR_DEFAULT - mtspr 1013, r3 /* BUCSR */ - - /* - * Cache invalidated and then enabled. - */ - se_li r3, LICSR1_ICINV - mtspr 1011, r3 /* LICSR1 */ -.inv: mfspr r3, 1011 /* LICSR1 */ - e_andi. r3, r3, LICSR1_ICINV - se_bne .inv - e_lis r3, BOOT_LICSR1_DEFAULT@h - e_or2i r3, BOOT_LICSR1_DEFAULT@l - mtspr 1011, r3 /* LICSR1 */ - - se_blr -#endif /* BOOT_PERFORM_CORE_INIT */ - - /* - * Exception vectors initialization. - */ - .align 4 -_ivinit: - /* MSR initialization.*/ - e_lis r3, BOOT_MSR_DEFAULT@h - e_ori r3, r3, BOOT_MSR_DEFAULT@l - mtMSR r3 - - /* IVPR initialization.*/ - e_lis r3, __ivpr_base__@h - e_or2i r3, __ivpr_base__@l - mtIVPR r3 - - /* IVORs initialization.*/ - e_lis r3, _unhandled_exception@h - e_or2i r3, _unhandled_exception@l - - mtspr 400, r3 /* IVOR0-15 */ - mtspr 401, r3 - mtspr 402, r3 - mtspr 403, r3 - mtspr 404, r3 - mtspr 405, r3 - mtspr 406, r3 - mtspr 407, r3 - mtspr 408, r3 - mtspr 409, r3 - mtspr 410, r3 - mtspr 411, r3 - mtspr 412, r3 - mtspr 413, r3 - mtspr 414, r3 - mtspr 415, r3 - mtspr 528, r3 /* IVOR32-34 */ - mtspr 529, r3 - mtspr 530, r3 - - se_blr - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC56ECxx/intc.h b/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC56ECxx/intc.h deleted file mode 100644 index 7a9c46cc2b..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC56ECxx/intc.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SPC56ECxx/intc.h - * @brief SPC56ECxx INTC module header. - * - * @addtogroup INTC - * @{ - */ - -#ifndef _INTC_H_ -#define _INTC_H_ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @name INTC addresses - * @{ - */ -#define INTC_BASE 0xFFF48000 -#define INTC_IACKR_ADDR (INTC_BASE + 0x10) -#define INTC_EOIR_ADDR (INTC_BASE + 0x18) -/** @} */ - -/** - * @brief INTC priority levels. - */ -#define INTC_PRIORITY_LEVELS 16U - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @name INTC-related macros - * @{ - */ -#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0))) -#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t))))) -#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t))))) -#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t))))) -#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t))))) -/** @} */ - -/** - * @brief Core selection macros for PSR register. - */ -#define INTC_PSR_CORE0 0x00 -#define INTC_PSR_CORE1 0xC0 -#define INTC_PSR_CORES01 0x40 - -/** - * @brief PSR register content helper - */ -#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -#endif /* _INTC_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC56ECxx/ppcparams.h b/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC56ECxx/ppcparams.h deleted file mode 100644 index ecea468c7b..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC56ECxx/ppcparams.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SPC56ECxx/ppcparams.h - * @brief PowerPC parameters for the SPC56ECxx. - * - * @defgroup PPC_SPC56ECxx SPC56ECxx Specific Parameters - * @ingroup PPC_SPECIFIC - * @details This file contains the PowerPC specific parameters for the - * SPC56ECxx platform. - * @{ - */ - -#ifndef _PPCPARAMS_H_ -#define _PPCPARAMS_H_ - -/** - * @brief Family identification macro. - */ -#define PPC_SPC56ECxx - -/** - * @brief PPC core model. - */ -#define PPC_VARIANT PPC_VARIANT_e200z4 - -/** - * @brief Number of cores. - */ -#define PPC_CORE_NUMBER 1 - -/** - * @brief Number of writable bits in IVPR register. - */ -#define PPC_IVPR_BITS 16 - -/** - * @brief IVORx registers support. - */ -#define PPC_SUPPORTS_IVORS TRUE - -/** - * @brief Book E instruction set support. - */ -#define PPC_SUPPORTS_BOOKE TRUE - -/** - * @brief VLE instruction set support. - */ -#define PPC_SUPPORTS_VLE TRUE - -/** - * @brief Supports VLS Load/Store Multiple Volatile instructions. - */ -#define PPC_SUPPORTS_VLE_MULTI TRUE - -/** - * @brief Supports the decrementer timer. - */ -#define PPC_SUPPORTS_DECREMENTER TRUE - -/** - * @brief Number of interrupt sources. - */ -#define PPC_NUM_VECTORS 279 - -#endif /* _PPCPARAMS_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC56ELxx/boot.h b/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC56ELxx/boot.h deleted file mode 100644 index b5db1adcb9..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC56ELxx/boot.h +++ /dev/null @@ -1,248 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file boot.h - * @brief Boot parameters for the SPC56ELxx. - * @{ - */ - -#ifndef _BOOT_H_ -#define _BOOT_H_ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @name MASx registers definitions - * @{ - */ -#define MAS0_TBLMAS_TBL 0x10000000 -#define MAS0_ESEL_MASK 0x000F0000 -#define MAS0_ESEL(n) ((n) << 16) - -#define MAS1_VALID 0x80000000 -#define MAS1_IPROT 0x40000000 -#define MAS1_TID_MASK 0x00FF0000 -#define MAS1_TS 0x00001000 -#define MAS1_TSISE_MASK 0x00000F80 -#define MAS1_TSISE_1K 0x00000000 -#define MAS1_TSISE_2K 0x00000080 -#define MAS1_TSISE_4K 0x00000100 -#define MAS1_TSISE_8K 0x00000180 -#define MAS1_TSISE_16K 0x00000200 -#define MAS1_TSISE_32K 0x00000280 -#define MAS1_TSISE_64K 0x00000300 -#define MAS1_TSISE_128K 0x00000380 -#define MAS1_TSISE_256K 0x00000400 -#define MAS1_TSISE_512K 0x00000480 -#define MAS1_TSISE_1M 0x00000500 -#define MAS1_TSISE_2M 0x00000580 -#define MAS1_TSISE_4M 0x00000600 -#define MAS1_TSISE_8M 0x00000680 -#define MAS1_TSISE_16M 0x00000700 -#define MAS1_TSISE_32M 0x00000780 -#define MAS1_TSISE_64M 0x00000800 -#define MAS1_TSISE_128M 0x00000880 -#define MAS1_TSISE_256M 0x00000900 -#define MAS1_TSISE_512M 0x00000980 -#define MAS1_TSISE_1G 0x00000A00 -#define MAS1_TSISE_2G 0x00000A80 -#define MAS1_TSISE_4G 0x00000B00 - -#define MAS2_EPN_MASK 0xFFFFFC00 -#define MAS2_EPN(n) ((n) & MAS2_EPN_MASK) -#define MAS2_EBOOK 0x00000000 -#define MAS2_VLE 0x00000020 -#define MAS2_W 0x00000010 -#define MAS2_I 0x00000008 -#define MAS2_M 0x00000004 -#define MAS2_G 0x00000002 -#define MAS2_E 0x00000001 - -#define MAS3_RPN_MASK 0xFFFFFC00 -#define MAS3_RPN(n) ((n) & MAS3_RPN_MASK) -#define MAS3_U0 0x00000200 -#define MAS3_U1 0x00000100 -#define MAS3_U2 0x00000080 -#define MAS3_U3 0x00000040 -#define MAS3_UX 0x00000020 -#define MAS3_SX 0x00000010 -#define MAS3_UW 0x00000008 -#define MAS3_SW 0x00000004 -#define MAS3_UR 0x00000002 -#define MAS3_SR 0x00000001 -/** @} */ - -/** - * @name BUCSR registers definitions - * @{ - */ -#define BUCSR_BPEN 0x00000001 -#define BUCSR_BPRED_MASK 0x00000006 -#define BUCSR_BPRED_0 0x00000000 -#define BUCSR_BPRED_1 0x00000002 -#define BUCSR_BPRED_2 0x00000004 -#define BUCSR_BPRED_3 0x00000006 -#define BUCSR_BALLOC_MASK 0x00000030 -#define BUCSR_BALLOC_0 0x00000000 -#define BUCSR_BALLOC_1 0x00000010 -#define BUCSR_BALLOC_2 0x00000020 -#define BUCSR_BALLOC_3 0x00000030 -#define BUCSR_BALLOC_BFI 0x00000200 -/** @} */ - -/** - * @name LICSR1 registers definitions - * @{ - */ -#define LICSR1_ICE 0x00000001 -#define LICSR1_ICINV 0x00000002 -#define LICSR1_ICORG 0x00000010 -/** @} */ - -/** - * @name MSR register definitions - * @{ - */ -#define MSR_UCLE 0x04000000 -#define MSR_SPE 0x02000000 -#define MSR_WE 0x00040000 -#define MSR_CE 0x00020000 -#define MSR_EE 0x00008000 -#define MSR_PR 0x00004000 -#define MSR_FP 0x00002000 -#define MSR_ME 0x00001000 -#define MSR_FE0 0x00000800 -#define MSR_DE 0x00000200 -#define MSR_FE1 0x00000100 -#define MSR_IS 0x00000020 -#define MSR_DS 0x00000010 -#define MSR_RI 0x00000002 -/** @} */ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/* - * TLB default settings. - */ -#define TLB0_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(0)) -#define TLB0_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_2M) -#define TLB0_MAS2 (MAS2_EPN(0x00000000) | MAS2_VLE) -#define TLB0_MAS3 (MAS3_RPN(0x00000000) | \ - MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \ - MAS3_UR | MAS3_SR) - -#define TLB1_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(1)) -#define TLB1_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_256K) -#define TLB1_MAS2 (MAS2_EPN(0x40000000) | MAS2_VLE) -#define TLB1_MAS3 (MAS3_RPN(0x40000000) | \ - MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \ - MAS3_UR | MAS3_SR) - -#define TLB2_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(2)) -#define TLB2_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M) -#define TLB2_MAS2 (MAS2_EPN(0xC3F00000) | MAS2_I) -#define TLB2_MAS3 (MAS3_RPN(0xC3F00000) | \ - MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR) - -#define TLB3_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(3)) -#define TLB3_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M) -#define TLB3_MAS2 (MAS2_EPN(0xFFE00000) | MAS2_I) -#define TLB3_MAS3 (MAS3_RPN(0xFFE00000) | \ - MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR) - -#define TLB4_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(4)) -#define TLB4_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M) -#define TLB4_MAS2 (MAS2_EPN(0x8FF00000) | MAS2_I) -#define TLB4_MAS3 (MAS3_RPN(0x8FF00000) | \ - MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR) - -#define TLB5_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(5)) -#define TLB5_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M) -#define TLB5_MAS2 (MAS2_EPN(0xFFF00000) | MAS2_I) -#define TLB5_MAS3 (MAS3_RPN(0xFFF00000) | \ - MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR) - -/* - * BUCSR default settings. - */ -#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__) -#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BPRED_0 | \ - BUCSR_BALLOC_0 | BUCSR_BALLOC_BFI) -#endif - -/* - * LICSR1 default settings. - */ -#if !defined(BOOT_LICSR1_DEFAULT) || defined(__DOXYGEN__) -#define BOOT_LICSR1_DEFAULT (LICSR1_ICE | LICSR1_ICORG) -#endif - -/* - * MSR default settings. - */ -#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__) -#define BOOT_MSR_DEFAULT (MSR_SPE | MSR_WE | MSR_CE | MSR_ME) -#endif - -/* - * Boot default settings. - */ -#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__) -#define BOOT_PERFORM_CORE_INIT 1 -#endif - -/* - * VLE mode default settings. - */ -#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__) -#define BOOT_USE_VLE 1 -#endif - -/* - * RAM relocation flag. - */ -#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__) -#define BOOT_RELOCATE_IN_RAM 0 -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -#endif /* _BOOT_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC56ELxx/boot.s b/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC56ELxx/boot.s deleted file mode 100644 index 7c8b0e51b2..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC56ELxx/boot.s +++ /dev/null @@ -1,405 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SPC56ELxx/boot.s - * @brief SPC56ELxx boot-related code. - * - * @addtogroup PPC_BOOT - * @{ - */ - -#include "boot.h" - -#if !defined(__DOXYGEN__) - - /* BAM record.*/ - .section .boot, "ax" - -#if BOOT_USE_VLE - .long 0x015A0000 -#else - .long 0x005A0000 -#endif - .long _reset_address - - .align 2 - .globl _reset_address - .type _reset_address, @function -_reset_address: - bl _coreinit - bl _ivinit - -#if BOOT_RELOCATE_IN_RAM - /* - * Image relocation in RAM. - */ - lis %r4, __ram_reloc_start__@h - ori %r4, %r4, __ram_reloc_start__@l - lis %r5, __ram_reloc_dest__@h - ori %r5, %r5, __ram_reloc_dest__@l - lis %r6, __ram_reloc_end__@h - ori %r6, %r6, __ram_reloc_end__@l -.relloop: - cmpl cr0, %r4, %r6 - bge cr0, .relend - lwz %r7, 0(%r4) - addi %r4, %r4, 4 - stw %r7, 0(%r5) - addi %r5, %r5, 4 - b .relloop -.relend: - lis %r3, _boot_address@h - ori %r3, %r3, _boot_address@l - mtctr %r3 - bctrl -#else - b _boot_address -#endif - -#if BOOT_PERFORM_CORE_INIT - .align 2 -_ramcode: - tlbwe - isync - blr -#endif /* BOOT_PERFORM_CORE_INIT */ - - .align 2 -_coreinit: -#if BOOT_PERFORM_CORE_INIT - /* - * Invalidating all TLBs except TLB0. - */ - lis %r3, 0 - mtspr 625, %r3 /* MAS1 */ - mtspr 626, %r3 /* MAS2 */ - mtspr 627, %r3 /* MAS3 */ - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(1))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - - /* - * TLB1 allocated to internal RAM. - */ - lis %r3, TLB1_MAS0@h - mtspr 624, %r3 /* MAS0 */ - lis %r3, TLB1_MAS1@h - ori %r3, %r3, TLB1_MAS1@l - mtspr 625, %r3 /* MAS1 */ - lis %r3, TLB1_MAS2@h - ori %r3, %r3, TLB1_MAS2@l - mtspr 626, %r3 /* MAS2 */ - lis %r3, TLB1_MAS3@h - ori %r3, %r3, TLB1_MAS3@l - mtspr 627, %r3 /* MAS3 */ - tlbwe - - /* - * TLB2 allocated to internal Peripherals Bridge A. - */ - lis %r3, TLB2_MAS0@h - mtspr 624, %r3 /* MAS0 */ - lis %r3, TLB2_MAS1@h - ori %r3, %r3, TLB2_MAS1@l - mtspr 625, %r3 /* MAS1 */ - lis %r3, TLB2_MAS2@h - ori %r3, %r3, TLB2_MAS2@l - mtspr 626, %r3 /* MAS2 */ - lis %r3, TLB2_MAS3@h - ori %r3, %r3, TLB2_MAS3@l - mtspr 627, %r3 /* MAS3 */ - tlbwe - - /* - * TLB3 allocated to internal Peripherals Bridge B. - */ - lis %r3, TLB3_MAS0@h - mtspr 624, %r3 /* MAS0 */ - lis %r3, TLB3_MAS1@h - ori %r3, %r3, TLB3_MAS1@l - mtspr 625, %r3 /* MAS1 */ - lis %r3, TLB3_MAS2@h - ori %r3, %r3, TLB3_MAS2@l - mtspr 626, %r3 /* MAS2 */ - lis %r3, TLB3_MAS3@h - ori %r3, %r3, TLB3_MAS3@l - mtspr 627, %r3 /* MAS3 */ - tlbwe - - /* - * TLB4 allocated to on-platform peripherals. - */ - lis %r3, TLB4_MAS0@h - mtspr 624, %r3 /* MAS0 */ - lis %r3, TLB4_MAS1@h - ori %r3, %r3, TLB4_MAS1@l - mtspr 625, %r3 /* MAS1 */ - lis %r3, TLB4_MAS2@h - ori %r3, %r3, TLB4_MAS2@l - mtspr 626, %r3 /* MAS2 */ - lis %r3, TLB4_MAS3@h - ori %r3, %r3, TLB4_MAS3@l - mtspr 627, %r3 /* MAS3 */ - tlbwe - - /* - * TLB5 allocated to on-platform peripherals. - */ - lis %r3, TLB5_MAS0@h - mtspr 624, %r3 /* MAS0 */ - lis %r3, TLB5_MAS1@h - ori %r3, %r3, TLB5_MAS1@l - mtspr 625, %r3 /* MAS1 */ - lis %r3, TLB5_MAS2@h - ori %r3, %r3, TLB5_MAS2@l - mtspr 626, %r3 /* MAS2 */ - lis %r3, TLB5_MAS3@h - ori %r3, %r3, TLB5_MAS3@l - mtspr 627, %r3 /* MAS3 */ - tlbwe - - /* - * RAM clearing, this device requires a write to all RAM location in - * order to initialize the ECC detection hardware, this is going to - * slow down the startup but there is no way around. - */ - xor %r0, %r0, %r0 - xor %r1, %r1, %r1 - xor %r2, %r2, %r2 - xor %r3, %r3, %r3 - xor %r4, %r4, %r4 - xor %r5, %r5, %r5 - xor %r6, %r6, %r6 - xor %r7, %r7, %r7 - xor %r8, %r8, %r8 - xor %r9, %r9, %r9 - xor %r10, %r10, %r10 - xor %r11, %r11, %r11 - xor %r12, %r12, %r12 - xor %r13, %r13, %r13 - xor %r14, %r14, %r14 - xor %r15, %r15, %r15 - xor %r16, %r16, %r16 - xor %r17, %r17, %r17 - xor %r18, %r18, %r18 - xor %r19, %r19, %r19 - xor %r20, %r20, %r20 - xor %r21, %r21, %r21 - xor %r22, %r22, %r22 - xor %r23, %r23, %r23 - xor %r24, %r24, %r24 - xor %r25, %r25, %r25 - xor %r26, %r26, %r26 - xor %r27, %r27, %r27 - xor %r28, %r28, %r28 - xor %r29, %r29, %r29 - xor %r30, %r30, %r30 - xor %r31, %r31, %r31 - lis %r4, __ram_start__@h - ori %r4, %r4, __ram_start__@l - lis %r5, __ram_end__@h - ori %r5, %r5, __ram_end__@l -.cleareccloop: - cmpl %cr0, %r4, %r5 - bge %cr0, .cleareccend - stmw %r16, 0(%r4) - addi %r4, %r4, 64 - b .cleareccloop -.cleareccend: -#endif /* BOOT_PERFORM_CORE_INIT */ - - /* - * Special function registers clearing, required in order to avoid - * possible problems with lockstep mode. - */ - mtcrf 0xFF, %r31 - mtspr 9, %r31 /* CTR */ - mtspr 22, %r31 /* DEC */ - mtspr 26, %r31 /* SRR0-1 */ - mtspr 27, %r31 - mtspr 54, %r31 /* DECAR */ - mtspr 58, %r31 /* CSRR0-1 */ - mtspr 59, %r31 - mtspr 61, %r31 /* DEAR */ - mtspr 256, %r31 /* USPRG0 */ - mtspr 272, %r31 /* SPRG1-7 */ - mtspr 273, %r31 - mtspr 274, %r31 - mtspr 275, %r31 - mtspr 276, %r31 - mtspr 277, %r31 - mtspr 278, %r31 - mtspr 279, %r31 - mtspr 285, %r31 /* TBU */ - mtspr 284, %r31 /* TBL */ -#if 0 - mtspr 318, %r31 /* DVC1-2 */ - mtspr 319, %r31 -#endif - mtspr 562, %r31 /* DBCNT */ - mtspr 570, %r31 /* MCSRR0 */ - mtspr 571, %r31 /* MCSRR1 */ - mtspr 604, %r31 /* SPRG8-9 */ - mtspr 605, %r31 - -#if BOOT_PERFORM_CORE_INIT - /* - * *Finally* the TLB0 is re-allocated to flash, note, the final phase - * is executed from RAM. - */ - lis %r3, TLB0_MAS0@h - mtspr 624, %r3 /* MAS0 */ - lis %r3, TLB0_MAS1@h - ori %r3, %r3, TLB0_MAS1@l - mtspr 625, %r3 /* MAS1 */ - lis %r3, TLB0_MAS2@h - ori %r3, %r3, TLB0_MAS2@l - mtspr 626, %r3 /* MAS2 */ - lis %r3, TLB0_MAS3@h - ori %r3, %r3, TLB0_MAS3@l - mtspr 627, %r3 /* MAS3 */ - mflr %r4 - lis %r6, _ramcode@h - ori %r6, %r6, _ramcode@l - lis %r7, 0x40010000@h - mtctr %r7 - lwz %r3, 0(%r6) - stw %r3, 0(%r7) - lwz %r3, 4(%r6) - stw %r3, 4(%r7) - lwz %r3, 8(%r6) - stw %r3, 8(%r7) - bctrl - mtlr %r4 -#endif /* BOOT_PERFORM_CORE_INIT */ - - /* - * Branch prediction enabled. - */ - li %r3, BOOT_BUCSR_DEFAULT - mtspr 1013, %r3 /* BUCSR */ - - /* - * Cache invalidated and then enabled. - */ - li %r3, LICSR1_ICINV - mtspr 1011, %r3 /* LICSR1 */ -.inv: mfspr %r3, 1011 /* LICSR1 */ - andi. %r3, %r3, LICSR1_ICINV - bne .inv - lis %r3, BOOT_LICSR1_DEFAULT@h - ori %r3, %r3, BOOT_LICSR1_DEFAULT@l - mtspr 1011, %r3 /* LICSR1 */ - - blr - - /* - * Exception vectors initialization. - */ - .align 2 -_ivinit: - /* MSR initialization.*/ - lis %r3, BOOT_MSR_DEFAULT@h - ori %r3, %r3, BOOT_MSR_DEFAULT@l - mtMSR %r3 - - /* IVPR initialization.*/ - lis %r3, __ivpr_base__@h - ori %r3, %r3, __ivpr_base__@l - mtIVPR %r3 - - /* IVORs initialization.*/ - lis %r3, _unhandled_exception@h - ori %r3, %r3, _unhandled_exception@l - - mtspr 400, %r3 /* IVOR0-15 */ - mtspr 401, %r3 - mtspr 402, %r3 - mtspr 403, %r3 - mtspr 404, %r3 - mtspr 405, %r3 - mtspr 406, %r3 - mtspr 407, %r3 - mtspr 408, %r3 - mtspr 409, %r3 - mtspr 410, %r3 - mtspr 411, %r3 - mtspr 412, %r3 - mtspr 413, %r3 - mtspr 414, %r3 - mtspr 415, %r3 - mtspr 528, %r3 /* IVOR32-34 */ - mtspr 529, %r3 - mtspr 530, %r3 - - blr - - .section .handlers, "ax" - - /* - * Unhandled exceptions handler. - */ - .weak _unhandled_exception - .type _unhandled_exception, @function -_unhandled_exception: - b _unhandled_exception - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC56ELxx/intc.h b/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC56ELxx/intc.h deleted file mode 100644 index 6993a9b0fe..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC56ELxx/intc.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SPC56ELxx/intc.h - * @brief SPC56ELxx INTC module header. - * - * @addtogroup INTC - * @{ - */ - -#ifndef _INTC_H_ -#define _INTC_H_ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @name INTC addresses - * @{ - */ -#define INTC_BASE 0xFFF48000 -#define INTC_IACKR_ADDR (INTC_BASE + 0x10) -#define INTC_EOIR_ADDR (INTC_BASE + 0x18) -/** @} */ - -/** - * @brief INTC priority levels. - */ -#define INTC_PRIORITY_LEVELS 16U - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @name INTC-related macros - * @{ - */ -#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0))) -#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t))))) -#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t))))) -#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t))))) -#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t))))) -/** @} */ - -/** - * @brief Core selection macros for PSR register. - */ -#define INTC_PSR_CORE0 0x00 - -/** - * @brief PSR register content helper - */ -#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -#endif /* _INTC_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC56ELxx/ppcparams.h b/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC56ELxx/ppcparams.h deleted file mode 100644 index a97787a221..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC56ELxx/ppcparams.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SPC56ELxx/ppcparams.h - * @brief PowerPC parameters for the SPC56ELxx. - * - * @defgroup PPC_SPC56ELxx SPC56ELxx Specific Parameters - * @ingroup PPC_SPECIFIC - * @details This file contains the PowerPC specific parameters for the - * SPC56ELxx platform. - * @{ - */ - -#ifndef _PPCPARAMS_H_ -#define _PPCPARAMS_H_ - -/** - * @brief Family identification macro. - */ -#define PPC_SPC56ELxx - -/** - * @brief PPC core model. - */ -#define PPC_VARIANT PPC_VARIANT_e200z4 - -/** - * @brief Number of cores. - */ -#define PPC_CORE_NUMBER 1 - -/** - * @brief Number of writable bits in IVPR register. - */ -#define PPC_IVPR_BITS 16 - -/** - * @brief IVORx registers support. - */ -#define PPC_SUPPORTS_IVORS TRUE - -/** - * @brief Book E instruction set support. - */ -#define PPC_SUPPORTS_BOOKE TRUE - -/** - * @brief VLE instruction set support. - */ -#define PPC_SUPPORTS_VLE TRUE - -/** - * @brief Supports VLS Load/Store Multiple Volatile instructions. - */ -#define PPC_SUPPORTS_VLE_MULTI TRUE - -/** - * @brief Supports the decrementer timer. - */ -#define PPC_SUPPORTS_DECREMENTER TRUE - -/** - * @brief Number of interrupt sources. - */ -#define PPC_NUM_VECTORS 256 - -#endif /* _PPCPARAMS_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC57EMxx_HSM/boot.h b/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC57EMxx_HSM/boot.h deleted file mode 100644 index 2866aac7e1..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC57EMxx_HSM/boot.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file boot.h - * @brief Boot parameters for the SPC57EMxx_HSM. - * @{ - */ - -#ifndef _BOOT_H_ -#define _BOOT_H_ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @name BUCSR registers definitions - * @{ - */ -#define BUCSR_BPEN 0x00000001 -#define BUCSR_BALLOC_BFI 0x00000200 -/** @} */ - -/** - * @name MSR register definitions - * @{ - */ -#define MSR_WE 0x00040000 -#define MSR_CE 0x00020000 -#define MSR_EE 0x00008000 -#define MSR_PR 0x00004000 -#define MSR_ME 0x00001000 -#define MSR_DE 0x00000200 -#define MSR_IS 0x00000020 -#define MSR_DS 0x00000010 -#define MSR_RI 0x00000002 -/** @} */ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/* - * BUCSR default settings. - */ -#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__) -#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI) -#endif - -/* - * MSR default settings. - */ -#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__) -#define BOOT_MSR_DEFAULT (MSR_WE | MSR_CE | MSR_ME) -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -#endif /* _BOOT_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC57EMxx_HSM/boot.s b/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC57EMxx_HSM/boot.s deleted file mode 100644 index d9ba18c1cc..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC57EMxx_HSM/boot.s +++ /dev/null @@ -1,208 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SPC57EMxx_HSM/boot.s - * @brief SPC57EMxx_HSM boot-related code. - * - * @addtogroup PPC_BOOT - * @{ - */ - -#include "boot.h" - -#define HSBI_CCR 0xA3F14004 -#define HSBI_CCR_CE 0x00000001 -#define HSBI_CCR_INV 0x00000002 - -#if !defined(__DOXYGEN__) - - /* Boot record.*/ - .section .boot, "ax" - - .long 0xFFFF0000 - .long 0xFFFF0000 - .long 0xFFFFFFFF - .long _reset_address - .long 0xFFFFFFFF - .long 0xFFFFFFFF - .long 0xFFFFFFFF - .long 0xFFFFFFFF - - .align 2 - .globl _reset_address - .type _reset_address, @function -_reset_address: - bl _coreinit - bl _ivinit - b _boot_address - - .align 2 -_coreinit: -#if 0 - /* - * Cache invalidate and enable. - */ - lis %r7, HSBI_CCR@h - ori %r7, %r7, HSBI_CCR@l - li %r0, HSBI_CCR_INV | HSBI_CCR_CE - stw %r0, 0(%r7) -.inv: - lwz %r0, 0(%r7) - andi. %r0, %r0, HSBI_CCR_INV - bne+ %cr0, .inv -#endif - - /* - * RAM clearing, this device requires a write to all RAM location in - * order to initialize the ECC detection hardware, this is going to - * slow down the startup but there is no way around. - */ - xor %r0, %r0, %r0 - xor %r1, %r1, %r1 - xor %r2, %r2, %r2 - xor %r3, %r3, %r3 - xor %r4, %r4, %r4 - xor %r5, %r5, %r5 - xor %r6, %r6, %r6 - xor %r7, %r7, %r7 - xor %r8, %r8, %r8 - xor %r9, %r9, %r9 - xor %r10, %r10, %r10 - xor %r11, %r11, %r11 - xor %r12, %r12, %r12 - xor %r13, %r13, %r13 - xor %r14, %r14, %r14 - xor %r15, %r15, %r15 - xor %r16, %r16, %r16 - xor %r17, %r17, %r17 - xor %r18, %r18, %r18 - xor %r19, %r19, %r19 - xor %r20, %r20, %r20 - xor %r21, %r21, %r21 - xor %r22, %r22, %r22 - xor %r23, %r23, %r23 - xor %r24, %r24, %r24 - xor %r25, %r25, %r25 - xor %r26, %r26, %r26 - xor %r27, %r27, %r27 - xor %r28, %r28, %r28 - xor %r29, %r29, %r29 - xor %r30, %r30, %r30 - xor %r31, %r31, %r31 - lis %r4, __ram_start__@h - ori %r4, %r4, __ram_start__@l - lis %r5, __ram_end__@h - ori %r5, %r5, __ram_end__@l -.cleareccloop: - cmpl %cr0, %r4, %r5 - bge %cr0, .cleareccend - stmw %r16, 0(%r4) - addi %r4, %r4, 64 - b .cleareccloop -.cleareccend: - - /* - * Branch prediction enabled. - */ - li %r3, BUCSR_DEFAULT - mtspr 1013, %r3 /* BUCSR */ - - blr - - /* - * Exception vectors initialization. - */ - .align 2 -_ivinit: - /* MSR initialization.*/ - lis %r3, MSR_DEFAULT@h - ori %r3, %r3, MSR_DEFAULT@l - mtMSR %r3 - - /* IVPR initialization.*/ - lis %r3, __ivpr_base__@h - ori %r3, %r3, __ivpr_base__@l - mtIVPR %r3 - - blr - - .section .ivors, "ax" - - .globl IVORS -IVORS: -IVOR0: b _IVOR0 - .align 4 -IVOR1: b _IVOR1 - .align 4 -IVOR2: b _IVOR2 - .align 4 -IVOR3: b _IVOR3 - .align 4 -IVOR4: b _IVOR4 - .align 4 -IVOR5: b _IVOR5 - .align 4 -IVOR6: b _IVOR6 - .align 4 -IVOR7: b _IVOR7 - .align 4 -IVOR8: b _IVOR8 - .align 4 -IVOR9: b _IVOR9 - .align 4 -IVOR10: b _IVOR10 - .align 4 -IVOR11: b _IVOR11 - .align 4 -IVOR12: b _IVOR12 - .align 4 -IVOR13: b _IVOR13 - .align 4 -IVOR14: b _IVOR14 - .align 4 -IVOR15: b _IVOR15 - - .section .handlers, "ax" - - /* - * Default IVOR handlers. - */ - .align 2 - .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5 - .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11 - .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15 -_IVOR0: -_IVOR1: -_IVOR2: -_IVOR3: -_IVOR5: -_IVOR6: -_IVOR7: -_IVOR8: -_IVOR9: -_IVOR11: -_IVOR12: -_IVOR13: -_IVOR14: -_IVOR15: - .global _unhandled_exception -_unhandled_exception: - b _unhandled_exception - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC57EMxx_HSM/intc.h b/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC57EMxx_HSM/intc.h deleted file mode 100644 index 804e867226..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC57EMxx_HSM/intc.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SPC57EMxx_HSM/intc.h - * @brief SPC57EMxx_HSM INTC module header. - * - * @addtogroup INTC - * @{ - */ - -#ifndef _INTC_H_ -#define _INTC_H_ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @name INTC addresses - * @{ - */ -#define INTC_BASE 0xA3F48000 -#define INTC_IACKR_ADDR (INTC_BASE + 0x20) -#define INTC_EOIR_ADDR (INTC_BASE + 0x30) -/** @} */ - -/** - * @brief INTC priority levels. - */ -#define INTC_PRIORITY_LEVELS 16U - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @name INTC-related macros - * @{ - */ -#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0))) -#define INTC_MPROT (*((volatile uint32_t *)(INTC_BASE + 4))) -#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t))))) -#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x20 + ((n) * sizeof (uint32_t))))) -#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x30 + ((n) * sizeof (uint32_t))))) -#define INTC_PSR(n) (*((volatile uint16_t *)(INTC_BASE + 0x60 + ((n) * sizeof (uint16_t))))) -/** @} */ - -/** - * @brief Core selection macros for PSR register. - */ -#define INTC_PSR_CORE4 0x8000 - -/** - * @brief PSR register content helper - */ -#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -#endif /* _INTC_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC57EMxx_HSM/ppcparams.h b/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC57EMxx_HSM/ppcparams.h deleted file mode 100644 index 7c89334f49..0000000000 --- a/firmware/ChibiOS_16/os/common/ports/e200/devices/SPC57EMxx_HSM/ppcparams.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SPC57EMxx_HSM/ppcparams.h - * @brief PowerPC parameters for the SPC57EMxx_HSM. - * - * @defgroup PPC_SPC57EMxx_HSM SPC57EMxx_HSM Specific Parameters - * @ingroup PPC_SPECIFIC - * @details This file contains the PowerPC specific parameters for the - * SPC57EMxx_HSM platform. - * @{ - */ - -#ifndef _PPCPARAMS_H_ -#define _PPCPARAMS_H_ - -/** - * @brief Family identification macro. - */ -#define PPC_SPC560Dxx - -/** - * @brief Alternate identification macro. - */ -#define PPC_SPC57EMxx_HSM - -/** - * @brief PPC core model. - */ -#define PPC_VARIANT PPC_VARIANT_e200z0 - -/** - * @brief Number of cores. - */ -#define PPC_CORE_NUMBER 1 - -/** - * @brief Number of writable bits in IVPR register. - */ -#define PPC_IVPR_BITS 20 - -/** - * @brief IVORx registers support. - */ -#define PPC_SUPPORTS_IVORS FALSE - -/** - * @brief Book E instruction set support. - */ -#define PPC_SUPPORTS_BOOKE FALSE - -/** - * @brief VLE instruction set support. - */ -#define PPC_SUPPORTS_VLE TRUE - -/** - * @brief Supports VLS Load/Store Multiple Volatile instructions. - */ -#define PPC_SUPPORTS_VLE_MULTI TRUE - -/** - * @brief Supports the decrementer timer. - */ -#define PPC_SUPPORTS_DECREMENTER FALSE - -/** - * @brief Number of interrupt sources. - */ -#define PPC_NUM_VECTORS 64 - -#endif /* _PPCPARAMS_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/ext/CMSIS/ST/STM32F4xx/stm32f407xx.h b/firmware/ChibiOS_16/os/ext/CMSIS/ST/STM32F4xx/stm32f407xx.h deleted file mode 100644 index f6dbf6c9ce..0000000000 --- a/firmware/ChibiOS_16/os/ext/CMSIS/ST/STM32F4xx/stm32f407xx.h +++ /dev/null @@ -1,8067 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f407xx.h - * @author MCD Application Team - * @version V2.4.2 - * @date 13-November-2015 - * @brief CMSIS STM32F407xx Device Peripheral Access Layer Header File. - * - * This file contains: - * - Data structures and the address mapping for all peripherals - * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f407xx - * @{ - */ - -#ifndef __STM32F407xx_H -#define __STM32F407xx_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ - -/** - * @brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ -#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ - -/** - * @} - */ - -/** @addtogroup Peripheral_interrupt_number_definition - * @{ - */ - -/** - * @brief STM32F4XX Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ -typedef enum -{ -/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ -/****** STM32 specific Interrupt Numbers **********************************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ - RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ - DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ - DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ - DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ - DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ - DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ - DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ - ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ - CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ - CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ - TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ - TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ - TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ - TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ - TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ - FSMC_IRQn = 48, /*!< FSMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ - TIM7_IRQn = 55, /*!< TIM7 global interrupt */ - DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ - DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ - DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ - DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ - DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ - ETH_IRQn = 61, /*!< Ethernet global Interrupt */ - ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ - CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ - CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ - CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ - CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ - OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ - DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ - DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ - DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ - USART6_IRQn = 71, /*!< USART6 global interrupt */ - I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ - I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ - OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ - OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ - OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ - OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ - DCMI_IRQn = 78, /*!< DCMI global interrupt */ - HASH_RNG_IRQn = 80, /*!< Hash and RNG global interrupt */ - FPU_IRQn = 81 /*!< FPU global interrupt */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ -#include "system_stm32f4xx.h" -#include - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ - __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ - __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ - __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ - __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ - __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ - __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ - __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ - __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ - __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ - __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ - __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ - __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ - __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ - __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ - __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ - __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ - __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ - __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual - AND triple modes, Address offset: ADC1 base address + 0x308 */ -} ADC_Common_TypeDef; - - -/** - * @brief Controller Area Network TxMailBox - */ - -typedef struct -{ - __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ - __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ - __IO uint32_t TDLR; /*!< CAN mailbox data low register */ - __IO uint32_t TDHR; /*!< CAN mailbox data high register */ -} CAN_TxMailBox_TypeDef; - -/** - * @brief Controller Area Network FIFOMailBox - */ - -typedef struct -{ - __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ - __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ - __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ - __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ -} CAN_FIFOMailBox_TypeDef; - -/** - * @brief Controller Area Network FilterRegister - */ - -typedef struct -{ - __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ - __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ -} CAN_FilterRegister_TypeDef; - -/** - * @brief Controller Area Network - */ - -typedef struct -{ - __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ - __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ - __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ - __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ - __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ - __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ - __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ - __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ - uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ - CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ - uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ - __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ - __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ - uint32_t RESERVED2; /*!< Reserved, 0x208 */ - __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ - uint32_t RESERVED3; /*!< Reserved, 0x210 */ - __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ - uint32_t RESERVED4; /*!< Reserved, 0x218 */ - __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ - uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ - CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ -} CAN_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - uint8_t RESERVED0; /*!< Reserved, 0x05 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -} CRC_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DCMI - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ - __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ - __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ - __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ - __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ - __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ - __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ - __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ - __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ - __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ - __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ -} DCMI_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DMA stream x configuration register */ - __IO uint32_t NDTR; /*!< DMA stream x number of data register */ - __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ - __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ - __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ - __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ -} DMA_Stream_TypeDef; - -typedef struct -{ - __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ - __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ - __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ - __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ -} DMA_TypeDef; - - -/** - * @brief Ethernet MAC - */ - -typedef struct -{ - __IO uint32_t MACCR; - __IO uint32_t MACFFR; - __IO uint32_t MACHTHR; - __IO uint32_t MACHTLR; - __IO uint32_t MACMIIAR; - __IO uint32_t MACMIIDR; - __IO uint32_t MACFCR; - __IO uint32_t MACVLANTR; /* 8 */ - uint32_t RESERVED0[2]; - __IO uint32_t MACRWUFFR; /* 11 */ - __IO uint32_t MACPMTCSR; - uint32_t RESERVED1[2]; - __IO uint32_t MACSR; /* 15 */ - __IO uint32_t MACIMR; - __IO uint32_t MACA0HR; - __IO uint32_t MACA0LR; - __IO uint32_t MACA1HR; - __IO uint32_t MACA1LR; - __IO uint32_t MACA2HR; - __IO uint32_t MACA2LR; - __IO uint32_t MACA3HR; - __IO uint32_t MACA3LR; /* 24 */ - uint32_t RESERVED2[40]; - __IO uint32_t MMCCR; /* 65 */ - __IO uint32_t MMCRIR; - __IO uint32_t MMCTIR; - __IO uint32_t MMCRIMR; - __IO uint32_t MMCTIMR; /* 69 */ - uint32_t RESERVED3[14]; - __IO uint32_t MMCTGFSCCR; /* 84 */ - __IO uint32_t MMCTGFMSCCR; - uint32_t RESERVED4[5]; - __IO uint32_t MMCTGFCR; - uint32_t RESERVED5[10]; - __IO uint32_t MMCRFCECR; - __IO uint32_t MMCRFAECR; - uint32_t RESERVED6[10]; - __IO uint32_t MMCRGUFCR; - uint32_t RESERVED7[334]; - __IO uint32_t PTPTSCR; - __IO uint32_t PTPSSIR; - __IO uint32_t PTPTSHR; - __IO uint32_t PTPTSLR; - __IO uint32_t PTPTSHUR; - __IO uint32_t PTPTSLUR; - __IO uint32_t PTPTSAR; - __IO uint32_t PTPTTHR; - __IO uint32_t PTPTTLR; - __IO uint32_t RESERVED8; - __IO uint32_t PTPTSSR; - uint32_t RESERVED9[565]; - __IO uint32_t DMABMR; - __IO uint32_t DMATPDR; - __IO uint32_t DMARPDR; - __IO uint32_t DMARDLAR; - __IO uint32_t DMATDLAR; - __IO uint32_t DMASR; - __IO uint32_t DMAOMR; - __IO uint32_t DMAIER; - __IO uint32_t DMAMFBOCR; - __IO uint32_t DMARSWTR; - uint32_t RESERVED10[8]; - __IO uint32_t DMACHTDR; - __IO uint32_t DMACHRDR; - __IO uint32_t DMACHTBAR; - __IO uint32_t DMACHRBAR; -} ETH_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ - __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ - __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ - __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ - __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ - __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ -} EXTI_TypeDef; - -/** - * @brief FLASH Registers - */ - -typedef struct -{ - __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ - __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ - __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ - __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ - __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ - __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */ -} FLASH_TypeDef; - - -/** - * @brief Flexible Static Memory Controller - */ - -typedef struct -{ - __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ -} FSMC_Bank1_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank1E - */ - -typedef struct -{ - __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ -} FSMC_Bank1E_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank2 - */ - -typedef struct -{ - __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ - __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ - __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ - __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ - uint32_t RESERVED0; /*!< Reserved, 0x70 */ - __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ - uint32_t RESERVED1; /*!< Reserved, 0x78 */ - uint32_t RESERVED2; /*!< Reserved, 0x7C */ - __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ - __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ - __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ - __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ - uint32_t RESERVED3; /*!< Reserved, 0x90 */ - __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ -} FSMC_Bank2_3_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank4 - */ - -typedef struct -{ - __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ - __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ - __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ - __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ - __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ -} FSMC_Bank4_TypeDef; - - -/** - * @brief General Purpose I/O - */ - -typedef struct -{ - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ -} GPIO_TypeDef; - -/** - * @brief System configuration controller - */ - -typedef struct -{ - __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ - __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ - __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ - uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ - __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ -} SYSCFG_TypeDef; - -/** - * @brief Inter-integrated Circuit Interface - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ - __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ - __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ - __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */ - __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ - __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ - __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ - __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ - __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */ -} I2C_TypeDef; - -/** - * @brief Independent WATCHDOG - */ - -typedef struct -{ - __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ - __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ - __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ -} IWDG_TypeDef; - -/** - * @brief Power Control - */ - -typedef struct -{ - __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ - __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ -} PWR_TypeDef; - -/** - * @brief Reset and Clock Control - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ - __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ - __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ - __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ - __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ - __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ - __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ - uint32_t RESERVED0; /*!< Reserved, 0x1C */ - __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ - __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ - uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ - __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ - __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ - __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ - uint32_t RESERVED2; /*!< Reserved, 0x3C */ - __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ - __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ - uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ - __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ - __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ - __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ - uint32_t RESERVED4; /*!< Reserved, 0x5C */ - __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ - __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ - uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ - __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ - __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ - uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ - __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ - __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ - -} RCC_TypeDef; - -/** - * @brief Real-Time Clock - */ - -typedef struct -{ - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ - __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ - __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */ - uint32_t RESERVED7; /*!< Reserved, 0x4C */ - __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ - __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ - __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ - __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ - __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ - __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ - __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ - __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ - __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ - __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ - __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ - __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ - __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ - __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ - __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ - __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ - __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ - __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ - __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ - __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ -} RTC_TypeDef; - - -/** - * @brief SD host Interface - */ - -typedef struct -{ - __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ - __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ - __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ - __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ - __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ - __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ - __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ - __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ - __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ - __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ - __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ - __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ - __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ - __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ - __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ - __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ - uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ - __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ - uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ - __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ -} SDIO_TypeDef; - -/** - * @brief Serial Peripheral Interface - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ - __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ - __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */ - __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ - __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ - __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ - __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ - __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ - __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ -} SPI_TypeDef; - -/** - * @brief TIM - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ - __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ - __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ - __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ - __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ - __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ - __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ - __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ - __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ - __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ - __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ - __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ - __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ -} TIM_TypeDef; - -/** - * @brief Universal Synchronous Asynchronous Receiver Transmitter - */ - -typedef struct -{ - __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ - __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ - __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ - __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ - __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ - __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ -} USART_TypeDef; - -/** - * @brief Window WATCHDOG - */ - -typedef struct -{ - __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ - __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ - __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ -} WWDG_TypeDef; - -/** - * @brief RNG - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ -} RNG_TypeDef; - - - -/** - * @brief __USB_OTG_Core_register - */ -typedef struct -{ - __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h*/ - __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h*/ - __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h*/ - __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch*/ - __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h*/ - __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h*/ - __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/ - __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/ - __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/ - __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/ - __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/ - __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/ - uint32_t Reserved30[2]; /* Reserved 030h*/ - __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/ - __IO uint32_t CID; /* User ID Register 03Ch*/ - uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/ - __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/ - __IO uint32_t DIEPTXF[0x0F];/* dev Periodic Transmit FIFO */ -} -USB_OTG_GlobalTypeDef; - - - -/** - * @brief __device_Registers - */ -typedef struct -{ - __IO uint32_t DCFG; /* dev Configuration Register 800h*/ - __IO uint32_t DCTL; /* dev Control Register 804h*/ - __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/ - uint32_t Reserved0C; /* Reserved 80Ch*/ - __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/ - __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/ - __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/ - __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/ - uint32_t Reserved20; /* Reserved 820h*/ - uint32_t Reserved9; /* Reserved 824h*/ - __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/ - __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/ - __IO uint32_t DTHRCTL; /* dev thr 830h*/ - __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/ - __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/ - __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/ - uint32_t Reserved40; /* dedicated EP mask 840h*/ - __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/ - uint32_t Reserved44[15]; /* Reserved 844-87Ch*/ - __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/ -} -USB_OTG_DeviceTypeDef; - - -/** - * @brief __IN_Endpoint-Specific_Register - */ -typedef struct -{ - __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/ - uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/ - __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/ - uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/ - __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/ - __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/ - __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/ - uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/ -} -USB_OTG_INEndpointTypeDef; - - -/** - * @brief __OUT_Endpoint-Specific_Registers - */ -typedef struct -{ - __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ - uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/ - __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/ - uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/ - __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/ - __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/ - uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/ -} -USB_OTG_OUTEndpointTypeDef; - - -/** - * @brief __Host_Mode_Register_Structures - */ -typedef struct -{ - __IO uint32_t HCFG; /* Host Configuration Register 400h*/ - __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/ - __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/ - uint32_t Reserved40C; /* Reserved 40Ch*/ - __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/ - __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/ - __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/ -} -USB_OTG_HostTypeDef; - - -/** - * @brief __Host_Channel_Specific_Registers - */ -typedef struct -{ - __IO uint32_t HCCHAR; - __IO uint32_t HCSPLT; - __IO uint32_t HCINT; - __IO uint32_t HCINTMSK; - __IO uint32_t HCTSIZ; - __IO uint32_t HCDMA; - uint32_t Reserved[2]; -} -USB_OTG_HostChannelTypeDef; - - -/** - * @brief Peripheral_memory_map - */ -#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */ -#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */ -#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */ -#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ -#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */ -#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ -#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */ -#define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ -#define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */ -#define FLASH_END ((uint32_t)0x080FFFFF) /*!< FLASH end address */ -#define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */ - -/* Legacy defines */ -#define SRAM_BASE SRAM1_BASE -#define SRAM_BB_BASE SRAM1_BB_BASE - - -/*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) -#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) -#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) - -/*!< APB1 peripherals */ -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) -#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) -#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) -#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) -#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) -#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) -#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800) -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) -#define UART5_BASE (APB1PERIPH_BASE + 0x5000) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) -#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) -#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400) - -/*!< APB2 peripherals */ -#define TIM1_BASE (APB2PERIPH_BASE + 0x0000) -#define TIM8_BASE (APB2PERIPH_BASE + 0x0400) -#define USART1_BASE (APB2PERIPH_BASE + 0x1000) -#define USART6_BASE (APB2PERIPH_BASE + 0x1400) -#define ADC1_BASE (APB2PERIPH_BASE + 0x2000) -#define ADC2_BASE (APB2PERIPH_BASE + 0x2100) -#define ADC3_BASE (APB2PERIPH_BASE + 0x2200) -#define ADC_BASE (APB2PERIPH_BASE + 0x2300) -#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) -#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) -#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) -#define TIM9_BASE (APB2PERIPH_BASE + 0x4000) -#define TIM10_BASE (APB2PERIPH_BASE + 0x4400) -#define TIM11_BASE (APB2PERIPH_BASE + 0x4800) - -/*!< AHB1 peripherals */ -#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) -#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) -#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) -#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) -#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) -#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400) -#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) -#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) -#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) -#define CRC_BASE (AHB1PERIPH_BASE + 0x3000) -#define RCC_BASE (AHB1PERIPH_BASE + 0x3800) -#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) -#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000) -#define DMA1_Stream0_BASE (DMA1_BASE + 0x010) -#define DMA1_Stream1_BASE (DMA1_BASE + 0x028) -#define DMA1_Stream2_BASE (DMA1_BASE + 0x040) -#define DMA1_Stream3_BASE (DMA1_BASE + 0x058) -#define DMA1_Stream4_BASE (DMA1_BASE + 0x070) -#define DMA1_Stream5_BASE (DMA1_BASE + 0x088) -#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0) -#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8) -#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400) -#define DMA2_Stream0_BASE (DMA2_BASE + 0x010) -#define DMA2_Stream1_BASE (DMA2_BASE + 0x028) -#define DMA2_Stream2_BASE (DMA2_BASE + 0x040) -#define DMA2_Stream3_BASE (DMA2_BASE + 0x058) -#define DMA2_Stream4_BASE (DMA2_BASE + 0x070) -#define DMA2_Stream5_BASE (DMA2_BASE + 0x088) -#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) -#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) -#define ETH_BASE (AHB1PERIPH_BASE + 0x8000) -#define ETH_MAC_BASE (ETH_BASE) -#define ETH_MMC_BASE (ETH_BASE + 0x0100) -#define ETH_PTP_BASE (ETH_BASE + 0x0700) -#define ETH_DMA_BASE (ETH_BASE + 0x1000) - -/*!< AHB2 peripherals */ -#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000) -#define RNG_BASE (AHB2PERIPH_BASE + 0x60800) - -/*!< FSMC Bankx registers base address */ -#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) -#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) -#define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060) -#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) - -/* Debug MCU registers base address */ -#define DBGMCU_BASE ((uint32_t )0xE0042000) - -/*!< USB registers base address */ -#define USB_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000) -#define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000) - -#define USB_OTG_GLOBAL_BASE ((uint32_t )0x000) -#define USB_OTG_DEVICE_BASE ((uint32_t )0x800) -#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900) -#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00) -#define USB_OTG_EP_REG_SIZE ((uint32_t )0x20) -#define USB_OTG_HOST_BASE ((uint32_t )0x400) -#define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440) -#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500) -#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20) -#define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00) -#define USB_OTG_FIFO_BASE ((uint32_t )0x1000) -#define USB_OTG_FIFO_SIZE ((uint32_t )0x1000) - -/** - * @} - */ - -/** @addtogroup Peripheral_declaration - * @{ - */ -#define TIM2 ((TIM_TypeDef *) TIM2_BASE) -#define TIM3 ((TIM_TypeDef *) TIM3_BASE) -#define TIM4 ((TIM_TypeDef *) TIM4_BASE) -#define TIM5 ((TIM_TypeDef *) TIM5_BASE) -#define TIM6 ((TIM_TypeDef *) TIM6_BASE) -#define TIM7 ((TIM_TypeDef *) TIM7_BASE) -#define TIM12 ((TIM_TypeDef *) TIM12_BASE) -#define TIM13 ((TIM_TypeDef *) TIM13_BASE) -#define TIM14 ((TIM_TypeDef *) TIM14_BASE) -#define RTC ((RTC_TypeDef *) RTC_BASE) -#define WWDG ((WWDG_TypeDef *) WWDG_BASE) -#define IWDG ((IWDG_TypeDef *) IWDG_BASE) -#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE) -#define SPI2 ((SPI_TypeDef *) SPI2_BASE) -#define SPI3 ((SPI_TypeDef *) SPI3_BASE) -#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) -#define USART2 ((USART_TypeDef *) USART2_BASE) -#define USART3 ((USART_TypeDef *) USART3_BASE) -#define UART4 ((USART_TypeDef *) UART4_BASE) -#define UART5 ((USART_TypeDef *) UART5_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define I2C3 ((I2C_TypeDef *) I2C3_BASE) -#define CAN1 ((CAN_TypeDef *) CAN1_BASE) -#define CAN2 ((CAN_TypeDef *) CAN2_BASE) -#define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) -#define TIM1 ((TIM_TypeDef *) TIM1_BASE) -#define TIM8 ((TIM_TypeDef *) TIM8_BASE) -#define USART1 ((USART_TypeDef *) USART1_BASE) -#define USART6 ((USART_TypeDef *) USART6_BASE) -#define ADC ((ADC_Common_TypeDef *) ADC_BASE) -#define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC2 ((ADC_TypeDef *) ADC2_BASE) -#define ADC3 ((ADC_TypeDef *) ADC3_BASE) -#define SDIO ((SDIO_TypeDef *) SDIO_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) -#define EXTI ((EXTI_TypeDef *) EXTI_BASE) -#define TIM9 ((TIM_TypeDef *) TIM9_BASE) -#define TIM10 ((TIM_TypeDef *) TIM10_BASE) -#define TIM11 ((TIM_TypeDef *) TIM11_BASE) -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) -#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) -#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) -#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) -#define CRC ((CRC_TypeDef *) CRC_BASE) -#define RCC ((RCC_TypeDef *) RCC_BASE) -#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) -#define DMA1 ((DMA_TypeDef *) DMA1_BASE) -#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) -#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) -#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) -#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) -#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) -#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) -#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) -#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) -#define DMA2 ((DMA_TypeDef *) DMA2_BASE) -#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) -#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) -#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) -#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) -#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) -#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) -#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) -#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) -#define ETH ((ETH_TypeDef *) ETH_BASE) -#define DCMI ((DCMI_TypeDef *) DCMI_BASE) -#define RNG ((RNG_TypeDef *) RNG_BASE) -#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) -#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) -#define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE) -#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) - -#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) - -#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) -#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE) - -/** - * @} - */ - -/** @addtogroup Exported_constants - * @{ - */ - - /** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ - -/******************************************************************************/ -/* Peripheral Registers_Bits_Definition */ -/******************************************************************************/ - -/******************************************************************************/ -/* */ -/* Analog to Digital Converter */ -/* */ -/******************************************************************************/ -/******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD ((uint32_t)0x00000001) /*!
© COPYRIGHT(c) 2015 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f4xx - * @{ - */ - -#ifndef __STM32F4xx_H -#define __STM32F4xx_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Library_configuration_section - * @{ - */ - -/** - * @brief STM32 Family - */ -#if !defined (STM32F4) -#define STM32F4 -#endif /* STM32F4 */ - -/* Uncomment the line below according to the target STM32 device used in your - application - */ -#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \ - !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \ - !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \ - !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \ - !defined (STM32F479xx) - /* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */ - /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */ - /* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */ - /* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */ - /* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */ - /* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */ - /* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG, - STM32F439NI, STM32F429IG and STM32F429II Devices */ - /* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, - STM32F439NI, STM32F439IG and STM32F439II Devices */ - /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */ - /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */ - /* #define STM32F410Tx */ /*!< STM32F410T8 and STM32F410TB Devices */ - /* #define STM32F410Cx */ /*!< STM32F410C8 and STM32F410CB Devices */ - /* #define STM32F410Rx */ /*!< STM32F410R8 and STM32F410RB Devices */ - /* #define STM32F411xE */ /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */ - /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC, - and STM32F446ZE Devices */ - /* #define STM32F469xx */ /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG, - STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */ - /* #define STM32F479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG - and STM32F479NG Devices */ -#endif - -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - */ -#if !defined (USE_HAL_DRIVER) -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - /*#define USE_HAL_DRIVER */ -#endif /* USE_HAL_DRIVER */ - -/** - * @brief CMSIS Device version number V2.4.2 - */ -#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ -#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */ -#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ -#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\ - |(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\ - |(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 << 8 )\ - |(__STM32F4xx_CMSIS_DEVICE_VERSION)) - -/** - * @} - */ - -/** @addtogroup Device_Included - * @{ - */ - -#if defined(STM32F405xx) - #include "stm32f405xx.h" -#elif defined(STM32F415xx) - #include "stm32f415xx.h" -#elif defined(STM32F407xx) - #include "stm32f407xx.h" -#elif defined(STM32F417xx) - #include "stm32f417xx.h" -#elif defined(STM32F427xx) - #include "stm32f427xx.h" -#elif defined(STM32F437xx) - #include "stm32f437xx.h" -#elif defined(STM32F429xx) - #include "stm32f429xx.h" -#elif defined(STM32F439xx) - #include "stm32f439xx.h" -#elif defined(STM32F401xC) - #include "stm32f401xc.h" -#elif defined(STM32F401xE) - #include "stm32f401xe.h" -#elif defined(STM32F410Tx) - #include "stm32f410tx.h" -#elif defined(STM32F410Cx) - #include "stm32f410cx.h" -#elif defined(STM32F410Rx) - #include "stm32f410rx.h" -#elif defined(STM32F411xE) - #include "stm32f411xe.h" -#elif defined(STM32F446xx) - #include "stm32f446xx.h" -#elif defined(STM32F469xx) - #include "stm32f469xx.h" -#elif defined(STM32F479xx) - #include "stm32f479xx.h" -#else - #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)" -#endif - -/** - * @} - */ - -/** @addtogroup Exported_types - * @{ - */ -typedef enum -{ - RESET = 0, - SET = !RESET -} FlagStatus, ITStatus; - -typedef enum -{ - DISABLE = 0, - ENABLE = !DISABLE -} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum -{ - ERROR = 0, - SUCCESS = !ERROR -} ErrorStatus; - -/** - * @} - */ - - -/** @addtogroup Exported_macro - * @{ - */ -#define SET_BIT(REG, BIT) ((REG) |= (BIT)) - -#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) - -#define READ_BIT(REG, BIT) ((REG) & (BIT)) - -#define CLEAR_REG(REG) ((REG) = (0x0)) - -#define WRITE_REG(REG, VAL) ((REG) = (VAL)) - -#define READ_REG(REG) ((REG)) - -#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) - -#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) - - -/** - * @} - */ - -#if defined (USE_HAL_DRIVER) - #include "stm32f4xx_hal.h" -#endif /* USE_HAL_DRIVER */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __STM32F4xx_H */ -/** - * @} - */ - -/** - * @} - */ - - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/firmware/ChibiOS_16/os/ext/CMSIS/ST/STM32F4xx/system_stm32f4xx.h b/firmware/ChibiOS_16/os/ext/CMSIS/ST/STM32F4xx/system_stm32f4xx.h deleted file mode 100644 index fa2c803289..0000000000 --- a/firmware/ChibiOS_16/os/ext/CMSIS/ST/STM32F4xx/system_stm32f4xx.h +++ /dev/null @@ -1,122 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32f4xx.h - * @author MCD Application Team - * @version V2.4.2 - * @date 13-November-2015 - * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f4xx_system - * @{ - */ - -/** - * @brief Define to prevent recursive inclusion - */ -#ifndef __SYSTEM_STM32F4XX_H -#define __SYSTEM_STM32F4XX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup STM32F4xx_System_Includes - * @{ - */ - -/** - * @} - */ - - -/** @addtogroup STM32F4xx_System_Exported_types - * @{ - */ - /* This variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetSysClockFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Exported_Functions - * @{ - */ - -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__SYSTEM_STM32F4XX_H */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/firmware/ChibiOS_16/os/ext/CMSIS/include/arm_common_tables.h b/firmware/ChibiOS_16/os/ext/CMSIS/include/arm_common_tables.h deleted file mode 100644 index 039cc3d66b..0000000000 --- a/firmware/ChibiOS_16/os/ext/CMSIS/include/arm_common_tables.h +++ /dev/null @@ -1,136 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_common_tables.h -* -* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions -* -* Target Processor: Cortex-M4/Cortex-M3 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#ifndef _ARM_COMMON_TABLES_H -#define _ARM_COMMON_TABLES_H - -#include "arm_math.h" - -extern const uint16_t armBitRevTable[1024]; -extern const q15_t armRecipTableQ15[64]; -extern const q31_t armRecipTableQ31[64]; -//extern const q31_t realCoefAQ31[1024]; -//extern const q31_t realCoefBQ31[1024]; -extern const float32_t twiddleCoef_16[32]; -extern const float32_t twiddleCoef_32[64]; -extern const float32_t twiddleCoef_64[128]; -extern const float32_t twiddleCoef_128[256]; -extern const float32_t twiddleCoef_256[512]; -extern const float32_t twiddleCoef_512[1024]; -extern const float32_t twiddleCoef_1024[2048]; -extern const float32_t twiddleCoef_2048[4096]; -extern const float32_t twiddleCoef_4096[8192]; -#define twiddleCoef twiddleCoef_4096 -extern const q31_t twiddleCoef_16_q31[24]; -extern const q31_t twiddleCoef_32_q31[48]; -extern const q31_t twiddleCoef_64_q31[96]; -extern const q31_t twiddleCoef_128_q31[192]; -extern const q31_t twiddleCoef_256_q31[384]; -extern const q31_t twiddleCoef_512_q31[768]; -extern const q31_t twiddleCoef_1024_q31[1536]; -extern const q31_t twiddleCoef_2048_q31[3072]; -extern const q31_t twiddleCoef_4096_q31[6144]; -extern const q15_t twiddleCoef_16_q15[24]; -extern const q15_t twiddleCoef_32_q15[48]; -extern const q15_t twiddleCoef_64_q15[96]; -extern const q15_t twiddleCoef_128_q15[192]; -extern const q15_t twiddleCoef_256_q15[384]; -extern const q15_t twiddleCoef_512_q15[768]; -extern const q15_t twiddleCoef_1024_q15[1536]; -extern const q15_t twiddleCoef_2048_q15[3072]; -extern const q15_t twiddleCoef_4096_q15[6144]; -extern const float32_t twiddleCoef_rfft_32[32]; -extern const float32_t twiddleCoef_rfft_64[64]; -extern const float32_t twiddleCoef_rfft_128[128]; -extern const float32_t twiddleCoef_rfft_256[256]; -extern const float32_t twiddleCoef_rfft_512[512]; -extern const float32_t twiddleCoef_rfft_1024[1024]; -extern const float32_t twiddleCoef_rfft_2048[2048]; -extern const float32_t twiddleCoef_rfft_4096[4096]; - - -/* floating-point bit reversal tables */ -#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) -#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) -#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) -#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) -#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) -#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) -#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) -#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) -#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; - -/* fixed-point bit reversal tables */ -#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 ) -#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 ) -#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 ) -#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 ) -#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 ) -#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 ) -#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) -#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) -#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; - -/* Tables for Fast Math Sine and Cosine */ -extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; -extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; -extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; - -#endif /* ARM_COMMON_TABLES_H */ diff --git a/firmware/ChibiOS_16/os/ext/CMSIS/include/arm_const_structs.h b/firmware/ChibiOS_16/os/ext/CMSIS/include/arm_const_structs.h deleted file mode 100644 index 726d06eb69..0000000000 --- a/firmware/ChibiOS_16/os/ext/CMSIS/include/arm_const_structs.h +++ /dev/null @@ -1,79 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_const_structs.h -* -* Description: This file has constant structs that are initialized for -* user convenience. For example, some can be given as -* arguments to the arm_cfft_f32() function. -* -* Target Processor: Cortex-M4/Cortex-M3 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#ifndef _ARM_CONST_STRUCTS_H -#define _ARM_CONST_STRUCTS_H - -#include "arm_math.h" -#include "arm_common_tables.h" - - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; - - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; - - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; - -#endif diff --git a/firmware/ChibiOS_16/os/ext/CMSIS/include/arm_math.h b/firmware/ChibiOS_16/os/ext/CMSIS/include/arm_math.h deleted file mode 100644 index e4b2f62e80..0000000000 --- a/firmware/ChibiOS_16/os/ext/CMSIS/include/arm_math.h +++ /dev/null @@ -1,7556 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2015 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_math.h -* -* Description: Public header file for CMSIS DSP Library -* -* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. - * -------------------------------------------------------------------- */ - -/** - \mainpage CMSIS DSP Software Library - * - * Introduction - * ------------ - * - * This user manual describes the CMSIS DSP software library, - * a suite of common signal processing functions for use on Cortex-M processor based devices. - * - * The library is divided into a number of functions each covering a specific category: - * - Basic math functions - * - Fast math functions - * - Complex math functions - * - Filters - * - Matrix functions - * - Transforms - * - Motor control functions - * - Statistical functions - * - Support functions - * - Interpolation functions - * - * The library has separate functions for operating on 8-bit integers, 16-bit integers, - * 32-bit integer and 32-bit floating-point values. - * - * Using the Library - * ------------ - * - * The library installer contains prebuilt versions of the libraries in the Lib folder. - * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7l_math.lib (Little endian on Cortex-M7) - * - arm_cortexM7b_math.lib (Big endian on Cortex-M7) - * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) - * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) - * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) - * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) - * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+) - * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+) - * - * The library functions are declared in the public file arm_math.h which is placed in the Include folder. - * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single - * public header file arm_math.h for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. - * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or - * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. - * - * Examples - * -------- - * - * The library ships with a number of examples which demonstrate how to use the library functions. - * - * Toolchain Support - * ------------ - * - * The library has been developed and tested with MDK-ARM version 5.14.0.0 - * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. - * - * Building the Library - * ------------ - * - * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. - * - arm_cortexM_math.uvprojx - * - * - * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. - * - * Pre-processor Macros - * ------------ - * - * Each library project have differant pre-processor macros. - * - * - UNALIGNED_SUPPORT_DISABLE: - * - * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access - * - * - ARM_MATH_BIG_ENDIAN: - * - * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. - * - * - ARM_MATH_MATRIX_CHECK: - * - * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices - * - * - ARM_MATH_ROUNDING: - * - * Define macro ARM_MATH_ROUNDING for rounding on support functions - * - * - ARM_MATH_CMx: - * - * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target - * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and - * ARM_MATH_CM7 for building the library on cortex-M7. - * - * - __FPU_PRESENT: - * - * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries - * - *
- * CMSIS-DSP in ARM::CMSIS Pack - * ----------------------------- - * - * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: - * |File/Folder |Content | - * |------------------------------|------------------------------------------------------------------------| - * |\b CMSIS\\Documentation\\DSP | This documentation | - * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | - * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | - * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | - * - *
- * Revision History of CMSIS-DSP - * ------------ - * Please refer to \ref ChangeLog_pg. - * - * Copyright Notice - * ------------ - * - * Copyright (C) 2010-2015 ARM Limited. All rights reserved. - */ - - -/** - * @defgroup groupMath Basic Math Functions - */ - -/** - * @defgroup groupFastMath Fast Math Functions - * This set of functions provides a fast approximation to sine, cosine, and square root. - * As compared to most of the other functions in the CMSIS math library, the fast math functions - * operate on individual values and not arrays. - * There are separate functions for Q15, Q31, and floating-point data. - * - */ - -/** - * @defgroup groupCmplxMath Complex Math Functions - * This set of functions operates on complex data vectors. - * The data in the complex arrays is stored in an interleaved fashion - * (real, imag, real, imag, ...). - * In the API functions, the number of samples in a complex array refers - * to the number of complex values; the array contains twice this number of - * real values. - */ - -/** - * @defgroup groupFilters Filtering Functions - */ - -/** - * @defgroup groupMatrix Matrix Functions - * - * This set of functions provides basic matrix math operations. - * The functions operate on matrix data structures. For example, - * the type - * definition for the floating-point matrix structure is shown - * below: - * 
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- *
- * There are similar definitions for Q15 and Q31 data types. - * - * The structure specifies the size of the matrix and then points to - * an array of data. The array is of size numRows X numCols - * and the values are arranged in row order. That is, the - * matrix element (i, j) is stored at: - * 
- *     pData[i*numCols + j]
- *
- * - * \par Init Functions - * There is an associated initialization function for each type of matrix - * data structure. - * The initialization function sets the values of the internal structure fields. - * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() - * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. - * - * \par - * Use of the initialization function is optional. However, if initialization function is used - * then the instance structure cannot be placed into a const data section. - * To place the instance structure in a const data - * section, manually initialize the data structure. For example: - * 
- * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
- *
- * where nRows specifies the number of rows, nColumns - * specifies the number of columns, and pData points to the - * data array. - * - * \par Size Checking - * By default all of the matrix functions perform size checking on the input and - * output matrices. For example, the matrix addition function verifies that the - * two input matrices and the output matrix all have the same number of rows and - * columns. If the size check fails the functions return: - * 
- *     ARM_MATH_SIZE_MISMATCH
- *
- * Otherwise the functions return - * 
- *     ARM_MATH_SUCCESS
- *
- * There is some overhead associated with this matrix size checking. - * The matrix size checking is enabled via the \#define - * 
- *     ARM_MATH_MATRIX_CHECK
- *
- * within the library project settings. By default this macro is defined - * and size checking is enabled. By changing the project settings and - * undefining this macro size checking is eliminated and the functions - * run a bit faster. With size checking disabled the functions always - * return ARM_MATH_SUCCESS. - */ - -/** - * @defgroup groupTransforms Transform Functions - */ - -/** - * @defgroup groupController Controller Functions - */ - -/** - * @defgroup groupStats Statistics Functions - */ -/** - * @defgroup groupSupport Support Functions - */ - -/** - * @defgroup groupInterpolation Interpolation Functions - * These functions perform 1- and 2-dimensional interpolation of data. - * Linear interpolation is used for 1-dimensional data and - * bilinear interpolation is used for 2-dimensional data. - */ - -/** - * @defgroup groupExamples Examples - */ -#ifndef _ARM_MATH_H -#define _ARM_MATH_H - -#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ - -#if defined(ARM_MATH_CM7) - #include "core_cm7.h" -#elif defined (ARM_MATH_CM4) - #include "core_cm4.h" -#elif defined (ARM_MATH_CM3) - #include "core_cm3.h" -#elif defined (ARM_MATH_CM0) - #include "core_cm0.h" -#define ARM_MATH_CM0_FAMILY - #elif defined (ARM_MATH_CM0PLUS) -#include "core_cm0plus.h" - #define ARM_MATH_CM0_FAMILY -#else - #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0" -#endif - -#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ -#include "string.h" -#include "math.h" -#ifdef __cplusplus -extern "C" -{ -#endif - - - /** - * @brief Macros required for reciprocal calculation in Normalized LMS - */ - -#define DELTA_Q31 (0x100) -#define DELTA_Q15 0x5 -#define INDEX_MASK 0x0000003F -#ifndef PI -#define PI 3.14159265358979f -#endif - - /** - * @brief Macros required for SINE and COSINE Fast math approximations - */ - -#define FAST_MATH_TABLE_SIZE 512 -#define FAST_MATH_Q31_SHIFT (32 - 10) -#define FAST_MATH_Q15_SHIFT (16 - 10) -#define CONTROLLER_Q31_SHIFT (32 - 9) -#define TABLE_SIZE 256 -#define TABLE_SPACING_Q31 0x400000 -#define TABLE_SPACING_Q15 0x80 - - /** - * @brief Macros required for SINE and COSINE Controller functions - */ - /* 1.31(q31) Fixed value of 2/360 */ - /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ -#define INPUT_SPACING 0xB60B61 - - /** - * @brief Macro for Unaligned Support - */ -#ifndef UNALIGNED_SUPPORT_DISABLE - #define ALIGN4 -#else - #if defined (__GNUC__) - #define ALIGN4 __attribute__((aligned(4))) - #else - #define ALIGN4 __align(4) - #endif -#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ - - /** - * @brief Error status returned by some functions in the library. - */ - - typedef enum - { - ARM_MATH_SUCCESS = 0, /**< No error */ - ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ - ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ - ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ - ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ - ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ - ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ - } arm_status; - - /** - * @brief 8-bit fractional data type in 1.7 format. - */ - typedef int8_t q7_t; - - /** - * @brief 16-bit fractional data type in 1.15 format. - */ - typedef int16_t q15_t; - - /** - * @brief 32-bit fractional data type in 1.31 format. - */ - typedef int32_t q31_t; - - /** - * @brief 64-bit fractional data type in 1.63 format. - */ - typedef int64_t q63_t; - - /** - * @brief 32-bit floating-point type definition. - */ - typedef float float32_t; - - /** - * @brief 64-bit floating-point type definition. - */ - typedef double float64_t; - - /** - * @brief definition to read/write two 16 bit values. - */ -#if defined __CC_ARM - #define __SIMD32_TYPE int32_t __packed - #define CMSIS_UNUSED __attribute__((unused)) -#elif defined __ICCARM__ - #define __SIMD32_TYPE int32_t __packed - #define CMSIS_UNUSED -#elif defined __GNUC__ - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED __attribute__((unused)) -#elif defined __CSMC__ /* Cosmic */ - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED -#elif defined __TASKING__ - #define __SIMD32_TYPE __unaligned int32_t - #define CMSIS_UNUSED -#else - #error Unknown compiler -#endif - -#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) -#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) - -#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) - -#define __SIMD64(addr) (*(int64_t **) & (addr)) - -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) - /** - * @brief definition to pack two 16 bit values. - */ -#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ - (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) -#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ - (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) - -#endif - - - /** - * @brief definition to pack four 8 bit values. - */ -#ifndef ARM_MATH_BIG_ENDIAN - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) -#else - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) - -#endif - - - /** - * @brief Clips Q63 to Q31 values. - */ - static __INLINE q31_t clip_q63_to_q31( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; - } - - /** - * @brief Clips Q63 to Q15 values. - */ - static __INLINE q15_t clip_q63_to_q15( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); - } - - /** - * @brief Clips Q31 to Q7 values. - */ - static __INLINE q7_t clip_q31_to_q7( - q31_t x) - { - return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? - ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; - } - - /** - * @brief Clips Q31 to Q15 values. - */ - static __INLINE q15_t clip_q31_to_q15( - q31_t x) - { - return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? - ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; - } - - /** - * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. - */ - - static __INLINE q63_t mult32x64( - q63_t x, - q31_t y) - { - return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + - (((q63_t) (x >> 32) * y))); - } - - -//#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) -//#define __CLZ __clz -//#endif - -//note: function can be removed when all toolchain support __CLZ for Cortex-M0 -#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ) - - static __INLINE uint32_t __CLZ( - q31_t data); - - - static __INLINE uint32_t __CLZ( - q31_t data) - { - uint32_t count = 0; - uint32_t mask = 0x80000000; - - while((data & mask) == 0) - { - count += 1u; - mask = mask >> 1u; - } - - return (count); - - } - -#endif - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. - */ - - static __INLINE uint32_t arm_recip_q31( - q31_t in, - q31_t * dst, - q31_t * pRecipTable) - { - - uint32_t out, tempVal; - uint32_t index, i; - uint32_t signBits; - - if(in > 0) - { - signBits = __CLZ(in) - 1; - } - else - { - signBits = __CLZ(-in) - 1; - } - - /* Convert input sample to 1.31 format */ - in = in << signBits; - - /* calculation of index for initial approximated Val */ - index = (uint32_t) (in >> 24u); - index = (index & INDEX_MASK); - - /* 1.31 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (q31_t) (((q63_t) in * out) >> 31u); - tempVal = 0x7FFFFFFF - tempVal; - /* 1.31 with exp 1 */ - //out = (q31_t) (((q63_t) out * tempVal) >> 30u); - out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1u); - - } - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. - */ - static __INLINE uint32_t arm_recip_q15( - q15_t in, - q15_t * dst, - q15_t * pRecipTable) - { - - uint32_t out = 0, tempVal = 0; - uint32_t index = 0, i = 0; - uint32_t signBits = 0; - - if(in > 0) - { - signBits = __CLZ(in) - 17; - } - else - { - signBits = __CLZ(-in) - 17; - } - - /* Convert input sample to 1.15 format */ - in = in << signBits; - - /* calculation of index for initial approximated Val */ - index = in >> 8; - index = (index & INDEX_MASK); - - /* 1.15 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0; i < 2; i++) - { - tempVal = (q15_t) (((q31_t) in * out) >> 15); - tempVal = 0x7FFF - tempVal; - /* 1.15 with exp 1 */ - out = (q15_t) (((q31_t) out * tempVal) >> 14); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1); - - } - - - /* - * @brief C custom defined intrinisic function for only M0 processors - */ -#if defined(ARM_MATH_CM0_FAMILY) - - static __INLINE q31_t __SSAT( - q31_t x, - uint32_t y) - { - int32_t posMax, negMin; - uint32_t i; - - posMax = 1; - for (i = 0; i < (y - 1); i++) - { - posMax = posMax * 2; - } - - if(x > 0) - { - posMax = (posMax - 1); - - if(x > posMax) - { - x = posMax; - } - } - else - { - negMin = -posMax; - - if(x < negMin) - { - x = negMin; - } - } - return (x); - - - } - -#endif /* end of ARM_MATH_CM0_FAMILY */ - - - - /* - * @brief C custom defined intrinsic function for M3 and M0 processors - */ -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) - - /* - * @brief C custom defined QADD8 for M3 and M0 processors - */ - static __INLINE q31_t __QADD8( - q31_t x, - q31_t y) - { - - q31_t sum; - q7_t r, s, t, u; - - r = (q7_t) x; - s = (q7_t) y; - - r = __SSAT((q31_t) (r + s), 8); - s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); - t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); - u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); - - sum = - (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | - (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); - - return sum; - - } - - /* - * @brief C custom defined QSUB8 for M3 and M0 processors - */ - static __INLINE q31_t __QSUB8( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s, t, u; - - r = (q7_t) x; - s = (q7_t) y; - - r = __SSAT((r - s), 8); - s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; - t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; - u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; - - sum = - (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & - 0x000000FF); - - return sum; - } - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - static __INLINE q31_t __QADD16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (q15_t) x; - s = (q15_t) y; - - r = __SSAT(r + s, 16); - s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - - } - - /* - * @brief C custom defined SHADD16 for M3 and M0 processors - */ - static __INLINE q31_t __SHADD16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (q15_t) x; - s = (q15_t) y; - - r = ((r >> 1) + (s >> 1)); - s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - - } - - /* - * @brief C custom defined QSUB16 for M3 and M0 processors - */ - static __INLINE q31_t __QSUB16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (q15_t) x; - s = (q15_t) y; - - r = __SSAT(r - s, 16); - s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - /* - * @brief C custom defined SHSUB16 for M3 and M0 processors - */ - static __INLINE q31_t __SHSUB16( - q31_t x, - q31_t y) - { - - q31_t diff; - q31_t r, s; - - r = (q15_t) x; - s = (q15_t) y; - - r = ((r >> 1) - (s >> 1)); - s = (((x >> 17) - (y >> 17)) << 16); - - diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return diff; - } - - /* - * @brief C custom defined QASX for M3 and M0 processors - */ - static __INLINE q31_t __QASX( - q31_t x, - q31_t y) - { - - q31_t sum = 0; - - sum = - ((sum + - clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) + - clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16))); - - return sum; - } - - /* - * @brief C custom defined SHASX for M3 and M0 processors - */ - static __INLINE q31_t __SHASX( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (q15_t) x; - s = (q15_t) y; - - r = ((r >> 1) - (y >> 17)); - s = (((x >> 17) + (s >> 1)) << 16); - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - - /* - * @brief C custom defined QSAX for M3 and M0 processors - */ - static __INLINE q31_t __QSAX( - q31_t x, - q31_t y) - { - - q31_t sum = 0; - - sum = - ((sum + - clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) + - clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16))); - - return sum; - } - - /* - * @brief C custom defined SHSAX for M3 and M0 processors - */ - static __INLINE q31_t __SHSAX( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (q15_t) x; - s = (q15_t) y; - - r = ((r >> 1) + (y >> 17)); - s = (((x >> 17) - (s >> 1)) << 16); - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - /* - * @brief C custom defined SMUSDX for M3 and M0 processors - */ - static __INLINE q31_t __SMUSDX( - q31_t x, - q31_t y) - { - - return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) - - ((q15_t) (x >> 16) * (q15_t) y))); - } - - /* - * @brief C custom defined SMUADX for M3 and M0 processors - */ - static __INLINE q31_t __SMUADX( - q31_t x, - q31_t y) - { - - return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) + - ((q15_t) (x >> 16) * (q15_t) y))); - } - - /* - * @brief C custom defined QADD for M3 and M0 processors - */ - static __INLINE q31_t __QADD( - q31_t x, - q31_t y) - { - return clip_q63_to_q31((q63_t) x + y); - } - - /* - * @brief C custom defined QSUB for M3 and M0 processors - */ - static __INLINE q31_t __QSUB( - q31_t x, - q31_t y) - { - return clip_q63_to_q31((q63_t) x - y); - } - - /* - * @brief C custom defined SMLAD for M3 and M0 processors - */ - static __INLINE q31_t __SMLAD( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + - ((q15_t) x * (q15_t) y)); - } - - /* - * @brief C custom defined SMLADX for M3 and M0 processors - */ - static __INLINE q31_t __SMLADX( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) + - ((q15_t) x * (q15_t) (y >> 16))); - } - - /* - * @brief C custom defined SMLSDX for M3 and M0 processors - */ - static __INLINE q31_t __SMLSDX( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) + - ((q15_t) x * (q15_t) (y >> 16))); - } - - /* - * @brief C custom defined SMLALD for M3 and M0 processors - */ - static __INLINE q63_t __SMLALD( - q31_t x, - q31_t y, - q63_t sum) - { - - return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + - ((q15_t) x * (q15_t) y)); - } - - /* - * @brief C custom defined SMLALDX for M3 and M0 processors - */ - static __INLINE q63_t __SMLALDX( - q31_t x, - q31_t y, - q63_t sum) - { - - return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + - ((q15_t) x * (q15_t) (y >> 16)); - } - - /* - * @brief C custom defined SMUAD for M3 and M0 processors - */ - static __INLINE q31_t __SMUAD( - q31_t x, - q31_t y) - { - - return (((x >> 16) * (y >> 16)) + - (((x << 16) >> 16) * ((y << 16) >> 16))); - } - - /* - * @brief C custom defined SMUSD for M3 and M0 processors - */ - static __INLINE q31_t __SMUSD( - q31_t x, - q31_t y) - { - - return (-((x >> 16) * (y >> 16)) + - (((x << 16) >> 16) * ((y << 16) >> 16))); - } - - - /* - * @brief C custom defined SXTB16 for M3 and M0 processors - */ - static __INLINE q31_t __SXTB16( - q31_t x) - { - - return ((((x << 24) >> 24) & 0x0000FFFF) | - (((x << 8) >> 8) & 0xFFFF0000)); - } - - -#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ - - - /** - * @brief Instance structure for the Q7 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q7; - - /** - * @brief Instance structure for the Q15 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_f32; - - - /** - * @brief Processing function for the Q7 FIR filter. - * @param[in] *S points to an instance of the Q7 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q7( - const arm_fir_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 FIR filter. - * @param[in,out] *S points to an instance of the Q7 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed. - * @return none - */ - void arm_fir_init_q7( - arm_fir_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR filter. - * @param[in] *S points to an instance of the Q15 FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_fast_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q15 FIR filter. - * @param[in,out] *S points to an instance of the Q15 FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if - * numTaps is not a supported value. - */ - - arm_status arm_fir_init_q15( - arm_fir_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR filter. - * @param[in] *S points to an instance of the Q31 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_fast_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR filter. - * @param[in,out] *S points to an instance of the Q31 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return none. - */ - void arm_fir_init_q31( - arm_fir_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the floating-point FIR filter. - * @param[in] *S points to an instance of the floating-point FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_f32( - const arm_fir_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point FIR filter. - * @param[in,out] *S points to an instance of the floating-point FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return none. - */ - void arm_fir_init_f32( - arm_fir_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 Biquad cascade filter. - */ - typedef struct - { - int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - - } arm_biquad_casd_df1_inst_q15; - - - /** - * @brief Instance structure for the Q31 Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - - } arm_biquad_casd_df1_inst_q31; - - /** - * @brief Instance structure for the floating-point Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - - - } arm_biquad_casd_df1_inst_f32; - - - - /** - * @brief Processing function for the Q15 Biquad cascade filter. - * @param[in] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q15 Biquad cascade filter. - * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cascade_df1_init_q15( - arm_biquad_casd_df1_inst_q15 * S, - uint8_t numStages, - q15_t * pCoeffs, - q15_t * pState, - int8_t postShift); - - - /** - * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_fast_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 Biquad cascade filter - * @param[in] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_fast_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 Biquad cascade filter. - * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cascade_df1_init_q31( - arm_biquad_casd_df1_inst_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q31_t * pState, - int8_t postShift); - - /** - * @brief Processing function for the floating-point Biquad cascade filter. - * @param[in] *S points to an instance of the floating-point Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_f32( - const arm_biquad_casd_df1_inst_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point Biquad cascade filter. - * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_df1_init_f32( - arm_biquad_casd_df1_inst_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float32_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f32; - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float64_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f64; - - /** - * @brief Instance structure for the Q15 matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q15_t *pData; /**< points to the data of the matrix. */ - - } arm_matrix_instance_q15; - - /** - * @brief Instance structure for the Q31 matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q31_t *pData; /**< points to the data of the matrix. */ - - } arm_matrix_instance_q31; - - - - /** - * @brief Floating-point matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - /** - * @brief Floating-point, complex, matrix multiplication. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_cmplx_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15, complex, matrix multiplication. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_cmplx_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pScratch); - - /** - * @brief Q31, complex, matrix multiplication. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_cmplx_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_f32( - const arm_matrix_instance_f32 * pSrc, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_q15( - const arm_matrix_instance_q15 * pSrc, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_q31( - const arm_matrix_instance_q31 * pSrc, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @param[in] *pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - /** - * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @param[in] *pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_fast_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - /** - * @brief Q31 matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - /** - * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_fast_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - /** - * @brief Floating-point matrix scaling. - * @param[in] *pSrc points to the input matrix - * @param[in] scale scale factor - * @param[out] *pDst points to the output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_f32( - const arm_matrix_instance_f32 * pSrc, - float32_t scale, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix scaling. - * @param[in] *pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_q15( - const arm_matrix_instance_q15 * pSrc, - q15_t scaleFract, - int32_t shift, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix scaling. - * @param[in] *pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_q31( - const arm_matrix_instance_q31 * pSrc, - q31_t scaleFract, - int32_t shift, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_q31( - arm_matrix_instance_q31 * S, - uint16_t nRows, - uint16_t nColumns, - q31_t * pData); - - /** - * @brief Q15 matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_q15( - arm_matrix_instance_q15 * S, - uint16_t nRows, - uint16_t nColumns, - q15_t * pData); - - /** - * @brief Floating-point matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_f32( - arm_matrix_instance_f32 * S, - uint16_t nRows, - uint16_t nColumns, - float32_t * pData); - - - - /** - * @brief Instance structure for the Q15 PID Control. - */ - typedef struct - { - q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ -#ifdef ARM_MATH_CM0_FAMILY - q15_t A1; - q15_t A2; -#else - q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ -#endif - q15_t state[3]; /**< The state array of length 3. */ - q15_t Kp; /**< The proportional gain. */ - q15_t Ki; /**< The integral gain. */ - q15_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q15; - - /** - * @brief Instance structure for the Q31 PID Control. - */ - typedef struct - { - q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - q31_t A2; /**< The derived gain, A2 = Kd . */ - q31_t state[3]; /**< The state array of length 3. */ - q31_t Kp; /**< The proportional gain. */ - q31_t Ki; /**< The integral gain. */ - q31_t Kd; /**< The derivative gain. */ - - } arm_pid_instance_q31; - - /** - * @brief Instance structure for the floating-point PID Control. - */ - typedef struct - { - float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - float32_t A2; /**< The derived gain, A2 = Kd . */ - float32_t state[3]; /**< The state array of length 3. */ - float32_t Kp; /**< The proportional gain. */ - float32_t Ki; /**< The integral gain. */ - float32_t Kd; /**< The derivative gain. */ - } arm_pid_instance_f32; - - - - /** - * @brief Initialization function for the floating-point PID Control. - * @param[in,out] *S points to an instance of the PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_f32( - arm_pid_instance_f32 * S, - int32_t resetStateFlag); - - /** - * @brief Reset function for the floating-point PID Control. - * @param[in,out] *S is an instance of the floating-point PID Control structure - * @return none - */ - void arm_pid_reset_f32( - arm_pid_instance_f32 * S); - - - /** - * @brief Initialization function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_q31( - arm_pid_instance_q31 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q31 PID Control structure - * @return none - */ - - void arm_pid_reset_q31( - arm_pid_instance_q31 * S); - - /** - * @brief Initialization function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_q15( - arm_pid_instance_q15 * S, - int32_t resetStateFlag); - - /** - * @brief Reset function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the q15 PID Control structure - * @return none - */ - void arm_pid_reset_q15( - arm_pid_instance_q15 * S); - - - /** - * @brief Instance structure for the floating-point Linear Interpolate function. - */ - typedef struct - { - uint32_t nValues; /**< nValues */ - float32_t x1; /**< x1 */ - float32_t xSpacing; /**< xSpacing */ - float32_t *pYData; /**< pointer to the table of Y values */ - } arm_linear_interp_instance_f32; - - /** - * @brief Instance structure for the floating-point bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - float32_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_f32; - - /** - * @brief Instance structure for the Q31 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q31_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q31; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q15_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q15; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q7_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q7; - - - /** - * @brief Q7 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - - - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q15( - arm_cfft_radix2_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q15( - const arm_cfft_radix2_instance_q15 * S, - q15_t * pSrc); - - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_q15( - arm_cfft_radix4_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_q15( - const arm_cfft_radix4_instance_q15 * S, - q15_t * pSrc); - - /** - * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q31; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q31( - arm_cfft_radix2_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q31( - const arm_cfft_radix2_instance_q31 * S, - q31_t * pSrc); - - /** - * @brief Instance structure for the Q31 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q31; - -/* Deprecated */ - void arm_cfft_radix4_q31( - const arm_cfft_radix4_instance_q31 * S, - q31_t * pSrc); - -/* Deprecated */ - arm_status arm_cfft_radix4_init_q31( - arm_cfft_radix4_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix2_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_f32( - arm_cfft_radix2_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_f32( - const arm_cfft_radix2_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix4_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_f32( - arm_cfft_radix4_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_f32( - const arm_cfft_radix4_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q15; - -void arm_cfft_q15( - const arm_cfft_instance_q15 * S, - q15_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q31; - -void arm_cfft_q31( - const arm_cfft_instance_q31 * S, - q31_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_f32; - - void arm_cfft_f32( - const arm_cfft_instance_f32 * S, - float32_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the Q15 RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q15; - - arm_status arm_rfft_init_q15( - arm_rfft_instance_q15 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q15( - const arm_rfft_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst); - - /** - * @brief Instance structure for the Q31 RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q31; - - arm_status arm_rfft_init_q31( - arm_rfft_instance_q31 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q31( - const arm_rfft_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint16_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_f32; - - arm_status arm_rfft_init_f32( - arm_rfft_instance_f32 * S, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_f32( - const arm_rfft_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - -typedef struct - { - arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ - uint16_t fftLenRFFT; /**< length of the real sequence */ - float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ - } arm_rfft_fast_instance_f32 ; - -arm_status arm_rfft_fast_init_f32 ( - arm_rfft_fast_instance_f32 * S, - uint16_t fftLen); - -void arm_rfft_fast_f32( - arm_rfft_fast_instance_f32 * S, - float32_t * p, float32_t * pOut, - uint8_t ifftFlag); - - /** - * @brief Instance structure for the floating-point DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - float32_t normalize; /**< normalizing factor. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - float32_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_f32; - - /** - * @brief Initialization function for the floating-point DCT4/IDCT4. - * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. - */ - - arm_status arm_dct4_init_f32( - arm_dct4_instance_f32 * S, - arm_rfft_instance_f32 * S_RFFT, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint16_t N, - uint16_t Nby2, - float32_t normalize); - - /** - * @brief Processing function for the floating-point DCT4/IDCT4. - * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_f32( - const arm_dct4_instance_f32 * S, - float32_t * pState, - float32_t * pInlineBuffer); - - /** - * @brief Instance structure for the Q31 DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - q31_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q31; - - /** - * @brief Initialization function for the Q31 DCT4/IDCT4. - * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure - * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - - arm_status arm_dct4_init_q31( - arm_dct4_instance_q31 * S, - arm_rfft_instance_q31 * S_RFFT, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); - - /** - * @brief Processing function for the Q31 DCT4/IDCT4. - * @param[in] *S points to an instance of the Q31 DCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_q31( - const arm_dct4_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); - - /** - * @brief Instance structure for the Q15 DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - q15_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q15; - - /** - * @brief Initialization function for the Q15 DCT4/IDCT4. - * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - - arm_status arm_dct4_init_q15( - arm_dct4_instance_q15 * S, - arm_rfft_instance_q15 * S_RFFT, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize); - - /** - * @brief Processing function for the Q15 DCT4/IDCT4. - * @param[in] *S points to an instance of the Q15 DCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_q15( - const arm_dct4_instance_q15 * S, - q15_t * pState, - q15_t * pInlineBuffer); - - /** - * @brief Floating-point vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a floating-point vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scale scale factor to be applied - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_f32( - float32_t * pSrc, - float32_t scale, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q7 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q7( - q7_t * pSrc, - q7_t scaleFract, - int8_t shift, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q15 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q15( - q15_t * pSrc, - q15_t scaleFract, - int8_t shift, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q31 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q31( - q31_t * pSrc, - q31_t scaleFract, - int8_t shift, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Dot product of floating-point vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t blockSize, - float32_t * result); - - /** - * @brief Dot product of Q7 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q7( - q7_t * pSrcA, - q7_t * pSrcB, - uint32_t blockSize, - q31_t * result); - - /** - * @brief Dot product of Q15 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - /** - * @brief Dot product of Q31 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - /** - * @brief Shifts the elements of a Q7 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q7( - q7_t * pSrc, - int8_t shiftBits, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Shifts the elements of a Q15 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q15( - q15_t * pSrc, - int8_t shiftBits, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Shifts the elements of a Q31 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q31( - q31_t * pSrc, - int8_t shiftBits, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a floating-point vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_f32( - float32_t * pSrc, - float32_t offset, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q7 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q7( - q7_t * pSrc, - q7_t offset, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q15 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q15( - q15_t * pSrc, - q15_t offset, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q31 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q31( - q31_t * pSrc, - q31_t offset, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a floating-point vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q7 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q15 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q31 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - /** - * @brief Copies the elements of a floating-point vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q7 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q15 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q31 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - /** - * @brief Fills a constant value into a floating-point vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_f32( - float32_t value, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q7 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q7( - q7_t value, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q15 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q15( - q15_t value, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q31 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q31( - q31_t value, - q31_t * pDst, - uint32_t blockSize); - -/** - * @brief Convolution of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return none. - */ - - - void arm_conv_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return none. - */ - - void arm_conv_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - - /** - * @brief Convolution of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return none. - */ - - void arm_conv_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Partial convolution of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Partial convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Partial convolution of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q7 sequences - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Partial convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - - /** - * @brief Instance structure for the Q15 FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - - } arm_fir_decimate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - - } arm_fir_decimate_instance_f32; - - - - /** - * @brief Processing function for the floating-point FIR decimator. - * @param[in] *S points to an instance of the floating-point FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_f32( - const arm_fir_decimate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR decimator. - * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_f32( - arm_fir_decimate_instance_f32 * S, - uint16_t numTaps, - uint8_t M, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 FIR decimator. - * @param[in] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_fast_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @brief Initialization function for the Q15 FIR decimator. - * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_q15( - arm_fir_decimate_instance_q15 * S, - uint16_t numTaps, - uint8_t M, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator. - * @param[in] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_q31( - const arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_fast_q31( - arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR decimator. - * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_q31( - arm_fir_decimate_instance_q31 * S, - uint16_t numTaps, - uint8_t M, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - - /** - * @brief Instance structure for the Q15 FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ - } arm_fir_interpolate_instance_f32; - - - /** - * @brief Processing function for the Q15 FIR interpolator. - * @param[in] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_q15( - const arm_fir_interpolate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR interpolator. - * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_q15( - arm_fir_interpolate_instance_q15 * S, - uint8_t L, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR interpolator. - * @param[in] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_q31( - const arm_fir_interpolate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR interpolator. - * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_q31( - arm_fir_interpolate_instance_q31 * S, - uint8_t L, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR interpolator. - * @param[in] *S points to an instance of the floating-point FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_f32( - const arm_fir_interpolate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point FIR interpolator. - * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_f32( - arm_fir_interpolate_instance_f32 * S, - uint8_t L, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - /** - * @brief Instance structure for the high precision Q31 Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ - - } arm_biquad_cas_df1_32x64_ins_q31; - - - /** - * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cas_df1_32x64_q31( - const arm_biquad_cas_df1_32x64_ins_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cas_df1_32x64_init_q31( - arm_biquad_cas_df1_32x64_ins_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q63_t * pState, - uint8_t postShift); - - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f32; - - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_stereo_df2T_instance_f32; - - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f64; - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] *S points to an instance of the filter data structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df2T_f32( - const arm_biquad_cascade_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels - * @param[in] *S points to an instance of the filter data structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_stereo_df2T_f32( - const arm_biquad_cascade_stereo_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] *S points to an instance of the filter data structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df2T_f64( - const arm_biquad_cascade_df2T_instance_f64 * S, - float64_t * pSrc, - float64_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] *S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_df2T_init_f32( - arm_biquad_cascade_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] *S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_stereo_df2T_init_f32( - arm_biquad_cascade_stereo_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] *S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_df2T_init_f64( - arm_biquad_cascade_df2T_instance_f64 * S, - uint8_t numStages, - float64_t * pCoeffs, - float64_t * pState); - - - - /** - * @brief Instance structure for the Q15 FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_f32; - - /** - * @brief Initialization function for the Q15 FIR lattice filter. - * @param[in] *S points to an instance of the Q15 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_q15( - arm_fir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pCoeffs, - q15_t * pState); - - - /** - * @brief Processing function for the Q15 FIR lattice filter. - * @param[in] *S points to an instance of the Q15 FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_lattice_q15( - const arm_fir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR lattice filter. - * @param[in] *S points to an instance of the Q31 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_q31( - arm_fir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pCoeffs, - q31_t * pState); - - - /** - * @brief Processing function for the Q31 FIR lattice filter. - * @param[in] *S points to an instance of the Q31 FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_fir_lattice_q31( - const arm_fir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - -/** - * @brief Initialization function for the floating-point FIR lattice filter. - * @param[in] *S points to an instance of the floating-point FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_f32( - arm_fir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - /** - * @brief Processing function for the floating-point FIR lattice filter. - * @param[in] *S points to an instance of the floating-point FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_fir_lattice_f32( - const arm_fir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Instance structure for the Q15 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_f32; - - /** - * @brief Processing function for the floating-point IIR lattice filter. - * @param[in] *S points to an instance of the floating-point IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_f32( - const arm_iir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point IIR lattice filter. - * @param[in] *S points to an instance of the floating-point IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_init_f32( - arm_iir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pkCoeffs, - float32_t * pvCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 IIR lattice filter. - * @param[in] *S points to an instance of the Q31 IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_q31( - const arm_iir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 IIR lattice filter. - * @param[in] *S points to an instance of the Q31 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_init_q31( - arm_iir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pkCoeffs, - q31_t * pvCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 IIR lattice filter. - * @param[in] *S points to an instance of the Q15 IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_q15( - const arm_iir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 IIR lattice filter. - * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process per call. - * @return none. - */ - - void arm_iir_lattice_init_q15( - arm_iir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pkCoeffs, - q15_t * pvCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Instance structure for the floating-point LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that controls filter coefficient updates. */ - } arm_lms_instance_f32; - - /** - * @brief Processing function for floating-point LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_f32( - const arm_lms_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for floating-point LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to the coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_init_f32( - arm_lms_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - /** - * @brief Instance structure for the Q15 LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q15; - - - /** - * @brief Initialization function for the Q15 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to the coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_init_q15( - arm_lms_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint32_t postShift); - - /** - * @brief Processing function for Q15 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_q15( - const arm_lms_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - - } arm_lms_instance_q31; - - /** - * @brief Processing function for Q31 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_q31( - const arm_lms_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for Q31 LMS filter. - * @param[in] *S points to an instance of the Q31 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_init_q31( - arm_lms_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint32_t postShift); - - /** - * @brief Instance structure for the floating-point normalized LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that control filter coefficient updates. */ - float32_t energy; /**< saves previous frame energy. */ - float32_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_f32; - - /** - * @brief Processing function for floating-point normalized LMS filter. - * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_f32( - arm_lms_norm_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for floating-point normalized LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_init_f32( - arm_lms_norm_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q31_t *recipTable; /**< points to the reciprocal initial value table. */ - q31_t energy; /**< saves previous frame energy. */ - q31_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q31; - - /** - * @brief Processing function for Q31 normalized LMS filter. - * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_q31( - arm_lms_norm_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for Q31 normalized LMS filter. - * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_norm_init_q31( - arm_lms_norm_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint8_t postShift); - - /** - * @brief Instance structure for the Q15 normalized LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q15_t *recipTable; /**< Points to the reciprocal initial value table. */ - q15_t energy; /**< saves previous frame energy. */ - q15_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q15; - - /** - * @brief Processing function for Q15 normalized LMS filter. - * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_q15( - arm_lms_norm_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q15 normalized LMS filter. - * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_norm_init_q15( - arm_lms_norm_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint8_t postShift); - - /** - * @brief Correlation of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Correlation of Q15 sequences - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @return none. - */ - void arm_correlate_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - - /** - * @brief Correlation of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @return none. - */ - - void arm_correlate_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - /** - * @brief Correlation of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return none. - */ - - void arm_correlate_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Instance structure for the floating-point sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_f32; - - /** - * @brief Instance structure for the Q31 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q31; - - /** - * @brief Instance structure for the Q15 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q15; - - /** - * @brief Instance structure for the Q7 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q7; - - /** - * @brief Processing function for the floating-point sparse FIR filter. - * @param[in] *S points to an instance of the floating-point sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_f32( - arm_fir_sparse_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - float32_t * pScratchIn, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point sparse FIR filter. - * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_f32( - arm_fir_sparse_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 sparse FIR filter. - * @param[in] *S points to an instance of the Q31 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q31( - arm_fir_sparse_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - q31_t * pScratchIn, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q31( - arm_fir_sparse_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 sparse FIR filter. - * @param[in] *S points to an instance of the Q15 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] *pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q15( - arm_fir_sparse_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - q15_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q15( - arm_fir_sparse_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q7 sparse FIR filter. - * @param[in] *S points to an instance of the Q7 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] *pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q7( - arm_fir_sparse_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - q7_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q7 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q7( - arm_fir_sparse_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /* - * @brief Floating-point sin_cos function. - * @param[in] theta input value in degrees - * @param[out] *pSinVal points to the processed sine output. - * @param[out] *pCosVal points to the processed cos output. - * @return none. - */ - - void arm_sin_cos_f32( - float32_t theta, - float32_t * pSinVal, - float32_t * pCcosVal); - - /* - * @brief Q31 sin_cos function. - * @param[in] theta scaled input value in degrees - * @param[out] *pSinVal points to the processed sine output. - * @param[out] *pCosVal points to the processed cosine output. - * @return none. - */ - - void arm_sin_cos_q31( - q31_t theta, - q31_t * pSinVal, - q31_t * pCosVal); - - - /** - * @brief Floating-point complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - - /** - * @brief Floating-point complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup PID PID Motor Control - * - * A Proportional Integral Derivative (PID) controller is a generic feedback control - * loop mechanism widely used in industrial control systems. - * A PID controller is the most commonly used type of feedback controller. - * - * This set of functions implements (PID) controllers - * for Q15, Q31, and floating-point data types. The functions operate on a single sample - * of data and each call to the function returns a single processed value. - * S points to an instance of the PID control data structure. in - * is the input sample value. The functions return the output value. - * - * \par Algorithm: - * 
-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd
- * - * \par - * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant - * - * \par - * \image html PID.gif "Proportional Integral Derivative Controller" - * - * \par - * The PID controller calculates an "error" value as the difference between - * the measured output and the reference input. - * The controller attempts to minimize the error by adjusting the process control inputs. - * The proportional value determines the reaction to the current error, - * the integral value determines the reaction based on the sum of recent errors, - * and the derivative value determines the reaction based on the rate at which the error has been changing. - * - * \par Instance Structure - * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. - * A separate instance structure must be defined for each PID Controller. - * There are separate instance structure declarations for each of the 3 supported data types. - * - * \par Reset Functions - * There is also an associated reset function for each data type which clears the state array. - * - * \par Initialization Functions - * There is also an associated initialization function for each data type. - * The initialization function performs the following operations: - * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. - * - Zeros out the values in the state buffer. - * - * \par - * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. - * - * \par Fixed-Point Behavior - * Care must be taken when using the fixed-point versions of the PID Controller functions. - * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup PID - * @{ - */ - - /** - * @brief Process function for the floating-point PID Control. - * @param[in,out] *S is an instance of the floating-point PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - */ - - - static __INLINE float32_t arm_pid_f32( - arm_pid_instance_f32 * S, - float32_t in) - { - float32_t out; - - /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ - out = (S->A0 * in) + - (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q31 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 64-bit accumulator. - * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. - * Thus, if the accumulator result overflows it wraps around rather than clip. - * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. - * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. - */ - - static __INLINE q31_t arm_pid_q31( - arm_pid_instance_q31 * S, - q31_t in) - { - q63_t acc; - q31_t out; - - /* acc = A0 * x[n] */ - acc = (q63_t) S->A0 * in; - - /* acc += A1 * x[n-1] */ - acc += (q63_t) S->A1 * S->state[0]; - - /* acc += A2 * x[n-2] */ - acc += (q63_t) S->A2 * S->state[1]; - - /* convert output to 1.31 format to add y[n-1] */ - out = (q31_t) (acc >> 31u); - - /* out += y[n-1] */ - out += S->state[2]; - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using a 64-bit internal accumulator. - * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. - * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. - * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. - * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. - * Lastly, the accumulator is saturated to yield a result in 1.15 format. - */ - - static __INLINE q15_t arm_pid_q15( - arm_pid_instance_q15 * S, - q15_t in) - { - q63_t acc; - q15_t out; - -#ifndef ARM_MATH_CM0_FAMILY - __SIMD32_TYPE *vstate; - - /* Implementation of PID controller */ - - /* acc = A0 * x[n] */ - acc = (q31_t) __SMUAD(S->A0, in); - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - vstate = __SIMD32_CONST(S->state); - acc = __SMLALD(S->A1, (q31_t) *vstate, acc); - -#else - /* acc = A0 * x[n] */ - acc = ((q31_t) S->A0) * in; - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc += (q31_t) S->A1 * S->state[0]; - acc += (q31_t) S->A2 * S->state[1]; - -#endif - - /* acc += y[n-1] */ - acc += (q31_t) S->state[2] << 15; - - /* saturate the output */ - out = (q15_t) (__SSAT((acc >> 15), 16)); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @} end of PID group - */ - - - /** - * @brief Floating-point matrix inverse. - * @param[in] *src points to the instance of the input floating-point matrix structure. - * @param[out] *dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - - arm_status arm_mat_inverse_f32( - const arm_matrix_instance_f32 * src, - arm_matrix_instance_f32 * dst); - - - /** - * @brief Floating-point matrix inverse. - * @param[in] *src points to the instance of the input floating-point matrix structure. - * @param[out] *dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - - arm_status arm_mat_inverse_f64( - const arm_matrix_instance_f64 * src, - arm_matrix_instance_f64 * dst); - - - - /** - * @ingroup groupController - */ - - - /** - * @defgroup clarke Vector Clarke Transform - * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. - * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents - * in the two-phase orthogonal stator axis Ialpha and Ibeta. - * When Ialpha is superposed with Ia as shown in the figure below - * \image html clarke.gif Stator current space vector and its components in (a,b). - * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta - * can be calculated using only Ia and Ib. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeFormula.gif - * where Ia and Ib are the instantaneous stator phases and - * pIalpha and pIbeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup clarke - * @{ - */ - - /** - * - * @brief Floating-point Clarke transform - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @return none. - */ - - static __INLINE void arm_clarke_f32( - float32_t Ia, - float32_t Ib, - float32_t * pIalpha, - float32_t * pIbeta) - { - /* Calculate pIalpha using the equation, pIalpha = Ia */ - *pIalpha = Ia; - - /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ - *pIbeta = - ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); - - } - - /** - * @brief Clarke transform for Q31 version - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - - static __INLINE void arm_clarke_q31( - q31_t Ia, - q31_t Ib, - q31_t * pIalpha, - q31_t * pIbeta) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIalpha from Ia by equation pIalpha = Ia */ - *pIalpha = Ia; - - /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); - - /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ - product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); - - /* pIbeta is calculated by adding the intermediate products */ - *pIbeta = __QADD(product1, product2); - } - - /** - * @} end of clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q31 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_q7_to_q31( - q7_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_clarke Vector Inverse Clarke Transform - * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeInvFormula.gif - * where pIa and pIb are the instantaneous stator phases and - * Ialpha and Ibeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_clarke - * @{ - */ - - /** - * @brief Floating-point Inverse Clarke transform - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] *pIa points to output three-phase coordinate a - * @param[out] *pIb points to output three-phase coordinate b - * @return none. - */ - - - static __INLINE void arm_inv_clarke_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pIa, - float32_t * pIb) - { - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ - *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; - - } - - /** - * @brief Inverse Clarke transform for Q31 version - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] *pIa points to output three-phase coordinate a - * @param[out] *pIb points to output three-phase coordinate b - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the subtraction, hence there is no risk of overflow. - */ - - static __INLINE void arm_inv_clarke_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pIa, - q31_t * pIb) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); - - /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); - - /* pIb is calculated by subtracting the products */ - *pIb = __QSUB(product2, product1); - - } - - /** - * @} end of inv_clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q15 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_q7_to_q15( - q7_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup park Vector Park Transform - * - * Forward Park transform converts the input two-coordinate vector to flux and torque components. - * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents - * from the stationary to the moving reference frame and control the spatial relationship between - * the stator vector current and rotor flux vector. - * If we consider the d axis aligned with the rotor flux, the diagram below shows the - * current vector and the relationship from the two reference frames: - * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkFormula.gif - * where Ialpha and Ibeta are the stator vector components, - * pId and pIq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup park - * @{ - */ - - /** - * @brief Floating-point Park transform - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] *pId points to output rotor reference frame d - * @param[out] *pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * The function implements the forward Park transform. - * - */ - - static __INLINE void arm_park_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pId, - float32_t * pIq, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ - *pId = Ialpha * cosVal + Ibeta * sinVal; - - /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ - *pIq = -Ialpha * sinVal + Ibeta * cosVal; - - } - - /** - * @brief Park transform for Q31 version - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] *pId points to output rotor reference frame d - * @param[out] *pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition and subtraction, hence there is no risk of overflow. - */ - - - static __INLINE void arm_park_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pId, - q31_t * pIq, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Ialpha * cosVal) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * sinVal) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Ialpha * sinVal) */ - product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * cosVal) */ - product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); - - /* Calculate pId by adding the two intermediate products 1 and 2 */ - *pId = __QADD(product1, product2); - - /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ - *pIq = __QSUB(product4, product3); - } - - /** - * @} end of park group - */ - - /** - * @brief Converts the elements of the Q7 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q7_to_float( - q7_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_park Vector Inverse Park transform - * Inverse Park transform converts the input flux and torque components to two-coordinate vector. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkInvFormula.gif - * where pIalpha and pIbeta are the stator vector components, - * Id and Iq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_park - * @{ - */ - - /** - * @brief Floating-point Inverse Park transform - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - */ - - static __INLINE void arm_inv_park_f32( - float32_t Id, - float32_t Iq, - float32_t * pIalpha, - float32_t * pIbeta, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ - *pIalpha = Id * cosVal - Iq * sinVal; - - /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ - *pIbeta = Id * sinVal + Iq * cosVal; - - } - - - /** - * @brief Inverse Park transform for Q31 version - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - - - static __INLINE void arm_inv_park_q31( - q31_t Id, - q31_t Iq, - q31_t * pIalpha, - q31_t * pIbeta, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Id * cosVal) */ - product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Iq * sinVal) */ - product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Id * sinVal) */ - product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Iq * cosVal) */ - product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); - - /* Calculate pIalpha by using the two intermediate products 1 and 2 */ - *pIalpha = __QSUB(product1, product2); - - /* Calculate pIbeta by using the two intermediate products 3 and 4 */ - *pIbeta = __QADD(product4, product3); - - } - - /** - * @} end of Inverse park group - */ - - - /** - * @brief Converts the elements of the Q31 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_float( - q31_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup LinearInterpolate Linear Interpolation - * - * Linear interpolation is a method of curve fitting using linear polynomials. - * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line - * - * \par - * \image html LinearInterp.gif "Linear interpolation" - * - * \par - * A Linear Interpolate function calculates an output value(y), for the input(x) - * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) - * - * \par Algorithm: - * 
-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   *
- * - * \par - * This set of functions implements Linear interpolation process - * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single - * sample of data and each call to the function returns a single processed value. - * S points to an instance of the Linear Interpolate function data structure. - * x is the input sample value. The functions returns the output value. - * - * \par - * if x is outside of the table boundary, Linear interpolation returns first value of the table - * if x is below input range and returns last value of table if x is above range. - */ - - /** - * @addtogroup LinearInterpolate - * @{ - */ - - /** - * @brief Process function for the floating-point Linear Interpolation Function. - * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure - * @param[in] x input sample to process - * @return y processed output sample. - * - */ - - static __INLINE float32_t arm_linear_interp_f32( - arm_linear_interp_instance_f32 * S, - float32_t x) - { - - float32_t y; - float32_t x0, x1; /* Nearest input values */ - float32_t y0, y1; /* Nearest output values */ - float32_t xSpacing = S->xSpacing; /* spacing between input values */ - int32_t i; /* Index variable */ - float32_t *pYData = S->pYData; /* pointer to output table */ - - /* Calculation of index */ - i = (int32_t) ((x - S->x1) / xSpacing); - - if(i < 0) - { - /* Iniatilize output for below specified range as least output value of table */ - y = pYData[0]; - } - else if((uint32_t)i >= S->nValues) - { - /* Iniatilize output for above specified range as last output value of table */ - y = pYData[S->nValues - 1]; - } - else - { - /* Calculation of nearest input values */ - x0 = S->x1 + i * xSpacing; - x1 = S->x1 + (i + 1) * xSpacing; - - /* Read of nearest output values */ - y0 = pYData[i]; - y1 = pYData[i + 1]; - - /* Calculation of output */ - y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); - - } - - /* returns output value */ - return (y); - } - - /** - * - * @brief Process function for the Q31 Linear Interpolation Function. - * @param[in] *pYData pointer to Q31 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - - - static __INLINE q31_t arm_linear_interp_q31( - q31_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q31_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20); - - if(index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else - { - - /* 20 bits for the fractional part */ - /* shift left by 11 to keep fract in 1.31 format */ - fract = (x & 0x000FFFFF) << 11; - - /* Read two nearest output values from the index in 1.31(q31) format */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract) and y is in 2.30 format */ - y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); - - /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ - y += ((q31_t) (((q63_t) y1 * fract) >> 32)); - - /* Convert y to 1.31 format */ - return (y << 1u); - - } - - } - - /** - * - * @brief Process function for the Q15 Linear Interpolation Function. - * @param[in] *pYData pointer to Q15 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - - - static __INLINE q15_t arm_linear_interp_q15( - q15_t * pYData, - q31_t x, - uint32_t nValues) - { - q63_t y; /* output */ - q15_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20u); - - if(index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract) and y is in 13.35 format */ - y = ((q63_t) y0 * (0xFFFFF - fract)); - - /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ - y += ((q63_t) y1 * (fract)); - - /* convert y to 1.15 format */ - return (y >> 20); - } - - - } - - /** - * - * @brief Process function for the Q7 Linear Interpolation Function. - * @param[in] *pYData pointer to Q7 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - */ - - - static __INLINE q7_t arm_linear_interp_q7( - q7_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q7_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - uint32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - if (x < 0) - { - return (pYData[0]); - } - index = (x >> 20) & 0xfff; - - - if(index >= (nValues - 1)) - { - return (pYData[nValues - 1]); - } - else - { - - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index and are in 1.7(q7) format */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ - y = ((y0 * (0xFFFFF - fract))); - - /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ - y += (y1 * fract); - - /* convert y to 1.7(q7) format */ - return (y >> 20u); - - } - - } - /** - * @} end of LinearInterpolate group - */ - - /** - * @brief Fast approximation to the trigonometric sine function for floating-point data. - * @param[in] x input value in radians. - * @return sin(x). - */ - - float32_t arm_sin_f32( - float32_t x); - - /** - * @brief Fast approximation to the trigonometric sine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - - q31_t arm_sin_q31( - q31_t x); - - /** - * @brief Fast approximation to the trigonometric sine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - - q15_t arm_sin_q15( - q15_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for floating-point data. - * @param[in] x input value in radians. - * @return cos(x). - */ - - float32_t arm_cos_f32( - float32_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - - q31_t arm_cos_q31( - q31_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - - q15_t arm_cos_q15( - q15_t x); - - - /** - * @ingroup groupFastMath - */ - - - /** - * @defgroup SQRT Square Root - * - * Computes the square root of a number. - * There are separate functions for Q15, Q31, and floating-point data types. - * The square root function is computed using the Newton-Raphson algorithm. - * This is an iterative algorithm of the form: - * 
-   *      x1 = x0 - f(x0)/f'(x0)
-   *
- * where x1 is the current estimate, - * x0 is the previous estimate, and - * f'(x0) is the derivative of f() evaluated at x0. - * For the square root function, the algorithm reduces to: - * 
-   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   *
- */ - - - /** - * @addtogroup SQRT - * @{ - */ - - /** - * @brief Floating-point square root function. - * @param[in] in input value. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - - static __INLINE arm_status arm_sqrt_f32( - float32_t in, - float32_t * pOut) - { - if(in >= 0.0f) - { - -// #if __FPU_USED -#if (__FPU_USED == 1) && defined ( __CC_ARM ) - *pOut = __sqrtf(in); -#else - *pOut = sqrtf(in); -#endif - - return (ARM_MATH_SUCCESS); - } - else - { - *pOut = 0.0f; - return (ARM_MATH_ARGUMENT_ERROR); - } - - } - - - /** - * @brief Q31 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q31( - q31_t in, - q31_t * pOut); - - /** - * @brief Q15 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q15( - q15_t in, - q15_t * pOut); - - /** - * @} end of SQRT group - */ - - - - - - - /** - * @brief floating-point Circular write function. - */ - - static __INLINE void arm_circularWrite_f32( - int32_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const int32_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief floating-point Circular Read function. - */ - static __INLINE void arm_circularRead_f32( - int32_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - int32_t * dst, - int32_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (int32_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - /** - * @brief Q15 Circular write function. - */ - - static __INLINE void arm_circularWrite_q15( - q15_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q15_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief Q15 Circular Read function. - */ - static __INLINE void arm_circularRead_q15( - q15_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q15_t * dst, - q15_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q15_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update wOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q7 Circular write function. - */ - - static __INLINE void arm_circularWrite_q7( - q7_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q7_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief Q7 Circular Read function. - */ - static __INLINE void arm_circularRead_q7( - q7_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q7_t * dst, - q7_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q7_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Sum of the squares of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Sum of the squares of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Sum of the squares of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q15( - q15_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Sum of the squares of the elements of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q7( - q7_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Mean value of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_mean_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult); - - /** - * @brief Mean value of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Mean value of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Mean value of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Variance of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Variance of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Variance of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Root Mean Square of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Root Mean Square of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Root Mean Square of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Standard deviation of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Standard deviation of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Standard deviation of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Floating-point complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t numSamples, - q31_t * realResult, - q31_t * imagResult); - - /** - * @brief Q31 complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t numSamples, - q63_t * realResult, - q63_t * imagResult); - - /** - * @brief Floating-point complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t numSamples, - float32_t * realResult, - float32_t * imagResult); - - /** - * @brief Q15 complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_q15( - q15_t * pSrcCmplx, - q15_t * pSrcReal, - q15_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Q31 complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_q31( - q31_t * pSrcCmplx, - q31_t * pSrcReal, - q31_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Floating-point complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_f32( - float32_t * pSrcCmplx, - float32_t * pSrcReal, - float32_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Minimum value of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *result is output pointer - * @param[in] index is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * result, - uint32_t * index); - - /** - * @brief Minimum value of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[in] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - /** - * @brief Minimum value of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[out] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - void arm_min_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - /** - * @brief Minimum value of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[out] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q7 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q15 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q31 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a floating-point vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - /** - * @brief Q15 complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Floating-point complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Converts the elements of the floating-point vector to Q31 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q31 output vector - * @param[in] blockSize length of the input vector - * @return none. - */ - void arm_float_to_q31( - float32_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the floating-point vector to Q15 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q15 output vector - * @param[in] blockSize length of the input vector - * @return none - */ - void arm_float_to_q15( - float32_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the floating-point vector to Q7 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q7 output vector - * @param[in] blockSize length of the input vector - * @return none - */ - void arm_float_to_q7( - float32_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q15 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_q15( - q31_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the Q31 vector to Q7 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_q7( - q31_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the Q15 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_float( - q15_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q31 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_q31( - q15_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q7 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_q7( - q15_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup BilinearInterpolate Bilinear Interpolation - * - * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. - * The underlying function f(x, y) is sampled on a regular grid and the interpolation process - * determines values between the grid points. - * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. - * Bilinear interpolation is often used in image processing to rescale images. - * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. - * - * Algorithm - * \par - * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. - * For floating-point, the instance structure is defined as: - * 
-   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   *
- * - * \par - * where numRows specifies the number of rows in the table; - * numCols specifies the number of columns in the table; - * and pData points to an array of size numRows*numCols values. - * The data table pTable is organized in row order and the supplied data values fall on integer indexes. - * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. - * - * \par - * Let (x, y) specify the desired interpolation point. Then define: - * 
-   *     XF = floor(x)
-   *     YF = floor(y)
-   *
- * \par - * The interpolated output point is computed as: - * 
-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   *
- * Note that the coordinates (x, y) contain integer and fractional components. - * The integer components specify which portion of the table to use while the - * fractional components control the interpolation processor. - * - * \par - * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. - */ - - /** - * @addtogroup BilinearInterpolate - * @{ - */ - - /** - * - * @brief Floating-point bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate. - * @param[in] Y interpolation coordinate. - * @return out interpolated value. - */ - - - static __INLINE float32_t arm_bilinear_interp_f32( - const arm_bilinear_interp_instance_f32 * S, - float32_t X, - float32_t Y) - { - float32_t out; - float32_t f00, f01, f10, f11; - float32_t *pData = S->pData; - int32_t xIndex, yIndex, index; - float32_t xdiff, ydiff; - float32_t b1, b2, b3, b4; - - xIndex = (int32_t) X; - yIndex = (int32_t) Y; - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 - || yIndex > (S->numCols - 1)) - { - return (0); - } - - /* Calculation of index for two nearest points in X-direction */ - index = (xIndex - 1) + (yIndex - 1) * S->numCols; - - - /* Read two nearest points in X-direction */ - f00 = pData[index]; - f01 = pData[index + 1]; - - /* Calculation of index for two nearest points in Y-direction */ - index = (xIndex - 1) + (yIndex) * S->numCols; - - - /* Read two nearest points in Y-direction */ - f10 = pData[index]; - f11 = pData[index + 1]; - - /* Calculation of intermediate values */ - b1 = f00; - b2 = f01 - f00; - b3 = f10 - f00; - b4 = f00 - f01 - f10 + f11; - - /* Calculation of fractional part in X */ - xdiff = X - xIndex; - - /* Calculation of fractional part in Y */ - ydiff = Y - yIndex; - - /* Calculation of bi-linear interpolated output */ - out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; - - /* return to application */ - return (out); - - } - - /** - * - * @brief Q31 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q31_t arm_bilinear_interp_q31( - arm_bilinear_interp_instance_q31 * S, - q31_t X, - q31_t Y) - { - q31_t out; /* Temporary output */ - q31_t acc = 0; /* output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q31_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q31_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20u); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20u); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* shift left xfract by 11 to keep 1.31 format */ - xfract = (X & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - /* 20 bits for the fractional part */ - /* shift left yfract by 11 to keep 1.31 format */ - yfract = (Y & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ - out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); - acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); - - /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); - - /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* Convert acc to 1.31(q31) format */ - return (acc << 2u); - - } - - /** - * @brief Q15 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q15_t arm_bilinear_interp_q15( - arm_bilinear_interp_instance_q15 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q15_t x1, x2, y1, y2; /* Nearest output values */ - q31_t xfract, yfract; /* X, Y fractional parts */ - int32_t rI, cI; /* Row and column indices */ - q15_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ - - /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ - /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ - out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); - acc = ((q63_t) out * (0xFFFFF - yfract)); - - /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); - acc += ((q63_t) out * (xfract)); - - /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* acc is in 13.51 format and down shift acc by 36 times */ - /* Convert out to 1.15 format */ - return (acc >> 36); - - } - - /** - * @brief Q7 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q7_t arm_bilinear_interp_q7( - arm_bilinear_interp_instance_q7 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q7_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q7_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ - out = ((x1 * (0xFFFFF - xfract))); - acc = (((q63_t) out * (0xFFFFF - yfract))); - - /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ - out = ((x2 * (0xFFFFF - yfract))); - acc += (((q63_t) out * (xfract))); - - /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y1 * (0xFFFFF - xfract))); - acc += (((q63_t) out * (yfract))); - - /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y2 * (yfract))); - acc += (((q63_t) out * (xfract))); - - /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ - return (acc >> 40); - - } - - /** - * @} end of BilinearInterpolate group - */ - - -//SMMLAR -#define multAcc_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) - -//SMMLSR -#define multSub_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) - -//SMMULR -#define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) - -//SMMLA -#define multAcc_32x32_keep32(a, x, y) \ - a += (q31_t) (((q63_t) x * y) >> 32) - -//SMMLS -#define multSub_32x32_keep32(a, x, y) \ - a -= (q31_t) (((q63_t) x * y) >> 32) - -//SMMUL -#define mult_32x32_keep32(a, x, y) \ - a = (q31_t) (((q63_t) x * y ) >> 32) - - -#if defined ( __CC_ARM ) //Keil - -//Enter low optimization region - place directly above function definition - #ifdef ARM_MATH_CM4 - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("push") \ - _Pragma ("O1") - #else - #define LOW_OPTIMIZATION_ENTER - #endif - -//Exit low optimization region - place directly after end of function definition - #ifdef ARM_MATH_CM4 - #define LOW_OPTIMIZATION_EXIT \ - _Pragma ("pop") - #else - #define LOW_OPTIMIZATION_EXIT - #endif - -//Enter low optimization region - place directly above function definition - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - -//Exit low optimization region - place directly after end of function definition - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__ICCARM__) //IAR - -//Enter low optimization region - place directly above function definition - #ifdef ARM_MATH_CM4 - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define LOW_OPTIMIZATION_ENTER - #endif - -//Exit low optimization region - place directly after end of function definition - #define LOW_OPTIMIZATION_EXIT - -//Enter low optimization region - place directly above function definition - #ifdef ARM_MATH_CM4 - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #endif - -//Exit low optimization region - place directly after end of function definition - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__GNUC__) - - #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) - - #define LOW_OPTIMIZATION_EXIT - - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__CSMC__) // Cosmic - -#define LOW_OPTIMIZATION_ENTER -#define LOW_OPTIMIZATION_EXIT -#define IAR_ONLY_LOW_OPTIMIZATION_ENTER -#define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__TASKING__) // TASKING - -#define LOW_OPTIMIZATION_ENTER -#define LOW_OPTIMIZATION_EXIT -#define IAR_ONLY_LOW_OPTIMIZATION_ENTER -#define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#endif - - -#ifdef __cplusplus -} -#endif - - -#endif /* _ARM_MATH_H */ - -/** - * - * End of file. - */ diff --git a/firmware/ChibiOS_16/os/ext/CMSIS/include/core_cm0.h b/firmware/ChibiOS_16/os/ext/CMSIS/include/core_cm0.h deleted file mode 100644 index cf2b5d66ba..0000000000 --- a/firmware/ChibiOS_16/os/ext/CMSIS/include/core_cm0.h +++ /dev/null @@ -1,740 +0,0 @@ -/**************************************************************************//** - * @file core_cm0.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V4.10 - * @date 18. March 2015 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifndef __CORE_CM0_H_GENERIC -#define __CORE_CM0_H_GENERIC - -#ifdef __cplusplus - extern "C" { -#endif - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M0 - @{ - */ - -/* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ - __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI__VFP_SUPPORT____ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0_H_DEPENDANT -#define __CORE_CM0_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0_REV - #define __CM0_REV 0x0000 - #warning "__CM0_REV not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M0 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31 /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30 /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29 /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28 /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31 /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29 /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28 /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24 /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t _reserved0:1; /*!< bit: 0 Reserved */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) - are only accessible over DAP and not via processor. Therefore - they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if((int32_t)(IRQn) < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if((int32_t)(IRQn) < 0) { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); - } - else { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); - } -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1) { __NOP(); } /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */ - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/firmware/ChibiOS_16/os/ext/CMSIS/include/core_cm0plus.h b/firmware/ChibiOS_16/os/ext/CMSIS/include/core_cm0plus.h deleted file mode 100644 index 123cb400a2..0000000000 --- a/firmware/ChibiOS_16/os/ext/CMSIS/include/core_cm0plus.h +++ /dev/null @@ -1,854 +0,0 @@ -/**************************************************************************//** - * @file core_cm0plus.h - * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File - * @version V4.10 - * @date 18. March 2015 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifndef __CORE_CM0PLUS_H_GENERIC -#define __CORE_CM0PLUS_H_GENERIC - -#ifdef __cplusplus - extern "C" { -#endif - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex-M0+ - @{ - */ - -/* CMSIS CM0P definitions */ -#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ -#define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ - __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI__VFP_SUPPORT____ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0PLUS_H_DEPENDANT -#define __CORE_CM0PLUS_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0PLUS_REV - #define __CM0PLUS_REV 0x0000 - #warning "__CM0PLUS_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0 - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex-M0+ */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31 /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30 /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29 /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28 /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31 /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29 /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28 /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24 /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if (__VTOR_PRESENT == 1) - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if (__VTOR_PRESENT == 1) -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) - are only accessible over DAP and not via processor. Therefore - they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0+ Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if((int32_t)(IRQn) < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if((int32_t)(IRQn) < 0) { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); - } - else { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); - } -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1) { __NOP(); } /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */ - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/firmware/ChibiOS_16/os/ext/CMSIS/include/core_cm3.h b/firmware/ChibiOS_16/os/ext/CMSIS/include/core_cm3.h deleted file mode 100644 index 092ee23da9..0000000000 --- a/firmware/ChibiOS_16/os/ext/CMSIS/include/core_cm3.h +++ /dev/null @@ -1,1693 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V4.10 - * @date 18. March 2015 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - -#ifdef __cplusplus - extern "C" { -#endif - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M3 - @{ - */ - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI__VFP_SUPPORT____ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200 - #warning "__CM3_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M3 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31 /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30 /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29 /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28 /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27 /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31 /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29 /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28 /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27 /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25 /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24 /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#if (__CM3_REV < 0x0201) /* core r2p1 */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#else -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if((int32_t)IRQn < 0) { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if((int32_t)IRQn < 0) { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS))); - } - else { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS))); - } -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1) { __NOP(); } /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */ - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0UL) { __NOP(); } - ITM->PORT[0].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/firmware/ChibiOS_16/os/ext/CMSIS/include/core_cm4.h b/firmware/ChibiOS_16/os/ext/CMSIS/include/core_cm4.h deleted file mode 100644 index 9749c27d24..0000000000 --- a/firmware/ChibiOS_16/os/ext/CMSIS/include/core_cm4.h +++ /dev/null @@ -1,1858 +0,0 @@ -/**************************************************************************//** - * @file core_cm4.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V4.10 - * @date 18. March 2015 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifndef __CORE_CM4_H_GENERIC -#define __CORE_CM4_H_GENERIC - -#ifdef __cplusplus - extern "C" { -#endif - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M4 - @{ - */ - -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ - __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x04) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ -#include /* Compiler specific SIMD Intrinsics */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM4_H_DEPENDANT -#define __CORE_CM4_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM4_REV - #define __CM4_REV 0x0000 - #warning "__CM4_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0 - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M4 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31 /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30 /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29 /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28 /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27 /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16 /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31 /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29 /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28 /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27 /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25 /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24 /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16 /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register */ -#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register */ -#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register */ -#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if((int32_t)IRQn < 0) { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if((int32_t)IRQn < 0) { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS))); - } - else { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS))); - } -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1) { __NOP(); } /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */ - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0UL) { __NOP(); } - ITM->PORT[0].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/firmware/ChibiOS_16/os/ext/CMSIS/include/core_cm7.h b/firmware/ChibiOS_16/os/ext/CMSIS/include/core_cm7.h deleted file mode 100644 index 842e323f67..0000000000 --- a/firmware/ChibiOS_16/os/ext/CMSIS/include/core_cm7.h +++ /dev/null @@ -1,2397 +0,0 @@ -/**************************************************************************//** - * @file core_cm7.h - * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File - * @version V4.10 - * @date 18. March 2015 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifndef __CORE_CM7_H_GENERIC -#define __CORE_CM7_H_GENERIC - -#ifdef __cplusplus - extern "C" { -#endif - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M7 - @{ - */ - -/* CMSIS CM7 definitions */ -#define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ -#define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \ - __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x07) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ -#include /* Compiler specific SIMD Intrinsics */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM7_H_DEPENDANT -#define __CORE_CM7_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM7_REV - #define __CM7_REV 0x0000 - #warning "__CM7_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0 - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __ICACHE_PRESENT - #define __ICACHE_PRESENT 0 - #warning "__ICACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DCACHE_PRESENT - #define __DCACHE_PRESENT 0 - #warning "__DCACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DTCM_PRESENT - #define __DTCM_PRESENT 0 - #warning "__DTCM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M7 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31 /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30 /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29 /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28 /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27 /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16 /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31 /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29 /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28 /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27 /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25 /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24 /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16 /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[1]; - __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED3[93]; - __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15]; - __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ - uint32_t RESERVED5[1]; - __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1]; - __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __O uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6]; - __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1]; - __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ - -#define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ - -#define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ - -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* Cache Level ID register */ -#define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* Cache Type register */ -#define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* Cache Size ID Register */ -#define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* Cache Size Selection Register */ -#define SCB_CSSELR_LEVEL_Pos 1 /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register */ -#define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* Instruction Tightly-Coupled Memory Control Register*/ -#define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Registers */ -#define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register */ -#define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register */ -#define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ - -/* AHBS control register */ -#define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register */ -#define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ - -#define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */ -#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ - -#define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */ -#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED3[981]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ - __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register */ -#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register */ -#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register */ -#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/* Media and FP Feature Register 2 */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if((int32_t)IRQn < 0) { - SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if((int32_t)IRQn < 0) { - return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS))); - } - else { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS))); - } -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1) { __NOP(); } /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \fn uint32_t SCB_GetFPUType(void) - \brief get FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = SCB->MVFR0; - if ((mvfr0 & 0x00000FF0UL) == 0x220UL) { - return 2UL; // Double + Single precision FPU - } else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) { - return 1UL; // Single precision FPU - } else { - return 0UL; // No FPU - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## Cache functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_CacheFunctions Cache Functions - \brief Functions that configure Instruction and Data cache. - @{ - */ - -/* Cache Size ID Register Macros */ -#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) -#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) -#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) /*>> SCB_CCSIDR_LINESIZE_Pos*/ ) - - -/** \brief Enable I-Cache - - The function turns on I-Cache - */ -__STATIC_INLINE void SCB_EnableICache (void) -{ - #if (__ICACHE_PRESENT == 1) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; // invalidate I-Cache - SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; // enable I-Cache - __DSB(); - __ISB(); - #endif -} - - -/** \brief Disable I-Cache - - The function turns off I-Cache - */ -__STATIC_INLINE void SCB_DisableICache (void) -{ - #if (__ICACHE_PRESENT == 1) - __DSB(); - __ISB(); - SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; // disable I-Cache - SCB->ICIALLU = 0UL; // invalidate I-Cache - __DSB(); - __ISB(); - #endif -} - - -/** \brief Invalidate I-Cache - - The function invalidates I-Cache - */ -__STATIC_INLINE void SCB_InvalidateICache (void) -{ - #if (__ICACHE_PRESENT == 1) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; - __DSB(); - __ISB(); - #endif -} - - -/** \brief Enable D-Cache - - The function turns on D-Cache - */ -__STATIC_INLINE void SCB_EnableDCache (void) -{ - #if (__DCACHE_PRESENT == 1) - uint32_t ccsidr, sshift, wshift, sw; - uint32_t sets, ways; - - SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache - ccsidr = SCB->CCSIDR; - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL); - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL); - - __DSB(); - - do { // invalidate D-Cache - uint32_t tmpways = ways; - do { - sw = ((tmpways << wshift) | (sets << sshift)); - SCB->DCISW = sw; - } while(tmpways--); - } while(sets--); - __DSB(); - - SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; // enable D-Cache - - __DSB(); - __ISB(); - #endif -} - - -/** \brief Disable D-Cache - - The function turns off D-Cache - */ -__STATIC_INLINE void SCB_DisableDCache (void) -{ - #if (__DCACHE_PRESENT == 1) - uint32_t ccsidr, sshift, wshift, sw; - uint32_t sets, ways; - - SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache - ccsidr = SCB->CCSIDR; - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL); - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL); - - __DSB(); - - SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; // disable D-Cache - - do { // clean & invalidate D-Cache - uint32_t tmpways = ways; - do { - sw = ((tmpways << wshift) | (sets << sshift)); - SCB->DCCISW = sw; - } while(tmpways--); - } while(sets--); - - - __DSB(); - __ISB(); - #endif -} - - -/** \brief Invalidate D-Cache - - The function invalidates D-Cache - */ -__STATIC_INLINE void SCB_InvalidateDCache (void) -{ - #if (__DCACHE_PRESENT == 1) - uint32_t ccsidr, sshift, wshift, sw; - uint32_t sets, ways; - - SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache - ccsidr = SCB->CCSIDR; - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL); - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL); - - __DSB(); - - do { // invalidate D-Cache - uint32_t tmpways = ways; - do { - sw = ((tmpways << wshift) | (sets << sshift)); - SCB->DCISW = sw; - } while(tmpways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** \brief Clean D-Cache - - The function cleans D-Cache - */ -__STATIC_INLINE void SCB_CleanDCache (void) -{ - #if (__DCACHE_PRESENT == 1) - uint32_t ccsidr, sshift, wshift, sw; - uint32_t sets, ways; - - SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache - ccsidr = SCB->CCSIDR; - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL); - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL); - - __DSB(); - - do { // clean D-Cache - uint32_t tmpways = ways; - do { - sw = ((tmpways << wshift) | (sets << sshift)); - SCB->DCCSW = sw; - } while(tmpways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** \brief Clean & Invalidate D-Cache - - The function cleans and Invalidates D-Cache - */ -__STATIC_INLINE void SCB_CleanInvalidateDCache (void) -{ - #if (__DCACHE_PRESENT == 1) - uint32_t ccsidr, sshift, wshift, sw; - uint32_t sets, ways; - - SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache - ccsidr = SCB->CCSIDR; - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL); - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL); - - __DSB(); - - do { // clean & invalidate D-Cache - uint32_t tmpways = ways; - do { - sw = ((tmpways << wshift) | (sets << sshift)); - SCB->DCCISW = sw; - } while(tmpways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** - \fn void SCB_InvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize) - \brief D-Cache Invalidate by address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if (__DCACHE_PRESENT == 1) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t)addr; - uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) - - __DSB(); - - while (op_size > 0) { - SCB->DCIMVAC = op_addr; - op_addr += linesize; - op_size -= (int32_t)linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/** - \fn void SCB_CleanDCache_by_Addr(volatile uint32_t *addr, int32_t dsize) - \brief D-Cache Clean by address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if (__DCACHE_PRESENT == 1) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t) addr; - uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) - - __DSB(); - - while (op_size > 0) { - SCB->DCCMVAC = op_addr; - op_addr += linesize; - op_size -= (int32_t)linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/** - \fn void SCB_CleanInvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize) - \brief D-Cache Clean and Invalidate by address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if (__DCACHE_PRESENT == 1) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t) addr; - uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) - - __DSB(); - - while (op_size > 0) { - SCB->DCCIMVAC = op_addr; - op_addr += linesize; - op_size -= (int32_t)linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/*@} end of CMSIS_Core_CacheFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */ - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0UL) { __NOP(); } - ITM->PORT[0].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/firmware/ChibiOS_16/os/ext/CMSIS/include/core_cmFunc.h b/firmware/ChibiOS_16/os/ext/CMSIS/include/core_cmFunc.h deleted file mode 100644 index 80d03e6bb0..0000000000 --- a/firmware/ChibiOS_16/os/ext/CMSIS/include/core_cmFunc.h +++ /dev/null @@ -1,667 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V4.10 - * @date 18. March 2015 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - - -/** \brief Set Base Priority with condition - - This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - register uint32_t __regBasePriMax __ASM("basepri_max"); - __regBasePriMax = (basePri & 0xff); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ - - -#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief Enable IRQ Interrupts - - This function enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); -} - - -/** \brief Set Base Priority with condition - - This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - uint32_t result; - - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#else - /* CHIBIOS FIX */ - (void)fpscr; -#endif -} - -#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ -#include - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - - -#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ -/* Cosmic specific functions */ -#include - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - -#endif /* __CORE_CMFUNC_H */ diff --git a/firmware/ChibiOS_16/os/ext/CMSIS/include/core_cmInstr.h b/firmware/ChibiOS_16/os/ext/CMSIS/include/core_cmInstr.h deleted file mode 100644 index b1e506426e..0000000000 --- a/firmware/ChibiOS_16/os/ext/CMSIS/include/core_cmInstr.h +++ /dev/null @@ -1,921 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V4.10 - * @date 18. March 2015 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* CHIBIOS FIX */ -#if !defined(__CORTEX_SC) -#define __CORTEX_SC 0 -#endif - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() do {\ - __schedule_barrier();\ - __isb(0xF);\ - __schedule_barrier();\ - } while (0) - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() do {\ - __schedule_barrier();\ - __dsb(0xF);\ - __schedule_barrier();\ - } while (0) - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() do {\ - __schedule_barrier();\ - __dmb(0xF);\ - __schedule_barrier();\ - } while (0) - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) - #define __RBIT __rbit -#else -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end - - result = value; // r will be reversed bits of v; first get LSB of v - for (value >>= 1; value; value >>= 1) - { - result <<= 1; - result |= value & 1; - s--; - } - result <<= s; // shift when v's highest bits are zero - return(result); -} -#endif - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - - -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) - -/** \brief LDR Exclusive (8 bit) - - This function executes a exclusive LDR instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function executes a exclusive LDR instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function executes a exclusive LDR instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function executes a exclusive STR instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function executes a exclusive STR instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function executes a exclusive STR instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#define __CLREX __clrex - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Rotate Right with Extend (32 bit) - - This function moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - - \param [in] value Value to rotate - \return Rotated value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) -{ - rrx r0, r0 - bx lr -} -#endif - - -/** \brief LDRT Unprivileged (8 bit) - - This function executes a Unprivileged LDRT instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) - - -/** \brief LDRT Unprivileged (16 bit) - - This function executes a Unprivileged LDRT instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) - - -/** \brief LDRT Unprivileged (32 bit) - - This function executes a Unprivileged LDRT instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) - - -/** \brief STRT Unprivileged (8 bit) - - This function executes a Unprivileged STRT instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRBT(value, ptr) __strt(value, ptr) - - -/** \brief STRT Unprivileged (16 bit) - - This function executes a Unprivileged STRT instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRHT(value, ptr) __strt(value, ptr) - - -/** \brief STRT Unprivileged (32 bit) - - This function executes a Unprivileged STRT instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRT(value, ptr) __strt(value, ptr) - -#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constrant "l" - * Otherwise, use general registers, specified by constrant "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb 0xF":::"memory"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb 0xF":::"memory"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb 0xF":::"memory"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); -#else - uint32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32 - op2)); -} - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end - - result = value; // r will be reversed bits of v; first get LSB of v - for (value >>= 1; value; value >>= 1) - { - result <<= 1; - result |= value & 1; - s--; - } - result <<= s; // shift when v's highest bits are zero -#endif - return(result); -} - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __builtin_clz - - -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) - -/** \brief LDR Exclusive (8 bit) - - This function executes a exclusive LDR instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDR Exclusive (16 bit) - - This function executes a exclusive LDR instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDR Exclusive (32 bit) - - This function executes a exclusive LDR instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** \brief STR Exclusive (8 bit) - - This function executes a exclusive STR instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** \brief STR Exclusive (16 bit) - - This function executes a exclusive STR instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** \brief STR Exclusive (32 bit) - - This function executes a exclusive STR instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Rotate Right with Extend (32 bit) - - This function moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - - \param [in] value Value to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** \brief LDRT Unprivileged (8 bit) - - This function executes a Unprivileged LDRT instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDRT Unprivileged (16 bit) - - This function executes a Unprivileged LDRT instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDRT Unprivileged (32 bit) - - This function executes a Unprivileged LDRT instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** \brief STRT Unprivileged (8 bit) - - This function executes a Unprivileged STRT instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** \brief STRT Unprivileged (16 bit) - - This function executes a Unprivileged STRT instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** \brief STRT Unprivileged (32 bit) - - This function executes a Unprivileged STRT instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); -} - -#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ -#include - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - - -#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ -/* Cosmic specific functions */ -#include - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/firmware/ChibiOS_16/os/ext/CMSIS/include/core_cmSimd.h b/firmware/ChibiOS_16/os/ext/CMSIS/include/core_cmSimd.h deleted file mode 100644 index 7b8e37fff6..0000000000 --- a/firmware/ChibiOS_16/os/ext/CMSIS/include/core_cmSimd.h +++ /dev/null @@ -1,697 +0,0 @@ -/**************************************************************************//** - * @file core_cmSimd.h - * @brief CMSIS Cortex-M SIMD Header File - * @version V4.10 - * @date 18. March 2015 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifndef __CORE_CMSIMD_H -#define __CORE_CMSIMD_H - -#ifdef __cplusplus - extern "C" { -#endif - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32) ) >> 32)) - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ // Little endian - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else // Big endian - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ // Little endian - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else // Big endian - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ // Little endian - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else // Big endian - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ // Little endian - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else // Big endian - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ -#include - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ -/* not yet supported */ - - -#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ -/* Cosmic specific functions */ -#include - -#endif - -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CMSIMD_H */ diff --git a/firmware/ChibiOS_16/os/ext/CMSIS/readme.txt b/firmware/ChibiOS_16/os/ext/CMSIS/readme.txt deleted file mode 100644 index 280c24342f..0000000000 --- a/firmware/ChibiOS_16/os/ext/CMSIS/readme.txt +++ /dev/null @@ -1,6 +0,0 @@ -CMSIS is Copyright (C) 2011-2013 ARM Limited. All rights reserved. - -This directory contains only part of the CMSIS package. If you need the whole -package please download it from: - -http://www.arm.com diff --git a/firmware/ChibiOS_16/os/ext/readme.txt b/firmware/ChibiOS_16/os/ext/readme.txt deleted file mode 100644 index 7db6a49e0d..0000000000 --- a/firmware/ChibiOS_16/os/ext/readme.txt +++ /dev/null @@ -1,6 +0,0 @@ -All the code contained under ./os/ext is not part of the ChibiOS project and -supplied as-is without any additional warranty by ChibiOS. For ownership and -copyright statements see the license details inside the code. - -Some modules may contain changes from the ChibiOS team in order to increase -compatibility or usability with ChibiOS itself. diff --git a/firmware/ChibiOS_16/os/hal/boards/readme.txt b/firmware/ChibiOS_16/os/hal/boards/readme.txt deleted file mode 100644 index e4d39bfa1d..0000000000 --- a/firmware/ChibiOS_16/os/hal/boards/readme.txt +++ /dev/null @@ -1,6 +0,0 @@ -This directory contains the support files for various board models. If you -want to support a new board: -- Create a new directory under ./os/hal/boards, give it the name of your board. -- Copy inside the new directory the files from a similar board. -- Customize board.c, board.h and board.mk in order to correctly initialize - your board. diff --git a/firmware/ChibiOS_16/os/hal/boards/simulator/board.c b/firmware/ChibiOS_16/os/hal/boards/simulator/board.c deleted file mode 100644 index 307e0887b1..0000000000 --- a/firmware/ChibiOS_16/os/hal/boards/simulator/board.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include "hal.h" - -/** - * @brief PAL setup. - * @details Digital I/O ports static configuration as defined in @p board.h. - */ -#if HAL_USE_PAL || defined(__DOXYGEN__) -const PALConfig pal_default_config = { - {0, 0, 0}, - {0, 0, 0} -}; -#endif - -/* - * Board-specific initialization code. - */ -void boardInit(void) { -} diff --git a/firmware/ChibiOS_16/os/hal/boards/simulator/board.h b/firmware/ChibiOS_16/os/hal/boards/simulator/board.h deleted file mode 100644 index 3b9fbd2b7a..0000000000 --- a/firmware/ChibiOS_16/os/hal/boards/simulator/board.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -#if !defined(_FROM_ASM_) -#ifdef __cplusplus -extern "C" { -#endif - void boardInit(void); -#ifdef __cplusplus -} -#endif -#endif /* _FROM_ASM_ */ - -#endif /* _BOARD_H_ */ diff --git a/firmware/ChibiOS_16/os/hal/boards/simulator/board.mk b/firmware/ChibiOS_16/os/hal/boards/simulator/board.mk deleted file mode 100644 index 1c2ba70a5a..0000000000 --- a/firmware/ChibiOS_16/os/hal/boards/simulator/board.mk +++ /dev/null @@ -1,5 +0,0 @@ -# List of all the simulator board related files. -BOARDSRC = ${CHIBIOS}/os/hal/boards/simulator/board.c - -# Required include directories -BOARDINC = ${CHIBIOS}/os/hal/boards/simulator diff --git a/firmware/ChibiOS_16/os/hal/hal.mk b/firmware/ChibiOS_16/os/hal/hal.mk deleted file mode 100644 index 847acc7f9d..0000000000 --- a/firmware/ChibiOS_16/os/hal/hal.mk +++ /dev/null @@ -1,100 +0,0 @@ -# List of all the ChibiOS/HAL files, there is no need to remove the files -# from this list, you can disable parts of the HAL by editing halconf.h. -ifeq ($(USE_SMART_BUILD),yes) -HALCONF := $(strip $(shell cat halconf.h | egrep -e "define")) - -HALSRC := $(CHIBIOS)/os/hal/src/hal.c \ - $(CHIBIOS)/os/hal/src/st.c \ - $(CHIBIOS)/os/hal/src/hal_buffers.c \ - $(CHIBIOS)/os/hal/src/hal_queues.c \ - $(CHIBIOS)/os/hal/src/hal_mmcsd.c -ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),) -HALSRC += $(CHIBIOS)/os/hal/src/adc.c -endif -ifneq ($(findstring HAL_USE_CAN TRUE,$(HALCONF)),) -HALSRC += $(CHIBIOS)/os/hal/src/can.c -endif -ifneq ($(findstring HAL_USE_DAC TRUE,$(HALCONF)),) -HALSRC += $(CHIBIOS)/os/hal/src/dac.c -endif -ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),) -HALSRC += $(CHIBIOS)/os/hal/src/ext.c -endif -ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),) -HALSRC += $(CHIBIOS)/os/hal/src/gpt.c -endif -ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),) -HALSRC += $(CHIBIOS)/os/hal/src/i2c.c -endif -ifneq ($(findstring HAL_USE_I2S TRUE,$(HALCONF)),) -HALSRC += $(CHIBIOS)/os/hal/src/i2s.c -endif -ifneq ($(findstring HAL_USE_ICU TRUE,$(HALCONF)),) -HALSRC += $(CHIBIOS)/os/hal/src/icu.c -endif -ifneq ($(findstring HAL_USE_MAC TRUE,$(HALCONF)),) -HALSRC += $(CHIBIOS)/os/hal/src/mac.c -endif -ifneq ($(findstring HAL_USE_MMC_SPI TRUE,$(HALCONF)),) -HALSRC += $(CHIBIOS)/os/hal/src/mmc_spi.c -endif -ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),) -HALSRC += $(CHIBIOS)/os/hal/src/pal.c -endif -ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),) -HALSRC += $(CHIBIOS)/os/hal/src/pwm.c -endif -ifneq ($(findstring HAL_USE_RTC TRUE,$(HALCONF)),) -HALSRC += $(CHIBIOS)/os/hal/src/rtc.c -endif -ifneq ($(findstring HAL_USE_SDC TRUE,$(HALCONF)),) -HALSRC += $(CHIBIOS)/os/hal/src/sdc.c -endif -ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),) -HALSRC += $(CHIBIOS)/os/hal/src/serial.c -endif -ifneq ($(findstring HAL_USE_SERIAL_USB TRUE,$(HALCONF)),) -HALSRC += $(CHIBIOS)/os/hal/src/serial_usb.c -endif -ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),) -HALSRC += $(CHIBIOS)/os/hal/src/spi.c -endif -ifneq ($(findstring HAL_USE_UART TRUE,$(HALCONF)),) -HALSRC += $(CHIBIOS)/os/hal/src/uart.c -endif -ifneq ($(findstring HAL_USE_USB TRUE,$(HALCONF)),) -HALSRC += $(CHIBIOS)/os/hal/src/usb.c -endif -ifneq ($(findstring HAL_USE_WDG TRUE,$(HALCONF)),) -HALSRC += $(CHIBIOS)/os/hal/src/wdg.c -endif -else -HALSRC = $(CHIBIOS)/os/hal/src/hal.c \ - $(CHIBIOS)/os/hal/src/hal_buffers.c \ - $(CHIBIOS)/os/hal/src/hal_queues.c \ - $(CHIBIOS)/os/hal/src/hal_mmcsd.c \ - $(CHIBIOS)/os/hal/src/adc.c \ - $(CHIBIOS)/os/hal/src/can.c \ - $(CHIBIOS)/os/hal/src/dac.c \ - $(CHIBIOS)/os/hal/src/ext.c \ - $(CHIBIOS)/os/hal/src/gpt.c \ - $(CHIBIOS)/os/hal/src/i2c.c \ - $(CHIBIOS)/os/hal/src/i2s.c \ - $(CHIBIOS)/os/hal/src/icu.c \ - $(CHIBIOS)/os/hal/src/mac.c \ - $(CHIBIOS)/os/hal/src/mmc_spi.c \ - $(CHIBIOS)/os/hal/src/pal.c \ - $(CHIBIOS)/os/hal/src/pwm.c \ - $(CHIBIOS)/os/hal/src/rtc.c \ - $(CHIBIOS)/os/hal/src/sdc.c \ - $(CHIBIOS)/os/hal/src/serial.c \ - $(CHIBIOS)/os/hal/src/serial_usb.c \ - $(CHIBIOS)/os/hal/src/spi.c \ - $(CHIBIOS)/os/hal/src/st.c \ - $(CHIBIOS)/os/hal/src/uart.c \ - $(CHIBIOS)/os/hal/src/usb.c \ - $(CHIBIOS)/os/hal/src/wdg.c -endif - -# Required include directories -HALINC = $(CHIBIOS)/os/hal/include diff --git a/firmware/ChibiOS_16/os/hal/include/adc.h b/firmware/ChibiOS_16/os/hal/include/adc.h deleted file mode 100644 index f72b1d4b75..0000000000 --- a/firmware/ChibiOS_16/os/hal/include/adc.h +++ /dev/null @@ -1,282 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file adc.h - * @brief ADC Driver macros and structures. - * - * @addtogroup ADC - * @{ - */ - -#ifndef _ADC_H_ -#define _ADC_H_ - -#if (HAL_USE_ADC == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name ADC configuration options - * @{ - */ -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) -#define ADC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define ADC_USE_MUTUAL_EXCLUSION TRUE -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - ADC_UNINIT = 0, /**< Not initialized. */ - ADC_STOP = 1, /**< Stopped. */ - ADC_READY = 2, /**< Ready. */ - ADC_ACTIVE = 3, /**< Converting. */ - ADC_COMPLETE = 4, /**< Conversion complete. */ - ADC_ERROR = 5 /**< Conversion error. */ -} adcstate_t; - -#include "adc_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Low level driver helper macros - * @{ - */ -#if (ADC_USE_WAIT == TRUE) || defined(__DOXYGEN__) -/** - * @brief Resumes a thread waiting for a conversion completion. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -#define _adc_reset_i(adcp) \ - osalThreadResumeI(&(adcp)->thread, MSG_RESET) - -/** - * @brief Resumes a thread waiting for a conversion completion. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -#define _adc_reset_s(adcp) \ - osalThreadResumeS(&(adcp)->thread, MSG_RESET) - -/** - * @brief Wakes up the waiting thread. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -#define _adc_wakeup_isr(adcp) { \ - osalSysLockFromISR(); \ - osalThreadResumeI(&(adcp)->thread, MSG_OK); \ - osalSysUnlockFromISR(); \ -} - -/** - * @brief Wakes up the waiting thread with a timeout message. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -#define _adc_timeout_isr(adcp) { \ - osalSysLockFromISR(); \ - osalThreadResumeI(&(adcp)->thread, MSG_TIMEOUT); \ - osalSysUnlockFromISR(); \ -} - -#else /* !ADC_USE_WAIT */ -#define _adc_reset_i(adcp) -#define _adc_reset_s(adcp) -#define _adc_wakeup_isr(adcp) -#define _adc_timeout_isr(adcp) -#endif /* !ADC_USE_WAIT */ - -/** - * @brief Common ISR code, half buffer event. - * @details This code handles the portable part of the ISR code: - * - Callback invocation. - * . - * @note This macro is meant to be used in the low level drivers - * implementation only. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -#define _adc_isr_half_code(adcp) { \ - if ((adcp)->grpp->end_cb != NULL) { \ - (adcp)->grpp->end_cb(adcp, (adcp)->samples, (adcp)->depth / 2); \ - } \ -} - -/** - * @brief Common ISR code, full buffer event. - * @details This code handles the portable part of the ISR code: - * - Callback invocation. - * - Waiting thread wakeup, if any. - * - Driver state transitions. - * . - * @note This macro is meant to be used in the low level drivers - * implementation only. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -#define _adc_isr_full_code(adcp) { \ - if ((adcp)->grpp->circular) { \ - /* Callback handling.*/ \ - if ((adcp)->grpp->end_cb != NULL) { \ - if ((adcp)->depth > 1) { \ - /* Invokes the callback passing the 2nd half of the buffer.*/ \ - size_t half = (adcp)->depth / 2; \ - size_t half_index = half * (adcp)->grpp->num_channels; \ - (adcp)->grpp->end_cb(adcp, (adcp)->samples + half_index, half); \ - } \ - else { \ - /* Invokes the callback passing the whole buffer.*/ \ - (adcp)->grpp->end_cb(adcp, (adcp)->samples, (adcp)->depth); \ - } \ - } \ - } \ - else { \ - /* End conversion.*/ \ - adc_lld_stop_conversion(adcp); \ - if ((adcp)->grpp->end_cb != NULL) { \ - (adcp)->state = ADC_COMPLETE; \ - /* Invoke the callback passing the whole buffer.*/ \ - (adcp)->grpp->end_cb(adcp, (adcp)->samples, (adcp)->depth); \ - if ((adcp)->state == ADC_COMPLETE) { \ - (adcp)->state = ADC_READY; \ - (adcp)->grpp = NULL; \ - } \ - } \ - else { \ - (adcp)->state = ADC_READY; \ - (adcp)->grpp = NULL; \ - } \ - _adc_wakeup_isr(adcp); \ - } \ -} - -/** - * @brief Common ISR code, error event. - * @details This code handles the portable part of the ISR code: - * - Callback invocation. - * - Waiting thread timeout signaling, if any. - * - Driver state transitions. - * . - * @note This macro is meant to be used in the low level drivers - * implementation only. - * - * @param[in] adcp pointer to the @p ADCDriver object - * @param[in] err platform dependent error code - * - * @notapi - */ -#define _adc_isr_error_code(adcp, err) { \ - adc_lld_stop_conversion(adcp); \ - if ((adcp)->grpp->error_cb != NULL) { \ - (adcp)->state = ADC_ERROR; \ - (adcp)->grpp->error_cb(adcp, err); \ - if ((adcp)->state == ADC_ERROR) \ - (adcp)->state = ADC_READY; \ - (adcp)->grpp = NULL; \ - } \ - else { \ - (adcp)->state = ADC_READY; \ - (adcp)->grpp = NULL; \ - } \ - _adc_timeout_isr(adcp); \ -} -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void adcInit(void); - void adcObjectInit(ADCDriver *adcp); - void adcStart(ADCDriver *adcp, const ADCConfig *config); - void adcStop(ADCDriver *adcp); - void adcStartConversion(ADCDriver *adcp, - const ADCConversionGroup *grpp, - adcsample_t *samples, - size_t depth); - void adcStartConversionI(ADCDriver *adcp, - const ADCConversionGroup *grpp, - adcsample_t *samples, - size_t depth); - void adcStopConversion(ADCDriver *adcp); - void adcStopConversionI(ADCDriver *adcp); -#if ADC_USE_WAIT == TRUE - msg_t adcConvert(ADCDriver *adcp, - const ADCConversionGroup *grpp, - adcsample_t *samples, - size_t depth); -#endif -#if ADC_USE_MUTUAL_EXCLUSION == TRUE - void adcAcquireBus(ADCDriver *adcp); - void adcReleaseBus(ADCDriver *adcp); -#endif -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_ADC == TRUE */ - -#endif /* _ADC_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/include/can.h b/firmware/ChibiOS_16/os/hal/include/can.h deleted file mode 100644 index 9107bbc432..0000000000 --- a/firmware/ChibiOS_16/os/hal/include/can.h +++ /dev/null @@ -1,156 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file can.h - * @brief CAN Driver macros and structures. - * - * @addtogroup CAN - * @{ - */ - -#ifndef _CAN_H_ -#define _CAN_H_ - -#if (HAL_USE_CAN == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name CAN status flags - * @{ - */ -/** - * @brief Errors rate warning. - */ -#define CAN_LIMIT_WARNING 1U -/** - * @brief Errors rate error. - */ -#define CAN_LIMIT_ERROR 2U -/** - * @brief Bus off condition reached. - */ -#define CAN_BUS_OFF_ERROR 4U -/** - * @brief Framing error of some kind on the CAN bus. - */ -#define CAN_FRAMING_ERROR 8U -/** - * @brief Overflow in receive queue. - */ -#define CAN_OVERFLOW_ERROR 16U -/** @} */ - -/** - * @brief Special mailbox identifier. - */ -#define CAN_ANY_MAILBOX 0 - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name CAN configuration options - * @{ - */ -/** - * @brief Sleep mode related APIs inclusion switch. - * @details This option can only be enabled if the CAN implementation supports - * the sleep mode, see the macro @p CAN_SUPPORTS_SLEEP exported by - * the underlying implementation. - */ -#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) -#define CAN_USE_SLEEP_MODE TRUE -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - CAN_UNINIT = 0, /**< Not initialized. */ - CAN_STOP = 1, /**< Stopped. */ - CAN_STARTING = 2, /**< Starting. */ - CAN_READY = 3, /**< Ready. */ - CAN_SLEEP = 4 /**< Sleep state. */ -} canstate_t; - -#include "can_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Converts a mailbox index to a bit mask. - */ -#define CAN_MAILBOX_TO_MASK(mbx) (1U << ((mbx) - 1U)) -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void canInit(void); - void canObjectInit(CANDriver *canp); - void canStart(CANDriver *canp, const CANConfig *config); - void canStop(CANDriver *canp); - bool canTryTransmitI(CANDriver *canp, - canmbx_t mailbox, - const CANTxFrame *ctfp); - bool canTryReceiveI(CANDriver *canp, - canmbx_t mailbox, - CANRxFrame *crfp); - msg_t canTransmit(CANDriver *canp, - canmbx_t mailbox, - const CANTxFrame *ctfp, - systime_t timeout); - msg_t canReceive(CANDriver *canp, - canmbx_t mailbox, - CANRxFrame *crfp, - systime_t timeout); -#if CAN_USE_SLEEP_MODE - void canSleep(CANDriver *canp); - void canWakeup(CANDriver *canp); -#endif -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_CAN == TRUE */ - -#endif /* _CAN_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/include/dac.h b/firmware/ChibiOS_16/os/hal/include/dac.h deleted file mode 100644 index 082dccfd7a..0000000000 --- a/firmware/ChibiOS_16/os/hal/include/dac.h +++ /dev/null @@ -1,267 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file dac.h - * @brief DAC Driver macros and structures. - * - * @addtogroup DAC - * @{ - */ - -#ifndef _DAC_H_ -#define _DAC_H_ - -#if (HAL_USE_DAC == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name DAC configuration options - * @{ - */ -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) -#define DAC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define DAC_USE_MUTUAL_EXCLUSION TRUE -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - DAC_UNINIT = 0, /**< Not initialized. */ - DAC_STOP = 1, /**< Stopped. */ - DAC_READY = 2, /**< Ready. */ - DAC_ACTIVE = 3, /**< Exchanging data. */ - DAC_COMPLETE = 4, /**< Asynchronous operation complete. */ - DAC_ERROR = 5 /**< Error. */ -} dacstate_t; - -#include "dac_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Low level driver helper macros - * @{ - */ -#if (DAC_USE_WAIT == TRUE) || defined(__DOXYGEN__) -/** - * @brief Waits for operation completion. - * @details This function waits for the driver to complete the current - * operation. - * @pre An operation must be running while the function is invoked. - * @note No more than one thread can wait on a DAC driver using - * this function. - * - * @param[in] dacp pointer to the @p DACDriver object - * - * @notapi - */ -#define _dac_wait_s(dacp) osalThreadSuspendS(&(dacp)->thread) - -/** - * @brief Resumes a thread waiting for a conversion completion. - * - * @param[in] dacp pointer to the @p DACDriver object - * - * @notapi - */ -#define _dac_reset_i(dacp) osalThreadResumeI(&(dacp)->thread, MSG_RESET) - -/** - * @brief Resumes a thread waiting for a conversion completion. - * - * @param[in] dacp pointer to the @p DACDriver object - * - * @notapi - */ -#define _dac_reset_s(dacp) osalThreadResumeS(&(dacp)->thread, MSG_RESET) - -/** - * @brief Wakes up the waiting thread. - * - * @param[in] dacp pointer to the @p DACDriver object - * - * @notapi - */ -#define _dac_wakeup_isr(dacp) { \ - osalSysLockFromISR(); \ - osalThreadResumeI(&(dacp)->thread, MSG_OK); \ - osalSysUnlockFromISR(); \ -} - -/** - * @brief Wakes up the waiting thread with a timeout message. - * - * @param[in] dacp pointer to the @p DACDriver object - * - * @notapi - */ -#define _dac_timeout_isr(dacp) { \ - osalSysLockFromISR(); \ - osalThreadResumeI(&(dacp)->thread, MSG_TIMEOUT); \ - osalSysUnlockFromISR(); \ -} - -#else /* !DAC_USE_WAIT */ -#define _dac_wait_s(dacp) -#define _dac_reset_i(dacp) -#define _dac_reset_s(dacp) -#define _dac_wakeup_isr(dacp) -#define _dac_timeout_isr(dacp) -#endif /* !DAC_USE_WAIT */ - -/** - * @brief Common ISR code, half buffer event. - * @details This code handles the portable part of the ISR code: - * - Callback invocation. - * . - * @note This macro is meant to be used in the low level drivers - * implementation only. - * - * @param[in] dacp pointer to the @p DACDriver object - * - * @notapi - */ -#define _dac_isr_half_code(dacp) { \ - if ((dacp)->grpp->end_cb != NULL) { \ - (dacp)->grpp->end_cb(dacp, (dacp)->samples, (dacp)->depth / 2); \ - } \ -} - -/** - * @brief Common ISR code, full buffer event. - * @details This code handles the portable part of the ISR code: - * - Callback invocation. - * - Waiting thread wakeup, if any. - * - Driver state transitions. - * . - * @note This macro is meant to be used in the low level drivers - * implementation only. - * - * @param[in] dacp pointer to the @p DACDriver object - * - * @notapi - */ -#define _dac_isr_full_code(dacp) { \ - if ((dacp)->grpp->end_cb != NULL) { \ - if ((dacp)->depth > 1) { \ - /* Invokes the callback passing the 2nd half of the buffer.*/ \ - size_t half = (dacp)->depth / 2; \ - size_t half_index = half * (dacp)->grpp->num_channels; \ - (dacp)->grpp->end_cb(dacp, (dacp)->samples + half_index, half); \ - } \ - else { \ - /* Invokes the callback passing the whole buffer.*/ \ - (dacp)->grpp->end_cb(dacp, (dacp)->samples, (dacp)->depth); \ - } \ - } \ -} - -/** - * @brief Common ISR code, error event. - * @details This code handles the portable part of the ISR code: - * - Callback invocation. - * - Waiting thread timeout signaling, if any. - * - Driver state transitions. - * . - * @note This macro is meant to be used in the low level drivers - * implementation only. - * - * @param[in] dacp pointer to the @p DACDriver object - * @param[in] err platform dependent error code - * - * @notapi - */ -#define _dac_isr_error_code(dacp, err) { \ - dac_lld_stop_conversion(dacp); \ - if ((dacp)->grpp->error_cb != NULL) { \ - (dacp)->state = DAC_ERROR; \ - (dacp)->grpp->error_cb(dacp, err); \ - if ((dacp)->state == DAC_ERROR) \ - (dacp)->state = DAC_READY; \ - } \ - (dacp)->grpp = NULL; \ - _dac_timeout_isr(dacp); \ -} -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void dacInit(void); - void dacObjectInit(DACDriver *dacp); - void dacStart(DACDriver *dacp, const DACConfig *config); - void dacStop(DACDriver *dacp); - void dacPutChannelX(DACDriver *dacp, - dacchannel_t channel, - dacsample_t sample); - void dacStartConversion(DACDriver *dacp, const DACConversionGroup *grpp, - const dacsample_t *samples, size_t depth); - void dacStartConversionI(DACDriver *dacp, const DACConversionGroup *grpp, - const dacsample_t *samples, size_t depth); - void dacStopConversion(DACDriver *dacp); - void dacStopConversionI(DACDriver *dacp); -#if DAC_USE_WAIT - msg_t dacConvert(DACDriver *dacp, const DACConversionGroup *grpp, - const dacsample_t *samples, size_t depth); -#endif -#if DAC_USE_MUTUAL_EXCLUSION - void dacAcquireBus(DACDriver *dacp); - void dacReleaseBus(DACDriver *dacp); -#endif -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_DAC == TRUE */ - -#endif /* _DAC_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/include/ext.h b/firmware/ChibiOS_16/os/hal/include/ext.h deleted file mode 100644 index fc1b73d4c8..0000000000 --- a/firmware/ChibiOS_16/os/hal/include/ext.h +++ /dev/null @@ -1,150 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file ext.h - * @brief EXT Driver macros and structures. - * - * @addtogroup EXT - * @{ - */ - -#ifndef _EXT_H_ -#define _EXT_H_ - -#if (HAL_USE_EXT == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name EXT channel modes - * @{ - */ -#define EXT_CH_MODE_EDGES_MASK 3U /**< @brief Mask of edges field. */ -#define EXT_CH_MODE_DISABLED 0U /**< @brief Channel disabled. */ -#define EXT_CH_MODE_RISING_EDGE 1U /**< @brief Rising edge callback. */ -#define EXT_CH_MODE_FALLING_EDGE 2U /**< @brief Falling edge callback. */ -#define EXT_CH_MODE_BOTH_EDGES 3U /**< @brief Both edges callback. */ - -#define EXT_CH_MODE_AUTOSTART 4U /**< @brief Channel started - automatically on driver start. */ -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - EXT_UNINIT = 0, /**< Not initialized. */ - EXT_STOP = 1, /**< Stopped. */ - EXT_ACTIVE = 2 /**< Active. */ -} extstate_t; - -/** - * @brief Type of a structure representing a EXT driver. - */ -typedef struct EXTDriver EXTDriver; - -#include "ext_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Enables an EXT channel. - * - * @param[in] extp pointer to the @p EXTDriver object - * @param[in] channel channel to be enabled - * - * @iclass - */ -#define extChannelEnableI(extp, channel) ext_lld_channel_enable(extp, channel) - -/** - * @brief Disables an EXT channel. - * - * @param[in] extp pointer to the @p EXTDriver object - * @param[in] channel channel to be disabled - * - * @iclass - */ -#define extChannelDisableI(extp, channel) ext_lld_channel_disable(extp, channel) - -/** - * @brief Changes the operation mode of a channel. - * @note This function attempts to write over the current configuration - * structure that must have been not declared constant. This - * violates the @p const qualifier in @p extStart() but it is - * intentional. This function cannot be used if the configuration - * structure is declared @p const. - * - * @param[in] extp pointer to the @p EXTDriver object - * @param[in] channel channel to be changed - * @param[in] extcp new configuration for the channel - * - * @api - */ -#define extSetChannelMode(extp, channel, extcp) { \ - osalSysLock(); \ - extSetChannelModeI(extp, channel, extcp); \ - osalSysUnlock(); \ -} - -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void extInit(void); - void extObjectInit(EXTDriver *extp); - void extStart(EXTDriver *extp, const EXTConfig *config); - void extStop(EXTDriver *extp); - void extChannelEnable(EXTDriver *extp, expchannel_t channel); - void extChannelDisable(EXTDriver *extp, expchannel_t channel); - void extSetChannelModeI(EXTDriver *extp, - expchannel_t channel, - const EXTChannelConfig *extcp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_EXT == TRUE */ - -#endif /* _EXT_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/include/gpt.h b/firmware/ChibiOS_16/os/hal/include/gpt.h deleted file mode 100644 index fd221b10fb..0000000000 --- a/firmware/ChibiOS_16/os/hal/include/gpt.h +++ /dev/null @@ -1,141 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file gpt.h - * @brief GPT Driver macros and structures. - * - * @addtogroup GPT - * @{ - */ - -#ifndef _GPT_H_ -#define _GPT_H_ - -#if (HAL_USE_GPT == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - GPT_UNINIT = 0, /**< Not initialized. */ - GPT_STOP = 1, /**< Stopped. */ - GPT_READY = 2, /**< Ready. */ - GPT_CONTINUOUS = 3, /**< Active in continuous mode. */ - GPT_ONESHOT = 4 /**< Active in one shot mode. */ -} gptstate_t; - -/** - * @brief Type of a structure representing a GPT driver. - */ -typedef struct GPTDriver GPTDriver; - -/** - * @brief GPT notification callback type. - * - * @param[in] gptp pointer to a @p GPTDriver object - */ -typedef void (*gptcallback_t)(GPTDriver *gptp); - -#include "gpt_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Changes the interval of GPT peripheral. - * @details This function changes the interval of a running GPT unit. - * @pre The GPT unit must be running in continuous mode. - * @post The GPT unit interval is changed to the new value. - * - * @param[in] gptp pointer to a @p GPTDriver object - * @param[in] interval new cycle time in timer ticks - * - * @iclass - */ -#define gptChangeIntervalI(gptp, interval) { \ - gpt_lld_change_interval(gptp, interval); \ -} - -/** - * @brief Returns the interval of GPT peripheral. - * @pre The GPT unit must be running in continuous mode. - * - * @param[in] gptp pointer to a @p GPTDriver object - * @return The current interval. - * - * @xclass - */ -#define gptGetIntervalX(gptp) gpt_lld_get_interval(gptp) - -/** - * @brief Returns the counter value of GPT peripheral. - * @pre The GPT unit must be running in continuous mode. - * @note The nature of the counter is not defined, it may count upward - * or downward, it could be continuously running or not. - * - * @param[in] gptp pointer to a @p GPTDriver object - * @return The current counter value. - * - * @xclass - */ -#define gptGetCounterX(gptp) gpt_lld_get_counter(gptp) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void gptInit(void); - void gptObjectInit(GPTDriver *gptp); - void gptStart(GPTDriver *gptp, const GPTConfig *config); - void gptStop(GPTDriver *gptp); - void gptStartContinuous(GPTDriver *gptp, gptcnt_t interval); - void gptStartContinuousI(GPTDriver *gptp, gptcnt_t interval); - void gptChangeInterval(GPTDriver *gptp, gptcnt_t interval); - void gptStartOneShot(GPTDriver *gptp, gptcnt_t interval); - void gptStartOneShotI(GPTDriver *gptp, gptcnt_t interval); - void gptStopTimer(GPTDriver *gptp); - void gptStopTimerI(GPTDriver *gptp); - void gptPolledDelay(GPTDriver *gptp, gptcnt_t interval); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_GPT == TRUE */ - -#endif /* _GPT_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/include/hal.h b/firmware/ChibiOS_16/os/hal/include/hal.h deleted file mode 100644 index a000fdcbe0..0000000000 --- a/firmware/ChibiOS_16/os/hal/include/hal.h +++ /dev/null @@ -1,162 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal.h - * @brief HAL subsystem header. - * - * @addtogroup HAL - * @{ - */ - -#ifndef _HAL_H_ -#define _HAL_H_ - -#include "osal.h" -#include "board.h" -#include "halconf.h" - -#include "hal_lld.h" - -/* Abstract interfaces.*/ -#include "hal_streams.h" -#include "hal_channels.h" -#include "hal_files.h" -#include "hal_ioblock.h" -#include "hal_mmcsd.h" - -/* Shared headers.*/ -#include "hal_buffers.h" -#include "hal_queues.h" - -/* Normal drivers.*/ -#include "pal.h" -#include "adc.h" -#include "can.h" -#include "dac.h" -#include "ext.h" -#include "gpt.h" -#include "i2c.h" -#include "i2s.h" -#include "icu.h" -#include "mac.h" -#include "mii.h" -#include "pwm.h" -#include "rtc.h" -#include "serial.h" -#include "sdc.h" -#include "spi.h" -#include "uart.h" -#include "usb.h" -#include "wdg.h" - -/* - * The ST driver is a special case, it is only included if the OSAL is - * configured to require it. - */ -#if OSAL_ST_MODE != OSAL_ST_MODE_NONE -#include "st.h" -#endif - -/* Complex drivers.*/ -#include "mmc_spi.h" -#include "serial_usb.h" - -/* Community drivers.*/ -#if defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) -#if (HAL_USE_COMMUNITY == TRUE) || defined(__DOXYGEN__) -#include "hal_community.h" -#endif -#endif - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief ChibiOS/HAL identification macro. - */ -#define _CHIBIOS_HAL_ - -/** - * @brief Stable release flag. - */ -#define CH_HAL_STABLE 1 - -/** - * @name ChibiOS/HAL version identification - * @{ - */ -/** - * @brief HAL version string. - */ -#define HAL_VERSION "4.0.7" - -/** - * @brief HAL version major number. - */ -#define CH_HAL_MAJOR 4 - -/** - * @brief HAL version minor number. - */ -#define CH_HAL_MINOR 0 - -/** - * @brief HAL version patch number. - */ -#define CH_HAL_PATCH 7 -/** @} */ - -/** - * @name Return codes - * @{ - */ -#define HAL_SUCCESS false -#define HAL_FAILED true -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void halInit(void); -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/include/hal_buffers.h b/firmware/ChibiOS_16/os/hal/include/hal_buffers.h deleted file mode 100644 index 8c245fe483..0000000000 --- a/firmware/ChibiOS_16/os/hal/include/hal_buffers.h +++ /dev/null @@ -1,275 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_buffers.h - * @brief I/O Buffers macros and structures. - * - * @addtogroup HAL_BUFFERS - * @{ - */ - -#ifndef _HAL_BUFFERS_H_ -#define _HAL_BUFFERS_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a generic queue of buffers. - */ -typedef struct io_buffers_queue io_buffers_queue_t; - -/** - * @brief Double buffer notification callback type. - * - * @param[in] iodbp the buffers queue pointer - */ -typedef void (*bqnotify_t)(io_buffers_queue_t *bqp); - -/** - * @brief Structure of a generic buffers queue. - */ -struct io_buffers_queue { - /** - * @brief Queue of waiting threads. - */ - threads_queue_t waiting; - /** - * @brief Active buffers counter. - */ - volatile size_t bcounter; - /** - * @brief Buffer write pointer. - */ - uint8_t *bwrptr; - /** - * @brief Buffer read pointer. - */ - uint8_t *brdptr; - /** - * @brief Pointer to the buffers boundary. - */ - uint8_t *btop; - /** - * @brief Size of buffers. - * @note The buffer size must be not lower than sizeof(size_t) + 2 - * because the first bytes are used to store the used size of the - * buffer. - */ - size_t bsize; - /** - * @brief Number of buffers. - */ - size_t bn; - /** - * @brief Queue of buffer objects. - */ - uint8_t *buffers; - /** - * @brief Pointer for R/W sequential access. - * @note It is @p NULL if a new buffer must be fetched from the queue. - */ - uint8_t *ptr; - /** - * @brief Boundary for R/W sequential access. - */ - uint8_t *top; - /** - * @brief Data notification callback. - */ - bqnotify_t notify; - /** - * @brief Application defined field. - */ - void *link; -}; - -/** - * @brief Type of an input buffers queue. - */ -typedef io_buffers_queue_t input_buffers_queue_t; - -/** - * @brief Type of an output buffers queue. - */ -typedef io_buffers_queue_t output_buffers_queue_t; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Computes the size of a buffers queue buffer size. - * - * @param[in] n number of buffers in the queue - * @param[in] size size of the buffers - */ -#define BQ_BUFFER_SIZE(n, size) \ - (((size_t)(size) + sizeof (size_t)) * (size_t)(n)) - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Returns the queue's number of buffers. - * - * @param[in] bqp pointer to an @p io_buffers_queue_t structure - * @return The number of buffers. - * - * @xclass - */ -#define bqSizeX(bqp) ((bqp)->bn) - -/** - * @brief Return the ready buffers number. - * @details Returns the number of filled buffers if used on an input queue - * or the number of empty buffers if used on an output queue. - * - * @param[in] bqp pointer to an @p io_buffers_queue_t structure - * @return The number of ready buffers. - * - * @iclass - */ -#define bqSpaceI(bqp) ((bqp)->bcounter) - -/** - * @brief Returns the queue application-defined link. - * - * @param[in] bqp pointer to an @p io_buffers_queue_t structure - * @return The application-defined link. - * - * @special - */ -#define bqGetLinkX(bqp) ((bqp)->link) - -/** - * @brief Evaluates to @p TRUE if the specified input buffers queue is empty. - * - * @param[in] ibqp pointer to an @p input_buffers_queue_t structure - * @return The queue status. - * @retval false if the queue is not empty. - * @retval true if the queue is empty. - * - * @iclass - */ -#define ibqIsEmptyI(ibqp) ((bool)(bqSpaceI(ibqp) == 0U)) - -/** - * @brief Evaluates to @p TRUE if the specified input buffers queue is full. - * - * @param[in] ibqp pointer to an @p input_buffers_queue_t structure - * @return The queue status. - * @retval false if the queue is not full. - * @retval true if the queue is full. - * - * @iclass - */ -#define ibqIsFullI(ibqp) \ - /*lint -save -e9007 [13.5] No side effects, a pointer is passed.*/ \ - ((bool)(((ibqp)->bwrptr == (ibqp)->brdptr) && ((ibqp)->bcounter != 0U))) \ - /*lint -restore*/ - -/** - * @brief Evaluates to @p true if the specified output buffers queue is empty. - * - * @param[in] obqp pointer to an @p output_buffers_queue_t structure - * @return The queue status. - * @retval false if the queue is not empty. - * @retval true if the queue is empty. - * - * @iclass - */ -#define obqIsEmptyI(obqp) \ - /*lint -save -e9007 [13.5] No side effects, a pointer is passed.*/ \ - ((bool)(((obqp)->bwrptr == (obqp)->brdptr) && ((obqp)->bcounter != 0U))) \ - /*lint -restore*/ - -/** - * @brief Evaluates to @p true if the specified output buffers queue is full. - * - * @param[in] obqp pointer to an @p output_buffers_queue_t structure - * @return The queue status. - * @retval false if the queue is not full. - * @retval true if the queue is full. - * - * @iclass - */ -#define obqIsFullI(obqp) ((bool)(bqSpaceI(obqp) == 0U)) -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void ibqObjectInit(input_buffers_queue_t *ibqp, uint8_t *bp, - size_t size, size_t n, - bqnotify_t infy, void *link); - void ibqResetI(input_buffers_queue_t *ibqp); - uint8_t *ibqGetEmptyBufferI(input_buffers_queue_t *ibqp); - void ibqPostFullBufferI(input_buffers_queue_t *ibqp, size_t size); - msg_t ibqGetFullBufferTimeout(input_buffers_queue_t *ibqp, - systime_t timeout); - msg_t ibqGetFullBufferTimeoutS(input_buffers_queue_t *ibqp, - systime_t timeout); - void ibqReleaseEmptyBuffer(input_buffers_queue_t *ibqp); - void ibqReleaseEmptyBufferS(input_buffers_queue_t *ibqp); - msg_t ibqGetTimeout(input_buffers_queue_t *ibqp, systime_t timeout); - size_t ibqReadTimeout(input_buffers_queue_t *ibqp, uint8_t *bp, - size_t n, systime_t timeout); - void obqObjectInit(output_buffers_queue_t *obqp, uint8_t *bp, - size_t size, size_t n, - bqnotify_t onfy, void *link); - void obqResetI(output_buffers_queue_t *obqp); - uint8_t *obqGetFullBufferI(output_buffers_queue_t *obqp, - size_t *sizep); - void obqReleaseEmptyBufferI(output_buffers_queue_t *obqp); - msg_t obqGetEmptyBufferTimeout(output_buffers_queue_t *obqp, - systime_t timeout); - msg_t obqGetEmptyBufferTimeoutS(output_buffers_queue_t *obqp, - systime_t timeout); - void obqPostFullBuffer(output_buffers_queue_t *obqp, size_t size); - void obqPostFullBufferS(output_buffers_queue_t *obqp, size_t size); - msg_t obqPutTimeout(output_buffers_queue_t *obqp, uint8_t b, - systime_t timeout); - size_t obqWriteTimeout(output_buffers_queue_t *obqp, const uint8_t *bp, - size_t n, systime_t timeout); - bool obqTryFlushI(output_buffers_queue_t *obqp); - void obqFlush(output_buffers_queue_t *obqp); -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_BUFFERS_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/include/hal_channels.h b/firmware/ChibiOS_16/os/hal/include/hal_channels.h deleted file mode 100644 index b03d3d6c42..0000000000 --- a/firmware/ChibiOS_16/os/hal/include/hal_channels.h +++ /dev/null @@ -1,287 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_channels.h - * @brief I/O channels access. - * @details This header defines an abstract interface useful to access generic - * I/O serial devices in a standardized way. - * - * @addtogroup IO_CHANNEL - * @details This module defines an abstract interface for I/O channels by - * extending the @p BaseSequentialStream interface.
- * Note that no code is present, I/O channels are just abstract - * interface like structures, you should look at the systems as - * to a set of abstract C++ classes (even if written in C). - * Specific device drivers can use/extend the interface and - * implement them.
- * This system has the advantage to make the access to channels - * independent from the implementation logic. - * @{ - */ - -#ifndef _HAL_CHANNELS_H_ -#define _HAL_CHANNELS_H_ - -/** - * @brief @p BaseChannel specific methods. - */ -#define _base_channel_methods \ - _base_sequential_stream_methods \ - /* Channel put method with timeout specification.*/ \ - msg_t (*putt)(void *instance, uint8_t b, systime_t time); \ - /* Channel get method with timeout specification.*/ \ - msg_t (*gett)(void *instance, systime_t time); \ - /* Channel write method with timeout specification.*/ \ - size_t (*writet)(void *instance, const uint8_t *bp, \ - size_t n, systime_t time); \ - /* Channel read method with timeout specification.*/ \ - size_t (*readt)(void *instance, uint8_t *bp, size_t n, systime_t time); - -/** - * @brief @p BaseChannel specific data. - * @note It is empty because @p BaseChannel is only an interface without - * implementation. - */ -#define _base_channel_data \ - _base_sequential_stream_data - -/** - * @extends BaseSequentialStreamVMT - * - * @brief @p BaseChannel virtual methods table. - */ -struct BaseChannelVMT { - _base_channel_methods -}; - -/** - * @extends BaseSequentialStream - * - * @brief Base channel class. - * @details This class represents a generic, byte-wide, I/O channel. This class - * introduces generic I/O primitives with timeout specification. - */ -typedef struct { - /** @brief Virtual Methods Table.*/ - const struct BaseChannelVMT *vmt; - _base_channel_data -} BaseChannel; - -/** - * @name Macro Functions (BaseChannel) - * @{ - */ -/** - * @brief Channel blocking byte write with timeout. - * @details This function writes a byte value to a channel. If the channel - * is not ready to accept data then the calling thread is suspended. - * - * @param[in] ip pointer to a @p BaseChannel or derived class - * @param[in] b the byte value to be written to the channel - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval STM_OK if the operation succeeded. - * @retval STM_TIMEOUT if the specified time expired. - * @retval STM_RESET if the channel associated queue (if any) was reset. - * - * @api - */ -#define chnPutTimeout(ip, b, time) ((ip)->vmt->putt(ip, b, time)) - -/** - * @brief Channel blocking byte read with timeout. - * @details This function reads a byte value from a channel. If the data - * is not available then the calling thread is suspended. - * - * @param[in] ip pointer to a @p BaseChannel or derived class - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return A byte value from the queue. - * @retval STM_TIMEOUT if the specified time expired. - * @retval STM_RESET if the channel associated queue (if any) has been - * reset. - * - * @api - */ -#define chnGetTimeout(ip, time) ((ip)->vmt->gett(ip, time)) - -/** - * @brief Channel blocking write. - * @details The function writes data from a buffer to a channel. If the channel - * is not ready to accept data then the calling thread is suspended. - * - * @param[in] ip pointer to a @p BaseChannel or derived class - * @param[out] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred - * - * @return The number of bytes transferred. - * - * @api - */ -#define chnWrite(ip, bp, n) streamWrite(ip, bp, n) - -/** - * @brief Channel blocking write with timeout. - * @details The function writes data from a buffer to a channel. If the channel - * is not ready to accept data then the calling thread is suspended. - * - * @param[in] ip pointer to a @p BaseChannel or derived class - * @param[out] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The number of bytes transferred. - * - * @api - */ -#define chnWriteTimeout(ip, bp, n, time) ((ip)->vmt->writet(ip, bp, n, time)) - -/** - * @brief Channel blocking read. - * @details The function reads data from a channel into a buffer. If the data - * is not available then the calling thread is suspended. - * - * @param[in] ip pointer to a @p BaseChannel or derived class - * @param[in] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred - * - * @return The number of bytes transferred. - * - * @api - */ -#define chnRead(ip, bp, n) streamRead(ip, bp, n) - -/** - * @brief Channel blocking read with timeout. - * @details The function reads data from a channel into a buffer. If the data - * is not available then the calling thread is suspended. - * - * @param[in] ip pointer to a @p BaseChannel or derived class - * @param[in] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The number of bytes transferred. - * - * @api - */ -#define chnReadTimeout(ip, bp, n, time) ((ip)->vmt->readt(ip, bp, n, time)) -/** @} */ - -/** - * @name I/O status flags added to the event listener - * @{ - */ -/** @brief No pending conditions.*/ -#define CHN_NO_ERROR (eventflags_t)0 -/** @brief Connection happened.*/ -#define CHN_CONNECTED (eventflags_t)1 -/** @brief Disconnection happened.*/ -#define CHN_DISCONNECTED (eventflags_t)2 -/** @brief Data available in the input queue.*/ -#define CHN_INPUT_AVAILABLE (eventflags_t)4 -/** @brief Output queue empty.*/ -#define CHN_OUTPUT_EMPTY (eventflags_t)8 -/** @brief Transmission end.*/ -#define CHN_TRANSMISSION_END (eventflags_t)16 -/** @} */ - -/** - * @brief @p BaseAsynchronousChannel specific methods. - */ -#define _base_asynchronous_channel_methods \ - _base_channel_methods \ - -/** - * @brief @p BaseAsynchronousChannel specific data. - */ -#define _base_asynchronous_channel_data \ - _base_channel_data \ - /* I/O condition event source.*/ \ - event_source_t event; - -/** - * @extends BaseChannelVMT - * - * @brief @p BaseAsynchronousChannel virtual methods table. - */ -struct BaseAsynchronousChannelVMT { - _base_asynchronous_channel_methods -}; - -/** - * @extends BaseChannel - * - * @brief Base asynchronous channel class. - * @details This class extends @p BaseChannel by adding event sources fields - * for asynchronous I/O for use in an event-driven environment. - */ -typedef struct { - /** @brief Virtual Methods Table.*/ - const struct BaseAsynchronousChannelVMT *vmt; - _base_asynchronous_channel_data -} BaseAsynchronousChannel; - -/** - * @name Macro Functions (BaseAsynchronousChannel) - * @{ - */ -/** - * @brief Returns the I/O condition event source. - * @details The event source is broadcasted when an I/O condition happens. - * - * @param[in] ip pointer to a @p BaseAsynchronousChannel or derived - * class - * @return A pointer to an @p EventSource object. - * - * @api - */ -#define chnGetEventSource(ip) (&((ip)->event)) - -/** - * @brief Adds status flags to the listeners's flags mask. - * @details This function is usually called from the I/O ISRs in order to - * notify I/O conditions such as data events, errors, signal - * changes etc. - * - * @param[in] ip pointer to a @p BaseAsynchronousChannel or derived - * class - * @param[in] flags condition flags to be added to the listener flags mask - * - * @iclass - */ -#define chnAddFlagsI(ip, flags) { \ - osalEventBroadcastFlagsI(&(ip)->event, flags); \ -} -/** @} */ - -#endif /* _HAL_CHANNELS_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/include/hal_files.h b/firmware/ChibiOS_16/os/hal/include/hal_files.h deleted file mode 100644 index f8b321f578..0000000000 --- a/firmware/ChibiOS_16/os/hal/include/hal_files.h +++ /dev/null @@ -1,238 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_files.h - * @brief Data files. - * @details This header defines abstract interfaces useful to access generic - * data files in a standardized way. - * - * @addtogroup HAL_FILES - * @details This module define an abstract interface for generic data files by - * extending the @p BaseSequentialStream interface. Note that no code - * is present, data files are just abstract interface-like structures, - * you should look at the systems as to a set of abstract C++ classes - * (even if written in C). This system has the advantage to make the - * access to streams independent from the implementation logic.
- * The data files interface can be used as base class for high level - * object types such as an API for a File System implementation. - * @{ - */ - -#ifndef _HAL_FILES_H_ -#define _HAL_FILES_H_ - -/** - * @name Files return codes - * @{ - */ -/** - * @brief No error return code. - */ -#define FILE_OK STM_OK - -/** - * @brief Error code from the file stream methods. - */ -#define FILE_ERROR STM_TIMEOUT - -/** - * @brief End-of-file condition for file get/put methods. - */ -#define FILE_EOF STM_RESET -/** @} */ - -/** - * @brief File offset type. - */ -typedef uint32_t fileoffset_t; - -/** - * @brief FileStream specific methods. - */ -#define _file_stream_methods \ - _base_sequential_stream_methods \ - /* File close method.*/ \ - msg_t (*close)(void *instance); \ - /* Get last error code method.*/ \ - msg_t (*geterror)(void *instance); \ - /* File get size method.*/ \ - msg_t (*getsize)(void *instance); \ - /* File get current position method.*/ \ - msg_t (*getposition)(void *instance); \ - /* File seek method.*/ \ - msg_t (*lseek)(void *instance, fileoffset_t offset); - -/** - * @brief @p FileStream specific data. - * @note It is empty because @p FileStream is only an interface - * without implementation. - */ -#define _file_stream_data \ - _base_sequential_stream_data - -/** - * @extends BaseSequentialStreamVMT - * - * @brief @p FileStream virtual methods table. - */ -struct FileStreamVMT { - _file_stream_methods -}; - -/** - * @extends BaseSequentialStream - * - * @brief Base file stream class. - * @details This class represents a generic file data stream. - */ -typedef struct { - /** @brief Virtual Methods Table.*/ - const struct FileStreamVMT *vmt; - _file_stream_data -} FileStream; - -/** - * @name Macro Functions (FileStream) - * @{ - */ -/** - * @brief File stream write. - * @details The function writes data from a buffer to a file stream. - * - * @param[in] ip pointer to a @p FileStream or derived class - * @param[in] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred - * @return The number of bytes transferred. The return value can - * be less than the specified number of bytes if an - * end-of-file condition has been met. - * @retval FILE_ERROR operation failed. - * - * @api - */ -#define fileStreamWrite(ip, bp, n) streamWrite(ip, bp, n) - -/** - * @brief File stream read. - * @details The function reads data from a file stream into a buffer. - * - * @param[in] ip pointer to a @p FileStream or derived class - * @param[out] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred - * @return The number of bytes transferred. The return value can - * be less than the specified number of bytes if an - * end-of-file condition has been met. - * @retval FILE_ERROR operation failed. - * - * @api - */ -#define fileStreamRead(ip, bp, n) streamRead(ip, bp, n) - -/** - * @brief File stream blocking byte write. - * @details This function writes a byte value to a channel. If the channel - * is not ready to accept data then the calling thread is suspended. - * - * @param[in] ip pointer to a @p FileStream or derived class - * @param[in] b the byte value to be written to the channel - * - * @return The operation status. - * @retval FILE_OK if the operation succeeded. - * @retval FILE_ERROR operation failed. - * @retval FILE_EOF if an end-of-file condition has been met. - * - * @api - */ -#define fileStreamPut(ip, b) streamPut(ip, b) - -/** - * @brief File stream blocking byte read. - * @details This function reads a byte value from a channel. If the data - * is not available then the calling thread is suspended. - * - * @param[in] ip pointer to a @p FileStream or derived class - * - * @return A byte value from the queue. - * @retval FILE_ERROR operation failed. - * @retval FILE_EOF if an end-of-file condition has been met. - * - * @api - */ -#define fileStreamGet(ip) streamGet(ip) - -/** - * @brief File Stream close. - * @details The function closes a file stream. - * - * @param[in] ip pointer to a @p FileStream or derived class - * @return The operation status. - * @retval FILE_OK no error. - * @retval FILE_ERROR operation failed. - * - * @api - */ -#define fileStreamClose(ip) ((ip)->vmt->close(ip)) - -/** - * @brief Returns an implementation dependent error code. - * @pre The previously called function must have returned @p FILE_ERROR. - * - * @param[in] ip pointer to a @p FileStream or derived class - * @return Implementation dependent error code. - * - * @api - */ -#define fileStreamGetError(ip) ((ip)->vmt->geterror(ip)) - -/** - * @brief Returns the current file size. - * - * @param[in] ip pointer to a @p FileStream or derived class - * @return The file size. - * @retval FILE_ERROR operation failed. - * - * @api - */ -#define fileStreamGetSize(ip) ((ip)->vmt->getsize(ip)) - -/** - * @brief Returns the current file pointer position. - * - * @param[in] ip pointer to a @p FileStream or derived class - * @return The current position inside the file. - * @retval FILE_ERROR operation failed. - * - * @api - */ -#define fileStreamGetPosition(ip) ((ip)->vmt->getposition(ip)) - -/** - * @brief Moves the file current pointer to an absolute position. - * - * @param[in] ip pointer to a @p FileStream or derived class - * @param[in] offset new absolute position - * @return The operation status. - * @retval FILE_OK no error. - * @retval FILE_ERROR operation failed. - * - * @api - */ -#define fileStreamSeek(ip, offset) ((ip)->vmt->lseek(ip, offset)) -/** @} */ - -#endif /* _HAL_FILES_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/include/hal_ioblock.h b/firmware/ChibiOS_16/os/hal/include/hal_ioblock.h deleted file mode 100644 index b1e2266711..0000000000 --- a/firmware/ChibiOS_16/os/hal/include/hal_ioblock.h +++ /dev/null @@ -1,265 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_ioblock.h - * @brief I/O block devices access. - * @details This header defines an abstract interface useful to access generic - * I/O block devices in a standardized way. - * - * @addtogroup IO_BLOCK - * @details This module defines an abstract interface for accessing generic - * block devices.
- * Note that no code is present, just abstract interfaces-like - * structures, you should look at the system as to a set of - * abstract C++ classes (even if written in C). This system - * has then advantage to make the access to block devices - * independent from the implementation logic. - * @{ - */ - -#ifndef _HAL_IOBLOCK_H_ -#define _HAL_IOBLOCK_H_ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - BLK_UNINIT = 0, /**< Not initialized. */ - BLK_STOP = 1, /**< Stopped. */ - BLK_ACTIVE = 2, /**< Interface active. */ - BLK_CONNECTING = 3, /**< Connection in progress. */ - BLK_DISCONNECTING = 4, /**< Disconnection in progress. */ - BLK_READY = 5, /**< Device ready. */ - BLK_READING = 6, /**< Read operation in progress. */ - BLK_WRITING = 7, /**< Write operation in progress. */ - BLK_SYNCING = 8 /**< Sync. operation in progress. */ -} blkstate_t; - -/** - * @brief Block device info. - */ -typedef struct { - uint32_t blk_size; /**< @brief Block size in bytes. */ - uint32_t blk_num; /**< @brief Total number of blocks. */ -} BlockDeviceInfo; - -/** - * @brief @p BaseBlockDevice specific methods. - */ -#define _base_block_device_methods \ - /* Removable media detection.*/ \ - bool (*is_inserted)(void *instance); \ - /* Removable write protection detection.*/ \ - bool (*is_protected)(void *instance); \ - /* Connection to the block device.*/ \ - bool (*connect)(void *instance); \ - /* Disconnection from the block device.*/ \ - bool (*disconnect)(void *instance); \ - /* Reads one or more blocks.*/ \ - bool (*read)(void *instance, uint32_t startblk, \ - uint8_t *buffer, uint32_t n); \ - /* Writes one or more blocks.*/ \ - bool (*write)(void *instance, uint32_t startblk, \ - const uint8_t *buffer, uint32_t n); \ - /* Write operations synchronization.*/ \ - bool (*sync)(void *instance); \ - /* Obtains info about the media.*/ \ - bool (*get_info)(void *instance, BlockDeviceInfo *bdip); - -/** - * @brief @p BaseBlockDevice specific data. - */ -#define _base_block_device_data \ - /* Driver state.*/ \ - blkstate_t state; - -/** - * @brief @p BaseBlockDevice virtual methods table. - */ -struct BaseBlockDeviceVMT { - _base_block_device_methods -}; - -/** - * @brief Base block device class. - * @details This class represents a generic, block-accessible, device. - */ -typedef struct { - /** @brief Virtual Methods Table.*/ - const struct BaseBlockDeviceVMT *vmt; - _base_block_device_data -} BaseBlockDevice; - -/** - * @name Macro Functions (BaseBlockDevice) - * @{ - */ -/** - * @brief Returns the driver state. - * @note Can be called in ISR context. - * - * @param[in] ip pointer to a @p BaseBlockDevice or derived class - * - * @return The driver state. - * - * @special - */ -#define blkGetDriverState(ip) ((ip)->state) - -/** - * @brief Determines if the device is transferring data. - * @note Can be called in ISR context. - * - * @param[in] ip pointer to a @p BaseBlockDevice or derived class - * - * @return The driver state. - * @retval FALSE the device is not transferring data. - * @retval TRUE the device not transferring data. - * - * @special - */ -#define blkIsTransferring(ip) ((((ip)->state) == BLK_CONNECTING) || \ - (((ip)->state) == BLK_DISCONNECTING) || \ - (((ip)->state) == BLK_READING) || \ - (((ip)->state) == BLK_WRITING)) - -/** - * @brief Returns the media insertion status. - * @note On some implementations this function can only be called if the - * device is not transferring data. - * The function @p blkIsTransferring() should be used before calling - * this function. - * - * @param[in] ip pointer to a @p BaseBlockDevice or derived class - * - * @return The media state. - * @retval FALSE media not inserted. - * @retval TRUE media inserted. - * - * @api - */ -#define blkIsInserted(ip) ((ip)->vmt->is_inserted(ip)) - -/** - * @brief Returns the media write protection status. - * - * @param[in] ip pointer to a @p BaseBlockDevice or derived class - * - * @return The media state. - * @retval FALSE writable media. - * @retval TRUE non writable media. - * - * @api - */ -#define blkIsWriteProtected(ip) ((ip)->vmt->is_protected(ip)) - -/** - * @brief Performs the initialization procedure on the block device. - * @details This function should be performed before I/O operations can be - * attempted on the block device and after insertion has been - * confirmed using @p blkIsInserted(). - * - * @param[in] ip pointer to a @p BaseBlockDevice or derived class - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @api - */ -#define blkConnect(ip) ((ip)->vmt->connect(ip)) - -/** - * @brief Terminates operations on the block device. - * @details This operation safely terminates operations on the block device. - * - * @param[in] ip pointer to a @p BaseBlockDevice or derived class - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @api - */ -#define blkDisconnect(ip) ((ip)->vmt->disconnect(ip)) - -/** - * @brief Reads one or more blocks. - * - * @param[in] ip pointer to a @p BaseBlockDevice or derived class - * @param[in] startblk first block to read - * @param[out] buf pointer to the read buffer - * @param[in] n number of blocks to read - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @api - */ -#define blkRead(ip, startblk, buf, n) \ - ((ip)->vmt->read(ip, startblk, buf, n)) - -/** - * @brief Writes one or more blocks. - * - * @param[in] ip pointer to a @p BaseBlockDevice or derived class - * @param[in] startblk first block to write - * @param[out] buf pointer to the write buffer - * @param[in] n number of blocks to write - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @api - */ -#define blkWrite(ip, startblk, buf, n) \ - ((ip)->vmt->write(ip, startblk, buf, n)) - -/** - * @brief Ensures write synchronization. - * - * @param[in] ip pointer to a @p BaseBlockDevice or derived class - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @api - */ -#define blkSync(ip) ((ip)->vmt->sync(ip)) - -/** - * @brief Returns a media information structure. - * - * @param[in] ip pointer to a @p BaseBlockDevice or derived class - * @param[out] bdip pointer to a @p BlockDeviceInfo structure - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @api - */ -#define blkGetInfo(ip, bdip) ((ip)->vmt->get_info(ip, bdip)) - -/** @} */ - -#endif /* _HAL_IOBLOCK_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/include/hal_mmcsd.h b/firmware/ChibiOS_16/os/hal/include/hal_mmcsd.h deleted file mode 100644 index 18a78e0da1..0000000000 --- a/firmware/ChibiOS_16/os/hal/include/hal_mmcsd.h +++ /dev/null @@ -1,498 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_mmcsd.h - * @brief MMC/SD cards common header. - * @details This header defines an abstract interface useful to access MMC/SD - * I/O block devices in a standardized way. - * - * @addtogroup MMCSD - * @{ - */ - -#ifndef _HAL_MMCSD_H_ -#define _HAL_MMCSD_H_ - -#if (HAL_USE_MMC_SPI == TRUE) || (HAL_USE_SDC == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Fixed block size for MMC/SD block devices. - */ -#define MMCSD_BLOCK_SIZE 512U - -/** - * @brief Mask of error bits in R1 responses. - */ -#define MMCSD_R1_ERROR_MASK 0xFDFFE008U - -/** - * @brief Fixed pattern for CMD8. - */ -#define MMCSD_CMD8_PATTERN 0x000001AAU - -/** - * @name SD/MMC status conditions - * @{ - */ -#define MMCSD_STS_IDLE 0U -#define MMCSD_STS_READY 1U -#define MMCSD_STS_IDENT 2U -#define MMCSD_STS_STBY 3U -#define MMCSD_STS_TRAN 4U -#define MMCSD_STS_DATA 5U -#define MMCSD_STS_RCV 6U -#define MMCSD_STS_PRG 7U -#define MMCSD_STS_DIS 8U -/** @} */ - -/** - * @name SD/MMC commands - * @{ - */ -#define MMCSD_CMD_GO_IDLE_STATE 0U -#define MMCSD_CMD_INIT 1U -#define MMCSD_CMD_ALL_SEND_CID 2U -#define MMCSD_CMD_SEND_RELATIVE_ADDR 3U -#define MMCSD_CMD_SET_BUS_WIDTH 6U -#define MMCSD_CMD_SWITCH MMCSD_CMD_SET_BUS_WIDTH -#define MMCSD_CMD_SEL_DESEL_CARD 7U -#define MMCSD_CMD_SEND_IF_COND 8U -#define MMCSD_CMD_SEND_EXT_CSD MMCSD_CMD_SEND_IF_COND -#define MMCSD_CMD_SEND_CSD 9U -#define MMCSD_CMD_SEND_CID 10U -#define MMCSD_CMD_STOP_TRANSMISSION 12U -#define MMCSD_CMD_SEND_STATUS 13U -#define MMCSD_CMD_SET_BLOCKLEN 16U -#define MMCSD_CMD_READ_SINGLE_BLOCK 17U -#define MMCSD_CMD_READ_MULTIPLE_BLOCK 18U -#define MMCSD_CMD_SET_BLOCK_COUNT 23U -#define MMCSD_CMD_WRITE_BLOCK 24U -#define MMCSD_CMD_WRITE_MULTIPLE_BLOCK 25U -#define MMCSD_CMD_ERASE_RW_BLK_START 32U -#define MMCSD_CMD_ERASE_RW_BLK_END 33U -#define MMCSD_CMD_ERASE 38U -#define MMCSD_CMD_APP_OP_COND 41U -#define MMCSD_CMD_LOCK_UNLOCK 42U -#define MMCSD_CMD_APP_CMD 55U -#define MMCSD_CMD_READ_OCR 58U -/** @} */ - -/** - * @name CSD record offsets - */ -/** - * @brief Slice position of values in CSD register. - */ -/* CSD for MMC */ -#define MMCSD_CSD_MMC_CSD_STRUCTURE_SLICE 127U,126U -#define MMCSD_CSD_MMC_SPEC_VERS_SLICE 125U,122U -#define MMCSD_CSD_MMC_TAAC_SLICE 119U,112U -#define MMCSD_CSD_MMC_NSAC_SLICE 111U,104U -#define MMCSD_CSD_MMC_TRAN_SPEED_SLICE 103U,96U -#define MMCSD_CSD_MMC_CCC_SLICE 95U,84U -#define MMCSD_CSD_MMC_READ_BL_LEN_SLICE 83U,80U -#define MMCSD_CSD_MMC_READ_BL_PARTIAL_SLICE 79U,79U -#define MMCSD_CSD_MMC_WRITE_BLK_MISALIGN_SLICE 78U,78U -#define MMCSD_CSD_MMC_READ_BLK_MISALIGN_SLICE 77U,77U -#define MMCSD_CSD_MMC_DSR_IMP_SLICE 76U,76U -#define MMCSD_CSD_MMC_C_SIZE_SLICE 73U,62U -#define MMCSD_CSD_MMC_VDD_R_CURR_MIN_SLICE 61U,59U -#define MMCSD_CSD_MMC_VDD_R_CURR_MAX_SLICE 58U,56U -#define MMCSD_CSD_MMC_VDD_W_CURR_MIN_SLICE 55U,53U -#define MMCSD_CSD_MMC_VDD_W_CURR_MAX_SLICE 52U,50U -#define MMCSD_CSD_MMC_C_SIZE_MULT_SLICE 49U,47U -#define MMCSD_CSD_MMC_ERASE_GRP_SIZE_SLICE 46U,42U -#define MMCSD_CSD_MMC_ERASE_GRP_MULT_SLICE 41U,37U -#define MMCSD_CSD_MMC_WP_GRP_SIZE_SLICE 36U,32U -#define MMCSD_CSD_MMC_WP_GRP_ENABLE_SLICE 31U,31U -#define MMCSD_CSD_MMC_DEFAULT_ECC_SLICE 30U,29U -#define MMCSD_CSD_MMC_R2W_FACTOR_SLICE 28U,26U -#define MMCSD_CSD_MMC_WRITE_BL_LEN_SLICE 25U,22U -#define MMCSD_CSD_MMC_WRITE_BL_PARTIAL_SLICE 21U,21U -#define MMCSD_CSD_MMC_CONTENT_PROT_APP_SLICE 16U,16U -#define MMCSD_CSD_MMC_FILE_FORMAT_GRP_SLICE 15U,15U -#define MMCSD_CSD_MMC_COPY_SLICE 14U,14U -#define MMCSD_CSD_MMC_PERM_WRITE_PROTECT_SLICE 13U,13U -#define MMCSD_CSD_MMC_TMP_WRITE_PROTECT_SLICE 12U,12U -#define MMCSD_CSD_MMC_FILE_FORMAT_SLICE 11U,10U -#define MMCSD_CSD_MMC_ECC_SLICE 9U,8U -#define MMCSD_CSD_MMC_CRC_SLICE 7U,1U - -/* CSD version 2.0 */ -#define MMCSD_CSD_20_CRC_SLICE 7U,1U -#define MMCSD_CSD_20_FILE_FORMAT_SLICE 11U,10U -#define MMCSD_CSD_20_TMP_WRITE_PROTECT_SLICE 12U,12U -#define MMCSD_CSD_20_PERM_WRITE_PROTECT_SLICE 13U,13U -#define MMCSD_CSD_20_COPY_SLICE 14U,14U -#define MMCSD_CSD_20_FILE_FORMAT_GRP_SLICE 15U,15U -#define MMCSD_CSD_20_WRITE_BL_PARTIAL_SLICE 21U,21U -#define MMCSD_CSD_20_WRITE_BL_LEN_SLICE 25U,12U -#define MMCSD_CSD_20_R2W_FACTOR_SLICE 28U,26U -#define MMCSD_CSD_20_WP_GRP_ENABLE_SLICE 31U,31U -#define MMCSD_CSD_20_WP_GRP_SIZE_SLICE 38U,32U -#define MMCSD_CSD_20_ERASE_SECTOR_SIZE_SLICE 45U,39U -#define MMCSD_CSD_20_ERASE_BLK_EN_SLICE 46U,46U -#define MMCSD_CSD_20_C_SIZE_SLICE 69U,48U -#define MMCSD_CSD_20_DSR_IMP_SLICE 76U,76U -#define MMCSD_CSD_20_READ_BLK_MISALIGN_SLICE 77U,77U -#define MMCSD_CSD_20_WRITE_BLK_MISALIGN_SLICE 78U,78U -#define MMCSD_CSD_20_READ_BL_PARTIAL_SLICE 79U,79U -#define MMCSD_CSD_20_READ_BL_LEN_SLICE 83U,80U -#define MMCSD_CSD_20_CCC_SLICE 95U,84U -#define MMCSD_CSD_20_TRANS_SPEED_SLICE 103U,96U -#define MMCSD_CSD_20_NSAC_SLICE 111U,104U -#define MMCSD_CSD_20_TAAC_SLICE 119U,112U -#define MMCSD_CSD_20_CSD_STRUCTURE_SLICE 127U,126U - -/* CSD version 1.0 */ -#define MMCSD_CSD_10_CRC_SLICE MMCSD_CSD_20_CRC_SLICE -#define MMCSD_CSD_10_FILE_FORMAT_SLICE MMCSD_CSD_20_FILE_FORMAT_SLICE -#define MMCSD_CSD_10_TMP_WRITE_PROTECT_SLICE MMCSD_CSD_20_TMP_WRITE_PROTECT_SLICE -#define MMCSD_CSD_10_PERM_WRITE_PROTECT_SLICE MMCSD_CSD_20_PERM_WRITE_PROTECT_SLICE -#define MMCSD_CSD_10_COPY_SLICE MMCSD_CSD_20_COPY_SLICE -#define MMCSD_CSD_10_FILE_FORMAT_GRP_SLICE MMCSD_CSD_20_FILE_FORMAT_GRP_SLICE -#define MMCSD_CSD_10_WRITE_BL_PARTIAL_SLICE MMCSD_CSD_20_WRITE_BL_PARTIAL_SLICE -#define MMCSD_CSD_10_WRITE_BL_LEN_SLICE MMCSD_CSD_20_WRITE_BL_LEN_SLICE -#define MMCSD_CSD_10_R2W_FACTOR_SLICE MMCSD_CSD_20_R2W_FACTOR_SLICE -#define MMCSD_CSD_10_WP_GRP_ENABLE_SLICE MMCSD_CSD_20_WP_GRP_ENABLE_SLICE -#define MMCSD_CSD_10_WP_GRP_SIZE_SLICE MMCSD_CSD_20_WP_GRP_SIZE_SLICE -#define MMCSD_CSD_10_ERASE_SECTOR_SIZE_SLICE MMCSD_CSD_20_ERASE_SECTOR_SIZE_SLICE -#define MMCSD_CSD_10_ERASE_BLK_EN_SLICE MMCSD_CSD_20_ERASE_BLK_EN_SLICE -#define MMCSD_CSD_10_C_SIZE_MULT_SLICE 49U,47U -#define MMCSD_CSD_10_VDD_W_CURR_MAX_SLICE 52U,50U -#define MMCSD_CSD_10_VDD_W_CURR_MIN_SLICE 55U,53U -#define MMCSD_CSD_10_VDD_R_CURR_MAX_SLICE 58U,56U -#define MMCSD_CSD_10_VDD_R_CURR_MIX_SLICE 61U,59U -#define MMCSD_CSD_10_C_SIZE_SLICE 73U,62U -#define MMCSD_CSD_10_DSR_IMP_SLICE MMCSD_CSD_20_DSR_IMP_SLICE -#define MMCSD_CSD_10_READ_BLK_MISALIGN_SLICE MMCSD_CSD_20_READ_BLK_MISALIGN_SLICE -#define MMCSD_CSD_10_WRITE_BLK_MISALIGN_SLICE MMCSD_CSD_20_WRITE_BLK_MISALIGN_SLICE -#define MMCSD_CSD_10_READ_BL_PARTIAL_SLICE MMCSD_CSD_20_READ_BL_PARTIAL_SLICE -#define MMCSD_CSD_10_READ_BL_LEN_SLICE 83U,80U -#define MMCSD_CSD_10_CCC_SLICE MMCSD_CSD_20_CCC_SLICE -#define MMCSD_CSD_10_TRANS_SPEED_SLICE MMCSD_CSD_20_TRANS_SPEED_SLICE -#define MMCSD_CSD_10_NSAC_SLICE MMCSD_CSD_20_NSAC_SLICE -#define MMCSD_CSD_10_TAAC_SLICE MMCSD_CSD_20_TAAC_SLICE -#define MMCSD_CSD_10_CSD_STRUCTURE_SLICE MMCSD_CSD_20_CSD_STRUCTURE_SLICE -/** @} */ - -/** - * @name CID record offsets - */ -/** - * @brief Slice position of values in CID register. - */ -/* CID for SDC */ -#define MMCSD_CID_SDC_CRC_SLICE 7U,1U -#define MMCSD_CID_SDC_MDT_M_SLICE 11U,8U -#define MMCSD_CID_SDC_MDT_Y_SLICE 19U,12U -#define MMCSD_CID_SDC_PSN_SLICE 55U,24U -#define MMCSD_CID_SDC_PRV_M_SLICE 59U,56U -#define MMCSD_CID_SDC_PRV_N_SLICE 63U,60U -#define MMCSD_CID_SDC_PNM0_SLICE 71U,64U -#define MMCSD_CID_SDC_PNM1_SLICE 79U,72U -#define MMCSD_CID_SDC_PNM2_SLICE 87U,80U -#define MMCSD_CID_SDC_PNM3_SLICE 95U,88U -#define MMCSD_CID_SDC_PNM4_SLICE 103U,96U -#define MMCSD_CID_SDC_OID_SLICE 119U,104U -#define MMCSD_CID_SDC_MID_SLICE 127U,120U - -/* CID for MMC */ -#define MMCSD_CID_MMC_CRC_SLICE 7U,1U -#define MMCSD_CID_MMC_MDT_Y_SLICE 11U,8U -#define MMCSD_CID_MMC_MDT_M_SLICE 15U,12U -#define MMCSD_CID_MMC_PSN_SLICE 47U,16U -#define MMCSD_CID_MMC_PRV_M_SLICE 51U,48U -#define MMCSD_CID_MMC_PRV_N_SLICE 55U,52U -#define MMCSD_CID_MMC_PNM0_SLICE 63U,56U -#define MMCSD_CID_MMC_PNM1_SLICE 71U,64U -#define MMCSD_CID_MMC_PNM2_SLICE 79U,72U -#define MMCSD_CID_MMC_PNM3_SLICE 87U,80U -#define MMCSD_CID_MMC_PNM4_SLICE 95U,88U -#define MMCSD_CID_MMC_PNM5_SLICE 103U,96U -#define MMCSD_CID_MMC_OID_SLICE 119U,104U -#define MMCSD_CID_MMC_MID_SLICE 127U,120U -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief @p MMCSDBlockDevice specific methods. - */ -#define _mmcsd_block_device_methods \ - _base_block_device_methods - -/** - * @brief @p MMCSDBlockDevice specific data. - * @note It is empty because @p MMCSDBlockDevice is only an interface - * without implementation. - */ -#define _mmcsd_block_device_data \ - _base_block_device_data \ - /* Card CID.*/ \ - uint32_t cid[4]; \ - /* Card CSD.*/ \ - uint32_t csd[4]; \ - /* Total number of blocks in card.*/ \ - uint32_t capacity; - -/** - * @extends BaseBlockDeviceVMT - * - * @brief @p MMCSDBlockDevice virtual methods table. - */ -struct MMCSDBlockDeviceVMT { - _base_block_device_methods -}; - -/** - * @extends BaseBlockDevice - * - * @brief MCC/SD block device class. - * @details This class represents a, block-accessible, MMC/SD device. - */ -typedef struct { - /** @brief Virtual Methods Table.*/ - const struct MMCSDBlockDeviceVMT *vmt; - _mmcsd_block_device_data -} MMCSDBlockDevice; - -/** - * @brief Unpacked CID register from SDC. - */ -typedef struct { - uint8_t mid; - uint16_t oid; - char pnm[5]; - uint8_t prv_n; - uint8_t prv_m; - uint32_t psn; - uint8_t mdt_m; - uint16_t mdt_y; - uint8_t crc; -} unpacked_sdc_cid_t; - -/** - * @brief Unpacked CID register from MMC. - */ -typedef struct { - uint8_t mid; - uint16_t oid; - char pnm[6]; - uint8_t prv_n; - uint8_t prv_m; - uint32_t psn; - uint8_t mdt_m; - uint16_t mdt_y; - uint8_t crc; -} unpacked_mmc_cid_t; - -/** - * @brief Unpacked CSD v1.0 register from SDC. - */ -typedef struct { - uint8_t csd_structure; - uint8_t taac; - uint8_t nsac; - uint8_t tran_speed; - uint16_t ccc; - uint8_t read_bl_len; - uint8_t read_bl_partial; - uint8_t write_blk_misalign; - uint8_t read_blk_misalign; - uint8_t dsr_imp; - uint16_t c_size; - uint8_t vdd_r_curr_min; - uint8_t vdd_r_curr_max; - uint8_t vdd_w_curr_min; - uint8_t vdd_w_curr_max; - uint8_t c_size_mult; - uint8_t erase_blk_en; - uint8_t erase_sector_size; - uint8_t wp_grp_size; - uint8_t wp_grp_enable; - uint8_t r2w_factor; - uint8_t write_bl_len; - uint8_t write_bl_partial; - uint8_t file_format_grp; - uint8_t copy; - uint8_t perm_write_protect; - uint8_t tmp_write_protect; - uint8_t file_format; - uint8_t crc; -} unpacked_sdc_csd_10_t; - -/** - * @brief Unpacked CSD v2.0 register from SDC. - */ -typedef struct { - uint8_t csd_structure; - uint8_t taac; - uint8_t nsac; - uint8_t tran_speed; - uint16_t ccc; - uint8_t read_bl_len; - uint8_t read_bl_partial; - uint8_t write_blk_misalign; - uint8_t read_blk_misalign; - uint8_t dsr_imp; - uint32_t c_size; - uint8_t erase_blk_en; - uint8_t erase_sector_size; - uint8_t wp_grp_size; - uint8_t wp_grp_enable; - uint8_t r2w_factor; - uint8_t write_bl_len; - uint8_t write_bl_partial; - uint8_t file_format_grp; - uint8_t copy; - uint8_t perm_write_protect; - uint8_t tmp_write_protect; - uint8_t file_format; - uint8_t crc; -} unpacked_sdc_csd_20_t; - -/** - * @brief Unpacked CSD register from MMC. - */ -typedef struct { - uint8_t csd_structure; - uint8_t spec_vers; - uint8_t taac; - uint8_t nsac; - uint8_t tran_speed; - uint16_t ccc; - uint8_t read_bl_len; - uint8_t read_bl_partial; - uint8_t write_blk_misalign; - uint8_t read_blk_misalign; - uint8_t dsr_imp; - uint16_t c_size; - uint8_t vdd_r_curr_min; - uint8_t vdd_r_curr_max; - uint8_t vdd_w_curr_min; - uint8_t vdd_w_curr_max; - uint8_t c_size_mult; - uint8_t erase_grp_size; - uint8_t erase_grp_mult; - uint8_t wp_grp_size; - uint8_t wp_grp_enable; - uint8_t default_ecc; - uint8_t r2w_factor; - uint8_t write_bl_len; - uint8_t write_bl_partial; - uint8_t content_prot_app; - uint8_t file_format_grp; - uint8_t copy; - uint8_t perm_write_protect; - uint8_t tmp_write_protect; - uint8_t file_format; - uint8_t ecc; - uint8_t crc; -} unpacked_mmc_csd_t; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name R1 response utilities - * @{ - */ -/** - * @brief Evaluates to @p TRUE if the R1 response contains error flags. - * - * @param[in] r1 the r1 response - */ -#define MMCSD_R1_ERROR(r1) (((r1) & MMCSD_R1_ERROR_MASK) != 0U) - -/** - * @brief Returns the status field of an R1 response. - * - * @param[in] r1 the r1 response - */ -#define MMCSD_R1_STS(r1) (((r1) >> 9U) & 15U) - -/** - * @brief Evaluates to @p TRUE if the R1 response indicates a locked card. - * - * @param[in] r1 the r1 response - */ -#define MMCSD_R1_IS_CARD_LOCKED(r1) ((((r1) >> 21U) & 1U) != 0U) -/** @} */ - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Returns the card capacity in blocks. - * - * @param[in] ip pointer to a @p MMCSDBlockDevice or derived class - * - * @return The card capacity. - * - * @api - */ -#define mmcsdGetCardCapacity(ip) ((ip)->capacity) -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - uint32_t _mmcsd_get_slice(const uint32_t *data, - uint32_t end, - uint32_t start); - uint32_t _mmcsd_get_capacity(const uint32_t *csd); - uint32_t _mmcsd_get_capacity_ext(const uint8_t *ext_csd); - void _mmcsd_unpack_sdc_cid(const MMCSDBlockDevice *sdcp, - unpacked_sdc_cid_t *cidsdc); - void _mmcsd_unpack_mmc_cid(const MMCSDBlockDevice *sdcp, - unpacked_mmc_cid_t *cidmmc); - void _mmcsd_unpack_csd_mmc(const MMCSDBlockDevice *sdcp, - unpacked_mmc_csd_t *csdmmc); - void _mmcsd_unpack_csd_v10(const MMCSDBlockDevice *sdcp, - unpacked_sdc_csd_10_t *csd10); - void _mmcsd_unpack_csd_v20(const MMCSDBlockDevice *sdcp, - unpacked_sdc_csd_20_t *csd20); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_MMC_SPI == TRUE || HAL_USE_MMC_SDC == TRUE */ - -#endif /* _HAL_MMCSD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/include/hal_queues.h b/firmware/ChibiOS_16/os/hal/include/hal_queues.h deleted file mode 100644 index d31e0a2403..0000000000 --- a/firmware/ChibiOS_16/os/hal/include/hal_queues.h +++ /dev/null @@ -1,335 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_queues.h - * @brief I/O Queues macros and structures. - * - * @addtogroup HAL_QUEUES - * @{ - */ - -#ifndef _HAL_QUEUES_H_ -#define _HAL_QUEUES_H_ - -/* The ChibiOS/RT kernel provides the following definitions by itself, this - check is performed in order to avoid conflicts. */ -#if !defined(_CHIBIOS_RT_) || (CH_CFG_USE_QUEUES == FALSE) || \ - defined(__DOXYGEN__) - -/** - * @name Queue functions returned status value - * @{ - */ -#define Q_OK MSG_OK /**< @brief Operation successful. */ -#define Q_TIMEOUT MSG_TIMEOUT /**< @brief Timeout condition. */ -#define Q_RESET MSG_RESET /**< @brief Queue has been reset. */ -#define Q_EMPTY (msg_t)-3 /**< @brief Queue empty. */ -#define Q_FULL (msg_t)-4 /**< @brief Queue full, */ -/** @} */ - -/** - * @brief Type of a generic I/O queue structure. - */ -typedef struct io_queue io_queue_t; - -/** - * @brief Queue notification callback type. - * - * @param[in] qp the queue pointer - */ -typedef void (*qnotify_t)(io_queue_t *qp); - -/** - * @brief Generic I/O queue structure. - * @details This structure represents a generic Input or Output asymmetrical - * queue. The queue is asymmetrical because one end is meant to be - * accessed from a thread context, and thus can be blocking, the other - * end is accessible from interrupt handlers or from within a kernel - * lock zone and is non-blocking. - */ -struct io_queue { - threads_queue_t q_waiting; /**< @brief Queue of waiting threads. */ - volatile size_t q_counter; /**< @brief Resources counter. */ - uint8_t *q_buffer; /**< @brief Pointer to the queue buffer.*/ - uint8_t *q_top; /**< @brief Pointer to the first - location after the buffer. */ - uint8_t *q_wrptr; /**< @brief Write pointer. */ - uint8_t *q_rdptr; /**< @brief Read pointer. */ - qnotify_t q_notify; /**< @brief Data notification callback. */ - void *q_link; /**< @brief Application defined field. */ -}; - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Returns the queue's buffer size. - * - * @param[in] qp pointer to a @p io_queue_t structure - * @return The buffer size. - * - * @xclass - */ -#define qSizeX(qp) \ - /*lint -save -e9033 [10.8] The cast is safe.*/ \ - ((size_t)((qp)->q_top - (qp)->q_buffer)) \ - /*lint -restore*/ - -/** - * @brief Queue space. - * @details Returns the used space if used on an input queue or the empty - * space if used on an output queue. - * - * @param[in] qp pointer to a @p io_queue_t structure - * @return The buffer space. - * - * @iclass - */ -#define qSpaceI(qp) ((qp)->q_counter) - -/** - * @brief Returns the queue application-defined link. - * @note This function can be called in any context. - * - * @param[in] qp pointer to a @p io_queue_t structure - * @return The application-defined link. - * - * @special - */ -#define qGetLink(qp) ((qp)->q_link) -/** @} */ - -/** - * @extends io_queue_t - * - * @brief Type of an input queue structure. - * @details This structure represents a generic asymmetrical input queue. - * Writing to the queue is non-blocking and can be performed from - * interrupt handlers or from within a kernel lock zone. - * Reading the queue can be a blocking operation and is supposed to - * be performed by a system thread. - */ -typedef io_queue_t input_queue_t; - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Returns the filled space into an input queue. - * - * @param[in] iqp pointer to an @p input_queue_t structure - * @return The number of full bytes in the queue. - * @retval 0 if the queue is empty. - * - * @iclass - */ -#define iqGetFullI(iqp) qSpaceI(iqp) - -/** - * @brief Returns the empty space into an input queue. - * - * @param[in] iqp pointer to an @p input_queue_t structure - * @return The number of empty bytes in the queue. - * @retval 0 if the queue is full. - * - * @iclass - */ -#define iqGetEmptyI(iqp) (qSizeX(iqp) - qSpaceI(iqp)) - -/** - * @brief Evaluates to @p true if the specified input queue is empty. - * - * @param[in] iqp pointer to an @p input_queue_t structure - * @return The queue status. - * @retval false if the queue is not empty. - * @retval true if the queue is empty. - * - * @iclass - */ -#define iqIsEmptyI(iqp) ((bool)(qSpaceI(iqp) == 0U)) - -/** - * @brief Evaluates to @p true if the specified input queue is full. - * - * @param[in] iqp pointer to an @p input_queue_t structure - * @return The queue status. - * @retval false if the queue is not full. - * @retval true if the queue is full. - * - * @iclass - */ -#define iqIsFullI(iqp) \ - /*lint -save -e9007 [13.5] No side effects, a pointer is passed.*/ \ - ((bool)(((iqp)->q_wrptr == (iqp)->q_rdptr) && ((iqp)->q_counter != 0U))) \ - /*lint -restore*/ - -/** - * @brief Input queue read. - * @details This function reads a byte value from an input queue. If the queue - * is empty then the calling thread is suspended until a byte arrives - * in the queue. - * - * @param[in] iqp pointer to an @p input_queue_t structure - * @return A byte value from the queue. - * @retval Q_RESET if the queue has been reset. - * - * @api - */ -#define iqGet(iqp) iqGetTimeout(iqp, TIME_INFINITE) -/** @} */ - -/** - * @extends io_queue_t - * - * @brief Type of an output queue structure. - * @details This structure represents a generic asymmetrical output queue. - * Reading from the queue is non-blocking and can be performed from - * interrupt handlers or from within a kernel lock zone. - * Writing the queue can be a blocking operation and is supposed to - * be performed by a system thread. - */ -typedef io_queue_t output_queue_t; - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Returns the filled space into an output queue. - * - * @param[in] oqp pointer to an @p output_queue_t structure - * @return The number of full bytes in the queue. - * @retval 0 if the queue is empty. - * - * @iclass - */ -#define oqGetFullI(oqp) (qSizeX(oqp) - qSpaceI(oqp)) - -/** - * @brief Returns the empty space into an output queue. - * - * @param[in] oqp pointer to an @p output_queue_t structure - * @return The number of empty bytes in the queue. - * @retval 0 if the queue is full. - * - * @iclass - */ -#define oqGetEmptyI(oqp) qSpaceI(oqp) - -/** - * @brief Evaluates to @p true if the specified output queue is empty. - * - * @param[in] oqp pointer to an @p output_queue_t structure - * @return The queue status. - * @retval false if the queue is not empty. - * @retval true if the queue is empty. - * - * @iclass - */ -#define oqIsEmptyI(oqp) \ - /*lint -save -e9007 [13.5] No side effects, a pointer is passed.*/ \ - ((bool)(((oqp)->q_wrptr == (oqp)->q_rdptr) && ((oqp)->q_counter != 0U))) \ - /*lint -restore*/ - -/** - * @brief Evaluates to @p true if the specified output queue is full. - * - * @param[in] oqp pointer to an @p output_queue_t structure - * @return The queue status. - * @retval false if the queue is not full. - * @retval true if the queue is full. - * - * @iclass - */ -#define oqIsFullI(oqp) ((bool)(qSpaceI(oqp) == 0U)) - -/** - * @brief Output queue write. - * @details This function writes a byte value to an output queue. If the queue - * is full then the calling thread is suspended until there is space - * in the queue. - * - * @param[in] oqp pointer to an @p output_queue_t structure - * @param[in] b the byte value to be written in the queue - * @return The operation status. - * @retval Q_OK if the operation succeeded. - * @retval Q_RESET if the queue has been reset. - * - * @api - */ -#define oqPut(oqp, b) oqPutTimeout(oqp, b, TIME_INFINITE) - /** @} */ - -#ifdef __cplusplus -extern "C" { -#endif - void iqObjectInit(input_queue_t *iqp, uint8_t *bp, size_t size, - qnotify_t infy, void *link); - void iqResetI(input_queue_t *iqp); - msg_t iqPutI(input_queue_t *iqp, uint8_t b); - msg_t iqGetTimeout(input_queue_t *iqp, systime_t timeout); - size_t iqReadTimeout(input_queue_t *iqp, uint8_t *bp, - size_t n, systime_t timeout); - - void oqObjectInit(output_queue_t *oqp, uint8_t *bp, size_t size, - qnotify_t onfy, void *link); - void oqResetI(output_queue_t *oqp); - msg_t oqPutTimeout(output_queue_t *oqp, uint8_t b, systime_t timeout); - msg_t oqGetI(output_queue_t *oqp); - size_t oqWriteTimeout(output_queue_t *oqp, const uint8_t *bp, - size_t n, systime_t timeout); -#ifdef __cplusplus -} -#endif - -#else /* defined(_CHIBIOS_RT_) && CH_CFG_USE_QUEUES */ - -/* If ChibiOS is being used and its own queues subsystem is activated then - this module will use the ChibiOS queues code.*/ -#define qSizeX(qp) chQSizeX(qp) -#define qSpaceI(qp) chQSpaceI(qp) -#define qGetLink(qp) chQGetLinkX(qp) -#define iqGetFullI(iqp) chIQGetFullI(iqp) -#define iqGetEmptyI(iqp) chIQGetEmptyI(iqp) -#define iqIsEmptyI(iqp) chIQIsEmptyI(iqp) -#define iqIsFullI(iqp) chIQIsFullI(iqp) -#define iqGet(iqp) chIQGet(iqp) -#define oqGetFullI(oqp) chOQGetFullI(oqp) -#define oqGetEmptyI(oqp) chOQGetEmptyI(oqp) -#define oqIsEmptyI(oqp) chOQIsEmptyI(oqp) -#define oqIsFullI(oqp) chOQIsFullI(oqp) -#define oqPut(oqp, b) chOQPut(oqp, b) -#define iqObjectInit(iqp, bp, size, infy, link) \ - chIQObjectInit(iqp, bp, size, infy, link) -#define iqResetI(iqp) chIQResetI(iqp) -#define iqPutI(iqp, b) chIQPutI(iqp, b) -#define iqGetTimeout(iqp, time) chIQGetTimeout(iqp, time) -#define iqReadTimeout(iqp, bp, n, time) chIQReadTimeout(iqp, bp, n, time) -#define oqObjectInit(oqp, bp, size, onfy, link) \ - chOQObjectInit(oqp, bp, size, onfy, link) -#define oqResetI(oqp) chOQResetI(oqp) -#define oqPutTimeout(oqp, b, time) chOQPutTimeout(oqp, b, time) -#define oqGetI(oqp) chOQGetI(oqp) -#define oqWriteTimeout(oqp, bp, n, time) chOQWriteTimeout(oqp, bp, n, time) - -#endif /* defined(_CHIBIOS_RT_) || (CH_CFG_USE_QUEUES == FALSE) */ - -#endif /* _HAL_QUEUES_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/include/hal_streams.h b/firmware/ChibiOS_16/os/hal/include/hal_streams.h deleted file mode 100644 index cd7910d857..0000000000 --- a/firmware/ChibiOS_16/os/hal/include/hal_streams.h +++ /dev/null @@ -1,158 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_streams.h - * @brief Data streams. - * @details This header defines abstract interfaces useful to access generic - * data streams in a standardized way. - * - * @addtogroup HAL_STREAMS - * @details This module define an abstract interface for generic data streams. - * Note that no code is present, just abstract interfaces-like - * structures, you should look at the system as to a set of - * abstract C++ classes (even if written in C). This system - * has then advantage to make the access to data streams - * independent from the implementation logic.
- * The stream interface can be used as base class for high level - * object types such as files, sockets, serial ports, pipes etc. - * @{ - */ - -#ifndef _HAL_STREAMS_H_ -#define _HAL_STREAMS_H_ - -/** - * @name Streams return codes - * @{ - */ -#define STM_OK MSG_OK -#define STM_TIMEOUT MSG_TIMEOUT -#define STM_RESET MSG_RESET -/** @} */ - -/* The ChibiOS/RT kernel provides the following definitions by itself, this - check is performed in order to avoid conflicts. */ -#if !defined(_CHIBIOS_RT_) || defined(__DOXYGEN__) - -/** - * @brief BaseSequentialStream specific methods. - */ -#define _base_sequential_stream_methods \ - /* Stream write buffer method.*/ \ - size_t (*write)(void *instance, const uint8_t *bp, size_t n); \ - /* Stream read buffer method.*/ \ - size_t (*read)(void *instance, uint8_t *bp, size_t n); \ - /* Channel put method, blocking.*/ \ - msg_t (*put)(void *instance, uint8_t b); \ - /* Channel get method, blocking.*/ \ - msg_t (*get)(void *instance); \ - -/** - * @brief @p BaseSequentialStream specific data. - * @note It is empty because @p BaseSequentialStream is only an interface - * without implementation. - */ -#define _base_sequential_stream_data - -/** - * @brief @p BaseSequentialStream virtual methods table. - */ -struct BaseSequentialStreamVMT { - _base_sequential_stream_methods -}; - -/** - * @brief Base stream class. - * @details This class represents a generic blocking unbuffered sequential - * data stream. - */ -typedef struct { - /** @brief Virtual Methods Table.*/ - const struct BaseSequentialStreamVMT *vmt; - _base_sequential_stream_data -} BaseSequentialStream; - -#endif /* !defined(_CHIBIOS_RT_)*/ - -/** - * @name Macro Functions (BaseSequentialStream) - * @{ - */ -/** - * @brief Sequential Stream write. - * @details The function writes data from a buffer to a stream. - * - * @param[in] ip pointer to a @p BaseSequentialStream or derived class - * @param[in] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred - * @return The number of bytes transferred. The return value can - * be less than the specified number of bytes if an - * end-of-file condition has been met. - * - * @api - */ -#define streamWrite(ip, bp, n) ((ip)->vmt->write(ip, bp, n)) - -/** - * @brief Sequential Stream read. - * @details The function reads data from a stream into a buffer. - * - * @param[in] ip pointer to a @p BaseSequentialStream or derived class - * @param[out] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred - * @return The number of bytes transferred. The return value can - * be less than the specified number of bytes if an - * end-of-file condition has been met. - * - * @api - */ -#define streamRead(ip, bp, n) ((ip)->vmt->read(ip, bp, n)) - -/** - * @brief Sequential Stream blocking byte write. - * @details This function writes a byte value to a channel. If the channel - * is not ready to accept data then the calling thread is suspended. - * - * @param[in] ip pointer to a @p BaseChannel or derived class - * @param[in] b the byte value to be written to the channel - * - * @return The operation status. - * @retval STM_OK if the operation succeeded. - * @retval STM_RESET if an end-of-file condition has been met. - * - * @api - */ -#define streamPut(ip, b) ((ip)->vmt->put(ip, b)) - -/** - * @brief Sequential Stream blocking byte read. - * @details This function reads a byte value from a channel. If the data - * is not available then the calling thread is suspended. - * - * @param[in] ip pointer to a @p BaseChannel or derived class - * - * @return A byte value from the queue. - * @retval STM_RESET if an end-of-file condition has been met. - * - * @api - */ -#define streamGet(ip) ((ip)->vmt->get(ip)) -/** @} */ - -#endif /* _HAL_STREAMS_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/include/i2c.h b/firmware/ChibiOS_16/os/hal/include/i2c.h deleted file mode 100644 index 76b8ef6f7e..0000000000 --- a/firmware/ChibiOS_16/os/hal/include/i2c.h +++ /dev/null @@ -1,166 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Concepts and parts of this file have been contributed by Uladzimir Pylinsky - aka barthess. - */ - -/** - * @file i2c.h - * @brief I2C Driver macros and structures. - * - * @addtogroup I2C - * @{ - */ - -#ifndef _I2C_H_ -#define _I2C_H_ - -#if (HAL_USE_I2C == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/* TODO: To be reviewed, too STM32-centric.*/ -/** - * @name I2C bus error conditions - * @{ - */ -#define I2C_NO_ERROR 0x00 /**< @brief No error. */ -#define I2C_BUS_ERROR 0x01 /**< @brief Bus Error. */ -#define I2C_ARBITRATION_LOST 0x02 /**< @brief Arbitration Lost. */ -#define I2C_ACK_FAILURE 0x04 /**< @brief Acknowledge Failure. */ -#define I2C_OVERRUN 0x08 /**< @brief Overrun/Underrun. */ -#define I2C_PEC_ERROR 0x10 /**< @brief PEC Error in - reception. */ -#define I2C_TIMEOUT 0x20 /**< @brief Hardware timeout. */ -#define I2C_SMB_ALERT 0x40 /**< @brief SMBus Alert. */ -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the mutual exclusion APIs on the I2C bus. - */ -#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define I2C_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - I2C_UNINIT = 0, /**< Not initialized. */ - I2C_STOP = 1, /**< Stopped. */ - I2C_READY = 2, /**< Ready. */ - I2C_ACTIVE_TX = 3, /**< Transmitting. */ - I2C_ACTIVE_RX = 4, /**< Receiving. */ - I2C_LOCKED = 5 /**> Bus or driver locked. */ -} i2cstate_t; - -#include "i2c_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Wakes up the waiting thread notifying no errors. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -#define _i2c_wakeup_isr(i2cp) do { \ - osalSysLockFromISR(); \ - osalThreadResumeI(&(i2cp)->thread, MSG_OK); \ - osalSysUnlockFromISR(); \ -} while(0) - -/** - * @brief Wakes up the waiting thread notifying errors. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -#define _i2c_wakeup_error_isr(i2cp) do { \ - osalSysLockFromISR(); \ - osalThreadResumeI(&(i2cp)->thread, MSG_RESET); \ - osalSysUnlockFromISR(); \ -} while(0) - -/** - * @brief Wrap i2cMasterTransmitTimeout function with TIME_INFINITE timeout. - * @api - */ -#define i2cMasterTransmit(i2cp, addr, txbuf, txbytes, rxbuf, rxbytes) \ - (i2cMasterTransmitTimeout(i2cp, addr, txbuf, txbytes, rxbuf, rxbytes, \ - TIME_INFINITE)) - -/** - * @brief Wrap i2cMasterReceiveTimeout function with TIME_INFINITE timeout. - * @api - */ -#define i2cMasterReceive(i2cp, addr, rxbuf, rxbytes) \ - (i2cMasterReceiveTimeout(i2cp, addr, rxbuf, rxbytes, TIME_INFINITE)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void i2cInit(void); - void i2cObjectInit(I2CDriver *i2cp); - void i2cStart(I2CDriver *i2cp, const I2CConfig *config); - void i2cStop(I2CDriver *i2cp); - i2cflags_t i2cGetErrors(I2CDriver *i2cp); - msg_t i2cMasterTransmitTimeout(I2CDriver *i2cp, - i2caddr_t addr, - const uint8_t *txbuf, size_t txbytes, - uint8_t *rxbuf, size_t rxbytes, - systime_t timeout); - msg_t i2cMasterReceiveTimeout(I2CDriver *i2cp, - i2caddr_t addr, - uint8_t *rxbuf, size_t rxbytes, - systime_t timeout); -#if I2C_USE_MUTUAL_EXCLUSION == TRUE - void i2cAcquireBus(I2CDriver *i2cp); - void i2cReleaseBus(I2CDriver *i2cp); -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_I2C == TRUE */ - -#endif /* _I2C_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/include/i2s.h b/firmware/ChibiOS_16/os/hal/include/i2s.h deleted file mode 100644 index 7ecd342d19..0000000000 --- a/firmware/ChibiOS_16/os/hal/include/i2s.h +++ /dev/null @@ -1,167 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file i2s.h - * @brief I2S Driver macros and structures. - * - * @addtogroup I2S - * @{ - */ - -#ifndef _I2S_H_ -#define _I2S_H_ - -#if (HAL_USE_I2S == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name I2S modes - * @{ - */ -#define I2S_MODE_SLAVE 0 -#define I2S_MODE_MASTER 1 -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - I2S_UNINIT = 0, /**< Not initialized. */ - I2S_STOP = 1, /**< Stopped. */ - I2S_READY = 2, /**< Ready. */ - I2S_ACTIVE = 3, /**< Active. */ - I2S_COMPLETE = 4 /**< Transmission complete. */ -} i2sstate_t; - -#include "i2s_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Starts a I2S data exchange. - * - * @param[in] i2sp pointer to the @p I2SDriver object - * - * @iclass - */ -#define i2sStartExchangeI(i2sp) { \ - i2s_lld_start_exchange(i2sp); \ - (i2sp)->state = I2S_ACTIVE; \ -} - -/** - * @brief Stops the ongoing data exchange. - * @details The ongoing data exchange, if any, is stopped, if the driver - * was not active the function does nothing. - * - * @param[in] i2sp pointer to the @p I2SDriver object - * - * @iclass - */ -#define i2sStopExchangeI(i2sp) { \ - i2s_lld_stop_exchange(i2sp); \ - (i2sp)->state = I2S_READY; \ -} - -/** - * @brief Common ISR code, half buffer event. - * @details This code handles the portable part of the ISR code: - * - Callback invocation. - * . - * @note This macro is meant to be used in the low level drivers - * implementation only. - * - * @param[in] i2sp pointer to the @p I2CDriver object - * - * @notapi - */ -#define _i2s_isr_half_code(i2sp) { \ - if ((i2sp)->config->end_cb != NULL) { \ - (i2sp)->config->end_cb(i2sp, 0, (i2sp)->config->size / 2); \ - } \ -} - -/** - * @brief Common ISR code. - * @details This code handles the portable part of the ISR code: - * - Callback invocation. - * - Driver state transitions. - * . - * @note This macro is meant to be used in the low level drivers - * implementation only. - * - * @param[in] i2sp pointer to the @p I2CDriver object - * - * @notapi - */ -#define _i2s_isr_full_code(i2sp) { \ - if ((i2sp)->config->end_cb) { \ - (i2sp)->state = I2S_COMPLETE; \ - (i2sp)->config->end_cb(i2sp, \ - (i2sp)->config->size / 2, \ - (i2sp)->config->size / 2); \ - if ((i2sp)->state == I2S_COMPLETE) \ - (i2sp)->state = I2S_READY; \ - } \ - else \ - (i2sp)->state = I2S_READY; \ -} -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void i2sInit(void); - void i2sObjectInit(I2SDriver *i2sp); - void i2sStart(I2SDriver *i2sp, const I2SConfig *config); - void i2sStop(I2SDriver *i2sp); - void i2sStartExchange(I2SDriver *i2sp); - void i2sStopExchange(I2SDriver *i2sp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_I2S == TRUE */ - -#endif /* _I2S_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/include/icu.h b/firmware/ChibiOS_16/os/hal/include/icu.h deleted file mode 100644 index a42e06da46..0000000000 --- a/firmware/ChibiOS_16/os/hal/include/icu.h +++ /dev/null @@ -1,238 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file icu.h - * @brief ICU Driver macros and structures. - * - * @addtogroup ICU - * @{ - */ - -#ifndef _ICU_H_ -#define _ICU_H_ - -#if (HAL_USE_ICU == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - ICU_UNINIT = 0, /**< Not initialized. */ - ICU_STOP = 1, /**< Stopped. */ - ICU_READY = 2, /**< Ready. */ - ICU_WAITING = 3, /**< Waiting for first front. */ - ICU_ACTIVE = 4 /**< First front detected. */ -} icustate_t; - -/** - * @brief Type of a structure representing an ICU driver. - */ -typedef struct ICUDriver ICUDriver; - -/** - * @brief ICU notification callback type. - * - * @param[in] icup pointer to a @p ICUDriver object - */ -typedef void (*icucallback_t)(ICUDriver *icup); - -#include "icu_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Starts the input capture. - * - * @param[in] icup pointer to the @p ICUDriver object - * - * @iclass - */ -#define icuStartCaptureI(icup) do { \ - icu_lld_start_capture(icup); \ - (icup)->state = ICU_WAITING; \ -} while (false) - -/** - * @brief Stops the input capture. - * - * @param[in] icup pointer to the @p ICUDriver object - * - * @iclass - */ -#define icuStopCaptureI(icup) do { \ - icu_lld_stop_capture(icup); \ - (icup)->state = ICU_READY; \ -} while (false) - -/** - * @brief Enables notifications. - * @pre The ICU unit must have been activated using @p icuStart(). - * @note If the notification is already enabled then the call has no effect. - * - * @param[in] icup pointer to the @p ICUDriver object - * - * @iclass - */ -#define icuEnableNotificationsI(icup) icu_lld_enable_notifications(icup) - -/** - * @brief Disables notifications. - * @pre The ICU unit must have been activated using @p icuStart(). - * @note If the notification is already disabled then the call has no effect. - * - * @param[in] icup pointer to the @p ICUDriver object - * - * @iclass - */ -#define icuDisableNotificationsI(icup) icu_lld_disable_notifications(icup) - -/** - * @brief Check on notifications status. - * - * @param[in] icup pointer to the @p ICUDriver object - * @return The notifications status. - * @retval false if notifications are not enabled. - * @retval true if notifications are enabled. - * - * @notapi - */ -#define icuAreNotificationsEnabledX(icup) \ - icu_lld_are_notifications_enabled(icup) - -/** - * @brief Returns the width of the latest pulse. - * @details The pulse width is defined as number of ticks between the start - * edge and the stop edge. - * @note This function is meant to be invoked from the width capture - * callback. - * - * @param[in] icup pointer to the @p ICUDriver object - * @return The number of ticks. - * - * @xclass - */ -#define icuGetWidthX(icup) icu_lld_get_width(icup) - -/** - * @brief Returns the width of the latest cycle. - * @details The cycle width is defined as number of ticks between a start - * edge and the next start edge. - * @note This function is meant to be invoked from the width capture - * callback. - * - * @param[in] icup pointer to the @p ICUDriver object - * @return The number of ticks. - * - * @xclass - */ -#define icuGetPeriodX(icup) icu_lld_get_period(icup) -/** @} */ - -/** - * @name Low level driver helper macros - * @{ - */ -/** - * @brief Common ISR code, ICU width event. - * - * @param[in] icup pointer to the @p ICUDriver object - * - * @notapi - */ -#define _icu_isr_invoke_width_cb(icup) do { \ - if (((icup)->state == ICU_ACTIVE) && \ - ((icup)->config->width_cb != NULL)) \ - (icup)->config->width_cb(icup); \ -} while (0) - -/** - * @brief Common ISR code, ICU period event. - * @note A period event brings the driver into the @p ICU_ACTIVE state. - * - * @param[in] icup pointer to the @p ICUDriver object - * - * @notapi - */ -#define _icu_isr_invoke_period_cb(icup) do { \ - if (((icup)->state == ICU_ACTIVE) && \ - ((icup)->config->period_cb != NULL)) \ - (icup)->config->period_cb(icup); \ - (icup)->state = ICU_ACTIVE; \ -} while (0) - -/** - * @brief Common ISR code, ICU timer overflow event. - * @note An overflow always brings the driver back to the @p ICU_WAITING - * state. - * - * @param[in] icup pointer to the @p ICUDriver object - * - * @notapi - */ -#define _icu_isr_invoke_overflow_cb(icup) do { \ - (icup)->config->overflow_cb(icup); \ - (icup)->state = ICU_WAITING; \ -} while (0) -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void icuInit(void); - void icuObjectInit(ICUDriver *icup); - void icuStart(ICUDriver *icup, const ICUConfig *config); - void icuStop(ICUDriver *icup); - void icuStartCapture(ICUDriver *icup); - bool icuWaitCapture(ICUDriver *icup); - void icuStopCapture(ICUDriver *icup); - void icuEnableNotifications(ICUDriver *icup); - void icuDisableNotifications(ICUDriver *icup); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_ICU == TRUE */ - -#endif /* _ICU_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/include/mac.h b/firmware/ChibiOS_16/os/hal/include/mac.h deleted file mode 100644 index 9c9e69c2a0..0000000000 --- a/firmware/ChibiOS_16/os/hal/include/mac.h +++ /dev/null @@ -1,202 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file mac.h - * @brief MAC Driver macros and structures. - * @addtogroup MAC - * @{ - */ - -#ifndef _MAC_H_ -#define _MAC_H_ - -#if (HAL_USE_MAC == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name MAC configuration options - * @{ - */ -/** - * @brief Enables an event sources for incoming packets. - */ -#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) -#define MAC_USE_ZERO_COPY FALSE -#endif - -/** - * @brief Enables an event sources for incoming packets. - */ -#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) -#define MAC_USE_EVENTS TRUE -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - MAC_UNINIT = 0, /**< Not initialized. */ - MAC_STOP = 1, /**< Stopped. */ - MAC_ACTIVE = 2 /**< Active. */ -} macstate_t; - -/** - * @brief Type of a structure representing a MAC driver. - */ -typedef struct MACDriver MACDriver; - -#include "mac_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Returns the received frames event source. - * - * @param[in] macp pointer to the @p MACDriver object - * @return The pointer to the @p EventSource structure. - * - * @api - */ -#if (MAC_USE_EVENTS == TRUE) || defined(__DOXYGEN__) -#define macGetReceiveEventSource(macp) (&(macp)->rdevent) -#endif - -/** - * @brief Writes to a transmit descriptor's stream. - * - * @param[in] tdp pointer to a @p MACTransmitDescriptor structure - * @param[in] buf pointer to the buffer containing the data to be written - * @param[in] size number of bytes to be written - * @return The number of bytes written into the descriptor's - * stream, this value can be less than the amount - * specified in the parameter @p size if the maximum frame - * size is reached. - * - * @api - */ -#define macWriteTransmitDescriptor(tdp, buf, size) \ - mac_lld_write_transmit_descriptor(tdp, buf, size) - -/** - * @brief Reads from a receive descriptor's stream. - * - * @param[in] rdp pointer to a @p MACReceiveDescriptor structure - * @param[in] buf pointer to the buffer that will receive the read data - * @param[in] size number of bytes to be read - * @return The number of bytes read from the descriptor's stream, - * this value can be less than the amount specified in the - * parameter @p size if there are no more bytes to read. - * - * @api - */ -#define macReadReceiveDescriptor(rdp, buf, size) \ - mac_lld_read_receive_descriptor(rdp, buf, size) - -#if (MAC_USE_ZERO_COPY == TRUE) || defined(__DOXYGEN__) -/** - * @brief Returns a pointer to the next transmit buffer in the descriptor - * chain. - * @note The API guarantees that enough buffers can be requested to fill - * a whole frame. - * - * @param[in] tdp pointer to a @p MACTransmitDescriptor structure - * @param[in] size size of the requested buffer. Specify the frame size - * on the first call then scale the value down subtracting - * the amount of data already copied into the previous - * buffers. - * @param[out] sizep pointer to variable receiving the real buffer size. - * The returned value can be less than the amount - * requested, this means that more buffers must be - * requested in order to fill the frame data entirely. - * @return Pointer to the returned buffer. - * - * @api - */ -#define macGetNextTransmitBuffer(tdp, size, sizep) \ - mac_lld_get_next_transmit_buffer(tdp, size, sizep) - -/** - * @brief Returns a pointer to the next receive buffer in the descriptor - * chain. - * @note The API guarantees that the descriptor chain contains a whole - * frame. - * - * @param[in] rdp pointer to a @p MACReceiveDescriptor structure - * @param[out] sizep pointer to variable receiving the buffer size, it is - * zero when the last buffer has already been returned. - * @return Pointer to the returned buffer. - * @retval NULL if the buffer chain has been entirely scanned. - * - * @api - */ -#define macGetNextReceiveBuffer(rdp, sizep) \ - mac_lld_get_next_receive_buffer(rdp, sizep) -#endif /* MAC_USE_ZERO_COPY */ -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void macInit(void); - void macObjectInit(MACDriver *macp); - void macStart(MACDriver *macp, const MACConfig *config); - void macStop(MACDriver *macp); - void macSetAddress(MACDriver *macp, const uint8_t *p); - msg_t macWaitTransmitDescriptor(MACDriver *macp, - MACTransmitDescriptor *tdp, - systime_t timeout); - void macReleaseTransmitDescriptor(MACTransmitDescriptor *tdp); - msg_t macWaitReceiveDescriptor(MACDriver *macp, - MACReceiveDescriptor *rdp, - systime_t timeout); - void macReleaseReceiveDescriptor(MACReceiveDescriptor *rdp); - bool macPollLinkStatus(MACDriver *macp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_MAC == TRUE */ - -#endif /* _MAC_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/include/mii.h b/firmware/ChibiOS_16/os/hal/include/mii.h deleted file mode 100644 index dc510161f6..0000000000 --- a/firmware/ChibiOS_16/os/hal/include/mii.h +++ /dev/null @@ -1,175 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file mii.h - * @brief MII macros and structures. - * - * @addtogroup MII - * @{ - */ - -#ifndef _MII_H_ -#define _MII_H_ - -/** - * @name Generic MII registers - * @{ - */ -#define MII_BMCR 0x00 /**< Basic mode control register. */ -#define MII_BMSR 0x01 /**< Basic mode status register. */ -#define MII_PHYSID1 0x02 /**< PHYS ID 1. */ -#define MII_PHYSID2 0x03 /**< PHYS ID 2. */ -#define MII_ADVERTISE 0x04 /**< Advertisement control reg. */ -#define MII_LPA 0x05 /**< Link partner ability reg. */ -#define MII_EXPANSION 0x06 /**< Expansion register. */ -#define MII_ANNPTR 0x07 /**< 1000BASE-T control. */ -#define MII_CTRL1000 0x09 /**< 1000BASE-T control. */ -#define MII_STAT1000 0x0a /**< 1000BASE-T status. */ -#define MII_ESTATUS 0x0f /**< Extended Status. */ -#define MII_PHYSTS 0x10 /**< PHY Status register. */ -#define MII_MICR 0x11 /**< MII Interrupt ctrl register. */ -#define MII_DCOUNTER 0x12 /**< Disconnect counter. */ -#define MII_FCSCOUNTER 0x13 /**< False carrier counter. */ -#define MII_NWAYTEST 0x14 /**< N-way auto-neg test reg. */ -#define MII_RERRCOUNTER 0x15 /**< Receive error counter. */ -#define MII_SREVISION 0x16 /**< Silicon revision. */ -#define MII_RESV1 0x17 /**< Reserved. */ -#define MII_LBRERROR 0x18 /**< Lpback, rx, bypass error. */ -#define MII_PHYADDR 0x19 /**< PHY address. */ -#define MII_RESV2 0x1a /**< Reserved. */ -#define MII_TPISTATUS 0x1b /**< TPI status for 10Mbps. */ -#define MII_NCONFIG 0x1c /**< Network interface config. */ -/** @} */ - -/** - * @name Basic mode control register - * @{ - */ -#define BMCR_RESV 0x007f /**< Unused. */ -#define BMCR_CTST 0x0080 /**< Collision test. */ -#define BMCR_FULLDPLX 0x0100 /**< Full duplex. */ -#define BMCR_ANRESTART 0x0200 /**< Auto negotiation restart. */ -#define BMCR_ISOLATE 0x0400 /**< Disconnect DP83840 from MII. */ -#define BMCR_PDOWN 0x0800 /**< Powerdown. */ -#define BMCR_ANENABLE 0x1000 /**< Enable auto negotiation. */ -#define BMCR_SPEED100 0x2000 /**< Select 100Mbps. */ -#define BMCR_LOOPBACK 0x4000 /**< TXD loopback bit. */ -#define BMCR_RESET 0x8000 /**< Reset. */ -/** @} */ - -/** - * @name Basic mode status register - * @{ - */ -#define BMSR_ERCAP 0x0001 /**< Ext-reg capability. */ -#define BMSR_JCD 0x0002 /**< Jabber detected. */ -#define BMSR_LSTATUS 0x0004 /**< Link status. */ -#define BMSR_ANEGCAPABLE 0x0008 /**< Able to do auto-negotiation. */ -#define BMSR_RFAULT 0x0010 /**< Remote fault detected. */ -#define BMSR_ANEGCOMPLETE 0x0020 /**< Auto-negotiation complete. */ -#define BMSR_MFPRESUPPCAP 0x0040 /**< Able to suppress preamble. */ -#define BMSR_RESV 0x0780 /**< Unused. */ -#define BMSR_10HALF 0x0800 /**< Can do 10mbps, half-duplex. */ -#define BMSR_10FULL 0x1000 /**< Can do 10mbps, full-duplex. */ -#define BMSR_100HALF 0x2000 /**< Can do 100mbps, half-duplex. */ -#define BMSR_100FULL 0x4000 /**< Can do 100mbps, full-duplex. */ -#define BMSR_100BASE4 0x8000 /**< Can do 100mbps, 4k packets. */ -/** @} */ - -/** - * @name Advertisement control register - * @{ - */ -#define ADVERTISE_SLCT 0x001f /**< Selector bits. */ -#define ADVERTISE_CSMA 0x0001 /**< Only selector supported. */ -#define ADVERTISE_10HALF 0x0020 /**< Try for 10mbps half-duplex. */ -#define ADVERTISE_10FULL 0x0040 /**< Try for 10mbps full-duplex. */ -#define ADVERTISE_100HALF 0x0080 /**< Try for 100mbps half-duplex. */ -#define ADVERTISE_100FULL 0x0100 /**< Try for 100mbps full-duplex. */ -#define ADVERTISE_100BASE4 0x0200 /**< Try for 100mbps 4k packets. */ -#define ADVERTISE_PAUSE_CAP 0x0400 /**< Try for pause. */ -#define ADVERTISE_PAUSE_ASYM 0x0800 /**< Try for asymetric pause. */ -#define ADVERTISE_RESV 0x1000 /**< Unused. */ -#define ADVERTISE_RFAULT 0x2000 /**< Say we can detect faults. */ -#define ADVERTISE_LPACK 0x4000 /**< Ack link partners response. */ -#define ADVERTISE_NPAGE 0x8000 /**< Next page bit. */ - -#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ - ADVERTISE_CSMA) -#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ - ADVERTISE_100HALF | ADVERTISE_100FULL) -/** @} */ - -/** - * @name Link partner ability register - * @{ - */ -#define LPA_SLCT 0x001f /**< Same as advertise selector. */ -#define LPA_10HALF 0x0020 /**< Can do 10mbps half-duplex. */ -#define LPA_10FULL 0x0040 /**< Can do 10mbps full-duplex. */ -#define LPA_100HALF 0x0080 /**< Can do 100mbps half-duplex. */ -#define LPA_100FULL 0x0100 /**< Can do 100mbps full-duplex. */ -#define LPA_100BASE4 0x0200 /**< Can do 100mbps 4k packets. */ -#define LPA_PAUSE_CAP 0x0400 /**< Can pause. */ -#define LPA_PAUSE_ASYM 0x0800 /**< Can pause asymetrically. */ -#define LPA_RESV 0x1000 /**< Unused. */ -#define LPA_RFAULT 0x2000 /**< Link partner faulted. */ -#define LPA_LPACK 0x4000 /**< Link partner acked us. */ -#define LPA_NPAGE 0x8000 /**< Next page bit. */ - -#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) -#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) -/** @} */ - -/** - * @name Expansion register for auto-negotiation - * @{ - */ -#define EXPANSION_NWAY 0x0001 /**< Can do N-way auto-nego. */ -#define EXPANSION_LCWP 0x0002 /**< Got new RX page code word. */ -#define EXPANSION_ENABLENPAGE 0x0004 /**< This enables npage words. */ -#define EXPANSION_NPCAPABLE 0x0008 /**< Link partner supports npage. */ -#define EXPANSION_MFAULTS 0x0010 /**< Multiple faults detected. */ -#define EXPANSION_RESV 0xffe0 /**< Unused. */ -/** @} */ - -/** - * @name N-way test register - * @{ - */ -#define NWAYTEST_RESV1 0x00ff /**< Unused. */ -#define NWAYTEST_LOOPBACK 0x0100 /**< Enable loopback for N-way. */ -#define NWAYTEST_RESV2 0xfe00 /**< Unused. */ -/** @} */ - -/** - * @name PHY identifiers - * @{ - */ -#define MII_DM9161_ID 0x0181b8a0 -#define MII_AM79C875_ID 0x00225540 -#define MII_KS8721_ID 0x00221610 -#define MII_STE101P_ID 0x00061C50 -#define MII_DP83848I_ID 0x20005C90 -#define MII_LAN8710A_ID 0x0007C0F1 -#define MII_LAN8720_ID 0x0007C0F0 -#define MII_LAN8742A_ID 0x0007C130 -/** @} */ - -#endif /* _MII_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/include/mmc_spi.h b/firmware/ChibiOS_16/os/hal/include/mmc_spi.h deleted file mode 100644 index eb60c25da4..0000000000 --- a/firmware/ChibiOS_16/os/hal/include/mmc_spi.h +++ /dev/null @@ -1,195 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file mmc_spi.h - * @brief MMC over SPI driver header. - * - * @addtogroup MMC_SPI - * @{ - */ - -#ifndef _MMC_SPI_H_ -#define _MMC_SPI_H_ - -#if (HAL_USE_MMC_SPI == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#define MMC_CMD0_RETRY 10U -#define MMC_CMD1_RETRY 100U -#define MMC_ACMD41_RETRY 100U -#define MMC_WAIT_DATA 10000U - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name MMC_SPI configuration options - * @{ - */ -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - * This option is recommended also if the SPI driver does not - * use a DMA channel and heavily loads the CPU. - */ -#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) -#define MMC_NICE_WAITING TRUE -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if (HAL_USE_SPI == FALSE) || (SPI_USE_WAIT == FALSE) -#error "MMC_SPI driver requires HAL_USE_SPI and SPI_USE_WAIT" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief MMC/SD over SPI driver configuration structure. - */ -typedef struct { - /** - * @brief SPI driver associated to this MMC driver. - */ - SPIDriver *spip; - /** - * @brief SPI low speed configuration used during initialization. - */ - const SPIConfig *lscfg; - /** - * @brief SPI high speed configuration used during transfers. - */ - const SPIConfig *hscfg; -} MMCConfig; - -/** - * @brief @p MMCDriver specific methods. - */ -#define _mmc_driver_methods \ - _mmcsd_block_device_methods - -/** - * @extends MMCSDBlockDeviceVMT - * - * @brief @p MMCDriver virtual methods table. - */ -struct MMCDriverVMT { - _mmc_driver_methods -}; - -/** - * @extends MMCSDBlockDevice - * - * @brief Structure representing a MMC/SD over SPI driver. - */ -typedef struct { - /** - * @brief Virtual Methods Table. - */ - const struct MMCDriverVMT *vmt; - _mmcsd_block_device_data - /** - * @brief Current configuration data. - */ - const MMCConfig *config; - /*** - * @brief Addresses use blocks instead of bytes. - */ - bool block_addresses; -} MMCDriver; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Returns the card insertion status. - * @note This macro wraps a low level function named - * @p sdc_lld_is_card_inserted(), this function must be - * provided by the application because it is not part of the - * SDC driver. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @return The card state. - * @retval FALSE card not inserted. - * @retval TRUE card inserted. - * - * @api - */ -#define mmcIsCardInserted(mmcp) mmc_lld_is_card_inserted(mmcp) - -/** - * @brief Returns the write protect status. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @return The card state. - * @retval FALSE card not inserted. - * @retval TRUE card inserted. - * - * @api - */ -#define mmcIsWriteProtected(mmcp) mmc_lld_is_write_protected(mmcp) -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void mmcInit(void); - void mmcObjectInit(MMCDriver *mmcp); - void mmcStart(MMCDriver *mmcp, const MMCConfig *config); - void mmcStop(MMCDriver *mmcp); - bool mmcConnect(MMCDriver *mmcp); - bool mmcDisconnect(MMCDriver *mmcp); - bool mmcStartSequentialRead(MMCDriver *mmcp, uint32_t startblk); - bool mmcSequentialRead(MMCDriver *mmcp, uint8_t *buffer); - bool mmcStopSequentialRead(MMCDriver *mmcp); - bool mmcStartSequentialWrite(MMCDriver *mmcp, uint32_t startblk); - bool mmcSequentialWrite(MMCDriver *mmcp, const uint8_t *buffer); - bool mmcStopSequentialWrite(MMCDriver *mmcp); - bool mmcSync(MMCDriver *mmcp); - bool mmcGetInfo(MMCDriver *mmcp, BlockDeviceInfo *bdip); - bool mmcErase(MMCDriver *mmcp, uint32_t startblk, uint32_t endblk); - bool mmc_lld_is_card_inserted(MMCDriver *mmcp); - bool mmc_lld_is_write_protected(MMCDriver *mmcp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_MMC_SPI == TRUE */ - -#endif /* _MMC_SPI_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/include/pal.h b/firmware/ChibiOS_16/os/hal/include/pal.h deleted file mode 100644 index bd6c94898e..0000000000 --- a/firmware/ChibiOS_16/os/hal/include/pal.h +++ /dev/null @@ -1,642 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file pal.h - * @brief I/O Ports Abstraction Layer macros, types and structures. - * - * @addtogroup PAL - * @{ - */ - -#ifndef _PAL_H_ -#define _PAL_H_ - -#if (HAL_USE_PAL == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name Pads mode constants - * @{ - */ -/** - * @brief After reset state. - * @details The state itself is not specified and is architecture dependent, - * it is guaranteed to be equal to the after-reset state. It is - * usually an input state. - */ -#define PAL_MODE_RESET 0U - -/** - * @brief Safe state for unconnected pads. - * @details The state itself is not specified and is architecture dependent, - * it may be mapped on @p PAL_MODE_INPUT_PULLUP, - * @p PAL_MODE_INPUT_PULLDOWN or @p PAL_MODE_OUTPUT_PUSHPULL for - * example. - */ -#define PAL_MODE_UNCONNECTED 1U - -/** - * @brief Regular input high-Z pad. - */ -#define PAL_MODE_INPUT 2U - -/** - * @brief Input pad with weak pull up resistor. - */ -#define PAL_MODE_INPUT_PULLUP 3U - -/** - * @brief Input pad with weak pull down resistor. - */ -#define PAL_MODE_INPUT_PULLDOWN 4U - -/** - * @brief Analog input mode. - */ -#define PAL_MODE_INPUT_ANALOG 5U - -/** - * @brief Push-pull output pad. - */ -#define PAL_MODE_OUTPUT_PUSHPULL 6U - -/** - * @brief Open-drain output pad. - */ -#define PAL_MODE_OUTPUT_OPENDRAIN 7U -/** @} */ - -/** - * @name Logic level constants - * @{ - */ -/** - * @brief Logical low state. - */ -#define PAL_LOW 0U - -/** - * @brief Logical high state. - */ -#define PAL_HIGH 1U -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -#include "pal_lld.h" - -/** - * @brief I/O bus descriptor. - * @details This structure describes a group of contiguous digital I/O lines - * that have to be handled as bus. - * @note I/O operations on a bus do not affect I/O lines on the same port but - * not belonging to the bus. - */ -typedef struct { - /** - * @brief Port identifier. - */ - ioportid_t portid; - /** - * @brief Bus mask aligned to port bit 0. - * @note The bus mask implicitly define the bus width. A logic AND is - * performed on the bus data. - */ - ioportmask_t mask; - /** - * @brief Offset, within the port, of the least significant bit of the bus. - */ - uint_fast8_t offset; -} IOBus; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Port bit helper macro. - * @details This macro calculates the mask of a bit within a port. - * - * @param[in] n bit position within the port - * @return The bit mask. - */ -#if !defined(PAL_PORT_BIT) || defined(__DOXYGEN__) -#define PAL_PORT_BIT(n) ((ioportmask_t)(1U << (n))) -#endif - -/** - * @brief Bits group mask helper. - * @details This macro calculates the mask of a bits group. - * - * @param[in] width group width - * @return The group mask. - */ -#if !defined(PAL_GROUP_MASK) || defined(__DOXYGEN__) -#define PAL_GROUP_MASK(width) ((ioportmask_t)(1U << (width)) - 1U) -#endif - -/** - * @brief Data part of a static I/O bus initializer. - * @details This macro should be used when statically initializing an I/O bus - * that is part of a bigger structure. - * - * @param[in] name name of the IOBus variable - * @param[in] port I/O port descriptor - * @param[in] width bus width in bits - * @param[in] offset bus bit offset within the port - */ -#define _IOBUS_DATA(name, port, width, offset) \ - {port, PAL_GROUP_MASK(width), offset} - -/** - * @brief Static I/O bus initializer. - * - * @param[in] name name of the IOBus variable - * @param[in] port I/O port descriptor - * @param[in] width bus width in bits - * @param[in] offset bus bit offset within the port - */ -#define IOBUS_DECL(name, port, width, offset) \ - IOBus name = _IOBUS_DATA(name, port, width, offset) - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief PAL subsystem initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @param[in] config pointer to an architecture specific configuration - * structure. This structure is defined in the low level driver - * header. - * - * @init - */ -#define palInit(config) pal_lld_init(config) - -/** - * @brief Reads the physical I/O port states. - * @note The default implementation always return zero and computes the - * parameter eventual side effects. - * @note The function can be called from any context. - * - * @param[in] port port identifier - * @return The port logic states. - * - * @special - */ -#if !defined(pal_lld_readport) || defined(__DOXYGEN__) -#define palReadPort(port) ((void)(port), 0U) -#else -#define palReadPort(port) pal_lld_readport(port) -#endif - -/** - * @brief Reads the output latch. - * @details The purpose of this function is to read back the latched output - * value. - * @note The default implementation always return zero and computes the - * parameter eventual side effects. - * @note The function can be called from any context. - * - * @param[in] port port identifier - * @return The latched logic states. - * - * @special - */ -#if !defined(pal_lld_readlatch) || defined(__DOXYGEN__) -#define palReadLatch(port) ((void)(port), 0U) -#else -#define palReadLatch(port) pal_lld_readlatch(port) -#endif - -/** - * @brief Writes a bits mask on a I/O port. - * @note The default implementation does nothing except computing the - * parameters eventual side effects. - * @note The function can be called from any context. - * - * @param[in] port port identifier - * @param[in] bits bits to be written on the specified port - * - * @special - */ -#if !defined(pal_lld_writeport) || defined(__DOXYGEN__) -#define palWritePort(port, bits) ((void)(port), (void)(bits)) -#else -#define palWritePort(port, bits) pal_lld_writeport(port, bits) -#endif - -/** - * @brief Sets a bits mask on a I/O port. - * @note The operation is not guaranteed to be atomic on all the - * architectures, for atomicity and/or portability reasons you may - * need to enclose port I/O operations between @p osalSysLock() and - * @p osalSysUnlock(). - * @note The default implementation is non atomic and not necessarily - * optimal. Low level drivers may optimize the function by using - * specific hardware or coding. - * @note The function can be called from any context. - * - * @param[in] port port identifier - * @param[in] bits bits to be ORed on the specified port - * - * @special - */ -#if !defined(pal_lld_setport) || defined(__DOXYGEN__) -#define palSetPort(port, bits) \ - palWritePort(port, palReadLatch(port) | (bits)) -#else -#define palSetPort(port, bits) pal_lld_setport(port, bits) -#endif - -/** - * @brief Clears a bits mask on a I/O port. - * @note The operation is not guaranteed to be atomic on all the - * architectures, for atomicity and/or portability reasons you may - * need to enclose port I/O operations between @p osalSysLock() and - * @p osalSysUnlock(). - * @note The default implementation is non atomic and not necessarily - * optimal. Low level drivers may optimize the function by using - * specific hardware or coding. - * @note The function can be called from any context. - * - * @param[in] port port identifier - * @param[in] bits bits to be cleared on the specified port - * - * @special - */ -#if !defined(pal_lld_clearport) || defined(__DOXYGEN__) -#define palClearPort(port, bits) \ - palWritePort(port, palReadLatch(port) & ~(bits)) -#else -#define palClearPort(port, bits) pal_lld_clearport(port, bits) -#endif - -/** - * @brief Toggles a bits mask on a I/O port. - * @note The operation is not guaranteed to be atomic on all the - * architectures, for atomicity and/or portability reasons you may - * need to enclose port I/O operations between @p osalSysLock() and - * @p osalSysUnlock(). - * @note The default implementation is non atomic and not necessarily - * optimal. Low level drivers may optimize the function by using - * specific hardware or coding. - * @note The function can be called from any context. - * - * @param[in] port port identifier - * @param[in] bits bits to be XORed on the specified port - * - * @special - */ -#if !defined(pal_lld_toggleport) || defined(__DOXYGEN__) -#define palTogglePort(port, bits) \ - palWritePort(port, palReadLatch(port) ^ (bits)) -#else -#define palTogglePort(port, bits) pal_lld_toggleport(port, bits) -#endif - -/** - * @brief Reads a group of bits. - * @note The function can be called from any context. - * - * @param[in] port port identifier - * @param[in] mask group mask, a logic AND is performed on the input - * data - * @param[in] offset group bit offset within the port - * @return The group logic states. - * - * @special - */ -#if !defined(pal_lld_readgroup) || defined(__DOXYGEN__) -#define palReadGroup(port, mask, offset) \ - ((palReadPort(port) >> (offset)) & (mask)) -#else -#define palReadGroup(port, mask, offset) pal_lld_readgroup(port, mask, offset) -#endif - -/** - * @brief Writes a group of bits. - * @note The function can be called from any context. - * - * @param[in] port port identifier - * @param[in] mask group mask, a logic AND is performed on the - * output data - * @param[in] offset group bit offset within the port - * @param[in] bits bits to be written. Values exceeding the group - * width are masked. - * - * @special - */ -#if !defined(pal_lld_writegroup) || defined(__DOXYGEN__) -#define palWriteGroup(port, mask, offset, bits) \ - palWritePort(port, (palReadLatch(port) & ~((mask) << (offset))) | \ - (((bits) & (mask)) << (offset))) -#else -#define palWriteGroup(port, mask, offset, bits) \ - pal_lld_writegroup(port, mask, offset, bits) -#endif - - -/** - * @brief Pads group mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * @note Programming an unknown or unsupported mode is silently ignored. - * @note The function can be called from any context. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] offset group bit offset within the port - * @param[in] mode group mode - * - * @special - */ -#if !defined(pal_lld_setgroupmode) || defined(__DOXYGEN__) -#define palSetGroupMode(port, mask, offset, mode) -#else -#define palSetGroupMode(port, mask, offset, mode) \ - pal_lld_setgroupmode(port, mask, offset, mode) -#endif - -/** - * @brief Reads an input pad logic state. - * @note The default implementation not necessarily optimal. Low level - * drivers may optimize the function by using specific hardware - * or coding. - * @note The default implementation internally uses the @p palReadPort(). - * @note The function can be called from any context. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * @return The logic state. - * @retval PAL_LOW low logic state. - * @retval PAL_HIGH high logic state. - * - * @special - */ -#if !defined(pal_lld_readpad) || defined(__DOXYGEN__) -#define palReadPad(port, pad) ((palReadPort(port) >> (pad)) & 1U) -#else -#define palReadPad(port, pad) pal_lld_readpad(port, pad) -#endif - -/** - * @brief Writes a logic state on an output pad. - * @note The operation is not guaranteed to be atomic on all the - * architectures, for atomicity and/or portability reasons you may - * need to enclose port I/O operations between @p osalSysLock() and - * @p osalSysUnlock(). - * @note The default implementation is non atomic and not necessarily - * optimal. Low level drivers may optimize the function by using - * specific hardware or coding. - * @note The default implementation internally uses the @p palReadLatch() - * and @p palWritePort(). - * @note The function can be called from any context. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * @param[in] bit logic value, the value must be @p PAL_LOW or - * @p PAL_HIGH - * - * @special - */ -#if !defined(pal_lld_writepad) || defined(__DOXYGEN__) -#define palWritePad(port, pad, bit) \ - palWritePort(port, (palReadLatch(port) & ~PAL_PORT_BIT(pad)) | \ - (((bit) & 1U) << pad)) -#else -#define palWritePad(port, pad, bit) pal_lld_writepad(port, pad, bit) -#endif - -/** - * @brief Sets a pad logic state to @p PAL_HIGH. - * @note The operation is not guaranteed to be atomic on all the - * architectures, for atomicity and/or portability reasons you may - * need to enclose port I/O operations between @p osalSysLock() and - * @p osalSysUnlock(). - * @note The default implementation is non atomic and not necessarily - * optimal. Low level drivers may optimize the function by using - * specific hardware or coding. - * @note The default implementation internally uses the @p palSetPort(). - * @note The function can be called from any context. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * - * @special - */ -#if !defined(pal_lld_setpad) || defined(__DOXYGEN__) -#define palSetPad(port, pad) palSetPort(port, PAL_PORT_BIT(pad)) -#else -#define palSetPad(port, pad) pal_lld_setpad(port, pad) -#endif - -/** - * @brief Clears a pad logic state to @p PAL_LOW. - * @note The operation is not guaranteed to be atomic on all the - * architectures, for atomicity and/or portability reasons you may - * need to enclose port I/O operations between @p osalSysLock() and - * @p osalSysUnlock(). - * @note The default implementation is non atomic and not necessarily - * optimal. Low level drivers may optimize the function by using - * specific hardware or coding. - * @note The default implementation internally uses the @p palClearPort(). - * @note The function can be called from any context. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * - * @special - */ -#if !defined(pal_lld_clearpad) || defined(__DOXYGEN__) -#define palClearPad(port, pad) palClearPort(port, PAL_PORT_BIT(pad)) -#else -#define palClearPad(port, pad) pal_lld_clearpad(port, pad) -#endif - -/** - * @brief Toggles a pad logic state. - * @note The operation is not guaranteed to be atomic on all the - * architectures, for atomicity and/or portability reasons you may - * need to enclose port I/O operations between @p osalSysLock() and - * @p osalSysUnlock(). - * @note The default implementation is non atomic and not necessarily - * optimal. Low level drivers may optimize the function by using - * specific hardware or coding. - * @note The default implementation internally uses the @p palTogglePort(). - * @note The function can be called from any context. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * - * @special - */ -#if !defined(pal_lld_togglepad) || defined(__DOXYGEN__) -#define palTogglePad(port, pad) palTogglePort(port, PAL_PORT_BIT(pad)) -#else -#define palTogglePad(port, pad) pal_lld_togglepad(port, pad) -#endif - -/** - * @brief Pad mode setup. - * @details This function programs a pad with the specified mode. - * @note The default implementation not necessarily optimal. Low level - * drivers may optimize the function by using specific hardware - * or coding. - * @note Programming an unknown or unsupported mode is silently ignored. - * @note The function can be called from any context. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * @param[in] mode pad mode - * - * @special - */ -#if !defined(pal_lld_setpadmode) || defined(__DOXYGEN__) -#define palSetPadMode(port, pad, mode) \ - palSetGroupMode(port, PAL_PORT_BIT(pad), 0U, mode) -#else -#define palSetPadMode(port, pad, mode) pal_lld_setpadmode(port, pad, mode) -#endif - -/** - * @brief Reads an input line logic state. - * @note The function can be called from any context. - * - * @param[in] line line identifier - * @return The logic state. - * @retval PAL_LOW low logic state. - * @retval PAL_HIGH high logic state. - * - * @special - */ -#if !defined(pal_lld_readline) || defined(__DOXYGEN__) -#define palReadLine(line) palReadPad(PAL_PORT(line), PAL_PAD(line)) -#else -#define palReadLine(line) pal_lld_readline(line) -#endif - -/** - * @brief Writes a logic state on an output line. - * @note The function can be called from any context. - * - * @param[in] line line identifier - * @param[in] bit logic value, the value must be @p PAL_LOW or - * @p PAL_HIGH - * - * @special - */ -#if !defined(pal_lld_writeline) || defined(__DOXYGEN__) -#define palWriteLine(line, bit) palWritePad(PAL_PORT(line), PAL_PAD(line), bit) -#else -#define palWriteLine(line, bit) pal_lld_writeline(line, bit) -#endif - -/** - * @brief Sets a line logic state to @p PAL_HIGH. - * @note The function can be called from any context. - * - * @param[in] line line identifier - * - * @special - */ -#if !defined(pal_lld_setline) || defined(__DOXYGEN__) -#define palSetLine(line) palSetPad(PAL_PORT(line), PAL_PAD(line)) -#else -#define palSetLine(line) pal_lld_setline(line) -#endif - -/** - * @brief Clears a line logic state to @p PAL_LOW. - * @note The function can be called from any context. - * - * @param[in] line line identifier - * - * @special - */ -#if !defined(pal_lld_clearline) || defined(__DOXYGEN__) -#define palClearLine(line) palClearPad(PAL_PORT(line), PAL_PAD(line)) -#else -#define palClearLine(line) pal_lld_clearline(line) -#endif - -/** - * @brief Toggles a line logic state. - * @note The function can be called from any context. - * - * @param[in] line line identifier - * - * @special - */ -#if !defined(pal_lld_toggleline) || defined(__DOXYGEN__) -#define palToggleLine(line) palTogglePad(PAL_PORT(line), PAL_PAD(line)) -#else -#define palToggleLine(line) pal_lld_toggleline(line) -#endif - -/** - * @brief Line mode setup. - * @note The function can be called from any context. - * - * @param[in] line line identifier - * @param[in] mode pad mode - * - * @special - */ -#if !defined(pal_lld_setlinemode) || defined(__DOXYGEN__) -#define palSetLineMode(line, mode) \ - palSetPadMode(PAL_PORT(line), PAL_PAD(line), mode) -#else -#define palSetLineMode(line, mode) pal_lld_setlinemode(line, mode) -#endif -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - ioportmask_t palReadBus(IOBus *bus); - void palWriteBus(IOBus *bus, ioportmask_t bits); - void palSetBusMode(IOBus *bus, iomode_t mode); -#ifdef __cplusplus -} -#endif - -#endif /* _PAL_H_ */ - -#endif /* HAL_USE_PAL == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/include/pwm.h b/firmware/ChibiOS_16/os/hal/include/pwm.h deleted file mode 100644 index 6cd51a34e5..0000000000 --- a/firmware/ChibiOS_16/os/hal/include/pwm.h +++ /dev/null @@ -1,308 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file pwm.h - * @brief PWM Driver macros and structures. - * - * @addtogroup PWM - * @{ - */ - -#ifndef _PWM_H_ -#define _PWM_H_ - -#if (HAL_USE_PWM == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name PWM output mode macros - * @{ - */ -/** - * @brief Standard output modes mask. - */ -#define PWM_OUTPUT_MASK 0x0FU - -/** - * @brief Output not driven, callback only. - */ -#define PWM_OUTPUT_DISABLED 0x00U - -/** - * @brief Positive PWM logic, active is logic level one. - */ -#define PWM_OUTPUT_ACTIVE_HIGH 0x01U - -/** - * @brief Inverse PWM logic, active is logic level zero. - */ -#define PWM_OUTPUT_ACTIVE_LOW 0x02U -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - PWM_UNINIT = 0, /**< Not initialized. */ - PWM_STOP = 1, /**< Stopped. */ - PWM_READY = 2 /**< Ready. */ -} pwmstate_t; - -/** - * @brief Type of a structure representing a PWM driver. - */ -typedef struct PWMDriver PWMDriver; - -/** - * @brief Type of a PWM notification callback. - * - * @param[in] pwmp pointer to a @p PWMDriver object - */ -typedef void (*pwmcallback_t)(PWMDriver *pwmp); - -#include "pwm_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name PWM duty cycle conversion - * @{ - */ -/** - * @brief Converts from fraction to pulse width. - * @note Be careful with rounding errors, this is integer math not magic. - * You can specify tenths of thousandth but make sure you have the - * proper hardware resolution by carefully choosing the clock source - * and prescaler settings, see @p PWM_COMPUTE_PSC. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] denominator denominator of the fraction - * @param[in] numerator numerator of the fraction - * @return The pulse width to be passed to @p pwmEnableChannel(). - * - * @api - */ -#define PWM_FRACTION_TO_WIDTH(pwmp, denominator, numerator) \ - ((pwmcnt_t)((((pwmcnt_t)(pwmp)->period) * \ - (pwmcnt_t)(numerator)) / (pwmcnt_t)(denominator))) - -/** - * @brief Converts from degrees to pulse width. - * @note Be careful with rounding errors, this is integer math not magic. - * You can specify hundredths of degrees but make sure you have the - * proper hardware resolution by carefully choosing the clock source - * and prescaler settings, see @p PWM_COMPUTE_PSC. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] degrees degrees as an integer between 0 and 36000 - * @return The pulse width to be passed to @p pwmEnableChannel(). - * - * @api - */ -#define PWM_DEGREES_TO_WIDTH(pwmp, degrees) \ - PWM_FRACTION_TO_WIDTH(pwmp, 36000, degrees) - -/** - * @brief Converts from percentage to pulse width. - * @note Be careful with rounding errors, this is integer math not magic. - * You can specify tenths of thousandth but make sure you have the - * proper hardware resolution by carefully choosing the clock source - * and prescaler settings, see @p PWM_COMPUTE_PSC. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] percentage percentage as an integer between 0 and 10000 - * @return The pulse width to be passed to @p pwmEnableChannel(). - * - * @api - */ -#define PWM_PERCENTAGE_TO_WIDTH(pwmp, percentage) \ - PWM_FRACTION_TO_WIDTH(pwmp, 10000, percentage) -/** @} */ - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Changes the period the PWM peripheral. - * @details This function changes the period of a PWM unit that has already - * been activated using @p pwmStart(). - * @pre The PWM unit must have been activated using @p pwmStart(). - * @post The PWM unit period is changed to the new value. - * @note If a period is specified that is shorter than the pulse width - * programmed in one of the channels then the behavior is not - * guaranteed. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] value new cycle time in ticks - * - * @iclass - */ -#define pwmChangePeriodI(pwmp, value) { \ - (pwmp)->period = (value); \ - pwm_lld_change_period(pwmp, value); \ -} - -/** - * @brief Enables a PWM channel. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @post The channel is active using the specified configuration. - * @note Depending on the hardware implementation this function has - * effect starting on the next cycle (recommended implementation) - * or immediately (fallback implementation). - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier (0...channels-1) - * @param[in] width PWM pulse width as clock pulses number - * - * @iclass - */ -#define pwmEnableChannelI(pwmp, channel, width) do { \ - (pwmp)->enabled |= ((pwmchnmsk_t)1U << (pwmchnmsk_t)(channel)); \ - pwm_lld_enable_channel(pwmp, channel, width); \ -} while (false) - -/** - * @brief Disables a PWM channel. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @post The channel is disabled and its output line returned to the - * idle state. - * @note Depending on the hardware implementation this function has - * effect starting on the next cycle (recommended implementation) - * or immediately (fallback implementation). - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier (0...channels-1) - * - * @iclass - */ -#define pwmDisableChannelI(pwmp, channel) do { \ - (pwmp)->enabled &= ~((pwmchnmsk_t)1U << (pwmchnmsk_t)(channel)); \ - pwm_lld_disable_channel(pwmp, channel); \ -} while (false) - -/** - * @brief Returns a PWM channel status. - * @pre The PWM unit must have been activated using @p pwmStart(). - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier (0...channels-1) - * - * @iclass - */ -#define pwmIsChannelEnabledI(pwmp, channel) \ - (((pwmp)->enabled & ((pwmchnmsk_t)1U << (pwmchnmsk_t)(channel))) != 0U) - -/** - * @brief Enables the periodic activation edge notification. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @note If the notification is already enabled then the call has no effect. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * - * @iclass - */ -#define pwmEnablePeriodicNotificationI(pwmp) \ - pwm_lld_enable_periodic_notification(pwmp) - -/** - * @brief Disables the periodic activation edge notification. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @note If the notification is already disabled then the call has no effect. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * - * @iclass - */ -#define pwmDisablePeriodicNotificationI(pwmp) \ - pwm_lld_disable_periodic_notification(pwmp) - -/** - * @brief Enables a channel de-activation edge notification. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @pre The channel must have been activated using @p pwmEnableChannel(). - * @note If the notification is already enabled then the call has no effect. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier (0...channels-1) - * - * @iclass - */ -#define pwmEnableChannelNotificationI(pwmp, channel) \ - pwm_lld_enable_channel_notification(pwmp, channel) - -/** - * @brief Disables a channel de-activation edge notification. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @pre The channel must have been activated using @p pwmEnableChannel(). - * @note If the notification is already disabled then the call has no effect. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier (0...channels-1) - * - * @iclass - */ -#define pwmDisableChannelNotificationI(pwmp, channel) \ - pwm_lld_disable_channel_notification(pwmp, channel) -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void pwmInit(void); - void pwmObjectInit(PWMDriver *pwmp); - void pwmStart(PWMDriver *pwmp, const PWMConfig *config); - void pwmStop(PWMDriver *pwmp); - void pwmChangePeriod(PWMDriver *pwmp, pwmcnt_t period); - void pwmEnableChannel(PWMDriver *pwmp, - pwmchannel_t channel, - pwmcnt_t width); - void pwmDisableChannel(PWMDriver *pwmp, pwmchannel_t channel); - void pwmEnablePeriodicNotification(PWMDriver *pwmp); - void pwmDisablePeriodicNotification(PWMDriver *pwmp); - void pwmEnableChannelNotification(PWMDriver *pwmp, pwmchannel_t channel); - void pwmDisableChannelNotification(PWMDriver *pwmp, pwmchannel_t channel); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_PWM == TRUE */ - -#endif /* _PWM_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/include/rtc.h b/firmware/ChibiOS_16/os/hal/include/rtc.h deleted file mode 100644 index 4962e71989..0000000000 --- a/firmware/ChibiOS_16/os/hal/include/rtc.h +++ /dev/null @@ -1,144 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Concepts and parts of this file have been contributed by Uladzimir Pylinsky - aka barthess. - */ - -/** - * @file rtc.h - * @brief RTC Driver macros and structures. - * - * @addtogroup RTC - * @{ - */ - -#ifndef _RTC_H_ -#define _RTC_H_ - -#if (HAL_USE_RTC == TRUE) || defined(__DOXYGEN__) - -/*lint -save -e829 [21.10] The header is required.*/ -#include -/*lint -restore*/ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Base year of the calendar. - */ -#define RTC_BASE_YEAR 1980U - -/** - * @name Date/Time bit masks for FAT format - * @{ - */ -#define RTC_FAT_TIME_SECONDS_MASK 0x0000001FU -#define RTC_FAT_TIME_MINUTES_MASK 0x000007E0U -#define RTC_FAT_TIME_HOURS_MASK 0x0000F800U -#define RTC_FAT_DATE_DAYS_MASK 0x001F0000U -#define RTC_FAT_DATE_MONTHS_MASK 0x01E00000U -#define RTC_FAT_DATE_YEARS_MASK 0xFE000000U -/** @} */ - -/** - * @name Day of week encoding - * @{ - */ -#define RTC_DAY_CATURDAY 0U -#define RTC_DAY_MONDAY 1U -#define RTC_DAY_TUESDAY 2U -#define RTC_DAY_WEDNESDAY 3U -#define RTC_DAY_THURSDAY 4U -#define RTC_DAY_FRIDAY 5U -#define RTC_DAY_SATURDAY 6U -#define RTC_DAY_SUNDAY 7U -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a structure representing an RTC driver. - */ -typedef struct RTCDriver RTCDriver; - -/** - * @brief Type of a structure representing an RTC date/time stamp. - */ -typedef struct { - /*lint -save -e46 [6.1] In this case uint32_t is fine.*/ - uint32_t year: 8; /**< @brief Years since 1980. */ - uint32_t month: 4; /**< @brief Months 1..12. */ - uint32_t dstflag: 1; /**< @brief DST correction flag. */ - uint32_t dayofweek: 3; /**< @brief Day of week 1..7. */ - uint32_t day: 5; /**< @brief Day of the month 1..31. */ - uint32_t millisecond: 27; /**< @brief Milliseconds since midnight.*/ - /*lint -restore*/ -} RTCDateTime; - -#include "rtc_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void rtcInit(void); - void rtcObjectInit(RTCDriver *rtcp); - void rtcSetTime(RTCDriver *rtcp, const RTCDateTime *timespec); - void rtcGetTime(RTCDriver *rtcp, RTCDateTime *timespec); -#if RTC_ALARMS > 0 - void rtcSetAlarm(RTCDriver *rtcp, - rtcalarm_t alarm, - const RTCAlarm *alarmspec); - void rtcGetAlarm(RTCDriver *rtcp, rtcalarm_t alarm, RTCAlarm *alarmspec); -#endif -#if RTC_SUPPORTS_CALLBACKS == TRUE - void rtcSetCallback(RTCDriver *rtcp, rtccb_t callback); -#endif - void rtcConvertDateTimeToStructTm(const RTCDateTime *timespec, - struct tm *timp, - uint32_t *tv_msec); - void rtcConvertStructTmToDateTime(const struct tm *timp, - uint32_t tv_msec, - RTCDateTime *timespec); - uint32_t rtcConvertDateTimeToFAT(const RTCDateTime *timespec); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_RTC == TRUE */ -#endif /* _RTC_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/include/sdc.h b/firmware/ChibiOS_16/os/hal/include/sdc.h deleted file mode 100644 index 38d93edea2..0000000000 --- a/firmware/ChibiOS_16/os/hal/include/sdc.h +++ /dev/null @@ -1,195 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file sdc.h - * @brief SDC Driver macros and structures. - * - * @addtogroup SDC - * @{ - */ - -#ifndef _SDC_H_ -#define _SDC_H_ - -#if (HAL_USE_SDC == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name SD card types - * @{ - */ -#define SDC_MODE_CARDTYPE_MASK 0xFU -#define SDC_MODE_CARDTYPE_SDV11 0U -#define SDC_MODE_CARDTYPE_SDV20 1U -#define SDC_MODE_CARDTYPE_MMC 2U -#define SDC_MODE_HIGH_CAPACITY 0x10U -/** @} */ - -/** - * @name SDC bus error conditions - * @{ - */ -#define SDC_NO_ERROR 0U -#define SDC_CMD_CRC_ERROR 1U -#define SDC_DATA_CRC_ERROR 2U -#define SDC_DATA_TIMEOUT 4U -#define SDC_COMMAND_TIMEOUT 8U -#define SDC_TX_UNDERRUN 16U -#define SDC_RX_OVERRUN 32U -#define SDC_STARTBIT_ERROR 64U -#define SDC_OVERFLOW_ERROR 128U -#define SDC_UNHANDLED_ERROR 0xFFFFFFFFU -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name SDC configuration options - * @{ - */ -/** - * @brief Number of initialization attempts before rejecting the card. - * @note Attempts are performed at 10mS intervals. - */ -#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) -#define SDC_INIT_RETRY 100 -#endif - -/** - * @brief Include support for MMC cards. - * @note MMC support is not yet implemented so this option must be kept - * at @p FALSE. - */ -#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) -#define SDC_MMC_SUPPORT FALSE -#endif - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - */ -#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) -#define SDC_NICE_WAITING TRUE -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of SDIO bus mode. - */ -typedef enum { - SDC_MODE_1BIT = 0, - SDC_MODE_4BIT, - SDC_MODE_8BIT -} sdcbusmode_t; - -/** - * @brief Max supported clock. - */ -typedef enum { - SDC_CLK_25MHz = 0, - SDC_CLK_50MHz -} sdcbusclk_t; - -#include "sdc_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Returns the card insertion status. - * @note This macro wraps a low level function named - * @p sdc_lld_is_card_inserted(), this function must be - * provided by the application because it is not part of the - * SDC driver. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @return The card state. - * @retval FALSE card not inserted. - * @retval TRUE card inserted. - * - * @api - */ -#define sdcIsCardInserted(sdcp) (sdc_lld_is_card_inserted(sdcp)) - -/** - * @brief Returns the write protect status. - * @note This macro wraps a low level function named - * @p sdc_lld_is_write_protected(), this function must be - * provided by the application because it is not part of the - * SDC driver. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @return The card state. - * @retval FALSE not write protected. - * @retval TRUE write protected. - * - * @api - */ -#define sdcIsWriteProtected(sdcp) (sdc_lld_is_write_protected(sdcp)) -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void sdcInit(void); - void sdcObjectInit(SDCDriver *sdcp); - void sdcStart(SDCDriver *sdcp, const SDCConfig *config); - void sdcStop(SDCDriver *sdcp); - bool sdcConnect(SDCDriver *sdcp); - bool sdcDisconnect(SDCDriver *sdcp); - bool sdcRead(SDCDriver *sdcp, uint32_t startblk, - uint8_t *buf, uint32_t n); - bool sdcWrite(SDCDriver *sdcp, uint32_t startblk, - const uint8_t *buf, uint32_t n); - sdcflags_t sdcGetAndClearErrors(SDCDriver *sdcp); - bool sdcSync(SDCDriver *sdcp); - bool sdcGetInfo(SDCDriver *sdcp, BlockDeviceInfo *bdip); - bool sdcErase(SDCDriver *sdcp, uint32_t startblk, uint32_t endblk); - bool _sdc_wait_for_transfer_state(SDCDriver *sdcp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_SDC == TRUE */ - -#endif /* _SDC_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/include/serial.h b/firmware/ChibiOS_16/os/hal/include/serial.h deleted file mode 100644 index ad61dedbe3..0000000000 --- a/firmware/ChibiOS_16/os/hal/include/serial.h +++ /dev/null @@ -1,286 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file serial.h - * @brief Serial Driver macros and structures. - * - * @addtogroup SERIAL - * @{ - */ - -#ifndef _SERIAL_H_ -#define _SERIAL_H_ - -#if (HAL_USE_SERIAL == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name Serial status flags - * @{ - */ -#define SD_PARITY_ERROR (eventflags_t)32 /**< @brief Parity. */ -#define SD_FRAMING_ERROR (eventflags_t)64 /**< @brief Framing. */ -#define SD_OVERRUN_ERROR (eventflags_t)128 /**< @brief Overflow. */ -#define SD_NOISE_ERROR (eventflags_t)256 /**< @brief Line noise. */ -#define SD_BREAK_DETECTED (eventflags_t)512 /**< @brief LIN Break. */ -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Serial configuration options - * @{ - */ -/** - * @brief Default bit rate. - * @details Configuration parameter, this is the baud rate selected for the - * default configuration. - */ -#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SERIAL_DEFAULT_BITRATE 38400 -#endif - -/** - * @brief Serial buffers size. - * @details Configuration parameter, you can change the depth of the queue - * buffers depending on the requirements of your application. - * @note The default is 16 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_BUFFERS_SIZE 16 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - SD_UNINIT = 0, /**< Not initialized. */ - SD_STOP = 1, /**< Stopped. */ - SD_READY = 2 /**< Ready. */ -} sdstate_t; - -/** - * @brief Structure representing a serial driver. - */ -typedef struct SerialDriver SerialDriver; - -#include "serial_lld.h" - -/** - * @brief @p SerialDriver specific methods. - */ -#define _serial_driver_methods \ - _base_asynchronous_channel_methods - -/** - * @extends BaseAsynchronousChannelVMT - * - * @brief @p SerialDriver virtual methods table. - */ -struct SerialDriverVMT { - _serial_driver_methods -}; - -/** - * @extends BaseAsynchronousChannel - * - * @brief Full duplex serial driver class. - * @details This class extends @p BaseAsynchronousChannel by adding physical - * I/O queues. - */ -struct SerialDriver { - /** @brief Virtual Methods Table.*/ - const struct SerialDriverVMT *vmt; - _serial_driver_data -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Direct write to a @p SerialDriver. - * @note This function bypasses the indirect access to the channel and - * writes directly on the output queue. This is faster but cannot - * be used to write to different channels implementations. - * - * @see chnPutTimeout() - * - * @api - */ -#define sdPut(sdp, b) oqPut(&(sdp)->oqueue, b) - -/** - * @brief Direct write to a @p SerialDriver with timeout specification. - * @note This function bypasses the indirect access to the channel and - * writes directly on the output queue. This is faster but cannot - * be used to write to different channels implementations. - * - * @see chnPutTimeout() - * - * @api - */ -#define sdPutTimeout(sdp, b, t) oqPutTimeout(&(sdp)->oqueue, b, t) - -/** - * @brief Direct read from a @p SerialDriver. - * @note This function bypasses the indirect access to the channel and - * reads directly from the input queue. This is faster but cannot - * be used to read from different channels implementations. - * - * @see chnGetTimeout() - * - * @api - */ -#define sdGet(sdp) iqGet(&(sdp)->iqueue) - -/** - * @brief Direct read from a @p SerialDriver with timeout specification. - * @note This function bypasses the indirect access to the channel and - * reads directly from the input queue. This is faster but cannot - * be used to read from different channels implementations. - * - * @see chnGetTimeout() - * - * @api - */ -#define sdGetTimeout(sdp, t) iqGetTimeout(&(sdp)->iqueue, t) - -/** - * @brief Direct blocking write to a @p SerialDriver. - * @note This function bypasses the indirect access to the channel and - * writes directly to the output queue. This is faster but cannot - * be used to write from different channels implementations. - * - * @see chnWrite() - * - * @api - */ -#define sdWrite(sdp, b, n) \ - oqWriteTimeout(&(sdp)->oqueue, b, n, TIME_INFINITE) - -/** - * @brief Direct blocking write to a @p SerialDriver with timeout - * specification. - * @note This function bypasses the indirect access to the channel and - * writes directly to the output queue. This is faster but cannot - * be used to write to different channels implementations. - * - * @see chnWriteTimeout() - * - * @api - */ -#define sdWriteTimeout(sdp, b, n, t) \ - oqWriteTimeout(&(sdp)->oqueue, b, n, t) - -/** - * @brief Direct non-blocking write to a @p SerialDriver. - * @note This function bypasses the indirect access to the channel and - * writes directly to the output queue. This is faster but cannot - * be used to write to different channels implementations. - * - * @see chnWriteTimeout() - * - * @api - */ -#define sdAsynchronousWrite(sdp, b, n) \ - oqWriteTimeout(&(sdp)->oqueue, b, n, TIME_IMMEDIATE) - -/** - * @brief Direct blocking read from a @p SerialDriver. - * @note This function bypasses the indirect access to the channel and - * reads directly from the input queue. This is faster but cannot - * be used to read from different channels implementations. - * - * @see chnRead() - * - * @api - */ -#define sdRead(sdp, b, n) \ - iqReadTimeout(&(sdp)->iqueue, b, n, TIME_INFINITE) - -/** - * @brief Direct blocking read from a @p SerialDriver with timeout - * specification. - * @note This function bypasses the indirect access to the channel and - * reads directly from the input queue. This is faster but cannot - * be used to read from different channels implementations. - * - * @see chnReadTimeout() - * - * @api - */ -#define sdReadTimeout(sdp, b, n, t) \ - iqReadTimeout(&(sdp)->iqueue, b, n, t) - -/** - * @brief Direct non-blocking read from a @p SerialDriver. - * @note This function bypasses the indirect access to the channel and - * reads directly from the input queue. This is faster but cannot - * be used to read from different channels implementations. - * - * @see chnReadTimeout() - * - * @api - */ -#define sdAsynchronousRead(sdp, b, n) \ - iqReadTimeout(&(sdp)->iqueue, b, n, TIME_IMMEDIATE) -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void sdInit(void); - void sdObjectInit(SerialDriver *sdp, qnotify_t inotify, qnotify_t onotify); - void sdStart(SerialDriver *sdp, const SerialConfig *config); - void sdStop(SerialDriver *sdp); - void sdIncomingDataI(SerialDriver *sdp, uint8_t b); - msg_t sdRequestDataI(SerialDriver *sdp); - bool sdPutWouldBlock(SerialDriver *sdp); - bool sdGetWouldBlock(SerialDriver *sdp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_SERIAL == TRUE */ - -#endif /* _SERIAL_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/include/serial_usb.h b/firmware/ChibiOS_16/os/hal/include/serial_usb.h deleted file mode 100644 index 0cc5d19519..0000000000 --- a/firmware/ChibiOS_16/os/hal/include/serial_usb.h +++ /dev/null @@ -1,195 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file serial_usb.h - * @brief Serial over USB Driver macros and structures. - * - * @addtogroup SERIAL_USB - * @{ - */ - -#ifndef _SERIAL_USB_H_ -#define _SERIAL_USB_H_ - -#if (HAL_USE_SERIAL_USB == TRUE) || defined(__DOXYGEN__) - -#include "usb_cdc.h" - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name SERIAL_USB configuration options - * @{ - */ -/** - * @brief Serial over USB buffers size. - * @details Configuration parameter, the buffer size must be a multiple of - * the USB data endpoint maximum packet size. - * @note The default is 256 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_SIZE 256 -#endif - -/** - * @brief Serial over USB number of buffers. - * @note The default is 2 buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_NUMBER 2 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if HAL_USE_USB == FALSE -#error "Serial over USB Driver requires HAL_USE_USB" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - SDU_UNINIT = 0, /**< Not initialized. */ - SDU_STOP = 1, /**< Stopped. */ - SDU_READY = 2 /**< Ready. */ -} sdustate_t; - -/** - * @brief Structure representing a serial over USB driver. - */ -typedef struct SerialUSBDriver SerialUSBDriver; - -/** - * @brief Serial over USB Driver configuration structure. - * @details An instance of this structure must be passed to @p sduStart() - * in order to configure and start the driver operations. - */ -typedef struct { - /** - * @brief USB driver to use. - */ - USBDriver *usbp; - /** - * @brief Bulk IN endpoint used for outgoing data transfer. - */ - usbep_t bulk_in; - /** - * @brief Bulk OUT endpoint used for incoming data transfer. - */ - usbep_t bulk_out; - /** - * @brief Interrupt IN endpoint used for notifications. - * @note If set to zero then the INT endpoint is assumed to be not - * present, USB descriptors must be changed accordingly. - */ - usbep_t int_in; -} SerialUSBConfig; - -/** - * @brief @p SerialDriver specific data. - */ -#define _serial_usb_driver_data \ - _base_asynchronous_channel_data \ - /* Driver state.*/ \ - sdustate_t state; \ - /* Input buffers queue.*/ \ - input_buffers_queue_t ibqueue; \ - /* Output queue.*/ \ - output_buffers_queue_t obqueue; \ - /* Input buffer.*/ \ - uint8_t ib[BQ_BUFFER_SIZE(SERIAL_USB_BUFFERS_NUMBER, \ - SERIAL_USB_BUFFERS_SIZE)]; \ - /* Output buffer.*/ \ - uint8_t ob[BQ_BUFFER_SIZE(SERIAL_USB_BUFFERS_NUMBER, \ - SERIAL_USB_BUFFERS_SIZE)]; \ - /* End of the mandatory fields.*/ \ - /* Current configuration data.*/ \ - const SerialUSBConfig *config; - -/** - * @brief @p SerialUSBDriver specific methods. - */ -#define _serial_usb_driver_methods \ - _base_asynchronous_channel_methods - -/** - * @extends BaseAsynchronousChannelVMT - * - * @brief @p SerialDriver virtual methods table. - */ -struct SerialUSBDriverVMT { - _serial_usb_driver_methods -}; - -/** - * @extends BaseAsynchronousChannel - * - * @brief Full duplex serial driver class. - * @details This class extends @p BaseAsynchronousChannel by adding physical - * I/O queues. - */ -struct SerialUSBDriver { - /** @brief Virtual Methods Table.*/ - const struct SerialUSBDriverVMT *vmt; - _serial_usb_driver_data -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void sduInit(void); - void sduObjectInit(SerialUSBDriver *sdup); - void sduStart(SerialUSBDriver *sdup, const SerialUSBConfig *config); - void sduStop(SerialUSBDriver *sdup); - void sduDisconnectI(SerialUSBDriver *sdup); - void sduConfigureHookI(SerialUSBDriver *sdup); - bool sduRequestsHook(USBDriver *usbp); - void sduSOFHookI(SerialUSBDriver *sdup); - void sduDataTransmitted(USBDriver *usbp, usbep_t ep); - void sduDataReceived(USBDriver *usbp, usbep_t ep); - void sduInterruptTransmitted(USBDriver *usbp, usbep_t ep); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_SERIAL_USB == TRUE */ - -#endif /* _SERIAL_USB_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/include/spi.h b/firmware/ChibiOS_16/os/hal/include/spi.h deleted file mode 100644 index 4c77090232..0000000000 --- a/firmware/ChibiOS_16/os/hal/include/spi.h +++ /dev/null @@ -1,291 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file spi.h - * @brief SPI Driver macros and structures. - * - * @addtogroup SPI - * @{ - */ - -#ifndef _SPI_H_ -#define _SPI_H_ - -#if (HAL_USE_SPI == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name SPI configuration options - * @{ - */ -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) -#define SPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define SPI_USE_MUTUAL_EXCLUSION TRUE -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - SPI_UNINIT = 0, /**< Not initialized. */ - SPI_STOP = 1, /**< Stopped. */ - SPI_READY = 2, /**< Ready. */ - SPI_ACTIVE = 3, /**< Exchanging data. */ - SPI_COMPLETE = 4 /**< Asynchronous operation complete. */ -} spistate_t; - -#include "spi_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Asserts the slave select signal and prepares for transfers. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @iclass - */ -#define spiSelectI(spip) { \ - spi_lld_select(spip); \ -} - -/** - * @brief Deasserts the slave select signal. - * @details The previously selected peripheral is unselected. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @iclass - */ -#define spiUnselectI(spip) { \ - spi_lld_unselect(spip); \ -} - -/** - * @brief Ignores data on the SPI bus. - * @details This asynchronous function starts the transmission of a series of - * idle words on the SPI bus and ignores the received data. - * @pre A slave must have been selected using @p spiSelect() or - * @p spiSelectI(). - * @post At the end of the operation the configured callback is invoked. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be ignored - * - * @iclass - */ -#define spiStartIgnoreI(spip, n) { \ - (spip)->state = SPI_ACTIVE; \ - spi_lld_ignore(spip, n); \ -} - -/** - * @brief Exchanges data on the SPI bus. - * @details This asynchronous function starts a simultaneous transmit/receive - * operation. - * @pre A slave must have been selected using @p spiSelect() or - * @p spiSelectI(). - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be exchanged - * @param[in] txbuf the pointer to the transmit buffer - * @param[out] rxbuf the pointer to the receive buffer - * - * @iclass - */ -#define spiStartExchangeI(spip, n, txbuf, rxbuf) { \ - (spip)->state = SPI_ACTIVE; \ - spi_lld_exchange(spip, n, txbuf, rxbuf); \ -} - -/** - * @brief Sends data over the SPI bus. - * @details This asynchronous function starts a transmit operation. - * @pre A slave must have been selected using @p spiSelect() or - * @p spiSelectI(). - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to send - * @param[in] txbuf the pointer to the transmit buffer - * - * @iclass - */ -#define spiStartSendI(spip, n, txbuf) { \ - (spip)->state = SPI_ACTIVE; \ - spi_lld_send(spip, n, txbuf); \ -} - -/** - * @brief Receives data from the SPI bus. - * @details This asynchronous function starts a receive operation. - * @pre A slave must have been selected using @p spiSelect() or - * @p spiSelectI(). - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to receive - * @param[out] rxbuf the pointer to the receive buffer - * - * @iclass - */ -#define spiStartReceiveI(spip, n, rxbuf) { \ - (spip)->state = SPI_ACTIVE; \ - spi_lld_receive(spip, n, rxbuf); \ -} - -/** - * @brief Exchanges one frame using a polled wait. - * @details This synchronous function exchanges one frame using a polled - * synchronization method. This function is useful when exchanging - * small amount of data on high speed channels, usually in this - * situation is much more efficient just wait for completion using - * polling than suspending the thread waiting for an interrupt. - * @note This API is implemented as a macro in order to minimize latency. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] frame the data frame to send over the SPI bus - * @return The received data frame from the SPI bus. - */ -#define spiPolledExchange(spip, frame) spi_lld_polled_exchange(spip, frame) -/** @} */ - -/** - * @name Low level driver helper macros - * @{ - */ -#if (SPI_USE_WAIT == TRUE) || defined(__DOXYGEN__) -/** - * @brief Wakes up the waiting thread. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -#define _spi_wakeup_isr(spip) { \ - osalSysLockFromISR(); \ - osalThreadResumeI(&(spip)->thread, MSG_OK); \ - osalSysUnlockFromISR(); \ -} -#else /* !SPI_USE_WAIT */ -#define _spi_wakeup_isr(spip) -#endif /* !SPI_USE_WAIT */ - -/** - * @brief Common ISR code. - * @details This code handles the portable part of the ISR code: - * - Callback invocation. - * - Waiting thread wakeup, if any. - * - Driver state transitions. - * . - * @note This macro is meant to be used in the low level drivers - * implementation only. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -#define _spi_isr_code(spip) { \ - if ((spip)->config->end_cb) { \ - (spip)->state = SPI_COMPLETE; \ - (spip)->config->end_cb(spip); \ - if ((spip)->state == SPI_COMPLETE) \ - (spip)->state = SPI_READY; \ - } \ - else \ - (spip)->state = SPI_READY; \ - _spi_wakeup_isr(spip); \ -} -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void spiInit(void); - void spiObjectInit(SPIDriver *spip); - void spiStart(SPIDriver *spip, const SPIConfig *config); - void spiStop(SPIDriver *spip); - void spiSelect(SPIDriver *spip); - void spiUnselect(SPIDriver *spip); - void spiStartIgnore(SPIDriver *spip, size_t n); - void spiStartExchange(SPIDriver *spip, size_t n, - const void *txbuf, void *rxbuf); - void spiStartSend(SPIDriver *spip, size_t n, const void *txbuf); - void spiStartReceive(SPIDriver *spip, size_t n, void *rxbuf); -#if SPI_USE_WAIT == TRUE - void spiIgnore(SPIDriver *spip, size_t n); - void spiExchange(SPIDriver *spip, size_t n, const void *txbuf, void *rxbuf); - void spiSend(SPIDriver *spip, size_t n, const void *txbuf); - void spiReceive(SPIDriver *spip, size_t n, void *rxbuf); -#endif -#if SPI_USE_MUTUAL_EXCLUSION == TRUE - void spiAcquireBus(SPIDriver *spip); - void spiReleaseBus(SPIDriver *spip); -#endif -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_SPI == TRUE */ - -#endif /* _SPI_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/include/st.h b/firmware/ChibiOS_16/os/hal/include/st.h deleted file mode 100644 index 9222279921..0000000000 --- a/firmware/ChibiOS_16/os/hal/include/st.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file st.h - * @brief ST Driver macros and structures. - * @details This header is designed to be include-able without having to - * include other files from the HAL. - * - * @addtogroup ST - * @{ - */ - -#ifndef _ST_H_ -#define _ST_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -#include "st_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Returns the time counter value. - * @note This functionality is only available in free running mode, the - * behaviour in periodic mode is undefined. - * - * @return The counter value. - * - * @api - */ -#define stGetCounter() st_lld_get_counter() - -/** - * @brief Determines if the alarm is active. - * - * @return The alarm status. - * @retval false if the alarm is not active. - * @retval true is the alarm is active - * - * @api - */ -#define stIsAlarmActive() st_lld_is_alarm_active() -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void stInit(void); - void stStartAlarm(systime_t abstime); - void stStopAlarm(void); - void stSetAlarm(systime_t abstime); - systime_t stGetAlarm(void); -#ifdef __cplusplus -} -#endif - -#endif /* _ST_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/include/uart.h b/firmware/ChibiOS_16/os/hal/include/uart.h deleted file mode 100644 index 68d7c1c4cd..0000000000 --- a/firmware/ChibiOS_16/os/hal/include/uart.h +++ /dev/null @@ -1,342 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file uart.h - * @brief UART Driver macros and structures. - * - * @addtogroup UART - * @{ - */ - -#ifndef _UART_H_ -#define _UART_H_ - -#if (HAL_USE_UART == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name UART status flags - * @{ - */ -#define UART_NO_ERROR 0 /**< @brief No pending conditions. */ -#define UART_PARITY_ERROR 4 /**< @brief Parity error happened. */ -#define UART_FRAMING_ERROR 8 /**< @brief Framing error happened. */ -#define UART_OVERRUN_ERROR 16 /**< @brief Overflow happened. */ -#define UART_NOISE_ERROR 32 /**< @brief Noise on the line. */ -#define UART_BREAK_DETECTED 64 /**< @brief Break detected. */ -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name UART configuration options - * @{ - */ -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) -#define UART_USE_WAIT FALSE -#endif - -/** - * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define UART_USE_MUTUAL_EXCLUSION FALSE -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - UART_UNINIT = 0, /**< Not initialized. */ - UART_STOP = 1, /**< Stopped. */ - UART_READY = 2 /**< Ready. */ -} uartstate_t; - -/** - * @brief Transmitter state machine states. - */ -typedef enum { - UART_TX_IDLE = 0, /**< Not transmitting. */ - UART_TX_ACTIVE = 1, /**< Transmitting. */ - UART_TX_COMPLETE = 2 /**< Buffer complete. */ -} uarttxstate_t; - -/** - * @brief Receiver state machine states. - */ -typedef enum { - UART_RX_IDLE = 0, /**< Not receiving. */ - UART_RX_ACTIVE = 1, /**< Receiving. */ - UART_RX_COMPLETE = 2 /**< Buffer complete. */ -} uartrxstate_t; - -#include "uart_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Low level driver helper macros - * @{ - */ -#if (UART_USE_WAIT == TRUE) || defined(__DOXYGEN__) -/** - * @brief Wakes up the waiting thread in case of early TX complete. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @notapi - */ -#define _uart_wakeup_tx1_isr(uartp) { \ - if ((uartp)->early == true) { \ - osalSysLockFromISR(); \ - osalThreadResumeI(&(uartp)->threadtx, MSG_OK); \ - osalSysUnlockFromISR(); \ - } \ -} -#else /* !UART_USE_WAIT */ -#define _uart_wakeup_tx1_isr(uartp) -#endif /* !UART_USE_WAIT */ - -#if (UART_USE_WAIT == TRUE) || defined(__DOXYGEN__) -/** - * @brief Wakes up the waiting thread in case of late TX complete. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @notapi - */ -#define _uart_wakeup_tx2_isr(uartp) { \ - if ((uartp)->early == false) { \ - osalSysLockFromISR(); \ - osalThreadResumeI(&(uartp)->threadtx, MSG_OK); \ - osalSysUnlockFromISR(); \ - } \ -} -#else /* !UART_USE_WAIT */ -#define _uart_wakeup_tx2_isr(uartp) -#endif /* !UART_USE_WAIT */ - -#if (UART_USE_WAIT == TRUE) || defined(__DOXYGEN__) -/** - * @brief Wakes up the waiting thread in case of RX complete. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @notapi - */ -#define _uart_wakeup_rx_complete_isr(uartp) { \ - osalSysLockFromISR(); \ - osalThreadResumeI(&(uartp)->threadrx, MSG_OK); \ - osalSysUnlockFromISR(); \ -} -#else /* !UART_USE_WAIT */ -#define _uart_wakeup_rx_complete_isr(uartp) -#endif /* !UART_USE_WAIT */ - -#if (UART_USE_WAIT == TRUE) || defined(__DOXYGEN__) -/** - * @brief Wakes up the waiting thread in case of RX error. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @notapi - */ -#define _uart_wakeup_rx_error_isr(uartp) { \ - osalSysLockFromISR(); \ - osalThreadResumeI(&(uartp)->threadrx, MSG_RESET); \ - osalSysUnlockFromISR(); \ -} -#else /* !UART_USE_WAIT */ -#define _uart_wakeup_rx_error_isr(uartp) -#endif /* !UART_USE_WAIT */ - -/** - * @brief Common ISR code for early TX. - * @details This code handles the portable part of the ISR code: - * - Callback invocation. - * - Waiting thread wakeup, if any. - * - Driver state transitions. - * . - * @note This macro is meant to be used in the low level drivers - * implementation only. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @notapi - */ -#define _uart_tx1_isr_code(uartp) { \ - (uartp)->txstate = UART_TX_COMPLETE; \ - if ((uartp)->config->txend1_cb != NULL) { \ - (uartp)->config->txend1_cb(uartp); \ - } \ - if ((uartp)->txstate == UART_TX_COMPLETE) { \ - (uartp)->txstate = UART_TX_IDLE; \ - } \ - _uart_wakeup_tx1_isr(uartp); \ -} - -/** - * @brief Common ISR code for late TX. - * @details This code handles the portable part of the ISR code: - * - Callback invocation. - * - Waiting thread wakeup, if any. - * - Driver state transitions. - * . - * @note This macro is meant to be used in the low level drivers - * implementation only. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @notapi - */ -#define _uart_tx2_isr_code(uartp) { \ - if ((uartp)->config->txend2_cb != NULL) { \ - (uartp)->config->txend2_cb(uartp); \ - } \ - _uart_wakeup_tx2_isr(uartp); \ -} - -/** - * @brief Common ISR code for RX complete. - * @details This code handles the portable part of the ISR code: - * - Callback invocation. - * - Waiting thread wakeup, if any. - * - Driver state transitions. - * . - * @note This macro is meant to be used in the low level drivers - * implementation only. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @notapi - */ -#define _uart_rx_complete_isr_code(uartp) { \ - (uartp)->rxstate = UART_RX_COMPLETE; \ - if ((uartp)->config->rxend_cb != NULL) { \ - (uartp)->config->rxend_cb(uartp); \ - } \ - if ((uartp)->rxstate == UART_RX_COMPLETE) { \ - (uartp)->rxstate = UART_RX_IDLE; \ - uart_enter_rx_idle_loop(uartp); \ - } \ - _uart_wakeup_rx_complete_isr(uartp); \ -} - -/** - * @brief Common ISR code for RX error. - * @details This code handles the portable part of the ISR code: - * - Callback invocation. - * - Waiting thread wakeup, if any. - * - Driver state transitions. - * . - * @note This macro is meant to be used in the low level drivers - * implementation only. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] errors mask of errors to be reported - * - * @notapi - */ -#define _uart_rx_error_isr_code(uartp, errors) { \ - if ((uartp)->config->rxerr_cb != NULL) { \ - (uartp)->config->rxerr_cb(uartp, errors); \ - } \ - _uart_wakeup_rx_error_isr(uartp); \ -} - - -/** - * @brief Common ISR code for RX on idle. - * @details This code handles the portable part of the ISR code: - * - Callback invocation. - * - Waiting thread wakeup, if any. - * - Driver state transitions. - * . - * @note This macro is meant to be used in the low level drivers - * implementation only. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @notapi - */ -#define _uart_rx_idle_code(uartp) { \ - if ((uartp)->config->rxchar_cb != NULL) \ - (uartp)->config->rxchar_cb(uartp, (uartp)->rxbuf); \ -} -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void uartInit(void); - void uartObjectInit(UARTDriver *uartp); - void uartStart(UARTDriver *uartp, const UARTConfig *config); - void uartStop(UARTDriver *uartp); - void uartStartSend(UARTDriver *uartp, size_t n, const void *txbuf); - void uartStartSendI(UARTDriver *uartp, size_t n, const void *txbuf); - size_t uartStopSend(UARTDriver *uartp); - size_t uartStopSendI(UARTDriver *uartp); - void uartStartReceive(UARTDriver *uartp, size_t n, void *rxbuf); - void uartStartReceiveI(UARTDriver *uartp, size_t n, void *rxbuf); - size_t uartStopReceive(UARTDriver *uartp); - size_t uartStopReceiveI(UARTDriver *uartp); -#if UART_USE_WAIT == TRUE - msg_t uartSendTimeout(UARTDriver *uartp, size_t *np, - const void *txbuf, systime_t timeout); - msg_t uartSendFullTimeout(UARTDriver *uartp, size_t *np, - const void *txbuf, systime_t timeout); - msg_t uartReceiveTimeout(UARTDriver *uartp, size_t *np, - void *rxbuf, systime_t timeout); -#endif -#if UART_USE_MUTUAL_EXCLUSION == TRUE - void uartAcquireBus(UARTDriver *uartp); - void uartReleaseBus(UARTDriver *uartp); -#endif -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_UART == TRUE */ - -#endif /* _UART_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/include/usb.h b/firmware/ChibiOS_16/os/hal/include/usb.h deleted file mode 100644 index fbe0dbc6db..0000000000 --- a/firmware/ChibiOS_16/os/hal/include/usb.h +++ /dev/null @@ -1,634 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file usb.h - * @brief USB Driver macros and structures. - * - * @addtogroup USB - * @{ - */ - -#ifndef _USB_H_ -#define _USB_H_ - -#if (HAL_USE_USB == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#define USB_ENDPOINT_OUT(ep) (ep) -#define USB_ENDPOINT_IN(ep) ((ep) | 0x80U) - -#define USB_RTYPE_DIR_MASK 0x80U -#define USB_RTYPE_DIR_HOST2DEV 0x00U -#define USB_RTYPE_DIR_DEV2HOST 0x80U -#define USB_RTYPE_TYPE_MASK 0x60U -#define USB_RTYPE_TYPE_STD 0x00U -#define USB_RTYPE_TYPE_CLASS 0x20U -#define USB_RTYPE_TYPE_VENDOR 0x40U -#define USB_RTYPE_TYPE_RESERVED 0x60U -#define USB_RTYPE_RECIPIENT_MASK 0x1FU -#define USB_RTYPE_RECIPIENT_DEVICE 0x00U -#define USB_RTYPE_RECIPIENT_INTERFACE 0x01U -#define USB_RTYPE_RECIPIENT_ENDPOINT 0x02U -#define USB_RTYPE_RECIPIENT_OTHER 0x03U - -#define USB_REQ_GET_STATUS 0U -#define USB_REQ_CLEAR_FEATURE 1U -#define USB_REQ_SET_FEATURE 3U -#define USB_REQ_SET_ADDRESS 5U -#define USB_REQ_GET_DESCRIPTOR 6U -#define USB_REQ_SET_DESCRIPTOR 7U -#define USB_REQ_GET_CONFIGURATION 8U -#define USB_REQ_SET_CONFIGURATION 9U -#define USB_REQ_GET_INTERFACE 10U -#define USB_REQ_SET_INTERFACE 11U -#define USB_REQ_SYNCH_FRAME 12U - -#define USB_DESCRIPTOR_DEVICE 1U -#define USB_DESCRIPTOR_CONFIGURATION 2U -#define USB_DESCRIPTOR_STRING 3U -#define USB_DESCRIPTOR_INTERFACE 4U -#define USB_DESCRIPTOR_ENDPOINT 5U -#define USB_DESCRIPTOR_DEVICE_QUALIFIER 6U -#define USB_DESCRIPTOR_OTHER_SPEED_CFG 7U -#define USB_DESCRIPTOR_INTERFACE_POWER 8U -#define USB_DESCRIPTOR_INTERFACE_ASSOCIATION 11U - -#define USB_FEATURE_ENDPOINT_HALT 0U -#define USB_FEATURE_DEVICE_REMOTE_WAKEUP 1U -#define USB_FEATURE_TEST_MODE 2U - -#define USB_EARLY_SET_ADDRESS 0 -#define USB_LATE_SET_ADDRESS 1 - -#define USB_EP0_STATUS_STAGE_SW 0 -#define USB_EP0_STATUS_STAGE_HW 1 - -#define USB_SET_ADDRESS_ACK_SW 0 -#define USB_SET_ADDRESS_ACK_HW 1 - -/** - * @name Helper macros for USB descriptors - * @{ - */ -/** - * @brief Helper macro for index values into descriptor strings. - */ -#define USB_DESC_INDEX(i) ((uint8_t)(i)) - -/** - * @brief Helper macro for byte values into descriptor strings. - */ -#define USB_DESC_BYTE(b) ((uint8_t)(b)) - -/** - * @brief Helper macro for word values into descriptor strings. - */ -#define USB_DESC_WORD(w) \ - (uint8_t)((w) & 255U), \ - (uint8_t)(((w) >> 8) & 255U) - -/** - * @brief Helper macro for BCD values into descriptor strings. - */ -#define USB_DESC_BCD(bcd) \ - (uint8_t)((bcd) & 255U), \ - (uint8_t)(((bcd) >> 8) & 255) - -/* - * @define Device Descriptor size. - */ -#define USB_DESC_DEVICE_SIZE 18U - -/** - * @brief Device Descriptor helper macro. - */ -#define USB_DESC_DEVICE(bcdUSB, bDeviceClass, bDeviceSubClass, \ - bDeviceProtocol, bMaxPacketSize, idVendor, \ - idProduct, bcdDevice, iManufacturer, \ - iProduct, iSerialNumber, bNumConfigurations) \ - USB_DESC_BYTE(USB_DESC_DEVICE_SIZE), \ - USB_DESC_BYTE(USB_DESCRIPTOR_DEVICE), \ - USB_DESC_BCD(bcdUSB), \ - USB_DESC_BYTE(bDeviceClass), \ - USB_DESC_BYTE(bDeviceSubClass), \ - USB_DESC_BYTE(bDeviceProtocol), \ - USB_DESC_BYTE(bMaxPacketSize), \ - USB_DESC_WORD(idVendor), \ - USB_DESC_WORD(idProduct), \ - USB_DESC_BCD(bcdDevice), \ - USB_DESC_INDEX(iManufacturer), \ - USB_DESC_INDEX(iProduct), \ - USB_DESC_INDEX(iSerialNumber), \ - USB_DESC_BYTE(bNumConfigurations) - -/** - * @brief Configuration Descriptor size. - */ -#define USB_DESC_CONFIGURATION_SIZE 9U - -/** - * @brief Configuration Descriptor helper macro. - */ -#define USB_DESC_CONFIGURATION(wTotalLength, bNumInterfaces, \ - bConfigurationValue, iConfiguration, \ - bmAttributes, bMaxPower) \ - USB_DESC_BYTE(USB_DESC_CONFIGURATION_SIZE), \ - USB_DESC_BYTE(USB_DESCRIPTOR_CONFIGURATION), \ - USB_DESC_WORD(wTotalLength), \ - USB_DESC_BYTE(bNumInterfaces), \ - USB_DESC_BYTE(bConfigurationValue), \ - USB_DESC_INDEX(iConfiguration), \ - USB_DESC_BYTE(bmAttributes), \ - USB_DESC_BYTE(bMaxPower) - -/** - * @brief Interface Descriptor size. - */ -#define USB_DESC_INTERFACE_SIZE 9U - -/** - * @brief Interface Descriptor helper macro. - */ -#define USB_DESC_INTERFACE(bInterfaceNumber, bAlternateSetting, \ - bNumEndpoints, bInterfaceClass, \ - bInterfaceSubClass, bInterfaceProtocol, \ - iInterface) \ - USB_DESC_BYTE(USB_DESC_INTERFACE_SIZE), \ - USB_DESC_BYTE(USB_DESCRIPTOR_INTERFACE), \ - USB_DESC_BYTE(bInterfaceNumber), \ - USB_DESC_BYTE(bAlternateSetting), \ - USB_DESC_BYTE(bNumEndpoints), \ - USB_DESC_BYTE(bInterfaceClass), \ - USB_DESC_BYTE(bInterfaceSubClass), \ - USB_DESC_BYTE(bInterfaceProtocol), \ - USB_DESC_INDEX(iInterface) - -/** - * @brief Interface Association Descriptor size. - */ -#define USB_DESC_INTERFACE_ASSOCIATION_SIZE 8U - -/** - * @brief Interface Association Descriptor helper macro. - */ -#define USB_DESC_INTERFACE_ASSOCIATION(bFirstInterface, \ - bInterfaceCount, bFunctionClass, \ - bFunctionSubClass, bFunctionProcotol, \ - iInterface) \ - USB_DESC_BYTE(USB_DESC_INTERFACE_ASSOCIATION_SIZE), \ - USB_DESC_BYTE(USB_DESCRIPTOR_INTERFACE_ASSOCIATION), \ - USB_DESC_BYTE(bFirstInterface), \ - USB_DESC_BYTE(bInterfaceCount), \ - USB_DESC_BYTE(bFunctionClass), \ - USB_DESC_BYTE(bFunctionSubClass), \ - USB_DESC_BYTE(bFunctionProcotol), \ - USB_DESC_INDEX(iInterface) - -/** - * @brief Endpoint Descriptor size. - */ -#define USB_DESC_ENDPOINT_SIZE 7U - -/** - * @brief Endpoint Descriptor helper macro. - */ -#define USB_DESC_ENDPOINT(bEndpointAddress, bmAttributes, wMaxPacketSize, \ - bInterval) \ - USB_DESC_BYTE(USB_DESC_ENDPOINT_SIZE), \ - USB_DESC_BYTE(USB_DESCRIPTOR_ENDPOINT), \ - USB_DESC_BYTE(bEndpointAddress), \ - USB_DESC_BYTE(bmAttributes), \ - USB_DESC_WORD(wMaxPacketSize), \ - USB_DESC_BYTE(bInterval) -/** @} */ - -/** - * @name Endpoint types and settings - * @{ - */ -#define USB_EP_MODE_TYPE 0x0003U /**< Endpoint type mask. */ -#define USB_EP_MODE_TYPE_CTRL 0x0000U /**< Control endpoint. */ -#define USB_EP_MODE_TYPE_ISOC 0x0001U /**< Isochronous endpoint. */ -#define USB_EP_MODE_TYPE_BULK 0x0002U /**< Bulk endpoint. */ -#define USB_EP_MODE_TYPE_INTR 0x0003U /**< Interrupt endpoint. */ -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) -#define USB_USE_WAIT FALSE -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a structure representing an USB driver. - */ -typedef struct USBDriver USBDriver; - -/** - * @brief Type of an endpoint identifier. - */ -typedef uint8_t usbep_t; - -/** - * @brief Type of a driver state machine possible states. - */ -typedef enum { - USB_UNINIT = 0, /**< Not initialized. */ - USB_STOP = 1, /**< Stopped. */ - USB_READY = 2, /**< Ready, after bus reset. */ - USB_SELECTED = 3, /**< Address assigned. */ - USB_ACTIVE = 4, /**< Active, configuration selected.*/ - USB_SUSPENDED = 5 /**< Suspended, low power mode. */ -} usbstate_t; - -/** - * @brief Type of an endpoint status. - */ -typedef enum { - EP_STATUS_DISABLED = 0, /**< Endpoint not active. */ - EP_STATUS_STALLED = 1, /**< Endpoint opened but stalled. */ - EP_STATUS_ACTIVE = 2 /**< Active endpoint. */ -} usbepstatus_t; - -/** - * @brief Type of an endpoint zero state machine states. - */ -typedef enum { - USB_EP0_WAITING_SETUP, /**< Waiting for SETUP data. */ - USB_EP0_TX, /**< Transmitting. */ - USB_EP0_WAITING_TX0, /**< Waiting transmit 0. */ - USB_EP0_WAITING_STS, /**< Waiting status. */ - USB_EP0_RX, /**< Receiving. */ - USB_EP0_SENDING_STS, /**< Sending status. */ - USB_EP0_ERROR /**< Error, EP0 stalled. */ -} usbep0state_t; - -/** - * @brief Type of an enumeration of the possible USB events. - */ -typedef enum { - USB_EVENT_RESET = 0, /**< Driver has been reset by host. */ - USB_EVENT_ADDRESS = 1, /**< Address assigned. */ - USB_EVENT_CONFIGURED = 2, /**< Configuration selected. */ - USB_EVENT_UNCONFIGURED = 3, /**< Configuration removed. */ - USB_EVENT_SUSPEND = 4, /**< Entering suspend mode. */ - USB_EVENT_WAKEUP = 5, /**< Leaving suspend mode. */ - USB_EVENT_STALLED = 6 /**< Endpoint 0 error, stalled. */ -} usbevent_t; - -/** - * @brief Type of an USB descriptor. - */ -typedef struct { - /** - * @brief Descriptor size in unicode characters. - */ - size_t ud_size; - /** - * @brief Pointer to the descriptor. - */ - const uint8_t *ud_string; -} USBDescriptor; - -/** - * @brief Type of an USB generic notification callback. - * - * @param[in] usbp pointer to the @p USBDriver object triggering the - * callback - */ -typedef void (*usbcallback_t)(USBDriver *usbp); - -/** - * @brief Type of an USB endpoint callback. - * - * @param[in] usbp pointer to the @p USBDriver object triggering the - * callback - * @param[in] ep endpoint number - */ -typedef void (*usbepcallback_t)(USBDriver *usbp, usbep_t ep); - -/** - * @brief Type of an USB event notification callback. - * - * @param[in] usbp pointer to the @p USBDriver object triggering the - * callback - * @param[in] event event type - */ -typedef void (*usbeventcb_t)(USBDriver *usbp, usbevent_t event); - -/** - * @brief Type of a requests handler callback. - * @details The request is encoded in the @p usb_setup buffer. - * - * @param[in] usbp pointer to the @p USBDriver object triggering the - * callback - * @return The request handling exit code. - * @retval false Request not recognized by the handler. - * @retval true Request handled. - */ -typedef bool (*usbreqhandler_t)(USBDriver *usbp); - -/** - * @brief Type of an USB descriptor-retrieving callback. - */ -typedef const USBDescriptor * (*usbgetdescriptor_t)(USBDriver *usbp, - uint8_t dtype, - uint8_t dindex, - uint16_t lang); - -#include "usb_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Returns the driver state. - * - * @param[in] usbp pointer to the @p USBDriver object - * @return The driver state. - * - * @iclass - */ -#define usbGetDriverStateI(usbp) ((usbp)->state) - -/** - * @brief Connects the USB device. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @api - */ -#define usbConnectBus(usbp) usb_lld_connect_bus(usbp) - -/** - * @brief Disconnect the USB device. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @api - */ -#define usbDisconnectBus(usbp) usb_lld_disconnect_bus(usbp) - -/** - * @brief Returns the current frame number. - * - * @param[in] usbp pointer to the @p USBDriver object - * @return The current frame number. - * - * @xclass - */ -#define usbGetFrameNumberX(usbp) usb_lld_get_frame_number(usbp) - -/** - * @brief Returns the status of an IN endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @return The operation status. - * @retval false Endpoint ready. - * @retval true Endpoint transmitting. - * - * @iclass - */ -#define usbGetTransmitStatusI(usbp, ep) \ - (((usbp)->transmitting & (uint16_t)((unsigned)1U << (unsigned)(ep))) != 0U) - -/** - * @brief Returns the status of an OUT endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @return The operation status. - * @retval false Endpoint ready. - * @retval true Endpoint receiving. - * - * @iclass - */ -#define usbGetReceiveStatusI(usbp, ep) \ - (((usbp)->receiving & (uint16_t)((unsigned)1U << (unsigned)(ep))) != 0U) - -/** - * @brief Returns the exact size of a receive transaction. - * @details The received size can be different from the size specified in - * @p usbStartReceiveI() because the last packet could have a size - * different from the expected one. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @return Received data size. - * - * @xclass - */ -#define usbGetReceiveTransactionSizeX(usbp, ep) \ - usb_lld_get_transaction_size(usbp, ep) - -/** - * @brief Request transfer setup. - * @details This macro is used by the request handling callbacks in order to - * prepare a transaction over the endpoint zero. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] buf pointer to a buffer for the transaction data - * @param[in] n number of bytes to be transferred - * @param[in] endcb callback to be invoked after the transfer or @p NULL - * - * @special - */ -#define usbSetupTransfer(usbp, buf, n, endcb) { \ - (usbp)->ep0next = (buf); \ - (usbp)->ep0n = (n); \ - (usbp)->ep0endcb = (endcb); \ -} - -/** - * @brief Reads a setup packet from the dedicated packet buffer. - * @details This function must be invoked in the context of the @p setup_cb - * callback in order to read the received setup packet. - * @pre In order to use this function the endpoint must have been - * initialized as a control endpoint. - * @note This function can be invoked both in thread and IRQ context. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @param[out] buf buffer where to copy the packet data - * - * @special - */ -#define usbReadSetup(usbp, ep, buf) usb_lld_read_setup(usbp, ep, buf) -/** @} */ - -/** - * @name Low level driver helper macros - * @{ - */ -/** - * @brief Common ISR code, usb event callback. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] evt USB event code - * - * @notapi - */ -#define _usb_isr_invoke_event_cb(usbp, evt) { \ - if (((usbp)->config->event_cb) != NULL) { \ - (usbp)->config->event_cb(usbp, evt); \ - } \ -} - -/** - * @brief Common ISR code, SOF callback. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -#define _usb_isr_invoke_sof_cb(usbp) { \ - if (((usbp)->config->sof_cb) != NULL) { \ - (usbp)->config->sof_cb(usbp); \ - } \ -} - -/** - * @brief Common ISR code, setup packet callback. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -#define _usb_isr_invoke_setup_cb(usbp, ep) { \ - (usbp)->epc[ep]->setup_cb(usbp, ep); \ -} - -/** - * @brief Common ISR code, IN endpoint callback. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -#if (USB_USE_WAIT == TRUE) || defined(__DOXYGEN__) -#define _usb_isr_invoke_in_cb(usbp, ep) { \ - (usbp)->transmitting &= ~(1 << (ep)); \ - if ((usbp)->epc[ep]->in_cb != NULL) { \ - (usbp)->epc[ep]->in_cb(usbp, ep); \ - } \ - osalSysLockFromISR(); \ - osalThreadResumeI(&(usbp)->epc[ep]->in_state->thread, MSG_OK); \ - osalSysUnlockFromISR(); \ -} -#else -#define _usb_isr_invoke_in_cb(usbp, ep) { \ - (usbp)->transmitting &= ~(1 << (ep)); \ - if ((usbp)->epc[ep]->in_cb != NULL) { \ - (usbp)->epc[ep]->in_cb(usbp, ep); \ - } \ -} -#endif - -/** - * @brief Common ISR code, OUT endpoint event. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -#if (USB_USE_WAIT == TRUE) || defined(__DOXYGEN__) -#define _usb_isr_invoke_out_cb(usbp, ep) { \ - (usbp)->receiving &= ~(1 << (ep)); \ - if ((usbp)->epc[ep]->out_cb != NULL) { \ - (usbp)->epc[ep]->out_cb(usbp, ep); \ - } \ - osalSysLockFromISR(); \ - osalThreadResumeI(&(usbp)->epc[ep]->out_state->thread, \ - usbGetReceiveTransactionSizeX(usbp, ep)); \ - osalSysUnlockFromISR(); \ -} -#else -#define _usb_isr_invoke_out_cb(usbp, ep) { \ - (usbp)->receiving &= ~(1 << (ep)); \ - if ((usbp)->epc[ep]->out_cb != NULL) { \ - (usbp)->epc[ep]->out_cb(usbp, ep); \ - } \ -} -#endif -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void usbInit(void); - void usbObjectInit(USBDriver *usbp); - void usbStart(USBDriver *usbp, const USBConfig *config); - void usbStop(USBDriver *usbp); - void usbInitEndpointI(USBDriver *usbp, usbep_t ep, - const USBEndpointConfig *epcp); - void usbDisableEndpointsI(USBDriver *usbp); - void usbReadSetupI(USBDriver *usbp, usbep_t ep, uint8_t *buf); - void usbStartReceiveI(USBDriver *usbp, usbep_t ep, - uint8_t *buf, size_t n); - void usbStartTransmitI(USBDriver *usbp, usbep_t ep, - const uint8_t *buf, size_t n); -#if USB_USE_WAIT == TRUE - msg_t usbReceive(USBDriver *usbp, usbep_t ep, uint8_t *buf, size_t n); - msg_t usbTransmit(USBDriver *usbp, usbep_t ep, const uint8_t *buf, size_t n); -#endif - bool usbStallReceiveI(USBDriver *usbp, usbep_t ep); - bool usbStallTransmitI(USBDriver *usbp, usbep_t ep); - void _usb_reset(USBDriver *usbp); - void _usb_suspend(USBDriver *usbp); - void _usb_wakeup(USBDriver *usbp); - void _usb_ep0setup(USBDriver *usbp, usbep_t ep); - void _usb_ep0in(USBDriver *usbp, usbep_t ep); - void _usb_ep0out(USBDriver *usbp, usbep_t ep); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_USB == TRUE */ - -#endif /* _USB_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/include/usb_cdc.h b/firmware/ChibiOS_16/os/hal/include/usb_cdc.h deleted file mode 100644 index eb1d4e06ed..0000000000 --- a/firmware/ChibiOS_16/os/hal/include/usb_cdc.h +++ /dev/null @@ -1,136 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file usb_cdc.h - * @brief USB CDC macros and structures. - * - * @addtogroup USB_CDC - * @{ - */ - -#ifndef _USB_CDC_H_ -#define _USB_CDC_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name CDC specific messages. - * @{ - */ -#define CDC_SEND_ENCAPSULATED_COMMAND 0x00U -#define CDC_GET_ENCAPSULATED_RESPONSE 0x01U -#define CDC_SET_COMM_FEATURE 0x02U -#define CDC_GET_COMM_FEATURE 0x03U -#define CDC_CLEAR_COMM_FEATURE 0x04U -#define CDC_SET_AUX_LINE_STATE 0x10U -#define CDC_SET_HOOK_STATE 0x11U -#define CDC_PULSE_SETUP 0x12U -#define CDC_SEND_PULSE 0x13U -#define CDC_SET_PULSE_TIME 0x14U -#define CDC_RING_AUX_JACK 0x15U -#define CDC_SET_LINE_CODING 0x20U -#define CDC_GET_LINE_CODING 0x21U -#define CDC_SET_CONTROL_LINE_STATE 0x22U -#define CDC_SEND_BREAK 0x23U -#define CDC_SET_RINGER_PARMS 0x30U -#define CDC_GET_RINGER_PARMS 0x31U -#define CDC_SET_OPERATION_PARMS 0x32U -#define CDC_GET_OPERATION_PARMS 0x33U -/** @} */ - -/** - * @name CDC classes - * @{ - */ -#define CDC_COMMUNICATION_INTERFACE_CLASS 0x02U -#define CDC_DATA_INTERFACE_CLASS 0x0AU -/** @} */ - -/** - * @name CDC subclasses - * @{ - */ -#define CDC_ABSTRACT_CONTROL_MODEL 0x02U -/** @} */ - -/** - * @name CDC descriptors - * @{ - */ -#define CDC_CS_INTERFACE 0x24U -/** @} */ - -/** - * @name CDC subdescriptors - * @{ - */ -#define CDC_HEADER 0x00U -#define CDC_CALL_MANAGEMENT 0x01U -#define CDC_ABSTRACT_CONTROL_MANAGEMENT 0x02U -#define CDC_UNION 0x06U -/** @} */ - -/** - * @name Line Control bit definitions. - * @{ - */ -#define LC_STOP_1 0U -#define LC_STOP_1P5 1U -#define LC_STOP_2 2U - -#define LC_PARITY_NONE 0U -#define LC_PARITY_ODD 1U -#define LC_PARITY_EVEN 2U -#define LC_PARITY_MARK 3U -#define LC_PARITY_SPACE 4U -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of Line Coding structure. - */ -typedef struct { - uint8_t dwDTERate[4]; - uint8_t bCharFormat; - uint8_t bParityType; - uint8_t bDataBits; -} cdc_linecoding_t; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#endif /* _USB_CDC_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/include/wdg.h b/firmware/ChibiOS_16/os/hal/include/wdg.h deleted file mode 100644 index 9aed3090fa..0000000000 --- a/firmware/ChibiOS_16/os/hal/include/wdg.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file wdg.h - * @brief WDG Driver macros and structures. - * - * @addtogroup WDG - * @{ - */ - -#ifndef _WDG_H_ -#define _WDG_H_ - -#if (HAL_USE_WDG == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - WDG_UNINIT = 0, /**< Not initialized. */ - WDG_STOP = 1, /**< Stopped. */ - WDG_READY = 2 /**< Ready. */ -} wdgstate_t; - -#include "wdg_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Resets WDG's counter. - * - * @param[in] wdgp pointer to the @p WDGDriver object - * - * @iclass - */ -#define wdgResetI(wdgp) wdg_lld_reset(wdgp) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void wdgInit(void); - void wdgStart(WDGDriver *wdgp, const WDGConfig * config); - void wdgStop(WDGDriver *wdgp); - void wdgReset(WDGDriver *wdgp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_WDG == TRUE */ - -#endif /* _WDG_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/lib/streams/chprintf.c b/firmware/ChibiOS_16/os/hal/lib/streams/chprintf.c deleted file mode 100644 index 351b09a77b..0000000000 --- a/firmware/ChibiOS_16/os/hal/lib/streams/chprintf.c +++ /dev/null @@ -1,370 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - Concepts and parts of this file have been contributed by Fabio Utzig, - chvprintf() added by Brent Roman. - */ - -/** - * @file chprintf.c - * @brief Mini printf-like functionality. - * - * @addtogroup chprintf - * @{ - */ - -#include "hal.h" -#include "chprintf.h" -#include "memstreams.h" - -#define MAX_FILLER 11 -#define FLOAT_PRECISION 9 - -static char *long_to_string_with_divisor(char *p, - long num, - unsigned radix, - long divisor) { - int i; - char *q; - long l, ll; - - l = num; - if (divisor == 0) { - ll = num; - } else { - ll = divisor; - } - - q = p + MAX_FILLER; - do { - i = (int)(l % radix); - i += '0'; - if (i > '9') - i += 'A' - '0' - 10; - *--q = i; - l /= radix; - } while ((ll /= radix) != 0); - - i = (int)(p + MAX_FILLER - q); - do - *p++ = *q++; - while (--i); - - return p; -} - -static char *ch_ltoa(char *p, long num, unsigned radix) { - - return long_to_string_with_divisor(p, num, radix, 0); -} - -#if CHPRINTF_USE_FLOAT -static const long pow10[FLOAT_PRECISION] = { - 10, 100, 1000, 10000, 100000, 1000000, 10000000, 100000000, 1000000000 -}; - -static char *ftoa(char *p, double num, unsigned long precision) { - long l; - - if ((precision == 0) || (precision > FLOAT_PRECISION)) - precision = FLOAT_PRECISION; - precision = pow10[precision - 1]; - - l = (long)num; - p = long_to_string_with_divisor(p, l, 10, 0); - *p++ = '.'; - l = (long)((num - l) * precision); - return long_to_string_with_divisor(p, l, 10, precision / 10); -} -#endif - -/** - * @brief System formatted output function. - * @details This function implements a minimal @p vprintf()-like functionality - * with output on a @p BaseSequentialStream. - * The general parameters format is: %[-][width|*][.precision|*][l|L]p. - * The following parameter types (p) are supported: - * - x hexadecimal integer. - * - X hexadecimal long. - * - o octal integer. - * - O octal long. - * - d decimal signed integer. - * - D decimal signed long. - * - u decimal unsigned integer. - * - U decimal unsigned long. - * - c character. - * - s string. - * . - * - * @param[in] chp pointer to a @p BaseSequentialStream implementing object - * @param[in] fmt formatting string - * @param[in] ap list of parameters - * @return The number of bytes that would have been - * written to @p chp if no stream error occurs - * - * @api - */ -int chvprintf(BaseSequentialStream *chp, const char *fmt, va_list ap) { - char *p, *s, c, filler; - int i, precision, width; - int n = 0; - bool is_long, left_align; - long l; -#if CHPRINTF_USE_FLOAT - float f; - char tmpbuf[2*MAX_FILLER + 1]; -#else - char tmpbuf[MAX_FILLER + 1]; -#endif - - while (true) { - c = *fmt++; - if (c == 0) - return n; - if (c != '%') { - streamPut(chp, (uint8_t)c); - n++; - continue; - } - p = tmpbuf; - s = tmpbuf; - left_align = FALSE; - if (*fmt == '-') { - fmt++; - left_align = TRUE; - } - filler = ' '; - if (*fmt == '0') { - fmt++; - filler = '0'; - } - width = 0; - while (TRUE) { - c = *fmt++; - if (c >= '0' && c <= '9') - c -= '0'; - else if (c == '*') - c = va_arg(ap, int); - else - break; - width = width * 10 + c; - } - precision = 0; - if (c == '.') { - while (TRUE) { - c = *fmt++; - if (c >= '0' && c <= '9') - c -= '0'; - else if (c == '*') - c = va_arg(ap, int); - else - break; - precision *= 10; - precision += c; - } - } - /* Long modifier.*/ - if (c == 'l' || c == 'L') { - is_long = TRUE; - if (*fmt) - c = *fmt++; - } - else - is_long = (c >= 'A') && (c <= 'Z'); - - /* Command decoding.*/ - switch (c) { - case 'c': - filler = ' '; - *p++ = va_arg(ap, int); - break; - case 's': - filler = ' '; - if ((s = va_arg(ap, char *)) == 0) - s = "(null)"; - if (precision == 0) - precision = 32767; - for (p = s; *p && (--precision >= 0); p++) - ; - break; - case 'D': - case 'd': - case 'I': - case 'i': - if (is_long) - l = va_arg(ap, long); - else - l = va_arg(ap, int); - if (l < 0) { - *p++ = '-'; - l = -l; - } - p = ch_ltoa(p, l, 10); - break; -#if CHPRINTF_USE_FLOAT - case 'f': - f = (float) va_arg(ap, double); - if (f < 0) { - *p++ = '-'; - f = -f; - } - p = ftoa(p, f, precision); - break; -#endif - case 'X': - case 'x': - c = 16; - goto unsigned_common; - case 'U': - case 'u': - c = 10; - goto unsigned_common; - case 'O': - case 'o': - c = 8; -unsigned_common: - if (is_long) - l = va_arg(ap, unsigned long); - else - l = va_arg(ap, unsigned int); - p = ch_ltoa(p, l, c); - break; - default: - *p++ = c; - break; - } - i = (int)(p - s); - if ((width -= i) < 0) - width = 0; - if (left_align == FALSE) - width = -width; - if (width < 0) { - if (*s == '-' && filler == '0') { - streamPut(chp, (uint8_t)*s++); - n++; - i--; - } - do { - streamPut(chp, (uint8_t)filler); - n++; - } while (++width != 0); - } - while (--i >= 0) { - streamPut(chp, (uint8_t)*s++); - n++; - } - - while (width) { - streamPut(chp, (uint8_t)filler); - n++; - width--; - } - } -} - -/** - * @brief System formatted output function. - * @details This function implements a minimal @p printf() like functionality - * with output on a @p BaseSequentialStream. - * The general parameters format is: %[-][width|*][.precision|*][l|L]p. - * The following parameter types (p) are supported: - * - x hexadecimal integer. - * - X hexadecimal long. - * - o octal integer. - * - O octal long. - * - d decimal signed integer. - * - D decimal signed long. - * - u decimal unsigned integer. - * - U decimal unsigned long. - * - c character. - * - s string. - * . - * - * @param[in] chp pointer to a @p BaseSequentialStream implementing object - * @param[in] fmt formatting string - * - * @api - */ -int chprintf(BaseSequentialStream *chp, const char *fmt, ...) { - va_list ap; - int formatted_bytes; - - va_start(ap, fmt); - formatted_bytes = chvprintf(chp, fmt, ap); - va_end(ap); - - return formatted_bytes; -} - -/** - * @brief System formatted output function. - * @details This function implements a minimal @p snprintf()-like functionality. - * The general parameters format is: %[-][width|*][.precision|*][l|L]p. - * The following parameter types (p) are supported: - * - x hexadecimal integer. - * - X hexadecimal long. - * - o octal integer. - * - O octal long. - * - d decimal signed integer. - * - D decimal signed long. - * - u decimal unsigned integer. - * - U decimal unsigned long. - * - c character. - * - s string. - * . - * @post @p str is NUL-terminated, unless @p size is 0. - * - * @param[in] str pointer to a buffer - * @param[in] size maximum size of the buffer - * @param[in] fmt formatting string - * @return The number of characters (excluding the - * terminating NUL byte) that would have been - * stored in @p str if there was room. - * - * @api - */ -int chsnprintf(char *str, size_t size, const char *fmt, ...) { - va_list ap; - MemoryStream ms; - BaseSequentialStream *chp; - size_t size_wo_nul; - int retval; - - if (size > 0) - size_wo_nul = size - 1; - else - size_wo_nul = 0; - - /* Memory stream object to be used as a string writer, reserving one - byte for the final zero.*/ - msObjectInit(&ms, (uint8_t *)str, size_wo_nul, 0); - - /* Performing the print operation using the common code.*/ - chp = (BaseSequentialStream *)(void *)&ms; - va_start(ap, fmt); - retval = chvprintf(chp, fmt, ap); - va_end(ap); - - /* Terminate with a zero, unless size==0.*/ - if (ms.eos < size) - str[ms.eos] = 0; - - /* Return number of bytes that would have been written.*/ - return retval; -} - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/lib/streams/chprintf.h b/firmware/ChibiOS_16/os/hal/lib/streams/chprintf.h deleted file mode 100644 index a86af2e4b1..0000000000 --- a/firmware/ChibiOS_16/os/hal/lib/streams/chprintf.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file chprintf.h - * @brief Mini printf-like functionality. - * - * @addtogroup chprintf - * @{ - */ - -#ifndef _CHPRINTF_H_ -#define _CHPRINTF_H_ - -#include - -/** - * @brief Float type support. - */ -#if !defined(CHPRINTF_USE_FLOAT) || defined(__DOXYGEN__) -#define CHPRINTF_USE_FLOAT FALSE -#endif - -#ifdef __cplusplus -extern "C" { -#endif - int chvprintf(BaseSequentialStream *chp, const char *fmt, va_list ap); - int chprintf(BaseSequentialStream *chp, const char *fmt, ...); - int chsnprintf(char *str, size_t size, const char *fmt, ...); -#ifdef __cplusplus -} -#endif - -#endif /* _CHPRINTF_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/lib/streams/memstreams.c b/firmware/ChibiOS_16/os/hal/lib/streams/memstreams.c deleted file mode 100644 index 13b42f3d1c..0000000000 --- a/firmware/ChibiOS_16/os/hal/lib/streams/memstreams.c +++ /dev/null @@ -1,113 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file memstreams.c - * @brief Memory streams code. - * - * @addtogroup memory_streams - * @{ - */ - -#include - -#include "hal.h" -#include "memstreams.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static size_t writes(void *ip, const uint8_t *bp, size_t n) { - MemoryStream *msp = ip; - - if (msp->size - msp->eos < n) - n = msp->size - msp->eos; - memcpy(msp->buffer + msp->eos, bp, n); - msp->eos += n; - return n; -} - -static size_t reads(void *ip, uint8_t *bp, size_t n) { - MemoryStream *msp = ip; - - if (msp->eos - msp->offset < n) - n = msp->eos - msp->offset; - memcpy(bp, msp->buffer + msp->offset, n); - msp->offset += n; - return n; -} - -static msg_t put(void *ip, uint8_t b) { - MemoryStream *msp = ip; - - if (msp->size - msp->eos <= 0) - return MSG_RESET; - *(msp->buffer + msp->eos) = b; - msp->eos += 1; - return MSG_OK; -} - -static msg_t get(void *ip) { - uint8_t b; - MemoryStream *msp = ip; - - if (msp->eos - msp->offset <= 0) - return MSG_RESET; - b = *(msp->buffer + msp->offset); - msp->offset += 1; - return b; -} - -static const struct MemStreamVMT vmt = {writes, reads, put, get}; - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Memory stream object initialization. - * - * @param[out] msp pointer to the @p MemoryStream object to be initialized - * @param[in] buffer pointer to the memory buffer for the memory stream - * @param[in] size total size of the memory stream buffer - * @param[in] eos initial End Of Stream offset. Normally you need to - * put this to zero for RAM buffers or equal to @p size - * for ROM streams. - */ -void msObjectInit(MemoryStream *msp, uint8_t *buffer, - size_t size, size_t eos) { - - msp->vmt = &vmt; - msp->buffer = buffer; - msp->size = size; - msp->eos = eos; - msp->offset = 0; -} - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/lib/streams/memstreams.h b/firmware/ChibiOS_16/os/hal/lib/streams/memstreams.h deleted file mode 100644 index 789ca96fe0..0000000000 --- a/firmware/ChibiOS_16/os/hal/lib/streams/memstreams.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file memstreams.h - * @brief Memory streams structures and macros. - - * @addtogroup memory_streams - * @{ - */ - -#ifndef _MEMSTREAMS_H_ -#define _MEMSTREAMS_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief @p MemStream specific data. - */ -#define _memory_stream_data \ - _base_sequential_stream_data \ - /* Pointer to the stream buffer.*/ \ - uint8_t *buffer; \ - /* Size of the stream.*/ \ - size_t size; \ - /* Current end of stream.*/ \ - size_t eos; \ - /* Current read offset.*/ \ - size_t offset; - -/** - * @brief @p MemStream virtual methods table. - */ -struct MemStreamVMT { - _base_sequential_stream_methods -}; - -/** - * @extends BaseSequentialStream - * - * @brief Memory stream object. - */ -typedef struct { - /** @brief Virtual Methods Table.*/ - const struct MemStreamVMT *vmt; - _memory_stream_data -} MemoryStream; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void msObjectInit(MemoryStream *msp, uint8_t *buffer, - size_t size, size_t eos); -#ifdef __cplusplus -} -#endif - -#endif /* _MEMSTREAMS_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/lib/streams/nullstreams.c b/firmware/ChibiOS_16/os/hal/lib/streams/nullstreams.c deleted file mode 100644 index 8c2dcf5da5..0000000000 --- a/firmware/ChibiOS_16/os/hal/lib/streams/nullstreams.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file nullstreams.c - * @brief Null streams code. - * - * @addtogroup null_streams - * @{ - */ - -#include "hal.h" -#include "nullstreams.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static size_t writes(void *ip, const uint8_t *bp, size_t n) { - - (void)ip; - (void)bp; - - return n; -} - -static size_t reads(void *ip, uint8_t *bp, size_t n) { - - (void)ip; - (void)bp; - (void)n; - - return 0; -} - -static msg_t put(void *ip, uint8_t b) { - - (void)ip; - (void)b; - - return MSG_OK; -} - -static msg_t get(void *ip) { - - (void)ip; - - return 4; -} - -static const struct NullStreamVMT vmt = {writes, reads, put, get}; - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Null stream object initialization. - * - * @param[out] nsp pointer to the @p NullStream object to be initialized - */ -void nullObjectInit(NullStream *nsp) { - - nsp->vmt = &vmt; -} - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/lib/streams/nullstreams.h b/firmware/ChibiOS_16/os/hal/lib/streams/nullstreams.h deleted file mode 100644 index 7aecc221b3..0000000000 --- a/firmware/ChibiOS_16/os/hal/lib/streams/nullstreams.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file nullstreams.h - * @brief Null streams structures and macros. - - * @addtogroup null_streams - * @{ - */ - -#ifndef _NULLSTREAMS_H_ -#define _NULLSTREAMS_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief @p NullStream specific data. - */ -#define _null_stream_data \ - _base_sequential_stream_data - -/** - * @brief @p NullStream virtual methods table. - */ -struct NullStreamVMT { - _base_sequential_stream_methods -}; - -/** - * @extends BaseSequentialStream - * - * @brief Null stream object. - */ -typedef struct { - /** @brief Virtual Methods Table.*/ - const struct NullStreamVMT *vmt; - _null_stream_data -} NullStream; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void nullObjectInit(NullStream *nsp); -#ifdef __cplusplus -} -#endif - -#endif /* _NULLSTREAMS_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/osal/nil/osal.c b/firmware/ChibiOS_16/os/hal/osal/nil/osal.c deleted file mode 100644 index 4ec1023cb4..0000000000 --- a/firmware/ChibiOS_16/os/hal/osal/nil/osal.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file osal.c - * @brief OSAL module code. - * - * @addtogroup OSAL - * @{ - */ - -#include "osal.h" - -/*===========================================================================*/ -/* Module local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -/** - * @brief Dequeues and wakes up one thread from the queue, if any. - * - * @param[in] tqp pointer to the threads queue object - * @param[in] msg the message code - * - * @iclass - */ -void osalThreadDequeueNextI(threads_queue_t *tqp, msg_t msg) { - semaphore_t *sp = &tqp->sem; - - if (chSemGetCounterI(&tqp->sem) < (cnt_t)0) { - thread_t *tp = nil.threads; - while (true) { - /* Is this thread waiting on this semaphore?*/ - if (tp->u1.semp == sp) { - sp->cnt++; - - chDbgAssert(NIL_THD_IS_WTSEM(tp), "not waiting"); - - (void) chSchReadyI(tp, msg); - return; - } - tp++; - - chDbgAssert(tp < &nil.threads[NIL_CFG_NUM_THREADS], - "pointer out of range"); - } - } -} - -/** - * @brief Dequeues and wakes up all threads from the queue. - * - * @param[in] tqp pointer to the threads queue object - * @param[in] msg the message code - * - * @iclass - */ -void osalThreadDequeueAllI(threads_queue_t *tqp, msg_t msg) { - semaphore_t *sp = &tqp->sem; - thread_t *tp; - cnt_t cnt; - - cnt = sp->cnt; - sp->cnt = (cnt_t)0; - tp = nil.threads; - while (cnt < (cnt_t)0) { - - chDbgAssert(tp < &nil.threads[NIL_CFG_NUM_THREADS], - "pointer out of range"); - - /* Is this thread waiting on this semaphore?*/ - if (tp->u1.semp == sp) { - - chDbgAssert(NIL_THD_IS_WTSEM(tp), "not waiting"); - - cnt++; - (void) chSchReadyI(tp, msg); - } - tp++; - } -} - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/osal/nil/osal.h b/firmware/ChibiOS_16/os/hal/osal/nil/osal.h deleted file mode 100644 index b205ab06a2..0000000000 --- a/firmware/ChibiOS_16/os/hal/osal/nil/osal.h +++ /dev/null @@ -1,920 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file osal.h - * @brief OSAL module header. - * - * @addtogroup OSAL - * @{ - */ - -#ifndef _OSAL_H_ -#define _OSAL_H_ - -#include -#include -#include - -#include "nil.h" - -#if defined(__SPC5_HAL__) -#include "platform.h" -#endif - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @name Common constants - * @{ - */ -#if !defined(FALSE) || defined(__DOXYGEN__) -#define FALSE 0 -#endif - -#if !defined(TRUE) || defined(__DOXYGEN__) -#define TRUE (!FALSE) -#endif - -#define OSAL_SUCCESS FALSE -#define OSAL_FAILED TRUE -/** @} */ - -#if 0 -/** - * @name Messages - * @{ - */ -#define MSG_OK RDY_OK -#define MSG_RESET RDY_RESET -#define MSG_TIMEOUT RDY_TIMEOUT -/** @} */ -#endif - -#if 0 -/** - * @name Special time constants - * @{ - */ -#define TIME_IMMEDIATE ((systime_t)0) -#define TIME_INFINITE ((systime_t)-1) -/** @} */ -#endif - -/** - * @name Systick modes. - * @{ - */ -#define OSAL_ST_MODE_NONE 0 -#define OSAL_ST_MODE_PERIODIC 1 -#define OSAL_ST_MODE_FREERUNNING 2 -/** @} */ - -/** - * @name Systick parameters. - * @{ - */ -/** - * @brief Size in bits of the @p systick_t type. - */ -#define OSAL_ST_RESOLUTION NIL_CFG_ST_RESOLUTION - -/** - * @brief Required systick frequency or resolution. - */ -#define OSAL_ST_FREQUENCY NIL_CFG_ST_FREQUENCY - -/** - * @brief Systick mode required by the underlying OS. - */ -#if (NIL_CFG_ST_TIMEDELTA == 0) || defined(__DOXYGEN__) -#define OSAL_ST_MODE OSAL_ST_MODE_PERIODIC -#else -#define OSAL_ST_MODE OSAL_ST_MODE_FREERUNNING -#endif -/** @} */ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if NIL_CFG_USE_EVENTS == FALSE -#error "OSAL requires NIL_CFG_USE_EVENTS=TRUE" -#endif - -#if !(OSAL_ST_MODE == OSAL_ST_MODE_NONE) && \ - !(OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) && \ - !(OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING) -#error "invalid OSAL_ST_MODE setting in osal.h" -#endif - -#if (OSAL_ST_RESOLUTION != 16) && (OSAL_ST_RESOLUTION != 32) -#error "invalid OSAL_ST_RESOLUTION, must be 16 or 32" -#endif - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -#if 0 -/** - * @brief Type of a system status word. - */ -typedef uint32_t syssts_t; -#endif - -#if 0 -/** - * @brief Type of a message. - */ -typedef int32_t msg_t; -#endif - -#if 0 -/** - * @brief Type of system time counter. - */ -typedef uint32_t systime_t; -#endif - -#if 0 -/** - * @brief Type of realtime counter. - */ -typedef uint32_t rtcnt_t; -#endif - -#if 0 -/** - * @brief Type of a thread reference. - */ -typedef thread_t * thread_reference_t; -#endif - -/** - * @brief Type of an event flags object. - * @note The content of this structure is not part of the API and should - * not be relied upon. Implementers may define this structure in - * an entirely different way. - * @note Retrieval and clearing of the flags are not defined in this - * API and are implementation-dependent. - */ -typedef struct event_source event_source_t; - -/** - * @brief Type of an event source callback. - * @note This type is not part of the OSAL API and is provided - * exclusively as an example and for convenience. - */ -typedef void (*eventcallback_t)(event_source_t *p); - -/** - * @brief Type of an event flags mask. - */ -typedef uint32_t eventflags_t; - -/** - * @brief Events source object. - * @note The content of this structure is not part of the API and should - * not be relied upon. Implementers may define this structure in - * an entirely different way. - * @note Retrieval and clearing of the flags are not defined in this - * API and are implementation-dependent. - */ -struct event_source { - volatile eventflags_t flags; /**< @brief Stored event flags. */ - eventcallback_t cb; /**< @brief Event source callback. */ - void *param; /**< @brief User defined field. */ -}; - -/** - * @brief Type of a mutex. - * @note If the OS does not support mutexes or there is no OS then them - * mechanism can be simulated. - */ -typedef semaphore_t mutex_t; - -/** - * @brief Type of a thread queue. - * @details A thread queue is a queue of sleeping threads, queued threads - * can be dequeued one at time or all together. - * @note In this implementation it is implemented as a single reference - * because there are no real threads. - */ -typedef struct { - semaphore_t sem; -} threads_queue_t; - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @name Debug related macros - * @{ - */ -/** - * @brief Condition assertion. - * @details If the condition check fails then the OSAL panics with a - * message and halts. - * @note The condition is tested only if the @p OSAL_ENABLE_ASSERTIONS - * switch is enabled. - * @note The remark string is not currently used except for putting a - * comment in the code about the assertion. - * - * @param[in] c the condition to be verified to be true - * @param[in] remark a remark string - * - * @api - */ -#define osalDbgAssert(c, remark) chDbgAssert(c, remark) - -/** - * @brief Function parameters check. - * @details If the condition check fails then the OSAL panics and halts. - * @note The condition is tested only if the @p OSAL_ENABLE_CHECKS switch - * is enabled. - * - * @param[in] c the condition to be verified to be true - * - * @api - */ -#define osalDbgCheck(c) chDbgAssert(c, "parameter check") - -/** - * @brief I-Class state check. - * @note Not implemented in this simplified OSAL. - */ -#define osalDbgCheckClassI() /*chDbgCheckClassI()*/ - -/** - * @brief S-Class state check. - * @note Not implemented in this simplified OSAL. - */ -#define osalDbgCheckClassS() /*chDbgCheckClassS()*/ -/** @} */ - -/** - * @name IRQ service routines wrappers - * @{ - */ -/** - * @brief Priority level verification macro. - */ -#define OSAL_IRQ_IS_VALID_PRIORITY(n) CH_IRQ_IS_VALID_KERNEL_PRIORITY(n) - -/** - * @brief IRQ prologue code. - * @details This macro must be inserted at the start of all IRQ handlers. - */ -#define OSAL_IRQ_PROLOGUE() CH_IRQ_PROLOGUE() - -/** - * @brief IRQ epilogue code. - * @details This macro must be inserted at the end of all IRQ handlers. - */ -#define OSAL_IRQ_EPILOGUE() CH_IRQ_EPILOGUE() - -/** - * @brief IRQ handler function declaration. - * @details This macro hides the details of an ISR function declaration. - * - * @param[in] id a vector name as defined in @p vectors.s - */ -#define OSAL_IRQ_HANDLER(id) CH_IRQ_HANDLER(id) -/** @} */ - -/** - * @name Time conversion utilities - * @{ - */ -/** - * @brief Seconds to system ticks. - * @details Converts from seconds to system ticks number. - * @note The result is rounded upward to the next tick boundary. - * - * @param[in] sec number of seconds - * @return The number of ticks. - * - * @api - */ -#define OSAL_S2ST(sec) S2ST(sec) - -/** - * @brief Milliseconds to system ticks. - * @details Converts from milliseconds to system ticks number. - * @note The result is rounded upward to the next tick boundary. - * - * @param[in] msec number of milliseconds - * @return The number of ticks. - * - * @api - */ -#define OSAL_MS2ST(msec) MS2ST(msec) - -/** - * @brief Microseconds to system ticks. - * @details Converts from microseconds to system ticks number. - * @note The result is rounded upward to the next tick boundary. - * - * @param[in] usec number of microseconds - * @return The number of ticks. - * - * @api - */ -#define OSAL_US2ST(usec) US2ST(usec) -/** @} */ - -/** - * @name Time conversion utilities for the realtime counter - * @{ - */ -/** - * @brief Seconds to realtime counter. - * @details Converts from seconds to realtime counter cycles. - * @note The macro assumes that @p freq >= @p 1. - * - * @param[in] freq clock frequency, in Hz, of the realtime counter - * @param[in] sec number of seconds - * @return The number of cycles. - * - * @api - */ -#define OSAL_S2RTC(freq, sec) S2RTC(freq, sec) - -/** - * @brief Milliseconds to realtime counter. - * @details Converts from milliseconds to realtime counter cycles. - * @note The result is rounded upward to the next millisecond boundary. - * @note The macro assumes that @p freq >= @p 1000. - * - * @param[in] freq clock frequency, in Hz, of the realtime counter - * @param[in] msec number of milliseconds - * @return The number of cycles. - * - * @api - */ -#define OSAL_MS2RTC(freq, msec) MS2RTC(freq, msec) - -/** - * @brief Microseconds to realtime counter. - * @details Converts from microseconds to realtime counter cycles. - * @note The result is rounded upward to the next microsecond boundary. - * @note The macro assumes that @p freq >= @p 1000000. - * - * @param[in] freq clock frequency, in Hz, of the realtime counter - * @param[in] usec number of microseconds - * @return The number of cycles. - * - * @api - */ -#define OSAL_US2RTC(freq, usec) US2RTC(freq, usec) -/** @} */ - -/** - * @name Sleep macros using absolute time - * @{ - */ -/** - * @brief Delays the invoking thread for the specified number of seconds. - * @note The specified time is rounded up to a value allowed by the real - * system tick clock. - * @note The maximum specifiable value is implementation dependent. - * - * @param[in] sec time in seconds, must be different from zero - * - * @api - */ -#define osalThreadSleepSeconds(sec) osalThreadSleep(OSAL_S2ST(sec)) - -/** - * @brief Delays the invoking thread for the specified number of - * milliseconds. - * @note The specified time is rounded up to a value allowed by the real - * system tick clock. - * @note The maximum specifiable value is implementation dependent. - * - * @param[in] msec time in milliseconds, must be different from zero - * - * @api - */ -#define osalThreadSleepMilliseconds(msec) osalThreadSleep(OSAL_MS2ST(msec)) - -/** - * @brief Delays the invoking thread for the specified number of - * microseconds. - * @note The specified time is rounded up to a value allowed by the real - * system tick clock. - * @note The maximum specifiable value is implementation dependent. - * - * @param[in] usec time in microseconds, must be different from zero - * - * @api - */ -#define osalThreadSleepMicroseconds(usec) osalThreadSleep(OSAL_US2ST(usec)) -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void osalThreadDequeueNextI(threads_queue_t *tqp, msg_t msg); - void osalThreadDequeueAllI(threads_queue_t *tqp, msg_t msg); -#ifdef __cplusplus -} -#endif - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -/** - * @brief OSAL module initialization. - * - * @api - */ -static inline void osalInit(void) { - -} - -/** - * @brief System halt with error message. - * - * @param[in] reason the halt message pointer - * - * @api - */ -static inline void osalSysHalt(const char *reason) { - - chSysHalt(reason); -} - -/** - * @brief Disables interrupts globally. - * - * @special - */ -static inline void osalSysDisable(void) { - - chSysDisable(); -} - -/** - * @brief Enables interrupts globally. - * - * @special - */ -static inline void osalSysEnable(void) { - - chSysEnable(); -} - -/** - * @brief Enters a critical zone from thread context. - * @note This function cannot be used for reentrant critical zones. - * - * @special - */ -static inline void osalSysLock(void) { - - chSysLock(); -} - -/** - * @brief Leaves a critical zone from thread context. - * @note This function cannot be used for reentrant critical zones. - * - * @special - */ -static inline void osalSysUnlock(void) { - - chSysUnlock(); -} - -/** - * @brief Enters a critical zone from ISR context. - * @note This function cannot be used for reentrant critical zones. - * - * @special - */ -static inline void osalSysLockFromISR(void) { - - chSysLockFromISR(); -} - -/** - * @brief Leaves a critical zone from ISR context. - * @note This function cannot be used for reentrant critical zones. - * - * @special - */ -static inline void osalSysUnlockFromISR(void) { - - chSysUnlockFromISR(); -} - -/** - * @brief Returns the execution status and enters a critical zone. - * @details This functions enters into a critical zone and can be called - * from any context. Because its flexibility it is less efficient - * than @p chSysLock() which is preferable when the calling context - * is known. - * @post The system is in a critical zone. - * - * @return The previous system status, the encoding of this - * status word is architecture-dependent and opaque. - * - * @xclass - */ -static inline syssts_t osalSysGetStatusAndLockX(void) { - - return chSysGetStatusAndLockX(); -} - -/** - * @brief Restores the specified execution status and leaves a critical zone. - * @note A call to @p chSchRescheduleS() is automatically performed - * if exiting the critical zone and if not in ISR context. - * - * @param[in] sts the system status to be restored. - * - * @xclass - */ -static inline void osalSysRestoreStatusX(syssts_t sts) { - - chSysRestoreStatusX(sts); -} - -/** - * @brief Polled delay. - * @note The real delay is always few cycles in excess of the specified - * value. - * - * @param[in] cycles number of cycles - * - * @xclass - */ -#if (PORT_SUPPORTS_RT == TRUE) || defined(__DOXYGEN__) -static inline void osalSysPolledDelayX(rtcnt_t cycles) { - - chSysPolledDelayX(cycles); -} -#endif - -/** - * @brief Systick callback for the underlying OS. - * @note This callback is only defined if the OSAL requires such a - * service from the HAL. - */ -#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__) -static inline void osalOsTimerHandlerI(void) { - - chSysTimerHandlerI(); -} -#endif - -/** - * @brief Checks if a reschedule is required and performs it. - * @note I-Class functions invoked from thread context must not reschedule - * by themselves, an explicit reschedule using this function is - * required in this scenario. - * @note Not implemented in this simplified OSAL. - * - * @sclass - */ -static inline void osalOsRescheduleS(void) { - - chSchRescheduleS(); -} - -/** - * @brief Current system time. - * @details Returns the number of system ticks since the @p osalInit() - * invocation. - * @note The counter can reach its maximum and then restart from zero. - * @note This function can be called from any context but its atomicity - * is not guaranteed on architectures whose word size is less than - * @p systime_t size. - * - * @return The system time in ticks. - * - * @xclass - */ -static inline systime_t osalOsGetSystemTimeX(void) { - - return chVTGetSystemTimeX(); -} - -/** - * @brief Checks if the specified time is within the specified time window. - * @note When start==end then the function returns always true because the - * whole time range is specified. - * @note This function can be called from any context. - * - * @param[in] time the time to be verified - * @param[in] start the start of the time window (inclusive) - * @param[in] end the end of the time window (non inclusive) - * @retval true current time within the specified time window. - * @retval false current time not within the specified time window. - * - * @xclass - */ -static inline bool osalOsIsTimeWithinX(systime_t time, - systime_t start, - systime_t end) { - - return chVTIsTimeWithinX(time, start, end); -} - -/** - * @brief Suspends the invoking thread for the specified time. - * - * @param[in] time the delay in system ticks, the special values are - * handled as follow: - * - @a TIME_INFINITE is allowed but interpreted as a - * normal time specification. - * - @a TIME_IMMEDIATE this value is not allowed. - * . - * - * @sclass - */ -static inline void osalThreadSleepS(systime_t time) { - - chThdSleepS(time); -} - -/** - * @brief Suspends the invoking thread for the specified time. - * - * @param[in] time the delay in system ticks, the special values are - * handled as follow: - * - @a TIME_INFINITE is allowed but interpreted as a - * normal time specification. - * - @a TIME_IMMEDIATE this value is not allowed. - * . - * - * @api - */ -static inline void osalThreadSleep(systime_t time) { - - chThdSleep(time); -} - -/** - * @brief Sends the current thread sleeping and sets a reference variable. - * @note This function must reschedule, it can only be called from thread - * context. - * - * @param[in] trp a pointer to a thread reference object - * @return The wake up message. - * - * @sclass - */ -static inline msg_t osalThreadSuspendS(thread_reference_t *trp) { - - return chThdSuspendTimeoutS(trp, TIME_INFINITE); -} - -/** - * @brief Sends the current thread sleeping and sets a reference variable. - * @note This function must reschedule, it can only be called from thread - * context. - * - * @param[in] trp a pointer to a thread reference object - * @param[in] timeout the timeout in system ticks, the special values are - * handled as follow: - * - @a TIME_INFINITE the thread enters an infinite sleep - * state. - * - @a TIME_IMMEDIATE the thread is not enqueued and - * the function returns @p MSG_TIMEOUT as if a timeout - * occurred. - * . - * @return The wake up message. - * @retval MSG_TIMEOUT if the operation timed out. - * - * @sclass - */ -static inline msg_t osalThreadSuspendTimeoutS(thread_reference_t *trp, - systime_t timeout) { - - return chThdSuspendTimeoutS(trp, timeout); -} - -/** - * @brief Wakes up a thread waiting on a thread reference object. - * @note This function must not reschedule because it can be called from - * ISR context. - * - * @param[in] trp a pointer to a thread reference object - * @param[in] msg the message code - * - * @iclass - */ -static inline void osalThreadResumeI(thread_reference_t *trp, msg_t msg) { - - chThdResumeI(trp, msg); -} - -/** - * @brief Wakes up a thread waiting on a thread reference object. - * @note This function must reschedule, it can only be called from thread - * context. - * - * @param[in] trp a pointer to a thread reference object - * @param[in] msg the message code - * - * @iclass - */ -static inline void osalThreadResumeS(thread_reference_t *trp, msg_t msg) { - - chThdResumeI(trp, msg); - chSchRescheduleS(); -} - -/** - * @brief Initializes a threads queue object. - * - * @param[out] tqp pointer to the threads queue object - * - * @init - */ -static inline void osalThreadQueueObjectInit(threads_queue_t *tqp) { - - chSemObjectInit(&tqp->sem, (cnt_t)0); -} - -/** - * @brief Enqueues the caller thread. - * @details The caller thread is enqueued and put to sleep until it is - * dequeued or the specified timeouts expires. - * - * @param[in] tqp pointer to the threads queue object - * @param[in] time the timeout in system ticks, the special values are - * handled as follow: - * - @a TIME_INFINITE the thread enters an infinite sleep - * state. - * - @a TIME_IMMEDIATE the thread is not enqueued and - * the function returns @p MSG_TIMEOUT as if a timeout - * occurred. - * . - * @return The message from @p osalQueueWakeupOneI() or - * @p osalQueueWakeupAllI() functions. - * @retval MSG_TIMEOUT if the thread has not been dequeued within the - * specified timeout or if the function has been - * invoked with @p TIME_IMMEDIATE as timeout - * specification. - * - * @sclass - */ -static inline msg_t osalThreadEnqueueTimeoutS(threads_queue_t *tqp, - systime_t time) { - - return chSemWaitTimeoutS(&tqp->sem, time); -} - -/** - * @brief Initializes an event flags object. - * - * @param[out] esp pointer to the event flags object - * - * @init - */ -static inline void osalEventObjectInit(event_source_t *esp) { - - osalDbgCheck(esp != NULL); - - esp->flags = 0; - esp->cb = NULL; - esp->param = NULL; -} - -/** - * @brief Add flags to an event source object. - * - * @param[in] esp pointer to the event flags object - * @param[in] flags flags to be ORed to the flags mask - * - * @iclass - */ -static inline void osalEventBroadcastFlagsI(event_source_t *esp, - eventflags_t flags) { - - osalDbgCheck(esp != NULL); - - esp->flags |= flags; - if (esp->cb != NULL) { - esp->cb(esp); - } -} - -/** - * @brief Add flags to an event source object. - * - * @param[in] esp pointer to the event flags object - * @param[in] flags flags to be ORed to the flags mask - * - * @iclass - */ -static inline void osalEventBroadcastFlags(event_source_t *esp, - eventflags_t flags) { - - osalDbgCheck(esp != NULL); - - chSysLock(); - osalEventBroadcastFlagsI(esp, flags); - chSchRescheduleS(); - chSysUnlock(); -} - -/** - * @brief Event callback setup. - * @note The callback is invoked from ISR context and can - * only invoke I-Class functions. The callback is meant - * to wakeup the task that will handle the event by - * calling @p osalEventGetAndClearFlagsI(). - * - * @param[in] esp pointer to the event flags object - * @param[in] cb pointer to the callback function - * @param[in] param parameter to be passed to the callback function - * - * @api - */ -static inline void osalEventSetCallback(event_source_t *esp, - eventcallback_t cb, - void *param) { - - osalDbgCheck(esp != NULL); - - esp->cb = cb; - esp->param = param; -} - -/** - * @brief Initializes s @p mutex_t object. - * - * @param[out] mp pointer to the @p mutex_t object - * - * @init - */ -static inline void osalMutexObjectInit(mutex_t *mp) { - - chSemObjectInit((semaphore_t *)mp, (cnt_t)1); -} - -/** - * @brief Locks the specified mutex. - * @post The mutex is locked and inserted in the per-thread stack of owned - * mutexes. - * - * @param[in,out] mp pointer to the @p mutex_t object - * - * @api - */ -static inline void osalMutexLock(mutex_t *mp) { - - (void) chSemWait((semaphore_t *)mp); -} - -/** - * @brief Unlocks the specified mutex. - * @note The HAL guarantees to release mutex in reverse lock order. The - * mutex being unlocked is guaranteed to be the last locked mutex - * by the invoking thread. - * The implementation can rely on this behavior and eventually - * ignore the @p mp parameter which is supplied in order to support - * those OSes not supporting a stack of the owned mutexes. - * - * @param[in,out] mp pointer to the @p mutex_t object - * - * @api - */ -static inline void osalMutexUnlock(mutex_t *mp) { - - chSemSignal((semaphore_t *)mp); -} - -#endif /* _OSAL_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/osal/nil/osal.mk b/firmware/ChibiOS_16/os/hal/osal/nil/osal.mk deleted file mode 100644 index d104bd6945..0000000000 --- a/firmware/ChibiOS_16/os/hal/osal/nil/osal.mk +++ /dev/null @@ -1,5 +0,0 @@ -# OSAL files. -OSALSRC += ${CHIBIOS}/os/hal/osal/nil/osal.c - -# Required include directories -OSALINC += ${CHIBIOS}/os/hal/osal/nil diff --git a/firmware/ChibiOS_16/os/hal/osal/os-less/ARMCMx/osal.c b/firmware/ChibiOS_16/os/hal/osal/os-less/ARMCMx/osal.c deleted file mode 100644 index 59ccd3c0b2..0000000000 --- a/firmware/ChibiOS_16/os/hal/osal/os-less/ARMCMx/osal.c +++ /dev/null @@ -1,580 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file osal.c - * @brief OSAL module code. - * - * @addtogroup OSAL - * @{ - */ - -#include "osal.h" - -/*===========================================================================*/ -/* Module local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -/** - * @brief Pointer to a halt error message. - * @note The message is meant to be retrieved by the debugger after the - * system halt caused by an unexpected error. - */ -const char *osal_halt_msg; - -/** - * @brief Virtual timers delta list header. - */ -virtual_timers_list_t vtlist; - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -/** - * @brief Timers initialization. - * - * @notapi - */ -static void vtInit(void) { - - /* Virtual Timers initialization.*/ - vtlist.vt_next = vtlist.vt_prev = (void *)&vtlist; - vtlist.vt_time = (systime_t)-1; - vtlist.vt_systime = 0; -} - -/** - * @brief Returns @p TRUE if the specified timer is armed. - * - * @param[out] vtp the @p virtual_timer_t structure pointer - * - * @notapi - */ -static bool vtIsArmedI(virtual_timer_t *vtp) { - - return vtp->vt_func != NULL; -} - -/** - * @brief Virtual timers ticker. - * @note The system lock is released before entering the callback and - * re-acquired immediately after. It is callback's responsibility - * to acquire the lock if needed. This is done in order to reduce - * interrupts jitter when many timers are in use. - * - * @notapi - */ -static void vtDoTickI(void) { - - vtlist.vt_systime++; - if (&vtlist != (virtual_timers_list_t *)vtlist.vt_next) { - virtual_timer_t *vtp; - - --vtlist.vt_next->vt_time; - while (!(vtp = vtlist.vt_next)->vt_time) { - vtfunc_t fn = vtp->vt_func; - vtp->vt_func = (vtfunc_t)NULL; - vtp->vt_next->vt_prev = (void *)&vtlist; - (&vtlist)->vt_next = vtp->vt_next; - osalSysUnlockFromISR(); - fn(vtp->vt_par); - osalSysLockFromISR(); - } - } -} - -/** - * @brief Enables a virtual timer. - * @note The associated function is invoked from interrupt context. - * - * @param[out] vtp the @p virtual_timer_t structure pointer - * @param[in] time the number of ticks before the operation timeouts, the - * special values are handled as follow: - * - @a TIME_INFINITE is allowed but interpreted as a - * normal time specification. - * - @a TIME_IMMEDIATE this value is not allowed. - * . - * @param[in] vtfunc the timer callback function. After invoking the - * callback the timer is disabled and the structure can - * be disposed or reused. - * @param[in] par a parameter that will be passed to the callback - * function - * - * @notapi - */ -static void vtSetI(virtual_timer_t *vtp, systime_t time, - vtfunc_t vtfunc, void *par) { - virtual_timer_t *p; - - vtp->vt_par = par; - vtp->vt_func = vtfunc; - p = vtlist.vt_next; - while (p->vt_time < time) { - time -= p->vt_time; - p = p->vt_next; - } - - vtp->vt_prev = (vtp->vt_next = p)->vt_prev; - vtp->vt_prev->vt_next = p->vt_prev = vtp; - vtp->vt_time = time; - if (p != (void *)&vtlist) - p->vt_time -= time; -} - -/** - * @brief Disables a Virtual Timer. - * @note The timer MUST be active when this function is invoked. - * - * @param[in] vtp the @p virtual_timer_t structure pointer - * - * @notapi - */ -static void vtResetI(virtual_timer_t *vtp) { - - if (vtp->vt_next != (void *)&vtlist) - vtp->vt_next->vt_time += vtp->vt_time; - vtp->vt_prev->vt_next = vtp->vt_next; - vtp->vt_next->vt_prev = vtp->vt_prev; - vtp->vt_func = (vtfunc_t)NULL; -} - - -static void callback_timeout(void *p) { - osalSysLockFromISR(); - osalThreadResumeI((thread_reference_t *)p, MSG_TIMEOUT); - osalSysUnlockFromISR(); -} - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -/** - * @brief OSAL module initialization. - * - * @api - */ -void osalInit(void) { - - vtInit(); - - OSAL_INIT_HOOK(); -} - -/** - * @brief System halt with error message. - * - * @param[in] reason the halt message pointer - * - * @api - */ -#if !defined(__DOXYGEN__) -__attribute__((weak, noreturn)) -#endif -void osalSysHalt(const char *reason) { - - osalSysDisable(); - osal_halt_msg = reason; - while (true) { - } -} - -/** - * @brief Polled delay. - * @note The real delay is always few cycles in excess of the specified - * value. - * - * @param[in] cycles number of cycles - * - * @xclass - */ -void osalSysPolledDelayX(rtcnt_t cycles) { - - (void)cycles; -} - -/** - * @brief System timer handler. - * @details The handler is used for scheduling and Virtual Timers management. - * - * @iclass - */ -void osalOsTimerHandlerI(void) { - - osalDbgCheckClassI(); - - vtDoTickI(); -} - -/** - * @brief Checks if a reschedule is required and performs it. - * @note I-Class functions invoked from thread context must not reschedule - * by themselves, an explicit reschedule using this function is - * required in this scenario. - * @note Not implemented in this simplified OSAL. - * - * @sclass - */ -void osalOsRescheduleS(void) { - -} - -/** - * @brief Current system time. - * @details Returns the number of system ticks since the @p osalInit() - * invocation. - * @note The counter can reach its maximum and then restart from zero. - * @note This function can be called from any context but its atomicity - * is not guaranteed on architectures whose word size is less than - * @p systime_t size. - * - * @return The system time in ticks. - * - * @xclass - */ -systime_t osalOsGetSystemTimeX(void) { - - return vtlist.vt_systime; -} - -/** - * @brief Suspends the invoking thread for the specified time. - * - * @param[in] time the delay in system ticks, the special values are - * handled as follow: - * - @a TIME_INFINITE is allowed but interpreted as a - * normal time specification. - * - @a TIME_IMMEDIATE this value is not allowed. - * . - * - * @sclass - */ -void osalThreadSleepS(systime_t time) { - virtual_timer_t vt; - thread_reference_t tr; - - tr = NULL; - vtSetI(&vt, time, callback_timeout, (void *)&tr); - osalThreadSuspendS(&tr); -} - -/** - * @brief Suspends the invoking thread for the specified time. - * - * @param[in] time the delay in system ticks, the special values are - * handled as follow: - * - @a TIME_INFINITE is allowed but interpreted as a - * normal time specification. - * - @a TIME_IMMEDIATE this value is not allowed. - * . - * - * @api - */ -void osalThreadSleep(systime_t time) { - - osalSysLock(); - osalThreadSleepS(time); - osalSysUnlock(); -} - -/** - * @brief Sends the current thread sleeping and sets a reference variable. - * @note This function must reschedule, it can only be called from thread - * context. - * - * @param[in] trp a pointer to a thread reference object - * @return The wake up message. - * - * @sclass - */ -msg_t osalThreadSuspendS(thread_reference_t *trp) { - thread_t self = {MSG_WAIT}; - - osalDbgCheck(trp != NULL); - - *trp = &self; - while (self.message == MSG_WAIT) { - osalSysUnlock(); - /* A state-changing interrupt could occur here and cause the loop to - terminate, an hook macro is executed while waiting.*/ - OSAL_IDLE_HOOK(); - osalSysLock(); - } - - return self.message; -} - -/** - * @brief Sends the current thread sleeping and sets a reference variable. - * @note This function must reschedule, it can only be called from thread - * context. - * - * @param[in] trp a pointer to a thread reference object - * @param[in] timeout the timeout in system ticks, the special values are - * handled as follow: - * - @a TIME_INFINITE the thread enters an infinite sleep - * state. - * - @a TIME_IMMEDIATE the thread is not enqueued and - * the function returns @p MSG_TIMEOUT as if a timeout - * occurred. - * . - * @return The wake up message. - * @retval MSG_TIMEOUT if the operation timed out. - * - * @sclass - */ -msg_t osalThreadSuspendTimeoutS(thread_reference_t *trp, systime_t timeout) { - msg_t msg; - virtual_timer_t vt; - - osalDbgCheck(trp != NULL); - - if (TIME_INFINITE == timeout) - return osalThreadSuspendS(trp); - - vtSetI(&vt, timeout, callback_timeout, (void *)trp); - msg = osalThreadSuspendS(trp); - if (vtIsArmedI(&vt)) - vtResetI(&vt); - - return msg; -} - -/** - * @brief Wakes up a thread waiting on a thread reference object. - * @note This function must not reschedule because it can be called from - * ISR context. - * - * @param[in] trp a pointer to a thread reference object - * @param[in] msg the message code - * - * @iclass - */ -void osalThreadResumeI(thread_reference_t *trp, msg_t msg) { - - osalDbgCheck(trp != NULL); - - if (*trp != NULL) { - (*trp)->message = msg; - *trp = NULL; - } -} - -/** - * @brief Wakes up a thread waiting on a thread reference object. - * @note This function must reschedule, it can only be called from thread - * context. - * - * @param[in] trp a pointer to a thread reference object - * @param[in] msg the message code - * - * @iclass - */ -void osalThreadResumeS(thread_reference_t *trp, msg_t msg) { - - osalDbgCheck(trp != NULL); - - if (*trp != NULL) { - (*trp)->message = msg; - *trp = NULL; - } -} - -/** - * @brief Enqueues the caller thread. - * @details The caller thread is enqueued and put to sleep until it is - * dequeued or the specified timeouts expires. - * - * @param[in] tqp pointer to the threads queue object - * @param[in] timeout the timeout in system ticks, the special values are - * handled as follow: - * - @a TIME_INFINITE the thread enters an infinite sleep - * state. - * - @a TIME_IMMEDIATE the thread is not enqueued and - * the function returns @p MSG_TIMEOUT as if a timeout - * occurred. - * . - * @return The message from @p osalQueueWakeupOneI() or - * @p osalQueueWakeupAllI() functions. - * @retval MSG_TIMEOUT if the thread has not been dequeued within the - * specified timeout or if the function has been - * invoked with @p TIME_IMMEDIATE as timeout - * specification. - * - * @sclass - */ -msg_t osalThreadEnqueueTimeoutS(threads_queue_t *tqp, systime_t timeout) { - msg_t msg; - virtual_timer_t vt; - - osalDbgCheck(tqp != NULL); - - if (TIME_IMMEDIATE == timeout) - return MSG_TIMEOUT; - - tqp->tr = NULL; - - if (TIME_INFINITE == timeout) - return osalThreadSuspendS(&tqp->tr); - - vtSetI(&vt, timeout, callback_timeout, (void *)&tqp->tr); - msg = osalThreadSuspendS(&tqp->tr); - if (vtIsArmedI(&vt)) - vtResetI(&vt); - - return msg; -} - -/** - * @brief Dequeues and wakes up one thread from the queue, if any. - * - * @param[in] tqp pointer to the threads queue object - * @param[in] msg the message code - * - * @iclass - */ -void osalThreadDequeueNextI(threads_queue_t *tqp, msg_t msg) { - - osalDbgCheck(tqp != NULL); - - osalThreadResumeI(&tqp->tr, msg); -} - -/** - * @brief Dequeues and wakes up all threads from the queue. - * - * @param[in] tqp pointer to the threads queue object - * @param[in] msg the message code - * - * @iclass - */ -void osalThreadDequeueAllI(threads_queue_t *tqp, msg_t msg) { - - osalDbgCheck(tqp != NULL); - - osalThreadResumeI(&tqp->tr, msg); -} - -/** - * @brief Add flags to an event source object. - * - * @param[in] esp pointer to the event flags object - * @param[in] flags flags to be ORed to the flags mask - * - * @iclass - */ -void osalEventBroadcastFlagsI(event_source_t *esp, eventflags_t flags) { - - osalDbgCheck(esp != NULL); - - esp->flags |= flags; - if (esp->cb != NULL) { - esp->cb(esp); - } -} - -/** - * @brief Add flags to an event source object. - * - * @param[in] esp pointer to the event flags object - * @param[in] flags flags to be ORed to the flags mask - * - * @iclass - */ -void osalEventBroadcastFlags(event_source_t *esp, eventflags_t flags) { - - osalDbgCheck(esp != NULL); - - osalSysLock(); - osalEventBroadcastFlagsI(esp, flags); - osalSysUnlock(); -} - -/** - * @brief Event callback setup. - * @note The callback is invoked from ISR context and can - * only invoke I-Class functions. The callback is meant - * to wakeup the task that will handle the event by - * calling @p osalEventGetAndClearFlagsI(). - * @note This function is not part of the OSAL API and is provided - * exclusively as an example and for convenience. - * - * @param[in] esp pointer to the event flags object - * @param[in] cb pointer to the callback function - * @param[in] param parameter to be passed to the callback function - * - * @api - */ -void osalEventSetCallback(event_source_t *esp, - eventcallback_t cb, - void *param) { - - osalDbgCheck(esp != NULL); - - esp->cb = cb; - esp->param = param; -} - -/** - * @brief Locks the specified mutex. - * @post The mutex is locked and inserted in the per-thread stack of owned - * mutexes. - * - * @param[in,out] mp pointer to the @p mutex_t object - * - * @api - */ -void osalMutexLock(mutex_t *mp) { - - osalDbgCheck(mp != NULL); - - *mp = 1; -} - -/** - * @brief Unlocks the specified mutex. - * @note The HAL guarantees to release mutex in reverse lock order. The - * mutex being unlocked is guaranteed to be the last locked mutex - * by the invoking thread. - * The implementation can rely on this behavior and eventually - * ignore the @p mp parameter which is supplied in order to support - * those OSes not supporting a stack of the owned mutexes. - * - * @param[in,out] mp pointer to the @p mutex_t object - * - * @api - */ -void osalMutexUnlock(mutex_t *mp) { - - osalDbgCheck(mp != NULL); - - *mp = 0; -} - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/osal/os-less/ARMCMx/osal.h b/firmware/ChibiOS_16/os/hal/osal/os-less/ARMCMx/osal.h deleted file mode 100644 index e09395dc45..0000000000 --- a/firmware/ChibiOS_16/os/hal/osal/os-less/ARMCMx/osal.h +++ /dev/null @@ -1,769 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file osal.h - * @brief OSAL module header. - * - * @addtogroup OSAL - * @{ - */ - -#ifndef _OSAL_H_ -#define _OSAL_H_ - -#include -#include -#include - -#include "cmparams.h" - -#include "osalconf.h" - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @name Common constants - * @{ - */ -#if !defined(FALSE) || defined(__DOXYGEN__) -#define FALSE 0 -#endif - -#if !defined(TRUE) || defined(__DOXYGEN__) -#define TRUE 1 -#endif - -#define OSAL_SUCCESS false -#define OSAL_FAILED true -/** @} */ - -/** - * @name Messages - * @{ - */ -#define MSG_OK (msg_t)0 -#define MSG_RESET (msg_t)-1 -#define MSG_TIMEOUT (msg_t)-2 -#define MSG_WAIT (msg_t)-10 -/** @} */ - - -/** - * @name Special time constants - * @{ - */ -#define TIME_IMMEDIATE ((systime_t)0) -#define TIME_INFINITE ((systime_t)-1) -/** @} */ - -/** - * @name Systick modes. - * @{ - */ -#define OSAL_ST_MODE_NONE 0 -#define OSAL_ST_MODE_PERIODIC 1 -#define OSAL_ST_MODE_FREERUNNING 2 -/** @} */ - -/** - * @name Systick parameters. - * @{ - */ -/** - * @brief Size in bits of the @p systick_t type. - */ -#define OSAL_ST_RESOLUTION 32 - -/** - * @brief Systick mode required by the underlying OS. - */ -#define OSAL_ST_MODE OSAL_ST_MODE_PERIODIC -/** @} */ - -/** - * @name IRQ-related constants - * @{ - */ -/** - * @brief Total priority levels. - */ -#define OSAL_IRQ_PRIORITY_LEVELS (1U << CORTEX_PRIORITY_BITS) - -/** - * @brief Highest IRQ priority for HAL drivers. - */ -#if (CORTEX_MODEL == 0) || defined(__DOXYGEN__) -#define OSAL_IRQ_MAXIMUM_PRIORITY 0 -#else -#define OSAL_IRQ_MAXIMUM_PRIORITY 1 -#endif -/** @} */ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Frequency in Hertz of the system tick. - */ -#if !defined(OSAL_ST_FREQUENCY) || defined(__DOXYGEN__) -#define OSAL_ST_FREQUENCY 1000 -#endif - -/** - * @brief Enables OSAL assertions. - */ -#if !defined(OSAL_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define OSAL_DBG_ENABLE_ASSERTS FALSE -#endif - -/** - * @brief Enables OSAL functions parameters checks. - */ -#if !defined(OSAL_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define OSAL_DBG_ENABLE_CHECKS FALSE -#endif - -/** - * @brief OSAL initialization hook. - */ -#if !defined(OSAL_INIT_HOOK) || defined(__DOXYGEN__) -#define OSAL_INIT_HOOK() -#endif - -/** - * @brief Idle loop hook macro. - */ -#if !defined(OSAL_IDLE_HOOK) || defined(__DOXYGEN__) -#define OSAL_IDLE_HOOK() -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a system status word. - */ -typedef uint32_t syssts_t; - -/** - * @brief Type of a message. - */ -typedef int32_t msg_t; - -/** - * @brief Type of system time counter. - */ -typedef uint32_t systime_t; - -/** - * @brief Type of a Virtual Timer callback function. - */ -typedef void (*vtfunc_t)(void *); - -/** - * @brief Type of a Virtual Timer structure. - */ -typedef struct virtual_timer virtual_timer_t; - -/** - * @brief Virtual timers list header. - * @note The content of this structure is not part of the API and should - * not be relied upon. Implementers may define this structure in - * an entirely different way. - * @note The delta list is implemented as a double link bidirectional list - * in order to make the unlink time constant, the reset of a virtual - * timer is often used in the code. - */ -typedef struct { - virtual_timer_t *vt_next; /**< @brief Next timer in the timers - list. */ - virtual_timer_t *vt_prev; /**< @brief Last timer in the timers - list. */ - systime_t vt_time; /**< @brief Must be initialized to -1. */ - volatile systime_t vt_systime; /**< @brief System Time counter. */ -} virtual_timers_list_t; - -/** - * @extends virtual_timers_list_t - * - * @brief Virtual Timer descriptor structure. - * @note The content of this structure is not part of the API and should - * not be relied upon. Implementers may define this structure in - * an entirely different way. - */ -struct virtual_timer { - virtual_timer_t *vt_next; /**< @brief Next timer in the timers - list. */ - virtual_timer_t *vt_prev; /**< @brief Previous timer in the timers - list. */ - systime_t vt_time; /**< @brief Time delta before timeout. */ - vtfunc_t vt_func; /**< @brief Timer callback function - pointer. */ - void *vt_par; /**< @brief Timer callback function - parameter. */ -}; - -/** - * @brief Type of realtime counter. - */ -typedef uint32_t rtcnt_t; - -/** - * @brief Type of a thread. - * @note The content of this structure is not part of the API and should - * not be relied upon. Implementers may define this structure in - * an entirely different way. - */ -typedef struct { - volatile msg_t message; -} thread_t; - -/** - * @brief Type of a thread reference. - */ -typedef thread_t * thread_reference_t; - -/** - * @brief Type of an event flags object. - * @note The content of this structure is not part of the API and should - * not be relied upon. Implementers may define this structure in - * an entirely different way. - * @note Retrieval and clearing of the flags are not defined in this - * API and are implementation-dependent. - */ -typedef struct event_source event_source_t; - -/** - * @brief Type of an event source callback. - * @note This type is not part of the OSAL API and is provided - * exclusively as an example and for convenience. - */ -typedef void (*eventcallback_t)(event_source_t *esp); - -/** - * @brief Type of an event flags mask. - */ -typedef uint32_t eventflags_t; - -/** - * @brief Events source object. - * @note The content of this structure is not part of the API and should - * not be relied upon. Implementers may define this structure in - * an entirely different way. - * @note Retrieval and clearing of the flags are not defined in this - * API and are implementation-dependent. - */ -struct event_source { - volatile eventflags_t flags; /**< @brief Stored event flags. */ - eventcallback_t cb; /**< @brief Event source callback. */ - void *param; /**< @brief User defined field. */ -}; - -/** - * @brief Type of a mutex. - * @note If the OS does not support mutexes or there is no OS then them - * mechanism can be simulated. - */ -typedef uint32_t mutex_t; - -/** - * @brief Type of a thread queue. - * @details A thread queue is a queue of sleeping threads, queued threads - * can be dequeued one at time or all together. - * @note If the OSAL is implemented on a bare metal machine without RTOS - * then the queue can be implemented as a single thread reference. - */ -typedef struct { - thread_reference_t tr; -} threads_queue_t; - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @name Debug related macros - * @{ - */ -/** - * @brief Condition assertion. - * @details If the condition check fails then the OSAL panics with a - * message and halts. - * @note The condition is tested only if the @p OSAL_ENABLE_ASSERTIONS - * switch is enabled. - * @note The remark string is not currently used except for putting a - * comment in the code about the assertion. - * - * @param[in] c the condition to be verified to be true - * @param[in] remark a remark string - * - * @api - */ -#define osalDbgAssert(c, remark) do { \ - /*lint -save -e506 -e774 [2.1, 14.3] Can be a constant by design.*/ \ - if (OSAL_DBG_ENABLE_ASSERTS != FALSE) { \ - if (!(c)) { \ - /*lint -restore*/ \ - osalSysHalt(__func__); \ - } \ - } \ -} while (false) - - -/** - * @brief Function parameters check. - * @details If the condition check fails then the OSAL panics and halts. - * @note The condition is tested only if the @p OSAL_ENABLE_CHECKS switch - * is enabled. - * - * @param[in] c the condition to be verified to be true - * - * @api - */ -#define osalDbgCheck(c) do { \ - /*lint -save -e506 -e774 [2.1, 14.3] Can be a constant by design.*/ \ - if (OSAL_DBG_ENABLE_CHECKS != FALSE) { \ - if (!(c)) { \ - /*lint -restore*/ \ - osalSysHalt(__func__); \ - } \ - } \ -} while (false) - - -/** - * @brief I-Class state check. - * @note Implementation is optional. - */ -#define osalDbgCheckClassI() - -/** - * @brief S-Class state check. - * @note Implementation is optional. - */ -#define osalDbgCheckClassS() -/** @} */ - -/** - * @name IRQ service routines wrappers - * @{ - */ -/** - * @brief Priority level verification macro. - */ -#define OSAL_IRQ_IS_VALID_PRIORITY(n) \ - (((n) >= OSAL_IRQ_MAXIMUM_PRIORITY) && ((n) < OSAL_IRQ_PRIORITY_LEVELS)) - -/** - * @brief IRQ prologue code. - * @details This macro must be inserted at the start of all IRQ handlers. - */ -#define OSAL_IRQ_PROLOGUE() - -/** - * @brief IRQ epilogue code. - * @details This macro must be inserted at the end of all IRQ handlers. - */ -#define OSAL_IRQ_EPILOGUE() - -/** - * @brief IRQ handler function declaration. - * @details This macro hides the details of an ISR function declaration. - * - * @param[in] id a vector name as defined in @p vectors.s - */ -#define OSAL_IRQ_HANDLER(id) void id(void) -/** @} */ - -/** - * @name Time conversion utilities - * @{ - */ -/** - * @brief Seconds to system ticks. - * @details Converts from seconds to system ticks number. - * @note The result is rounded upward to the next tick boundary. - * - * @param[in] sec number of seconds - * @return The number of ticks. - * - * @api - */ -#define OSAL_S2ST(sec) \ - ((systime_t)((uint32_t)(sec) * (uint32_t)OSAL_ST_FREQUENCY)) - -/** - * @brief Milliseconds to system ticks. - * @details Converts from milliseconds to system ticks number. - * @note The result is rounded upward to the next tick boundary. - * - * @param[in] msec number of milliseconds - * @return The number of ticks. - * - * @api - */ -#define OSAL_MS2ST(msec) \ - ((systime_t)((((uint32_t)(msec)) * \ - ((uint32_t)OSAL_ST_FREQUENCY) + 999UL) / 1000UL)) - -/** - * @brief Microseconds to system ticks. - * @details Converts from microseconds to system ticks number. - * @note The result is rounded upward to the next tick boundary. - * - * @param[in] usec number of microseconds - * @return The number of ticks. - * - * @api - */ -#define OSAL_US2ST(usec) \ - ((systime_t)((((uint32_t)(usec)) * \ - ((uint32_t)OSAL_ST_FREQUENCY) + 999999UL) / 1000000UL)) -/** @} */ - -/** - * @name Time conversion utilities for the realtime counter - * @{ - */ -/** - * @brief Seconds to realtime counter. - * @details Converts from seconds to realtime counter cycles. - * @note The macro assumes that @p freq >= @p 1. - * - * @param[in] freq clock frequency, in Hz, of the realtime counter - * @param[in] sec number of seconds - * @return The number of cycles. - * - * @api - */ -#define OSAL_S2RTC(freq, sec) ((freq) * (sec)) - -/** - * @brief Milliseconds to realtime counter. - * @details Converts from milliseconds to realtime counter cycles. - * @note The result is rounded upward to the next millisecond boundary. - * @note The macro assumes that @p freq >= @p 1000. - * - * @param[in] freq clock frequency, in Hz, of the realtime counter - * @param[in] msec number of milliseconds - * @return The number of cycles. - * - * @api - */ -#define OSAL_MS2RTC(freq, msec) (rtcnt_t)((((freq) + 999UL) / 1000UL) * (msec)) - -/** - * @brief Microseconds to realtime counter. - * @details Converts from microseconds to realtime counter cycles. - * @note The result is rounded upward to the next microsecond boundary. - * @note The macro assumes that @p freq >= @p 1000000. - * - * @param[in] freq clock frequency, in Hz, of the realtime counter - * @param[in] usec number of microseconds - * @return The number of cycles. - * - * @api - */ -#define OSAL_US2RTC(freq, usec) (rtcnt_t)((((freq) + 999999UL) / 1000000UL) * (usec)) -/** @} */ - -/** - * @name Sleep macros using absolute time - * @{ - */ -/** - * @brief Delays the invoking thread for the specified number of seconds. - * @note The specified time is rounded up to a value allowed by the real - * system tick clock. - * @note The maximum specifiable value is implementation dependent. - * - * @param[in] sec time in seconds, must be different from zero - * - * @api - */ -#define osalThreadSleepSeconds(sec) osalThreadSleep(OSAL_S2ST(sec)) - -/** - * @brief Delays the invoking thread for the specified number of - * milliseconds. - * @note The specified time is rounded up to a value allowed by the real - * system tick clock. - * @note The maximum specifiable value is implementation dependent. - * - * @param[in] msec time in milliseconds, must be different from zero - * - * @api - */ -#define osalThreadSleepMilliseconds(msec) osalThreadSleep(OSAL_MS2ST(msec)) - -/** - * @brief Delays the invoking thread for the specified number of - * microseconds. - * @note The specified time is rounded up to a value allowed by the real - * system tick clock. - * @note The maximum specifiable value is implementation dependent. - * - * @param[in] usec time in microseconds, must be different from zero - * - * @api - */ -#define osalThreadSleepMicroseconds(usec) osalThreadSleep(OSAL_US2ST(usec)) -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -extern const char *osal_halt_msg; - -#ifdef __cplusplus -extern "C" { -#endif - void osalInit(void); - void osalSysHalt(const char *reason); - void osalSysPolledDelayX(rtcnt_t cycles); - void osalOsTimerHandlerI(void); - void osalOsRescheduleS(void); - systime_t osalOsGetSystemTimeX(void); - void osalThreadSleepS(systime_t time); - void osalThreadSleep(systime_t time); - msg_t osalThreadSuspendS(thread_reference_t *trp); - msg_t osalThreadSuspendTimeoutS(thread_reference_t *trp, systime_t timeout); - void osalThreadResumeI(thread_reference_t *trp, msg_t msg); - void osalThreadResumeS(thread_reference_t *trp, msg_t msg); - msg_t osalThreadEnqueueTimeoutS(threads_queue_t *tqp, systime_t timeout); - void osalThreadDequeueNextI(threads_queue_t *tqp, msg_t msg); - void osalThreadDequeueAllI(threads_queue_t *tqp, msg_t msg); - void osalEventBroadcastFlagsI(event_source_t *esp, eventflags_t flags); - void osalEventBroadcastFlags(event_source_t *esp, eventflags_t flags); - void osalEventSetCallback(event_source_t *esp, - eventcallback_t cb, - void *param); - void osalMutexLock(mutex_t *mp); - void osalMutexUnlock(mutex_t *mp); -#ifdef __cplusplus -} -#endif - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -/** - * @brief Disables interrupts globally. - * - * @special - */ -static inline void osalSysDisable(void) { - - __disable_irq(); -} - -/** - * @brief Enables interrupts globally. - * - * @special - */ -static inline void osalSysEnable(void) { - - __enable_irq(); -} - -/** - * @brief Enters a critical zone from thread context. - * @note This function cannot be used for reentrant critical zones. - * - * @special - */ -static inline void osalSysLock(void) { - -#if CORTEX_MODEL == 0 - __disable_irq(); -#else - __set_BASEPRI(OSAL_IRQ_MAXIMUM_PRIORITY); -#endif -} - -/** - * @brief Leaves a critical zone from thread context. - * @note This function cannot be used for reentrant critical zones. - * - * @special - */ -static inline void osalSysUnlock(void) { - -#if CORTEX_MODEL == 0 - __enable_irq(); -#else - __set_BASEPRI(0); -#endif -} - -/** - * @brief Enters a critical zone from ISR context. - * @note This function cannot be used for reentrant critical zones. - * - * @special - */ -static inline void osalSysLockFromISR(void) { - -#if CORTEX_MODEL == 0 - __disable_irq(); -#else - __set_BASEPRI(OSAL_IRQ_MAXIMUM_PRIORITY); -#endif -} - -/** - * @brief Leaves a critical zone from ISR context. - * @note This function cannot be used for reentrant critical zones. - * - * @special - */ -static inline void osalSysUnlockFromISR(void) { - -#if CORTEX_MODEL == 0 - __enable_irq(); -#else - __set_BASEPRI(0); -#endif -} - -/** - * @brief Returns the execution status and enters a critical zone. - * @details This functions enters into a critical zone and can be called - * from any context. Because its flexibility it is less efficient - * than @p chSysLock() which is preferable when the calling context - * is known. - * @post The system is in a critical zone. - * - * @return The previous system status, the encoding of this - * status word is architecture-dependent and opaque. - * - * @xclass - */ -static inline syssts_t osalSysGetStatusAndLockX(void) { - syssts_t sts; - -#if CORTEX_MODEL == 0 - sts = (syssts_t)__get_PRIMASK(); - __disable_irq(); -#else - sts = (syssts_t)__get_BASEPRI(); - __set_BASEPRI(OSAL_IRQ_MAXIMUM_PRIORITY); -#endif - return sts; -} - -/** - * @brief Restores the specified execution status and leaves a critical zone. - * @note A call to @p chSchRescheduleS() is automatically performed - * if exiting the critical zone and if not in ISR context. - * - * @param[in] sts the system status to be restored. - * - * @xclass - */ -static inline void osalSysRestoreStatusX(syssts_t sts) { - -#if CORTEX_MODEL == 0 - if ((sts & (syssts_t)1) == (syssts_t)0) { - __enable_irq(); - } -#else - if (sts == (syssts_t)0) { - __set_BASEPRI(0); - } -#endif -} - -/** - * @brief Checks if the specified time is within the specified time window. - * @note When start==end then the function returns always true because the - * whole time range is specified. - * @note This function can be called from any context. - * - * @param[in] time the time to be verified - * @param[in] start the start of the time window (inclusive) - * @param[in] end the end of the time window (non inclusive) - * @retval true current time within the specified time window. - * @retval false current time not within the specified time window. - * - * @xclass - */ -static inline bool osalOsIsTimeWithinX(systime_t time, - systime_t start, - systime_t end) { - - return (bool)((time - start) < (end - start)); -} - -/** - * @brief Initializes a threads queue object. - * - * @param[out] tqp pointer to the threads queue object - * - * @init - */ -static inline void osalThreadQueueObjectInit(threads_queue_t *tqp) { - - osalDbgCheck(tqp != NULL); - - (void)tqp; -} - -/** - * @brief Initializes an event flags object. - * - * @param[out] esp pointer to the event flags object - * - * @init - */ -static inline void osalEventObjectInit(event_source_t *esp) { - - osalDbgCheck(esp != NULL); - - esp->flags = (eventflags_t)0; - esp->cb = NULL; - esp->param = NULL; -} - -/** - * @brief Initializes s @p mutex_t object. - * - * @param[out] mp pointer to the @p mutex_t object - * - * @init - */ -static inline void osalMutexObjectInit(mutex_t *mp) { - - osalDbgCheck(mp != NULL); - - *mp = 0; -} - -#endif /* _OSAL_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/osal/os-less/ARMCMx/osal.mk b/firmware/ChibiOS_16/os/hal/osal/os-less/ARMCMx/osal.mk deleted file mode 100644 index 9cb4af0a0c..0000000000 --- a/firmware/ChibiOS_16/os/hal/osal/os-less/ARMCMx/osal.mk +++ /dev/null @@ -1,5 +0,0 @@ -# OSAL files. -OSALSRC += ${CHIBIOS}/os/hal/osal/os-less/ARMCMx/osal.c - -# Required include directories -OSALINC += ${CHIBIOS}/os/hal/osal/os-less/ARMCMx diff --git a/firmware/ChibiOS_16/os/hal/osal/rt/osal.c b/firmware/ChibiOS_16/os/hal/osal/rt/osal.c deleted file mode 100644 index 1f1c5b9a26..0000000000 --- a/firmware/ChibiOS_16/os/hal/osal/rt/osal.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file osal.c - * @brief OSAL module code. - * - * @addtogroup OSAL - * @{ - */ - -#include "osal.h" - -/*===========================================================================*/ -/* Module local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/osal/rt/osal.h b/firmware/ChibiOS_16/os/hal/osal/rt/osal.h deleted file mode 100644 index c8aa3c3fdd..0000000000 --- a/firmware/ChibiOS_16/os/hal/osal/rt/osal.h +++ /dev/null @@ -1,941 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file osal.h - * @brief OSAL module header. - * - * @addtogroup OSAL - * @{ - */ - -#ifndef _OSAL_H_ -#define _OSAL_H_ - -#include -#include -#include - -#include "ch.h" - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @name Common constants - * @{ - */ -#if !defined(FALSE) || defined(__DOXYGEN__) -#define FALSE 0 -#endif - -#if !defined(TRUE) || defined(__DOXYGEN__) -#define TRUE (!FALSE) -#endif - -#define OSAL_SUCCESS FALSE -#define OSAL_FAILED TRUE -/** @} */ - -#if 0 -/** - * @name Messages - * @{ - */ -#define MSG_OK RDY_OK -#define MSG_RESET RDY_RESET -#define MSG_TIMEOUT RDY_TIMEOUT -/** @} */ -#endif - -#if 0 -/** - * @name Special time constants - * @{ - */ -#define TIME_IMMEDIATE ((systime_t)0) -#define TIME_INFINITE ((systime_t)-1) -/** @} */ -#endif - -/** - * @name Systick modes. - * @{ - */ -#define OSAL_ST_MODE_NONE 0 -#define OSAL_ST_MODE_PERIODIC 1 -#define OSAL_ST_MODE_FREERUNNING 2 -/** @} */ - -/** - * @name Systick parameters. - * @{ - */ -/** - * @brief Size in bits of the @p systick_t type. - */ -#define OSAL_ST_RESOLUTION CH_CFG_ST_RESOLUTION - -/** - * @brief Required systick frequency or resolution. - */ -#define OSAL_ST_FREQUENCY CH_CFG_ST_FREQUENCY - -/** - * @brief Systick mode required by the underlying OS. - */ -#if (CH_CFG_ST_TIMEDELTA == 0) || defined(__DOXYGEN__) -#define OSAL_ST_MODE OSAL_ST_MODE_PERIODIC -#else -#define OSAL_ST_MODE OSAL_ST_MODE_FREERUNNING -#endif -/** @} */ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !(OSAL_ST_MODE == OSAL_ST_MODE_NONE) && \ - !(OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) && \ - !(OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING) -#error "invalid OSAL_ST_MODE setting in osal.h" -#endif - -#if (OSAL_ST_RESOLUTION != 16) && (OSAL_ST_RESOLUTION != 32) -#error "invalid OSAL_ST_RESOLUTION, must be 16 or 32" -#endif - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -#if 0 -/** - * @brief Type of a system status word. - */ -typedef uint32_t syssts_t; -#endif - -#if 0 -/** - * @brief Type of a message. - */ -typedef int32_t msg_t; -#endif - -#if 0 -/** - * @brief Type of system time counter. - */ -typedef uint32_t systime_t; -#endif - -#if 0 -/** - * @brief Type of realtime counter. - */ -typedef uint32_t rtcnt_t; -#endif - -#if 0 -/** - * @brief Type of a thread reference. - */ -typedef thread_t * thread_reference_t; -#endif - -#if 0 -/** - * @brief Type of an event flags mask. - */ -typedef uint32_t eventflags_t; -#endif - -#if !CH_CFG_USE_EVENTS -/** - * @brief Type of an event flags object. - * @note The content of this structure is not part of the API and should - * not be relied upon. Implementers may define this structure in - * an entirely different way. - * @note Retrieval and clearing of the flags are not defined in this - * API and are implementation-dependent. - */ -typedef struct { - volatile eventflags_t flags; /**< @brief Flags stored into the - object. */ -} event_source_t; -#endif - -/** - * @brief Type of a mutex. - * @note If the OS does not support mutexes or there is no OS then them - * mechanism can be simulated. - */ -#if CH_CFG_USE_MUTEXES || defined(__DOXYGEN__) -#elif CH_CFG_USE_SEMAPHORES -typedef semaphore_t mutex_t; -#else -typedef uint32_t mutex_t; -#endif - -#if 0 -/** - * @brief Type of a thread queue. - * @details A thread queue is a queue of sleeping threads, queued threads - * can be dequeued one at time or all together. - * @note In this implementation it is implemented as a single reference - * because there are no real threads. - */ -typedef struct { - thread_reference_t tr; -} threads_queue_t; -#endif - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/* Temporary names provided for ChibiOS 2.x compatibility.*/ -#define osalQueueInit osalThreadQueueObjectInit -#define osalQueueWakeupAllI osalThreadDequeueAllI -#define osalQueueWakeupOneI osalThreadDequeueNextI -#define osalQueueGoSleepTimeoutS osalThreadEnqueueTimeoutS -#define osalEventInit osalEventObjectInit - -/** - * @name Debug related macros - * @{ - */ -/** - * @brief Condition assertion. - * @details If the condition check fails then the OSAL panics with a - * message and halts. - * @note The condition is tested only if the @p OSAL_ENABLE_ASSERTIONS - * switch is enabled. - * @note The remark string is not currently used except for putting a - * comment in the code about the assertion. - * - * @param[in] c the condition to be verified to be true - * @param[in] remark a remark string - * - * @api - */ -#define osalDbgAssert(c, remark) chDbgAssert(c, remark) - -/** - * @brief Function parameters check. - * @details If the condition check fails then the OSAL panics and halts. - * @note The condition is tested only if the @p OSAL_ENABLE_CHECKS switch - * is enabled. - * - * @param[in] c the condition to be verified to be true - * - * @api - */ -#define osalDbgCheck(c) chDbgCheck(c) - -/** - * @brief I-Class state check. - * @note Not implemented in this simplified OSAL. - */ -#define osalDbgCheckClassI() chDbgCheckClassI() - -/** - * @brief S-Class state check. - * @note Not implemented in this simplified OSAL. - */ -#define osalDbgCheckClassS() chDbgCheckClassS() -/** @} */ - -/** - * @name IRQ service routines wrappers - * @{ - */ -/** - * @brief Priority level verification macro. - */ -#define OSAL_IRQ_IS_VALID_PRIORITY(n) CH_IRQ_IS_VALID_KERNEL_PRIORITY(n) - -/** - * @brief IRQ prologue code. - * @details This macro must be inserted at the start of all IRQ handlers. - */ -#define OSAL_IRQ_PROLOGUE() CH_IRQ_PROLOGUE() - -/** - * @brief IRQ epilogue code. - * @details This macro must be inserted at the end of all IRQ handlers. - */ -#define OSAL_IRQ_EPILOGUE() CH_IRQ_EPILOGUE() - -/** - * @brief IRQ handler function declaration. - * @details This macro hides the details of an ISR function declaration. - * - * @param[in] id a vector name as defined in @p vectors.s - */ -#define OSAL_IRQ_HANDLER(id) CH_IRQ_HANDLER(id) -/** @} */ - -/** - * @name Time conversion utilities - * @{ - */ -/** - * @brief Seconds to system ticks. - * @details Converts from seconds to system ticks number. - * @note The result is rounded upward to the next tick boundary. - * - * @param[in] sec number of seconds - * @return The number of ticks. - * - * @api - */ -#define OSAL_S2ST(sec) S2ST(sec) - -/** - * @brief Milliseconds to system ticks. - * @details Converts from milliseconds to system ticks number. - * @note The result is rounded upward to the next tick boundary. - * - * @param[in] msec number of milliseconds - * @return The number of ticks. - * - * @api - */ -#define OSAL_MS2ST(msec) MS2ST(msec) - -/** - * @brief Microseconds to system ticks. - * @details Converts from microseconds to system ticks number. - * @note The result is rounded upward to the next tick boundary. - * - * @param[in] usec number of microseconds - * @return The number of ticks. - * - * @api - */ -#define OSAL_US2ST(usec) US2ST(usec) -/** @} */ - -/** - * @name Time conversion utilities for the realtime counter - * @{ - */ -/** - * @brief Seconds to realtime counter. - * @details Converts from seconds to realtime counter cycles. - * @note The macro assumes that @p freq >= @p 1. - * - * @param[in] freq clock frequency, in Hz, of the realtime counter - * @param[in] sec number of seconds - * @return The number of cycles. - * - * @api - */ -#define OSAL_S2RTC(freq, sec) S2RTC(freq, sec) - -/** - * @brief Milliseconds to realtime counter. - * @details Converts from milliseconds to realtime counter cycles. - * @note The result is rounded upward to the next millisecond boundary. - * @note The macro assumes that @p freq >= @p 1000. - * - * @param[in] freq clock frequency, in Hz, of the realtime counter - * @param[in] msec number of milliseconds - * @return The number of cycles. - * - * @api - */ -#define OSAL_MS2RTC(freq, msec) MS2RTC(freq, msec) - -/** - * @brief Microseconds to realtime counter. - * @details Converts from microseconds to realtime counter cycles. - * @note The result is rounded upward to the next microsecond boundary. - * @note The macro assumes that @p freq >= @p 1000000. - * - * @param[in] freq clock frequency, in Hz, of the realtime counter - * @param[in] usec number of microseconds - * @return The number of cycles. - * - * @api - */ -#define OSAL_US2RTC(freq, usec) US2RTC(freq, usec) -/** @} */ - -/** - * @name Sleep macros using absolute time - * @{ - */ -/** - * @brief Delays the invoking thread for the specified number of seconds. - * @note The specified time is rounded up to a value allowed by the real - * system tick clock. - * @note The maximum specifiable value is implementation dependent. - * - * @param[in] sec time in seconds, must be different from zero - * - * @api - */ -#define osalThreadSleepSeconds(sec) osalThreadSleep(OSAL_S2ST(sec)) - -/** - * @brief Delays the invoking thread for the specified number of - * milliseconds. - * @note The specified time is rounded up to a value allowed by the real - * system tick clock. - * @note The maximum specifiable value is implementation dependent. - * - * @param[in] msec time in milliseconds, must be different from zero - * - * @api - */ -#define osalThreadSleepMilliseconds(msec) osalThreadSleep(OSAL_MS2ST(msec)) - -/** - * @brief Delays the invoking thread for the specified number of - * microseconds. - * @note The specified time is rounded up to a value allowed by the real - * system tick clock. - * @note The maximum specifiable value is implementation dependent. - * - * @param[in] usec time in microseconds, must be different from zero - * - * @api - */ -#define osalThreadSleepMicroseconds(usec) osalThreadSleep(OSAL_US2ST(usec)) -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -/** - * @brief OSAL module initialization. - * - * @api - */ -static inline void osalInit(void) { - -} - -/** - * @brief System halt with error message. - * - * @param[in] reason the halt message pointer - * - * @api - */ -static inline void osalSysHalt(const char *reason) { - - chSysHalt(reason); -} - -/** - * @brief Disables interrupts globally. - * - * @special - */ -static inline void osalSysDisable(void) { - - chSysDisable(); -} - -/** - * @brief Enables interrupts globally. - * - * @special - */ -static inline void osalSysEnable(void) { - - chSysEnable(); -} - -/** - * @brief Enters a critical zone from thread context. - * @note This function cannot be used for reentrant critical zones. - * - * @special - */ -static inline void osalSysLock(void) { - - chSysLock(); -} - -/** - * @brief Leaves a critical zone from thread context. - * @note This function cannot be used for reentrant critical zones. - * - * @special - */ -static inline void osalSysUnlock(void) { - - chSysUnlock(); -} - -/** - * @brief Enters a critical zone from ISR context. - * @note This function cannot be used for reentrant critical zones. - * - * @special - */ -static inline void osalSysLockFromISR(void) { - - chSysLockFromISR(); -} - -/** - * @brief Leaves a critical zone from ISR context. - * @note This function cannot be used for reentrant critical zones. - * - * @special - */ -static inline void osalSysUnlockFromISR(void) { - - chSysUnlockFromISR(); -} - -/** - * @brief Returns the execution status and enters a critical zone. - * @details This functions enters into a critical zone and can be called - * from any context. Because its flexibility it is less efficient - * than @p chSysLock() which is preferable when the calling context - * is known. - * @post The system is in a critical zone. - * - * @return The previous system status, the encoding of this - * status word is architecture-dependent and opaque. - * - * @xclass - */ -static inline syssts_t osalSysGetStatusAndLockX(void) { - - return chSysGetStatusAndLockX(); -} - -/** - * @brief Restores the specified execution status and leaves a critical zone. - * @note A call to @p chSchRescheduleS() is automatically performed - * if exiting the critical zone and if not in ISR context. - * - * @param[in] sts the system status to be restored. - * - * @xclass - */ -static inline void osalSysRestoreStatusX(syssts_t sts) { - - chSysRestoreStatusX(sts); -} - -/** - * @brief Polled delay. - * @note The real delay is always few cycles in excess of the specified - * value. - * - * @param[in] cycles number of cycles - * - * @xclass - */ -#if PORT_SUPPORTS_RT || defined(__DOXYGEN__) -static inline void osalSysPolledDelayX(rtcnt_t cycles) { - - chSysPolledDelayX(cycles); -} -#endif - -/** - * @brief Systick callback for the underlying OS. - * @note This callback is only defined if the OSAL requires such a - * service from the HAL. - */ -#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__) -static inline void osalOsTimerHandlerI(void) { - - chSysTimerHandlerI(); -} -#endif - -/** - * @brief Checks if a reschedule is required and performs it. - * @note I-Class functions invoked from thread context must not reschedule - * by themselves, an explicit reschedule using this function is - * required in this scenario. - * @note Not implemented in this simplified OSAL. - * - * @sclass - */ -static inline void osalOsRescheduleS(void) { - - chSchRescheduleS(); -} - -/** - * @brief Current system time. - * @details Returns the number of system ticks since the @p osalInit() - * invocation. - * @note The counter can reach its maximum and then restart from zero. - * @note This function can be called from any context but its atomicity - * is not guaranteed on architectures whose word size is less than - * @p systime_t size. - * - * @return The system time in ticks. - * - * @xclass - */ -static inline systime_t osalOsGetSystemTimeX(void) { - - return chVTGetSystemTimeX(); -} - -/** - * @brief Checks if the specified time is within the specified time window. - * @note When start==end then the function returns always true because the - * whole time range is specified. - * @note This function can be called from any context. - * - * @param[in] time the time to be verified - * @param[in] start the start of the time window (inclusive) - * @param[in] end the end of the time window (non inclusive) - * @retval true current time within the specified time window. - * @retval false current time not within the specified time window. - * - * @xclass - */ -static inline bool osalOsIsTimeWithinX(systime_t time, - systime_t start, - systime_t end) { - - return chVTIsTimeWithinX(time, start, end); -} - -/** - * @brief Suspends the invoking thread for the specified time. - * - * @param[in] time the delay in system ticks, the special values are - * handled as follow: - * - @a TIME_INFINITE is allowed but interpreted as a - * normal time specification. - * - @a TIME_IMMEDIATE this value is not allowed. - * . - * - * @sclass - */ -static inline void osalThreadSleepS(systime_t time) { - - chThdSleepS(time); -} - -/** - * @brief Suspends the invoking thread for the specified time. - * - * @param[in] time the delay in system ticks, the special values are - * handled as follow: - * - @a TIME_INFINITE is allowed but interpreted as a - * normal time specification. - * - @a TIME_IMMEDIATE this value is not allowed. - * . - * - * @api - */ -static inline void osalThreadSleep(systime_t time) { - - chThdSleep(time); -} - -/** - * @brief Sends the current thread sleeping and sets a reference variable. - * @note This function must reschedule, it can only be called from thread - * context. - * - * @param[in] trp a pointer to a thread reference object - * @return The wake up message. - * - * @sclass - */ -static inline msg_t osalThreadSuspendS(thread_reference_t *trp) { - - return chThdSuspendS(trp); -} - -/** - * @brief Sends the current thread sleeping and sets a reference variable. - * @note This function must reschedule, it can only be called from thread - * context. - * - * @param[in] trp a pointer to a thread reference object - * @param[in] timeout the timeout in system ticks, the special values are - * handled as follow: - * - @a TIME_INFINITE the thread enters an infinite sleep - * state. - * - @a TIME_IMMEDIATE the thread is not enqueued and - * the function returns @p MSG_TIMEOUT as if a timeout - * occurred. - * . - * @return The wake up message. - * @retval MSG_TIMEOUT if the operation timed out. - * - * @sclass - */ -static inline msg_t osalThreadSuspendTimeoutS(thread_reference_t *trp, - systime_t timeout) { - - return chThdSuspendTimeoutS(trp, timeout); -} - -/** - * @brief Wakes up a thread waiting on a thread reference object. - * @note This function must not reschedule because it can be called from - * ISR context. - * - * @param[in] trp a pointer to a thread reference object - * @param[in] msg the message code - * - * @iclass - */ -static inline void osalThreadResumeI(thread_reference_t *trp, msg_t msg) { - - chThdResumeI(trp, msg); -} - -/** - * @brief Wakes up a thread waiting on a thread reference object. - * @note This function must reschedule, it can only be called from thread - * context. - * - * @param[in] trp a pointer to a thread reference object - * @param[in] msg the message code - * - * @iclass - */ -static inline void osalThreadResumeS(thread_reference_t *trp, msg_t msg) { - - chThdResumeS(trp, msg); -} - -/** - * @brief Initializes a threads queue object. - * - * @param[out] tqp pointer to the threads queue object - * - * @init - */ -static inline void osalThreadQueueObjectInit(threads_queue_t *tqp) { - - chThdQueueObjectInit(tqp); -} - -/** - * @brief Enqueues the caller thread. - * @details The caller thread is enqueued and put to sleep until it is - * dequeued or the specified timeouts expires. - * - * @param[in] tqp pointer to the threads queue object - * @param[in] time the timeout in system ticks, the special values are - * handled as follow: - * - @a TIME_INFINITE the thread enters an infinite sleep - * state. - * - @a TIME_IMMEDIATE the thread is not enqueued and - * the function returns @p MSG_TIMEOUT as if a timeout - * occurred. - * . - * @return The message from @p osalQueueWakeupOneI() or - * @p osalQueueWakeupAllI() functions. - * @retval MSG_TIMEOUT if the thread has not been dequeued within the - * specified timeout or if the function has been - * invoked with @p TIME_IMMEDIATE as timeout - * specification. - * - * @sclass - */ -static inline msg_t osalThreadEnqueueTimeoutS(threads_queue_t *tqp, - systime_t time) { - - return chThdEnqueueTimeoutS(tqp, time); -} - -/** - * @brief Dequeues and wakes up one thread from the queue, if any. - * - * @param[in] tqp pointer to the threads queue object - * @param[in] msg the message code - * - * @iclass - */ -static inline void osalThreadDequeueNextI(threads_queue_t *tqp, msg_t msg) { - - chThdDequeueNextI(tqp, msg); -} - -/** - * @brief Dequeues and wakes up all threads from the queue. - * - * @param[in] tqp pointer to the threads queue object - * @param[in] msg the message code - * - * @iclass - */ -static inline void osalThreadDequeueAllI(threads_queue_t *tqp, msg_t msg) { - - chThdDequeueAllI(tqp, msg); -} - -#if CH_CFG_USE_EVENTS || defined(__DOXYGEN__) -/** - * @brief Initializes an event flags object. - * - * @param[out] esp pointer to the event flags object - * - * @init - */ -static inline void osalEventObjectInit(event_source_t *esp) { - - chEvtObjectInit(esp); -} -#else -static inline void osalEventObjectInit(event_source_t *esp) { - - esp->flags = 0; -} -#endif - -#if CH_CFG_USE_EVENTS || defined(__DOXYGEN__) -/** - * @brief Add flags to an event source object. - * - * @param[in] esp pointer to the event flags object - * @param[in] flags flags to be ORed to the flags mask - * - * @iclass - */ -static inline void osalEventBroadcastFlagsI(event_source_t *esp, - eventflags_t flags) { - - chEvtBroadcastFlagsI(esp, flags); -} -#else -static inline void osalEventBroadcastFlagsI(event_source_t *esp, - eventflags_t flags) { - - esp->flags |= flags; -} -#endif - -#if CH_CFG_USE_EVENTS || defined(__DOXYGEN__) -/** - * @brief Add flags to an event source object. - * - * @param[in] esp pointer to the event flags object - * @param[in] flags flags to be ORed to the flags mask - * - * @iclass - */ -static inline void osalEventBroadcastFlags(event_source_t *esp, - eventflags_t flags) { - - chEvtBroadcastFlags(esp, flags); -} -#else -static inline void osalEventBroadcastFlags(event_source_t *esp, - eventflags_t flags) { - osalSysLock(); - esp->flags |= flags; - osalSysUnlock(); -} -#endif - -/** - * @brief Initializes s @p mutex_t object. - * - * @param[out] mp pointer to the @p mutex_t object - * - * @init - */ -static inline void osalMutexObjectInit(mutex_t *mp) { - -#if CH_CFG_USE_MUTEXES - chMtxObjectInit(mp); -#elif CH_CFG_USE_SEMAPHORES - chSemObjectInit((semaphore_t *)mp, 1); -#else - *mp = 0; -#endif -} - -/** - * @brief Locks the specified mutex. - * @post The mutex is locked and inserted in the per-thread stack of owned - * mutexes. - * - * @param[in,out] mp pointer to the @p mutex_t object - * - * @api - */ -static inline void osalMutexLock(mutex_t *mp) { - -#if CH_CFG_USE_MUTEXES - chMtxLock(mp); -#elif CH_CFG_USE_SEMAPHORES - chSemWait((semaphore_t *)mp); -#else - *mp = 1; -#endif -} - -/** - * @brief Unlocks the specified mutex. - * @note The HAL guarantees to release mutex in reverse lock order. The - * mutex being unlocked is guaranteed to be the last locked mutex - * by the invoking thread. - * The implementation can rely on this behavior and eventually - * ignore the @p mp parameter which is supplied in order to support - * those OSes not supporting a stack of the owned mutexes. - * - * @param[in,out] mp pointer to the @p mutex_t object - * - * @api - */ -static inline void osalMutexUnlock(mutex_t *mp) { - -#if CH_CFG_USE_MUTEXES - chMtxUnlock(mp); -#elif CH_CFG_USE_SEMAPHORES - chSemSignal((semaphore_t *)mp); -#else - *mp = 0; -#endif -} - -#endif /* _OSAL_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/osal/rt/osal.mk b/firmware/ChibiOS_16/os/hal/osal/rt/osal.mk deleted file mode 100644 index f1559d9d51..0000000000 --- a/firmware/ChibiOS_16/os/hal/osal/rt/osal.mk +++ /dev/null @@ -1,5 +0,0 @@ -# OSAL files. -OSALSRC += ${CHIBIOS}/os/hal/osal/rt/osal.c - -# Required include directories -OSALINC += ${CHIBIOS}/os/hal/osal/rt diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/ADCv1/adc_lld.c b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/ADCv1/adc_lld.c deleted file mode 100644 index d8337228ca..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/ADCv1/adc_lld.c +++ /dev/null @@ -1,336 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/LLD/ADCv1/adc_lld.c - * @brief STM32 ADC subsystem low level driver source. - * - * @addtogroup ADC - * @{ - */ - -#include "hal.h" - -#if HAL_USE_ADC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define ADC1_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_CHN) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief ADC1 driver identifier.*/ -#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__) -ADCDriver ADCD1; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Stops an ongoing conversion, if any. - * - * @param[in] adc pointer to the ADC registers block - */ -static void adc_lld_stop_adc(ADC_TypeDef *adc) { - - if (adc->CR & ADC_CR_ADSTART) { - adc->CR |= ADC_CR_ADSTP; - while (adc->CR & ADC_CR_ADSTP) - ; - } -} - -/** - * @brief ADC DMA ISR service routine. - * - * @param[in] adcp pointer to the @p ADCDriver object - * @param[in] flags pre-shifted content of the ISR register - */ -static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) { - - /* DMA errors handling.*/ - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - /* DMA, this could help only if the DMA tries to access an unmapped - address space or violates alignment rules.*/ - _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE); - } - else { - /* It is possible that the conversion group has already be reset by the - ADC error handler, in this case this interrupt is spurious.*/ - if (adcp->grpp != NULL) { - if ((flags & STM32_DMA_ISR_TCIF) != 0) { - /* Transfer complete processing.*/ - _adc_isr_full_code(adcp); - } - else if ((flags & STM32_DMA_ISR_HTIF) != 0) { - /* Half transfer processing.*/ - _adc_isr_half_code(adcp); - } - } - } -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if (STM32_ADC_USE_ADC1 && (STM32_ADC1_IRQ_SHARED_WITH_EXTI == FALSE)) || \ - defined(__DOXYGEN__) -#if !defined(STM32_ADC1_HANDLER) -#error "STM32_ADC1_HANDLER not defined" -#endif -/** - * @brief ADC interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_ADC1_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - adc_lld_serve_interrupt(&ADCD1); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level ADC driver initialization. - * - * @notapi - */ -void adc_lld_init(void) { - -#if STM32_ADC_USE_ADC1 - /* Driver initialization.*/ - adcObjectInit(&ADCD1); - ADCD1.adc = ADC1; - ADCD1.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC1_DMA_STREAM); - ADCD1.dmamode = STM32_DMA_CR_CHSEL(ADC1_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | - STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; - -#if STM32_ADC1_IRQ_SHARED_WITH_EXTI == FALSE - /* The shared vector is initialized on driver initialization and never - disabled.*/ - nvicEnableVector(12, STM32_ADC_ADC1_IRQ_PRIORITY); -#endif -#endif - - /* Calibration procedure.*/ - rccEnableADC1(FALSE); - - /* CCR setup.*/ -#if STM32_ADC_SUPPORTS_PRESCALER - ADC->CCR = STM32_ADC_PRESC << 18; -#else - ADC->CCR = 0; -#endif - - osalDbgAssert(ADC1->CR == 0, "invalid register state"); - ADC1->CR |= ADC_CR_ADCAL; - osalDbgAssert(ADC1->CR != 0, "invalid register state"); - while (ADC1->CR & ADC_CR_ADCAL) - ; - rccDisableADC1(FALSE); -} - -/** - * @brief Configures and activates the ADC peripheral. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_start(ADCDriver *adcp) { - - /* If in stopped state then enables the ADC and DMA clocks.*/ - if (adcp->state == ADC_STOP) { -#if STM32_ADC_USE_ADC1 - if (&ADCD1 == adcp) { - bool b; - b = dmaStreamAllocate(adcp->dmastp, - STM32_ADC_ADC1_DMA_IRQ_PRIORITY, - (stm32_dmaisr_t)adc_lld_serve_rx_interrupt, - (void *)adcp); - osalDbgAssert(!b, "stream already allocated"); - dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR); - rccEnableADC1(FALSE); - - /* Clock settings.*/ - adcp->adc->CFGR2 = STM32_ADC_ADC1_CKMODE; - } -#endif /* STM32_ADC_USE_ADC1 */ - - /* ADC initial setup, starting the analog part here in order to reduce - the latency when starting a conversion.*/ - adcp->adc->CR = ADC_CR_ADEN; - while (!(adcp->adc->ISR & ADC_ISR_ADRDY)) - ; - } -} - -/** - * @brief Deactivates the ADC peripheral. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_stop(ADCDriver *adcp) { - - /* If in ready state then disables the ADC clock and analog part.*/ - if (adcp->state == ADC_READY) { - - dmaStreamRelease(adcp->dmastp); - - /* Restoring CCR default.*/ -#if STM32_ADC_SUPPORTS_PRESCALER - ADC->CCR = STM32_ADC_PRESC << 18; -#else - ADC->CCR = 0; -#endif - - /* Disabling ADC.*/ - if (adcp->adc->CR & ADC_CR_ADEN) { - adc_lld_stop_adc(adcp->adc); - adcp->adc->CR |= ADC_CR_ADDIS; - while (adcp->adc->CR & ADC_CR_ADDIS) - ; - } - -#if STM32_ADC_USE_ADC1 - if (&ADCD1 == adcp) - rccDisableADC1(FALSE); -#endif - } -} - -/** - * @brief Starts an ADC conversion. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_start_conversion(ADCDriver *adcp) { - uint32_t mode, cfgr1; - const ADCConversionGroup *grpp = adcp->grpp; - - /* DMA setup.*/ - mode = adcp->dmamode; - cfgr1 = grpp->cfgr1 | ADC_CFGR1_DMAEN; - if (grpp->circular) { - mode |= STM32_DMA_CR_CIRC; - cfgr1 |= ADC_CFGR1_DMACFG; - if (adcp->depth > 1) { - /* If circular buffer depth > 1, then the half transfer interrupt - is enabled in order to allow streaming processing.*/ - mode |= STM32_DMA_CR_HTIE; - } - } - dmaStreamSetMemory0(adcp->dmastp, adcp->samples); - dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels * - (uint32_t)adcp->depth); - dmaStreamSetMode(adcp->dmastp, mode); - dmaStreamEnable(adcp->dmastp); - - /* ADC setup, if it is defined a callback for the analog watch dog then it - is enabled.*/ - adcp->adc->ISR = adcp->adc->ISR; - adcp->adc->IER = ADC_IER_OVRIE | ADC_IER_AWDIE; - adcp->adc->TR = grpp->tr; - adcp->adc->SMPR = grpp->smpr; - adcp->adc->CHSELR = grpp->chselr; - - /* ADC configuration and start.*/ - adcp->adc->CFGR1 = cfgr1; -#if STM32_ADC_SUPPORTS_OVERSAMPLING == TRUE - { - uint32_t cfgr2 = adcp->adc->CFGR2 & STM32_ADC_CKMODE_MASK; - adcp->adc->CFGR2 = cfgr2 | grpp->cfgr2; - } -#endif - - /* ADC conversion start.*/ - adcp->adc->CR |= ADC_CR_ADSTART; -} - -/** - * @brief Stops an ongoing conversion. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_stop_conversion(ADCDriver *adcp) { - - dmaStreamDisable(adcp->dmastp); - adc_lld_stop_adc(adcp->adc); -} - -/** - * @brief ISR code. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_serve_interrupt(ADCDriver *adcp) { - uint32_t isr; - - isr = adcp->adc->ISR; - adcp->adc->ISR = isr; - - /* It could be a spurious interrupt caused by overflows after DMA disabling, - just ignore it in this case.*/ - if (adcp->grpp != NULL) { - /* Note, an overflow may occur after the conversion ended before the driver - is able to stop the ADC, this is why the DMA channel is checked too.*/ - if ((isr & ADC_ISR_OVR) && - (dmaStreamGetTransactionSize(adcp->dmastp) > 0)) { - /* ADC overflow condition, this could happen only if the DMA is unable - to read data fast enough.*/ - _adc_isr_error_code(adcp, ADC_ERR_OVERFLOW); - } - if (isr & ADC_ISR_AWD) { - /* Analog watchdog error.*/ - _adc_isr_error_code(adcp, ADC_ERR_AWD); - } - } -} - -#endif /* HAL_USE_ADC */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/ADCv1/adc_lld.h b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/ADCv1/adc_lld.h deleted file mode 100644 index 98ff463927..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/ADCv1/adc_lld.h +++ /dev/null @@ -1,441 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/LLD/ADCv1/adc_lld.h - * @brief STM32 ADC subsystem low level driver header. - * - * @addtogroup ADC - * @{ - */ - -#ifndef _ADC_LLD_H_ -#define _ADC_LLD_H_ - -#if HAL_USE_ADC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name Sampling rates - * @{ - */ -#define ADC_SMPR_SMP_1P5 0U /**< @brief 14 cycles conversion time */ -#define ADC_SMPR_SMP_7P5 1U /**< @brief 21 cycles conversion time. */ -#define ADC_SMPR_SMP_13P5 2U /**< @brief 28 cycles conversion time. */ -#define ADC_SMPR_SMP_28P5 3U /**< @brief 41 cycles conversion time. */ -#define ADC_SMPR_SMP_41P5 4U /**< @brief 54 cycles conversion time. */ -#define ADC_SMPR_SMP_55P5 5U /**< @brief 68 cycles conversion time. */ -#define ADC_SMPR_SMP_71P5 6U /**< @brief 84 cycles conversion time. */ -#define ADC_SMPR_SMP_239P5 7U /**< @brief 252 cycles conversion time. */ -/** @} */ - -/** - * @name CFGR1 register configuration helpers - * @{ - */ -#define ADC_CFGR1_RES_12BIT (0U << 3U) -#define ADC_CFGR1_RES_10BIT (1U << 3U) -#define ADC_CFGR1_RES_8BIT (2U << 3U) -#define ADC_CFGR1_RES_6BIT (3U << 3U) - -#define ADC_CFGR1_EXTSEL_MASK (15U << 6U) -#define ADC_CFGR1_EXTSEL_SRC(n) ((n) << 6U) - -#define ADC_CFGR1_EXTEN_MASK (3U << 10U) -#define ADC_CFGR1_EXTEN_DISABLED (0U << 10U) -#define ADC_CFGR1_EXTEN_RISING (1U << 10U) -#define ADC_CFGR1_EXTEN_FALLING (2U << 10U) -#define ADC_CFGR1_EXTEN_BOTH (3U << 10U) -/** @} */ - -/** - * @name CFGR2 register configuration helpers - * @{ - */ -#define STM32_ADC_CKMODE_MASK (3U << 30U) -#define STM32_ADC_CKMODE_ADCCLK (0U << 30U) -#define STM32_ADC_CKMODE_PCLK_DIV2 (1U << 30U) -#define STM32_ADC_CKMODE_PCLK_DIV4 (2U << 30U) -#define STM32_ADC_CKMODE_PCLK (3U << 30U) - -#if (STM32_ADC_SUPPORTS_OVERSAMPLING == TRUE) || defined(__DOXYGEN__) -#define ADC_CFGR2_OVSR_MASK (7U << 2U) -#define ADC_CFGR2_OVSR_2X (0U << 2U) -#define ADC_CFGR2_OVSR_4X (1U << 2U) -#define ADC_CFGR2_OVSR_8X (2U << 2U) -#define ADC_CFGR2_OVSR_16X (3U << 2U) -#define ADC_CFGR2_OVSR_32X (4U << 2U) -#define ADC_CFGR2_OVSR_64X (5U << 2U) -#define ADC_CFGR2_OVSR_128X (6U << 2U) -#define ADC_CFGR2_OVSR_256X (7U << 2U) - -#define ADC_CFGR2_OVSS_MASK (15 << 5U) -#define ADC_CFGR2_OVSS_SHIFT(n) ((n) << 5U) -#endif -/** @} */ - -/** - * @name Threashold register initializer - * @{ - */ -#define ADC_TR(low, high) (((uint32_t)(high) << 16U) | \ - (uint32_t)(low)) -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief ADC1 driver enable switch. - * @details If set to @p TRUE the support for ADC1 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__) -#define STM32_ADC_USE_ADC1 FALSE -#endif - -/** - * @brief ADC1 clock source selection. - */ -#if !defined(STM32_ADC_ADC1_CKMODE) || defined(__DOXYGEN__) -#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK -#endif - -/** - * @brief ADC1 DMA priority (0..3|lowest..highest). - */ -#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#endif - -/** - * @brief ADC interrupt priority level setting. - */ -#if !defined(STM32_ADC_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_ADC1_IRQ_PRIORITY 2 -#endif - -/** - * @brief ADC1 DMA interrupt priority level setting. - */ -#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2 -#endif - -#if (STM32_ADC_SUPPORTS_PRESCALER == TRUE) || defined(__DOXYGEN__) -/* - * @brief ADC prescaler setting. - * @note This setting has effect only in asynchronous clock mode (the - * default, @p STM32_ADC_CKMODE_ADCCLK). - */ -#if !defined(STM32_ADC_PRESCALER_VALUE) || defined(__DOXYGEN__) -#define STM32_ADC_PRESCALER_VALUE 1 -#endif -#endif - -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1 -#error "ADC1 not present in the selected device" -#endif - -#if !STM32_ADC_USE_ADC1 -#error "ADC driver activated but no ADC peripheral assigned" -#endif - -#if STM32_ADC1_IRQ_SHARED_WITH_EXTI == FALSE -#if STM32_ADC_USE_ADC1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to ADC1" -#endif -#endif - -#if STM32_ADC_USE_ADC1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to ADC1 DMA" -#endif - -#if STM32_ADC_USE_ADC1 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_PRIORITY) -#error "Invalid DMA priority assigned to ADC1" -#endif - -#if STM32_ADC_SUPPORTS_PRESCALER == TRUE -#if STM32_ADC_PRESCALER_VALUE == 1 -#define STM32_ADC_PRESC 0U -#elif STM32_ADC_PRESCALER_VALUE == 2 -#define STM32_ADC_PRESC 1U -#elif STM32_ADC_PRESCALER_VALUE == 4 -#define STM32_ADC_PRESC 2U -#elif STM32_ADC_PRESCALER_VALUE == 6 -#define STM32_ADC_PRESC 3U -#elif STM32_ADC_PRESCALER_VALUE == 8 -#define STM32_ADC_PRESC 4U -#elif STM32_ADC_PRESCALER_VALUE == 10 -#define STM32_ADC_PRESC 5U -#elif STM32_ADC_PRESCALER_VALUE == 12 -#define STM32_ADC_PRESC 6U -#elif STM32_ADC_PRESCALER_VALUE == 16 -#define STM32_ADC_PRESC 7U -#elif STM32_ADC_PRESCALER_VALUE == 32 -#define STM32_ADC_PRESC 8U -#elif STM32_ADC_PRESCALER_VALUE == 64 -#define STM32_ADC_PRESC 9U -#elif STM32_ADC_PRESCALER_VALUE == 128 -#define STM32_ADC_PRESC 10U -#elif STM32_ADC_PRESCALER_VALUE == 256 -#define STM32_ADC_PRESC 11U -#else -#error "Invalid value assigned to STM32_ADC_PRESCALER_VALUE" -#endif -#endif - -/* Check on the presence of the DMA streams settings in mcuconf.h.*/ -#if STM32_ADC_USE_ADC1 && !defined(STM32_ADC_ADC1_DMA_STREAM) -#error "ADC DMA stream not defined" -#endif - -/* Check on the validity of the assigned DMA channels.*/ -#if STM32_ADC_USE_ADC1 && \ - !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_MSK) -#error "invalid DMA stream associated to ADC1" -#endif - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief ADC sample data type. - */ -typedef uint16_t adcsample_t; - -/** - * @brief Channels number in a conversion group. - */ -typedef uint16_t adc_channels_num_t; - -/** - * @brief Possible ADC failure causes. - * @note Error codes are architecture dependent and should not relied - * upon. - */ -typedef enum { - ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */ - ADC_ERR_OVERFLOW = 1, /**< ADC overflow condition. */ - ADC_ERR_AWD = 2 /**< Analog watchdog triggered. */ -} adcerror_t; - -/** - * @brief Type of a structure representing an ADC driver. - */ -typedef struct ADCDriver ADCDriver; - -/** - * @brief ADC notification callback type. - * - * @param[in] adcp pointer to the @p ADCDriver object triggering the - * callback - * @param[in] buffer pointer to the most recent samples data - * @param[in] n number of buffer rows available starting from @p buffer - */ -typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n); - -/** - * @brief ADC error callback type. - * - * @param[in] adcp pointer to the @p ADCDriver object triggering the - * callback - * @param[in] err ADC error code - */ -typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err); - -/** - * @brief Conversion group configuration structure. - * @details This implementation-dependent structure describes a conversion - * operation. - * @note The use of this configuration structure requires knowledge of - * STM32 ADC cell registers interface, please refer to the STM32 - * reference manual for details. - */ -typedef struct { - /** - * @brief Enables the circular buffer mode for the group. - */ - bool circular; - /** - * @brief Number of the analog channels belonging to the conversion group. - */ - adc_channels_num_t num_channels; - /** - * @brief Callback function associated to the group or @p NULL. - */ - adccallback_t end_cb; - /** - * @brief Error callback or @p NULL. - */ - adcerrorcallback_t error_cb; - /* End of the mandatory fields.*/ - /** - * @brief ADC CFGR1 register initialization data. - * @note The bits DMAEN and DMACFG are enforced internally - * to the driver, keep them to zero. - * @note The bits @p ADC_CFGR1_CONT or @p ADC_CFGR1_DISCEN must be - * specified in continuous more or if the buffer depth is - * greater than one. - */ - uint32_t cfgr1; -#if (STM32_ADC_SUPPORTS_OVERSAMPLING == TRUE) || defined(__DOXYGEN__) - /** - * @brief ADC CFGR2 register initialization data. - * @note CKMODE bits must not be specified in this field and left to - * zero. - */ - uint32_t cfgr2; -#endif - /** - * @brief ADC TR register initialization data. - */ - uint32_t tr; - /** - * @brief ADC SMPR register initialization data. - */ - uint32_t smpr; - /** - * @brief ADC CHSELR register initialization data. - * @details The number of bits at logic level one in this register must - * be equal to the number in the @p num_channels field. - */ - uint32_t chselr; -} ADCConversionGroup; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - uint32_t dummy; -} ADCConfig; - -/** - * @brief Structure representing an ADC driver. - */ -struct ADCDriver { - /** - * @brief Driver state. - */ - adcstate_t state; - /** - * @brief Current configuration data. - */ - const ADCConfig *config; - /** - * @brief Current samples buffer pointer or @p NULL. - */ - adcsample_t *samples; - /** - * @brief Current samples buffer depth or @p 0. - */ - size_t depth; - /** - * @brief Current conversion group pointer or @p NULL. - */ - const ADCConversionGroup *grpp; -#if ADC_USE_WAIT || defined(__DOXYGEN__) - /** - * @brief Waiting thread. - */ - thread_reference_t thread; -#endif -#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the peripheral. - */ - mutex_t mutex; -#endif /* ADC_USE_MUTUAL_EXCLUSION */ -#if defined(ADC_DRIVER_EXT_FIELDS) - ADC_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the ADCx registers block. - */ - ADC_TypeDef *adc; - /** - * @brief Pointer to associated DMA channel. - */ - const stm32_dma_stream_t *dmastp; - /** - * @brief DMA mode bit mask. - */ - uint32_t dmamode; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Changes the value of the ADC CCR register. - * @details Use this function in order to enable or disable the internal - * analog sources. See the documentation in the STM32 Reference - * Manual. - * @note PRESC bits must not be specified and left to zero. - */ -#define adcSTM32SetCCR(ccr) (ADC->CCR = (ccr)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__) -extern ADCDriver ADCD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void adc_lld_init(void); - void adc_lld_start(ADCDriver *adcp); - void adc_lld_stop(ADCDriver *adcp); - void adc_lld_start_conversion(ADCDriver *adcp); - void adc_lld_stop_conversion(ADCDriver *adcp); - void adc_lld_serve_interrupt(ADCDriver *adcp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_ADC */ - -#endif /* _ADC_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/ADCv1/notes.txt b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/ADCv1/notes.txt deleted file mode 100644 index ec7103c3e5..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/ADCv1/notes.txt +++ /dev/null @@ -1,16 +0,0 @@ -STM32 ADCv1 driver. - -Driver capability: - -- Supports the STM32 "simple" ADC, the one found on small devices (F0, L0). - -The file registry must export: - -STM32_HAS_ADC1 - ADC1 presence flag. -STM32_ADC_SUPPORTS_PRESCALER - Support of CCR PRESC field. -STM32_ADC_SUPPORTS_OVERSAMPLING - Support of oversampling-related fields. -STM32_ADC1_IRQ_SHARED_WITH_EXTI - TRUE if the IRQ is shared with EXTI. -STM32_ADC1_HANDLER - IRQ vector name. -STM32_ADC1_NUMBER - IRQ vector number. -STM32_ADC1_DMA_MSK - Mask of the compatible DMA channels. -STM32_ADC1_DMA_CHN - Mask of the channels mapping. diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/ADCv2/adc_lld.c b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/ADCv2/adc_lld.c deleted file mode 100644 index 9064d5c784..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/ADCv2/adc_lld.c +++ /dev/null @@ -1,428 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/LLD/ADCv2/adc_lld.c - * @brief STM32 ADC subsystem low level driver source. - * - * @addtogroup ADC - * @{ - */ - -#include "hal.h" - -#if HAL_USE_ADC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define ADC1_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_CHN) - -#define ADC2_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_ADC_ADC2_DMA_STREAM, STM32_ADC2_DMA_CHN) - -#define ADC3_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_ADC_ADC3_DMA_STREAM, STM32_ADC3_DMA_CHN) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief ADC1 driver identifier.*/ -#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__) -ADCDriver ADCD1; -#endif - -/** @brief ADC2 driver identifier.*/ -#if STM32_ADC_USE_ADC2 || defined(__DOXYGEN__) -ADCDriver ADCD2; -#endif - -/** @brief ADC3 driver identifier.*/ -#if STM32_ADC_USE_ADC3 || defined(__DOXYGEN__) -ADCDriver ADCD3; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief ADC DMA ISR service routine. - * - * @param[in] adcp pointer to the @p ADCDriver object - * @param[in] flags pre-shifted content of the ISR register - */ -static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) { - - /* DMA errors handling.*/ - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - /* DMA, this could help only if the DMA tries to access an unmapped - address space or violates alignment rules.*/ - _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE); - } - else { - /* It is possible that the conversion group has already be reset by the - ADC error handler, in this case this interrupt is spurious.*/ - if (adcp->grpp != NULL) { - - if ((flags & STM32_DMA_ISR_TCIF) != 0) { - /* Transfer complete processing.*/ - _adc_isr_full_code(adcp); - } - else if ((flags & STM32_DMA_ISR_HTIF) != 0) { - /* Half transfer processing.*/ - _adc_isr_half_code(adcp); - } - } - } -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2 || STM32_ADC_USE_ADC3 || \ - defined(__DOXYGEN__) -/** - * @brief ADC interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_ADC_HANDLER) { - uint32_t sr; - - OSAL_IRQ_PROLOGUE(); - -#if STM32_ADC_USE_ADC1 - sr = ADC1->SR; - ADC1->SR = 0; - /* Note, an overflow may occur after the conversion ended before the driver - is able to stop the ADC, this is why the DMA channel is checked too.*/ - if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD1.dmastp) > 0)) { - /* ADC overflow condition, this could happen only if the DMA is unable - to read data fast enough.*/ - if (ADCD1.grpp != NULL) - _adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW); - } - /* TODO: Add here analog watchdog handling.*/ -#endif /* STM32_ADC_USE_ADC1 */ - -#if STM32_ADC_USE_ADC2 - sr = ADC2->SR; - ADC2->SR = 0; - /* Note, an overflow may occur after the conversion ended before the driver - is able to stop the ADC, this is why the DMA channel is checked too.*/ - if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD2.dmastp) > 0)) { - /* ADC overflow condition, this could happen only if the DMA is unable - to read data fast enough.*/ - if (ADCD2.grpp != NULL) - _adc_isr_error_code(&ADCD2, ADC_ERR_OVERFLOW); - } - /* TODO: Add here analog watchdog handling.*/ -#endif /* STM32_ADC_USE_ADC2 */ - -#if STM32_ADC_USE_ADC3 - sr = ADC3->SR; - ADC3->SR = 0; - /* Note, an overflow may occur after the conversion ended before the driver - is able to stop the ADC, this is why the DMA channel is checked too.*/ - if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD3.dmastp) > 0)) { - /* ADC overflow condition, this could happen only if the DMA is unable - to read data fast enough.*/ - if (ADCD3.grpp != NULL) - _adc_isr_error_code(&ADCD3, ADC_ERR_OVERFLOW); - } - /* TODO: Add here analog watchdog handling.*/ -#endif /* STM32_ADC_USE_ADC3 */ - - OSAL_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level ADC driver initialization. - * - * @notapi - */ -void adc_lld_init(void) { - -#if STM32_ADC_USE_ADC1 - /* Driver initialization.*/ - adcObjectInit(&ADCD1); - ADCD1.adc = ADC1; - ADCD1.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC1_DMA_STREAM); - ADCD1.dmamode = STM32_DMA_CR_CHSEL(ADC1_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | - STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; -#endif - -#if STM32_ADC_USE_ADC2 - /* Driver initialization.*/ - adcObjectInit(&ADCD2); - ADCD2.adc = ADC2; - ADCD2.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC2_DMA_STREAM); - ADCD2.dmamode = STM32_DMA_CR_CHSEL(ADC2_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_ADC_ADC2_DMA_PRIORITY) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | - STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; -#endif - -#if STM32_ADC_USE_ADC3 - /* Driver initialization.*/ - adcObjectInit(&ADCD3); - ADCD3.adc = ADC3; - ADCD3.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC3_DMA_STREAM); - ADCD3.dmamode = STM32_DMA_CR_CHSEL(ADC3_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_ADC_ADC3_DMA_PRIORITY) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | - STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; -#endif - - /* The shared vector is initialized on driver initialization and never - disabled because sharing.*/ - nvicEnableVector(STM32_ADC_NUMBER, STM32_ADC_IRQ_PRIORITY); -} - -/** - * @brief Configures and activates the ADC peripheral. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_start(ADCDriver *adcp) { - - /* If in stopped state then enables the ADC and DMA clocks.*/ - if (adcp->state == ADC_STOP) { -#if STM32_ADC_USE_ADC1 - if (&ADCD1 == adcp) { - bool b; - b = dmaStreamAllocate(adcp->dmastp, - STM32_ADC_ADC1_DMA_IRQ_PRIORITY, - (stm32_dmaisr_t)adc_lld_serve_rx_interrupt, - (void *)adcp); - osalDbgAssert(!b, "stream already allocated"); - dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR); - rccEnableADC1(FALSE); - } -#endif /* STM32_ADC_USE_ADC1 */ - -#if STM32_ADC_USE_ADC2 - if (&ADCD2 == adcp) { - bool b; - b = dmaStreamAllocate(adcp->dmastp, - STM32_ADC_ADC2_DMA_IRQ_PRIORITY, - (stm32_dmaisr_t)adc_lld_serve_rx_interrupt, - (void *)adcp); - osalDbgAssert(!b, "stream already allocated"); - dmaStreamSetPeripheral(adcp->dmastp, &ADC2->DR); - rccEnableADC2(FALSE); - } -#endif /* STM32_ADC_USE_ADC2 */ - -#if STM32_ADC_USE_ADC3 - if (&ADCD3 == adcp) { - bool b; - b = dmaStreamAllocate(adcp->dmastp, - STM32_ADC_ADC3_DMA_IRQ_PRIORITY, - (stm32_dmaisr_t)adc_lld_serve_rx_interrupt, - (void *)adcp); - osalDbgAssert(!b, "stream already allocated"); - dmaStreamSetPeripheral(adcp->dmastp, &ADC3->DR); - rccEnableADC3(FALSE); - } -#endif /* STM32_ADC_USE_ADC3 */ - - /* This is a common register but apparently it requires that at least one - of the ADCs is clocked in order to allow writing, see bug 3575297.*/ - ADC->CCR = (ADC->CCR & (ADC_CCR_TSVREFE | ADC_CCR_VBATE)) | - (STM32_ADC_ADCPRE << 16); - - /* ADC initial setup, starting the analog part here in order to reduce - the latency when starting a conversion.*/ - adcp->adc->CR1 = 0; - adcp->adc->CR2 = 0; - adcp->adc->CR2 = ADC_CR2_ADON; - } -} - -/** - * @brief Deactivates the ADC peripheral. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_stop(ADCDriver *adcp) { - - /* If in ready state then disables the ADC clock.*/ - if (adcp->state == ADC_READY) { - dmaStreamRelease(adcp->dmastp); - adcp->adc->CR1 = 0; - adcp->adc->CR2 = 0; - -#if STM32_ADC_USE_ADC1 - if (&ADCD1 == adcp) - rccDisableADC1(FALSE); -#endif - -#if STM32_ADC_USE_ADC2 - if (&ADCD2 == adcp) - rccDisableADC2(FALSE); -#endif - -#if STM32_ADC_USE_ADC3 - if (&ADCD3 == adcp) - rccDisableADC3(FALSE); -#endif - } -} - -/** - * @brief Starts an ADC conversion. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_start_conversion(ADCDriver *adcp) { - uint32_t mode; - uint32_t cr2; - const ADCConversionGroup *grpp = adcp->grpp; - - /* DMA setup.*/ - mode = adcp->dmamode; - if (grpp->circular) { - mode |= STM32_DMA_CR_CIRC; - if (adcp->depth > 1) { - /* If circular buffer depth > 1, then the half transfer interrupt - is enabled in order to allow streaming processing.*/ - mode |= STM32_DMA_CR_HTIE; - } - } - dmaStreamSetMemory0(adcp->dmastp, adcp->samples); - dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels * - (uint32_t)adcp->depth); - dmaStreamSetMode(adcp->dmastp, mode); - dmaStreamEnable(adcp->dmastp); - - /* ADC setup.*/ - adcp->adc->SR = 0; - adcp->adc->SMPR1 = grpp->smpr1; - adcp->adc->SMPR2 = grpp->smpr2; - adcp->adc->SQR1 = grpp->sqr1; - adcp->adc->SQR2 = grpp->sqr2; - adcp->adc->SQR3 = grpp->sqr3; - - /* ADC configuration and start.*/ - adcp->adc->CR1 = grpp->cr1 | ADC_CR1_OVRIE | ADC_CR1_SCAN; - - /* Enforcing the mandatory bits in CR2.*/ - cr2 = grpp->cr2 | ADC_CR2_DMA | ADC_CR2_DDS | ADC_CR2_ADON; - - /* The start method is different dependign if HW or SW triggered, the - start is performed using the method specified in the CR2 configuration.*/ - if ((cr2 & ADC_CR2_SWSTART) != 0) { - /* Initializing CR2 while keeping ADC_CR2_SWSTART at zero.*/ - adcp->adc->CR2 = (cr2 | ADC_CR2_CONT) & ~ADC_CR2_SWSTART; - - /* Finally enabling ADC_CR2_SWSTART.*/ - adcp->adc->CR2 = (cr2 | ADC_CR2_CONT); - } - else - adcp->adc->CR2 = cr2; -} - -/** - * @brief Stops an ongoing conversion. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_stop_conversion(ADCDriver *adcp) { - - dmaStreamDisable(adcp->dmastp); - adcp->adc->CR1 = 0; - adcp->adc->CR2 = 0; - adcp->adc->CR2 = ADC_CR2_ADON; -} - -/** - * @brief Enables the TSVREFE bit. - * @details The TSVREFE bit is required in order to sample the internal - * temperature sensor and internal reference voltage. - * @note This is an STM32-only functionality. - */ -void adcSTM32EnableTSVREFE(void) { - - ADC->CCR |= ADC_CCR_TSVREFE; -} - -/** - * @brief Disables the TSVREFE bit. - * @details The TSVREFE bit is required in order to sample the internal - * temperature sensor and internal reference voltage. - * @note This is an STM32-only functionality. - */ -void adcSTM32DisableTSVREFE(void) { - - ADC->CCR &= ~ADC_CCR_TSVREFE; -} - -/** - * @brief Enables the VBATE bit. - * @details The VBATE bit is required in order to sample the VBAT channel. - * @note This is an STM32-only functionality. - * @note This function is meant to be called after @p adcStart(). - */ -void adcSTM32EnableVBATE(void) { - - ADC->CCR |= ADC_CCR_VBATE; -} - -/** - * @brief Disables the VBATE bit. - * @details The VBATE bit is required in order to sample the VBAT channel. - * @note This is an STM32-only functionality. - * @note This function is meant to be called after @p adcStart(). - */ -void adcSTM32DisableVBATE(void) { - - ADC->CCR &= ~ADC_CCR_VBATE; -} - -#endif /* HAL_USE_ADC */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/ADCv2/adc_lld.h b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/ADCv2/adc_lld.h deleted file mode 100644 index 590f7c3d19..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/ADCv2/adc_lld.h +++ /dev/null @@ -1,570 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/LLD/ADCv2/adc_lld.h - * @brief STM32 ADC subsystem low level driver header. - * - * @addtogroup ADC - * @{ - */ - -#ifndef _ADC_LLD_H_ -#define _ADC_LLD_H_ - -#if HAL_USE_ADC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name Absolute Maximum Ratings - * @{ - */ -/** - * @brief Minimum ADC clock frequency. - */ -#define STM32_ADCCLK_MIN 600000 - -/** - * @brief Maximum ADC clock frequency. - */ -#if defined(STM32F4XX) || defined(__DOXYGEN__) -#define STM32_ADCCLK_MAX 36000000 -#else -#define STM32_ADCCLK_MAX 30000000 -#endif -/** @} */ - -/** - * @name Triggers selection - * @{ - */ -#define ADC_CR2_EXTEN_MASK (3U << 28U) -#define ADC_CR2_EXTEN_DISABLED (0U << 28U) -#define ADC_CR2_EXTEN_RISING (1U << 28U) -#define ADC_CR2_EXTEN_FALLING (2U << 28U) -#define ADC_CR2_EXTEN_BOTH (3U << 28U) - -#define ADC_CR2_EXTSEL_MASK (15U << 24U) -#define ADC_CR2_EXTSEL_SRC(n) ((n) << 24U) -/** @} */ - -/** - * @name ADC clock divider settings - * @{ - */ -#define ADC_CCR_ADCPRE_DIV2 0 -#define ADC_CCR_ADCPRE_DIV4 1 -#define ADC_CCR_ADCPRE_DIV6 2 -#define ADC_CCR_ADCPRE_DIV8 3 -/** @} */ - -/** - * @name Available analog channels - * @{ - */ -#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */ -#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */ -#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */ -#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */ -#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */ -#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */ -#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */ -#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */ -#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */ -#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */ -#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */ -#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */ -#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */ -#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */ -#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */ -#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */ -#define ADC_CHANNEL_SENSOR 16 /**< @brief Internal temperature sensor. - @note Available onADC1 only. */ -#define ADC_CHANNEL_VREFINT 17 /**< @brief Internal reference. - @note Available onADC1 only. */ -#define ADC_CHANNEL_VBAT 18 /**< @brief VBAT. - @note Available onADC1 only. */ -/** @} */ - -/** - * @name Sampling rates - * @{ - */ -#define ADC_SAMPLE_3 0 /**< @brief 3 cycles sampling time. */ -#define ADC_SAMPLE_15 1 /**< @brief 15 cycles sampling time. */ -#define ADC_SAMPLE_28 2 /**< @brief 28 cycles sampling time. */ -#define ADC_SAMPLE_56 3 /**< @brief 56 cycles sampling time. */ -#define ADC_SAMPLE_84 4 /**< @brief 84 cycles sampling time. */ -#define ADC_SAMPLE_112 5 /**< @brief 112 cycles sampling time. */ -#define ADC_SAMPLE_144 6 /**< @brief 144 cycles sampling time. */ -#define ADC_SAMPLE_480 7 /**< @brief 480 cycles sampling time. */ -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief ADC common clock divider. - * @note This setting is influenced by the VDDA voltage and other - * external conditions, please refer to the datasheet for more - * info.
- * See section 5.3.20 "12-bit ADC characteristics". - */ -#if !defined(STM32_ADC_ADCPRE) || defined(__DOXYGEN__) -#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV2 -#endif - -/** - * @brief ADC1 driver enable switch. - * @details If set to @p TRUE the support for ADC1 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__) -#define STM32_ADC_USE_ADC1 FALSE -#endif - -/** - * @brief ADC2 driver enable switch. - * @details If set to @p TRUE the support for ADC2 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_ADC_USE_ADC2) || defined(__DOXYGEN__) -#define STM32_ADC_USE_ADC2 FALSE -#endif - -/** - * @brief ADC3 driver enable switch. - * @details If set to @p TRUE the support for ADC3 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_ADC_USE_ADC3) || defined(__DOXYGEN__) -#define STM32_ADC_USE_ADC3 FALSE -#endif - -/** - * @brief DMA stream used for ADC1 operations. - */ -#if !defined(STM32_ADC_ADC1_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) -#endif - -/** - * @brief DMA stream used for ADC2 operations. - */ -#if !defined(STM32_ADC_ADC2_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#endif - -/** - * @brief DMA stream used for ADC3 operations. - */ -#if !defined(STM32_ADC_ADC3_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#endif - -/** - * @brief ADC1 DMA priority (0..3|lowest..highest). - */ -#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#endif - -/** - * @brief ADC2 DMA priority (0..3|lowest..highest). - */ -#if !defined(STM32_ADC_ADC2_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_ADC2_DMA_PRIORITY 2 -#endif - -/** - * @brief ADC3 DMA priority (0..3|lowest..highest). - */ -#if !defined(STM32_ADC_ADC3_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_ADC3_DMA_PRIORITY 2 -#endif - -/** - * @brief ADC interrupt priority level setting. - * @note This setting is shared among ADC1, ADC2 and ADC3 because - * all ADCs share the same vector. - */ -#if !defined(STM32_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_IRQ_PRIORITY 5 -#endif - -/** - * @brief ADC1 DMA interrupt priority level setting. - */ -#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 -#endif - -/** - * @brief ADC2 DMA interrupt priority level setting. - */ -#if !defined(STM32_ADC_ADC2_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 -#endif - -/** - * @brief ADC3 DMA interrupt priority level setting. - */ -#if !defined(STM32_ADC_ADC3_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 -#endif - -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1 -#error "ADC1 not present in the selected device" -#endif - -#if STM32_ADC_USE_ADC2 && !STM32_HAS_ADC2 -#error "ADC2 not present in the selected device" -#endif - -#if STM32_ADC_USE_ADC3 && !STM32_HAS_ADC3 -#error "ADC3 not present in the selected device" -#endif - -#if !STM32_ADC_USE_ADC1 && !STM32_ADC_USE_ADC2 && !STM32_ADC_USE_ADC3 -#error "ADC driver activated but no ADC peripheral assigned" -#endif - -#if STM32_ADC_USE_ADC1 && \ - !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_MSK) -#error "invalid DMA stream associated to ADC1" -#endif - -#if STM32_ADC_USE_ADC2 && \ - !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC2_DMA_STREAM, STM32_ADC2_DMA_MSK) -#error "invalid DMA stream associated to ADC2" -#endif - -#if STM32_ADC_USE_ADC3 && \ - !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC3_DMA_STREAM, STM32_ADC3_DMA_MSK) -#error "invalid DMA stream associated to ADC3" -#endif - -/* ADC clock related settings and checks.*/ -#if STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV2 -#define STM32_ADCCLK (STM32_PCLK2 / 2) -#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV4 -#define STM32_ADCCLK (STM32_PCLK2 / 4) -#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV6 -#define STM32_ADCCLK (STM32_PCLK2 / 6) -#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV8 -#define STM32_ADCCLK (STM32_PCLK2 / 8) -#else -#error "invalid STM32_ADC_ADCPRE value specified" -#endif - -#if (STM32_ADCCLK < STM32_ADCCLK_MIN) || (STM32_ADCCLK > STM32_ADCCLK_MAX) -#error "STM32_ADCCLK outside acceptable range (STM32_ADCCLK_MIN...STM32_ADCCLK_MAX)" -#endif - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief ADC sample data type. - */ -typedef uint16_t adcsample_t; - -/** - * @brief Channels number in a conversion group. - */ -typedef uint16_t adc_channels_num_t; - -/** - * @brief Possible ADC failure causes. - * @note Error codes are architecture dependent and should not relied - * upon. - */ -typedef enum { - ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */ - ADC_ERR_OVERFLOW = 1 /**< ADC overflow condition. */ -} adcerror_t; - -/** - * @brief Type of a structure representing an ADC driver. - */ -typedef struct ADCDriver ADCDriver; - -/** - * @brief ADC notification callback type. - * - * @param[in] adcp pointer to the @p ADCDriver object triggering the - * callback - * @param[in] buffer pointer to the most recent samples data - * @param[in] n number of buffer rows available starting from @p buffer - */ -typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n); - -/** - * @brief ADC error callback type. - * - * @param[in] adcp pointer to the @p ADCDriver object triggering the - * callback - * @param[in] err ADC error code - */ -typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err); - -/** - * @brief Conversion group configuration structure. - * @details This implementation-dependent structure describes a conversion - * operation. - * @note The use of this configuration structure requires knowledge of - * STM32 ADC cell registers interface, please refer to the STM32 - * reference manual for details. - */ -typedef struct { - /** - * @brief Enables the circular buffer mode for the group. - */ - bool circular; - /** - * @brief Number of the analog channels belonging to the conversion group. - */ - adc_channels_num_t num_channels; - /** - * @brief Callback function associated to the group or @p NULL. - */ - adccallback_t end_cb; - /** - * @brief Error callback or @p NULL. - */ - adcerrorcallback_t error_cb; - /* End of the mandatory fields.*/ - /** - * @brief ADC CR1 register initialization data. - * @note All the required bits must be defined into this field except - * @p ADC_CR1_SCAN that is enforced inside the driver. - */ - uint32_t cr1; - /** - * @brief ADC CR2 register initialization data. - * @note All the required bits must be defined into this field except - * @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are - * enforced inside the driver. - */ - uint32_t cr2; - /** - * @brief ADC SMPR1 register initialization data. - * @details In this field must be specified the sample times for channels - * 10...18. - */ - uint32_t smpr1; - /** - * @brief ADC SMPR2 register initialization data. - * @details In this field must be specified the sample times for channels - * 0...9. - */ - uint32_t smpr2; - /** - * @brief ADC SQR1 register initialization data. - * @details Conversion group sequence 13...16 + sequence length. - */ - uint32_t sqr1; - /** - * @brief ADC SQR2 register initialization data. - * @details Conversion group sequence 7...12. - */ - uint32_t sqr2; - /** - * @brief ADC SQR3 register initialization data. - * @details Conversion group sequence 1...6. - */ - uint32_t sqr3; -} ADCConversionGroup; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - uint32_t dummy; -} ADCConfig; - -/** - * @brief Structure representing an ADC driver. - */ -struct ADCDriver { - /** - * @brief Driver state. - */ - adcstate_t state; - /** - * @brief Current configuration data. - */ - const ADCConfig *config; - /** - * @brief Current samples buffer pointer or @p NULL. - */ - adcsample_t *samples; - /** - * @brief Current samples buffer depth or @p 0. - */ - size_t depth; - /** - * @brief Current conversion group pointer or @p NULL. - */ - const ADCConversionGroup *grpp; -#if ADC_USE_WAIT || defined(__DOXYGEN__) - /** - * @brief Waiting thread. - */ - thread_reference_t thread; -#endif -#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the peripheral. - */ - mutex_t mutex; -#endif /* ADC_USE_MUTUAL_EXCLUSION */ -#if defined(ADC_DRIVER_EXT_FIELDS) - ADC_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the ADCx registers block. - */ - ADC_TypeDef *adc; - /** - * @brief Pointer to associated DMA channel. - */ - const stm32_dma_stream_t *dmastp; - /** - * @brief DMA mode bit mask. - */ - uint32_t dmamode; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Sequences building helper macros - * @{ - */ -/** - * @brief Number of channels in a conversion sequence. - */ -#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 20) - -#define ADC_SQR3_SQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */ -#define ADC_SQR3_SQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */ -#define ADC_SQR3_SQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */ -#define ADC_SQR3_SQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */ -#define ADC_SQR3_SQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */ -#define ADC_SQR3_SQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */ - -#define ADC_SQR2_SQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */ -#define ADC_SQR2_SQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */ -#define ADC_SQR2_SQ9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */ -#define ADC_SQR2_SQ10_N(n) ((n) << 15) /**< @brief 10th channel in seq.*/ -#define ADC_SQR2_SQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/ -#define ADC_SQR2_SQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/ - -#define ADC_SQR1_SQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/ -#define ADC_SQR1_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/ -#define ADC_SQR1_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/ -#define ADC_SQR1_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/ -/** @} */ - -/** - * @name Sampling rate settings helper macros - * @{ - */ -#define ADC_SMPR2_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */ -#define ADC_SMPR2_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */ -#define ADC_SMPR2_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */ -#define ADC_SMPR2_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */ -#define ADC_SMPR2_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */ -#define ADC_SMPR2_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */ -#define ADC_SMPR2_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */ -#define ADC_SMPR2_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */ -#define ADC_SMPR2_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */ -#define ADC_SMPR2_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */ - -#define ADC_SMPR1_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */ -#define ADC_SMPR1_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */ -#define ADC_SMPR1_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */ -#define ADC_SMPR1_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */ -#define ADC_SMPR1_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */ -#define ADC_SMPR1_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */ -#define ADC_SMPR1_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor - sampling time. */ -#define ADC_SMPR1_SMP_VREF(n) ((n) << 21) /**< @brief Voltage Reference - sampling time. */ -#define ADC_SMPR1_SMP_VBAT(n) ((n) << 24) /**< @brief VBAT sampling time. */ -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__) -extern ADCDriver ADCD1; -#endif - -#if STM32_ADC_USE_ADC2 && !defined(__DOXYGEN__) -extern ADCDriver ADCD2; -#endif - -#if STM32_ADC_USE_ADC3 && !defined(__DOXYGEN__) -extern ADCDriver ADCD3; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void adc_lld_init(void); - void adc_lld_start(ADCDriver *adcp); - void adc_lld_stop(ADCDriver *adcp); - void adc_lld_start_conversion(ADCDriver *adcp); - void adc_lld_stop_conversion(ADCDriver *adcp); - void adcSTM32EnableTSVREFE(void); - void adcSTM32DisableTSVREFE(void); - void adcSTM32EnableVBATE(void); - void adcSTM32DisableVBATE(void); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_ADC */ - -#endif /* _ADC_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/ADCv2/notes.txt b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/ADCv2/notes.txt deleted file mode 100644 index 4b79a3467c..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/ADCv2/notes.txt +++ /dev/null @@ -1,13 +0,0 @@ -STM32 ADCv2 driver. - -Driver capability: - -- Supports the STM32 "advanced" ADC found on F2, F4 and F7 sub-families. - -The file registry must export: - -STM32_HAS_ADCx - ADCx presence flag (1..3). -STM32_ADC_HANDLER - IRQ vector name for ADCs (shared). -STM32_ADC_NUMBER - IRQ vector number for ADCs (shared). -STM32_ADCx_DMA_MSK - Mask of the compatible DMA channels. -STM32_ADCx_DMA_CHN - Mask of the channels mapping. diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/ADCv3/adc_lld.c b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/ADCv3/adc_lld.c deleted file mode 100644 index a8e0b27b76..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/ADCv3/adc_lld.c +++ /dev/null @@ -1,959 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/LLD/ADCv3/adc_lld.c - * @brief STM32 ADC subsystem low level driver source. - * - * @addtogroup ADC - * @{ - */ - -#include "hal.h" - -#if HAL_USE_ADC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define ADC1_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_CHN) - -#define ADC2_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_ADC_ADC2_DMA_STREAM, STM32_ADC2_DMA_CHN) - -#define ADC3_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_ADC_ADC3_DMA_STREAM, STM32_ADC3_DMA_CHN) - -#define ADC4_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_ADC_ADC4_DMA_STREAM, STM32_ADC4_DMA_CHN) - -#if STM32_ADC_DUAL_MODE -#if STM32_ADC_COMPACT_SAMPLES -/* Compact type dual mode.*/ -#define ADC_DMA_SIZE (STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD) -#define ADC_DMA_MDMA ADC_CCR_MDMA_HWORD - -#else /* !STM32_ADC_COMPACT_SAMPLES */ -/* Large type dual mode.*/ -#define ADC_DMA_SIZE (STM32_DMA_CR_MSIZE_WORD | STM32_DMA_CR_PSIZE_WORD) -#define ADC_DMA_MDMA ADC_CCR_MDMA_WORD -#endif /* !STM32_ADC_COMPACT_SAMPLES */ - -#else /* !STM32_ADC_DUAL_MODE */ -#if STM32_ADC_COMPACT_SAMPLES -/* Compact type single mode.*/ -#define ADC_DMA_SIZE (STM32_DMA_CR_MSIZE_BYTE | STM32_DMA_CR_PSIZE_BYTE) -#define ADC_DMA_MDMA ADC_CCR_MDMA_DISABLED - -#else /* !STM32_ADC_COMPACT_SAMPLES */ -/* Large type single mode.*/ -#define ADC_DMA_SIZE (STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD) -#define ADC_DMA_MDMA ADC_CCR_MDMA_DISABLED -#endif /* !STM32_ADC_COMPACT_SAMPLES */ -#endif /* !STM32_ADC_DUAL_MODE */ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief ADC1 driver identifier.*/ -#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__) -ADCDriver ADCD1; -#endif - -/** @brief ADC2 driver identifier.*/ -#if STM32_ADC_USE_ADC2 || defined(__DOXYGEN__) -ADCDriver ADCD2; -#endif - -/** @brief ADC3 driver identifier.*/ -#if STM32_ADC_USE_ADC3 || defined(__DOXYGEN__) -ADCDriver ADCD3; -#endif - -/** @brief ADC4 driver identifier.*/ -#if STM32_ADC_USE_ADC4 || defined(__DOXYGEN__) -ADCDriver ADCD4; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -static const ADCConfig default_config = { - difsel: 0 -}; - -static uint32_t clkmask; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Enables the ADC voltage regulator. - * - * @param[in] adcp pointer to the @p ADCDriver object - */ -static void adc_lld_vreg_on(ADCDriver *adcp) { - -#if defined(STM32F3XX) - adcp->adcm->CR = 0; /* RM 12.4.3.*/ - adcp->adcm->CR = ADC_CR_ADVREGEN_0; -#if STM32_ADC_DUAL_MODE - adcp->adcs->CR = ADC_CR_ADVREGEN_0; -#endif - osalSysPolledDelayX(OSAL_US2RTC(STM32_HCLK, 10)); -#endif - -#if defined(STM32L4XX) - adcp->adcm->CR = 0; /* RM 16.3.6.*/ - adcp->adcm->CR = ADC_CR_ADVREGEN; -#if STM32_ADC_DUAL_MODE - adcp->adcs->CR = ADC_CR_ADVREGEN; -#endif - osalSysPolledDelayX(OSAL_US2RTC(STM32_HCLK, 20)); -#endif -} - -/** - * @brief Disables the ADC voltage regulator. - * - * @param[in] adcp pointer to the @p ADCDriver object - */ -static void adc_lld_vreg_off(ADCDriver *adcp) { - -#if defined(STM32F3XX) - adcp->adcm->CR = 0; /* RM 12.4.3.*/ - adcp->adcm->CR = ADC_CR_ADVREGEN_1; -#if STM32_ADC_DUAL_MODE - adcp->adcs->CR = 0; - adcp->adcs->CR = ADC_CR_ADVREGEN_1; -#endif -#endif - -#if defined(STM32L4XX) - adcp->adcm->CR = 0; /* RM 12.4.3.*/ - adcp->adcm->CR = ADC_CR_DEEPPWD; -#if STM32_ADC_DUAL_MODE - adcp->adcs->CR = 0; - adcp->adcs->CR = ADC_CR_DEEPPWD; -#endif -#endif -} - -/** - * @brief Enables the ADC analog circuit. - * - * @param[in] adcp pointer to the @p ADCDriver object - */ -static void adc_lld_analog_on(ADCDriver *adcp) { - -#if defined(STM32F3XX) - adcp->adcm->CR |= ADC_CR_ADEN; - while ((adcp->adcm->ISR & ADC_ISR_ADRD) == 0) - ; -#if STM32_ADC_DUAL_MODE - adcp->adcs->CR |= ADC_CR_ADEN; - while ((adcp->adcs->ISR & ADC_ISR_ADRD) == 0) - ; -#endif -#endif - -#if defined(STM32L4XX) - adcp->adcm->CR |= ADC_CR_ADEN; - while ((adcp->adcm->ISR & ADC_ISR_ADRDY) == 0) - ; -#if STM32_ADC_DUAL_MODE - adcp->adcs->CR |= ADC_CR_ADEN; - while ((adcp->adcs->ISR & ADC_ISR_ADRDY) == 0) - ; -#endif -#endif -} - -/** - * @brief Disables the ADC analog circuit. - * - * @param[in] adcp pointer to the @p ADCDriver object - */ -static void adc_lld_analog_off(ADCDriver *adcp) { - - adcp->adcm->CR |= ADC_CR_ADDIS; - while ((adcp->adcm->CR & ADC_CR_ADDIS) != 0) - ; -#if STM32_ADC_DUAL_MODE - adcp->adcs->CR |= ADC_CR_ADDIS; - while ((adcp->adcs->CR & ADC_CR_ADDIS) != 0) - ; -#endif -} - -/** - * @brief Calibrates and ADC unit. - * - * @param[in] adcp pointer to the @p ADCDriver object - */ -static void adc_lld_calibrate(ADCDriver *adcp) { - -#if defined(STM32F3XX) - osalDbgAssert(adcp->adcm->CR == ADC_CR_ADVREGEN_0, "invalid register state"); - adcp->adcm->CR |= ADC_CR_ADCAL; - while ((adcp->adcm->CR & ADC_CR_ADCAL) != 0) - ; -#if STM32_ADC_DUAL_MODE - osalDbgAssert(adcp->adcs->CR == ADC_CR_ADVREGEN_0, "invalid register state"); - adcp->adcs->CR |= ADC_CR_ADCAL; - while ((adcp->adcs->CR & ADC_CR_ADCAL) != 0) - ; -#endif -#endif - -#if defined(STM32L4XX) - osalDbgAssert(adcp->adcm->CR == ADC_CR_ADVREGEN, "invalid register state"); - adcp->adcm->CR |= ADC_CR_ADCAL; - while ((adcp->adcm->CR & ADC_CR_ADCAL) != 0) - ; -#if STM32_ADC_DUAL_MODE - osalDbgAssert(adcp->adcs->CR == ADC_CR_ADVREGEN, "invalid register state"); - adcp->adcs->CR |= ADC_CR_ADCAL; - while ((adcp->adcs->CR & ADC_CR_ADCAL) != 0) - ; -#endif -#endif -} - -/** - * @brief Stops an ongoing conversion, if any. - * - * @param[in] adcp pointer to the @p ADCDriver object - */ -static void adc_lld_stop_adc(ADCDriver *adcp) { - - if (adcp->adcm->CR & ADC_CR_ADSTART) { - adcp->adcm->CR |= ADC_CR_ADSTP; - while (adcp->adcm->CR & ADC_CR_ADSTP) - ; - } -} - -/** - * @brief ADC DMA ISR service routine. - * - * @param[in] adcp pointer to the @p ADCDriver object - * @param[in] flags pre-shifted content of the ISR register - */ -static void adc_lld_serve_dma_interrupt(ADCDriver *adcp, uint32_t flags) { - - /* DMA errors handling.*/ - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - /* DMA, this could help only if the DMA tries to access an unmapped - address space or violates alignment rules.*/ - _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE); - } - else { - /* It is possible that the conversion group has already be reset by the - ADC error handler, in this case this interrupt is spurious.*/ - if (adcp->grpp != NULL) { - if ((flags & STM32_DMA_ISR_TCIF) != 0) { - /* Transfer complete processing.*/ - _adc_isr_full_code(adcp); - } - else if ((flags & STM32_DMA_ISR_HTIF) != 0) { - /* Half transfer processing.*/ - _adc_isr_half_code(adcp); - } - } - } -} - -/** - * @brief ADC ISR service routine. - * - * @param[in] adcp pointer to the @p ADCDriver object - * @param[in] isr content of the ISR register - */ -static void adc_lld_serve_interrupt(ADCDriver *adcp, uint32_t isr) { - - /* It could be a spurious interrupt caused by overflows after DMA disabling, - just ignore it in this case.*/ - if (adcp->grpp != NULL) { - /* Note, an overflow may occur after the conversion ended before the driver - is able to stop the ADC, this is why the DMA channel is checked too.*/ - if ((isr & ADC_ISR_OVR) && - (dmaStreamGetTransactionSize(adcp->dmastp) > 0)) { - /* ADC overflow condition, this could happen only if the DMA is unable - to read data fast enough.*/ - _adc_isr_error_code(adcp, ADC_ERR_OVERFLOW); - } - if (isr & ADC_ISR_AWD1) { - /* Analog watchdog error.*/ - _adc_isr_error_code(adcp, ADC_ERR_AWD1); - } - if (isr & ADC_ISR_AWD2) { - /* Analog watchdog error.*/ - _adc_isr_error_code(adcp, ADC_ERR_AWD2); - } - if (isr & ADC_ISR_AWD3) { - /* Analog watchdog error.*/ - _adc_isr_error_code(adcp, ADC_ERR_AWD3); - } - } -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2 || defined(__DOXYGEN__) -/** - * @brief ADC1/ADC2 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_ADC1_HANDLER) { - uint32_t isr; - - OSAL_IRQ_PROLOGUE(); - -#if STM32_ADC_DUAL_MODE - isr = ADC1->ISR; - isr |= ADC2->ISR; - ADC1->ISR = isr; - ADC2->ISR = isr; - - adc_lld_serve_interrupt(&ADCD1, isr); -#else /* !STM32_ADC_DUAL_MODE */ -#if STM32_ADC_USE_ADC1 - isr = ADC1->ISR; - ADC1->ISR = isr; - - adc_lld_serve_interrupt(&ADCD1, isr); -#endif -#if STM32_ADC_USE_ADC2 - isr = ADC2->ISR; - ADC2->ISR = isr; - - adc_lld_serve_interrupt(&ADCD2, isr); -#endif -#endif /* !STM32_ADC_DUAL_MODE */ - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_ADC_USE_ADC1 */ - -#if STM32_ADC_USE_ADC3 || defined(__DOXYGEN__) -/** - * @brief ADC3 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_ADC3_HANDLER) { - uint32_t isr; - - OSAL_IRQ_PROLOGUE(); - - isr = ADC3->ISR; - ADC3->ISR = isr; - - adc_lld_serve_interrupt(&ADCD3, isr); - - OSAL_IRQ_EPILOGUE(); -} - -#if STM32_ADC_DUAL_MODE -/** - * @brief ADC4 interrupt handler (as ADC3 slave). - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_ADC4_HANDLER) { - uint32_t isr; - - OSAL_IRQ_PROLOGUE(); - - isr = ADC4->ISR; - ADC4->ISR = isr; - - adc_lld_serve_interrupt(&ADCD3, isr); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_ADC_DUAL_MODE */ -#endif /* STM32_ADC_USE_ADC3 */ - -#if STM32_ADC_USE_ADC4 || defined(__DOXYGEN__) -/** - * @brief ADC4 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_ADC4_HANDLER) { - uint32_t isr; - - OSAL_IRQ_PROLOGUE(); - - isr = ADC4->ISR; - ADC4->ISR = isr; - - adc_lld_serve_interrupt(&ADCD4, isr); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_ADC_USE_ADC4 */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level ADC driver initialization. - * - * @notapi - */ -void adc_lld_init(void) { - - clkmask = 0; - -#if STM32_ADC_USE_ADC1 - /* Driver initialization.*/ - adcObjectInit(&ADCD1); -#if defined(ADC1_2_COMMON) - ADCD1.adcc = ADC1_2_COMMON; -#elif defined(ADC123_COMMON) - ADCD1.adcc = ADC123_COMMON; -#else - ADCD1.adcc = ADC1_COMMON; -#endif - ADCD1.adcm = ADC1; -#if STM32_ADC_DUAL_MODE - ADCD1.adcs = ADC2; -#endif - ADCD1.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC1_DMA_STREAM); - ADCD1.dmamode = ADC_DMA_SIZE | - STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; -#endif /* STM32_ADC_USE_ADC1 */ - -#if STM32_ADC_USE_ADC2 - /* Driver initialization.*/ - adcObjectInit(&ADCD2); -#if defined(ADC1_2_COMMON) - ADCD2.adcc = ADC1_2_COMMON; -#elif defined(ADC123_COMMON) - ADCD2.adcc = ADC123_COMMON; -#endif - ADCD2.adcm = ADC2; - ADCD2.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC2_DMA_STREAM); - ADCD2.dmamode = ADC_DMA_SIZE | - STM32_DMA_CR_PL(STM32_ADC_ADC2_DMA_PRIORITY) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; -#endif /* STM32_ADC_USE_ADC2 */ - -#if STM32_ADC_USE_ADC3 - /* Driver initialization.*/ - adcObjectInit(&ADCD3); -#if defined(ADC3_4_COMMON) - ADCD3.adcc = ADC3_4_COMMON; -#elif defined(ADC123_COMMON) - ADCD1.adcc = ADC123_COMMON; -#else - ADCD3.adcc = ADC3_COMMON; -#endif - ADCD3.adcm = ADC3; -#if STM32_ADC_DUAL_MODE - ADCD3.adcs = ADC4; -#endif - ADCD3.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC3_DMA_STREAM); - ADCD3.dmamode = ADC_DMA_SIZE | - STM32_DMA_CR_PL(STM32_ADC_ADC3_DMA_PRIORITY) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; -#endif /* STM32_ADC_USE_ADC3 */ - -#if STM32_ADC_USE_ADC4 - /* Driver initialization.*/ - adcObjectInit(&ADCD4); - ADCD4.adcc = ADC3_4_COMMON; - ADCD4.adcm = ADC4; - ADCD4.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC4_DMA_STREAM); - ADCD4.dmamode = ADC_DMA_SIZE | - STM32_DMA_CR_PL(STM32_ADC_ADC4_DMA_PRIORITY) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; -#endif /* STM32_ADC_USE_ADC4 */ - - /* IRQs setup.*/ -#if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2 - nvicEnableVector(STM32_ADC1_NUMBER, STM32_ADC_ADC12_IRQ_PRIORITY); -#endif -#if STM32_ADC_USE_ADC3 - nvicEnableVector(STM32_ADC3_NUMBER, STM32_ADC_ADC3_IRQ_PRIORITY); -#if STM32_ADC_DUAL_MODE - nvicEnableVector(STM32_ADC4_NUMBER, STM32_ADC_ADC3_IRQ_PRIORITY); -#endif -#endif -#if STM32_ADC_USE_ADC4 - nvicEnableVector(STM32_ADC4_NUMBER, STM32_ADC_ADC3_IRQ_PRIORITY); -#endif - - /* ADC units pre-initializations.*/ -#if defined(STM32F3XX) -#if STM32_HAS_ADC1 && STM32_HAS_ADC2 -#if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2 - rccEnableADC12(FALSE); - rccResetADC12(); - ADC1_2_COMMON->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA; - rccDisableADC12(FALSE); -#endif -#else -#if STM32_ADC_USE_ADC1 - rccEnableADC12(FALSE); - rccResetADC12(); - ADC1_COMMON->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA; - rccDisableADC12(FALSE); -#endif -#endif -#if STM32_ADC_USE_ADC3 || STM32_ADC_USE_ADC4 - rccEnableADC34(FALSE); - rccResetADC34(); - ADC3_4_COMMON->CCR = STM32_ADC_ADC34_CLOCK_MODE | ADC_DMA_MDMA; - rccDisableADC34(FALSE); -#endif -#endif - -#if defined(STM32L4XX) - rccEnableADC123(FALSE); - rccResetADC123(); - -#if defined(ADC1_2_COMMON) - ADC1_2_COMMON->CCR = STM32_ADC_ADC123_CLOCK_MODE | ADC_DMA_MDMA; -#elif defined(ADC123_COMMON) - ADC123_COMMON->CCR = STM32_ADC_ADC123_CLOCK_MODE | ADC_DMA_MDMA; -#else - ADC1_COMMON->CCR = STM32_ADC_ADC123_CLOCK_MODE | ADC_DMA_MDMA; -#endif - rccDisableADC123(FALSE); -#endif -} - -/** - * @brief Configures and activates the ADC peripheral. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_start(ADCDriver *adcp) { - - /* Handling the default configuration.*/ - if (adcp->config == NULL) { - adcp->config = &default_config; - } - - /* If in stopped state then enables the ADC and DMA clocks.*/ - if (adcp->state == ADC_STOP) { -#if STM32_ADC_USE_ADC1 - if (&ADCD1 == adcp) { - bool b; - b = dmaStreamAllocate(adcp->dmastp, - STM32_ADC_ADC1_DMA_IRQ_PRIORITY, - (stm32_dmaisr_t)adc_lld_serve_dma_interrupt, - (void *)adcp); - osalDbgAssert(!b, "stream already allocated"); - - clkmask |= (1 << 0); -#if defined(STM32F3XX) - rccEnableADC12(FALSE); -#endif -#if defined(STM32L4XX) - rccEnableADC123(FALSE); -#endif - } -#endif /* STM32_ADC_USE_ADC1 */ - -#if STM32_ADC_USE_ADC2 - if (&ADCD2 == adcp) { - bool b; - b = dmaStreamAllocate(adcp->dmastp, - STM32_ADC_ADC2_DMA_IRQ_PRIORITY, - (stm32_dmaisr_t)adc_lld_serve_dma_interrupt, - (void *)adcp); - osalDbgAssert(!b, "stream already allocated"); - - clkmask |= (1 << 1); -#if defined(STM32F3XX) - rccEnableADC12(FALSE); -#endif -#if defined(STM32L4XX) - rccEnableADC123(FALSE); -#endif - } -#endif /* STM32_ADC_USE_ADC2 */ - -#if STM32_ADC_USE_ADC3 - if (&ADCD3 == adcp) { - bool b; - b = dmaStreamAllocate(adcp->dmastp, - STM32_ADC_ADC3_DMA_IRQ_PRIORITY, - (stm32_dmaisr_t)adc_lld_serve_dma_interrupt, - (void *)adcp); - osalDbgAssert(!b, "stream already allocated"); - - clkmask |= (1 << 2); -#if defined(STM32F3XX) - rccEnableADC34(FALSE); -#endif -#if defined(STM32L4XX) - rccEnableADC123(FALSE); -#endif - } -#endif /* STM32_ADC_USE_ADC3 */ - -#if STM32_ADC_USE_ADC4 - if (&ADCD4 == adcp) { - bool b; - b = dmaStreamAllocate(adcp->dmastp, - STM32_ADC_ADC4_DMA_IRQ_PRIORITY, - (stm32_dmaisr_t)adc_lld_serve_dma_interrupt, - (void *)adcp); - osalDbgAssert(!b, "stream already allocated"); - - clkmask |= (1 << 3); -#if defined(STM32F3XX) - rccEnableADC34(FALSE); -#endif -#if defined(STM32L4XX) - rccEnableADC123(FALSE); -#endif - } -#endif /* STM32_ADC_USE_ADC4 */ - - /* Setting DMA peripheral-side pointer.*/ -#if STM32_ADC_DUAL_MODE - dmaStreamSetPeripheral(adcp->dmastp, &adcp->adcc->CDR); -#else - dmaStreamSetPeripheral(adcp->dmastp, &adcp->adcm->DR); -#endif - - /* Differential channels setting.*/ -#if STM32_ADC_DUAL_MODE - adcp->adcm->DIFSEL = adcp->config->difsel; - adcp->adcs->DIFSEL = adcp->config->difsel; -#else - adcp->adcm->DIFSEL = adcp->config->difsel; -#endif - - /* Master ADC calibration.*/ - adc_lld_vreg_on(adcp); - adc_lld_calibrate(adcp); - - /* Master ADC enabled here in order to reduce conversions latencies.*/ - adc_lld_analog_on(adcp); - } -} - -/** - * @brief Deactivates the ADC peripheral. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_stop(ADCDriver *adcp) { - - /* If in ready state then disables the ADC clock and analog part.*/ - if (adcp->state == ADC_READY) { - - /* Releasing the associated DMA channel.*/ - dmaStreamRelease(adcp->dmastp); - - /* Stopping the ongoing conversion, if any.*/ - adc_lld_stop_adc(adcp); - - /* Disabling ADC analog circuit and regulator.*/ - adc_lld_analog_off(adcp); - adc_lld_vreg_off(adcp); - -#if defined(STM32L4XX) - /* Resetting CCR options except default ones.*/ - adcp->adcc->CCR = STM32_ADC_ADC123_CLOCK_MODE | ADC_DMA_MDMA; -#endif - -#if STM32_ADC_USE_ADC1 - if (&ADCD1 == adcp) { -#if defined(STM32F3XX) - /* Resetting CCR options except default ones.*/ - adcp->adcc->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA; -#endif - clkmask &= ~(1 << 0); - } -#endif - -#if STM32_ADC_USE_ADC2 - if (&ADCD2 == adcp) { -#if defined(STM32F3XX) - /* Resetting CCR options except default ones.*/ - adcp->adcc->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA; -#endif - clkmask &= ~(1 << 1); - } -#endif - -#if STM32_ADC_USE_ADC3 - if (&ADCD3 == adcp) { -#if defined(STM32F3XX) - /* Resetting CCR options except default ones.*/ - adcp->adcc->CCR = STM32_ADC_ADC34_CLOCK_MODE | ADC_DMA_MDMA; -#endif - clkmask &= ~(1 << 2); - } -#endif - -#if STM32_ADC_USE_ADC4 - if (&ADCD4 == adcp) { -#if defined(STM32F3XX) - /* Resetting CCR options except default ones.*/ - adcp->adcc->CCR = STM32_ADC_ADC34_CLOCK_MODE | ADC_DMA_MDMA; -#endif - clkmask &= ~(1 << 3); - } -#endif - -#if defined(STM32F3XX) -#if STM32_HAS_ADC1 || STM32_HAS_ADC2 - if ((clkmask & 0x3) == 0) { - rccDisableADC12(FALSE); - } -#endif - -#if STM32_HAS_ADC3 || STM32_HAS_ADC4 - if ((clkmask & 0xC) == 0) { - rccDisableADC34(FALSE); - } -#endif -#endif - -#if defined(STM32L4XX) - if ((clkmask & 0x7) == 0) { - rccDisableADC123(FALSE); - } -#endif - } -} - -/** - * @brief Starts an ADC conversion. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_start_conversion(ADCDriver *adcp) { - uint32_t dmamode, cfgr; - const ADCConversionGroup *grpp = adcp->grpp; -#if STM32_ADC_DUAL_MODE - uint32_t ccr = grpp->ccr & ~(ADC_CCR_CKMODE_MASK | ADC_CCR_MDMA_MASK); -#endif - - osalDbgAssert(!STM32_ADC_DUAL_MODE || ((grpp->num_channels & 1) == 0), - "odd number of channels in dual mode"); - - /* Calculating control registers values.*/ - dmamode = adcp->dmamode; - cfgr = grpp->cfgr | ADC_CFGR_DMAEN; - if (grpp->circular) { - dmamode |= STM32_DMA_CR_CIRC; -#if STM32_ADC_DUAL_MODE - ccr |= ADC_CCR_DMACFG_CIRCULAR; -#else - cfgr |= ADC_CFGR_DMACFG_CIRCULAR; -#endif - if (adcp->depth > 1) { - /* If circular buffer depth > 1, then the half transfer interrupt - is enabled in order to allow streaming processing.*/ - dmamode |= STM32_DMA_CR_HTIE; - } - } - - /* DMA setup.*/ - dmaStreamSetMemory0(adcp->dmastp, adcp->samples); -#if STM32_ADC_DUAL_MODE - dmaStreamSetTransactionSize(adcp->dmastp, ((uint32_t)grpp->num_channels/2) * - (uint32_t)adcp->depth); -#else - dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels * - (uint32_t)adcp->depth); -#endif - dmaStreamSetMode(adcp->dmastp, dmamode); - dmaStreamEnable(adcp->dmastp); - - /* ADC setup, if it is defined a callback for the analog watch dog then it - is enabled.*/ - adcp->adcm->ISR = adcp->adcm->ISR; - adcp->adcm->IER = ADC_IER_OVR | ADC_IER_AWD1; - adcp->adcm->TR1 = grpp->tr1; -#if STM32_ADC_DUAL_MODE - - /* Configuring the CCR register with the user-specified settings - in the conversion group configuration structure, static settings are - preserved.*/ - adcp->adcc->CCR = (adcp->adcc->CCR & - (ADC_CCR_CKMODE_MASK | ADC_CCR_MDMA_MASK)) | ccr; - - adcp->adcm->SMPR1 = grpp->smpr[0]; - adcp->adcm->SMPR2 = grpp->smpr[1]; - adcp->adcm->SQR1 = grpp->sqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels / 2); - adcp->adcm->SQR2 = grpp->sqr[1]; - adcp->adcm->SQR3 = grpp->sqr[2]; - adcp->adcm->SQR4 = grpp->sqr[3]; - adcp->adcs->SMPR1 = grpp->ssmpr[0]; - adcp->adcs->SMPR2 = grpp->ssmpr[1]; - adcp->adcs->SQR1 = grpp->ssqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels / 2); - adcp->adcs->SQR2 = grpp->ssqr[1]; - adcp->adcs->SQR3 = grpp->ssqr[2]; - adcp->adcs->SQR4 = grpp->ssqr[3]; - -#else /* !STM32_ADC_DUAL_MODE */ - adcp->adcm->SMPR1 = grpp->smpr[0]; - adcp->adcm->SMPR2 = grpp->smpr[1]; - adcp->adcm->SQR1 = grpp->sqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels); - adcp->adcm->SQR2 = grpp->sqr[1]; - adcp->adcm->SQR3 = grpp->sqr[2]; - adcp->adcm->SQR4 = grpp->sqr[3]; -#endif /* !STM32_ADC_DUAL_MODE */ - - /* ADC configuration.*/ - adcp->adcm->CFGR = cfgr; - - /* Starting conversion.*/ - adcp->adcm->CR |= ADC_CR_ADSTART; -} - -/** - * @brief Stops an ongoing conversion. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_stop_conversion(ADCDriver *adcp) { - - dmaStreamDisable(adcp->dmastp); - adc_lld_stop_adc(adcp); -} - -/** - * @brief Enables the VREFEN bit. - * @details The VREFEN bit is required in order to sample the VREF channel. - * @note This is an STM32-only functionality. - * @note This function is meant to be called after @p adcStart(). - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adcSTM32EnableVREF(ADCDriver *adcp) { - - adcp->adcc->CCR |= ADC_CCR_VREFEN; -} - -/** - * @brief Disables the VREFEN bit. - * @details The VREFEN bit is required in order to sample the VREF channel. - * @note This is an STM32-only functionality. - * @note This function is meant to be called after @p adcStart(). - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adcSTM32DisableVREF(ADCDriver *adcp) { - - adcp->adcc->CCR &= ~ADC_CCR_VREFEN; -} - -/** - * @brief Enables the TSEN bit. - * @details The TSEN bit is required in order to sample the internal - * temperature sensor and internal reference voltage. - * @note This is an STM32-only functionality. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adcSTM32EnableTS(ADCDriver *adcp) { - - adcp->adcc->CCR |= ADC_CCR_TSEN; -} - -/** - * @brief Disables the TSEN bit. - * @details The TSEN bit is required in order to sample the internal - * temperature sensor and internal reference voltage. - * @note This is an STM32-only functionality. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adcSTM32DisableTS(ADCDriver *adcp) { - - adcp->adcc->CCR &= ~ADC_CCR_TSEN; -} - -/** - * @brief Enables the VBATEN bit. - * @details The VBATEN bit is required in order to sample the VBAT channel. - * @note This is an STM32-only functionality. - * @note This function is meant to be called after @p adcStart(). - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adcSTM32EnableVBAT(ADCDriver *adcp) { - - adcp->adcc->CCR |= ADC_CCR_VBATEN; -} - -/** - * @brief Disables the VBATEN bit. - * @details The VBATEN bit is required in order to sample the VBAT channel. - * @note This is an STM32-only functionality. - * @note This function is meant to be called after @p adcStart(). - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adcSTM32DisableVBAT(ADCDriver *adcp) { - - adcp->adcc->CCR &= ~ADC_CCR_VBATEN; -} - -#endif /* HAL_USE_ADC */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/ADCv3/adc_lld.h b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/ADCv3/adc_lld.h deleted file mode 100644 index ee93100f91..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/ADCv3/adc_lld.h +++ /dev/null @@ -1,890 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/LLD/ADCv3/adc_lld.h - * @brief STM32 ADC subsystem low level driver header. - * - * @addtogroup ADC - * @{ - */ - -#ifndef _ADC_LLD_H_ -#define _ADC_LLD_H_ - -#if HAL_USE_ADC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name Available analog channels - * @{ - */ -#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */ -#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */ -#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */ -#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */ -#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */ -#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */ -#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */ -#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */ -#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */ -#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */ -#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */ -#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */ -#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */ -#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */ -#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */ -#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */ -#define ADC_CHANNEL_IN16 16 /**< @brief External analog input 16. */ -#define ADC_CHANNEL_IN17 17 /**< @brief External analog input 17. */ -#define ADC_CHANNEL_IN18 18 /**< @brief External analog input 18. */ -/** @} */ - -/** - * @name Sampling rates - * @{ - */ -#if defined(STM32F3XX) -#define ADC_SMPR_SMP_1P5 0 /**< @brief 14 cycles conversion time */ -#define ADC_SMPR_SMP_2P5 1 /**< @brief 15 cycles conversion time. */ -#define ADC_SMPR_SMP_4P5 2 /**< @brief 17 cycles conversion time. */ -#define ADC_SMPR_SMP_7P5 3 /**< @brief 20 cycles conversion time. */ -#define ADC_SMPR_SMP_19P5 4 /**< @brief 32 cycles conversion time. */ -#define ADC_SMPR_SMP_61P5 5 /**< @brief 74 cycles conversion time. */ -#define ADC_SMPR_SMP_181P5 6 /**< @brief 194 cycles conversion time. */ -#define ADC_SMPR_SMP_601P5 7 /**< @brief 614 cycles conversion time. */ -#endif -#if defined(STM32L4XX) -#define ADC_SMPR_SMP_2P5 0 /**< @brief 15 cycles conversion time */ -#define ADC_SMPR_SMP_6P5 1 /**< @brief 19 cycles conversion time. */ -#define ADC_SMPR_SMP_12P5 2 /**< @brief 25 cycles conversion time. */ -#define ADC_SMPR_SMP_24P5 3 /**< @brief 37 cycles conversion time. */ -#define ADC_SMPR_SMP_47P5 4 /**< @brief 60 cycles conversion time. */ -#define ADC_SMPR_SMP_92P5 5 /**< @brief 105 cycles conversion time. */ -#define ADC_SMPR_SMP_247P5 6 /**< @brief 260 cycles conversion time. */ -#define ADC_SMPR_SMP_640P5 7 /**< @brief 653 cycles conversion time. */ -#endif -/** @} */ - -/** - * @name Resolution - * @{ - */ -#define ADC_CFGR1_RES_12BIT (0 << 3) -#define ADC_CFGR1_RES_10BIT (1 << 3) -#define ADC_CFGR1_RES_8BIT (2 << 3) -#define ADC_CFGR1_RES_6BIT (3 << 3) -/** @} */ - -/** - * @name CFGR register configuration helpers - * @{ - */ -#define ADC_CFGR_DMACFG_MASK (1 << 1) -#define ADC_CFGR_DMACFG_ONESHOT (0 << 1) -#define ADC_CFGR_DMACFG_CIRCULAR (1 << 1) - -#define ADC_CFGR_RES_MASK (3 << 3) -#define ADC_CFGR_RES_12BITS (0 << 3) -#define ADC_CFGR_RES_10BITS (1 << 3) -#define ADC_CFGR_RES_8BITS (2 << 3) -#define ADC_CFGR_RES_6BITS (3 << 3) - -#define ADC_CFGR_ALIGN_MASK (1 << 5) -#define ADC_CFGR_ALIGN_RIGHT (0 << 5) -#define ADC_CFGR_ALIGN_LEFT (1 << 5) - -#define ADC_CFGR_EXTSEL_MASK (15 << 6) -#define ADC_CFGR_EXTSEL_SRC(n) ((n) << 6) - -#define ADC_CFGR_EXTEN_MASK (3 << 10) -#define ADC_CFGR_EXTEN_DISABLED (0 << 10) -#define ADC_CFGR_EXTEN_RISING (1 << 10) -#define ADC_CFGR_EXTEN_FALLING (2 << 10) -#define ADC_CFGR_EXTEN_BOTH (3 << 10) - -#define ADC_CFGR_DISCEN_MASK (1 << 16) -#define ADC_CFGR_DISCEN_DISABLED (0 << 16) -#define ADC_CFGR_DISCEN_ENABLED (1 << 16) - -#define ADC_CFGR_DISCNUM_MASK (7 << 17) -#define ADC_CFGR_DISCNUM_VAL(n) ((n) << 17) - -#define ADC_CFGR_AWD1_DISABLED 0 -#define ADC_CFGR_AWD1_ALL (1 << 23) -#define ADC_CFGR_AWD1_SINGLE(n) (((n) << 26) | (1 << 23) | (1 << 22)) -/** @} */ - -/** - * @name CCR register configuration helpers - * @{ - */ -#define ADC_CCR_DUAL_MASK (31 << 0) -#define ADC_CCR_DUAL_FIELD(n) ((n) << 0) -#define ADC_CCR_DELAY_MASK (15 << 8) -#define ADC_CCR_DELAY_FIELD(n) ((n) << 8) -#define ADC_CCR_DMACFG_MASK (1 << 13) -#define ADC_CCR_DMACFG_ONESHOT (0 << 13) -#define ADC_CCR_DMACFG_CIRCULAR (1 << 13) -#define ADC_CCR_MDMA_MASK (3 << 14) -#define ADC_CCR_MDMA_DISABLED (0 << 14) -#define ADC_CCR_MDMA_WORD (2 << 14) -#define ADC_CCR_MDMA_HWORD (3 << 14) -#define ADC_CCR_CKMODE_MASK (3 << 16) -#define ADC_CCR_CKMODE_ADCCK (0 << 16) -#define ADC_CCR_CKMODE_AHB_DIV1 (1 << 16) -#define ADC_CCR_CKMODE_AHB_DIV2 (2 << 16) -#define ADC_CCR_CKMODE_AHB_DIV4 (3 << 16) - -/* F3 headers do not define the following macros, L4 headers do.*/ -#if !defined(ADC_CCR_VREFEN) || defined(__DOXYGEN__) -#define ADC_CCR_VREFEN (1 << 22) -#endif - -#if !defined(ADC_CCR_TSEN) || defined(__DOXYGEN__) -#define ADC_CCR_TSEN (1 << 23) -#endif - -#if !defined(ADC_CCR_VBATEN) || defined(__DOXYGEN__) -#define ADC_CCR_VBATEN (1 << 24) -#endif -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief Enables the ADC master/slave mode. - * @note In dual mode only ADCD1 and ADCD3 are available. - */ -#if !defined(STM32_ADC_DUAL_MODE) || defined(__DOXYGEN__) -#define STM32_ADC_DUAL_MODE FALSE -#endif - -/** - * @brief Makes the ADC samples type an 8bits one. - * @note 10 and 12 bits sampling mode must not be used when this option - * is enabled. - */ -#if !defined(STM32_ADC_COMPACT_SAMPLES) || defined(__DOXYGEN__) -#define STM32_ADC_COMPACT_SAMPLES FALSE -#endif - -/** - * @brief ADC1 driver enable switch. - * @details If set to @p TRUE the support for ADC1 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__) -#define STM32_ADC_USE_ADC1 FALSE -#endif - -/** - * @brief ADC2 driver enable switch. - * @details If set to @p TRUE the support for ADC2 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_ADC_USE_ADC2) || defined(__DOXYGEN__) -#define STM32_ADC_USE_ADC2 FALSE -#endif - -/** - * @brief ADC3 driver enable switch. - * @details If set to @p TRUE the support for ADC3 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_ADC_USE_ADC3) || defined(__DOXYGEN__) -#define STM32_ADC_USE_ADC3 FALSE -#endif -/** - * @brief ADC4 driver enable switch. - * @details If set to @p TRUE the support for ADC4 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_ADC_USE_ADC4) || defined(__DOXYGEN__) -#define STM32_ADC_USE_ADC4 FALSE -#endif - -/** - * @brief ADC1 DMA priority (0..3|lowest..highest). - */ -#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#endif - -/** - * @brief ADC2 DMA priority (0..3|lowest..highest). - */ -#if !defined(STM32_ADC_ADC2_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_ADC2_DMA_PRIORITY 2 -#endif - -/** - * @brief ADC3 DMA priority (0..3|lowest..highest). - */ -#if !defined(STM32_ADC_ADC3_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_ADC3_DMA_PRIORITY 2 -#endif - -/** - * @brief ADC4 DMA priority (0..3|lowest..highest). - */ -#if !defined(STM32_ADC_ADC4_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_ADC4_DMA_PRIORITY 2 -#endif - -/** - * @brief ADC1/ADC2 interrupt priority level setting. - */ -#if !defined(STM32_ADC_ADC12_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_ADC12_IRQ_PRIORITY 5 -#endif - -/** - * @brief ADC3 interrupt priority level setting. - */ -#if !defined(STM32_ADC3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_ADC3_IRQ_PRIORITY 5 -#endif - -/** - * @brief ADC4 interrupt priority level setting. - */ -#if !defined(STM32_ADC4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_ADC4_IRQ_PRIORITY 5 -#endif - -/** - * @brief ADC1 DMA interrupt priority level setting. - */ -#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 -#endif - -/** - * @brief ADC2 DMA interrupt priority level setting. - */ -#if !defined(STM32_ADC_ADC2_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 -#endif - -/** - * @brief ADC3 DMA interrupt priority level setting. - */ -#if !defined(STM32_ADC_ADC3_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 -#endif - -/** - * @brief ADC4 DMA interrupt priority level setting. - */ -#if !defined(STM32_ADC_ADC4_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5 -#endif - -#if defined(STM32F3XX) || defined(__DOXYGEN__) -/** - * @brief ADC1/ADC2 clock source and mode. - */ -#if !defined(STM32_ADC_ADC12_CLOCK_MODE) || defined(__DOXYGEN__) -#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 -#endif - -/** - * @brief ADC3/ADC4 clock source and mode. - */ -#if !defined(STM32_ADC_ADC34_CLOCK_MODE) || defined(__DOXYGEN__) -#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 -#endif -#endif /* defined(STM32F3XX) */ - -#if defined(STM32L4XX) || defined(__DOXYGEN__) -/** - * @brief ADC1/ADC2/ADC3 clock source and mode. - */ -#if !defined(STM32_ADC_ADC123_CLOCK_MODE) || defined(__DOXYGEN__) -#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 -#endif -#endif /* defined(STM32L4XX) */ - -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/* Supported devices checks.*/ -#if !defined(STM32F3XX) && !defined(STM32L4XX) -#error "ADCv3 only supports F3 and L4 STM32 devices" -#endif - -/* Registry checks.*/ -#if !defined(STM32_HAS_ADC1) || !defined(STM32_HAS_ADC2) || \ - !defined(STM32_HAS_ADC3) || !defined(STM32_HAS_ADC4) -#error "STM32_ADC_USE_ADCx not defined in registry" -#endif - -#if (STM32_ADC_USE_ADC1 && !defined(STM32_ADC1_HANDLER)) || \ - (STM32_ADC_USE_ADC2 && !defined(STM32_ADC2_HANDLER)) || \ - (STM32_ADC_USE_ADC3 && !defined(STM32_ADC3_HANDLER)) || \ - (STM32_ADC_USE_ADC4 && !defined(STM32_ADC4_HANDLER)) -#error "STM32_ADCx_HANDLER not defined in registry" -#endif - -#if (STM32_ADC_USE_ADC1 && !defined(STM32_ADC1_NUMBER)) || \ - (STM32_ADC_USE_ADC2 && !defined(STM32_ADC2_NUMBER)) || \ - (STM32_ADC_USE_ADC3 && !defined(STM32_ADC3_NUMBER)) || \ - (STM32_ADC_USE_ADC4 && !defined(STM32_ADC4_NUMBER)) -#error "STM32_ADCx_NUMBER not defined in registry" -#endif - -#if (STM32_ADC_USE_ADC1 && !defined(STM32_ADC1_DMA_MSK)) || \ - (STM32_ADC_USE_ADC2 && !defined(STM32_ADC2_DMA_MSK)) || \ - (STM32_ADC_USE_ADC3 && !defined(STM32_ADC3_DMA_MSK)) || \ - (STM32_ADC_USE_ADC4 && !defined(STM32_ADC4_DMA_MSK)) -#error "STM32_ADCx_DMA_MSK not defined in registry" -#endif - -#if (STM32_ADC_USE_ADC1 && !defined(STM32_ADC1_DMA_CHN)) || \ - (STM32_ADC_USE_ADC2 && !defined(STM32_ADC2_DMA_CHN)) || \ - (STM32_ADC_USE_ADC3 && !defined(STM32_ADC3_DMA_CHN)) || \ - (STM32_ADC_USE_ADC4 && !defined(STM32_ADC4_DMA_CHN)) -#error "STM32_ADCx_DMA_CHN not defined in registry" -#endif - -/* Units checks.*/ -#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1 -#error "ADC1 not present in the selected device" -#endif - -#if STM32_ADC_USE_ADC2 && !STM32_HAS_ADC2 -#error "ADC2 not present in the selected device" -#endif - -#if STM32_ADC_USE_ADC3 && !STM32_HAS_ADC3 -#error "ADC3 not present in the selected device" -#endif - -#if STM32_ADC_USE_ADC4 && !STM32_HAS_ADC4 -#error "ADC4 not present in the selected device" -#endif - -/* Units checks related to dual mode.*/ -#if STM32_ADC_DUAL_MODE && STM32_ADC_USE_ADC1 && !STM32_HAS_ADC2 -#error "ADC2 not present in the selected device, required for dual mode" -#endif - -#if STM32_ADC_DUAL_MODE && STM32_ADC_USE_ADC3 && !STM32_HAS_ADC4 -#error "ADC4 not present in the selected device, required for dual mode" -#endif - -#if STM32_ADC_DUAL_MODE && STM32_ADC_USE_ADC2 -#error "ADC2 cannot be used in dual mode" -#endif - -#if STM32_ADC_DUAL_MODE && STM32_ADC_USE_ADC4 -#error "ADC4 cannot be used in dual mode" -#endif - -/* At least one ADC must be assigned.*/ -#if !STM32_ADC_USE_ADC1 && !STM32_ADC_USE_ADC2 && \ - !STM32_ADC_USE_ADC3 && !STM32_ADC_USE_ADC4 -#error "ADC driver activated but no ADC peripheral assigned" -#endif - -/* ISR arrangments checks.*/ -#if STM32_HAS_ADC1 && STM32_HAS_ADC2 -#if STM32_ADC1_NUMBER != STM32_ADC2_NUMBER -#error "ADCv3 driver expects STM32_ADC1_NUMBER == STM32_ADC2_NUMBER from registry" -#endif -#endif - -/* ADC IRQ priority tests.*/ -#if STM32_ADC_USE_ADC1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC12_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to ADC1" -#endif - -/* ADC IRQ priority tests.*/ -#if STM32_ADC_USE_ADC2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC12_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to ADC2" -#endif - -#if STM32_ADC_USE_ADC3 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to ADC3" -#endif - -#if STM32_ADC_USE_ADC4 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC4_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to ADC4" -#endif - -/* DMA IRQ priority tests.*/ -#if STM32_ADC_USE_ADC1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to ADC1 DMA" -#endif - -#if STM32_ADC_USE_ADC2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC2_DMA_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to ADC2 DMA" -#endif - -#if STM32_ADC_USE_ADC3 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC3_DMA_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to ADC3 DMA" -#endif - -#if STM32_ADC_USE_ADC4 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC4_DMA_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to ADC4 DMA" -#endif - -/* DMA priority tests.*/ -#if STM32_ADC_USE_ADC1 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_PRIORITY) -#error "Invalid DMA priority assigned to ADC1" -#endif - -#if STM32_ADC_USE_ADC2 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC2_DMA_PRIORITY) -#error "Invalid DMA priority assigned to ADC2" -#endif - -#if STM32_ADC_USE_ADC3 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC3_DMA_PRIORITY) -#error "Invalid DMA priority assigned to ADC3" -#endif - -#if STM32_ADC_USE_ADC4 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC4_DMA_PRIORITY) -#error "Invalid DMA priority assigned to ADC4" -#endif - -/* Check on the presence of the DMA streams settings in mcuconf.h.*/ -#if STM32_ADC_USE_ADC1 && !defined(STM32_ADC_ADC1_DMA_STREAM) -#error "ADC1 DMA stream not defined" -#endif - -#if STM32_ADC_USE_ADC2 && !defined(STM32_ADC_ADC2_DMA_STREAM) -#error "ADC2 DMA stream not defined" -#endif - -#if STM32_ADC_USE_ADC3 && !defined(STM32_ADC_ADC3_DMA_STREAM) -#error "ADC3 DMA stream not defined" -#endif - -#if STM32_ADC_USE_ADC4 && !defined(STM32_ADC_ADC4_DMA_STREAM) -#error "ADC4 DMA stream not defined" -#endif - -/* Check on the validity of the assigned DMA channels.*/ -#if STM32_ADC_USE_ADC1 && \ - !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_MSK) -#error "invalid DMA stream associated to ADC1" -#endif - -#if STM32_ADC_USE_ADC2 && \ - !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC2_DMA_STREAM, STM32_ADC2_DMA_MSK) -#error "invalid DMA stream associated to ADC2" -#endif - -#if STM32_ADC_USE_ADC3 && \ - !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC3_DMA_STREAM, STM32_ADC3_DMA_MSK) -#error "invalid DMA stream associated to ADC3" -#endif - -#if STM32_ADC_USE_ADC4 && \ - !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC4_DMA_STREAM, STM32_ADC4_DMA_MSK) -#error "invalid DMA stream associated to ADC4" -#endif - -/* ADC clock source checks.*/ -#if defined(STM32F3XX) -#if STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK -#define STM32_ADC12_CLOCK STM32_ADC12CLK -#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1 -#define STM32_ADC12_CLOCK (STM32_HCLK / 1) -#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2 -#define STM32_ADC12_CLOCK (STM32_HCLK / 2) -#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4 -#define STM32_ADC12_CLOCK (STM32_HCLK / 4) -#else -#error "invalid clock mode selected for STM32_ADC_ADC12_CLOCK_MODE" -#endif - -#if STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK -#define STM32_ADC34_CLOCK STM32_ADC34CLK -#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1 -#define STM32_ADC34_CLOCK (STM32_HCLK / 1) -#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2 -#define STM32_ADC34_CLOCK (STM32_HCLK / 2) -#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4 -#define STM32_ADC34_CLOCK (STM32_HCLK / 4) -#else -#error "invalid clock mode selected for STM32_ADC_ADC12_CLOCK_MODE" -#endif - -#if STM32_ADC12_CLOCK > STM32_ADCCLK_MAX -#error "STM32_ADC12_CLOCK exceeding maximum frequency (STM32_ADCCLK_MAX)" -#endif - -#if STM32_ADC34_CLOCK > STM32_ADCCLK_MAX -#error "STM32_ADC34_CLOCK exceeding maximum frequency (STM32_ADCCLK_MAX)" -#endif -#endif /* defined(STM32F3XX) */ - -#if defined(STM32L4XX) -#if STM32_ADC_ADC123_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK -#define STM32_ADC123_CLOCK STM32_ADC12CLK -#elif STM32_ADC_ADC123_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1 -#define STM32_ADC123_CLOCK (STM32_HCLK / 1) -#elif STM32_ADC_ADC123_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2 -#define STM32_ADC123_CLOCK (STM32_HCLK / 2) -#elif STM32_ADC_ADC123_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4 -#define STM32_ADC123_CLOCK (STM32_HCLK / 4) -#else -#error "invalid clock mode selected for STM32_ADC_ADC123_CLOCK_MODE" -#endif - -#if STM32_ADC123_CLOCK > STM32_ADCCLK_MAX -#error "STM32_ADC123_CLOCK exceeding maximum frequency (STM32_ADCCLK_MAX)" -#endif -#endif /* defined(STM32L4XX) */ - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief ADC sample data type. - */ -#if !STM32_ADC_COMPACT_SAMPLES || defined(__DOXYGEN__) -typedef uint16_t adcsample_t; -#else -typedef uint8_t adcsample_t; -#endif - -/** - * @brief Channels number in a conversion group. - */ -typedef uint16_t adc_channels_num_t; - -/** - * @brief Possible ADC failure causes. - * @note Error codes are architecture dependent and should not relied - * upon. - */ -typedef enum { - ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */ - ADC_ERR_OVERFLOW = 1, /**< ADC overflow condition. */ - ADC_ERR_AWD1 = 2, /**< Watchdog 1 triggered. */ - ADC_ERR_AWD2 = 3, /**< Watchdog 2 triggered. */ - ADC_ERR_AWD3 = 4 /**< Watchdog 3 triggered. */ -} adcerror_t; - -/** - * @brief Type of a structure representing an ADC driver. - */ -typedef struct ADCDriver ADCDriver; - -/** - * @brief ADC notification callback type. - * - * @param[in] adcp pointer to the @p ADCDriver object triggering the - * callback - * @param[in] buffer pointer to the most recent samples data - * @param[in] n number of buffer rows available starting from @p buffer - */ -typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n); - -/** - * @brief ADC error callback type. - * - * @param[in] adcp pointer to the @p ADCDriver object triggering the - * callback - * @param[in] err ADC error code - */ -typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err); - -/** - * @brief Conversion group configuration structure. - * @details This implementation-dependent structure describes a conversion - * operation. - * @note The use of this configuration structure requires knowledge of - * STM32 ADC cell registers interface, please refer to the STM32 - * reference manual for details. - */ -typedef struct { - /** - * @brief Enables the circular buffer mode for the group. - */ - bool circular; - /** - * @brief Number of the analog channels belonging to the conversion group. - */ - adc_channels_num_t num_channels; - /** - * @brief Callback function associated to the group or @p NULL. - */ - adccallback_t end_cb; - /** - * @brief Error callback or @p NULL. - */ - adcerrorcallback_t error_cb; - /* End of the mandatory fields.*/ - /** - * @brief ADC CFGR register initialization data. - * @note The bits DMAEN and DMACFG are enforced internally - * to the driver, keep them to zero. - * @note The bits @p ADC_CFGR_CONT or @p ADC_CFGR_DISCEN must be - * specified in continuous mode or if the buffer depth is - * greater than one. - */ - uint32_t cfgr; - /** - * @brief ADC TR1 register initialization data. - */ - uint32_t tr1; -#if STM32_ADC_DUAL_MODE || defined(__DOXYGEN__) - /** - * @brief ADC CCR register initialization data. - * @note The bits CKMODE, MDMA, DMACFG are enforced internally to the - * driver, keep them to zero. - * @note This field is only present in dual mode. - */ - uint32_t ccr; -#endif - /** - * @brief ADC SMPRx registers initialization data. - */ - uint32_t smpr[2]; - /** - * @brief ADC SQRx register initialization data. - */ - uint32_t sqr[4]; -#if STM32_ADC_DUAL_MODE || defined(__DOXYGEN__) - /** - * @brief Slave ADC SMPRx registers initialization data. - * @note This field is only present in dual mode. - */ - uint32_t ssmpr[2]; - /** - * @brief Slave ADC SQRx register initialization data. - * @note This field is only present in dual mode. - */ - uint32_t ssqr[4]; -#endif /* STM32_ADC_DUAL_MODE */ -} ADCConversionGroup; - -/** - * @brief Driver configuration structure. - */ -typedef struct { - /** - * @brief ADC DIFSEL register initialization data. - */ - uint32_t difsel; -} ADCConfig; - -/** - * @brief Structure representing an ADC driver. - */ -struct ADCDriver { - /** - * @brief Driver state. - */ - adcstate_t state; - /** - * @brief Current configuration data. - */ - const ADCConfig *config; - /** - * @brief Current samples buffer pointer or @p NULL. - */ - adcsample_t *samples; - /** - * @brief Current samples buffer depth or @p 0. - */ - size_t depth; - /** - * @brief Current conversion group pointer or @p NULL. - */ - const ADCConversionGroup *grpp; -#if ADC_USE_WAIT || defined(__DOXYGEN__) - /** - * @brief Waiting thread. - */ - thread_reference_t thread; -#endif -#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the peripheral. - */ - mutex_t mutex; -#endif /* ADC_USE_MUTUAL_EXCLUSION */ -#if defined(ADC_DRIVER_EXT_FIELDS) - ADC_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the master ADCx registers block. - */ - ADC_TypeDef *adcm; -#if STM32_ADC_DUAL_MODE || defined(__DOXYGEN__) - /** - * @brief Pointer to the slave ADCx registers block. - */ - ADC_TypeDef *adcs; -#endif /* STM32_ADC_DUAL_MODE */ - /** - * @brief Pointer to the common ADCx_y registers block. - */ - ADC_Common_TypeDef *adcc; - /** - * @brief Pointer to associated DMA channel. - */ - const stm32_dma_stream_t *dmastp; - /** - * @brief DMA mode bit mask. - */ - uint32_t dmamode; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Threashold register initializer - * @{ - */ -#define ADC_TR(low, high) (((uint32_t)(high) << 16) | (uint32_t)(low)) -/** @} */ - -/** - * @name Sequences building helper macros - * @{ - */ -/** - * @brief Number of channels in a conversion sequence. - */ -#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 0) - -#define ADC_SQR1_SQ1_N(n) ((n) << 6) /**< @brief 1st channel in seq. */ -#define ADC_SQR1_SQ2_N(n) ((n) << 12) /**< @brief 2nd channel in seq. */ -#define ADC_SQR1_SQ3_N(n) ((n) << 18) /**< @brief 3rd channel in seq. */ -#define ADC_SQR1_SQ4_N(n) ((n) << 24) /**< @brief 4th channel in seq. */ - -#define ADC_SQR2_SQ5_N(n) ((n) << 0) /**< @brief 5th channel in seq. */ -#define ADC_SQR2_SQ6_N(n) ((n) << 6) /**< @brief 6th channel in seq. */ -#define ADC_SQR2_SQ7_N(n) ((n) << 12) /**< @brief 7th channel in seq. */ -#define ADC_SQR2_SQ8_N(n) ((n) << 18) /**< @brief 8th channel in seq. */ -#define ADC_SQR2_SQ9_N(n) ((n) << 24) /**< @brief 9th channel in seq. */ - -#define ADC_SQR3_SQ10_N(n) ((n) << 0) /**< @brief 10th channel in seq.*/ -#define ADC_SQR3_SQ11_N(n) ((n) << 6) /**< @brief 11th channel in seq.*/ -#define ADC_SQR3_SQ12_N(n) ((n) << 12) /**< @brief 12th channel in seq.*/ -#define ADC_SQR3_SQ13_N(n) ((n) << 18) /**< @brief 13th channel in seq.*/ -#define ADC_SQR3_SQ14_N(n) ((n) << 24) /**< @brief 14th channel in seq.*/ - -#define ADC_SQR4_SQ15_N(n) ((n) << 0) /**< @brief 15th channel in seq.*/ -#define ADC_SQR4_SQ16_N(n) ((n) << 6) /**< @brief 16th channel in seq.*/ -/** @} */ - -/** - * @name Sampling rate settings helper macros - * @{ - */ -#define ADC_SMPR1_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */ -#define ADC_SMPR1_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */ -#define ADC_SMPR1_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */ -#define ADC_SMPR1_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */ -#define ADC_SMPR1_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */ -#define ADC_SMPR1_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */ -#define ADC_SMPR1_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */ -#define ADC_SMPR1_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */ -#define ADC_SMPR1_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */ -#define ADC_SMPR1_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */ - -#define ADC_SMPR2_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */ -#define ADC_SMPR2_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */ -#define ADC_SMPR2_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */ -#define ADC_SMPR2_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */ -#define ADC_SMPR2_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */ -#define ADC_SMPR2_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */ -#define ADC_SMPR2_SMP_AN16(n) ((n) << 18) /**< @brief AN16 sampling time. */ -#define ADC_SMPR2_SMP_AN17(n) ((n) << 21) /**< @brief AN17 sampling time. */ -#define ADC_SMPR2_SMP_AN18(n) ((n) << 24) /**< @brief AN18 sampling time. */ -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__) -extern ADCDriver ADCD1; -#endif - -#if STM32_ADC_USE_ADC2 && !defined(__DOXYGEN__) -extern ADCDriver ADCD2; -#endif - -#if STM32_ADC_USE_ADC3 && !defined(__DOXYGEN__) -extern ADCDriver ADCD3; -#endif - -#if STM32_ADC_USE_ADC4 && !defined(__DOXYGEN__) -extern ADCDriver ADCD4; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void adc_lld_init(void); - void adc_lld_start(ADCDriver *adcp); - void adc_lld_stop(ADCDriver *adcp); - void adc_lld_start_conversion(ADCDriver *adcp); - void adc_lld_stop_conversion(ADCDriver *adcp); - void adcSTM32EnableVREF(ADCDriver *adcp); - void adcSTM32DisableVREF(ADCDriver *adcp); - void adcSTM32EnableTS(ADCDriver *adcp); - void adcSTM32DisableTS(ADCDriver *adcp); - void adcSTM32EnableVBAT(ADCDriver *adcp); - void adcSTM32DisableVBAT(ADCDriver *adcp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_ADC */ - -#endif /* HAL_ADC_LLD_H */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/ADCv3/notes.txt b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/ADCv3/notes.txt deleted file mode 100644 index 37155ca0ab..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/ADCv3/notes.txt +++ /dev/null @@ -1,19 +0,0 @@ -STM32 ADCv3 driver. - -Driver capability: - -- Supports the STM32 "fast" ADC found on F3 and L4 sub-families. - -The file registry must export: - -STM32_HAS_ADCx - ADCx presence flag (1..4). -STM32_ADC1_HANDLER - IRQ vector name for ADC1. -STM32_ADC1_NUMBER - IRQ vector number for ADC1. -STM32_ADC2_HANDLER - IRQ vector name for ADC2. -STM32_ADC2_NUMBER - IRQ vector number for ADC2. -STM32_ADC3_HANDLER - IRQ vector name for ADC3. -STM32_ADC3_NUMBER - IRQ vector number for ADC3. -STM32_ADC4_HANDLER - IRQ vector name for ADC4. -STM32_ADC4_NUMBER - IRQ vector number for ADC4. -STM32_ADCx_DMA_MSK - Mask of the compatible DMA channels (1..4). -STM32_ADCx_DMA_CHN - Mask of the channels mapping (1..4). diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/CANv1/can_lld.c b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/CANv1/can_lld.c deleted file mode 100644 index 841dac1697..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/CANv1/can_lld.c +++ /dev/null @@ -1,848 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/can_lld.c - * @brief STM32 CAN subsystem low level driver source. - * - * @addtogroup CAN - * @{ - */ - -#include "hal.h" - -#if HAL_USE_CAN || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/* - * Addressing differences in the headers, they seem unable to agree on names. - */ -#if STM32_CAN_USE_CAN1 -#if !defined(CAN1) -#define CAN1 CAN -#endif -#endif - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief CAN1 driver identifier.*/ -#if STM32_CAN_USE_CAN1 || defined(__DOXYGEN__) -CANDriver CAND1; -#endif - -/** @brief CAN2 driver identifier.*/ -#if STM32_CAN_USE_CAN2 || defined(__DOXYGEN__) -CANDriver CAND2; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Programs the filters. - * - * @param[in] can2sb number of the first filter assigned to CAN2 - * @param[in] num number of entries in the filters array, if zero then - * a default filter is programmed - * @param[in] cfp pointer to the filters array, can be @p NULL if - * (num == 0) - * - * @notapi - */ -static void can_lld_set_filters(uint32_t can2sb, - uint32_t num, - const CANFilter *cfp) { - - /* Temporarily enabling CAN1 clock.*/ - rccEnableCAN1(FALSE); - - /* Filters initialization.*/ - CAN1->FMR = (CAN1->FMR & 0xFFFF0000) | CAN_FMR_FINIT; - CAN1->FMR |= (can2sb << 8); - if (num > 0) { - uint32_t i, fmask; - - /* All filters cleared.*/ - CAN1->FA1R = 0; - CAN1->FM1R = 0; - CAN1->FS1R = 0; - CAN1->FFA1R = 0; - for (i = 0; i < STM32_CAN_MAX_FILTERS; i++) { - CAN1->sFilterRegister[i].FR1 = 0; - CAN1->sFilterRegister[i].FR2 = 0; - } - - /* Scanning the filters array.*/ - for (i = 0; i < num; i++) { - fmask = 1 << cfp->filter; - if (cfp->mode) - CAN1->FM1R |= fmask; - if (cfp->scale) - CAN1->FS1R |= fmask; - if (cfp->assignment) - CAN1->FFA1R |= fmask; - CAN1->sFilterRegister[cfp->filter].FR1 = cfp->register1; - CAN1->sFilterRegister[cfp->filter].FR2 = cfp->register2; - CAN1->FA1R |= fmask; - cfp++; - } - } - else { - /* Setting up a single default filter that enables everything for both - CANs.*/ - CAN1->sFilterRegister[0].FR1 = 0; - CAN1->sFilterRegister[0].FR2 = 0; -#if STM32_HAS_CAN2 - CAN1->sFilterRegister[can2sb].FR1 = 0; - CAN1->sFilterRegister[can2sb].FR2 = 0; -#endif - CAN1->FM1R = 0; - CAN1->FFA1R = 0; -#if STM32_HAS_CAN2 - CAN1->FS1R = 1 | (1 << can2sb); - CAN1->FA1R = 1 | (1 << can2sb); -#else - CAN1->FS1R = 1; - CAN1->FA1R = 1; -#endif - } - CAN1->FMR &= ~CAN_FMR_FINIT; - - /* Clock disabled, it will be enabled again in can_lld_start().*/ - rccDisableCAN1(FALSE); -} - -/** - * @brief Common TX ISR handler. - * - * @param[in] canp pointer to the @p CANDriver object - * - * @notapi - */ -static void can_lld_tx_handler(CANDriver *canp) { - uint32_t tsr; - eventflags_t flags; - - /* Clearing IRQ sources.*/ - tsr = canp->can->TSR; - canp->can->TSR = tsr; - - /* Flags to be signaled through the TX event source.*/ - flags = 0U; - - /* Checking mailbox 0.*/ - if ((tsr & CAN_TSR_RQCP0) != 0U) { - if ((tsr & (CAN_TSR_ALST0 | CAN_TSR_TERR0)) != 0U) { - flags |= CAN_MAILBOX_TO_MASK(1U) << 16U; - } - else { - flags |= CAN_MAILBOX_TO_MASK(1U); - } - } - - /* Checking mailbox 1.*/ - if ((tsr & CAN_TSR_RQCP1) != 0U) { - if ((tsr & (CAN_TSR_ALST1 | CAN_TSR_TERR1)) != 0U) { - flags |= CAN_MAILBOX_TO_MASK(2U) << 16U; - } - else { - flags |= CAN_MAILBOX_TO_MASK(2U); - } - } - - /* Checking mailbox 2.*/ - if ((tsr & CAN_TSR_RQCP2) != 0U) { - if ((tsr & (CAN_TSR_ALST2 | CAN_TSR_TERR2)) != 0U) { - flags |= CAN_MAILBOX_TO_MASK(3U) << 16U; - } - else { - flags |= CAN_MAILBOX_TO_MASK(3U); - } - } - - /* Signaling flags and waking up threads waiting for a transmission slot.*/ - osalSysLockFromISR(); - osalThreadDequeueAllI(&canp->txqueue, MSG_OK); - osalEventBroadcastFlagsI(&canp->txempty_event, flags); - osalSysUnlockFromISR(); -} - -/** - * @brief Common RX0 ISR handler. - * - * @param[in] canp pointer to the @p CANDriver object - * - * @notapi - */ -static void can_lld_rx0_handler(CANDriver *canp) { - uint32_t rf0r; - - rf0r = canp->can->RF0R; - if ((rf0r & CAN_RF0R_FMP0) > 0) { - /* No more receive events until the queue 0 has been emptied.*/ - canp->can->IER &= ~CAN_IER_FMPIE0; - osalSysLockFromISR(); - osalThreadDequeueAllI(&canp->rxqueue, MSG_OK); - osalEventBroadcastFlagsI(&canp->rxfull_event, CAN_MAILBOX_TO_MASK(1U)); - osalSysUnlockFromISR(); - } - if ((rf0r & CAN_RF0R_FOVR0) > 0) { - /* Overflow events handling.*/ - canp->can->RF0R = CAN_RF0R_FOVR0; - osalSysLockFromISR(); - osalEventBroadcastFlagsI(&canp->error_event, CAN_OVERFLOW_ERROR); - osalSysUnlockFromISR(); - } -} - -/** - * @brief Common RX1 ISR handler. - * - * @param[in] canp pointer to the @p CANDriver object - * - * @notapi - */ -static void can_lld_rx1_handler(CANDriver *canp) { - uint32_t rf1r; - - rf1r = canp->can->RF1R; - if ((rf1r & CAN_RF1R_FMP1) > 0) { - /* No more receive events until the queue 0 has been emptied.*/ - canp->can->IER &= ~CAN_IER_FMPIE1; - osalSysLockFromISR(); - osalThreadDequeueAllI(&canp->rxqueue, MSG_OK); - osalEventBroadcastFlagsI(&canp->rxfull_event, CAN_MAILBOX_TO_MASK(2U)); - osalSysUnlockFromISR(); - } - if ((rf1r & CAN_RF1R_FOVR1) > 0) { - /* Overflow events handling.*/ - canp->can->RF1R = CAN_RF1R_FOVR1; - osalSysLockFromISR(); - osalEventBroadcastFlagsI(&canp->error_event, CAN_OVERFLOW_ERROR); - osalSysUnlockFromISR(); - } -} - -/** - * @brief Common SCE ISR handler. - * - * @param[in] canp pointer to the @p CANDriver object - * - * @notapi - */ -static void can_lld_sce_handler(CANDriver *canp) { - uint32_t msr; - - /* Clearing IRQ sources.*/ - msr = canp->can->MSR; - canp->can->MSR = msr; - - /* Wakeup event.*/ -#if CAN_USE_SLEEP_MODE - if (msr & CAN_MSR_WKUI) { - canp->state = CAN_READY; - canp->can->MCR &= ~CAN_MCR_SLEEP; - osalSysLockFromISR(); - osalEventBroadcastFlagsI(&canp->wakeup_event, 0); - osalSysUnlockFromISR(); - } -#endif /* CAN_USE_SLEEP_MODE */ - /* Error event.*/ - if (msr & CAN_MSR_ERRI) { - eventflags_t flags; - uint32_t esr = canp->can->ESR; - -#if STM32_CAN_REPORT_ALL_ERRORS - flags = (eventflags_t)(esr & 7); - if ((esr & CAN_ESR_LEC) > 0) - flags |= CAN_FRAMING_ERROR; -#else - flags = 0; -#endif - - osalSysLockFromISR(); - /* The content of the ESR register is copied unchanged in the upper - half word of the listener flags mask.*/ - osalEventBroadcastFlagsI(&canp->error_event, - flags | (eventflags_t)(esr << 16U)); - osalSysUnlockFromISR(); - } -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if STM32_CAN_USE_CAN1 || defined(__DOXYGEN__) -#if defined(STM32_CAN1_UNIFIED_HANDLER) -/** - * @brief CAN1 unified interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_CAN1_UNIFIED_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - can_lld_tx_handler(&CAND1); - can_lld_rx0_handler(&CAND1); - can_lld_rx1_handler(&CAND1); - can_lld_sce_handler(&CAND1); - - OSAL_IRQ_EPILOGUE(); -} -#else /* !defined(STM32_CAN1_UNIFIED_HANDLER) */ - -#if !defined(STM32_CAN1_TX_HANDLER) -#error "STM32_CAN1_TX_HANDLER not defined" -#endif -#if !defined(STM32_CAN1_RX0_HANDLER) -#error "STM32_CAN1_RX0_HANDLER not defined" -#endif -#if !defined(STM32_CAN1_RX1_HANDLER) -#error "STM32_CAN1_RX1_HANDLER not defined" -#endif -#if !defined(STM32_CAN1_SCE_HANDLER) -#error "STM32_CAN1_SCE_HANDLER not defined" -#endif - -/** - * @brief CAN1 TX interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_CAN1_TX_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - can_lld_tx_handler(&CAND1); - - OSAL_IRQ_EPILOGUE(); -} - -/* - * @brief CAN1 RX0 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_CAN1_RX0_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - can_lld_rx0_handler(&CAND1); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief CAN1 RX1 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_CAN1_RX1_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - can_lld_rx1_handler(&CAND1); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief CAN1 SCE interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_CAN1_SCE_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - can_lld_sce_handler(&CAND1); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* !defined(STM32_CAN1_UNIFIED_HANDLER) */ -#endif /* STM32_CAN_USE_CAN1 */ - -#if STM32_CAN_USE_CAN2 || defined(__DOXYGEN__) -#if defined(STM32_CAN2_UNIFIED_HANDLER) -/** - * @brief CAN1 unified interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_CAN2_UNIFIED_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - can_lld_tx_handler(&CAND2); - can_lld_rx0_handler(&CAND2); - can_lld_rx1_handler(&CAND2); - can_lld_sce_handler(&CAND2); - - OSAL_IRQ_EPILOGUE(); -} -#else /* !defined(STM32_CAN2_UNIFIED_HANDLER) */ - -#if !defined(STM32_CAN1_TX_HANDLER) -#error "STM32_CAN1_TX_HANDLER not defined" -#endif -#if !defined(STM32_CAN1_RX0_HANDLER) -#error "STM32_CAN1_RX0_HANDLER not defined" -#endif -#if !defined(STM32_CAN1_RX1_HANDLER) -#error "STM32_CAN1_RX1_HANDLER not defined" -#endif -#if !defined(STM32_CAN1_SCE_HANDLER) -#error "STM32_CAN1_SCE_HANDLER not defined" -#endif - -/** - * @brief CAN2 TX interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_CAN2_TX_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - can_lld_tx_handler(&CAND2); - - OSAL_IRQ_EPILOGUE(); -} - -/* - * @brief CAN2 RX0 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_CAN2_RX0_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - can_lld_rx0_handler(&CAND2); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief CAN2 RX1 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_CAN2_RX1_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - can_lld_rx1_handler(&CAND2); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief CAN2 SCE interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_CAN2_SCE_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - can_lld_sce_handler(&CAND2); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* !defined(STM32_CAN2_UNIFIED_HANDLER) */ -#endif /* STM32_CAN_USE_CAN2 */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level CAN driver initialization. - * - * @notapi - */ -void can_lld_init(void) { - -#if STM32_CAN_USE_CAN1 - /* Driver initialization.*/ - canObjectInit(&CAND1); - CAND1.can = CAN1; -#endif -#if STM32_CAN_USE_CAN2 - /* Driver initialization.*/ - canObjectInit(&CAND2); - CAND2.can = CAN2; -#endif - - /* Filters initialization.*/ -#if STM32_HAS_CAN2 - can_lld_set_filters(STM32_CAN_MAX_FILTERS / 2, 0, NULL); -#else - can_lld_set_filters(STM32_CAN_MAX_FILTERS, 0, NULL); -#endif -} - -/** - * @brief Configures and activates the CAN peripheral. - * - * @param[in] canp pointer to the @p CANDriver object - * - * @notapi - */ -void can_lld_start(CANDriver *canp) { - - /* Clock activation.*/ -#if STM32_CAN_USE_CAN1 - if (&CAND1 == canp) { -#if defined(STM32_CAN1_UNIFIED_NUMBER) - nvicEnableVector(STM32_CAN1_UNIFIED_NUMBER, STM32_CAN_CAN1_IRQ_PRIORITY); -#else - nvicEnableVector(STM32_CAN1_TX_NUMBER, STM32_CAN_CAN1_IRQ_PRIORITY); - nvicEnableVector(STM32_CAN1_RX0_NUMBER, STM32_CAN_CAN1_IRQ_PRIORITY); - nvicEnableVector(STM32_CAN1_RX1_NUMBER, STM32_CAN_CAN1_IRQ_PRIORITY); - nvicEnableVector(STM32_CAN1_SCE_NUMBER, STM32_CAN_CAN1_IRQ_PRIORITY); -#endif - rccEnableCAN1(FALSE); - } -#endif -#if STM32_CAN_USE_CAN2 - if (&CAND2 == canp) { - - osalDbgAssert(CAND1.state != CAN_STOP, "CAN1 must be started"); - -#if defined(STM32_CAN2_UNIFIED_NUMBER) - nvicEnableVector(STM32_CAN2_UNIFIED_NUMBER, STM32_CAN_CAN2_IRQ_PRIORITY); -#else - nvicEnableVector(STM32_CAN2_TX_NUMBER, STM32_CAN_CAN2_IRQ_PRIORITY); - nvicEnableVector(STM32_CAN2_RX0_NUMBER, STM32_CAN_CAN2_IRQ_PRIORITY); - nvicEnableVector(STM32_CAN2_RX1_NUMBER, STM32_CAN_CAN2_IRQ_PRIORITY); - nvicEnableVector(STM32_CAN2_SCE_NUMBER, STM32_CAN_CAN2_IRQ_PRIORITY); -#endif - rccEnableCAN2(FALSE); - } -#endif - - /* Configuring CAN. */ - canp->can->MCR = CAN_MCR_INRQ; - while ((canp->can->MSR & CAN_MSR_INAK) == 0) - osalThreadSleepS(1); - canp->can->BTR = canp->config->btr; - canp->can->MCR = canp->config->mcr; - - /* Interrupt sources initialization.*/ -#if STM32_CAN_REPORT_ALL_ERRORS - canp->can->IER = CAN_IER_TMEIE | CAN_IER_FMPIE0 | CAN_IER_FMPIE1 | - CAN_IER_WKUIE | CAN_IER_ERRIE | CAN_IER_LECIE | - CAN_IER_BOFIE | CAN_IER_EPVIE | CAN_IER_EWGIE | - CAN_IER_FOVIE0 | CAN_IER_FOVIE1; -#else - canp->can->IER = CAN_IER_TMEIE | CAN_IER_FMPIE0 | CAN_IER_FMPIE1 | - CAN_IER_WKUIE | CAN_IER_ERRIE | - CAN_IER_BOFIE | CAN_IER_EPVIE | CAN_IER_EWGIE | - CAN_IER_FOVIE0 | CAN_IER_FOVIE1; -#endif -} - -/** - * @brief Deactivates the CAN peripheral. - * - * @param[in] canp pointer to the @p CANDriver object - * - * @notapi - */ -void can_lld_stop(CANDriver *canp) { - - /* If in ready state then disables the CAN peripheral.*/ - if (canp->state == CAN_READY) { -#if STM32_CAN_USE_CAN1 - if (&CAND1 == canp) { - -#if STM32_CAN_USE_CAN2 - osalDbgAssert(CAND2.state == CAN_STOP, "CAN2 must be stopped"); -#endif - - CAN1->MCR = 0x00010002; /* Register reset value. */ - CAN1->IER = 0x00000000; /* All sources disabled. */ -#if defined(STM32_CAN1_UNIFIED_NUMBER) - nvicDisableVector(STM32_CAN1_UNIFIED_NUMBER); -#else - nvicDisableVector(STM32_CAN1_TX_NUMBER); - nvicDisableVector(STM32_CAN1_RX0_NUMBER); - nvicDisableVector(STM32_CAN1_RX1_NUMBER); - nvicDisableVector(STM32_CAN1_SCE_NUMBER); -#endif - rccDisableCAN1(FALSE); - } -#endif -#if STM32_CAN_USE_CAN2 - if (&CAND2 == canp) { - CAN2->MCR = 0x00010002; /* Register reset value. */ - CAN2->IER = 0x00000000; /* All sources disabled. */ -#if defined(STM32_CAN2_UNIFIED_NUMBER) - nvicDisableVector(STM32_CAN2_UNIFIED_NUMBER); -#else - nvicDisableVector(STM32_CAN2_TX_NUMBER); - nvicDisableVector(STM32_CAN2_RX0_NUMBER); - nvicDisableVector(STM32_CAN2_RX1_NUMBER); - nvicDisableVector(STM32_CAN2_SCE_NUMBER); -#endif - rccDisableCAN2(FALSE); - } -#endif - } -} - -/** - * @brief Determines whether a frame can be transmitted. - * - * @param[in] canp pointer to the @p CANDriver object - * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox - * - * @return The queue space availability. - * @retval FALSE no space in the transmit queue. - * @retval TRUE transmit slot available. - * - * @notapi - */ -bool can_lld_is_tx_empty(CANDriver *canp, canmbx_t mailbox) { - - switch (mailbox) { - case CAN_ANY_MAILBOX: - return (canp->can->TSR & CAN_TSR_TME) != 0; - case 1: - return (canp->can->TSR & CAN_TSR_TME0) != 0; - case 2: - return (canp->can->TSR & CAN_TSR_TME1) != 0; - case 3: - return (canp->can->TSR & CAN_TSR_TME2) != 0; - default: - return FALSE; - } -} - -/** - * @brief Inserts a frame into the transmit queue. - * - * @param[in] canp pointer to the @p CANDriver object - * @param[in] ctfp pointer to the CAN frame to be transmitted - * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox - * - * @notapi - */ -void can_lld_transmit(CANDriver *canp, - canmbx_t mailbox, - const CANTxFrame *ctfp) { - uint32_t tir; - CAN_TxMailBox_TypeDef *tmbp; - - /* Pointer to a free transmission mailbox.*/ - switch (mailbox) { - case CAN_ANY_MAILBOX: - tmbp = &canp->can->sTxMailBox[(canp->can->TSR & CAN_TSR_CODE) >> 24]; - break; - case 1: - tmbp = &canp->can->sTxMailBox[0]; - break; - case 2: - tmbp = &canp->can->sTxMailBox[1]; - break; - case 3: - tmbp = &canp->can->sTxMailBox[2]; - break; - default: - return; - } - - /* Preparing the message.*/ - if (ctfp->IDE) - tir = ((uint32_t)ctfp->EID << 3) | ((uint32_t)ctfp->RTR << 1) | - CAN_TI0R_IDE; - else - tir = ((uint32_t)ctfp->SID << 21) | ((uint32_t)ctfp->RTR << 1); - tmbp->TDTR = ctfp->DLC; - tmbp->TDLR = ctfp->data32[0]; - tmbp->TDHR = ctfp->data32[1]; - tmbp->TIR = tir | CAN_TI0R_TXRQ; -} - -/** - * @brief Determines whether a frame has been received. - * - * @param[in] canp pointer to the @p CANDriver object - * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox - * - * @return The queue space availability. - * @retval FALSE no space in the transmit queue. - * @retval TRUE transmit slot available. - * - * @notapi - */ -bool can_lld_is_rx_nonempty(CANDriver *canp, canmbx_t mailbox) { - - switch (mailbox) { - case CAN_ANY_MAILBOX: - return ((canp->can->RF0R & CAN_RF0R_FMP0) != 0 || - (canp->can->RF1R & CAN_RF1R_FMP1) != 0); - case 1: - return (canp->can->RF0R & CAN_RF0R_FMP0) != 0; - case 2: - return (canp->can->RF1R & CAN_RF1R_FMP1) != 0; - default: - return FALSE; - } -} - -/** - * @brief Receives a frame from the input queue. - * - * @param[in] canp pointer to the @p CANDriver object - * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox - * @param[out] crfp pointer to the buffer where the CAN frame is copied - * - * @notapi - */ -void can_lld_receive(CANDriver *canp, - canmbx_t mailbox, - CANRxFrame *crfp) { - uint32_t rir, rdtr; - - if (mailbox == CAN_ANY_MAILBOX) { - if ((canp->can->RF0R & CAN_RF0R_FMP0) != 0) - mailbox = 1; - else if ((canp->can->RF1R & CAN_RF1R_FMP1) != 0) - mailbox = 2; - else { - /* Should not happen, do nothing.*/ - return; - } - } - switch (mailbox) { - case 1: - /* Fetches the message.*/ - rir = canp->can->sFIFOMailBox[0].RIR; - rdtr = canp->can->sFIFOMailBox[0].RDTR; - crfp->data32[0] = canp->can->sFIFOMailBox[0].RDLR; - crfp->data32[1] = canp->can->sFIFOMailBox[0].RDHR; - - /* Releases the mailbox.*/ - canp->can->RF0R = CAN_RF0R_RFOM0; - - /* If the queue is empty re-enables the interrupt in order to generate - events again.*/ - if ((canp->can->RF0R & CAN_RF0R_FMP0) == 0) - canp->can->IER |= CAN_IER_FMPIE0; - break; - case 2: - /* Fetches the message.*/ - rir = canp->can->sFIFOMailBox[1].RIR; - rdtr = canp->can->sFIFOMailBox[1].RDTR; - crfp->data32[0] = canp->can->sFIFOMailBox[1].RDLR; - crfp->data32[1] = canp->can->sFIFOMailBox[1].RDHR; - - /* Releases the mailbox.*/ - canp->can->RF1R = CAN_RF1R_RFOM1; - - /* If the queue is empty re-enables the interrupt in order to generate - events again.*/ - if ((canp->can->RF1R & CAN_RF1R_FMP1) == 0) - canp->can->IER |= CAN_IER_FMPIE1; - break; - default: - /* Should not happen, do nothing.*/ - return; - } - - /* Decodes the various fields in the RX frame.*/ - crfp->RTR = (rir & CAN_RI0R_RTR) >> 1; - crfp->IDE = (rir & CAN_RI0R_IDE) >> 2; - if (crfp->IDE) - crfp->EID = rir >> 3; - else - crfp->SID = rir >> 21; - crfp->DLC = rdtr & CAN_RDT0R_DLC; - crfp->FMI = (uint8_t)(rdtr >> 8); - crfp->TIME = (uint16_t)(rdtr >> 16); -} - -#if CAN_USE_SLEEP_MODE || defined(__DOXYGEN__) -/** - * @brief Enters the sleep mode. - * - * @param[in] canp pointer to the @p CANDriver object - * - * @notapi - */ -void can_lld_sleep(CANDriver *canp) { - - canp->can->MCR |= CAN_MCR_SLEEP; -} - -/** - * @brief Enforces leaving the sleep mode. - * - * @param[in] canp pointer to the @p CANDriver object - * - * @notapi - */ -void can_lld_wakeup(CANDriver *canp) { - - canp->can->MCR &= ~CAN_MCR_SLEEP; -} -#endif /* CAN_USE_SLEEP_MODE */ - -/** - * @brief Programs the filters. - * @note This is an STM32-specific API. - * - * @param[in] can2sb number of the first filter assigned to CAN2 - * @param[in] num number of entries in the filters array, if zero then - * a default filter is programmed - * @param[in] cfp pointer to the filters array, can be @p NULL if - * (num == 0) - * - * @api - */ -void canSTM32SetFilters(uint32_t can2sb, uint32_t num, const CANFilter *cfp) { - - osalDbgCheck((can2sb >= 1) && (can2sb < STM32_CAN_MAX_FILTERS) && - (num <= STM32_CAN_MAX_FILTERS)); - -#if STM32_CAN_USE_CAN1 - osalDbgAssert(CAND1.state == CAN_STOP, "invalid state"); -#endif -#if STM32_CAN_USE_CAN2 - osalDbgAssert(CAND2.state == CAN_STOP, "invalid state"); -#endif - - can_lld_set_filters(can2sb, num, cfp); -} - -#endif /* HAL_USE_CAN */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/CANv1/can_lld.h b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/CANv1/can_lld.h deleted file mode 100644 index fec47888b1..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/CANv1/can_lld.h +++ /dev/null @@ -1,379 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/can_lld.h - * @brief STM32 CAN subsystem low level driver header. - * - * @addtogroup CAN - * @{ - */ - -#ifndef _CAN_LLD_H_ -#define _CAN_LLD_H_ - -#if HAL_USE_CAN || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/* - * The following macros from the ST header file are replaced with better - * equivalents. - */ -#undef CAN_BTR_BRP -#undef CAN_BTR_TS1 -#undef CAN_BTR_TS2 -#undef CAN_BTR_SJW - -/** - * @brief This switch defines whether the driver implementation supports - * a low power switch mode with automatic an wakeup feature. - */ -#define CAN_SUPPORTS_SLEEP TRUE - -/** - * @brief This implementation supports three transmit mailboxes. - */ -#define CAN_TX_MAILBOXES 3 - -/** - * @brief This implementation supports two receive mailboxes. - */ -#define CAN_RX_MAILBOXES 2 - -/** - * @name CAN registers helper macros - * @{ - */ -#define CAN_BTR_BRP(n) (n) /**< @brief BRP field macro.*/ -#define CAN_BTR_TS1(n) ((n) << 16) /**< @brief TS1 field macro.*/ -#define CAN_BTR_TS2(n) ((n) << 20) /**< @brief TS2 field macro.*/ -#define CAN_BTR_SJW(n) ((n) << 24) /**< @brief SJW field macro.*/ - -#define CAN_IDE_STD 0 /**< @brief Standard id. */ -#define CAN_IDE_EXT 1 /**< @brief Extended id. */ - -#define CAN_RTR_DATA 0 /**< @brief Data frame. */ -#define CAN_RTR_REMOTE 1 /**< @brief Remote frame. */ -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief CAN pedantic errors report. - * @details Use of this option is IRQ-intensive. - */ -#if !defined(STM32_CAN_REPORT_ALL_ERRORS) || defined(__DOXYGEN__) -#define STM32_CAN_REPORT_ALL_ERRORS FALSE -#endif - -/** - * @brief CAN1 driver enable switch. - * @details If set to @p TRUE the support for CAN1 is included. - */ -#if !defined(STM32_CAN_USE_CAN1) || defined(__DOXYGEN__) -#define STM32_CAN_USE_CAN1 FALSE -#endif - -/** - * @brief CAN2 driver enable switch. - * @details If set to @p TRUE the support for CAN2 is included. - */ -#if !defined(STM32_CAN_USE_CAN2) || defined(__DOXYGEN__) -#define STM32_CAN_USE_CAN2 FALSE -#endif - -/** - * @brief CAN1 interrupt priority level setting. - */ -#if !defined(STM32_CAN_CAN1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_CAN_CAN1_IRQ_PRIORITY 11 -#endif -/** @} */ - -/** - * @brief CAN2 interrupt priority level setting. - */ -#if !defined(STM32_CAN_CAN2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_CAN_CAN2_IRQ_PRIORITY 11 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_CAN_USE_CAN1 && !STM32_HAS_CAN1 -#error "CAN1 not present in the selected device" -#endif - -#if STM32_CAN_USE_CAN2 && !STM32_HAS_CAN2 -#error "CAN2 not present in the selected device" -#endif - -#if !STM32_CAN_USE_CAN1 && !STM32_CAN_USE_CAN2 -#error "CAN driver activated but no CAN peripheral assigned" -#endif - -#if !STM32_CAN_USE_CAN1 && STM32_CAN_USE_CAN2 -#error "CAN2 requires CAN1, it cannot operate independently" -#endif - -#if CAN_USE_SLEEP_MODE && !CAN_SUPPORTS_SLEEP -#error "CAN sleep mode not supported in this architecture" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a transmission mailbox index. - */ -typedef uint32_t canmbx_t; - -/** - * @brief CAN transmission frame. - * @note Accessing the frame data as word16 or word32 is not portable because - * machine data endianness, it can be still useful for a quick filling. - */ -typedef struct { - struct { - uint8_t DLC:4; /**< @brief Data length. */ - uint8_t RTR:1; /**< @brief Frame type. */ - uint8_t IDE:1; /**< @brief Identifier type. */ - }; - union { - struct { - uint32_t SID:11; /**< @brief Standard identifier.*/ - }; - struct { - uint32_t EID:29; /**< @brief Extended identifier.*/ - }; - }; - union { - uint8_t data8[8]; /**< @brief Frame data. */ - uint16_t data16[4]; /**< @brief Frame data. */ - uint32_t data32[2]; /**< @brief Frame data. */ - uint64_t data64[1]; /**< @brief Frame data. */ - }; -} CANTxFrame; - -/** - * @brief CAN received frame. - * @note Accessing the frame data as word16 or word32 is not portable because - * machine data endianness, it can be still useful for a quick filling. - */ -typedef struct { - struct { - uint8_t FMI; /**< @brief Filter id. */ - uint16_t TIME; /**< @brief Time stamp. */ - }; - struct { - uint8_t DLC:4; /**< @brief Data length. */ - uint8_t RTR:1; /**< @brief Frame type. */ - uint8_t IDE:1; /**< @brief Identifier type. */ - }; - union { - struct { - uint32_t SID:11; /**< @brief Standard identifier.*/ - }; - struct { - uint32_t EID:29; /**< @brief Extended identifier.*/ - }; - }; - union { - uint8_t data8[8]; /**< @brief Frame data. */ - uint16_t data16[4]; /**< @brief Frame data. */ - uint32_t data32[2]; /**< @brief Frame data. */ - uint64_t data64[1]; /**< @brief Frame data. */ - }; -} CANRxFrame; - -/** - * @brief CAN filter. - * @note Refer to the STM32 reference manual for info about filters. - */ -typedef struct { - /** - * @brief Number of the filter to be programmed. - */ - uint32_t filter; - /** - * @brief Filter mode. - * @note This bit represent the CAN_FM1R register bit associated to this - * filter (0=mask mode, 1=list mode). - */ - uint32_t mode:1; - /** - * @brief Filter scale. - * @note This bit represent the CAN_FS1R register bit associated to this - * filter (0=16 bits mode, 1=32 bits mode). - */ - uint32_t scale:1; - /** - * @brief Filter mode. - * @note This bit represent the CAN_FFA1R register bit associated to this - * filter, must be set to zero in this version of the driver. - */ - uint32_t assignment:1; - /** - * @brief Filter register 1 (identifier). - */ - uint32_t register1; - /** - * @brief Filter register 2 (mask/identifier depending on mode=0/1). - */ - uint32_t register2; -} CANFilter; - -/** - * @brief Driver configuration structure. - */ -typedef struct { - /** - * @brief CAN MCR register initialization data. - * @note Some bits in this register are enforced by the driver regardless - * their status in this field. - */ - uint32_t mcr; - /** - * @brief CAN BTR register initialization data. - * @note Some bits in this register are enforced by the driver regardless - * their status in this field. - */ - uint32_t btr; -} CANConfig; - -/** - * @brief Structure representing an CAN driver. - */ -typedef struct { - /** - * @brief Driver state. - */ - canstate_t state; - /** - * @brief Current configuration data. - */ - const CANConfig *config; - /** - * @brief Transmission threads queue. - */ - threads_queue_t txqueue; - /** - * @brief Receive threads queue. - */ - threads_queue_t rxqueue; - /** - * @brief One or more frames become available. - * @note After broadcasting this event it will not be broadcasted again - * until the received frames queue has been completely emptied. It - * is not broadcasted for each received frame. It is - * responsibility of the application to empty the queue by - * repeatedly invoking @p canReceive() when listening to this event. - * This behavior minimizes the interrupt served by the system - * because CAN traffic. - * @note The flags associated to the listeners will indicate which - * receive mailboxes become non-empty. - */ - event_source_t rxfull_event; - /** - * @brief One or more transmission mailbox become available. - * @note The flags associated to the listeners will indicate which - * transmit mailboxes become empty. - * @note The upper 16 bits are transmission error flags associated - * to the transmit mailboxes. - * - */ - event_source_t txempty_event; - /** - * @brief A CAN bus error happened. - * @note The flags associated to the listeners will indicate that - * receive error(s) have occurred. - * @note In this implementation the upper 16 bits are filled with the - * unprocessed content of the ESR register. - */ - event_source_t error_event; -#if CAN_USE_SLEEP_MODE || defined (__DOXYGEN__) - /** - * @brief Entering sleep state event. - */ - event_source_t sleep_event; - /** - * @brief Exiting sleep state event. - */ - event_source_t wakeup_event; -#endif /* CAN_USE_SLEEP_MODE */ - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the CAN registers. - */ - CAN_TypeDef *can; -} CANDriver; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_CAN_USE_CAN1 && !defined(__DOXYGEN__) -extern CANDriver CAND1; -#endif - -#if STM32_CAN_USE_CAN2 && !defined(__DOXYGEN__) -extern CANDriver CAND2; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void can_lld_init(void); - void can_lld_start(CANDriver *canp); - void can_lld_stop(CANDriver *canp); - bool can_lld_is_tx_empty(CANDriver *canp, canmbx_t mailbox); - void can_lld_transmit(CANDriver *canp, - canmbx_t mailbox, - const CANTxFrame *crfp); - bool can_lld_is_rx_nonempty(CANDriver *canp, canmbx_t mailbox); - void can_lld_receive(CANDriver *canp, - canmbx_t mailbox, - CANRxFrame *ctfp); -#if CAN_USE_SLEEP_MODE - void can_lld_sleep(CANDriver *canp); - void can_lld_wakeup(CANDriver *canp); -#endif /* CAN_USE_SLEEP_MODE */ - void canSTM32SetFilters(uint32_t can2sb, uint32_t num, const CANFilter *cfp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_CAN */ - -#endif /* _CAN_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/DACv1/dac_lld.c b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/DACv1/dac_lld.c deleted file mode 100644 index fb8a54e2bd..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/DACv1/dac_lld.c +++ /dev/null @@ -1,536 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file DACv1/dac_lld.c - * @brief STM32 DAC subsystem low level driver source. - * - * @addtogroup DAC - * @{ - */ - -#include "hal.h" - -#if HAL_USE_DAC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/* Because ST headers naming inconsistencies.*/ -#if !defined(DAC1) -#define DAC1 DAC -#endif - -#define DAC1_CH1_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_DAC_DAC1_CH1_DMA_STREAM, \ - STM32_DAC1_CH1_DMA_CHN) - -#define DAC1_CH2_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_DAC_DAC1_CH2_DMA_STREAM, \ - STM32_DAC1_CH2_DMA_CHN) - -#define DAC2_CH1_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_DAC_DAC2_CH1_DMA_STREAM, \ - STM32_DAC2_CH1_DMA_CHN) - -#define DAC2_CH2_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_DAC_DAC2_CH2_DMA_STREAM, \ - STM32_DAC2_CH2_DMA_CHN) - -#define CHANNEL_DATA_OFFSET 3U - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief DAC1 CH1 driver identifier.*/ -#if STM32_DAC_USE_DAC1_CH1 || defined(__DOXYGEN__) -DACDriver DACD1; -#endif - -/** @brief DAC1 CH2 driver identifier.*/ -#if (STM32_DAC_USE_DAC1_CH2 && !STM32_DAC_DUAL_MODE) || defined(__DOXYGEN__) -DACDriver DACD2; -#endif - -/** @brief DAC2 CH1 driver identifier.*/ -#if STM32_DAC_USE_DAC2_CH1 || defined(__DOXYGEN__) -DACDriver DACD3; -#endif - -/** @brief DAC2 CH2 driver identifier.*/ -#if (STM32_DAC_USE_DAC2_CH2 && !STM32_DAC_DUAL_MODE) || defined(__DOXYGEN__) -DACDriver DACD4; -#endif - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -#if STM32_DAC_USE_DAC1_CH1 == TRUE -static const dacparams_t dma1_ch1_params = { - .dac = DAC1, - .dataoffset = 0U, - .regshift = 0U, - .regmask = 0xFFFF0000U, - .dma = STM32_DMA_STREAM(STM32_DAC_DAC1_CH1_DMA_STREAM), - .dmamode = STM32_DMA_CR_CHSEL(DAC1_CH1_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_DAC_DAC1_CH1_DMA_PRIORITY) | - STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE | - STM32_DMA_CR_TCIE, - .dmairqprio = STM32_DAC_DAC1_CH1_IRQ_PRIORITY -}; -#endif - -#if STM32_DAC_USE_DAC1_CH2 == TRUE -static const dacparams_t dma1_ch2_params = { - .dac = DAC1, - .dataoffset = CHANNEL_DATA_OFFSET, - .regshift = 16U, - .regmask = 0x0000FFFFU, - .dma = STM32_DMA_STREAM(STM32_DAC_DAC1_CH2_DMA_STREAM), - .dmamode = STM32_DMA_CR_CHSEL(DAC1_CH2_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_DAC_DAC1_CH2_DMA_PRIORITY) | - STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE | - STM32_DMA_CR_TCIE, - .dmairqprio = STM32_DAC_DAC1_CH2_IRQ_PRIORITY -}; -#endif - -#if STM32_DAC_USE_DAC2_CH1 == TRUE -static const dacparams_t dma2_ch1_params = { - .dac = DAC2, - .dataoffset = 0U, - .regshift = 0U, - .regmask = 0xFFFF0000U, - .dma = STM32_DMA_STREAM(STM32_DAC_DAC2_CH1_DMA_STREAM), - .dmamode = STM32_DMA_CR_CHSEL(DAC2_CH1_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_DAC_DAC2_CH1_DMA_PRIORITY) | - STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE | - STM32_DMA_CR_TCIE, - .dmairqprio = STM32_DAC_DAC2_CH1_IRQ_PRIORITY -}; -#endif - -#if STM32_DAC_USE_DAC2_CH2 == TRUE -static const dacparams_t dma1_ch2_params = { - .dac = DAC2, - .dataoffset = CHANNEL_DATA_OFFSET, - .regshift = 16U, - .regmask = 0x0000FFFFU, - .dma = STM32_DMA_STREAM(STM32_DAC_DAC2_CH2_DMA_STREAM), - .dmamode = STM32_DMA_CR_CHSEL(DAC2_CH2_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_DAC_DAC2_CH2_DMA_PRIORITY) | - STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE | - STM32_DMA_CR_TCIE, - .dmairqprio = STM32_DAC_DAC2_CH2_IRQ_PRIORITY -}; -#endif - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Shared end/half-of-tx service routine. - * - * @param[in] dacp pointer to the @p DACDriver object - * @param[in] flags pre-shifted content of the ISR register - */ -static void dac_lld_serve_tx_interrupt(DACDriver *dacp, uint32_t flags) { - - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - /* DMA errors handling.*/ - _dac_isr_error_code(dacp, DAC_ERR_DMAFAILURE); - } - else { - if ((flags & STM32_DMA_ISR_HTIF) != 0) { - /* Half transfer processing.*/ - _dac_isr_half_code(dacp); - } - if ((flags & STM32_DMA_ISR_TCIF) != 0) { - /* Transfer complete processing.*/ - _dac_isr_full_code(dacp); - } - } -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level DAC driver initialization. - * - * @notapi - */ -void dac_lld_init(void) { - -#if STM32_DAC_USE_DAC1_CH1 - dacObjectInit(&DACD1); - DACD1.params = &dma1_ch1_params; -#endif - -#if STM32_DAC_USE_DAC1_CH2 - dacObjectInit(&DACD2); - DACD2.params = &dma1_ch2_params; -#endif - -#if STM32_DAC_USE_DAC2_CH1 - dacObjectInit(&DACD3); - DACD3.params = &dma2_ch1_params; -#endif - -#if STM32_DAC_USE_DAC2_CH2 - dacObjectInit(&DACD4); - DACD4.params = &dma2_ch2_params; -#endif -} - -/** - * @brief Configures and activates the DAC peripheral. - * - * @param[in] dacp pointer to the @p DACDriver object - * - * @notapi - */ -void dac_lld_start(DACDriver *dacp) { - - /* If the driver is in DAC_STOP state then a full initialization is - required.*/ - if (dacp->state == DAC_STOP) { - dacchannel_t channel = 0; - - /* Enabling the clock source.*/ -#if STM32_DAC_USE_DAC1_CH1 - if (&DACD1 == dacp) { - rccEnableDAC1(false); - } -#endif - -#if STM32_DAC_USE_DAC1_CH2 - if (&DACD2 == dacp) { - rccEnableDAC1(false); - channel = 1; - } -#endif - -#if STM32_DAC_USE_DAC2_CH1 - if (&DACD3 == dacp) { - rccEnableDAC2(false); - } -#endif - -#if STM32_DAC_USE_DAC2_CH2 - if (&DACD4 == dacp) { - rccEnableDAC2(false); - channel = 1; - } -#endif - /* Enabling DAC in SW triggering mode initially, initializing data to - zero.*/ -#if STM32_DAC_DUAL_MODE == FALSE - dacp->params->dac->CR &= dacp->params->regmask; - dacp->params->dac->CR |= (DAC_CR_EN1 | dacp->config->cr) << dacp->params->regshift; - dac_lld_put_channel(dacp, channel, dacp->config->init); -#else - if ((dacp->config->datamode == DAC_DHRM_12BIT_RIGHT_DUAL) || - (dacp->config->datamode == DAC_DHRM_12BIT_LEFT_DUAL) || - (dacp->config->datamode == DAC_DHRM_8BIT_RIGHT_DUAL)) { - dacp->params->dac->CR = DAC_CR_EN2 | (dacp->config->cr << 16) | DAC_CR_EN1 | dacp->config->cr; - dac_lld_put_channel(dacp, 1U, dacp->config->init); - } - else { - dacp->params->dac->CR = DAC_CR_EN1 | dacp->config->cr; - } - dac_lld_put_channel(dacp, channel, dacp->config->init); -#endif - } -} - -/** - * @brief Deactivates the DAC peripheral. - * - * @param[in] dacp pointer to the @p DACDriver object - * - * @notapi - */ -void dac_lld_stop(DACDriver *dacp) { - - /* If in ready state then disables the DAC clock.*/ - if (dacp->state == DAC_READY) { - - /* Disabling DAC.*/ - dacp->params->dac->CR &= dacp->params->regmask; - -#if STM32_DAC_USE_DAC1_CH1 - if (&DACD1 == dacp) { - if ((dacp->params->dac->CR & DAC_CR_EN1) == 0U) { - rccDisableDAC1(false); - } - } -#endif - -#if STM32_DAC_USE_DAC1_CH2 - if (&DACD2 == dacp) { - if ((dacp->params->dac->CR & DAC_CR_EN2) == 0U) { - rccDisableDAC1(false); - } - } -#endif - -#if STM32_DAC_USE_DAC2_CH1 - if (&DACD3 == dacp) { - if ((dacp->params->dac->CR & DAC_CR_EN1) == 0U) { - rccDisableDAC2(false); - } - } -#endif - -#if STM32_DAC_USE_DAC2_CH2 - if (&DACD4 == dacp) { - if ((dacp->params->dac->CR & DAC_CR_EN2) == 0U) { - rccDisableDAC2(false); - } - } -#endif - } -} - -/** - * @brief Outputs a value directly on a DAC channel. - * - * @param[in] dacp pointer to the @p DACDriver object - * @param[in] channel DAC channel number - * @param[in] sample value to be output - * - * @api - */ -void dac_lld_put_channel(DACDriver *dacp, - dacchannel_t channel, - dacsample_t sample) { - - switch (dacp->config->datamode) { - case DAC_DHRM_12BIT_RIGHT: -#if STM32_DAC_DUAL_MODE - case DAC_DHRM_12BIT_RIGHT_DUAL: -#endif - if (channel == 0U) { -#if STM32_DAC_DUAL_MODE - dacp->params->dac->DHR12R1 = (uint32_t)sample; -#else - *(&dacp->params->dac->DHR12R1 + dacp->params->dataoffset) = (uint32_t)sample; -#endif - } -#if (STM32_HAS_DAC1_CH2 || STM32_HAS_DAC2_CH2) - else { - dacp->params->dac->DHR12R2 = (uint32_t)sample; - } -#endif - break; - case DAC_DHRM_12BIT_LEFT: -#if STM32_DAC_DUAL_MODE - case DAC_DHRM_12BIT_LEFT_DUAL: -#endif - if (channel == 0U) { -#if STM32_DAC_DUAL_MODE - dacp->params->dac->DHR12L1 = (uint32_t)sample; -#else - *(&dacp->params->dac->DHR12L1 + dacp->params->dataoffset) = (uint32_t)sample; -#endif - } -#if (STM32_HAS_DAC1_CH2 || STM32_HAS_DAC2_CH2) - else { - dacp->params->dac->DHR12L2 = (uint32_t)sample; - } -#endif - break; - case DAC_DHRM_8BIT_RIGHT: -#if STM32_DAC_DUAL_MODE - case DAC_DHRM_8BIT_RIGHT_DUAL: -#endif - if (channel == 0U) { -#if STM32_DAC_DUAL_MODE - dacp->params->dac->DHR8R1 = (uint32_t)sample; -#else - *(&dacp->params->dac->DHR8R1 + dacp->params->dataoffset) = (uint32_t)sample; -#endif - } -#if (STM32_HAS_DAC1_CH2 || STM32_HAS_DAC2_CH2) - else { - dacp->params->dac->DHR8R2 = (uint32_t)sample; - } -#endif - break; - default: - osalDbgAssert(false, "unexpected DAC mode"); - break; - } -} - -/** - * @brief Starts a DAC conversion. - * @details Starts an asynchronous conversion operation. - * @note In @p DAC_DHRM_8BIT_RIGHT mode the parameters passed to the - * callback are wrong because two samples are packed in a single - * dacsample_t element. This will not be corrected, do not rely - * on those parameters. - * @note In @p DAC_DHRM_8BIT_RIGHT_DUAL mode two samples are treated - * as a single 16 bits sample and packed into a single dacsample_t - * element. The num_channels must be set to one in the group - * conversion configuration structure. - * - * @param[in] dacp pointer to the @p DACDriver object - * - * @notapi - */ -void dac_lld_start_conversion(DACDriver *dacp) { - uint32_t n, cr, dmamode; - - /* Number of DMA operations per buffer.*/ - n = dacp->depth * dacp->grpp->num_channels; - - /* Allocating the DMA channel.*/ - bool b = dmaStreamAllocate(dacp->params->dma, dacp->params->dmairqprio, - (stm32_dmaisr_t)dac_lld_serve_tx_interrupt, - (void *)dacp); - osalDbgAssert(!b, "stream already allocated"); - - /* DMA settings depend on the chosed DAC mode.*/ - switch (dacp->config->datamode) { - /* Sets the DAC data register */ - case DAC_DHRM_12BIT_RIGHT: - osalDbgAssert(dacp->grpp->num_channels == 1, "invalid number of channels"); - - dmaStreamSetPeripheral(dacp->params->dma, &dacp->params->dac->DHR12R1 + - dacp->params->dataoffset); - dmamode = dacp->params->dmamode | - STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; - break; - case DAC_DHRM_12BIT_LEFT: - osalDbgAssert(dacp->grpp->num_channels == 1, "invalid number of channels"); - - dmaStreamSetPeripheral(dacp->params->dma, &dacp->params->dac->DHR12L1 + - dacp->params->dataoffset); - dmamode = dacp->params->dmamode | - STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; - break; - case DAC_DHRM_8BIT_RIGHT: - osalDbgAssert(dacp->grpp->num_channels == 1, "invalid number of channels"); - - dmaStreamSetPeripheral(dacp->params->dma, &dacp->params->dac->DHR8R1 + - dacp->params->dataoffset); - dmamode = dacp->params->dmamode | - STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE; - - /* In this mode the size of the buffer is halved because two samples - packed in a single dacsample_t element.*/ - n = (n + 1) / 2; - break; -#if STM32_DAC_DUAL_MODE == TRUE - case DAC_DHRM_12BIT_RIGHT_DUAL: - osalDbgAssert(dacp->grpp->num_channels == 2, "invalid number of channels"); - - dmaStreamSetPeripheral(dacp->params->dma, &dacp->params->dac->DHR12RD); - dmamode = dacp->params->dmamode | - STM32_DMA_CR_PSIZE_WORD | STM32_DMA_CR_MSIZE_WORD; - n /= 2; - break; - case DAC_DHRM_12BIT_LEFT_DUAL: - osalDbgAssert(dacp->grpp->num_channels == 2, "invalid number of channels"); - - dmaStreamSetPeripheral(dacp->params->dma, &dacp->params->dac->DHR12LD); - dmamode = dacp->params->dmamode | - STM32_DMA_CR_PSIZE_WORD | STM32_DMA_CR_MSIZE_WORD; - n /= 2; - break; - case DAC_DHRM_8BIT_RIGHT_DUAL: - osalDbgAssert(dacp->grpp->num_channels == 1, "invalid number of channels"); - - dmaStreamSetPeripheral(dacp->params->dma, &dacp->params->dac->DHR8RD); - dmamode = dacp->params->dmamode | - STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; - n /= 2; - break; -#endif - default: - osalDbgAssert(false, "unexpected DAC mode"); - return; - } - - dmaStreamSetMemory0(dacp->params->dma, dacp->samples); - dmaStreamSetTransactionSize(dacp->params->dma, n); - dmaStreamSetMode(dacp->params->dma, dmamode | - STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | - STM32_DMA_CR_HTIE | STM32_DMA_CR_TCIE); - dmaStreamEnable(dacp->params->dma); - - /* DAC configuration.*/ -#if STM32_DAC_DUAL_MODE == FALSE - cr = DAC_CR_DMAEN1 | (dacp->grpp->trigger << 3) | DAC_CR_TEN1 | DAC_CR_EN1 | dacp->config->cr; - dacp->params->dac->CR &= dacp->params->regmask; - dacp->params->dac->CR |= cr << dacp->params->regshift; -#else - dacp->params->dac->CR = 0; - cr = DAC_CR_DMAEN1 | (dacp->grpp->trigger << 3) | DAC_CR_TEN1 | DAC_CR_EN1 | dacp->config->cr - | (dacp->grpp->trigger << 19) | DAC_CR_TEN2 | DAC_CR_EN2 | (dacp->config->cr << 16); - dacp->params->dac->CR = cr; -#endif -} - -/** - * @brief Stops an ongoing conversion. - * @details This function stops the currently ongoing conversion and returns - * the driver in the @p DAC_READY state. If there was no conversion - * being processed then the function does nothing. - * - * @param[in] dacp pointer to the @p DACDriver object - * - * @iclass - */ -void dac_lld_stop_conversion(DACDriver *dacp) { - - /* DMA channel disabled and released.*/ - dmaStreamDisable(dacp->params->dma); - dmaStreamRelease(dacp->params->dma); - -#if STM32_DAC_DUAL_MODE == FALSE - dacp->params->dac->CR &= dacp->params->regmask; - dacp->params->dac->CR |= (DAC_CR_EN1 | dacp->config->cr) << dacp->params->regshift; -#else - if ((dacp->config->datamode == DAC_DHRM_12BIT_RIGHT_DUAL) || - (dacp->config->datamode == DAC_DHRM_12BIT_LEFT_DUAL) || - (dacp->config->datamode == DAC_DHRM_8BIT_RIGHT_DUAL)) { - dacp->params->dac->CR = DAC_CR_EN2 | (dacp->config->cr << 16) | DAC_CR_EN1 | dacp->config->cr; - } - else { - dacp->params->dac->CR = DAC_CR_EN1 | dacp->config->cr; - } -#endif -} - -#endif /* HAL_USE_DAC */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/DACv1/dac_lld.h b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/DACv1/dac_lld.h deleted file mode 100644 index 03948b09c9..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/DACv1/dac_lld.h +++ /dev/null @@ -1,469 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/DACv1/dac_lld.h - * @brief STM32 DAC subsystem low level driver header. - * - * @addtogroup DAC - * @{ - */ - -#ifndef _DAC_LLD_H_ -#define _DAC_LLD_H_ - -#if HAL_USE_DAC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name DAC trigger modes - * @{ - */ -#define DAC_TRG_MASK 7U -#define DAC_TRG(n) (n) -#define DAC_TRG_EXT 6U -#define DAC_TRG_SW 7U -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief Enables the DAC dual mode. - * @note In dual mode DAC second channels cannot be accessed individually. - */ -#if !defined(STM32_DAC_DUAL_MODE) || defined(__DOXYGEN__) -#define STM32_DAC_DUAL_MODE FALSE -#endif - -/** - * @brief DAC1 CH1 driver enable switch. - * @details If set to @p TRUE the support for DAC1 channel 1 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_DAC_USE_DAC1_CH1) || defined(__DOXYGEN__) -#define STM32_DAC_USE_DAC1_CH1 FALSE -#endif - -/** - * @brief DAC1 CH2 driver enable switch. - * @details If set to @p TRUE the support for DAC1 channel 2 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_DAC_USE_DAC1_CH2) || defined(__DOXYGEN__) -#define STM32_DAC_USE_DAC1_CH2 FALSE -#endif - -/** - * @brief DAC2 CH1 driver enable switch. - * @details If set to @p TRUE the support for DAC2 channel 1 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_DAC_USE_DAC2_CH1) || defined(__DOXYGEN__) -#define STM32_DAC_USE_DAC2_CH1 FALSE -#endif - -/** - * @brief DAC2 CH2 driver enable switch. - * @details If set to @p TRUE the support for DAC2 channel 2 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_DAC_USE_DAC2_CH2) || defined(__DOXYGEN__) -#define STM32_DAC_USE_DAC2_CH2 FALSE -#endif - -/** - * @brief DAC1 CH1 interrupt priority level setting. - */ -#if !defined(STM32_DAC_DAC1_CH1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 -#endif - -/** - * @brief DAC1 CH2 interrupt priority level setting. - */ -#if !defined(STM32_DAC_DAC1_CH2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 -#endif - -/** - * @brief DAC2 CH1 interrupt priority level setting. - */ -#if !defined(STM32_DAC_DAC2_CH1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_DAC_DAC2_CH1_IRQ_PRIORITY 10 -#endif - -/** - * @brief DAC2 CH2 interrupt priority level setting. - */ -#if !defined(STM32_DAC_DAC2_CH2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_DAC_DAC2_CH2_IRQ_PRIORITY 10 -#endif - -/** - * @brief DAC1 CH1 DMA priority (0..3|lowest..highest). - */ -#if !defined(STM32_DAC_DAC1_CH1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 -#endif - -/** - * @brief DAC1 CH2 DMA priority (0..3|lowest..highest). - */ -#if !defined(STM32_DAC_DAC1_CH2_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 -#endif - -/** - * @brief DAC2 CH1 DMA priority (0..3|lowest..highest). - */ -#if !defined(STM32_DAC_DAC2_CH1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_DAC_DAC2_CH1_DMA_PRIORITY 2 -#endif - -/** - * @brief DAC2 CH2 DMA priority (0..3|lowest..highest). - */ -#if !defined(STM32_DAC_DAC2_CH2_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_DAC_DAC2_CH2_DMA_PRIORITY 2 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_DAC_USE_DAC1_CH1 && !STM32_HAS_DAC1_CH1 -#error "DAC1 CH1 not present in the selected device" -#endif - -#if STM32_DAC_USE_DAC1_CH2 && !STM32_HAS_DAC1_CH2 -#error "DAC1 CH2 not present in the selected device" -#endif - -#if STM32_DAC_USE_DAC2_CH1 && !STM32_HAS_DAC2_CH1 -#error "DAC2 CH1 not present in the selected device" -#endif - -#if STM32_DAC_USE_DAC2_CH2 && !STM32_HAS_DAC2_CH2 -#error "DAC2 CH2 not present in the selected device" -#endif - -#if (STM32_DAC_USE_DAC1_CH2 || STM32_DAC_USE_DAC2_CH2) && STM32_DAC_DUAL_MODE -#error "DACx CH2 cannot be used independently in dual mode" -#endif - -#if !STM32_DAC_USE_DAC1_CH1 && !STM32_DAC_USE_DAC1_CH2 && \ - !STM32_DAC_USE_DAC2_CH1 && !STM32_DAC_USE_DAC2_CH2 -#error "DAC driver activated but no DAC peripheral assigned" -#endif - -/* The following checks are only required when there is a DMA able to - reassign streams to different channels.*/ -#if STM32_ADVANCED_DMA -/* Check on the presence of the DMA streams settings in mcuconf.h.*/ -#if STM32_DAC_USE_DAC1_CH1 && !defined(STM32_DAC_DAC1_CH1_DMA_STREAM) -#error "DAC1 CH1 DMA stream not defined" -#endif - -#if STM32_DAC_USE_DAC1_CH2 && !defined(STM32_DAC_DAC1_CH2_DMA_STREAM) -#error "DAC1 CH2 DMA stream not defined" -#endif - -#if STM32_DAC_USE_DAC2_CH1 && !defined(STM32_DAC_DAC2_CH1_DMA_STREAM) -#error "DAC2 CH1 DMA stream not defined" -#endif - -#if STM32_DAC_USE_DAC2_CH2 && !defined(STM32_DAC_DAC2_CH2_DMA_STREAM) -#error "DAC2 CH2 DMA stream not defined" -#endif - -/* Check on the validity of the assigned DMA channels.*/ -#if STM32_DAC_USE_DAC1_CH1 && \ - !STM32_DMA_IS_VALID_ID(STM32_DAC_DAC1_CH1_DMA_STREAM, STM32_DAC1_CH1_DMA_MSK) -#error "invalid DMA stream associated to DAC1 CH1" -#endif - -#if STM32_DAC_USE_DAC1_CH2 && \ - !STM32_DMA_IS_VALID_ID(STM32_DAC_DAC1_CH2_DMA_STREAM, STM32_DAC1_CH2_DMA_MSK) -#error "invalid DMA stream associated to DAC1 CH2" -#endif - -#if STM32_DAC_USE_DAC2_CH1 && \ - !STM32_DMA_IS_VALID_ID(STM32_DAC_DAC2_CH1_DMA_STREAM, STM32_DAC2_CH1_DMA_MSK) -#error "invalid DMA stream associated to DAC2 CH1" -#endif - -#if STM32_DAC_USE_DAC2_CH2 && \ - !STM32_DMA_IS_VALID_ID(STM32_DAC_DAC2_CH2_DMA_STREAM, STM32_DAC2_CH2_DMA_MSK) -#error "invalid DMA stream associated to DAC2 CH2" -#endif -#endif /* STM32_ADVANCED_DMA */ - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif - -/** - * @brief Max DAC channels. - */ -#if STM32_DAC_DUAL_MODE == FALSE -#define DAC_MAX_CHANNELS 1 -#else -#define DAC_MAX_CHANNELS 2 -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a DAC channel index. - */ -typedef uint32_t dacchannel_t; - -/** - * @brief DAC channel parameters type. - */ -typedef struct { - /** - * @brief Pointer to the DAC registers block. - */ - DAC_TypeDef *dac; - /** - * @brief DAC data registers offset. - */ - uint32_t dataoffset; - /** - * @brief DAC CR register bit offset. - */ - uint32_t regshift; - /** - * @brief DAC CR register mask. - */ - uint32_t regmask; - /** - * @brief Associated DMA. - */ - const stm32_dma_stream_t *dma; - /** - * @brief Mode bits for the DMA. - */ - uint32_t dmamode; - /** - * @brief DMA channel IRQ priority. - */ - uint32_t dmairqprio; -} dacparams_t; - -/** - * @brief Type of a structure representing an DAC driver. - */ -typedef struct DACDriver DACDriver; - -/** - * @brief Type representing a DAC sample. - */ -typedef uint16_t dacsample_t; - -/** - * @brief Possible DAC failure causes. - * @note Error codes are architecture dependent and should not relied - * upon. - */ -typedef enum { - DAC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */ - DAC_ERR_UNDERFLOW = 1 /**< DAC overflow condition. */ -} dacerror_t; - -/** - * @brief DAC notification callback type. - * - * @param[in] dacp pointer to the @p DACDriver object triggering the - * @param[in] buffer pointer to the next semi-buffer to be filled - * @param[in] n number of buffer rows available starting from @p buffer - * callback - */ -typedef void (*daccallback_t)(DACDriver *dacp, - const dacsample_t *buffer, - size_t n); - -/** - * @brief ADC error callback type. - * - * @param[in] dacp pointer to the @p DACDriver object triggering the - * callback - * @param[in] err ADC error code - */ -typedef void (*dacerrorcallback_t)(DACDriver *dacp, dacerror_t err); - -/** - * @brief Samples alignment and size mode. - */ -typedef enum { - DAC_DHRM_12BIT_RIGHT = 0, - DAC_DHRM_12BIT_LEFT = 1, - DAC_DHRM_8BIT_RIGHT = 2, -#if STM32_DAC_DUAL_MODE && !defined(__DOXYGEN__) - DAC_DHRM_12BIT_RIGHT_DUAL = 3, - DAC_DHRM_12BIT_LEFT_DUAL = 4, - DAC_DHRM_8BIT_RIGHT_DUAL = 5 -#endif -} dacdhrmode_t; - -/** - * @brief DAC Conversion group structure. - */ -typedef struct { - /** - * @brief Number of DAC channels. - */ - uint32_t num_channels; - /** - * @brief Operation complete callback or @p NULL. - */ - daccallback_t end_cb; - /** - * @brief Error handling callback or @p NULL. - */ - dacerrorcallback_t error_cb; - /* End of the mandatory fields.*/ - /** - * @brief DAC initialization data. - * @note This field contains the (not shifted) value to be put into the - * TSEL field of the DAC CR register during initialization. All - * other fields are handled internally. - */ - uint32_t trigger; -} DACConversionGroup; - -/** - * @brief Driver configuration structure. - */ -typedef struct { - /* End of the mandatory fields.*/ - /** - * @brief Initial output on DAC channels. - */ - dacsample_t init; - /** - * @brief DAC data holding register mode. - */ - dacdhrmode_t datamode; - /** - * @brief DAC control register. - */ - uint16_t cr; -} DACConfig; - -/** - * @brief Structure representing a DAC driver. - */ -struct DACDriver { - /** - * @brief Driver state. - */ - dacstate_t state; - /** - * @brief Conversion group. - */ - const DACConversionGroup *grpp; - /** - * @brief Samples buffer pointer. - */ - const dacsample_t *samples; - /** - * @brief Samples buffer size. - */ - uint16_t depth; - /** - * @brief Current configuration data. - */ - const DACConfig *config; -#if DAC_USE_WAIT || defined(__DOXYGEN__) - /** - * @brief Waiting thread. - */ - thread_reference_t thread; -#endif /* DAC_USE_WAIT */ -#if DAC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the bus. - */ - mutex_t mutex; -#endif /* DAC_USE_MUTUAL_EXCLUSION */ -#if defined(DAC_DRIVER_EXT_FIELDS) - DAC_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief DAC channel parameters. - */ - const dacparams_t *params; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_DAC_USE_DAC1_CH1 && !defined(__DOXYGEN__) -extern DACDriver DACD1; -#endif - -#if STM32_DAC_USE_DAC1_CH2 && !STM32_DAC_DUAL_MODE && !defined(__DOXYGEN__) -extern DACDriver DACD2; -#endif - -#if STM32_DAC_USE_DAC2_CH1 && !defined(__DOXYGEN__) -extern DACDriver DACD3; -#endif - -#if STM32_DAC_USE_DAC2_CH2 && !STM32_DAC_DUAL_MODE && !defined(__DOXYGEN__) -extern DACDriver DACD4; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void dac_lld_init(void); - void dac_lld_start(DACDriver *dacp); - void dac_lld_stop(DACDriver *dacp); - void dac_lld_put_channel(DACDriver *dacp, - dacchannel_t channel, - dacsample_t sample); - void dac_lld_start_conversion(DACDriver *dacp); - void dac_lld_stop_conversion(DACDriver *dacp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_DAC */ - -#endif /* _DAC_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/DMAv1/notes.txt b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/DMAv1/notes.txt deleted file mode 100644 index 376c69fc7b..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/DMAv1/notes.txt +++ /dev/null @@ -1,25 +0,0 @@ -STM32 DMAv1 driver. - -Driver capability: - -- The driver supports the STM32 traditional DMA controller in the following - configurations: 5ch, 7ch, 7ch+5ch, 7ch+7ch. -- Support for automatic the channel selection through the CSELR register. -- For devices without CSELR register it is possible to select channels but - the SYSCFG CFGR register is not configured, the user has to configure it - before starting the DMA driver. -- The driver supports shared ISR handlers with a quirk: the IRQ priority is - established by the first allocated channel among the channels sharing the - ISR. - -The file registry must export: - -STM32_ADVANCED_DMA - TRUE not used by the DMA drivers but other - drivers use it to enable checks on DMA - channels. Probably will be removed in the - future. -STM32_DMA_SUPPORTS_CSELR - TRUE if the DMA have a CSELR register. -STM32_DMAn_NUM_CHANNELS - Number of channels in DMAs "n" (1..2). -STM32_DMAn_CHx_HANDLER - Vector name for IRQ "x" (1..7). If the macro - is not exported then the ISR is not declared. -STM32_DMAn_CHx_NUMBER - Vector number for IRQ "x" (1..7). diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c deleted file mode 100644 index 427c62285b..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c +++ /dev/null @@ -1,557 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F3xx/stm32_dma.c - * @brief DMA helper driver code. - * - * @addtogroup STM32F3xx_DMA - * @details DMA sharing helper driver. In the STM32 the DMA streams are a - * shared resource, this driver allows to allocate and free DMA - * streams at runtime in order to allow all the other device - * drivers to coordinate the access to the resource. - * @note The DMA ISR handlers are all declared into this module because - * sharing, the various device drivers can associate a callback to - * ISRs when allocating streams. - * @{ - */ - -#include "hal.h" - -/* The following macro is only defined if some driver requiring DMA services - has been enabled.*/ -#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/** - * @brief Mask of the DMA1 streams in @p dma_streams_mask. - */ -#define STM32_DMA1_STREAMS_MASK ((1U << STM32_DMA1_NUM_CHANNELS) - 1U) - -/** - * @brief Mask of the DMA2 streams in @p dma_streams_mask. - */ -#define STM32_DMA2_STREAMS_MASK (((1U << STM32_DMA2_NUM_CHANNELS) - \ - 1U) << STM32_DMA1_NUM_CHANNELS) - -/** - * @brief Post-reset value of the stream CCR register. - */ -#define STM32_DMA_CCR_RESET_VALUE 0x00000000U - -#if STM32_DMA_SUPPORTS_CSELR == TRUE - -#if defined(DMA1_CSELR) -#define ADDR_DMA1_CSELR &DMA1_CSELR->CSELR -#else -#define ADDR_DMA1_CSELR &DMA1->CSELR -#endif - -#if defined(DMA2_CSELR) -#define ADDR_DMA2_CSELR &DMA2_CSELR->CSELR -#else -#define ADDR_DMA2_CSELR &DMA2->CSELR -#endif - -#else /* !defined(DMA1_CSELR) */ - -#define ADDR_DMA1_CSELR NULL -#define ADDR_DMA2_CSELR NULL - -#endif /* !defined(DMA1_CSELR) */ - -/* - * Default ISR collision masks. - */ -#if !defined(DMA1_CH1_CMASK) -#define DMA1_CH1_CMASK 0x00000001U -#endif - -#if !defined(DMA1_CH2_CMASK) -#define DMA1_CH2_CMASK 0x00000002U -#endif - -#if !defined(DMA1_CH3_CMASK) -#define DMA1_CH3_CMASK 0x00000004U -#endif - -#if !defined(DMA1_CH4_CMASK) -#define DMA1_CH4_CMASK 0x00000008U -#endif - -#if !defined(DMA1_CH5_CMASK) -#define DMA1_CH5_CMASK 0x00000010U -#endif - -#if !defined(DMA1_CH6_CMASK) -#define DMA1_CH6_CMASK 0x00000020U -#endif - -#if !defined(DMA1_CH7_CMASK) -#define DMA1_CH7_CMASK 0x00000040U -#endif - -#if !defined(DMA2_CH1_CMASK) -#define DMA2_CH1_CMASK 0x00000080U -#endif - -#if !defined(DMA2_CH2_CMASK) -#define DMA2_CH2_CMASK 0x00000100U -#endif - -#if !defined(DMA2_CH3_CMASK) -#define DMA2_CH3_CMASK 0x00000200U -#endif - -#if !defined(DMA2_CH4_CMASK) -#define DMA2_CH4_CMASK 0x00000400U -#endif - -#if !defined(DMA2_CH5_CMASK) -#define DMA2_CH5_CMASK 0x00000800U -#endif - -#if !defined(DMA2_CH6_CMASK) -#define DMA2_CH6_CMASK 0x00001000U -#endif - -#if !defined(DMA2_CH7_CMASK) -#define DMA2_CH7_CMASK 0x00002000U -#endif - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief DMA streams descriptors. - * @details This table keeps the association between an unique stream - * identifier and the involved physical registers. - * @note Don't use this array directly, use the appropriate wrapper macros - * instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc. - */ -const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = { - {DMA1, DMA1_Channel1, DMA1_CH1_CMASK, ADDR_DMA1_CSELR, 0, 0, STM32_DMA1_CH1_NUMBER}, - {DMA1, DMA1_Channel2, DMA1_CH2_CMASK, ADDR_DMA1_CSELR, 4, 1, STM32_DMA1_CH2_NUMBER}, - {DMA1, DMA1_Channel3, DMA1_CH3_CMASK, ADDR_DMA1_CSELR, 8, 2, STM32_DMA1_CH3_NUMBER}, - {DMA1, DMA1_Channel4, DMA1_CH4_CMASK, ADDR_DMA1_CSELR, 12, 3, STM32_DMA1_CH4_NUMBER}, - {DMA1, DMA1_Channel5, DMA1_CH5_CMASK, ADDR_DMA1_CSELR, 16, 4, STM32_DMA1_CH5_NUMBER}, -#if STM32_DMA1_NUM_CHANNELS > 5 - {DMA1, DMA1_Channel6, DMA1_CH6_CMASK, ADDR_DMA1_CSELR, 20, 5, STM32_DMA1_CH6_NUMBER}, -#if STM32_DMA1_NUM_CHANNELS > 6 - {DMA1, DMA1_Channel7, DMA1_CH7_CMASK, ADDR_DMA1_CSELR, 24, 6, STM32_DMA1_CH7_NUMBER}, -#if STM32_DMA2_NUM_CHANNELS > 0 - {DMA2, DMA2_Channel1, DMA2_CH1_CMASK, ADDR_DMA2_CSELR, 0, 7, STM32_DMA2_CH1_NUMBER}, - {DMA2, DMA2_Channel2, DMA2_CH2_CMASK, ADDR_DMA2_CSELR, 4, 8, STM32_DMA2_CH2_NUMBER}, - {DMA2, DMA2_Channel3, DMA2_CH3_CMASK, ADDR_DMA2_CSELR, 8, 9, STM32_DMA2_CH3_NUMBER}, - {DMA2, DMA2_Channel4, DMA2_CH4_CMASK, ADDR_DMA2_CSELR, 12, 10, STM32_DMA2_CH4_NUMBER}, - {DMA2, DMA2_Channel5, DMA2_CH5_CMASK, ADDR_DMA2_CSELR, 16, 11, STM32_DMA2_CH5_NUMBER}, -#if STM32_DMA2_NUM_CHANNELS > 5 - {DMA2, DMA2_Channel6, DMA2_CH6_CMASK, ADDR_DMA2_CSELR, 20, 12, STM32_DMA2_CH6_NUMBER}, -#if STM32_DMA2_NUM_CHANNELS > 6 - {DMA2, DMA2_Channel7, DMA2_CH7_CMASK, ADDR_DMA2_CSELR, 24, 13, STM32_DMA2_CH7_NUMBER}, -#endif -#endif -#endif -#endif -#endif -}; - -/** - * @brief DMA IRQ redirectors. - */ -dma_isr_redir_t _stm32_dma_isr_redir[STM32_DMA_STREAMS]; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief Mask of the allocated streams. - */ -static uint32_t dma_streams_mask; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if defined(STM32_DMA1_CH1_HANDLER) || defined(__DOXYGEN__) -/** - * @brief DMA1 stream 1 shared ISR. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_DMA1_CH1_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - dmaServeInterrupt(STM32_DMA1_STREAM1); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if defined(STM32_DMA1_CH2_HANDLER) || defined(__DOXYGEN__) -/** - * @brief DMA1 stream 2 shared ISR. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_DMA1_CH2_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - dmaServeInterrupt(STM32_DMA1_STREAM2); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if defined(STM32_DMA1_CH3_HANDLER) || defined(__DOXYGEN__) -/** - * @brief DMA1 stream 3 shared ISR. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_DMA1_CH3_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - dmaServeInterrupt(STM32_DMA1_STREAM3); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if defined(STM32_DMA1_CH4_HANDLER) || defined(__DOXYGEN__) -/** - * @brief DMA1 stream 4 shared ISR. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_DMA1_CH4_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - dmaServeInterrupt(STM32_DMA1_STREAM4); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if defined(STM32_DMA1_CH5_HANDLER) || defined(__DOXYGEN__) -/** - * @brief DMA1 stream 5 shared ISR. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_DMA1_CH5_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - dmaServeInterrupt(STM32_DMA1_STREAM5); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if defined(STM32_DMA1_CH6_HANDLER) || defined(__DOXYGEN__) -/** - * @brief DMA1 stream 6 shared ISR. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_DMA1_CH6_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - dmaServeInterrupt(STM32_DMA1_STREAM6); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if defined(STM32_DMA1_CH7_HANDLER) || defined(__DOXYGEN__) -/** - * @brief DMA1 stream 7 shared ISR. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_DMA1_CH7_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - dmaServeInterrupt(STM32_DMA1_STREAM7); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if defined(STM32_DMA2_CH1_HANDLER) || defined(__DOXYGEN__) -/** - * @brief DMA2 stream 1 shared ISR. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_DMA2_CH1_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - dmaServeInterrupt(STM32_DMA2_STREAM1); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if defined(STM32_DMA2_CH2_HANDLER) || defined(__DOXYGEN__) -/** - * @brief DMA2 stream 2 shared ISR. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_DMA2_CH2_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - dmaServeInterrupt(STM32_DMA2_STREAM2); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if defined(STM32_DMA2_CH3_HANDLER) || defined(__DOXYGEN__) -/** - * @brief DMA2 stream 3 shared ISR. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_DMA2_CH3_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - dmaServeInterrupt(STM32_DMA2_STREAM3); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if defined(STM32_DMA2_CH4_HANDLER) || defined(__DOXYGEN__) -/** - * @brief DMA2 stream 4 shared ISR. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_DMA2_CH4_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - dmaServeInterrupt(STM32_DMA2_STREAM4); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if defined(STM32_DMA2_CH5_HANDLER) || defined(__DOXYGEN__) -/** - * @brief DMA2 stream 5 shared ISR. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_DMA2_CH5_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - dmaServeInterrupt(STM32_DMA2_STREAM5); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if defined(STM32_DMA2_CH6_HANDLER) || defined(__DOXYGEN__) -/** - * @brief DMA2 stream 6 shared ISR. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_DMA2_CH6_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - dmaServeInterrupt(STM32_DMA2_STREAM6); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if defined(STM32_DMA2_CH7_HANDLER) || defined(__DOXYGEN__) -/** - * @brief DMA2 stream 7 shared ISR. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_DMA2_CH7_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - dmaServeInterrupt(STM32_DMA2_STREAM7); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief STM32 DMA helper initialization. - * - * @init - */ -void dmaInit(void) { - int i; - - dma_streams_mask = 0U; - for (i = 0; i < STM32_DMA_STREAMS; i++) { - _stm32_dma_streams[i].channel->CCR = 0U; - _stm32_dma_isr_redir[i].dma_func = NULL; - } - DMA1->IFCR = 0xFFFFFFFFU; -#if STM32_DMA2_NUM_CHANNELS > 0 - DMA2->IFCR = 0xFFFFFFFFU; -#endif -} - -/** - * @brief Allocates a DMA stream. - * @details The stream is allocated and, if required, the DMA clock enabled. - * The function also enables the IRQ vector associated to the stream - * and initializes its priority. - * @pre The stream must not be already in use or an error is returned. - * @post The stream is allocated and the default ISR handler redirected - * to the specified function. - * @post The stream ISR vector is enabled and its priority configured. - * @post The stream must be freed using @p dmaStreamRelease() before it can - * be reused with another peripheral. - * @post The stream is in its post-reset state. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] priority IRQ priority mask for the DMA stream - * @param[in] func handling function pointer, can be @p NULL - * @param[in] param a parameter to be passed to the handling function - * @return The operation status. - * @retval false no error, stream taken. - * @retval true error, stream already taken. - * - * @special - */ -bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp, - uint32_t priority, - stm32_dmaisr_t func, - void *param) { - - osalDbgCheck(dmastp != NULL); - - /* Checks if the stream is already taken.*/ - if ((dma_streams_mask & (1U << dmastp->selfindex)) != 0U) - return true; - - /* Installs the DMA handler.*/ - _stm32_dma_isr_redir[dmastp->selfindex].dma_func = func; - _stm32_dma_isr_redir[dmastp->selfindex].dma_param = param; - - /* Enabling DMA clocks required by the current streams set.*/ - if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0U) { - rccEnableDMA1(false); - } -#if STM32_DMA2_NUM_CHANNELS > 0 - if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0U) { - rccEnableDMA2(false); - } -#endif - - /* Putting the stream in a safe state.*/ - dmaStreamDisable(dmastp); - dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE; - - /* Enables the associated IRQ vector if not alread enabled and if a - callback is defined.*/ - if (((dma_streams_mask & dmastp->cmask) == 0U) && - (func != NULL)) { - nvicEnableVector(dmastp->vector, priority); - } - - /* Marks the stream as allocated.*/ - dma_streams_mask |= (1U << dmastp->selfindex); - - return false; -} - -/** - * @brief Releases a DMA stream. - * @details The stream is freed and, if required, the DMA clock disabled. - * Trying to release a unallocated stream is an illegal operation - * and is trapped if assertions are enabled. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post The stream is again available. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * - * @special - */ -void dmaStreamRelease(const stm32_dma_stream_t *dmastp) { - - osalDbgCheck(dmastp != NULL); - - /* Check if the streams is not taken.*/ - osalDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0U, - "not allocated"); - - /* Marks the stream as not allocated.*/ - dma_streams_mask &= ~(1U << dmastp->selfindex); - - /* Disables the associated IRQ vector if it is no more in use.*/ - if ((dma_streams_mask & dmastp->cmask) == 0U) { - nvicDisableVector(dmastp->vector); - } - - /* Removes the DMA handler.*/ - _stm32_dma_isr_redir[dmastp->selfindex].dma_func = NULL; - _stm32_dma_isr_redir[dmastp->selfindex].dma_param = NULL; - - /* Shutting down clocks that are no more required, if any.*/ - if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0U) { - rccDisableDMA1(false); - } -#if STM32_DMA2_NUM_CHANNELS > 0 - if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0U) { - rccDisableDMA2(false); - } -#endif -} - -#endif /* STM32_DMA_REQUIRED */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.h b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.h deleted file mode 100644 index 75b6542313..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.h +++ /dev/null @@ -1,480 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file DMAv1/stm32_dma.h - * @brief DMA helper driver header. - * @note This driver uses the new naming convention used for the STM32F2xx - * so the "DMA channels" are referred as "DMA streams". - * - * @addtogroup STM32_DMA - * @{ - */ - -#ifndef _STM32_DMA_H_ -#define _STM32_DMA_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief DMA capability. - * @details if @p TRUE then the DMA is able of burst transfers, FIFOs, - * scatter gather and other advanced features. - */ -#define STM32_DMA_ADVANCED FALSE - -/** - * @brief Total number of DMA streams. - * @details This is the total number of streams among all the DMA units. - */ -#define STM32_DMA_STREAMS (STM32_DMA1_NUM_CHANNELS + \ - STM32_DMA2_NUM_CHANNELS) - -/** - * @brief Mask of the ISR bits passed to the DMA callback functions. - */ -#define STM32_DMA_ISR_MASK 0x0E - -/** - * @brief From stream number to shift factor in @p ISR and @p IFCR registers. - */ -#define STM32_DMA_ISR_SHIFT(stream) (((stream) - 1U) * 4U) - -/** - * @brief Returns the request line associated to the specified stream. - * @note In some STM32 manuals the request line is named confusingly - * channel. - * - * @param[in] id the unique numeric stream identifier - * @param[in] c a stream/request association word, one request per - * nibble - * @return Returns the request associated to the stream. - */ -#define STM32_DMA_GETCHANNEL(id, c) (((c) >> (((id) % 7U) * 4U)) & 15U) - -/** - * @brief Checks if a DMA priority is within the valid range. - * @param[in] prio DMA priority - * - * @retval The check result. - * @retval false invalid DMA priority. - * @retval true correct DMA priority. - */ -#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0U) && ((prio) <= 3U)) - -/** - * @brief Returns an unique numeric identifier for a DMA stream. - * - * @param[in] dma the DMA unit number - * @param[in] stream the stream number - * @return An unique numeric stream identifier. - */ -#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1U) * 7U) + ((stream) - 1U)) - -/** - * @brief Returns a DMA stream identifier mask. - * - * - * @param[in] dma the DMA unit number - * @param[in] stream the stream number - * @return A DMA stream identifier mask. - */ -#define STM32_DMA_STREAM_ID_MSK(dma, stream) \ - (1U << STM32_DMA_STREAM_ID(dma, stream)) - -/** - * @brief Checks if a DMA stream unique identifier belongs to a mask. - * - * @param[in] id the stream numeric identifier - * @param[in] mask the stream numeric identifiers mask - * - * @retval The check result. - * @retval false id does not belong to the mask. - * @retval true id belongs to the mask. - */ -#define STM32_DMA_IS_VALID_ID(id, mask) (((1U << (id)) & (mask))) - -/** - * @name DMA streams identifiers - * @{ - */ -/** - * @brief Returns a pointer to a stm32_dma_stream_t structure. - * - * @param[in] id the stream numeric identifier - * @return A pointer to the stm32_dma_stream_t constant structure - * associated to the DMA stream. - */ -#define STM32_DMA_STREAM(id) (&_stm32_dma_streams[id]) - -#define STM32_DMA1_STREAM1 STM32_DMA_STREAM(0) -#define STM32_DMA1_STREAM2 STM32_DMA_STREAM(1) -#define STM32_DMA1_STREAM3 STM32_DMA_STREAM(2) -#define STM32_DMA1_STREAM4 STM32_DMA_STREAM(3) -#define STM32_DMA1_STREAM5 STM32_DMA_STREAM(4) -#define STM32_DMA1_STREAM6 STM32_DMA_STREAM(5) -#define STM32_DMA1_STREAM7 STM32_DMA_STREAM(6) -#define STM32_DMA2_STREAM1 STM32_DMA_STREAM(7) -#define STM32_DMA2_STREAM2 STM32_DMA_STREAM(8) -#define STM32_DMA2_STREAM3 STM32_DMA_STREAM(9) -#define STM32_DMA2_STREAM4 STM32_DMA_STREAM(10) -#define STM32_DMA2_STREAM5 STM32_DMA_STREAM(11) -#define STM32_DMA2_STREAM6 STM32_DMA_STREAM(12) -#define STM32_DMA2_STREAM7 STM32_DMA_STREAM(13) -/** @} */ - -/** - * @name CR register constants common to all DMA types - * @{ - */ -#define STM32_DMA_CR_EN DMA_CCR_EN -#define STM32_DMA_CR_TEIE DMA_CCR_TEIE -#define STM32_DMA_CR_HTIE DMA_CCR_HTIE -#define STM32_DMA_CR_TCIE DMA_CCR_TCIE -#define STM32_DMA_CR_DIR_MASK (DMA_CCR_DIR | DMA_CCR_MEM2MEM) -#define STM32_DMA_CR_DIR_P2M 0U -#define STM32_DMA_CR_DIR_M2P DMA_CCR_DIR -#define STM32_DMA_CR_DIR_M2M DMA_CCR_MEM2MEM -#define STM32_DMA_CR_CIRC DMA_CCR_CIRC -#define STM32_DMA_CR_PINC DMA_CCR_PINC -#define STM32_DMA_CR_MINC DMA_CCR_MINC -#define STM32_DMA_CR_PSIZE_MASK DMA_CCR_PSIZE -#define STM32_DMA_CR_PSIZE_BYTE 0U -#define STM32_DMA_CR_PSIZE_HWORD DMA_CCR_PSIZE_0 -#define STM32_DMA_CR_PSIZE_WORD DMA_CCR_PSIZE_1 -#define STM32_DMA_CR_MSIZE_MASK DMA_CCR_MSIZE -#define STM32_DMA_CR_MSIZE_BYTE 0U -#define STM32_DMA_CR_MSIZE_HWORD DMA_CCR_MSIZE_0 -#define STM32_DMA_CR_MSIZE_WORD DMA_CCR_MSIZE_1 -#define STM32_DMA_CR_SIZE_MASK (STM32_DMA_CR_PSIZE_MASK | \ - STM32_DMA_CR_MSIZE_MASK) -#define STM32_DMA_CR_PL_MASK DMA_CCR_PL -#define STM32_DMA_CR_PL(n) ((n) << 12U) -/** @} */ - -/** - * @name Request line selector macro - * @{ - */ -#if STM32_DMA_SUPPORTS_CSELR || defined(__DOXYGEN__) -#define STM32_DMA_CR_CHSEL_MASK (15U << 16U) -#define STM32_DMA_CR_CHSEL(n) ((n) << 16U) -#else -#define STM32_DMA_CR_CHSEL_MASK 0U -#define STM32_DMA_CR_CHSEL(n) 0U -#endif -/** @} */ - -/** - * @name CR register constants only found in enhanced DMA - * @{ - */ -#define STM32_DMA_CR_DMEIE 0U /**< @brief Ignored by normal DMA. */ -/** @} */ - -/** - * @name Status flags passed to the ISR callbacks - * @{ - */ -#define STM32_DMA_ISR_FEIF 0U -#define STM32_DMA_ISR_DMEIF 0U -#define STM32_DMA_ISR_TEIF DMA_ISR_TEIF1 -#define STM32_DMA_ISR_HTIF DMA_ISR_HTIF1 -#define STM32_DMA_ISR_TCIF DMA_ISR_TCIF1 -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !defined(STM32_DMA_SUPPORTS_CSELR) -#error "STM32_DMA_SUPPORTS_CSELR not defined in registry" -#endif - -#if !defined(STM32_DMA1_NUM_CHANNELS) -#error "STM32_DMA1_NUM_CHANNELS not defined in registry" -#endif - -#if !defined(STM32_DMA2_NUM_CHANNELS) -#error "STM32_DMA2_NUM_CHANNELS not defined in registry" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief STM32 DMA stream descriptor structure. - */ -typedef struct { - DMA_TypeDef *dma ; /**< @brief Associated DMA. */ - DMA_Channel_TypeDef *channel; /**< @brief Associated DMA channel. */ - uint32_t cmask; /**< @brief Mask of streams sharing - the same ISR. */ - volatile uint32_t *cselr; /**< @brief Associated CSELR reg. */ - uint8_t shift; /**< @brief Bit offset in ISR, IFCR - and CSELR registers. */ - uint8_t selfindex; /**< @brief Index to self in array. */ - uint8_t vector; /**< @brief Associated IRQ vector. */ -} stm32_dma_stream_t; - -/** - * @brief STM32 DMA ISR function type. - * - * @param[in] p parameter for the registered function - * @param[in] flags pre-shifted content of the ISR register, the bits - * are aligned to bit zero - */ -typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); - -/** - * @brief DMA ISR redirector type. - */ -typedef struct { - stm32_dmaisr_t dma_func; /**< @brief DMA callback function. */ - void *dma_param; /**< @brief DMA callback parameter. */ -} dma_isr_redir_t; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Associates a peripheral data register to a DMA stream. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] addr value to be written in the CPAR register - * - * @special - */ -#define dmaStreamSetPeripheral(dmastp, addr) { \ - (dmastp)->channel->CPAR = (uint32_t)(addr); \ -} - -/** - * @brief Associates a memory destination to a DMA stream. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] addr value to be written in the CMAR register - * - * @special - */ -#define dmaStreamSetMemory0(dmastp, addr) { \ - (dmastp)->channel->CMAR = (uint32_t)(addr); \ -} - -/** - * @brief Sets the number of transfers to be performed. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] size value to be written in the CNDTR register - * - * @special - */ -#define dmaStreamSetTransactionSize(dmastp, size) { \ - (dmastp)->channel->CNDTR = (uint32_t)(size); \ -} - -/** - * @brief Returns the number of transfers to be performed. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @return The number of transfers to be performed. - * - * @special - */ -#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR)) - -/** - * @brief Programs the stream mode settings. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] mode value to be written in the CCR register - * - * @special - */ -#if STM32_DMA_SUPPORTS_CSELR || defined(__DOXYGEN__) -#define dmaStreamSetMode(dmastp, mode) { \ - uint32_t cselr = *(dmastp)->cselr; \ - cselr &= ~(0x0000000FU << (dmastp)->shift); \ - cselr |= (((uint32_t)(mode) >> 16U) << (dmastp)->shift); \ - *(dmastp)->cselr = cselr; \ - (dmastp)->channel->CCR = (uint32_t)(mode); \ -} -#else -#define dmaStreamSetMode(dmastp, mode) { \ - (dmastp)->channel->CCR = (uint32_t)(mode); \ -} -#endif - -/** - * @brief DMA stream enable. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * - * @special - */ -#define dmaStreamEnable(dmastp) { \ - (dmastp)->channel->CCR |= STM32_DMA_CR_EN; \ -} - -/** - * @brief DMA stream disable. - * @details The function disables the specified stream and then clears any - * pending interrupt. - * @note This function can be invoked in both ISR or thread context. - * @note Interrupts enabling flags are set to zero after this call, see - * bug 3607518. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * - * @special - */ -#define dmaStreamDisable(dmastp) { \ - (dmastp)->channel->CCR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | \ - STM32_DMA_CR_TEIE | STM32_DMA_CR_EN); \ - dmaStreamClearInterrupt(dmastp); \ -} - -/** - * @brief DMA stream interrupt sources clear. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * - * @special - */ -#define dmaStreamClearInterrupt(dmastp) { \ - (dmastp)->dma->IFCR = STM32_DMA_ISR_MASK << (dmastp)->shift; \ -} - -/** - * @brief Starts a memory to memory operation using the specified stream. - * @note The default transfer data mode is "byte to byte" but it can be - * changed by specifying extra options in the @p mode parameter. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] mode value to be written in the CCR register, this value - * is implicitly ORed with: - * - @p STM32_DMA_CR_MINC - * - @p STM32_DMA_CR_PINC - * - @p STM32_DMA_CR_DIR_M2M - * - @p STM32_DMA_CR_EN - * . - * @param[in] src source address - * @param[in] dst destination address - * @param[in] n number of data units to copy - */ -#define dmaStartMemCopy(dmastp, mode, src, dst, n) { \ - dmaStreamSetPeripheral(dmastp, src); \ - dmaStreamSetMemory0(dmastp, dst); \ - dmaStreamSetTransactionSize(dmastp, n); \ - dmaStreamSetMode(dmastp, (mode) | \ - STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \ - STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); \ -} - -/** - * @brief Polled wait for DMA transfer end. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - */ -#define dmaWaitCompletion(dmastp) { \ - while ((dmastp)->channel->CNDTR > 0U) \ - ; \ - dmaStreamDisable(dmastp); \ -} - -/** - * @brief Serves a DMA IRQ. - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - */ -#define dmaServeInterrupt(dmastp) { \ - uint32_t flags; \ - uint32_t idx = (dmastp)->selfindex; \ - \ - flags = ((dmastp)->dma->ISR >> (dmastp)->shift) & STM32_DMA_ISR_MASK; \ - if (flags & (dmastp)->channel->CCR) { \ - (dmastp)->dma->IFCR = flags << (dmastp)->shift; \ - if (_stm32_dma_isr_redir[idx].dma_func) { \ - _stm32_dma_isr_redir[idx].dma_func(_stm32_dma_isr_redir[idx].dma_param, flags); \ - } \ - } \ -} -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS]; -extern dma_isr_redir_t _stm32_dma_isr_redir[STM32_DMA_STREAMS]; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void dmaInit(void); - bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp, - uint32_t priority, - stm32_dmaisr_t func, - void *param); - void dmaStreamRelease(const stm32_dma_stream_t *dmastp); -#ifdef __cplusplus -} -#endif - -#endif /* _STM32_DMA_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/DMAv2/notes.txt b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/DMAv2/notes.txt deleted file mode 100644 index 7242e8e528..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/DMAv2/notes.txt +++ /dev/null @@ -1,20 +0,0 @@ -STM32 DMAv2 driver. - -Driver capability: - -- The driver supports the STM32 enhanced DMA controller found on F2, F4 and - F7 sub-families. -- Support for automatic the channel selection. -- Support for cache flushing and invalidation. - -The file registry must export: - -STM32_ADVANCED_DMA - TRUE not used by the DMA drivers but other - drivers use it to enable checks on DMA - channels. Probably will be removed in the - future. -STM32_HAS_DMAx - Support for DMA unit "x" (1..2). -STM32_DMAx_CHn_HANDLER - Vector name for channel "n" (0..7). -STM32_DMAn_CHx_NUMBER - Vector number for channel "n" (0..7). -STM32_DMA_CACHE_HANDLING - TRUE if the device requires explicit cache - handling on DMA buffers. \ No newline at end of file diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c deleted file mode 100644 index 6ec0ac68d6..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c +++ /dev/null @@ -1,522 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file DMAv2/stm32_dma.c - * @brief Enhanced DMA helper driver code. - * - * @addtogroup STM32_DMA - * @details DMA sharing helper driver. In the STM32 the DMA streams are a - * shared resource, this driver allows to allocate and free DMA - * streams at runtime in order to allow all the other device - * drivers to coordinate the access to the resource. - * @note The DMA ISR handlers are all declared into this module because - * sharing, the various device drivers can associate a callback to - * ISRs when allocating streams. - * @{ - */ - -#include "hal.h" - -/* The following macro is only defined if some driver requiring DMA services - has been enabled.*/ -#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/** - * @brief Mask of the DMA1 streams in @p dma_streams_mask. - */ -#define STM32_DMA1_STREAMS_MASK 0x000000FFU - -/** - * @brief Mask of the DMA2 streams in @p dma_streams_mask. - */ -#define STM32_DMA2_STREAMS_MASK 0x0000FF00U - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief DMA streams descriptors. - * @details This table keeps the association between an unique stream - * identifier and the involved physical registers. - * @note Don't use this array directly, use the appropriate wrapper macros - * instead: @p STM32_DMA1_STREAM0, @p STM32_DMA1_STREAM1 etc. - */ -const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = { - {DMA1_Stream0, &DMA1->LIFCR, 0, 0, STM32_DMA1_CH0_NUMBER}, - {DMA1_Stream1, &DMA1->LIFCR, 6, 1, STM32_DMA1_CH1_NUMBER}, - {DMA1_Stream2, &DMA1->LIFCR, 16, 2, STM32_DMA1_CH2_NUMBER}, - {DMA1_Stream3, &DMA1->LIFCR, 22, 3, STM32_DMA1_CH3_NUMBER}, - {DMA1_Stream4, &DMA1->HIFCR, 0, 4, STM32_DMA1_CH4_NUMBER}, - {DMA1_Stream5, &DMA1->HIFCR, 6, 5, STM32_DMA1_CH5_NUMBER}, - {DMA1_Stream6, &DMA1->HIFCR, 16, 6, STM32_DMA1_CH6_NUMBER}, - {DMA1_Stream7, &DMA1->HIFCR, 22, 7, STM32_DMA1_CH7_NUMBER}, - {DMA2_Stream0, &DMA2->LIFCR, 0, 8, STM32_DMA2_CH0_NUMBER}, - {DMA2_Stream1, &DMA2->LIFCR, 6, 9, STM32_DMA2_CH1_NUMBER}, - {DMA2_Stream2, &DMA2->LIFCR, 16, 10, STM32_DMA2_CH2_NUMBER}, - {DMA2_Stream3, &DMA2->LIFCR, 22, 11, STM32_DMA2_CH3_NUMBER}, - {DMA2_Stream4, &DMA2->HIFCR, 0, 12, STM32_DMA2_CH4_NUMBER}, - {DMA2_Stream5, &DMA2->HIFCR, 6, 13, STM32_DMA2_CH5_NUMBER}, - {DMA2_Stream6, &DMA2->HIFCR, 16, 14, STM32_DMA2_CH6_NUMBER}, - {DMA2_Stream7, &DMA2->HIFCR, 22, 15, STM32_DMA2_CH7_NUMBER}, -}; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief DMA ISR redirector type. - */ -typedef struct { - stm32_dmaisr_t dma_func; /**< @brief DMA callback function. */ - void *dma_param; /**< @brief DMA callback parameter. */ -} dma_isr_redir_t; - -/** - * @brief Mask of the allocated streams. - */ -static uint32_t dma_streams_mask; - -/** - * @brief DMA IRQ redirectors. - */ -static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS]; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief DMA1 stream 0 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_DMA1_CH0_HANDLER) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA1->LISR >> 0U) & STM32_DMA_ISR_MASK; - DMA1->LIFCR = flags << 0U; - if (dma_isr_redir[0].dma_func) - dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 1 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_DMA1_CH1_HANDLER) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA1->LISR >> 6U) & STM32_DMA_ISR_MASK; - DMA1->LIFCR = flags << 6U; - if (dma_isr_redir[1].dma_func) - dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 2 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_DMA1_CH2_HANDLER) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA1->LISR >> 16U) & STM32_DMA_ISR_MASK; - DMA1->LIFCR = flags << 16U; - if (dma_isr_redir[2].dma_func) - dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 3 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_DMA1_CH3_HANDLER) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA1->LISR >> 22U) & STM32_DMA_ISR_MASK; - DMA1->LIFCR = flags << 22U; - if (dma_isr_redir[3].dma_func) - dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 4 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_DMA1_CH4_HANDLER) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA1->HISR >> 0U) & STM32_DMA_ISR_MASK; - DMA1->HIFCR = flags << 0U; - if (dma_isr_redir[4].dma_func) - dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 5 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_DMA1_CH5_HANDLER) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA1->HISR >> 6U) & STM32_DMA_ISR_MASK; - DMA1->HIFCR = flags << 6U; - if (dma_isr_redir[5].dma_func) - dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 6 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_DMA1_CH6_HANDLER) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA1->HISR >> 16U) & STM32_DMA_ISR_MASK; - DMA1->HIFCR = flags << 16U; - if (dma_isr_redir[6].dma_func) - dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 7 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_DMA1_CH7_HANDLER) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA1->HISR >> 22U) & STM32_DMA_ISR_MASK; - DMA1->HIFCR = flags << 22U; - if (dma_isr_redir[7].dma_func) - dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 0 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_DMA2_CH0_HANDLER) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA2->LISR >> 0U) & STM32_DMA_ISR_MASK; - DMA2->LIFCR = flags << 0U; - if (dma_isr_redir[8].dma_func) - dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 1 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_DMA2_CH1_HANDLER) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA2->LISR >> 6U) & STM32_DMA_ISR_MASK; - DMA2->LIFCR = flags << 6U; - if (dma_isr_redir[9].dma_func) - dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 2 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_DMA2_CH2_HANDLER) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA2->LISR >> 16U) & STM32_DMA_ISR_MASK; - DMA2->LIFCR = flags << 16U; - if (dma_isr_redir[10].dma_func) - dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 3 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_DMA2_CH3_HANDLER) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA2->LISR >> 22U) & STM32_DMA_ISR_MASK; - DMA2->LIFCR = flags << 22U; - if (dma_isr_redir[11].dma_func) - dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 4 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_DMA2_CH4_HANDLER) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA2->HISR >> 0U) & STM32_DMA_ISR_MASK; - DMA2->HIFCR = flags << 0U; - if (dma_isr_redir[12].dma_func) - dma_isr_redir[12].dma_func(dma_isr_redir[12].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 5 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_DMA2_CH5_HANDLER) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA2->HISR >> 6U) & STM32_DMA_ISR_MASK; - DMA2->HIFCR = flags << 6U; - if (dma_isr_redir[13].dma_func) - dma_isr_redir[13].dma_func(dma_isr_redir[13].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 6 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_DMA2_CH6_HANDLER) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA2->HISR >> 16U) & STM32_DMA_ISR_MASK; - DMA2->HIFCR = flags << 16U; - if (dma_isr_redir[14].dma_func) - dma_isr_redir[14].dma_func(dma_isr_redir[14].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 7 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_DMA2_CH7_HANDLER) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA2->HISR >> 22U) & STM32_DMA_ISR_MASK; - DMA2->HIFCR = flags << 22U; - if (dma_isr_redir[15].dma_func) - dma_isr_redir[15].dma_func(dma_isr_redir[15].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief STM32 DMA helper initialization. - * - * @init - */ -void dmaInit(void) { - unsigned i; - - dma_streams_mask = 0U; - for (i = 0U; i < STM32_DMA_STREAMS; i++) { - _stm32_dma_streams[i].stream->CR = 0U; - dma_isr_redir[i].dma_func = NULL; - } - DMA1->LIFCR = 0xFFFFFFFFU; - DMA1->HIFCR = 0xFFFFFFFFU; - DMA2->LIFCR = 0xFFFFFFFFU; - DMA2->HIFCR = 0xFFFFFFFFU; -} - -/** - * @brief Allocates a DMA stream. - * @details The stream is allocated and, if required, the DMA clock enabled. - * The function also enables the IRQ vector associated to the stream - * and initializes its priority. - * @pre The stream must not be already in use or an error is returned. - * @post The stream is allocated and the default ISR handler redirected - * to the specified function. - * @post The stream ISR vector is enabled and its priority configured. - * @post The stream must be freed using @p dmaStreamRelease() before it can - * be reused with another peripheral. - * @post The stream is in its post-reset state. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] priority IRQ priority mask for the DMA stream - * @param[in] func handling function pointer, can be @p NULL - * @param[in] param a parameter to be passed to the handling function - * @return The operation status. - * @retval false no error, stream taken. - * @retval true error, stream already taken. - * - * @special - */ -bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp, - uint32_t priority, - stm32_dmaisr_t func, - void *param) { - - osalDbgCheck(dmastp != NULL); - - /* Checks if the stream is already taken.*/ - if ((dma_streams_mask & (1U << dmastp->selfindex)) != 0U) - return true; - - /* Marks the stream as allocated.*/ - dma_isr_redir[dmastp->selfindex].dma_func = func; - dma_isr_redir[dmastp->selfindex].dma_param = param; - dma_streams_mask |= (1U << dmastp->selfindex); - - /* Enabling DMA clocks required by the current streams set.*/ - if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0U) { - rccEnableDMA1(false); - } - if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0U) { - rccEnableDMA2(false); - } - - /* Putting the stream in a safe state.*/ - dmaStreamDisable(dmastp); - dmastp->stream->CR = STM32_DMA_CR_RESET_VALUE; - dmastp->stream->FCR = STM32_DMA_FCR_RESET_VALUE; - - /* Enables the associated IRQ vector if a callback is defined.*/ - if (func != NULL) { - nvicEnableVector(dmastp->vector, priority); - } - - return false; -} - -/** - * @brief Releases a DMA stream. - * @details The stream is freed and, if required, the DMA clock disabled. - * Trying to release a unallocated stream is an illegal operation - * and is trapped if assertions are enabled. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post The stream is again available. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * - * @special - */ -void dmaStreamRelease(const stm32_dma_stream_t *dmastp) { - - osalDbgCheck(dmastp != NULL); - - /* Check if the streams is not taken.*/ - osalDbgAssert((dma_streams_mask & (1U << dmastp->selfindex)) != 0U, - "not allocated"); - - /* Disables the associated IRQ vector.*/ - nvicDisableVector(dmastp->vector); - - /* Marks the stream as not allocated.*/ - dma_streams_mask &= ~(1U << dmastp->selfindex); - - /* Shutting down clocks that are no more required, if any.*/ - if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0U) { - rccDisableDMA1(false); - } - if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0U) { - rccDisableDMA2(false); - } -} - -#endif /* STM32_DMA_REQUIRED */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h deleted file mode 100644 index cef410d85a..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h +++ /dev/null @@ -1,676 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file DMAv2/stm32_dma.h - * @brief Enhanced-DMA helper driver header. - * - * @addtogroup STM32_DMA - * @{ - */ - -#ifndef _STM32_DMA_H_ -#define _STM32_DMA_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief DMA capability. - * @details if @p TRUE then the DMA is able of burst transfers, FIFOs, - * scatter gather and other advanced features. - */ -#define STM32_DMA_ADVANCED TRUE - -/** - * @brief Total number of DMA streams. - * @details This is the total number of streams among all the DMA units. - */ -#define STM32_DMA_STREAMS 16U - -/** - * @brief Mask of the ISR bits passed to the DMA callback functions. - */ -#define STM32_DMA_ISR_MASK 0x3DU - -/** - * @brief Returns the channel associated to the specified stream. - * - * @param[in] id the unique numeric stream identifier - * @param[in] c a stream/channel association word, one channel per - * nibble - * @return Returns the channel associated to the stream. - */ -#define STM32_DMA_GETCHANNEL(id, c) (((c) >> (((id) & 7U) * 4U)) & 7U) - -/** - * @brief Checks if a DMA priority is within the valid range. - * @param[in] prio DMA priority - * - * @retval The check result. - * @retval FALSE invalid DMA priority. - * @retval TRUE correct DMA priority. - */ -#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0U) && ((prio) <= 3U)) - -/** - * @brief Returns an unique numeric identifier for a DMA stream. - * - * @param[in] dma the DMA unit number - * @param[in] stream the stream number - * @return An unique numeric stream identifier. - */ -#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1U) * 8U) + (stream)) - -/** - * @brief Returns a DMA stream identifier mask. - * - * - * @param[in] dma the DMA unit number - * @param[in] stream the stream number - * @return A DMA stream identifier mask. - */ -#define STM32_DMA_STREAM_ID_MSK(dma, stream) \ - (1U << STM32_DMA_STREAM_ID(dma, stream)) - -/** - * @brief Checks if a DMA stream unique identifier belongs to a mask. - * @param[in] id the stream numeric identifier - * @param[in] mask the stream numeric identifiers mask - * - * @retval The check result. - * @retval FALSE id does not belong to the mask. - * @retval TRUE id belongs to the mask. - */ -#define STM32_DMA_IS_VALID_ID(id, mask) (((1U << (id)) & (mask))) - -/** - * @name DMA streams identifiers - * @{ - */ -/** - * @brief Returns a pointer to a stm32_dma_stream_t structure. - * - * @param[in] id the stream numeric identifier - * @return A pointer to the stm32_dma_stream_t constant structure - * associated to the DMA stream. - */ -#define STM32_DMA_STREAM(id) (&_stm32_dma_streams[id]) - -#define STM32_DMA1_STREAM0 STM32_DMA_STREAM(0) -#define STM32_DMA1_STREAM1 STM32_DMA_STREAM(1) -#define STM32_DMA1_STREAM2 STM32_DMA_STREAM(2) -#define STM32_DMA1_STREAM3 STM32_DMA_STREAM(3) -#define STM32_DMA1_STREAM4 STM32_DMA_STREAM(4) -#define STM32_DMA1_STREAM5 STM32_DMA_STREAM(5) -#define STM32_DMA1_STREAM6 STM32_DMA_STREAM(6) -#define STM32_DMA1_STREAM7 STM32_DMA_STREAM(7) -#define STM32_DMA2_STREAM0 STM32_DMA_STREAM(8) -#define STM32_DMA2_STREAM1 STM32_DMA_STREAM(9) -#define STM32_DMA2_STREAM2 STM32_DMA_STREAM(10) -#define STM32_DMA2_STREAM3 STM32_DMA_STREAM(11) -#define STM32_DMA2_STREAM4 STM32_DMA_STREAM(12) -#define STM32_DMA2_STREAM5 STM32_DMA_STREAM(13) -#define STM32_DMA2_STREAM6 STM32_DMA_STREAM(14) -#define STM32_DMA2_STREAM7 STM32_DMA_STREAM(15) -/** @} */ - -/** - * @name CR register constants common to all DMA types - * @{ - */ -#define STM32_DMA_CR_RESET_VALUE 0x00000000U -#define STM32_DMA_CR_EN DMA_SxCR_EN -#define STM32_DMA_CR_TEIE DMA_SxCR_TEIE -#define STM32_DMA_CR_HTIE DMA_SxCR_HTIE -#define STM32_DMA_CR_TCIE DMA_SxCR_TCIE -#define STM32_DMA_CR_DIR_MASK DMA_SxCR_DIR -#define STM32_DMA_CR_DIR_P2M 0 -#define STM32_DMA_CR_DIR_M2P DMA_SxCR_DIR_0 -#define STM32_DMA_CR_DIR_M2M DMA_SxCR_DIR_1 -#define STM32_DMA_CR_CIRC DMA_SxCR_CIRC -#define STM32_DMA_CR_PINC DMA_SxCR_PINC -#define STM32_DMA_CR_MINC DMA_SxCR_MINC -#define STM32_DMA_CR_PSIZE_MASK DMA_SxCR_PSIZE -#define STM32_DMA_CR_PSIZE_BYTE 0 -#define STM32_DMA_CR_PSIZE_HWORD DMA_SxCR_PSIZE_0 -#define STM32_DMA_CR_PSIZE_WORD DMA_SxCR_PSIZE_1 -#define STM32_DMA_CR_MSIZE_MASK DMA_SxCR_MSIZE -#define STM32_DMA_CR_MSIZE_BYTE 0 -#define STM32_DMA_CR_MSIZE_HWORD DMA_SxCR_MSIZE_0 -#define STM32_DMA_CR_MSIZE_WORD DMA_SxCR_MSIZE_1 -#define STM32_DMA_CR_SIZE_MASK (STM32_DMA_CR_PSIZE_MASK | \ - STM32_DMA_CR_MSIZE_MASK) -#define STM32_DMA_CR_PL_MASK DMA_SxCR_PL -#define STM32_DMA_CR_PL(n) ((n) << 16U) -/** @} */ - -/** - * @name CR register constants only found in STM32F2xx/STM32F4xx - * @{ - */ -#define STM32_DMA_CR_DMEIE DMA_SxCR_DMEIE -#define STM32_DMA_CR_PFCTRL DMA_SxCR_PFCTRL -#define STM32_DMA_CR_PINCOS DMA_SxCR_PINCOS -#define STM32_DMA_CR_DBM DMA_SxCR_DBM -#define STM32_DMA_CR_CT DMA_SxCR_CT -#define STM32_DMA_CR_PBURST_MASK DMA_SxCR_PBURST -#define STM32_DMA_CR_PBURST_SINGLE 0 -#define STM32_DMA_CR_PBURST_INCR4 DMA_SxCR_PBURST_0 -#define STM32_DMA_CR_PBURST_INCR8 DMA_SxCR_PBURST_1 -#define STM32_DMA_CR_PBURST_INCR16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) -#define STM32_DMA_CR_MBURST_MASK DMA_SxCR_MBURST -#define STM32_DMA_CR_MBURST_SINGLE 0 -#define STM32_DMA_CR_MBURST_INCR4 DMA_SxCR_MBURST_0 -#define STM32_DMA_CR_MBURST_INCR8 DMA_SxCR_MBURST_1 -#define STM32_DMA_CR_MBURST_INCR16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) -#define STM32_DMA_CR_CHSEL_MASK DMA_SxCR_CHSEL -#define STM32_DMA_CR_CHSEL(n) ((n) << 25U) -/** @} */ - -/** - * @name FCR register constants only found in STM32F2xx/STM32F4xx - * @{ - */ -#define STM32_DMA_FCR_RESET_VALUE 0x00000021U -#define STM32_DMA_FCR_FEIE DMA_SxFCR_FEIE -#define STM32_DMA_FCR_FS_MASK DMA_SxFCR_FS -#define STM32_DMA_FCR_DMDIS DMA_SxFCR_DMDIS -#define STM32_DMA_FCR_FTH_MASK DMA_SxFCR_FTH -#define STM32_DMA_FCR_FTH_1Q 0 -#define STM32_DMA_FCR_FTH_HALF DMA_SxFCR_FTH_0 -#define STM32_DMA_FCR_FTH_3Q DMA_SxFCR_FTH_1 -#define STM32_DMA_FCR_FTH_FULL (DMA_SxFCR_FTH_0 | DMA_SxFCR_FTH_1) -/** @} */ - -/** - * @name Status flags passed to the ISR callbacks - */ -#define STM32_DMA_ISR_FEIF DMA_LISR_FEIF0 -#define STM32_DMA_ISR_DMEIF DMA_LISR_DMEIF0 -#define STM32_DMA_ISR_TEIF DMA_LISR_TEIF0 -#define STM32_DMA_ISR_HTIF DMA_LISR_HTIF0 -#define STM32_DMA_ISR_TCIF DMA_LISR_TCIF0 -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !defined(STM32_DMA_CACHE_HANDLING) -#error "STM32_DMA_CACHE_HANDLING missing in registry" -#endif - -#if !defined(STM32_HAS_DMA1) -#error "STM32_HAS_DMA1 missing in registry" -#endif - -#if !defined(STM32_HAS_DMA2) -#error "STM32_HAS_DMA2 missing in registry" -#endif - -#if !defined(STM32_DMA1_CH0_HANDLER) -#error "STM32_DMA1_CH0_HANDLER missing in registry" -#endif - -#if !defined(STM32_DMA1_CH1_HANDLER) -#error "STM32_DMA1_CH1_HANDLER missing in registry" -#endif - -#if !defined(STM32_DMA1_CH2_HANDLER) -#error "STM32_DMA1_CH2_HANDLER missing in registry" -#endif - -#if !defined(STM32_DMA1_CH3_HANDLER) -#error "STM32_DMA1_CH3_HANDLER missing in registry" -#endif - -#if !defined(STM32_DMA1_CH4_HANDLER) -#error "STM32_DMA1_CH4_HANDLER missing in registry" -#endif - -#if !defined(STM32_DMA1_CH5_HANDLER) -#error "STM32_DMA1_CH5_HANDLER missing in registry" -#endif - -#if !defined(STM32_DMA1_CH6_HANDLER) -#error "STM32_DMA1_CH6_HANDLER missing in registry" -#endif - -#if !defined(STM32_DMA1_CH7_HANDLER) -#error "STM32_DMA1_CH7_HANDLER missing in registry" -#endif - -#if !defined(STM32_DMA2_CH0_HANDLER) -#error "STM32_DMA2_CH0_HANDLER missing in registry" -#endif - -#if !defined(STM32_DMA2_CH1_HANDLER) -#error "STM32_DMA2_CH1_HANDLER missing in registry" -#endif - -#if !defined(STM32_DMA2_CH2_HANDLER) -#error "STM32_DMA2_CH2_HANDLER missing in registry" -#endif - -#if !defined(STM32_DMA2_CH3_HANDLER) -#error "STM32_DMA2_CH3_HANDLER missing in registry" -#endif - -#if !defined(STM32_DMA2_CH4_HANDLER) -#error "STM32_DMA2_CH4_HANDLER missing in registry" -#endif - -#if !defined(STM32_DMA2_CH5_HANDLER) -#error "STM32_DMA2_CH5_HANDLER missing in registry" -#endif - -#if !defined(STM32_DMA2_CH6_HANDLER) -#error "STM32_DMA2_CH6_HANDLER missing in registry" -#endif - -#if !defined(STM32_DMA2_CH7_HANDLER) -#error "STM32_DMA2_CH7_HANDLER missing in registry" -#endif - -#if !defined(STM32_DMA1_CH0_NUMBER) -#error "STM32_DMA1_CH0_NUMBER missing in registry" -#endif - -#if !defined(STM32_DMA1_CH1_NUMBER) -#error "STM32_DMA1_CH1_NUMBER missing in registry" -#endif - -#if !defined(STM32_DMA1_CH2_NUMBER) -#error "STM32_DMA1_CH2_NUMBER missing in registry" -#endif - -#if !defined(STM32_DMA1_CH3_NUMBER) -#error "STM32_DMA1_CH3_NUMBER missing in registry" -#endif - -#if !defined(STM32_DMA1_CH4_NUMBER) -#error "STM32_DMA1_CH4_NUMBER missing in registry" -#endif - -#if !defined(STM32_DMA1_CH5_NUMBER) -#error "STM32_DMA1_CH5_NUMBER missing in registry" -#endif - -#if !defined(STM32_DMA1_CH6_NUMBER) -#error "STM32_DMA1_CH6_NUMBER missing in registry" -#endif - -#if !defined(STM32_DMA1_CH7_NUMBER) -#error "STM32_DMA1_CH7_NUMBER missing in registry" -#endif - -#if !defined(STM32_DMA2_CH0_NUMBER) -#error "STM32_DMA2_CH0_NUMBER missing in registry" -#endif - -#if !defined(STM32_DMA2_CH1_NUMBER) -#error "STM32_DMA2_CH1_NUMBER missing in registry" -#endif - -#if !defined(STM32_DMA2_CH2_NUMBER) -#error "STM32_DMA2_CH2_NUMBER missing in registry" -#endif - -#if !defined(STM32_DMA2_CH3_NUMBER) -#error "STM32_DMA2_CH3_NUMBER missing in registry" -#endif - -#if !defined(STM32_DMA2_CH4_NUMBER) -#error "STM32_DMA2_CH4_NUMBER missing in registry" -#endif - -#if !defined(STM32_DMA2_CH5_NUMBER) -#error "STM32_DMA2_CH5_NUMBER missing in registry" -#endif - -#if !defined(STM32_DMA2_CH6_NUMBER) -#error "STM32_DMA2_CH6_NUMBER missing in registry" -#endif - -#if !defined(STM32_DMA2_CH7_NUMBER) -#error "STM32_DMA2_CH7_NUMBER missing in registry" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief STM32 DMA stream descriptor structure. - */ -typedef struct { - DMA_Stream_TypeDef *stream; /**< @brief Associated DMA stream. */ - volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */ - uint8_t ishift; /**< @brief Bits offset in xIFCR - register. */ - uint8_t selfindex; /**< @brief Index to self in array. */ - uint8_t vector; /**< @brief Associated IRQ vector. */ -} stm32_dma_stream_t; - -/** - * @brief STM32 DMA ISR function type. - * - * @param[in] p parameter for the registered function - * @param[in] flags pre-shifted content of the xISR register, the bits - * are aligned to bit zero - */ -typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -#if STM32_DMA_CACHE_HANDLING || defined(__DOXYGEN__) -/** - * @brief Invalidates the data cache lines overlapping a DMA buffer. - * @details This function is meant to make sure that data written in - * data cache is invalidated. It is used for DMA buffers that - * must have been written by a DMA stream. - * @note On devices without data cache this function does nothing. - * @note The function does not consider the lower 5 bits of addresses, - * the buffers are meant to be aligned to a 32 bytes boundary or - * adjacent data can be invalidated as side effect. - * - * @param[in] saddr start address of the DMA buffer - * @param[in] n size of the DMA buffer in bytes - * - * @api - */ -#define dmaBufferInvalidate(saddr, n) { \ - uint8_t *start = (uint8_t *)(saddr); \ - uint8_t *end = start + (size_t)(n); \ - __DSB(); \ - while (start < end) { \ - SCB->DCIMVAC = (uint32_t)start; \ - start += 32U; \ - } \ - __DSB(); \ - __ISB(); \ -} - -/** - * @brief Flushes the data cache lines overlapping a DMA buffer. - * @details This function is meant to make sure that data written in - * data cache is flushed to RAM. It is used for DMA buffers that - * must be read by a DMA stream. - * @note On devices without data cache this function does nothing. - * @note The function does not consider the lower 5 bits of addresses, - * the buffers are meant to be aligned to a 32 bytes boundary or - * adjacent data can be flushed as side effect. - * - * @param[in] saddr start address of the DMA buffer - * @param[in] n size of the DMA buffer in bytes - * - * @api - */ -#define dmaBufferFlush(saddr, n) { \ - uint8_t *start = (uint8_t *)(saddr); \ - uint8_t *end = start + (size_t)(n); \ - __DSB(); \ - while (start < end) { \ - SCB->DCCIMVAC = (uint32_t)start; \ - start += 32U; \ - } \ - __DSB(); \ - __ISB(); \ -} -#else -#define dmaBufferInvalidate(addr, size) { \ - (void)(addr); \ - (void)(size); \ -} -#define dmaBufferFlush(addr, size) { \ - (void)(addr); \ - (void)(size); \ -} -#endif - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Associates a peripheral data register to a DMA stream. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] addr value to be written in the PAR register - * - * @special - */ -#define dmaStreamSetPeripheral(dmastp, addr) { \ - (dmastp)->stream->PAR = (uint32_t)(addr); \ -} - -/** - * @brief Associates a memory destination to a DMA stream. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] addr value to be written in the M0AR register - * - * @special - */ -#define dmaStreamSetMemory0(dmastp, addr) { \ - (dmastp)->stream->M0AR = (uint32_t)(addr); \ -} - -/** - * @brief Associates an alternate memory destination to a DMA stream. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] addr value to be written in the M1AR register - * - * @special - */ -#define dmaStreamSetMemory1(dmastp, addr) { \ - (dmastp)->stream->M1AR = (uint32_t)(addr); \ -} - -/** - * @brief Sets the number of transfers to be performed. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] size value to be written in the CNDTR register - * - * @special - */ -#define dmaStreamSetTransactionSize(dmastp, size) { \ - (dmastp)->stream->NDTR = (uint32_t)(size); \ -} - -/** - * @brief Returns the number of transfers to be performed. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @return The number of transfers to be performed. - * - * @special - */ -#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->stream->NDTR)) - -/** - * @brief Programs the stream mode settings. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] mode value to be written in the CR register - * - * @special - */ -#define dmaStreamSetMode(dmastp, mode) { \ - (dmastp)->stream->CR = (uint32_t)(mode); \ -} - -/** - * @brief Programs the stream FIFO settings. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] mode value to be written in the FCR register - * - * @special - */ -#define dmaStreamSetFIFO(dmastp, mode) { \ - (dmastp)->stream->FCR = (uint32_t)(mode); \ -} - -/** - * @brief DMA stream enable. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * - * @special - */ -#define dmaStreamEnable(dmastp) { \ - (dmastp)->stream->CR |= STM32_DMA_CR_EN; \ -} - -/** - * @brief DMA stream disable. - * @details The function disables the specified stream, waits for the disable - * operation to complete and then clears any pending interrupt. - * @note This function can be invoked in both ISR or thread context. - * @note Interrupts enabling flags are set to zero after this call, see - * bug 3607518. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * - * @special - */ -#define dmaStreamDisable(dmastp) { \ - (dmastp)->stream->CR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | \ - STM32_DMA_CR_TEIE | STM32_DMA_CR_DMEIE | \ - STM32_DMA_CR_EN); \ - while (((dmastp)->stream->CR & STM32_DMA_CR_EN) != 0) \ - ; \ - dmaStreamClearInterrupt(dmastp); \ -} - -/** - * @brief DMA stream interrupt sources clear. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * - * @special - */ -#define dmaStreamClearInterrupt(dmastp) { \ - *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \ -} - -/** - * @brief Starts a memory to memory operation using the specified stream. - * @note The default transfer data mode is "byte to byte" but it can be - * changed by specifying extra options in the @p mode parameter. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] mode value to be written in the CCR register, this value - * is implicitly ORed with: - * - @p STM32_DMA_CR_MINC - * - @p STM32_DMA_CR_PINC - * - @p STM32_DMA_CR_DIR_M2M - * - @p STM32_DMA_CR_EN - * . - * @param[in] src source address - * @param[in] dst destination address - * @param[in] n number of data units to copy - */ -#define dmaStartMemCopy(dmastp, mode, src, dst, n) { \ - dmaStreamSetPeripheral(dmastp, src); \ - dmaStreamSetMemory0(dmastp, dst); \ - dmaStreamSetTransactionSize(dmastp, n); \ - dmaStreamSetMode(dmastp, (mode) | \ - STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \ - STM32_DMA_CR_DIR_M2M); \ - dmaStreamEnable(dmastp); \ -} - -/** - * @brief Polled wait for DMA transfer end. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - */ -#define dmaWaitCompletion(dmastp) { \ - (dmastp)->stream->CR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | \ - STM32_DMA_CR_TEIE | STM32_DMA_CR_DMEIE); \ - while ((dmastp)->stream->CR & STM32_DMA_CR_EN) \ - ; \ - dmaStreamClearInterrupt(dmastp); \ -} -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS]; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void dmaInit(void); - bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp, - uint32_t priority, - stm32_dmaisr_t func, - void *param); - void dmaStreamRelease(const stm32_dma_stream_t *dmastp); -#ifdef __cplusplus -} -#endif - -#endif /* _STM32_DMA_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c deleted file mode 100644 index 473ce39174..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c +++ /dev/null @@ -1,239 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/EXTIv1/ext_lld.c - * @brief STM32 EXT subsystem low level driver source. - * - * @addtogroup EXT - * @{ - */ - -#include "hal.h" - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/* Handling a difference in ST headers.*/ -#if defined(STM32L4XX) -#define EMR EMR1 -#define IMR IMR1 -#define PR PR1 -#define RTSR RTSR1 -#define FTSR FTSR1 -#endif - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief EXTD1 driver identifier. - */ -EXTDriver EXTD1; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level EXT driver initialization. - * - * @notapi - */ -void ext_lld_init(void) { - - /* Driver initialization.*/ - extObjectInit(&EXTD1); -} - -/** - * @brief Configures and activates the EXT peripheral. - * - * @param[in] extp pointer to the @p EXTDriver object - * - * @notapi - */ -void ext_lld_start(EXTDriver *extp) { - expchannel_t line; - - if (extp->state == EXT_STOP) - ext_lld_exti_irq_enable(); - - /* Configuration of automatic channels.*/ - for (line = 0; line < EXT_MAX_CHANNELS; line++) - if (extp->config->channels[line].mode & EXT_CH_MODE_AUTOSTART) - ext_lld_channel_enable(extp, line); - else - ext_lld_channel_disable(extp, line); -} - -/** - * @brief Deactivates the EXT peripheral. - * - * @param[in] extp pointer to the @p EXTDriver object - * - * @notapi - */ -void ext_lld_stop(EXTDriver *extp) { - - if (extp->state == EXT_ACTIVE) - ext_lld_exti_irq_disable(); - - EXTI->EMR = 0; - EXTI->IMR = STM32_EXTI_IMR_MASK; - EXTI->PR = ~STM32_EXTI_IMR_MASK; -#if STM32_EXTI_NUM_LINES > 32 - EXTI->IMR2 = STM32_EXTI_IMR2_MASK; - EXTI->PR2 = ~STM32_EXTI_IMR2_MASK; -#endif -} - -/** - * @brief Enables an EXT channel. - * - * @param[in] extp pointer to the @p EXTDriver object - * @param[in] channel channel to be enabled - * - * @notapi - */ -void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) { - uint32_t cmask = (1 << (channel & 0x1F)); - - /* Setting the associated GPIO for external channels.*/ - if (channel < 16) { - uint32_t n = channel >> 2; - uint32_t mask = ~(0xF << ((channel & 3) * 4)); - uint32_t port = ((extp->config->channels[channel].mode & - EXT_MODE_GPIO_MASK) >> - EXT_MODE_GPIO_OFF) << ((channel & 3) * 4); - -#if defined(STM32F1XX) - AFIO->EXTICR[n] = (AFIO->EXTICR[n] & mask) | port; -#else /* !defined(STM32F1XX) */ - SYSCFG->EXTICR[n] = (SYSCFG->EXTICR[n] & mask) | port; -#endif /* !defined(STM32F1XX) */ - } - -#if STM32_EXTI_NUM_LINES > 32 - if (channel < 32) { -#endif - /* Masked out lines must not be touched by this driver.*/ - if ((cmask & STM32_EXTI_IMR_MASK) != 0U) { - return; - } - - /* Programming edge registers.*/ - if (extp->config->channels[channel].mode & EXT_CH_MODE_RISING_EDGE) - EXTI->RTSR |= cmask; - else - EXTI->RTSR &= ~cmask; - if (extp->config->channels[channel].mode & EXT_CH_MODE_FALLING_EDGE) - EXTI->FTSR |= cmask; - else - EXTI->FTSR &= ~cmask; - - /* Programming interrupt and event registers.*/ - if (extp->config->channels[channel].cb != NULL) { - EXTI->IMR |= cmask; - EXTI->EMR &= ~cmask; - } - else { - EXTI->EMR |= cmask; - EXTI->IMR &= ~cmask; - } -#if STM32_EXTI_NUM_LINES > 32 - } - else { - /* Masked out lines must not be touched by this driver.*/ - if ((cmask & STM32_EXTI_IMR2_MASK) != 0U) { - return; - } - - /* Programming edge registers.*/ - if (extp->config->channels[channel].mode & EXT_CH_MODE_RISING_EDGE) - EXTI->RTSR2 |= cmask; - else - EXTI->RTSR2 &= ~cmask; - if (extp->config->channels[channel].mode & EXT_CH_MODE_FALLING_EDGE) - EXTI->FTSR2 |= cmask; - else - EXTI->FTSR2 &= ~cmask; - - /* Programming interrupt and event registers.*/ - if (extp->config->channels[channel].cb != NULL) { - EXTI->IMR2 |= cmask; - EXTI->EMR2 &= ~cmask; - } - else { - EXTI->EMR2 |= cmask; - EXTI->IMR2 &= ~cmask; - } - } -#endif -} - -/** - * @brief Disables an EXT channel. - * - * @param[in] extp pointer to the @p EXTDriver object - * @param[in] channel channel to be disabled - * - * @notapi - */ -void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) { - uint32_t cmask = (1 << (channel & 0x1F)); - - (void)extp; - -#if STM32_EXTI_NUM_LINES > 32 - if (channel < 32) { -#endif - EXTI->IMR &= ~cmask; - EXTI->EMR &= ~cmask; - EXTI->RTSR &= ~cmask; - EXTI->FTSR &= ~cmask; - EXTI->PR = cmask; -#if STM32_EXTI_NUM_LINES > 32 - } - else { - EXTI->IMR2 &= ~cmask; - EXTI->EMR2 &= ~cmask; - EXTI->RTSR2 &= ~cmask; - EXTI->FTSR2 &= ~cmask; - EXTI->PR2 = cmask; - } -#endif -} - -#endif /* HAL_USE_EXT */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.h b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.h deleted file mode 100644 index 0c8383b4e4..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/EXTIv1/ext_lld.h - * @brief STM32 EXT subsystem low level driver header. - * - * @addtogroup EXT - * @{ - */ - -#ifndef _EXT_LLD_H_ -#define _EXT_LLD_H_ - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -#include "ext_lld_isr.h" - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Available number of EXT channels. - */ -#define EXT_MAX_CHANNELS STM32_EXTI_NUM_LINES - -/** - * @name STM32-specific EXT channel modes - * @{ - */ -#define EXT_MODE_GPIO_MASK 0xF0 /**< @brief Port field mask. */ -#define EXT_MODE_GPIO_OFF 4 /**< @brief Port field offset. */ -#define EXT_MODE_GPIOA 0x00 /**< @brief GPIOA identifier. */ -#define EXT_MODE_GPIOB 0x10 /**< @brief GPIOB identifier. */ -#define EXT_MODE_GPIOC 0x20 /**< @brief GPIOC identifier. */ -#define EXT_MODE_GPIOD 0x30 /**< @brief GPIOD identifier. */ -#define EXT_MODE_GPIOE 0x40 /**< @brief GPIOE identifier. */ -#define EXT_MODE_GPIOF 0x50 /**< @brief GPIOF identifier. */ -#define EXT_MODE_GPIOG 0x60 /**< @brief GPIOG identifier. */ -#define EXT_MODE_GPIOH 0x70 /**< @brief GPIOH identifier. */ -#define EXT_MODE_GPIOI 0x80 /**< @brief GPIOI identifier. */ -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief EXT channel identifier. - */ -typedef uint32_t expchannel_t; - -/** - * @brief Type of an EXT generic notification callback. - * - * @param[in] extp pointer to the @p EXPDriver object triggering the - * callback - */ -typedef void (*extcallback_t)(EXTDriver *extp, expchannel_t channel); - -/** - * @brief Channel configuration structure. - */ -typedef struct { - /** - * @brief Channel mode. - */ - uint32_t mode; - /** - * @brief Channel callback. - * @details In the STM32 implementation a @p NULL callback pointer is - * valid and configures the channel as an event sources instead - * of an interrupt source. - */ - extcallback_t cb; -} EXTChannelConfig; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief Channel configurations. - */ - EXTChannelConfig channels[EXT_MAX_CHANNELS]; - /* End of the mandatory fields.*/ -} EXTConfig; - -/** - * @brief Structure representing an EXT driver. - */ -struct EXTDriver { - /** - * @brief Driver state. - */ - extstate_t state; - /** - * @brief Current configuration data. - */ - const EXTConfig *config; - /* End of the mandatory fields.*/ -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -extern EXTDriver EXTD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void ext_lld_init(void); - void ext_lld_start(EXTDriver *extp); - void ext_lld_stop(EXTDriver *extp); - void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel); - void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_EXT */ - -#endif /* _EXT_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/EXTIv1/notes.txt b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/EXTIv1/notes.txt deleted file mode 100644 index 138f97e043..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/EXTIv1/notes.txt +++ /dev/null @@ -1,23 +0,0 @@ -STM32 EXT driver implementation through EXTI unit. - -There are several kind of EXTI lines: - -1) GPIO lines. Always in range 0..15, always handled by the EXT driver. -2) Configurable peripheral events not shared, always handled by the EXT driver. -3) Configurable peripheral events shared with other, non EXTI, interrupts. - The EXTI driver declares the ISR and has to call the IRQ handler of the - other driver. -4) Direct lines (1 in IMR register after reset). The EXTI driver never touches - the default configuration for direct lines and does not declare ISRs. -5) Unused lines. The EXTI driver does not declare ISRs. - -The file registry must export: -STM32_EXTI_NUM_LINES - Range of configurable lines, it can have holes of - unused or direct lines. Configurable line numbers go - from 0 to STM32_EXTI_NUM_LINES-1. -STM32_EXTI_IMR_MASK - Direct lines and unused lines marked as 1 in this - mask, configurable lines marked as 0. -STM32_EXTI_IMR2_MASK - Optional, for lines 32...63. - -ISRs are not declared inside the driver, each sub-family must have its own -ext_lld_isr.h and ext_lld_isr.c files. diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/GPIOv1/pal_lld.c b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/GPIOv1/pal_lld.c deleted file mode 100644 index 383121adf6..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/GPIOv1/pal_lld.c +++ /dev/null @@ -1,183 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/GPIOv1/pal_lld.c - * @brief STM32 PAL low level driver code. - * - * @addtogroup PAL - * @{ - */ - -#include "hal.h" - -#if HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#if STM32_HAS_GPIOG -#define APB2_EN_MASK (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | \ - RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | \ - RCC_APB2ENR_IOPEEN | RCC_APB2ENR_IOPFEN | \ - RCC_APB2ENR_IOPGEN | RCC_APB2ENR_AFIOEN) -#elif STM32_HAS_GPIOE -#define APB2_EN_MASK (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | \ - RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | \ - RCC_APB2ENR_IOPEEN | RCC_APB2ENR_AFIOEN) -#else -#define APB2_EN_MASK (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | \ - RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | \ - RCC_APB2ENR_AFIOEN) -#endif - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief STM32 I/O ports configuration. - * @details Ports A-D(E, F, G) clocks enabled, AFIO clock enabled. - * - * @param[in] config the STM32 ports configuration - * - * @notapi - */ -void _pal_lld_init(const PALConfig *config) { - - /* - * Enables the GPIO related clocks. - */ - rccEnableAPB2(APB2_EN_MASK, FALSE); - - /* - * Initial GPIO setup. - */ - GPIOA->ODR = config->PAData.odr; - GPIOA->CRH = config->PAData.crh; - GPIOA->CRL = config->PAData.crl; - GPIOB->ODR = config->PBData.odr; - GPIOB->CRH = config->PBData.crh; - GPIOB->CRL = config->PBData.crl; - GPIOC->ODR = config->PCData.odr; - GPIOC->CRH = config->PCData.crh; - GPIOC->CRL = config->PCData.crl; - GPIOD->ODR = config->PDData.odr; - GPIOD->CRH = config->PDData.crh; - GPIOD->CRL = config->PDData.crl; -#if STM32_HAS_GPIOE || defined(__DOXYGEN__) - GPIOE->ODR = config->PEData.odr; - GPIOE->CRH = config->PEData.crh; - GPIOE->CRL = config->PEData.crl; -#if STM32_HAS_GPIOF || defined(__DOXYGEN__) - GPIOF->ODR = config->PFData.odr; - GPIOF->CRH = config->PFData.crh; - GPIOF->CRL = config->PFData.crl; -#if STM32_HAS_GPIOG || defined(__DOXYGEN__) - GPIOG->ODR = config->PGData.odr; - GPIOG->CRH = config->PGData.crh; - GPIOG->CRL = config->PGData.crl; -#endif -#endif -#endif -} - -/** - * @brief Pads mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output at 2MHz. - * @note Writing on pads programmed as pull-up or pull-down has the side - * effect to modify the resistor setting because the output latched - * data is used for the resistor selection. - * - * @param[in] port the port identifier - * @param[in] mask the group mask - * @param[in] mode the mode - * - * @notapi - */ -void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - iomode_t mode) { - static const uint8_t cfgtab[] = { - 4, /* PAL_MODE_RESET, implemented as input.*/ - 2, /* PAL_MODE_UNCONNECTED, implemented as push pull output 2MHz.*/ - 4, /* PAL_MODE_INPUT */ - 8, /* PAL_MODE_INPUT_PULLUP */ - 8, /* PAL_MODE_INPUT_PULLDOWN */ - 0, /* PAL_MODE_INPUT_ANALOG */ - 3, /* PAL_MODE_OUTPUT_PUSHPULL, 50MHz.*/ - 7, /* PAL_MODE_OUTPUT_OPENDRAIN, 50MHz.*/ - 8, /* Reserved.*/ - 8, /* Reserved.*/ - 8, /* Reserved.*/ - 8, /* Reserved.*/ - 8, /* Reserved.*/ - 8, /* Reserved.*/ - 8, /* Reserved.*/ - 8, /* Reserved.*/ - 0xB, /* PAL_MODE_STM32_ALTERNATE_PUSHPULL, 50MHz.*/ - 0xF, /* PAL_MODE_STM32_ALTERNATE_OPENDRAIN, 50MHz.*/ - }; - uint32_t mh, ml, crh, crl, cfg; - unsigned i; - - if (mode == PAL_MODE_INPUT_PULLUP) - port->BSRR = mask; - else if (mode == PAL_MODE_INPUT_PULLDOWN) - port->BRR = mask; - cfg = cfgtab[mode]; - mh = ml = crh = crl = 0; - for (i = 0; i < 8; i++) { - ml <<= 4; - mh <<= 4; - crl <<= 4; - crh <<= 4; - if ((mask & 0x0080) == 0) - ml |= 0xf; - else - crl |= cfg; - if ((mask & 0x8000) == 0) - mh |= 0xf; - else - crh |= cfg; - mask <<= 1; - } - port->CRH = (port->CRH & mh) | crh; - port->CRL = (port->CRL & ml) | crl; -} - -#endif /* HAL_USE_PAL */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/GPIOv1/pal_lld.h b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/GPIOv1/pal_lld.h deleted file mode 100644 index 00c2bfbde9..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/GPIOv1/pal_lld.h +++ /dev/null @@ -1,376 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/GPIOv1/pal_lld.h - * @brief STM32 PAL low level driver header. - * - * @addtogroup PAL - * @{ - */ - -#ifndef _PAL_LLD_H_ -#define _PAL_LLD_H_ - -#if HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Unsupported modes and specific modes */ -/*===========================================================================*/ - -/** - * @name STM32-specific I/O mode flags - * @{ - */ -/** - * @brief STM32 specific alternate push-pull output mode. - */ -#define PAL_MODE_STM32_ALTERNATE_PUSHPULL 16 - -/** - * @brief STM32 specific alternate open-drain output mode. - */ -#define PAL_MODE_STM32_ALTERNATE_OPENDRAIN 17 -/** @} */ - -/*===========================================================================*/ -/* I/O Ports Types and constants. */ -/*===========================================================================*/ - -/** - * @name Port related definitions - * @{ - */ -/** - * @brief Width, in bits, of an I/O port. - */ -#define PAL_IOPORTS_WIDTH 16 - -/** - * @brief Whole port mask. - * @details This macro specifies all the valid bits into a port. - */ -#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF) -/** @} */ - -/** - * @name Line handling macros - * @{ - */ -/** - * @brief Forms a line identifier. - * @details A port/pad pair are encoded into an @p ioline_t type. The encoding - * of this type is platform-dependent. - * @note In this driver the pad number is encoded in the lower 4 bits of - * the GPIO address which are guaranteed to be zero. - */ -#define PAL_LINE(port, pad) \ - ((ioline_t)((uint32_t)(port)) | ((uint32_t)(pad))) - -/** - * @brief Decodes a port identifier from a line identifier. - */ -#define PAL_PORT(line) \ - ((GPIO_TypeDef *)(((uint32_t)(line)) & 0xFFFFFFF0U)) - -/** - * @brief Decodes a pad identifier from a line identifier. - */ -#define PAL_PAD(line) \ - ((uint32_t)((uint32_t)(line) & 0x0000000FU)) - -/** - * @brief Value identifying an invalid line. - */ -#define PAL_NOLINE 0U -/** @} */ - -/** - * @brief GPIO port setup info. - */ -typedef struct { - /** Initial value for ODR register.*/ - uint32_t odr; - /** Initial value for CRL register.*/ - uint32_t crl; - /** Initial value for CRH register.*/ - uint32_t crh; -} stm32_gpio_setup_t; - -/** - * @brief STM32 GPIO static initializer. - * @details An instance of this structure must be passed to @p palInit() at - * system startup time in order to initialize the digital I/O - * subsystem. This represents only the initial setup, specific pads - * or whole ports can be reprogrammed at later time. - */ -typedef struct { - /** @brief Port A setup data.*/ - stm32_gpio_setup_t PAData; - /** @brief Port B setup data.*/ - stm32_gpio_setup_t PBData; - /** @brief Port C setup data.*/ - stm32_gpio_setup_t PCData; - /** @brief Port D setup data.*/ - stm32_gpio_setup_t PDData; -#if STM32_HAS_GPIOE || defined(__DOXYGEN__) - /** @brief Port E setup data.*/ - stm32_gpio_setup_t PEData; -#if STM32_HAS_GPIOF || defined(__DOXYGEN__) - /** @brief Port F setup data.*/ - stm32_gpio_setup_t PFData; -#if STM32_HAS_GPIOG || defined(__DOXYGEN__) - /** @brief Port G setup data.*/ - stm32_gpio_setup_t PGData; -#endif -#endif -#endif -} PALConfig; - -/** - * @brief Digital I/O port sized unsigned type. - */ -typedef uint32_t ioportmask_t; - -/** - * @brief Digital I/O modes. - */ -typedef uint32_t iomode_t; - -/** - * @brief Type of an I/O line. - */ -typedef uint32_t ioline_t; - -/** - * @brief Port Identifier. - * @details This type can be a scalar or some kind of pointer, do not make - * any assumption about it, use the provided macros when populating - * variables of this type. - */ -typedef GPIO_TypeDef * ioportid_t; - -/*===========================================================================*/ -/* I/O Ports Identifiers. */ -/* The low level driver wraps the definitions already present in the STM32 */ -/* firmware library. */ -/*===========================================================================*/ - -/** - * @brief GPIO port A identifier. - */ -#if STM32_HAS_GPIOA || defined(__DOXYGEN__) -#define IOPORT1 GPIOA -#endif - -/** - * @brief GPIO port B identifier. - */ -#if STM32_HAS_GPIOB || defined(__DOXYGEN__) -#define IOPORT2 GPIOB -#endif - -/** - * @brief GPIO port C identifier. - */ -#if STM32_HAS_GPIOC || defined(__DOXYGEN__) -#define IOPORT3 GPIOC -#endif - -/** - * @brief GPIO port D identifier. - */ -#if STM32_HAS_GPIOD || defined(__DOXYGEN__) -#define IOPORT4 GPIOD -#endif - -/** - * @brief GPIO port E identifier. - */ -#if STM32_HAS_GPIOE || defined(__DOXYGEN__) -#define IOPORT5 GPIOE -#endif - -/** - * @brief GPIO port F identifier. - */ -#if STM32_HAS_GPIOF || defined(__DOXYGEN__) -#define IOPORT6 GPIOF -#endif - -/** - * @brief GPIO port G identifier. - */ -#if STM32_HAS_GPIOG || defined(__DOXYGEN__) -#define IOPORT7 GPIOG -#endif - -/*===========================================================================*/ -/* Implementation, some of the following macros could be implemented as */ -/* functions, if so please put them in pal_lld.c. */ -/*===========================================================================*/ - -/** - * @brief GPIO ports subsystem initialization. - * - * @notapi - */ -#define pal_lld_init(config) _pal_lld_init(config) - -/** - * @brief Reads an I/O port. - * @details This function is implemented by reading the GPIO IDR register, the - * implementation has no side effects. - * @note This function is not meant to be invoked directly by the application - * code. - * - * @param[in] port port identifier - * @return The port bits. - * - * @notapi - */ -#define pal_lld_readport(port) ((port)->IDR) - -/** - * @brief Reads the output latch. - * @details This function is implemented by reading the GPIO ODR register, the - * implementation has no side effects. - * @note This function is not meant to be invoked directly by the application - * code. - * - * @param[in] port port identifier - * @return The latched logical states. - * - * @notapi - */ -#define pal_lld_readlatch(port) ((port)->ODR) - -/** - * @brief Writes on a I/O port. - * @details This function is implemented by writing the GPIO ODR register, the - * implementation has no side effects. - * @note Writing on pads programmed as pull-up or pull-down has the side - * effect to modify the resistor setting because the output latched - * data is used for the resistor selection. - * - * @param[in] port port identifier - * @param[in] bits bits to be written on the specified port - * - * @notapi - */ -#define pal_lld_writeport(port, bits) ((port)->ODR = (bits)) - -/** - * @brief Sets a bits mask on a I/O port. - * @details This function is implemented by writing the GPIO BSRR register, the - * implementation has no side effects. - * @note Writing on pads programmed as pull-up or pull-down has the side - * effect to modify the resistor setting because the output latched - * data is used for the resistor selection. - * - * @param[in] port port identifier - * @param[in] bits bits to be ORed on the specified port - * - * @notapi - */ -#define pal_lld_setport(port, bits) ((port)->BSRR = (bits)) - -/** - * @brief Clears a bits mask on a I/O port. - * @details This function is implemented by writing the GPIO BRR register, the - * implementation has no side effects. - * @note Writing on pads programmed as pull-up or pull-down has the side - * effect to modify the resistor setting because the output latched - * data is used for the resistor selection. - * - * @param[in] port port identifier - * @param[in] bits bits to be cleared on the specified port - * - * @notapi - */ -#define pal_lld_clearport(port, bits) ((port)->BRR = (bits)) - -/** - * @brief Writes a group of bits. - * @details This function is implemented by writing the GPIO BSRR register, the - * implementation has no side effects. - * @note Writing on pads programmed as pull-up or pull-down has the side - * effect to modify the resistor setting because the output latched - * data is used for the resistor selection. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] offset the group bit offset within the port - * @param[in] bits bits to be written. Values exceeding the group - * width are masked. - * - * @notapi - */ -#define pal_lld_writegroup(port, mask, offset, bits) \ - ((port)->BSRR = ((~(bits) & (mask)) << (16 + (offset))) | \ - (((bits) & (mask)) << (offset))) - -/** - * @brief Pads group mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * @note Writing on pads programmed as pull-up or pull-down has the side - * effect to modify the resistor setting because the output latched - * data is used for the resistor selection. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] offset group bit offset within the port - * @param[in] mode group mode - * - * @notapi - */ -#define pal_lld_setgroupmode(port, mask, offset, mode) \ - _pal_lld_setgroupmode(port, mask << offset, mode) - -/** - * @brief Writes a logical state on an output pad. - * @note Writing on pads programmed as pull-up or pull-down has the side - * effect to modify the resistor setting because the output latched - * data is used for the resistor selection. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * @param[in] bit logical value, the value must be @p PAL_LOW or - * @p PAL_HIGH - * - * @notapi - */ -#define pal_lld_writepad(port, pad, bit) pal_lld_writegroup(port, 1, pad, bit) - -extern const PALConfig pal_default_config; - -#ifdef __cplusplus -extern "C" { -#endif - void _pal_lld_init(const PALConfig *config); - void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - iomode_t mode); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_PAL */ - -#endif /* _PAL_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c deleted file mode 100644 index b87564a008..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c +++ /dev/null @@ -1,212 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/GPIOv2/pal_lld.c - * @brief STM32 PAL low level driver code. - * - * @addtogroup PAL - * @{ - */ - -#include "hal.h" - -#if HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#if defined(STM32L0XX) || defined(STM32L1XX) -#define AHB_EN_MASK STM32_GPIO_EN_MASK -#define AHB_LPEN_MASK AHB_EN_MASK - -#elif defined(STM32F0XX) || defined(STM32F3XX) || defined(STM32F37X) -#define AHB_EN_MASK STM32_GPIO_EN_MASK -#define AHB_LPEN_MASK 0 - -#elif defined(STM32F2XX) || defined(STM32F4XX) || defined(STM32F7XX) -#define AHB1_EN_MASK STM32_GPIO_EN_MASK -#define AHB1_LPEN_MASK AHB1_EN_MASK - -#else -#error "missing or unsupported platform for GPIOv2 PAL driver" -#endif - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void initgpio(stm32_gpio_t *gpiop, const stm32_gpio_setup_t *config) { - - gpiop->OTYPER = config->otyper; - gpiop->OSPEEDR = config->ospeedr; - gpiop->PUPDR = config->pupdr; - gpiop->ODR = config->odr; - gpiop->AFRL = config->afrl; - gpiop->AFRH = config->afrh; - gpiop->MODER = config->moder; -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief STM32 I/O ports configuration. - * @details Ports A-D(E, F, G, H) clocks enabled. - * - * @param[in] config the STM32 ports configuration - * - * @notapi - */ -void _pal_lld_init(const PALConfig *config) { - - /* - * Enables the GPIO related clocks. - */ -#if defined(STM32L0XX) - RCC->IOPENR |= AHB_EN_MASK; - RCC->IOPSMENR |= AHB_LPEN_MASK; -#elif defined(STM32L1XX) - rccEnableAHB(AHB_EN_MASK, TRUE); - RCC->AHBLPENR |= AHB_LPEN_MASK; -#elif defined(STM32F0XX) - rccEnableAHB(AHB_EN_MASK, TRUE); -#elif defined(STM32F3XX) || defined(STM32F37X) - rccEnableAHB(AHB_EN_MASK, TRUE); -#elif defined(STM32F2XX) || defined(STM32F4XX) || defined(STM32F7XX) - RCC->AHB1ENR |= AHB1_EN_MASK; - RCC->AHB1LPENR |= AHB1_LPEN_MASK; -#endif - - /* - * Initial GPIO setup. - */ -#if STM32_HAS_GPIOA - initgpio(GPIOA, &config->PAData); -#endif -#if STM32_HAS_GPIOB - initgpio(GPIOB, &config->PBData); -#endif -#if STM32_HAS_GPIOC - initgpio(GPIOC, &config->PCData); -#endif -#if STM32_HAS_GPIOD - initgpio(GPIOD, &config->PDData); -#endif -#if STM32_HAS_GPIOE - initgpio(GPIOE, &config->PEData); -#endif -#if STM32_HAS_GPIOF - initgpio(GPIOF, &config->PFData); -#endif -#if STM32_HAS_GPIOG - initgpio(GPIOG, &config->PGData); -#endif -#if STM32_HAS_GPIOH - initgpio(GPIOH, &config->PHData); -#endif -#if STM32_HAS_GPIOI - initgpio(GPIOI, &config->PIData); -#endif -#if STM32_HAS_GPIOJ - initgpio(GPIOJ, &config->PJData); -#endif -#if STM32_HAS_GPIOK - initgpio(GPIOK, &config->PKData); -#endif -} - -/** - * @brief Pads mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * @note @p PAL_MODE_UNCONNECTED is implemented as push pull at minimum - * speed. - * - * @param[in] port the port identifier - * @param[in] mask the group mask - * @param[in] mode the mode - * - * @notapi - */ -void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - iomode_t mode) { - - uint32_t moder = (mode & PAL_STM32_MODE_MASK) >> 0; - uint32_t otyper = (mode & PAL_STM32_OTYPE_MASK) >> 2; - uint32_t ospeedr = (mode & PAL_STM32_OSPEED_MASK) >> 3; - uint32_t pupdr = (mode & PAL_STM32_PUPDR_MASK) >> 5; - uint32_t altr = (mode & PAL_STM32_ALTERNATE_MASK) >> 7; - uint32_t bit = 0; - while (true) { - if ((mask & 1) != 0) { - uint32_t altrmask, m1, m2, m4; - - altrmask = altr << ((bit & 7) * 4); - m1 = 1 << bit; - m2 = 3 << (bit * 2); - m4 = 15 << ((bit & 7) * 4); - port->OTYPER = (port->OTYPER & ~m1) | otyper; - port->OSPEEDR = (port->OSPEEDR & ~m2) | ospeedr; - port->PUPDR = (port->PUPDR & ~m2) | pupdr; - if ((mode & PAL_STM32_MODE_MASK) == PAL_STM32_MODE_ALTERNATE) { - /* If going in alternate mode then the alternate number is set - before switching mode in order to avoid glitches.*/ - if (bit < 8) - port->AFRL = (port->AFRL & ~m4) | altrmask; - else - port->AFRH = (port->AFRH & ~m4) | altrmask; - port->MODER = (port->MODER & ~m2) | moder; - } - else { - /* If going into a non-alternate mode then the mode is switched - before setting the alternate mode in order to avoid glitches.*/ - port->MODER = (port->MODER & ~m2) | moder; - if (bit < 8) - port->AFRL = (port->AFRL & ~m4) | altrmask; - else - port->AFRH = (port->AFRH & ~m4) | altrmask; - } - } - mask >>= 1; - if (!mask) - return; - otyper <<= 1; - ospeedr <<= 2; - pupdr <<= 2; - moder <<= 2; - bit++; - } -} - -#endif /* HAL_USE_PAL */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.h b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.h deleted file mode 100644 index ede10a0917..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.h +++ /dev/null @@ -1,559 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/GPIOv2/pal_lld.h - * @brief STM32 PAL low level driver header. - * - * @addtogroup PAL - * @{ - */ - -#ifndef _PAL_LLD_H_ -#define _PAL_LLD_H_ - -#if HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Unsupported modes and specific modes */ -/*===========================================================================*/ - -#undef PAL_MODE_RESET -#undef PAL_MODE_UNCONNECTED -#undef PAL_MODE_INPUT -#undef PAL_MODE_INPUT_PULLUP -#undef PAL_MODE_INPUT_PULLDOWN -#undef PAL_MODE_INPUT_ANALOG -#undef PAL_MODE_OUTPUT_PUSHPULL -#undef PAL_MODE_OUTPUT_OPENDRAIN - -/** - * @name STM32-specific I/O mode flags - * @{ - */ -#define PAL_STM32_MODE_MASK (3U << 0U) -#define PAL_STM32_MODE_INPUT (0U << 0U) -#define PAL_STM32_MODE_OUTPUT (1U << 0U) -#define PAL_STM32_MODE_ALTERNATE (2U << 0U) -#define PAL_STM32_MODE_ANALOG (3U << 0U) - -#define PAL_STM32_OTYPE_MASK (1U << 2U) -#define PAL_STM32_OTYPE_PUSHPULL (0U << 2U) -#define PAL_STM32_OTYPE_OPENDRAIN (1U << 2U) - -#define PAL_STM32_OSPEED_MASK (3U << 3U) -#define PAL_STM32_OSPEED_LOWEST (0U << 3U) -#if defined(STM32F0XX) || defined(STM32F30X) || defined(STM32F37X) -#define PAL_STM32_OSPEED_MID (1U << 3U) -#else -#define PAL_STM32_OSPEED_MID1 (1U << 3U) -#define PAL_STM32_OSPEED_MID2 (2U << 3U) -#endif -#define PAL_STM32_OSPEED_HIGHEST (3U << 3U) - -#define PAL_STM32_PUPDR_MASK (3U << 5U) -#define PAL_STM32_PUPDR_FLOATING (0U << 5U) -#define PAL_STM32_PUPDR_PULLUP (1U << 5U) -#define PAL_STM32_PUPDR_PULLDOWN (2U << 5U) - -#define PAL_STM32_ALTERNATE_MASK (15U << 7U) -#define PAL_STM32_ALTERNATE(n) ((n) << 7U) - -/** - * @brief Alternate function. - * - * @param[in] n alternate function selector - */ -#define PAL_MODE_ALTERNATE(n) (PAL_STM32_MODE_ALTERNATE | \ - PAL_STM32_ALTERNATE(n)) -/** @} */ - -/** - * @name Standard I/O mode flags - * @{ - */ -/** - * @brief This mode is implemented as input. - */ -#define PAL_MODE_RESET PAL_STM32_MODE_INPUT - -/** - * @brief This mode is implemented as input with pull-up. - */ -#define PAL_MODE_UNCONNECTED PAL_MODE_INPUT_PULLUP - -/** - * @brief Regular input high-Z pad. - */ -#define PAL_MODE_INPUT PAL_STM32_MODE_INPUT - -/** - * @brief Input pad with weak pull up resistor. - */ -#define PAL_MODE_INPUT_PULLUP (PAL_STM32_MODE_INPUT | \ - PAL_STM32_PUPDR_PULLUP) - -/** - * @brief Input pad with weak pull down resistor. - */ -#define PAL_MODE_INPUT_PULLDOWN (PAL_STM32_MODE_INPUT | \ - PAL_STM32_PUPDR_PULLDOWN) - -/** - * @brief Analog input mode. - */ -#define PAL_MODE_INPUT_ANALOG PAL_STM32_MODE_ANALOG - -/** - * @brief Push-pull output pad. - */ -#define PAL_MODE_OUTPUT_PUSHPULL (PAL_STM32_MODE_OUTPUT | \ - PAL_STM32_OTYPE_PUSHPULL) - -/** - * @brief Open-drain output pad. - */ -#define PAL_MODE_OUTPUT_OPENDRAIN (PAL_STM32_MODE_OUTPUT | \ - PAL_STM32_OTYPE_OPENDRAIN) -/** @} */ - -/* Discarded definitions from the ST headers, the PAL driver uses its own - definitions in order to have an unified handling for all devices. - Unfortunately the ST headers have no uniform definitions for the same - objects across the various sub-families.*/ -#undef GPIOA -#undef GPIOB -#undef GPIOC -#undef GPIOD -#undef GPIOE -#undef GPIOF -#undef GPIOG -#undef GPIOH -#undef GPIOI -#undef GPIOJ -#undef GPIOK - -/** - * @name GPIO ports definitions - * @{ - */ -#define GPIOA ((stm32_gpio_t *)GPIOA_BASE) -#define GPIOB ((stm32_gpio_t *)GPIOB_BASE) -#define GPIOC ((stm32_gpio_t *)GPIOC_BASE) -#define GPIOD ((stm32_gpio_t *)GPIOD_BASE) -#define GPIOE ((stm32_gpio_t *)GPIOE_BASE) -#define GPIOF ((stm32_gpio_t *)GPIOF_BASE) -#define GPIOG ((stm32_gpio_t *)GPIOG_BASE) -#define GPIOH ((stm32_gpio_t *)GPIOH_BASE) -#define GPIOI ((stm32_gpio_t *)GPIOI_BASE) -#define GPIOJ ((stm32_gpio_t *)GPIOJ_BASE) -#define GPIOK ((stm32_gpio_t *)GPIOK_BASE) -/** @} */ - -/*===========================================================================*/ -/* I/O Ports Types and constants. */ -/*===========================================================================*/ - -/** - * @name Port related definitions - * @{ - */ -/** - * @brief Width, in bits, of an I/O port. - */ -#define PAL_IOPORTS_WIDTH 16 - -/** - * @brief Whole port mask. - * @details This macro specifies all the valid bits into a port. - */ -#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF) -/** @} */ - -/** - * @name Line handling macros - * @{ - */ -/** - * @brief Forms a line identifier. - * @details A port/pad pair are encoded into an @p ioline_t type. The encoding - * of this type is platform-dependent. - * @note In this driver the pad number is encoded in the lower 4 bits of - * the GPIO address which are guaranteed to be zero. - */ -#define PAL_LINE(port, pad) \ - ((ioline_t)((uint32_t)(port)) | ((uint32_t)(pad))) - -/** - * @brief Decodes a port identifier from a line identifier. - */ -#define PAL_PORT(line) \ - ((stm32_gpio_t *)(((uint32_t)(line)) & 0xFFFFFFF0U)) - -/** - * @brief Decodes a pad identifier from a line identifier. - */ -#define PAL_PAD(line) \ - ((uint32_t)((uint32_t)(line) & 0x0000000FU)) - -/** - * @brief Value identifying an invalid line. - */ -#define PAL_NOLINE 0U -/** @} */ - -/** - * @brief STM32 GPIO registers block. - */ -typedef struct { - - volatile uint32_t MODER; - volatile uint32_t OTYPER; - volatile uint32_t OSPEEDR; - volatile uint32_t PUPDR; - volatile uint32_t IDR; - volatile uint32_t ODR; - volatile union { - uint32_t W; - struct { - uint16_t set; - uint16_t clear; - } H; - } BSRR; - volatile uint32_t LCKR; - volatile uint32_t AFRL; - volatile uint32_t AFRH; - volatile uint32_t BRR; -} stm32_gpio_t; - -/** - * @brief GPIO port setup info. - */ -typedef struct { - /** Initial value for MODER register.*/ - uint32_t moder; - /** Initial value for OTYPER register.*/ - uint32_t otyper; - /** Initial value for OSPEEDR register.*/ - uint32_t ospeedr; - /** Initial value for PUPDR register.*/ - uint32_t pupdr; - /** Initial value for ODR register.*/ - uint32_t odr; - /** Initial value for AFRL register.*/ - uint32_t afrl; - /** Initial value for AFRH register.*/ - uint32_t afrh; -} stm32_gpio_setup_t; - -/** - * @brief STM32 GPIO static initializer. - * @details An instance of this structure must be passed to @p palInit() at - * system startup time in order to initialize the digital I/O - * subsystem. This represents only the initial setup, specific pads - * or whole ports can be reprogrammed at later time. - */ -typedef struct { -#if STM32_HAS_GPIOA || defined(__DOXYGEN__) - /** @brief Port A setup data.*/ - stm32_gpio_setup_t PAData; -#endif -#if STM32_HAS_GPIOB || defined(__DOXYGEN__) - /** @brief Port B setup data.*/ - stm32_gpio_setup_t PBData; -#endif -#if STM32_HAS_GPIOC || defined(__DOXYGEN__) - /** @brief Port C setup data.*/ - stm32_gpio_setup_t PCData; -#endif -#if STM32_HAS_GPIOD || defined(__DOXYGEN__) - /** @brief Port D setup data.*/ - stm32_gpio_setup_t PDData; -#endif -#if STM32_HAS_GPIOE || defined(__DOXYGEN__) - /** @brief Port E setup data.*/ - stm32_gpio_setup_t PEData; -#endif -#if STM32_HAS_GPIOF || defined(__DOXYGEN__) - /** @brief Port F setup data.*/ - stm32_gpio_setup_t PFData; -#endif -#if STM32_HAS_GPIOG || defined(__DOXYGEN__) - /** @brief Port G setup data.*/ - stm32_gpio_setup_t PGData; -#endif -#if STM32_HAS_GPIOH || defined(__DOXYGEN__) - /** @brief Port H setup data.*/ - stm32_gpio_setup_t PHData; -#endif -#if STM32_HAS_GPIOI || defined(__DOXYGEN__) - /** @brief Port I setup data.*/ - stm32_gpio_setup_t PIData; -#endif -#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) - /** @brief Port I setup data.*/ - stm32_gpio_setup_t PJData; -#endif -#if STM32_HAS_GPIOK || defined(__DOXYGEN__) - /** @brief Port I setup data.*/ - stm32_gpio_setup_t PKData; -#endif -} PALConfig; - -/** - * @brief Type of digital I/O port sized unsigned integer. - */ -typedef uint32_t ioportmask_t; - -/** - * @brief Type of digital I/O modes. - */ -typedef uint32_t iomode_t; - -/** - * @brief Type of an I/O line. - */ -typedef uint32_t ioline_t; - -/** - * @brief Port Identifier. - * @details This type can be a scalar or some kind of pointer, do not make - * any assumption about it, use the provided macros when populating - * variables of this type. - */ -typedef stm32_gpio_t * ioportid_t; - -/*===========================================================================*/ -/* I/O Ports Identifiers. */ -/* The low level driver wraps the definitions already present in the STM32 */ -/* firmware library. */ -/*===========================================================================*/ - -/** - * @brief GPIO port A identifier. - */ -#if STM32_HAS_GPIOA || defined(__DOXYGEN__) -#define IOPORT1 GPIOA -#endif - -/** - * @brief GPIO port B identifier. - */ -#if STM32_HAS_GPIOB || defined(__DOXYGEN__) -#define IOPORT2 GPIOB -#endif - -/** - * @brief GPIO port C identifier. - */ -#if STM32_HAS_GPIOC || defined(__DOXYGEN__) -#define IOPORT3 GPIOC -#endif - -/** - * @brief GPIO port D identifier. - */ -#if STM32_HAS_GPIOD || defined(__DOXYGEN__) -#define IOPORT4 GPIOD -#endif - -/** - * @brief GPIO port E identifier. - */ -#if STM32_HAS_GPIOE || defined(__DOXYGEN__) -#define IOPORT5 GPIOE -#endif - -/** - * @brief GPIO port F identifier. - */ -#if STM32_HAS_GPIOF || defined(__DOXYGEN__) -#define IOPORT6 GPIOF -#endif - -/** - * @brief GPIO port G identifier. - */ -#if STM32_HAS_GPIOG || defined(__DOXYGEN__) -#define IOPORT7 GPIOG -#endif - -/** - * @brief GPIO port H identifier. - */ -#if STM32_HAS_GPIOH || defined(__DOXYGEN__) -#define IOPORT8 GPIOH -#endif - -/** - * @brief GPIO port I identifier. - */ -#if STM32_HAS_GPIOI || defined(__DOXYGEN__) -#define IOPORT9 GPIOI -#endif - -/** - * @brief GPIO port J identifier. - */ -#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) -#define IOPORT10 GPIOJ -#endif - -/** - * @brief GPIO port K identifier. - */ -#if STM32_HAS_GPIOK || defined(__DOXYGEN__) -#define IOPORT11 GPIOK -#endif - -/*===========================================================================*/ -/* Implementation, some of the following macros could be implemented as */ -/* functions, if so please put them in pal_lld.c. */ -/*===========================================================================*/ - -/** - * @brief GPIO ports subsystem initialization. - * - * @notapi - */ -#define pal_lld_init(config) _pal_lld_init(config) - -/** - * @brief Reads an I/O port. - * @details This function is implemented by reading the GPIO IDR register, the - * implementation has no side effects. - * @note This function is not meant to be invoked directly by the application - * code. - * - * @param[in] port port identifier - * @return The port bits. - * - * @notapi - */ -#define pal_lld_readport(port) ((port)->IDR) - -/** - * @brief Reads the output latch. - * @details This function is implemented by reading the GPIO ODR register, the - * implementation has no side effects. - * @note This function is not meant to be invoked directly by the application - * code. - * - * @param[in] port port identifier - * @return The latched logical states. - * - * @notapi - */ -#define pal_lld_readlatch(port) ((port)->ODR) - -/** - * @brief Writes on a I/O port. - * @details This function is implemented by writing the GPIO ODR register, the - * implementation has no side effects. - * - * @param[in] port port identifier - * @param[in] bits bits to be written on the specified port - * - * @notapi - */ -#define pal_lld_writeport(port, bits) ((port)->ODR = (bits)) - -/** - * @brief Sets a bits mask on a I/O port. - * @details This function is implemented by writing the GPIO BSRR register, the - * implementation has no side effects. - * - * @param[in] port port identifier - * @param[in] bits bits to be ORed on the specified port - * - * @notapi - */ -#define pal_lld_setport(port, bits) ((port)->BSRR.H.set = (uint16_t)(bits)) - -/** - * @brief Clears a bits mask on a I/O port. - * @details This function is implemented by writing the GPIO BSRR register, the - * implementation has no side effects. - * - * @param[in] port port identifier - * @param[in] bits bits to be cleared on the specified port - * - * @notapi - */ -#define pal_lld_clearport(port, bits) ((port)->BSRR.H.clear = (uint16_t)(bits)) - -/** - * @brief Writes a group of bits. - * @details This function is implemented by writing the GPIO BSRR register, the - * implementation has no side effects. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] offset the group bit offset within the port - * @param[in] bits bits to be written. Values exceeding the group - * width are masked. - * - * @notapi - */ -#define pal_lld_writegroup(port, mask, offset, bits) \ - ((port)->BSRR.W = ((~(bits) & (mask)) << (16U + (offset))) | \ - (((bits) & (mask)) << (offset))) - -/** - * @brief Pads group mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] offset group bit offset within the port - * @param[in] mode group mode - * - * @notapi - */ -#define pal_lld_setgroupmode(port, mask, offset, mode) \ - _pal_lld_setgroupmode(port, mask << offset, mode) - -/** - * @brief Writes a logical state on an output pad. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * @param[in] bit logical value, the value must be @p PAL_LOW or - * @p PAL_HIGH - * - * @notapi - */ -#define pal_lld_writepad(port, pad, bit) pal_lld_writegroup(port, 1, pad, bit) - -extern const PALConfig pal_default_config; - -#ifdef __cplusplus -extern "C" { -#endif - void _pal_lld_init(const PALConfig *config); - void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - iomode_t mode); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_PAL */ - -#endif /* _PAL_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/GPIOv3/pal_lld.c b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/GPIOv3/pal_lld.c deleted file mode 100644 index f4151261bf..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/GPIOv3/pal_lld.c +++ /dev/null @@ -1,199 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/GPIOv3/pal_lld.c - * @brief STM32 PAL low level driver code. - * - * @addtogroup PAL - * @{ - */ - -#include "hal.h" - -#if HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#if defined(STM32L4XX) -#define AHB1_EN_MASK STM32_GPIO_EN_MASK -#define AHB1_LPEN_MASK 0 - -#else -#error "missing or unsupported platform for GPIOv3 PAL driver" -#endif - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void initgpio(stm32_gpio_t *gpiop, const stm32_gpio_setup_t *config) { - - gpiop->OTYPER = config->otyper; - gpiop->ASCR = config->ascr; - gpiop->OSPEEDR = config->ospeedr; - gpiop->PUPDR = config->pupdr; - gpiop->ODR = config->odr; - gpiop->AFRL = config->afrl; - gpiop->AFRH = config->afrh; - gpiop->MODER = config->moder; - gpiop->LOCKR = config->lockr; -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief STM32 I/O ports configuration. - * @details Ports A-D(E, F, G, H) clocks enabled. - * - * @param[in] config the STM32 ports configuration - * - * @notapi - */ -void _pal_lld_init(const PALConfig *config) { - - /* - * Enables the GPIO related clocks. - */ -#if defined(STM32L4XX) - RCC->AHB2ENR |= AHB1_EN_MASK; -#endif - - /* - * Initial GPIO setup. - */ -#if STM32_HAS_GPIOA - initgpio(GPIOA, &config->PAData); -#endif -#if STM32_HAS_GPIOB - initgpio(GPIOB, &config->PBData); -#endif -#if STM32_HAS_GPIOC - initgpio(GPIOC, &config->PCData); -#endif -#if STM32_HAS_GPIOD - initgpio(GPIOD, &config->PDData); -#endif -#if STM32_HAS_GPIOE - initgpio(GPIOE, &config->PEData); -#endif -#if STM32_HAS_GPIOF - initgpio(GPIOF, &config->PFData); -#endif -#if STM32_HAS_GPIOG - initgpio(GPIOG, &config->PGData); -#endif -#if STM32_HAS_GPIOH - initgpio(GPIOH, &config->PHData); -#endif -#if STM32_HAS_GPIOI - initgpio(GPIOI, &config->PIData); -#endif -#if STM32_HAS_GPIOJ - initgpio(GPIOJ, &config->PJData); -#endif -#if STM32_HAS_GPIOK - initgpio(GPIOK, &config->PKData); -#endif -} - -/** - * @brief Pads mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * @note @p PAL_MODE_UNCONNECTED is implemented as push pull at minimum - * speed. - * - * @param[in] port the port identifier - * @param[in] mask the group mask - * @param[in] mode the mode - * - * @notapi - */ -void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - iomode_t mode) { - - uint32_t moder = (mode & PAL_STM32_MODE_MASK) >> 0; - uint32_t otyper = (mode & PAL_STM32_OTYPE_MASK) >> 2; - uint32_t ospeedr = (mode & PAL_STM32_OSPEED_MASK) >> 3; - uint32_t pupdr = (mode & PAL_STM32_PUPDR_MASK) >> 5; - uint32_t altr = (mode & PAL_STM32_ALTERNATE_MASK) >> 7; - uint32_t ascr = (mode & PAL_STM32_ASCR_MASK) >> 11; - uint32_t lockr = (mode & PAL_STM32_LOCKR_MASK) >> 12; - uint32_t bit = 0; - while (true) { - if ((mask & 1) != 0) { - uint32_t altrmask, m1, m2, m4; - - altrmask = altr << ((bit & 7) * 4); - m1 = 1 << bit; - m2 = 3 << (bit * 2); - m4 = 15 << ((bit & 7) * 4); - port->OTYPER = (port->OTYPER & ~m1) | otyper; - port->ASCR = (port->ASCR & ~m1) | ascr; - port->OSPEEDR = (port->OSPEEDR & ~m2) | ospeedr; - port->PUPDR = (port->PUPDR & ~m2) | pupdr; - if ((mode & PAL_STM32_MODE_MASK) == PAL_STM32_MODE_ALTERNATE) { - /* If going in alternate mode then the alternate number is set - before switching mode in order to avoid glitches.*/ - if (bit < 8) - port->AFRL = (port->AFRL & ~m4) | altrmask; - else - port->AFRH = (port->AFRH & ~m4) | altrmask; - port->MODER = (port->MODER & ~m2) | moder; - } - else { - /* If going into a non-alternate mode then the mode is switched - before setting the alternate mode in order to avoid glitches.*/ - port->MODER = (port->MODER & ~m2) | moder; - if (bit < 8) - port->AFRL = (port->AFRL & ~m4) | altrmask; - else - port->AFRH = (port->AFRH & ~m4) | altrmask; - } - port->LOCKR = (port->LOCKR & ~m1) | lockr; - } - mask >>= 1; - if (!mask) - return; - otyper <<= 1; - ospeedr <<= 2; - pupdr <<= 2; - moder <<= 2; - bit++; - } -} - -#endif /* HAL_USE_PAL */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/GPIOv3/pal_lld.h b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/GPIOv3/pal_lld.h deleted file mode 100644 index f2a339de38..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/GPIOv3/pal_lld.h +++ /dev/null @@ -1,571 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/GPIOv3/pal_lld.h - * @brief STM32 PAL low level driver header. - * - * @addtogroup PAL - * @{ - */ - -#ifndef _PAL_LLD_H_ -#define _PAL_LLD_H_ - -#if HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Unsupported modes and specific modes */ -/*===========================================================================*/ - -#undef PAL_MODE_RESET -#undef PAL_MODE_UNCONNECTED -#undef PAL_MODE_INPUT -#undef PAL_MODE_INPUT_PULLUP -#undef PAL_MODE_INPUT_PULLDOWN -#undef PAL_MODE_INPUT_ANALOG -#undef PAL_MODE_OUTPUT_PUSHPULL -#undef PAL_MODE_OUTPUT_OPENDRAIN - -/** - * @name STM32-specific I/O mode flags - * @{ - */ -#define PAL_STM32_MODE_MASK (3U << 0U) -#define PAL_STM32_MODE_INPUT (0U << 0U) -#define PAL_STM32_MODE_OUTPUT (1U << 0U) -#define PAL_STM32_MODE_ALTERNATE (2U << 0U) -#define PAL_STM32_MODE_ANALOG (3U << 0U) - -#define PAL_STM32_OTYPE_MASK (1U << 2U) -#define PAL_STM32_OTYPE_PUSHPULL (0U << 2U) -#define PAL_STM32_OTYPE_OPENDRAIN (1U << 2U) - -#define PAL_STM32_OSPEED_MASK (3U << 3U) -#define PAL_STM32_OSPEED_LOW (0U << 3U) -#define PAL_STM32_OSPEED_MEDIUM (1U << 3U) -#define PAL_STM32_OSPEED_FAST (2U << 3U) -#define PAL_STM32_OSPEED_HIGH (3U << 3U) - -#define PAL_STM32_PUPDR_MASK (3U << 5U) -#define PAL_STM32_PUPDR_FLOATING (0U << 5U) -#define PAL_STM32_PUPDR_PULLUP (1U << 5U) -#define PAL_STM32_PUPDR_PULLDOWN (2U << 5U) - -#define PAL_STM32_ALTERNATE_MASK (15U << 7U) -#define PAL_STM32_ALTERNATE(n) ((n) << 7U) - -#define PAL_STM32_ASCR_MASK (1U << 11U) -#define PAL_STM32_ASCR_OFF (0U << 11U) -#define PAL_STM32_ASCR_ON (1U << 11U) - -#define PAL_STM32_LOCKR_MASK (1U << 12U) -#define PAL_STM32_LOCKR_OFF (0U << 12U) -#define PAL_STM32_LOCKR_ON (1U << 12U) - -/** - * @brief Alternate function. - * - * @param[in] n alternate function selector - */ -#define PAL_MODE_ALTERNATE(n) (PAL_STM32_MODE_ALTERNATE | \ - PAL_STM32_ALTERNATE(n)) -/** @} */ - -/** - * @name Standard I/O mode flags - * @{ - */ -/** - * @brief Implemented as input. - */ -#define PAL_MODE_RESET PAL_STM32_MODE_INPUT - -/** - * @brief Implemented as analog with analog switch disabled and lock. - */ -#define PAL_MODE_UNCONNECTED (PAL_STM32_MODE_ANALOG | \ - PAL_STM32_ASCR_OFF | \ - PAL_STM32_LOCKR_ON) - -/** - * @brief Regular input high-Z pad. - */ -#define PAL_MODE_INPUT PAL_STM32_MODE_INPUT - -/** - * @brief Input pad with weak pull up resistor. - */ -#define PAL_MODE_INPUT_PULLUP (PAL_STM32_MODE_INPUT | \ - PAL_STM32_PUPDR_PULLUP) - -/** - * @brief Input pad with weak pull down resistor. - */ -#define PAL_MODE_INPUT_PULLDOWN (PAL_STM32_MODE_INPUT | \ - PAL_STM32_PUPDR_PULLDOWN) - -/** - * @brief Analog input mode. - */ -#define PAL_MODE_INPUT_ANALOG (PAL_STM32_MODE_ANALOG | \ - PAL_STM32_ASCR_ON) - -/** - * @brief Push-pull output pad. - */ -#define PAL_MODE_OUTPUT_PUSHPULL (PAL_STM32_MODE_OUTPUT | \ - PAL_STM32_OTYPE_PUSHPULL) - -/** - * @brief Open-drain output pad. - */ -#define PAL_MODE_OUTPUT_OPENDRAIN (PAL_STM32_MODE_OUTPUT | \ - PAL_STM32_OTYPE_OPENDRAIN) -/** @} */ - -/* Discarded definitions from the ST headers, the PAL driver uses its own - definitions in order to have an unified handling for all devices. - Unfortunately the ST headers have no uniform definitions for the same - objects across the various sub-families.*/ -#undef GPIOA -#undef GPIOB -#undef GPIOC -#undef GPIOD -#undef GPIOE -#undef GPIOF -#undef GPIOG -#undef GPIOH -#undef GPIOI -#undef GPIOJ -#undef GPIOK - -/** - * @name GPIO ports definitions - * @{ - */ -#define GPIOA ((stm32_gpio_t *)GPIOA_BASE) -#define GPIOB ((stm32_gpio_t *)GPIOB_BASE) -#define GPIOC ((stm32_gpio_t *)GPIOC_BASE) -#define GPIOD ((stm32_gpio_t *)GPIOD_BASE) -#define GPIOE ((stm32_gpio_t *)GPIOE_BASE) -#define GPIOF ((stm32_gpio_t *)GPIOF_BASE) -#define GPIOG ((stm32_gpio_t *)GPIOG_BASE) -#define GPIOH ((stm32_gpio_t *)GPIOH_BASE) -#define GPIOI ((stm32_gpio_t *)GPIOI_BASE) -#define GPIOJ ((stm32_gpio_t *)GPIOJ_BASE) -#define GPIOK ((stm32_gpio_t *)GPIOK_BASE) -/** @} */ - -/*===========================================================================*/ -/* I/O Ports Types and constants. */ -/*===========================================================================*/ - -/** - * @name Port related definitions - * @{ - */ -/** - * @brief Width, in bits, of an I/O port. - */ -#define PAL_IOPORTS_WIDTH 16 - -/** - * @brief Whole port mask. - * @details This macro specifies all the valid bits into a port. - */ -#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF) -/** @} */ - -/** - * @name Line handling macros - * @{ - */ -/** - * @brief Forms a line identifier. - * @details A port/pad pair are encoded into an @p ioline_t type. The encoding - * of this type is platform-dependent. - * @note In this driver the pad number is encoded in the lower 4 bits of - * the GPIO address which are guaranteed to be zero. - */ -#define PAL_LINE(port, pad) \ - ((ioline_t)((uint32_t)(port)) | ((uint32_t)(pad))) - -/** - * @brief Decodes a port identifier from a line identifier. - */ -#define PAL_PORT(line) \ - ((stm32_gpio_t *)(((uint32_t)(line)) & 0xFFFFFFF0U)) - -/** - * @brief Decodes a pad identifier from a line identifier. - */ -#define PAL_PAD(line) \ - ((uint32_t)((uint32_t)(line) & 0x0000000FU)) - -/** - * @brief Value identifying an invalid line. - */ -#define PAL_NOLINE 0U -/** @} */ - -/** - * @brief STM32 GPIO registers block. - */ -typedef struct { - - volatile uint32_t MODER; - volatile uint32_t OTYPER; - volatile uint32_t OSPEEDR; - volatile uint32_t PUPDR; - volatile uint32_t IDR; - volatile uint32_t ODR; - volatile union { - uint32_t W; - struct { - uint16_t set; - uint16_t clear; - } H; - } BSRR; - volatile uint32_t LOCKR; - volatile uint32_t AFRL; - volatile uint32_t AFRH; - volatile uint32_t BRR; - volatile uint32_t ASCR; -} stm32_gpio_t; - -/** - * @brief GPIO port setup info. - */ -typedef struct { - /** Initial value for MODER register.*/ - uint32_t moder; - /** Initial value for OTYPER register.*/ - uint32_t otyper; - /** Initial value for OSPEEDR register.*/ - uint32_t ospeedr; - /** Initial value for PUPDR register.*/ - uint32_t pupdr; - /** Initial value for ODR register.*/ - uint32_t odr; - /** Initial value for AFRL register.*/ - uint32_t afrl; - /** Initial value for AFRH register.*/ - uint32_t afrh; - /** Initial value for ASCR register.*/ - uint32_t ascr; - /** Initial value for LOCKR register.*/ - uint32_t lockr; -} stm32_gpio_setup_t; - -/** - * @brief STM32 GPIO static initializer. - * @details An instance of this structure must be passed to @p palInit() at - * system startup time in order to initialize the digital I/O - * subsystem. This represents only the initial setup, specific pads - * or whole ports can be reprogrammed at later time. - */ -typedef struct { -#if STM32_HAS_GPIOA || defined(__DOXYGEN__) - /** @brief Port A setup data.*/ - stm32_gpio_setup_t PAData; -#endif -#if STM32_HAS_GPIOB || defined(__DOXYGEN__) - /** @brief Port B setup data.*/ - stm32_gpio_setup_t PBData; -#endif -#if STM32_HAS_GPIOC || defined(__DOXYGEN__) - /** @brief Port C setup data.*/ - stm32_gpio_setup_t PCData; -#endif -#if STM32_HAS_GPIOD || defined(__DOXYGEN__) - /** @brief Port D setup data.*/ - stm32_gpio_setup_t PDData; -#endif -#if STM32_HAS_GPIOE || defined(__DOXYGEN__) - /** @brief Port E setup data.*/ - stm32_gpio_setup_t PEData; -#endif -#if STM32_HAS_GPIOF || defined(__DOXYGEN__) - /** @brief Port F setup data.*/ - stm32_gpio_setup_t PFData; -#endif -#if STM32_HAS_GPIOG || defined(__DOXYGEN__) - /** @brief Port G setup data.*/ - stm32_gpio_setup_t PGData; -#endif -#if STM32_HAS_GPIOH || defined(__DOXYGEN__) - /** @brief Port H setup data.*/ - stm32_gpio_setup_t PHData; -#endif -#if STM32_HAS_GPIOI || defined(__DOXYGEN__) - /** @brief Port I setup data.*/ - stm32_gpio_setup_t PIData; -#endif -#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) - /** @brief Port I setup data.*/ - stm32_gpio_setup_t PJData; -#endif -#if STM32_HAS_GPIOK || defined(__DOXYGEN__) - /** @brief Port I setup data.*/ - stm32_gpio_setup_t PKData; -#endif -} PALConfig; - -/** - * @brief Type of digital I/O port sized unsigned integer. - */ -typedef uint32_t ioportmask_t; - -/** - * @brief Type of digital I/O modes. - */ -typedef uint32_t iomode_t; - -/** - * @brief Type of an I/O line. - */ -typedef uint32_t ioline_t; - -/** - * @brief Port Identifier. - * @details This type can be a scalar or some kind of pointer, do not make - * any assumption about it, use the provided macros when populating - * variables of this type. - */ -typedef stm32_gpio_t * ioportid_t; - -/*===========================================================================*/ -/* I/O Ports Identifiers. */ -/* The low level driver wraps the definitions already present in the STM32 */ -/* firmware library. */ -/*===========================================================================*/ - -/** - * @brief GPIO port A identifier. - */ -#if STM32_HAS_GPIOA || defined(__DOXYGEN__) -#define IOPORT1 GPIOA -#endif - -/** - * @brief GPIO port B identifier. - */ -#if STM32_HAS_GPIOB || defined(__DOXYGEN__) -#define IOPORT2 GPIOB -#endif - -/** - * @brief GPIO port C identifier. - */ -#if STM32_HAS_GPIOC || defined(__DOXYGEN__) -#define IOPORT3 GPIOC -#endif - -/** - * @brief GPIO port D identifier. - */ -#if STM32_HAS_GPIOD || defined(__DOXYGEN__) -#define IOPORT4 GPIOD -#endif - -/** - * @brief GPIO port E identifier. - */ -#if STM32_HAS_GPIOE || defined(__DOXYGEN__) -#define IOPORT5 GPIOE -#endif - -/** - * @brief GPIO port F identifier. - */ -#if STM32_HAS_GPIOF || defined(__DOXYGEN__) -#define IOPORT6 GPIOF -#endif - -/** - * @brief GPIO port G identifier. - */ -#if STM32_HAS_GPIOG || defined(__DOXYGEN__) -#define IOPORT7 GPIOG -#endif - -/** - * @brief GPIO port H identifier. - */ -#if STM32_HAS_GPIOH || defined(__DOXYGEN__) -#define IOPORT8 GPIOH -#endif - -/** - * @brief GPIO port I identifier. - */ -#if STM32_HAS_GPIOI || defined(__DOXYGEN__) -#define IOPORT9 GPIOI -#endif - -/** - * @brief GPIO port J identifier. - */ -#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) -#define IOPORT10 GPIOJ -#endif - -/** - * @brief GPIO port K identifier. - */ -#if STM32_HAS_GPIOK || defined(__DOXYGEN__) -#define IOPORT11 GPIOK -#endif - -/*===========================================================================*/ -/* Implementation, some of the following macros could be implemented as */ -/* functions, if so please put them in pal_lld.c. */ -/*===========================================================================*/ - -/** - * @brief GPIO ports subsystem initialization. - * - * @notapi - */ -#define pal_lld_init(config) _pal_lld_init(config) - -/** - * @brief Reads an I/O port. - * @details This function is implemented by reading the GPIO IDR register, the - * implementation has no side effects. - * @note This function is not meant to be invoked directly by the application - * code. - * - * @param[in] port port identifier - * @return The port bits. - * - * @notapi - */ -#define pal_lld_readport(port) ((port)->IDR) - -/** - * @brief Reads the output latch. - * @details This function is implemented by reading the GPIO ODR register, the - * implementation has no side effects. - * @note This function is not meant to be invoked directly by the application - * code. - * - * @param[in] port port identifier - * @return The latched logical states. - * - * @notapi - */ -#define pal_lld_readlatch(port) ((port)->ODR) - -/** - * @brief Writes on a I/O port. - * @details This function is implemented by writing the GPIO ODR register, the - * implementation has no side effects. - * - * @param[in] port port identifier - * @param[in] bits bits to be written on the specified port - * - * @notapi - */ -#define pal_lld_writeport(port, bits) ((port)->ODR = (bits)) - -/** - * @brief Sets a bits mask on a I/O port. - * @details This function is implemented by writing the GPIO BSRR register, the - * implementation has no side effects. - * - * @param[in] port port identifier - * @param[in] bits bits to be ORed on the specified port - * - * @notapi - */ -#define pal_lld_setport(port, bits) ((port)->BSRR.H.set = (uint16_t)(bits)) - -/** - * @brief Clears a bits mask on a I/O port. - * @details This function is implemented by writing the GPIO BSRR register, the - * implementation has no side effects. - * - * @param[in] port port identifier - * @param[in] bits bits to be cleared on the specified port - * - * @notapi - */ -#define pal_lld_clearport(port, bits) ((port)->BSRR.H.clear = (uint16_t)(bits)) - -/** - * @brief Writes a group of bits. - * @details This function is implemented by writing the GPIO BSRR register, the - * implementation has no side effects. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] offset the group bit offset within the port - * @param[in] bits bits to be written. Values exceeding the group - * width are masked. - * - * @notapi - */ -#define pal_lld_writegroup(port, mask, offset, bits) \ - ((port)->BSRR.W = ((~(bits) & (mask)) << (16U + (offset))) | \ - (((bits) & (mask)) << (offset))) - -/** - * @brief Pads group mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] offset group bit offset within the port - * @param[in] mode group mode - * - * @notapi - */ -#define pal_lld_setgroupmode(port, mask, offset, mode) \ - _pal_lld_setgroupmode(port, mask << offset, mode) - -/** - * @brief Writes a logical state on an output pad. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * @param[in] bit logical value, the value must be @p PAL_LOW or - * @p PAL_HIGH - * - * @notapi - */ -#define pal_lld_writepad(port, pad, bit) pal_lld_writegroup(port, 1, pad, bit) - -extern const PALConfig pal_default_config; - -#ifdef __cplusplus -extern "C" { -#endif - void _pal_lld_init(const PALConfig *config); - void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - iomode_t mode); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_PAL */ - -#endif /* _PAL_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/I2Cv1/i2c_lld.c b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/I2Cv1/i2c_lld.c deleted file mode 100644 index 3955b6a66c..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/I2Cv1/i2c_lld.c +++ /dev/null @@ -1,855 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Concepts and parts of this file have been contributed by Uladzimir Pylinsky - aka barthess. - */ - -/** - * @file STM32/I2Cv1/i2c_lld.c - * @brief STM32 I2C subsystem low level driver source. - * - * @addtogroup I2C - * @{ - */ - -#include "hal.h" - -#if HAL_USE_I2C || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define I2C1_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_RX_DMA_STREAM, \ - STM32_I2C1_RX_DMA_CHN) - -#define I2C1_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_TX_DMA_STREAM, \ - STM32_I2C1_TX_DMA_CHN) - -#define I2C2_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_I2C_I2C2_RX_DMA_STREAM, \ - STM32_I2C2_RX_DMA_CHN) - -#define I2C2_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_I2C_I2C2_TX_DMA_STREAM, \ - STM32_I2C2_TX_DMA_CHN) - -#define I2C3_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_I2C_I2C3_RX_DMA_STREAM, \ - STM32_I2C3_RX_DMA_CHN) - -#define I2C3_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_I2C_I2C3_TX_DMA_STREAM, \ - STM32_I2C3_TX_DMA_CHN) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#define I2C_EV5_MASTER_MODE_SELECT \ - ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY) << 16) | I2C_SR1_SB)) - -#define I2C_EV6_MASTER_TRA_MODE_SELECTED \ - ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY | I2C_SR2_TRA) << 16) | \ - I2C_SR1_ADDR | I2C_SR1_TXE)) - -#define I2C_EV6_MASTER_REC_MODE_SELECTED \ - ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY)<< 16) | I2C_SR1_ADDR)) - -#define I2C_EV8_2_MASTER_BYTE_TRANSMITTED \ - ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY | I2C_SR2_TRA) << 16) | \ - I2C_SR1_BTF | I2C_SR1_TXE)) - -#define I2C_EV9_MASTER_ADD10 \ - ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY) << 16) | I2C_SR1_ADD10)) - -#define I2C_EV_MASK 0x00FFFFFF - -#define I2C_ERROR_MASK \ - ((uint16_t)(I2C_SR1_BERR | I2C_SR1_ARLO | I2C_SR1_AF | I2C_SR1_OVR | \ - I2C_SR1_PECERR | I2C_SR1_TIMEOUT | I2C_SR1_SMBALERT)) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief I2C1 driver identifier.*/ -#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__) -I2CDriver I2CD1; -#endif - -/** @brief I2C2 driver identifier.*/ -#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__) -I2CDriver I2CD2; -#endif - -/** @brief I2C3 driver identifier.*/ -#if STM32_I2C_USE_I2C3 || defined(__DOXYGEN__) -I2CDriver I2CD3; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Aborts an I2C transaction. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -static void i2c_lld_abort_operation(I2CDriver *i2cp) { - I2C_TypeDef *dp = i2cp->i2c; - - /* Stops the I2C peripheral.*/ - dp->CR1 = I2C_CR1_SWRST; - dp->CR1 = 0; - dp->CR2 = 0; - dp->SR1 = 0; - - /* Stops the associated DMA streams.*/ - dmaStreamDisable(i2cp->dmatx); - dmaStreamDisable(i2cp->dmarx); -} - -/** - * @brief Set clock speed. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -static void i2c_lld_set_clock(I2CDriver *i2cp) { - I2C_TypeDef *dp = i2cp->i2c; - uint16_t regCCR, clock_div; - int32_t clock_speed = i2cp->config->clock_speed; - i2cdutycycle_t duty = i2cp->config->duty_cycle; - - osalDbgCheck((i2cp != NULL) && - (clock_speed > 0) && - (clock_speed <= 4000000)); - - /* CR2 Configuration.*/ - dp->CR2 &= (uint16_t)~I2C_CR2_FREQ; - dp->CR2 |= (uint16_t)I2C_CLK_FREQ; - - /* CCR Configuration.*/ - regCCR = 0; - clock_div = I2C_CCR_CCR; - - if (clock_speed <= 100000) { - /* Configure clock_div in standard mode.*/ - osalDbgAssert(duty == STD_DUTY_CYCLE, "invalid standard mode duty cycle"); - - /* Standard mode clock_div calculate: Tlow/Thigh = 1/1.*/ - osalDbgAssert((STM32_PCLK1 % (clock_speed * 2)) == 0, - "PCLK1 must be divisible without remainder"); - clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 2)); - - osalDbgAssert(clock_div >= 0x04, - "clock divider less then 0x04 not allowed"); - regCCR |= (clock_div & I2C_CCR_CCR); - - /* Sets the Maximum Rise Time for standard mode.*/ - dp->TRISE = I2C_CLK_FREQ + 1; - } - else if (clock_speed <= 400000) { - /* Configure clock_div in fast mode.*/ - osalDbgAssert((duty == FAST_DUTY_CYCLE_2) || - (duty == FAST_DUTY_CYCLE_16_9), - "invalid fast mode duty cycle"); - - if (duty == FAST_DUTY_CYCLE_2) { - /* Fast mode clock_div calculate: Tlow/Thigh = 2/1.*/ - osalDbgAssert((STM32_PCLK1 % (clock_speed * 3)) == 0, - "PCLK1 must be divided without remainder"); - clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 3)); - } - else if (duty == FAST_DUTY_CYCLE_16_9) { - /* Fast mode clock_div calculate: Tlow/Thigh = 16/9.*/ - osalDbgAssert((STM32_PCLK1 % (clock_speed * 25)) == 0, - "PCLK1 must be divided without remainder"); - clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 25)); - regCCR |= I2C_CCR_DUTY; - } - - osalDbgAssert(clock_div >= 0x01, - "clock divider less then 0x04 not allowed"); - regCCR |= (I2C_CCR_FS | (clock_div & I2C_CCR_CCR)); - - /* Sets the Maximum Rise Time for fast mode.*/ - dp->TRISE = (I2C_CLK_FREQ * 300 / 1000) + 1; - } - - osalDbgAssert((clock_div <= I2C_CCR_CCR), "the selected clock is too low"); - - dp->CCR = regCCR; -} - -/** - * @brief Set operation mode of I2C hardware. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -static void i2c_lld_set_opmode(I2CDriver *i2cp) { - I2C_TypeDef *dp = i2cp->i2c; - i2copmode_t opmode = i2cp->config->op_mode; - uint16_t regCR1; - - regCR1 = dp->CR1; - switch (opmode) { - case OPMODE_I2C: - regCR1 &= (uint16_t)~(I2C_CR1_SMBUS|I2C_CR1_SMBTYPE); - break; - case OPMODE_SMBUS_DEVICE: - regCR1 |= I2C_CR1_SMBUS; - regCR1 &= (uint16_t)~(I2C_CR1_SMBTYPE); - break; - case OPMODE_SMBUS_HOST: - regCR1 |= (I2C_CR1_SMBUS|I2C_CR1_SMBTYPE); - break; - } - dp->CR1 = regCR1; -} - -/** - * @brief I2C shared ISR code. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp) { - I2C_TypeDef *dp = i2cp->i2c; - uint32_t regSR2 = dp->SR2; - uint32_t event = dp->SR1; - - /* Interrupts are disabled just before dmaStreamEnable() because there - is no need of interrupts until next transaction begin. All the work is - done by the DMA.*/ - switch (I2C_EV_MASK & (event | (regSR2 << 16))) { - case I2C_EV5_MASTER_MODE_SELECT: - if ((i2cp->addr >> 8) > 0) { - /* 10-bit address: 1 1 1 1 0 X X R/W */ - dp->DR = 0xF0 | (0x6 & (i2cp->addr >> 8)) | (0x1 & i2cp->addr); - } else { - dp->DR = i2cp->addr; - } - break; - case I2C_EV9_MASTER_ADD10: - /* Set second addr byte (10-bit addressing)*/ - dp->DR = (0xFF & (i2cp->addr >> 1)); - break; - case I2C_EV6_MASTER_REC_MODE_SELECTED: - dp->CR2 &= ~I2C_CR2_ITEVTEN; - dmaStreamEnable(i2cp->dmarx); - dp->CR2 |= I2C_CR2_LAST; /* Needed in receiver mode. */ - if (dmaStreamGetTransactionSize(i2cp->dmarx) < 2) - dp->CR1 &= ~I2C_CR1_ACK; - break; - case I2C_EV6_MASTER_TRA_MODE_SELECTED: - dp->CR2 &= ~I2C_CR2_ITEVTEN; - dmaStreamEnable(i2cp->dmatx); - break; - case I2C_EV8_2_MASTER_BYTE_TRANSMITTED: - /* Catches BTF event after the end of transmission.*/ - if (dmaStreamGetTransactionSize(i2cp->dmarx) > 0) { - /* Starts "read after write" operation, LSB = 1 -> receive.*/ - i2cp->addr |= 0x01; - dp->CR1 |= I2C_CR1_START | I2C_CR1_ACK; - return; - } - dp->CR2 &= ~I2C_CR2_ITEVTEN; - dp->CR1 |= I2C_CR1_STOP; - _i2c_wakeup_isr(i2cp); - break; - default: - break; - } - /* Clear ADDR flag. */ - if (event & (I2C_SR1_ADDR | I2C_SR1_ADD10)) - (void)dp->SR2; -} - -/** - * @brief DMA RX end IRQ handler. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] flags pre-shifted content of the ISR register - * - * @notapi - */ -static void i2c_lld_serve_rx_end_irq(I2CDriver *i2cp, uint32_t flags) { - I2C_TypeDef *dp = i2cp->i2c; - - /* DMA errors handling.*/ -#if defined(STM32_I2C_DMA_ERROR_HOOK) - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - STM32_I2C_DMA_ERROR_HOOK(i2cp); - } -#else - (void)flags; -#endif - - dmaStreamDisable(i2cp->dmarx); - - dp->CR2 &= ~I2C_CR2_LAST; - dp->CR1 &= ~I2C_CR1_ACK; - dp->CR1 |= I2C_CR1_STOP; - _i2c_wakeup_isr(i2cp); -} - -/** - * @brief DMA TX end IRQ handler. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -static void i2c_lld_serve_tx_end_irq(I2CDriver *i2cp, uint32_t flags) { - I2C_TypeDef *dp = i2cp->i2c; - - /* DMA errors handling.*/ -#if defined(STM32_I2C_DMA_ERROR_HOOK) - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - STM32_I2C_DMA_ERROR_HOOK(i2cp); - } -#else - (void)flags; -#endif - - dmaStreamDisable(i2cp->dmatx); - /* Enables interrupts to catch BTF event meaning transmission part complete. - Interrupt handler will decide to generate STOP or to begin receiving part - of R/W transaction itself.*/ - dp->CR2 |= I2C_CR2_ITEVTEN; -} - -/** - * @brief I2C error handler. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] sr content of the SR1 register to be decoded - * - * @notapi - */ -static void i2c_lld_serve_error_interrupt(I2CDriver *i2cp, uint16_t sr) { - - /* Clears interrupt flags just to be safe.*/ - dmaStreamDisable(i2cp->dmatx); - dmaStreamDisable(i2cp->dmarx); - - i2cp->errors = I2C_NO_ERROR; - - if (sr & I2C_SR1_BERR) /* Bus error. */ - i2cp->errors |= I2C_BUS_ERROR; - - if (sr & I2C_SR1_ARLO) /* Arbitration lost. */ - i2cp->errors |= I2C_ARBITRATION_LOST; - - if (sr & I2C_SR1_AF) { /* Acknowledge fail. */ - i2cp->i2c->CR2 &= ~I2C_CR2_ITEVTEN; - i2cp->i2c->CR1 |= I2C_CR1_STOP; /* Setting stop bit. */ - i2cp->errors |= I2C_ACK_FAILURE; - } - - if (sr & I2C_SR1_OVR) /* Overrun. */ - i2cp->errors |= I2C_OVERRUN; - - if (sr & I2C_SR1_TIMEOUT) /* SMBus Timeout. */ - i2cp->errors |= I2C_TIMEOUT; - - if (sr & I2C_SR1_PECERR) /* PEC error. */ - i2cp->errors |= I2C_PEC_ERROR; - - if (sr & I2C_SR1_SMBALERT) /* SMBus alert. */ - i2cp->errors |= I2C_SMB_ALERT; - - /* If some error has been identified then sends wakes the waiting thread.*/ - if (i2cp->errors != I2C_NO_ERROR) - _i2c_wakeup_error_isr(i2cp); -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__) -/** - * @brief I2C1 event interrupt handler. - * - * @notapi - */ -OSAL_IRQ_HANDLER(STM32_I2C1_EVENT_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - i2c_lld_serve_event_interrupt(&I2CD1); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief I2C1 error interrupt handler. - */ -OSAL_IRQ_HANDLER(STM32_I2C1_ERROR_HANDLER) { - uint16_t sr = I2CD1.i2c->SR1; - - OSAL_IRQ_PROLOGUE(); - - I2CD1.i2c->SR1 = ~(sr & I2C_ERROR_MASK); - i2c_lld_serve_error_interrupt(&I2CD1, sr); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_I2C_USE_I2C1 */ - -#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__) -/** - * @brief I2C2 event interrupt handler. - * - * @notapi - */ -OSAL_IRQ_HANDLER(STM32_I2C2_EVENT_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - i2c_lld_serve_event_interrupt(&I2CD2); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief I2C2 error interrupt handler. - * - * @notapi - */ -OSAL_IRQ_HANDLER(STM32_I2C2_ERROR_HANDLER) { - uint16_t sr = I2CD2.i2c->SR1; - - OSAL_IRQ_PROLOGUE(); - - I2CD2.i2c->SR1 = ~(sr & I2C_ERROR_MASK); - i2c_lld_serve_error_interrupt(&I2CD2, sr); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_I2C_USE_I2C2 */ - -#if STM32_I2C_USE_I2C3 || defined(__DOXYGEN__) -/** - * @brief I2C3 event interrupt handler. - * - * @notapi - */ -OSAL_IRQ_HANDLER(STM32_I2C3_EVENT_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - i2c_lld_serve_event_interrupt(&I2CD3); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief I2C3 error interrupt handler. - * - * @notapi - */ -OSAL_IRQ_HANDLER(STM32_I2C3_ERROR_HANDLER) { - uint16_t sr = I2CD3.i2c->SR1; - - OSAL_IRQ_PROLOGUE(); - - I2CD3.i2c->SR1 = ~(sr & I2C_ERROR_MASK); - i2c_lld_serve_error_interrupt(&I2CD3, sr); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_I2C_USE_I2C3 */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level I2C driver initialization. - * - * @notapi - */ -void i2c_lld_init(void) { - -#if STM32_I2C_USE_I2C1 - i2cObjectInit(&I2CD1); - I2CD1.thread = NULL; - I2CD1.i2c = I2C1; - I2CD1.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C1_RX_DMA_STREAM); - I2CD1.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C1_TX_DMA_STREAM); -#endif /* STM32_I2C_USE_I2C1 */ - -#if STM32_I2C_USE_I2C2 - i2cObjectInit(&I2CD2); - I2CD2.thread = NULL; - I2CD2.i2c = I2C2; - I2CD2.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C2_RX_DMA_STREAM); - I2CD2.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C2_TX_DMA_STREAM); -#endif /* STM32_I2C_USE_I2C2 */ - -#if STM32_I2C_USE_I2C3 - i2cObjectInit(&I2CD3); - I2CD3.thread = NULL; - I2CD3.i2c = I2C3; - I2CD3.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C3_RX_DMA_STREAM); - I2CD3.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C3_TX_DMA_STREAM); -#endif /* STM32_I2C_USE_I2C3 */ -} - -/** - * @brief Configures and activates the I2C peripheral. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -void i2c_lld_start(I2CDriver *i2cp) { - I2C_TypeDef *dp = i2cp->i2c; - - i2cp->txdmamode = STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE | - STM32_DMA_CR_MINC | STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE | STM32_DMA_CR_TCIE | - STM32_DMA_CR_DIR_M2P; - i2cp->rxdmamode = STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE | - STM32_DMA_CR_MINC | STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE | STM32_DMA_CR_TCIE | - STM32_DMA_CR_DIR_P2M; - - /* If in stopped state then enables the I2C and DMA clocks.*/ - if (i2cp->state == I2C_STOP) { - -#if STM32_I2C_USE_I2C1 - if (&I2CD1 == i2cp) { - bool b; - - rccResetI2C1(); - b = dmaStreamAllocate(i2cp->dmarx, - STM32_I2C_I2C1_IRQ_PRIORITY, - (stm32_dmaisr_t)i2c_lld_serve_rx_end_irq, - (void *)i2cp); - osalDbgAssert(!b, "stream already allocated"); - b = dmaStreamAllocate(i2cp->dmatx, - STM32_I2C_I2C1_IRQ_PRIORITY, - (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq, - (void *)i2cp); - osalDbgAssert(!b, "stream already allocated"); - rccEnableI2C1(FALSE); - nvicEnableVector(I2C1_EV_IRQn, STM32_I2C_I2C1_IRQ_PRIORITY); - nvicEnableVector(I2C1_ER_IRQn, STM32_I2C_I2C1_IRQ_PRIORITY); - - i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C1_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY); - i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C1_TX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY); - } -#endif /* STM32_I2C_USE_I2C1 */ - -#if STM32_I2C_USE_I2C2 - if (&I2CD2 == i2cp) { - bool b; - - rccResetI2C2(); - b = dmaStreamAllocate(i2cp->dmarx, - STM32_I2C_I2C2_IRQ_PRIORITY, - (stm32_dmaisr_t)i2c_lld_serve_rx_end_irq, - (void *)i2cp); - osalDbgAssert(!b, "stream already allocated"); - b = dmaStreamAllocate(i2cp->dmatx, - STM32_I2C_I2C2_IRQ_PRIORITY, - (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq, - (void *)i2cp); - osalDbgAssert(!b, "stream already allocated"); - rccEnableI2C2(FALSE); - nvicEnableVector(I2C2_EV_IRQn, STM32_I2C_I2C2_IRQ_PRIORITY); - nvicEnableVector(I2C2_ER_IRQn, STM32_I2C_I2C2_IRQ_PRIORITY); - - i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C2_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY); - i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C2_TX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY); - } -#endif /* STM32_I2C_USE_I2C2 */ - -#if STM32_I2C_USE_I2C3 - if (&I2CD3 == i2cp) { - bool b; - - rccResetI2C3(); - b = dmaStreamAllocate(i2cp->dmarx, - STM32_I2C_I2C3_IRQ_PRIORITY, - (stm32_dmaisr_t)i2c_lld_serve_rx_end_irq, - (void *)i2cp); - osalDbgAssert(!b, "stream already allocated"); - b = dmaStreamAllocate(i2cp->dmatx, - STM32_I2C_I2C3_IRQ_PRIORITY, - (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq, - (void *)i2cp); - osalDbgAssert(!b, "stream already allocated"); - rccEnableI2C3(FALSE); - nvicEnableVector(I2C3_EV_IRQn, STM32_I2C_I2C3_IRQ_PRIORITY); - nvicEnableVector(I2C3_ER_IRQn, STM32_I2C_I2C3_IRQ_PRIORITY); - - i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C3_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_I2C_I2C3_DMA_PRIORITY); - i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C3_TX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_I2C_I2C3_DMA_PRIORITY); - } -#endif /* STM32_I2C_USE_I2C3 */ - } - - /* I2C registers pointed by the DMA.*/ - dmaStreamSetPeripheral(i2cp->dmarx, &dp->DR); - dmaStreamSetPeripheral(i2cp->dmatx, &dp->DR); - - /* Reset i2c peripheral.*/ - dp->CR1 = I2C_CR1_SWRST; - dp->CR1 = 0; - dp->CR2 = I2C_CR2_ITERREN | I2C_CR2_DMAEN; - - /* Setup I2C parameters.*/ - i2c_lld_set_clock(i2cp); - i2c_lld_set_opmode(i2cp); - - /* Ready to go.*/ - dp->CR1 |= I2C_CR1_PE; -} - -/** - * @brief Deactivates the I2C peripheral. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -void i2c_lld_stop(I2CDriver *i2cp) { - - /* If not in stopped state then disables the I2C clock.*/ - if (i2cp->state != I2C_STOP) { - - /* I2C disable.*/ - i2c_lld_abort_operation(i2cp); - dmaStreamRelease(i2cp->dmatx); - dmaStreamRelease(i2cp->dmarx); - -#if STM32_I2C_USE_I2C1 - if (&I2CD1 == i2cp) { - nvicDisableVector(I2C1_EV_IRQn); - nvicDisableVector(I2C1_ER_IRQn); - rccDisableI2C1(FALSE); - } -#endif - -#if STM32_I2C_USE_I2C2 - if (&I2CD2 == i2cp) { - nvicDisableVector(I2C2_EV_IRQn); - nvicDisableVector(I2C2_ER_IRQn); - rccDisableI2C2(FALSE); - } -#endif - -#if STM32_I2C_USE_I2C3 - if (&I2CD3 == i2cp) { - nvicDisableVector(I2C3_EV_IRQn); - nvicDisableVector(I2C3_ER_IRQn); - rccDisableI2C3(FALSE); - } -#endif - } -} - -/** - * @brief Receives data via the I2C bus as master. - * @details Number of receiving bytes must be more than 1 on STM32F1x. This is - * hardware restriction. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] addr slave device address - * @param[out] rxbuf pointer to the receive buffer - * @param[in] rxbytes number of bytes to be received - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval MSG_OK if the function succeeded. - * @retval MSG_RESET if one or more I2C errors occurred, the errors can - * be retrieved using @p i2cGetErrors(). - * @retval MSG_TIMEOUT if a timeout occurred before operation end. After a - * timeout the driver must be stopped and restarted - * because the bus is in an uncertain state. - * - * @notapi - */ -msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, - uint8_t *rxbuf, size_t rxbytes, - systime_t timeout) { - I2C_TypeDef *dp = i2cp->i2c; - systime_t start, end; - -#if defined(STM32F1XX_I2C) - osalDbgCheck(rxbytes > 1); -#endif - - /* Resetting error flags for this transfer.*/ - i2cp->errors = I2C_NO_ERROR; - - /* Initializes driver fields, LSB = 1 -> receive.*/ - i2cp->addr = (addr << 1) | 0x01; - - /* Releases the lock from high level driver.*/ - osalSysUnlock(); - - /* RX DMA setup.*/ - dmaStreamSetMode(i2cp->dmarx, i2cp->rxdmamode); - dmaStreamSetMemory0(i2cp->dmarx, rxbuf); - dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes); - - /* Calculating the time window for the timeout on the busy bus condition.*/ - start = osalOsGetSystemTimeX(); - end = start + OSAL_MS2ST(STM32_I2C_BUSY_TIMEOUT); - - /* Waits until BUSY flag is reset or, alternatively, for a timeout - condition.*/ - while (true) { - osalSysLock(); - - /* If the bus is not busy then the operation can continue, note, the - loop is exited in the locked state.*/ - if (!(dp->SR2 & I2C_SR2_BUSY) && !(dp->CR1 & I2C_CR1_STOP)) - break; - - /* If the system time went outside the allowed window then a timeout - condition is returned.*/ - if (!osalOsIsTimeWithinX(osalOsGetSystemTimeX(), start, end)) - return MSG_TIMEOUT; - - osalSysUnlock(); - } - - /* Starts the operation.*/ - dp->CR2 |= I2C_CR2_ITEVTEN; - dp->CR1 |= I2C_CR1_START | I2C_CR1_ACK; - - /* Waits for the operation completion or a timeout.*/ - return osalThreadSuspendTimeoutS(&i2cp->thread, timeout); -} - -/** - * @brief Transmits data via the I2C bus as master. - * @details Number of receiving bytes must be 0 or more than 1 on STM32F1x. - * This is hardware restriction. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] addr slave device address - * @param[in] txbuf pointer to the transmit buffer - * @param[in] txbytes number of bytes to be transmitted - * @param[out] rxbuf pointer to the receive buffer - * @param[in] rxbytes number of bytes to be received - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval MSG_OK if the function succeeded. - * @retval MSG_RESET if one or more I2C errors occurred, the errors can - * be retrieved using @p i2cGetErrors(). - * @retval MSG_TIMEOUT if a timeout occurred before operation end. After a - * timeout the driver must be stopped and restarted - * because the bus is in an uncertain state. - * - * @notapi - */ -msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, - const uint8_t *txbuf, size_t txbytes, - uint8_t *rxbuf, size_t rxbytes, - systime_t timeout) { - I2C_TypeDef *dp = i2cp->i2c; - systime_t start, end; - -#if defined(STM32F1XX_I2C) - osalDbgCheck((rxbytes == 0) || ((rxbytes > 1) && (rxbuf != NULL))); -#endif - - /* Resetting error flags for this transfer.*/ - i2cp->errors = I2C_NO_ERROR; - - /* Initializes driver fields, LSB = 0 -> transmit.*/ - i2cp->addr = (addr << 1); - - /* Releases the lock from high level driver.*/ - osalSysUnlock(); - - /* TX DMA setup.*/ - dmaStreamSetMode(i2cp->dmatx, i2cp->txdmamode); - dmaStreamSetMemory0(i2cp->dmatx, txbuf); - dmaStreamSetTransactionSize(i2cp->dmatx, txbytes); - - /* RX DMA setup.*/ - dmaStreamSetMode(i2cp->dmarx, i2cp->rxdmamode); - dmaStreamSetMemory0(i2cp->dmarx, rxbuf); - dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes); - - /* Calculating the time window for the timeout on the busy bus condition.*/ - start = osalOsGetSystemTimeX(); - end = start + OSAL_MS2ST(STM32_I2C_BUSY_TIMEOUT); - - /* Waits until BUSY flag is reset or, alternatively, for a timeout - condition.*/ - while (true) { - osalSysLock(); - - /* If the bus is not busy then the operation can continue, note, the - loop is exited in the locked state.*/ - if (!(dp->SR2 & I2C_SR2_BUSY) && !(dp->CR1 & I2C_CR1_STOP)) - break; - - /* If the system time went outside the allowed window then a timeout - condition is returned.*/ - if (!osalOsIsTimeWithinX(osalOsGetSystemTimeX(), start, end)) - return MSG_TIMEOUT; - - osalSysUnlock(); - } - - /* Starts the operation.*/ - dp->CR2 |= I2C_CR2_ITEVTEN; - dp->CR1 |= I2C_CR1_START; - - /* Waits for the operation completion or a timeout.*/ - return osalThreadSuspendTimeoutS(&i2cp->thread, timeout); -} - -#endif /* HAL_USE_I2C */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/I2Cv1/i2c_lld.h b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/I2Cv1/i2c_lld.h deleted file mode 100644 index 2ddbbd067d..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/I2Cv1/i2c_lld.h +++ /dev/null @@ -1,513 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Concepts and parts of this file have been contributed by Uladzimir Pylinsky - aka barthess. - */ - -/** - * @file STM32/I2Cv1/i2c_lld.h - * @brief STM32 I2C subsystem low level driver header. - * - * @addtogroup I2C - * @{ - */ - -#ifndef _I2C_LLD_H_ -#define _I2C_LLD_H_ - -#if HAL_USE_I2C || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Peripheral clock frequency. - */ -#define I2C_CLK_FREQ ((STM32_PCLK1) / 1000000) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief I2C1 driver enable switch. - * @details If set to @p TRUE the support for I2C1 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_I2C_USE_I2C1) || defined(__DOXYGEN__) -#define STM32_I2C_USE_I2C1 FALSE -#endif - -/** - * @brief I2C2 driver enable switch. - * @details If set to @p TRUE the support for I2C2 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_I2C_USE_I2C2) || defined(__DOXYGEN__) -#define STM32_I2C_USE_I2C2 FALSE -#endif - -/** - * @brief I2C3 driver enable switch. - * @details If set to @p TRUE the support for I2C3 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_I2C_USE_I2C3) || defined(__DOXYGEN__) -#define STM32_I2C_USE_I2C3 FALSE -#endif - -/** - * @brief I2C timeout on busy condition in milliseconds. - */ -#if !defined(STM32_I2C_BUSY_TIMEOUT) || defined(__DOXYGEN__) -#define STM32_I2C_BUSY_TIMEOUT 50 -#endif - -/** - * @brief I2C1 interrupt priority level setting. - */ -#if !defined(STM32_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2C_I2C1_IRQ_PRIORITY 10 -#endif - -/** - * @brief I2C2 interrupt priority level setting. - */ -#if !defined(STM32_I2C_I2C2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2C_I2C2_IRQ_PRIORITY 10 -#endif - -/** - * @brief I2C3 interrupt priority level setting. - */ -#if !defined(STM32_I2C_I2C3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2C_I2C3_IRQ_PRIORITY 10 -#endif - -/** -* @brief I2C1 DMA priority (0..3|lowest..highest). -* @note The priority level is used for both the TX and RX DMA streams but -* because of the streams ordering the RX stream has always priority -* over the TX stream. -*/ -#if !defined(STM32_I2C_I2C1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2C_I2C1_DMA_PRIORITY 1 -#endif - -/** -* @brief I2C2 DMA priority (0..3|lowest..highest). -* @note The priority level is used for both the TX and RX DMA streams but -* because of the streams ordering the RX stream has always priority -* over the TX stream. -*/ -#if !defined(STM32_I2C_I2C2_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2C_I2C2_DMA_PRIORITY 1 -#endif - -/** -* @brief I2C3 DMA priority (0..3|lowest..highest). -* @note The priority level is used for both the TX and RX DMA streams but -* because of the streams ordering the RX stream has always priority -* over the TX stream. -*/ -#if !defined(STM32_I2C_I2C3_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2C_I2C3_DMA_PRIORITY 1 -#endif - -/** - * @brief I2C DMA error hook. - * @note The default action for DMA errors is a system halt because DMA - * error can only happen because programming errors. - */ -#if !defined(STM32_I2C_DMA_ERROR_HOOK) || defined(__DOXYGEN__) -#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") -#endif - -#if STM32_ADVANCED_DMA || defined(__DOXYGEN__) - -/** - * @brief DMA stream used for I2C1 RX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_I2C_I2C1_RX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#endif - -/** - * @brief DMA stream used for I2C1 TX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_I2C_I2C1_TX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#endif - -/** - * @brief DMA stream used for I2C2 RX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_I2C_I2C2_RX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#endif - -/** - * @brief DMA stream used for I2C2 TX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_I2C_I2C2_TX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#endif - -/** - * @brief DMA stream used for I2C3 RX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_I2C_I2C3_RX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#endif - -/** - * @brief DMA stream used for I2C3 TX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_I2C_I2C3_TX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#endif - -#else /* !STM32_ADVANCED_DMA */ - -/* Fixed streams for platforms using the old DMA peripheral, the values are - valid for both STM32F1xx and STM32L1xx.*/ -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) - -#endif /* !STM32_ADVANCED_DMA*/ - -/* Flag for the whole STM32F1XX family. */ -#if defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \ - defined(STM32F10X_HD_VL) || defined(STM32F10X_LD) || \ - defined(STM32F10X_MD) || defined(STM32F10X_HD) || \ - defined(STM32F10X_XL) || defined(STM32F10X_CL) -#define STM32F1XX_I2C -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/** @brief error checks */ -#if STM32_I2C_USE_I2C1 && !STM32_HAS_I2C1 -#error "I2C1 not present in the selected device" -#endif - -#if STM32_I2C_USE_I2C2 && !STM32_HAS_I2C2 -#error "I2C2 not present in the selected device" -#endif - -#if STM32_I2C_USE_I2C3 && !STM32_HAS_I2C3 -#error "I2C3 not present in the selected device" -#endif - -#if !STM32_I2C_USE_I2C1 && !STM32_I2C_USE_I2C2 && \ - !STM32_I2C_USE_I2C3 -#error "I2C driver activated but no I2C peripheral assigned" -#endif - -#if STM32_I2C_USE_I2C1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2C_I2C1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to I2C1" -#endif - -#if STM32_I2C_USE_I2C2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2C_I2C2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to I2C2" -#endif - -#if STM32_I2C_USE_I2C3 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2C_I2C3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to I2C3" -#endif - -#if STM32_I2C_USE_I2C1 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_I2C_I2C1_DMA_PRIORITY) -#error "Invalid DMA priority assigned to I2C1" -#endif - -#if STM32_I2C_USE_I2C2 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_I2C_I2C2_DMA_PRIORITY) -#error "Invalid DMA priority assigned to I2C2" -#endif - -#if STM32_I2C_USE_I2C3 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_I2C_I2C3_DMA_PRIORITY) -#error "Invalid DMA priority assigned to I2C3" -#endif - -/* The following checks are only required when there is a DMA able to - reassign streams to different channels.*/ -#if STM32_ADVANCED_DMA -/* Check on the presence of the DMA streams settings in mcuconf.h.*/ -#if STM32_I2C_USE_I2C1 && (!defined(STM32_I2C_I2C1_RX_DMA_STREAM) || \ - !defined(STM32_I2C_I2C1_TX_DMA_STREAM)) -#error "I2C1 DMA streams not defined" -#endif - -#if STM32_I2C_USE_I2C2 && (!defined(STM32_I2C_I2C2_RX_DMA_STREAM) || \ - !defined(STM32_I2C_I2C2_TX_DMA_STREAM)) -#error "I2C2 DMA streams not defined" -#endif - -/* Check on the validity of the assigned DMA channels.*/ -#if STM32_I2C_USE_I2C1 && \ - !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_RX_DMA_STREAM, \ - STM32_I2C1_RX_DMA_MSK) -#error "invalid DMA stream associated to I2C1 RX" -#endif - -#if STM32_I2C_USE_I2C1 && \ - !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_TX_DMA_STREAM, \ - STM32_I2C1_TX_DMA_MSK) -#error "invalid DMA stream associated to I2C1 TX" -#endif - -#if STM32_I2C_USE_I2C2 && \ - !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C2_RX_DMA_STREAM, \ - STM32_I2C2_RX_DMA_MSK) -#error "invalid DMA stream associated to I2C2 RX" -#endif - -#if STM32_I2C_USE_I2C2 && \ - !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C2_TX_DMA_STREAM, \ - STM32_I2C2_TX_DMA_MSK) -#error "invalid DMA stream associated to I2C2 TX" -#endif - -#if STM32_I2C_USE_I2C3 && \ - !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C3_RX_DMA_STREAM, \ - STM32_I2C3_RX_DMA_MSK) -#error "invalid DMA stream associated to I2C3 RX" -#endif - -#if STM32_I2C_USE_I2C3 && \ - !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C3_TX_DMA_STREAM, \ - STM32_I2C3_TX_DMA_MSK) -#error "invalid DMA stream associated to I2C3 TX" -#endif -#endif /* STM32_ADVANCED_DMA */ - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif - -/* Check clock range. */ -#if defined(STM32F4XX) -#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 42) -#error "I2C peripheral clock frequency out of range." -#endif - -#elif defined(STM32L1XX) -#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 32) -#error "I2C peripheral clock frequency out of range." -#endif - -#elif defined(STM32F2XX) -#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 30) -#error "I2C peripheral clock frequency out of range." -#endif - -#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \ - defined(STM32F10X_HD_VL) -#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 24) -#error "I2C peripheral clock frequency out of range." -#endif - -#elif defined(STM32F10X_LD) || defined(STM32F10X_MD) || \ - defined(STM32F10X_HD) || defined(STM32F10X_XL) || \ - defined(STM32F10X_CL) -#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 36) -#error "I2C peripheral clock frequency out of range." -#endif -#else -#error "unspecified, unsupported or invalid STM32 platform" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type representing an I2C address. - */ -typedef uint16_t i2caddr_t; - -/** - * @brief Type of I2C driver condition flags. - */ -typedef uint32_t i2cflags_t; - -/** - * @brief Supported modes for the I2C bus. - */ -typedef enum { - OPMODE_I2C = 1, - OPMODE_SMBUS_DEVICE = 2, - OPMODE_SMBUS_HOST = 3, -} i2copmode_t; - -/** - * @brief Supported duty cycle modes for the I2C bus. - */ -typedef enum { - STD_DUTY_CYCLE = 1, - FAST_DUTY_CYCLE_2 = 2, - FAST_DUTY_CYCLE_16_9 = 3, -} i2cdutycycle_t; - -/** - * @brief Type of I2C driver configuration structure. - */ -typedef struct { - /* End of the mandatory fields.*/ - i2copmode_t op_mode; /**< @brief Specifies the I2C mode. */ - uint32_t clock_speed; /**< @brief Specifies the clock frequency. - @note Must be set to a value lower - than 400kHz. */ - i2cdutycycle_t duty_cycle; /**< @brief Specifies the I2C fast mode - duty cycle. */ -} I2CConfig; - -/** - * @brief Type of a structure representing an I2C driver. - */ -typedef struct I2CDriver I2CDriver; - -/** - * @brief Structure representing an I2C driver. - */ -struct I2CDriver { - /** - * @brief Driver state. - */ - i2cstate_t state; - /** - * @brief Current configuration data. - */ - const I2CConfig *config; - /** - * @brief Error flags. - */ - i2cflags_t errors; -#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the bus. - */ - mutex_t mutex; -#endif /* I2C_USE_MUTUAL_EXCLUSION */ -#if defined(I2C_DRIVER_EXT_FIELDS) - I2C_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Thread waiting for I/O completion. - */ - thread_reference_t thread; - /** - * @brief Current slave address without R/W bit. - */ - i2caddr_t addr; - /** - * @brief RX DMA mode bit mask. - */ - uint32_t rxdmamode; - /** - * @brief TX DMA mode bit mask. - */ - uint32_t txdmamode; - /** - * @brief Receive DMA channel. - */ - const stm32_dma_stream_t *dmarx; - /** - * @brief Transmit DMA channel. - */ - const stm32_dma_stream_t *dmatx; - /** - * @brief Pointer to the I2Cx registers block. - */ - I2C_TypeDef *i2c; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Get errors from I2C driver. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -#define i2c_lld_get_errors(i2cp) ((i2cp)->errors) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -#if STM32_I2C_USE_I2C1 -extern I2CDriver I2CD1; -#endif - -#if STM32_I2C_USE_I2C2 -extern I2CDriver I2CD2; -#endif - -#if STM32_I2C_USE_I2C3 -extern I2CDriver I2CD3; -#endif -#endif /* !defined(__DOXYGEN__) */ - -#ifdef __cplusplus -extern "C" { -#endif - void i2c_lld_init(void); - void i2c_lld_start(I2CDriver *i2cp); - void i2c_lld_stop(I2CDriver *i2cp); - msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, - const uint8_t *txbuf, size_t txbytes, - uint8_t *rxbuf, size_t rxbytes, - systime_t timeout); - msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, - uint8_t *rxbuf, size_t rxbytes, - systime_t timeout); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_I2C */ - -#endif /* _I2C_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.c b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.c deleted file mode 100644 index d67e13915d..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.c +++ /dev/null @@ -1,1156 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/I2Cv2/i2c_lld.c - * @brief STM32 I2C subsystem low level driver source. - * - * @addtogroup I2C - * @{ - */ - -#include "hal.h" - -#if HAL_USE_I2C || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#if STM32_I2C_USE_DMA == TRUE -#define DMAMODE_COMMON \ - (STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE | \ - STM32_DMA_CR_MINC | STM32_DMA_CR_DMEIE | \ - STM32_DMA_CR_TEIE | STM32_DMA_CR_TCIE) - -#define I2C1_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_RX_DMA_STREAM, \ - STM32_I2C1_RX_DMA_CHN) - -#define I2C1_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_TX_DMA_STREAM, \ - STM32_I2C1_TX_DMA_CHN) - -#define I2C2_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_I2C_I2C2_RX_DMA_STREAM, \ - STM32_I2C2_RX_DMA_CHN) - -#define I2C2_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_I2C_I2C2_TX_DMA_STREAM, \ - STM32_I2C2_TX_DMA_CHN) - -#define I2C3_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_I2C_I2C3_RX_DMA_STREAM, \ - STM32_I2C3_RX_DMA_CHN) - -#define I2C3_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_I2C_I2C3_TX_DMA_STREAM, \ - STM32_I2C3_TX_DMA_CHN) - -#define I2C4_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_I2C_I2C4_RX_DMA_STREAM, \ - STM32_I2C4_RX_DMA_CHN) - -#define I2C4_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_I2C_I2C4_TX_DMA_STREAM, \ - STM32_I2C4_TX_DMA_CHN) -#endif /* STM32_I2C_USE_DMA == TRUE */ - -#if STM32_I2C_USE_DMA == TRUE -#define i2c_lld_get_rxbytes(i2cp) dmaStreamGetTransactionSize((i2cp)->dmarx) -#define i2c_lld_get_txbytes(i2cp) dmaStreamGetTransactionSize((i2cp)->dmatx) -#else -#define i2c_lld_get_rxbytes(i2cp) (i2cp)->rxbytes -#define i2c_lld_get_txbytes(i2cp) (i2cp)->txbytes -#endif - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#define I2C_ERROR_MASK \ - ((uint32_t)(I2C_ISR_BERR | I2C_ISR_ARLO | I2C_ISR_OVR | I2C_ISR_PECERR | \ - I2C_ISR_TIMEOUT | I2C_ISR_ALERT)) - -#define I2C_INT_MASK \ - ((uint32_t)(I2C_ISR_TCR | I2C_ISR_TC | I2C_ISR_STOPF | I2C_ISR_NACKF | \ - I2C_ISR_ADDR | I2C_ISR_RXNE | I2C_ISR_TXIS)) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief I2C1 driver identifier.*/ -#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__) -I2CDriver I2CD1; -#endif - -/** @brief I2C2 driver identifier.*/ -#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__) -I2CDriver I2CD2; -#endif - -/** @brief I2C3 driver identifier.*/ -#if STM32_I2C_USE_I2C3 || defined(__DOXYGEN__) -I2CDriver I2CD3; -#endif - -/** @brief I2C4 driver identifier.*/ -#if STM32_I2C_USE_I2C4 || defined(__DOXYGEN__) -I2CDriver I2CD4; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Slave address setup. - * @note The RW bit is set to zero internally. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] addr slave device address - * - * @notapi - */ -static void i2c_lld_set_address(I2CDriver *i2cp, i2caddr_t addr) { - I2C_TypeDef *dp = i2cp->i2c; - - /* Address alignment depends on the addressing mode selected.*/ - if ((i2cp->config->cr2 & I2C_CR2_ADD10) == 0U) - dp->CR2 = (uint32_t)addr << 1U; - else - dp->CR2 = (uint32_t)addr; -} - -/** - * @brief I2C RX transfer setup. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -static void i2c_lld_setup_rx_transfer(I2CDriver *i2cp) { - I2C_TypeDef *dp = i2cp->i2c; - uint32_t reload; - size_t n; - - /* The unit can transfer 255 bytes maximum in a single operation.*/ - n = i2c_lld_get_rxbytes(i2cp); - if (n > 255U) { - n = 255U; - reload = I2C_CR2_RELOAD; - } - else { - reload = 0U; - } - - /* Configures the CR2 registers with both the calculated and static - settings.*/ - dp->CR2 = (dp->CR2 & ~(I2C_CR2_NBYTES | I2C_CR2_RELOAD)) | i2cp->config->cr2 | - I2C_CR2_RD_WRN | (n << 16U) | reload; -} - -/** - * @brief I2C TX transfer setup. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -static void i2c_lld_setup_tx_transfer(I2CDriver *i2cp) { - I2C_TypeDef *dp = i2cp->i2c; - uint32_t reload; - size_t n; - - /* The unit can transfer 255 bytes maximum in a single operation.*/ - n = i2c_lld_get_txbytes(i2cp); - if (n > 255U) { - n = 255U; - reload = I2C_CR2_RELOAD; - } - else { - reload = 0U; - } - - /* Configures the CR2 registers with both the calculated and static - settings.*/ - dp->CR2 = (dp->CR2 & ~(I2C_CR2_NBYTES | I2C_CR2_RELOAD)) | i2cp->config->cr2 | - (n << 16U) | reload; -} - -/** - * @brief Aborts an I2C transaction. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -static void i2c_lld_abort_operation(I2CDriver *i2cp) { - I2C_TypeDef *dp = i2cp->i2c; - - if (dp->CR1 & I2C_CR1_PE) { - /* Stops the I2C peripheral.*/ - dp->CR1 &= ~I2C_CR1_PE; - while (dp->CR1 & I2C_CR1_PE) - dp->CR1 &= ~I2C_CR1_PE; - dp->CR1 |= I2C_CR1_PE; - } - -#if STM32_I2C_USE_DMA == TRUE - /* Stops the associated DMA streams.*/ - dmaStreamDisable(i2cp->dmatx); - dmaStreamDisable(i2cp->dmarx); -#else - dp->CR1 &= ~(I2C_CR1_TXIE | I2C_CR1_RXIE); -#endif -} - -/** - * @brief I2C shared ISR code. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] isr content of the ISR register to be decoded - * - * @notapi - */ -static void i2c_lld_serve_interrupt(I2CDriver *i2cp, uint32_t isr) { - I2C_TypeDef *dp = i2cp->i2c; - - /* Special case of a received NACK, the transfer is aborted.*/ - if ((isr & I2C_ISR_NACKF) != 0U) { -#if STM32_I2C_USE_DMA == TRUE - /* Stops the associated DMA streams.*/ - dmaStreamDisable(i2cp->dmatx); - dmaStreamDisable(i2cp->dmarx); -#endif - - /* Error flag.*/ - i2cp->errors |= I2C_ACK_FAILURE; - - /* Transaction finished sending the STOP.*/ - dp->CR2 |= I2C_CR2_STOP; - - /* Make sure no more interrupts.*/ - dp->CR1 &= ~(I2C_CR1_TCIE | I2C_CR1_TXIE | I2C_CR1_RXIE); - - /* Errors are signaled to the upper layer.*/ - _i2c_wakeup_error_isr(i2cp); - - return; - } - -#if STM32_I2C_USE_DMA == FALSE - /* Handling of data transfer if the DMA mode is disabled.*/ - { - uint32_t cr1 = dp->CR1; - - if (i2cp->state == I2C_ACTIVE_TX) { - /* Transmission phase.*/ - if (((cr1 &I2C_CR1_TXIE) != 0U) && ((isr & I2C_ISR_TXIS) != 0U)) { - dp->TXDR = (uint32_t)*i2cp->txptr; - i2cp->txptr++; - i2cp->txbytes--; - if (i2cp->txbytes == 0U) { - dp->CR1 &= ~I2C_CR1_TXIE; - } - } - } - else { - /* Receive phase.*/ - if (((cr1 & I2C_CR1_RXIE) != 0U) && ((isr & I2C_ISR_RXNE) != 0U)) { - *i2cp->rxptr = (uint8_t)dp->RXDR; - i2cp->rxptr++; - i2cp->rxbytes--; - if (i2cp->rxbytes == 0U) { - dp->CR1 &= ~I2C_CR1_RXIE; - } - } - } - } -#endif - - /* Partial transfer handling, restarting the transfer and returning.*/ - if ((isr & I2C_ISR_TCR) != 0U) { - if (i2cp->state == I2C_ACTIVE_TX) { - i2c_lld_setup_tx_transfer(i2cp); - } - else { - i2c_lld_setup_rx_transfer(i2cp); - } - return; - } - - /* The following condition is true if a transfer phase has been completed.*/ - if ((isr & I2C_ISR_TC) != 0U) { - if (i2cp->state == I2C_ACTIVE_TX) { - /* End of the transmit phase.*/ - -#if STM32_I2C_USE_DMA == TRUE - /* Disabling TX DMA channel.*/ - dmaStreamDisable(i2cp->dmatx); -#endif - - /* Starting receive phase if necessary.*/ - if (i2c_lld_get_rxbytes(i2cp) > 0U) { - /* Setting up the peripheral.*/ - i2c_lld_setup_rx_transfer(i2cp); - -#if STM32_I2C_USE_DMA == TRUE - /* Enabling RX DMA.*/ - dmaStreamEnable(i2cp->dmarx); -#else - /* RX interrupt enabled.*/ - dp->CR1 |= I2C_CR1_RXIE; -#endif - - /* Starts the read operation.*/ - dp->CR2 |= I2C_CR2_START; - - /* State change.*/ - i2cp->state = I2C_ACTIVE_RX; - - /* Note, returning because the transaction is not over yet.*/ - return; - } - } - else { - /* End of the receive phase.*/ -#if STM32_I2C_USE_DMA == TRUE - /* Disabling RX DMA channel.*/ - dmaStreamDisable(i2cp->dmarx); -#endif - } - - /* Transaction finished sending the STOP.*/ - dp->CR2 |= I2C_CR2_STOP; - - /* Make sure no more 'Transfer Complete' interrupts.*/ - dp->CR1 &= ~I2C_CR1_TCIE; - - /* Normal transaction end.*/ - _i2c_wakeup_isr(i2cp); - } -} - -/** - * @brief I2C error handler. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] isr content of the ISR register to be decoded - * - * @notapi - */ -static void i2c_lld_serve_error_interrupt(I2CDriver *i2cp, uint32_t isr) { - -#if STM32_I2C_USE_DMA == TRUE - /* Clears DMA interrupt flags just to be safe.*/ - dmaStreamDisable(i2cp->dmatx); - dmaStreamDisable(i2cp->dmarx); -#else - /* Disabling RX and TX interrupts.*/ - i2cp->i2c->CR1 &= ~(I2C_CR1_TXIE | I2C_CR1_RXIE); -#endif - - if (isr & I2C_ISR_BERR) - i2cp->errors |= I2C_BUS_ERROR; - - if (isr & I2C_ISR_ARLO) - i2cp->errors |= I2C_ARBITRATION_LOST; - - if (isr & I2C_ISR_OVR) - i2cp->errors |= I2C_OVERRUN; - - if (isr & I2C_ISR_TIMEOUT) - i2cp->errors |= I2C_TIMEOUT; - - /* If some error has been identified then sends wakes the waiting thread.*/ - if (i2cp->errors != I2C_NO_ERROR) - _i2c_wakeup_error_isr(i2cp); -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__) -#if defined(STM32_I2C1_GLOBAL_HANDLER) || defined(__DOXYGEN__) -/** - * @brief I2C1 event interrupt handler. - * - * @notapi - */ -OSAL_IRQ_HANDLER(STM32_I2C1_GLOBAL_HANDLER) { - uint32_t isr = I2CD1.i2c->ISR; - - OSAL_IRQ_PROLOGUE(); - - /* Clearing IRQ bits.*/ - I2CD1.i2c->ICR = isr; - - if (isr & I2C_ERROR_MASK) - i2c_lld_serve_error_interrupt(&I2CD1, isr); - else if (isr & I2C_INT_MASK) - i2c_lld_serve_interrupt(&I2CD1, isr); - - OSAL_IRQ_EPILOGUE(); -} - -#elif defined(STM32_I2C1_EVENT_HANDLER) && defined(STM32_I2C1_ERROR_HANDLER) -OSAL_IRQ_HANDLER(STM32_I2C1_EVENT_HANDLER) { - uint32_t isr = I2CD1.i2c->ISR; - - OSAL_IRQ_PROLOGUE(); - - /* Clearing IRQ bits.*/ - I2CD1.i2c->ICR = isr & I2C_INT_MASK; - - i2c_lld_serve_interrupt(&I2CD1, isr); - - OSAL_IRQ_EPILOGUE(); -} - -OSAL_IRQ_HANDLER(STM32_I2C1_ERROR_HANDLER) { - uint32_t isr = I2CD1.i2c->ISR; - - OSAL_IRQ_PROLOGUE(); - - /* Clearing IRQ bits.*/ - I2CD1.i2c->ICR = isr & I2C_ERROR_MASK; - - i2c_lld_serve_error_interrupt(&I2CD1, isr); - - OSAL_IRQ_EPILOGUE(); -} - -#else -#error "I2C1 interrupt handlers not defined" -#endif -#endif /* STM32_I2C_USE_I2C1 */ - -#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__) -#if defined(STM32_I2C2_GLOBAL_HANDLER) || defined(__DOXYGEN__) -/** - * @brief I2C2 event interrupt handler. - * - * @notapi - */ -OSAL_IRQ_HANDLER(STM32_I2C2_GLOBAL_HANDLER) { - uint32_t isr = I2CD2.i2c->ISR; - - OSAL_IRQ_PROLOGUE(); - - /* Clearing IRQ bits.*/ - I2CD2.i2c->ICR = isr; - - if (isr & I2C_ERROR_MASK) - i2c_lld_serve_error_interrupt(&I2CD2, isr); - else if (isr & I2C_INT_MASK) - i2c_lld_serve_interrupt(&I2CD2, isr); - - OSAL_IRQ_EPILOGUE(); -} - -#elif defined(STM32_I2C2_EVENT_HANDLER) && defined(STM32_I2C2_ERROR_HANDLER) -OSAL_IRQ_HANDLER(STM32_I2C2_EVENT_HANDLER) { - uint32_t isr = I2CD2.i2c->ISR; - - OSAL_IRQ_PROLOGUE(); - - /* Clearing IRQ bits.*/ - I2CD2.i2c->ICR = isr & I2C_INT_MASK; - - i2c_lld_serve_interrupt(&I2CD2, isr); - - OSAL_IRQ_EPILOGUE(); -} - -OSAL_IRQ_HANDLER(STM32_I2C2_ERROR_HANDLER) { - uint32_t isr = I2CD2.i2c->ISR; - - OSAL_IRQ_PROLOGUE(); - - /* Clearing IRQ bits.*/ - I2CD2.i2c->ICR = isr & I2C_ERROR_MASK; - - i2c_lld_serve_error_interrupt(&I2CD2, isr); - - OSAL_IRQ_EPILOGUE(); -} - -#else -#error "I2C2 interrupt handlers not defined" -#endif -#endif /* STM32_I2C_USE_I2C2 */ - -#if STM32_I2C_USE_I2C3 || defined(__DOXYGEN__) -#if defined(STM32_I2C3_GLOBAL_HANDLER) || defined(__DOXYGEN__) -/** - * @brief I2C3 event interrupt handler. - * - * @notapi - */ -OSAL_IRQ_HANDLER(STM32_I2C3_GLOBAL_HANDLER) { - uint32_t isr = I2CD3.i2c->ISR; - - OSAL_IRQ_PROLOGUE(); - - /* Clearing IRQ bits.*/ - I2CD3.i2c->ICR = isr; - - if (isr & I2C_ERROR_MASK) - i2c_lld_serve_error_interrupt(&I2CD3, isr); - else if (isr & I2C_INT_MASK) - i2c_lld_serve_interrupt(&I2CD3, isr); - - OSAL_IRQ_EPILOGUE(); -} - -#elif defined(STM32_I2C3_EVENT_HANDLER) && defined(STM32_I2C3_ERROR_HANDLER) -OSAL_IRQ_HANDLER(STM32_I2C3_EVENT_HANDLER) { - uint32_t isr = I2CD3.i2c->ISR; - - OSAL_IRQ_PROLOGUE(); - - /* Clearing IRQ bits.*/ - I2CD3.i2c->ICR = isr & I2C_INT_MASK; - - i2c_lld_serve_interrupt(&I2CD3, isr); - - OSAL_IRQ_EPILOGUE(); -} - -OSAL_IRQ_HANDLER(STM32_I2C3_ERROR_HANDLER) { - uint32_t isr = I2CD3.i2c->ISR; - - OSAL_IRQ_PROLOGUE(); - - /* Clearing IRQ bits.*/ - I2CD3.i2c->ICR = isr & I2C_ERROR_MASK; - - i2c_lld_serve_error_interrupt(&I2CD3, isr); - - OSAL_IRQ_EPILOGUE(); -} - -#else -#error "I2C3 interrupt handlers not defined" -#endif -#endif /* STM32_I2C_USE_I2C3 */ - -#if STM32_I2C_USE_I2C4 || defined(__DOXYGEN__) -#if defined(STM32_I2C4_GLOBAL_HANDLER) || defined(__DOXYGEN__) -/** - * @brief I2C4 event interrupt handler. - * - * @notapi - */ -OSAL_IRQ_HANDLER(STM32_I2C4_GLOBAL_HANDLER) { - uint32_t isr = I2CD4.i2c->ISR; - - OSAL_IRQ_PROLOGUE(); - - /* Clearing IRQ bits.*/ - I2CD4.i2c->ICR = isr; - - if (isr & I2C_ERROR_MASK) - i2c_lld_serve_error_interrupt(&I2CD4, isr); - else if (isr & I2C_INT_MASK) - i2c_lld_serve_interrupt(&I2CD4, isr); - - OSAL_IRQ_EPILOGUE(); -} - -#elif defined(STM32_I2C4_EVENT_HANDLER) && defined(STM32_I2C4_ERROR_HANDLER) -OSAL_IRQ_HANDLER(STM32_I2C4_EVENT_HANDLER) { - uint32_t isr = I2CD4.i2c->ISR; - - OSAL_IRQ_PROLOGUE(); - - /* Clearing IRQ bits.*/ - I2CD4.i2c->ICR = isr & I2C_INT_MASK; - - i2c_lld_serve_interrupt(&I2CD4, isr); - - OSAL_IRQ_EPILOGUE(); -} - -OSAL_IRQ_HANDLER(STM32_I2C4_ERROR_HANDLER) { - uint32_t isr = I2CD4.i2c->ISR; - - OSAL_IRQ_PROLOGUE(); - - /* Clearing IRQ bits.*/ - I2CD4.i2c->ICR = isr & I2C_ERROR_MASK; - - i2c_lld_serve_error_interrupt(&I2CD4, isr); - - OSAL_IRQ_EPILOGUE(); -} - -#else -#error "I2C4 interrupt handlers not defined" -#endif -#endif /* STM32_I2C_USE_I2C4 */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level I2C driver initialization. - * - * @notapi - */ -void i2c_lld_init(void) { - -#if STM32_I2C_USE_I2C1 - i2cObjectInit(&I2CD1); - I2CD1.thread = NULL; - I2CD1.i2c = I2C1; -#if STM32_I2C_USE_DMA == TRUE - I2CD1.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C1_RX_DMA_STREAM); - I2CD1.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C1_TX_DMA_STREAM); -#endif -#endif /* STM32_I2C_USE_I2C1 */ - -#if STM32_I2C_USE_I2C2 - i2cObjectInit(&I2CD2); - I2CD2.thread = NULL; - I2CD2.i2c = I2C2; -#if STM32_I2C_USE_DMA == TRUE - I2CD2.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C2_RX_DMA_STREAM); - I2CD2.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C2_TX_DMA_STREAM); -#endif -#endif /* STM32_I2C_USE_I2C2 */ - -#if STM32_I2C_USE_I2C3 - i2cObjectInit(&I2CD3); - I2CD3.thread = NULL; - I2CD3.i2c = I2C3; -#if STM32_I2C_USE_DMA == TRUE - I2CD3.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C3_RX_DMA_STREAM); - I2CD3.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C3_TX_DMA_STREAM); -#endif -#endif /* STM32_I2C_USE_I2C3 */ - -#if STM32_I2C_USE_I2C4 - i2cObjectInit(&I2CD4); - I2CD4.thread = NULL; - I2CD4.i2c = I2C4; -#if STM32_I2C_USE_DMA == TRUE - I2CD4.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C4_RX_DMA_STREAM); - I2CD4.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C4_TX_DMA_STREAM); -#endif -#endif /* STM32_I2C_USE_I2C4 */ -} - -/** - * @brief Configures and activates the I2C peripheral. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -void i2c_lld_start(I2CDriver *i2cp) { - I2C_TypeDef *dp = i2cp->i2c; - -#if STM32_I2C_USE_DMA == TRUE - /* Common DMA modes.*/ - i2cp->txdmamode = DMAMODE_COMMON | STM32_DMA_CR_DIR_M2P; - i2cp->rxdmamode = DMAMODE_COMMON | STM32_DMA_CR_DIR_P2M; -#endif - - /* Make sure I2C peripheral is disabled */ - dp->CR1 &= ~I2C_CR1_PE; - - /* If in stopped state then enables the I2C and DMA clocks.*/ - if (i2cp->state == I2C_STOP) { - -#if STM32_I2C_USE_I2C1 - if (&I2CD1 == i2cp) { - - rccResetI2C1(); - rccEnableI2C1(FALSE); -#if STM32_I2C_USE_DMA == TRUE - { - bool b; - - b = dmaStreamAllocate(i2cp->dmarx, - STM32_I2C_I2C1_IRQ_PRIORITY, - NULL, - (void *)i2cp); - osalDbgAssert(!b, "stream already allocated"); - b = dmaStreamAllocate(i2cp->dmatx, - STM32_I2C_I2C1_IRQ_PRIORITY, - NULL, - (void *)i2cp); - osalDbgAssert(!b, "stream already allocated"); - - i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C1_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY); - i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C1_TX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY); - } -#endif /* STM32_I2C_USE_DMA == TRUE */ - -#if defined(STM32_I2C1_GLOBAL_NUMBER) || defined(__DOXYGEN__) - nvicEnableVector(STM32_I2C1_GLOBAL_NUMBER, STM32_I2C_I2C1_IRQ_PRIORITY); -#elif defined(STM32_I2C1_EVENT_NUMBER) && defined(STM32_I2C1_ERROR_NUMBER) - nvicEnableVector(STM32_I2C1_EVENT_NUMBER, STM32_I2C_I2C1_IRQ_PRIORITY); - nvicEnableVector(STM32_I2C1_ERROR_NUMBER, STM32_I2C_I2C1_IRQ_PRIORITY); -#else -#error "I2C1 interrupt numbers not defined" -#endif - } -#endif /* STM32_I2C_USE_I2C1 */ - -#if STM32_I2C_USE_I2C2 - if (&I2CD2 == i2cp) { - - rccResetI2C2(); - rccEnableI2C2(FALSE); -#if STM32_I2C_USE_DMA == TRUE - { - bool b; - - b = dmaStreamAllocate(i2cp->dmarx, - STM32_I2C_I2C2_IRQ_PRIORITY, - NULL, - (void *)i2cp); - osalDbgAssert(!b, "stream already allocated"); - b = dmaStreamAllocate(i2cp->dmatx, - STM32_I2C_I2C2_IRQ_PRIORITY, - NULL, - (void *)i2cp); - osalDbgAssert(!b, "stream already allocated"); - - i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C2_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY); - i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C2_TX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY); - } -#endif /*STM32_I2C_USE_DMA == TRUE */ - -#if defined(STM32_I2C2_GLOBAL_NUMBER) || defined(__DOXYGEN__) - nvicEnableVector(STM32_I2C2_GLOBAL_NUMBER, STM32_I2C_I2C2_IRQ_PRIORITY); -#elif defined(STM32_I2C2_EVENT_NUMBER) && defined(STM32_I2C2_ERROR_NUMBER) - nvicEnableVector(STM32_I2C2_EVENT_NUMBER, STM32_I2C_I2C2_IRQ_PRIORITY); - nvicEnableVector(STM32_I2C2_ERROR_NUMBER, STM32_I2C_I2C2_IRQ_PRIORITY); -#else -#error "I2C2 interrupt numbers not defined" -#endif - } -#endif /* STM32_I2C_USE_I2C2 */ - -#if STM32_I2C_USE_I2C3 - if (&I2CD3 == i2cp) { - - rccResetI2C3(); - rccEnableI2C3(FALSE); -#if STM32_I2C_USE_DMA == TRUE - { - bool b; - - b = dmaStreamAllocate(i2cp->dmarx, - STM32_I2C_I2C3_IRQ_PRIORITY, - NULL, - (void *)i2cp); - osalDbgAssert(!b, "stream already allocated"); - b = dmaStreamAllocate(i2cp->dmatx, - STM32_I2C_I2C3_IRQ_PRIORITY, - NULL, - (void *)i2cp); - osalDbgAssert(!b, "stream already allocated"); - - i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C3_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_I2C_I2C3_DMA_PRIORITY); - i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C3_TX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_I2C_I2C3_DMA_PRIORITY); - } -#endif /*STM32_I2C_USE_DMA == TRUE */ - -#if defined(STM32_I2C3_GLOBAL_NUMBER) || defined(__DOXYGEN__) - nvicEnableVector(STM32_I2C3_GLOBAL_NUMBER, STM32_I2C_I2C3_IRQ_PRIORITY); -#elif defined(STM32_I2C3_EVENT_NUMBER) && defined(STM32_I2C3_ERROR_NUMBER) - nvicEnableVector(STM32_I2C3_EVENT_NUMBER, STM32_I2C_I2C3_IRQ_PRIORITY); - nvicEnableVector(STM32_I2C3_ERROR_NUMBER, STM32_I2C_I2C3_IRQ_PRIORITY); -#else -#error "I2C3 interrupt numbers not defined" -#endif - } -#endif /* STM32_I2C_USE_I2C3 */ - -#if STM32_I2C_USE_I2C4 - if (&I2CD4 == i2cp) { - - rccResetI2C4(); - rccEnableI2C4(FALSE); -#if STM32_I2C_USE_DMA == TRUE - { - bool b; - - b = dmaStreamAllocate(i2cp->dmarx, - STM32_I2C_I2C4_IRQ_PRIORITY, - NULL, - (void *)i2cp); - osalDbgAssert(!b, "stream already allocated"); - b = dmaStreamAllocate(i2cp->dmatx, - STM32_I2C_I2C4_IRQ_PRIORITY, - NULL, - (void *)i2cp); - osalDbgAssert(!b, "stream already allocated"); - - i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C4_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_I2C_I2C4_DMA_PRIORITY); - i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C4_TX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_I2C_I2C4_DMA_PRIORITY); - } -#endif /*STM32_I2C_USE_DMA == TRUE */ - -#if defined(STM32_I2C4_GLOBAL_NUMBER) || defined(__DOXYGEN__) - nvicEnableVector(STM32_I2C4_GLOBAL_NUMBER, STM32_I2C_I2C4_IRQ_PRIORITY); -#elif defined(STM32_I2C4_EVENT_NUMBER) && defined(STM32_I2C4_ERROR_NUMBER) - nvicEnableVector(STM32_I2C4_EVENT_NUMBER, STM32_I2C_I2C4_IRQ_PRIORITY); - nvicEnableVector(STM32_I2C4_ERROR_NUMBER, STM32_I2C_I2C4_IRQ_PRIORITY); -#else -#error "I2C4 interrupt numbers not defined" -#endif - } -#endif /* STM32_I2C_USE_I2C4 */ - } - -#if STM32_I2C_USE_DMA == TRUE - /* I2C registers pointed by the DMA.*/ - dmaStreamSetPeripheral(i2cp->dmarx, &dp->RXDR); - dmaStreamSetPeripheral(i2cp->dmatx, &dp->TXDR); -#endif - - /* Reset i2c peripheral, the TCIE bit will be handled separately.*/ - dp->CR1 = i2cp->config->cr1 | -#if STM32_I2C_USE_DMA == TRUE - I2C_CR1_TXDMAEN | I2C_CR1_RXDMAEN | /* Enable only if using DMA */ -#endif - I2C_CR1_ERRIE | I2C_CR1_NACKIE; - - /* Setup I2C parameters.*/ - dp->TIMINGR = i2cp->config->timingr; - - /* Ready to go.*/ - dp->CR1 |= I2C_CR1_PE; -} - -/** - * @brief Deactivates the I2C peripheral. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -void i2c_lld_stop(I2CDriver *i2cp) { - - /* If not in stopped state then disables the I2C clock.*/ - if (i2cp->state != I2C_STOP) { - - /* I2C disable.*/ - i2c_lld_abort_operation(i2cp); -#if STM32_I2C_USE_DMA == TRUE - dmaStreamRelease(i2cp->dmatx); - dmaStreamRelease(i2cp->dmarx); -#endif - -#if STM32_I2C_USE_I2C1 - if (&I2CD1 == i2cp) { -#if defined(STM32_I2C1_GLOBAL_NUMBER) || defined(__DOXYGEN__) - nvicDisableVector(STM32_I2C1_GLOBAL_NUMBER); -#elif defined(STM32_I2C1_EVENT_NUMBER) && defined(STM32_I2C1_ERROR_NUMBER) - nvicDisableVector(STM32_I2C1_EVENT_NUMBER); - nvicDisableVector(STM32_I2C1_ERROR_NUMBER); -#else -#error "I2C1 interrupt numbers not defined" -#endif - - rccDisableI2C1(FALSE); - } -#endif - -#if STM32_I2C_USE_I2C2 - if (&I2CD2 == i2cp) { -#if defined(STM32_I2C2_GLOBAL_NUMBER) || defined(__DOXYGEN__) - nvicDisableVector(STM32_I2C2_GLOBAL_NUMBER); -#elif defined(STM32_I2C2_EVENT_NUMBER) && defined(STM32_I2C2_ERROR_NUMBER) - nvicDisableVector(STM32_I2C2_EVENT_NUMBER); - nvicDisableVector(STM32_I2C2_ERROR_NUMBER); -#else -#error "I2C2 interrupt numbers not defined" -#endif - - rccDisableI2C2(FALSE); - } -#endif - -#if STM32_I2C_USE_I2C3 - if (&I2CD3 == i2cp) { -#if defined(STM32_I2C3_GLOBAL_NUMBER) || defined(__DOXYGEN__) - nvicDisableVector(STM32_I2C3_GLOBAL_NUMBER); -#elif defined(STM32_I2C3_EVENT_NUMBER) && defined(STM32_I2C3_ERROR_NUMBER) - nvicDisableVector(STM32_I2C3_EVENT_NUMBER); - nvicDisableVector(STM32_I2C3_ERROR_NUMBER); -#else -#error "I2C3 interrupt numbers not defined" -#endif - - rccDisableI2C3(FALSE); - } -#endif - -#if STM32_I2C_USE_I2C4 - if (&I2CD4 == i2cp) { -#if defined(STM32_I2C4_GLOBAL_NUMBER) || defined(__DOXYGEN__) - nvicDisableVector(STM32_I2C4_GLOBAL_NUMBER); -#elif defined(STM32_I2C4_EVENT_NUMBER) && defined(STM32_I2C4_ERROR_NUMBER) - nvicDisableVector(STM32_I2C4_EVENT_NUMBER); - nvicDisableVector(STM32_I2C4_ERROR_NUMBER); -#else -#error "I2C4 interrupt numbers not defined" -#endif - - rccDisableI2C4(FALSE); - } -#endif - } -} - -/** - * @brief Receives data via the I2C bus as master. - * @details Number of receiving bytes must be more than 1 on STM32F1x. This is - * hardware restriction. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] addr slave device address - * @param[out] rxbuf pointer to the receive buffer - * @param[in] rxbytes number of bytes to be received - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval MSG_OK if the function succeeded. - * @retval MSG_RESET if one or more I2C errors occurred, the errors can - * be retrieved using @p i2cGetErrors(). - * @retval MSG_TIMEOUT if a timeout occurred before operation end. After a - * timeout the driver must be stopped and restarted - * because the bus is in an uncertain state. - * - * @notapi - */ -msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, - uint8_t *rxbuf, size_t rxbytes, - systime_t timeout) { - msg_t msg; - I2C_TypeDef *dp = i2cp->i2c; - systime_t start, end; - - /* Resetting error flags for this transfer.*/ - i2cp->errors = I2C_NO_ERROR; - - /* Releases the lock from high level driver.*/ - osalSysUnlock(); - -#if STM32_I2C_USE_DMA == TRUE - /* RX DMA setup.*/ - dmaStreamSetMode(i2cp->dmarx, i2cp->rxdmamode); - dmaStreamSetMemory0(i2cp->dmarx, rxbuf); - dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes); -#else - i2cp->rxptr = rxbuf; - i2cp->rxbytes = rxbytes; -#endif - - /* Calculating the time window for the timeout on the busy bus condition.*/ - start = osalOsGetSystemTimeX(); - end = start + OSAL_MS2ST(STM32_I2C_BUSY_TIMEOUT); - - /* Waits until BUSY flag is reset or, alternatively, for a timeout - condition.*/ - while (true) { - osalSysLock(); - - /* If the bus is not busy then the operation can continue, note, the - loop is exited in the locked state.*/ - if ((dp->ISR & I2C_ISR_BUSY) == 0) - break; - - /* If the system time went outside the allowed window then a timeout - condition is returned.*/ - if (!osalOsIsTimeWithinX(osalOsGetSystemTimeX(), start, end)) { - return MSG_TIMEOUT; - } - - osalSysUnlock(); - } - - /* Setting up the slave address.*/ - i2c_lld_set_address(i2cp, addr); - - /* Setting up the peripheral.*/ - i2c_lld_setup_rx_transfer(i2cp); - -#if STM32_I2C_USE_DMA == TRUE - /* Enabling RX DMA.*/ - dmaStreamEnable(i2cp->dmarx); - - /* Transfer complete interrupt enabled.*/ - dp->CR1 |= I2C_CR1_TCIE; -#else - - /* Transfer complete and RX interrupts enabled.*/ - dp->CR1 |= I2C_CR1_TCIE | I2C_CR1_RXIE; -#endif - - /* Starts the operation.*/ - dp->CR2 |= I2C_CR2_START; - - /* Waits for the operation completion or a timeout.*/ - msg = osalThreadSuspendTimeoutS(&i2cp->thread, timeout); - - /* In case of a software timeout a STOP is sent as an extreme attempt - to release the bus.*/ - if (msg == MSG_TIMEOUT) { - dp->CR2 |= I2C_CR2_STOP; - } - - return msg; -} - -/** - * @brief Transmits data via the I2C bus as master. - * @details Number of receiving bytes must be 0 or more than 1 on STM32F1x. - * This is hardware restriction. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] addr slave device address - * @param[in] txbuf pointer to the transmit buffer - * @param[in] txbytes number of bytes to be transmitted - * @param[out] rxbuf pointer to the receive buffer - * @param[in] rxbytes number of bytes to be received - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval MSG_OK if the function succeeded. - * @retval MSG_RESET if one or more I2C errors occurred, the errors can - * be retrieved using @p i2cGetErrors(). - * @retval MSG_TIMEOUT if a timeout occurred before operation end. After a - * timeout the driver must be stopped and restarted - * because the bus is in an uncertain state. - * - * @notapi - */ -msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, - const uint8_t *txbuf, size_t txbytes, - uint8_t *rxbuf, size_t rxbytes, - systime_t timeout) { - msg_t msg; - I2C_TypeDef *dp = i2cp->i2c; - systime_t start, end; - - /* Resetting error flags for this transfer.*/ - i2cp->errors = I2C_NO_ERROR; - - /* Releases the lock from high level driver.*/ - osalSysUnlock(); - -#if STM32_I2C_USE_DMA == TRUE - /* TX DMA setup.*/ - dmaStreamSetMode(i2cp->dmatx, i2cp->txdmamode); - dmaStreamSetMemory0(i2cp->dmatx, txbuf); - dmaStreamSetTransactionSize(i2cp->dmatx, txbytes); - - /* RX DMA setup, note, rxbytes can be zero but we write the value anyway.*/ - dmaStreamSetMode(i2cp->dmarx, i2cp->rxdmamode); - dmaStreamSetMemory0(i2cp->dmarx, rxbuf); - dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes); -#else - i2cp->txptr = txbuf; - i2cp->txbytes = txbytes; - i2cp->rxptr = rxbuf; - i2cp->rxbytes = rxbytes; -#endif - - /* Calculating the time window for the timeout on the busy bus condition.*/ - start = osalOsGetSystemTimeX(); - end = start + OSAL_MS2ST(STM32_I2C_BUSY_TIMEOUT); - - /* Waits until BUSY flag is reset or, alternatively, for a timeout - condition.*/ - while (true) { - osalSysLock(); - - /* If the bus is not busy then the operation can continue, note, the - loop is exited in the locked state.*/ - if ((dp->ISR & I2C_ISR_BUSY) == 0) - break; - - /* If the system time went outside the allowed window then a timeout - condition is returned.*/ - if (!osalOsIsTimeWithinX(osalOsGetSystemTimeX(), start, end)) { - return MSG_TIMEOUT; - } - - osalSysUnlock(); - } - - /* Setting up the slave address.*/ - i2c_lld_set_address(i2cp, addr); - - /* Preparing the transfer.*/ - i2c_lld_setup_tx_transfer(i2cp); - -#if STM32_I2C_USE_DMA == TRUE - /* Enabling TX DMA.*/ - dmaStreamEnable(i2cp->dmatx); - - /* Transfer complete interrupt enabled.*/ - dp->CR1 |= I2C_CR1_TCIE; -#else - /* Transfer complete and TX interrupts enabled.*/ - dp->CR1 |= I2C_CR1_TCIE | I2C_CR1_TXIE; -#endif - - /* Starts the operation.*/ - dp->CR2 |= I2C_CR2_START; - - /* Waits for the operation completion or a timeout.*/ - msg = osalThreadSuspendTimeoutS(&i2cp->thread, timeout); - - /* In case of a software timeout a STOP is sent as an extreme attempt - to release the bus.*/ - if (msg == MSG_TIMEOUT) { - dp->CR2 |= I2C_CR2_STOP; - } - - return msg; -} - -#endif /* HAL_USE_I2C */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.h b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.h deleted file mode 100644 index 05b268a6f3..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.h +++ /dev/null @@ -1,502 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Concepts and parts of this file have been contributed by Uladzimir Pylinsky - aka barthess. - */ - -/** - * @file STM32/I2Cv2/i2c_lld.h - * @brief STM32 I2C subsystem low level driver header. - * - * @addtogroup I2C - * @{ - */ - -#ifndef _I2C_LLD_H_ -#define _I2C_LLD_H_ - -#if HAL_USE_I2C || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name TIMINGR register definitions - * @{ - */ -#define STM32_TIMINGR_PRESC_MASK (15U << 28) -#define STM32_TIMINGR_PRESC(n) ((n) << 28) -#define STM32_TIMINGR_SCLDEL_MASK (15U << 20) -#define STM32_TIMINGR_SCLDEL(n) ((n) << 20) -#define STM32_TIMINGR_SDADEL_MASK (15U << 16) -#define STM32_TIMINGR_SDADEL(n) ((n) << 16) -#define STM32_TIMINGR_SCLH_MASK (255U << 8) -#define STM32_TIMINGR_SCLH(n) ((n) << 8) -#define STM32_TIMINGR_SCLL_MASK (255U << 0) -#define STM32_TIMINGR_SCLL(n) ((n) << 0) -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief I2C1 driver enable switch. - * @details If set to @p TRUE the support for I2C1 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_I2C_USE_I2C1) || defined(__DOXYGEN__) -#define STM32_I2C_USE_I2C1 FALSE -#endif - -/** - * @brief I2C2 driver enable switch. - * @details If set to @p TRUE the support for I2C2 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_I2C_USE_I2C2) || defined(__DOXYGEN__) -#define STM32_I2C_USE_I2C2 FALSE -#endif - -/** - * @brief I2C3 driver enable switch. - * @details If set to @p TRUE the support for I2C3 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_I2C_USE_I2C3) || defined(__DOXYGEN__) -#define STM32_I2C_USE_I2C3 FALSE -#endif - -/** - * @brief I2C4 driver enable switch. - * @details If set to @p TRUE the support for I2C4 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_I2C_USE_I2C4) || defined(__DOXYGEN__) -#define STM32_I2C_USE_I2C4 FALSE -#endif - -/** - * @brief I2C timeout on busy condition in milliseconds. - */ -#if !defined(STM32_I2C_BUSY_TIMEOUT) || defined(__DOXYGEN__) -#define STM32_I2C_BUSY_TIMEOUT 50 -#endif - -/** - * @brief I2C1 interrupt priority level setting. - */ -#if !defined(STM32_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2C_I2C1_IRQ_PRIORITY 10 -#endif - -/** - * @brief I2C2 interrupt priority level setting. - */ -#if !defined(STM32_I2C_I2C2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2C_I2C2_IRQ_PRIORITY 10 -#endif - -/** - * @brief I2C3 interrupt priority level setting. - */ -#if !defined(STM32_I2C_I2C3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2C_I2C3_IRQ_PRIORITY 10 -#endif - -/** - * @brief I2C4 interrupt priority level setting. - */ -#if !defined(STM32_I2C_I2C4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2C_I2C4_IRQ_PRIORITY 10 -#endif - -/** - * @brief DMA use switch. - */ -#if !defined(STM32_I2C_USE_DMA) || defined(__DOXYGEN__) -#define STM32_I2C_USE_DMA TRUE -#endif - -/** - * @brief I2C1 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA streams but - * because of the streams ordering the RX stream has always priority - * over the TX stream. - */ -#if !defined(STM32_I2C_I2C1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2C_I2C1_DMA_PRIORITY 1 -#endif - -/** - * @brief I2C2 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA streams but - * because of the streams ordering the RX stream has always priority - * over the TX stream. - */ -#if !defined(STM32_I2C_I2C2_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2C_I2C2_DMA_PRIORITY 1 -#endif - -/** - * @brief I2C3 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA streams but - * because of the streams ordering the RX stream has always priority - * over the TX stream. - */ -#if !defined(STM32_I2C_I2C3_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2C_I2C3_DMA_PRIORITY 1 -#endif - -/** - * @brief I2C4 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA streams but - * because of the streams ordering the RX stream has always priority - * over the TX stream. - */ -#if !defined(STM32_I2C_I2C4_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2C_I2C4_DMA_PRIORITY 1 -#endif - -/** - * @brief I2C DMA error hook. - * @note The default action for DMA errors is a system halt because DMA - * error can only happen because programming errors. - */ -#if !defined(STM32_I2C_DMA_ERROR_HOOK) || defined(__DOXYGEN__) -#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/** @brief error checks */ -#if STM32_I2C_USE_I2C1 && !STM32_HAS_I2C1 -#error "I2C1 not present in the selected device" -#endif - -#if STM32_I2C_USE_I2C2 && !STM32_HAS_I2C2 -#error "I2C2 not present in the selected device" -#endif - -#if STM32_I2C_USE_I2C3 && !STM32_HAS_I2C3 -#error "I2C3 not present in the selected device" -#endif - -#if STM32_I2C_USE_I2C4 && !STM32_HAS_I2C4 -#error "I2C4 not present in the selected device" -#endif - -#if !STM32_I2C_USE_I2C1 && !STM32_I2C_USE_I2C2 && !STM32_I2C_USE_I2C3 && \ - !STM32_I2C_USE_I2C4 -#error "I2C driver activated but no I2C peripheral assigned" -#endif - -#if STM32_I2C_USE_I2C1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2C_I2C1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to I2C1" -#endif - -#if STM32_I2C_USE_I2C2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2C_I2C2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to I2C2" -#endif - -#if STM32_I2C_USE_I2C3 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2C_I2C3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to I2C3" -#endif - -#if STM32_I2C_USE_I2C4 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2C_I2C4_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to I2C4" -#endif - -#if STM32_I2C_USE_DMA == TRUE -#if STM32_I2C_USE_I2C1 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_I2C_I2C1_DMA_PRIORITY) -#error "Invalid DMA priority assigned to I2C1" -#endif - -#if STM32_I2C_USE_I2C2 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_I2C_I2C2_DMA_PRIORITY) -#error "Invalid DMA priority assigned to I2C2" -#endif - -#if STM32_I2C_USE_I2C3 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_I2C_I2C3_DMA_PRIORITY) -#error "Invalid DMA priority assigned to I2C3" -#endif - -#if STM32_I2C_USE_I2C4 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_I2C_I2C4_DMA_PRIORITY) -#error "Invalid DMA priority assigned to I2C4" -#endif - -/* The following checks are only required when there is a DMA able to - reassign streams to different channels.*/ -#if STM32_ADVANCED_DMA -/* Check on the presence of the DMA streams settings in mcuconf.h.*/ -#if STM32_I2C_USE_I2C1 && (!defined(STM32_I2C_I2C1_RX_DMA_STREAM) || \ - !defined(STM32_I2C_I2C1_TX_DMA_STREAM)) -#error "I2C1 DMA streams not defined" -#endif - -#if STM32_I2C_USE_I2C2 && (!defined(STM32_I2C_I2C2_RX_DMA_STREAM) || \ - !defined(STM32_I2C_I2C2_TX_DMA_STREAM)) -#error "I2C2 DMA streams not defined" -#endif - -#if STM32_I2C_USE_I2C3 && (!defined(STM32_I2C_I2C3_RX_DMA_STREAM) || \ - !defined(STM32_I2C_I2C3_TX_DMA_STREAM)) -#error "I2C3 DMA streams not defined" -#endif - -#if STM32_I2C_USE_I2C4 && (!defined(STM32_I2C_I2C4_RX_DMA_STREAM) || \ - !defined(STM32_I2C_I2C4_TX_DMA_STREAM)) -#error "I2C4 DMA streams not defined" -#endif - -/* Check on the validity of the assigned DMA channels.*/ -#if STM32_I2C_USE_I2C1 && \ - !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_RX_DMA_STREAM, \ - STM32_I2C1_RX_DMA_MSK) -#error "invalid DMA stream associated to I2C1 RX" -#endif - -#if STM32_I2C_USE_I2C1 && \ - !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_TX_DMA_STREAM, \ - STM32_I2C1_TX_DMA_MSK) -#error "invalid DMA stream associated to I2C1 TX" -#endif - -#if STM32_I2C_USE_I2C2 && \ - !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C2_RX_DMA_STREAM, \ - STM32_I2C2_RX_DMA_MSK) -#error "invalid DMA stream associated to I2C2 RX" -#endif - -#if STM32_I2C_USE_I2C2 && \ - !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C2_TX_DMA_STREAM, \ - STM32_I2C2_TX_DMA_MSK) -#error "invalid DMA stream associated to I2C2 TX" -#endif - -#if STM32_I2C_USE_I2C3 && \ - !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C3_RX_DMA_STREAM, \ - STM32_I2C3_RX_DMA_MSK) -#error "invalid DMA stream associated to I2C3 RX" -#endif - -#if STM32_I2C_USE_I2C3 && \ - !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C3_TX_DMA_STREAM, \ - STM32_I2C3_TX_DMA_MSK) -#error "invalid DMA stream associated to I2C3 TX" -#endif - -#if STM32_I2C_USE_I2C4 && \ - !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C4_RX_DMA_STREAM, \ - STM32_I2C4_RX_DMA_MSK) -#error "invalid DMA stream associated to I2C4 RX" -#endif - -#if STM32_I2C_USE_I2C4 && \ - !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C4_TX_DMA_STREAM, \ - STM32_I2C4_TX_DMA_MSK) -#error "invalid DMA stream associated to I2C4 TX" -#endif -#endif /* STM32_ADVANCED_DMA */ - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif -#endif /* STM32_I2C_USE_DMA == TRUE */ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type representing an I2C address. - */ -typedef uint16_t i2caddr_t; - -/** - * @brief Type of I2C driver condition flags. - */ -typedef uint32_t i2cflags_t; - -/** - * @brief Type of I2C driver configuration structure. - */ -typedef struct { - /** - * @brief TIMINGR register initialization. - * @note Refer to the STM32 reference manual, the values are affected - * by the system clock settings in mcuconf.h. - */ - uint32_t timingr; - /** - * @brief CR1 register initialization. - * @note Leave to zero unless you know what you are doing. - */ - uint32_t cr1; - /** - * @brief CR2 register initialization. - * @note Only the ADD10 bit can eventually be specified here. - */ - uint32_t cr2; -} I2CConfig; - -/** - * @brief Type of a structure representing an I2C driver. - */ -typedef struct I2CDriver I2CDriver; - -/** - * @brief Structure representing an I2C driver. - */ -struct I2CDriver { - /** - * @brief Driver state. - */ - i2cstate_t state; - /** - * @brief Current configuration data. - */ - const I2CConfig *config; - /** - * @brief Error flags. - */ - i2cflags_t errors; -#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) - mutex_t mutex; -#endif /* I2C_USE_MUTUAL_EXCLUSION */ -#if defined(I2C_DRIVER_EXT_FIELDS) - I2C_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Thread waiting for I/O completion. - */ - thread_reference_t thread; -#if (STM32_I2C_USE_DMA == TRUE) || defined(__DOXYGEN__) - /** - * @brief RX DMA mode bit mask. - */ - uint32_t rxdmamode; - /** - * @brief TX DMA mode bit mask. - */ - uint32_t txdmamode; - /** - * @brief Receive DMA channel. - */ - const stm32_dma_stream_t *dmarx; - /** - * @brief Transmit DMA channel. - */ - const stm32_dma_stream_t *dmatx; -#else /* STM32_I2C_USE_DMA == FALSE */ - /** - * @brief Pointer to the next TX buffer location. - */ - const uint8_t *txptr; - /** - * @brief Number of bytes in TX phase. - */ - size_t txbytes; - /** - * @brief Pointer to the next RX buffer location. - */ - uint8_t *rxptr; - /** - * @brief Number of bytes in RX phase. - */ - size_t rxbytes; -#endif /* STM32_I2C_USE_DMA == FALSE */ - /** - * @brief Pointer to the I2Cx registers block. - */ - I2C_TypeDef *i2c; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Get errors from I2C driver. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -#define i2c_lld_get_errors(i2cp) ((i2cp)->errors) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -#if STM32_I2C_USE_I2C1 -extern I2CDriver I2CD1; -#endif - -#if STM32_I2C_USE_I2C2 -extern I2CDriver I2CD2; -#endif - -#if STM32_I2C_USE_I2C3 -extern I2CDriver I2CD3; -#endif - -#if STM32_I2C_USE_I2C4 -extern I2CDriver I2CD4; -#endif - -#endif /* !defined(__DOXYGEN__) */ - -#ifdef __cplusplus -extern "C" { -#endif - void i2c_lld_init(void); - void i2c_lld_start(I2CDriver *i2cp); - void i2c_lld_stop(I2CDriver *i2cp); - msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, - const uint8_t *txbuf, size_t txbytes, - uint8_t *rxbuf, size_t rxbytes, - systime_t timeout); - msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, - uint8_t *rxbuf, size_t rxbytes, - systime_t timeout); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_I2C */ - -#endif /* _I2C_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/MACv1/mac_lld.c b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/MACv1/mac_lld.c deleted file mode 100644 index 8a8b4855e6..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/MACv1/mac_lld.c +++ /dev/null @@ -1,757 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/mac_lld.c - * @brief STM32 low level MAC driver code. - * - * @addtogroup MAC - * @{ - */ - -#include - -#include "hal.h" - -#if HAL_USE_MAC || defined(__DOXYGEN__) - -#include "mii.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define BUFFER_SIZE ((((STM32_MAC_BUFFERS_SIZE - 1) | 3) + 1) / 4) - -/* Fixing inconsistencies in ST headers.*/ -#if !defined(ETH_MACMIIAR_CR_Div102) && defined(ETH_MACMIIAR_CR_DIV102) -#define ETH_MACMIIAR_CR_Div102 ETH_MACMIIAR_CR_DIV102 -#endif -#if !defined(ETH_MACMIIAR_CR_Div62) && defined(ETH_MACMIIAR_CR_DIV62) -#define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_DIV62 -#endif -#if !defined(ETH_MACMIIAR_CR_Div42) && defined(ETH_MACMIIAR_CR_DIV42) -#define ETH_MACMIIAR_CR_Div42 ETH_MACMIIAR_CR_DIV42 -#endif -#if !defined(ETH_MACMIIAR_CR_Div26) && defined(ETH_MACMIIAR_CR_DIV26) -#define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_DIV26 -#endif -#if !defined(ETH_MACMIIAR_CR_Div16) && defined(ETH_MACMIIAR_CR_DIV16) -#define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_DIV16 -#endif - -/* MII divider optimal value.*/ -#if (STM32_HCLK >= 150000000) -#define MACMIIDR_CR ETH_MACMIIAR_CR_Div102 -#elif (STM32_HCLK >= 100000000) -#define MACMIIDR_CR ETH_MACMIIAR_CR_Div62 -#elif (STM32_HCLK >= 60000000) -#define MACMIIDR_CR ETH_MACMIIAR_CR_Div42 -#elif (STM32_HCLK >= 35000000) -#define MACMIIDR_CR ETH_MACMIIAR_CR_Div26 -#elif (STM32_HCLK >= 20000000) -#define MACMIIDR_CR ETH_MACMIIAR_CR_Div16 -#else -#error "STM32_HCLK below minimum frequency for ETH operations (20MHz)" -#endif - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief Ethernet driver 1. - */ -MACDriver ETHD1; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -static const uint8_t default_mac_address[] = {0xAA, 0x55, 0x13, - 0x37, 0x01, 0x10}; - -static stm32_eth_rx_descriptor_t __eth_rd[STM32_MAC_RECEIVE_BUFFERS]; -static stm32_eth_tx_descriptor_t __eth_td[STM32_MAC_TRANSMIT_BUFFERS]; - -static uint32_t __eth_rb[STM32_MAC_RECEIVE_BUFFERS][BUFFER_SIZE]; -static uint32_t __eth_tb[STM32_MAC_TRANSMIT_BUFFERS][BUFFER_SIZE]; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Writes a PHY register. - * - * @param[in] macp pointer to the @p MACDriver object - * @param[in] reg register number - * @param[in] value new register value - * - * @notapi - */ -void mii_write(MACDriver *macp, uint32_t reg, uint32_t value) { - - ETH->MACMIIDR = value; - ETH->MACMIIAR = macp->phyaddr | (reg << 6) | MACMIIDR_CR | - ETH_MACMIIAR_MW | ETH_MACMIIAR_MB; - while ((ETH->MACMIIAR & ETH_MACMIIAR_MB) != 0) - ; -} - -/** - * @brief Reads a PHY register. - * - * @param[in] macp pointer to the @p MACDriver object - * @param[in] reg register number - * - * @return The PHY register content. - * - * @notapi - */ -uint32_t mii_read(MACDriver *macp, uint32_t reg) { - - ETH->MACMIIAR = macp->phyaddr | (reg << 6) | MACMIIDR_CR | ETH_MACMIIAR_MB; - while ((ETH->MACMIIAR & ETH_MACMIIAR_MB) != 0) - ; - return ETH->MACMIIDR; -} - -#if !defined(BOARD_PHY_ADDRESS) -/** - * @brief PHY address detection. - * - * @param[in] macp pointer to the @p MACDriver object - */ -static void mii_find_phy(MACDriver *macp) { - uint32_t i; - -#if STM32_MAC_PHY_TIMEOUT > 0 - unsigned n = STM32_MAC_PHY_TIMEOUT; - do { -#endif - for (i = 0U; i < 31U; i++) { - macp->phyaddr = i << 11U; - ETH->MACMIIDR = (i << 6U) | MACMIIDR_CR; - if ((mii_read(macp, MII_PHYSID1) == (BOARD_PHY_ID >> 16U)) && - ((mii_read(macp, MII_PHYSID2) & 0xFFF0U) == (BOARD_PHY_ID & 0xFFF0U))) { - return; - } - } -#if STM32_MAC_PHY_TIMEOUT > 0 - n--; - } while (n > 0U); -#endif - /* Wrong or defective board.*/ - osalSysHalt("MAC failure"); -} -#endif - -/** - * @brief MAC address setup. - * - * @param[in] p pointer to a six bytes buffer containing the MAC - * address - */ -static void mac_lld_set_address(const uint8_t *p) { - - /* MAC address configuration, only a single address comparator is used, - hash table not used.*/ - ETH->MACA0HR = ((uint32_t)p[5] << 8) | - ((uint32_t)p[4] << 0); - ETH->MACA0LR = ((uint32_t)p[3] << 24) | - ((uint32_t)p[2] << 16) | - ((uint32_t)p[1] << 8) | - ((uint32_t)p[0] << 0); - ETH->MACA1HR = 0x0000FFFF; - ETH->MACA1LR = 0xFFFFFFFF; - ETH->MACA2HR = 0x0000FFFF; - ETH->MACA2LR = 0xFFFFFFFF; - ETH->MACA3HR = 0x0000FFFF; - ETH->MACA3LR = 0xFFFFFFFF; - ETH->MACHTHR = 0; - ETH->MACHTLR = 0; -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -OSAL_IRQ_HANDLER(STM32_ETH_HANDLER) { - uint32_t dmasr; - - OSAL_IRQ_PROLOGUE(); - - dmasr = ETH->DMASR; - ETH->DMASR = dmasr; /* Clear status bits.*/ - - if (dmasr & ETH_DMASR_RS) { - /* Data Received.*/ - osalSysLockFromISR(); - osalThreadDequeueAllI(ÐD1.rdqueue, MSG_RESET); -#if MAC_USE_EVENTS - osalEventBroadcastFlagsI(ÐD1.rdevent, 0); -#endif - osalSysUnlockFromISR(); - } - - if (dmasr & ETH_DMASR_TS) { - /* Data Transmitted.*/ - osalSysLockFromISR(); - osalThreadDequeueAllI(ÐD1.tdqueue, MSG_RESET); - osalSysUnlockFromISR(); - } - - OSAL_IRQ_EPILOGUE(); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level MAC initialization. - * - * @notapi - */ -void mac_lld_init(void) { - unsigned i; - - macObjectInit(ÐD1); - ETHD1.link_up = false; - - /* Descriptor tables are initialized in chained mode, note that the first - word is not initialized here but in mac_lld_start().*/ - for (i = 0; i < STM32_MAC_RECEIVE_BUFFERS; i++) { - __eth_rd[i].rdes1 = STM32_RDES1_RCH | STM32_MAC_BUFFERS_SIZE; - __eth_rd[i].rdes2 = (uint32_t)__eth_rb[i]; - __eth_rd[i].rdes3 = (uint32_t)&__eth_rd[(i + 1) % STM32_MAC_RECEIVE_BUFFERS]; - } - for (i = 0; i < STM32_MAC_TRANSMIT_BUFFERS; i++) { - __eth_td[i].tdes1 = 0; - __eth_td[i].tdes2 = (uint32_t)__eth_tb[i]; - __eth_td[i].tdes3 = (uint32_t)&__eth_td[(i + 1) % STM32_MAC_TRANSMIT_BUFFERS]; - } - - /* Selection of the RMII or MII mode based on info exported by board.h.*/ -#if defined(STM32F10X_CL) -#if defined(BOARD_PHY_RMII) - AFIO->MAPR |= AFIO_MAPR_MII_RMII_SEL; -#else - AFIO->MAPR &= ~AFIO_MAPR_MII_RMII_SEL; -#endif -#elif defined(STM32F2XX) || defined(STM32F4XX) || defined(STM32F7XX) -#if defined(BOARD_PHY_RMII) - SYSCFG->PMC |= SYSCFG_PMC_MII_RMII_SEL; -#else - SYSCFG->PMC &= ~SYSCFG_PMC_MII_RMII_SEL; -#endif -#else -#error "unsupported STM32 platform for MAC driver" -#endif - - /* Reset of the MAC core.*/ - rccResetETH(); - - /* MAC clocks temporary activation.*/ - rccEnableETH(false); - - /* PHY address setup.*/ -#if defined(BOARD_PHY_ADDRESS) - ETHD1.phyaddr = BOARD_PHY_ADDRESS << 11; -#else - mii_find_phy(ÐD1); -#endif - -#if defined(BOARD_PHY_RESET) - /* PHY board-specific reset procedure.*/ - BOARD_PHY_RESET(); -#else - /* PHY soft reset procedure.*/ - mii_write(ÐD1, MII_BMCR, BMCR_RESET); -#if defined(BOARD_PHY_RESET_DELAY) - osalSysPolledDelayX(BOARD_PHY_RESET_DELAY); -#endif - while (mii_read(ÐD1, MII_BMCR) & BMCR_RESET) - ; -#endif - -#if STM32_MAC_ETH1_CHANGE_PHY_STATE - /* PHY in power down mode until the driver will be started.*/ - mii_write(ÐD1, MII_BMCR, mii_read(ÐD1, MII_BMCR) | BMCR_PDOWN); -#endif - - /* MAC clocks stopped again.*/ - rccDisableETH(false); -} - -/** - * @brief Configures and activates the MAC peripheral. - * - * @param[in] macp pointer to the @p MACDriver object - * - * @notapi - */ -void mac_lld_start(MACDriver *macp) { - unsigned i; - - /* Resets the state of all descriptors.*/ - for (i = 0; i < STM32_MAC_RECEIVE_BUFFERS; i++) - __eth_rd[i].rdes0 = STM32_RDES0_OWN; - macp->rxptr = (stm32_eth_rx_descriptor_t *)__eth_rd; - for (i = 0; i < STM32_MAC_TRANSMIT_BUFFERS; i++) - __eth_td[i].tdes0 = STM32_TDES0_TCH; - macp->txptr = (stm32_eth_tx_descriptor_t *)__eth_td; - - /* MAC clocks activation and commanded reset procedure.*/ - rccEnableETH(false); -#if defined(STM32_MAC_DMABMR_SR) - ETH->DMABMR |= ETH_DMABMR_SR; - while(ETH->DMABMR & ETH_DMABMR_SR) - ; -#endif - - /* ISR vector enabled.*/ - nvicEnableVector(STM32_ETH_NUMBER, STM32_MAC_ETH1_IRQ_PRIORITY); - -#if STM32_MAC_ETH1_CHANGE_PHY_STATE - /* PHY in power up mode.*/ - mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) & ~BMCR_PDOWN); -#endif - - /* MAC configuration.*/ - ETH->MACFFR = 0; - ETH->MACFCR = 0; - ETH->MACVLANTR = 0; - - /* MAC address setup.*/ - if (macp->config->mac_address == NULL) - mac_lld_set_address(default_mac_address); - else - mac_lld_set_address(macp->config->mac_address); - - /* Transmitter and receiver enabled. - Note that the complete setup of the MAC is performed when the link - status is detected.*/ -#if STM32_MAC_IP_CHECKSUM_OFFLOAD - ETH->MACCR = ETH_MACCR_IPCO | ETH_MACCR_RE | ETH_MACCR_TE; -#else - ETH->MACCR = ETH_MACCR_RE | ETH_MACCR_TE; -#endif - - /* DMA configuration: - Descriptor chains pointers.*/ - ETH->DMARDLAR = (uint32_t)__eth_rd; - ETH->DMATDLAR = (uint32_t)__eth_td; - - /* Enabling required interrupt sources.*/ - ETH->DMASR = ETH->DMASR; - ETH->DMAIER = ETH_DMAIER_NISE | ETH_DMAIER_RIE | ETH_DMAIER_TIE; - - /* DMA general settings.*/ - ETH->DMABMR = ETH_DMABMR_AAB | ETH_DMABMR_RDP_1Beat | ETH_DMABMR_PBL_1Beat; - - /* Transmit FIFO flush.*/ - ETH->DMAOMR = ETH_DMAOMR_FTF; - while (ETH->DMAOMR & ETH_DMAOMR_FTF) - ; - - /* DMA final configuration and start.*/ - ETH->DMAOMR = ETH_DMAOMR_DTCEFD | ETH_DMAOMR_RSF | ETH_DMAOMR_TSF | - ETH_DMAOMR_ST | ETH_DMAOMR_SR; -} - -/** - * @brief Deactivates the MAC peripheral. - * - * @param[in] macp pointer to the @p MACDriver object - * - * @notapi - */ -void mac_lld_stop(MACDriver *macp) { - - if (macp->state != MAC_STOP) { -#if STM32_MAC_ETH1_CHANGE_PHY_STATE - /* PHY in power down mode until the driver will be restarted.*/ - mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) | BMCR_PDOWN); -#endif - - /* MAC and DMA stopped.*/ - ETH->MACCR = 0; - ETH->DMAOMR = 0; - ETH->DMAIER = 0; - ETH->DMASR = ETH->DMASR; - - /* MAC clocks stopped.*/ - rccDisableETH(false); - - /* ISR vector disabled.*/ - nvicDisableVector(STM32_ETH_NUMBER); - } -} - -/** - * @brief Returns a transmission descriptor. - * @details One of the available transmission descriptors is locked and - * returned. - * - * @param[in] macp pointer to the @p MACDriver object - * @param[out] tdp pointer to a @p MACTransmitDescriptor structure - * @return The operation status. - * @retval MSG_OK the descriptor has been obtained. - * @retval MSG_TIMEOUT descriptor not available. - * - * @notapi - */ -msg_t mac_lld_get_transmit_descriptor(MACDriver *macp, - MACTransmitDescriptor *tdp) { - stm32_eth_tx_descriptor_t *tdes; - - if (!macp->link_up) - return MSG_TIMEOUT; - - osalSysLock(); - - /* Get Current TX descriptor.*/ - tdes = macp->txptr; - - /* Ensure that descriptor isn't owned by the Ethernet DMA or locked by - another thread.*/ - if (tdes->tdes0 & (STM32_TDES0_OWN | STM32_TDES0_LOCKED)) { - osalSysUnlock(); - return MSG_TIMEOUT; - } - - /* Marks the current descriptor as locked using a reserved bit.*/ - tdes->tdes0 |= STM32_TDES0_LOCKED; - - /* Next TX descriptor to use.*/ - macp->txptr = (stm32_eth_tx_descriptor_t *)tdes->tdes3; - - osalSysUnlock(); - - /* Set the buffer size and configuration.*/ - tdp->offset = 0; - tdp->size = STM32_MAC_BUFFERS_SIZE; - tdp->physdesc = tdes; - - return MSG_OK; -} - -/** - * @brief Releases a transmit descriptor and starts the transmission of the - * enqueued data as a single frame. - * - * @param[in] tdp the pointer to the @p MACTransmitDescriptor structure - * - * @notapi - */ -void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) { - - osalDbgAssert(!(tdp->physdesc->tdes0 & STM32_TDES0_OWN), - "attempt to release descriptor already owned by DMA"); - - osalSysLock(); - - /* Unlocks the descriptor and returns it to the DMA engine.*/ - tdp->physdesc->tdes1 = tdp->offset; - tdp->physdesc->tdes0 = STM32_TDES0_CIC(STM32_MAC_IP_CHECKSUM_OFFLOAD) | - STM32_TDES0_IC | STM32_TDES0_LS | STM32_TDES0_FS | - STM32_TDES0_TCH | STM32_TDES0_OWN; - - /* If the DMA engine is stalled then a restart request is issued.*/ - if ((ETH->DMASR & ETH_DMASR_TPS) == ETH_DMASR_TPS_Suspended) { - ETH->DMASR = ETH_DMASR_TBUS; - ETH->DMATPDR = ETH_DMASR_TBUS; /* Any value is OK.*/ - } - - osalSysUnlock(); -} - -/** - * @brief Returns a receive descriptor. - * - * @param[in] macp pointer to the @p MACDriver object - * @param[out] rdp pointer to a @p MACReceiveDescriptor structure - * @return The operation status. - * @retval MSG_OK the descriptor has been obtained. - * @retval MSG_TIMEOUT descriptor not available. - * - * @notapi - */ -msg_t mac_lld_get_receive_descriptor(MACDriver *macp, - MACReceiveDescriptor *rdp) { - stm32_eth_rx_descriptor_t *rdes; - - osalSysLock(); - - /* Get Current RX descriptor.*/ - rdes = macp->rxptr; - - /* Iterates through received frames until a valid one is found, invalid - frames are discarded.*/ - while (!(rdes->rdes0 & STM32_RDES0_OWN)) { - if (!(rdes->rdes0 & (STM32_RDES0_AFM | STM32_RDES0_ES)) -#if STM32_MAC_IP_CHECKSUM_OFFLOAD - && (rdes->rdes0 & STM32_RDES0_FT) - && !(rdes->rdes0 & (STM32_RDES0_IPHCE | STM32_RDES0_PCE)) -#endif - && (rdes->rdes0 & STM32_RDES0_FS) && (rdes->rdes0 & STM32_RDES0_LS)) { - /* Found a valid one.*/ - rdp->offset = 0; - rdp->size = ((rdes->rdes0 & STM32_RDES0_FL_MASK) >> 16) - 4; - rdp->physdesc = rdes; - macp->rxptr = (stm32_eth_rx_descriptor_t *)rdes->rdes3; - - osalSysUnlock(); - return MSG_OK; - } - /* Invalid frame found, purging.*/ - rdes->rdes0 = STM32_RDES0_OWN; - rdes = (stm32_eth_rx_descriptor_t *)rdes->rdes3; - } - - /* Next descriptor to check.*/ - macp->rxptr = rdes; - - osalSysUnlock(); - return MSG_TIMEOUT; -} - -/** - * @brief Releases a receive descriptor. - * @details The descriptor and its buffer are made available for more incoming - * frames. - * - * @param[in] rdp the pointer to the @p MACReceiveDescriptor structure - * - * @notapi - */ -void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp) { - - osalDbgAssert(!(rdp->physdesc->rdes0 & STM32_RDES0_OWN), - "attempt to release descriptor already owned by DMA"); - - osalSysLock(); - - /* Give buffer back to the Ethernet DMA.*/ - rdp->physdesc->rdes0 = STM32_RDES0_OWN; - - /* If the DMA engine is stalled then a restart request is issued.*/ - if ((ETH->DMASR & ETH_DMASR_RPS) == ETH_DMASR_RPS_Suspended) { - ETH->DMASR = ETH_DMASR_RBUS; - ETH->DMARPDR = ETH_DMASR_RBUS; /* Any value is OK.*/ - } - - osalSysUnlock(); -} - -/** - * @brief Updates and returns the link status. - * - * @param[in] macp pointer to the @p MACDriver object - * @return The link status. - * @retval true if the link is active. - * @retval false if the link is down. - * - * @notapi - */ -bool mac_lld_poll_link_status(MACDriver *macp) { - uint32_t maccr, bmsr, bmcr; - - maccr = ETH->MACCR; - - /* PHY CR and SR registers read.*/ - (void)mii_read(macp, MII_BMSR); - bmsr = mii_read(macp, MII_BMSR); - bmcr = mii_read(macp, MII_BMCR); - - /* Check on auto-negotiation mode.*/ - if (bmcr & BMCR_ANENABLE) { - uint32_t lpa; - - /* Auto-negotiation must be finished without faults and link established.*/ - if ((bmsr & (BMSR_LSTATUS | BMSR_RFAULT | BMSR_ANEGCOMPLETE)) != - (BMSR_LSTATUS | BMSR_ANEGCOMPLETE)) - return macp->link_up = false; - - /* Auto-negotiation enabled, checks the LPA register.*/ - lpa = mii_read(macp, MII_LPA); - - /* Check on link speed.*/ - if (lpa & (LPA_100HALF | LPA_100FULL | LPA_100BASE4)) - maccr |= ETH_MACCR_FES; - else - maccr &= ~ETH_MACCR_FES; - - /* Check on link mode.*/ - if (lpa & (LPA_10FULL | LPA_100FULL)) - maccr |= ETH_MACCR_DM; - else - maccr &= ~ETH_MACCR_DM; - } - else { - /* Link must be established.*/ - if (!(bmsr & BMSR_LSTATUS)) - return macp->link_up = false; - - /* Check on link speed.*/ - if (bmcr & BMCR_SPEED100) - maccr |= ETH_MACCR_FES; - else - maccr &= ~ETH_MACCR_FES; - - /* Check on link mode.*/ - if (bmcr & BMCR_FULLDPLX) - maccr |= ETH_MACCR_DM; - else - maccr &= ~ETH_MACCR_DM; - } - - /* Changes the mode in the MAC.*/ - ETH->MACCR = maccr; - - /* Returns the link status.*/ - return macp->link_up = true; -} - -/** - * @brief Writes to a transmit descriptor's stream. - * - * @param[in] tdp pointer to a @p MACTransmitDescriptor structure - * @param[in] buf pointer to the buffer containing the data to be - * written - * @param[in] size number of bytes to be written - * @return The number of bytes written into the descriptor's - * stream, this value can be less than the amount - * specified in the parameter @p size if the maximum - * frame size is reached. - * - * @notapi - */ -size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp, - uint8_t *buf, - size_t size) { - - osalDbgAssert(!(tdp->physdesc->tdes0 & STM32_TDES0_OWN), - "attempt to write descriptor already owned by DMA"); - - if (size > tdp->size - tdp->offset) - size = tdp->size - tdp->offset; - - if (size > 0) { - memcpy((uint8_t *)(tdp->physdesc->tdes2) + tdp->offset, buf, size); - tdp->offset += size; - } - return size; -} - -/** - * @brief Reads from a receive descriptor's stream. - * - * @param[in] rdp pointer to a @p MACReceiveDescriptor structure - * @param[in] buf pointer to the buffer that will receive the read data - * @param[in] size number of bytes to be read - * @return The number of bytes read from the descriptor's - * stream, this value can be less than the amount - * specified in the parameter @p size if there are - * no more bytes to read. - * - * @notapi - */ -size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp, - uint8_t *buf, - size_t size) { - - osalDbgAssert(!(rdp->physdesc->rdes0 & STM32_RDES0_OWN), - "attempt to read descriptor already owned by DMA"); - - if (size > rdp->size - rdp->offset) - size = rdp->size - rdp->offset; - - if (size > 0) { - memcpy(buf, (uint8_t *)(rdp->physdesc->rdes2) + rdp->offset, size); - rdp->offset += size; - } - return size; -} - -#if MAC_USE_ZERO_COPY || defined(__DOXYGEN__) -/** - * @brief Returns a pointer to the next transmit buffer in the descriptor - * chain. - * @note The API guarantees that enough buffers can be requested to fill - * a whole frame. - * - * @param[in] tdp pointer to a @p MACTransmitDescriptor structure - * @param[in] size size of the requested buffer. Specify the frame size - * on the first call then scale the value down subtracting - * the amount of data already copied into the previous - * buffers. - * @param[out] sizep pointer to variable receiving the buffer size, it is - * zero when the last buffer has already been returned. - * Note that a returned size lower than the amount - * requested means that more buffers must be requested - * in order to fill the frame data entirely. - * @return Pointer to the returned buffer. - * @retval NULL if the buffer chain has been entirely scanned. - * - * @notapi - */ -uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp, - size_t size, - size_t *sizep) { - - if (tdp->offset == 0) { - *sizep = tdp->size; - tdp->offset = size; - return (uint8_t *)tdp->physdesc->tdes2; - } - *sizep = 0; - return NULL; -} - -/** - * @brief Returns a pointer to the next receive buffer in the descriptor - * chain. - * @note The API guarantees that the descriptor chain contains a whole - * frame. - * - * @param[in] rdp pointer to a @p MACReceiveDescriptor structure - * @param[out] sizep pointer to variable receiving the buffer size, it is - * zero when the last buffer has already been returned. - * @return Pointer to the returned buffer. - * @retval NULL if the buffer chain has been entirely scanned. - * - * @notapi - */ -const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp, - size_t *sizep) { - - if (rdp->size > 0) { - *sizep = rdp->size; - rdp->offset = rdp->size; - rdp->size = 0; - return (uint8_t *)rdp->physdesc->rdes2; - } - *sizep = 0; - return NULL; -} -#endif /* MAC_USE_ZERO_COPY */ - -#endif /* HAL_USE_MAC */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/MACv1/mac_lld.h b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/MACv1/mac_lld.h deleted file mode 100644 index 34a8c940ad..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/MACv1/mac_lld.h +++ /dev/null @@ -1,359 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/mac_lld.h - * @brief STM32 low level MAC driver header. - * - * @addtogroup MAC - * @{ - */ - -#ifndef _MAC_LLD_H_ -#define _MAC_LLD_H_ - -#if HAL_USE_MAC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief This implementation supports the zero-copy mode API. - */ -#define MAC_SUPPORTS_ZERO_COPY TRUE - -/** - * @name RDES0 constants - * @{ - */ -#define STM32_RDES0_OWN 0x80000000 -#define STM32_RDES0_AFM 0x40000000 -#define STM32_RDES0_FL_MASK 0x3FFF0000 -#define STM32_RDES0_ES 0x00008000 -#define STM32_RDES0_DESERR 0x00004000 -#define STM32_RDES0_SAF 0x00002000 -#define STM32_RDES0_LE 0x00001000 -#define STM32_RDES0_OE 0x00000800 -#define STM32_RDES0_VLAN 0x00000400 -#define STM32_RDES0_FS 0x00000200 -#define STM32_RDES0_LS 0x00000100 -#define STM32_RDES0_IPHCE 0x00000080 -#define STM32_RDES0_LCO 0x00000040 -#define STM32_RDES0_FT 0x00000020 -#define STM32_RDES0_RWT 0x00000010 -#define STM32_RDES0_RE 0x00000008 -#define STM32_RDES0_DE 0x00000004 -#define STM32_RDES0_CE 0x00000002 -#define STM32_RDES0_PCE 0x00000001 -/** @} */ - -/** - * @name RDES1 constants - * @{ - */ -#define STM32_RDES1_DIC 0x80000000 -#define STM32_RDES1_RBS2_MASK 0x1FFF0000 -#define STM32_RDES1_RER 0x00008000 -#define STM32_RDES1_RCH 0x00004000 -#define STM32_RDES1_RBS1_MASK 0x00001FFF -/** @} */ - -/** - * @name TDES0 constants - * @{ - */ -#define STM32_TDES0_OWN 0x80000000 -#define STM32_TDES0_IC 0x40000000 -#define STM32_TDES0_LS 0x20000000 -#define STM32_TDES0_FS 0x10000000 -#define STM32_TDES0_DC 0x08000000 -#define STM32_TDES0_DP 0x04000000 -#define STM32_TDES0_TTSE 0x02000000 -#define STM32_TDES0_LOCKED 0x01000000 /* NOTE: Pseudo flag. */ -#define STM32_TDES0_CIC_MASK 0x00C00000 -#define STM32_TDES0_CIC(n) ((n) << 22) -#define STM32_TDES0_TER 0x00200000 -#define STM32_TDES0_TCH 0x00100000 -#define STM32_TDES0_TTSS 0x00020000 -#define STM32_TDES0_IHE 0x00010000 -#define STM32_TDES0_ES 0x00008000 -#define STM32_TDES0_JT 0x00004000 -#define STM32_TDES0_FF 0x00002000 -#define STM32_TDES0_IPE 0x00001000 -#define STM32_TDES0_LCA 0x00000800 -#define STM32_TDES0_NC 0x00000400 -#define STM32_TDES0_LCO 0x00000200 -#define STM32_TDES0_EC 0x00000100 -#define STM32_TDES0_VF 0x00000080 -#define STM32_TDES0_CC_MASK 0x00000078 -#define STM32_TDES0_ED 0x00000004 -#define STM32_TDES0_UF 0x00000002 -#define STM32_TDES0_DB 0x00000001 -/** @} */ - -/** - * @name TDES1 constants - * @{ - */ -#define STM32_TDES1_TBS2_MASK 0x1FFF0000 -#define STM32_TDES1_TBS1_MASK 0x00001FFF -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief Number of available transmit buffers. - */ -#if !defined(STM32_MAC_TRANSMIT_BUFFERS) || defined(__DOXYGEN__) -#define STM32_MAC_TRANSMIT_BUFFERS 2 -#endif - -/** - * @brief Number of available receive buffers. - */ -#if !defined(STM32_MAC_RECEIVE_BUFFERS) || defined(__DOXYGEN__) -#define STM32_MAC_RECEIVE_BUFFERS 4 -#endif - -/** - * @brief Maximum supported frame size. - */ -#if !defined(STM32_MAC_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define STM32_MAC_BUFFERS_SIZE 1522 -#endif - -/** - * @brief PHY detection timeout. - * @details Timeout for PHY address detection, the scan for a PHY is performed - * the specified number of times before invoking the failure handler. - * This setting applies only if the PHY address is not explicitly - * set in the board header file using @p BOARD_PHY_ADDRESS. A zero - * value disables the timeout and a single search is performed. - */ -#if !defined(STM32_MAC_PHY_TIMEOUT) || defined(__DOXYGEN__) -#define STM32_MAC_PHY_TIMEOUT 100 -#endif - -/** - * @brief Change the PHY power state inside the driver. - */ -#if !defined(STM32_MAC_ETH1_CHANGE_PHY_STATE) || defined(__DOXYGEN__) -#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE -#endif - -/** - * @brief ETHD1 interrupt priority level setting. - */ -#if !defined(STM32_MAC_ETH1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_MAC_ETH1_IRQ_PRIORITY 13 -#endif - -/** - * @brief IP checksum offload. - * @details The following modes are available: - * - 0 Function disabled. - * - 1 Only IP header checksum calculation and insertion are enabled. - * - 2 IP header checksum and payload checksum calculation and - * insertion are enabled, but pseudo-header checksum is not - * calculated in hardware. - * - 3 IP Header checksum and payload checksum calculation and - * insertion are enabled, and pseudo-header checksum is - * calculated in hardware. - * . - */ -#if !defined(STM32_MAC_IP_CHECKSUM_OFFLOAD) || defined(__DOXYGEN__) -#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of an STM32 Ethernet receive descriptor. - */ -typedef struct { - volatile uint32_t rdes0; - volatile uint32_t rdes1; - volatile uint32_t rdes2; - volatile uint32_t rdes3; -} stm32_eth_rx_descriptor_t; - -/** - * @brief Type of an STM32 Ethernet transmit descriptor. - */ -typedef struct { - volatile uint32_t tdes0; - volatile uint32_t tdes1; - volatile uint32_t tdes2; - volatile uint32_t tdes3; -} stm32_eth_tx_descriptor_t; - -/** - * @brief Driver configuration structure. - */ -typedef struct { - /** - * @brief MAC address. - */ - uint8_t *mac_address; - /* End of the mandatory fields.*/ -} MACConfig; - -/** - * @brief Structure representing a MAC driver. - */ -struct MACDriver { - /** - * @brief Driver state. - */ - macstate_t state; - /** - * @brief Current configuration data. - */ - const MACConfig *config; - /** - * @brief Transmit semaphore. - */ - threads_queue_t tdqueue; - /** - * @brief Receive semaphore. - */ - threads_queue_t rdqueue; -#if MAC_USE_EVENTS || defined(__DOXYGEN__) - /** - * @brief Receive event. - */ - event_source_t rdevent; -#endif - /* End of the mandatory fields.*/ - /** - * @brief Link status flag. - */ - bool link_up; - /** - * @brief PHY address (pre shifted). - */ - uint32_t phyaddr; - /** - * @brief Receive next frame pointer. - */ - stm32_eth_rx_descriptor_t *rxptr; - /** - * @brief Transmit next frame pointer. - */ - stm32_eth_tx_descriptor_t *txptr; -}; - -/** - * @brief Structure representing a transmit descriptor. - */ -typedef struct { - /** - * @brief Current write offset. - */ - size_t offset; - /** - * @brief Available space size. - */ - size_t size; - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the physical descriptor. - */ - stm32_eth_tx_descriptor_t *physdesc; -} MACTransmitDescriptor; - -/** - * @brief Structure representing a receive descriptor. - */ -typedef struct { - /** - * @brief Current read offset. - */ - size_t offset; - /** - * @brief Available data size. - */ - size_t size; - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the physical descriptor. - */ - stm32_eth_rx_descriptor_t *physdesc; -} MACReceiveDescriptor; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -extern MACDriver ETHD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void mii_write(MACDriver *macp, uint32_t reg, uint32_t value); - uint32_t mii_read(MACDriver *macp, uint32_t reg); - void mac_lld_init(void); - void mac_lld_start(MACDriver *macp); - void mac_lld_stop(MACDriver *macp); - msg_t mac_lld_get_transmit_descriptor(MACDriver *macp, - MACTransmitDescriptor *tdp); - void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp); - msg_t mac_lld_get_receive_descriptor(MACDriver *macp, - MACReceiveDescriptor *rdp); - void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp); - bool mac_lld_poll_link_status(MACDriver *macp); - size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp, - uint8_t *buf, - size_t size); - size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp, - uint8_t *buf, - size_t size); -#if MAC_USE_ZERO_COPY - uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp, - size_t size, - size_t *sizep); - const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp, - size_t *sizep); -#endif /* MAC_USE_ZERO_COPY */ -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_MAC */ - -#endif /* _MAC_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/OTGv1/stm32_otg.h b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/OTGv1/stm32_otg.h deleted file mode 100644 index 797e7c222f..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/OTGv1/stm32_otg.h +++ /dev/null @@ -1,933 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file OTGv1/stm32_otg.h - * @brief STM32 OTG registers layout header. - * - * @addtogroup USB - * @{ - */ - -#ifndef _STM32_OTG_H_ -#define _STM32_OTG_H_ - -/** - * @brief Number of the implemented endpoints in OTG_FS. - * @details This value does not include the endpoint 0 that is always present. - */ -#define STM32_OTG1_ENDOPOINTS_NUMBER 3 - -/** - * @brief Number of the implemented endpoints in OTG_HS. - * @details This value does not include the endpoint 0 that is always present. - */ -#define STM32_OTG2_ENDOPOINTS_NUMBER 5 - -/** - * @brief OTG_FS FIFO memory size in words. - */ -#define STM32_OTG1_FIFO_MEM_SIZE 320 - -/** - * @brief OTG_HS FIFO memory size in words. - */ -#define STM32_OTG2_FIFO_MEM_SIZE 1024 - -/** - * @brief Host channel registers group. - */ -typedef struct { - volatile uint32_t HCCHAR; /**< @brief Host channel characteristics - register. */ - volatile uint32_t resvd8; - volatile uint32_t HCINT; /**< @brief Host channel interrupt register.*/ - volatile uint32_t HCINTMSK; /**< @brief Host channel interrupt mask - register. */ - volatile uint32_t HCTSIZ; /**< @brief Host channel transfer size - register. */ - volatile uint32_t resvd14; - volatile uint32_t resvd18; - volatile uint32_t resvd1c; -} stm32_otg_host_chn_t; - -/** - * @brief Device input endpoint registers group. - */ -typedef struct { - volatile uint32_t DIEPCTL; /**< @brief Device control IN endpoint - control register. */ - volatile uint32_t resvd4; - volatile uint32_t DIEPINT; /**< @brief Device IN endpoint interrupt - register. */ - volatile uint32_t resvdC; - volatile uint32_t DIEPTSIZ; /**< @brief Device IN endpoint transfer size - register. */ - volatile uint32_t resvd14; - volatile uint32_t DTXFSTS; /**< @brief Device IN endpoint transmit FIFO - status register. */ - volatile uint32_t resvd1C; -} stm32_otg_in_ep_t; - -/** - * @brief Device output endpoint registers group. - */ -typedef struct { - volatile uint32_t DOEPCTL; /**< @brief Device control OUT endpoint - control register. */ - volatile uint32_t resvd4; - volatile uint32_t DOEPINT; /**< @brief Device OUT endpoint interrupt - register. */ - volatile uint32_t resvdC; - volatile uint32_t DOEPTSIZ; /**< @brief Device OUT endpoint transfer - size register. */ - volatile uint32_t resvd14; - volatile uint32_t resvd18; - volatile uint32_t resvd1C; -} stm32_otg_out_ep_t; - -/** - * @brief USB registers memory map. - */ -typedef struct { - volatile uint32_t GOTGCTL; /**< @brief OTG control and status register.*/ - volatile uint32_t GOTGINT; /**< @brief OTG interrupt register. */ - volatile uint32_t GAHBCFG; /**< @brief AHB configuration register. */ - volatile uint32_t GUSBCFG; /**< @brief USB configuration register. */ - volatile uint32_t GRSTCTL; /**< @brief Reset register size. */ - volatile uint32_t GINTSTS; /**< @brief Interrupt register. */ - volatile uint32_t GINTMSK; /**< @brief Interrupt mask register. */ - volatile uint32_t GRXSTSR; /**< @brief Receive status debug read - register. */ - volatile uint32_t GRXSTSP; /**< @brief Receive status read/pop - register. */ - volatile uint32_t GRXFSIZ; /**< @brief Receive FIFO size register. */ - volatile uint32_t DIEPTXF0; /**< @brief Endpoint 0 transmit FIFO size - register. */ - volatile uint32_t HNPTXSTS; /**< @brief Non-periodic transmit FIFO/queue - status register. */ - volatile uint32_t resvd30; - volatile uint32_t resvd34; - volatile uint32_t GCCFG; /**< @brief General core configuration. */ - volatile uint32_t CID; /**< @brief Core ID register. */ - volatile uint32_t resvd58[48]; - volatile uint32_t HPTXFSIZ; /**< @brief Host periodic transmit FIFO size - register. */ - volatile uint32_t DIEPTXF[15];/**< @brief Device IN endpoint transmit FIFO - size registers. */ - volatile uint32_t resvd140[176]; - volatile uint32_t HCFG; /**< @brief Host configuration register. */ - volatile uint32_t HFIR; /**< @brief Host frame interval register. */ - volatile uint32_t HFNUM; /**< @brief Host frame number/frame time - Remaining register. */ - volatile uint32_t resvd40C; - volatile uint32_t HPTXSTS; /**< @brief Host periodic transmit FIFO/queue - status register. */ - volatile uint32_t HAINT; /**< @brief Host all channels interrupt - register. */ - volatile uint32_t HAINTMSK; /**< @brief Host all channels interrupt mask - register. */ - volatile uint32_t resvd41C[9]; - volatile uint32_t HPRT; /**< @brief Host port control and status - register. */ - volatile uint32_t resvd444[47]; - stm32_otg_host_chn_t hc[16]; /**< @brief Host channels array. */ - volatile uint32_t resvd700[64]; - volatile uint32_t DCFG; /**< @brief Device configuration register. */ - volatile uint32_t DCTL; /**< @brief Device control register. */ - volatile uint32_t DSTS; /**< @brief Device status register. */ - volatile uint32_t resvd80C; - volatile uint32_t DIEPMSK; /**< @brief Device IN endpoint common - interrupt mask register. */ - volatile uint32_t DOEPMSK; /**< @brief Device OUT endpoint common - interrupt mask register. */ - volatile uint32_t DAINT; /**< @brief Device all endpoints interrupt - register. */ - volatile uint32_t DAINTMSK; /**< @brief Device all endpoints interrupt - mask register. */ - volatile uint32_t resvd820; - volatile uint32_t resvd824; - volatile uint32_t DVBUSDIS; /**< @brief Device VBUS discharge time - register. */ - volatile uint32_t DVBUSPULSE; /**< @brief Device VBUS pulsing time - register. */ - volatile uint32_t resvd830; - volatile uint32_t DIEPEMPMSK; /**< @brief Device IN endpoint FIFO empty - interrupt mask register. */ - volatile uint32_t resvd838; - volatile uint32_t resvd83C; - volatile uint32_t resvd840[16]; - volatile uint32_t resvd880[16]; - volatile uint32_t resvd8C0[16]; - stm32_otg_in_ep_t ie[16]; /**< @brief Input endpoints. */ - stm32_otg_out_ep_t oe[16]; /**< @brief Output endpoints. */ - volatile uint32_t resvdD00[64]; - volatile uint32_t PCGCCTL; /**< @brief Power and clock gating control - register. */ - volatile uint32_t resvdE04[127]; - volatile uint32_t FIFO[16][1024]; -} stm32_otg_t; - -/** - * @name GOTGCTL register bit definitions - * @{ - */ -#define GOTGCTL_BSVLD (1U<<19) /**< B-Session Valid. */ -#define GOTGCTL_ASVLD (1U<<18) /**< A-Session Valid. */ -#define GOTGCTL_DBCT (1U<<17) /**< Long/Short debounce time. */ -#define GOTGCTL_CIDSTS (1U<<16) /**< Connector ID status. */ -#define GOTGCTL_EHEN (1U<<12) -#define GOTGCTL_DHNPEN (1U<<11) /**< Device HNP enabled. */ -#define GOTGCTL_HSHNPEN (1U<<10) /**< Host Set HNP enable. */ -#define GOTGCTL_HNPRQ (1U<<9) /**< HNP request. */ -#define GOTGCTL_HNGSCS (1U<<8) /**< Host negotiation success. */ -#define GOTGCTL_BVALOVAL (1U<<7) -#define GOTGCTL_BVALOEN (1U<<6) -#define GOTGCTL_AVALOVAL (1U<<5) -#define GOTGCTL_AVALOEN (1U<<4) -#define GOTGCTL_VBVALOVAL (1U<<3) -#define GOTGCTL_VBVALOEN (1U<<2) -#define GOTGCTL_SRQ (1U<<1) /**< Session request. */ -#define GOTGCTL_SRQSCS (1U<<0) /**< Session request success. */ -/** @} */ - -/** - * @name GOTGINT register bit definitions - * @{ - */ -#define GOTGINT_DBCDNE (1U<<19) /**< Debounce done. */ -#define GOTGINT_ADTOCHG (1U<<18) /**< A-Device timeout change. */ -#define GOTGINT_HNGDET (1U<<17) /**< Host negotiation detected. */ -#define GOTGINT_HNSSCHG (1U<<9) /**< Host negotiation success - status change. */ -#define GOTGINT_SRSSCHG (1U<<8) /**< Session request success - status change. */ -#define GOTGINT_SEDET (1U<<2) /**< Session end detected. */ -/** @} */ - -/** - * @name GAHBCFG register bit definitions - * @{ - */ -#define GAHBCFG_PTXFELVL (1U<<8) /**< Periodic TxFIFO empty - level. */ -#define GAHBCFG_TXFELVL (1U<<7) /**< Non-periodic TxFIFO empty - level. */ -#define GAHBCFG_DMAEN (1U<<5) /**< DMA enable (HS only). */ -#define GAHBCFG_HBSTLEN_MASK (15U<<1) /**< Burst length/type mask (HS - only). */ -#define GAHBCFG_HBSTLEN(n) ((n)<<1) /**< Burst length/type (HS - only). */ -#define GAHBCFG_GINTMSK (1U<<0) /**< Global interrupt mask. */ -/** @} */ - -/** - * @name GUSBCFG register bit definitions - * @{ - */ -#define GUSBCFG_CTXPKT (1U<<31) /**< Corrupt Tx packet. */ -#define GUSBCFG_FDMOD (1U<<30) /**< Force Device Mode. */ -#define GUSBCFG_FHMOD (1U<<29) /**< Force Host Mode. */ -#define GUSBCFG_TRDT_MASK (15U<<10) /**< USB Turnaround time field - mask. */ -#define GUSBCFG_TRDT(n) ((n)<<10) /**< USB Turnaround time field - value. */ -#define GUSBCFG_HNPCAP (1U<<9) /**< HNP-Capable. */ -#define GUSBCFG_SRPCAP (1U<<8) /**< SRP-Capable. */ -#define GUSBCFG_PHYSEL (1U<<6) /**< USB 2.0 High-Speed PHY or - USB 1.1 Full-Speed serial - transceiver Select. */ -#define GUSBCFG_TOCAL_MASK (7U<<0) /**< HS/FS timeout calibration - field mask. */ -#define GUSBCFG_TOCAL(n) ((n)<<0) /**< HS/FS timeout calibration - field value. */ -/** @} */ - -/** - * @name GRSTCTL register bit definitions - * @{ - */ -#define GRSTCTL_AHBIDL (1U<<31) /**< AHB Master Idle. */ -#define GRSTCTL_TXFNUM_MASK (31U<<6) /**< TxFIFO number field mask. */ -#define GRSTCTL_TXFNUM(n) ((n)<<6) /**< TxFIFO number field value. */ -#define GRSTCTL_TXFFLSH (1U<<5) /**< TxFIFO flush. */ -#define GRSTCTL_RXFFLSH (1U<<4) /**< RxFIFO flush. */ -#define GRSTCTL_FCRST (1U<<2) /**< Host frame counter reset. */ -#define GRSTCTL_HSRST (1U<<1) /**< HClk soft reset. */ -#define GRSTCTL_CSRST (1U<<0) /**< Core soft reset. */ -/** @} */ - -/** - * @name GINTSTS register bit definitions - * @{ - */ -#define GINTSTS_WKUPINT (1U<<31) /**< Resume/Remote wakeup - detected interrupt. */ -#define GINTSTS_SRQINT (1U<<30) /**< Session request/New session - detected interrupt. */ -#define GINTSTS_DISCINT (1U<<29) /**< Disconnect detected - interrupt. */ -#define GINTSTS_CIDSCHG (1U<<28) /**< Connector ID status change.*/ -#define GINTSTS_PTXFE (1U<<26) /**< Periodic TxFIFO empty. */ -#define GINTSTS_HCINT (1U<<25) /**< Host channels interrupt. */ -#define GINTSTS_HPRTINT (1U<<24) /**< Host port interrupt. */ -#define GINTSTS_IPXFR (1U<<21) /**< Incomplete periodic - transfer. */ -#define GINTSTS_IISOOXFR (1U<<21) /**< Incomplete isochronous OUT - transfer. */ -#define GINTSTS_IISOIXFR (1U<<20) /**< Incomplete isochronous IN - transfer. */ -#define GINTSTS_OEPINT (1U<<19) /**< OUT endpoints interrupt. */ -#define GINTSTS_IEPINT (1U<<18) /**< IN endpoints interrupt. */ -#define GINTSTS_EOPF (1U<<15) /**< End of periodic frame - interrupt. */ -#define GINTSTS_ISOODRP (1U<<14) /**< Isochronous OUT packet - dropped interrupt. */ -#define GINTSTS_ENUMDNE (1U<<13) /**< Enumeration done. */ -#define GINTSTS_USBRST (1U<<12) /**< USB reset. */ -#define GINTSTS_USBSUSP (1U<<11) /**< USB suspend. */ -#define GINTSTS_ESUSP (1U<<10) /**< Early suspend. */ -#define GINTSTS_GONAKEFF (1U<<7) /**< Global OUT NAK effective. */ -#define GINTSTS_GINAKEFF (1U<<6) /**< Global IN non-periodic NAK - effective. */ -#define GINTSTS_NPTXFE (1U<<5) /**< Non-periodic TxFIFO empty. */ -#define GINTSTS_RXFLVL (1U<<4) /**< RxFIFO non-empty. */ -#define GINTSTS_SOF (1U<<3) /**< Start of frame. */ -#define GINTSTS_OTGINT (1U<<2) /**< OTG interrupt. */ -#define GINTSTS_MMIS (1U<<1) /**< Mode Mismatch interrupt. */ -#define GINTSTS_CMOD (1U<<0) /**< Current mode of operation. */ -/** @} */ - -/** - * @name GINTMSK register bit definitions - * @{ - */ -#define GINTMSK_WKUM (1U<<31) /**< Resume/remote wakeup - detected interrupt mask. */ -#define GINTMSK_SRQM (1U<<30) /**< Session request/New session - detected interrupt mask. */ -#define GINTMSK_DISCM (1U<<29) /**< Disconnect detected - interrupt mask. */ -#define GINTMSK_CIDSCHGM (1U<<28) /**< Connector ID status change - mask. */ -#define GINTMSK_PTXFEM (1U<<26) /**< Periodic TxFIFO empty mask.*/ -#define GINTMSK_HCM (1U<<25) /**< Host channels interrupt - mask. */ -#define GINTMSK_HPRTM (1U<<24) /**< Host port interrupt mask. */ -#define GINTMSK_IPXFRM (1U<<21) /**< Incomplete periodic - transfer mask. */ -#define GINTMSK_IISOOXFRM (1U<<21) /**< Incomplete isochronous OUT - transfer mask. */ -#define GINTMSK_IISOIXFRM (1U<<20) /**< Incomplete isochronous IN - transfer mask. */ -#define GINTMSK_OEPM (1U<<19) /**< OUT endpoints interrupt - mask. */ -#define GINTMSK_IEPM (1U<<18) /**< IN endpoints interrupt - mask. */ -#define GINTMSK_EOPFM (1U<<15) /**< End of periodic frame - interrupt mask. */ -#define GINTMSK_ISOODRPM (1U<<14) /**< Isochronous OUT packet - dropped interrupt mask. */ -#define GINTMSK_ENUMDNEM (1U<<13) /**< Enumeration done mask. */ -#define GINTMSK_USBRSTM (1U<<12) /**< USB reset mask. */ -#define GINTMSK_USBSUSPM (1U<<11) /**< USB suspend mask. */ -#define GINTMSK_ESUSPM (1U<<10) /**< Early suspend mask. */ -#define GINTMSK_GONAKEFFM (1U<<7) /**< Global OUT NAK effective - mask. */ -#define GINTMSK_GINAKEFFM (1U<<6) /**< Global non-periodic IN NAK - effective mask. */ -#define GINTMSK_NPTXFEM (1U<<5) /**< Non-periodic TxFIFO empty - mask. */ -#define GINTMSK_RXFLVLM (1U<<4) /**< Receive FIFO non-empty - mask. */ -#define GINTMSK_SOFM (1U<<3) /**< Start of (micro)frame mask.*/ -#define GINTMSK_OTGM (1U<<2) /**< OTG interrupt mask. */ -#define GINTMSK_MMISM (1U<<1) /**< Mode Mismatch interrupt - mask. */ -/** @} */ - -/** - * @name GRXSTSR register bit definitions - * @{ - */ -#define GRXSTSR_PKTSTS_MASK (15U<<17) /**< Packet status mask. */ -#define GRXSTSR_PKTSTS(n) ((n)<<17) /**< Packet status value. */ -#define GRXSTSR_OUT_GLOBAL_NAK GRXSTSR_PKTSTS(1) -#define GRXSTSR_OUT_DATA GRXSTSR_PKTSTS(2) -#define GRXSTSR_OUT_COMP GRXSTSR_PKTSTS(3) -#define GRXSTSR_SETUP_COMP GRXSTSR_PKTSTS(4) -#define GRXSTSR_SETUP_DATA GRXSTSR_PKTSTS(6) -#define GRXSTSR_DPID_MASK (3U<<15) /**< Data PID mask. */ -#define GRXSTSR_DPID(n) ((n)<<15) /**< Data PID value. */ -#define GRXSTSR_BCNT_MASK (0x7FF<<4) /**< Byte count mask. */ -#define GRXSTSR_BCNT(n) ((n)<<4) /**< Byte count value. */ -#define GRXSTSR_CHNUM_MASK (15U<<0) /**< Channel number mask. */ -#define GRXSTSR_CHNUM(n) ((n)<<0) /**< Channel number value. */ -#define GRXSTSR_EPNUM_MASK (15U<<0) /**< Endpoint number mask. */ -#define GRXSTSR_EPNUM(n) ((n)<<0) /**< Endpoint number value. */ -/** @} */ - -/** - * @name GRXSTSP register bit definitions - * @{ - */ -#define GRXSTSP_PKTSTS_MASK (15<<17) /**< Packet status mask. */ -#define GRXSTSP_PKTSTS(n) ((n)<<17) /**< Packet status value. */ -#define GRXSTSP_OUT_GLOBAL_NAK GRXSTSP_PKTSTS(1) -#define GRXSTSP_OUT_DATA GRXSTSP_PKTSTS(2) -#define GRXSTSP_OUT_COMP GRXSTSP_PKTSTS(3) -#define GRXSTSP_SETUP_COMP GRXSTSP_PKTSTS(4) -#define GRXSTSP_SETUP_DATA GRXSTSP_PKTSTS(6) -#define GRXSTSP_DPID_MASK (3U<<15) /**< Data PID mask. */ -#define GRXSTSP_DPID(n) ((n)<<15) /**< Data PID value. */ -#define GRXSTSP_BCNT_MASK (0x7FF<<4) /**< Byte count mask. */ -#define GRXSTSP_BCNT_OFF 4 /**< Byte count offset. */ -#define GRXSTSP_BCNT(n) ((n)<<4) /**< Byte count value. */ -#define GRXSTSP_CHNUM_MASK (15U<<0) /**< Channel number mask. */ -#define GRXSTSP_CHNUM(n) ((n)<<0) /**< Channel number value. */ -#define GRXSTSP_EPNUM_MASK (15U<<0) /**< Endpoint number mask. */ -#define GRXSTSP_EPNUM_OFF 0 /**< Endpoint number offset. */ -#define GRXSTSP_EPNUM(n) ((n)<<0) /**< Endpoint number value. */ -/** @} */ - -/** - * @name GRXFSIZ register bit definitions - * @{ - */ -#define GRXFSIZ_RXFD_MASK (0xFFFF<<0) /**< RxFIFO depth mask. */ -#define GRXFSIZ_RXFD(n) ((n)<<0) /**< RxFIFO depth value. */ -/** @} */ - -/** - * @name DIEPTXFx register bit definitions - * @{ - */ -#define DIEPTXF_INEPTXFD_MASK (0xFFFFU<<16)/**< IN endpoint TxFIFO depth - mask. */ -#define DIEPTXF_INEPTXFD(n) ((n)<<16) /**< IN endpoint TxFIFO depth - value. */ -#define DIEPTXF_INEPTXSA_MASK (0xFFFF<<0) /**< IN endpoint FIFOx transmit - RAM start address mask. */ -#define DIEPTXF_INEPTXSA(n) ((n)<<0) /**< IN endpoint FIFOx transmit - RAM start address value. */ -/** @} */ - -/** - * @name GCCFG register bit definitions - * @{ - */ -/* Definitions for stepping 1.*/ -#define GCCFG_NOVBUSSENS (1U<<21) /**< VBUS sensing disable. */ -#define GCCFG_SOFOUTEN (1U<<20) /**< SOF output enable. */ -#define GCCFG_VBUSBSEN (1U<<19) /**< Enable the VBUS sensing "B" - device. */ -#define GCCFG_VBUSASEN (1U<<18) /**< Enable the VBUS sensing "A" - device. */ - -/* Definitions for stepping 2.*/ -#define GCCFG_VBDEN (1U<<21) /**< VBUS sensing enable. */ -#define GCCFG_PWRDWN (1U<<16) /**< Power down. */ -/** @} */ - -/** - * @name HPTXFSIZ register bit definitions - * @{ - */ -#define HPTXFSIZ_PTXFD_MASK (0xFFFFU<<16)/**< Host periodic TxFIFO - depth mask. */ -#define HPTXFSIZ_PTXFD(n) ((n)<<16) /**< Host periodic TxFIFO - depth value. */ -#define HPTXFSIZ_PTXSA_MASK (0xFFFFU<<0)/**< Host periodic TxFIFO - Start address mask. */ -#define HPTXFSIZ_PTXSA(n) ((n)<<0) /**< Host periodic TxFIFO - start address value. */ -/** @} */ - -/** - * @name HCFG register bit definitions - * @{ - */ -#define HCFG_FSLSS (1U<<2) /**< FS- and LS-only support. */ -#define HCFG_FSLSPCS_MASK (3U<<0) /**< FS/LS PHY clock select - mask. */ -#define HCFG_FSLSPCS_48 (1U<<0) /**< PHY clock is running at - 48 MHz. */ -#define HCFG_FSLSPCS_6 (2U<<0) /**< PHY clock is running at - 6 MHz. */ -/** @} */ - -/** - * @name HFIR register bit definitions - * @{ - */ -#define HFIR_FRIVL_MASK (0xFFFFU<<0)/**< Frame interval mask. */ -#define HFIR_FRIVL(n) ((n)<<0) /**< Frame interval value. */ -/** @} */ - -/** - * @name HFNUM register bit definitions - * @{ - */ -#define HFNUM_FTREM_MASK (0xFFFFU<<16)/**< Frame time Remaining mask.*/ -#define HFNUM_FTREM(n) ((n)<<16) /**< Frame time Remaining value.*/ -#define HFNUM_FRNUM_MASK (0xFFFFU<<0)/**< Frame number mask. */ -#define HFNUM_FRNUM(n) ((n)<<0) /**< Frame number value. */ -/** @} */ - -/** - * @name HPTXSTS register bit definitions - * @{ - */ -#define HPTXSTS_PTXQTOP_MASK (0xFFU<<24) /**< Top of the periodic - transmit request queue - mask. */ -#define HPTXSTS_PTXQTOP(n) ((n)<<24) /**< Top of the periodic - transmit request queue - value. */ -#define HPTXSTS_PTXQSAV_MASK (0xFF<<16) /**< Periodic transmit request - queue Space Available - mask. */ -#define HPTXSTS_PTXQSAV(n) ((n)<<16) /**< Periodic transmit request - queue Space Available - value. */ -#define HPTXSTS_PTXFSAVL_MASK (0xFFFF<<0) /**< Periodic transmit Data - FIFO Space Available - mask. */ -#define HPTXSTS_PTXFSAVL(n) ((n)<<0) /**< Periodic transmit Data - FIFO Space Available - value. */ -/** @} */ - -/** - * @name HAINT register bit definitions - * @{ - */ -#define HAINT_HAINT_MASK (0xFFFFU<<0)/**< Channel interrupts mask. */ -#define HAINT_HAINT(n) ((n)<<0) /**< Channel interrupts value. */ -/** @} */ - -/** - * @name HAINTMSK register bit definitions - * @{ - */ -#define HAINTMSK_HAINTM_MASK (0xFFFFU<<0)/**< Channel interrupt mask - mask. */ -#define HAINTMSK_HAINTM(n) ((n)<<0) /**< Channel interrupt mask - value. */ -/** @} */ - -/** - * @name HPRT register bit definitions - * @{ - */ -#define HPRT_PSPD_MASK (3U<<17) /**< Port speed mask. */ -#define HPRT_PSPD_FS (1U<<17) /**< Full speed value. */ -#define HPRT_PSPD_LS (2U<<17) /**< Low speed value. */ -#define HPRT_PTCTL_MASK (15<<13) /**< Port Test control mask. */ -#define HPRT_PTCTL(n) ((n)<<13) /**< Port Test control value. */ -#define HPRT_PPWR (1U<<12) /**< Port power. */ -#define HPRT_PLSTS_MASK (3U<<11) /**< Port Line status mask. */ -#define HPRT_PLSTS_DM (1U<<11) /**< Logic level of D-. */ -#define HPRT_PLSTS_DP (1U<<10) /**< Logic level of D+. */ -#define HPRT_PRST (1U<<8) /**< Port reset. */ -#define HPRT_PSUSP (1U<<7) /**< Port suspend. */ -#define HPRT_PRES (1U<<6) /**< Port Resume. */ -#define HPRT_POCCHNG (1U<<5) /**< Port overcurrent change. */ -#define HPRT_POCA (1U<<4) /**< Port overcurrent active. */ -#define HPRT_PENCHNG (1U<<3) /**< Port enable/disable change.*/ -#define HPRT_PENA (1U<<2) /**< Port enable. */ -#define HPRT_PCDET (1U<<1) /**< Port Connect detected. */ -#define HPRT_PCSTS (1U<<0) /**< Port connect status. */ -/** @} */ - -/** - * @name HCCHAR register bit definitions - * @{ - */ -#define HCCHAR_CHENA (1U<<31) /**< Channel enable. */ -#define HCCHAR_CHDIS (1U<<30) /**< Channel Disable. */ -#define HCCHAR_ODDFRM (1U<<29) /**< Odd frame. */ -#define HCCHAR_DAD_MASK (0x7FU<<22) /**< Device Address mask. */ -#define HCCHAR_DAD(n) ((n)<<22) /**< Device Address value. */ -#define HCCHAR_MCNT_MASK (3U<<20) /**< Multicount mask. */ -#define HCCHAR_MCNT(n) ((n)<<20) /**< Multicount value. */ -#define HCCHAR_EPTYP_MASK (3U<<18) /**< Endpoint type mask. */ -#define HCCHAR_EPTYP(n) ((n)<<18) /**< Endpoint type value. */ -#define HCCHAR_EPTYP_CTL (0U<<18) /**< Control endpoint value. */ -#define HCCHAR_EPTYP_ISO (1U<<18) /**< Isochronous endpoint value.*/ -#define HCCHAR_EPTYP_BULK (2U<<18) /**< Bulk endpoint value. */ -#define HCCHAR_EPTYP_INTR (3U<<18) /**< Interrupt endpoint value. */ -#define HCCHAR_LSDEV (1U<<17) /**< Low-Speed device. */ -#define HCCHAR_EPDIR (1U<<15) /**< Endpoint direction. */ -#define HCCHAR_EPNUM_MASK (15U<<11) /**< Endpoint number mask. */ -#define HCCHAR_EPNUM(n) ((n)<<11) /**< Endpoint number value. */ -#define HCCHAR_MPS_MASK (0x7FFU<<0) /**< Maximum packet size mask. */ -#define HCCHAR_MPS(n) ((n)<<0) /**< Maximum packet size value. */ -/** @} */ - -/** - * @name HCINT register bit definitions - * @{ - */ -#define HCINT_DTERR (1U<<10) /**< Data toggle error. */ -#define HCINT_FRMOR (1U<<9) /**< Frame overrun. */ -#define HCINT_BBERR (1U<<8) /**< Babble error. */ -#define HCINT_TRERR (1U<<7) /**< Transaction Error. */ -#define HCINT_ACK (1U<<5) /**< ACK response - received/transmitted - interrupt. */ -#define HCINT_NAK (1U<<4) /**< NAK response received - interrupt. */ -#define HCINT_STALL (1U<<3) /**< STALL response received - interrupt. */ -#define HCINT_AHBERR (1U<<2) /**< AHB error interrupt. */ -#define HCINT_CHH (1U<<1) /**< Channel halted. */ -#define HCINT_XFRC (1U<<0) /**< Transfer completed. */ -/** @} */ - -/** - * @name HCINTMSK register bit definitions - * @{ - */ -#define HCINTMSK_DTERRM (1U<<10) /**< Data toggle error mask. */ -#define HCINTMSK_FRMORM (1U<<9) /**< Frame overrun mask. */ -#define HCINTMSK_BBERRM (1U<<8) /**< Babble error mask. */ -#define HCINTMSK_TRERRM (1U<<7) /**< Transaction error mask. */ -#define HCINTMSK_NYET (1U<<6) /**< NYET response received - interrupt mask. */ -#define HCINTMSK_ACKM (1U<<5) /**< ACK Response - received/transmitted - interrupt mask. */ -#define HCINTMSK_NAKM (1U<<4) /**< NAK response received - interrupt mask. */ -#define HCINTMSK_STALLM (1U<<3) /**< STALL response received - interrupt mask. */ -#define HCINTMSK_AHBERRM (1U<<2) /**< AHB error interrupt mask. */ -#define HCINTMSK_CHHM (1U<<1) /**< Channel halted mask. */ -#define HCINTMSK_XFRCM (1U<<0) /**< Transfer completed mask. */ -/** @} */ - -/** - * @name HCTSIZ register bit definitions - * @{ - */ -#define HCTSIZ_DPID_MASK (3U<<29) /**< PID mask. */ -#define HCTSIZ_DPID_DATA0 (0U<<29) /**< DATA0. */ -#define HCTSIZ_DPID_DATA2 (1U<<29) /**< DATA2. */ -#define HCTSIZ_DPID_DATA1 (2U<<29) /**< DATA1. */ -#define HCTSIZ_DPID_MDATA (3U<<29) /**< MDATA. */ -#define HCTSIZ_DPID_SETUP (3U<<29) /**< SETUP. */ -#define HCTSIZ_PKTCNT_MASK (0x3FFU<<19)/**< Packet count mask. */ -#define HCTSIZ_PKTCNT(n) ((n)<<19) /**< Packet count value. */ -#define HCTSIZ_XFRSIZ_MASK (0x7FFFF<<0)/**< Transfer size mask. */ -#define HCTSIZ_XFRSIZ(n) ((n)<<0) /**< Transfer size value. */ -/** @} */ - -/** - * @name DCFG register bit definitions - * @{ - */ -#define DCFG_PFIVL_MASK (3U<<11) /**< Periodic frame interval - mask. */ -#define DCFG_PFIVL(n) ((n)<<11) /**< Periodic frame interval - value. */ -#define DCFG_DAD_MASK (0x7FU<<4) /**< Device address mask. */ -#define DCFG_DAD(n) ((n)<<4) /**< Device address value. */ -#define DCFG_NZLSOHSK (1U<<2) /**< Non-Zero-Length status - OUT handshake. */ -#define DCFG_DSPD_MASK (3U<<0) /**< Device speed mask. */ -#define DCFG_DSPD_HS (0U<<0) /**< High speed (USB 2.0). */ -#define DCFG_DSPD_HS_FS (1U<<0) /**< High speed (USB 2.0) in FS - mode. */ -#define DCFG_DSPD_FS11 (3U<<0) /**< Full speed (USB 1.1 - transceiver clock is 48 - MHz). */ -/** @} */ - -/** - * @name DCTL register bit definitions - * @{ - */ -#define DCTL_POPRGDNE (1U<<11) /**< Power-on programming done. */ -#define DCTL_CGONAK (1U<<10) /**< Clear global OUT NAK. */ -#define DCTL_SGONAK (1U<<9) /**< Set global OUT NAK. */ -#define DCTL_CGINAK (1U<<8) /**< Clear global non-periodic - IN NAK. */ -#define DCTL_SGINAK (1U<<7) /**< Set global non-periodic - IN NAK. */ -#define DCTL_TCTL_MASK (7U<<4) /**< Test control mask. */ -#define DCTL_TCTL(n) ((n)<<4 /**< Test control value. */ -#define DCTL_GONSTS (1U<<3) /**< Global OUT NAK status. */ -#define DCTL_GINSTS (1U<<2) /**< Global non-periodic IN - NAK status. */ -#define DCTL_SDIS (1U<<1) /**< Soft disconnect. */ -#define DCTL_RWUSIG (1U<<0) /**< Remote wakeup signaling. */ -/** @} */ - -/** - * @name DSTS register bit definitions - * @{ - */ -#define DSTS_FNSOF_MASK (0x3FFU<<8) /**< Frame number of the received - SOF mask. */ -#define DSTS_FNSOF(n) ((n)<<8) /**< Frame number of the received - SOF value. */ -#define DSTS_FNSOF_ODD (1U<<8) /**< Frame parity of the received - SOF value. */ -#define DSTS_EERR (1U<<3) /**< Erratic error. */ -#define DSTS_ENUMSPD_MASK (3U<<1) /**< Enumerated speed mask. */ -#define DSTS_ENUMSPD_FS_48 (3U<<1) /**< Full speed (PHY clock is - running at 48 MHz). */ -#define DSTS_ENUMSPD_HS_480 (0U<<1) /**< High speed. */ -#define DSTS_SUSPSTS (1U<<0) /**< Suspend status. */ -/** @} */ - -/** - * @name DIEPMSK register bit definitions - * @{ - */ -#define DIEPMSK_TXFEM (1U<<6) /**< Transmit FIFO empty mask. */ -#define DIEPMSK_INEPNEM (1U<<6) /**< IN endpoint NAK effective - mask. */ -#define DIEPMSK_ITTXFEMSK (1U<<4) /**< IN token received when - TxFIFO empty mask. */ -#define DIEPMSK_TOCM (1U<<3) /**< Timeout condition mask. */ -#define DIEPMSK_EPDM (1U<<1) /**< Endpoint disabled - interrupt mask. */ -#define DIEPMSK_XFRCM (1U<<0) /**< Transfer completed - interrupt mask. */ -/** @} */ - -/** - * @name DOEPMSK register bit definitions - * @{ - */ -#define DOEPMSK_OTEPDM (1U<<4) /**< OUT token received when - endpoint disabled mask. */ -#define DOEPMSK_STUPM (1U<<3) /**< SETUP phase done mask. */ -#define DOEPMSK_EPDM (1U<<1) /**< Endpoint disabled - interrupt mask. */ -#define DOEPMSK_XFRCM (1U<<0) /**< Transfer completed - interrupt mask. */ -/** @} */ - -/** - * @name DAINT register bit definitions - * @{ - */ -#define DAINT_OEPINT_MASK (0xFFFFU<<16)/**< OUT endpoint interrupt - bits mask. */ -#define DAINT_OEPINT(n) ((n)<<16) /**< OUT endpoint interrupt - bits value. */ -#define DAINT_IEPINT_MASK (0xFFFFU<<0)/**< IN endpoint interrupt - bits mask. */ -#define DAINT_IEPINT(n) ((n)<<0) /**< IN endpoint interrupt - bits value. */ -/** @} */ - -/** - * @name DAINTMSK register bit definitions - * @{ - */ -#define DAINTMSK_OEPM_MASK (0xFFFFU<<16)/**< OUT EP interrupt mask - bits mask. */ -#define DAINTMSK_OEPM(n) (1U<<(16+(n)))/**< OUT EP interrupt mask - bits value. */ -#define DAINTMSK_IEPM_MASK (0xFFFFU<<0)/**< IN EP interrupt mask - bits mask. */ -#define DAINTMSK_IEPM(n) (1U<<(n)) /**< IN EP interrupt mask - bits value. */ -/** @} */ - -/** - * @name DVBUSDIS register bit definitions - * @{ - */ -#define DVBUSDIS_VBUSDT_MASK (0xFFFFU<<0)/**< Device VBUS discharge - time mask. */ -#define DVBUSDIS_VBUSDT(n) ((n)<<0) /**< Device VBUS discharge - time value. */ -/** @} */ - -/** - * @name DVBUSPULSE register bit definitions - * @{ - */ -#define DVBUSPULSE_DVBUSP_MASK (0xFFFU<<0) /**< Device VBUSpulsing time - mask. */ -#define DVBUSPULSE_DVBUSP(n) ((n)<<0) /**< Device VBUS pulsing time - value. */ -/** @} */ - -/** - * @name DIEPEMPMSK register bit definitions - * @{ - */ -#define DIEPEMPMSK_INEPTXFEM(n) (1U<<(n)) /**< IN EP Tx FIFO empty - interrupt mask bit. */ -/** @} */ - -/** - * @name DIEPCTL register bit definitions - * @{ - */ -#define DIEPCTL_EPENA (1U<<31) /**< Endpoint enable. */ -#define DIEPCTL_EPDIS (1U<<30) /**< Endpoint disable. */ -#define DIEPCTL_SD1PID (1U<<29) /**< Set DATA1 PID. */ -#define DIEPCTL_SODDFRM (1U<<29) /**< Set odd frame. */ -#define DIEPCTL_SD0PID (1U<<28) /**< Set DATA0 PID. */ -#define DIEPCTL_SEVNFRM (1U<<28) /**< Set even frame. */ -#define DIEPCTL_SNAK (1U<<27) /**< Set NAK. */ -#define DIEPCTL_CNAK (1U<<26) /**< Clear NAK. */ -#define DIEPCTL_TXFNUM_MASK (15U<<22) /**< TxFIFO number mask. */ -#define DIEPCTL_TXFNUM(n) ((n)<<22) /**< TxFIFO number value. */ -#define DIEPCTL_STALL (1U<<21) /**< STALL handshake. */ -#define DIEPCTL_SNPM (1U<<20) /**< Snoop mode. */ -#define DIEPCTL_EPTYP_MASK (3<<18) /**< Endpoint type mask. */ -#define DIEPCTL_EPTYP_CTRL (0U<<18) /**< Control. */ -#define DIEPCTL_EPTYP_ISO (1U<<18) /**< Isochronous. */ -#define DIEPCTL_EPTYP_BULK (2U<<18) /**< Bulk. */ -#define DIEPCTL_EPTYP_INTR (3U<<18) /**< Interrupt. */ -#define DIEPCTL_NAKSTS (1U<<17) /**< NAK status. */ -#define DIEPCTL_EONUM (1U<<16) /**< Even/odd frame. */ -#define DIEPCTL_DPID (1U<<16) /**< Endpoint data PID. */ -#define DIEPCTL_USBAEP (1U<<15) /**< USB active endpoint. */ -#define DIEPCTL_MPSIZ_MASK (0x3FFU<<0) /**< Maximum Packet size mask. */ -#define DIEPCTL_MPSIZ(n) ((n)<<0) /**< Maximum Packet size value. */ -/** @} */ - -/** - * @name DIEPINT register bit definitions - * @{ - */ -#define DIEPINT_TXFE (1U<<7) /**< Transmit FIFO empty. */ -#define DIEPINT_INEPNE (1U<<6) /**< IN endpoint NAK effective. */ -#define DIEPINT_ITTXFE (1U<<4) /**< IN Token received when - TxFIFO is empty. */ -#define DIEPINT_TOC (1U<<3) /**< Timeout condition. */ -#define DIEPINT_EPDISD (1U<<1) /**< Endpoint disabled - interrupt. */ -#define DIEPINT_XFRC (1U<<0) /**< Transfer completed. */ -/** @} */ - -/** - * @name DIEPTSIZ register bit definitions - * @{ - */ -#define DIEPTSIZ_MCNT_MASK (3U<<29) /**< Multi count mask. */ -#define DIEPTSIZ_MCNT(n) ((n)<<29) /**< Multi count value. */ -#define DIEPTSIZ_PKTCNT_MASK (0x3FF<<19) /**< Packet count mask. */ -#define DIEPTSIZ_PKTCNT(n) ((n)<<19) /**< Packet count value. */ -#define DIEPTSIZ_XFRSIZ_MASK (0x7FFFFU<<0)/**< Transfer size mask. */ -#define DIEPTSIZ_XFRSIZ(n) ((n)<<0) /**< Transfer size value. */ -/** @} */ - -/** - * @name DTXFSTS register bit definitions. - * @{ - */ -#define DTXFSTS_INEPTFSAV_MASK (0xFFFF<<0) /**< IN endpoint TxFIFO space - available. */ -/** @} */ - -/** - * @name DOEPCTL register bit definitions. - * @{ - */ -#define DOEPCTL_EPENA (1U<<31) /**< Endpoint enable. */ -#define DOEPCTL_EPDIS (1U<<30) /**< Endpoint disable. */ -#define DOEPCTL_SD1PID (1U<<29) /**< Set DATA1 PID. */ -#define DOEPCTL_SODDFRM (1U<<29) /**< Set odd frame. */ -#define DOEPCTL_SD0PID (1U<<28) /**< Set DATA0 PID. */ -#define DOEPCTL_SEVNFRM (1U<<28) /**< Set even frame. */ -#define DOEPCTL_SNAK (1U<<27) /**< Set NAK. */ -#define DOEPCTL_CNAK (1U<<26) /**< Clear NAK. */ -#define DOEPCTL_STALL (1U<<21) /**< STALL handshake. */ -#define DOEPCTL_SNPM (1U<<20) /**< Snoop mode. */ -#define DOEPCTL_EPTYP_MASK (3U<<18) /**< Endpoint type mask. */ -#define DOEPCTL_EPTYP_CTRL (0U<<18) /**< Control. */ -#define DOEPCTL_EPTYP_ISO (1U<<18) /**< Isochronous. */ -#define DOEPCTL_EPTYP_BULK (2U<<18) /**< Bulk. */ -#define DOEPCTL_EPTYP_INTR (3U<<18) /**< Interrupt. */ -#define DOEPCTL_NAKSTS (1U<<17) /**< NAK status. */ -#define DOEPCTL_EONUM (1U<<16) /**< Even/odd frame. */ -#define DOEPCTL_DPID (1U<<16) /**< Endpoint data PID. */ -#define DOEPCTL_USBAEP (1U<<15) /**< USB active endpoint. */ -#define DOEPCTL_MPSIZ_MASK (0x3FFU<<0) /**< Maximum Packet size mask. */ -#define DOEPCTL_MPSIZ(n) ((n)<<0) /**< Maximum Packet size value. */ -/** @} */ - -/** - * @name DOEPINT register bit definitions - * @{ - */ -#define DOEPINT_B2BSTUP (1U<<6) /**< Back-to-back SETUP packets - received. */ -#define DOEPINT_OTEPDIS (1U<<4) /**< OUT token received when - endpoint disabled. */ -#define DOEPINT_STUP (1U<<3) /**< SETUP phase done. */ -#define DOEPINT_EPDISD (1U<<1) /**< Endpoint disabled - interrupt. */ -#define DOEPINT_XFRC (1U<<0) /**< Transfer completed - interrupt. */ -/** @} */ - -/** - * @name DOEPTSIZ register bit definitions - * @{ - */ -#define DOEPTSIZ_RXDPID_MASK (3U<<29) /**< Received data PID mask. */ -#define DOEPTSIZ_RXDPID(n) ((n)<<29) /**< Received data PID value. */ -#define DOEPTSIZ_STUPCNT_MASK (3U<<29) /**< SETUP packet count mask. */ -#define DOEPTSIZ_STUPCNT(n) ((n)<<29) /**< SETUP packet count value. */ -#define DOEPTSIZ_PKTCNT_MASK (0x3FFU<<19)/**< Packet count mask. */ -#define DOEPTSIZ_PKTCNT(n) ((n)<<19) /**< Packet count value. */ -#define DOEPTSIZ_XFRSIZ_MASK (0x7FFFFU<<0)/**< Transfer size mask. */ -#define DOEPTSIZ_XFRSIZ(n) ((n)<<0) /**< Transfer size value. */ -/** @} */ - -/** - * @name PCGCCTL register bit definitions - * @{ - */ -#define PCGCCTL_PHYSUSP (1U<<4) /**< PHY Suspended. */ -#define PCGCCTL_GATEHCLK (1U<<1) /**< Gate HCLK. */ -#define PCGCCTL_STPPCLK (1U<<0) /**< Stop PCLK. */ -/** @} */ - -/** - * @brief OTG_FS registers block memory address. - */ -#define OTG_FS_ADDR 0x50000000 - -/** - * @brief OTG_HS registers block memory address. - */ -#define OTG_HS_ADDR 0x40040000 - -/** - * @brief Accesses to the OTG_FS registers block. - */ -#define OTG_FS ((stm32_otg_t *)OTG_FS_ADDR) - -/** - * @brief Accesses to the OTG_HS registers block. - */ -#define OTG_HS ((stm32_otg_t *)OTG_HS_ADDR) - -#endif /* _STM32_OTG_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/OTGv1/usb_lld.c b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/OTGv1/usb_lld.c deleted file mode 100644 index 6ebeed28e8..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/OTGv1/usb_lld.c +++ /dev/null @@ -1,1356 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/OTGv1/usb_lld.c - * @brief STM32 USB subsystem low level driver source. - * - * @addtogroup USB - * @{ - */ - -#include - -#include "hal.h" - -#if HAL_USE_USB || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define TRDT_VALUE_FS 5 -#define TRDT_VALUE_HS 9 - -#define EP0_MAX_INSIZE 64 -#define EP0_MAX_OUTSIZE 64 - -#if STM32_OTG_STEPPING == 1 -#if defined(BOARD_OTG_NOVBUSSENS) -#define GCCFG_INIT_VALUE (GCCFG_NOVBUSSENS | GCCFG_VBUSASEN | \ - GCCFG_VBUSBSEN | GCCFG_PWRDWN) -#else -#define GCCFG_INIT_VALUE (GCCFG_VBUSASEN | GCCFG_VBUSBSEN | \ - GCCFG_PWRDWN) -#endif - -#elif STM32_OTG_STEPPING == 2 -#if defined(BOARD_OTG_NOVBUSSENS) -#define GCCFG_INIT_VALUE GCCFG_PWRDWN -#else -#define GCCFG_INIT_VALUE (GCCFG_VBDEN | GCCFG_PWRDWN) -#endif - -#endif - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief OTG_FS driver identifier.*/ -#if STM32_USB_USE_OTG1 || defined(__DOXYGEN__) -USBDriver USBD1; -#endif - -/** @brief OTG_HS driver identifier.*/ -#if STM32_USB_USE_OTG2 || defined(__DOXYGEN__) -USBDriver USBD2; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief EP0 state. - * @note It is an union because IN and OUT endpoints are never used at the - * same time for EP0. - */ -static union { - /** - * @brief IN EP0 state. - */ - USBInEndpointState in; - /** - * @brief OUT EP0 state. - */ - USBOutEndpointState out; -} ep0_state; - -/** - * @brief Buffer for the EP0 setup packets. - */ -static uint8_t ep0setup_buffer[8]; - -/** - * @brief EP0 initialization structure. - */ -static const USBEndpointConfig ep0config = { - USB_EP_MODE_TYPE_CTRL, - _usb_ep0setup, - _usb_ep0in, - _usb_ep0out, - 0x40, - 0x40, - &ep0_state.in, - &ep0_state.out, - 1, - ep0setup_buffer -}; - -#if STM32_USB_USE_OTG1 -static const stm32_otg_params_t fsparams = { - STM32_USB_OTG1_RX_FIFO_SIZE / 4, - STM32_OTG1_FIFO_MEM_SIZE, - STM32_OTG1_ENDOPOINTS_NUMBER -}; -#endif - -#if STM32_USB_USE_OTG2 -static const stm32_otg_params_t hsparams = { - STM32_USB_OTG2_RX_FIFO_SIZE / 4, - STM32_OTG2_FIFO_MEM_SIZE, - STM32_OTG2_ENDOPOINTS_NUMBER -}; -#endif - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void otg_core_reset(USBDriver *usbp) { - stm32_otg_t *otgp = usbp->otg; - - osalSysPolledDelayX(32); - - /* Core reset and delay of at least 3 PHY cycles.*/ - otgp->GRSTCTL = GRSTCTL_CSRST; - while ((otgp->GRSTCTL & GRSTCTL_CSRST) != 0) - ; - - osalSysPolledDelayX(18); - - /* Wait AHB idle condition.*/ - while ((otgp->GRSTCTL & GRSTCTL_AHBIDL) == 0) - ; -} - -static void otg_disable_ep(USBDriver *usbp) { - stm32_otg_t *otgp = usbp->otg; - unsigned i; - - for (i = 0; i <= usbp->otgparams->num_endpoints; i++) { - otgp->ie[i].DIEPCTL = 0; - otgp->ie[i].DIEPTSIZ = 0; - otgp->ie[i].DIEPINT = 0xFFFFFFFF; - - otgp->oe[i].DOEPCTL = 0; - otgp->oe[i].DOEPTSIZ = 0; - otgp->oe[i].DOEPINT = 0xFFFFFFFF; - } - otgp->DAINTMSK = DAINTMSK_OEPM(0) | DAINTMSK_IEPM(0); -} - -static void otg_rxfifo_flush(USBDriver *usbp) { - stm32_otg_t *otgp = usbp->otg; - - otgp->GRSTCTL = GRSTCTL_RXFFLSH; - while ((otgp->GRSTCTL & GRSTCTL_RXFFLSH) != 0) - ; - /* Wait for 3 PHY Clocks.*/ - osalSysPolledDelayX(18); -} - -static void otg_txfifo_flush(USBDriver *usbp, uint32_t fifo) { - stm32_otg_t *otgp = usbp->otg; - - otgp->GRSTCTL = GRSTCTL_TXFNUM(fifo) | GRSTCTL_TXFFLSH; - while ((otgp->GRSTCTL & GRSTCTL_TXFFLSH) != 0) - ; - /* Wait for 3 PHY Clocks.*/ - osalSysPolledDelayX(18); -} - -/** - * @brief Resets the FIFO RAM memory allocator. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -static void otg_ram_reset(USBDriver *usbp) { - - usbp->pmnext = usbp->otgparams->rx_fifo_size; -} - -/** - * @brief Allocates a block from the FIFO RAM memory. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] size size of the packet buffer to allocate in words - * - * @notapi - */ -static uint32_t otg_ram_alloc(USBDriver *usbp, size_t size) { - uint32_t next; - - next = usbp->pmnext; - usbp->pmnext += size; - osalDbgAssert(usbp->pmnext <= usbp->otgparams->otg_ram_size, - "OTG FIFO memory overflow"); - return next; -} - -/** - * @brief Writes to a TX FIFO. - * - * @param[in] fifop pointer to the FIFO register - * @param[in] buf buffer where to copy the endpoint data - * @param[in] n maximum number of bytes to copy - * - * @notapi - */ -static void otg_fifo_write_from_buffer(volatile uint32_t *fifop, - const uint8_t *buf, - size_t n) { - - osalDbgAssert(n > 0, "is zero"); - - while (true) { - *fifop = *((uint32_t *)buf); - if (n <= 4) { - break; - } - n -= 4; - buf += 4; - } -} - -/** - * @brief Reads a packet from the RXFIFO. - * - * @param[in] fifop pointer to the FIFO register - * @param[out] buf buffer where to copy the endpoint data - * @param[in] n number of bytes to pull from the FIFO - * @param[in] max number of bytes to copy into the buffer - * - * @notapi - */ -static void otg_fifo_read_to_buffer(volatile uint32_t *fifop, - uint8_t *buf, - size_t n, - size_t max) { - uint32_t w = 0; - size_t i = 0; - - while (i < n) { - if ((i & 3) == 0){ - w = *fifop; - } - if (i < max) { - *buf++ = (uint8_t)w; - w >>= 8; - } - i++; - } -} - -/** - * @brief Incoming packets handler. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -static void otg_rxfifo_handler(USBDriver *usbp) { - uint32_t sts, cnt, ep; - - sts = usbp->otg->GRXSTSP; - switch (sts & GRXSTSP_PKTSTS_MASK) { - case GRXSTSP_SETUP_COMP: - break; - case GRXSTSP_SETUP_DATA: - cnt = (sts & GRXSTSP_BCNT_MASK) >> GRXSTSP_BCNT_OFF; - ep = (sts & GRXSTSP_EPNUM_MASK) >> GRXSTSP_EPNUM_OFF; - otg_fifo_read_to_buffer(usbp->otg->FIFO[0], usbp->epc[ep]->setup_buf, - cnt, 8); - break; - case GRXSTSP_OUT_DATA: - cnt = (sts & GRXSTSP_BCNT_MASK) >> GRXSTSP_BCNT_OFF; - ep = (sts & GRXSTSP_EPNUM_MASK) >> GRXSTSP_EPNUM_OFF; - otg_fifo_read_to_buffer(usbp->otg->FIFO[0], - usbp->epc[ep]->out_state->rxbuf, - cnt, - usbp->epc[ep]->out_state->rxsize - - usbp->epc[ep]->out_state->rxcnt); - usbp->epc[ep]->out_state->rxbuf += cnt; - usbp->epc[ep]->out_state->rxcnt += cnt; - break; - case GRXSTSP_OUT_GLOBAL_NAK: - case GRXSTSP_OUT_COMP: - default: - ; - } -} - -/** - * @brief Outgoing packets handler. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -static bool otg_txfifo_handler(USBDriver *usbp, usbep_t ep) { - - /* The TXFIFO is filled until there is space and data to be transmitted.*/ - while (true) { - uint32_t n; - - /* Transaction end condition.*/ - if (usbp->epc[ep]->in_state->txcnt >= usbp->epc[ep]->in_state->txsize) - return true; - - /* Number of bytes remaining in current transaction.*/ - n = usbp->epc[ep]->in_state->txsize - usbp->epc[ep]->in_state->txcnt; - if (n > usbp->epc[ep]->in_maxsize) - n = usbp->epc[ep]->in_maxsize; - - /* Checks if in the TXFIFO there is enough space to accommodate the - next packet.*/ - if (((usbp->otg->ie[ep].DTXFSTS & DTXFSTS_INEPTFSAV_MASK) * 4) < n) - return false; - -#if STM32_USB_OTGFIFO_FILL_BASEPRI - __set_BASEPRI(CORTEX_PRIO_MASK(STM32_USB_OTGFIFO_FILL_BASEPRI)); -#endif - otg_fifo_write_from_buffer(usbp->otg->FIFO[ep], - usbp->epc[ep]->in_state->txbuf, - n); - usbp->epc[ep]->in_state->txbuf += n; -#if STM32_USB_OTGFIFO_FILL_BASEPRI - __set_BASEPRI(0); -#endif - usbp->epc[ep]->in_state->txcnt += n; - } -} - -/** - * @brief Generic endpoint IN handler. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -static void otg_epin_handler(USBDriver *usbp, usbep_t ep) { - stm32_otg_t *otgp = usbp->otg; - uint32_t epint = otgp->ie[ep].DIEPINT; - - otgp->ie[ep].DIEPINT = epint; - - if (epint & DIEPINT_TOC) { - /* Timeouts not handled yet, not sure how to handle.*/ - } - if ((epint & DIEPINT_XFRC) && (otgp->DIEPMSK & DIEPMSK_XFRCM)) { - /* Transmit transfer complete.*/ - USBInEndpointState *isp = usbp->epc[ep]->in_state; - - if (isp->txsize < isp->totsize) { - /* In case the transaction covered only part of the total transfer - then another transaction is immediately started in order to - cover the remaining.*/ - isp->txsize = isp->totsize - isp->txsize; - isp->txcnt = 0; - osalSysLockFromISR(); - usb_lld_start_in(usbp, ep); - osalSysUnlockFromISR(); - } - else { - /* End on IN transfer.*/ - _usb_isr_invoke_in_cb(usbp, ep); - } - } - if ((epint & DIEPINT_TXFE) && - (otgp->DIEPEMPMSK & DIEPEMPMSK_INEPTXFEM(ep))) { - /* The thread is made ready, it will be scheduled on ISR exit.*/ - osalSysLockFromISR(); - usbp->txpending |= (1 << ep); - otgp->DIEPEMPMSK &= ~(1 << ep); - osalThreadResumeI(&usbp->wait, MSG_OK); - osalSysUnlockFromISR(); - } -} - -/** - * @brief Generic endpoint OUT handler. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -static void otg_epout_handler(USBDriver *usbp, usbep_t ep) { - stm32_otg_t *otgp = usbp->otg; - uint32_t epint = otgp->oe[ep].DOEPINT; - - /* Resets all EP IRQ sources.*/ - otgp->oe[ep].DOEPINT = epint; - - if ((epint & DOEPINT_STUP) && (otgp->DOEPMSK & DOEPMSK_STUPM)) { - /* Setup packets handling, setup packets are handled using a - specific callback.*/ - _usb_isr_invoke_setup_cb(usbp, ep); - } - if ((epint & DOEPINT_XFRC) && (otgp->DOEPMSK & DOEPMSK_XFRCM)) { - USBOutEndpointState *osp; - - /* Receive transfer complete, checking if it is a SETUP transfer on EP0, - that it must be ignored, the STUPM handler will take care of it.*/ - if ((ep == 0) && (usbp->ep0state == USB_EP0_WAITING_SETUP)) - return; - - /* OUT state structure pointer for this endpoint.*/ - osp = usbp->epc[ep]->out_state; - - /* A short packet always terminates a transaction.*/ - if (((osp->rxcnt % usbp->epc[ep]->out_maxsize) == 0) && - (osp->rxsize < osp->totsize)) { - /* In case the transaction covered only part of the total transfer - then another transaction is immediately started in order to - cover the remaining.*/ - osp->rxsize = osp->totsize - osp->rxsize; - osp->rxcnt = 0; - osalSysLockFromISR(); - usb_lld_start_out(usbp, ep); - osalSysUnlockFromISR(); - } - else { - /* End on OUT transfer.*/ - _usb_isr_invoke_out_cb(usbp, ep); - } - } -} - -/** - * @brief Isochronous IN transfer failed handler. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -static void otg_isoc_in_failed_handler(USBDriver *usbp) { - usbep_t ep; - stm32_otg_t *otgp = usbp->otg; - - for (ep = 0; ep <= usbp->otgparams->num_endpoints; ep++) { - if (((otgp->ie[ep].DIEPCTL & DIEPCTL_EPTYP_MASK) == DIEPCTL_EPTYP_ISO) && - ((otgp->ie[ep].DIEPCTL & DIEPCTL_EPENA) != 0)) { - /* Endpoint enabled -> ISOC IN transfer failed */ - /* Disable endpoint */ - otgp->ie[ep].DIEPCTL |= (DIEPCTL_EPDIS | DIEPCTL_SNAK); - while (otgp->ie[ep].DIEPCTL & DIEPCTL_EPENA) - ; - - /* Flush FIFO */ - otg_txfifo_flush(usbp, ep); - - /* Prepare data for next frame */ - _usb_isr_invoke_in_cb(usbp, ep); - - /* Pump out data for next frame */ - osalSysLockFromISR(); - otgp->DIEPEMPMSK &= ~(1 << ep); - usbp->txpending |= (1 << ep); - osalThreadResumeI(&usbp->wait, MSG_OK); - osalSysUnlockFromISR(); - } - } -} - -/** - * @brief Isochronous OUT transfer failed handler. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -static void otg_isoc_out_failed_handler(USBDriver *usbp) { - usbep_t ep; - stm32_otg_t *otgp = usbp->otg; - - for (ep = 0; ep <= usbp->otgparams->num_endpoints; ep++) { - if (((otgp->oe[ep].DOEPCTL & DOEPCTL_EPTYP_MASK) == DOEPCTL_EPTYP_ISO) && - ((otgp->oe[ep].DOEPCTL & DOEPCTL_EPENA) != 0)) { - /* Endpoint enabled -> ISOC OUT transfer failed */ - /* Disable endpoint */ - /* FIXME: Core stucks here */ - /*otgp->oe[ep].DOEPCTL |= (DOEPCTL_EPDIS | DOEPCTL_SNAK); - while (otgp->oe[ep].DOEPCTL & DOEPCTL_EPENA) - ;*/ - /* Prepare transfer for next frame */ - _usb_isr_invoke_out_cb(usbp, ep); - } - } -} - -/** - * @brief OTG shared ISR. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -static void usb_lld_serve_interrupt(USBDriver *usbp) { - stm32_otg_t *otgp = usbp->otg; - uint32_t sts, src; - - sts = otgp->GINTSTS; - sts &= otgp->GINTMSK; - otgp->GINTSTS = sts; - - /* Reset interrupt handling.*/ - if (sts & GINTSTS_USBRST) { - - /* Resetting pending operations.*/ - usbp->txpending = 0; - - /* Default reset action.*/ - _usb_reset(usbp); - - /* Preventing execution of more handlers, the core has been reset.*/ - return; - } - - /* Wake-up handling.*/ - if (sts & GINTSTS_WKUPINT) { - /* If clocks are gated off, turn them back on (may be the case if - coming out of suspend mode).*/ - if (otgp->PCGCCTL & (PCGCCTL_STPPCLK | PCGCCTL_GATEHCLK)) { - /* Set to zero to un-gate the USB core clocks.*/ - otgp->PCGCCTL &= ~(PCGCCTL_STPPCLK | PCGCCTL_GATEHCLK); - } - - /* Clear the Remote Wake-up Signaling.*/ - otgp->DCTL |= DCTL_RWUSIG; - - _usb_wakeup(usbp); - } - - /* Suspend handling.*/ - if (sts & GINTSTS_USBSUSP) { - - /* Resetting pending operations.*/ - usbp->txpending = 0; - - /* Default suspend action.*/ - _usb_suspend(usbp); - } - - /* Enumeration done.*/ - if (sts & GINTSTS_ENUMDNE) { - /* Full or High speed timing selection.*/ - if ((otgp->DSTS & DSTS_ENUMSPD_MASK) == DSTS_ENUMSPD_HS_480) { - otgp->GUSBCFG = (otgp->GUSBCFG & ~(GUSBCFG_TRDT_MASK)) | - GUSBCFG_TRDT(TRDT_VALUE_HS); - } - else { - otgp->GUSBCFG = (otgp->GUSBCFG & ~(GUSBCFG_TRDT_MASK)) | - GUSBCFG_TRDT(TRDT_VALUE_FS); - } - } - - /* SOF interrupt handling.*/ - if (sts & GINTSTS_SOF) { - _usb_isr_invoke_sof_cb(usbp); - } - - /* Isochronous IN failed handling */ - if (sts & GINTSTS_IISOIXFR) { - otg_isoc_in_failed_handler(usbp); - } - - /* Isochronous OUT failed handling */ - if (sts & GINTSTS_IISOOXFR) { - otg_isoc_out_failed_handler(usbp); - } - - /* RX FIFO not empty handling.*/ - if (sts & GINTSTS_RXFLVL) { - /* The interrupt is masked while the thread has control or it would - be triggered again.*/ - osalSysLockFromISR(); - otgp->GINTMSK &= ~GINTMSK_RXFLVLM; - osalThreadResumeI(&usbp->wait, MSG_OK); - osalSysUnlockFromISR(); - } - - /* IN/OUT endpoints event handling.*/ - src = otgp->DAINT; - if (sts & GINTSTS_IEPINT) { - if (src & (1 << 0)) - otg_epin_handler(usbp, 0); - if (src & (1 << 1)) - otg_epin_handler(usbp, 1); - if (src & (1 << 2)) - otg_epin_handler(usbp, 2); - if (src & (1 << 3)) - otg_epin_handler(usbp, 3); -#if STM32_USB_USE_OTG2 - if (src & (1 << 4)) - otg_epin_handler(usbp, 4); - if (src & (1 << 5)) - otg_epin_handler(usbp, 5); -#endif - } - if (sts & GINTSTS_OEPINT) { - if (src & (1 << 16)) - otg_epout_handler(usbp, 0); - if (src & (1 << 17)) - otg_epout_handler(usbp, 1); - if (src & (1 << 18)) - otg_epout_handler(usbp, 2); - if (src & (1 << 19)) - otg_epout_handler(usbp, 3); -#if STM32_USB_USE_OTG2 - if (src & (1 << 20)) - otg_epout_handler(usbp, 4); - if (src & (1 << 21)) - otg_epout_handler(usbp, 5); -#endif - } -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if STM32_USB_USE_OTG1 || defined(__DOXYGEN__) -#if !defined(STM32_OTG1_HANDLER) -#error "STM32_OTG1_HANDLER not defined" -#endif -/** - * @brief OTG1 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_OTG1_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - usb_lld_serve_interrupt(&USBD1); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if STM32_USB_USE_OTG2 || defined(__DOXYGEN__) -#if !defined(STM32_OTG2_HANDLER) -#error "STM32_OTG2_HANDLER not defined" -#endif -/** - * @brief OTG2 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_OTG2_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - usb_lld_serve_interrupt(&USBD2); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level USB driver initialization. - * - * @notapi - */ -void usb_lld_init(void) { - - /* Driver initialization.*/ -#if STM32_USB_USE_OTG1 - usbObjectInit(&USBD1); - USBD1.wait = NULL; - USBD1.otg = OTG_FS; - USBD1.otgparams = &fsparams; - -#if defined(_CHIBIOS_RT_) - USBD1.tr = NULL; - /* Filling the thread working area here because the function - @p chThdCreateI() does not do it.*/ -#if CH_DBG_FILL_THREADS - { - void *wsp = USBD1.wa_pump; - _thread_memfill((uint8_t *)wsp, - (uint8_t *)wsp + sizeof(thread_t), - CH_DBG_THREAD_FILL_VALUE); - _thread_memfill((uint8_t *)wsp + sizeof(thread_t), - (uint8_t *)wsp + sizeof(USBD1.wa_pump), - CH_DBG_STACK_FILL_VALUE); - } -#endif /* CH_DBG_FILL_THREADS */ -#endif /* defined(_CHIBIOS_RT_) */ -#endif - -#if STM32_USB_USE_OTG2 - usbObjectInit(&USBD2); - USBD2.wait = NULL; - USBD2.otg = OTG_HS; - USBD2.otgparams = &hsparams; - -#if defined(_CHIBIOS_RT_) - USBD2.tr = NULL; - /* Filling the thread working area here because the function - @p chThdCreateI() does not do it.*/ -#if CH_DBG_FILL_THREADS - { - void *wsp = USBD2.wa_pump; - _thread_memfill((uint8_t *)wsp, - (uint8_t *)wsp + sizeof(thread_t), - CH_DBG_THREAD_FILL_VALUE); - _thread_memfill((uint8_t *)wsp + sizeof(thread_t), - (uint8_t *)wsp + sizeof(USBD2.wa_pump), - CH_DBG_STACK_FILL_VALUE); - } -#endif /* CH_DBG_FILL_THREADS */ -#endif /* defined(_CHIBIOS_RT_) */ -#endif -} - -/** - * @brief Configures and activates the USB peripheral. - * @note Starting the OTG cell can be a slow operation carried out with - * interrupts disabled, perform it before starting time-critical - * operations. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -void usb_lld_start(USBDriver *usbp) { - stm32_otg_t *otgp = usbp->otg; - - if (usbp->state == USB_STOP) { - /* Clock activation.*/ - -#if STM32_USB_USE_OTG1 - if (&USBD1 == usbp) { - /* OTG FS clock enable and reset.*/ - rccEnableOTG_FS(false); - rccResetOTG_FS(); - - /* Enables IRQ vector.*/ - nvicEnableVector(STM32_OTG1_NUMBER, STM32_USB_OTG1_IRQ_PRIORITY); - - /* - Forced device mode. - - USB turn-around time = TRDT_VALUE_FS. - - Full Speed 1.1 PHY.*/ - otgp->GUSBCFG = GUSBCFG_FDMOD | GUSBCFG_TRDT(TRDT_VALUE_FS) | - GUSBCFG_PHYSEL; - - /* 48MHz 1.1 PHY.*/ - otgp->DCFG = 0x02200000 | DCFG_DSPD_FS11; - } -#endif - -#if STM32_USB_USE_OTG2 - if (&USBD2 == usbp) { - /* OTG HS clock enable and reset.*/ - rccEnableOTG_HS(false); - rccResetOTG_HS(); - - /* ULPI clock is managed depending on the presence of an external - PHY.*/ -#if defined(BOARD_OTG2_USES_ULPI) - rccEnableOTG_HSULPI(true); -#else - /* Workaround for the problem described here: - http://forum.chibios.org/phpbb/viewtopic.php?f=16&t=1798.*/ - rccDisableOTG_HSULPI(true); -#endif - - /* Enables IRQ vector.*/ - nvicEnableVector(STM32_OTG2_NUMBER, STM32_USB_OTG2_IRQ_PRIORITY); - - /* - Forced device mode. - - USB turn-around time = TRDT_VALUE_HS or TRDT_VALUE_FS.*/ -#if defined(BOARD_OTG2_USES_ULPI) - /* High speed ULPI PHY.*/ - otgp->GUSBCFG = GUSBCFG_FDMOD | GUSBCFG_TRDT(TRDT_VALUE_HS) | - GUSBCFG_SRPCAP | GUSBCFG_HNPCAP; -#else - otgp->GUSBCFG = GUSBCFG_FDMOD | GUSBCFG_TRDT(TRDT_VALUE_FS) | - GUSBCFG_PHYSEL; -#endif - -#if defined(BOARD_OTG2_USES_ULPI) -#if STM32_USE_USB_OTG2_HS - /* USB 2.0 High Speed PHY in HS mode.*/ - otgp->DCFG = 0x02200000 | DCFG_DSPD_HS; -#else - /* USB 2.0 High Speed PHY in FS mode.*/ - otgp->DCFG = 0x02200000 | DCFG_DSPD_HS_FS; -#endif -#else - /* 48MHz 1.1 PHY.*/ - otgp->DCFG = 0x02200000 | DCFG_DSPD_FS11; -#endif - } -#endif - - /* Clearing mask of TXFIFOs to be filled.*/ - usbp->txpending = 0; - - /* PHY enabled.*/ - otgp->PCGCCTL = 0; - - /* VBUS sensing and transceiver enabled.*/ - otgp->GOTGCTL = GOTGCTL_BVALOEN | GOTGCTL_BVALOVAL; - -#if defined(BOARD_OTG2_USES_ULPI) -#if STM32_USB_USE_OTG1 - if (&USBD1 == usbp) { - otgp->GCCFG = GCCFG_INIT_VALUE; - } -#endif - -#if STM32_USB_USE_OTG2 - if (&USBD2 == usbp) { - otgp->GCCFG = 0; - } -#endif -#else - otgp->GCCFG = GCCFG_INIT_VALUE; -#endif - - /* Soft core reset.*/ - otg_core_reset(usbp); - - /* Interrupts on TXFIFOs half empty.*/ - otgp->GAHBCFG = 0; - - /* Endpoints re-initialization.*/ - otg_disable_ep(usbp); - - /* Clear all pending Device Interrupts, only the USB Reset interrupt - is required initially.*/ - otgp->DIEPMSK = 0; - otgp->DOEPMSK = 0; - otgp->DAINTMSK = 0; - if (usbp->config->sof_cb == NULL) - otgp->GINTMSK = GINTMSK_ENUMDNEM | GINTMSK_USBRSTM | GINTMSK_USBSUSPM | - GINTMSK_ESUSPM | GINTMSK_SRQM | GINTMSK_WKUM | - GINTMSK_IISOIXFRM | GINTMSK_IISOOXFRM; - else - otgp->GINTMSK = GINTMSK_ENUMDNEM | GINTMSK_USBRSTM | GINTMSK_USBSUSPM | - GINTMSK_ESUSPM | GINTMSK_SRQM | GINTMSK_WKUM | - GINTMSK_IISOIXFRM | GINTMSK_IISOOXFRM | - GINTMSK_SOFM; - - /* Clears all pending IRQs, if any. */ - otgp->GINTSTS = 0xFFFFFFFF; - -#if defined(_CHIBIOS_RT_) - /* Creates the data pump thread. Note, it is created only once.*/ - if (usbp->tr == NULL) { - usbp->tr = chThdCreateI(usbp->wa_pump, sizeof usbp->wa_pump, - STM32_USB_OTG_THREAD_PRIO, - usb_lld_pump, usbp); - chThdStartI(usbp->tr); - chSchRescheduleS(); - } -#endif - - /* Global interrupts enable.*/ - otgp->GAHBCFG |= GAHBCFG_GINTMSK; - } -} - -/** - * @brief Deactivates the USB peripheral. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -void usb_lld_stop(USBDriver *usbp) { - stm32_otg_t *otgp = usbp->otg; - - /* If in ready state then disables the USB clock.*/ - if (usbp->state != USB_STOP) { - - /* Disabling all endpoints in case the driver has been stopped while - active.*/ - otg_disable_ep(usbp); - - usbp->txpending = 0; - - otgp->DAINTMSK = 0; - otgp->GAHBCFG = 0; - otgp->GCCFG = 0; - -#if STM32_USB_USE_OTG1 - if (&USBD1 == usbp) { - nvicDisableVector(STM32_OTG1_NUMBER); - rccDisableOTG_FS(false); - } -#endif - -#if STM32_USB_USE_OTG2 - if (&USBD2 == usbp) { - nvicDisableVector(STM32_OTG2_NUMBER); - rccDisableOTG_HS(false); -#if defined(BOARD_OTG2_USES_ULPI) - rccDisableOTG_HSULPI(true) -#endif - } -#endif - } -} - -/** - * @brief USB low level reset routine. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -void usb_lld_reset(USBDriver *usbp) { - unsigned i; - stm32_otg_t *otgp = usbp->otg; - - /* Flush the Tx FIFO.*/ - otg_txfifo_flush(usbp, 0); - - /* Endpoint interrupts all disabled and cleared.*/ - otgp->DIEPEMPMSK = 0; - otgp->DAINTMSK = DAINTMSK_OEPM(0) | DAINTMSK_IEPM(0); - - /* All endpoints in NAK mode, interrupts cleared.*/ - for (i = 0; i <= usbp->otgparams->num_endpoints; i++) { - otgp->ie[i].DIEPCTL = DIEPCTL_SNAK; - otgp->oe[i].DOEPCTL = DOEPCTL_SNAK; - otgp->ie[i].DIEPINT = 0xFFFFFFFF; - otgp->oe[i].DOEPINT = 0xFFFFFFFF; - } - - /* Resets the FIFO memory allocator.*/ - otg_ram_reset(usbp); - - /* Receive FIFO size initialization, the address is always zero.*/ - otgp->GRXFSIZ = usbp->otgparams->rx_fifo_size; - otg_rxfifo_flush(usbp); - - /* Resets the device address to zero.*/ - otgp->DCFG = (otgp->DCFG & ~DCFG_DAD_MASK) | DCFG_DAD(0); - - /* Enables also EP-related interrupt sources.*/ - otgp->GINTMSK |= GINTMSK_RXFLVLM | GINTMSK_OEPM | GINTMSK_IEPM; - otgp->DIEPMSK = DIEPMSK_TOCM | DIEPMSK_XFRCM; - otgp->DOEPMSK = DOEPMSK_STUPM | DOEPMSK_XFRCM; - - /* EP0 initialization, it is a special case.*/ - usbp->epc[0] = &ep0config; - otgp->oe[0].DOEPTSIZ = 0; - otgp->oe[0].DOEPCTL = DOEPCTL_SD0PID | DOEPCTL_USBAEP | DOEPCTL_EPTYP_CTRL | - DOEPCTL_MPSIZ(ep0config.out_maxsize); - otgp->ie[0].DIEPTSIZ = 0; - otgp->ie[0].DIEPCTL = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_CTRL | - DIEPCTL_TXFNUM(0) | DIEPCTL_MPSIZ(ep0config.in_maxsize); - otgp->DIEPTXF0 = DIEPTXF_INEPTXFD(ep0config.in_maxsize / 4) | - DIEPTXF_INEPTXSA(otg_ram_alloc(usbp, - ep0config.in_maxsize / 4)); -} - -/** - * @brief Sets the USB address. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -void usb_lld_set_address(USBDriver *usbp) { - stm32_otg_t *otgp = usbp->otg; - - otgp->DCFG = (otgp->DCFG & ~DCFG_DAD_MASK) | DCFG_DAD(usbp->address); -} - -/** - * @brief Enables an endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) { - uint32_t ctl, fsize; - stm32_otg_t *otgp = usbp->otg; - - /* IN and OUT common parameters.*/ - switch (usbp->epc[ep]->ep_mode & USB_EP_MODE_TYPE) { - case USB_EP_MODE_TYPE_CTRL: - ctl = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_CTRL; - break; - case USB_EP_MODE_TYPE_ISOC: - ctl = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_ISO; - break; - case USB_EP_MODE_TYPE_BULK: - ctl = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_BULK; - break; - case USB_EP_MODE_TYPE_INTR: - ctl = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_INTR; - break; - default: - return; - } - - /* OUT endpoint activation or deactivation.*/ - otgp->oe[ep].DOEPTSIZ = 0; - if (usbp->epc[ep]->out_state != NULL) { - otgp->oe[ep].DOEPCTL = ctl | DOEPCTL_MPSIZ(usbp->epc[ep]->out_maxsize); - otgp->DAINTMSK |= DAINTMSK_OEPM(ep); - } - else { - otgp->oe[ep].DOEPCTL &= ~DOEPCTL_USBAEP; - otgp->DAINTMSK &= ~DAINTMSK_OEPM(ep); - } - - /* IN endpoint activation or deactivation.*/ - otgp->ie[ep].DIEPTSIZ = 0; - if (usbp->epc[ep]->in_state != NULL) { - /* FIFO allocation for the IN endpoint.*/ - fsize = usbp->epc[ep]->in_maxsize / 4; - if (usbp->epc[ep]->in_multiplier > 1) - fsize *= usbp->epc[ep]->in_multiplier; - otgp->DIEPTXF[ep - 1] = DIEPTXF_INEPTXFD(fsize) | - DIEPTXF_INEPTXSA(otg_ram_alloc(usbp, fsize)); - otg_txfifo_flush(usbp, ep); - - otgp->ie[ep].DIEPCTL = ctl | - DIEPCTL_TXFNUM(ep) | - DIEPCTL_MPSIZ(usbp->epc[ep]->in_maxsize); - otgp->DAINTMSK |= DAINTMSK_IEPM(ep); - } - else { - otgp->DIEPTXF[ep - 1] = 0x02000400; /* Reset value.*/ - otg_txfifo_flush(usbp, ep); - otgp->ie[ep].DIEPCTL &= ~DIEPCTL_USBAEP; - otgp->DAINTMSK &= ~DAINTMSK_IEPM(ep); - } -} - -/** - * @brief Disables all the active endpoints except the endpoint zero. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -void usb_lld_disable_endpoints(USBDriver *usbp) { - - /* Resets the FIFO memory allocator.*/ - otg_ram_reset(usbp); - - /* Disabling all endpoints.*/ - otg_disable_ep(usbp); -} - -/** - * @brief Returns the status of an OUT endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @return The endpoint status. - * @retval EP_STATUS_DISABLED The endpoint is not active. - * @retval EP_STATUS_STALLED The endpoint is stalled. - * @retval EP_STATUS_ACTIVE The endpoint is active. - * - * @notapi - */ -usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep) { - uint32_t ctl; - - (void)usbp; - - ctl = usbp->otg->oe[ep].DOEPCTL; - if (!(ctl & DOEPCTL_USBAEP)) - return EP_STATUS_DISABLED; - if (ctl & DOEPCTL_STALL) - return EP_STATUS_STALLED; - return EP_STATUS_ACTIVE; -} - -/** - * @brief Returns the status of an IN endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @return The endpoint status. - * @retval EP_STATUS_DISABLED The endpoint is not active. - * @retval EP_STATUS_STALLED The endpoint is stalled. - * @retval EP_STATUS_ACTIVE The endpoint is active. - * - * @notapi - */ -usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep) { - uint32_t ctl; - - (void)usbp; - - ctl = usbp->otg->ie[ep].DIEPCTL; - if (!(ctl & DIEPCTL_USBAEP)) - return EP_STATUS_DISABLED; - if (ctl & DIEPCTL_STALL) - return EP_STATUS_STALLED; - return EP_STATUS_ACTIVE; -} - -/** - * @brief Reads a setup packet from the dedicated packet buffer. - * @details This function must be invoked in the context of the @p setup_cb - * callback in order to read the received setup packet. - * @pre In order to use this function the endpoint must have been - * initialized as a control endpoint. - * @post The endpoint is ready to accept another packet. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @param[out] buf buffer where to copy the packet data - * - * @notapi - */ -void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) { - - memcpy(buf, usbp->epc[ep]->setup_buf, 8); -} - -/** - * @brief Starts a receive operation on an OUT endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_start_out(USBDriver *usbp, usbep_t ep) { - uint32_t pcnt, rxsize; - USBOutEndpointState *osp = usbp->epc[ep]->out_state; - - /* Transfer initialization.*/ - osp->totsize = osp->rxsize; - if ((ep == 0) && (osp->rxsize > EP0_MAX_OUTSIZE)) - osp->rxsize = EP0_MAX_OUTSIZE; - - /* Transaction size is rounded to a multiple of packet size because the - following requirement in the RM: - "For OUT transfers, the transfer size field in the endpoint's transfer - size register must be a multiple of the maximum packet size of the - endpoint, adjusted to the Word boundary".*/ - pcnt = (osp->rxsize + usbp->epc[ep]->out_maxsize - 1U) / - usbp->epc[ep]->out_maxsize; - rxsize = (pcnt * usbp->epc[ep]->out_maxsize + 3U) & 0xFFFFFFFCU; - - /*Setting up transaction parameters in DOEPTSIZ.*/ - usbp->otg->oe[ep].DOEPTSIZ = DOEPTSIZ_STUPCNT(3) | DOEPTSIZ_PKTCNT(pcnt) | - DOEPTSIZ_XFRSIZ(rxsize); - - /* Special case of isochronous endpoint.*/ - if ((usbp->epc[ep]->ep_mode & USB_EP_MODE_TYPE) == USB_EP_MODE_TYPE_ISOC) { - /* Odd/even bit toggling for isochronous endpoint.*/ - if (usbp->otg->DSTS & DSTS_FNSOF_ODD) - usbp->otg->oe[ep].DOEPCTL |= DOEPCTL_SEVNFRM; - else - usbp->otg->oe[ep].DOEPCTL |= DOEPCTL_SODDFRM; - } - - /* Starting operation.*/ - usbp->otg->oe[ep].DOEPCTL |= DOEPCTL_EPENA | DOEPCTL_CNAK; -} - -/** - * @brief Starts a transmit operation on an IN endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_start_in(USBDriver *usbp, usbep_t ep) { - USBInEndpointState *isp = usbp->epc[ep]->in_state; - - /* Transfer initialization.*/ - isp->totsize = isp->txsize; - if (isp->txsize == 0) { - /* Special case, sending zero size packet.*/ - usbp->otg->ie[ep].DIEPTSIZ = DIEPTSIZ_PKTCNT(1) | DIEPTSIZ_XFRSIZ(0); - } - else { - if ((ep == 0) && (isp->txsize > EP0_MAX_INSIZE)) - isp->txsize = EP0_MAX_INSIZE; - - /* Normal case.*/ - uint32_t pcnt = (isp->txsize + usbp->epc[ep]->in_maxsize - 1) / - usbp->epc[ep]->in_maxsize; - /* TODO: Support more than one packet per frame for isochronous transfers.*/ - usbp->otg->ie[ep].DIEPTSIZ = DIEPTSIZ_MCNT(1) | DIEPTSIZ_PKTCNT(pcnt) | - DIEPTSIZ_XFRSIZ(isp->txsize); - } - - /* Special case of isochronous endpoint.*/ - if ((usbp->epc[ep]->ep_mode & USB_EP_MODE_TYPE) == USB_EP_MODE_TYPE_ISOC) { - /* Odd/even bit toggling.*/ - if (usbp->otg->DSTS & DSTS_FNSOF_ODD) - usbp->otg->ie[ep].DIEPCTL |= DIEPCTL_SEVNFRM; - else - usbp->otg->ie[ep].DIEPCTL |= DIEPCTL_SODDFRM; - } - - /* Starting operation.*/ - usbp->otg->ie[ep].DIEPCTL |= DIEPCTL_EPENA | DIEPCTL_CNAK; - usbp->otg->DIEPEMPMSK |= DIEPEMPMSK_INEPTXFEM(ep); -} - -/** - * @brief Brings an OUT endpoint in the stalled state. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_stall_out(USBDriver *usbp, usbep_t ep) { - - usbp->otg->oe[ep].DOEPCTL |= DOEPCTL_STALL; -} - -/** - * @brief Brings an IN endpoint in the stalled state. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_stall_in(USBDriver *usbp, usbep_t ep) { - - usbp->otg->ie[ep].DIEPCTL |= DIEPCTL_STALL; -} - -/** - * @brief Brings an OUT endpoint in the active state. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_clear_out(USBDriver *usbp, usbep_t ep) { - - usbp->otg->oe[ep].DOEPCTL &= ~DOEPCTL_STALL; -} - -/** - * @brief Brings an IN endpoint in the active state. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_clear_in(USBDriver *usbp, usbep_t ep) { - - usbp->otg->ie[ep].DIEPCTL &= ~DIEPCTL_STALL; -} - -/** - * @brief USB data transfer loop. - * @details This function must be executed by a system thread in order to - * make the USB driver work. - * @note The data copy part of the driver is implemented in this thread - * in order to not perform heavy tasks within interrupt handlers. - * - * @param[in] p pointer to the @p USBDriver object - * - * @special - */ -void usb_lld_pump(void *p) { - USBDriver *usbp = (USBDriver *)p; - stm32_otg_t *otgp = usbp->otg; - -#if defined(_CHIBIOS_RT_) - chRegSetThreadName("usb_lld_pump"); -#endif - osalSysLock(); - while (true) { - usbep_t ep; - uint32_t epmask; - - /* Nothing to do, going to sleep.*/ - if ((usbp->state == USB_STOP) || - ((usbp->txpending == 0) && !(otgp->GINTSTS & GINTSTS_RXFLVL))) { - otgp->GINTMSK |= GINTMSK_RXFLVLM; - osalThreadSuspendS(&usbp->wait); - } - osalSysUnlock(); - - /* Checks if there are TXFIFOs to be filled.*/ - for (ep = 0; ep <= usbp->otgparams->num_endpoints; ep++) { - - /* Empties the RX FIFO.*/ - while (otgp->GINTSTS & GINTSTS_RXFLVL) { - otg_rxfifo_handler(usbp); - } - - epmask = (1 << ep); - if (usbp->txpending & epmask) { - bool done; - - osalSysLock(); - /* USB interrupts are globally *suspended* because the peripheral - does not allow any interference during the TX FIFO filling - operation. - Synopsys document: DesignWare Cores USB 2.0 Hi-Speed On-The-Go (OTG) - "The application has to finish writing one complete packet before - switching to a different channel/endpoint FIFO. Violating this - rule results in an error.".*/ - otgp->GAHBCFG &= ~GAHBCFG_GINTMSK; - usbp->txpending &= ~epmask; - osalSysUnlock(); - - done = otg_txfifo_handler(usbp, ep); - - osalSysLock(); - otgp->GAHBCFG |= GAHBCFG_GINTMSK; - if (!done) - otgp->DIEPEMPMSK |= epmask; - osalSysUnlock(); - } - } - osalSysLock(); - } -} - -#endif /* HAL_USE_USB */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/OTGv1/usb_lld.h b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/OTGv1/usb_lld.h deleted file mode 100644 index de9f31b3fa..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/OTGv1/usb_lld.h +++ /dev/null @@ -1,595 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/OTGv1/usb_lld.h - * @brief STM32 USB subsystem low level driver header. - * - * @addtogroup USB - * @{ - */ - -#ifndef _USB_LLD_H_ -#define _USB_LLD_H_ - -#if HAL_USE_USB || defined(__DOXYGEN__) - -#include "stm32_otg.h" - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Status stage handling method. - */ -#define USB_EP0_STATUS_STAGE USB_EP0_STATUS_STAGE_SW - -/** - * @brief The address can be changed immediately upon packet reception. - */ -#define USB_SET_ADDRESS_MODE USB_EARLY_SET_ADDRESS - -/** - * @brief Method for set address acknowledge. - */ -#define USB_SET_ADDRESS_ACK_HANDLING USB_SET_ADDRESS_ACK_SW - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief OTG1 driver enable switch. - * @details If set to @p TRUE the support for OTG_FS is included. - * @note The default is @p FALSE - */ -#if !defined(STM32_USB_USE_OTG1) || defined(__DOXYGEN__) -#define STM32_USB_USE_OTG1 FALSE -#endif - -/** - * @brief OTG2 driver enable switch. - * @details If set to @p TRUE the support for OTG_HS is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_USB_USE_OTG2) || defined(__DOXYGEN__) -#define STM32_USB_USE_OTG2 FALSE -#endif - -/** - * @brief OTG1 interrupt priority level setting. - */ -#if !defined(STM32_USB_OTG1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_USB_OTG1_IRQ_PRIORITY 14 -#endif - -/** - * @brief OTG2 interrupt priority level setting. - */ -#if !defined(STM32_USB_OTG2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_USB_OTG2_IRQ_PRIORITY 14 -#endif - -/** - * @brief OTG1 RX shared FIFO size. - * @note Must be a multiple of 4. - */ -#if !defined(STM32_USB_OTG1_RX_FIFO_SIZE) || defined(__DOXYGEN__) -#define STM32_USB_OTG1_RX_FIFO_SIZE 512 -#endif - -/** - * @brief OTG2 RX shared FIFO size. - * @note Must be a multiple of 4. - */ -#if !defined(STM32_USB_OTG2_RX_FIFO_SIZE) || defined(__DOXYGEN__) -#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 -#endif - -/** - * @brief Enables HS mode on OTG2 else FS mode. - * @note The default is @p TRUE. - * @note Has effect only if @p BOARD_OTG2_USES_ULPI is defined. - */ -#if !defined(STM32_USE_USB_OTG2_HS) || defined(__DOXYGEN__) -#define STM32_USE_USB_OTG2_HS TRUE -#endif - -/** - * @brief Dedicated data pump threads priority. - */ -#if !defined(STM32_USB_OTG_THREAD_PRIO) || defined(__DOXYGEN__) -#define STM32_USB_OTG_THREAD_PRIO LOWPRIO -#endif - -/** - * @brief Dedicated data pump threads stack size. - */ -#if !defined(STM32_USB_OTG_THREAD_STACK_SIZE) || defined(__DOXYGEN__) -#define STM32_USB_OTG_THREAD_STACK_SIZE 128 -#endif - -/** - * @brief Exception priority level during TXFIFOs operations. - * @note Because an undocumented silicon behavior the operation of - * copying a packet into a TXFIFO must not be interrupted by - * any other operation on the OTG peripheral. - * This parameter represents the priority mask during copy - * operations. The default value only allows to call USB - * functions from callbacks invoked from USB ISR handlers. - * If you need to invoke USB functions from other handlers - * then raise this priority mast to the same level of the - * handler you need to use. - * @note The value zero means disabled, when disabled calling USB - * functions is only safe from thread level or from USB - * callbacks. - */ -#if !defined(STM32_USB_OTGFIFO_FILL_BASEPRI) || defined(__DOXYGEN__) -#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/* Registry checks.*/ -#if !defined(STM32_OTG_STEPPING) -#error "STM32_OTG_STEPPING not defined in registry" -#endif - -#if (STM32_OTG_STEPPING < 1) || (STM32_OTG_STEPPING > 2) -#error "unsupported STM32_OTG_STEPPING" -#endif - -#if !defined(STM32_HAS_OTG1) || !defined(STM32_HAS_OTG2) -#error "STM32_HAS_OTGx not defined in registry" -#endif - -#if STM32_HAS_OTG1 && !defined(STM32_OTG1_ENDPOINTS) -#error "STM32_OTG1_ENDPOINTS not defined in registry" -#endif - -#if STM32_HAS_OTG2 && !defined(STM32_OTG2_ENDPOINTS) -#error "STM32_OTG2_ENDPOINTS not defined in registry" -#endif - -#if (STM32_USB_USE_OTG1 && !defined(STM32_OTG1_HANDLER)) || \ - (STM32_USB_USE_OTG2 && !defined(STM32_OTG2_HANDLER)) -#error "STM32_OTGx_HANDLER not defined in registry" -#endif - -#if (STM32_USB_USE_OTG1 && !defined(STM32_OTG1_NUMBER)) || \ - (STM32_USB_USE_OTG2 && !defined(STM32_OTG2_NUMBER)) -#error "STM32_OTGx_NUMBER not defined in registry" -#endif - -/** - * @brief Maximum endpoint address. - */ -#if (STM32_HAS_OTG2 && STM32_USB_USE_OTG2) || defined(__DOXYGEN__) -#if (STM32_OTG1_ENDPOINTS < STM32_OTG2_ENDPOINTS) || defined(__DOXYGEN__) -#define USB_MAX_ENDPOINTS STM32_OTG2_ENDPOINTS -#else -#define USB_MAX_ENDPOINTS STM32_OTG1_ENDPOINTS -#endif -#else -#define USB_MAX_ENDPOINTS STM32_OTG1_ENDPOINTS -#endif - -#if STM32_USB_USE_OTG1 && !STM32_HAS_OTG1 -#error "OTG1 not present in the selected device" -#endif - -#if STM32_USB_USE_OTG2 && !STM32_HAS_OTG2 -#error "OTG2 not present in the selected device" -#endif - -#if !STM32_USB_USE_OTG1 && !STM32_USB_USE_OTG2 -#error "USB driver activated but no USB peripheral assigned" -#endif - -#if STM32_USB_USE_OTG1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_USB_OTG1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to OTG1" -#endif - -#if STM32_USB_USE_OTG2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_USB_OTG2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to OTG2" -#endif - -#if (STM32_USB_OTG1_RX_FIFO_SIZE & 3) != 0 -#error "OTG1 RX FIFO size must be a multiple of 4" -#endif - -#if (STM32_USB_OTG2_RX_FIFO_SIZE & 3) != 0 -#error "OTG2 RX FIFO size must be a multiple of 4" -#endif - -#if defined(STM32F2XX) || defined(STM32F4XX) || defined(STM32F7XX) -#define STM32_USBCLK STM32_PLL48CLK -#elif defined(STM32F10X_CL) -#define STM32_USBCLK STM32_OTGFSCLK -#elif defined(STM32L4XX) -#define STM32_USBCLK STM32_48CLK -#else -#error "unsupported STM32 platform for OTG functionality" -#endif - -#if STM32_USBCLK != 48000000 -#error "the USB OTG driver requires a 48MHz clock" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Peripheral-specific parameters block. - */ -typedef struct { - uint32_t rx_fifo_size; - uint32_t otg_ram_size; - uint32_t num_endpoints; -} stm32_otg_params_t; - -/** - * @brief Type of an IN endpoint state structure. - */ -typedef struct { - /** - * @brief Requested transmit transfer size. - */ - size_t txsize; - /** - * @brief Transmitted bytes so far. - */ - size_t txcnt; - /** - * @brief Pointer to the transmission linear buffer. - */ - const uint8_t *txbuf; -#if (USB_USE_WAIT == TRUE) || defined(__DOXYGEN__) - /** - * @brief Waiting thread. - */ - thread_reference_t thread; -#endif - /* End of the mandatory fields.*/ - /** - * @brief Total transmit transfer size. - */ - size_t totsize; -} USBInEndpointState; - -/** - * @brief Type of an OUT endpoint state structure. - */ -typedef struct { - /** - * @brief Requested receive transfer size. - */ - size_t rxsize; - /** - * @brief Received bytes so far. - */ - size_t rxcnt; - /** - * @brief Pointer to the receive linear buffer. - */ - uint8_t *rxbuf; -#if (USB_USE_WAIT == TRUE) || defined(__DOXYGEN__) - /** - * @brief Waiting thread. - */ - thread_reference_t thread; -#endif - /* End of the mandatory fields.*/ - /** - * @brief Total receive transfer size. - */ - size_t totsize; -} USBOutEndpointState; - -/** - * @brief Type of an USB endpoint configuration structure. - * @note Platform specific restrictions may apply to endpoints. - */ -typedef struct { - /** - * @brief Type and mode of the endpoint. - */ - uint32_t ep_mode; - /** - * @brief Setup packet notification callback. - * @details This callback is invoked when a setup packet has been - * received. - * @post The application must immediately call @p usbReadPacket() in - * order to access the received packet. - * @note This field is only valid for @p USB_EP_MODE_TYPE_CTRL - * endpoints, it should be set to @p NULL for other endpoint - * types. - */ - usbepcallback_t setup_cb; - /** - * @brief IN endpoint notification callback. - * @details This field must be set to @p NULL if callback is not required. - */ - usbepcallback_t in_cb; - /** - * @brief OUT endpoint notification callback. - * @details This field must be set to @p NULL if callback is not required. - */ - usbepcallback_t out_cb; - /** - * @brief IN endpoint maximum packet size. - * @details This field must be set to zero if the IN endpoint is not used. - */ - uint16_t in_maxsize; - /** - * @brief OUT endpoint maximum packet size. - * @details This field must be set to zero if the OUT endpoint is not used. - */ - uint16_t out_maxsize; - /** - * @brief @p USBEndpointState associated to the IN endpoint. - * @details This field must be set to @p NULL if the IN endpoint is not - * used. - */ - USBInEndpointState *in_state; - /** - * @brief @p USBEndpointState associated to the OUT endpoint. - * @details This field must be set to @p NULL if the OUT endpoint is not - * used. - */ - USBOutEndpointState *out_state; - /* End of the mandatory fields.*/ - /** - * @brief Determines the space allocated for the TXFIFO as multiples of - * the packet size (@p in_maxsize). Note that zero is interpreted - * as one for simplicity and robustness. - */ - uint16_t in_multiplier; - /** - * @brief Pointer to a buffer for setup packets. - * @details Setup packets require a dedicated 8-bytes buffer, set this - * field to @p NULL for non-control endpoints. - */ - uint8_t *setup_buf; -} USBEndpointConfig; - -/** - * @brief Type of an USB driver configuration structure. - */ -typedef struct { - /** - * @brief USB events callback. - * @details This callback is invoked when an USB driver event is registered. - */ - usbeventcb_t event_cb; - /** - * @brief Device GET_DESCRIPTOR request callback. - * @note This callback is mandatory and cannot be set to @p NULL. - */ - usbgetdescriptor_t get_descriptor_cb; - /** - * @brief Requests hook callback. - * @details This hook allows to be notified of standard requests or to - * handle non standard requests. - */ - usbreqhandler_t requests_hook_cb; - /** - * @brief Start Of Frame callback. - */ - usbcallback_t sof_cb; - /* End of the mandatory fields.*/ -} USBConfig; - -/** - * @brief Structure representing an USB driver. - */ -struct USBDriver { - /** - * @brief Driver state. - */ - usbstate_t state; - /** - * @brief Current configuration data. - */ - const USBConfig *config; - /** - * @brief Bit map of the transmitting IN endpoints. - */ - uint16_t transmitting; - /** - * @brief Bit map of the receiving OUT endpoints. - */ - uint16_t receiving; - /** - * @brief Active endpoints configurations. - */ - const USBEndpointConfig *epc[USB_MAX_ENDPOINTS + 1]; - /** - * @brief Fields available to user, it can be used to associate an - * application-defined handler to an IN endpoint. - * @note The base index is one, the endpoint zero does not have a - * reserved element in this array. - */ - void *in_params[USB_MAX_ENDPOINTS]; - /** - * @brief Fields available to user, it can be used to associate an - * application-defined handler to an OUT endpoint. - * @note The base index is one, the endpoint zero does not have a - * reserved element in this array. - */ - void *out_params[USB_MAX_ENDPOINTS]; - /** - * @brief Endpoint 0 state. - */ - usbep0state_t ep0state; - /** - * @brief Next position in the buffer to be transferred through endpoint 0. - */ - uint8_t *ep0next; - /** - * @brief Number of bytes yet to be transferred through endpoint 0. - */ - size_t ep0n; - /** - * @brief Endpoint 0 end transaction callback. - */ - usbcallback_t ep0endcb; - /** - * @brief Setup packet buffer. - */ - uint8_t setup[8]; - /** - * @brief Current USB device status. - */ - uint16_t status; - /** - * @brief Assigned USB address. - */ - uint8_t address; - /** - * @brief Current USB device configuration. - */ - uint8_t configuration; - /** - * @brief State of the driver when a suspend happened. - */ - usbstate_t saved_state; -#if defined(USB_DRIVER_EXT_FIELDS) - USB_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the OTG peripheral associated to this driver. - */ - stm32_otg_t *otg; - /** - * @brief Peripheral-specific parameters. - */ - const stm32_otg_params_t *otgparams; - /** - * @brief Pointer to the next address in the packet memory. - */ - uint32_t pmnext; - /** - * @brief Mask of TXFIFOs to be filled by the pump thread. - */ - uint32_t txpending; - /** - * @brief Pointer to the thread when it is sleeping or @p NULL. - */ - thread_reference_t wait; -#if defined(_CHIBIOS_RT_) - /** - * @brief Pointer to the thread. - */ - thread_reference_t tr; - /** - * @brief Working area for the dedicated data pump thread; - */ - THD_WORKING_AREA(wa_pump, STM32_USB_OTG_THREAD_STACK_SIZE); -#endif -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Returns the exact size of a receive transaction. - * @details The received size can be different from the size specified in - * @p usbStartReceiveI() because the last packet could have a size - * different from the expected one. - * @pre The OUT endpoint must have been configured in transaction mode - * in order to use this function. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @return Received data size. - * - * @notapi - */ -#define usb_lld_get_transaction_size(usbp, ep) \ - ((usbp)->epc[ep]->out_state->rxcnt) - -/** - * @brief Connects the USB device. - * - * @api - */ -#if (STM32_OTG_STEPPING == 1) || defined(__DOXYGEN__) -#define usb_lld_connect_bus(usbp) ((usbp)->otg->GCCFG |= GCCFG_VBUSBSEN) -#else -#define usb_lld_connect_bus(usbp) ((usbp)->otg->DCTL &= ~DCTL_SDIS) -#endif - -/** - * @brief Disconnect the USB device. - * - * @api - */ -#if (STM32_OTG_STEPPING == 1) || defined(__DOXYGEN__) -#define usb_lld_disconnect_bus(usbp) ((usbp)->otg->GCCFG &= ~GCCFG_VBUSBSEN) -#else -#define usb_lld_disconnect_bus(usbp) ((usbp)->otg->DCTL |= DCTL_SDIS) -#endif - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_USB_USE_OTG1 && !defined(__DOXYGEN__) -extern USBDriver USBD1; -#endif - -#if STM32_USB_USE_OTG2 && !defined(__DOXYGEN__) -extern USBDriver USBD2; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void usb_lld_init(void); - void usb_lld_start(USBDriver *usbp); - void usb_lld_stop(USBDriver *usbp); - void usb_lld_reset(USBDriver *usbp); - void usb_lld_set_address(USBDriver *usbp); - void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep); - void usb_lld_disable_endpoints(USBDriver *usbp); - usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep); - usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep); - void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf); - void usb_lld_start_out(USBDriver *usbp, usbep_t ep); - void usb_lld_start_in(USBDriver *usbp, usbep_t ep); - void usb_lld_stall_out(USBDriver *usbp, usbep_t ep); - void usb_lld_stall_in(USBDriver *usbp, usbep_t ep); - void usb_lld_clear_out(USBDriver *usbp, usbep_t ep); - void usb_lld_clear_in(USBDriver *usbp, usbep_t ep); - void usb_lld_pump(void *p); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_USB */ - -#endif /* _USB_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/RTCv1/rtc_lld.c b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/RTCv1/rtc_lld.c deleted file mode 100644 index 08c87d9ad6..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/RTCv1/rtc_lld.c +++ /dev/null @@ -1,443 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Concepts and parts of this file have been contributed by Uladzimir Pylinsky - aka barthess. - */ - -/** - * @file STM32/RTCv1/rtc_lld.c - * @brief STM32 RTC subsystem low level driver header. - * - * @addtogroup RTC - * @{ - */ - -#include "hal.h" - -#if HAL_USE_RTC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief RTC driver identifier. - */ -RTCDriver RTCD1; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Wait for synchronization of RTC registers with APB1 bus. - * @details This function must be invoked before trying to read RTC registers - * in the backup domain: DIV, CNT, ALR. CR registers can always - * be read. - * - * @notapi - */ -static void rtc_apb1_sync(void) { - - while ((RTC->CRL & RTC_CRL_RSF) == 0) - ; -} - -/** - * @brief Wait for for previous write operation complete. - * @details This function must be invoked before writing to any RTC registers - * - * @notapi - */ -static void rtc_wait_write_completed(void) { - - while ((RTC->CRL & RTC_CRL_RTOFF) == 0) - ; -} - -/** - * @brief Acquires write access to RTC registers. - * @details Before writing to the backup domain RTC registers the previous - * write operation must be completed. Use this function before - * writing to PRL, CNT, ALR registers. - * - * @notapi - */ -static void rtc_acquire_access(void) { - - rtc_wait_write_completed(); - RTC->CRL |= RTC_CRL_CNF; -} - -/** - * @brief Releases write access to RTC registers. - * - * @notapi - */ -static void rtc_release_access(void) { - - RTC->CRL &= ~RTC_CRL_CNF; -} - -/** - * @brief Converts time from timespec to seconds counter. - * - * @param[in] timespec pointer to a @p RTCDateTime structure - * @return the TR register encoding. - * - * @notapi - */ -static time_t rtc_encode(const RTCDateTime *timespec) { - struct tm tim; - - rtcConvertDateTimeToStructTm(timespec, &tim, NULL); - return mktime(&tim); -} - -/** - * @brief Converts time from seconds/milliseconds to timespec. - * - * @param[in] tv_sec seconds value - * @param[in] tv_msec milliseconds value - * @param[out] timespec pointer to a @p RTCDateTime structure - * - * @notapi - */ -static void rtc_decode(uint32_t tv_sec, - uint32_t tv_msec, - RTCDateTime *timespec) { - struct tm tim; - struct tm *t; - - /* If the conversion is successful the function returns a pointer - to the object the result was written into.*/ -#if defined(__GNUC__) || defined(__CC_ARM) - t = localtime_r((time_t *)&(tv_sec), &tim); - osalDbgAssert(t != NULL, "conversion failed"); -#else - struct tm *t = localtime(&tv_sec); - memcpy(&tim, t, sizeof(struct tm)); -#endif - - rtcConvertStructTmToDateTime(&tim, tv_msec, timespec); -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief RTC interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_RTC1_HANDLER) { - uint16_t flags; - - OSAL_IRQ_PROLOGUE(); - - /* Code hits this wait only when AHB1 bus was previously powered off by any - reason (standby, reset, etc). In other cases there is no waiting.*/ - rtc_apb1_sync(); - - /* Mask of all enabled and pending sources.*/ - flags = RTCD1.rtc->CRH & RTCD1.rtc->CRL; - RTCD1.rtc->CRL &= ~(RTC_CRL_SECF | RTC_CRL_ALRF | RTC_CRL_OWF); - - if (flags & RTC_CRL_SECF) - RTCD1.callback(&RTCD1, RTC_EVENT_SECOND); - - if (flags & RTC_CRL_ALRF) - RTCD1.callback(&RTCD1, RTC_EVENT_ALARM); - - if (flags & RTC_CRL_OWF) - RTCD1.callback(&RTCD1, RTC_EVENT_OVERFLOW); - - OSAL_IRQ_EPILOGUE(); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Load value of RTCCLK to prescaler registers. - * @note The pre-scaler must not be set on every reset as RTC clock - * counts are lost when it is set. - * @note This function designed to be called from - * hal_lld_backup_domain_init(). Because there is only place - * where possible to detect BKP domain reset event reliably. - * - * @notapi - */ -void rtc_lld_set_prescaler(void) { - syssts_t sts; - - /* Entering a reentrant critical zone.*/ - sts = osalSysGetStatusAndLockX(); - - rtc_acquire_access(); - RTC->PRLH = (uint16_t)((STM32_RTCCLK - 1) >> 16) & 0x000F; - RTC->PRLL = (uint16_t)(((STM32_RTCCLK - 1)) & 0xFFFF); - rtc_release_access(); - - /* Leaving a reentrant critical zone.*/ - osalSysRestoreStatusX(sts); -} - -/** - * @brief Initialize RTC. - * - * @notapi - */ -void rtc_lld_init(void) { - - /* RTC object initialization.*/ - rtcObjectInit(&RTCD1); - - /* RTC pointer initialization.*/ - RTCD1.rtc = RTC; - - /* RSF bit must be cleared by software after an APB1 reset or an APB1 clock - stop. Otherwise its value will not be actual. */ - RTCD1.rtc->CRL &= ~RTC_CRL_RSF; - - /* Required because access to PRL.*/ - rtc_apb1_sync(); - - /* All interrupts initially disabled.*/ - rtc_wait_write_completed(); - RTCD1.rtc->CRH = 0; - - /* Callback initially disabled.*/ - RTCD1.callback = NULL; - - /* IRQ vector permanently assigned to this driver.*/ - nvicEnableVector(STM32_RTC1_NUMBER, STM32_RTC_IRQ_PRIORITY); -} - -/** - * @brief Set current time. - * @note Fractional part will be silently ignored. There is no possibility - * to change it on STM32F1xx platform. - * @note The function can be called from any context. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[in] timespec pointer to a @p RTCDateTime structure - * - * @notapi - */ -void rtc_lld_set_time(RTCDriver *rtcp, const RTCDateTime *timespec) { - time_t tv_sec = rtc_encode(timespec); - - rtcSTM32SetSec(rtcp, tv_sec); -} - -/** - * @brief Get current time. - * @note The function can be called from any context. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[in] timespec pointer to a @p RTCDateTime structure - * - * @notapi - */ -void rtc_lld_get_time(RTCDriver *rtcp, RTCDateTime *timespec) { - uint32_t tv_sec, tv_msec; - - rtcSTM32GetSecMsec(rtcp, &tv_sec, &tv_msec); - rtc_decode(tv_sec, tv_msec, timespec); -} - -/** - * @brief Set alarm time. - * - * @note Default value after BKP domain reset is 0xFFFFFFFF - * @note The function can be called from any context. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[in] alarm alarm identifier - * @param[in] alarmspec pointer to a @p RTCAlarm structure - * - * @notapi - */ -void rtc_lld_set_alarm(RTCDriver *rtcp, - rtcalarm_t alarm_number, - const RTCAlarm *alarmspec) { - syssts_t sts; - (void)alarm_number; - - /* Entering a reentrant critical zone.*/ - sts = osalSysGetStatusAndLockX(); - - rtc_acquire_access(); - if (alarmspec != NULL) { - rtcp->rtc->ALRH = (uint16_t)(alarmspec->tv_sec >> 16); - rtcp->rtc->ALRL = (uint16_t)(alarmspec->tv_sec & 0xFFFF); - } - else { - rtcp->rtc->ALRH = 0; - rtcp->rtc->ALRL = 0; - } - rtc_release_access(); - - /* Leaving a reentrant critical zone.*/ - osalSysRestoreStatusX(sts); -} - -/** - * @brief Get current alarm. - * @note If an alarm has not been set then the returned alarm specification - * is not meaningful. - * @note The function can be called from any context. - * @note Default value after BKP domain reset is 0xFFFFFFFF. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[in] alarm alarm identifier - * @param[out] alarmspec pointer to a @p RTCAlarm structure - * - * @notapi - */ -void rtc_lld_get_alarm(RTCDriver *rtcp, - rtcalarm_t alarm_number, - RTCAlarm *alarmspec) { - syssts_t sts; - (void)alarm_number; - - /* Entering a reentrant critical zone.*/ - sts = osalSysGetStatusAndLockX(); - - /* Required because access to ALR.*/ - rtc_apb1_sync(); - - alarmspec->tv_sec = ((rtcp->rtc->ALRH << 16) + rtcp->rtc->ALRL); - - /* Leaving a reentrant critical zone.*/ - osalSysRestoreStatusX(sts); -} - -/** - * @brief Enables or disables RTC callbacks. - * @details This function enables or disables callbacks, use a @p NULL pointer - * in order to disable a callback. - * @note The function can be called from any context. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[in] callback callback function pointer or @p NULL - * - * @notapi - */ -void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback) { - syssts_t sts; - - /* Entering a reentrant critical zone.*/ - sts = osalSysGetStatusAndLockX(); - - if (callback != NULL) { - - /* IRQ sources enabled only after setting up the callback.*/ - rtcp->callback = callback; - - rtc_wait_write_completed(); - rtcp->rtc->CRL &= ~(RTC_CRL_OWF | RTC_CRL_ALRF | RTC_CRL_SECF); - rtcp->rtc->CRH = RTC_CRH_OWIE | RTC_CRH_ALRIE | RTC_CRH_SECIE; - } - else { - rtc_wait_write_completed(); - rtcp->rtc->CRH = 0; - - /* Callback set to NULL only after disabling the IRQ sources.*/ - rtcp->callback = NULL; - } - - /* Leaving a reentrant critical zone.*/ - osalSysRestoreStatusX(sts); -} - -/** - * @brief Get seconds and (optionally) milliseconds from RTC. - * @note The function can be called from any context. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[out] tv_sec pointer to seconds value - * @param[out] tv_msec pointer to milliseconds value, set it - * to @p NULL if not needed - * - * @api - */ -void rtcSTM32GetSecMsec(RTCDriver *rtcp, uint32_t *tv_sec, uint32_t *tv_msec) { - uint32_t time_frac; - syssts_t sts; - - osalDbgCheck((NULL != tv_sec) && (NULL != rtcp)); - - /* Entering a reentrant critical zone.*/ - sts = osalSysGetStatusAndLockX(); - - /* Required because access to CNT and DIV.*/ - rtc_apb1_sync(); - - /* Loops until two consecutive read returning the same value.*/ - do { - *tv_sec = ((uint32_t)(rtcp->rtc->CNTH) << 16) + rtcp->rtc->CNTL; - time_frac = (((uint32_t)rtcp->rtc->DIVH) << 16) + (uint32_t)rtcp->rtc->DIVL; - } while ((*tv_sec) != (((uint32_t)(rtcp->rtc->CNTH) << 16) + rtcp->rtc->CNTL)); - - /* Leaving a reentrant critical zone.*/ - osalSysRestoreStatusX(sts); - - if (NULL != tv_msec) - *tv_msec = (((uint32_t)STM32_RTCCLK - 1 - time_frac) * 1000) / STM32_RTCCLK; -} - -/** - * @brief Set seconds in RTC. - * @note The function can be called from any context. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[in] tv_sec seconds value - * - * @api - */ -void rtcSTM32SetSec(RTCDriver *rtcp, uint32_t tv_sec) { - syssts_t sts; - - osalDbgCheck(NULL != rtcp); - - /* Entering a reentrant critical zone.*/ - sts = osalSysGetStatusAndLockX(); - - rtc_acquire_access(); - rtcp->rtc->CNTH = (uint16_t)(tv_sec >> 16); - rtcp->rtc->CNTL = (uint16_t)(tv_sec & 0xFFFF); - rtc_release_access(); - - /* Leaving a reentrant critical zone.*/ - osalSysRestoreStatusX(sts); -} - -#endif /* HAL_USE_RTC */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/RTCv1/rtc_lld.h b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/RTCv1/rtc_lld.h deleted file mode 100644 index 87cd758668..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/RTCv1/rtc_lld.h +++ /dev/null @@ -1,198 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Concepts and parts of this file have been contributed by Uladzimir Pylinsky - aka barthess. - */ - -/** - * @file STM32/RTCv1/rtc_lld.h - * @brief STM32F1xx RTC subsystem low level driver header. - * - * @addtogroup RTC - * @{ - */ - -#ifndef _RTC_LLD_H_ -#define _RTC_LLD_H_ - -#if HAL_USE_RTC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name Implementation capabilities - */ -/** - * @brief This RTC implementation supports callbacks. - */ -#define RTC_SUPPORTS_CALLBACKS TRUE - -/** - * @brief One alarm comparator available. - */ -#define RTC_ALARMS 1 - -/** - * @brief Presence of a local persistent storage. - */ -#define RTC_HAS_STORAGE FALSE -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/* - * RTC driver system settings. - */ -#define STM32_RTC_IRQ_PRIORITY 15 -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if HAL_USE_RTC && !STM32_HAS_RTC -#error "RTC not present in the selected device" -#endif - -#if STM32_RTCCLK == 0 -#error "RTC clock not enabled" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief FileStream specific methods. - */ -#define _rtc_driver_methods \ - _file_stream_methods - -/** - * @brief Type of a structure representing an RTC alarm time stamp. - */ -typedef struct RTCAlarm RTCAlarm; - -/** - * @brief Type of an RTC alarm. - * @details Meaningful on platforms with more than 1 alarm comparator. - */ -typedef uint32_t rtcalarm_t; - -/** - * @brief Type of an RTC event. - */ -typedef enum { - RTC_EVENT_SECOND = 0, /** Triggered every second. */ - RTC_EVENT_ALARM = 1, /** Triggered on alarm. */ - RTC_EVENT_OVERFLOW = 2 /** Triggered on counter overflow. */ -} rtcevent_t; - -/** - * @brief Type of a generic RTC callback. - */ -typedef void (*rtccb_t)(RTCDriver *rtcp, rtcevent_t event); - -/** - * @brief Structure representing an RTC alarm time stamp. - */ -struct RTCAlarm { - /** - * @brief Seconds since UNIX epoch. - */ - uint32_t tv_sec; -}; - -#if RTC_HAS_STORAGE || defined(__DOXYGEN__) -/** - * @extends FileStream - * - * @brief @p RTCDriver virtual methods table. - */ -struct RTCDriverVMT { - _rtc_driver_methods -}; -#endif - -/** - * @brief Structure representing an RTC driver. - */ -struct RTCDriver{ -#if RTC_HAS_STORAGE || defined(__DOXYGEN__) - /** - * @brief Virtual Methods Table. - */ - const struct RTCDriverVMT *vmt; -#endif - /** - * @brief Pointer to the RTC registers block. - */ - RTC_TypeDef *rtc; - /** - * @brief Callback pointer. - */ - rtccb_t callback; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -extern RTCDriver RTCD1; -#if RTC_HAS_STORAGE -extern struct RTCDriverVMT _rtc_lld_vmt; -#endif -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void rtc_lld_set_prescaler(void); - void rtc_lld_init(void); - void rtc_lld_set_time(RTCDriver *rtcp, const RTCDateTime *timespec); - void rtc_lld_get_time(RTCDriver *rtcp, RTCDateTime *timespec); - void rtc_lld_set_alarm(RTCDriver *rtcp, - rtcalarm_t alarm_number, - const RTCAlarm *alarmspec); - void rtc_lld_get_alarm(RTCDriver *rtcp, - rtcalarm_t alarm_number, - RTCAlarm *alarmspec); - void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback); - void rtcSTM32GetSecMsec(RTCDriver *rtcp, uint32_t *tv_sec, uint32_t *tv_msec); - void rtcSTM32SetSec(RTCDriver *rtcp, uint32_t tv_sec); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_RTC */ - -#endif /* _RTC_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.c b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.c deleted file mode 100644 index 17068ab6de..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.c +++ /dev/null @@ -1,555 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Concepts and parts of this file have been contributed by Uladzimir Pylinsky - aka barthess. - */ - -/** - * @file STM32/RTCv2/rtc_lld.c - * @brief STM32L1xx/STM32F2xx/STM32F4xx RTC low level driver. - * - * @addtogroup RTC - * @{ - */ - -#include "hal.h" - -#if HAL_USE_RTC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define RTC_TR_PM_OFFSET 22 -#define RTC_TR_HT_OFFSET 20 -#define RTC_TR_HU_OFFSET 16 -#define RTC_TR_MNT_OFFSET 12 -#define RTC_TR_MNU_OFFSET 8 -#define RTC_TR_ST_OFFSET 4 -#define RTC_TR_SU_OFFSET 0 - -#define RTC_DR_YT_OFFSET 20 -#define RTC_DR_YU_OFFSET 16 -#define RTC_DR_WDU_OFFSET 13 -#define RTC_DR_MT_OFFSET 12 -#define RTC_DR_MU_OFFSET 8 -#define RTC_DR_DT_OFFSET 4 -#define RTC_DR_DU_OFFSET 0 - -#define RTC_CR_BKP_OFFSET 18 - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief RTC driver identifier. - */ -RTCDriver RTCD1; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Beginning of configuration procedure. - * - * @notapi - */ -static void rtc_enter_init(void) { - - RTCD1.rtc->ISR |= RTC_ISR_INIT; - while ((RTCD1.rtc->ISR & RTC_ISR_INITF) == 0) - ; -} - -/** - * @brief Finalizing of configuration procedure. - * - * @notapi - */ -static inline void rtc_exit_init(void) { - - RTCD1.rtc->ISR &= ~RTC_ISR_INIT; -} - -/** - * @brief Converts time from TR register encoding to timespec. - * - * @param[in] tr TR register value - * @param[out] timespec pointer to a @p RTCDateTime structure - * - * @notapi - */ -static void rtc_decode_time(uint32_t tr, RTCDateTime *timespec) { - uint32_t n; - - n = ((tr >> RTC_TR_HT_OFFSET) & 3) * 36000000; - n += ((tr >> RTC_TR_HU_OFFSET) & 15) * 3600000; - n += ((tr >> RTC_TR_MNT_OFFSET) & 7) * 600000; - n += ((tr >> RTC_TR_MNU_OFFSET) & 15) * 60000; - n += ((tr >> RTC_TR_ST_OFFSET) & 7) * 10000; - n += ((tr >> RTC_TR_SU_OFFSET) & 15) * 1000; - timespec->millisecond = n; -} - -/** - * @brief Converts date from DR register encoding to timespec. - * - * @param[in] dr DR register value - * @param[out] timespec pointer to a @p RTCDateTime structure - * - * @notapi - */ -static void rtc_decode_date(uint32_t dr, RTCDateTime *timespec) { - - timespec->year = (((dr >> RTC_DR_YT_OFFSET) & 15) * 10) + - ((dr >> RTC_DR_YU_OFFSET) & 15); - timespec->month = (((dr >> RTC_TR_MNT_OFFSET) & 1) * 10) + - ((dr >> RTC_TR_MNU_OFFSET) & 15); - timespec->day = (((dr >> RTC_DR_DT_OFFSET) & 3) * 10) + - ((dr >> RTC_DR_DU_OFFSET) & 15); - timespec->dayofweek = (dr >> RTC_DR_WDU_OFFSET) & 7; -} - -/** - * @brief Converts time from timespec to TR register encoding. - * - * @param[in] timespec pointer to a @p RTCDateTime structure - * @return the TR register encoding. - * - * @notapi - */ -static uint32_t rtc_encode_time(const RTCDateTime *timespec) { - uint32_t n, tr = 0; - - /* Subseconds cannot be set.*/ - n = timespec->millisecond / 1000; - - /* Seconds conversion.*/ - tr = tr | ((n % 10) << RTC_TR_SU_OFFSET); - n /= 10; - tr = tr | ((n % 6) << RTC_TR_ST_OFFSET); - n /= 6; - - /* Minutes conversion.*/ - tr = tr | ((n % 10) << RTC_TR_MNU_OFFSET); - n /= 10; - tr = tr | ((n % 6) << RTC_TR_MNT_OFFSET); - n /= 6; - - /* Hours conversion.*/ - tr = tr | ((n % 10) << RTC_TR_HU_OFFSET); - n /= 10; - tr = tr | (n << RTC_TR_HT_OFFSET); - - return tr; -} - -/** - * @brief Converts a date from timespec to DR register encoding. - * - * @param[in] timespec pointer to a @p RTCDateTime structure - * @return the DR register encoding. - * - * @notapi - */ -static uint32_t rtc_encode_date(const RTCDateTime *timespec) { - uint32_t n, dr = 0; - - /* Year conversion. Note, only years last two digits are considered.*/ - n = timespec->year; - dr = dr | ((n % 10) << RTC_DR_YU_OFFSET); - n /= 10; - dr = dr | ((n % 10) << RTC_DR_YT_OFFSET); - - /* Months conversion.*/ - n = timespec->month; - dr = dr | ((n % 10) << RTC_DR_MU_OFFSET); - n /= 10; - dr = dr | ((n % 10) << RTC_DR_MT_OFFSET); - - /* Days conversion.*/ - n = timespec->day; - dr = dr | ((n % 10) << RTC_DR_DU_OFFSET); - n /= 10; - dr = dr | ((n % 10) << RTC_DR_DT_OFFSET); - - /* Days of week conversion.*/ - dr = dr | (timespec->dayofweek << RTC_DR_WDU_OFFSET); - - return dr; -} - -#if RTC_HAS_STORAGE -/* TODO: Map on the backup SRAM on devices that have it.*/ -static size_t _write(void *instance, const uint8_t *bp, size_t n) { - - (void)instance; - (void)bp; - (void)n; - - return 0; -} - -static size_t _read(void *instance, uint8_t *bp, size_t n) { - - (void)instance; - (void)bp; - (void)n; - - return 0; -} - -static msg_t _put(void *instance, uint8_t b) { - - (void)instance; - (void)b; - - return FILE_OK; -} - -static msg_t _get(void *instance) { - - (void)instance; - - return FILE_OK; -} - -static msg_t _close(void *instance) { - - /* Close is not supported.*/ - (void)instance; - - return FILE_OK; -} - -static msg_t _geterror(void *instance) { - - (void)instance; - - return (msg_t)0; -} - -static msg_t _getsize(void *instance) { - - (void)instance; - - return 0; -} - -static msg_t _getposition(void *instance) { - - (void)instance; - - return 0; -} - -static msg_t _lseek(void *instance, fileoffset_t offset) { - - (void)instance; - (void)offset; - - return FILE_OK; -} - -/** - * @brief VMT for the RTC storage file interface. - */ -struct RTCDriverVMT _rtc_lld_vmt = { - _write, _read, _put, _get, - _close, _geterror, _getsize, _getposition, _lseek -}; -#endif /* RTC_HAS_STORAGE */ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Enable access to registers. - * - * @notapi - */ -void rtc_lld_init(void) { - - /* RTC object initialization.*/ - rtcObjectInit(&RTCD1); - - /* RTC pointer initialization.*/ - RTCD1.rtc = RTC; - - /* Disable write protection. */ - RTCD1.rtc->WPR = 0xCA; - RTCD1.rtc->WPR = 0x53; - - /* If calendar has not been initialized yet then proceed with the - initial setup.*/ - if (!(RTCD1.rtc->ISR & RTC_ISR_INITS)) { - - rtc_enter_init(); - - RTCD1.rtc->CR = 0; - RTCD1.rtc->ISR = RTC_ISR_INIT; /* Clearing all but RTC_ISR_INIT. */ - RTCD1.rtc->PRER = STM32_RTC_PRER_BITS; - RTCD1.rtc->PRER = STM32_RTC_PRER_BITS; - - rtc_exit_init(); - } - else - RTCD1.rtc->ISR &= ~RTC_ISR_RSF; -} - -/** - * @brief Set current time. - * @note Fractional part will be silently ignored. There is no possibility - * to set it on STM32 platform. - * @note The function can be called from any context. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[in] timespec pointer to a @p RTCDateTime structure - * - * @notapi - */ -void rtc_lld_set_time(RTCDriver *rtcp, const RTCDateTime *timespec) { - uint32_t dr, tr; - syssts_t sts; - - tr = rtc_encode_time(timespec); - dr = rtc_encode_date(timespec); - - /* Entering a reentrant critical zone.*/ - sts = osalSysGetStatusAndLockX(); - - /* Writing the registers.*/ - rtc_enter_init(); - rtcp->rtc->TR = tr; - rtcp->rtc->DR = dr; - rtcp->rtc->CR |= timespec->dstflag << RTC_CR_BKP_OFFSET; - rtc_exit_init(); - - /* Leaving a reentrant critical zone.*/ - osalSysRestoreStatusX(sts); -} - -/** - * @brief Get current time. - * @note The function can be called from any context. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[out] timespec pointer to a @p RTCDateTime structure - * - * @notapi - */ -void rtc_lld_get_time(RTCDriver *rtcp, RTCDateTime *timespec) { - uint32_t dr, tr, cr; - uint32_t subs; -#if STM32_RTC_HAS_SUBSECONDS - uint32_t ssr; -#endif /* STM32_RTC_HAS_SUBSECONDS */ - syssts_t sts; - - /* Entering a reentrant critical zone.*/ - sts = osalSysGetStatusAndLockX(); - - /* Synchronization with the RTC and reading the registers, note - DR must be read last.*/ - while ((rtcp->rtc->ISR & RTC_ISR_RSF) == 0) - ; -#if STM32_RTC_HAS_SUBSECONDS - ssr = rtcp->rtc->SSR; -#endif /* STM32_RTC_HAS_SUBSECONDS */ - tr = rtcp->rtc->TR; - dr = rtcp->rtc->DR; - cr = rtcp->rtc->CR; - rtcp->rtc->ISR &= ~RTC_ISR_RSF; - - /* Leaving a reentrant critical zone.*/ - osalSysRestoreStatusX(sts); - - /* Decoding day time, this starts the atomic read sequence, see "Reading - the calendar" in the RTC documentation.*/ - rtc_decode_time(tr, timespec); - - /* If the RTC is capable of sub-second counting then the value is - normalized in milliseconds and added to the time.*/ -#if STM32_RTC_HAS_SUBSECONDS - subs = (((STM32_RTC_PRESS_VALUE - 1U) - ssr) * 1000U) / STM32_RTC_PRESS_VALUE; -#else - subs = 0; -#endif /* STM32_RTC_HAS_SUBSECONDS */ - timespec->millisecond += subs; - - /* Decoding date, this concludes the atomic read sequence.*/ - rtc_decode_date(dr, timespec); - - /* Retrieving the DST bit.*/ - timespec->dstflag = (cr >> RTC_CR_BKP_OFFSET) & 1; -} - -#if (RTC_ALARMS > 0) || defined(__DOXYGEN__) -/** - * @brief Set alarm time. - * @note Default value after BKP domain reset for both comparators is 0. - * @note Function does not performs any checks of alarm time validity. - * @note The function can be called from any context. - * - * @param[in] rtcp pointer to RTC driver structure. - * @param[in] alarm alarm identifier. Can be 1 or 2. - * @param[in] alarmspec pointer to a @p RTCAlarm structure. - * - * @notapi - */ -void rtc_lld_set_alarm(RTCDriver *rtcp, - rtcalarm_t alarm, - const RTCAlarm *alarmspec) { - syssts_t sts; - - /* Entering a reentrant critical zone.*/ - sts = osalSysGetStatusAndLockX(); - - if (alarm == 0) { - if (alarmspec != NULL) { - rtcp->rtc->CR &= ~RTC_CR_ALRAE; - while (!(rtcp->rtc->ISR & RTC_ISR_ALRAWF)) - ; - rtcp->rtc->ALRMAR = alarmspec->alrmr; - rtcp->rtc->CR |= RTC_CR_ALRAE; - rtcp->rtc->CR |= RTC_CR_ALRAIE; - } - else { - rtcp->rtc->CR &= ~RTC_CR_ALRAIE; - rtcp->rtc->CR &= ~RTC_CR_ALRAE; - } - } -#if RTC_ALARMS > 1 - else { - if (alarmspec != NULL) { - rtcp->rtc->CR &= ~RTC_CR_ALRBE; - while (!(rtcp->rtc->ISR & RTC_ISR_ALRBWF)) - ; - rtcp->rtc->ALRMBR = alarmspec->alrmr; - rtcp->rtc->CR |= RTC_CR_ALRBE; - rtcp->rtc->CR |= RTC_CR_ALRBIE; - } - else { - rtcp->rtc->CR &= ~RTC_CR_ALRBIE; - rtcp->rtc->CR &= ~RTC_CR_ALRBE; - } - } -#endif /* RTC_ALARMS > 1 */ - - /* Leaving a reentrant critical zone.*/ - osalSysRestoreStatusX(sts); -} - -/** - * @brief Get alarm time. - * @note The function can be called from any context. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[in] alarm alarm identifier - * @param[out] alarmspec pointer to a @p RTCAlarm structure - * - * @notapi - */ -void rtc_lld_get_alarm(RTCDriver *rtcp, - rtcalarm_t alarm, - RTCAlarm *alarmspec) { - - if (alarm == 0) - alarmspec->alrmr = rtcp->rtc->ALRMAR; -#if RTC_ALARMS > 1 - else - alarmspec->alrmr = rtcp->rtc->ALRMBR; -#endif /* RTC_ALARMS > 1 */ -} -#endif /* RTC_ALARMS > 0 */ - -#if STM32_RTC_HAS_PERIODIC_WAKEUPS || defined(__DOXYGEN__) -/** - * @brief Sets time of periodic wakeup. - * @note Default value after BKP domain reset is 0x0000FFFF - * @note The function can be called from any context. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[in] wakeupspec pointer to a @p RTCWakeup structure - * - * @api - */ -void rtcSTM32SetPeriodicWakeup(RTCDriver *rtcp, const RTCWakeup *wakeupspec) { - syssts_t sts; - - /* Entering a reentrant critical zone.*/ - sts = osalSysGetStatusAndLockX(); - - if (wakeupspec != NULL) { - osalDbgCheck(wakeupspec->wutr != 0x30000); - - rtcp->rtc->CR &= ~RTC_CR_WUTE; - while (!(rtcp->rtc->ISR & RTC_ISR_WUTWF)) - ; - rtcp->rtc->WUTR = wakeupspec->wutr & 0xFFFF; - rtcp->rtc->CR = (wakeupspec->wutr >> 16) & 0x7; - rtcp->rtc->CR |= RTC_CR_WUTIE; - rtcp->rtc->CR |= RTC_CR_WUTE; - } - else { - rtcp->rtc->CR &= ~RTC_CR_WUTIE; - rtcp->rtc->CR &= ~RTC_CR_WUTE; - } - - /* Leaving a reentrant critical zone.*/ - osalSysRestoreStatusX(sts); -} - -/** - * @brief Gets time of periodic wakeup. - * @note Default value after BKP domain reset is 0x0000FFFF - * @note The function can be called from any context. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[out] wakeupspec pointer to a @p RTCWakeup structure - * - * @api - */ -void rtcSTM32GetPeriodicWakeup(RTCDriver *rtcp, RTCWakeup *wakeupspec) { - syssts_t sts; - - /* Entering a reentrant critical zone.*/ - sts = osalSysGetStatusAndLockX(); - - wakeupspec->wutr = 0; - wakeupspec->wutr |= rtcp->rtc->WUTR; - wakeupspec->wutr |= (((uint32_t)rtcp->rtc->CR) & 0x7) << 16; - - /* Leaving a reentrant critical zone.*/ - osalSysRestoreStatusX(sts); -} -#endif /* STM32_RTC_HAS_PERIODIC_WAKEUPS */ - -#endif /* HAL_USE_RTC */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.h b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.h deleted file mode 100644 index 8cc2794fd1..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.h +++ /dev/null @@ -1,237 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Concepts and parts of this file have been contributed by Uladzimir Pylinsky - aka barthess. - */ - -/** - * @file STM32/RTCv2/rtc_lld.h - * @brief STM32L1xx/STM32F2xx/STM32F4xx RTC low level driver header. - * - * @addtogroup RTC - * @{ - */ - -#ifndef _RTC_LLD_H_ -#define _RTC_LLD_H_ - -#if HAL_USE_RTC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name Implementation capabilities - */ -/** - * @brief Callback support int the driver. - */ -#define RTC_SUPPORTS_CALLBACKS STM32_RTC_HAS_INTERRUPTS - -/** - * @brief Number of alarms available. - */ -#define RTC_ALARMS STM32_RTC_NUM_ALARMS - -/** - * @brief Presence of a local persistent storage. - */ -#define RTC_HAS_STORAGE FALSE -/** @} */ - -/** - * @brief RTC PRER register initializer. - */ -#define RTC_PRER(a, s) ((((a) - 1) << 16) | ((s) - 1)) - -/** - * @name Alarm helper macros - * @{ - */ -#define RTC_ALRM_MSK4 (1U << 31) -#define RTC_ALRM_WDSEL (1U << 30) -#define RTC_ALRM_DT(n) ((n) << 28) -#define RTC_ALRM_DU(n) ((n) << 24) -#define RTC_ALRM_MSK3 (1U << 23) -#define RTC_ALRM_HT(n) ((n) << 20) -#define RTC_ALRM_HU(n) ((n) << 16) -#define RTC_ALRM_MSK2 (1U << 15) -#define RTC_ALRM_MNT(n) ((n) << 12) -#define RTC_ALRM_MNU(n) ((n) << 8) -#define RTC_ALRM_MSK1 (1U << 7) -#define RTC_ALRM_ST(n) ((n) << 4) -#define RTC_ALRM_SU(n) ((n) << 0) -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief RTC PRES register initialization. - * @note The default is calculated for a 32768Hz clock. - */ -#if !defined(STM32_RTC_PRESA_VALUE) || defined(__DOXYGEN__) -#define STM32_RTC_PRESA_VALUE 32 -#endif - -/** - * @brief RTC PRESS divider initialization. - * @note The default is calculated for a 32768Hz clock. - */ -#if !defined(STM32_RTC_PRESS_VALUE) || defined(__DOXYGEN__) -#define STM32_RTC_PRESS_VALUE 1024 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if HAL_USE_RTC && !STM32_HAS_RTC -#error "RTC not present in the selected device" -#endif - -#if !(STM32_RTCSEL == STM32_RTCSEL_LSE) && \ - !(STM32_RTCSEL == STM32_RTCSEL_LSI) && \ - !(STM32_RTCSEL == STM32_RTCSEL_HSEDIV) -#error "invalid source selected for RTC clock" -#endif - -#if STM32_PCLK1 < (STM32_RTCCLK * 7) -#error "STM32_PCLK1 frequency is too low" -#endif - -/** - * @brief Initialization for the RTC_PRER register. - */ -#define STM32_RTC_PRER_BITS RTC_PRER(STM32_RTC_PRESA_VALUE, \ - STM32_RTC_PRESS_VALUE) - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief FileStream specific methods. - */ -#define _rtc_driver_methods \ - _file_stream_methods - -/** - * @brief Type of an RTC alarm number. - */ -typedef uint32_t rtcalarm_t; - -/** - * @brief Type of a structure representing an RTC alarm time stamp. - */ -typedef struct { - /** - * @brief Type of an alarm as encoded in RTC ALRMxR registers. - */ - uint32_t alrmr; -} RTCAlarm; - -#if STM32_RTC_HAS_PERIODIC_WAKEUPS -/** - * @brief Type of a wakeup as encoded in RTC WUTR register. - */ -typedef struct { - /** - * @brief Wakeup as encoded in RTC WUTR register. - * @note ((WUTR == 0) || (WUCKSEL == 3)) are a forbidden combination. - */ - uint32_t wutr; -} RTCWakeup; -#endif - -#if RTC_HAS_STORAGE || defined(__DOXYGEN__) -/** - * @extends FileStream - * - * @brief @p RTCDriver virtual methods table. - */ -struct RTCDriverVMT { - _rtc_driver_methods -}; -#endif - -/** - * @brief Structure representing an RTC driver. - */ -struct RTCDriver { -#if RTC_HAS_STORAGE || defined(__DOXYGEN__) - /** - * @brief Virtual Methods Table. - */ - const struct RTCDriverVMT *vmt; -#endif - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the RTC registers block. - */ - RTC_TypeDef *rtc; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -extern RTCDriver RTCD1; -#if RTC_HAS_STORAGE -extern struct RTCDriverVMT _rtc_lld_vmt; -#endif -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void rtc_lld_init(void); - void rtc_lld_set_time(RTCDriver *rtcp, const RTCDateTime *timespec); - void rtc_lld_get_time(RTCDriver *rtcp, RTCDateTime *timespec); -#if RTC_ALARMS > 0 - void rtc_lld_set_alarm(RTCDriver *rtcp, - rtcalarm_t alarm, - const RTCAlarm *alarmspec); - void rtc_lld_get_alarm(RTCDriver *rtcp, - rtcalarm_t alarm, - RTCAlarm *alarmspec); -#endif -#if STM32_RTC_HAS_PERIODIC_WAKEUPS - void rtcSTM32SetPeriodicWakeup(RTCDriver *rtcp, const RTCWakeup *wakeupspec); - void rtcSTM32GetPeriodicWakeup(RTCDriver *rtcp, RTCWakeup *wakeupspec); -#endif /* STM32_RTC_HAS_PERIODIC_WAKEUPS */ -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_RTC */ - -#endif /* _RTC_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/SDIOv1/sdc_lld.c b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/SDIOv1/sdc_lld.c deleted file mode 100644 index 634ed81ccc..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/SDIOv1/sdc_lld.c +++ /dev/null @@ -1,872 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/SDIOv1/sdc_lld.c - * @brief STM32 SDC subsystem low level driver source. - * - * @addtogroup SDC - * @{ - */ - -#include - -#include "hal.h" - -#if HAL_USE_SDC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SDC_SDIO_DMA_STREAM, \ - STM32_SDC_SDIO_DMA_CHN) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief SDCD1 driver identifier.*/ -SDCDriver SDCD1; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -#if STM32_SDC_SDIO_UNALIGNED_SUPPORT -/** - * @brief Buffer for temporary storage during unaligned transfers. - */ -static union { - uint32_t alignment; - uint8_t buf[MMCSD_BLOCK_SIZE]; -} u; -#endif /* STM32_SDC_SDIO_UNALIGNED_SUPPORT */ - -/** - * @brief SDIO default configuration. - */ -static const SDCConfig sdc_default_cfg = { - NULL, - SDC_MODE_4BIT -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Prepares to handle read transaction. - * @details Designed for read special registers from card. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[out] buf pointer to the read buffer - * @param[in] bytes number of bytes to read - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @notapi - */ -static bool sdc_lld_prepare_read_bytes(SDCDriver *sdcp, - uint8_t *buf, uint32_t bytes) { - osalDbgCheck(bytes < 0x1000000); - - sdcp->sdio->DTIMER = STM32_SDC_READ_TIMEOUT; - - /* Checks for errors and waits for the card to be ready for reading.*/ - if (_sdc_wait_for_transfer_state(sdcp)) - return HAL_FAILED; - - /* Prepares the DMA channel for writing.*/ - dmaStreamSetMemory0(sdcp->dma, buf); - dmaStreamSetTransactionSize(sdcp->dma, bytes / sizeof (uint32_t)); - dmaStreamSetMode(sdcp->dma, sdcp->dmamode | STM32_DMA_CR_DIR_P2M); - dmaStreamEnable(sdcp->dma); - - /* Setting up data transfer.*/ - sdcp->sdio->ICR = STM32_SDIO_ICR_ALL_FLAGS; - sdcp->sdio->MASK = SDIO_MASK_DCRCFAILIE | - SDIO_MASK_DTIMEOUTIE | - SDIO_MASK_STBITERRIE | - SDIO_MASK_RXOVERRIE | - SDIO_MASK_DATAENDIE; - sdcp->sdio->DLEN = bytes; - - /* Transaction starts just after DTEN bit setting.*/ - sdcp->sdio->DCTRL = SDIO_DCTRL_DTDIR | - SDIO_DCTRL_DTMODE | /* multibyte data transfer */ - SDIO_DCTRL_DMAEN | - SDIO_DCTRL_DTEN; - - return HAL_SUCCESS; -} - -/** - * @brief Prepares card to handle read transaction. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] startblk first block to read - * @param[in] n number of blocks to read - * @param[in] resp pointer to the response buffer - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @notapi - */ -static bool sdc_lld_prepare_read(SDCDriver *sdcp, uint32_t startblk, - uint32_t n, uint32_t *resp) { - - /* Driver handles data in 512 bytes blocks (just like HC cards). But if we - have not HC card than we must convert address from blocks to bytes.*/ - if (!(sdcp->cardmode & SDC_MODE_HIGH_CAPACITY)) - startblk *= MMCSD_BLOCK_SIZE; - - if (n > 1) { - /* Send read multiple blocks command to card.*/ - if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_READ_MULTIPLE_BLOCK, - startblk, resp) || MMCSD_R1_ERROR(resp[0])) - return HAL_FAILED; - } - else{ - /* Send read single block command.*/ - if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_READ_SINGLE_BLOCK, - startblk, resp) || MMCSD_R1_ERROR(resp[0])) - return HAL_FAILED; - } - - return HAL_SUCCESS; -} - -/** - * @brief Prepares card to handle write transaction. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] startblk first block to read - * @param[in] n number of blocks to write - * @param[in] resp pointer to the response buffer - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @notapi - */ -static bool sdc_lld_prepare_write(SDCDriver *sdcp, uint32_t startblk, - uint32_t n, uint32_t *resp) { - - /* Driver handles data in 512 bytes blocks (just like HC cards). But if we - have not HC card than we must convert address from blocks to bytes.*/ - if (!(sdcp->cardmode & SDC_MODE_HIGH_CAPACITY)) - startblk *= MMCSD_BLOCK_SIZE; - - if (n > 1) { - /* Write multiple blocks command.*/ - if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_WRITE_MULTIPLE_BLOCK, - startblk, resp) || MMCSD_R1_ERROR(resp[0])) - return HAL_FAILED; - } - else{ - /* Write single block command.*/ - if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_WRITE_BLOCK, - startblk, resp) || MMCSD_R1_ERROR(resp[0])) - return HAL_FAILED; - } - - return HAL_SUCCESS; -} - -/** - * @brief Wait end of data transaction and performs finalizations. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] n number of blocks in transaction - * @param[in] resp pointer to the response buffer - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - */ -static bool sdc_lld_wait_transaction_end(SDCDriver *sdcp, uint32_t n, - uint32_t *resp) { - - /* Note the mask is checked before going to sleep because the interrupt - may have occurred before reaching the critical zone.*/ - osalSysLock(); - if (sdcp->sdio->MASK != 0) - osalThreadSuspendS(&sdcp->thread); - if ((sdcp->sdio->STA & SDIO_STA_DATAEND) == 0) { - osalSysUnlock(); - return HAL_FAILED; - } - -#if (defined(STM32F4XX) || defined(STM32F2XX)) - /* Wait until DMA channel enabled to be sure that all data transferred.*/ - while (sdcp->dma->stream->CR & STM32_DMA_CR_EN) - ; - - /* DMA event flags must be manually cleared.*/ - dmaStreamClearInterrupt(sdcp->dma); - - sdcp->sdio->ICR = STM32_SDIO_ICR_ALL_FLAGS; - sdcp->sdio->DCTRL = 0; - osalSysUnlock(); - - /* Wait until interrupt flags to be cleared.*/ - /*while (((DMA2->LISR) >> (sdcp->dma->ishift)) & STM32_DMA_ISR_TCIF) - dmaStreamClearInterrupt(sdcp->dma);*/ -#else - /* Waits for transfer completion at DMA level, then the stream is - disabled and cleared.*/ - dmaWaitCompletion(sdcp->dma); - - sdcp->sdio->ICR = STM32_SDIO_ICR_ALL_FLAGS; - sdcp->sdio->DCTRL = 0; - osalSysUnlock(); -#endif - - /* Finalize transaction.*/ - if (n > 1) - return sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_STOP_TRANSMISSION, 0, resp); - - return HAL_SUCCESS; -} - -/** - * @brief Gets SDC errors. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] sta value of the STA register - * - * @notapi - */ -static void sdc_lld_collect_errors(SDCDriver *sdcp, uint32_t sta) { - uint32_t errors = SDC_NO_ERROR; - - if (sta & SDIO_STA_CCRCFAIL) - errors |= SDC_CMD_CRC_ERROR; - if (sta & SDIO_STA_DCRCFAIL) - errors |= SDC_DATA_CRC_ERROR; - if (sta & SDIO_STA_CTIMEOUT) - errors |= SDC_COMMAND_TIMEOUT; - if (sta & SDIO_STA_DTIMEOUT) - errors |= SDC_DATA_TIMEOUT; - if (sta & SDIO_STA_TXUNDERR) - errors |= SDC_TX_UNDERRUN; - if (sta & SDIO_STA_RXOVERR) - errors |= SDC_RX_OVERRUN; - if (sta & SDIO_STA_STBITERR) - errors |= SDC_STARTBIT_ERROR; - - sdcp->errors |= errors; -} - -/** - * @brief Performs clean transaction stopping in case of errors. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] n number of blocks in transaction - * @param[in] resp pointer to the response buffer - * - * @notapi - */ -static void sdc_lld_error_cleanup(SDCDriver *sdcp, - uint32_t n, - uint32_t *resp) { - uint32_t sta = sdcp->sdio->STA; - - dmaStreamClearInterrupt(sdcp->dma); - dmaStreamDisable(sdcp->dma); - sdcp->sdio->ICR = STM32_SDIO_ICR_ALL_FLAGS; - sdcp->sdio->MASK = 0; - sdcp->sdio->DCTRL = 0; - sdc_lld_collect_errors(sdcp, sta); - if (n > 1) - sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_STOP_TRANSMISSION, 0, resp); -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if !defined(STM32_SDIO_HANDLER) -#error "STM32_SDIO_HANDLER not defined" -#endif -/** - * @brief SDIO IRQ handler. - * @details It just wakes transaction thread. All error handling performs in - * that thread. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_SDIO_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - osalSysLockFromISR(); - - /* Disables the source but the status flags are not reset because the - read/write functions needs to check them.*/ - SDIO->MASK = 0; - - osalThreadResumeI(&SDCD1.thread, MSG_OK); - - osalSysUnlockFromISR(); - - OSAL_IRQ_EPILOGUE(); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level SDC driver initialization. - * - * @notapi - */ -void sdc_lld_init(void) { - - sdcObjectInit(&SDCD1); - SDCD1.thread = NULL; - SDCD1.dma = STM32_DMA_STREAM(STM32_SDC_SDIO_DMA_STREAM); - SDCD1.sdio = SDIO; -} - -/** - * @brief Configures and activates the SDC peripheral. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @notapi - */ -void sdc_lld_start(SDCDriver *sdcp) { - - /* Checking configuration, using a default if NULL has been passed.*/ - if (sdcp->config == NULL) { - sdcp->config = &sdc_default_cfg; - } - - sdcp->dmamode = STM32_DMA_CR_CHSEL(DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SDC_SDIO_DMA_PRIORITY) | - STM32_DMA_CR_PSIZE_WORD | - STM32_DMA_CR_MSIZE_WORD | - STM32_DMA_CR_MINC; - -#if (defined(STM32F4XX) || defined(STM32F2XX)) - sdcp->dmamode |= STM32_DMA_CR_PFCTRL | - STM32_DMA_CR_PBURST_INCR4 | - STM32_DMA_CR_MBURST_INCR4; -#endif - - if (sdcp->state == BLK_STOP) { - /* Note, the DMA must be enabled before the IRQs.*/ - bool b; - b = dmaStreamAllocate(sdcp->dma, STM32_SDC_SDIO_IRQ_PRIORITY, NULL, NULL); - osalDbgAssert(!b, "stream already allocated"); - dmaStreamSetPeripheral(sdcp->dma, &sdcp->sdio->FIFO); -#if (defined(STM32F4XX) || defined(STM32F2XX)) - dmaStreamSetFIFO(sdcp->dma, STM32_DMA_FCR_DMDIS | STM32_DMA_FCR_FTH_FULL); -#endif - nvicEnableVector(STM32_SDIO_NUMBER, STM32_SDC_SDIO_IRQ_PRIORITY); - rccEnableSDIO(FALSE); - } - - /* Configuration, card clock is initially stopped.*/ - sdcp->sdio->POWER = 0; - sdcp->sdio->CLKCR = 0; - sdcp->sdio->DCTRL = 0; - sdcp->sdio->DTIMER = 0; -} - -/** - * @brief Deactivates the SDC peripheral. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @notapi - */ -void sdc_lld_stop(SDCDriver *sdcp) { - - if (sdcp->state != BLK_STOP) { - - /* SDIO deactivation.*/ - sdcp->sdio->POWER = 0; - sdcp->sdio->CLKCR = 0; - sdcp->sdio->DCTRL = 0; - sdcp->sdio->DTIMER = 0; - - /* Clock deactivation.*/ - nvicDisableVector(STM32_SDIO_NUMBER); - dmaStreamRelease(sdcp->dma); - rccDisableSDIO(FALSE); - } -} - -/** - * @brief Starts the SDIO clock and sets it to init mode (400kHz or less). - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @notapi - */ -void sdc_lld_start_clk(SDCDriver *sdcp) { - - /* Initial clock setting: 400kHz, 1bit mode.*/ - sdcp->sdio->CLKCR = STM32_SDIO_DIV_LS; - sdcp->sdio->POWER |= SDIO_POWER_PWRCTRL_0 | SDIO_POWER_PWRCTRL_1; - sdcp->sdio->CLKCR |= SDIO_CLKCR_CLKEN; - - /* Clock activation delay.*/ - osalThreadSleep(OSAL_MS2ST(STM32_SDC_CLOCK_ACTIVATION_DELAY)); -} - -/** - * @brief Sets the SDIO clock to data mode (25MHz or less). - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] clk the clock mode - * - * @notapi - */ -void sdc_lld_set_data_clk(SDCDriver *sdcp, sdcbusclk_t clk) { -#if 0 - if (SDC_CLK_50MHz == clk) { - sdcp->sdio->CLKCR = (sdcp->sdio->CLKCR & 0xFFFFFF00U) | STM32_SDIO_DIV_HS - | SDIO_CLKCR_BYPASS; - } - else - sdcp->sdio->CLKCR = (sdcp->sdio->CLKCR & 0xFFFFFF00U) | STM32_SDIO_DIV_HS; -#else - (void)clk; - - sdcp->sdio->CLKCR = (sdcp->sdio->CLKCR & 0xFFFFFF00U) | STM32_SDIO_DIV_HS; -#endif -} - -/** - * @brief Stops the SDIO clock. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @notapi - */ -void sdc_lld_stop_clk(SDCDriver *sdcp) { - - sdcp->sdio->CLKCR = 0; - sdcp->sdio->POWER = 0; -} - -/** - * @brief Switches the bus to 4 bits mode. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] mode bus mode - * - * @notapi - */ -void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode) { - uint32_t clk = sdcp->sdio->CLKCR & ~SDIO_CLKCR_WIDBUS; - - switch (mode) { - case SDC_MODE_1BIT: - sdcp->sdio->CLKCR = clk; - break; - case SDC_MODE_4BIT: - sdcp->sdio->CLKCR = clk | SDIO_CLKCR_WIDBUS_0; - break; - case SDC_MODE_8BIT: - sdcp->sdio->CLKCR = clk | SDIO_CLKCR_WIDBUS_1; - break; - } -} - -/** - * @brief Sends an SDIO command with no response expected. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] cmd card command - * @param[in] arg command argument - * - * @notapi - */ -void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg) { - - sdcp->sdio->ARG = arg; - sdcp->sdio->CMD = (uint32_t)cmd | SDIO_CMD_CPSMEN; - while ((sdcp->sdio->STA & SDIO_STA_CMDSENT) == 0) - ; - sdcp->sdio->ICR = SDIO_ICR_CMDSENTC; -} - -/** - * @brief Sends an SDIO command with a short response expected. - * @note The CRC is not verified. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] cmd card command - * @param[in] arg command argument - * @param[out] resp pointer to the response buffer (one word) - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @notapi - */ -bool sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, - uint32_t *resp) { - uint32_t sta; - - sdcp->sdio->ARG = arg; - sdcp->sdio->CMD = (uint32_t)cmd | SDIO_CMD_WAITRESP_0 | SDIO_CMD_CPSMEN; - while (((sta = sdcp->sdio->STA) & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT | - SDIO_STA_CCRCFAIL)) == 0) - ; - sdcp->sdio->ICR = sta & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT | - SDIO_STA_CCRCFAIL); - if ((sta & (SDIO_STA_CTIMEOUT)) != 0) { - sdc_lld_collect_errors(sdcp, sta); - return HAL_FAILED; - } - *resp = sdcp->sdio->RESP1; - return HAL_SUCCESS; -} - -/** - * @brief Sends an SDIO command with a short response expected and CRC. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] cmd card command - * @param[in] arg command argument - * @param[out] resp pointer to the response buffer (one word) - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @notapi - */ -bool sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, - uint32_t *resp) { - uint32_t sta; - - sdcp->sdio->ARG = arg; - sdcp->sdio->CMD = (uint32_t)cmd | SDIO_CMD_WAITRESP_0 | SDIO_CMD_CPSMEN; - while (((sta = sdcp->sdio->STA) & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT | - SDIO_STA_CCRCFAIL)) == 0) - ; - sdcp->sdio->ICR = sta & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT | SDIO_STA_CCRCFAIL); - if ((sta & (SDIO_STA_CTIMEOUT | SDIO_STA_CCRCFAIL)) != 0) { - sdc_lld_collect_errors(sdcp, sta); - return HAL_FAILED; - } - *resp = sdcp->sdio->RESP1; - return HAL_SUCCESS; -} - -/** - * @brief Sends an SDIO command with a long response expected and CRC. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] cmd card command - * @param[in] arg command argument - * @param[out] resp pointer to the response buffer (four words) - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @notapi - */ -bool sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, - uint32_t *resp) { - uint32_t sta; - - (void)sdcp; - - sdcp->sdio->ARG = arg; - sdcp->sdio->CMD = (uint32_t)cmd | SDIO_CMD_WAITRESP_0 | SDIO_CMD_WAITRESP_1 | - SDIO_CMD_CPSMEN; - while (((sta = sdcp->sdio->STA) & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT | - SDIO_STA_CCRCFAIL)) == 0) - ; - sdcp->sdio->ICR = sta & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT | - SDIO_STA_CCRCFAIL); - if ((sta & (STM32_SDIO_STA_ERROR_MASK)) != 0) { - sdc_lld_collect_errors(sdcp, sta); - return HAL_FAILED; - } - /* Save bytes in reverse order because MSB in response comes first.*/ - *resp++ = sdcp->sdio->RESP4; - *resp++ = sdcp->sdio->RESP3; - *resp++ = sdcp->sdio->RESP2; - *resp = sdcp->sdio->RESP1; - return HAL_SUCCESS; -} - -/** - * @brief Reads special registers using data bus. - * @details Needs only during card detection procedure. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[out] buf pointer to the read buffer - * @param[in] bytes number of bytes to read - * @param[in] cmd card command - * @param[in] arg argument for command - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @notapi - */ -bool sdc_lld_read_special(SDCDriver *sdcp, uint8_t *buf, size_t bytes, - uint8_t cmd, uint32_t arg) { - uint32_t resp[1]; - - if(sdc_lld_prepare_read_bytes(sdcp, buf, bytes)) - goto error; - - if (sdc_lld_send_cmd_short_crc(sdcp, cmd, arg, resp) - || MMCSD_R1_ERROR(resp[0])) - goto error; - - if (sdc_lld_wait_transaction_end(sdcp, 1, resp)) - goto error; - - return HAL_SUCCESS; - -error: - sdc_lld_error_cleanup(sdcp, 1, resp); - return HAL_FAILED; -} - -/** - * @brief Reads one or more blocks. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] startblk first block to read - * @param[out] buf pointer to the read buffer - * @param[in] blocks number of blocks to read - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @notapi - */ -bool sdc_lld_read_aligned(SDCDriver *sdcp, uint32_t startblk, - uint8_t *buf, uint32_t blocks) { - uint32_t resp[1]; - - osalDbgCheck(blocks < 0x1000000 / MMCSD_BLOCK_SIZE); - - sdcp->sdio->DTIMER = STM32_SDC_READ_TIMEOUT; - - /* Checks for errors and waits for the card to be ready for reading.*/ - if (_sdc_wait_for_transfer_state(sdcp)) - return HAL_FAILED; - - /* Prepares the DMA channel for writing.*/ - dmaStreamSetMemory0(sdcp->dma, buf); - dmaStreamSetTransactionSize(sdcp->dma, - (blocks * MMCSD_BLOCK_SIZE) / sizeof (uint32_t)); - dmaStreamSetMode(sdcp->dma, sdcp->dmamode | STM32_DMA_CR_DIR_P2M); - dmaStreamEnable(sdcp->dma); - - /* Setting up data transfer.*/ - sdcp->sdio->ICR = STM32_SDIO_ICR_ALL_FLAGS; - sdcp->sdio->MASK = SDIO_MASK_DCRCFAILIE | - SDIO_MASK_DTIMEOUTIE | - SDIO_MASK_STBITERRIE | - SDIO_MASK_RXOVERRIE | - SDIO_MASK_DATAENDIE; - sdcp->sdio->DLEN = blocks * MMCSD_BLOCK_SIZE; - - /* Transaction starts just after DTEN bit setting.*/ - sdcp->sdio->DCTRL = SDIO_DCTRL_DTDIR | - SDIO_DCTRL_DBLOCKSIZE_3 | - SDIO_DCTRL_DBLOCKSIZE_0 | - SDIO_DCTRL_DMAEN | - SDIO_DCTRL_DTEN; - - if (sdc_lld_prepare_read(sdcp, startblk, blocks, resp) == TRUE) - goto error; - - if (sdc_lld_wait_transaction_end(sdcp, blocks, resp) == TRUE) - goto error; - - return HAL_SUCCESS; - -error: - sdc_lld_error_cleanup(sdcp, blocks, resp); - return HAL_FAILED; -} - -/** - * @brief Writes one or more blocks. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] startblk first block to write - * @param[out] buf pointer to the write buffer - * @param[in] n number of blocks to write - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @notapi - */ -bool sdc_lld_write_aligned(SDCDriver *sdcp, uint32_t startblk, - const uint8_t *buf, uint32_t blocks) { - uint32_t resp[1]; - - osalDbgCheck(blocks < 0x1000000 / MMCSD_BLOCK_SIZE); - - sdcp->sdio->DTIMER = STM32_SDC_WRITE_TIMEOUT; - - /* Checks for errors and waits for the card to be ready for writing.*/ - if (_sdc_wait_for_transfer_state(sdcp)) - return HAL_FAILED; - - /* Prepares the DMA channel for writing.*/ - dmaStreamSetMemory0(sdcp->dma, buf); - dmaStreamSetTransactionSize(sdcp->dma, - (blocks * MMCSD_BLOCK_SIZE) / sizeof (uint32_t)); - dmaStreamSetMode(sdcp->dma, sdcp->dmamode | STM32_DMA_CR_DIR_M2P); - dmaStreamEnable(sdcp->dma); - - /* Setting up data transfer.*/ - sdcp->sdio->ICR = STM32_SDIO_ICR_ALL_FLAGS; - sdcp->sdio->MASK = SDIO_MASK_DCRCFAILIE | - SDIO_MASK_DTIMEOUTIE | - SDIO_MASK_STBITERRIE | - SDIO_MASK_TXUNDERRIE | - SDIO_MASK_DATAENDIE; - sdcp->sdio->DLEN = blocks * MMCSD_BLOCK_SIZE; - - /* Talk to card what we want from it.*/ - if (sdc_lld_prepare_write(sdcp, startblk, blocks, resp) == TRUE) - goto error; - - /* Transaction starts just after DTEN bit setting.*/ - sdcp->sdio->DCTRL = SDIO_DCTRL_DBLOCKSIZE_3 | - SDIO_DCTRL_DBLOCKSIZE_0 | - SDIO_DCTRL_DMAEN | - SDIO_DCTRL_DTEN; - - if (sdc_lld_wait_transaction_end(sdcp, blocks, resp) == TRUE) - goto error; - - return HAL_SUCCESS; - -error: - sdc_lld_error_cleanup(sdcp, blocks, resp); - return HAL_FAILED; -} - -/** - * @brief Reads one or more blocks. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] startblk first block to read - * @param[out] buf pointer to the read buffer - * @param[in] blocks number of blocks to read - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @notapi - */ -bool sdc_lld_read(SDCDriver *sdcp, uint32_t startblk, - uint8_t *buf, uint32_t blocks) { - -#if STM32_SDC_SDIO_UNALIGNED_SUPPORT - if (((unsigned)buf & 3) != 0) { - uint32_t i; - for (i = 0; i < blocks; i++) { - if (sdc_lld_read_aligned(sdcp, startblk, u.buf, 1)) - return HAL_FAILED; - memcpy(buf, u.buf, MMCSD_BLOCK_SIZE); - buf += MMCSD_BLOCK_SIZE; - startblk++; - } - return HAL_SUCCESS; - } -#endif /* STM32_SDC_SDIO_UNALIGNED_SUPPORT */ - return sdc_lld_read_aligned(sdcp, startblk, buf, blocks); -} - -/** - * @brief Writes one or more blocks. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] startblk first block to write - * @param[out] buf pointer to the write buffer - * @param[in] blocks number of blocks to write - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @notapi - */ -bool sdc_lld_write(SDCDriver *sdcp, uint32_t startblk, - const uint8_t *buf, uint32_t blocks) { - -#if STM32_SDC_SDIO_UNALIGNED_SUPPORT - if (((unsigned)buf & 3) != 0) { - uint32_t i; - for (i = 0; i < blocks; i++) { - memcpy(u.buf, buf, MMCSD_BLOCK_SIZE); - buf += MMCSD_BLOCK_SIZE; - if (sdc_lld_write_aligned(sdcp, startblk, u.buf, 1)) - return HAL_FAILED; - startblk++; - } - return HAL_SUCCESS; - } -#endif /* STM32_SDC_SDIO_UNALIGNED_SUPPORT */ - return sdc_lld_write_aligned(sdcp, startblk, buf, blocks); -} - -/** - * @brief Waits for card idle condition. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @return The operation status. - * @retval HAL_SUCCESS the operation succeeded. - * @retval HAL_FAILED the operation failed. - * - * @api - */ -bool sdc_lld_sync(SDCDriver *sdcp) { - - /* TODO: Implement.*/ - (void)sdcp; - return HAL_SUCCESS; -} - -#endif /* HAL_USE_SDC */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/SDIOv1/sdc_lld.h b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/SDIOv1/sdc_lld.h deleted file mode 100644 index 87c5d807e9..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/SDIOv1/sdc_lld.h +++ /dev/null @@ -1,350 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/SDIOv1/sdc_lld.h - * @brief STM32 SDC subsystem low level driver header. - * - * @addtogroup SDC - * @{ - */ - -#ifndef _SDC_LLD_H_ -#define _SDC_LLD_H_ - -#if HAL_USE_SDC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/* - * The following definitions are missing from some implementations, fixing - * as zeroed masks. - */ -#if !defined(SDIO_STA_STBITERR) -#define SDIO_STA_STBITERR 0 -#endif - -#if !defined(SDIO_ICR_STBITERRC) -#define SDIO_ICR_STBITERRC 0 -#endif - -#if !defined(SDIO_ICR_CEATAENDC) -#define SDIO_ICR_CEATAENDC 0 -#endif - -#if !defined(SDIO_MASK_STBITERRIE) -#define SDIO_MASK_STBITERRIE 0 -#endif - -/** - * @brief Value to clear all interrupts flag at once. - */ -#define STM32_SDIO_ICR_ALL_FLAGS (SDIO_ICR_CCRCFAILC | SDIO_ICR_DCRCFAILC | \ - SDIO_ICR_CTIMEOUTC | SDIO_ICR_DTIMEOUTC | \ - SDIO_ICR_TXUNDERRC | SDIO_ICR_RXOVERRC | \ - SDIO_ICR_CMDRENDC | SDIO_ICR_CMDSENTC | \ - SDIO_ICR_DATAENDC | SDIO_ICR_STBITERRC | \ - SDIO_ICR_DBCKENDC | SDIO_ICR_SDIOITC | \ - SDIO_ICR_CEATAENDC) - -/** - * @brief Mask of error flags in STA register. - */ -#define STM32_SDIO_STA_ERROR_MASK (SDIO_STA_CCRCFAIL | SDIO_STA_DCRCFAIL | \ - SDIO_STA_CTIMEOUT | SDIO_STA_DTIMEOUT | \ - SDIO_STA_TXUNDERR | SDIO_STA_RXOVERR) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief SDIO DMA priority (0..3|lowest..highest). - */ -#if !defined(STM32_SDC_SDIO_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SDC_SDIO_DMA_PRIORITY 3 -#endif - -/** - * @brief SDIO interrupt priority level setting. - */ -#if !defined(STM32_SDC_SDIO_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SDC_SDIO_IRQ_PRIORITY 9 -#endif - -/** - * @brief Write timeout in milliseconds. - */ -#if !defined(STM32_SDC_WRITE_TIMEOUT_MS) || defined(__DOXYGEN__) -#define STM32_SDC_WRITE_TIMEOUT_MS 250 -#endif - -/** - * @brief Read timeout in milliseconds. - */ -#if !defined(STM32_SDC_READ_TIMEOUT_MS) || defined(__DOXYGEN__) -#define STM32_SDC_READ_TIMEOUT_MS 25 -#endif - -/** - * @brief Card clock activation delay in milliseconds. - */ -#if !defined(STM32_SDC_CLOCK_ACTIVATION_DELAY) || defined(__DOXYGEN__) -#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 -#endif - -/** - * @brief Support for unaligned transfers. - * @note Unaligned transfers are much slower. - */ -#if !defined(STM32_SDC_SDIO_UNALIGNED_SUPPORT) || defined(__DOXYGEN__) -#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !STM32_HAS_SDIO -#error "SDIO not present in the selected device" -#endif - -#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SDC_SDIO_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SDIO" -#endif - -#if !STM32_DMA_IS_VALID_PRIORITY(STM32_SDC_SDIO_DMA_PRIORITY) -#error "Invalid DMA priority assigned to SDIO" -#endif - -/* The following checks are only required when there is a DMA able to - reassign streams to different channels.*/ -#if STM32_ADVANCED_DMA -/* Check on the presence of the DMA streams settings in mcuconf.h.*/ -#if !defined(STM32_SDC_SDIO_DMA_STREAM) -#error "SDIO DMA streams not defined" -#endif - -/* Check on the validity of the assigned DMA channels.*/ -#if !STM32_DMA_IS_VALID_ID(STM32_SDC_SDIO_DMA_STREAM, STM32_SDC_SDIO_DMA_MSK) -#error "invalid DMA stream associated to SDIO" -#endif -#endif /* STM32_ADVANCED_DMA */ - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif - -/* - * SDIO clock divider. - */ -#if (defined(STM32F4XX) || defined(STM32F2XX)) -#define STM32_SDIO_DIV_HS 0 -#define STM32_SDIO_DIV_LS 120 - -#elif STM32_HCLK > 48000000 -#define STM32_SDIO_DIV_HS 1 -#define STM32_SDIO_DIV_LS 178 -#else - -#define STM32_SDIO_DIV_HS 0 -#define STM32_SDIO_DIV_LS 118 -#endif - -/** - * @brief SDIO data timeouts in SDIO clock cycles. - */ -#if (defined(STM32F4XX) || defined(STM32F2XX)) -#if !STM32_CLOCK48_REQUIRED -#error "SDIO requires STM32_CLOCK48_REQUIRED to be enabled" -#endif - -#if STM32_PLL48CLK != 48000000 -#error "invalid STM32_PLL48CLK clock value" -#endif - -#define STM32_SDC_WRITE_TIMEOUT \ - (((STM32_PLL48CLK / (STM32_SDIO_DIV_HS + 2)) / 1000) * \ - STM32_SDC_WRITE_TIMEOUT_MS) -#define STM32_SDC_READ_TIMEOUT \ - (((STM32_PLL48CLK / (STM32_SDIO_DIV_HS + 2)) / 1000) * \ - STM32_SDC_READ_TIMEOUT_MS) - -#else /* !(defined(STM32F4XX) || defined(STM32F2XX)) */ - -#define STM32_SDC_WRITE_TIMEOUT \ - (((STM32_HCLK / (STM32_SDIO_DIV_HS + 2)) / 1000) * \ - STM32_SDC_WRITE_TIMEOUT_MS) -#define STM32_SDC_READ_TIMEOUT \ - (((STM32_HCLK / (STM32_SDIO_DIV_HS + 2)) / 1000) * \ - STM32_SDC_READ_TIMEOUT_MS) - -#endif /* !(defined(STM32F4XX) || defined(STM32F2XX)) */ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of card flags. - */ -typedef uint32_t sdcmode_t; - -/** - * @brief SDC Driver condition flags type. - */ -typedef uint32_t sdcflags_t; - -/** - * @brief Type of a structure representing an SDC driver. - */ -typedef struct SDCDriver SDCDriver; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief Working area for memory consuming operations. - * @note Buffer must be word aligned and big enough to store 512 bytes. - * @note It is mandatory for detecting MMC cards bigger than 2GB else it - * can be @p NULL. SD cards do NOT need it. - * @note Memory pointed by this buffer is only used by @p sdcConnect(), - * afterward it can be reused for other purposes. - */ - uint8_t *scratchpad; - /** - * @brief Bus width. - */ - sdcbusmode_t bus_width; - /* End of the mandatory fields.*/ -} SDCConfig; - -/** - * @brief @p SDCDriver specific methods. - */ -#define _sdc_driver_methods \ - _mmcsd_block_device_methods - -/** - * @extends MMCSDBlockDeviceVMT - * - * @brief @p SDCDriver virtual methods table. - */ -struct SDCDriverVMT { - _sdc_driver_methods -}; - -/** - * @brief Structure representing an SDC driver. - */ -struct SDCDriver { - /** - * @brief Virtual Methods Table. - */ - const struct SDCDriverVMT *vmt; - _mmcsd_block_device_data - /** - * @brief Current configuration data. - */ - const SDCConfig *config; - /** - * @brief Various flags regarding the mounted card. - */ - sdcmode_t cardmode; - /** - * @brief Errors flags. - */ - sdcflags_t errors; - /** - * @brief Card RCA. - */ - uint32_t rca; - /* End of the mandatory fields.*/ - /** - * @brief Thread waiting for I/O completion IRQ. - */ - thread_reference_t thread; - /** - * @brief DMA mode bit mask. - */ - uint32_t dmamode; - /** - * @brief Transmit DMA channel. - */ - const stm32_dma_stream_t *dma; - /** - * @brief Pointer to the SDIO registers block. - * @note Needed for debugging aid. - */ - SDIO_TypeDef *sdio; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -extern SDCDriver SDCD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void sdc_lld_init(void); - void sdc_lld_start(SDCDriver *sdcp); - void sdc_lld_stop(SDCDriver *sdcp); - void sdc_lld_start_clk(SDCDriver *sdcp); - void sdc_lld_set_data_clk(SDCDriver *sdcp, sdcbusclk_t clk); - void sdc_lld_stop_clk(SDCDriver *sdcp); - void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode); - void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg); - bool sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, - uint32_t *resp); - bool sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, - uint32_t *resp); - bool sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, - uint32_t *resp); - bool sdc_lld_read_special(SDCDriver *sdcp, uint8_t *buf, size_t bytes, - uint8_t cmd, uint32_t argument); - bool sdc_lld_read(SDCDriver *sdcp, uint32_t startblk, - uint8_t *buf, uint32_t blocks); - bool sdc_lld_write(SDCDriver *sdcp, uint32_t startblk, - const uint8_t *buf, uint32_t blocks); - bool sdc_lld_sync(SDCDriver *sdcp); - bool sdc_lld_is_card_inserted(SDCDriver *sdcp); - bool sdc_lld_is_write_protected(SDCDriver *sdcp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_SDC */ - -#endif /* _SDC_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/SDMMCv1/sdc_lld.c b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/SDMMCv1/sdc_lld.c deleted file mode 100644 index 8053da6051..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/SDMMCv1/sdc_lld.c +++ /dev/null @@ -1,884 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/SDMMCv1/sdc_lld.c - * @brief STM32 SDC subsystem low level driver source. - * - * @addtogroup SDC - * @{ - */ - -#include - -#include "hal.h" - -#if HAL_USE_SDC || defined(__DOXYGEN__) - -#if !defined(STM32_SDMMCCLK) -#error "STM32_SDMMCCLK not defined" -#endif - -#if STM32_SDMMCCLK > 48000000 -#error "STM32_SDMMCCLK exceeding 48MHz" -#endif - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define SDMMC_ICR_ALL_FLAGS \ - (SDMMC_ICR_CCRCFAILC | SDMMC_ICR_DCRCFAILC | \ - SDMMC_ICR_CTIMEOUTC | SDMMC_ICR_DTIMEOUTC | \ - SDMMC_ICR_TXUNDERRC | SDMMC_ICR_RXOVERRC | \ - SDMMC_ICR_CMDRENDC | SDMMC_ICR_CMDSENTC | \ - SDMMC_ICR_DATAENDC | SDMMC_ICR_DBCKENDC | \ - SDMMC_ICR_SDIOITC) - -#define SDMMC_STA_ERROR_MASK \ - (SDMMC_STA_CCRCFAIL | SDMMC_STA_DCRCFAIL | \ - SDMMC_STA_CTIMEOUT | SDMMC_STA_DTIMEOUT | \ - SDMMC_STA_TXUNDERR | SDMMC_STA_RXOVERR) - -#define SDMMC_CLKDIV_HS (2 - 2) -#define SDMMC_CLKDIV_LS (120 - 2) - -#define SDMMC_WRITE_TIMEOUT \ - (((STM32_SDMMCCLK / (SDMMC_CLKDIV_HS + 2)) / 1000) * \ - STM32_SDC_SDMMC_WRITE_TIMEOUT) -#define SDMMC_READ_TIMEOUT \ - (((STM32_SDMMCCLK / (SDMMC_CLKDIV_HS + 2)) / 1000) * \ - STM32_SDC_SDMMC_READ_TIMEOUT) - -#define DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SDC_SDMMC1_DMA_STREAM, \ - STM32_SDC_SDMMC1_DMA_CHN) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief SDCD1 driver identifier.*/ -SDCDriver SDCD1; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -#if STM32_SDC_SDMMC_UNALIGNED_SUPPORT -/** - * @brief Buffer for temporary storage during unaligned transfers. - */ -static union { - uint32_t alignment; - uint8_t buf[MMCSD_BLOCK_SIZE]; -} u; -#endif /* STM32_SDC_SDMMC_UNALIGNED_SUPPORT */ - -/** - * @brief SDIO default configuration. - */ -static const SDCConfig sdc_default_cfg = { - NULL, - SDC_MODE_4BIT -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Prepares to handle read transaction. - * @details Designed for read special registers from card. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[out] buf pointer to the read buffer - * @param[in] bytes number of bytes to read - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @notapi - */ -static bool sdc_lld_prepare_read_bytes(SDCDriver *sdcp, - uint8_t *buf, uint32_t bytes) { - osalDbgCheck(bytes < 0x1000000); - - sdcp->sdmmc->DTIMER = SDMMC_READ_TIMEOUT; - - /* Checks for errors and waits for the card to be ready for reading.*/ - if (_sdc_wait_for_transfer_state(sdcp)) - return HAL_FAILED; - - /* Prepares the DMA channel for writing.*/ - dmaStreamSetMemory0(sdcp->dma, buf); - dmaStreamSetTransactionSize(sdcp->dma, bytes / sizeof (uint32_t)); - dmaStreamSetMode(sdcp->dma, sdcp->dmamode | STM32_DMA_CR_DIR_P2M); - dmaStreamEnable(sdcp->dma); - - /* Setting up data transfer.*/ - sdcp->sdmmc->ICR = SDMMC_ICR_ALL_FLAGS; - sdcp->sdmmc->MASK = SDMMC_MASK_DCRCFAILIE | - SDMMC_MASK_DTIMEOUTIE | - SDMMC_MASK_RXOVERRIE | - SDMMC_MASK_DATAENDIE; - sdcp->sdmmc->DLEN = bytes; - - /* Transaction starts just after DTEN bit setting.*/ - sdcp->sdmmc->DCTRL = SDMMC_DCTRL_DTDIR | - SDMMC_DCTRL_DTMODE | /* multibyte data transfer */ - SDMMC_DCTRL_DMAEN | - SDMMC_DCTRL_DTEN; - - return HAL_SUCCESS; -} - -/** - * @brief Prepares card to handle read transaction. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] startblk first block to read - * @param[in] n number of blocks to read - * @param[in] resp pointer to the response buffer - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @notapi - */ -static bool sdc_lld_prepare_read(SDCDriver *sdcp, uint32_t startblk, - uint32_t n, uint32_t *resp) { - - /* Driver handles data in 512 bytes blocks (just like HC cards). But if we - have not HC card than we must convert address from blocks to bytes.*/ - if (!(sdcp->cardmode & SDC_MODE_HIGH_CAPACITY)) - startblk *= MMCSD_BLOCK_SIZE; - - if (n > 1) { - /* Send read multiple blocks command to card.*/ - if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_READ_MULTIPLE_BLOCK, - startblk, resp) || MMCSD_R1_ERROR(resp[0])) - return HAL_FAILED; - } - else{ - /* Send read single block command.*/ - if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_READ_SINGLE_BLOCK, - startblk, resp) || MMCSD_R1_ERROR(resp[0])) - return HAL_FAILED; - } - - return HAL_SUCCESS; -} - -/** - * @brief Prepares card to handle write transaction. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] startblk first block to read - * @param[in] n number of blocks to write - * @param[in] resp pointer to the response buffer - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @notapi - */ -static bool sdc_lld_prepare_write(SDCDriver *sdcp, uint32_t startblk, - uint32_t n, uint32_t *resp) { - - /* Driver handles data in 512 bytes blocks (just like HC cards). But if we - have not HC card than we must convert address from blocks to bytes.*/ - if (!(sdcp->cardmode & SDC_MODE_HIGH_CAPACITY)) - startblk *= MMCSD_BLOCK_SIZE; - - if (n > 1) { - /* Write multiple blocks command.*/ - if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_WRITE_MULTIPLE_BLOCK, - startblk, resp) || MMCSD_R1_ERROR(resp[0])) - return HAL_FAILED; - } - else{ - /* Write single block command.*/ - if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_WRITE_BLOCK, - startblk, resp) || MMCSD_R1_ERROR(resp[0])) - return HAL_FAILED; - } - - return HAL_SUCCESS; -} - -/** - * @brief Wait end of data transaction and performs finalizations. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] n number of blocks in transaction - * @param[in] resp pointer to the response buffer - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - */ -static bool sdc_lld_wait_transaction_end(SDCDriver *sdcp, uint32_t n, - uint32_t *resp) { - - /* Note the mask is checked before going to sleep because the interrupt - may have occurred before reaching the critical zone.*/ - osalSysLock(); - if (sdcp->sdmmc->MASK != 0) - osalThreadSuspendS(&sdcp->thread); - if ((sdcp->sdmmc->STA & SDMMC_STA_DATAEND) == 0) { - osalSysUnlock(); - return HAL_FAILED; - } - - /* Waits for transfer completion at DMA level, then the stream is - disabled and cleared.*/ - dmaWaitCompletion(sdcp->dma); - - sdcp->sdmmc->ICR = SDMMC_ICR_ALL_FLAGS; - sdcp->sdmmc->DCTRL = 0; - osalSysUnlock(); - - /* Finalize transaction.*/ - if (n > 1) - return sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_STOP_TRANSMISSION, 0, resp); - - return HAL_SUCCESS; -} - -/** - * @brief Gets SDC errors. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] sta value of the STA register - * - * @notapi - */ -static void sdc_lld_collect_errors(SDCDriver *sdcp, uint32_t sta) { - uint32_t errors = SDC_NO_ERROR; - - if (sta & SDMMC_STA_CCRCFAIL) - errors |= SDC_CMD_CRC_ERROR; - if (sta & SDMMC_STA_DCRCFAIL) - errors |= SDC_DATA_CRC_ERROR; - if (sta & SDMMC_STA_CTIMEOUT) - errors |= SDC_COMMAND_TIMEOUT; - if (sta & SDMMC_STA_DTIMEOUT) - errors |= SDC_DATA_TIMEOUT; - if (sta & SDMMC_STA_TXUNDERR) - errors |= SDC_TX_UNDERRUN; - if (sta & SDMMC_STA_RXOVERR) - errors |= SDC_RX_OVERRUN; -/* if (sta & SDMMC_STA_STBITERR) - errors |= SDC_STARTBIT_ERROR;*/ - - sdcp->errors |= errors; -} - -/** - * @brief Performs clean transaction stopping in case of errors. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] n number of blocks in transaction - * @param[in] resp pointer to the response buffer - * - * @notapi - */ -static void sdc_lld_error_cleanup(SDCDriver *sdcp, - uint32_t n, - uint32_t *resp) { - uint32_t sta = sdcp->sdmmc->STA; - - dmaStreamDisable(sdcp->dma); - sdcp->sdmmc->ICR = SDMMC_ICR_ALL_FLAGS; - sdcp->sdmmc->MASK = 0; - sdcp->sdmmc->DCTRL = 0; - sdc_lld_collect_errors(sdcp, sta); - - if (n > 1) - sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_STOP_TRANSMISSION, 0, resp); -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if !defined(STM32_SDMMC1_HANDLER) -#error "STM32_SDMMC1_HANDLER not defined" -#endif - -/** - * @brief SDIO IRQ handler. - * @details It just wakes transaction thread. All error handling performs in - * that thread. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_SDMMC1_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - osalSysLockFromISR(); - - /* Disables the source but the status flags are not reset because the - read/write functions needs to check them.*/ - SDMMC1->MASK = 0; - - osalThreadResumeI(&SDCD1.thread, MSG_OK); - - osalSysUnlockFromISR(); - - OSAL_IRQ_EPILOGUE(); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level SDC driver initialization. - * - * @notapi - */ -void sdc_lld_init(void) { - - sdcObjectInit(&SDCD1); - SDCD1.thread = NULL; - SDCD1.dma = STM32_DMA_STREAM(STM32_SDC_SDMMC1_DMA_STREAM); - SDCD1.sdmmc = SDMMC1; -} - -/** - * @brief Configures and activates the SDC peripheral. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @notapi - */ -void sdc_lld_start(SDCDriver *sdcp) { - - /* Checking configuration, using a default if NULL has been passed.*/ - if (sdcp->config == NULL) { - sdcp->config = &sdc_default_cfg; - } - - sdcp->dmamode = STM32_DMA_CR_CHSEL(DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SDC_SDMMC1_DMA_PRIORITY) | - STM32_DMA_CR_PSIZE_WORD | - STM32_DMA_CR_MSIZE_WORD | - STM32_DMA_CR_MINC; - -#if STM32_DMA_ADVANCED - sdcp->dmamode |= STM32_DMA_CR_PFCTRL | - STM32_DMA_CR_PBURST_INCR4 | - STM32_DMA_CR_MBURST_INCR4; -#endif - - if (sdcp->state == BLK_STOP) { - /* Note, the DMA must be enabled before the IRQs.*/ - bool b; - b = dmaStreamAllocate(sdcp->dma, STM32_SDC_SDMMC1_IRQ_PRIORITY, NULL, NULL); - osalDbgAssert(!b, "stream already allocated"); - dmaStreamSetPeripheral(sdcp->dma, &sdcp->sdmmc->FIFO); -#if STM32_DMA_ADVANCED - dmaStreamSetFIFO(sdcp->dma, STM32_DMA_FCR_DMDIS | STM32_DMA_FCR_FTH_FULL); -#endif - nvicEnableVector(STM32_SDMMC1_NUMBER, STM32_SDC_SDMMC1_IRQ_PRIORITY); - rccEnableSDMMC1(FALSE); - } - - /* Configuration, card clock is initially stopped.*/ - sdcp->sdmmc->POWER = 0; - sdcp->sdmmc->CLKCR = 0; - sdcp->sdmmc->DCTRL = 0; - sdcp->sdmmc->DTIMER = 0; -} - -/** - * @brief Deactivates the SDC peripheral. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @notapi - */ -void sdc_lld_stop(SDCDriver *sdcp) { - - if (sdcp->state != BLK_STOP) { - - /* SDIO deactivation.*/ - sdcp->sdmmc->POWER = 0; - sdcp->sdmmc->CLKCR = 0; - sdcp->sdmmc->DCTRL = 0; - sdcp->sdmmc->DTIMER = 0; - - /* Clock deactivation.*/ - nvicDisableVector(STM32_SDMMC1_NUMBER); - dmaStreamRelease(sdcp->dma); - rccDisableSDMMC1(FALSE); - } -} - -/** - * @brief Starts the SDIO clock and sets it to init mode (400kHz or less). - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @notapi - */ -void sdc_lld_start_clk(SDCDriver *sdcp) { - - /* Initial clock setting: 400kHz, 1bit mode.*/ - sdcp->sdmmc->CLKCR = SDMMC_CLKDIV_LS; - sdcp->sdmmc->POWER |= SDMMC_POWER_PWRCTRL_0 | SDMMC_POWER_PWRCTRL_1; - sdcp->sdmmc->CLKCR |= SDMMC_CLKCR_CLKEN; - - /* Clock activation delay.*/ - osalThreadSleep(OSAL_MS2ST(STM32_SDC_SDMMC_CLOCK_DELAY)); -} - -/** - * @brief Sets the SDIO clock to data mode (25MHz or less). - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] clk the clock mode - * - * @notapi - */ -void sdc_lld_set_data_clk(SDCDriver *sdcp, sdcbusclk_t clk) { -#if 0 - if (SDC_CLK_50MHz == clk) { - sdcp->sdmmc->CLKCR = (sdcp->sdmmc->CLKCR & 0xFFFFFF00U) | - SDMMC_CLKDIV_HS | SDMMC_CLKCR_BYPASS; - } - else - sdcp->sdmmc->CLKCR = (sdcp->sdmmc->CLKCR & 0xFFFFFF00U) | SDMMC_CLKDIV_HS; -#else - (void)clk; - - sdcp->sdmmc->CLKCR = (sdcp->sdmmc->CLKCR & 0xFFFFFF00U) | SDMMC_CLKDIV_HS; -#endif -} - -/** - * @brief Stops the SDIO clock. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @notapi - */ -void sdc_lld_stop_clk(SDCDriver *sdcp) { - - sdcp->sdmmc->CLKCR = 0; - sdcp->sdmmc->POWER = 0; -} - -/** - * @brief Switches the bus to 4 bits mode. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] mode bus mode - * - * @notapi - */ -void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode) { - uint32_t clk = sdcp->sdmmc->CLKCR & ~SDMMC_CLKCR_WIDBUS; - - switch (mode) { - case SDC_MODE_1BIT: - sdcp->sdmmc->CLKCR = clk; - break; - case SDC_MODE_4BIT: - sdcp->sdmmc->CLKCR = clk | SDMMC_CLKCR_WIDBUS_0; - break; - case SDC_MODE_8BIT: - sdcp->sdmmc->CLKCR = clk | SDMMC_CLKCR_WIDBUS_1; - break; - } -} - -/** - * @brief Sends an SDIO command with no response expected. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] cmd card command - * @param[in] arg command argument - * - * @notapi - */ -void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg) { - - sdcp->sdmmc->ARG = arg; - sdcp->sdmmc->CMD = (uint32_t)cmd | SDMMC_CMD_CPSMEN; - while ((sdcp->sdmmc->STA & SDMMC_STA_CMDSENT) == 0) - ; - sdcp->sdmmc->ICR = SDMMC_ICR_CMDSENTC; -} - -/** - * @brief Sends an SDIO command with a short response expected. - * @note The CRC is not verified. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] cmd card command - * @param[in] arg command argument - * @param[out] resp pointer to the response buffer (one word) - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @notapi - */ -bool sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, - uint32_t *resp) { - uint32_t sta; - - sdcp->sdmmc->ARG = arg; - sdcp->sdmmc->CMD = (uint32_t)cmd | SDMMC_CMD_WAITRESP_0 | SDMMC_CMD_CPSMEN; - while (((sta = sdcp->sdmmc->STA) & (SDMMC_STA_CMDREND | SDMMC_STA_CTIMEOUT | - SDMMC_STA_CCRCFAIL)) == 0) - ; - sdcp->sdmmc->ICR = sta & (SDMMC_STA_CMDREND | SDMMC_STA_CTIMEOUT | - SDMMC_STA_CCRCFAIL); - if ((sta & (SDMMC_STA_CTIMEOUT)) != 0) { - sdc_lld_collect_errors(sdcp, sta); - return HAL_FAILED; - } - *resp = sdcp->sdmmc->RESP1; - return HAL_SUCCESS; -} - -/** - * @brief Sends an SDIO command with a short response expected and CRC. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] cmd card command - * @param[in] arg command argument - * @param[out] resp pointer to the response buffer (one word) - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @notapi - */ -bool sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, - uint32_t *resp) { - uint32_t sta; - - sdcp->sdmmc->ARG = arg; - sdcp->sdmmc->CMD = (uint32_t)cmd | SDMMC_CMD_WAITRESP_0 | SDMMC_CMD_CPSMEN; - while (((sta = sdcp->sdmmc->STA) & (SDMMC_STA_CMDREND | SDMMC_STA_CTIMEOUT | - SDMMC_STA_CCRCFAIL)) == 0) - ; - sdcp->sdmmc->ICR = sta & (SDMMC_STA_CMDREND | SDMMC_STA_CTIMEOUT | SDMMC_STA_CCRCFAIL); - if ((sta & (SDMMC_STA_CTIMEOUT | SDMMC_STA_CCRCFAIL)) != 0) { - sdc_lld_collect_errors(sdcp, sta); - return HAL_FAILED; - } - *resp = sdcp->sdmmc->RESP1; - return HAL_SUCCESS; -} - -/** - * @brief Sends an SDIO command with a long response expected and CRC. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] cmd card command - * @param[in] arg command argument - * @param[out] resp pointer to the response buffer (four words) - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @notapi - */ -bool sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, - uint32_t *resp) { - uint32_t sta; - - (void)sdcp; - - sdcp->sdmmc->ARG = arg; - sdcp->sdmmc->CMD = (uint32_t)cmd | SDMMC_CMD_WAITRESP_0 | SDMMC_CMD_WAITRESP_1 | - SDMMC_CMD_CPSMEN; - while (((sta = sdcp->sdmmc->STA) & (SDMMC_STA_CMDREND | SDMMC_STA_CTIMEOUT | - SDMMC_STA_CCRCFAIL)) == 0) - ; - sdcp->sdmmc->ICR = sta & (SDMMC_STA_CMDREND | SDMMC_STA_CTIMEOUT | - SDMMC_STA_CCRCFAIL); - if ((sta & (SDMMC_STA_ERROR_MASK)) != 0) { - sdc_lld_collect_errors(sdcp, sta); - return HAL_FAILED; - } - /* Save bytes in reverse order because MSB in response comes first.*/ - *resp++ = sdcp->sdmmc->RESP4; - *resp++ = sdcp->sdmmc->RESP3; - *resp++ = sdcp->sdmmc->RESP2; - *resp = sdcp->sdmmc->RESP1; - return HAL_SUCCESS; -} - -/** - * @brief Reads special registers using data bus. - * @details Needs only during card detection procedure. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[out] buf pointer to the read buffer - * @param[in] bytes number of bytes to read - * @param[in] cmd card command - * @param[in] arg argument for command - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @notapi - */ -bool sdc_lld_read_special(SDCDriver *sdcp, uint8_t *buf, size_t bytes, - uint8_t cmd, uint32_t arg) { - uint32_t resp[1]; - - if(sdc_lld_prepare_read_bytes(sdcp, buf, bytes)) - goto error; - - if (sdc_lld_send_cmd_short_crc(sdcp, cmd, arg, resp) - || MMCSD_R1_ERROR(resp[0])) - goto error; - - if (sdc_lld_wait_transaction_end(sdcp, 1, resp)) - goto error; - - return HAL_SUCCESS; - -error: - sdc_lld_error_cleanup(sdcp, 1, resp); - return HAL_FAILED; -} - -/** - * @brief Reads one or more blocks. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] startblk first block to read - * @param[out] buf pointer to the read buffer - * @param[in] blocks number of blocks to read - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @notapi - */ -bool sdc_lld_read_aligned(SDCDriver *sdcp, uint32_t startblk, - uint8_t *buf, uint32_t blocks) { - uint32_t resp[1]; - - osalDbgCheck(blocks < 0x1000000 / MMCSD_BLOCK_SIZE); - - sdcp->sdmmc->DTIMER = SDMMC_READ_TIMEOUT; - - /* Checks for errors and waits for the card to be ready for reading.*/ - if (_sdc_wait_for_transfer_state(sdcp)) - return HAL_FAILED; - - /* Prepares the DMA channel for writing.*/ - dmaStreamSetMemory0(sdcp->dma, buf); - dmaStreamSetTransactionSize(sdcp->dma, - (blocks * MMCSD_BLOCK_SIZE) / sizeof (uint32_t)); - dmaStreamSetMode(sdcp->dma, sdcp->dmamode | STM32_DMA_CR_DIR_P2M); - dmaStreamEnable(sdcp->dma); - - /* Setting up data transfer.*/ - sdcp->sdmmc->ICR = SDMMC_ICR_ALL_FLAGS; - sdcp->sdmmc->MASK = SDMMC_MASK_DCRCFAILIE | - SDMMC_MASK_DTIMEOUTIE | - SDMMC_MASK_RXOVERRIE | - SDMMC_MASK_DATAENDIE; - sdcp->sdmmc->DLEN = blocks * MMCSD_BLOCK_SIZE; - - /* Transaction starts just after DTEN bit setting.*/ - sdcp->sdmmc->DCTRL = SDMMC_DCTRL_DTDIR | - SDMMC_DCTRL_DBLOCKSIZE_3 | - SDMMC_DCTRL_DBLOCKSIZE_0 | - SDMMC_DCTRL_DMAEN | - SDMMC_DCTRL_DTEN; - - if (sdc_lld_prepare_read(sdcp, startblk, blocks, resp) == TRUE) - goto error; - - if (sdc_lld_wait_transaction_end(sdcp, blocks, resp) == TRUE) - goto error; - - return HAL_SUCCESS; - -error: - sdc_lld_error_cleanup(sdcp, blocks, resp); - return HAL_FAILED; -} - -/** - * @brief Writes one or more blocks. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] startblk first block to write - * @param[out] buf pointer to the write buffer - * @param[in] n number of blocks to write - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @notapi - */ -bool sdc_lld_write_aligned(SDCDriver *sdcp, uint32_t startblk, - const uint8_t *buf, uint32_t blocks) { - uint32_t resp[1]; - - osalDbgCheck(blocks < 0x1000000 / MMCSD_BLOCK_SIZE); - - sdcp->sdmmc->DTIMER = SDMMC_WRITE_TIMEOUT; - - /* Checks for errors and waits for the card to be ready for writing.*/ - if (_sdc_wait_for_transfer_state(sdcp)) - return HAL_FAILED; - - /* Prepares the DMA channel for writing.*/ - dmaStreamSetMemory0(sdcp->dma, buf); - dmaStreamSetTransactionSize(sdcp->dma, - (blocks * MMCSD_BLOCK_SIZE) / sizeof (uint32_t)); - dmaStreamSetMode(sdcp->dma, sdcp->dmamode | STM32_DMA_CR_DIR_M2P); - dmaStreamEnable(sdcp->dma); - - /* Setting up data transfer.*/ - sdcp->sdmmc->ICR = SDMMC_ICR_ALL_FLAGS; - sdcp->sdmmc->MASK = SDMMC_MASK_DCRCFAILIE | - SDMMC_MASK_DTIMEOUTIE | - SDMMC_MASK_TXUNDERRIE | - SDMMC_MASK_DATAENDIE; - sdcp->sdmmc->DLEN = blocks * MMCSD_BLOCK_SIZE; - - /* Talk to card what we want from it.*/ - if (sdc_lld_prepare_write(sdcp, startblk, blocks, resp) == TRUE) - goto error; - - /* Transaction starts just after DTEN bit setting.*/ - sdcp->sdmmc->DCTRL = SDMMC_DCTRL_DBLOCKSIZE_3 | - SDMMC_DCTRL_DBLOCKSIZE_0 | - SDMMC_DCTRL_DMAEN | - SDMMC_DCTRL_DTEN; - - if (sdc_lld_wait_transaction_end(sdcp, blocks, resp) == TRUE) - goto error; - - return HAL_SUCCESS; - -error: - sdc_lld_error_cleanup(sdcp, blocks, resp); - return HAL_FAILED; -} - -/** - * @brief Reads one or more blocks. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] startblk first block to read - * @param[out] buf pointer to the read buffer - * @param[in] blocks number of blocks to read - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @notapi - */ -bool sdc_lld_read(SDCDriver *sdcp, uint32_t startblk, - uint8_t *buf, uint32_t blocks) { - -#if STM32_SDC_SDMMC_UNALIGNED_SUPPORT - if (((unsigned)buf & 3) != 0) { - uint32_t i; - for (i = 0; i < blocks; i++) { - if (sdc_lld_read_aligned(sdcp, startblk, u.buf, 1)) - return HAL_FAILED; - memcpy(buf, u.buf, MMCSD_BLOCK_SIZE); - buf += MMCSD_BLOCK_SIZE; - startblk++; - } - return HAL_SUCCESS; - } -#endif /* STM32_SDC_SDMMC_UNALIGNED_SUPPORT */ - return sdc_lld_read_aligned(sdcp, startblk, buf, blocks); -} - -/** - * @brief Writes one or more blocks. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] startblk first block to write - * @param[out] buf pointer to the write buffer - * @param[in] blocks number of blocks to write - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @notapi - */ -bool sdc_lld_write(SDCDriver *sdcp, uint32_t startblk, - const uint8_t *buf, uint32_t blocks) { - -#if STM32_SDC_SDMMC_UNALIGNED_SUPPORT - if (((unsigned)buf & 3) != 0) { - uint32_t i; - for (i = 0; i < blocks; i++) { - memcpy(u.buf, buf, MMCSD_BLOCK_SIZE); - buf += MMCSD_BLOCK_SIZE; - if (sdc_lld_write_aligned(sdcp, startblk, u.buf, 1)) - return HAL_FAILED; - startblk++; - } - return HAL_SUCCESS; - } -#endif /* STM32_SDC_SDMMC_UNALIGNED_SUPPORT */ - return sdc_lld_write_aligned(sdcp, startblk, buf, blocks); -} - -/** - * @brief Waits for card idle condition. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @return The operation status. - * @retval HAL_SUCCESS the operation succeeded. - * @retval HAL_FAILED the operation failed. - * - * @api - */ -bool sdc_lld_sync(SDCDriver *sdcp) { - - /* TODO: Implement.*/ - (void)sdcp; - return HAL_SUCCESS; -} - -#endif /* HAL_USE_SDC */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/SDMMCv1/sdc_lld.h b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/SDMMCv1/sdc_lld.h deleted file mode 100644 index 2622cdf623..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/SDMMCv1/sdc_lld.h +++ /dev/null @@ -1,275 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/SDMMCv1/sdc_lld.h - * @brief STM32 SDC subsystem low level driver header. - * - * @addtogroup SDC - * @{ - */ - -#ifndef _SDC_LLD_H_ -#define _SDC_LLD_H_ - -#if HAL_USE_SDC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief SDMMC driver enable switch. - * @details If set to @p TRUE the support for SDMMC1 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SDC_USE_SDMMC1) || defined(__DOXYGEN__) -#define STM32_SDC_USE_SDMMC1 FALSE -#endif - -/** - * @brief Support for unaligned transfers. - * @note Unaligned transfers are much slower. - */ -#if !defined(STM32_SDC_SDMMC_UNALIGNED_SUPPORT) || defined(__DOXYGEN__) -#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE -#endif - -/** - * @brief Write timeout in milliseconds. - */ -#if !defined(STM32_SDC_SDMMC_WRITE_TIMEOUT) || defined(__DOXYGEN__) -#define STM32_SDC_SDMMC_WRITE_TIMEOUT 250 -#endif - -/** - * @brief Read timeout in milliseconds. - */ -#if !defined(STM32_SDC_SDMMC_READ_TIMEOUT) || defined(__DOXYGEN__) -#define STM32_SDC_SDMMC_READ_TIMEOUT 25 -#endif - -/** - * @brief Card clock activation delay in milliseconds. - */ -#if !defined(STM32_SDC_SDMMC_CLOCK_DELAY) || defined(__DOXYGEN__) -#define STM32_SDC_SDMMC_CLOCK_DELAY 10 -#endif - -/** - * @brief SDMMC1 DMA priority (0..3|lowest..highest). - */ -#if !defined(STM32_SDC_SDMMC1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SDC_SDMMC1_DMA_PRIORITY 3 -#endif - -/** - * @brief SDMMC1 interrupt priority level setting. - */ -#if !defined(STM32_SDC_SDMMC1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_SDC_USE_SDMMC1 && !STM32_HAS_SDMMC1 -#error "SDMMC1 not present in the selected device" -#endif - -#if !STM32_SDC_USE_SDMMC1 -#error "SDC driver activated but no SDMMC peripheral assigned" -#endif - -#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SDC_SDMMC1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SDIO" -#endif - -#if !STM32_DMA_IS_VALID_PRIORITY(STM32_SDC_SDMMC1_DMA_PRIORITY) -#error "Invalid DMA priority assigned to SDIO" -#endif - -/* Check on the presence of the DMA streams settings in mcuconf.h.*/ -#if !defined(STM32_SDC_SDMMC1_DMA_STREAM) -#error "SDMMC1 DMA streams not defined" -#endif - -/* Check on the validity of the assigned DMA channels.*/ -#if !STM32_DMA_IS_VALID_ID(STM32_SDC_SDMMC1_DMA_STREAM, STM32_SDC_SDMMC1_DMA_MSK) -#error "invalid DMA stream associated to SDMMC1" -#endif - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of card flags. - */ -typedef uint32_t sdcmode_t; - -/** - * @brief SDC Driver condition flags type. - */ -typedef uint32_t sdcflags_t; - -/** - * @brief Type of a structure representing an SDC driver. - */ -typedef struct SDCDriver SDCDriver; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief Working area for memory consuming operations. - * @note Buffer must be word aligned and big enough to store 512 bytes. - * @note It is mandatory for detecting MMC cards bigger than 2GB else it - * can be @p NULL. SD cards do NOT need it. - * @note Memory pointed by this buffer is only used by @p sdcConnect(), - * afterward it can be reused for other purposes. - */ - uint8_t *scratchpad; - /** - * @brief Bus width. - */ - sdcbusmode_t bus_width; - /* End of the mandatory fields.*/ -} SDCConfig; - -/** - * @brief @p SDCDriver specific methods. - */ -#define _sdc_driver_methods \ - _mmcsd_block_device_methods - -/** - * @extends MMCSDBlockDeviceVMT - * - * @brief @p SDCDriver virtual methods table. - */ -struct SDCDriverVMT { - _sdc_driver_methods -}; - -/** - * @brief Structure representing an SDC driver. - */ -struct SDCDriver { - /** - * @brief Virtual Methods Table. - */ - const struct SDCDriverVMT *vmt; - _mmcsd_block_device_data - /** - * @brief Current configuration data. - */ - const SDCConfig *config; - /** - * @brief Various flags regarding the mounted card. - */ - sdcmode_t cardmode; - /** - * @brief Errors flags. - */ - sdcflags_t errors; - /** - * @brief Card RCA. - */ - uint32_t rca; - /* End of the mandatory fields.*/ - /** - * @brief Thread waiting for I/O completion IRQ. - */ - thread_reference_t thread; - /** - * @brief DMA mode bit mask. - */ - uint32_t dmamode; - /** - * @brief Transmit DMA channel. - */ - const stm32_dma_stream_t *dma; - /** - * @brief Pointer to the SDMMC registers block. - * @note Needed for debugging aid. - */ - SDMMC_TypeDef *sdmmc; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -extern SDCDriver SDCD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void sdc_lld_init(void); - void sdc_lld_start(SDCDriver *sdcp); - void sdc_lld_stop(SDCDriver *sdcp); - void sdc_lld_start_clk(SDCDriver *sdcp); - void sdc_lld_set_data_clk(SDCDriver *sdcp, sdcbusclk_t clk); - void sdc_lld_stop_clk(SDCDriver *sdcp); - void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode); - void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg); - bool sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, - uint32_t *resp); - bool sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, - uint32_t *resp); - bool sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, - uint32_t *resp); - bool sdc_lld_read_special(SDCDriver *sdcp, uint8_t *buf, size_t bytes, - uint8_t cmd, uint32_t argument); - bool sdc_lld_read(SDCDriver *sdcp, uint32_t startblk, - uint8_t *buf, uint32_t blocks); - bool sdc_lld_write(SDCDriver *sdcp, uint32_t startblk, - const uint8_t *buf, uint32_t blocks); - bool sdc_lld_sync(SDCDriver *sdcp); - bool sdc_lld_is_card_inserted(SDCDriver *sdcp); - bool sdc_lld_is_write_protected(SDCDriver *sdcp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_SDC */ - -#endif /* _SDC_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/SPIv1/i2s_lld.c b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/SPIv1/i2s_lld.c deleted file mode 100644 index 103f35fa7f..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/SPIv1/i2s_lld.c +++ /dev/null @@ -1,577 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file i2s_lld.c - * @brief STM32 I2S subsystem low level driver source. - * - * @addtogroup I2S - * @{ - */ - -#include "hal.h" - -#if HAL_USE_I2S || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define I2S1_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_I2S_SPI1_RX_DMA_STREAM, \ - STM32_SPI1_RX_DMA_CHN) - -#define I2S1_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_I2S_SPI1_TX_DMA_STREAM, \ - STM32_SPI1_TX_DMA_CHN) - -#define I2S2_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_I2S_SPI2_RX_DMA_STREAM, \ - STM32_SPI2_RX_DMA_CHN) - -#define I2S2_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_I2S_SPI2_TX_DMA_STREAM, \ - STM32_SPI2_TX_DMA_CHN) - -#define I2S3_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_I2S_SPI3_RX_DMA_STREAM, \ - STM32_SPI3_RX_DMA_CHN) - -#define I2S3_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_I2S_SPI3_TX_DMA_STREAM, \ - STM32_SPI3_TX_DMA_CHN) - -/* - * Static I2S settings for I2S1. - */ -#if !STM32_I2S_IS_MASTER(STM32_I2S_SPI1_MODE) -#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE) -#define STM32_I2S1_CFGR_CFG 0 -#endif -#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE) -#define STM32_I2S1_CFGR_CFG SPI_I2SCFGR_I2SCFG_0 -#endif -#else /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI1_MODE) */ -#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE) -#define STM32_I2S1_CFGR_CFG SPI_I2SCFGR_I2SCFG_1 -#endif -#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE) -#define STM32_I2S1_CFGR_CFG (SPI_I2SCFGR_I2SCFG_1 | \ - SPI_I2SCFGR_I2SCFG_0) -#endif -#endif /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI1_MODE) */ - -/* - * Static I2S settings for I2S2. - */ -#if !STM32_I2S_IS_MASTER(STM32_I2S_SPI2_MODE) -#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE) -#define STM32_I2S2_CFGR_CFG 0 -#endif -#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE) -#define STM32_I2S2_CFGR_CFG SPI_I2SCFGR_I2SCFG_0 -#endif -#else /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI2_MODE) */ -#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE) -#define STM32_I2S2_CFGR_CFG SPI_I2SCFGR_I2SCFG_1 -#endif -#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE) -#define STM32_I2S2_CFGR_CFG (SPI_I2SCFGR_I2SCFG_1 | \ - SPI_I2SCFGR_I2SCFG_0) -#endif -#endif /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI2_MODE) */ - -/* - * Static I2S settings for I2S3. - */ -#if !STM32_I2S_IS_MASTER(STM32_I2S_SPI3_MODE) -#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE) -#define STM32_I2S3_CFGR_CFG 0 -#endif -#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE) -#define STM32_I2S3_CFGR_CFG SPI_I2SCFGR_I2SCFG_0 -#endif -#else /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI3_MODE) */ -#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE) -#define STM32_I2S3_CFGR_CFG SPI_I2SCFGR_I2SCFG_1 -#endif -#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE) -#define STM32_I2S3_CFGR_CFG (SPI_I2SCFGR_I2SCFG_1 | \ - SPI_I2SCFGR_I2SCFG_0) -#endif -#endif /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI3_MODE) */ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief I2S1 driver identifier.*/ -#if STM32_I2S_USE_SPI1 || defined(__DOXYGEN__) -I2SDriver I2SD1; -#endif - -/** @brief I2S2 driver identifier.*/ -#if STM32_I2S_USE_SPI2 || defined(__DOXYGEN__) -I2SDriver I2SD2; -#endif - -/** @brief I2S3 driver identifier.*/ -#if STM32_I2S_USE_SPI3 || defined(__DOXYGEN__) -I2SDriver I2SD3; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE) || \ - STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE) || \ - STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE) || defined(__DOXYGEN__) -/** - * @brief Shared end-of-rx service routine. - * - * @param[in] i2sp pointer to the @p I2SDriver object - * @param[in] flags pre-shifted content of the ISR register - */ -static void i2s_lld_serve_rx_interrupt(I2SDriver *i2sp, uint32_t flags) { - - (void)i2sp; - - /* DMA errors handling.*/ -#if defined(STM32_I2S_DMA_ERROR_HOOK) - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - STM32_I2S_DMA_ERROR_HOOK(i2sp); - } -#endif - - /* Callbacks handling, note it is portable code defined in the high - level driver.*/ - if ((flags & STM32_DMA_ISR_TCIF) != 0) { - /* Transfer complete processing.*/ - _i2s_isr_full_code(i2sp); - } - else if ((flags & STM32_DMA_ISR_HTIF) != 0) { - /* Half transfer processing.*/ - _i2s_isr_half_code(i2sp); - } -} -#endif - -#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE) || \ - STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE) || \ - STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE) || defined(__DOXYGEN__) -/** - * @brief Shared end-of-tx service routine. - * - * @param[in] i2sp pointer to the @p I2SDriver object - * @param[in] flags pre-shifted content of the ISR register - */ -static void i2s_lld_serve_tx_interrupt(I2SDriver *i2sp, uint32_t flags) { - - (void)i2sp; - - /* DMA errors handling.*/ -#if defined(STM32_I2S_DMA_ERROR_HOOK) - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - STM32_I2S_DMA_ERROR_HOOK(i2sp); - } -#endif - - /* Callbacks handling, note it is portable code defined in the high - level driver.*/ - if ((flags & STM32_DMA_ISR_TCIF) != 0) { - /* Transfer complete processing.*/ - _i2s_isr_full_code(i2sp); - } - else if ((flags & STM32_DMA_ISR_HTIF) != 0) { - /* Half transfer processing.*/ - _i2s_isr_half_code(i2sp); - } -} -#endif - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level I2S driver initialization. - * - * @notapi - */ -void i2s_lld_init(void) { - -#if STM32_I2S_USE_SPI1 - i2sObjectInit(&I2SD1); - I2SD1.spi = SPI1; - I2SD1.cfg = STM32_I2S1_CFGR_CFG; -#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE) - I2SD1.dmarx = STM32_DMA_STREAM(STM32_I2S_SPI1_RX_DMA_STREAM); - I2SD1.rxdmamode = STM32_DMA_CR_CHSEL(I2S1_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_I2S_SPI1_DMA_PRIORITY) | - STM32_DMA_CR_PSIZE_HWORD | - STM32_DMA_CR_MSIZE_HWORD | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_MINC | - STM32_DMA_CR_CIRC | - STM32_DMA_CR_HTIE | - STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; -#else - I2SD1.dmarx = NULL; - I2SD1.rxdmamode = 0; -#endif -#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE) - I2SD1.dmatx = STM32_DMA_STREAM(STM32_I2S_SPI1_TX_DMA_STREAM); - I2SD1.txdmamode = STM32_DMA_CR_CHSEL(I2S1_TX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_I2S_SPI1_DMA_PRIORITY) | - STM32_DMA_CR_PSIZE_HWORD | - STM32_DMA_CR_MSIZE_HWORD | - STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_MINC | - STM32_DMA_CR_CIRC | - STM32_DMA_CR_HTIE | - STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; -#else - I2SD1.dmatx = NULL; - I2SD1.txdmamode = 0; -#endif -#endif - -#if STM32_I2S_USE_SPI2 - i2sObjectInit(&I2SD2); - I2SD2.spi = SPI2; - I2SD2.cfg = STM32_I2S2_CFGR_CFG; -#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE) - I2SD2.dmarx = STM32_DMA_STREAM(STM32_I2S_SPI2_RX_DMA_STREAM); - I2SD2.rxdmamode = STM32_DMA_CR_CHSEL(I2S2_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_I2S_SPI2_DMA_PRIORITY) | - STM32_DMA_CR_PSIZE_HWORD | - STM32_DMA_CR_MSIZE_HWORD | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_MINC | - STM32_DMA_CR_CIRC | - STM32_DMA_CR_HTIE | - STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; -#else - I2SD2.dmarx = NULL; - I2SD2.rxdmamode = 0; -#endif -#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE) - I2SD2.dmatx = STM32_DMA_STREAM(STM32_I2S_SPI2_TX_DMA_STREAM); - I2SD2.txdmamode = STM32_DMA_CR_CHSEL(I2S2_TX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_I2S_SPI2_DMA_PRIORITY) | - STM32_DMA_CR_PSIZE_HWORD | - STM32_DMA_CR_MSIZE_HWORD | - STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_MINC | - STM32_DMA_CR_CIRC | - STM32_DMA_CR_HTIE | - STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; -#else - I2SD2.dmatx = NULL; - I2SD2.txdmamode = 0; -#endif -#endif - -#if STM32_I2S_USE_SPI3 - i2sObjectInit(&I2SD3); - I2SD3.spi = SPI3; - I2SD3.cfg = STM32_I2S3_CFGR_CFG; -#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE) - I2SD3.dmarx = STM32_DMA_STREAM(STM32_I2S_SPI3_RX_DMA_STREAM); - I2SD3.rxdmamode = STM32_DMA_CR_CHSEL(I2S3_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_I2S_SPI3_DMA_PRIORITY) | - STM32_DMA_CR_PSIZE_HWORD | - STM32_DMA_CR_MSIZE_HWORD | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_MINC | - STM32_DMA_CR_CIRC | - STM32_DMA_CR_HTIE | - STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; -#else - I2SD3.dmarx = NULL; - I2SD3.rxdmamode = 0; -#endif -#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE) - I2SD3.dmatx = STM32_DMA_STREAM(STM32_I2S_SPI3_TX_DMA_STREAM); - I2SD3.txdmamode = STM32_DMA_CR_CHSEL(I2S3_TX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_I2S_SPI3_DMA_PRIORITY) | - STM32_DMA_CR_PSIZE_HWORD | - STM32_DMA_CR_MSIZE_HWORD | - STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_MINC | - STM32_DMA_CR_CIRC | - STM32_DMA_CR_HTIE | - STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; -#else - I2SD3.dmatx = NULL; - I2SD3.txdmamode = 0; -#endif -#endif -} - -/** - * @brief Configures and activates the I2S peripheral. - * - * @param[in] i2sp pointer to the @p I2SDriver object - * - * @notapi - */ -void i2s_lld_start(I2SDriver *i2sp) { - - /* If in stopped state then enables the SPI and DMA clocks.*/ - if (i2sp->state == I2S_STOP) { - -#if STM32_I2S_USE_SPI1 - if (&I2SD1 == i2sp) { - bool b; - - /* Enabling I2S unit clock.*/ - rccEnableSPI1(FALSE); - -#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE) - b = dmaStreamAllocate(i2sp->dmarx, - STM32_I2S_SPI1_IRQ_PRIORITY, - (stm32_dmaisr_t)i2s_lld_serve_rx_interrupt, - (void *)i2sp); - osalDbgAssert(!b, "stream already allocated"); - - /* CRs settings are done here because those never changes until - the driver is stopped.*/ - i2sp->spi->CR1 = 0; - i2sp->spi->CR2 = SPI_CR2_RXDMAEN; -#endif -#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE) - b = dmaStreamAllocate(i2sp->dmatx, - STM32_I2S_SPI1_IRQ_PRIORITY, - (stm32_dmaisr_t)i2s_lld_serve_tx_interrupt, - (void *)i2sp); - osalDbgAssert(!b, "stream already allocated"); - - /* CRs settings are done here because those never changes until - the driver is stopped.*/ - i2sp->spi->CR1 = 0; - i2sp->spi->CR2 = SPI_CR2_TXDMAEN; -#endif - } -#endif - -#if STM32_I2S_USE_SPI2 - if (&I2SD2 == i2sp) { - bool b; - - /* Enabling I2S unit clock.*/ - rccEnableSPI2(FALSE); - -#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE) - b = dmaStreamAllocate(i2sp->dmarx, - STM32_I2S_SPI2_IRQ_PRIORITY, - (stm32_dmaisr_t)i2s_lld_serve_rx_interrupt, - (void *)i2sp); - osalDbgAssert(!b, "stream already allocated"); - - /* CRs settings are done here because those never changes until - the driver is stopped.*/ - i2sp->spi->CR1 = 0; - i2sp->spi->CR2 = SPI_CR2_RXDMAEN; -#endif -#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE) - b = dmaStreamAllocate(i2sp->dmatx, - STM32_I2S_SPI2_IRQ_PRIORITY, - (stm32_dmaisr_t)i2s_lld_serve_tx_interrupt, - (void *)i2sp); - osalDbgAssert(!b, "stream already allocated"); - - /* CRs settings are done here because those never changes until - the driver is stopped.*/ - i2sp->spi->CR1 = 0; - i2sp->spi->CR2 = SPI_CR2_TXDMAEN; -#endif - } -#endif - -#if STM32_I2S_USE_SPI3 - if (&I2SD3 == i2sp) { - bool b; - - /* Enabling I2S unit clock.*/ - rccEnableSPI3(FALSE); - -#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE) - b = dmaStreamAllocate(i2sp->dmarx, - STM32_I2S_SPI3_IRQ_PRIORITY, - (stm32_dmaisr_t)i2s_lld_serve_rx_interrupt, - (void *)i2sp); - osalDbgAssert(!b, "stream already allocated"); - - /* CRs settings are done here because those never changes until - the driver is stopped.*/ - i2sp->spi->CR1 = 0; - i2sp->spi->CR2 = SPI_CR2_RXDMAEN; -#endif -#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE) - b = dmaStreamAllocate(i2sp->dmatx, - STM32_I2S_SPI3_IRQ_PRIORITY, - (stm32_dmaisr_t)i2s_lld_serve_tx_interrupt, - (void *)i2sp); - osalDbgAssert(!b, "stream already allocated"); - - /* CRs settings are done here because those never changes until - the driver is stopped.*/ - i2sp->spi->CR1 = 0; - i2sp->spi->CR2 = SPI_CR2_TXDMAEN; -#endif - } -#endif - } - - /* I2S (re)configuration.*/ - i2sp->spi->I2SPR = i2sp->config->i2spr; - i2sp->spi->I2SCFGR = i2sp->config->i2scfgr | i2sp->cfg | SPI_I2SCFGR_I2SMOD; -} - -/** - * @brief Deactivates the I2S peripheral. - * - * @param[in] i2sp pointer to the @p I2SDriver object - * - * @notapi - */ -void i2s_lld_stop(I2SDriver *i2sp) { - - /* If in ready state then disables the SPI clock.*/ - if (i2sp->state == I2S_READY) { - - /* SPI disable.*/ - i2sp->spi->CR2 = 0; - if (NULL != i2sp->dmarx) - dmaStreamRelease(i2sp->dmarx); - if (NULL != i2sp->dmatx) - dmaStreamRelease(i2sp->dmatx); - -#if STM32_I2S_USE_SPI1 - if (&I2SD1 == i2sp) - rccDisableSPI1(FALSE); -#endif - -#if STM32_I2S_USE_SPI2 - if (&I2SD2 == i2sp) - rccDisableSPI2(FALSE); -#endif - -#if STM32_I2S_USE_SPI3 - if (&I2SD3 == i2sp) - rccDisableSPI3(FALSE); -#endif - } -} - -/** - * @brief Starts a I2S data exchange. - * - * @param[in] i2sp pointer to the @p I2SDriver object - * - * @notapi - */ -void i2s_lld_start_exchange(I2SDriver *i2sp) { - size_t size = i2sp->config->size; - - /* In 32 bit modes the DMA has to perform double operations because fetches - are always performed using 16 bit accesses. - DATLEN CHLEN SIZE - 00 (16) 0 (16) 16 - 00 (16) 1 (32) 16 - 01 (24) X 32 - 10 (32) X 32 - 11 (NA) X NA - */ - if ((i2sp->config->i2scfgr & SPI_I2SCFGR_DATLEN) != 0) - size *= 2; - - /* RX DMA setup.*/ - if (NULL != i2sp->dmarx) { - dmaStreamSetMode(i2sp->dmarx, i2sp->rxdmamode); - dmaStreamSetPeripheral(i2sp->dmarx, &i2sp->spi->DR); - dmaStreamSetMemory0(i2sp->dmarx, i2sp->config->rx_buffer); - dmaStreamSetTransactionSize(i2sp->dmarx, size); - dmaStreamEnable(i2sp->dmarx); - } - - /* TX DMA setup.*/ - if (NULL != i2sp->dmatx) { - dmaStreamSetMode(i2sp->dmatx, i2sp->txdmamode); - dmaStreamSetPeripheral(i2sp->dmatx, &i2sp->spi->DR); - dmaStreamSetMemory0(i2sp->dmatx, i2sp->config->tx_buffer); - dmaStreamSetTransactionSize(i2sp->dmatx, size); - dmaStreamEnable(i2sp->dmatx); - } - - /* Starting transfer.*/ - i2sp->spi->I2SCFGR |= SPI_I2SCFGR_I2SE; -} - -/** - * @brief Stops the ongoing data exchange. - * @details The ongoing data exchange, if any, is stopped, if the driver - * was not active the function does nothing. - * - * @param[in] i2sp pointer to the @p I2SDriver object - * - * @notapi - */ -void i2s_lld_stop_exchange(I2SDriver *i2sp) { - - /* Stop TX DMA, if enabled.*/ - if (NULL != i2sp->dmatx) { - dmaStreamDisable(i2sp->dmatx); - - /* From the RM: To switch off the I2S, by clearing I2SE, it is mandatory - to wait for TXE = 1 and BSY = 0.*/ - while ((i2sp->spi->SR & (SPI_SR_TXE | SPI_SR_BSY)) != SPI_SR_TXE) - ; - } - - /* Stop SPI/I2S peripheral.*/ - i2sp->spi->I2SCFGR &= ~SPI_I2SCFGR_I2SE; - - /* Stop RX DMA, if enabled.*/ - if (NULL != i2sp->dmarx) - dmaStreamDisable(i2sp->dmarx); -} - -#endif /* HAL_USE_I2S */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/SPIv1/i2s_lld.h b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/SPIv1/i2s_lld.h deleted file mode 100644 index 8b1d4965d7..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/SPIv1/i2s_lld.h +++ /dev/null @@ -1,432 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file i2s_lld.h - * @brief STM32 I2S subsystem low level driver header. - * - * @addtogroup I2S - * @{ - */ - -#ifndef _I2S_LLD_H_ -#define _I2S_LLD_H_ - -#if HAL_USE_I2S || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name Static I2S modes - * @{ - */ -#define STM32_I2S_MODE_SLAVE 0 -#define STM32_I2S_MODE_MASTER 1 -#define STM32_I2S_MODE_RX 2 -#define STM32_I2S_MODE_TX 4 -#define STM32_I2S_MODE_RXTX (STM32_I2S_MODE_RX | \ - STM32_I2S_MODE_TX) -/** @} */ - -/** - * @name Mode checks - * @{ - */ -#define STM32_I2S_IS_MASTER(mode) ((mode) & STM32_I2S_MODE_MASTER) -#define STM32_I2S_RX_ENABLED(mode) ((mode) & STM32_I2S_MODE_RX) -#define STM32_I2S_TX_ENABLED(mode) ((mode) & STM32_I2S_MODE_TX) -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief I2S1 driver enable switch. - * @details If set to @p TRUE the support for I2S1 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_I2S_USE_SPI1) || defined(__DOXYGEN__) -#define STM32_I2S_USE_SPI1 FALSE -#endif - -/** - * @brief I2S2 driver enable switch. - * @details If set to @p TRUE the support for I2S2 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_I2S_USE_SPI2) || defined(__DOXYGEN__) -#define STM32_I2S_USE_SPI2 FALSE -#endif - -/** - * @brief I2S3 driver enable switch. - * @details If set to @p TRUE the support for I2S3 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_I2S_USE_SPI3) || defined(__DOXYGEN__) -#define STM32_I2S_USE_SPI3 FALSE -#endif - -/** - * @brief I2S1 mode. - */ -#if !defined(STM32_I2S_SPI1_MODE) || defined(__DOXYGEN__) -#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \ - STM32_I2S_MODE_RX) -#endif - -/** - * @brief I2S2 mode. - */ -#if !defined(STM32_I2S_SPI2_MODE) || defined(__DOXYGEN__) -#define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_MASTER | \ - STM32_I2S_MODE_RX) -#endif - -/** - * @brief I2S3 mode. - */ -#if !defined(STM32_I2S_SPI3_MODE) || defined(__DOXYGEN__) -#define STM32_I2S_SPI3_MODE (STM32_I2S_MODE_MASTER | \ - STM32_I2S_MODE_RX) -#endif - -/** - * @brief I2S1 interrupt priority level setting. - */ -#if !defined(STM32_I2S_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2S_SPI1_IRQ_PRIORITY 10 -#endif - -/** - * @brief I2S2 interrupt priority level setting. - */ -#if !defined(STM32_I2S_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2S_SPI2_IRQ_PRIORITY 10 -#endif - -/** - * @brief I2S3 interrupt priority level setting. - */ -#if !defined(STM32_I2S_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2S_SPI3_IRQ_PRIORITY 10 -#endif - -/** - * @brief I2S1 DMA priority (0..3|lowest..highest). - */ -#if !defined(STM32_I2S_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2S_SPI1_DMA_PRIORITY 1 -#endif - -/** - * @brief I2S2 DMA priority (0..3|lowest..highest). - */ -#if !defined(STM32_I2S_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2S_SPI2_DMA_PRIORITY 1 -#endif - -/** - * @brief I2S3 DMA priority (0..3|lowest..highest). - */ -#if !defined(STM32_I2S_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2S_SPI3_DMA_PRIORITY 1 -#endif - -/** - * @brief I2S DMA error hook. - */ -#if !defined(STM32_I2S_DMA_ERROR_HOOK) || defined(__DOXYGEN__) -#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_I2S_USE_SPI1 && !STM32_SPI1_SUPPORTS_I2S -#error "SPI1 does not support I2S mode" -#endif - -#if STM32_I2S_USE_SPI2 && !STM32_SPI2_SUPPORTS_I2S -#error "SPI2 does not support I2S mode" -#endif - -#if STM32_I2S_USE_SPI3 && !STM32_SPI3_SUPPORTS_I2S -#error "SPI3 does not support I2S mode" -#endif - -#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE) && \ - STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE) -#error "I2S1 RX and TX mode not supported in this driver implementation" -#endif - -#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE) && \ - STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE) -#error "I2S2 RX and TX mode not supported in this driver implementation" -#endif - -#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE) && \ - STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE) -#error "I2S3 RX and TX mode not supported in this driver implementation" -#endif - -#if STM32_I2S_USE_SPI1 && !STM32_HAS_SPI1 -#error "SPI1 not present in the selected device" -#endif - -#if STM32_I2S_USE_SPI2 && !STM32_HAS_SPI2 -#error "SPI2 not present in the selected device" -#endif - -#if STM32_I2S_USE_SPI3 && !STM32_HAS_SPI3 -#error "SPI3 not present in the selected device" -#endif - -#if !STM32_I2S_USE_SPI1 && !STM32_I2S_USE_SPI2 && !STM32_I2S_USE_SPI3 -#error "I2S driver activated but no SPI peripheral assigned" -#endif - -#if STM32_I2S_USE_SPI1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2S_SPI1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SPI1" -#endif - -#if STM32_I2S_USE_SPI2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2S_SPI2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SPI2" -#endif - -#if STM32_I2S_USE_SPI3 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2S_SPI3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SPI3" -#endif - -#if STM32_I2S_USE_SPI1 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_I2S_SPI1_DMA_PRIORITY) -#error "Invalid DMA priority assigned to SPI1" -#endif - -#if STM32_I2S_USE_SPI2 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_I2S_SPI2_DMA_PRIORITY) -#error "Invalid DMA priority assigned to SPI2" -#endif - -#if STM32_I2S_USE_SPI3 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_I2S_SPI3_DMA_PRIORITY) -#error "Invalid DMA priority assigned to SPI3" -#endif - -/* The following checks are only required when there is a DMA able to - reassign streams to different channels.*/ -#if STM32_ADVANCED_DMA -/* Check on the presence of the DMA streams settings in mcuconf.h.*/ -#if STM32_I2S_USE_SPI1 && (!defined(STM32_I2S_SPI1_RX_DMA_STREAM) || \ - !defined(STM32_I2S_SPI1_TX_DMA_STREAM)) -#error "SPI1 DMA streams not defined" -#endif - -#if STM32_I2S_USE_SPI2 && (!defined(STM32_I2S_SPI2_RX_DMA_STREAM) || \ - !defined(STM32_I2S_SPI2_TX_DMA_STREAM)) -#error "SPI2 DMA streams not defined" -#endif - -#if STM32_I2S_USE_SPI3 && (!defined(STM32_I2S_SPI3_RX_DMA_STREAM) || \ - !defined(STM32_I2S_SPI3_TX_DMA_STREAM)) -#error "SPI3 DMA streams not defined" -#endif - -/* Check on the validity of the assigned DMA channels.*/ -#if STM32_I2S_USE_SPI1 && \ - !STM32_DMA_IS_VALID_ID(STM32_I2S_SPI1_RX_DMA_STREAM, STM32_SPI1_RX_DMA_MSK) -#error "invalid DMA stream associated to SPI1 RX" -#endif - -#if STM32_I2S_USE_SPI1 && \ - !STM32_DMA_IS_VALID_ID(STM32_I2S_SPI1_TX_DMA_STREAM, STM32_SPI1_TX_DMA_MSK) -#error "invalid DMA stream associated to SPI1 TX" -#endif - -#if STM32_I2S_USE_SPI2 && \ - !STM32_DMA_IS_VALID_ID(STM32_I2S_SPI2_RX_DMA_STREAM, STM32_SPI2_RX_DMA_MSK) -#error "invalid DMA stream associated to SPI2 RX" -#endif - -#if STM32_I2S_USE_SPI2 && \ - !STM32_DMA_IS_VALID_ID(STM32_I2S_SPI2_TX_DMA_STREAM, STM32_SPI2_TX_DMA_MSK) -#error "invalid DMA stream associated to SPI2 TX" -#endif - -#if STM32_I2S_USE_SPI3 && \ - !STM32_DMA_IS_VALID_ID(STM32_I2S_SPI3_RX_DMA_STREAM, STM32_SPI3_RX_DMA_MSK) -#error "invalid DMA stream associated to SPI3 RX" -#endif - -#if STM32_I2S_USE_SPI3 && \ - !STM32_DMA_IS_VALID_ID(STM32_I2S_SPI3_TX_DMA_STREAM, STM32_SPI3_TX_DMA_MSK) -#error "invalid DMA stream associated to SPI3 TX" -#endif -#endif /* STM32_ADVANCED_DMA */ - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a structure representing an I2S driver. - */ -typedef struct I2SDriver I2SDriver; - -/** - * @brief I2S notification callback type. - * - * @param[in] i2sp pointer to the @p I2SDriver object - * @param[in] offset offset in buffers of the data to read/write - * @param[in] n number of samples to read/write - */ -typedef void (*i2scallback_t)(I2SDriver *i2sp, size_t offset, size_t n); - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief Transmission buffer pointer. - * @note Can be @p NULL if TX is not required. - */ - const void *tx_buffer; - /** - * @brief Receive buffer pointer. - * @note Can be @p NULL if RX is not required. - */ - void *rx_buffer; - /** - * @brief TX and RX buffers size as number of samples. - */ - size_t size; - /** - * @brief Callback function called during streaming. - */ - i2scallback_t end_cb; - /* End of the mandatory fields.*/ - /** - * @brief Configuration of the I2SCFGR register. - * @details See the STM32 reference manual, this register is used for - * the I2S configuration, the following bits must not be - * specified because handled directly by the driver: - * - I2SMOD - * - I2SE - * - I2SCFG - * . - */ - int16_t i2scfgr; - /** - * @brief Configuration of the I2SPR register. - * @details See the STM32 reference manual, this register is used for - * the I2S clock setup. - */ - int16_t i2spr; -} I2SConfig; - -/** - * @brief Structure representing an I2S driver. - */ -struct I2SDriver { - /** - * @brief Driver state. - */ - i2sstate_t state; - /** - * @brief Current configuration data. - */ - const I2SConfig *config; - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the SPIx registers block. - */ - SPI_TypeDef *spi; - /** - * @brief Calculated part of the I2SCFGR register. - */ - uint16_t cfg; - /** - * @brief Receive DMA stream or @p NULL. - */ - const stm32_dma_stream_t *dmarx; - /** - * @brief Transmit DMA stream or @p NULL. - */ - const stm32_dma_stream_t *dmatx; - /** - * @brief RX DMA mode bit mask. - */ - uint32_t rxdmamode; - /** - * @brief TX DMA mode bit mask. - */ - uint32_t txdmamode; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_I2S_USE_SPI1 && !defined(__DOXYGEN__) -extern I2SDriver I2SD1; -#endif - -#if STM32_I2S_USE_SPI2 && !defined(__DOXYGEN__) -extern I2SDriver I2SD2; -#endif - -#if STM32_I2S_USE_SPI3 && !defined(__DOXYGEN__) -extern I2SDriver I2SD3; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void i2s_lld_init(void); - void i2s_lld_start(I2SDriver *i2sp); - void i2s_lld_stop(I2SDriver *i2sp); - void i2s_lld_start_exchange(I2SDriver *i2sp); - void i2s_lld_stop_exchange(I2SDriver *i2sp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_I2S */ - -#endif /* _I2S_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/SPIv1/spi_lld.c b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/SPIv1/spi_lld.c deleted file mode 100644 index 7ce86dfa23..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/SPIv1/spi_lld.c +++ /dev/null @@ -1,635 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/SPIv1/spi_lld.c - * @brief STM32 SPI subsystem low level driver source. - * - * @addtogroup SPI - * @{ - */ - -#include "hal.h" - -#if HAL_USE_SPI || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define SPI1_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI1_RX_DMA_STREAM, \ - STM32_SPI1_RX_DMA_CHN) - -#define SPI1_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI1_TX_DMA_STREAM, \ - STM32_SPI1_TX_DMA_CHN) - -#define SPI2_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI2_RX_DMA_STREAM, \ - STM32_SPI2_RX_DMA_CHN) - -#define SPI2_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI2_TX_DMA_STREAM, \ - STM32_SPI2_TX_DMA_CHN) - -#define SPI3_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI3_RX_DMA_STREAM, \ - STM32_SPI3_RX_DMA_CHN) - -#define SPI3_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI3_TX_DMA_STREAM, \ - STM32_SPI3_TX_DMA_CHN) - -#define SPI4_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI4_RX_DMA_STREAM, \ - STM32_SPI4_RX_DMA_CHN) - -#define SPI4_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI4_TX_DMA_STREAM, \ - STM32_SPI4_TX_DMA_CHN) - -#define SPI5_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI5_RX_DMA_STREAM, \ - STM32_SPI5_RX_DMA_CHN) - -#define SPI5_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI5_TX_DMA_STREAM, \ - STM32_SPI5_TX_DMA_CHN) - -#define SPI6_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI6_RX_DMA_STREAM, \ - STM32_SPI6_RX_DMA_CHN) - -#define SPI6_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI6_TX_DMA_STREAM, \ - STM32_SPI6_TX_DMA_CHN) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief SPI1 driver identifier.*/ -#if STM32_SPI_USE_SPI1 || defined(__DOXYGEN__) -SPIDriver SPID1; -#endif - -/** @brief SPI2 driver identifier.*/ -#if STM32_SPI_USE_SPI2 || defined(__DOXYGEN__) -SPIDriver SPID2; -#endif - -/** @brief SPI3 driver identifier.*/ -#if STM32_SPI_USE_SPI3 || defined(__DOXYGEN__) -SPIDriver SPID3; -#endif - -/** @brief SPI4 driver identifier.*/ -#if STM32_SPI_USE_SPI4 || defined(__DOXYGEN__) -SPIDriver SPID4; -#endif - -/** @brief SPI5 driver identifier.*/ -#if STM32_SPI_USE_SPI5 || defined(__DOXYGEN__) -SPIDriver SPID5; -#endif - -/** @brief SPI6 driver identifier.*/ -#if STM32_SPI_USE_SPI6 || defined(__DOXYGEN__) -SPIDriver SPID6; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -static uint16_t dummytx; -static uint16_t dummyrx; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Shared end-of-rx service routine. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] flags pre-shifted content of the ISR register - */ -static void spi_lld_serve_rx_interrupt(SPIDriver *spip, uint32_t flags) { - - /* DMA errors handling.*/ -#if defined(STM32_SPI_DMA_ERROR_HOOK) - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - STM32_SPI_DMA_ERROR_HOOK(spip); - } -#else - (void)flags; -#endif - - /* Stop everything.*/ - dmaStreamDisable(spip->dmatx); - dmaStreamDisable(spip->dmarx); - - /* Portable SPI ISR code defined in the high level driver, note, it is - a macro.*/ - _spi_isr_code(spip); -} - -/** - * @brief Shared end-of-tx service routine. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] flags pre-shifted content of the ISR register - */ -static void spi_lld_serve_tx_interrupt(SPIDriver *spip, uint32_t flags) { - - /* DMA errors handling.*/ -#if defined(STM32_SPI_DMA_ERROR_HOOK) - (void)spip; - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - STM32_SPI_DMA_ERROR_HOOK(spip); - } -#else - (void)spip; - (void)flags; -#endif -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level SPI driver initialization. - * - * @notapi - */ -void spi_lld_init(void) { - - dummytx = 0xFFFF; - -#if STM32_SPI_USE_SPI1 - spiObjectInit(&SPID1); - SPID1.spi = SPI1; - SPID1.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI1_RX_DMA_STREAM); - SPID1.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI1_TX_DMA_STREAM); - SPID1.rxdmamode = STM32_DMA_CR_CHSEL(SPI1_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; - SPID1.txdmamode = STM32_DMA_CR_CHSEL(SPI1_TX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) | - STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; -#endif - -#if STM32_SPI_USE_SPI2 - spiObjectInit(&SPID2); - SPID2.spi = SPI2; - SPID2.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI2_RX_DMA_STREAM); - SPID2.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI2_TX_DMA_STREAM); - SPID2.rxdmamode = STM32_DMA_CR_CHSEL(SPI2_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; - SPID2.txdmamode = STM32_DMA_CR_CHSEL(SPI2_TX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) | - STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; -#endif - -#if STM32_SPI_USE_SPI3 - spiObjectInit(&SPID3); - SPID3.spi = SPI3; - SPID3.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI3_RX_DMA_STREAM); - SPID3.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI3_TX_DMA_STREAM); - SPID3.rxdmamode = STM32_DMA_CR_CHSEL(SPI3_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; - SPID3.txdmamode = STM32_DMA_CR_CHSEL(SPI3_TX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) | - STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; -#endif - -#if STM32_SPI_USE_SPI4 - spiObjectInit(&SPID4); - SPID4.spi = SPI4; - SPID4.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI4_RX_DMA_STREAM); - SPID4.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI4_TX_DMA_STREAM); - SPID4.rxdmamode = STM32_DMA_CR_CHSEL(SPI4_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI4_DMA_PRIORITY) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; - SPID4.txdmamode = STM32_DMA_CR_CHSEL(SPI4_TX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI4_DMA_PRIORITY) | - STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; -#endif - -#if STM32_SPI_USE_SPI5 - spiObjectInit(&SPID5); - SPID5.spi = SPI5; - SPID5.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI5_RX_DMA_STREAM); - SPID5.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI5_TX_DMA_STREAM); - SPID5.rxdmamode = STM32_DMA_CR_CHSEL(SPI5_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI5_DMA_PRIORITY) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; - SPID5.txdmamode = STM32_DMA_CR_CHSEL(SPI5_TX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI5_DMA_PRIORITY) | - STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; -#endif - -#if STM32_SPI_USE_SPI6 - spiObjectInit(&SPID6); - SPID6.spi = SPI6; - SPID6.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI6_RX_DMA_STREAM); - SPID6.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI6_TX_DMA_STREAM); - SPID6.rxdmamode = STM32_DMA_CR_CHSEL(SPI6_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI6_DMA_PRIORITY) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; - SPID6.txdmamode = STM32_DMA_CR_CHSEL(SPI6_TX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI6_DMA_PRIORITY) | - STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; -#endif -} - -/** - * @brief Configures and activates the SPI peripheral. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_start(SPIDriver *spip) { - - /* If in stopped state then enables the SPI and DMA clocks.*/ - if (spip->state == SPI_STOP) { -#if STM32_SPI_USE_SPI1 - if (&SPID1 == spip) { - bool b; - b = dmaStreamAllocate(spip->dmarx, - STM32_SPI_SPI1_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, - (void *)spip); - osalDbgAssert(!b, "stream already allocated"); - b = dmaStreamAllocate(spip->dmatx, - STM32_SPI_SPI1_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, - (void *)spip); - osalDbgAssert(!b, "stream already allocated"); - rccEnableSPI1(FALSE); - } -#endif -#if STM32_SPI_USE_SPI2 - if (&SPID2 == spip) { - bool b; - b = dmaStreamAllocate(spip->dmarx, - STM32_SPI_SPI2_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, - (void *)spip); - osalDbgAssert(!b, "stream already allocated"); - b = dmaStreamAllocate(spip->dmatx, - STM32_SPI_SPI2_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, - (void *)spip); - osalDbgAssert(!b, "stream already allocated"); - rccEnableSPI2(FALSE); - } -#endif -#if STM32_SPI_USE_SPI3 - if (&SPID3 == spip) { - bool b; - b = dmaStreamAllocate(spip->dmarx, - STM32_SPI_SPI3_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, - (void *)spip); - osalDbgAssert(!b, "stream already allocated"); - b = dmaStreamAllocate(spip->dmatx, - STM32_SPI_SPI3_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, - (void *)spip); - osalDbgAssert(!b, "stream already allocated"); - rccEnableSPI3(FALSE); - } -#endif -#if STM32_SPI_USE_SPI4 - if (&SPID4 == spip) { - bool b; - b = dmaStreamAllocate(spip->dmarx, - STM32_SPI_SPI4_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, - (void *)spip); - osalDbgAssert(!b, "stream already allocated"); - b = dmaStreamAllocate(spip->dmatx, - STM32_SPI_SPI4_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, - (void *)spip); - osalDbgAssert(!b, "stream already allocated"); - rccEnableSPI4(FALSE); - } -#endif -#if STM32_SPI_USE_SPI5 - if (&SPID5 == spip) { - bool b; - b = dmaStreamAllocate(spip->dmarx, - STM32_SPI_SPI5_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, - (void *)spip); - osalDbgAssert(!b, "stream already allocated"); - b = dmaStreamAllocate(spip->dmatx, - STM32_SPI_SPI5_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, - (void *)spip); - osalDbgAssert(!b, "stream already allocated"); - rccEnableSPI5(FALSE); - } -#endif -#if STM32_SPI_USE_SPI6 - if (&SPID6 == spip) { - bool b; - b = dmaStreamAllocate(spip->dmarx, - STM32_SPI_SPI6_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, - (void *)spip); - osalDbgAssert(!b, "stream already allocated"); - b = dmaStreamAllocate(spip->dmatx, - STM32_SPI_SPI6_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, - (void *)spip); - osalDbgAssert(!b, "stream already allocated"); - rccEnableSPI6(FALSE); - } -#endif - - /* DMA setup.*/ - dmaStreamSetPeripheral(spip->dmarx, &spip->spi->DR); - dmaStreamSetPeripheral(spip->dmatx, &spip->spi->DR); - } - - /* Configuration-specific DMA setup.*/ - if ((spip->config->cr1 & SPI_CR1_DFF) == 0) { - /* Frame width is 8 bits or smaller.*/ - spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) | - STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE; - spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) | - STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE; - } - else { - /* Frame width is larger than 8 bits.*/ - spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) | - STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; - spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) | - STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; - } - /* SPI setup and enable.*/ - spip->spi->CR1 = 0; - spip->spi->CR1 = spip->config->cr1 | SPI_CR1_MSTR | SPI_CR1_SSM | - SPI_CR1_SSI; - spip->spi->CR2 = SPI_CR2_SSOE | SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN; - spip->spi->CR1 |= SPI_CR1_SPE; -} - -/** - * @brief Deactivates the SPI peripheral. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_stop(SPIDriver *spip) { - - /* If in ready state then disables the SPI clock.*/ - if (spip->state == SPI_READY) { - - /* SPI disable.*/ - spip->spi->CR1 = 0; - spip->spi->CR2 = 0; - dmaStreamRelease(spip->dmarx); - dmaStreamRelease(spip->dmatx); - -#if STM32_SPI_USE_SPI1 - if (&SPID1 == spip) - rccDisableSPI1(FALSE); -#endif -#if STM32_SPI_USE_SPI2 - if (&SPID2 == spip) - rccDisableSPI2(FALSE); -#endif -#if STM32_SPI_USE_SPI3 - if (&SPID3 == spip) - rccDisableSPI3(FALSE); -#endif -#if STM32_SPI_USE_SPI4 - if (&SPID4 == spip) - rccDisableSPI4(FALSE); -#endif -#if STM32_SPI_USE_SPI5 - if (&SPID5 == spip) - rccDisableSPI5(FALSE); -#endif -#if STM32_SPI_USE_SPI6 - if (&SPID6 == spip) - rccDisableSPI6(FALSE); -#endif - } -} - -/** - * @brief Asserts the slave select signal and prepares for transfers. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_select(SPIDriver *spip) { - - palClearPad(spip->config->ssport, spip->config->sspad); -} - -/** - * @brief Deasserts the slave select signal. - * @details The previously selected peripheral is unselected. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_unselect(SPIDriver *spip) { - - palSetPad(spip->config->ssport, spip->config->sspad); -} - -/** - * @brief Ignores data on the SPI bus. - * @details This asynchronous function starts the transmission of a series of - * idle words on the SPI bus and ignores the received data. - * @post At the end of the operation the configured callback is invoked. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be ignored - * - * @notapi - */ -void spi_lld_ignore(SPIDriver *spip, size_t n) { - - dmaStreamSetMemory0(spip->dmarx, &dummyrx); - dmaStreamSetTransactionSize(spip->dmarx, n); - dmaStreamSetMode(spip->dmarx, spip->rxdmamode); - - dmaStreamSetMemory0(spip->dmatx, &dummytx); - dmaStreamSetTransactionSize(spip->dmatx, n); - dmaStreamSetMode(spip->dmatx, spip->txdmamode); - - dmaStreamEnable(spip->dmarx); - dmaStreamEnable(spip->dmatx); -} - -/** - * @brief Exchanges data on the SPI bus. - * @details This asynchronous function starts a simultaneous transmit/receive - * operation. - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be exchanged - * @param[in] txbuf the pointer to the transmit buffer - * @param[out] rxbuf the pointer to the receive buffer - * - * @notapi - */ -void spi_lld_exchange(SPIDriver *spip, size_t n, - const void *txbuf, void *rxbuf) { - - dmaStreamSetMemory0(spip->dmarx, rxbuf); - dmaStreamSetTransactionSize(spip->dmarx, n); - dmaStreamSetMode(spip->dmarx, spip->rxdmamode| STM32_DMA_CR_MINC); - - dmaStreamSetMemory0(spip->dmatx, txbuf); - dmaStreamSetTransactionSize(spip->dmatx, n); - dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC); - - dmaStreamEnable(spip->dmarx); - dmaStreamEnable(spip->dmatx); -} - -/** - * @brief Sends data over the SPI bus. - * @details This asynchronous function starts a transmit operation. - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to send - * @param[in] txbuf the pointer to the transmit buffer - * - * @notapi - */ -void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { - - dmaStreamSetMemory0(spip->dmarx, &dummyrx); - dmaStreamSetTransactionSize(spip->dmarx, n); - dmaStreamSetMode(spip->dmarx, spip->rxdmamode); - - dmaStreamSetMemory0(spip->dmatx, txbuf); - dmaStreamSetTransactionSize(spip->dmatx, n); - dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC); - - dmaStreamEnable(spip->dmarx); - dmaStreamEnable(spip->dmatx); -} - -/** - * @brief Receives data from the SPI bus. - * @details This asynchronous function starts a receive operation. - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to receive - * @param[out] rxbuf the pointer to the receive buffer - * - * @notapi - */ -void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { - - dmaStreamSetMemory0(spip->dmarx, rxbuf); - dmaStreamSetTransactionSize(spip->dmarx, n); - dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_MINC); - - dmaStreamSetMemory0(spip->dmatx, &dummytx); - dmaStreamSetTransactionSize(spip->dmatx, n); - dmaStreamSetMode(spip->dmatx, spip->txdmamode); - - dmaStreamEnable(spip->dmarx); - dmaStreamEnable(spip->dmatx); -} - -/** - * @brief Exchanges one frame using a polled wait. - * @details This synchronous function exchanges one frame using a polled - * synchronization method. This function is useful when exchanging - * small amount of data on high speed channels, usually in this - * situation is much more efficient just wait for completion using - * polling than suspending the thread waiting for an interrupt. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] frame the data frame to send over the SPI bus - * @return The received data frame from the SPI bus. - */ -uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) { - - spip->spi->DR = frame; - while ((spip->spi->SR & SPI_SR_RXNE) == 0) - ; - return spip->spi->DR; -} - -#endif /* HAL_USE_SPI */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/SPIv1/spi_lld.h b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/SPIv1/spi_lld.h deleted file mode 100644 index 5fbf29d607..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/SPIv1/spi_lld.h +++ /dev/null @@ -1,543 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/SPIv1/spi_lld.h - * @brief STM32 SPI subsystem low level driver header. - * - * @addtogroup SPI - * @{ - */ - -#ifndef _SPI_LLD_H_ -#define _SPI_LLD_H_ - -#if HAL_USE_SPI || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief SPI1 driver enable switch. - * @details If set to @p TRUE the support for SPI1 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SPI_USE_SPI1) || defined(__DOXYGEN__) -#define STM32_SPI_USE_SPI1 FALSE -#endif - -/** - * @brief SPI2 driver enable switch. - * @details If set to @p TRUE the support for SPI2 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SPI_USE_SPI2) || defined(__DOXYGEN__) -#define STM32_SPI_USE_SPI2 FALSE -#endif - -/** - * @brief SPI3 driver enable switch. - * @details If set to @p TRUE the support for SPI3 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SPI_USE_SPI3) || defined(__DOXYGEN__) -#define STM32_SPI_USE_SPI3 FALSE -#endif - -/** - * @brief SPI4 driver enable switch. - * @details If set to @p TRUE the support for SPI4 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SPI_USE_SPI4) || defined(__DOXYGEN__) -#define STM32_SPI_USE_SPI4 FALSE -#endif - -/** - * @brief SPI5 driver enable switch. - * @details If set to @p TRUE the support for SPI5 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SPI_USE_SPI5) || defined(__DOXYGEN__) -#define STM32_SPI_USE_SPI5 FALSE -#endif - -/** - * @brief SPI6 driver enable switch. - * @details If set to @p TRUE the support for SPI6 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SPI_USE_SPI6) || defined(__DOXYGEN__) -#define STM32_SPI_USE_SPI6 FALSE -#endif - -/** - * @brief SPI1 interrupt priority level setting. - */ -#if !defined(STM32_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI1_IRQ_PRIORITY 10 -#endif - -/** - * @brief SPI2 interrupt priority level setting. - */ -#if !defined(STM32_SPI_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI2_IRQ_PRIORITY 10 -#endif - -/** - * @brief SPI3 interrupt priority level setting. - */ -#if !defined(STM32_SPI_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI3_IRQ_PRIORITY 10 -#endif - -/** - * @brief SPI4 interrupt priority level setting. - */ -#if !defined(STM32_SPI_SPI4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI4_IRQ_PRIORITY 10 -#endif - -/** - * @brief SPI5 interrupt priority level setting. - */ -#if !defined(STM32_SPI_SPI5_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI5_IRQ_PRIORITY 10 -#endif - -/** - * @brief SPI6 interrupt priority level setting. - */ -#if !defined(STM32_SPI_SPI6_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI6_IRQ_PRIORITY 10 -#endif - -/** - * @brief SPI1 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA streams but - * because of the streams ordering the RX stream has always priority - * over the TX stream. - */ -#if !defined(STM32_SPI_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#endif - -/** - * @brief SPI2 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA streams but - * because of the streams ordering the RX stream has always priority - * over the TX stream. - */ -#if !defined(STM32_SPI_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI2_DMA_PRIORITY 1 -#endif - -/** - * @brief SPI3 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA streams but - * because of the streams ordering the RX stream has always priority - * over the TX stream. - */ -#if !defined(STM32_SPI_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI3_DMA_PRIORITY 1 -#endif - -/** - * @brief SPI4 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA streams but - * because of the streams ordering the RX stream has always priority - * over the TX stream. - */ -#if !defined(STM32_SPI_SPI4_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI4_DMA_PRIORITY 1 -#endif - -/** - * @brief SPI5 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA streams but - * because of the streams ordering the RX stream has always priority - * over the TX stream. - */ -#if !defined(STM32_SPI_SPI5_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI5_DMA_PRIORITY 1 -#endif - -/** - * @brief SPI6 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA streams but - * because of the streams ordering the RX stream has always priority - * over the TX stream. - */ -#if !defined(STM32_SPI_SPI6_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI6_DMA_PRIORITY 1 -#endif - -/** - * @brief SPI DMA error hook. - */ -#if !defined(STM32_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__) -#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_SPI_USE_SPI1 && !STM32_HAS_SPI1 -#error "SPI1 not present in the selected device" -#endif - -#if STM32_SPI_USE_SPI2 && !STM32_HAS_SPI2 -#error "SPI2 not present in the selected device" -#endif - -#if STM32_SPI_USE_SPI3 && !STM32_HAS_SPI3 -#error "SPI3 not present in the selected device" -#endif - -#if STM32_SPI_USE_SPI4 && !STM32_HAS_SPI4 -#error "SPI4 not present in the selected device" -#endif - -#if STM32_SPI_USE_SPI5 && !STM32_HAS_SPI5 -#error "SPI5 not present in the selected device" -#endif - -#if STM32_SPI_USE_SPI6 && !STM32_HAS_SPI6 -#error "SPI6 not present in the selected device" -#endif - -#if !STM32_SPI_USE_SPI1 && !STM32_SPI_USE_SPI2 && !STM32_SPI_USE_SPI3 && \ - !STM32_SPI_USE_SPI4 && !STM32_SPI_USE_SPI5 && !STM32_SPI_USE_SPI6 -#error "SPI driver activated but no SPI peripheral assigned" -#endif - -#if STM32_SPI_USE_SPI1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SPI1" -#endif - -#if STM32_SPI_USE_SPI2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SPI2" -#endif - -#if STM32_SPI_USE_SPI3 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SPI3" -#endif - -#if STM32_SPI_USE_SPI4 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI4_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SPI4" -#endif - -#if STM32_SPI_USE_SPI5 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI5_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SPI5" -#endif - -#if STM32_SPI_USE_SPI6 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI6_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SPI6" -#endif - -#if STM32_SPI_USE_SPI1 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI1_DMA_PRIORITY) -#error "Invalid DMA priority assigned to SPI1" -#endif - -#if STM32_SPI_USE_SPI2 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI2_DMA_PRIORITY) -#error "Invalid DMA priority assigned to SPI2" -#endif - -#if STM32_SPI_USE_SPI3 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI3_DMA_PRIORITY) -#error "Invalid DMA priority assigned to SPI3" -#endif - -#if STM32_SPI_USE_SPI4 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI4_DMA_PRIORITY) -#error "Invalid DMA priority assigned to SPI4" -#endif - -#if STM32_SPI_USE_SPI5 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI5_DMA_PRIORITY) -#error "Invalid DMA priority assigned to SPI5" -#endif - -#if STM32_SPI_USE_SPI6 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI6_DMA_PRIORITY) -#error "Invalid DMA priority assigned to SPI6" -#endif - -/* The following checks are only required when there is a DMA able to - reassign streams to different channels.*/ -#if STM32_ADVANCED_DMA -/* Check on the presence of the DMA streams settings in mcuconf.h.*/ -#if STM32_SPI_USE_SPI1 && (!defined(STM32_SPI_SPI1_RX_DMA_STREAM) || \ - !defined(STM32_SPI_SPI1_TX_DMA_STREAM)) -#error "SPI1 DMA streams not defined" -#endif - -#if STM32_SPI_USE_SPI2 && (!defined(STM32_SPI_SPI2_RX_DMA_STREAM) || \ - !defined(STM32_SPI_SPI2_TX_DMA_STREAM)) -#error "SPI2 DMA streams not defined" -#endif - -#if STM32_SPI_USE_SPI3 && (!defined(STM32_SPI_SPI3_RX_DMA_STREAM) || \ - !defined(STM32_SPI_SPI3_TX_DMA_STREAM)) -#error "SPI3 DMA streams not defined" -#endif - -#if STM32_SPI_USE_SPI4 && (!defined(STM32_SPI_SPI4_RX_DMA_STREAM) || \ - !defined(STM32_SPI_SPI4_TX_DMA_STREAM)) -#error "SPI4 DMA streams not defined" -#endif - -#if STM32_SPI_USE_SPI5 && (!defined(STM32_SPI_SPI5_RX_DMA_STREAM) || \ - !defined(STM32_SPI_SPI5_TX_DMA_STREAM)) -#error "SPI5 DMA streams not defined" -#endif - -#if STM32_SPI_USE_SPI6 && (!defined(STM32_SPI_SPI6_RX_DMA_STREAM) || \ - !defined(STM32_SPI_SPI6_TX_DMA_STREAM)) -#error "SPI6 DMA streams not defined" -#endif - -/* Check on the validity of the assigned DMA channels.*/ -#if STM32_SPI_USE_SPI1 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_RX_DMA_STREAM, STM32_SPI1_RX_DMA_MSK) -#error "invalid DMA stream associated to SPI1 RX" -#endif - -#if STM32_SPI_USE_SPI1 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_TX_DMA_STREAM, STM32_SPI1_TX_DMA_MSK) -#error "invalid DMA stream associated to SPI1 TX" -#endif - -#if STM32_SPI_USE_SPI2 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI2_RX_DMA_STREAM, STM32_SPI2_RX_DMA_MSK) -#error "invalid DMA stream associated to SPI2 RX" -#endif - -#if STM32_SPI_USE_SPI2 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI2_TX_DMA_STREAM, STM32_SPI2_TX_DMA_MSK) -#error "invalid DMA stream associated to SPI2 TX" -#endif - -#if STM32_SPI_USE_SPI3 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI3_RX_DMA_STREAM, STM32_SPI3_RX_DMA_MSK) -#error "invalid DMA stream associated to SPI3 RX" -#endif - -#if STM32_SPI_USE_SPI3 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI3_TX_DMA_STREAM, STM32_SPI3_TX_DMA_MSK) -#error "invalid DMA stream associated to SPI3 TX" -#endif - -#if STM32_SPI_USE_SPI4 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI4_RX_DMA_STREAM, STM32_SPI4_RX_DMA_MSK) -#error "invalid DMA stream associated to SPI4 RX" -#endif - -#if STM32_SPI_USE_SPI4 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI4_TX_DMA_STREAM, STM32_SPI4_TX_DMA_MSK) -#error "invalid DMA stream associated to SPI4 TX" -#endif - -#if STM32_SPI_USE_SPI5 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI5_RX_DMA_STREAM, STM32_SPI5_RX_DMA_MSK) -#error "invalid DMA stream associated to SPI5 RX" -#endif - -#if STM32_SPI_USE_SPI5 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI5_TX_DMA_STREAM, STM32_SPI5_TX_DMA_MSK) -#error "invalid DMA stream associated to SPI5 TX" -#endif - -#if STM32_SPI_USE_SPI6 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI6_RX_DMA_STREAM, STM32_SPI6_RX_DMA_MSK) -#error "invalid DMA stream associated to SPI6 RX" -#endif - -#if STM32_SPI_USE_SPI6 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI6_TX_DMA_STREAM, STM32_SPI6_TX_DMA_MSK) -#error "invalid DMA stream associated to SPI6 TX" -#endif -#endif /* STM32_ADVANCED_DMA */ - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a structure representing an SPI driver. - */ -typedef struct SPIDriver SPIDriver; - -/** - * @brief SPI notification callback type. - * - * @param[in] spip pointer to the @p SPIDriver object triggering the - * callback - */ -typedef void (*spicallback_t)(SPIDriver *spip); - -/** - * @brief Driver configuration structure. - */ -typedef struct { - /** - * @brief Operation complete callback or @p NULL. - */ - spicallback_t end_cb; - /* End of the mandatory fields.*/ - /** - * @brief The chip select line port. - */ - ioportid_t ssport; - /** - * @brief The chip select line pad number. - */ - uint16_t sspad; - /** - * @brief SPI initialization data. - */ - uint16_t cr1; -} SPIConfig; - -/** - * @brief Structure representing an SPI driver. - */ -struct SPIDriver { - /** - * @brief Driver state. - */ - spistate_t state; - /** - * @brief Current configuration data. - */ - const SPIConfig *config; -#if SPI_USE_WAIT || defined(__DOXYGEN__) - /** - * @brief Waiting thread. - */ - thread_reference_t thread; -#endif /* SPI_USE_WAIT */ -#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the bus. - */ - mutex_t mutex; -#endif /* SPI_USE_MUTUAL_EXCLUSION */ -#if defined(SPI_DRIVER_EXT_FIELDS) - SPI_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the SPIx registers block. - */ - SPI_TypeDef *spi; - /** - * @brief Receive DMA stream. - */ - const stm32_dma_stream_t *dmarx; - /** - * @brief Transmit DMA stream. - */ - const stm32_dma_stream_t *dmatx; - /** - * @brief RX DMA mode bit mask. - */ - uint32_t rxdmamode; - /** - * @brief TX DMA mode bit mask. - */ - uint32_t txdmamode; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_SPI_USE_SPI1 && !defined(__DOXYGEN__) -extern SPIDriver SPID1; -#endif - -#if STM32_SPI_USE_SPI2 && !defined(__DOXYGEN__) -extern SPIDriver SPID2; -#endif - -#if STM32_SPI_USE_SPI3 && !defined(__DOXYGEN__) -extern SPIDriver SPID3; -#endif - -#if STM32_SPI_USE_SPI4 && !defined(__DOXYGEN__) -extern SPIDriver SPID4; -#endif - -#if STM32_SPI_USE_SPI5 && !defined(__DOXYGEN__) -extern SPIDriver SPID5; -#endif - -#if STM32_SPI_USE_SPI6 && !defined(__DOXYGEN__) -extern SPIDriver SPID6; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void spi_lld_init(void); - void spi_lld_start(SPIDriver *spip); - void spi_lld_stop(SPIDriver *spip); - void spi_lld_select(SPIDriver *spip); - void spi_lld_unselect(SPIDriver *spip); - void spi_lld_ignore(SPIDriver *spip, size_t n); - void spi_lld_exchange(SPIDriver *spip, size_t n, - const void *txbuf, void *rxbuf); - void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); - void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); - uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_SPI */ - -#endif /* _SPI_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/SPIv2/i2s_lld.c b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/SPIv2/i2s_lld.c deleted file mode 100644 index 103f35fa7f..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/SPIv2/i2s_lld.c +++ /dev/null @@ -1,577 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file i2s_lld.c - * @brief STM32 I2S subsystem low level driver source. - * - * @addtogroup I2S - * @{ - */ - -#include "hal.h" - -#if HAL_USE_I2S || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define I2S1_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_I2S_SPI1_RX_DMA_STREAM, \ - STM32_SPI1_RX_DMA_CHN) - -#define I2S1_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_I2S_SPI1_TX_DMA_STREAM, \ - STM32_SPI1_TX_DMA_CHN) - -#define I2S2_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_I2S_SPI2_RX_DMA_STREAM, \ - STM32_SPI2_RX_DMA_CHN) - -#define I2S2_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_I2S_SPI2_TX_DMA_STREAM, \ - STM32_SPI2_TX_DMA_CHN) - -#define I2S3_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_I2S_SPI3_RX_DMA_STREAM, \ - STM32_SPI3_RX_DMA_CHN) - -#define I2S3_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_I2S_SPI3_TX_DMA_STREAM, \ - STM32_SPI3_TX_DMA_CHN) - -/* - * Static I2S settings for I2S1. - */ -#if !STM32_I2S_IS_MASTER(STM32_I2S_SPI1_MODE) -#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE) -#define STM32_I2S1_CFGR_CFG 0 -#endif -#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE) -#define STM32_I2S1_CFGR_CFG SPI_I2SCFGR_I2SCFG_0 -#endif -#else /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI1_MODE) */ -#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE) -#define STM32_I2S1_CFGR_CFG SPI_I2SCFGR_I2SCFG_1 -#endif -#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE) -#define STM32_I2S1_CFGR_CFG (SPI_I2SCFGR_I2SCFG_1 | \ - SPI_I2SCFGR_I2SCFG_0) -#endif -#endif /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI1_MODE) */ - -/* - * Static I2S settings for I2S2. - */ -#if !STM32_I2S_IS_MASTER(STM32_I2S_SPI2_MODE) -#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE) -#define STM32_I2S2_CFGR_CFG 0 -#endif -#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE) -#define STM32_I2S2_CFGR_CFG SPI_I2SCFGR_I2SCFG_0 -#endif -#else /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI2_MODE) */ -#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE) -#define STM32_I2S2_CFGR_CFG SPI_I2SCFGR_I2SCFG_1 -#endif -#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE) -#define STM32_I2S2_CFGR_CFG (SPI_I2SCFGR_I2SCFG_1 | \ - SPI_I2SCFGR_I2SCFG_0) -#endif -#endif /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI2_MODE) */ - -/* - * Static I2S settings for I2S3. - */ -#if !STM32_I2S_IS_MASTER(STM32_I2S_SPI3_MODE) -#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE) -#define STM32_I2S3_CFGR_CFG 0 -#endif -#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE) -#define STM32_I2S3_CFGR_CFG SPI_I2SCFGR_I2SCFG_0 -#endif -#else /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI3_MODE) */ -#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE) -#define STM32_I2S3_CFGR_CFG SPI_I2SCFGR_I2SCFG_1 -#endif -#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE) -#define STM32_I2S3_CFGR_CFG (SPI_I2SCFGR_I2SCFG_1 | \ - SPI_I2SCFGR_I2SCFG_0) -#endif -#endif /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI3_MODE) */ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief I2S1 driver identifier.*/ -#if STM32_I2S_USE_SPI1 || defined(__DOXYGEN__) -I2SDriver I2SD1; -#endif - -/** @brief I2S2 driver identifier.*/ -#if STM32_I2S_USE_SPI2 || defined(__DOXYGEN__) -I2SDriver I2SD2; -#endif - -/** @brief I2S3 driver identifier.*/ -#if STM32_I2S_USE_SPI3 || defined(__DOXYGEN__) -I2SDriver I2SD3; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE) || \ - STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE) || \ - STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE) || defined(__DOXYGEN__) -/** - * @brief Shared end-of-rx service routine. - * - * @param[in] i2sp pointer to the @p I2SDriver object - * @param[in] flags pre-shifted content of the ISR register - */ -static void i2s_lld_serve_rx_interrupt(I2SDriver *i2sp, uint32_t flags) { - - (void)i2sp; - - /* DMA errors handling.*/ -#if defined(STM32_I2S_DMA_ERROR_HOOK) - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - STM32_I2S_DMA_ERROR_HOOK(i2sp); - } -#endif - - /* Callbacks handling, note it is portable code defined in the high - level driver.*/ - if ((flags & STM32_DMA_ISR_TCIF) != 0) { - /* Transfer complete processing.*/ - _i2s_isr_full_code(i2sp); - } - else if ((flags & STM32_DMA_ISR_HTIF) != 0) { - /* Half transfer processing.*/ - _i2s_isr_half_code(i2sp); - } -} -#endif - -#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE) || \ - STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE) || \ - STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE) || defined(__DOXYGEN__) -/** - * @brief Shared end-of-tx service routine. - * - * @param[in] i2sp pointer to the @p I2SDriver object - * @param[in] flags pre-shifted content of the ISR register - */ -static void i2s_lld_serve_tx_interrupt(I2SDriver *i2sp, uint32_t flags) { - - (void)i2sp; - - /* DMA errors handling.*/ -#if defined(STM32_I2S_DMA_ERROR_HOOK) - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - STM32_I2S_DMA_ERROR_HOOK(i2sp); - } -#endif - - /* Callbacks handling, note it is portable code defined in the high - level driver.*/ - if ((flags & STM32_DMA_ISR_TCIF) != 0) { - /* Transfer complete processing.*/ - _i2s_isr_full_code(i2sp); - } - else if ((flags & STM32_DMA_ISR_HTIF) != 0) { - /* Half transfer processing.*/ - _i2s_isr_half_code(i2sp); - } -} -#endif - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level I2S driver initialization. - * - * @notapi - */ -void i2s_lld_init(void) { - -#if STM32_I2S_USE_SPI1 - i2sObjectInit(&I2SD1); - I2SD1.spi = SPI1; - I2SD1.cfg = STM32_I2S1_CFGR_CFG; -#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE) - I2SD1.dmarx = STM32_DMA_STREAM(STM32_I2S_SPI1_RX_DMA_STREAM); - I2SD1.rxdmamode = STM32_DMA_CR_CHSEL(I2S1_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_I2S_SPI1_DMA_PRIORITY) | - STM32_DMA_CR_PSIZE_HWORD | - STM32_DMA_CR_MSIZE_HWORD | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_MINC | - STM32_DMA_CR_CIRC | - STM32_DMA_CR_HTIE | - STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; -#else - I2SD1.dmarx = NULL; - I2SD1.rxdmamode = 0; -#endif -#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE) - I2SD1.dmatx = STM32_DMA_STREAM(STM32_I2S_SPI1_TX_DMA_STREAM); - I2SD1.txdmamode = STM32_DMA_CR_CHSEL(I2S1_TX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_I2S_SPI1_DMA_PRIORITY) | - STM32_DMA_CR_PSIZE_HWORD | - STM32_DMA_CR_MSIZE_HWORD | - STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_MINC | - STM32_DMA_CR_CIRC | - STM32_DMA_CR_HTIE | - STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; -#else - I2SD1.dmatx = NULL; - I2SD1.txdmamode = 0; -#endif -#endif - -#if STM32_I2S_USE_SPI2 - i2sObjectInit(&I2SD2); - I2SD2.spi = SPI2; - I2SD2.cfg = STM32_I2S2_CFGR_CFG; -#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE) - I2SD2.dmarx = STM32_DMA_STREAM(STM32_I2S_SPI2_RX_DMA_STREAM); - I2SD2.rxdmamode = STM32_DMA_CR_CHSEL(I2S2_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_I2S_SPI2_DMA_PRIORITY) | - STM32_DMA_CR_PSIZE_HWORD | - STM32_DMA_CR_MSIZE_HWORD | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_MINC | - STM32_DMA_CR_CIRC | - STM32_DMA_CR_HTIE | - STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; -#else - I2SD2.dmarx = NULL; - I2SD2.rxdmamode = 0; -#endif -#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE) - I2SD2.dmatx = STM32_DMA_STREAM(STM32_I2S_SPI2_TX_DMA_STREAM); - I2SD2.txdmamode = STM32_DMA_CR_CHSEL(I2S2_TX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_I2S_SPI2_DMA_PRIORITY) | - STM32_DMA_CR_PSIZE_HWORD | - STM32_DMA_CR_MSIZE_HWORD | - STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_MINC | - STM32_DMA_CR_CIRC | - STM32_DMA_CR_HTIE | - STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; -#else - I2SD2.dmatx = NULL; - I2SD2.txdmamode = 0; -#endif -#endif - -#if STM32_I2S_USE_SPI3 - i2sObjectInit(&I2SD3); - I2SD3.spi = SPI3; - I2SD3.cfg = STM32_I2S3_CFGR_CFG; -#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE) - I2SD3.dmarx = STM32_DMA_STREAM(STM32_I2S_SPI3_RX_DMA_STREAM); - I2SD3.rxdmamode = STM32_DMA_CR_CHSEL(I2S3_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_I2S_SPI3_DMA_PRIORITY) | - STM32_DMA_CR_PSIZE_HWORD | - STM32_DMA_CR_MSIZE_HWORD | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_MINC | - STM32_DMA_CR_CIRC | - STM32_DMA_CR_HTIE | - STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; -#else - I2SD3.dmarx = NULL; - I2SD3.rxdmamode = 0; -#endif -#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE) - I2SD3.dmatx = STM32_DMA_STREAM(STM32_I2S_SPI3_TX_DMA_STREAM); - I2SD3.txdmamode = STM32_DMA_CR_CHSEL(I2S3_TX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_I2S_SPI3_DMA_PRIORITY) | - STM32_DMA_CR_PSIZE_HWORD | - STM32_DMA_CR_MSIZE_HWORD | - STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_MINC | - STM32_DMA_CR_CIRC | - STM32_DMA_CR_HTIE | - STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; -#else - I2SD3.dmatx = NULL; - I2SD3.txdmamode = 0; -#endif -#endif -} - -/** - * @brief Configures and activates the I2S peripheral. - * - * @param[in] i2sp pointer to the @p I2SDriver object - * - * @notapi - */ -void i2s_lld_start(I2SDriver *i2sp) { - - /* If in stopped state then enables the SPI and DMA clocks.*/ - if (i2sp->state == I2S_STOP) { - -#if STM32_I2S_USE_SPI1 - if (&I2SD1 == i2sp) { - bool b; - - /* Enabling I2S unit clock.*/ - rccEnableSPI1(FALSE); - -#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE) - b = dmaStreamAllocate(i2sp->dmarx, - STM32_I2S_SPI1_IRQ_PRIORITY, - (stm32_dmaisr_t)i2s_lld_serve_rx_interrupt, - (void *)i2sp); - osalDbgAssert(!b, "stream already allocated"); - - /* CRs settings are done here because those never changes until - the driver is stopped.*/ - i2sp->spi->CR1 = 0; - i2sp->spi->CR2 = SPI_CR2_RXDMAEN; -#endif -#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE) - b = dmaStreamAllocate(i2sp->dmatx, - STM32_I2S_SPI1_IRQ_PRIORITY, - (stm32_dmaisr_t)i2s_lld_serve_tx_interrupt, - (void *)i2sp); - osalDbgAssert(!b, "stream already allocated"); - - /* CRs settings are done here because those never changes until - the driver is stopped.*/ - i2sp->spi->CR1 = 0; - i2sp->spi->CR2 = SPI_CR2_TXDMAEN; -#endif - } -#endif - -#if STM32_I2S_USE_SPI2 - if (&I2SD2 == i2sp) { - bool b; - - /* Enabling I2S unit clock.*/ - rccEnableSPI2(FALSE); - -#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE) - b = dmaStreamAllocate(i2sp->dmarx, - STM32_I2S_SPI2_IRQ_PRIORITY, - (stm32_dmaisr_t)i2s_lld_serve_rx_interrupt, - (void *)i2sp); - osalDbgAssert(!b, "stream already allocated"); - - /* CRs settings are done here because those never changes until - the driver is stopped.*/ - i2sp->spi->CR1 = 0; - i2sp->spi->CR2 = SPI_CR2_RXDMAEN; -#endif -#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE) - b = dmaStreamAllocate(i2sp->dmatx, - STM32_I2S_SPI2_IRQ_PRIORITY, - (stm32_dmaisr_t)i2s_lld_serve_tx_interrupt, - (void *)i2sp); - osalDbgAssert(!b, "stream already allocated"); - - /* CRs settings are done here because those never changes until - the driver is stopped.*/ - i2sp->spi->CR1 = 0; - i2sp->spi->CR2 = SPI_CR2_TXDMAEN; -#endif - } -#endif - -#if STM32_I2S_USE_SPI3 - if (&I2SD3 == i2sp) { - bool b; - - /* Enabling I2S unit clock.*/ - rccEnableSPI3(FALSE); - -#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE) - b = dmaStreamAllocate(i2sp->dmarx, - STM32_I2S_SPI3_IRQ_PRIORITY, - (stm32_dmaisr_t)i2s_lld_serve_rx_interrupt, - (void *)i2sp); - osalDbgAssert(!b, "stream already allocated"); - - /* CRs settings are done here because those never changes until - the driver is stopped.*/ - i2sp->spi->CR1 = 0; - i2sp->spi->CR2 = SPI_CR2_RXDMAEN; -#endif -#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE) - b = dmaStreamAllocate(i2sp->dmatx, - STM32_I2S_SPI3_IRQ_PRIORITY, - (stm32_dmaisr_t)i2s_lld_serve_tx_interrupt, - (void *)i2sp); - osalDbgAssert(!b, "stream already allocated"); - - /* CRs settings are done here because those never changes until - the driver is stopped.*/ - i2sp->spi->CR1 = 0; - i2sp->spi->CR2 = SPI_CR2_TXDMAEN; -#endif - } -#endif - } - - /* I2S (re)configuration.*/ - i2sp->spi->I2SPR = i2sp->config->i2spr; - i2sp->spi->I2SCFGR = i2sp->config->i2scfgr | i2sp->cfg | SPI_I2SCFGR_I2SMOD; -} - -/** - * @brief Deactivates the I2S peripheral. - * - * @param[in] i2sp pointer to the @p I2SDriver object - * - * @notapi - */ -void i2s_lld_stop(I2SDriver *i2sp) { - - /* If in ready state then disables the SPI clock.*/ - if (i2sp->state == I2S_READY) { - - /* SPI disable.*/ - i2sp->spi->CR2 = 0; - if (NULL != i2sp->dmarx) - dmaStreamRelease(i2sp->dmarx); - if (NULL != i2sp->dmatx) - dmaStreamRelease(i2sp->dmatx); - -#if STM32_I2S_USE_SPI1 - if (&I2SD1 == i2sp) - rccDisableSPI1(FALSE); -#endif - -#if STM32_I2S_USE_SPI2 - if (&I2SD2 == i2sp) - rccDisableSPI2(FALSE); -#endif - -#if STM32_I2S_USE_SPI3 - if (&I2SD3 == i2sp) - rccDisableSPI3(FALSE); -#endif - } -} - -/** - * @brief Starts a I2S data exchange. - * - * @param[in] i2sp pointer to the @p I2SDriver object - * - * @notapi - */ -void i2s_lld_start_exchange(I2SDriver *i2sp) { - size_t size = i2sp->config->size; - - /* In 32 bit modes the DMA has to perform double operations because fetches - are always performed using 16 bit accesses. - DATLEN CHLEN SIZE - 00 (16) 0 (16) 16 - 00 (16) 1 (32) 16 - 01 (24) X 32 - 10 (32) X 32 - 11 (NA) X NA - */ - if ((i2sp->config->i2scfgr & SPI_I2SCFGR_DATLEN) != 0) - size *= 2; - - /* RX DMA setup.*/ - if (NULL != i2sp->dmarx) { - dmaStreamSetMode(i2sp->dmarx, i2sp->rxdmamode); - dmaStreamSetPeripheral(i2sp->dmarx, &i2sp->spi->DR); - dmaStreamSetMemory0(i2sp->dmarx, i2sp->config->rx_buffer); - dmaStreamSetTransactionSize(i2sp->dmarx, size); - dmaStreamEnable(i2sp->dmarx); - } - - /* TX DMA setup.*/ - if (NULL != i2sp->dmatx) { - dmaStreamSetMode(i2sp->dmatx, i2sp->txdmamode); - dmaStreamSetPeripheral(i2sp->dmatx, &i2sp->spi->DR); - dmaStreamSetMemory0(i2sp->dmatx, i2sp->config->tx_buffer); - dmaStreamSetTransactionSize(i2sp->dmatx, size); - dmaStreamEnable(i2sp->dmatx); - } - - /* Starting transfer.*/ - i2sp->spi->I2SCFGR |= SPI_I2SCFGR_I2SE; -} - -/** - * @brief Stops the ongoing data exchange. - * @details The ongoing data exchange, if any, is stopped, if the driver - * was not active the function does nothing. - * - * @param[in] i2sp pointer to the @p I2SDriver object - * - * @notapi - */ -void i2s_lld_stop_exchange(I2SDriver *i2sp) { - - /* Stop TX DMA, if enabled.*/ - if (NULL != i2sp->dmatx) { - dmaStreamDisable(i2sp->dmatx); - - /* From the RM: To switch off the I2S, by clearing I2SE, it is mandatory - to wait for TXE = 1 and BSY = 0.*/ - while ((i2sp->spi->SR & (SPI_SR_TXE | SPI_SR_BSY)) != SPI_SR_TXE) - ; - } - - /* Stop SPI/I2S peripheral.*/ - i2sp->spi->I2SCFGR &= ~SPI_I2SCFGR_I2SE; - - /* Stop RX DMA, if enabled.*/ - if (NULL != i2sp->dmarx) - dmaStreamDisable(i2sp->dmarx); -} - -#endif /* HAL_USE_I2S */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/SPIv2/i2s_lld.h b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/SPIv2/i2s_lld.h deleted file mode 100644 index 8b1d4965d7..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/SPIv2/i2s_lld.h +++ /dev/null @@ -1,432 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file i2s_lld.h - * @brief STM32 I2S subsystem low level driver header. - * - * @addtogroup I2S - * @{ - */ - -#ifndef _I2S_LLD_H_ -#define _I2S_LLD_H_ - -#if HAL_USE_I2S || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name Static I2S modes - * @{ - */ -#define STM32_I2S_MODE_SLAVE 0 -#define STM32_I2S_MODE_MASTER 1 -#define STM32_I2S_MODE_RX 2 -#define STM32_I2S_MODE_TX 4 -#define STM32_I2S_MODE_RXTX (STM32_I2S_MODE_RX | \ - STM32_I2S_MODE_TX) -/** @} */ - -/** - * @name Mode checks - * @{ - */ -#define STM32_I2S_IS_MASTER(mode) ((mode) & STM32_I2S_MODE_MASTER) -#define STM32_I2S_RX_ENABLED(mode) ((mode) & STM32_I2S_MODE_RX) -#define STM32_I2S_TX_ENABLED(mode) ((mode) & STM32_I2S_MODE_TX) -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief I2S1 driver enable switch. - * @details If set to @p TRUE the support for I2S1 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_I2S_USE_SPI1) || defined(__DOXYGEN__) -#define STM32_I2S_USE_SPI1 FALSE -#endif - -/** - * @brief I2S2 driver enable switch. - * @details If set to @p TRUE the support for I2S2 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_I2S_USE_SPI2) || defined(__DOXYGEN__) -#define STM32_I2S_USE_SPI2 FALSE -#endif - -/** - * @brief I2S3 driver enable switch. - * @details If set to @p TRUE the support for I2S3 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_I2S_USE_SPI3) || defined(__DOXYGEN__) -#define STM32_I2S_USE_SPI3 FALSE -#endif - -/** - * @brief I2S1 mode. - */ -#if !defined(STM32_I2S_SPI1_MODE) || defined(__DOXYGEN__) -#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \ - STM32_I2S_MODE_RX) -#endif - -/** - * @brief I2S2 mode. - */ -#if !defined(STM32_I2S_SPI2_MODE) || defined(__DOXYGEN__) -#define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_MASTER | \ - STM32_I2S_MODE_RX) -#endif - -/** - * @brief I2S3 mode. - */ -#if !defined(STM32_I2S_SPI3_MODE) || defined(__DOXYGEN__) -#define STM32_I2S_SPI3_MODE (STM32_I2S_MODE_MASTER | \ - STM32_I2S_MODE_RX) -#endif - -/** - * @brief I2S1 interrupt priority level setting. - */ -#if !defined(STM32_I2S_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2S_SPI1_IRQ_PRIORITY 10 -#endif - -/** - * @brief I2S2 interrupt priority level setting. - */ -#if !defined(STM32_I2S_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2S_SPI2_IRQ_PRIORITY 10 -#endif - -/** - * @brief I2S3 interrupt priority level setting. - */ -#if !defined(STM32_I2S_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2S_SPI3_IRQ_PRIORITY 10 -#endif - -/** - * @brief I2S1 DMA priority (0..3|lowest..highest). - */ -#if !defined(STM32_I2S_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2S_SPI1_DMA_PRIORITY 1 -#endif - -/** - * @brief I2S2 DMA priority (0..3|lowest..highest). - */ -#if !defined(STM32_I2S_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2S_SPI2_DMA_PRIORITY 1 -#endif - -/** - * @brief I2S3 DMA priority (0..3|lowest..highest). - */ -#if !defined(STM32_I2S_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2S_SPI3_DMA_PRIORITY 1 -#endif - -/** - * @brief I2S DMA error hook. - */ -#if !defined(STM32_I2S_DMA_ERROR_HOOK) || defined(__DOXYGEN__) -#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_I2S_USE_SPI1 && !STM32_SPI1_SUPPORTS_I2S -#error "SPI1 does not support I2S mode" -#endif - -#if STM32_I2S_USE_SPI2 && !STM32_SPI2_SUPPORTS_I2S -#error "SPI2 does not support I2S mode" -#endif - -#if STM32_I2S_USE_SPI3 && !STM32_SPI3_SUPPORTS_I2S -#error "SPI3 does not support I2S mode" -#endif - -#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE) && \ - STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE) -#error "I2S1 RX and TX mode not supported in this driver implementation" -#endif - -#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE) && \ - STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE) -#error "I2S2 RX and TX mode not supported in this driver implementation" -#endif - -#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE) && \ - STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE) -#error "I2S3 RX and TX mode not supported in this driver implementation" -#endif - -#if STM32_I2S_USE_SPI1 && !STM32_HAS_SPI1 -#error "SPI1 not present in the selected device" -#endif - -#if STM32_I2S_USE_SPI2 && !STM32_HAS_SPI2 -#error "SPI2 not present in the selected device" -#endif - -#if STM32_I2S_USE_SPI3 && !STM32_HAS_SPI3 -#error "SPI3 not present in the selected device" -#endif - -#if !STM32_I2S_USE_SPI1 && !STM32_I2S_USE_SPI2 && !STM32_I2S_USE_SPI3 -#error "I2S driver activated but no SPI peripheral assigned" -#endif - -#if STM32_I2S_USE_SPI1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2S_SPI1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SPI1" -#endif - -#if STM32_I2S_USE_SPI2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2S_SPI2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SPI2" -#endif - -#if STM32_I2S_USE_SPI3 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2S_SPI3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SPI3" -#endif - -#if STM32_I2S_USE_SPI1 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_I2S_SPI1_DMA_PRIORITY) -#error "Invalid DMA priority assigned to SPI1" -#endif - -#if STM32_I2S_USE_SPI2 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_I2S_SPI2_DMA_PRIORITY) -#error "Invalid DMA priority assigned to SPI2" -#endif - -#if STM32_I2S_USE_SPI3 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_I2S_SPI3_DMA_PRIORITY) -#error "Invalid DMA priority assigned to SPI3" -#endif - -/* The following checks are only required when there is a DMA able to - reassign streams to different channels.*/ -#if STM32_ADVANCED_DMA -/* Check on the presence of the DMA streams settings in mcuconf.h.*/ -#if STM32_I2S_USE_SPI1 && (!defined(STM32_I2S_SPI1_RX_DMA_STREAM) || \ - !defined(STM32_I2S_SPI1_TX_DMA_STREAM)) -#error "SPI1 DMA streams not defined" -#endif - -#if STM32_I2S_USE_SPI2 && (!defined(STM32_I2S_SPI2_RX_DMA_STREAM) || \ - !defined(STM32_I2S_SPI2_TX_DMA_STREAM)) -#error "SPI2 DMA streams not defined" -#endif - -#if STM32_I2S_USE_SPI3 && (!defined(STM32_I2S_SPI3_RX_DMA_STREAM) || \ - !defined(STM32_I2S_SPI3_TX_DMA_STREAM)) -#error "SPI3 DMA streams not defined" -#endif - -/* Check on the validity of the assigned DMA channels.*/ -#if STM32_I2S_USE_SPI1 && \ - !STM32_DMA_IS_VALID_ID(STM32_I2S_SPI1_RX_DMA_STREAM, STM32_SPI1_RX_DMA_MSK) -#error "invalid DMA stream associated to SPI1 RX" -#endif - -#if STM32_I2S_USE_SPI1 && \ - !STM32_DMA_IS_VALID_ID(STM32_I2S_SPI1_TX_DMA_STREAM, STM32_SPI1_TX_DMA_MSK) -#error "invalid DMA stream associated to SPI1 TX" -#endif - -#if STM32_I2S_USE_SPI2 && \ - !STM32_DMA_IS_VALID_ID(STM32_I2S_SPI2_RX_DMA_STREAM, STM32_SPI2_RX_DMA_MSK) -#error "invalid DMA stream associated to SPI2 RX" -#endif - -#if STM32_I2S_USE_SPI2 && \ - !STM32_DMA_IS_VALID_ID(STM32_I2S_SPI2_TX_DMA_STREAM, STM32_SPI2_TX_DMA_MSK) -#error "invalid DMA stream associated to SPI2 TX" -#endif - -#if STM32_I2S_USE_SPI3 && \ - !STM32_DMA_IS_VALID_ID(STM32_I2S_SPI3_RX_DMA_STREAM, STM32_SPI3_RX_DMA_MSK) -#error "invalid DMA stream associated to SPI3 RX" -#endif - -#if STM32_I2S_USE_SPI3 && \ - !STM32_DMA_IS_VALID_ID(STM32_I2S_SPI3_TX_DMA_STREAM, STM32_SPI3_TX_DMA_MSK) -#error "invalid DMA stream associated to SPI3 TX" -#endif -#endif /* STM32_ADVANCED_DMA */ - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a structure representing an I2S driver. - */ -typedef struct I2SDriver I2SDriver; - -/** - * @brief I2S notification callback type. - * - * @param[in] i2sp pointer to the @p I2SDriver object - * @param[in] offset offset in buffers of the data to read/write - * @param[in] n number of samples to read/write - */ -typedef void (*i2scallback_t)(I2SDriver *i2sp, size_t offset, size_t n); - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief Transmission buffer pointer. - * @note Can be @p NULL if TX is not required. - */ - const void *tx_buffer; - /** - * @brief Receive buffer pointer. - * @note Can be @p NULL if RX is not required. - */ - void *rx_buffer; - /** - * @brief TX and RX buffers size as number of samples. - */ - size_t size; - /** - * @brief Callback function called during streaming. - */ - i2scallback_t end_cb; - /* End of the mandatory fields.*/ - /** - * @brief Configuration of the I2SCFGR register. - * @details See the STM32 reference manual, this register is used for - * the I2S configuration, the following bits must not be - * specified because handled directly by the driver: - * - I2SMOD - * - I2SE - * - I2SCFG - * . - */ - int16_t i2scfgr; - /** - * @brief Configuration of the I2SPR register. - * @details See the STM32 reference manual, this register is used for - * the I2S clock setup. - */ - int16_t i2spr; -} I2SConfig; - -/** - * @brief Structure representing an I2S driver. - */ -struct I2SDriver { - /** - * @brief Driver state. - */ - i2sstate_t state; - /** - * @brief Current configuration data. - */ - const I2SConfig *config; - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the SPIx registers block. - */ - SPI_TypeDef *spi; - /** - * @brief Calculated part of the I2SCFGR register. - */ - uint16_t cfg; - /** - * @brief Receive DMA stream or @p NULL. - */ - const stm32_dma_stream_t *dmarx; - /** - * @brief Transmit DMA stream or @p NULL. - */ - const stm32_dma_stream_t *dmatx; - /** - * @brief RX DMA mode bit mask. - */ - uint32_t rxdmamode; - /** - * @brief TX DMA mode bit mask. - */ - uint32_t txdmamode; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_I2S_USE_SPI1 && !defined(__DOXYGEN__) -extern I2SDriver I2SD1; -#endif - -#if STM32_I2S_USE_SPI2 && !defined(__DOXYGEN__) -extern I2SDriver I2SD2; -#endif - -#if STM32_I2S_USE_SPI3 && !defined(__DOXYGEN__) -extern I2SDriver I2SD3; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void i2s_lld_init(void); - void i2s_lld_start(I2SDriver *i2sp); - void i2s_lld_stop(I2SDriver *i2sp); - void i2s_lld_start_exchange(I2SDriver *i2sp); - void i2s_lld_stop_exchange(I2SDriver *i2sp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_I2S */ - -#endif /* _I2S_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/SPIv2/spi_lld.c b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/SPIv2/spi_lld.c deleted file mode 100644 index 7138e81946..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/SPIv2/spi_lld.c +++ /dev/null @@ -1,652 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/SPIv2/spi_lld.c - * @brief STM32 SPI subsystem low level driver source. - * - * @addtogroup SPI - * @{ - */ - -#include "hal.h" - -#if HAL_USE_SPI || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define SPI1_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI1_RX_DMA_STREAM, \ - STM32_SPI1_RX_DMA_CHN) - -#define SPI1_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI1_TX_DMA_STREAM, \ - STM32_SPI1_TX_DMA_CHN) - -#define SPI2_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI2_RX_DMA_STREAM, \ - STM32_SPI2_RX_DMA_CHN) - -#define SPI2_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI2_TX_DMA_STREAM, \ - STM32_SPI2_TX_DMA_CHN) - -#define SPI3_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI3_RX_DMA_STREAM, \ - STM32_SPI3_RX_DMA_CHN) - -#define SPI3_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI3_TX_DMA_STREAM, \ - STM32_SPI3_TX_DMA_CHN) - -#define SPI4_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI4_RX_DMA_STREAM, \ - STM32_SPI4_RX_DMA_CHN) - -#define SPI4_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI4_TX_DMA_STREAM, \ - STM32_SPI4_TX_DMA_CHN) - -#define SPI5_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI5_RX_DMA_STREAM, \ - STM32_SPI5_RX_DMA_CHN) - -#define SPI5_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI5_TX_DMA_STREAM, \ - STM32_SPI5_TX_DMA_CHN) - -#define SPI6_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI6_RX_DMA_STREAM, \ - STM32_SPI6_RX_DMA_CHN) - -#define SPI6_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI6_TX_DMA_STREAM, \ - STM32_SPI6_TX_DMA_CHN) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief SPI1 driver identifier.*/ -#if STM32_SPI_USE_SPI1 || defined(__DOXYGEN__) -SPIDriver SPID1; -#endif - -/** @brief SPI2 driver identifier.*/ -#if STM32_SPI_USE_SPI2 || defined(__DOXYGEN__) -SPIDriver SPID2; -#endif - -/** @brief SPI3 driver identifier.*/ -#if STM32_SPI_USE_SPI3 || defined(__DOXYGEN__) -SPIDriver SPID3; -#endif - -/** @brief SPI4 driver identifier.*/ -#if STM32_SPI_USE_SPI4 || defined(__DOXYGEN__) -SPIDriver SPID4; -#endif - -/** @brief SPI5 driver identifier.*/ -#if STM32_SPI_USE_SPI5 || defined(__DOXYGEN__) -SPIDriver SPID5; -#endif - -/** @brief SPI6 driver identifier.*/ -#if STM32_SPI_USE_SPI6 || defined(__DOXYGEN__) -SPIDriver SPID6; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -static const uint16_t dummytx = 0xFFFFU; -static uint16_t dummyrx; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Shared end-of-rx service routine. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] flags pre-shifted content of the ISR register - */ -static void spi_lld_serve_rx_interrupt(SPIDriver *spip, uint32_t flags) { - - /* DMA errors handling.*/ -#if defined(STM32_SPI_DMA_ERROR_HOOK) - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - STM32_SPI_DMA_ERROR_HOOK(spip); - } -#else - (void)flags; -#endif - - /* Stop everything.*/ - dmaStreamDisable(spip->dmatx); - dmaStreamDisable(spip->dmarx); - - /* Portable SPI ISR code defined in the high level driver, note, it is - a macro.*/ - _spi_isr_code(spip); -} - -/** - * @brief Shared end-of-tx service routine. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] flags pre-shifted content of the ISR register - */ -static void spi_lld_serve_tx_interrupt(SPIDriver *spip, uint32_t flags) { - - /* DMA errors handling.*/ -#if defined(STM32_SPI_DMA_ERROR_HOOK) - (void)spip; - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - STM32_SPI_DMA_ERROR_HOOK(spip); - } -#else - (void)spip; - (void)flags; -#endif -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level SPI driver initialization. - * - * @notapi - */ -void spi_lld_init(void) { - -#if STM32_SPI_USE_SPI1 - spiObjectInit(&SPID1); - SPID1.spi = SPI1; - SPID1.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI1_RX_DMA_STREAM); - SPID1.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI1_TX_DMA_STREAM); - SPID1.rxdmamode = STM32_DMA_CR_CHSEL(SPI1_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; - SPID1.txdmamode = STM32_DMA_CR_CHSEL(SPI1_TX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) | - STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; -#endif - -#if STM32_SPI_USE_SPI2 - spiObjectInit(&SPID2); - SPID2.spi = SPI2; - SPID2.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI2_RX_DMA_STREAM); - SPID2.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI2_TX_DMA_STREAM); - SPID2.rxdmamode = STM32_DMA_CR_CHSEL(SPI2_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; - SPID2.txdmamode = STM32_DMA_CR_CHSEL(SPI2_TX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) | - STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; -#endif - -#if STM32_SPI_USE_SPI3 - spiObjectInit(&SPID3); - SPID3.spi = SPI3; - SPID3.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI3_RX_DMA_STREAM); - SPID3.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI3_TX_DMA_STREAM); - SPID3.rxdmamode = STM32_DMA_CR_CHSEL(SPI3_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; - SPID3.txdmamode = STM32_DMA_CR_CHSEL(SPI3_TX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) | - STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; -#endif - -#if STM32_SPI_USE_SPI4 - spiObjectInit(&SPID4); - SPID4.spi = SPI4; - SPID4.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI4_RX_DMA_STREAM); - SPID4.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI4_TX_DMA_STREAM); - SPID4.rxdmamode = STM32_DMA_CR_CHSEL(SPI4_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI4_DMA_PRIORITY) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; - SPID4.txdmamode = STM32_DMA_CR_CHSEL(SPI4_TX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI4_DMA_PRIORITY) | - STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; -#endif - -#if STM32_SPI_USE_SPI5 - spiObjectInit(&SPID5); - SPID5.spi = SPI5; - SPID5.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI5_RX_DMA_STREAM); - SPID5.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI5_TX_DMA_STREAM); - SPID5.rxdmamode = STM32_DMA_CR_CHSEL(SPI5_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI5_DMA_PRIORITY) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; - SPID5.txdmamode = STM32_DMA_CR_CHSEL(SPI5_TX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI5_DMA_PRIORITY) | - STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; -#endif - -#if STM32_SPI_USE_SPI6 - spiObjectInit(&SPID6); - SPID6.spi = SPI6; - SPID6.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI6_RX_DMA_STREAM); - SPID6.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI6_TX_DMA_STREAM); - SPID6.rxdmamode = STM32_DMA_CR_CHSEL(SPI6_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI6_DMA_PRIORITY) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; - SPID6.txdmamode = STM32_DMA_CR_CHSEL(SPI6_TX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI6_DMA_PRIORITY) | - STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; -#endif -} - -/** - * @brief Configures and activates the SPI peripheral. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_start(SPIDriver *spip) { - uint32_t ds; - - /* If in stopped state then enables the SPI and DMA clocks.*/ - if (spip->state == SPI_STOP) { -#if STM32_SPI_USE_SPI1 - if (&SPID1 == spip) { - bool b; - b = dmaStreamAllocate(spip->dmarx, - STM32_SPI_SPI1_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, - (void *)spip); - osalDbgAssert(!b, "stream already allocated"); - b = dmaStreamAllocate(spip->dmatx, - STM32_SPI_SPI1_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, - (void *)spip); - osalDbgAssert(!b, "stream already allocated"); - rccEnableSPI1(FALSE); - } -#endif -#if STM32_SPI_USE_SPI2 - if (&SPID2 == spip) { - bool b; - b = dmaStreamAllocate(spip->dmarx, - STM32_SPI_SPI2_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, - (void *)spip); - osalDbgAssert(!b, "stream already allocated"); - b = dmaStreamAllocate(spip->dmatx, - STM32_SPI_SPI2_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, - (void *)spip); - osalDbgAssert(!b, "stream already allocated"); - rccEnableSPI2(FALSE); - } -#endif -#if STM32_SPI_USE_SPI3 - if (&SPID3 == spip) { - bool b; - b = dmaStreamAllocate(spip->dmarx, - STM32_SPI_SPI3_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, - (void *)spip); - osalDbgAssert(!b, "stream already allocated"); - b = dmaStreamAllocate(spip->dmatx, - STM32_SPI_SPI3_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, - (void *)spip); - osalDbgAssert(!b, "stream already allocated"); - rccEnableSPI3(FALSE); - } -#endif -#if STM32_SPI_USE_SPI4 - if (&SPID4 == spip) { - bool b; - b = dmaStreamAllocate(spip->dmarx, - STM32_SPI_SPI4_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, - (void *)spip); - osalDbgAssert(!b, "stream already allocated"); - b = dmaStreamAllocate(spip->dmatx, - STM32_SPI_SPI4_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, - (void *)spip); - osalDbgAssert(!b, "stream already allocated"); - rccEnableSPI4(FALSE); - } -#endif -#if STM32_SPI_USE_SPI5 - if (&SPID5 == spip) { - bool b; - b = dmaStreamAllocate(spip->dmarx, - STM32_SPI_SPI5_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, - (void *)spip); - osalDbgAssert(!b, "stream already allocated"); - b = dmaStreamAllocate(spip->dmatx, - STM32_SPI_SPI5_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, - (void *)spip); - osalDbgAssert(!b, "stream already allocated"); - rccEnableSPI5(FALSE); - } -#endif -#if STM32_SPI_USE_SPI6 - if (&SPID6 == spip) { - bool b; - b = dmaStreamAllocate(spip->dmarx, - STM32_SPI_SPI6_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, - (void *)spip); - osalDbgAssert(!b, "stream already allocated"); - b = dmaStreamAllocate(spip->dmatx, - STM32_SPI_SPI6_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, - (void *)spip); - osalDbgAssert(!b, "stream already allocated"); - rccEnableSPI6(FALSE); - } -#endif - - /* DMA setup.*/ - dmaStreamSetPeripheral(spip->dmarx, &spip->spi->DR); - dmaStreamSetPeripheral(spip->dmatx, &spip->spi->DR); - } - - /* Configuration-specific DMA setup.*/ - ds = spip->config->cr2 & SPI_CR2_DS; - if (!ds || (ds <= (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0))) { - /* Frame width is 8 bits or smaller.*/ - spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) | - STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE; - spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) | - STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE; - } - else { - /* Frame width is larger than 8 bits.*/ - spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) | - STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; - spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) | - STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; - } - - /* SPI setup and enable.*/ - spip->spi->CR1 = 0; - spip->spi->CR1 = spip->config->cr1 | SPI_CR1_MSTR; - spip->spi->CR2 = spip->config->cr2 | SPI_CR2_FRXTH | SPI_CR2_SSOE | - SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN; - spip->spi->CR1 |= SPI_CR1_SPE; -} - -/** - * @brief Deactivates the SPI peripheral. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_stop(SPIDriver *spip) { - - /* If in ready state then disables the SPI clock.*/ - if (spip->state == SPI_READY) { - - /* SPI disable.*/ - spip->spi->CR1 = 0; - spip->spi->CR2 = 0; - dmaStreamRelease(spip->dmarx); - dmaStreamRelease(spip->dmatx); - -#if STM32_SPI_USE_SPI1 - if (&SPID1 == spip) - rccDisableSPI1(FALSE); -#endif -#if STM32_SPI_USE_SPI2 - if (&SPID2 == spip) - rccDisableSPI2(FALSE); -#endif -#if STM32_SPI_USE_SPI3 - if (&SPID3 == spip) - rccDisableSPI3(FALSE); -#endif -#if STM32_SPI_USE_SPI4 - if (&SPID4 == spip) - rccDisableSPI4(FALSE); -#endif -#if STM32_SPI_USE_SPI5 - if (&SPID5 == spip) - rccDisableSPI5(FALSE); -#endif -#if STM32_SPI_USE_SPI6 - if (&SPID6 == spip) - rccDisableSPI6(FALSE); -#endif - } -} - -/** - * @brief Asserts the slave select signal and prepares for transfers. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_select(SPIDriver *spip) { - - palClearPad(spip->config->ssport, spip->config->sspad); -} - -/** - * @brief Deasserts the slave select signal. - * @details The previously selected peripheral is unselected. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_unselect(SPIDriver *spip) { - - palSetPad(spip->config->ssport, spip->config->sspad); -} - -/** - * @brief Ignores data on the SPI bus. - * @details This asynchronous function starts the transmission of a series of - * idle words on the SPI bus and ignores the received data. - * @post At the end of the operation the configured callback is invoked. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be ignored - * - * @notapi - */ -void spi_lld_ignore(SPIDriver *spip, size_t n) { - - dmaStreamSetMemory0(spip->dmarx, &dummyrx); - dmaStreamSetTransactionSize(spip->dmarx, n); - dmaStreamSetMode(spip->dmarx, spip->rxdmamode); - - dmaStreamSetMemory0(spip->dmatx, &dummytx); - dmaStreamSetTransactionSize(spip->dmatx, n); - dmaStreamSetMode(spip->dmatx, spip->txdmamode); - - dmaStreamEnable(spip->dmarx); - dmaStreamEnable(spip->dmatx); -} - -/** - * @brief Exchanges data on the SPI bus. - * @details This asynchronous function starts a simultaneous transmit/receive - * operation. - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be exchanged - * @param[in] txbuf the pointer to the transmit buffer - * @param[out] rxbuf the pointer to the receive buffer - * - * @notapi - */ -void spi_lld_exchange(SPIDriver *spip, size_t n, - const void *txbuf, void *rxbuf) { - - dmaStreamSetMemory0(spip->dmarx, rxbuf); - dmaStreamSetTransactionSize(spip->dmarx, n); - dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_MINC); - - dmaStreamSetMemory0(spip->dmatx, txbuf); - dmaStreamSetTransactionSize(spip->dmatx, n); - dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC); - - dmaStreamEnable(spip->dmarx); - dmaStreamEnable(spip->dmatx); -} - -/** - * @brief Sends data over the SPI bus. - * @details This asynchronous function starts a transmit operation. - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to send - * @param[in] txbuf the pointer to the transmit buffer - * - * @notapi - */ -void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { - - dmaStreamSetMemory0(spip->dmarx, &dummyrx); - dmaStreamSetTransactionSize(spip->dmarx, n); - dmaStreamSetMode(spip->dmarx, spip->rxdmamode); - - dmaStreamSetMemory0(spip->dmatx, txbuf); - dmaStreamSetTransactionSize(spip->dmatx, n); - dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC); - - dmaStreamEnable(spip->dmarx); - dmaStreamEnable(spip->dmatx); -} - -/** - * @brief Receives data from the SPI bus. - * @details This asynchronous function starts a receive operation. - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to receive - * @param[out] rxbuf the pointer to the receive buffer - * - * @notapi - */ -void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { - - dmaStreamSetMemory0(spip->dmarx, rxbuf); - dmaStreamSetTransactionSize(spip->dmarx, n); - dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_MINC); - - dmaStreamSetMemory0(spip->dmatx, &dummytx); - dmaStreamSetTransactionSize(spip->dmatx, n); - dmaStreamSetMode(spip->dmatx, spip->txdmamode); - - dmaStreamEnable(spip->dmarx); - dmaStreamEnable(spip->dmatx); -} - -/** - * @brief Exchanges one frame using a polled wait. - * @details This synchronous function exchanges one frame using a polled - * synchronization method. This function is useful when exchanging - * small amount of data on high speed channels, usually in this - * situation is much more efficient just wait for completion using - * polling than suspending the thread waiting for an interrupt. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] frame the data frame to send over the SPI bus - * @return The received data frame from the SPI bus. - */ -uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) { - - /* - * Data register must be accessed with the appropriate data size. - * Byte size access (uint8_t *) for transactions that are <= 8-bit. - * Halfword size access (uint16_t) for transactions that are <= 8-bit. - */ - if ((spip->config->cr2 & SPI_CR2_DS) <= (SPI_CR2_DS_2 | - SPI_CR2_DS_1 | - SPI_CR2_DS_0)) { - volatile uint8_t *spidr = (volatile uint8_t *)&spip->spi->DR; - *spidr = (uint8_t)frame; - while ((spip->spi->SR & SPI_SR_RXNE) == 0) - ; - return (uint16_t)*spidr; - } - else { - spip->spi->DR = frame; - while ((spip->spi->SR & SPI_SR_RXNE) == 0) - ; - return spip->spi->DR; - } -} - -#endif /* HAL_USE_SPI */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/SPIv2/spi_lld.h b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/SPIv2/spi_lld.h deleted file mode 100644 index 167e0d7641..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/SPIv2/spi_lld.h +++ /dev/null @@ -1,547 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/SPIv2/spi_lld.h - * @brief STM32 SPI subsystem low level driver header. - * - * @addtogroup SPI - * @{ - */ - -#ifndef _SPI_LLD_H_ -#define _SPI_LLD_H_ - -#if HAL_USE_SPI || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief SPI1 driver enable switch. - * @details If set to @p TRUE the support for SPI1 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SPI_USE_SPI1) || defined(__DOXYGEN__) -#define STM32_SPI_USE_SPI1 FALSE -#endif - -/** - * @brief SPI2 driver enable switch. - * @details If set to @p TRUE the support for SPI2 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SPI_USE_SPI2) || defined(__DOXYGEN__) -#define STM32_SPI_USE_SPI2 FALSE -#endif - -/** - * @brief SPI3 driver enable switch. - * @details If set to @p TRUE the support for SPI3 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SPI_USE_SPI3) || defined(__DOXYGEN__) -#define STM32_SPI_USE_SPI3 FALSE -#endif - -/** - * @brief SPI4 driver enable switch. - * @details If set to @p TRUE the support for SPI4 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SPI_USE_SPI4) || defined(__DOXYGEN__) -#define STM32_SPI_USE_SPI4 FALSE -#endif - -/** - * @brief SPI5 driver enable switch. - * @details If set to @p TRUE the support for SPI5 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SPI_USE_SPI5) || defined(__DOXYGEN__) -#define STM32_SPI_USE_SPI5 FALSE -#endif - -/** - * @brief SPI6 driver enable switch. - * @details If set to @p TRUE the support for SPI6 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SPI_USE_SPI6) || defined(__DOXYGEN__) -#define STM32_SPI_USE_SPI6 FALSE -#endif - -/** - * @brief SPI1 interrupt priority level setting. - */ -#if !defined(STM32_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI1_IRQ_PRIORITY 10 -#endif - -/** - * @brief SPI2 interrupt priority level setting. - */ -#if !defined(STM32_SPI_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI2_IRQ_PRIORITY 10 -#endif - -/** - * @brief SPI3 interrupt priority level setting. - */ -#if !defined(STM32_SPI_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI3_IRQ_PRIORITY 10 -#endif - -/** - * @brief SPI4 interrupt priority level setting. - */ -#if !defined(STM32_SPI_SPI4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI4_IRQ_PRIORITY 10 -#endif - -/** - * @brief SPI5 interrupt priority level setting. - */ -#if !defined(STM32_SPI_SPI5_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI5_IRQ_PRIORITY 10 -#endif - -/** - * @brief SPI6 interrupt priority level setting. - */ -#if !defined(STM32_SPI_SPI6_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI6_IRQ_PRIORITY 10 -#endif - -/** - * @brief SPI1 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA streams but - * because of the streams ordering the RX stream has always priority - * over the TX stream. - */ -#if !defined(STM32_SPI_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#endif - -/** - * @brief SPI2 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA streams but - * because of the streams ordering the RX stream has always priority - * over the TX stream. - */ -#if !defined(STM32_SPI_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI2_DMA_PRIORITY 1 -#endif - -/** - * @brief SPI3 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA streams but - * because of the streams ordering the RX stream has always priority - * over the TX stream. - */ -#if !defined(STM32_SPI_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI3_DMA_PRIORITY 1 -#endif - -/** - * @brief SPI4 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA streams but - * because of the streams ordering the RX stream has always priority - * over the TX stream. - */ -#if !defined(STM32_SPI_SPI4_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI4_DMA_PRIORITY 1 -#endif - -/** - * @brief SPI5 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA streams but - * because of the streams ordering the RX stream has always priority - * over the TX stream. - */ -#if !defined(STM32_SPI_SPI5_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI5_DMA_PRIORITY 1 -#endif - -/** - * @brief SPI6 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA streams but - * because of the streams ordering the RX stream has always priority - * over the TX stream. - */ -#if !defined(STM32_SPI_SPI6_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI6_DMA_PRIORITY 1 -#endif - -/** - * @brief SPI DMA error hook. - */ -#if !defined(STM32_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__) -#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_SPI_USE_SPI1 && !STM32_HAS_SPI1 -#error "SPI1 not present in the selected device" -#endif - -#if STM32_SPI_USE_SPI2 && !STM32_HAS_SPI2 -#error "SPI2 not present in the selected device" -#endif - -#if STM32_SPI_USE_SPI3 && !STM32_HAS_SPI3 -#error "SPI3 not present in the selected device" -#endif - -#if STM32_SPI_USE_SPI4 && !STM32_HAS_SPI4 -#error "SPI4 not present in the selected device" -#endif - -#if STM32_SPI_USE_SPI5 && !STM32_HAS_SPI5 -#error "SPI5 not present in the selected device" -#endif - -#if STM32_SPI_USE_SPI6 && !STM32_HAS_SPI6 -#error "SPI6 not present in the selected device" -#endif - -#if !STM32_SPI_USE_SPI1 && !STM32_SPI_USE_SPI2 && !STM32_SPI_USE_SPI3 && \ - !STM32_SPI_USE_SPI4 && !STM32_SPI_USE_SPI5 && !STM32_SPI_USE_SPI6 -#error "SPI driver activated but no SPI peripheral assigned" -#endif - -#if STM32_SPI_USE_SPI1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SPI1" -#endif - -#if STM32_SPI_USE_SPI2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SPI2" -#endif - -#if STM32_SPI_USE_SPI3 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SPI3" -#endif - -#if STM32_SPI_USE_SPI4 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI4_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SPI4" -#endif - -#if STM32_SPI_USE_SPI5 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI5_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SPI5" -#endif - -#if STM32_SPI_USE_SPI6 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI6_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SPI6" -#endif - -#if STM32_SPI_USE_SPI1 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI1_DMA_PRIORITY) -#error "Invalid DMA priority assigned to SPI1" -#endif - -#if STM32_SPI_USE_SPI2 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI2_DMA_PRIORITY) -#error "Invalid DMA priority assigned to SPI2" -#endif - -#if STM32_SPI_USE_SPI3 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI3_DMA_PRIORITY) -#error "Invalid DMA priority assigned to SPI3" -#endif - -#if STM32_SPI_USE_SPI4 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI4_DMA_PRIORITY) -#error "Invalid DMA priority assigned to SPI4" -#endif - -#if STM32_SPI_USE_SPI5 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI5_DMA_PRIORITY) -#error "Invalid DMA priority assigned to SPI5" -#endif - -#if STM32_SPI_USE_SPI6 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI6_DMA_PRIORITY) -#error "Invalid DMA priority assigned to SPI6" -#endif - -/* The following checks are only required when there is a DMA able to - reassign streams to different channels.*/ -#if STM32_ADVANCED_DMA -/* Check on the presence of the DMA streams settings in mcuconf.h.*/ -#if STM32_SPI_USE_SPI1 && (!defined(STM32_SPI_SPI1_RX_DMA_STREAM) || \ - !defined(STM32_SPI_SPI1_TX_DMA_STREAM)) -#error "SPI1 DMA streams not defined" -#endif - -#if STM32_SPI_USE_SPI2 && (!defined(STM32_SPI_SPI2_RX_DMA_STREAM) || \ - !defined(STM32_SPI_SPI2_TX_DMA_STREAM)) -#error "SPI2 DMA streams not defined" -#endif - -#if STM32_SPI_USE_SPI3 && (!defined(STM32_SPI_SPI3_RX_DMA_STREAM) || \ - !defined(STM32_SPI_SPI3_TX_DMA_STREAM)) -#error "SPI3 DMA streams not defined" -#endif - -#if STM32_SPI_USE_SPI4 && (!defined(STM32_SPI_SPI4_RX_DMA_STREAM) || \ - !defined(STM32_SPI_SPI4_TX_DMA_STREAM)) -#error "SPI4 DMA streams not defined" -#endif - -#if STM32_SPI_USE_SPI5 && (!defined(STM32_SPI_SPI5_RX_DMA_STREAM) || \ - !defined(STM32_SPI_SPI5_TX_DMA_STREAM)) -#error "SPI5 DMA streams not defined" -#endif - -#if STM32_SPI_USE_SPI6 && (!defined(STM32_SPI_SPI6_RX_DMA_STREAM) || \ - !defined(STM32_SPI_SPI6_TX_DMA_STREAM)) -#error "SPI6 DMA streams not defined" -#endif - -/* Check on the validity of the assigned DMA channels.*/ -#if STM32_SPI_USE_SPI1 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_RX_DMA_STREAM, STM32_SPI1_RX_DMA_MSK) -#error "invalid DMA stream associated to SPI1 RX" -#endif - -#if STM32_SPI_USE_SPI1 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_TX_DMA_STREAM, STM32_SPI1_TX_DMA_MSK) -#error "invalid DMA stream associated to SPI1 TX" -#endif - -#if STM32_SPI_USE_SPI2 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI2_RX_DMA_STREAM, STM32_SPI2_RX_DMA_MSK) -#error "invalid DMA stream associated to SPI2 RX" -#endif - -#if STM32_SPI_USE_SPI2 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI2_TX_DMA_STREAM, STM32_SPI2_TX_DMA_MSK) -#error "invalid DMA stream associated to SPI2 TX" -#endif - -#if STM32_SPI_USE_SPI3 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI3_RX_DMA_STREAM, STM32_SPI3_RX_DMA_MSK) -#error "invalid DMA stream associated to SPI3 RX" -#endif - -#if STM32_SPI_USE_SPI3 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI3_TX_DMA_STREAM, STM32_SPI3_TX_DMA_MSK) -#error "invalid DMA stream associated to SPI3 TX" -#endif - -#if STM32_SPI_USE_SPI4 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI4_RX_DMA_STREAM, STM32_SPI4_RX_DMA_MSK) -#error "invalid DMA stream associated to SPI4 RX" -#endif - -#if STM32_SPI_USE_SPI4 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI4_TX_DMA_STREAM, STM32_SPI4_TX_DMA_MSK) -#error "invalid DMA stream associated to SPI4 TX" -#endif - -#if STM32_SPI_USE_SPI5 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI5_RX_DMA_STREAM, STM32_SPI5_RX_DMA_MSK) -#error "invalid DMA stream associated to SPI5 RX" -#endif - -#if STM32_SPI_USE_SPI5 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI5_TX_DMA_STREAM, STM32_SPI5_TX_DMA_MSK) -#error "invalid DMA stream associated to SPI5 TX" -#endif - -#if STM32_SPI_USE_SPI6 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI6_RX_DMA_STREAM, STM32_SPI6_RX_DMA_MSK) -#error "invalid DMA stream associated to SPI6 RX" -#endif - -#if STM32_SPI_USE_SPI6 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI6_TX_DMA_STREAM, STM32_SPI6_TX_DMA_MSK) -#error "invalid DMA stream associated to SPI6 TX" -#endif -#endif /* STM32_ADVANCED_DMA */ - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a structure representing an SPI driver. - */ -typedef struct SPIDriver SPIDriver; - -/** - * @brief SPI notification callback type. - * - * @param[in] spip pointer to the @p SPIDriver object triggering the - * callback - */ -typedef void (*spicallback_t)(SPIDriver *spip); - -/** - * @brief Driver configuration structure. - */ -typedef struct { - /** - * @brief Operation complete callback or @p NULL. - */ - spicallback_t end_cb; - /* End of the mandatory fields.*/ - /** - * @brief The chip select line port. - */ - ioportid_t ssport; - /** - * @brief The chip select line pad number. - */ - uint16_t sspad; - /** - * @brief SPI CR1 register initialization data. - */ - uint16_t cr1; - /** - * @brief SPI CR2 register initialization data. - */ - uint16_t cr2; -} SPIConfig; - -/** - * @brief Structure representing an SPI driver. - */ -struct SPIDriver { - /** - * @brief Driver state. - */ - spistate_t state; - /** - * @brief Current configuration data. - */ - const SPIConfig *config; -#if SPI_USE_WAIT || defined(__DOXYGEN__) - /** - * @brief Waiting thread. - */ - thread_reference_t thread; -#endif /* SPI_USE_WAIT */ -#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the peripheral. - */ - mutex_t mutex; -#endif /* SPI_USE_MUTUAL_EXCLUSION */ -#if defined(SPI_DRIVER_EXT_FIELDS) - SPI_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the SPIx registers block. - */ - SPI_TypeDef *spi; - /** - * @brief Receive DMA stream. - */ - const stm32_dma_stream_t *dmarx; - /** - * @brief Transmit DMA stream. - */ - const stm32_dma_stream_t *dmatx; - /** - * @brief RX DMA mode bit mask. - */ - uint32_t rxdmamode; - /** - * @brief TX DMA mode bit mask. - */ - uint32_t txdmamode; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_SPI_USE_SPI1 && !defined(__DOXYGEN__) -extern SPIDriver SPID1; -#endif - -#if STM32_SPI_USE_SPI2 && !defined(__DOXYGEN__) -extern SPIDriver SPID2; -#endif - -#if STM32_SPI_USE_SPI3 && !defined(__DOXYGEN__) -extern SPIDriver SPID3; -#endif - -#if STM32_SPI_USE_SPI4 && !defined(__DOXYGEN__) -extern SPIDriver SPID4; -#endif - -#if STM32_SPI_USE_SPI5 && !defined(__DOXYGEN__) -extern SPIDriver SPID5; -#endif - -#if STM32_SPI_USE_SPI6 && !defined(__DOXYGEN__) -extern SPIDriver SPID6; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void spi_lld_init(void); - void spi_lld_start(SPIDriver *spip); - void spi_lld_stop(SPIDriver *spip); - void spi_lld_select(SPIDriver *spip); - void spi_lld_unselect(SPIDriver *spip); - void spi_lld_ignore(SPIDriver *spip, size_t n); - void spi_lld_exchange(SPIDriver *spip, size_t n, - const void *txbuf, void *rxbuf); - void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); - void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); - uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_SPI */ - -#endif /* _SPI_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c deleted file mode 100644 index 3735582578..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c +++ /dev/null @@ -1,892 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/gpt_lld.c - * @brief STM32 GPT subsystem low level driver source. - * - * @addtogroup GPT - * @{ - */ - -#include "hal.h" - -#if HAL_USE_GPT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief GPTD1 driver identifier. - * @note The driver GPTD1 allocates the complex timer TIM1 when enabled. - */ -#if STM32_GPT_USE_TIM1 || defined(__DOXYGEN__) -GPTDriver GPTD1; -#endif - -/** - * @brief GPTD2 driver identifier. - * @note The driver GPTD2 allocates the timer TIM2 when enabled. - */ -#if STM32_GPT_USE_TIM2 || defined(__DOXYGEN__) -GPTDriver GPTD2; -#endif - -/** - * @brief GPTD3 driver identifier. - * @note The driver GPTD3 allocates the timer TIM3 when enabled. - */ -#if STM32_GPT_USE_TIM3 || defined(__DOXYGEN__) -GPTDriver GPTD3; -#endif - -/** - * @brief GPTD4 driver identifier. - * @note The driver GPTD4 allocates the timer TIM4 when enabled. - */ -#if STM32_GPT_USE_TIM4 || defined(__DOXYGEN__) -GPTDriver GPTD4; -#endif - -/** - * @brief GPTD5 driver identifier. - * @note The driver GPTD5 allocates the timer TIM5 when enabled. - */ -#if STM32_GPT_USE_TIM5 || defined(__DOXYGEN__) -GPTDriver GPTD5; -#endif - -/** - * @brief GPTD6 driver identifier. - * @note The driver GPTD6 allocates the timer TIM6 when enabled. - */ -#if STM32_GPT_USE_TIM6 || defined(__DOXYGEN__) -GPTDriver GPTD6; -#endif - -/** - * @brief GPTD7 driver identifier. - * @note The driver GPTD7 allocates the timer TIM7 when enabled. - */ -#if STM32_GPT_USE_TIM7 || defined(__DOXYGEN__) -GPTDriver GPTD7; -#endif - -/** - * @brief GPTD8 driver identifier. - * @note The driver GPTD8 allocates the timer TIM8 when enabled. - */ -#if STM32_GPT_USE_TIM8 || defined(__DOXYGEN__) -GPTDriver GPTD8; -#endif - -/** - * @brief GPTD9 driver identifier. - * @note The driver GPTD9 allocates the timer TIM9 when enabled. - */ -#if STM32_GPT_USE_TIM9 || defined(__DOXYGEN__) -GPTDriver GPTD9; -#endif - -/** - * @brief GPTD11 driver identifier. - * @note The driver GPTD11 allocates the timer TIM11 when enabled. - */ -#if STM32_GPT_USE_TIM11 || defined(__DOXYGEN__) -GPTDriver GPTD11; -#endif - -/** - * @brief GPTD12 driver identifier. - * @note The driver GPTD12 allocates the timer TIM12 when enabled. - */ -#if STM32_GPT_USE_TIM12 || defined(__DOXYGEN__) -GPTDriver GPTD12; -#endif - -/** - * @brief GPTD14 driver identifier. - * @note The driver GPTD14 allocates the timer TIM14 when enabled. - */ -#if STM32_GPT_USE_TIM14 || defined(__DOXYGEN__) -GPTDriver GPTD14; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if STM32_GPT_USE_TIM1 || defined(__DOXYGEN__) -#if !defined(STM32_TIM1_SUPPRESS_ISR) -#if !defined(STM32_TIM1_UP_HANDLER) -#error "STM32_TIM1_UP_HANDLER not defined" -#endif -/** - * @brief TIM2 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD1); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* !defined(STM32_TIM1_SUPPRESS_ISR) */ -#endif /* STM32_GPT_USE_TIM1 */ - -#if STM32_GPT_USE_TIM2 || defined(__DOXYGEN__) -#if !defined(STM32_TIM2_SUPPRESS_ISR) -#if !defined(STM32_TIM2_HANDLER) -#error "STM32_TIM2_HANDLER not defined" -#endif -/** - * @brief TIM2 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM2_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD2); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* !defined(STM32_TIM2_SUPPRESS_ISR) */ -#endif /* STM32_GPT_USE_TIM2 */ - -#if STM32_GPT_USE_TIM3 || defined(__DOXYGEN__) -#if !defined(STM32_TIM3_SUPPRESS_ISR) -#if !defined(STM32_TIM3_HANDLER) -#error "STM32_TIM3_HANDLER not defined" -#endif -/** - * @brief TIM3 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM3_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD3); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* !defined(STM32_TIM3_SUPPRESS_ISR) */ -#endif /* STM32_GPT_USE_TIM3 */ - -#if STM32_GPT_USE_TIM4 || defined(__DOXYGEN__) -#if !defined(STM32_TIM4_SUPPRESS_ISR) -#if !defined(STM32_TIM4_HANDLER) -#error "STM32_TIM4_HANDLER not defined" -#endif -/** - * @brief TIM4 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM4_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD4); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* !defined(STM32_TIM4_SUPPRESS_ISR) */ -#endif /* STM32_GPT_USE_TIM4 */ - -#if STM32_GPT_USE_TIM5 || defined(__DOXYGEN__) -#if !defined(STM32_TIM5_SUPPRESS_ISR) -#if !defined(STM32_TIM5_HANDLER) -#error "STM32_TIM5_HANDLER not defined" -#endif -/** - * @brief TIM5 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM5_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD5); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* !defined(STM32_TIM5_SUPPRESS_ISR) */ -#endif /* STM32_GPT_USE_TIM5 */ - -#if STM32_GPT_USE_TIM6 || defined(__DOXYGEN__) -#if !defined(STM32_TIM6_SUPPRESS_ISR) -#if !defined(STM32_TIM6_HANDLER) -#error "STM32_TIM6_HANDLER not defined" -#endif -/** - * @brief TIM6 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM6_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD6); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* !defined(STM32_TIM6_SUPPRESS_ISR) */ -#endif /* STM32_GPT_USE_TIM6 */ - -#if STM32_GPT_USE_TIM7 || defined(__DOXYGEN__) -#if !defined(STM32_TIM7_SUPPRESS_ISR) -#if !defined(STM32_TIM7_HANDLER) -#error "STM32_TIM7_HANDLER not defined" -#endif -/** - * @brief TIM7 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM7_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD7); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* !defined(STM32_TIM7_SUPPRESS_ISR) */ -#endif /* STM32_GPT_USE_TIM7 */ - -#if STM32_GPT_USE_TIM8 || defined(__DOXYGEN__) -#if !defined(STM32_TIM8_SUPPRESS_ISR) -#if !defined(STM32_TIM8_UP_HANDLER) -#error "STM32_TIM8_UP_HANDLER not defined" -#endif -/** - * @brief TIM8 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD8); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* !defined(STM32_TIM8_SUPPRESS_ISR) */ -#endif /* STM32_GPT_USE_TIM8 */ - -#if STM32_GPT_USE_TIM9 || defined(__DOXYGEN__) -#if !defined(STM32_TIM9_SUPPRESS_ISR) -#if !defined(STM32_TIM9_HANDLER) -#error "STM32_TIM9_HANDLER not defined" -#endif -/** - * @brief TIM9 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM9_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD9); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* !defined(STM32_TIM9_SUPPRESS_ISR) */ -#endif /* STM32_GPT_USE_TIM9 */ - -#if STM32_GPT_USE_TIM11 || defined(__DOXYGEN__) -#if !defined(STM32_TIM11_SUPPRESS_ISR) -#if !defined(STM32_TIM11_HANDLER) -#error "STM32_TIM11_HANDLER not defined" -#endif -/** - * @brief TIM11 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM11_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD11); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* !defined(STM32_TIM11_SUPPRESS_ISR) */ -#endif /* STM32_GPT_USE_TIM11 */ - -#if STM32_GPT_USE_TIM12 || defined(__DOXYGEN__) -#if !defined(STM32_TIM12_SUPPRESS_ISR) -#if !defined(STM32_TIM12_HANDLER) -#error "STM32_TIM12_HANDLER not defined" -#endif -/** - * @brief TIM12 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM12_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD12); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* !defined(STM32_TIM12_SUPPRESS_ISR) */ -#endif /* STM32_GPT_USE_TIM12 */ - -#if STM32_GPT_USE_TIM14 || defined(__DOXYGEN__) -#if !defined(STM32_TIM14_SUPPRESS_ISR) -#if !defined(STM32_TIM14_HANDLER) -#error "STM32_TIM14_HANDLER not defined" -#endif -/** - * @brief TIM14 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM14_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD14); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* !defined(STM32_TIM14_SUPPRESS_ISR) */ -#endif /* STM32_GPT_USE_TIM14 */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level GPT driver initialization. - * - * @notapi - */ -void gpt_lld_init(void) { - -#if STM32_GPT_USE_TIM1 - /* Driver initialization.*/ - GPTD1.tim = STM32_TIM1; - gptObjectInit(&GPTD1); -#endif - -#if STM32_GPT_USE_TIM2 - /* Driver initialization.*/ - GPTD2.tim = STM32_TIM2; - gptObjectInit(&GPTD2); -#endif - -#if STM32_GPT_USE_TIM3 - /* Driver initialization.*/ - GPTD3.tim = STM32_TIM3; - gptObjectInit(&GPTD3); -#endif - -#if STM32_GPT_USE_TIM4 - /* Driver initialization.*/ - GPTD4.tim = STM32_TIM4; - gptObjectInit(&GPTD4); -#endif - -#if STM32_GPT_USE_TIM5 - /* Driver initialization.*/ - GPTD5.tim = STM32_TIM5; - gptObjectInit(&GPTD5); -#endif - -#if STM32_GPT_USE_TIM6 - /* Driver initialization.*/ - GPTD6.tim = STM32_TIM6; - gptObjectInit(&GPTD6); -#endif - -#if STM32_GPT_USE_TIM7 - /* Driver initialization.*/ - GPTD7.tim = STM32_TIM7; - gptObjectInit(&GPTD7); -#endif - -#if STM32_GPT_USE_TIM8 - /* Driver initialization.*/ - GPTD8.tim = STM32_TIM8; - gptObjectInit(&GPTD8); -#endif - -#if STM32_GPT_USE_TIM9 - /* Driver initialization.*/ - GPTD9.tim = STM32_TIM9; - gptObjectInit(&GPTD9); -#endif - -#if STM32_GPT_USE_TIM11 - /* Driver initialization.*/ - GPTD11.tim = STM32_TIM11; - gptObjectInit(&GPTD11); -#endif - -#if STM32_GPT_USE_TIM12 - /* Driver initialization.*/ - GPTD12.tim = STM32_TIM12; - gptObjectInit(&GPTD12); -#endif - -#if STM32_GPT_USE_TIM14 - /* Driver initialization.*/ - GPTD14.tim = STM32_TIM14; - gptObjectInit(&GPTD14); -#endif -} - -/** - * @brief Configures and activates the GPT peripheral. - * - * @param[in] gptp pointer to the @p GPTDriver object - * - * @notapi - */ -void gpt_lld_start(GPTDriver *gptp) { - uint16_t psc; - - if (gptp->state == GPT_STOP) { - /* Clock activation.*/ -#if STM32_GPT_USE_TIM1 - if (&GPTD1 == gptp) { - rccEnableTIM1(FALSE); - rccResetTIM1(); -#if !defined(STM32_TIM1_SUPPRESS_ISR) - nvicEnableVector(STM32_TIM1_UP_NUMBER, STM32_GPT_TIM1_IRQ_PRIORITY); -#endif -#if defined(STM32_TIM1CLK) - gptp->clock = STM32_TIM1CLK; -#else - gptp->clock = STM32_TIMCLK2; -#endif - } -#endif - -#if STM32_GPT_USE_TIM2 - if (&GPTD2 == gptp) { - rccEnableTIM2(FALSE); - rccResetTIM2(); -#if !defined(STM32_TIM2_SUPPRESS_ISR) - nvicEnableVector(STM32_TIM2_NUMBER, STM32_GPT_TIM2_IRQ_PRIORITY); -#endif -#if defined(STM32_TIM2CLK) - gptp->clock = STM32_TIM2CLK; -#else - gptp->clock = STM32_TIMCLK1; -#endif - } -#endif - -#if STM32_GPT_USE_TIM3 - if (&GPTD3 == gptp) { - rccEnableTIM3(FALSE); - rccResetTIM3(); -#if !defined(STM32_TIM3_SUPPRESS_ISR) - nvicEnableVector(STM32_TIM3_NUMBER, STM32_GPT_TIM3_IRQ_PRIORITY); -#endif -#if defined(STM32_TIM3CLK) - gptp->clock = STM32_TIM3CLK; -#else - gptp->clock = STM32_TIMCLK1; -#endif - } -#endif - -#if STM32_GPT_USE_TIM4 - if (&GPTD4 == gptp) { - rccEnableTIM4(FALSE); - rccResetTIM4(); -#if !defined(STM32_TIM4_SUPPRESS_ISR) - nvicEnableVector(STM32_TIM4_NUMBER, STM32_GPT_TIM4_IRQ_PRIORITY); -#endif -#if defined(STM32_TIM4CLK) - gptp->clock = STM32_TIM4CLK; -#else - gptp->clock = STM32_TIMCLK1; -#endif - } -#endif - -#if STM32_GPT_USE_TIM5 - if (&GPTD5 == gptp) { - rccEnableTIM5(FALSE); - rccResetTIM5(); -#if !defined(STM32_TIM5_SUPPRESS_ISR) - nvicEnableVector(STM32_TIM5_NUMBER, STM32_GPT_TIM5_IRQ_PRIORITY); -#endif -#if defined(STM32_TIM5CLK) - gptp->clock = STM32_TIM5CLK; -#else - gptp->clock = STM32_TIMCLK1; -#endif - } -#endif - -#if STM32_GPT_USE_TIM6 - if (&GPTD6 == gptp) { - rccEnableTIM6(FALSE); - rccResetTIM6(); -#if !defined(STM32_TIM6_SUPPRESS_ISR) - nvicEnableVector(STM32_TIM6_NUMBER, STM32_GPT_TIM6_IRQ_PRIORITY); -#endif -#if defined(STM32_TIM6CLK) - gptp->clock = STM32_TIM6CLK; -#else - gptp->clock = STM32_TIMCLK1; -#endif - } -#endif - -#if STM32_GPT_USE_TIM7 - if (&GPTD7 == gptp) { - rccEnableTIM7(FALSE); - rccResetTIM7(); -#if !defined(STM32_TIM7_SUPPRESS_ISR) - nvicEnableVector(STM32_TIM7_NUMBER, STM32_GPT_TIM7_IRQ_PRIORITY); -#endif -#if defined(STM32_TIM7CLK) - gptp->clock = STM32_TIM7CLK; -#else - gptp->clock = STM32_TIMCLK1; -#endif - } -#endif - -#if STM32_GPT_USE_TIM8 - if (&GPTD8 == gptp) { - rccEnableTIM8(FALSE); - rccResetTIM8(); -#if !defined(STM32_TIM8_SUPPRESS_ISR) - nvicEnableVector(STM32_TIM8_UP_NUMBER, STM32_GPT_TIM8_IRQ_PRIORITY); -#endif -#if defined(STM32_TIM8CLK) - gptp->clock = STM32_TIM8CLK; -#else - gptp->clock = STM32_TIMCLK2; -#endif - } -#endif - -#if STM32_GPT_USE_TIM9 - if (&GPTD9 == gptp) { - rccEnableTIM9(FALSE); - rccResetTIM9(); -#if !defined(STM32_TIM9_SUPPRESS_ISR) - nvicEnableVector(STM32_TIM9_NUMBER, STM32_GPT_TIM9_IRQ_PRIORITY); -#endif -#if defined(STM32_TIM9CLK) - gptp->clock = STM32_TIM9CLK; -#else - gptp->clock = STM32_TIMCLK2; -#endif - } -#endif - -#if STM32_GPT_USE_TIM11 - if (&GPTD11 == gptp) { - rccEnableTIM11(FALSE); - rccResetTIM11(); -#if !defined(STM32_TIM11_SUPPRESS_ISR) - nvicEnableVector(STM32_TIM11_NUMBER, STM32_GPT_TIM11_IRQ_PRIORITY); -#endif -#if defined(STM32_TIM11CLK) - gptp->clock = STM32_TIM11CLK; -#else - gptp->clock = STM32_TIMCLK2; -#endif - } -#endif - -#if STM32_GPT_USE_TIM12 - if (&GPTD12 == gptp) { - rccEnableTIM12(FALSE); - rccResetTIM12(); -#if !defined(STM32_TIM12_SUPPRESS_ISR) - nvicEnableVector(STM32_TIM12_NUMBER, STM32_GPT_TIM12_IRQ_PRIORITY); -#endif -#if defined(STM32_TIM12CLK) - gptp->clock = STM32_TIM12CLK; -#else - gptp->clock = STM32_TIMCLK1; -#endif - } -#endif - -#if STM32_GPT_USE_TIM14 - if (&GPTD14 == gptp) { - rccEnableTIM14(FALSE); - rccResetTIM14(); -#if !defined(STM32_TIM14_SUPPRESS_ISR) - nvicEnableVector(STM32_TIM14_NUMBER, STM32_GPT_TIM14_IRQ_PRIORITY); -#endif -#if defined(STM32_TIM14CLK) - gptp->clock = STM32_TIM14CLK; -#else - gptp->clock = STM32_TIMCLK1; -#endif - } -#endif - } - - /* Prescaler value calculation.*/ - psc = (uint16_t)((gptp->clock / gptp->config->frequency) - 1); - osalDbgAssert(((uint32_t)(psc + 1) * gptp->config->frequency) == gptp->clock, - "invalid frequency"); - - /* Timer configuration.*/ - gptp->tim->CR1 = 0; /* Initially stopped. */ - gptp->tim->CR2 = gptp->config->cr2; - gptp->tim->PSC = psc; /* Prescaler value. */ - gptp->tim->SR = 0; /* Clear pending IRQs. */ - gptp->tim->DIER = gptp->config->dier & /* DMA-related DIER bits. */ - ~STM32_TIM_DIER_IRQ_MASK; -} - -/** - * @brief Deactivates the GPT peripheral. - * - * @param[in] gptp pointer to the @p GPTDriver object - * - * @notapi - */ -void gpt_lld_stop(GPTDriver *gptp) { - - if (gptp->state == GPT_READY) { - gptp->tim->CR1 = 0; /* Timer disabled. */ - gptp->tim->DIER = 0; /* All IRQs disabled. */ - gptp->tim->SR = 0; /* Clear pending IRQs. */ - -#if STM32_GPT_USE_TIM1 - if (&GPTD1 == gptp) { -#if !defined(STM32_TIM1_SUPPRESS_ISR) - nvicDisableVector(STM32_TIM1_UP_NUMBER); -#endif - rccDisableTIM1(FALSE); - } -#endif - -#if STM32_GPT_USE_TIM2 - if (&GPTD2 == gptp) { -#if !defined(STM32_TIM2_SUPPRESS_ISR) - nvicDisableVector(STM32_TIM2_NUMBER); -#endif - rccDisableTIM2(FALSE); - } -#endif - -#if STM32_GPT_USE_TIM3 - if (&GPTD3 == gptp) { -#if !defined(STM32_TIM3_SUPPRESS_ISR) - nvicDisableVector(STM32_TIM3_NUMBER); -#endif - rccDisableTIM3(FALSE); - } -#endif - -#if STM32_GPT_USE_TIM4 - if (&GPTD4 == gptp) { -#if !defined(STM32_TIM4_SUPPRESS_ISR) - nvicDisableVector(STM32_TIM4_NUMBER); -#endif - rccDisableTIM4(FALSE); - } -#endif - -#if STM32_GPT_USE_TIM5 - if (&GPTD5 == gptp) { -#if !defined(STM32_TIM5_SUPPRESS_ISR) - nvicDisableVector(STM32_TIM5_NUMBER); -#endif - rccDisableTIM5(FALSE); - } -#endif - -#if STM32_GPT_USE_TIM6 - if (&GPTD6 == gptp) { -#if !defined(STM32_TIM6_SUPPRESS_ISR) - nvicDisableVector(STM32_TIM6_NUMBER); -#endif - rccDisableTIM6(FALSE); - } -#endif - -#if STM32_GPT_USE_TIM7 - if (&GPTD7 == gptp) { -#if !defined(STM32_TIM7_SUPPRESS_ISR) - nvicDisableVector(STM32_TIM7_NUMBER); -#endif - rccDisableTIM7(FALSE); - } -#endif - -#if STM32_GPT_USE_TIM8 - if (&GPTD8 == gptp) { -#if !defined(STM32_TIM8_SUPPRESS_ISR) - nvicDisableVector(STM32_TIM8_UP_NUMBER); -#endif - rccDisableTIM8(FALSE); - } -#endif - -#if STM32_GPT_USE_TIM9 - if (&GPTD9 == gptp) { -#if !defined(STM32_TIM9_SUPPRESS_ISR) - nvicDisableVector(STM32_TIM9_NUMBER); -#endif - rccDisableTIM9(FALSE); - } -#endif - -#if STM32_GPT_USE_TIM11 - if (&GPTD11 == gptp) { -#if !defined(STM32_TIM11_SUPPRESS_ISR) - nvicDisableVector(STM32_TIM11_NUMBER); -#endif - rccDisableTIM11(FALSE); - } -#endif - -#if STM32_GPT_USE_TIM12 - if (&GPTD12 == gptp) { -#if !defined(STM32_TIM12_SUPPRESS_ISR) - nvicDisableVector(STM32_TIM12_NUMBER); -#endif - rccDisableTIM12(FALSE); - } -#endif - -#if STM32_GPT_USE_TIM14 - if (&GPTD14 == gptp) { -#if !defined(STM32_TIM14_SUPPRESS_ISR) - nvicDisableVector(STM32_TIM14_NUMBER); -#endif - rccDisableTIM14(FALSE); - } -#endif - } -} - -/** - * @brief Starts the timer in continuous mode. - * - * @param[in] gptp pointer to the @p GPTDriver object - * @param[in] interval period in ticks - * - * @notapi - */ -void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) { - - gptp->tim->ARR = (uint32_t)(interval - 1); /* Time constant. */ - gptp->tim->EGR = STM32_TIM_EGR_UG; /* Update event. */ - gptp->tim->CNT = 0; /* Reset counter. */ - - /* NOTE: After generating the UG event it takes several clock cycles before - SR bit 0 goes to 1. This is because the clearing of CNT has been inserted - before the clearing of SR, to give it some time.*/ - gptp->tim->SR = 0; /* Clear pending IRQs. */ - if (NULL != gptp->config->callback) - gptp->tim->DIER |= STM32_TIM_DIER_UIE; /* Update Event IRQ enabled.*/ - gptp->tim->CR1 = STM32_TIM_CR1_ARPE | STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN; -} - -/** - * @brief Stops the timer. - * - * @param[in] gptp pointer to the @p GPTDriver object - * - * @notapi - */ -void gpt_lld_stop_timer(GPTDriver *gptp) { - - gptp->tim->CR1 = 0; /* Initially stopped. */ - gptp->tim->SR = 0; /* Clear pending IRQs. */ - - /* All interrupts disabled.*/ - gptp->tim->DIER &= ~STM32_TIM_DIER_IRQ_MASK; -} - -/** - * @brief Starts the timer in one shot mode and waits for completion. - * @details This function specifically polls the timer waiting for completion - * in order to not have extra delays caused by interrupt servicing, - * this function is only recommended for short delays. - * - * @param[in] gptp pointer to the @p GPTDriver object - * @param[in] interval time interval in ticks - * - * @notapi - */ -void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) { - - gptp->tim->ARR = (uint32_t)(interval - 1); /* Time constant. */ - gptp->tim->EGR = STM32_TIM_EGR_UG; /* Update event. */ - gptp->tim->SR = 0; /* Clear pending IRQs. */ - gptp->tim->CR1 = STM32_TIM_CR1_OPM | STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN; - while (!(gptp->tim->SR & STM32_TIM_SR_UIF)) - ; - gptp->tim->SR = 0; /* Clear pending IRQs. */ -} - -/** - * @brief Shared IRQ handler. - * - * @param[in] gptp pointer to a @p GPTDriver object - * - * @notapi - */ -void gpt_lld_serve_interrupt(GPTDriver *gptp) { - - gptp->tim->SR = 0; - if (gptp->state == GPT_ONESHOT) { - gptp->state = GPT_READY; /* Back in GPT_READY state. */ - gpt_lld_stop_timer(gptp); /* Timer automatically stopped. */ - } - gptp->config->callback(gptp); -} - -#endif /* HAL_USE_GPT */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.h b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.h deleted file mode 100644 index e49be90be3..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.h +++ /dev/null @@ -1,641 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/gpt_lld.h - * @brief STM32 GPT subsystem low level driver header. - * - * @addtogroup GPT - * @{ - */ - -#ifndef _GPT_LLD_H_ -#define _GPT_LLD_H_ - -#include "stm32_tim.h" - -#if HAL_USE_GPT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief GPTD1 driver enable switch. - * @details If set to @p TRUE the support for GPTD1 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_GPT_USE_TIM1) || defined(__DOXYGEN__) -#define STM32_GPT_USE_TIM1 FALSE -#endif - -/** - * @brief GPTD2 driver enable switch. - * @details If set to @p TRUE the support for GPTD2 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_GPT_USE_TIM2) || defined(__DOXYGEN__) -#define STM32_GPT_USE_TIM2 FALSE -#endif - -/** - * @brief GPTD3 driver enable switch. - * @details If set to @p TRUE the support for GPTD3 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_GPT_USE_TIM3) || defined(__DOXYGEN__) -#define STM32_GPT_USE_TIM3 FALSE -#endif - -/** - * @brief GPTD4 driver enable switch. - * @details If set to @p TRUE the support for GPTD4 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_GPT_USE_TIM4) || defined(__DOXYGEN__) -#define STM32_GPT_USE_TIM4 FALSE -#endif - -/** - * @brief GPTD5 driver enable switch. - * @details If set to @p TRUE the support for GPTD5 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_GPT_USE_TIM5) || defined(__DOXYGEN__) -#define STM32_GPT_USE_TIM5 FALSE -#endif - -/** - * @brief GPTD6 driver enable switch. - * @details If set to @p TRUE the support for GPTD6 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_GPT_USE_TIM6) || defined(__DOXYGEN__) -#define STM32_GPT_USE_TIM6 FALSE -#endif - -/** - * @brief GPTD7 driver enable switch. - * @details If set to @p TRUE the support for GPTD7 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_GPT_USE_TIM7) || defined(__DOXYGEN__) -#define STM32_GPT_USE_TIM7 FALSE -#endif - -/** - * @brief GPTD8 driver enable switch. - * @details If set to @p TRUE the support for GPTD8 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_GPT_USE_TIM8) || defined(__DOXYGEN__) -#define STM32_GPT_USE_TIM8 FALSE -#endif - -/** - * @brief GPTD9 driver enable switch. - * @details If set to @p TRUE the support for GPTD9 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_GPT_USE_TIM9) || defined(__DOXYGEN__) -#define STM32_GPT_USE_TIM9 FALSE -#endif - -/** - * @brief GPTD11 driver enable switch. - * @details If set to @p TRUE the support for GPTD11 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_GPT_USE_TIM11) || defined(__DOXYGEN__) -#define STM32_GPT_USE_TIM11 FALSE -#endif - -/** - * @brief GPTD12 driver enable switch. - * @details If set to @p TRUE the support for GPTD12 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_GPT_USE_TIM12) || defined(__DOXYGEN__) -#define STM32_GPT_USE_TIM12 FALSE -#endif - -/** - * @brief GPTD14 driver enable switch. - * @details If set to @p TRUE the support for GPTD14 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_GPT_USE_TIM14) || defined(__DOXYGEN__) -#define STM32_GPT_USE_TIM14 FALSE -#endif - -/** - * @brief GPTD1 interrupt priority level setting. - */ -#if !defined(STM32_GPT_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_GPT_TIM1_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD2 interrupt priority level setting. - */ -#if !defined(STM32_GPT_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_GPT_TIM2_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD3 interrupt priority level setting. - */ -#if !defined(STM32_GPT_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_GPT_TIM3_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD4 interrupt priority level setting. - */ -#if !defined(STM32_GPT_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_GPT_TIM4_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD5 interrupt priority level setting. - */ -#if !defined(STM32_GPT_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_GPT_TIM5_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD6 interrupt priority level setting. - */ -#if !defined(STM32_GPT_TIM6_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_GPT_TIM6_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD7 interrupt priority level setting. - */ -#if !defined(STM32_GPT_TIM7_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_GPT_TIM7_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD8 interrupt priority level setting. - */ -#if !defined(STM32_GPT_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_GPT_TIM8_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD9 interrupt priority level setting. - */ -#if !defined(STM32_GPT_TIM9_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_GPT_TIM9_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD11 interrupt priority level setting. - */ -#if !defined(STM32_GPT_TIM11_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_GPT_TIM11_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD12 interrupt priority level setting. - */ -#if !defined(STM32_GPT_TIM12_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_GPT_TIM12_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD14 interrupt priority level setting. - */ -#if !defined(STM32_GPT_TIM14_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_GPT_TIM14_IRQ_PRIORITY 7 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_GPT_USE_TIM1 && !STM32_HAS_TIM1 -#error "TIM1 not present in the selected device" -#endif - -#if STM32_GPT_USE_TIM2 && !STM32_HAS_TIM2 -#error "TIM2 not present in the selected device" -#endif - -#if STM32_GPT_USE_TIM3 && !STM32_HAS_TIM3 -#error "TIM3 not present in the selected device" -#endif - -#if STM32_GPT_USE_TIM4 && !STM32_HAS_TIM4 -#error "TIM4 not present in the selected device" -#endif - -#if STM32_GPT_USE_TIM5 && !STM32_HAS_TIM5 -#error "TIM5 not present in the selected device" -#endif - -#if STM32_GPT_USE_TIM6 && !STM32_HAS_TIM6 -#error "TIM6 not present in the selected device" -#endif - -#if STM32_GPT_USE_TIM7 && !STM32_HAS_TIM7 -#error "TIM7 not present in the selected device" -#endif - -#if STM32_GPT_USE_TIM8 && !STM32_HAS_TIM8 -#error "TIM8 not present in the selected device" -#endif - -#if STM32_GPT_USE_TIM9 && !STM32_HAS_TIM9 -#error "TIM9 not present in the selected device" -#endif - -#if STM32_GPT_USE_TIM11 && !STM32_HAS_TIM11 -#error "TIM11 not present in the selected device" -#endif - -#if STM32_GPT_USE_TIM12 && !STM32_HAS_TIM12 -#error "TIM12 not present in the selected device" -#endif - -#if STM32_GPT_USE_TIM14 && !STM32_HAS_TIM14 -#error "TIM14 not present in the selected device" -#endif - -#if !STM32_GPT_USE_TIM1 && !STM32_GPT_USE_TIM2 && \ - !STM32_GPT_USE_TIM3 && !STM32_GPT_USE_TIM4 && \ - !STM32_GPT_USE_TIM5 && !STM32_GPT_USE_TIM6 && \ - !STM32_GPT_USE_TIM7 && !STM32_GPT_USE_TIM8 && \ - !STM32_GPT_USE_TIM9 && !STM32_GPT_USE_TIM11 && \ - !STM32_GPT_USE_TIM12 && !STM32_GPT_USE_TIM14 -#error "GPT driver activated but no TIM peripheral assigned" -#endif - -/* Checks on allocation of TIMx units.*/ -#if STM32_GPT_USE_TIM1 -#if defined(STM32_TIM1_IS_USED) -#error "GPTD1 requires TIM1 but the timer is already used" -#else -#define STM32_TIM1_IS_USED -#endif -#endif - -#if STM32_GPT_USE_TIM2 -#if defined(STM32_TIM2_IS_USED) -#error "GPTD2 requires TIM2 but the timer is already used" -#else -#define STM32_TIM2_IS_USED -#endif -#endif - -#if STM32_GPT_USE_TIM3 -#if defined(STM32_TIM3_IS_USED) -#error "GPTD3 requires TIM3 but the timer is already used" -#else -#define STM32_TIM3_IS_USED -#endif -#endif - -#if STM32_GPT_USE_TIM4 -#if defined(STM32_TIM4_IS_USED) -#error "GPTD4 requires TIM4 but the timer is already used" -#else -#define STM32_TIM4_IS_USED -#endif -#endif - -#if STM32_GPT_USE_TIM5 -#if defined(STM32_TIM5_IS_USED) -#error "GPTD5 requires TIM5 but the timer is already used" -#else -#define STM32_TIM5_IS_USED -#endif -#endif - -#if STM32_GPT_USE_TIM6 -#if defined(STM32_TIM6_IS_USED) -#error "GPTD6 requires TIM6 but the timer is already used" -#else -#define STM32_TIM6_IS_USED -#endif -#endif - -#if STM32_GPT_USE_TIM7 -#if defined(STM32_TIM7_IS_USED) -#error "GPTD7 requires TIM7 but the timer is already used" -#else -#define STM32_TIM7_IS_USED -#endif -#endif - -#if STM32_GPT_USE_TIM8 -#if defined(STM32_TIM8_IS_USED) -#error "GPTD8 requires TIM8 but the timer is already used" -#else -#define STM32_TIM8_IS_USED -#endif -#endif - -#if STM32_GPT_USE_TIM9 -#if defined(STM32_TIM9_IS_USED) -#error "GPTD9 requires TIM9 but the timer is already used" -#else -#define STM32_TIM9_IS_USED -#endif -#endif - -#if STM32_GPT_USE_TIM11 -#if defined(STM32_TIM11_IS_USED) -#error "GPTD11 requires TIM11 but the timer is already used" -#else -#define STM32_TIM11_IS_USED -#endif -#endif - -#if STM32_GPT_USE_TIM12 -#if defined(STM32_TIM12_IS_USED) -#error "GPTD12 requires TIM12 but the timer is already used" -#else -#define STM32_TIM12_IS_USED -#endif -#endif - -#if STM32_GPT_USE_TIM14 -#if defined(STM32_TIM14_IS_USED) -#error "GPTD14 requires TIM14 but the timer is already used" -#else -#define STM32_TIM14_IS_USED -#endif -#endif - -/* IRQ priority checks.*/ -#if STM32_GPT_USE_TIM1 && !defined(STM32_TIM1_SUPPRESS_ISR) && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_GPT_TIM1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM1" -#endif - -#if STM32_GPT_USE_TIM2 && !defined(STM32_TIM2_SUPPRESS_ISR) && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_GPT_TIM2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM2" -#endif - -#if STM32_GPT_USE_TIM3 && !defined(STM32_TIM3_SUPPRESS_ISR) && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_GPT_TIM3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM3" -#endif - -#if STM32_GPT_USE_TIM4 && !defined(STM32_TIM_SUPPRESS_ISR) && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_GPT_TIM4_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM4" -#endif - -#if STM32_GPT_USE_TIM5 && !defined(STM32_TIM5_SUPPRESS_ISR) && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_GPT_TIM5_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM5" -#endif - -#if STM32_GPT_USE_TIM6 && !defined(STM32_TIM6_SUPPRESS_ISR) && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_GPT_TIM6_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM6" -#endif - -#if STM32_GPT_USE_TIM7 && !defined(STM32_TIM7_SUPPRESS_ISR) && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_GPT_TIM7_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM7" -#endif - -#if STM32_GPT_USE_TIM8 && !defined(STM32_TIM8_SUPPRESS_ISR) && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_GPT_TIM8_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM8" -#endif - -#if STM32_GPT_USE_TIM9 && !defined(STM32_TIM9_SUPPRESS_ISR) && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_GPT_TIM9_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM9" -#endif - -#if STM32_GPT_USE_TIM11 && !defined(STM32_TIM11_SUPPRESS_ISR) && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_GPT_TIM11_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM11" -#endif - -#if STM32_GPT_USE_TIM12 && !defined(STM32_TIM12_SUPPRESS_ISR) && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_GPT_TIM12_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM12" -#endif - -#if STM32_GPT_USE_TIM14 && !defined(STM32_TIM14_SUPPRESS_ISR) && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_GPT_TIM14_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM14" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief GPT frequency type. - */ -typedef uint32_t gptfreq_t; - -/** - * @brief GPT counter type. - */ -typedef uint32_t gptcnt_t; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief Timer clock in Hz. - * @note The low level can use assertions in order to catch invalid - * frequency specifications. - */ - gptfreq_t frequency; - /** - * @brief Timer callback pointer. - * @note This callback is invoked on GPT counter events. - * @note This callback can be set to @p NULL but in that case the - * one-shot mode cannot be used. - */ - gptcallback_t callback; - /* End of the mandatory fields.*/ - /** - * @brief TIM CR2 register initialization data. - * @note The value of this field should normally be equal to zero. - */ - uint32_t cr2; - /** - * @brief TIM DIER register initialization data. - * @note The value of this field should normally be equal to zero. - * @note Only the DMA-related bits can be specified in this field. - */ - uint32_t dier; -} GPTConfig; - -/** - * @brief Structure representing a GPT driver. - */ -struct GPTDriver { - /** - * @brief Driver state. - */ - gptstate_t state; - /** - * @brief Current configuration data. - */ - const GPTConfig *config; -#if defined(GPT_DRIVER_EXT_FIELDS) - GPT_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Timer base clock. - */ - uint32_t clock; - /** - * @brief Pointer to the TIMx registers block. - */ - stm32_tim_t *tim; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Changes the interval of GPT peripheral. - * @details This function changes the interval of a running GPT unit. - * @pre The GPT unit must be running in continuous mode. - * @post The GPT unit interval is changed to the new value. - * @note The function has effect at the next cycle start. - * - * @param[in] gptp pointer to a @p GPTDriver object - * @param[in] interval new cycle time in timer ticks - * - * @notapi - */ -#define gpt_lld_change_interval(gptp, interval) \ - ((gptp)->tim->ARR = (uint32_t)((interval) - 1)) - -/** - * @brief Returns the interval of GPT peripheral. - * @pre The GPT unit must be running in continuous mode. - * - * @param[in] gptp pointer to a @p GPTDriver object - * @return The current interval. - * - * @notapi - */ -#define gpt_lld_get_interval(gptp) ((gptcnt_t)(gptp)->tim->ARR + 1) - -/** - * @brief Returns the counter value of GPT peripheral. - * @pre The GPT unit must be running in continuous mode. - * @note The nature of the counter is not defined, it may count upward - * or downward, it could be continuously running or not. - * - * @param[in] gptp pointer to a @p GPTDriver object - * @return The current counter value. - * - * @notapi - */ -#define gpt_lld_get_counter(gptp) ((gptcnt_t)(gptp)->tim->CNT) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_GPT_USE_TIM1 && !defined(__DOXYGEN__) -extern GPTDriver GPTD1; -#endif - -#if STM32_GPT_USE_TIM2 && !defined(__DOXYGEN__) -extern GPTDriver GPTD2; -#endif - -#if STM32_GPT_USE_TIM3 && !defined(__DOXYGEN__) -extern GPTDriver GPTD3; -#endif - -#if STM32_GPT_USE_TIM4 && !defined(__DOXYGEN__) -extern GPTDriver GPTD4; -#endif - -#if STM32_GPT_USE_TIM5 && !defined(__DOXYGEN__) -extern GPTDriver GPTD5; -#endif - -#if STM32_GPT_USE_TIM6 && !defined(__DOXYGEN__) -extern GPTDriver GPTD6; -#endif - -#if STM32_GPT_USE_TIM7 && !defined(__DOXYGEN__) -extern GPTDriver GPTD7; -#endif - -#if STM32_GPT_USE_TIM8 && !defined(__DOXYGEN__) -extern GPTDriver GPTD8; -#endif - -#if STM32_GPT_USE_TIM9 && !defined(__DOXYGEN__) -extern GPTDriver GPTD9; -#endif - -#if STM32_GPT_USE_TIM11 && !defined(__DOXYGEN__) -extern GPTDriver GPTD11; -#endif - -#if STM32_GPT_USE_TIM12 && !defined(__DOXYGEN__) -extern GPTDriver GPTD12; -#endif - -#if STM32_GPT_USE_TIM14 && !defined(__DOXYGEN__) -extern GPTDriver GPTD14; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void gpt_lld_init(void); - void gpt_lld_start(GPTDriver *gptp); - void gpt_lld_stop(GPTDriver *gptp); - void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period); - void gpt_lld_stop_timer(GPTDriver *gptp); - void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval); - void gpt_lld_serve_interrupt(GPTDriver *gptp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_GPT */ - -#endif /* _GPT_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c deleted file mode 100644 index aaeb16efa0..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c +++ /dev/null @@ -1,805 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Concepts and parts of this file have been contributed by Fabio Utzig and - Xo Wang. - */ - -/** - * @file STM32/icu_lld.c - * @brief STM32 ICU subsystem low level driver header. - * - * @addtogroup ICU - * @{ - */ - -#include "hal.h" - -#if HAL_USE_ICU || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief ICUD1 driver identifier. - * @note The driver ICUD1 allocates the complex timer TIM1 when enabled. - */ -#if STM32_ICU_USE_TIM1 || defined(__DOXYGEN__) -ICUDriver ICUD1; -#endif - -/** - * @brief ICUD2 driver identifier. - * @note The driver ICUD1 allocates the timer TIM2 when enabled. - */ -#if STM32_ICU_USE_TIM2 || defined(__DOXYGEN__) -ICUDriver ICUD2; -#endif - -/** - * @brief ICUD3 driver identifier. - * @note The driver ICUD1 allocates the timer TIM3 when enabled. - */ -#if STM32_ICU_USE_TIM3 || defined(__DOXYGEN__) -ICUDriver ICUD3; -#endif - -/** - * @brief ICUD4 driver identifier. - * @note The driver ICUD4 allocates the timer TIM4 when enabled. - */ -#if STM32_ICU_USE_TIM4 || defined(__DOXYGEN__) -ICUDriver ICUD4; -#endif - -/** - * @brief ICUD5 driver identifier. - * @note The driver ICUD5 allocates the timer TIM5 when enabled. - */ -#if STM32_ICU_USE_TIM5 || defined(__DOXYGEN__) -ICUDriver ICUD5; -#endif - -/** - * @brief ICUD8 driver identifier. - * @note The driver ICUD8 allocates the timer TIM8 when enabled. - */ -#if STM32_ICU_USE_TIM8 || defined(__DOXYGEN__) -ICUDriver ICUD8; -#endif - -/** - * @brief ICUD9 driver identifier. - * @note The driver ICUD9 allocates the timer TIM9 when enabled. - */ -#if STM32_ICU_USE_TIM9 || defined(__DOXYGEN__) -ICUDriver ICUD9; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static bool icu_lld_wait_edge(ICUDriver *icup) { - uint32_t sr; - bool result; - - /* Polled mode so re-enabling the interrupts while the operation is - performed.*/ - osalSysUnlock(); - - /* Polling the right bit depending on the input channel.*/ - if (icup->config->channel == ICU_CHANNEL_1) { - /* Waiting for an edge.*/ - while (((sr = icup->tim->SR) & - (STM32_TIM_SR_CC1IF | STM32_TIM_SR_UIF)) == 0) - ; - } - else { - /* Waiting for an edge.*/ - while (((sr = icup->tim->SR) & - (STM32_TIM_SR_CC2IF | STM32_TIM_SR_UIF)) == 0) - ; - } - - /* Edge or overflow?*/ - result = (sr & STM32_TIM_SR_UIF) != 0 ? true : false; - - /* Done, disabling interrupts again.*/ - osalSysLock(); - - /* Resetting all flags.*/ - icup->tim->SR &= ~(STM32_TIM_SR_CC1IF | - STM32_TIM_SR_CC2IF | - STM32_TIM_SR_UIF); - - return result; -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if STM32_ICU_USE_TIM1 || defined(__DOXYGEN__) -#if !defined(STM32_TIM1_SUPPRESS_ISR) -#if !defined(STM32_TIM1_UP_HANDLER) -#error "STM32_TIM1_UP_HANDLER not defined" -#endif -/** - * @brief TIM1 compare interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - icu_lld_serve_interrupt(&ICUD1); - - OSAL_IRQ_EPILOGUE(); -} - -#if !defined(STM32_TIM1_CC_HANDLER) -#error "STM32_TIM1_CC_HANDLER not defined" -#endif -/** - * @brief TIM1 compare interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM1_CC_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - icu_lld_serve_interrupt(&ICUD1); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* !defined(STM32_TIM1_SUPPRESS_ISR) */ -#endif /* STM32_ICU_USE_TIM1 */ - -#if STM32_ICU_USE_TIM2 || defined(__DOXYGEN__) -#if !defined(STM32_TIM2_SUPPRESS_ISR) -#if !defined(STM32_TIM2_HANDLER) -#error "STM32_TIM2_HANDLER not defined" -#endif -/** - * @brief TIM2 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM2_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - icu_lld_serve_interrupt(&ICUD2); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* !defined(STM32_TIM2_SUPPRESS_ISR) */ -#endif /* STM32_ICU_USE_TIM2 */ - -#if STM32_ICU_USE_TIM3 || defined(__DOXYGEN__) -#if !defined(STM32_TIM3_SUPPRESS_ISR) -#if !defined(STM32_TIM3_HANDLER) -#error "STM32_TIM3_HANDLER not defined" -#endif -/** - * @brief TIM3 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM3_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - icu_lld_serve_interrupt(&ICUD3); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* !defined(STM32_TIM3_SUPPRESS_ISR) */ -#endif /* STM32_ICU_USE_TIM3 */ - -#if STM32_ICU_USE_TIM4 || defined(__DOXYGEN__) -#if !defined(STM32_TIM4_SUPPRESS_ISR) -#if !defined(STM32_TIM4_HANDLER) -#error "STM32_TIM4_HANDLER not defined" -#endif -/** - * @brief TIM4 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM4_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - icu_lld_serve_interrupt(&ICUD4); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* !defined(STM32_TIM4_SUPPRESS_ISR) */ -#endif /* STM32_ICU_USE_TIM4 */ - -#if STM32_ICU_USE_TIM5 || defined(__DOXYGEN__) -#if !defined(STM32_TIM5_SUPPRESS_ISR) -#if !defined(STM32_TIM5_HANDLER) -#error "STM32_TIM5_HANDLER not defined" -#endif -/** - * @brief TIM5 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM5_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - icu_lld_serve_interrupt(&ICUD5); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* !defined(STM32_TIM5_SUPPRESS_ISR) */ -#endif /* STM32_ICU_USE_TIM5 */ - -#if STM32_ICU_USE_TIM8 || defined(__DOXYGEN__) -#if !defined(STM32_TIM8_SUPPRESS_ISR) -#if !defined(STM32_TIM8_UP_HANDLER) -#error "STM32_TIM8_UP_HANDLER not defined" -#endif -/** - * @brief TIM8 compare interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - icu_lld_serve_interrupt(&ICUD8); - - OSAL_IRQ_EPILOGUE(); -} - -#if !defined(STM32_TIM8_CC_HANDLER) -#error "STM32_TIM8_CC_HANDLER not defined" -#endif -/** - * @brief TIM8 compare interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM8_CC_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - icu_lld_serve_interrupt(&ICUD8); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* !defined(STM32_TIM8_SUPPRESS_ISR) */ -#endif /* STM32_ICU_USE_TIM8 */ - -#if STM32_ICU_USE_TIM9 || defined(__DOXYGEN__) -#if !defined(STM32_TIM9_SUPPRESS_ISR) -#if !defined(STM32_TIM9_HANDLER) -#error "STM32_TIM9_HANDLER not defined" -#endif -/** - * @brief TIM9 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM9_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - icu_lld_serve_interrupt(&ICUD9); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* !defined(STM32_TIM9_SUPPRESS_ISR) */ -#endif /* STM32_ICU_USE_TIM9 */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level ICU driver initialization. - * - * @notapi - */ -void icu_lld_init(void) { - -#if STM32_ICU_USE_TIM1 - /* Driver initialization.*/ - icuObjectInit(&ICUD1); - ICUD1.tim = STM32_TIM1; -#endif - -#if STM32_ICU_USE_TIM2 - /* Driver initialization.*/ - icuObjectInit(&ICUD2); - ICUD2.tim = STM32_TIM2; -#endif - -#if STM32_ICU_USE_TIM3 - /* Driver initialization.*/ - icuObjectInit(&ICUD3); - ICUD3.tim = STM32_TIM3; -#endif - -#if STM32_ICU_USE_TIM4 - /* Driver initialization.*/ - icuObjectInit(&ICUD4); - ICUD4.tim = STM32_TIM4; -#endif - -#if STM32_ICU_USE_TIM5 - /* Driver initialization.*/ - icuObjectInit(&ICUD5); - ICUD5.tim = STM32_TIM5; -#endif - -#if STM32_ICU_USE_TIM8 - /* Driver initialization.*/ - icuObjectInit(&ICUD8); - ICUD8.tim = STM32_TIM8; -#endif - -#if STM32_ICU_USE_TIM9 - /* Driver initialization.*/ - icuObjectInit(&ICUD9); - ICUD9.tim = STM32_TIM9; -#endif -} - -/** - * @brief Configures and activates the ICU peripheral. - * - * @param[in] icup pointer to the @p ICUDriver object - * - * @notapi - */ -void icu_lld_start(ICUDriver *icup) { - uint32_t psc; - - osalDbgAssert((icup->config->channel == ICU_CHANNEL_1) || - (icup->config->channel == ICU_CHANNEL_2), - "invalid input"); - - if (icup->state == ICU_STOP) { - /* Clock activation and timer reset.*/ -#if STM32_ICU_USE_TIM1 - if (&ICUD1 == icup) { - rccEnableTIM1(FALSE); - rccResetTIM1(); -#if !defined(STM32_TIM1_SUPPRESS_ISR) - nvicEnableVector(STM32_TIM1_UP_NUMBER, STM32_ICU_TIM1_IRQ_PRIORITY); - nvicEnableVector(STM32_TIM1_CC_NUMBER, STM32_ICU_TIM1_IRQ_PRIORITY); -#endif -#if defined(STM32_TIM1CLK) - icup->clock = STM32_TIM1CLK; -#else - icup->clock = STM32_TIMCLK2; -#endif - } -#endif - -#if STM32_ICU_USE_TIM2 - if (&ICUD2 == icup) { - rccEnableTIM2(FALSE); - rccResetTIM2(); -#if !defined(STM32_TIM2_SUPPRESS_ISR) - nvicEnableVector(STM32_TIM2_NUMBER, STM32_ICU_TIM2_IRQ_PRIORITY); -#endif -#if defined(STM32_TIM2CLK) - icup->clock = STM32_TIM2CLK; -#else - icup->clock = STM32_TIMCLK1; -#endif - } -#endif - -#if STM32_ICU_USE_TIM3 - if (&ICUD3 == icup) { - rccEnableTIM3(FALSE); - rccResetTIM3(); -#if !defined(STM32_TIM3_SUPPRESS_ISR) - nvicEnableVector(STM32_TIM3_NUMBER, STM32_ICU_TIM3_IRQ_PRIORITY); -#endif -#if defined(STM32_TIM3CLK) - icup->clock = STM32_TIM3CLK; -#else - icup->clock = STM32_TIMCLK1; -#endif - } -#endif - -#if STM32_ICU_USE_TIM4 - if (&ICUD4 == icup) { - rccEnableTIM4(FALSE); - rccResetTIM4(); -#if !defined(STM32_TIM4_SUPPRESS_ISR) - nvicEnableVector(STM32_TIM4_NUMBER, STM32_ICU_TIM4_IRQ_PRIORITY); -#endif -#if defined(STM32_TIM4CLK) - icup->clock = STM32_TIM4CLK; -#else - icup->clock = STM32_TIMCLK1; -#endif - } -#endif - -#if STM32_ICU_USE_TIM5 - if (&ICUD5 == icup) { - rccEnableTIM5(FALSE); - rccResetTIM5(); -#if !defined(STM32_TIM5_SUPPRESS_ISR) - nvicEnableVector(STM32_TIM5_NUMBER, STM32_ICU_TIM5_IRQ_PRIORITY); -#endif -#if defined(STM32_TIM5CLK) - icup->clock = STM32_TIM5CLK; -#else - icup->clock = STM32_TIMCLK1; -#endif - } -#endif - -#if STM32_ICU_USE_TIM8 - if (&ICUD8 == icup) { - rccEnableTIM8(FALSE); - rccResetTIM8(); -#if !defined(STM32_TIM8_SUPPRESS_ISR) - nvicEnableVector(STM32_TIM8_UP_NUMBER, STM32_ICU_TIM8_IRQ_PRIORITY); - nvicEnableVector(STM32_TIM8_CC_NUMBER, STM32_ICU_TIM8_IRQ_PRIORITY); -#endif -#if defined(STM32_TIM8CLK) - icup->clock = STM32_TIM8CLK; -#else - icup->clock = STM32_TIMCLK2; -#endif - } -#endif - -#if STM32_ICU_USE_TIM9 - if (&ICUD9 == icup) { - rccEnableTIM9(FALSE); - rccResetTIM9(); -#if !defined(STM32_TIM9_SUPPRESS_ISR) - nvicEnableVector(STM32_TIM9_NUMBER, STM32_ICU_TIM9_IRQ_PRIORITY); -#endif -#if defined(STM32_TIM9CLK) - icup->clock = STM32_TIM9CLK; -#else - icup->clock = STM32_TIMCLK2; -#endif - } -#endif - } - else { - /* Driver re-configuration scenario, it must be stopped first.*/ - icup->tim->CR1 = 0; /* Timer disabled. */ - icup->tim->CCR[0] = 0; /* Comparator 1 disabled. */ - icup->tim->CCR[1] = 0; /* Comparator 2 disabled. */ - icup->tim->CNT = 0; /* Counter reset to zero. */ - } - - /* Timer configuration.*/ - icup->tim->SR = 0; /* Clear eventual pending IRQs. */ - icup->tim->DIER = icup->config->dier & /* DMA-related DIER settings. */ - ~STM32_TIM_DIER_IRQ_MASK; - psc = (icup->clock / icup->config->frequency) - 1; - osalDbgAssert((psc <= 0xFFFF) && - ((psc + 1) * icup->config->frequency) == icup->clock, - "invalid frequency"); - icup->tim->PSC = psc; - icup->tim->ARR = 0xFFFF; - - if (icup->config->channel == ICU_CHANNEL_1) { - /* Selected input 1. - CCMR1_CC1S = 01 = CH1 Input on TI1. - CCMR1_CC2S = 10 = CH2 Input on TI1.*/ - icup->tim->CCMR1 = STM32_TIM_CCMR1_CC1S(1) | STM32_TIM_CCMR1_CC2S(2); - - /* SMCR_TS = 101, input is TI1FP1. - SMCR_SMS = 100, reset on rising edge.*/ - icup->tim->SMCR = STM32_TIM_SMCR_TS(5) | STM32_TIM_SMCR_SMS(4); - - /* The CCER settings depend on the selected trigger mode. - ICU_INPUT_ACTIVE_HIGH: Active on rising edge, idle on falling edge. - ICU_INPUT_ACTIVE_LOW: Active on falling edge, idle on rising edge.*/ - if (icup->config->mode == ICU_INPUT_ACTIVE_HIGH) - icup->tim->CCER = STM32_TIM_CCER_CC1E | - STM32_TIM_CCER_CC2E | STM32_TIM_CCER_CC2P; - else - icup->tim->CCER = STM32_TIM_CCER_CC1E | STM32_TIM_CCER_CC1P | - STM32_TIM_CCER_CC2E; - - /* Direct pointers to the capture registers in order to make reading - data faster from within callbacks.*/ - icup->wccrp = &icup->tim->CCR[1]; - icup->pccrp = &icup->tim->CCR[0]; - } - else { - /* Selected input 2. - CCMR1_CC1S = 10 = CH1 Input on TI2. - CCMR1_CC2S = 01 = CH2 Input on TI2.*/ - icup->tim->CCMR1 = STM32_TIM_CCMR1_CC1S(2) | STM32_TIM_CCMR1_CC2S(1); - - /* SMCR_TS = 110, input is TI2FP2. - SMCR_SMS = 100, reset on rising edge.*/ - icup->tim->SMCR = STM32_TIM_SMCR_TS(6) | STM32_TIM_SMCR_SMS(4); - - /* The CCER settings depend on the selected trigger mode. - ICU_INPUT_ACTIVE_HIGH: Active on rising edge, idle on falling edge. - ICU_INPUT_ACTIVE_LOW: Active on falling edge, idle on rising edge.*/ - if (icup->config->mode == ICU_INPUT_ACTIVE_HIGH) - icup->tim->CCER = STM32_TIM_CCER_CC1E | STM32_TIM_CCER_CC1P | - STM32_TIM_CCER_CC2E; - else - icup->tim->CCER = STM32_TIM_CCER_CC1E | - STM32_TIM_CCER_CC2E | STM32_TIM_CCER_CC2P; - - /* Direct pointers to the capture registers in order to make reading - data faster from within callbacks.*/ - icup->wccrp = &icup->tim->CCR[0]; - icup->pccrp = &icup->tim->CCR[1]; - } -} - -/** - * @brief Deactivates the ICU peripheral. - * - * @param[in] icup pointer to the @p ICUDriver object - * - * @notapi - */ -void icu_lld_stop(ICUDriver *icup) { - - if (icup->state == ICU_READY) { - /* Clock deactivation.*/ - icup->tim->CR1 = 0; /* Timer disabled. */ - icup->tim->DIER = 0; /* All IRQs disabled. */ - icup->tim->SR = 0; /* Clear eventual pending IRQs. */ - -#if STM32_ICU_USE_TIM1 - if (&ICUD1 == icup) { -#if !defined(STM32_TIM1_SUPPRESS_ISR) - nvicDisableVector(STM32_TIM1_UP_NUMBER); - nvicDisableVector(STM32_TIM1_CC_NUMBER); -#endif - rccDisableTIM1(FALSE); - } -#endif - -#if STM32_ICU_USE_TIM2 - if (&ICUD2 == icup) { -#if !defined(STM32_TIM2_SUPPRESS_ISR) - nvicDisableVector(STM32_TIM2_NUMBER); -#endif - rccDisableTIM2(FALSE); - } -#endif - -#if STM32_ICU_USE_TIM3 - if (&ICUD3 == icup) { -#if !defined(STM32_TIM3_SUPPRESS_ISR) - nvicDisableVector(STM32_TIM3_NUMBER); -#endif - rccDisableTIM3(FALSE); - } -#endif - -#if STM32_ICU_USE_TIM4 - if (&ICUD4 == icup) { -#if !defined(STM32_TIM4_SUPPRESS_ISR) - nvicDisableVector(STM32_TIM4_NUMBER); -#endif - rccDisableTIM4(FALSE); - } -#endif - -#if STM32_ICU_USE_TIM5 - if (&ICUD5 == icup) { -#if !defined(STM32_TIM5_SUPPRESS_ISR) - nvicDisableVector(STM32_TIM5_NUMBER); -#endif - rccDisableTIM5(FALSE); - } -#endif - -#if STM32_ICU_USE_TIM8 - if (&ICUD8 == icup) { -#if !defined(STM32_TIM8_SUPPRESS_ISR) - nvicDisableVector(STM32_TIM8_UP_NUMBER); - nvicDisableVector(STM32_TIM8_CC_NUMBER); -#endif - rccDisableTIM8(FALSE); - } -#endif - -#if STM32_ICU_USE_TIM9 - if (&ICUD9 == icup) { -#if !defined(STM32_TIM9_SUPPRESS_ISR) - nvicDisableVector(STM32_TIM9_NUMBER); -#endif - rccDisableTIM9(FALSE); - } -#endif - } -} - -/** - * @brief Starts the input capture. - * - * @param[in] icup pointer to the @p ICUDriver object - * - * @notapi - */ -void icu_lld_start_capture(ICUDriver *icup) { - - /* Triggering an UG and clearing the IRQ status.*/ - icup->tim->EGR |= STM32_TIM_EGR_UG; - icup->tim->SR = 0; - - /* Timer is started.*/ - icup->tim->CR1 = STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN; -} - -/** - * @brief Waits for a completed capture. - * @note The operation is performed in polled mode. - * @note In order to use this function notifications must be disabled. - * - * @param[in] icup pointer to the @p ICUDriver object - * @return The capture status. - * @retval false if the capture is successful. - * @retval true if a timer overflow occurred. - * - * @notapi - */ -bool icu_lld_wait_capture(ICUDriver *icup) { - - /* If the driver is still in the ICU_WAITING state then we need to wait - for the first activation edge.*/ - if (icup->state == ICU_WAITING) - if (icu_lld_wait_edge(icup)) - return true; - - /* This edge marks the availability of a capture result.*/ - return icu_lld_wait_edge(icup); -} - -/** - * @brief Stops the input capture. - * - * @param[in] icup pointer to the @p ICUDriver object - * - * @notapi - */ -void icu_lld_stop_capture(ICUDriver *icup) { - - /* Timer stopped.*/ - icup->tim->CR1 = 0; - - /* All interrupts disabled.*/ - icup->tim->DIER &= ~STM32_TIM_DIER_IRQ_MASK; -} - -/** - * @brief Enables notifications. - * @pre The ICU unit must have been activated using @p icuStart(). - * @note If the notification is already enabled then the call has no effect. - * - * @param[in] icup pointer to the @p ICUDriver object - * - * @notapi - */ -void icu_lld_enable_notifications(ICUDriver *icup) { - uint32_t dier = icup->tim->DIER; - - /* If interrupts were already enabled then the operation is skipped. - This is done in order to avoid clearing the SR and risk losing - pending interrupts.*/ - if ((dier & STM32_TIM_DIER_IRQ_MASK) == 0) { - /* Previously triggered IRQs are ignored, status cleared.*/ - icup->tim->SR = 0; - - if (icup->config->channel == ICU_CHANNEL_1) { - /* Enabling periodic callback on CC1.*/ - dier |= STM32_TIM_DIER_CC1IE; - - /* Optionally enabling width callback on CC2.*/ - if (icup->config->width_cb != NULL) - dier |= STM32_TIM_DIER_CC2IE; - } - else { - /* Enabling periodic callback on CC2.*/ - dier |= STM32_TIM_DIER_CC2IE; - - /* Optionally enabling width callback on CC1.*/ - if (icup->config->width_cb != NULL) - dier |= STM32_TIM_DIER_CC1IE; - } - - /* If an overflow callback is defined then also the overflow callback - is enabled.*/ - if (icup->config->overflow_cb != NULL) - dier |= STM32_TIM_DIER_UIE; - - /* One single atomic write.*/ - icup->tim->DIER = dier; - } -} - -/** - * @brief Disables notifications. - * @pre The ICU unit must have been activated using @p icuStart(). - * @note If the notification is already disabled then the call has no effect. - * - * @param[in] icup pointer to the @p ICUDriver object - * - * @notapi - */ -void icu_lld_disable_notifications(ICUDriver *icup) { - - /* All interrupts disabled.*/ - icup->tim->DIER &= ~STM32_TIM_DIER_IRQ_MASK; -} - -/** - * @brief Shared IRQ handler. - * - * @param[in] icup pointer to the @p ICUDriver object - * - * @notapi - */ -void icu_lld_serve_interrupt(ICUDriver *icup) { - uint32_t sr; - - sr = icup->tim->SR; - sr &= icup->tim->DIER & STM32_TIM_DIER_IRQ_MASK; - icup->tim->SR = ~sr; - if (icup->config->channel == ICU_CHANNEL_1) { - if ((sr & STM32_TIM_SR_CC2IF) != 0) - _icu_isr_invoke_width_cb(icup); - if ((sr & STM32_TIM_SR_CC1IF) != 0) - _icu_isr_invoke_period_cb(icup); - } - else { - if ((sr & STM32_TIM_SR_CC1IF) != 0) - _icu_isr_invoke_width_cb(icup); - if ((sr & STM32_TIM_SR_CC2IF) != 0) - _icu_isr_invoke_period_cb(icup); - } - if ((sr & STM32_TIM_SR_UIF) != 0) - _icu_isr_invoke_overflow_cb(icup); -} - -#endif /* HAL_USE_ICU */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/TIMv1/icu_lld.h b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/TIMv1/icu_lld.h deleted file mode 100644 index a557d64c53..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/TIMv1/icu_lld.h +++ /dev/null @@ -1,487 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/icu_lld.h - * @brief STM32 ICU subsystem low level driver header. - * - * @addtogroup ICU - * @{ - */ - -#ifndef _ICU_LLD_H_ -#define _ICU_LLD_H_ - -#if HAL_USE_ICU || defined(__DOXYGEN__) - -#include "stm32_tim.h" - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief ICUD1 driver enable switch. - * @details If set to @p TRUE the support for ICUD1 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_ICU_USE_TIM1) || defined(__DOXYGEN__) -#define STM32_ICU_USE_TIM1 FALSE -#endif - -/** - * @brief ICUD2 driver enable switch. - * @details If set to @p TRUE the support for ICUD2 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_ICU_USE_TIM2) || defined(__DOXYGEN__) -#define STM32_ICU_USE_TIM2 FALSE -#endif - -/** - * @brief ICUD3 driver enable switch. - * @details If set to @p TRUE the support for ICUD3 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_ICU_USE_TIM3) || defined(__DOXYGEN__) -#define STM32_ICU_USE_TIM3 FALSE -#endif - -/** - * @brief ICUD4 driver enable switch. - * @details If set to @p TRUE the support for ICUD4 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_ICU_USE_TIM4) || defined(__DOXYGEN__) -#define STM32_ICU_USE_TIM4 FALSE -#endif - -/** - * @brief ICUD5 driver enable switch. - * @details If set to @p TRUE the support for ICUD5 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_ICU_USE_TIM5) || defined(__DOXYGEN__) -#define STM32_ICU_USE_TIM5 FALSE -#endif - -/** - * @brief ICUD8 driver enable switch. - * @details If set to @p TRUE the support for ICUD8 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_ICU_USE_TIM8) || defined(__DOXYGEN__) -#define STM32_ICU_USE_TIM8 FALSE -#endif - -/** - * @brief ICUD9 driver enable switch. - * @details If set to @p TRUE the support for ICUD9 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_ICU_USE_TIM9) || defined(__DOXYGEN__) -#define STM32_ICU_USE_TIM9 FALSE -#endif - -/** - * @brief ICUD1 interrupt priority level setting. - */ -#if !defined(STM32_ICU_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ICU_TIM1_IRQ_PRIORITY 7 -#endif - -/** - * @brief ICUD2 interrupt priority level setting. - */ -#if !defined(STM32_ICU_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ICU_TIM2_IRQ_PRIORITY 7 -#endif - -/** - * @brief ICUD3 interrupt priority level setting. - */ -#if !defined(STM32_ICU_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ICU_TIM3_IRQ_PRIORITY 7 -#endif - -/** - * @brief ICUD4 interrupt priority level setting. - */ -#if !defined(STM32_ICU_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ICU_TIM4_IRQ_PRIORITY 7 -#endif - -/** - * @brief ICUD5 interrupt priority level setting. - */ -#if !defined(STM32_ICU_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ICU_TIM5_IRQ_PRIORITY 7 -#endif - -/** - * @brief ICUD8 interrupt priority level setting. - */ -#if !defined(STM32_ICU_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ICU_TIM8_IRQ_PRIORITY 7 -#endif - -/** - * @brief ICUD9 interrupt priority level setting. - */ -#if !defined(STM32_ICU_TIM9_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ICU_TIM9_IRQ_PRIORITY 7 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_ICU_USE_TIM1 && !STM32_HAS_TIM1 -#error "TIM1 not present in the selected device" -#endif - -#if STM32_ICU_USE_TIM2 && !STM32_HAS_TIM2 -#error "TIM2 not present in the selected device" -#endif - -#if STM32_ICU_USE_TIM3 && !STM32_HAS_TIM3 -#error "TIM3 not present in the selected device" -#endif - -#if STM32_ICU_USE_TIM4 && !STM32_HAS_TIM4 -#error "TIM4 not present in the selected device" -#endif - -#if STM32_ICU_USE_TIM5 && !STM32_HAS_TIM5 -#error "TIM5 not present in the selected device" -#endif - -#if STM32_ICU_USE_TIM8 && !STM32_HAS_TIM8 -#error "TIM8 not present in the selected device" -#endif - -#if STM32_ICU_USE_TIM9 && !STM32_HAS_TIM9 -#error "TIM9 not present in the selected device" -#endif - -#if !STM32_ICU_USE_TIM1 && !STM32_ICU_USE_TIM2 && \ - !STM32_ICU_USE_TIM3 && !STM32_ICU_USE_TIM4 && \ - !STM32_ICU_USE_TIM5 && !STM32_ICU_USE_TIM8 && \ - !STM32_ICU_USE_TIM9 -#error "ICU driver activated but no TIM peripheral assigned" -#endif - -/* Checks on allocation of TIMx units.*/ -#if STM32_ICU_USE_TIM1 -#if defined(STM32_TIM1_IS_USED) -#error "ICUD1 requires TIM1 but the timer is already used" -#else -#define STM32_TIM1_IS_USED -#endif -#endif - -#if STM32_ICU_USE_TIM2 -#if defined(STM32_TIM2_IS_USED) -#error "ICUD2 requires TIM2 but the timer is already used" -#else -#define STM32_TIM2_IS_USED -#endif -#endif - -#if STM32_ICU_USE_TIM3 -#if defined(STM32_TIM3_IS_USED) -#error "ICUD3 requires TIM3 but the timer is already used" -#else -#define STM32_TIM3_IS_USED -#endif -#endif - -#if STM32_ICU_USE_TIM4 -#if defined(STM32_TIM4_IS_USED) -#error "ICUD4 requires TIM4 but the timer is already used" -#else -#define STM32_TIM4_IS_USED -#endif -#endif - -#if STM32_ICU_USE_TIM5 -#if defined(STM32_TIM5_IS_USED) -#error "ICUD5 requires TIM5 but the timer is already used" -#else -#define STM32_TIM5_IS_USED -#endif -#endif - -#if STM32_ICU_USE_TIM8 -#if defined(STM32_TIM8_IS_USED) -#error "ICUD8 requires TIM8 but the timer is already used" -#else -#define STM32_TIM8_IS_USED -#endif -#endif - -#if STM32_ICU_USE_TIM9 -#if defined(STM32_TIM9_IS_USED) -#error "ICUD9 requires TIM9 but the timer is already used" -#else -#define STM32_TIM9_IS_USED -#endif -#endif - -/* IRQ priority checks.*/ -#if STM32_ICU_USE_TIM1 && !defined(STM32_TIM1_SUPPRESS_ISR) && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ICU_TIM1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM1" -#endif - -#if STM32_ICU_USE_TIM2 && !defined(STM32_TIM2_SUPPRESS_ISR) && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ICU_TIM2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM2" -#endif - -#if STM32_ICU_USE_TIM3 && !defined(STM32_TIM3_SUPPRESS_ISR) && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ICU_TIM3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM3" -#endif - -#if STM32_ICU_USE_TIM4 && !defined(STM32_TIM4_SUPPRESS_ISR) && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ICU_TIM4_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM4" -#endif - -#if STM32_ICU_USE_TIM5 && !defined(STM32_TIM5_SUPPRESS_ISR) && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ICU_TIM5_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM5" -#endif - -#if STM32_ICU_USE_TIM8 && !defined(STM32_TIM8_SUPPRESS_ISR) && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ICU_TIM8_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM8" -#endif - -#if STM32_ICU_USE_TIM9 && !defined(STM32_TIM9_SUPPRESS_ISR) && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ICU_TIM9_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM9" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief ICU driver mode. - */ -typedef enum { - ICU_INPUT_ACTIVE_HIGH = 0, /**< Trigger on rising edge. */ - ICU_INPUT_ACTIVE_LOW = 1, /**< Trigger on falling edge. */ -} icumode_t; - -/** - * @brief ICU frequency type. - */ -typedef uint32_t icufreq_t; - -/** - * @brief ICU channel type. - */ -typedef enum { - ICU_CHANNEL_1 = 0, /**< Use TIMxCH1. */ - ICU_CHANNEL_2 = 1, /**< Use TIMxCH2. */ -} icuchannel_t; - -/** - * @brief ICU counter type. - */ -typedef uint32_t icucnt_t; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief Driver mode. - */ - icumode_t mode; - /** - * @brief Timer clock in Hz. - * @note The low level can use assertions in order to catch invalid - * frequency specifications. - */ - icufreq_t frequency; - /** - * @brief Callback for pulse width measurement. - */ - icucallback_t width_cb; - /** - * @brief Callback for cycle period measurement. - */ - icucallback_t period_cb; - /** - * @brief Callback for timer overflow. - */ - icucallback_t overflow_cb; - /* End of the mandatory fields.*/ - /** - * @brief Timer input channel to be used. - * @note Only inputs TIMx 1 and 2 are supported. - */ - icuchannel_t channel; - /** - * @brief TIM DIER register initialization data. - * @note The value of this field should normally be equal to zero. - * @note Only the DMA-related bits can be specified in this field. - */ - uint32_t dier; -} ICUConfig; - -/** - * @brief Structure representing an ICU driver. - */ -struct ICUDriver { - /** - * @brief Driver state. - */ - icustate_t state; - /** - * @brief Current configuration data. - */ - const ICUConfig *config; -#if defined(ICU_DRIVER_EXT_FIELDS) - ICU_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Timer base clock. - */ - uint32_t clock; - /** - * @brief Pointer to the TIMx registers block. - */ - stm32_tim_t *tim; - /** - * @brief CCR register used for width capture. - */ - volatile uint32_t *wccrp; - /** - * @brief CCR register used for period capture. - */ - volatile uint32_t *pccrp; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Returns the width of the latest pulse. - * @details The pulse width is defined as number of ticks between the start - * edge and the stop edge. - * - * @param[in] icup pointer to the @p ICUDriver object - * @return The number of ticks. - * - * @notapi - */ -#define icu_lld_get_width(icup) (*((icup)->wccrp) + 1) - -/** - * @brief Returns the width of the latest cycle. - * @details The cycle width is defined as number of ticks between a start - * edge and the next start edge. - * - * @param[in] icup pointer to the @p ICUDriver object - * @return The number of ticks. - * - * @notapi - */ -#define icu_lld_get_period(icup) (*((icup)->pccrp) + 1) - -/** - * @brief Check on notifications status. - * - * @param[in] icup pointer to the @p ICUDriver object - * @return The notifications status. - * @retval false if notifications are not enabled. - * @retval true if notifications are enabled. - * - * @notapi - */ -#define icu_lld_are_notifications_enabled(icup) \ - (bool)(((icup)->tim->DIER & STM32_TIM_DIER_IRQ_MASK) != 0) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_ICU_USE_TIM1 && !defined(__DOXYGEN__) -extern ICUDriver ICUD1; -#endif - -#if STM32_ICU_USE_TIM2 && !defined(__DOXYGEN__) -extern ICUDriver ICUD2; -#endif - -#if STM32_ICU_USE_TIM3 && !defined(__DOXYGEN__) -extern ICUDriver ICUD3; -#endif - -#if STM32_ICU_USE_TIM4 && !defined(__DOXYGEN__) -extern ICUDriver ICUD4; -#endif - -#if STM32_ICU_USE_TIM5 && !defined(__DOXYGEN__) -extern ICUDriver ICUD5; -#endif - -#if STM32_ICU_USE_TIM8 && !defined(__DOXYGEN__) -extern ICUDriver ICUD8; -#endif - -#if STM32_ICU_USE_TIM9 && !defined(__DOXYGEN__) -extern ICUDriver ICUD9; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void icu_lld_init(void); - void icu_lld_start(ICUDriver *icup); - void icu_lld_stop(ICUDriver *icup); - void icu_lld_start_capture(ICUDriver *icup); - bool icu_lld_wait_capture(ICUDriver *icup); - void icu_lld_stop_capture(ICUDriver *icup); - void icu_lld_enable_notifications(ICUDriver *icup); - void icu_lld_disable_notifications(ICUDriver *icup); - void icu_lld_serve_interrupt(ICUDriver *icup); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_ICU */ - -#endif /* _ICU_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c deleted file mode 100644 index 68918178f0..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c +++ /dev/null @@ -1,858 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/pwm_lld.c - * @brief STM32 PWM subsystem low level driver header. - * - * @addtogroup PWM - * @{ - */ - -#include "hal.h" - -#if HAL_USE_PWM || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief PWMD1 driver identifier. - * @note The driver PWMD1 allocates the complex timer TIM1 when enabled. - */ -#if STM32_PWM_USE_TIM1 || defined(__DOXYGEN__) -PWMDriver PWMD1; -#endif - -/** - * @brief PWMD2 driver identifier. - * @note The driver PWMD2 allocates the timer TIM2 when enabled. - */ -#if STM32_PWM_USE_TIM2 || defined(__DOXYGEN__) -PWMDriver PWMD2; -#endif - -/** - * @brief PWMD3 driver identifier. - * @note The driver PWMD3 allocates the timer TIM3 when enabled. - */ -#if STM32_PWM_USE_TIM3 || defined(__DOXYGEN__) -PWMDriver PWMD3; -#endif - -/** - * @brief PWMD4 driver identifier. - * @note The driver PWMD4 allocates the timer TIM4 when enabled. - */ -#if STM32_PWM_USE_TIM4 || defined(__DOXYGEN__) -PWMDriver PWMD4; -#endif - -/** - * @brief PWMD5 driver identifier. - * @note The driver PWMD5 allocates the timer TIM5 when enabled. - */ -#if STM32_PWM_USE_TIM5 || defined(__DOXYGEN__) -PWMDriver PWMD5; -#endif - -/** - * @brief PWMD8 driver identifier. - * @note The driver PWMD8 allocates the timer TIM8 when enabled. - */ -#if STM32_PWM_USE_TIM8 || defined(__DOXYGEN__) -PWMDriver PWMD8; -#endif - -/** - * @brief PWMD9 driver identifier. - * @note The driver PWMD9 allocates the timer TIM9 when enabled. - */ -#if STM32_PWM_USE_TIM9 || defined(__DOXYGEN__) -PWMDriver PWMD9; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if STM32_PWM_USE_TIM1 || defined(__DOXYGEN__) -#if !defined(STM32_TIM1_SUPPRESS_ISR) -#if !defined(STM32_TIM1_UP_HANDLER) -#error "STM32_TIM1_UP_HANDLER not defined" -#endif -/** - * @brief TIM1 update interrupt handler. - * @note It is assumed that this interrupt is only activated if the callback - * pointer is not equal to @p NULL in order to not perform an extra - * check in a potentially critical interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - pwm_lld_serve_interrupt(&PWMD1); - - OSAL_IRQ_EPILOGUE(); -} - -#if !defined(STM32_TIM1_CC_HANDLER) -#error "STM32_TIM1_CC_HANDLER not defined" -#endif -/** - * @brief TIM1 compare interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM1_CC_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - pwm_lld_serve_interrupt(&PWMD1); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* !defined(STM32_TIM1_SUPPRESS_ISR) */ -#endif /* STM32_PWM_USE_TIM1 */ - -#if STM32_PWM_USE_TIM2 || defined(__DOXYGEN__) -#if !defined(STM32_TIM2_SUPPRESS_ISR) -#if !defined(STM32_TIM2_HANDLER) -#error "STM32_TIM2_HANDLER not defined" -#endif -/** - * @brief TIM2 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM2_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - pwm_lld_serve_interrupt(&PWMD2); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* !defined(STM32_TIM2_SUPPRESS_ISR) */ -#endif /* STM32_PWM_USE_TIM2 */ - -#if STM32_PWM_USE_TIM3 || defined(__DOXYGEN__) -#if !defined(STM32_TIM3_SUPPRESS_ISR) -#if !defined(STM32_TIM3_HANDLER) -#error "STM32_TIM3_HANDLER not defined" -#endif -/** - * @brief TIM3 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM3_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - pwm_lld_serve_interrupt(&PWMD3); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* !defined(STM32_TIM3_SUPPRESS_ISR) */ -#endif /* STM32_PWM_USE_TIM3 */ - -#if STM32_PWM_USE_TIM4 || defined(__DOXYGEN__) -#if !defined(STM32_TIM4_SUPPRESS_ISR) -#if !defined(STM32_TIM4_HANDLER) -#error "STM32_TIM4_HANDLER not defined" -#endif -/** - * @brief TIM4 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM4_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - pwm_lld_serve_interrupt(&PWMD4); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* !defined(STM32_TIM4_SUPPRESS_ISR) */ -#endif /* STM32_PWM_USE_TIM4 */ - -#if STM32_PWM_USE_TIM5 || defined(__DOXYGEN__) -#if !defined(STM32_TIM5_SUPPRESS_ISR) -#if !defined(STM32_TIM5_HANDLER) -#error "STM32_TIM5_HANDLER not defined" -#endif -/** - * @brief TIM5 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM5_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - pwm_lld_serve_interrupt(&PWMD5); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* !defined(STM32_TIM5_SUPPRESS_ISR) */ -#endif /* STM32_PWM_USE_TIM5 */ - -#if STM32_PWM_USE_TIM8 || defined(__DOXYGEN__) -#if !defined(STM32_TIM8_SUPPRESS_ISR) -#if !defined(STM32_TIM8_UP_HANDLER) -#error "STM32_TIM8_UP_HANDLER not defined" -#endif -/** - * @brief TIM8 update interrupt handler. - * @note It is assumed that this interrupt is only activated if the callback - * pointer is not equal to @p NULL in order to not perform an extra - * check in a potentially critical interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - pwm_lld_serve_interrupt(&PWMD8); - - OSAL_IRQ_EPILOGUE(); -} - -#if !defined(STM32_TIM8_CC_HANDLER) -#error "STM32_TIM8_CC_HANDLER not defined" -#endif -/** - * @brief TIM8 compare interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM8_CC_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - pwm_lld_serve_interrupt(&PWMD8); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* !defined(STM32_TIM8_SUPPRESS_ISR) */ -#endif /* STM32_PWM_USE_TIM8 */ - -#if STM32_PWM_USE_TIM9 || defined(__DOXYGEN__) -#if !defined(STM32_TIM9_SUPPRESS_ISR) -#if !defined(STM32_TIM9_HANDLER) -#error "STM32_TIM9_HANDLER not defined" -#endif -/** - * @brief TIM9 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM9_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - pwm_lld_serve_interrupt(&PWMD9); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* !defined(STM32_TIM9_SUPPRESS_ISR) */ -#endif /* STM32_PWM_USE_TIM9 */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level PWM driver initialization. - * - * @notapi - */ -void pwm_lld_init(void) { - -#if STM32_PWM_USE_TIM1 - /* Driver initialization.*/ - pwmObjectInit(&PWMD1); - PWMD1.channels = STM32_TIM1_CHANNELS; - PWMD1.tim = STM32_TIM1; -#endif - -#if STM32_PWM_USE_TIM2 - /* Driver initialization.*/ - pwmObjectInit(&PWMD2); - PWMD2.channels = STM32_TIM2_CHANNELS; - PWMD2.tim = STM32_TIM2; -#endif - -#if STM32_PWM_USE_TIM3 - /* Driver initialization.*/ - pwmObjectInit(&PWMD3); - PWMD3.channels = STM32_TIM3_CHANNELS; - PWMD3.tim = STM32_TIM3; -#endif - -#if STM32_PWM_USE_TIM4 - /* Driver initialization.*/ - pwmObjectInit(&PWMD4); - PWMD4.channels = STM32_TIM4_CHANNELS; - PWMD4.tim = STM32_TIM4; -#endif - -#if STM32_PWM_USE_TIM5 - /* Driver initialization.*/ - pwmObjectInit(&PWMD5); - PWMD5.channels = STM32_TIM5_CHANNELS; - PWMD5.tim = STM32_TIM5; -#endif - -#if STM32_PWM_USE_TIM8 - /* Driver initialization.*/ - pwmObjectInit(&PWMD8); - PWMD8.channels = STM32_TIM8_CHANNELS; - PWMD8.tim = STM32_TIM8; -#endif - -#if STM32_PWM_USE_TIM9 - /* Driver initialization.*/ - pwmObjectInit(&PWMD9); - PWMD9.channels = STM32_TIM9_CHANNELS; - PWMD9.tim = STM32_TIM9; -#endif -} - -/** - * @brief Configures and activates the PWM peripheral. - * @note Starting a driver that is already in the @p PWM_READY state - * disables all the active channels. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * - * @notapi - */ -void pwm_lld_start(PWMDriver *pwmp) { - uint32_t psc; - uint32_t ccer; - - if (pwmp->state == PWM_STOP) { - /* Clock activation and timer reset.*/ -#if STM32_PWM_USE_TIM1 - if (&PWMD1 == pwmp) { - rccEnableTIM1(FALSE); - rccResetTIM1(); -#if !defined(STM32_TIM1_SUPPRESS_ISR) - nvicEnableVector(STM32_TIM1_UP_NUMBER, STM32_PWM_TIM1_IRQ_PRIORITY); - nvicEnableVector(STM32_TIM1_CC_NUMBER, STM32_PWM_TIM1_IRQ_PRIORITY); -#endif -#if defined(STM32_TIM1CLK) - pwmp->clock = STM32_TIM1CLK; -#else - pwmp->clock = STM32_TIMCLK2; -#endif - } -#endif - -#if STM32_PWM_USE_TIM2 - if (&PWMD2 == pwmp) { - rccEnableTIM2(FALSE); - rccResetTIM2(); -#if !defined(STM32_TIM2_SUPPRESS_ISR) - nvicEnableVector(STM32_TIM2_NUMBER, STM32_PWM_TIM2_IRQ_PRIORITY); -#endif -#if defined(STM32_TIM2CLK) - pwmp->clock = STM32_TIM2CLK; -#else - pwmp->clock = STM32_TIMCLK1; -#endif - } -#endif - -#if STM32_PWM_USE_TIM3 - if (&PWMD3 == pwmp) { - rccEnableTIM3(FALSE); - rccResetTIM3(); -#if !defined(STM32_TIM3_SUPPRESS_ISR) - nvicEnableVector(STM32_TIM3_NUMBER, STM32_PWM_TIM3_IRQ_PRIORITY); -#endif -#if defined(STM32_TIM3CLK) - pwmp->clock = STM32_TIM3CLK; -#else - pwmp->clock = STM32_TIMCLK1; -#endif - } -#endif - -#if STM32_PWM_USE_TIM4 - if (&PWMD4 == pwmp) { - rccEnableTIM4(FALSE); - rccResetTIM4(); -#if !defined(STM32_TIM4_SUPPRESS_ISR) - nvicEnableVector(STM32_TIM4_NUMBER, STM32_PWM_TIM4_IRQ_PRIORITY); -#endif -#if defined(STM32_TIM4CLK) - pwmp->clock = STM32_TIM4CLK; -#else - pwmp->clock = STM32_TIMCLK1; -#endif - } -#endif - -#if STM32_PWM_USE_TIM5 - if (&PWMD5 == pwmp) { - rccEnableTIM5(FALSE); - rccResetTIM5(); -#if !defined(STM32_TIM5_SUPPRESS_ISR) - nvicEnableVector(STM32_TIM5_NUMBER, STM32_PWM_TIM5_IRQ_PRIORITY); -#endif -#if defined(STM32_TIM5CLK) - pwmp->clock = STM32_TIM5CLK; -#else - pwmp->clock = STM32_TIMCLK1; -#endif - } -#endif - -#if STM32_PWM_USE_TIM8 - if (&PWMD8 == pwmp) { - rccEnableTIM8(FALSE); - rccResetTIM8(); -#if !defined(STM32_TIM8_SUPPRESS_ISR) - nvicEnableVector(STM32_TIM8_UP_NUMBER, STM32_PWM_TIM8_IRQ_PRIORITY); - nvicEnableVector(STM32_TIM8_CC_NUMBER, STM32_PWM_TIM8_IRQ_PRIORITY); -#endif -#if defined(STM32_TIM8CLK) - pwmp->clock = STM32_TIM8CLK; -#else - pwmp->clock = STM32_TIMCLK2; -#endif - } -#endif - -#if STM32_PWM_USE_TIM9 - if (&PWMD9 == pwmp) { - rccEnableTIM9(FALSE); - rccResetTIM9(); -#if !defined(STM32_TIM9_SUPPRESS_ISR) - nvicEnableVector(STM32_TIM9_NUMBER, STM32_PWM_TIM9_IRQ_PRIORITY); -#endif -#if defined(STM32_TIM9CLK) - pwmp->clock = STM32_TIM9CLK; -#else - pwmp->clock = STM32_TIMCLK2; -#endif - } -#endif - - /* All channels configured in PWM1 mode with preload enabled and will - stay that way until the driver is stopped.*/ - pwmp->tim->CCMR1 = STM32_TIM_CCMR1_OC1M(6) | STM32_TIM_CCMR1_OC1PE | - STM32_TIM_CCMR1_OC2M(6) | STM32_TIM_CCMR1_OC2PE; - pwmp->tim->CCMR2 = STM32_TIM_CCMR2_OC3M(6) | STM32_TIM_CCMR2_OC3PE | - STM32_TIM_CCMR2_OC4M(6) | STM32_TIM_CCMR2_OC4PE; -#if STM32_TIM_MAX_CHANNELS > 4 - pwmp->tim->CCMR3 = STM32_TIM_CCMR3_OC5M(6) | STM32_TIM_CCMR3_OC5PE | - STM32_TIM_CCMR3_OC6M(6) | STM32_TIM_CCMR3_OC6PE; -#endif - } - else { - /* Driver re-configuration scenario, it must be stopped first.*/ - pwmp->tim->CR1 = 0; /* Timer disabled. */ - pwmp->tim->CCR[0] = 0; /* Comparator 1 disabled. */ - pwmp->tim->CCR[1] = 0; /* Comparator 2 disabled. */ - pwmp->tim->CCR[2] = 0; /* Comparator 3 disabled. */ - pwmp->tim->CCR[3] = 0; /* Comparator 4 disabled. */ -#if STM32_TIM_MAX_CHANNELS > 4 - if (pwmp->channels > 4) { - pwmp->tim->CCXR[0] = 0; /* Comparator 5 disabled. */ - pwmp->tim->CCXR[1] = 0; /* Comparator 6 disabled. */ - } -#endif - pwmp->tim->CNT = 0; /* Counter reset to zero. */ - } - - /* Timer configuration.*/ - psc = (pwmp->clock / pwmp->config->frequency) - 1; - osalDbgAssert((psc <= 0xFFFF) && - ((psc + 1) * pwmp->config->frequency) == pwmp->clock, - "invalid frequency"); - pwmp->tim->PSC = psc; - pwmp->tim->ARR = pwmp->period - 1; - pwmp->tim->CR2 = pwmp->config->cr2; - - /* Output enables and polarities setup.*/ - ccer = 0; - switch (pwmp->config->channels[0].mode & PWM_OUTPUT_MASK) { - case PWM_OUTPUT_ACTIVE_LOW: - ccer |= STM32_TIM_CCER_CC1P; - case PWM_OUTPUT_ACTIVE_HIGH: - ccer |= STM32_TIM_CCER_CC1E; - default: - ; - } - switch (pwmp->config->channels[1].mode & PWM_OUTPUT_MASK) { - case PWM_OUTPUT_ACTIVE_LOW: - ccer |= STM32_TIM_CCER_CC2P; - case PWM_OUTPUT_ACTIVE_HIGH: - ccer |= STM32_TIM_CCER_CC2E; - default: - ; - } - switch (pwmp->config->channels[2].mode & PWM_OUTPUT_MASK) { - case PWM_OUTPUT_ACTIVE_LOW: - ccer |= STM32_TIM_CCER_CC3P; - case PWM_OUTPUT_ACTIVE_HIGH: - ccer |= STM32_TIM_CCER_CC3E; - default: - ; - } - switch (pwmp->config->channels[3].mode & PWM_OUTPUT_MASK) { - case PWM_OUTPUT_ACTIVE_LOW: - ccer |= STM32_TIM_CCER_CC4P; - case PWM_OUTPUT_ACTIVE_HIGH: - ccer |= STM32_TIM_CCER_CC4E; - default: - ; - } -#if STM32_PWM_USE_ADVANCED -#if STM32_PWM_USE_TIM1 && !STM32_PWM_USE_TIM8 - if (&PWMD1 == pwmp) { -#endif -#if !STM32_PWM_USE_TIM1 && STM32_PWM_USE_TIM8 - if (&PWMD8 == pwmp) { -#endif -#if STM32_PWM_USE_TIM1 && STM32_PWM_USE_TIM8 - if ((&PWMD1 == pwmp) || (&PWMD8 == pwmp)) { -#endif - switch (pwmp->config->channels[0].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) { - case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW: - ccer |= STM32_TIM_CCER_CC1NP; - case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH: - ccer |= STM32_TIM_CCER_CC1NE; - default: - ; - } - switch (pwmp->config->channels[1].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) { - case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW: - ccer |= STM32_TIM_CCER_CC2NP; - case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH: - ccer |= STM32_TIM_CCER_CC2NE; - default: - ; - } - switch (pwmp->config->channels[2].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) { - case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW: - ccer |= STM32_TIM_CCER_CC3NP; - case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH: - ccer |= STM32_TIM_CCER_CC3NE; - default: - ; - } - } -#endif /* STM32_PWM_USE_ADVANCED*/ - - pwmp->tim->CCER = ccer; - pwmp->tim->EGR = STM32_TIM_EGR_UG; /* Update event. */ - pwmp->tim->SR = 0; /* Clear pending IRQs. */ - pwmp->tim->DIER = pwmp->config->dier & /* DMA-related DIER settings. */ - ~STM32_TIM_DIER_IRQ_MASK; -#if STM32_PWM_USE_TIM1 || STM32_PWM_USE_TIM8 -#if STM32_PWM_USE_ADVANCED - pwmp->tim->BDTR = pwmp->config->bdtr | STM32_TIM_BDTR_MOE; -#else - pwmp->tim->BDTR = STM32_TIM_BDTR_MOE; -#endif -#endif - /* Timer configured and started.*/ - pwmp->tim->CR1 = STM32_TIM_CR1_ARPE | STM32_TIM_CR1_URS | - STM32_TIM_CR1_CEN; -} - -/** - * @brief Deactivates the PWM peripheral. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * - * @notapi - */ -void pwm_lld_stop(PWMDriver *pwmp) { - - /* If in ready state then disables the PWM clock.*/ - if (pwmp->state == PWM_READY) { - pwmp->tim->CR1 = 0; /* Timer disabled. */ - pwmp->tim->DIER = 0; /* All IRQs disabled. */ - pwmp->tim->SR = 0; /* Clear eventual pending IRQs. */ -#if STM32_PWM_USE_TIM1 || STM32_PWM_USE_TIM8 - pwmp->tim->BDTR = 0; -#endif - -#if STM32_PWM_USE_TIM1 - if (&PWMD1 == pwmp) { -#if !defined(STM32_TIM1_SUPPRESS_ISR) - nvicDisableVector(STM32_TIM1_UP_NUMBER); - nvicDisableVector(STM32_TIM1_CC_NUMBER); -#endif - rccDisableTIM1(FALSE); - } -#endif - -#if STM32_PWM_USE_TIM2 - if (&PWMD2 == pwmp) { -#if !defined(STM32_TIM2_SUPPRESS_ISR) - nvicDisableVector(STM32_TIM2_NUMBER); -#endif - rccDisableTIM2(FALSE); - } -#endif - -#if STM32_PWM_USE_TIM3 - if (&PWMD3 == pwmp) { -#if !defined(STM32_TIM3_SUPPRESS_ISR) - nvicDisableVector(STM32_TIM3_NUMBER); -#endif - rccDisableTIM3(FALSE); - } -#endif - -#if STM32_PWM_USE_TIM4 - if (&PWMD4 == pwmp) { -#if !defined(STM32_TIM4_SUPPRESS_ISR) - nvicDisableVector(STM32_TIM4_NUMBER); -#endif - rccDisableTIM4(FALSE); - } -#endif - -#if STM32_PWM_USE_TIM5 - if (&PWMD5 == pwmp) { -#if !defined(STM32_TIM5_SUPPRESS_ISR) - nvicDisableVector(STM32_TIM5_NUMBER); -#endif - rccDisableTIM5(FALSE); - } -#endif - -#if STM32_PWM_USE_TIM8 - if (&PWMD8 == pwmp) { -#if !defined(STM32_TIM8_SUPPRESS_ISR) - nvicDisableVector(STM32_TIM8_UP_NUMBER); - nvicDisableVector(STM32_TIM8_CC_NUMBER); -#endif - rccDisableTIM8(FALSE); - } -#endif - -#if STM32_PWM_USE_TIM9 - if (&PWMD9 == pwmp) { -#if !defined(STM32_TIM9_SUPPRESS_ISR) - nvicDisableVector(STM32_TIM9_NUMBER); -#endif - rccDisableTIM9(FALSE); - } -#endif - } -} - -/** - * @brief Enables a PWM channel. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @post The channel is active using the specified configuration. - * @note The function has effect at the next cycle start. - * @note Channel notification is not enabled. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier (0...channels-1) - * @param[in] width PWM pulse width as clock pulses number - * - * @notapi - */ -void pwm_lld_enable_channel(PWMDriver *pwmp, - pwmchannel_t channel, - pwmcnt_t width) { - - /* Changing channel duty cycle on the fly.*/ -#if STM32_TIM_MAX_CHANNELS <= 4 - pwmp->tim->CCR[channel] = width; -#else - if (channel < 4) - pwmp->tim->CCR[channel] = width; - else - pwmp->tim->CCXR[channel - 4] = width; -#endif -} - -/** - * @brief Disables a PWM channel and its notification. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @post The channel is disabled and its output line returned to the - * idle state. - * @note The function has effect at the next cycle start. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier (0...channels-1) - * - * @notapi - */ -void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) { - -#if STM32_TIM_MAX_CHANNELS <= 4 - pwmp->tim->CCR[channel] = 0; - pwmp->tim->DIER &= ~(2 << channel); -#else - if (channel < 4) { - pwmp->tim->CCR[channel] = 0; - pwmp->tim->DIER &= ~(2 << channel); - } - else - pwmp->tim->CCXR[channel - 4] = 0; -#endif -} - -/** - * @brief Enables the periodic activation edge notification. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @note If the notification is already enabled then the call has no effect. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * - * @notapi - */ -void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) { - uint32_t dier = pwmp->tim->DIER; - - /* If the IRQ is not already enabled care must be taken to clear it, - it is probably already pending because the timer is running.*/ - if ((dier & STM32_TIM_DIER_UIE) == 0) { - pwmp->tim->DIER = dier | STM32_TIM_DIER_UIE; - pwmp->tim->SR &= STM32_TIM_SR_UIF; - } -} - -/** - * @brief Disables the periodic activation edge notification. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @note If the notification is already disabled then the call has no effect. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * - * @notapi - */ -void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) { - - pwmp->tim->DIER &= ~STM32_TIM_DIER_UIE; -} - -/** - * @brief Enables a channel de-activation edge notification. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @pre The channel must have been activated using @p pwmEnableChannel(). - * @note If the notification is already enabled then the call has no effect. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier (0...channels-1) - * - * @notapi - */ -void pwm_lld_enable_channel_notification(PWMDriver *pwmp, - pwmchannel_t channel) { - uint32_t dier = pwmp->tim->DIER; - -#if STM32_TIM_MAX_CHANNELS > 4 - /* Channels 4 and 5 do not support callbacks.*/ - osalDbgAssert(channel < 4, "callback not supported"); -#endif - - /* If the IRQ is not already enabled care must be taken to clear it, - it is probably already pending because the timer is running.*/ - if ((dier & (2 << channel)) == 0) { - pwmp->tim->DIER = dier | (2 << channel); - pwmp->tim->SR = ~(2 << channel); - } -} - -/** - * @brief Disables a channel de-activation edge notification. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @pre The channel must have been activated using @p pwmEnableChannel(). - * @note If the notification is already disabled then the call has no effect. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier (0...channels-1) - * - * @notapi - */ -void pwm_lld_disable_channel_notification(PWMDriver *pwmp, - pwmchannel_t channel) { - - pwmp->tim->DIER &= ~(2 << channel); -} - -/** - * @brief Common TIM2...TIM5,TIM9 IRQ handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * - * @notapi - */ -void pwm_lld_serve_interrupt(PWMDriver *pwmp) { - uint32_t sr; - - sr = pwmp->tim->SR; - sr &= pwmp->tim->DIER & STM32_TIM_DIER_IRQ_MASK; - pwmp->tim->SR = ~sr; - if (((sr & STM32_TIM_SR_CC1IF) != 0) && - (pwmp->config->channels[0].callback != NULL)) - pwmp->config->channels[0].callback(pwmp); - if (((sr & STM32_TIM_SR_CC2IF) != 0) && - (pwmp->config->channels[1].callback != NULL)) - pwmp->config->channels[1].callback(pwmp); - if (((sr & STM32_TIM_SR_CC3IF) != 0) && - (pwmp->config->channels[2].callback != NULL)) - pwmp->config->channels[2].callback(pwmp); - if (((sr & STM32_TIM_SR_CC4IF) != 0) && - (pwmp->config->channels[3].callback != NULL)) - pwmp->config->channels[3].callback(pwmp); - if (((sr & STM32_TIM_SR_UIF) != 0) && (pwmp->config->callback != NULL)) - pwmp->config->callback(pwmp); -} - -#endif /* HAL_USE_PWM */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.h b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.h deleted file mode 100644 index 6f18974b3b..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.h +++ /dev/null @@ -1,550 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/pwm_lld.h - * @brief STM32 PWM subsystem low level driver header. - * - * @addtogroup PWM - * @{ - */ - -#ifndef _PWM_LLD_H_ -#define _PWM_LLD_H_ - -#if HAL_USE_PWM || defined(__DOXYGEN__) - -#include "stm32_tim.h" - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Number of PWM channels per PWM driver. - */ -#define PWM_CHANNELS STM32_TIM_MAX_CHANNELS - -/** - * @name STM32-specific PWM complementary output mode macros - * @{ - */ -/** - * @brief Complementary output modes mask. - * @note This is an STM32-specific setting. - */ -#define PWM_COMPLEMENTARY_OUTPUT_MASK 0xF0 - -/** - * @brief Complementary output not driven. - * @note This is an STM32-specific setting. - */ -#define PWM_COMPLEMENTARY_OUTPUT_DISABLED 0x00 - -/** - * @brief Complementary output, active is logic level one. - * @note This is an STM32-specific setting. - * @note This setting is only available if the configuration option - * @p STM32_PWM_USE_ADVANCED is set to TRUE and only for advanced - * timers TIM1 and TIM8. - */ -#define PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH 0x10 - -/** - * @brief Complementary output, active is logic level zero. - * @note This is an STM32-specific setting. - * @note This setting is only available if the configuration option - * @p STM32_PWM_USE_ADVANCED is set to TRUE and only for advanced - * timers TIM1 and TIM8. - */ -#define PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW 0x20 -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief If advanced timer features switch. - * @details If set to @p TRUE the advanced features for TIM1 and TIM8 are - * enabled. - * @note The default is @p TRUE. - */ -#if !defined(STM32_PWM_USE_ADVANCED) || defined(__DOXYGEN__) -#define STM32_PWM_USE_ADVANCED FALSE -#endif - -/** - * @brief PWMD1 driver enable switch. - * @details If set to @p TRUE the support for PWMD1 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_PWM_USE_TIM1) || defined(__DOXYGEN__) -#define STM32_PWM_USE_TIM1 FALSE -#endif - -/** - * @brief PWMD2 driver enable switch. - * @details If set to @p TRUE the support for PWMD2 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_PWM_USE_TIM2) || defined(__DOXYGEN__) -#define STM32_PWM_USE_TIM2 FALSE -#endif - -/** - * @brief PWMD3 driver enable switch. - * @details If set to @p TRUE the support for PWMD3 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_PWM_USE_TIM3) || defined(__DOXYGEN__) -#define STM32_PWM_USE_TIM3 FALSE -#endif - -/** - * @brief PWMD4 driver enable switch. - * @details If set to @p TRUE the support for PWMD4 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_PWM_USE_TIM4) || defined(__DOXYGEN__) -#define STM32_PWM_USE_TIM4 FALSE -#endif - -/** - * @brief PWMD5 driver enable switch. - * @details If set to @p TRUE the support for PWMD5 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_PWM_USE_TIM5) || defined(__DOXYGEN__) -#define STM32_PWM_USE_TIM5 FALSE -#endif - -/** - * @brief PWMD8 driver enable switch. - * @details If set to @p TRUE the support for PWMD8 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_PWM_USE_TIM8) || defined(__DOXYGEN__) -#define STM32_PWM_USE_TIM8 FALSE -#endif - -/** - * @brief PWMD9 driver enable switch. - * @details If set to @p TRUE the support for PWMD9 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_PWM_USE_TIM9) || defined(__DOXYGEN__) -#define STM32_PWM_USE_TIM9 FALSE -#endif - -/** - * @brief PWMD1 interrupt priority level setting. - */ -#if !defined(STM32_PWM_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_PWM_TIM1_IRQ_PRIORITY 7 -#endif - -/** - * @brief PWMD2 interrupt priority level setting. - */ -#if !defined(STM32_PWM_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_PWM_TIM2_IRQ_PRIORITY 7 -#endif - -/** - * @brief PWMD3 interrupt priority level setting. - */ -#if !defined(STM32_PWM_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_PWM_TIM3_IRQ_PRIORITY 7 -#endif - -/** - * @brief PWMD4 interrupt priority level setting. - */ -#if !defined(STM32_PWM_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_PWM_TIM4_IRQ_PRIORITY 7 -#endif - -/** - * @brief PWMD5 interrupt priority level setting. - */ -#if !defined(STM32_PWM_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_PWM_TIM5_IRQ_PRIORITY 7 -#endif - -/** - * @brief PWMD8 interrupt priority level setting. - */ -#if !defined(STM32_PWM_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_PWM_TIM8_IRQ_PRIORITY 7 -#endif -/** @} */ - -/** - * @brief PWMD9 interrupt priority level setting. - */ -#if !defined(STM32_PWM_TIM9_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_PWM_TIM9_IRQ_PRIORITY 7 -#endif -/** @} */ - -/*===========================================================================*/ -/* Configuration checks. */ -/*===========================================================================*/ - -#if STM32_PWM_USE_TIM1 && !STM32_HAS_TIM1 -#error "TIM1 not present in the selected device" -#endif - -#if STM32_PWM_USE_TIM2 && !STM32_HAS_TIM2 -#error "TIM2 not present in the selected device" -#endif - -#if STM32_PWM_USE_TIM3 && !STM32_HAS_TIM3 -#error "TIM3 not present in the selected device" -#endif - -#if STM32_PWM_USE_TIM4 && !STM32_HAS_TIM4 -#error "TIM4 not present in the selected device" -#endif - -#if STM32_PWM_USE_TIM5 && !STM32_HAS_TIM5 -#error "TIM5 not present in the selected device" -#endif - -#if STM32_PWM_USE_TIM8 && !STM32_HAS_TIM8 -#error "TIM8 not present in the selected device" -#endif - -#if STM32_PWM_USE_TIM9 && !STM32_HAS_TIM9 -#error "TIM9 not present in the selected device" -#endif - -#if !STM32_PWM_USE_TIM1 && !STM32_PWM_USE_TIM2 && \ - !STM32_PWM_USE_TIM3 && !STM32_PWM_USE_TIM4 && \ - !STM32_PWM_USE_TIM5 && !STM32_PWM_USE_TIM8 && \ - !STM32_PWM_USE_TIM9 -#error "PWM driver activated but no TIM peripheral assigned" -#endif - -#if STM32_PWM_USE_ADVANCED && !STM32_PWM_USE_TIM1 && !STM32_PWM_USE_TIM8 -#error "advanced mode selected but no advanced timer assigned" -#endif - -/* Checks on allocation of TIMx units.*/ -#if STM32_PWM_USE_TIM1 -#if defined(STM32_TIM1_IS_USED) -#error "PWMD1 requires TIM1 but the timer is already used" -#else -#define STM32_TIM1_IS_USED -#endif -#endif - -#if STM32_PWM_USE_TIM2 -#if defined(STM32_TIM2_IS_USED) -#error "PWMD2 requires TIM2 but the timer is already used" -#else -#define STM32_TIM2_IS_USED -#endif -#endif - -#if STM32_PWM_USE_TIM3 -#if defined(STM32_TIM3_IS_USED) -#error "PWMD3 requires TIM3 but the timer is already used" -#else -#define STM32_TIM3_IS_USED -#endif -#endif - -#if STM32_PWM_USE_TIM4 -#if defined(STM32_TIM4_IS_USED) -#error "PWMD4 requires TIM4 but the timer is already used" -#else -#define STM32_TIM4_IS_USED -#endif -#endif - -#if STM32_PWM_USE_TIM5 -#if defined(STM32_TIM5_IS_USED) -#error "PWMD5 requires TIM5 but the timer is already used" -#else -#define STM32_TIM5_IS_USED -#endif -#endif - -#if STM32_PWM_USE_TIM8 -#if defined(STM32_TIM8_IS_USED) -#error "PWMD8 requires TIM8 but the timer is already used" -#else -#define STM32_TIM8_IS_USED -#endif -#endif - -#if STM32_PWM_USE_TIM9 -#if defined(STM32_TIM9_IS_USED) -#error "PWMD9 requires TIM9 but the timer is already used" -#else -#define STM32_TIM9_IS_USED -#endif -#endif - -/* IRQ priority checks.*/ -#if STM32_PWM_USE_TIM1 && !defined(STM32_TIM1_SUPPRESS_ISR) && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_PWM_TIM1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM1" -#endif - -#if STM32_PWM_USE_TIM2 && !defined(STM32_TIM2_SUPPRESS_ISR) && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_PWM_TIM2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM2" -#endif - -#if STM32_PWM_USE_TIM3 && !defined(STM32_TIM3_SUPPRESS_ISR) && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_PWM_TIM3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM3" -#endif - -#if STM32_PWM_USE_TIM4 && !defined(STM32_TIM4_SUPPRESS_ISR) && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_PWM_TIM4_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM4" -#endif - -#if STM32_PWM_USE_TIM5 && !defined(STM32_TIM5_SUPPRESS_ISR) && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_PWM_TIM5_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM5" -#endif - -#if STM32_PWM_USE_TIM8 && !defined(STM32_TIM8_SUPPRESS_ISR) && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_PWM_TIM8_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM8" -#endif - -#if STM32_PWM_USE_TIM9 && !defined(STM32_TIM9_SUPPRESS_ISR) && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_PWM_TIM9_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM9" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a PWM mode. - */ -typedef uint32_t pwmmode_t; - -/** - * @brief Type of a PWM channel. - */ -typedef uint8_t pwmchannel_t; - -/** - * @brief Type of a channels mask. - */ -typedef uint32_t pwmchnmsk_t; - -/** - * @brief Type of a PWM counter. - */ -typedef uint32_t pwmcnt_t; - -/** - * @brief Type of a PWM driver channel configuration structure. - */ -typedef struct { - /** - * @brief Channel active logic level. - */ - pwmmode_t mode; - /** - * @brief Channel callback pointer. - * @note This callback is invoked on the channel compare event. If set to - * @p NULL then the callback is disabled. - */ - pwmcallback_t callback; - /* End of the mandatory fields.*/ -} PWMChannelConfig; - -/** - * @brief Type of a PWM driver configuration structure. - */ -typedef struct { - /** - * @brief Timer clock in Hz. - * @note The low level can use assertions in order to catch invalid - * frequency specifications. - */ - uint32_t frequency; - /** - * @brief PWM period in ticks. - * @note The low level can use assertions in order to catch invalid - * period specifications. - */ - pwmcnt_t period; - /** - * @brief Periodic callback pointer. - * @note This callback is invoked on PWM counter reset. If set to - * @p NULL then the callback is disabled. - */ - pwmcallback_t callback; - /** - * @brief Channels configurations. - */ - PWMChannelConfig channels[PWM_CHANNELS]; - /* End of the mandatory fields.*/ - /** - * @brief TIM CR2 register initialization data. - * @note The value of this field should normally be equal to zero. - */ - uint32_t cr2; -#if STM32_PWM_USE_ADVANCED || defined(__DOXYGEN__) - /** - * @brief TIM BDTR (break & dead-time) register initialization data. - * @note The value of this field should normally be equal to zero. - */ \ - uint32_t bdtr; -#endif - /** - * @brief TIM DIER register initialization data. - * @note The value of this field should normally be equal to zero. - * @note Only the DMA-related bits can be specified in this field. - */ - uint32_t dier; -} PWMConfig; - -/** - * @brief Structure representing a PWM driver. - */ -struct PWMDriver { - /** - * @brief Driver state. - */ - pwmstate_t state; - /** - * @brief Current driver configuration data. - */ - const PWMConfig *config; - /** - * @brief Current PWM period in ticks. - */ - pwmcnt_t period; - /** - * @brief Mask of the enabled channels. - */ - pwmchnmsk_t enabled; - /** - * @brief Number of channels in this instance. - */ - pwmchannel_t channels; -#if defined(PWM_DRIVER_EXT_FIELDS) - PWM_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Timer base clock. - */ - uint32_t clock; - /** - * @brief Pointer to the TIMx registers block. - */ - stm32_tim_t *tim; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Changes the period the PWM peripheral. - * @details This function changes the period of a PWM unit that has already - * been activated using @p pwmStart(). - * @pre The PWM unit must have been activated using @p pwmStart(). - * @post The PWM unit period is changed to the new value. - * @note The function has effect at the next cycle start. - * @note If a period is specified that is shorter than the pulse width - * programmed in one of the channels then the behavior is not - * guaranteed. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] period new cycle time in ticks - * - * @notapi - */ -#define pwm_lld_change_period(pwmp, period) \ - ((pwmp)->tim->ARR = ((period) - 1)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_PWM_USE_TIM1 && !defined(__DOXYGEN__) -extern PWMDriver PWMD1; -#endif - -#if STM32_PWM_USE_TIM2 && !defined(__DOXYGEN__) -extern PWMDriver PWMD2; -#endif - -#if STM32_PWM_USE_TIM3 && !defined(__DOXYGEN__) -extern PWMDriver PWMD3; -#endif - -#if STM32_PWM_USE_TIM4 && !defined(__DOXYGEN__) -extern PWMDriver PWMD4; -#endif - -#if STM32_PWM_USE_TIM5 && !defined(__DOXYGEN__) -extern PWMDriver PWMD5; -#endif - -#if STM32_PWM_USE_TIM8 && !defined(__DOXYGEN__) -extern PWMDriver PWMD8; -#endif - -#if STM32_PWM_USE_TIM9 && !defined(__DOXYGEN__) -extern PWMDriver PWMD9; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void pwm_lld_init(void); - void pwm_lld_start(PWMDriver *pwmp); - void pwm_lld_stop(PWMDriver *pwmp); - void pwm_lld_enable_channel(PWMDriver *pwmp, - pwmchannel_t channel, - pwmcnt_t width); - void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel); - void pwm_lld_enable_periodic_notification(PWMDriver *pwmp); - void pwm_lld_disable_periodic_notification(PWMDriver *pwmp); - void pwm_lld_enable_channel_notification(PWMDriver *pwmp, - pwmchannel_t channel); - void pwm_lld_disable_channel_notification(PWMDriver *pwmp, - pwmchannel_t channel); - void pwm_lld_serve_interrupt(PWMDriver *pwmp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_PWM */ - -#endif /* _PWM_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/TIMv1/st_lld.c b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/TIMv1/st_lld.c deleted file mode 100644 index 1dccd125b0..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/TIMv1/st_lld.c +++ /dev/null @@ -1,308 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/st_lld.c - * @brief ST Driver subsystem low level driver code. - * - * @addtogroup ST - * @{ - */ - -#include "hal.h" - -#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING - -#if (OSAL_ST_RESOLUTION == 32) -#define ST_ARR_INIT 0xFFFFFFFF -#else -#define ST_ARR_INIT 0x0000FFFF -#endif - -#if STM32_ST_USE_TIMER == 2 -#if (OSAL_ST_RESOLUTION == 32) && !STM32_TIM2_IS_32BITS -#error "TIM2 is not a 32bits timer" -#endif - -#if defined(STM32_TIM2_IS_USED) -#error "ST requires TIM2 but the timer is already used" -#else -#define STM32_TIM2_IS_USED -#endif - -#define ST_HANDLER STM32_TIM2_HANDLER -#define ST_NUMBER STM32_TIM2_NUMBER -#define ST_CLOCK_SRC STM32_TIMCLK1 -#define ST_ENABLE_CLOCK() rccEnableTIM2(FALSE) -#if defined(STM32F1XX) -#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM2_STOP -#elif defined(STM32L4XX) -#define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM2_STOP -#else -#define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_TIM2_STOP -#endif - -#elif STM32_ST_USE_TIMER == 3 -#if (OSAL_ST_RESOLUTION == 32) && !STM32_TIM3_IS_32BITS -#error "TIM3 is not a 32bits timer" -#endif - -#if defined(STM32_TIM3_IS_USED) -#error "ST requires TIM3 but the timer is already used" -#else -#define STM32_TIM3_IS_USED -#endif - -#define ST_HANDLER STM32_TIM3_HANDLER -#define ST_NUMBER STM32_TIM3_NUMBER -#define ST_CLOCK_SRC STM32_TIMCLK1 -#define ST_ENABLE_CLOCK() rccEnableTIM3(FALSE) -#if defined(STM32F1XX) -#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM3_STOP -#elif defined(STM32L4XX) -#define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM3_STOP -#else -#define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_TIM3_STOP -#endif - -#elif STM32_ST_USE_TIMER == 4 -#if (OSAL_ST_RESOLUTION == 32) && !STM32_TIM4_IS_32BITS -#error "TIM4 is not a 32bits timer" -#endif - -#if defined(STM32_TIM4_IS_USED) -#error "ST requires TIM4 but the timer is already used" -#else -#define STM32_TIM4_IS_USED -#endif - -#define ST_HANDLER STM32_TIM4_HANDLER -#define ST_NUMBER STM32_TIM4_NUMBER -#define ST_CLOCK_SRC STM32_TIMCLK1 -#define ST_ENABLE_CLOCK() rccEnableTIM4(FALSE) -#if defined(STM32F1XX) -#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM4_STOP -#elif defined(STM32L4XX) -#define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM4_STOP -#else -#define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_TIM4_STOP -#endif - -#elif STM32_ST_USE_TIMER == 5 -#if (OSAL_ST_RESOLUTION == 32) && !STM32_TIM5_IS_32BITS -#error "TIM5 is not a 32bits timer" -#endif - -#if defined(STM32_TIM5_IS_USED) -#error "ST requires TIM5 but the timer is already used" -#else -#define STM32_TIM5_IS_USED -#endif - -#define ST_HANDLER STM32_TIM5_HANDLER -#define ST_NUMBER STM32_TIM5_NUMBER -#define ST_CLOCK_SRC STM32_TIMCLK1 -#define ST_ENABLE_CLOCK() rccEnableTIM5(FALSE) -#if defined(STM32F1XX) -#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM5_STOP -#elif defined(STM32L4XX) -#define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM5_STOP -#else -#define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_TIM5_STOP -#endif - -#elif STM32_ST_USE_TIMER == 21 -#if (OSAL_ST_RESOLUTION == 32) && !STM32_TIM21_IS_32BITS -#error "TIM21 is not a 32bits timer" -#endif - -#if defined(STM32_TIM21_IS_USED) -#error "ST requires TIM21 but the timer is already used" -#else -#define STM32_TIM21_IS_USED -#endif - -#define ST_HANDLER STM32_TIM21_HANDLER -#define ST_NUMBER STM32_TIM21_NUMBER -#define ST_CLOCK_SRC STM32_TIMCLK2 -#define ST_ENABLE_CLOCK() rccEnableTIM21(FALSE) -#define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB2_FZ_DBG_TIM21_STOP - -#elif STM32_ST_USE_TIMER == 22 -#if (OSAL_ST_RESOLUTION == 32) && !STM32_TIM22_IS_32BITS -#error "TIM21 is not a 32bits timer" -#endif - -#if defined(STM32_TIM22_IS_USED) -#error "ST requires TIM22 but the timer is already used" -#else -#define STM32_TIM22_IS_USED -#endif - -#define ST_HANDLER STM32_TIM22_HANDLER -#define ST_NUMBER STM32_TIM22_NUMBER -#define ST_CLOCK_SRC STM32_TIMCLK2 -#define ST_ENABLE_CLOCK() rccEnableTIM22(FALSE) -#define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB2_FZ_DBG_TIM21_STOP - -#else -#error "STM32_ST_USE_TIMER specifies an unsupported timer" -#endif - -#if ST_CLOCK_SRC % OSAL_ST_FREQUENCY != 0 -#error "the selected ST frequency is not obtainable because integer rounding" -#endif - -#if (ST_CLOCK_SRC / OSAL_ST_FREQUENCY) - 1 > 0xFFFF -#error "the selected ST frequency is not obtainable because TIM timer prescaler limits" -#endif - -#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */ - -#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC - -#if STM32_HCLK % OSAL_ST_FREQUENCY != 0 -#error "the selected ST frequency is not obtainable because integer rounding" -#endif - -#if (STM32_HCLK / OSAL_ST_FREQUENCY) - 1 > 0xFFFFFF -#error "the selected ST frequency is not obtainable because SysTick timer counter limits" -#endif - -#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if (OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) || defined(__DOXYGEN__) -/** - * @brief System Timer vector. - * @details This interrupt is used for system tick in periodic mode. - * - * @isr - */ -OSAL_IRQ_HANDLER(SysTick_Handler) { - - OSAL_IRQ_PROLOGUE(); - - osalSysLockFromISR(); - osalOsTimerHandlerI(); - osalSysUnlockFromISR(); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */ - -#if (OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING) || defined(__DOXYGEN__) -/** - * @brief TIM2 interrupt handler. - * @details This interrupt is used for system tick in free running mode. - * - * @isr - */ -OSAL_IRQ_HANDLER(ST_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - /* Note, under rare circumstances an interrupt can remain latched even if - the timer SR register has been cleared, in those cases the interrupt - is simply ignored.*/ - if ((STM32_ST_TIM->SR & TIM_SR_CC1IF) != 0U) { - STM32_ST_TIM->SR = 0U; - - osalSysLockFromISR(); - osalOsTimerHandlerI(); - osalSysUnlockFromISR(); - } - - OSAL_IRQ_EPILOGUE(); -} -#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level ST driver initialization. - * - * @notapi - */ -void st_lld_init(void) { - -#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING - /* Free running counter mode.*/ - - /* Enabling timer clock.*/ - ST_ENABLE_CLOCK(); - - /* Enabling the stop mode during debug for this timer.*/ - ST_ENABLE_STOP(); - - /* Initializing the counter in free running mode.*/ - STM32_ST_TIM->PSC = (ST_CLOCK_SRC / OSAL_ST_FREQUENCY) - 1; - STM32_ST_TIM->ARR = ST_ARR_INIT; - STM32_ST_TIM->CCMR1 = 0; - STM32_ST_TIM->CCR[0] = 0; - STM32_ST_TIM->DIER = 0; - STM32_ST_TIM->CR2 = 0; - STM32_ST_TIM->EGR = TIM_EGR_UG; - STM32_ST_TIM->CR1 = TIM_CR1_CEN; - - /* IRQ enabled.*/ - nvicEnableVector(ST_NUMBER, STM32_ST_IRQ_PRIORITY); -#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */ - -#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC - /* Periodic systick mode, the Cortex-Mx internal systick timer is used - in this mode.*/ - SysTick->LOAD = (STM32_HCLK / OSAL_ST_FREQUENCY) - 1; - SysTick->VAL = 0; - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk | - SysTick_CTRL_TICKINT_Msk; - - /* IRQ enabled.*/ - nvicSetSystemHandlerPriority(HANDLER_SYSTICK, STM32_ST_IRQ_PRIORITY); -#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */ -} - -#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/TIMv1/st_lld.h b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/TIMv1/st_lld.h deleted file mode 100644 index 6c9835d3a8..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/TIMv1/st_lld.h +++ /dev/null @@ -1,210 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/st_lld.h - * @brief ST Driver subsystem low level driver header. - * @details This header is designed to be include-able without having to - * include other files from the HAL. - * - * @addtogroup ST - * @{ - */ - -#ifndef _ST_LLD_H_ -#define _ST_LLD_H_ - -#include "mcuconf.h" -#include "stm32_registry.h" -#include "stm32_tim.h" - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief SysTick timer IRQ priority. - */ -#if !defined(STM32_ST_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ST_IRQ_PRIORITY 8 -#endif - -/** - * @brief TIMx unit (by number) to be used for free running operations. - * @note You must select a 32 bits timer if a 32 bits @p systick_t type - * is required. - * @note Timers 2, 3, 4 and 5 are supported. - */ -#if !defined(STM32_ST_USE_TIMER) || defined(__DOXYGEN__) -#define STM32_ST_USE_TIMER 2 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_ST_USE_TIMER == 2 -#if !STM32_HAS_TIM2 -#error "TIM2 not present" -#endif -#define STM32_ST_TIM STM32_TIM2 - -#elif STM32_ST_USE_TIMER == 3 -#if !STM32_HAS_TIM3 -#error "TIM3 not present" -#endif -#define STM32_ST_TIM STM32_TIM3 - -#elif STM32_ST_USE_TIMER == 4 -#if !STM32_HAS_TIM4 -#error "TIM4 not present" -#endif -#define STM32_ST_TIM STM32_TIM4 - -#elif STM32_ST_USE_TIMER == 5 -#if !STM32_HAS_TIM5 -#error "TIM5 not present" -#endif -#define STM32_ST_TIM STM32_TIM5 - -#elif STM32_ST_USE_TIMER == 21 -#if !STM32_HAS_TIM21 -#error "TIM21 not present" -#endif -#define STM32_ST_TIM STM32_TIM21 - -#elif STM32_ST_USE_TIMER == 22 -#if !STM32_HAS_TIM22 -#error "TIM22 not present" -#endif -#define STM32_ST_TIM STM32_TIM22 - -#else -#error "STM32_ST_USE_TIMER specifies an unsupported timer" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void st_lld_init(void); -#ifdef __cplusplus -} -#endif - -/*===========================================================================*/ -/* Driver inline functions. */ -/*===========================================================================*/ - -/** - * @brief Returns the time counter value. - * - * @return The counter value. - * - * @notapi - */ -static inline systime_t st_lld_get_counter(void) { - - return (systime_t)STM32_ST_TIM->CNT; -} - -/** - * @brief Starts the alarm. - * @note Makes sure that no spurious alarms are triggered after - * this call. - * - * @param[in] time the time to be set for the first alarm - * - * @notapi - */ -static inline void st_lld_start_alarm(systime_t time) { - - STM32_ST_TIM->CCR[0] = (uint32_t)time; - STM32_ST_TIM->SR = 0; - STM32_ST_TIM->DIER = STM32_TIM_DIER_CC1IE; -} - -/** - * @brief Stops the alarm interrupt. - * - * @notapi - */ -static inline void st_lld_stop_alarm(void) { - - STM32_ST_TIM->DIER = 0; -} - -/** - * @brief Sets the alarm time. - * - * @param[in] time the time to be set for the next alarm - * - * @notapi - */ -static inline void st_lld_set_alarm(systime_t time) { - - STM32_ST_TIM->CCR[0] = (uint32_t)time; -} - -/** - * @brief Returns the current alarm time. - * - * @return The currently set alarm time. - * - * @notapi - */ -static inline systime_t st_lld_get_alarm(void) { - - return (systime_t)STM32_ST_TIM->CCR[0]; -} - -/** - * @brief Determines if the alarm is active. - * - * @return The alarm status. - * @retval false if the alarm is not active. - * @retval true is the alarm is active - * - * @notapi - */ -static inline bool st_lld_is_alarm_active(void) { - - return (bool)((STM32_ST_TIM->DIER & STM32_TIM_DIER_CC1IE) != 0); -} - -#endif /* _ST_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/TIMv1/stm32_tim.h b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/TIMv1/stm32_tim.h deleted file mode 100644 index bd4d0d0e95..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/TIMv1/stm32_tim.h +++ /dev/null @@ -1,450 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file stm32_tim.h - * @brief STM32 TIM units common header. - * @note This file requires definitions from the ST STM32 header file. - * - * @addtogroup STM32_TIMv1 - * @{ - */ - -#ifndef _STM32_TIM_H_ -#define _STM32_TIM_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name TIM_CR1 register - * @{ - */ -#define STM32_TIM_CR1_CEN (1U << 0) -#define STM32_TIM_CR1_UDIS (1U << 1) -#define STM32_TIM_CR1_URS (1U << 2) -#define STM32_TIM_CR1_OPM (1U << 3) -#define STM32_TIM_CR1_DIR (1U << 4) - -#define STM32_TIM_CR1_CMS_MASK (3U << 5) -#define STM32_TIM_CR1_CMS(n) ((n) << 5) - -#define STM32_TIM_CR1_ARPE (1U << 7) - -#define STM32_TIM_CR1_CKD_MASK (3U << 8) -#define STM32_TIM_CR1_CKD(n) ((n) << 8) - -#define STM32_TIM_CR1_UIFREMAP (1U << 11) -/** @} */ - -/** - * @name TIM_CR2 register - * @{ - */ -#define STM32_TIM_CR2_CCPC (1U << 0) -#define STM32_TIM_CR2_CCUS (1U << 2) -#define STM32_TIM_CR2_CCDS (1U << 3) - -#define STM32_TIM_CR2_MMS_MASK (7U << 4) -#define STM32_TIM_CR2_MMS(n) ((n) << 4) - -#define STM32_TIM_CR2_TI1S (1U << 7) -#define STM32_TIM_CR2_OIS1 (1U << 8) -#define STM32_TIM_CR2_OIS1N (1U << 9) -#define STM32_TIM_CR2_OIS2 (1U << 10) -#define STM32_TIM_CR2_OIS2N (1U << 11) -#define STM32_TIM_CR2_OIS3 (1U << 12) -#define STM32_TIM_CR2_OIS3N (1U << 13) -#define STM32_TIM_CR2_OIS4 (1U << 14) -#define STM32_TIM_CR2_OIS5 (1U << 16) -#define STM32_TIM_CR2_OIS6 (1U << 18) - -#define STM32_TIM_CR2_MMS2_MASK (15U << 20) -#define STM32_TIM_CR2_MMS2(n) ((n) << 20) -/** @} */ - -/** - * @name TIM_SMCR register - * @{ - */ -#define STM32_TIM_SMCR_SMS_MASK ((7U << 0) | (1U << 16)) -#define STM32_TIM_SMCR_SMS(n) ((((n) & 7) << 0) | \ - (((n) >> 3) << 16)) - -#define STM32_TIM_SMCR_OCCS (1U << 3) - -#define STM32_TIM_SMCR_TS_MASK (7U << 4) -#define STM32_TIM_SMCR_TS(n) ((n) << 4) - -#define STM32_TIM_SMCR_MSM (1U << 7) - -#define STM32_TIM_SMCR_ETF_MASK (15U << 8) -#define STM32_TIM_SMCR_ETF(n) ((n) << 8) - -#define STM32_TIM_SMCR_ETPS_MASK (3U << 12) -#define STM32_TIM_SMCR_ETPS(n) ((n) << 12) - -#define STM32_TIM_SMCR_ECE (1U << 14) -#define STM32_TIM_SMCR_ETP (1U << 15) -/** @} */ - -/** - * @name TIM_DIER register - * @{ - */ -#define STM32_TIM_DIER_UIE (1U << 0) -#define STM32_TIM_DIER_CC1IE (1U << 1) -#define STM32_TIM_DIER_CC2IE (1U << 2) -#define STM32_TIM_DIER_CC3IE (1U << 3) -#define STM32_TIM_DIER_CC4IE (1U << 4) -#define STM32_TIM_DIER_COMIE (1U << 5) -#define STM32_TIM_DIER_TIE (1U << 6) -#define STM32_TIM_DIER_BIE (1U << 7) -#define STM32_TIM_DIER_UDE (1U << 8) -#define STM32_TIM_DIER_CC1DE (1U << 9) -#define STM32_TIM_DIER_CC2DE (1U << 10) -#define STM32_TIM_DIER_CC3DE (1U << 11) -#define STM32_TIM_DIER_CC4DE (1U << 12) -#define STM32_TIM_DIER_COMDE (1U << 13) -#define STM32_TIM_DIER_TDE (1U << 14) - -#define STM32_TIM_DIER_IRQ_MASK (STM32_TIM_DIER_UIE | \ - STM32_TIM_DIER_CC1IE | \ - STM32_TIM_DIER_CC2IE | \ - STM32_TIM_DIER_CC3IE | \ - STM32_TIM_DIER_CC4IE | \ - STM32_TIM_DIER_COMIE | \ - STM32_TIM_DIER_TIE | \ - STM32_TIM_DIER_BIE) - -/** @} */ - -/** - * @name TIM_SR register - * @{ - */ -#define STM32_TIM_SR_UIF (1U << 0) -#define STM32_TIM_SR_CC1IF (1U << 1) -#define STM32_TIM_SR_CC2IF (1U << 2) -#define STM32_TIM_SR_CC3IF (1U << 3) -#define STM32_TIM_SR_CC4IF (1U << 4) -#define STM32_TIM_SR_COMIF (1U << 5) -#define STM32_TIM_SR_TIF (1U << 6) -#define STM32_TIM_SR_BIF (1U << 7) -#define STM32_TIM_SR_B2IF (1U << 8) -#define STM32_TIM_SR_CC1OF (1U << 9) -#define STM32_TIM_SR_CC2OF (1U << 10) -#define STM32_TIM_SR_CC3OF (1U << 11) -#define STM32_TIM_SR_CC4OF (1U << 12) -#define STM32_TIM_SR_CC5IF (1U << 16) -#define STM32_TIM_SR_CC6IF (1U << 17) -/** @} */ - -/** - * @name TIM_EGR register - * @{ - */ -#define STM32_TIM_EGR_UG (1U << 0) -#define STM32_TIM_EGR_CC1G (1U << 1) -#define STM32_TIM_EGR_CC2G (1U << 2) -#define STM32_TIM_EGR_CC3G (1U << 3) -#define STM32_TIM_EGR_CC4G (1U << 4) -#define STM32_TIM_EGR_COMG (1U << 5) -#define STM32_TIM_EGR_TG (1U << 6) -#define STM32_TIM_EGR_BG (1U << 7) -#define STM32_TIM_EGR_B2G (1U << 8) -/** @} */ - -/** - * @name TIM_CCMR1 register (output) - * @{ - */ -#define STM32_TIM_CCMR1_CC1S_MASK (3U << 0) -#define STM32_TIM_CCMR1_CC1S(n) ((n) << 0) - -#define STM32_TIM_CCMR1_OC1FE (1U << 2) -#define STM32_TIM_CCMR1_OC1PE (1U << 3) - -#define STM32_TIM_CCMR1_OC1M_MASK ((7U << 4) | (1U << 16)) -#define STM32_TIM_CCMR1_OC1M(n) ((((n) & 7) << 4) | \ - (((n) >> 3) << 16)) - -#define STM32_TIM_CCMR1_OC1CE (1U << 7) - -#define STM32_TIM_CCMR1_CC2S_MASK (3U << 8) -#define STM32_TIM_CCMR1_CC2S(n) ((n) << 8) - -#define STM32_TIM_CCMR1_OC2FE (1U << 10) -#define STM32_TIM_CCMR1_OC2PE (1U << 11) - -#define STM32_TIM_CCMR1_OC2M_MASK ((7U << 12) | (1U << 24)) -#define STM32_TIM_CCMR1_OC2M(n) ((((n) & 7) << 12) | \ - (((n) >> 3) << 24)) - -#define STM32_TIM_CCMR1_OC2CE (1U << 15) -/** @} */ - -/** - * @name CCMR1 register (input) - * @{ - */ -#define STM32_TIM_CCMR1_IC1PSC_MASK (3U << 2) -#define STM32_TIM_CCMR1_IC1PSC(n) ((n) << 2) - -#define STM32_TIM_CCMR1_IC1F_MASK (15U << 4) -#define STM32_TIM_CCMR1_IC1F(n) ((n) << 4) - -#define STM32_TIM_CCMR1_IC2PSC_MASK (3U << 10) -#define STM32_TIM_CCMR1_IC2PSC(n) ((n) << 10) - -#define STM32_TIM_CCMR1_IC2F_MASK (15U << 12) -#define STM32_TIM_CCMR1_IC2F(n) ((n) << 12) -/** @} */ - -/** - * @name TIM_CCMR2 register (output) - * @{ - */ -#define STM32_TIM_CCMR2_CC3S_MASK (3U << 0) -#define STM32_TIM_CCMR2_CC3S(n) ((n) << 0) - -#define STM32_TIM_CCMR2_OC3FE (1U << 2) -#define STM32_TIM_CCMR2_OC3PE (1U << 3) - -#define STM32_TIM_CCMR2_OC3M_MASK ((7U << 4) | (1U << 16)) -#define STM32_TIM_CCMR2_OC3M(n) ((((n) & 7) << 4) | \ - (((n) >> 3) << 16)) - -#define STM32_TIM_CCMR2_OC3CE (1U << 7) - -#define STM32_TIM_CCMR2_CC4S_MASK (3U << 8) -#define STM32_TIM_CCMR2_CC4S(n) ((n) << 8) - -#define STM32_TIM_CCMR2_OC4FE (1U << 10) -#define STM32_TIM_CCMR2_OC4PE (1U << 11) - -#define STM32_TIM_CCMR2_OC4M_MASK ((7U << 12) | (1U << 24)) -#define STM32_TIM_CCMR2_OC4M(n) ((((n) & 7) << 12) | \ - (((n) >> 3) << 24)) - -#define STM32_TIM_CCMR2_OC4CE (1U << 15) -/** @} */ - -/** - * @name TIM_CCMR2 register (input) - * @{ - */ -#define STM32_TIM_CCMR2_IC3PSC_MASK (3U << 2) -#define STM32_TIM_CCMR2_IC3PSC(n) ((n) << 2) - -#define STM32_TIM_CCMR2_IC3F_MASK (15U << 4) -#define STM32_TIM_CCMR2_IC3F(n) ((n) << 4) - -#define STM32_TIM_CCMR2_IC4PSC_MASK (3U << 10) -#define STM32_TIM_CCMR2_IC4PSC(n) ((n) << 10) - -#define STM32_TIM_CCMR2_IC4F_MASK (15U << 12) -#define STM32_TIM_CCMR2_IC4F(n) ((n) << 12) -/** @} */ - -/** - * @name TIM_CCER register - * @{ - */ -#define STM32_TIM_CCER_CC1E (1U << 0) -#define STM32_TIM_CCER_CC1P (1U << 1) -#define STM32_TIM_CCER_CC1NE (1U << 2) -#define STM32_TIM_CCER_CC1NP (1U << 3) -#define STM32_TIM_CCER_CC2E (1U << 4) -#define STM32_TIM_CCER_CC2P (1U << 5) -#define STM32_TIM_CCER_CC2NE (1U << 6) -#define STM32_TIM_CCER_CC2NP (1U << 7) -#define STM32_TIM_CCER_CC3E (1U << 8) -#define STM32_TIM_CCER_CC3P (1U << 9) -#define STM32_TIM_CCER_CC3NE (1U << 10) -#define STM32_TIM_CCER_CC3NP (1U << 11) -#define STM32_TIM_CCER_CC4E (1U << 12) -#define STM32_TIM_CCER_CC4P (1U << 13) -#define STM32_TIM_CCER_CC4NP (1U << 15) -#define STM32_TIM_CCER_CC5E (1U << 16) -#define STM32_TIM_CCER_CC5P (1U << 17) -#define STM32_TIM_CCER_CC6E (1U << 20) -#define STM32_TIM_CCER_CC6P (1U << 21) -/** @} */ - -/** - * @name TIM_CNT register - * @{ - */ -#define STM32_TIM_CNT_UIFCPY (1U << 31) -/** @} */ - -/** - * @name TIM_BDTR register - * @{ - */ -#define STM32_TIM_BDTR_DTG_MASK (255U << 0) -#define STM32_TIM_BDTR_DTG(n) ((n) << 0) - -#define STM32_TIM_BDTR_LOCK_MASK (3U << 8) -#define STM32_TIM_BDTR_LOCK(n) ((n) << 8) - -#define STM32_TIM_BDTR_OSSI (1U << 10) -#define STM32_TIM_BDTR_OSSR (1U << 11) -#define STM32_TIM_BDTR_BKE (1U << 12) -#define STM32_TIM_BDTR_BKP (1U << 13) -#define STM32_TIM_BDTR_AOE (1U << 14) -#define STM32_TIM_BDTR_MOE (1U << 15) - -#define STM32_TIM_BDTR_BKF_MASK (15U << 16) -#define STM32_TIM_BDTR_BKF(n) ((n) << 16) -#define STM32_TIM_BDTR_BK2F_MASK (15U << 20) -#define STM32_TIM_BDTR_BK2F(n) ((n) << 20) - -#define STM32_TIM_BDTR_BK2E (1U << 24) -#define STM32_TIM_BDTR_BK2P (1U << 25) -/** @} */ - -/** - * @name TIM_DCR register - * @{ - */ -#define STM32_TIM_DCR_DBA_MASK (31U << 0) -#define STM32_TIM_DCR_DBA(n) ((n) << 0) - -#define STM32_TIM_DCR_DBL_MASK (31U << 8) -#define STM32_TIM_DCR_DBL(b) ((n) << 8) -/** @} */ - -/** - * @name TIM16_OR register - * @{ - */ -#define STM32_TIM16_OR_TI1_RMP_MASK (3U << 6) -#define STM32_TIM16_OR_TI1_RMP(n) ((n) << 6) -/** @} */ - -/** - * @name TIM_OR register - * @{ - */ -#define STM32_TIM_OR_ETR_RMP_MASK (15U << 0) -#define STM32_TIM_OR_ETR_RMP(n) ((n) << 0) -/** @} */ - -/** - * @name TIM_CCMR3 register - * @{ - */ -#define STM32_TIM_CCMR3_OC5FE (1U << 2) -#define STM32_TIM_CCMR3_OC5PE (1U << 3) - -#define STM32_TIM_CCMR3_OC5M_MASK ((7U << 4) | (1U << 16)) -#define STM32_TIM_CCMR3_OC5M(n) ((((n) & 7) << 4) | \ - (((n) >> 2) << 16)) - -#define STM32_TIM_CCMR3_OC5CE (1U << 7) - -#define STM32_TIM_CCMR3_OC6FE (1U << 10) -#define STM32_TIM_CCMR3_OC6PE (1U << 11) - -#define STM32_TIM_CCMR3_OC6M_MASK ((7U << 12) | (1U << 24)) -#define STM32_TIM_CCMR3_OC6M(n) ((((n) & 7) << 12) | \ - (((n) >> 2) << 24)) - -#define STM32_TIM_CCMR3_OC6CE (1U << 15) -/** @} */ - -/** - * @name TIM units references - * @{ - */ -#define STM32_TIM1 ((stm32_tim_t *)TIM1_BASE) -#define STM32_TIM2 ((stm32_tim_t *)TIM2_BASE) -#define STM32_TIM3 ((stm32_tim_t *)TIM3_BASE) -#define STM32_TIM4 ((stm32_tim_t *)TIM4_BASE) -#define STM32_TIM5 ((stm32_tim_t *)TIM5_BASE) -#define STM32_TIM6 ((stm32_tim_t *)TIM6_BASE) -#define STM32_TIM7 ((stm32_tim_t *)TIM7_BASE) -#define STM32_TIM8 ((stm32_tim_t *)TIM8_BASE) -#define STM32_TIM9 ((stm32_tim_t *)TIM9_BASE) -#define STM32_TIM10 ((stm32_tim_t *)TIM10_BASE) -#define STM32_TIM11 ((stm32_tim_t *)TIM11_BASE) -#define STM32_TIM12 ((stm32_tim_t *)TIM12_BASE) -#define STM32_TIM13 ((stm32_tim_t *)TIM13_BASE) -#define STM32_TIM14 ((stm32_tim_t *)TIM14_BASE) -#define STM32_TIM15 ((stm32_tim_t *)TIM15_BASE) -#define STM32_TIM16 ((stm32_tim_t *)TIM16_BASE) -#define STM32_TIM17 ((stm32_tim_t *)TIM17_BASE) -#define STM32_TIM18 ((stm32_tim_t *)TIM18_BASE) -#define STM32_TIM19 ((stm32_tim_t *)TIM19_BASE) -#define STM32_TIM20 ((stm32_tim_t *)TIM20_BASE) -#define STM32_TIM21 ((stm32_tim_t *)TIM21_BASE) -#define STM32_TIM22 ((stm32_tim_t *)TIM22_BASE) -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief STM32 TIM registers block. - * @note This is the most general known form, not all timers have - * necessarily all registers and bits. - */ -typedef struct { - volatile uint32_t CR1; - volatile uint32_t CR2; - volatile uint32_t SMCR; - volatile uint32_t DIER; - volatile uint32_t SR; - volatile uint32_t EGR; - volatile uint32_t CCMR1; - volatile uint32_t CCMR2; - volatile uint32_t CCER; - volatile uint32_t CNT; - volatile uint32_t PSC; - volatile uint32_t ARR; - volatile uint32_t RCR; - volatile uint32_t CCR[4]; - volatile uint32_t BDTR; - volatile uint32_t DCR; - volatile uint32_t DMAR; - volatile uint32_t OR; - volatile uint32_t CCMR3; - volatile uint32_t CCXR[2]; -} stm32_tim_t; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#endif /* _STM32_TIM_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/TIMv1/tim_irq_mapping.txt b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/TIMv1/tim_irq_mapping.txt deleted file mode 100644 index 9c980c51e9..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/TIMv1/tim_irq_mapping.txt +++ /dev/null @@ -1,14 +0,0 @@ -TIM units IRQ collisions mapping. - - 1B 1UP 1TC 1CC 2 3 4 5 6 7 8B 8UP 8TC 8CC 9 10 11 12 13 14 15 16 17 18 19 20 21 22 LP1 LP2 -F0xx 1---1 2---2 * * * * * * * * -F030 1---1 2---2 * * * * * -F1xx 1 2 3 * * * * * * * 1 2 3 -F100 1 2 3 * * * * * * * 1 2 3 -F3xx 1 2 3 * * * * * * * * * * 1 2 3 -F37x * * * * * * * * * * * * * * -F4xx 1 2 3 * * * * * * * 4 5 6 * 1 2 3 4 5 6 -F7xx 1 2 3 * * * * * * * 4 5 6 * 1 2 3 4 5 6 * -L0xx * * * * * -L1xx * * * * * * * * * -L4xx 1 2 3 * * * * * * * * * * * 1 2 3 * * diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/USARTv1/serial_lld.c b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/USARTv1/serial_lld.c deleted file mode 100644 index 0ee5b8132c..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/USARTv1/serial_lld.c +++ /dev/null @@ -1,631 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/USARTv1/serial_lld.c - * @brief STM32 low level serial driver code. - * - * @addtogroup SERIAL - * @{ - */ - -#include "hal.h" - -#if HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief USART1 serial driver identifier.*/ -#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__) -SerialDriver SD1; -#endif - -/** @brief USART2 serial driver identifier.*/ -#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__) -SerialDriver SD2; -#endif - -/** @brief USART3 serial driver identifier.*/ -#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__) -SerialDriver SD3; -#endif - -/** @brief UART4 serial driver identifier.*/ -#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__) -SerialDriver SD4; -#endif - -/** @brief UART5 serial driver identifier.*/ -#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__) -SerialDriver SD5; -#endif - -/** @brief USART6 serial driver identifier.*/ -#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__) -SerialDriver SD6; -#endif - -/** @brief UART7 serial driver identifier.*/ -#if STM32_SERIAL_USE_UART7 || defined(__DOXYGEN__) -SerialDriver SD7; -#endif - -/** @brief UART8 serial driver identifier.*/ -#if STM32_SERIAL_USE_UART8 || defined(__DOXYGEN__) -SerialDriver SD8; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** @brief Driver default configuration.*/ -static const SerialConfig default_config = -{ - SERIAL_DEFAULT_BITRATE, - 0, - USART_CR2_STOP1_BITS | USART_CR2_LINEN, - 0 -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief USART initialization. - * @details This function must be invoked with interrupts disabled. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] config the architecture-dependent serial driver configuration - */ -static void usart_init(SerialDriver *sdp, const SerialConfig *config) { - USART_TypeDef *u = sdp->usart; - - /* Baud rate setting.*/ -#if STM32_HAS_USART6 - if ((sdp->usart == USART1) || (sdp->usart == USART6)) -#else - if (sdp->usart == USART1) -#endif - u->BRR = STM32_PCLK2 / config->speed; - else - u->BRR = STM32_PCLK1 / config->speed; - - /* Note that some bits are enforced.*/ - u->CR2 = config->cr2 | USART_CR2_LBDIE; - u->CR3 = config->cr3 | USART_CR3_EIE; - u->CR1 = config->cr1 | USART_CR1_UE | USART_CR1_PEIE | - USART_CR1_RXNEIE | USART_CR1_TE | - USART_CR1_RE; - u->SR = 0; - (void)u->SR; /* SR reset step 1.*/ - (void)u->DR; /* SR reset step 2.*/ -} - -/** - * @brief USART de-initialization. - * @details This function must be invoked with interrupts disabled. - * - * @param[in] u pointer to an USART I/O block - */ -static void usart_deinit(USART_TypeDef *u) { - - u->CR1 = 0; - u->CR2 = 0; - u->CR3 = 0; -} - -/** - * @brief Error handling routine. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] sr USART SR register value - */ -static void set_error(SerialDriver *sdp, uint16_t sr) { - eventflags_t sts = 0; - - if (sr & USART_SR_ORE) - sts |= SD_OVERRUN_ERROR; - if (sr & USART_SR_PE) - sts |= SD_PARITY_ERROR; - if (sr & USART_SR_FE) - sts |= SD_FRAMING_ERROR; - if (sr & USART_SR_NE) - sts |= SD_NOISE_ERROR; - chnAddFlagsI(sdp, sts); -} - -/** - * @brief Common IRQ handler. - * - * @param[in] sdp communication channel associated to the USART - */ -static void serve_interrupt(SerialDriver *sdp) { - USART_TypeDef *u = sdp->usart; - uint16_t cr1 = u->CR1; - uint16_t sr = u->SR; - - /* Special case, LIN break detection.*/ - if (sr & USART_SR_LBD) { - osalSysLockFromISR(); - chnAddFlagsI(sdp, SD_BREAK_DETECTED); - u->SR = ~USART_SR_LBD; - osalSysUnlockFromISR(); - } - - /* Data available.*/ - osalSysLockFromISR(); - while (sr & (USART_SR_RXNE | USART_SR_ORE | USART_SR_NE | USART_SR_FE | - USART_SR_PE)) { - uint8_t b; - - /* Error condition detection.*/ - if (sr & (USART_SR_ORE | USART_SR_NE | USART_SR_FE | USART_SR_PE)) - set_error(sdp, sr); - b = u->DR; - if (sr & USART_SR_RXNE) - sdIncomingDataI(sdp, b); - sr = u->SR; - } - osalSysUnlockFromISR(); - - /* Transmission buffer empty.*/ - if ((cr1 & USART_CR1_TXEIE) && (sr & USART_SR_TXE)) { - msg_t b; - osalSysLockFromISR(); - b = oqGetI(&sdp->oqueue); - if (b < Q_OK) { - chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); - u->CR1 = (cr1 & ~USART_CR1_TXEIE) | USART_CR1_TCIE; - } - else - u->DR = b; - osalSysUnlockFromISR(); - } - - /* Physical transmission end.*/ - if (sr & USART_SR_TC) { - osalSysLockFromISR(); - if (oqIsEmptyI(&sdp->oqueue)) - chnAddFlagsI(sdp, CHN_TRANSMISSION_END); - u->CR1 = cr1 & ~USART_CR1_TCIE; - u->SR = ~USART_SR_TC; - osalSysUnlockFromISR(); - } -} - -#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__) -static void notify1(io_queue_t *qp) { - - (void)qp; - USART1->CR1 |= USART_CR1_TXEIE; -} -#endif - -#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__) -static void notify2(io_queue_t *qp) { - - (void)qp; - USART2->CR1 |= USART_CR1_TXEIE; -} -#endif - -#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__) -static void notify3(io_queue_t *qp) { - - (void)qp; - USART3->CR1 |= USART_CR1_TXEIE; -} -#endif - -#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__) -static void notify4(io_queue_t *qp) { - - (void)qp; - UART4->CR1 |= USART_CR1_TXEIE; -} -#endif - -#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__) -static void notify5(io_queue_t *qp) { - - (void)qp; - UART5->CR1 |= USART_CR1_TXEIE; -} -#endif - -#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__) -static void notify6(io_queue_t *qp) { - - (void)qp; - USART6->CR1 |= USART_CR1_TXEIE; -} -#endif - -#if STM32_SERIAL_USE_UART7 || defined(__DOXYGEN__) -static void notify7(io_queue_t *qp) { - - (void)qp; - UART7->CR1 |= USART_CR1_TXEIE; -} -#endif - -#if STM32_SERIAL_USE_UART8 || defined(__DOXYGEN__) -static void notify8(io_queue_t *qp) { - - (void)qp; - UART8->CR1 |= USART_CR1_TXEIE; -} -#endif - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__) -#if !defined(STM32_USART1_HANDLER) -#error "STM32_USART1_HANDLER not defined" -#endif -/** - * @brief USART1 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_USART1_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - serve_interrupt(&SD1); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__) -#if !defined(STM32_USART2_HANDLER) -#error "STM32_USART2_HANDLER not defined" -#endif -/** - * @brief USART2 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_USART2_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - serve_interrupt(&SD2); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__) -#if !defined(STM32_USART3_HANDLER) -#error "STM32_USART3_HANDLER not defined" -#endif -/** - * @brief USART3 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_USART3_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - serve_interrupt(&SD3); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__) -#if !defined(STM32_UART4_HANDLER) -#error "STM32_UART4_HANDLER not defined" -#endif -/** - * @brief UART4 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_UART4_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - serve_interrupt(&SD4); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__) -#if !defined(STM32_UART5_HANDLER) -#error "STM32_UART5_HANDLER not defined" -#endif -/** - * @brief UART5 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_UART5_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - serve_interrupt(&SD5); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__) -#if !defined(STM32_USART6_HANDLER) -#error "STM32_USART6_HANDLER not defined" -#endif -/** - * @brief USART6 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_USART6_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - serve_interrupt(&SD6); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if STM32_SERIAL_USE_UART7 || defined(__DOXYGEN__) -#if !defined(STM32_UART7_HANDLER) -#error "STM32_UART7_HANDLER not defined" -#endif -/** - * @brief UART7 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_UART7_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - serve_interrupt(&SD7); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if STM32_SERIAL_USE_UART8 || defined(__DOXYGEN__) -#if !defined(STM32_UART8_HANDLER) -#error "STM32_UART8_HANDLER not defined" -#endif -/** - * @brief UART8 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_UART8_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - serve_interrupt(&SD8); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level serial driver initialization. - * - * @notapi - */ -void sd_lld_init(void) { - -#if STM32_SERIAL_USE_USART1 - sdObjectInit(&SD1, NULL, notify1); - SD1.usart = USART1; -#endif - -#if STM32_SERIAL_USE_USART2 - sdObjectInit(&SD2, NULL, notify2); - SD2.usart = USART2; -#endif - -#if STM32_SERIAL_USE_USART3 - sdObjectInit(&SD3, NULL, notify3); - SD3.usart = USART3; -#endif - -#if STM32_SERIAL_USE_UART4 - sdObjectInit(&SD4, NULL, notify4); - SD4.usart = UART4; -#endif - -#if STM32_SERIAL_USE_UART5 - sdObjectInit(&SD5, NULL, notify5); - SD5.usart = UART5; -#endif - -#if STM32_SERIAL_USE_USART6 - sdObjectInit(&SD6, NULL, notify6); - SD6.usart = USART6; -#endif - -#if STM32_SERIAL_USE_UART7 - sdObjectInit(&SD7, NULL, notify7); - SD7.usart = UART7; -#endif - -#if STM32_SERIAL_USE_UART8 - sdObjectInit(&SD8, NULL, notify8); - SD8.usart = UART8; -#endif -} - -/** - * @brief Low level serial driver configuration and (re)start. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] config the architecture-dependent serial driver configuration. - * If this parameter is set to @p NULL then a default - * configuration is used. - * - * @notapi - */ -void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { - - if (config == NULL) - config = &default_config; - - if (sdp->state == SD_STOP) { -#if STM32_SERIAL_USE_USART1 - if (&SD1 == sdp) { - rccEnableUSART1(FALSE); - nvicEnableVector(STM32_USART1_NUMBER, STM32_SERIAL_USART1_PRIORITY); - } -#endif -#if STM32_SERIAL_USE_USART2 - if (&SD2 == sdp) { - rccEnableUSART2(FALSE); - nvicEnableVector(STM32_USART2_NUMBER, STM32_SERIAL_USART2_PRIORITY); - } -#endif -#if STM32_SERIAL_USE_USART3 - if (&SD3 == sdp) { - rccEnableUSART3(FALSE); - nvicEnableVector(STM32_USART3_NUMBER, STM32_SERIAL_USART3_PRIORITY); - } -#endif -#if STM32_SERIAL_USE_UART4 - if (&SD4 == sdp) { - rccEnableUART4(FALSE); - nvicEnableVector(STM32_UART4_NUMBER, STM32_SERIAL_UART4_PRIORITY); - } -#endif -#if STM32_SERIAL_USE_UART5 - if (&SD5 == sdp) { - rccEnableUART5(FALSE); - nvicEnableVector(STM32_UART5_NUMBER, STM32_SERIAL_UART5_PRIORITY); - } -#endif -#if STM32_SERIAL_USE_USART6 - if (&SD6 == sdp) { - rccEnableUSART6(FALSE); - nvicEnableVector(STM32_USART6_NUMBER, STM32_SERIAL_USART6_PRIORITY); - } -#endif -#if STM32_SERIAL_USE_UART7 - if (&SD7 == sdp) { - rccEnableUART7(FALSE); - nvicEnableVector(STM32_UART7_NUMBER, STM32_SERIAL_UART7_PRIORITY); - } -#endif -#if STM32_SERIAL_USE_UART8 - if (&SD8 == sdp) { - rccEnableUART8(FALSE); - nvicEnableVector(STM32_UART8_NUMBER, STM32_SERIAL_UART8_PRIORITY); - } -#endif - } - usart_init(sdp, config); -} - -/** - * @brief Low level serial driver stop. - * @details De-initializes the USART, stops the associated clock, resets the - * interrupt vector. - * - * @param[in] sdp pointer to a @p SerialDriver object - * - * @notapi - */ -void sd_lld_stop(SerialDriver *sdp) { - - if (sdp->state == SD_READY) { - usart_deinit(sdp->usart); -#if STM32_SERIAL_USE_USART1 - if (&SD1 == sdp) { - rccDisableUSART1(FALSE); - nvicDisableVector(STM32_USART1_NUMBER); - return; - } -#endif -#if STM32_SERIAL_USE_USART2 - if (&SD2 == sdp) { - rccDisableUSART2(FALSE); - nvicDisableVector(STM32_USART2_NUMBER); - return; - } -#endif -#if STM32_SERIAL_USE_USART3 - if (&SD3 == sdp) { - rccDisableUSART3(FALSE); - nvicDisableVector(STM32_USART3_NUMBER); - return; - } -#endif -#if STM32_SERIAL_USE_UART4 - if (&SD4 == sdp) { - rccDisableUART4(FALSE); - nvicDisableVector(STM32_UART4_NUMBER); - return; - } -#endif -#if STM32_SERIAL_USE_UART5 - if (&SD5 == sdp) { - rccDisableUART5(FALSE); - nvicDisableVector(STM32_UART5_NUMBER); - return; - } -#endif -#if STM32_SERIAL_USE_USART6 - if (&SD6 == sdp) { - rccDisableUSART6(FALSE); - nvicDisableVector(STM32_USART6_NUMBER); - return; - } -#endif -#if STM32_SERIAL_USE_UART7 - if (&SD7 == sdp) { - rccDisableUART7(FALSE); - nvicDisableVector(STM32_UART7_NUMBER); - return; - } -#endif -#if STM32_SERIAL_USE_UART8 - if (&SD8 == sdp) { - rccDisableUART8(FALSE); - nvicDisableVector(STM32_UART8_NUMBER); - return; - } -#endif - } -} - -#endif /* HAL_USE_SERIAL */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/USARTv1/serial_lld.h b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/USARTv1/serial_lld.h deleted file mode 100644 index aea0848985..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/USARTv1/serial_lld.h +++ /dev/null @@ -1,360 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/USARTv1/serial_lld.h - * @brief STM32 low level serial driver header. - * - * @addtogroup SERIAL - * @{ - */ - -#ifndef _SERIAL_LLD_H_ -#define _SERIAL_LLD_H_ - -#if HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief USART1 driver enable switch. - * @details If set to @p TRUE the support for USART1 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SERIAL_USE_USART1) || defined(__DOXYGEN__) -#define STM32_SERIAL_USE_USART1 FALSE -#endif - -/** - * @brief USART2 driver enable switch. - * @details If set to @p TRUE the support for USART2 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SERIAL_USE_USART2) || defined(__DOXYGEN__) -#define STM32_SERIAL_USE_USART2 FALSE -#endif - -/** - * @brief USART3 driver enable switch. - * @details If set to @p TRUE the support for USART3 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SERIAL_USE_USART3) || defined(__DOXYGEN__) -#define STM32_SERIAL_USE_USART3 FALSE -#endif - -/** - * @brief UART4 driver enable switch. - * @details If set to @p TRUE the support for UART4 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SERIAL_USE_UART4) || defined(__DOXYGEN__) -#define STM32_SERIAL_USE_UART4 FALSE -#endif - -/** - * @brief UART5 driver enable switch. - * @details If set to @p TRUE the support for UART5 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SERIAL_USE_UART5) || defined(__DOXYGEN__) -#define STM32_SERIAL_USE_UART5 FALSE -#endif - -/** - * @brief USART6 driver enable switch. - * @details If set to @p TRUE the support for USART6 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SERIAL_USE_USART6) || defined(__DOXYGEN__) -#define STM32_SERIAL_USE_USART6 FALSE -#endif - -/** - * @brief UART7 driver enable switch. - * @details If set to @p TRUE the support for UART7 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SERIAL_USE_UART7) || defined(__DOXYGEN__) -#define STM32_SERIAL_USE_UART7 FALSE -#endif - -/** - * @brief UART8 driver enable switch. - * @details If set to @p TRUE the support for UART8 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SERIAL_USE_UART8) || defined(__DOXYGEN__) -#define STM32_SERIAL_USE_UART8 FALSE -#endif - -/** - * @brief USART1 interrupt priority level setting. - */ -#if !defined(STM32_SERIAL_USART1_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SERIAL_USART1_PRIORITY 12 -#endif - -/** - * @brief USART2 interrupt priority level setting. - */ -#if !defined(STM32_SERIAL_USART2_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SERIAL_USART2_PRIORITY 12 -#endif - -/** - * @brief USART3 interrupt priority level setting. - */ -#if !defined(STM32_SERIAL_USART3_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SERIAL_USART3_PRIORITY 12 -#endif - -/** - * @brief UART4 interrupt priority level setting. - */ -#if !defined(STM32_SERIAL_UART4_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SERIAL_UART4_PRIORITY 12 -#endif - -/** - * @brief UART5 interrupt priority level setting. - */ -#if !defined(STM32_SERIAL_UART5_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SERIAL_UART5_PRIORITY 12 -#endif - -/** - * @brief USART6 interrupt priority level setting. - */ -#if !defined(STM32_SERIAL_USART6_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SERIAL_USART6_PRIORITY 12 -#endif - -/** - * @brief UART7 interrupt priority level setting. - */ -#if !defined(STM32_SERIAL_UART7_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SERIAL_UART7_PRIORITY 12 -#endif - -/** - * @brief UART8 interrupt priority level setting. - */ -#if !defined(STM32_SERIAL_UART8_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SERIAL_UART8_PRIORITY 12 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_SERIAL_USE_USART1 && !STM32_HAS_USART1 -#error "USART1 not present in the selected device" -#endif - -#if STM32_SERIAL_USE_USART2 && !STM32_HAS_USART2 -#error "USART2 not present in the selected device" -#endif - -#if STM32_SERIAL_USE_USART3 && !STM32_HAS_USART3 -#error "USART3 not present in the selected device" -#endif - -#if STM32_SERIAL_USE_UART4 && !STM32_HAS_UART4 -#error "UART4 not present in the selected device" -#endif - -#if STM32_SERIAL_USE_UART5 && !STM32_HAS_UART5 -#error "UART5 not present in the selected device" -#endif - -#if STM32_SERIAL_USE_USART6 && !STM32_HAS_USART6 -#error "USART6 not present in the selected device" -#endif - -#if STM32_SERIAL_USE_UART7 && !STM32_HAS_UART7 -#error "UART7 not present in the selected device" -#endif - -#if STM32_SERIAL_USE_UART8 && !STM32_HAS_UART8 -#error "UART8 not present in the selected device" -#endif - -#if !STM32_SERIAL_USE_USART1 && !STM32_SERIAL_USE_USART2 && \ - !STM32_SERIAL_USE_USART3 && !STM32_SERIAL_USE_UART4 && \ - !STM32_SERIAL_USE_UART5 && !STM32_SERIAL_USE_USART6 && \ - !STM32_SERIAL_USE_UART7 && !STM32_SERIAL_USE_UART8 -#error "SERIAL driver activated but no USART/UART peripheral assigned" -#endif - -#if STM32_SERIAL_USE_USART1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_USART1_PRIORITY) -#error "Invalid IRQ priority assigned to USART1" -#endif - -#if STM32_SERIAL_USE_USART2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_USART2_PRIORITY) -#error "Invalid IRQ priority assigned to USART2" -#endif - -#if STM32_SERIAL_USE_USART3 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_USART3_PRIORITY) -#error "Invalid IRQ priority assigned to USART3" -#endif - -#if STM32_SERIAL_USE_UART4 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_UART4_PRIORITY) -#error "Invalid IRQ priority assigned to UART4" -#endif - -#if STM32_SERIAL_USE_UART5 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_UART5_PRIORITY) -#error "Invalid IRQ priority assigned to UART5" -#endif - -#if STM32_SERIAL_USE_USART6 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_USART6_PRIORITY) -#error "Invalid IRQ priority assigned to USART6" -#endif - -#if STM32_SERIAL_USE_UART7 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_UART7_PRIORITY) -#error "Invalid IRQ priority assigned to UART7" -#endif - -#if STM32_SERIAL_USE_UART8 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_UART8_PRIORITY) -#error "Invalid IRQ priority assigned to UART8" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief STM32 Serial Driver configuration structure. - * @details An instance of this structure must be passed to @p sdStart() - * in order to configure and start a serial driver operations. - * @note This structure content is architecture dependent, each driver - * implementation defines its own version and the custom static - * initializers. - */ -typedef struct { - /** - * @brief Bit rate. - */ - uint32_t speed; - /* End of the mandatory fields.*/ - /** - * @brief Initialization value for the CR1 register. - */ - uint16_t cr1; - /** - * @brief Initialization value for the CR2 register. - */ - uint16_t cr2; - /** - * @brief Initialization value for the CR3 register. - */ - uint16_t cr3; -} SerialConfig; - -/** - * @brief @p SerialDriver specific data. - */ -#define _serial_driver_data \ - _base_asynchronous_channel_data \ - /* Driver state.*/ \ - sdstate_t state; \ - /* Input queue.*/ \ - input_queue_t iqueue; \ - /* Output queue.*/ \ - output_queue_t oqueue; \ - /* Input circular buffer.*/ \ - uint8_t ib[SERIAL_BUFFERS_SIZE]; \ - /* Output circular buffer.*/ \ - uint8_t ob[SERIAL_BUFFERS_SIZE]; \ - /* End of the mandatory fields.*/ \ - /* Pointer to the USART registers block.*/ \ - USART_TypeDef *usart; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/* - * Extra USARTs definitions here (missing from the ST header file). - */ -#define USART_CR2_STOP1_BITS (0 << 12) /**< @brief CR2 1 stop bit value.*/ -#define USART_CR2_STOP0P5_BITS (1 << 12) /**< @brief CR2 0.5 stop bit value.*/ -#define USART_CR2_STOP2_BITS (2 << 12) /**< @brief CR2 2 stop bit value.*/ -#define USART_CR2_STOP1P5_BITS (3 << 12) /**< @brief CR2 1.5 stop bit value.*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_SERIAL_USE_USART1 && !defined(__DOXYGEN__) -extern SerialDriver SD1; -#endif -#if STM32_SERIAL_USE_USART2 && !defined(__DOXYGEN__) -extern SerialDriver SD2; -#endif -#if STM32_SERIAL_USE_USART3 && !defined(__DOXYGEN__) -extern SerialDriver SD3; -#endif -#if STM32_SERIAL_USE_UART4 && !defined(__DOXYGEN__) -extern SerialDriver SD4; -#endif -#if STM32_SERIAL_USE_UART5 && !defined(__DOXYGEN__) -extern SerialDriver SD5; -#endif -#if STM32_SERIAL_USE_USART6 && !defined(__DOXYGEN__) -extern SerialDriver SD6; -#endif -#if STM32_SERIAL_USE_UART7 && !defined(__DOXYGEN__) -extern SerialDriver SD7; -#endif -#if STM32_SERIAL_USE_UART8 && !defined(__DOXYGEN__) -extern SerialDriver SD8; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void sd_lld_init(void); - void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); - void sd_lld_stop(SerialDriver *sdp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_SERIAL */ - -#endif /* _SERIAL_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/USARTv1/uart_lld.c b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/USARTv1/uart_lld.c deleted file mode 100644 index b15ab94752..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/USARTv1/uart_lld.c +++ /dev/null @@ -1,811 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/USARTv1/uart_lld.c - * @brief STM32 low level UART driver code. - * - * @addtogroup UART - * @{ - */ - -#include "hal.h" - -#if HAL_USE_UART || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define USART1_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_USART1_RX_DMA_STREAM, \ - STM32_USART1_RX_DMA_CHN) - -#define USART1_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_USART1_TX_DMA_STREAM, \ - STM32_USART1_TX_DMA_CHN) - -#define USART2_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_USART2_RX_DMA_STREAM, \ - STM32_USART2_RX_DMA_CHN) - -#define USART2_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_USART2_TX_DMA_STREAM, \ - STM32_USART2_TX_DMA_CHN) - -#define USART3_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_USART3_RX_DMA_STREAM, \ - STM32_USART3_RX_DMA_CHN) - -#define USART3_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_USART3_TX_DMA_STREAM, \ - STM32_USART3_TX_DMA_CHN) - -#define UART4_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_UART4_RX_DMA_STREAM, \ - STM32_UART4_RX_DMA_CHN) - -#define UART4_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_UART4_TX_DMA_STREAM, \ - STM32_UART4_TX_DMA_CHN) - -#define UART5_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_UART5_RX_DMA_STREAM, \ - STM32_UART5_RX_DMA_CHN) - -#define UART5_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_UART5_TX_DMA_STREAM, \ - STM32_UART5_TX_DMA_CHN) - -#define USART6_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_USART6_RX_DMA_STREAM, \ - STM32_USART6_RX_DMA_CHN) - -#define USART6_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_USART6_TX_DMA_STREAM, \ - STM32_USART6_TX_DMA_CHN) - -#define STM32_UART45_CR2_CHECK_MASK \ - (USART_CR2_STOP_0 | USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | \ - USART_CR2_LBCL) - -#define STM32_UART45_CR3_CHECK_MASK \ - (USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | USART_CR3_SCEN | \ - USART_CR3_NACK) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief USART1 UART driver identifier.*/ -#if STM32_UART_USE_USART1 || defined(__DOXYGEN__) -UARTDriver UARTD1; -#endif - -/** @brief USART2 UART driver identifier.*/ -#if STM32_UART_USE_USART2 || defined(__DOXYGEN__) -UARTDriver UARTD2; -#endif - -/** @brief USART3 UART driver identifier.*/ -#if STM32_UART_USE_USART3 || defined(__DOXYGEN__) -UARTDriver UARTD3; -#endif - -/** @brief UART4 UART driver identifier.*/ -#if STM32_UART_USE_UART4 || defined(__DOXYGEN__) -UARTDriver UARTD4; -#endif - -/** @brief UART5 UART driver identifier.*/ -#if STM32_UART_USE_UART5 || defined(__DOXYGEN__) -UARTDriver UARTD5; -#endif - -/** @brief USART6 UART driver identifier.*/ -#if STM32_UART_USE_USART6 || defined(__DOXYGEN__) -UARTDriver UARTD6; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Status bits translation. - * - * @param[in] sr USART SR register value - * - * @return The error flags. - */ -static uartflags_t translate_errors(uint16_t sr) { - uartflags_t sts = 0; - - if (sr & USART_SR_ORE) - sts |= UART_OVERRUN_ERROR; - if (sr & USART_SR_PE) - sts |= UART_PARITY_ERROR; - if (sr & USART_SR_FE) - sts |= UART_FRAMING_ERROR; - if (sr & USART_SR_NE) - sts |= UART_NOISE_ERROR; - if (sr & USART_SR_LBD) - sts |= UART_BREAK_DETECTED; - return sts; -} - -/** - * @brief Puts the receiver in the UART_RX_IDLE state. - * - * @param[in] uartp pointer to the @p UARTDriver object - */ -static void uart_enter_rx_idle_loop(UARTDriver *uartp) { - uint32_t mode; - - /* RX DMA channel preparation, if the char callback is defined then the - TCIE interrupt is enabled too.*/ - if (uartp->config->rxchar_cb == NULL) - mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC; - else - mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC | STM32_DMA_CR_TCIE; - dmaStreamSetMemory0(uartp->dmarx, &uartp->rxbuf); - dmaStreamSetTransactionSize(uartp->dmarx, 1); - dmaStreamSetMode(uartp->dmarx, uartp->dmamode | mode); - dmaStreamEnable(uartp->dmarx); -} - -/** - * @brief USART de-initialization. - * @details This function must be invoked with interrupts disabled. - * - * @param[in] uartp pointer to the @p UARTDriver object - */ -static void usart_stop(UARTDriver *uartp) { - - /* Stops RX and TX DMA channels.*/ - dmaStreamDisable(uartp->dmarx); - dmaStreamDisable(uartp->dmatx); - - /* Stops USART operations.*/ - uartp->usart->CR1 = 0; - uartp->usart->CR2 = 0; - uartp->usart->CR3 = 0; -} - -/** - * @brief USART initialization. - * @details This function must be invoked with interrupts disabled. - * - * @param[in] uartp pointer to the @p UARTDriver object - */ -static void usart_start(UARTDriver *uartp) { - uint16_t cr1; - USART_TypeDef *u = uartp->usart; - - /* Defensive programming, starting from a clean state.*/ - usart_stop(uartp); - - /* Baud rate setting.*/ -#if STM32_HAS_USART6 - if ((uartp->usart == USART1) || (uartp->usart == USART6)) -#else - if (uartp->usart == USART1) -#endif - u->BRR = STM32_PCLK2 / uartp->config->speed; - else - u->BRR = STM32_PCLK1 / uartp->config->speed; - - /* Resetting eventual pending status flags.*/ - (void)u->SR; /* SR reset step 1.*/ - (void)u->DR; /* SR reset step 2.*/ - u->SR = 0; - - /* Note that some bits are enforced because required for correct driver - operations.*/ - u->CR2 = uartp->config->cr2 | USART_CR2_LBDIE; - u->CR3 = uartp->config->cr3 | USART_CR3_DMAT | USART_CR3_DMAR | - USART_CR3_EIE; - - /* Mustn't ever set TCIE here - if done, it causes an immediate - interrupt.*/ - cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE; - u->CR1 = uartp->config->cr1 | cr1; - - /* Starting the receiver idle loop.*/ - uart_enter_rx_idle_loop(uartp); -} - -/** - * @brief RX DMA common service routine. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] flags pre-shifted content of the ISR register - */ -static void uart_lld_serve_rx_end_irq(UARTDriver *uartp, uint32_t flags) { - - /* DMA errors handling.*/ -#if defined(STM32_UART_DMA_ERROR_HOOK) - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - STM32_UART_DMA_ERROR_HOOK(uartp); - } -#else - (void)flags; -#endif - - if (uartp->rxstate == UART_RX_IDLE) { - /* Receiver in idle state, a callback is generated, if enabled, for each - received character and then the driver stays in the same state.*/ - _uart_rx_idle_code(uartp); - } - else { - /* Receiver in active state, a callback is generated, if enabled, after - a completed transfer.*/ - dmaStreamDisable(uartp->dmarx); - _uart_rx_complete_isr_code(uartp); - } -} - -/** - * @brief TX DMA common service routine. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] flags pre-shifted content of the ISR register - */ -static void uart_lld_serve_tx_end_irq(UARTDriver *uartp, uint32_t flags) { - - /* DMA errors handling.*/ -#if defined(STM32_UART_DMA_ERROR_HOOK) - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - STM32_UART_DMA_ERROR_HOOK(uartp); - } -#else - (void)flags; -#endif - - dmaStreamDisable(uartp->dmatx); - - /* A callback is generated, if enabled, after a completed transfer.*/ - _uart_tx1_isr_code(uartp); -} - -/** - * @brief USART common service routine. - * - * @param[in] uartp pointer to the @p UARTDriver object - */ -static void serve_usart_irq(UARTDriver *uartp) { - uint16_t sr; - USART_TypeDef *u = uartp->usart; - uint32_t cr1 = u->CR1; - - sr = u->SR; /* SR reset step 1.*/ - (void)u->DR; /* SR reset step 2.*/ - - if (sr & (USART_SR_LBD | USART_SR_ORE | USART_SR_NE | - USART_SR_FE | USART_SR_PE)) { - u->SR = ~USART_SR_LBD; - _uart_rx_error_isr_code(uartp, translate_errors(sr)); - } - - if ((sr & USART_SR_TC) && (cr1 & USART_CR1_TCIE)) { - /* TC interrupt cleared and disabled.*/ - u->SR = ~USART_SR_TC; - u->CR1 = cr1 & ~USART_CR1_TCIE; - - /* End of transmission, a callback is generated.*/ - _uart_tx2_isr_code(uartp); - } -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if STM32_UART_USE_USART1 || defined(__DOXYGEN__) -#if !defined(STM32_USART1_HANDLER) -#error "STM32_USART1_HANDLER not defined" -#endif -/** - * @brief USART1 IRQ handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_USART1_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - serve_usart_irq(&UARTD1); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_UART_USE_USART1 */ - -#if STM32_UART_USE_USART2 || defined(__DOXYGEN__) -#if !defined(STM32_USART2_HANDLER) -#error "STM32_USART2_HANDLER not defined" -#endif -/** - * @brief USART2 IRQ handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_USART2_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - serve_usart_irq(&UARTD2); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_UART_USE_USART2 */ - -#if STM32_UART_USE_USART3 || defined(__DOXYGEN__) -#if !defined(STM32_USART3_HANDLER) -#error "STM32_USART3_HANDLER not defined" -#endif -/** - * @brief USART3 IRQ handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_USART3_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - serve_usart_irq(&UARTD3); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_UART_USE_USART3 */ - -#if STM32_UART_USE_UART4 || defined(__DOXYGEN__) -#if !defined(STM32_UART4_HANDLER) -#error "STM32_UART4_HANDLER not defined" -#endif -/** - * @brief UART4 IRQ handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_UART4_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - serve_usart_irq(&UARTD4); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_UART_USE_UART4 */ - -#if STM32_UART_USE_UART5 || defined(__DOXYGEN__) -#if !defined(STM32_UART5_HANDLER) -#error "STM32_UART5_HANDLER not defined" -#endif -/** - * @brief UART5 IRQ handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_UART5_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - serve_usart_irq(&UARTD5); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_UART_USE_UART5 */ - -#if STM32_UART_USE_USART6 || defined(__DOXYGEN__) -#if !defined(STM32_USART6_HANDLER) -#error "STM32_USART6_HANDLER not defined" -#endif -/** - * @brief USART6 IRQ handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_USART6_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - serve_usart_irq(&UARTD6); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_UART_USE_USART6 */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level UART driver initialization. - * - * @notapi - */ -void uart_lld_init(void) { - -#if STM32_UART_USE_USART1 - uartObjectInit(&UARTD1); - UARTD1.usart = USART1; - UARTD1.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; - UARTD1.dmarx = STM32_DMA_STREAM(STM32_UART_USART1_RX_DMA_STREAM); - UARTD1.dmatx = STM32_DMA_STREAM(STM32_UART_USART1_TX_DMA_STREAM); -#endif - -#if STM32_UART_USE_USART2 - uartObjectInit(&UARTD2); - UARTD2.usart = USART2; - UARTD2.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; - UARTD2.dmarx = STM32_DMA_STREAM(STM32_UART_USART2_RX_DMA_STREAM); - UARTD2.dmatx = STM32_DMA_STREAM(STM32_UART_USART2_TX_DMA_STREAM); -#endif - -#if STM32_UART_USE_USART3 - uartObjectInit(&UARTD3); - UARTD3.usart = USART3; - UARTD3.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; - UARTD3.dmarx = STM32_DMA_STREAM(STM32_UART_USART3_RX_DMA_STREAM); - UARTD3.dmatx = STM32_DMA_STREAM(STM32_UART_USART3_TX_DMA_STREAM); -#endif - -#if STM32_UART_USE_UART4 - uartObjectInit(&UARTD4); - UARTD4.usart = UART4; - UARTD4.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; - UARTD4.dmarx = STM32_DMA_STREAM(STM32_UART_UART4_RX_DMA_STREAM); - UARTD4.dmatx = STM32_DMA_STREAM(STM32_UART_UART4_TX_DMA_STREAM); -#endif - -#if STM32_UART_USE_UART5 - uartObjectInit(&UARTD5); - UARTD5.usart = UART5; - UARTD5.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; - UARTD5.dmarx = STM32_DMA_STREAM(STM32_UART_UART5_RX_DMA_STREAM); - UARTD5.dmatx = STM32_DMA_STREAM(STM32_UART_UART5_TX_DMA_STREAM); -#endif - -#if STM32_UART_USE_USART6 - uartObjectInit(&UARTD6); - UARTD6.usart = USART6; - UARTD6.dmarx = STM32_DMA_STREAM(STM32_UART_USART6_RX_DMA_STREAM); - UARTD6.dmatx = STM32_DMA_STREAM(STM32_UART_USART6_TX_DMA_STREAM); -#endif -} - -/** - * @brief Configures and activates the UART peripheral. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @notapi - */ -void uart_lld_start(UARTDriver *uartp) { - - if (uartp->state == UART_STOP) { -#if STM32_UART_USE_USART1 - if (&UARTD1 == uartp) { - bool b; - b = dmaStreamAllocate(uartp->dmarx, - STM32_UART_USART1_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, - (void *)uartp); - osalDbgAssert(!b, "stream already allocated"); - b = dmaStreamAllocate(uartp->dmatx, - STM32_UART_USART1_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, - (void *)uartp); - osalDbgAssert(!b, "stream already allocated"); - rccEnableUSART1(FALSE); - nvicEnableVector(STM32_USART1_NUMBER, STM32_UART_USART1_IRQ_PRIORITY); - uartp->dmamode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY); - } -#endif - -#if STM32_UART_USE_USART2 - if (&UARTD2 == uartp) { - bool b; - b = dmaStreamAllocate(uartp->dmarx, - STM32_UART_USART2_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, - (void *)uartp); - osalDbgAssert(!b, "stream already allocated"); - b = dmaStreamAllocate(uartp->dmatx, - STM32_UART_USART2_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, - (void *)uartp); - osalDbgAssert(!b, "stream already allocated"); - rccEnableUSART2(FALSE); - nvicEnableVector(STM32_USART2_NUMBER, STM32_UART_USART2_IRQ_PRIORITY); - uartp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY); - } -#endif - -#if STM32_UART_USE_USART3 - if (&UARTD3 == uartp) { - bool b; - b = dmaStreamAllocate(uartp->dmarx, - STM32_UART_USART3_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, - (void *)uartp); - osalDbgAssert(!b, "stream already allocated"); - b = dmaStreamAllocate(uartp->dmatx, - STM32_UART_USART3_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, - (void *)uartp); - osalDbgAssert(!b, "stream already allocated"); - rccEnableUSART3(FALSE); - nvicEnableVector(STM32_USART3_NUMBER, STM32_UART_USART3_IRQ_PRIORITY); - uartp->dmamode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY); - } -#endif - -#if STM32_UART_USE_UART4 - if (&UARTD4 == uartp) { - bool b; - - chDbgAssert((uartp->config->cr2 & STM32_UART45_CR2_CHECK_MASK) == 0, - "specified invalid bits in UART4 CR2 register settings"); - chDbgAssert((uartp->config->cr3 & STM32_UART45_CR3_CHECK_MASK) == 0, - "specified invalid bits in UART4 CR3 register settings"); - - b = dmaStreamAllocate(uartp->dmarx, - STM32_UART_UART4_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, - (void *)uartp); - osalDbgAssert(!b, "stream already allocated"); - b = dmaStreamAllocate(uartp->dmatx, - STM32_UART_UART4_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, - (void *)uartp); - osalDbgAssert(!b, "stream already allocated"); - rccEnableUART4(FALSE); - nvicEnableVector(STM32_UART4_NUMBER, STM32_UART_UART4_IRQ_PRIORITY); - uartp->dmamode |= STM32_DMA_CR_CHSEL(UART4_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_UART_UART4_DMA_PRIORITY); - } -#endif - -#if STM32_UART_USE_UART5 - if (&UARTD5 == uartp) { - bool b; - - chDbgAssert((uartp->config->cr2 & STM32_UART45_CR2_CHECK_MASK) == 0, - "specified invalid bits in UART5 CR2 register settings"); - chDbgAssert((uartp->config->cr3 & STM32_UART45_CR3_CHECK_MASK) == 0, - "specified invalid bits in UART5 CR3 register settings"); - - b = dmaStreamAllocate(uartp->dmarx, - STM32_UART_UART5_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, - (void *)uartp); - osalDbgAssert(!b, "stream already allocated"); - b = dmaStreamAllocate(uartp->dmatx, - STM32_UART_UART5_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, - (void *)uartp); - osalDbgAssert(!b, "stream already allocated"); - rccEnableUART5(FALSE); - nvicEnableVector(STM32_UART5_NUMBER, STM32_UART_UART5_IRQ_PRIORITY); - uartp->dmamode |= STM32_DMA_CR_CHSEL(UART5_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_UART_UART5_DMA_PRIORITY); - } -#endif - -#if STM32_UART_USE_USART6 - if (&UARTD6 == uartp) { - bool b; - b = dmaStreamAllocate(uartp->dmarx, - STM32_UART_USART6_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, - (void *)uartp); - osalDbgAssert(!b, "stream already allocated"); - b = dmaStreamAllocate(uartp->dmatx, - STM32_UART_USART6_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, - (void *)uartp); - osalDbgAssert(!b, "stream already allocated"); - rccEnableUSART6(FALSE); - nvicEnableVector(STM32_USART6_NUMBER, STM32_UART_USART6_IRQ_PRIORITY); - uartp->dmamode |= STM32_DMA_CR_CHSEL(USART6_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_UART_USART6_DMA_PRIORITY); - } -#endif - - /* Static DMA setup, the transfer size depends on the USART settings, - it is 16 bits if M=1 and PCE=0 else it is 8 bits.*/ - if ((uartp->config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M) - uartp->dmamode |= STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; - dmaStreamSetPeripheral(uartp->dmarx, &uartp->usart->DR); - dmaStreamSetPeripheral(uartp->dmatx, &uartp->usart->DR); - uartp->rxbuf = 0; - } - - uartp->rxstate = UART_RX_IDLE; - uartp->txstate = UART_TX_IDLE; - usart_start(uartp); -} - -/** - * @brief Deactivates the UART peripheral. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @notapi - */ -void uart_lld_stop(UARTDriver *uartp) { - - if (uartp->state == UART_READY) { - usart_stop(uartp); - dmaStreamRelease(uartp->dmarx); - dmaStreamRelease(uartp->dmatx); - -#if STM32_UART_USE_USART1 - if (&UARTD1 == uartp) { - nvicDisableVector(STM32_USART1_NUMBER); - rccDisableUSART1(FALSE); - return; - } -#endif - -#if STM32_UART_USE_USART2 - if (&UARTD2 == uartp) { - nvicDisableVector(STM32_USART2_NUMBER); - rccDisableUSART2(FALSE); - return; - } -#endif - -#if STM32_UART_USE_USART3 - if (&UARTD3 == uartp) { - nvicDisableVector(STM32_USART3_NUMBER); - rccDisableUSART3(FALSE); - return; - } -#endif - -#if STM32_UART_USE_UART4 - if (&UARTD4 == uartp) { - nvicDisableVector(STM32_UART4_NUMBER); - rccDisableUART4(FALSE); - return; - } -#endif - -#if STM32_UART_USE_UART5 - if (&UARTD5 == uartp) { - nvicDisableVector(STM32_UART5_NUMBER); - rccDisableUART5(FALSE); - return; - } -#endif - -#if STM32_UART_USE_USART6 - if (&UARTD6 == uartp) { - nvicDisableVector(STM32_USART6_NUMBER); - rccDisableUSART6(FALSE); - return; - } -#endif - } -} - -/** - * @brief Starts a transmission on the UART peripheral. - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] n number of data frames to send - * @param[in] txbuf the pointer to the transmit buffer - * - * @notapi - */ -void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) { - - /* TX DMA channel preparation.*/ - dmaStreamSetMemory0(uartp->dmatx, txbuf); - dmaStreamSetTransactionSize(uartp->dmatx, n); - dmaStreamSetMode(uartp->dmatx, uartp->dmamode | STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE); - - /* Only enable TC interrupt if there's a callback attached to it. - Also we need to clear TC flag which could be set before. */ - if (uartp->config->txend2_cb != NULL) { - uartp->usart->SR = ~USART_SR_TC; - uartp->usart->CR1 |= USART_CR1_TCIE; - } - - /* Starting transfer.*/ - dmaStreamEnable(uartp->dmatx); -} - -/** - * @brief Stops any ongoing transmission. - * @note Stopping a transmission also suppresses the transmission callbacks. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @return The number of data frames not transmitted by the - * stopped transmit operation. - * - * @notapi - */ -size_t uart_lld_stop_send(UARTDriver *uartp) { - - dmaStreamDisable(uartp->dmatx); - - return dmaStreamGetTransactionSize(uartp->dmatx); -} - -/** - * @brief Starts a receive operation on the UART peripheral. - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] n number of data frames to send - * @param[out] rxbuf the pointer to the receive buffer - * - * @notapi - */ -void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) { - - /* Stopping previous activity (idle state).*/ - dmaStreamDisable(uartp->dmarx); - - /* RX DMA channel preparation.*/ - dmaStreamSetMemory0(uartp->dmarx, rxbuf); - dmaStreamSetTransactionSize(uartp->dmarx, n); - dmaStreamSetMode(uartp->dmarx, uartp->dmamode | STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE); - - /* Starting transfer.*/ - dmaStreamEnable(uartp->dmarx); -} - -/** - * @brief Stops any ongoing receive operation. - * @note Stopping a receive operation also suppresses the receive callbacks. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @return The number of data frames not received by the - * stopped receive operation. - * - * @notapi - */ -size_t uart_lld_stop_receive(UARTDriver *uartp) { - size_t n; - - dmaStreamDisable(uartp->dmarx); - n = dmaStreamGetTransactionSize(uartp->dmarx); - uart_enter_rx_idle_loop(uartp); - - return n; -} - -#endif /* HAL_USE_UART */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/USARTv1/uart_lld.h b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/USARTv1/uart_lld.h deleted file mode 100644 index f073263f23..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/USARTv1/uart_lld.h +++ /dev/null @@ -1,623 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/USARTv1/uart_lld.h - * @brief STM32 low level UART driver header. - * - * @addtogroup UART - * @{ - */ - -#ifndef _UART_LLD_H_ -#define _UART_LLD_H_ - -#if HAL_USE_UART || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief UART driver on USART1 enable switch. - * @details If set to @p TRUE the support for USART1 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_UART_USE_USART1) || defined(__DOXYGEN__) -#define STM32_UART_USE_USART1 FALSE -#endif - -/** - * @brief UART driver on USART2 enable switch. - * @details If set to @p TRUE the support for USART2 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_UART_USE_USART2) || defined(__DOXYGEN__) -#define STM32_UART_USE_USART2 FALSE -#endif - -/** - * @brief UART driver on USART3 enable switch. - * @details If set to @p TRUE the support for USART3 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_UART_USE_USART3) || defined(__DOXYGEN__) -#define STM32_UART_USE_USART3 FALSE -#endif - -/** - * @brief UART driver on UART4 enable switch. - * @details If set to @p TRUE the support for UART4 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_UART_USE_UART4) || defined(__DOXYGEN__) -#define STM32_UART_USE_UART4 FALSE -#endif - -/** - * @brief UART driver on UART5 enable switch. - * @details If set to @p TRUE the support for UART5 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_UART_USE_UART5) || defined(__DOXYGEN__) -#define STM32_UART_USE_UART5 FALSE -#endif - -/** - * @brief UART driver on USART6 enable switch. - * @details If set to @p TRUE the support for USART6 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_UART_USE_USART6) || defined(__DOXYGEN__) -#define STM32_UART_USE_USART6 FALSE -#endif - -/** - * @brief USART1 interrupt priority level setting. - */ -#if !defined(STM32_UART_USART1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART1_IRQ_PRIORITY 12 -#endif - -/** - * @brief USART2 interrupt priority level setting. - */ -#if !defined(STM32_UART_USART2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART2_IRQ_PRIORITY 12 -#endif - -/** - * @brief USART3 interrupt priority level setting. - */ -#if !defined(STM32_UART_USART3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART3_IRQ_PRIORITY 12 -#endif - -/** - * @brief UART4 interrupt priority level setting. - */ -#if !defined(STM32_UART_UART4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_UART4_IRQ_PRIORITY 12 -#endif - -/** - * @brief UART5 interrupt priority level setting. - */ -#if !defined(STM32_UART_UART5_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_UART5_IRQ_PRIORITY 12 -#endif - -/** - * @brief USART6 interrupt priority level setting. - */ -#if !defined(STM32_UART_USART6_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART6_IRQ_PRIORITY 12 -#endif - -/** - * @brief USART1 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA channels but - * because of the channels ordering the RX channel has always priority - * over the TX channel. - */ -#if !defined(STM32_UART_USART1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART1_DMA_PRIORITY 0 -#endif - -/** - * @brief USART2 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA channels but - * because of the channels ordering the RX channel has always priority - * over the TX channel. - */ -#if !defined(STM32_UART_USART2_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART2_DMA_PRIORITY 0 -#endif - -/** - * @brief USART3 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA channels but - * because of the channels ordering the RX channel has always priority - * over the TX channel. - */ -#if !defined(STM32_UART_USART3_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART3_DMA_PRIORITY 0 -#endif - -/** - * @brief UART4 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA channels but - * because of the channels ordering the RX channel has always priority - * over the TX channel. - */ -#if !defined(STM32_UART_UART4_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_UART4_DMA_PRIORITY 0 -#endif - -/** - * @brief UART5 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA channels but - * because of the channels ordering the RX channel has always priority - * over the TX channel. - */ -#if !defined(STM32_UART_UART5_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_UART5_DMA_PRIORITY 0 -#endif - -/** - * @brief USART6 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA channels but - * because of the channels ordering the RX channel has always priority - * over the TX channel. - */ -#if !defined(STM32_UART_USART6_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART6_DMA_PRIORITY 0 -#endif - -/** - * @brief USART DMA error hook. - * @note The default action for DMA errors is a system halt because DMA - * error can only happen because programming errors. - */ -#if !defined(STM32_UART_DMA_ERROR_HOOK) || defined(__DOXYGEN__) -#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_UART_USE_USART1 && !STM32_HAS_USART1 -#error "USART1 not present in the selected device" -#endif - -#if STM32_UART_USE_USART2 && !STM32_HAS_USART2 -#error "USART2 not present in the selected device" -#endif - -#if STM32_UART_USE_USART3 && !STM32_HAS_USART3 -#error "USART3 not present in the selected device" -#endif - -#if STM32_UART_USE_UART4 -#if !STM32_HAS_UART4 -#error "UART4 not present in the selected device" -#endif - -#if !defined(STM32F2XX) && !defined(STM32F4XX) -#error "UART4 DMA access not supported in this platform" -#endif -#endif /* STM32_UART_USE_UART4 */ - -#if STM32_UART_USE_UART5 -#if !STM32_HAS_UART5 -#error "UART5 not present in the selected device" -#endif - -#if !defined(STM32F2XX) && !defined(STM32F4XX) -#error "UART5 DMA access not supported in this platform" -#endif -#endif /* STM32_UART_USE_UART5 */ - -#if STM32_UART_USE_USART6 && !STM32_HAS_USART6 -#error "USART6 not present in the selected device" -#endif - -#if !STM32_UART_USE_USART1 && !STM32_UART_USE_USART2 && \ - !STM32_UART_USE_USART3 && !STM32_UART_USE_UART4 && \ - !STM32_UART_USE_UART5 && !STM32_UART_USE_USART6 -#error "UART driver activated but no USART/UART peripheral assigned" -#endif - -#if STM32_UART_USE_USART1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_USART1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to USART1" -#endif - -#if STM32_UART_USE_USART2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_USART2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to USART2" -#endif - -#if STM32_UART_USE_USART3 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_USART3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to USART3" -#endif - -#if STM32_UART_USE_UART4 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_UART4_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to UART4" -#endif - -#if STM32_UART_USE_UART5 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_UART5_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to UART5" -#endif - -#if STM32_UART_USE_USART6 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_USART6_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to USART6" -#endif - -#if STM32_UART_USE_USART1 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART1_DMA_PRIORITY) -#error "Invalid DMA priority assigned to USART1" -#endif - -#if STM32_UART_USE_USART2 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART2_DMA_PRIORITY) -#error "Invalid DMA priority assigned to USART2" -#endif - -#if STM32_UART_USE_USART3 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART3_DMA_PRIORITY) -#error "Invalid DMA priority assigned to USART3" -#endif - -#if STM32_UART_USE_UART4 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_UART4_DMA_PRIORITY) -#error "Invalid DMA priority assigned to UART4" -#endif - -#if STM32_UART_USE_UART5 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_UART5_DMA_PRIORITY) -#error "Invalid DMA priority assigned to UART5" -#endif - -#if STM32_UART_USE_USART6 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART6_DMA_PRIORITY) -#error "Invalid DMA priority assigned to USART6" -#endif - -/* The following checks are only required when there is a DMA able to - reassign streams to different channels.*/ -#if STM32_ADVANCED_DMA -/* Check on the presence of the DMA streams settings in mcuconf.h.*/ -#if STM32_UART_USE_USART1 && (!defined(STM32_UART_USART1_RX_DMA_STREAM) || \ - !defined(STM32_UART_USART1_TX_DMA_STREAM)) -#error "USART1 DMA streams not defined" -#endif - -#if STM32_UART_USE_USART2 && (!defined(STM32_UART_USART2_RX_DMA_STREAM) || \ - !defined(STM32_UART_USART2_TX_DMA_STREAM)) -#error "USART2 DMA streams not defined" -#endif - -#if STM32_UART_USE_USART3 && (!defined(STM32_UART_USART3_RX_DMA_STREAM) || \ - !defined(STM32_UART_USART3_TX_DMA_STREAM)) -#error "USART3 DMA streams not defined" -#endif - -#if STM32_UART_USE_UART4 && (!defined(STM32_UART_UART4_RX_DMA_STREAM) || \ - !defined(STM32_UART_UART4_TX_DMA_STREAM)) -#error "UART4 DMA streams not defined" -#endif - -#if STM32_UART_USE_UART5 && (!defined(STM32_UART_UART5_RX_DMA_STREAM) || \ - !defined(STM32_UART_UART5_TX_DMA_STREAM)) -#error "UART5 DMA streams not defined" -#endif - -#if STM32_UART_USE_USART6 && (!defined(STM32_UART_USART6_RX_DMA_STREAM) || \ - !defined(STM32_UART_USART6_TX_DMA_STREAM)) -#error "USART6 DMA streams not defined" -#endif - -/* Check on the validity of the assigned DMA channels.*/ -#if STM32_UART_USE_USART1 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_USART1_RX_DMA_STREAM, \ - STM32_USART1_RX_DMA_MSK) -#error "invalid DMA stream associated to USART1 RX" -#endif - -#if STM32_UART_USE_USART1 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_USART1_TX_DMA_STREAM, \ - STM32_USART1_TX_DMA_MSK) -#error "invalid DMA stream associated to USART1 TX" -#endif - -#if STM32_UART_USE_USART2 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_USART2_RX_DMA_STREAM, \ - STM32_USART2_RX_DMA_MSK) -#error "invalid DMA stream associated to USART2 RX" -#endif - -#if STM32_UART_USE_USART2 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_USART2_TX_DMA_STREAM, \ - STM32_USART2_TX_DMA_MSK) -#error "invalid DMA stream associated to USART2 TX" -#endif - -#if STM32_UART_USE_USART3 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_USART3_RX_DMA_STREAM, \ - STM32_USART3_RX_DMA_MSK) -#error "invalid DMA stream associated to USART3 RX" -#endif - -#if STM32_UART_USE_USART3 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_USART3_TX_DMA_STREAM, \ - STM32_USART3_TX_DMA_MSK) -#error "invalid DMA stream associated to USART3 TX" -#endif - -#if STM32_UART_USE_UART4 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_UART4_RX_DMA_STREAM, \ - STM32_UART4_RX_DMA_MSK) -#error "invalid DMA stream associated to UART4 RX" -#endif - -#if STM32_UART_USE_UART4 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_UART4_TX_DMA_STREAM, \ - STM32_UART4_TX_DMA_MSK) -#error "invalid DMA stream associated to UART4 TX" -#endif - -#if STM32_UART_USE_UART5 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_UART5_RX_DMA_STREAM, \ - STM32_UART5_RX_DMA_MSK) -#error "invalid DMA stream associated to UART5 RX" -#endif - -#if STM32_UART_USE_UART5 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_UART5_TX_DMA_STREAM, \ - STM32_UART5_TX_DMA_MSK) -#error "invalid DMA stream associated to UART5 TX" -#endif - -#if STM32_UART_USE_USART6 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_USART6_RX_DMA_STREAM, \ - STM32_USART6_RX_DMA_MSK) -#error "invalid DMA stream associated to USART6 RX" -#endif - -#if STM32_UART_USE_USART6 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_USART6_TX_DMA_STREAM, \ - STM32_USART6_TX_DMA_MSK) -#error "invalid DMA stream associated to USART6 TX" -#endif -#endif /* STM32_ADVANCED_DMA */ - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief UART driver condition flags type. - */ -typedef uint32_t uartflags_t; - -/** - * @brief Structure representing an UART driver. - */ -typedef struct UARTDriver UARTDriver; - -/** - * @brief Generic UART notification callback type. - * - * @param[in] uartp pointer to the @p UARTDriver object - */ -typedef void (*uartcb_t)(UARTDriver *uartp); - -/** - * @brief Character received UART notification callback type. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] c received character - */ -typedef void (*uartccb_t)(UARTDriver *uartp, uint16_t c); - -/** - * @brief Receive error UART notification callback type. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] e receive error mask - */ -typedef void (*uartecb_t)(UARTDriver *uartp, uartflags_t e); - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief End of transmission buffer callback. - */ - uartcb_t txend1_cb; - /** - * @brief Physical end of transmission callback. - */ - uartcb_t txend2_cb; - /** - * @brief Receive buffer filled callback. - */ - uartcb_t rxend_cb; - /** - * @brief Character received while out if the @p UART_RECEIVE state. - */ - uartccb_t rxchar_cb; - /** - * @brief Receive error callback. - */ - uartecb_t rxerr_cb; - /* End of the mandatory fields.*/ - /** - * @brief Bit rate. - */ - uint32_t speed; - /** - * @brief Initialization value for the CR1 register. - */ - uint16_t cr1; - /** - * @brief Initialization value for the CR2 register. - */ - uint16_t cr2; - /** - * @brief Initialization value for the CR3 register. - */ - uint16_t cr3; -} UARTConfig; - -/** - * @brief Structure representing an UART driver. - */ -struct UARTDriver { - /** - * @brief Driver state. - */ - uartstate_t state; - /** - * @brief Transmitter state. - */ - uarttxstate_t txstate; - /** - * @brief Receiver state. - */ - uartrxstate_t rxstate; - /** - * @brief Current configuration data. - */ - const UARTConfig *config; -#if (UART_USE_WAIT == TRUE) || defined(__DOXYGEN__) - /** - * @brief Synchronization flag for transmit operations. - */ - bool early; - /** - * @brief Waiting thread on RX. - */ - thread_reference_t threadrx; - /** - * @brief Waiting thread on TX. - */ - thread_reference_t threadtx; -#endif /* UART_USE_WAIT */ -#if (UART_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the peripheral. - */ - mutex_t mutex; -#endif /* UART_USE_MUTUAL_EXCLUSION */ -#if defined(UART_DRIVER_EXT_FIELDS) - UART_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the USART registers block. - */ - USART_TypeDef *usart; - /** - * @brief DMA mode bit mask. - */ - uint32_t dmamode; - /** - * @brief Receive DMA channel. - */ - const stm32_dma_stream_t *dmarx; - /** - * @brief Transmit DMA channel. - */ - const stm32_dma_stream_t *dmatx; - /** - * @brief Default receive buffer while into @p UART_RX_IDLE state. - */ - volatile uint16_t rxbuf; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_UART_USE_USART1 && !defined(__DOXYGEN__) -extern UARTDriver UARTD1; -#endif - -#if STM32_UART_USE_USART2 && !defined(__DOXYGEN__) -extern UARTDriver UARTD2; -#endif - -#if STM32_UART_USE_USART3 && !defined(__DOXYGEN__) -extern UARTDriver UARTD3; -#endif - -#if STM32_UART_USE_UART4 && !defined(__DOXYGEN__) -extern UARTDriver UARTD4; -#endif - -#if STM32_UART_USE_UART5 && !defined(__DOXYGEN__) -extern UARTDriver UARTD5; -#endif - -#if STM32_UART_USE_USART6 && !defined(__DOXYGEN__) -extern UARTDriver UARTD6; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void uart_lld_init(void); - void uart_lld_start(UARTDriver *uartp); - void uart_lld_stop(UARTDriver *uartp); - void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf); - size_t uart_lld_stop_send(UARTDriver *uartp); - void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf); - size_t uart_lld_stop_receive(UARTDriver *uartp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_UART */ - -#endif /* _UART_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/USARTv2/serial_lld.c b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/USARTv2/serial_lld.c deleted file mode 100644 index ea223aea50..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/USARTv2/serial_lld.c +++ /dev/null @@ -1,764 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/USARTv2/serial_lld.c - * @brief STM32 low level serial driver code. - * - * @addtogroup SERIAL - * @{ - */ - -#include "hal.h" - -#if HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/* For compatibility for those devices without LIN support in the USARTs.*/ -#if !defined(USART_ISR_LBDF) -#define USART_ISR_LBDF 0 -#endif - -#if !defined(USART_CR2_LBDIE) -#define USART_CR2_LBDIE 0 -#endif - -/* STM32L0xx/STM32F7xx ST headers difference.*/ -#if !defined(USART_ISR_LBDF) -#define USART_ISR_LBDF USART_ISR_LBD -#endif - -/* Handling the case where UART4 and UART5 are actually USARTs, this happens - in the STM32F0xx.*/ -#if defined(USART4) -#define UART4 USART4 -#endif - -#if defined(USART5) -#define UART5 USART5 -#endif - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief USART1 serial driver identifier.*/ -#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__) -SerialDriver SD1; -#endif - -/** @brief USART2 serial driver identifier.*/ -#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__) -SerialDriver SD2; -#endif - -/** @brief USART3 serial driver identifier.*/ -#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__) -SerialDriver SD3; -#endif - -/** @brief UART4 serial driver identifier.*/ -#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__) -SerialDriver SD4; -#endif - -/** @brief UART5 serial driver identifier.*/ -#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__) -SerialDriver SD5; -#endif - -/** @brief USART6 serial driver identifier.*/ -#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__) -SerialDriver SD6; -#endif - -/** @brief UART7 serial driver identifier.*/ -#if STM32_SERIAL_USE_UART7 || defined(__DOXYGEN__) -SerialDriver SD7; -#endif - -/** @brief UART8 serial driver identifier.*/ -#if STM32_SERIAL_USE_UART8 || defined(__DOXYGEN__) -SerialDriver SD8; -#endif - -/** @brief LPUART1 serial driver identifier.*/ -#if STM32_SERIAL_USE_LPUART1 || defined(__DOXYGEN__) -SerialDriver LPSD1; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** @brief Driver default configuration.*/ -static const SerialConfig default_config = -{ - SERIAL_DEFAULT_BITRATE, - 0, - USART_CR2_STOP1_BITS | USART_CR2_LINEN, - 0 -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief USART initialization. - * @details This function must be invoked with interrupts disabled. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] config the architecture-dependent serial driver configuration - */ -static void usart_init(SerialDriver *sdp, const SerialConfig *config) { - USART_TypeDef *u = sdp->usart; - - /* Baud rate setting.*/ -#if STM32_SERIAL_USE_LPUART1 - if ( sdp == &LPSD1 ) - { - u->BRR = (uint32_t)( ( (uint64_t)sdp->clock * 256 ) / config->speed); - } - else -#endif - u->BRR = (uint32_t)(sdp->clock / config->speed); - - /* Note that some bits are enforced.*/ - u->CR2 = config->cr2 | USART_CR2_LBDIE; - u->CR3 = config->cr3 | USART_CR3_EIE; - u->CR1 = config->cr1 | USART_CR1_UE | USART_CR1_PEIE | - USART_CR1_RXNEIE | USART_CR1_TE | - USART_CR1_RE; - u->ICR = 0xFFFFFFFFU; -} - -/** - * @brief USART de-initialization. - * @details This function must be invoked with interrupts disabled. - * - * @param[in] u pointer to an USART I/O block - */ -static void usart_deinit(USART_TypeDef *u) { - - u->CR1 = 0; - u->CR2 = 0; - u->CR3 = 0; -} - -/** - * @brief Error handling routine. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] isr USART ISR register value - */ -static void set_error(SerialDriver *sdp, uint32_t isr) { - eventflags_t sts = 0; - - if (isr & USART_ISR_ORE) - sts |= SD_OVERRUN_ERROR; - if (isr & USART_ISR_PE) - sts |= SD_PARITY_ERROR; - if (isr & USART_ISR_FE) - sts |= SD_FRAMING_ERROR; - if (isr & USART_ISR_NE) - sts |= SD_NOISE_ERROR; - osalSysLockFromISR(); - chnAddFlagsI(sdp, sts); - osalSysUnlockFromISR(); -} - -/** - * @brief Common IRQ handler. - * - * @param[in] sdp communication channel associated to the USART - */ -static void serve_interrupt(SerialDriver *sdp) { - USART_TypeDef *u = sdp->usart; - uint32_t cr1 = u->CR1; - uint32_t isr; - - /* Reading and clearing status.*/ - isr = u->ISR; - u->ICR = isr; - - /* Error condition detection.*/ - if (isr & (USART_ISR_ORE | USART_ISR_NE | USART_ISR_FE | USART_ISR_PE)) - set_error(sdp, isr); - - /* Special case, LIN break detection.*/ - if (isr & USART_ISR_LBDF) { - osalSysLockFromISR(); - chnAddFlagsI(sdp, SD_BREAK_DETECTED); - osalSysUnlockFromISR(); - } - - /* Data available.*/ - if (isr & USART_ISR_RXNE) { - osalSysLockFromISR(); - sdIncomingDataI(sdp, (uint8_t)u->RDR); - osalSysUnlockFromISR(); - } - - /* Transmission buffer empty.*/ - if ((cr1 & USART_CR1_TXEIE) && (isr & USART_ISR_TXE)) { - msg_t b; - osalSysLockFromISR(); - b = oqGetI(&sdp->oqueue); - if (b < Q_OK) { - chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); - u->CR1 = (cr1 & ~USART_CR1_TXEIE) | USART_CR1_TCIE; - } - else - u->TDR = b; - osalSysUnlockFromISR(); - } - - /* Physical transmission end.*/ - if (isr & USART_ISR_TC) { - osalSysLockFromISR(); - if (oqIsEmptyI(&sdp->oqueue)) - chnAddFlagsI(sdp, CHN_TRANSMISSION_END); - u->CR1 = cr1 & ~USART_CR1_TCIE; - osalSysUnlockFromISR(); - } -} - -#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__) -static void notify1(io_queue_t *qp) { - - (void)qp; - USART1->CR1 |= USART_CR1_TXEIE; -} -#endif - -#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__) -static void notify2(io_queue_t *qp) { - - (void)qp; - USART2->CR1 |= USART_CR1_TXEIE; -} -#endif - -#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__) -static void notify3(io_queue_t *qp) { - - (void)qp; - USART3->CR1 |= USART_CR1_TXEIE; -} -#endif - -#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__) -static void notify4(io_queue_t *qp) { - - (void)qp; - UART4->CR1 |= USART_CR1_TXEIE; -} -#endif - -#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__) -static void notify5(io_queue_t *qp) { - - (void)qp; - UART5->CR1 |= USART_CR1_TXEIE; -} -#endif - -#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__) -static void notify6(io_queue_t *qp) { - - (void)qp; - USART6->CR1 |= USART_CR1_TXEIE; -} -#endif - -#if STM32_SERIAL_USE_UART7 || defined(__DOXYGEN__) -static void notify7(io_queue_t *qp) { - - (void)qp; - UART7->CR1 |= USART_CR1_TXEIE; -} -#endif - -#if STM32_SERIAL_USE_UART8 || defined(__DOXYGEN__) -static void notify8(io_queue_t *qp) { - - (void)qp; - UART8->CR1 |= USART_CR1_TXEIE; -} -#endif - -#if STM32_SERIAL_USE_LPUART1 || defined(__DOXYGEN__) -static void notifylp1(io_queue_t *qp) { - - (void)qp; - LPUART1->CR1 |= USART_CR1_TXEIE; -} -#endif - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__) -#if !defined(STM32_USART1_HANDLER) -#error "STM32_USART1_HANDLER not defined" -#endif -/** - * @brief USART1 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_USART1_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - serve_interrupt(&SD1); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__) -#if !defined(STM32_USART2_HANDLER) -#error "STM32_USART2_HANDLER not defined" -#endif -/** - * @brief USART2 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_USART2_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - serve_interrupt(&SD2); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if defined(STM32_USART3_8_HANDLER) -#if STM32_SERIAL_USE_USART3 || STM32_SERIAL_USE_UART4 || \ - STM32_SERIAL_USE_UART5 || STM32_SERIAL_USE_USART6 || \ - STM32_SERIAL_USE_UART7 || STM32_SERIAL_USE_UART8 || defined(__DOXYGEN__) -/** - * @brief USART3..8 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_USART3_8_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - -#if STM32_SERIAL_USE_USART3 - serve_interrupt(&SD3); -#endif -#if STM32_SERIAL_USE_UART4 - serve_interrupt(&SD4); -#endif -#if STM32_SERIAL_USE_UART5 - serve_interrupt(&SD5); -#endif -#if STM32_SERIAL_USE_USART6 - serve_interrupt(&SD6); -#endif - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#else /* !defined(STM32_USART3_8_HANDLER) */ - -#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__) -#if !defined(STM32_USART3_HANDLER) -#error "STM32_USART3_HANDLER not defined" -#endif -/** - * @brief USART3 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_USART3_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - serve_interrupt(&SD3); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__) -#if !defined(STM32_UART4_HANDLER) -#error "STM32_UART4_HANDLER not defined" -#endif -/** - * @brief UART4 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_UART4_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - serve_interrupt(&SD4); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__) -#if !defined(STM32_UART5_HANDLER) -#error "STM32_UART5_HANDLER not defined" -#endif -/** - * @brief UART5 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_UART5_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - serve_interrupt(&SD5); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__) -#if !defined(STM32_USART6_HANDLER) -#error "STM32_USART6_HANDLER not defined" -#endif -/** - * @brief USART6 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_USART6_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - serve_interrupt(&SD6); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#endif /* !defined(STM32_USART3_8_HANDLER) */ - -#if STM32_SERIAL_USE_UART7 || defined(__DOXYGEN__) -#if !defined(STM32_UART7_HANDLER) -#error "STM32_UART7_HANDLER not defined" -#endif -/** - * @brief UART7 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_UART7_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - serve_interrupt(&SD7); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if STM32_SERIAL_USE_UART8 || defined(__DOXYGEN__) -#if !defined(STM32_UART8_HANDLER) -#error "STM32_UART8_HANDLER not defined" -#endif -/** - * @brief UART8 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_UART8_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - serve_interrupt(&SD8); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if STM32_SERIAL_USE_LPUART1 || defined(__DOXYGEN__) -#if !defined(STM32_LPUART1_HANDLER) -#error "STM32_LPUART1_HANDLER not defined" -#endif -/** - * @brief LPUART1 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_LPUART1_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - serve_interrupt(&LPSD1); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level serial driver initialization. - * - * @notapi - */ -void sd_lld_init(void) { - -#if STM32_SERIAL_USE_USART1 - sdObjectInit(&SD1, NULL, notify1); - SD1.usart = USART1; - SD1.clock = STM32_USART1CLK; -#if defined(STM32_USART1_NUMBER) - nvicEnableVector(STM32_USART1_NUMBER, STM32_SERIAL_USART1_PRIORITY); -#endif -#endif - -#if STM32_SERIAL_USE_USART2 - sdObjectInit(&SD2, NULL, notify2); - SD2.usart = USART2; - SD2.clock = STM32_USART2CLK; -#if defined(STM32_USART2_NUMBER) - nvicEnableVector(STM32_USART2_NUMBER, STM32_SERIAL_USART2_PRIORITY); -#endif -#endif - -#if STM32_SERIAL_USE_USART3 - sdObjectInit(&SD3, NULL, notify3); - SD3.usart = USART3; - SD3.clock = STM32_USART3CLK; -#if defined(STM32_USART3_NUMBER) - nvicEnableVector(STM32_USART3_NUMBER, STM32_SERIAL_USART3_PRIORITY); -#endif -#endif - -#if STM32_SERIAL_USE_UART4 - sdObjectInit(&SD4, NULL, notify4); - SD4.usart = UART4; - SD4.clock = STM32_UART4CLK; -#if defined(STM32_UART4_NUMBER) - nvicEnableVector(STM32_UART4_NUMBER, STM32_SERIAL_UART4_PRIORITY); -#endif -#endif - -#if STM32_SERIAL_USE_UART5 - sdObjectInit(&SD5, NULL, notify5); - SD5.usart = UART5; - SD5.clock = STM32_UART5CLK; -#if defined(STM32_UART5_NUMBER) - nvicEnableVector(STM32_UART5_NUMBER, STM32_SERIAL_UART5_PRIORITY); -#endif -#endif - -#if STM32_SERIAL_USE_USART6 - sdObjectInit(&SD6, NULL, notify6); - SD6.usart = USART6; - SD6.clock = STM32_USART6CLK; -#if defined(STM32_USART6_NUMBER) - nvicEnableVector(STM32_USART6_NUMBER, STM32_SERIAL_USART6_PRIORITY); -#endif -#endif - -#if STM32_SERIAL_USE_UART7 - sdObjectInit(&SD7, NULL, notify7); - SD7.usart = UART7; - SD7.clock = STM32_UART7CLK; -#if defined(STM32_UART7_NUMBER) - nvicEnableVector(STM32_UART7_NUMBER, STM32_SERIAL_UART7_PRIORITY); -#endif -#endif - -#if STM32_SERIAL_USE_UART8 - sdObjectInit(&SD8, NULL, notify8); - SD8.usart = UART8; - SD8.clock = STM32_UART8CLK; -#if defined(STM32_UART8_NUMBER) - nvicEnableVector(STM32_UART8_NUMBER, STM32_SERIAL_UART8_PRIORITY); -#endif -#endif - -#if STM32_SERIAL_USE_LPUART1 - sdObjectInit(&LPSD1, NULL, notifylp1); - LPSD1.usart = LPUART1; - LPSD1.clock = STM32_LPUART1CLK; -#if defined(STM32_LPUART1_NUMBER) - nvicEnableVector(STM32_LPUART1_NUMBER, STM32_SERIAL_LPUART1_PRIORITY); -#endif -#endif - -#if STM32_SERIAL_USE_USART3 || STM32_SERIAL_USE_UART4 || \ - STM32_SERIAL_USE_UART5 || STM32_SERIAL_USE_USART6 || \ - STM32_SERIAL_USE_UART7 || STM32_SERIAL_USE_UART8 || defined(__DOXYGEN__) -#if defined(STM32_USART3_8_HANDLER) - nvicEnableVector(STM32_USART3_8_NUMBER, STM32_SERIAL_USART3_8_PRIORITY); -#endif -#endif -} - -/** - * @brief Low level serial driver configuration and (re)start. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] config the architecture-dependent serial driver configuration. - * If this parameter is set to @p NULL then a default - * configuration is used. - * - * @notapi - */ -void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { - - if (config == NULL) - config = &default_config; - - if (sdp->state == SD_STOP) { -#if STM32_SERIAL_USE_USART1 - if (&SD1 == sdp) { - rccEnableUSART1(FALSE); - } -#endif -#if STM32_SERIAL_USE_USART2 - if (&SD2 == sdp) { - rccEnableUSART2(FALSE); - } -#endif -#if STM32_SERIAL_USE_USART3 - if (&SD3 == sdp) { - rccEnableUSART3(FALSE); - } -#endif -#if STM32_SERIAL_USE_UART4 - if (&SD4 == sdp) { - rccEnableUART4(FALSE); - } -#endif -#if STM32_SERIAL_USE_UART5 - if (&SD5 == sdp) { - rccEnableUART5(FALSE); - } -#endif -#if STM32_SERIAL_USE_USART6 - if (&SD6 == sdp) { - rccEnableUSART6(FALSE); - } -#endif -#if STM32_SERIAL_USE_UART7 - if (&SD7 == sdp) { - rccEnableUART7(FALSE); - } -#endif -#if STM32_SERIAL_USE_UART8 - if (&SD8 == sdp) { - rccEnableUART8(FALSE); - } -#endif -#if STM32_SERIAL_USE_LPUART1 - if (&LPSD1 == sdp) { - rccEnableLPUART1(FALSE); - } -#endif - } - usart_init(sdp, config); -} - -/** - * @brief Low level serial driver stop. - * @details De-initializes the USART, stops the associated clock, resets the - * interrupt vector. - * - * @param[in] sdp pointer to a @p SerialDriver object - * - * @notapi - */ -void sd_lld_stop(SerialDriver *sdp) { - - if (sdp->state == SD_READY) { - /* UART is de-initialized then clocks are disabled.*/ - usart_deinit(sdp->usart); - -#if STM32_SERIAL_USE_USART1 - if (&SD1 == sdp) { - rccDisableUSART1(FALSE); - return; - } -#endif -#if STM32_SERIAL_USE_USART2 - if (&SD2 == sdp) { - rccDisableUSART2(FALSE); - return; - } -#endif -#if STM32_SERIAL_USE_USART3 - if (&SD3 == sdp) { - rccDisableUSART3(FALSE); - return; - } -#endif -#if STM32_SERIAL_USE_UART4 - if (&SD4 == sdp) { - rccDisableUART4(FALSE); - return; - } -#endif -#if STM32_SERIAL_USE_UART5 - if (&SD5 == sdp) { - rccDisableUART5(FALSE); - return; - } -#endif -#if STM32_SERIAL_USE_USART6 - if (&SD6 == sdp) { - rccDisableUSART6(FALSE); - return; - } -#endif -#if STM32_SERIAL_USE_UART7 - if (&SD7 == sdp) { - rccDisableUART7(FALSE); - return; - } -#endif -#if STM32_SERIAL_USE_UART8 - if (&SD8 == sdp) { - rccDisableUART8(FALSE); - return; - } -#endif -#if STM32_SERIAL_USE_LPUART1 - if (&LPSD1 == sdp) { - rccDisableLPUART1(FALSE); - return; - } -#endif - } -} - -#endif /* HAL_USE_SERIAL */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/USARTv2/serial_lld.h b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/USARTv2/serial_lld.h deleted file mode 100644 index 2cf78113ff..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/USARTv2/serial_lld.h +++ /dev/null @@ -1,399 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/USARTv2/serial_lld.h - * @brief STM32 low level serial driver header. - * - * @addtogroup SERIAL - * @{ - */ - -#ifndef _SERIAL_LLD_H_ -#define _SERIAL_LLD_H_ - -#if HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief USART1 driver enable switch. - * @details If set to @p TRUE the support for USART1 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SERIAL_USE_USART1) || defined(__DOXYGEN__) -#define STM32_SERIAL_USE_USART1 FALSE -#endif - -/** - * @brief USART2 driver enable switch. - * @details If set to @p TRUE the support for USART2 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SERIAL_USE_USART2) || defined(__DOXYGEN__) -#define STM32_SERIAL_USE_USART2 FALSE -#endif - -/** - * @brief USART3 driver enable switch. - * @details If set to @p TRUE the support for USART3 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SERIAL_USE_USART3) || defined(__DOXYGEN__) -#define STM32_SERIAL_USE_USART3 FALSE -#endif - -/** - * @brief UART4 driver enable switch. - * @details If set to @p TRUE the support for UART4 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SERIAL_USE_UART4) || defined(__DOXYGEN__) -#define STM32_SERIAL_USE_UART4 FALSE -#endif - -/** - * @brief UART5 driver enable switch. - * @details If set to @p TRUE the support for UART5 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SERIAL_USE_UART5) || defined(__DOXYGEN__) -#define STM32_SERIAL_USE_UART5 FALSE -#endif - -/** - * @brief USART6 driver enable switch. - * @details If set to @p TRUE the support for USART6 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SERIAL_USE_USART6) || defined(__DOXYGEN__) -#define STM32_SERIAL_USE_USART6 FALSE -#endif - -/** - * @brief UART7 driver enable switch. - * @details If set to @p TRUE the support for UART7 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SERIAL_USE_UART7) || defined(__DOXYGEN__) -#define STM32_SERIAL_USE_UART7 FALSE -#endif - -/** - * @brief UART8 driver enable switch. - * @details If set to @p TRUE the support for UART8 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SERIAL_USE_UART8) || defined(__DOXYGEN__) -#define STM32_SERIAL_USE_UART8 FALSE -#endif - -/** - * @brief LPUART1 driver enable switch. - * @details If set to @p TRUE the support for LPUART is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SERIAL_USE_LPUART1) || defined(__DOXYGEN__) -#define STM32_SERIAL_USE_LPUART1 FALSE -#endif - -/** - * @brief USART1 interrupt priority level setting. - */ -#if !defined(STM32_SERIAL_USART1_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SERIAL_USART1_PRIORITY 12 -#endif - -/** - * @brief USART2 interrupt priority level setting. - */ -#if !defined(STM32_SERIAL_USART2_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SERIAL_USART2_PRIORITY 12 -#endif - -/** - * @brief USART3 interrupt priority level setting. - */ -#if !defined(STM32_SERIAL_USART3_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SERIAL_USART3_PRIORITY 12 -#endif - -/** - * @brief USART3..8 interrupt priority level setting. - * @note Only valid on those devices with a shared IRQ. - */ -#if !defined(STM32_SERIAL_USART3_8_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SERIAL_USART3_8_PRIORITY 12 -#endif - -/** - * @brief UART4 interrupt priority level setting. - */ -#if !defined(STM32_SERIAL_UART4_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SERIAL_UART4_PRIORITY 12 -#endif - -/** - * @brief UART5 interrupt priority level setting. - */ -#if !defined(STM32_SERIAL_UART5_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SERIAL_UART5_PRIORITY 12 -#endif - -/** - * @brief USART6 interrupt priority level setting. - */ -#if !defined(STM32_SERIAL_USART6_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SERIAL_USART6_PRIORITY 12 -#endif - -/** - * @brief UART7 interrupt priority level setting. - */ -#if !defined(STM32_SERIAL_UART7_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SERIAL_UART7_PRIORITY 12 -#endif - -/** - * @brief UART8 interrupt priority level setting. - */ -#if !defined(STM32_SERIAL_UART8_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SERIAL_UART8_PRIORITY 12 -#endif - -/** - * @brief LPUART1 interrupt priority level setting. - */ -#if !defined(STM32_SERIAL_LPUART1_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SERIAL_LPUART1_PRIORITY 12 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_SERIAL_USE_USART1 && !STM32_HAS_USART1 -#error "USART1 not present in the selected device" -#endif - -#if STM32_SERIAL_USE_USART2 && !STM32_HAS_USART2 -#error "USART2 not present in the selected device" -#endif - -#if STM32_SERIAL_USE_USART3 && !STM32_HAS_USART3 -#error "USART3 not present in the selected device" -#endif - -#if STM32_SERIAL_USE_UART4 && !STM32_HAS_UART4 -#error "UART4 not present in the selected device" -#endif - -#if STM32_SERIAL_USE_UART5 && !STM32_HAS_UART5 -#error "UART5 not present in the selected device" -#endif - -#if STM32_SERIAL_USE_USART6 && !STM32_HAS_USART6 -#error "USART6 not present in the selected device" -#endif - -#if STM32_SERIAL_USE_UART7 && !STM32_HAS_UART7 -#error "UART7 not present in the selected device" -#endif - -#if STM32_SERIAL_USE_UART8 && !STM32_HAS_UART8 -#error "UART8 not present in the selected device" -#endif - -#if STM32_SERIAL_USE_LPUART1 && !STM32_HAS_LPUART1 -#error "LPUART1 not present in the selected device" -#endif - -#if !STM32_SERIAL_USE_USART1 && !STM32_SERIAL_USE_USART2 && \ - !STM32_SERIAL_USE_USART3 && !STM32_SERIAL_USE_UART4 && \ - !STM32_SERIAL_USE_UART5 && !STM32_SERIAL_USE_USART6 && \ - !STM32_SERIAL_USE_UART7 && !STM32_SERIAL_USE_UART8 && \ - !STM32_SERIAL_USE_LPUART1 -#error "SERIAL driver activated but no USART/UART peripheral assigned" -#endif - -#if STM32_SERIAL_USE_USART1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_USART1_PRIORITY) -#error "Invalid IRQ priority assigned to USART1" -#endif - -#if STM32_SERIAL_USE_USART2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_USART2_PRIORITY) -#error "Invalid IRQ priority assigned to USART2" -#endif - -#if STM32_SERIAL_USE_USART3 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_USART3_PRIORITY) -#error "Invalid IRQ priority assigned to USART3" -#endif - -#if STM32_SERIAL_USE_UART4 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_UART4_PRIORITY) -#error "Invalid IRQ priority assigned to UART4" -#endif - -#if STM32_SERIAL_USE_UART5 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_UART5_PRIORITY) -#error "Invalid IRQ priority assigned to UART5" -#endif - -#if STM32_SERIAL_USE_USART6 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_USART6_PRIORITY) -#error "Invalid IRQ priority assigned to USART6" -#endif - -#if STM32_SERIAL_USE_UART7 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_UART7_PRIORITY) -#error "Invalid IRQ priority assigned to UART7" -#endif - -#if STM32_SERIAL_USE_UART8 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_UART8_PRIORITY) -#error "Invalid IRQ priority assigned to UART8" -#endif - -#if STM32_SERIAL_USE_LPUART1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_LPUART1_PRIORITY) -#error "Invalid IRQ priority assigned to LPUART1" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief STM32 Serial Driver configuration structure. - * @details An instance of this structure must be passed to @p sdStart() - * in order to configure and start a serial driver operations. - * @note This structure content is architecture dependent, each driver - * implementation defines its own version and the custom static - * initializers. - */ -typedef struct { - /** - * @brief Bit rate. - */ - uint32_t speed; - /* End of the mandatory fields.*/ - /** - * @brief Initialization value for the CR1 register. - */ - uint32_t cr1; - /** - * @brief Initialization value for the CR2 register. - */ - uint32_t cr2; - /** - * @brief Initialization value for the CR3 register. - */ - uint32_t cr3; -} SerialConfig; - -/** - * @brief @p SerialDriver specific data. - */ -#define _serial_driver_data \ - _base_asynchronous_channel_data \ - /* Driver state.*/ \ - sdstate_t state; \ - /* Input queue.*/ \ - input_queue_t iqueue; \ - /* Output queue.*/ \ - output_queue_t oqueue; \ - /* Input circular buffer.*/ \ - uint8_t ib[SERIAL_BUFFERS_SIZE]; \ - /* Output circular buffer.*/ \ - uint8_t ob[SERIAL_BUFFERS_SIZE]; \ - /* End of the mandatory fields.*/ \ - /* Pointer to the USART registers block.*/ \ - USART_TypeDef *usart; \ - /* Clock frequency for the associated USART/UART.*/ \ - uint32_t clock; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/* - * Extra USARTs definitions here (missing from the ST header file). - */ -#define USART_CR2_STOP1_BITS (0 << 12) /**< @brief CR2 1 stop bit value.*/ -#define USART_CR2_STOP0P5_BITS (1 << 12) /**< @brief CR2 0.5 stop bit value.*/ -#define USART_CR2_STOP2_BITS (2 << 12) /**< @brief CR2 2 stop bit value.*/ -#define USART_CR2_STOP1P5_BITS (3 << 12) /**< @brief CR2 1.5 stop bit value.*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_SERIAL_USE_USART1 && !defined(__DOXYGEN__) -extern SerialDriver SD1; -#endif -#if STM32_SERIAL_USE_USART2 && !defined(__DOXYGEN__) -extern SerialDriver SD2; -#endif -#if STM32_SERIAL_USE_USART3 && !defined(__DOXYGEN__) -extern SerialDriver SD3; -#endif -#if STM32_SERIAL_USE_UART4 && !defined(__DOXYGEN__) -extern SerialDriver SD4; -#endif -#if STM32_SERIAL_USE_UART5 && !defined(__DOXYGEN__) -extern SerialDriver SD5; -#endif -#if STM32_SERIAL_USE_USART6 && !defined(__DOXYGEN__) -extern SerialDriver SD6; -#endif -#if STM32_SERIAL_USE_UART7 && !defined(__DOXYGEN__) -extern SerialDriver SD7; -#endif -#if STM32_SERIAL_USE_UART8 && !defined(__DOXYGEN__) -extern SerialDriver SD8; -#endif -#if STM32_SERIAL_USE_LPUART1 && !defined(__DOXYGEN__) -extern SerialDriver LPSD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void sd_lld_init(void); - void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); - void sd_lld_stop(SerialDriver *sdp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_SERIAL */ - -#endif /* _SERIAL_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/USARTv2/uart_lld.c b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/USARTv2/uart_lld.c deleted file mode 100644 index deab3deb30..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/USARTv2/uart_lld.c +++ /dev/null @@ -1,931 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/USARTv2/uart_lld.c - * @brief STM32 low level UART driver code. - * - * @addtogroup UART - * @{ - */ - -#include "hal.h" - -#if HAL_USE_UART || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/* STM32L0xx/STM32F7xx ST headers difference.*/ -#if !defined(USART_ISR_LBDF) -#define USART_ISR_LBDF USART_ISR_LBD -#endif - -#define USART1_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_USART1_RX_DMA_STREAM, \ - STM32_USART1_RX_DMA_CHN) - -#define USART1_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_USART1_TX_DMA_STREAM, \ - STM32_USART1_TX_DMA_CHN) - -#define USART2_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_USART2_RX_DMA_STREAM, \ - STM32_USART2_RX_DMA_CHN) - -#define USART2_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_USART2_TX_DMA_STREAM, \ - STM32_USART2_TX_DMA_CHN) - -#define USART3_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_USART3_RX_DMA_STREAM, \ - STM32_USART3_RX_DMA_CHN) - -#define USART3_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_USART3_TX_DMA_STREAM, \ - STM32_USART3_TX_DMA_CHN) - -#define UART4_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_UART4_RX_DMA_STREAM, \ - STM32_UART4_RX_DMA_CHN) - -#define UART4_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_UART4_TX_DMA_STREAM, \ - STM32_UART4_TX_DMA_CHN) - -#define UART5_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_UART5_RX_DMA_STREAM, \ - STM32_UART5_RX_DMA_CHN) - -#define UART5_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_UART5_TX_DMA_STREAM, \ - STM32_UART5_TX_DMA_CHN) - -#define USART6_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_USART6_RX_DMA_STREAM, \ - STM32_USART6_RX_DMA_CHN) - -#define USART6_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_USART6_TX_DMA_STREAM, \ - STM32_USART6_TX_DMA_CHN) - -#define UART7_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_UART7_RX_DMA_STREAM, \ - STM32_UART7_RX_DMA_CHN) - -#define UART7_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_UART7_TX_DMA_STREAM, \ - STM32_UART7_TX_DMA_CHN) - -#define UART8_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_UART8_RX_DMA_STREAM, \ - STM32_UART8_RX_DMA_CHN) - -#define UART8_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_UART8_TX_DMA_STREAM, \ - STM32_UART8_TX_DMA_CHN) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief USART1 UART driver identifier.*/ -#if STM32_UART_USE_USART1 || defined(__DOXYGEN__) -UARTDriver UARTD1; -#endif - -/** @brief USART2 UART driver identifier.*/ -#if STM32_UART_USE_USART2 || defined(__DOXYGEN__) -UARTDriver UARTD2; -#endif - -/** @brief USART3 UART driver identifier.*/ -#if STM32_UART_USE_USART3 || defined(__DOXYGEN__) -UARTDriver UARTD3; -#endif - -/** @brief UART4 UART driver identifier.*/ -#if STM32_UART_USE_UART4 || defined(__DOXYGEN__) -UARTDriver UARTD4; -#endif - -/** @brief UART5 UART driver identifier.*/ -#if STM32_UART_USE_UART5 || defined(__DOXYGEN__) -UARTDriver UARTD5; -#endif - -/** @brief USART6 UART driver identifier.*/ -#if STM32_UART_USE_USART6 || defined(__DOXYGEN__) -UARTDriver UARTD6; -#endif - -/** @brief UART7 UART driver identifier.*/ -#if STM32_UART_USE_UART7 || defined(__DOXYGEN__) -UARTDriver UARTD7; -#endif - -/** @brief UART8 UART driver identifier.*/ -#if STM32_UART_USE_UART8 || defined(__DOXYGEN__) -UARTDriver UARTD8; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Status bits translation. - * - * @param[in] sr USART SR register value - * - * @return The error flags. - */ -static uartflags_t translate_errors(uint32_t isr) { - uartflags_t sts = 0; - - if (isr & USART_ISR_ORE) - sts |= UART_OVERRUN_ERROR; - if (isr & USART_ISR_PE) - sts |= UART_PARITY_ERROR; - if (isr & USART_ISR_FE) - sts |= UART_FRAMING_ERROR; - if (isr & USART_ISR_NE) - sts |= UART_NOISE_ERROR; - if (isr & USART_ISR_LBDF) - sts |= UART_BREAK_DETECTED; - return sts; -} - -/** - * @brief Puts the receiver in the UART_RX_IDLE state. - * - * @param[in] uartp pointer to the @p UARTDriver object - */ -static void uart_enter_rx_idle_loop(UARTDriver *uartp) { - uint32_t mode; - - /* RX DMA channel preparation, if the char callback is defined then the - TCIE interrupt is enabled too.*/ - if (uartp->config->rxchar_cb == NULL) - mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC; - else - mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC | STM32_DMA_CR_TCIE; - dmaStreamSetMemory0(uartp->dmarx, &uartp->rxbuf); - dmaStreamSetTransactionSize(uartp->dmarx, 1); - dmaStreamSetMode(uartp->dmarx, uartp->dmamode | mode); - dmaStreamEnable(uartp->dmarx); -} - -/** - * @brief USART de-initialization. - * @details This function must be invoked with interrupts disabled. - * - * @param[in] uartp pointer to the @p UARTDriver object - */ -static void usart_stop(UARTDriver *uartp) { - - /* Stops RX and TX DMA channels.*/ - dmaStreamDisable(uartp->dmarx); - dmaStreamDisable(uartp->dmatx); - - /* Stops USART operations.*/ - uartp->usart->CR1 = 0; - uartp->usart->CR2 = 0; - uartp->usart->CR3 = 0; -} - -/** - * @brief USART initialization. - * @details This function must be invoked with interrupts disabled. - * - * @param[in] uartp pointer to the @p UARTDriver object - */ -static void usart_start(UARTDriver *uartp) { - uint32_t cr1; - USART_TypeDef *u = uartp->usart; - - /* Defensive programming, starting from a clean state.*/ - usart_stop(uartp); - - /* Baud rate setting.*/ - u->BRR = (uint32_t)(uartp->clock / uartp->config->speed); - - /* Resetting eventual pending status flags.*/ - u->ICR = 0xFFFFFFFFU; - - /* Note that some bits are enforced because required for correct driver - operations.*/ - u->CR2 = uartp->config->cr2 | USART_CR2_LBDIE; - u->CR3 = uartp->config->cr3 | USART_CR3_DMAT | USART_CR3_DMAR | - USART_CR3_EIE; - - /* Mustn't ever set TCIE here - if done, it causes an immediate - interrupt.*/ - cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE; - u->CR1 = uartp->config->cr1 | cr1; - - /* Starting the receiver idle loop.*/ - uart_enter_rx_idle_loop(uartp); -} - -/** - * @brief RX DMA common service routine. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] flags pre-shifted content of the ISR register - */ -static void uart_lld_serve_rx_end_irq(UARTDriver *uartp, uint32_t flags) { - - /* DMA errors handling.*/ -#if defined(STM32_UART_DMA_ERROR_HOOK) - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - STM32_UART_DMA_ERROR_HOOK(uartp); - } -#else - (void)flags; -#endif - - if (uartp->rxstate == UART_RX_IDLE) { - /* Receiver in idle state, a callback is generated, if enabled, for each - received character and then the driver stays in the same state.*/ - _uart_rx_idle_code(uartp); - } - else { - /* Receiver in active state, a callback is generated, if enabled, after - a completed transfer.*/ - dmaStreamDisable(uartp->dmarx); - _uart_rx_complete_isr_code(uartp); - } -} - -/** - * @brief TX DMA common service routine. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] flags pre-shifted content of the ISR register - */ -static void uart_lld_serve_tx_end_irq(UARTDriver *uartp, uint32_t flags) { - - /* DMA errors handling.*/ -#if defined(STM32_UART_DMA_ERROR_HOOK) - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - STM32_UART_DMA_ERROR_HOOK(uartp); - } -#else - (void)flags; -#endif - - dmaStreamDisable(uartp->dmatx); - - /* A callback is generated, if enabled, after a completed transfer.*/ - _uart_tx1_isr_code(uartp); -} - -/** - * @brief USART common service routine. - * - * @param[in] uartp pointer to the @p UARTDriver object - */ -static void serve_usart_irq(UARTDriver *uartp) { - uint32_t isr; - USART_TypeDef *u = uartp->usart; - uint32_t cr1 = u->CR1; - - /* Reading and clearing status.*/ - isr = u->ISR; - u->ICR = isr; - - if (isr & (USART_ISR_LBDF | USART_ISR_ORE | USART_ISR_NE | - USART_ISR_FE | USART_ISR_PE)) { - _uart_rx_error_isr_code(uartp, translate_errors(isr)); - } - - if ((isr & USART_ISR_TC) && (cr1 & USART_CR1_TCIE)) { - /* TC interrupt disabled.*/ - u->CR1 = cr1 & ~USART_CR1_TCIE; - - /* End of transmission, a callback is generated.*/ - _uart_tx2_isr_code(uartp); - } -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if STM32_UART_USE_USART1 || defined(__DOXYGEN__) -#if !defined(STM32_USART1_HANDLER) -#error "STM32_USART1_HANDLER not defined" -#endif -/** - * @brief USART1 IRQ handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_USART1_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - serve_usart_irq(&UARTD1); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_UART_USE_USART1 */ - -#if STM32_UART_USE_USART2 || defined(__DOXYGEN__) -#if !defined(STM32_USART2_HANDLER) -#error "STM32_USART2_HANDLER not defined" -#endif -/** - * @brief USART2 IRQ handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_USART2_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - serve_usart_irq(&UARTD2); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_UART_USE_USART2 */ - -#if STM32_UART_USE_USART3 || defined(__DOXYGEN__) -#if !defined(STM32_USART3_HANDLER) -#error "STM32_USART3_HANDLER not defined" -#endif -/** - * @brief USART3 IRQ handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_USART3_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - serve_usart_irq(&UARTD3); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_UART_USE_USART3 */ - -#if STM32_UART_USE_UART4 || defined(__DOXYGEN__) -#if !defined(STM32_UART4_HANDLER) -#error "STM32_UART4_HANDLER not defined" -#endif -/** - * @brief UART4 IRQ handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_UART4_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - serve_usart_irq(&UARTD4); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_UART_USE_UART4 */ - -#if STM32_UART_USE_UART5 || defined(__DOXYGEN__) -#if !defined(STM32_UART5_HANDLER) -#error "STM32_UART5_HANDLER not defined" -#endif -/** - * @brief UART5 IRQ handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_UART5_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - serve_usart_irq(&UARTD5); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_UART_USE_UART5 */ - -#if STM32_UART_USE_USART6 || defined(__DOXYGEN__) -#if !defined(STM32_USART6_HANDLER) -#error "STM32_USART6_HANDLER not defined" -#endif -/** - * @brief USART6 IRQ handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_USART6_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - serve_usart_irq(&UARTD6); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_UART_USE_USART6 */ - -#if STM32_UART_USE_UART7 || defined(__DOXYGEN__) -#if !defined(STM32_UART7_HANDLER) -#error "STM32_UART7_HANDLER not defined" -#endif -/** - * @brief UART7 IRQ handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_UART7_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - serve_usart_irq(&UARTD7); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_UART_USE_UART7 */ - -#if STM32_UART_USE_UART8 || defined(__DOXYGEN__) -#if !defined(STM32_UART8_HANDLER) -#error "STM32_UART8_HANDLER not defined" -#endif -/** - * @brief UART8 IRQ handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_UART8_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - serve_usart_irq(&UARTD8); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_UART_USE_UART8 */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level UART driver initialization. - * - * @notapi - */ -void uart_lld_init(void) { - -#if STM32_UART_USE_USART1 - uartObjectInit(&UARTD1); - UARTD1.usart = USART1; - UARTD1.clock = STM32_USART1CLK; - UARTD1.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; - UARTD1.dmarx = STM32_DMA_STREAM(STM32_UART_USART1_RX_DMA_STREAM); - UARTD1.dmatx = STM32_DMA_STREAM(STM32_UART_USART1_TX_DMA_STREAM); -#endif - -#if STM32_UART_USE_USART2 - uartObjectInit(&UARTD2); - UARTD2.usart = USART2; - UARTD2.clock = STM32_USART2CLK; - UARTD2.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; - UARTD2.dmarx = STM32_DMA_STREAM(STM32_UART_USART2_RX_DMA_STREAM); - UARTD2.dmatx = STM32_DMA_STREAM(STM32_UART_USART2_TX_DMA_STREAM); -#endif - -#if STM32_UART_USE_USART3 - uartObjectInit(&UARTD3); - UARTD3.usart = USART3; - UARTD3.clock = STM32_USART3CLK; - UARTD3.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; - UARTD3.dmarx = STM32_DMA_STREAM(STM32_UART_USART3_RX_DMA_STREAM); - UARTD3.dmatx = STM32_DMA_STREAM(STM32_UART_USART3_TX_DMA_STREAM); -#endif - -#if STM32_UART_USE_UART4 - uartObjectInit(&UARTD4); - UARTD4.usart = UART4; - UARTD4.clock = STM32_UART4CLK; - UARTD4.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; - UARTD4.dmarx = STM32_DMA_STREAM(STM32_UART_UART4_RX_DMA_STREAM); - UARTD4.dmatx = STM32_DMA_STREAM(STM32_UART_UART4_TX_DMA_STREAM); -#endif - -#if STM32_UART_USE_UART5 - uartObjectInit(&UARTD5); - UARTD5.usart = UART5; - UARTD5.clock = STM32_UART5CLK; - UARTD5.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; - UARTD5.dmarx = STM32_DMA_STREAM(STM32_UART_UART5_RX_DMA_STREAM); - UARTD5.dmatx = STM32_DMA_STREAM(STM32_UART_UART5_TX_DMA_STREAM); -#endif - -#if STM32_UART_USE_USART6 - uartObjectInit(&UARTD6); - UARTD6.usart = USART6; - UARTD6.clock = STM32_USART6CLK; - UARTD6.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; - UARTD6.dmarx = STM32_DMA_STREAM(STM32_UART_USART6_RX_DMA_STREAM); - UARTD6.dmatx = STM32_DMA_STREAM(STM32_UART_USART6_TX_DMA_STREAM); -#endif - -#if STM32_UART_USE_UART7 - uartObjectInit(&UARTD7); - UARTD7.usart = UART7; - UARTD7.clock = STM32_UART7CLK; - UARTD7.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; - UARTD7.dmarx = STM32_DMA_STREAM(STM32_UART_UART7_RX_DMA_STREAM); - UARTD7.dmatx = STM32_DMA_STREAM(STM32_UART_UART7_TX_DMA_STREAM); -#endif - -#if STM32_UART_USE_UART8 - uartObjectInit(&UARTD8); - UARTD8.usart = UART8; - UARTD8.clock = STM32_UART8CLK; - UARTD8.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; - UARTD8.dmarx = STM32_DMA_STREAM(STM32_UART_UART8_RX_DMA_STREAM); - UARTD8.dmatx = STM32_DMA_STREAM(STM32_UART_UART8_TX_DMA_STREAM); -#endif -} - -/** - * @brief Configures and activates the UART peripheral. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @notapi - */ -void uart_lld_start(UARTDriver *uartp) { - - if (uartp->state == UART_STOP) { -#if STM32_UART_USE_USART1 - if (&UARTD1 == uartp) { - bool b; - b = dmaStreamAllocate(uartp->dmarx, - STM32_UART_USART1_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, - (void *)uartp); - osalDbgAssert(!b, "stream already allocated"); - b = dmaStreamAllocate(uartp->dmatx, - STM32_UART_USART1_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, - (void *)uartp); - osalDbgAssert(!b, "stream already allocated"); - rccEnableUSART1(FALSE); - nvicEnableVector(STM32_USART1_NUMBER, STM32_UART_USART1_IRQ_PRIORITY); - uartp->dmamode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY); - } -#endif - -#if STM32_UART_USE_USART2 - if (&UARTD2 == uartp) { - bool b; - b = dmaStreamAllocate(uartp->dmarx, - STM32_UART_USART2_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, - (void *)uartp); - osalDbgAssert(!b, "stream already allocated"); - b = dmaStreamAllocate(uartp->dmatx, - STM32_UART_USART2_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, - (void *)uartp); - osalDbgAssert(!b, "stream already allocated"); - rccEnableUSART2(FALSE); - nvicEnableVector(STM32_USART2_NUMBER, STM32_UART_USART2_IRQ_PRIORITY); - uartp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY); - } -#endif - -#if STM32_UART_USE_USART3 - if (&UARTD3 == uartp) { - bool b; - b = dmaStreamAllocate(uartp->dmarx, - STM32_UART_USART3_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, - (void *)uartp); - osalDbgAssert(!b, "stream already allocated"); - b = dmaStreamAllocate(uartp->dmatx, - STM32_UART_USART3_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, - (void *)uartp); - osalDbgAssert(!b, "stream already allocated"); - rccEnableUSART3(FALSE); - nvicEnableVector(STM32_USART3_NUMBER, STM32_UART_USART3_IRQ_PRIORITY); - uartp->dmamode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY); - } -#endif - -#if STM32_UART_USE_UART4 - if (&UARTD4 == uartp) { - bool b; - b = dmaStreamAllocate(uartp->dmarx, - STM32_UART_UART4_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, - (void *)uartp); - osalDbgAssert(!b, "stream already allocated"); - b = dmaStreamAllocate(uartp->dmatx, - STM32_UART_UART4_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, - (void *)uartp); - osalDbgAssert(!b, "stream already allocated"); - rccEnableUART4(FALSE); - nvicEnableVector(STM32_UART4_NUMBER, STM32_UART_UART4_IRQ_PRIORITY); - uartp->dmamode |= STM32_DMA_CR_CHSEL(UART4_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_UART_UART4_DMA_PRIORITY); - } -#endif - -#if STM32_UART_USE_UART5 - if (&UARTD5 == uartp) { - bool b; - b = dmaStreamAllocate(uartp->dmarx, - STM32_UART_UART5_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, - (void *)uartp); - osalDbgAssert(!b, "stream already allocated"); - b = dmaStreamAllocate(uartp->dmatx, - STM32_UART_UART5_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, - (void *)uartp); - osalDbgAssert(!b, "stream already allocated"); - rccEnableUART5(FALSE); - nvicEnableVector(STM32_UART5_NUMBER, STM32_UART_UART5_IRQ_PRIORITY); - uartp->dmamode |= STM32_DMA_CR_CHSEL(UART5_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_UART_UART5_DMA_PRIORITY); - } -#endif - -#if STM32_UART_USE_USART6 - if (&UARTD6 == uartp) { - bool b; - b = dmaStreamAllocate(uartp->dmarx, - STM32_UART_USART6_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, - (void *)uartp); - osalDbgAssert(!b, "stream already allocated"); - b = dmaStreamAllocate(uartp->dmatx, - STM32_UART_USART6_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, - (void *)uartp); - osalDbgAssert(!b, "stream already allocated"); - rccEnableUSART6(FALSE); - nvicEnableVector(STM32_USART6_NUMBER, STM32_UART_USART6_IRQ_PRIORITY); - uartp->dmamode |= STM32_DMA_CR_CHSEL(USART6_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_UART_USART6_DMA_PRIORITY); - } -#endif - -#if STM32_UART_USE_UART7 - if (&UARTD7 == uartp) { - bool b; - b = dmaStreamAllocate(uartp->dmarx, - STM32_UART_UART7_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, - (void *)uartp); - osalDbgAssert(!b, "stream already allocated"); - b = dmaStreamAllocate(uartp->dmatx, - STM32_UART_UART7_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, - (void *)uartp); - osalDbgAssert(!b, "stream already allocated"); - rccEnableUART7(FALSE); - nvicEnableVector(STM32_UART7_NUMBER, STM32_UART_UART7_IRQ_PRIORITY); - uartp->dmamode |= STM32_DMA_CR_CHSEL(UART7_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_UART_UART7_DMA_PRIORITY); - } -#endif - -#if STM32_UART_USE_UART8 - if (&UARTD8 == uartp) { - bool b; - b = dmaStreamAllocate(uartp->dmarx, - STM32_UART_UART8_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, - (void *)uartp); - osalDbgAssert(!b, "stream already allocated"); - b = dmaStreamAllocate(uartp->dmatx, - STM32_UART_UART8_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, - (void *)uartp); - osalDbgAssert(!b, "stream already allocated"); - rccEnableUART8(FALSE); - nvicEnableVector(STM32_UART8_NUMBER, STM32_UART_UART8_IRQ_PRIORITY); - uartp->dmamode |= STM32_DMA_CR_CHSEL(UART8_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_UART_UART8_DMA_PRIORITY); - } -#endif - - /* Static DMA setup, the transfer size depends on the USART settings, - it is 16 bits if M=1 and PCE=0 else it is 8 bits.*/ - if ((uartp->config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M) - uartp->dmamode |= STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; - dmaStreamSetPeripheral(uartp->dmarx, &uartp->usart->RDR); - dmaStreamSetPeripheral(uartp->dmatx, &uartp->usart->TDR); - uartp->rxbuf = 0; - } - - uartp->rxstate = UART_RX_IDLE; - uartp->txstate = UART_TX_IDLE; - usart_start(uartp); -} - -/** - * @brief Deactivates the UART peripheral. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @notapi - */ -void uart_lld_stop(UARTDriver *uartp) { - - if (uartp->state == UART_READY) { - usart_stop(uartp); - dmaStreamRelease(uartp->dmarx); - dmaStreamRelease(uartp->dmatx); - -#if STM32_UART_USE_USART1 - if (&UARTD1 == uartp) { - nvicDisableVector(STM32_USART1_NUMBER); - rccDisableUSART1(FALSE); - return; - } -#endif - -#if STM32_UART_USE_USART2 - if (&UARTD2 == uartp) { - nvicDisableVector(STM32_USART2_NUMBER); - rccDisableUSART2(FALSE); - return; - } -#endif - -#if STM32_UART_USE_USART3 - if (&UARTD3 == uartp) { - nvicDisableVector(STM32_USART3_NUMBER); - rccDisableUSART3(FALSE); - return; - } -#endif - -#if STM32_UART_USE_UART4 - if (&UARTD4 == uartp) { - nvicDisableVector(STM32_UART4_NUMBER); - rccDisableUART4(FALSE); - return; - } -#endif - -#if STM32_UART_USE_UART5 - if (&UARTD5 == uartp) { - nvicDisableVector(STM32_UART5_NUMBER); - rccDisableUART5(FALSE); - return; - } -#endif - -#if STM32_UART_USE_USART6 - if (&UARTD6 == uartp) { - nvicDisableVector(STM32_USART6_NUMBER); - rccDisableUSART6(FALSE); - return; - } -#endif - -#if STM32_UART_USE_UART7 - if (&UARTD7 == uartp) { - nvicDisableVector(STM32_UART7_NUMBER); - rccDisableUART7(FALSE); - return; - } -#endif - -#if STM32_UART_USE_UART8 - if (&UARTD8 == uartp) { - nvicDisableVector(STM32_UART8_NUMBER); - rccDisableUART8(FALSE); - return; - } -#endif - } -} - -/** - * @brief Starts a transmission on the UART peripheral. - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] n number of data frames to send - * @param[in] txbuf the pointer to the transmit buffer - * - * @notapi - */ -void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) { - - /* TX DMA channel preparation.*/ - dmaStreamSetMemory0(uartp->dmatx, txbuf); - dmaStreamSetTransactionSize(uartp->dmatx, n); - dmaStreamSetMode(uartp->dmatx, uartp->dmamode | STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE); - - /* Only enable TC interrupt if there's a callback attached to it. - Also we need to clear TC flag which could be set before. */ - if (uartp->config->txend2_cb != NULL) { - uartp->usart->ICR = USART_ICR_TCCF; - uartp->usart->CR1 |= USART_CR1_TCIE; - } - - /* Starting transfer.*/ - dmaStreamEnable(uartp->dmatx); -} - -/** - * @brief Stops any ongoing transmission. - * @note Stopping a transmission also suppresses the transmission callbacks. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @return The number of data frames not transmitted by the - * stopped transmit operation. - * - * @notapi - */ -size_t uart_lld_stop_send(UARTDriver *uartp) { - - dmaStreamDisable(uartp->dmatx); - - return dmaStreamGetTransactionSize(uartp->dmatx); -} - -/** - * @brief Starts a receive operation on the UART peripheral. - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] n number of data frames to send - * @param[out] rxbuf the pointer to the receive buffer - * - * @notapi - */ -void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) { - - /* Stopping previous activity (idle state).*/ - dmaStreamDisable(uartp->dmarx); - - /* RX DMA channel preparation.*/ - dmaStreamSetMemory0(uartp->dmarx, rxbuf); - dmaStreamSetTransactionSize(uartp->dmarx, n); - dmaStreamSetMode(uartp->dmarx, uartp->dmamode | STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE); - - /* Starting transfer.*/ - dmaStreamEnable(uartp->dmarx); -} - -/** - * @brief Stops any ongoing receive operation. - * @note Stopping a receive operation also suppresses the receive callbacks. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @return The number of data frames not received by the - * stopped receive operation. - * - * @notapi - */ -size_t uart_lld_stop_receive(UARTDriver *uartp) { - size_t n; - - dmaStreamDisable(uartp->dmarx); - n = dmaStreamGetTransactionSize(uartp->dmarx); - uart_enter_rx_idle_loop(uartp); - - return n; -} - -#endif /* HAL_USE_UART */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/USARTv2/uart_lld.h b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/USARTv2/uart_lld.h deleted file mode 100644 index 361d6d62b0..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/USARTv2/uart_lld.h +++ /dev/null @@ -1,734 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/USARTv2/uart_lld.h - * @brief STM32 low level UART driver header. - * - * @addtogroup UART - * @{ - */ - -#ifndef _UART_LLD_H_ -#define _UART_LLD_H_ - -#if HAL_USE_UART || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief UART driver on USART1 enable switch. - * @details If set to @p TRUE the support for USART1 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_UART_USE_USART1) || defined(__DOXYGEN__) -#define STM32_UART_USE_USART1 FALSE -#endif - -/** - * @brief UART driver on USART2 enable switch. - * @details If set to @p TRUE the support for USART2 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_UART_USE_USART2) || defined(__DOXYGEN__) -#define STM32_UART_USE_USART2 FALSE -#endif - -/** - * @brief UART driver on USART3 enable switch. - * @details If set to @p TRUE the support for USART3 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_UART_USE_USART3) || defined(__DOXYGEN__) -#define STM32_UART_USE_USART3 FALSE -#endif - -/** - * @brief UART driver on UART4 enable switch. - * @details If set to @p TRUE the support for UART4 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_UART_USE_UART4) || defined(__DOXYGEN__) -#define STM32_UART_USE_UART4 FALSE -#endif - -/** - * @brief UART driver on UART5 enable switch. - * @details If set to @p TRUE the support for UART5 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_UART_USE_UART5) || defined(__DOXYGEN__) -#define STM32_UART_USE_UART5 FALSE -#endif - -/** - * @brief UART driver on USART6 enable switch. - * @details If set to @p TRUE the support for USART6 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_UART_USE_USART6) || defined(__DOXYGEN__) -#define STM32_UART_USE_USART6 FALSE -#endif - -/** - * @brief UART driver on UART7 enable switch. - * @details If set to @p TRUE the support for UART7 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_UART_USE_UART7) || defined(__DOXYGEN__) -#define STM32_UART_USE_UART7 FALSE -#endif - -/** - * @brief UART driver on UART8 enable switch. - * @details If set to @p TRUE the support for UART8 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_UART_USE_UART8) || defined(__DOXYGEN__) -#define STM32_UART_USE_UART8 FALSE -#endif - -/** - * @brief USART1 interrupt priority level setting. - */ -#if !defined(STM32_UART_USART1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART1_IRQ_PRIORITY 12 -#endif - -/** - * @brief USART2 interrupt priority level setting. - */ -#if !defined(STM32_UART_USART2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART2_IRQ_PRIORITY 12 -#endif - -/** - * @brief USART3 interrupt priority level setting. - */ -#if !defined(STM32_UART_USART3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART3_IRQ_PRIORITY 12 -#endif - -/** - * @brief UART4 interrupt priority level setting. - */ -#if !defined(STM32_UART_UART4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_UART4_IRQ_PRIORITY 12 -#endif - -/** - * @brief UART5 interrupt priority level setting. - */ -#if !defined(STM32_UART_UART5_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_UART5_IRQ_PRIORITY 12 -#endif - -/** - * @brief USART6 interrupt priority level setting. - */ -#if !defined(STM32_UART_USART6_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART6_IRQ_PRIORITY 12 -#endif - -/** - * @brief UART7 interrupt priority level setting. - */ -#if !defined(STM32_UART_UART7_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_UART7_IRQ_PRIORITY 12 -#endif - -/** - * @brief UART8 interrupt priority level setting. - */ -#if !defined(STM32_UART_UART8_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_UART8_IRQ_PRIORITY 12 -#endif - -/** - * @brief USART1 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA channels but - * because of the channels ordering the RX channel has always priority - * over the TX channel. - */ -#if !defined(STM32_UART_USART1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART1_DMA_PRIORITY 0 -#endif - -/** - * @brief USART2 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA channels but - * because of the channels ordering the RX channel has always priority - * over the TX channel. - */ -#if !defined(STM32_UART_USART2_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART2_DMA_PRIORITY 0 -#endif - -/** - * @brief USART3 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA channels but - * because of the channels ordering the RX channel has always priority - * over the TX channel. - */ -#if !defined(STM32_UART_USART3_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART3_DMA_PRIORITY 0 -#endif - -/** - * @brief UART4 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA channels but - * because of the channels ordering the RX channel has always priority - * over the TX channel. - */ -#if !defined(STM32_UART_UART4_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_UART4_DMA_PRIORITY 0 -#endif - -/** - * @brief UART5 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA channels but - * because of the channels ordering the RX channel has always priority - * over the TX channel. - */ -#if !defined(STM32_UART_UART5_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_UART5_DMA_PRIORITY 0 -#endif - -/** - * @brief USART6 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA channels but - * because of the channels ordering the RX channel has always priority - * over the TX channel. - */ -#if !defined(STM32_UART_USART6_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART6_DMA_PRIORITY 0 -#endif - -/** - * @brief UART7 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA channels but - * because of the channels ordering the RX channel has always priority - * over the TX channel. - */ -#if !defined(STM32_UART_UART7_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_UART7_DMA_PRIORITY 0 -#endif - -/** - * @brief UART8 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA channels but - * because of the channels ordering the RX channel has always priority - * over the TX channel. - */ -#if !defined(STM32_UART_UART8_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_UART8_DMA_PRIORITY 0 -#endif - -/** - * @brief UART DMA error hook. - * @note The default action for DMA errors is a system halt because DMA - * error can only happen because programming errors. - */ -#if !defined(STM32_UART_DMA_ERROR_HOOK) || defined(__DOXYGEN__) -#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_UART_USE_USART1 && !STM32_HAS_USART1 -#error "USART1 not present in the selected device" -#endif - -#if STM32_UART_USE_USART2 && !STM32_HAS_USART2 -#error "USART2 not present in the selected device" -#endif - -#if STM32_UART_USE_USART3 && !STM32_HAS_USART3 -#error "USART3 not present in the selected device" -#endif - -#if STM32_UART_USE_UART4 && !STM32_HAS_UART4 -#error "UART4 not present in the selected device" -#endif - -#if STM32_UART_USE_UART5 && !STM32_HAS_UART5 -#error "UART5 not present in the selected device" -#endif - -#if STM32_UART_USE_UART7 && !STM32_HAS_UART7 -#error "UART7 not present in the selected device" -#endif - -#if STM32_UART_USE_UART8 && !STM32_HAS_UART8 -#error "UART8 not present in the selected device" -#endif - -#if !STM32_UART_USE_USART1 && !STM32_UART_USE_USART2 && \ - !STM32_UART_USE_USART3 && !STM32_UART_USE_UART4 && \ - !STM32_UART_USE_UART5 && !STM32_UART_USE_USART6 && \ - !STM32_UART_USE_UART7 && !STM32_UART_USE_UART8 -#error "UART driver activated but no USART/UART peripheral assigned" -#endif - -#if STM32_UART_USE_USART1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_USART1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to USART1" -#endif - -#if STM32_UART_USE_USART2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_USART2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to USART2" -#endif - -#if STM32_UART_USE_USART3 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_USART3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to USART3" -#endif - -#if STM32_UART_USE_UART4 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_UART4_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to UART4" -#endif - -#if STM32_UART_USE_UART5 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_UART5_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to UART5" -#endif - -#if STM32_UART_USE_USART6 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_USART6_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to USART6" -#endif - -#if STM32_UART_USE_UART7 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_UART7_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to UART7" -#endif - -#if STM32_UART_USE_UART8 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_UART8_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to UART8" -#endif - -#if STM32_UART_USE_USART1 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART1_DMA_PRIORITY) -#error "Invalid DMA priority assigned to USART1" -#endif - -#if STM32_UART_USE_USART2 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART2_DMA_PRIORITY) -#error "Invalid DMA priority assigned to USART2" -#endif - -#if STM32_UART_USE_USART3 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART3_DMA_PRIORITY) -#error "Invalid DMA priority assigned to USART3" -#endif - -#if STM32_UART_USE_UART4 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_UART4_DMA_PRIORITY) -#error "Invalid DMA priority assigned to UART4" -#endif - -#if STM32_UART_USE_UART5 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_UART5_DMA_PRIORITY) -#error "Invalid DMA priority assigned to UART5" -#endif - -#if STM32_UART_USE_USART6 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART6_DMA_PRIORITY) -#error "Invalid DMA priority assigned to USART6" -#endif - -#if STM32_UART_USE_UART7 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_UART7_DMA_PRIORITY) -#error "Invalid DMA priority assigned to UART7" -#endif - -#if STM32_UART_USE_UART8 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_UART8_DMA_PRIORITY) -#error "Invalid DMA priority assigned to UART8" -#endif - -/* The following checks are only required when there is a DMA able to - reassign streams to different channels.*/ -#if STM32_ADVANCED_DMA -/* Check on the presence of the DMA streams settings in mcuconf.h.*/ -#if STM32_UART_USE_USART1 && (!defined(STM32_UART_USART1_RX_DMA_STREAM) || \ - !defined(STM32_UART_USART1_TX_DMA_STREAM)) -#error "USART1 DMA streams not defined" -#endif - -#if STM32_UART_USE_USART2 && (!defined(STM32_UART_USART2_RX_DMA_STREAM) || \ - !defined(STM32_UART_USART2_TX_DMA_STREAM)) -#error "USART2 DMA streams not defined" -#endif - -#if STM32_UART_USE_USART3 && (!defined(STM32_UART_USART3_RX_DMA_STREAM) || \ - !defined(STM32_UART_USART3_TX_DMA_STREAM)) -#error "USART3 DMA streams not defined" -#endif - -#if STM32_UART_USE_UART4 && (!defined(STM32_UART_UART4_RX_DMA_STREAM) || \ - !defined(STM32_UART_UART4_TX_DMA_STREAM)) -#error "UART4 DMA streams not defined" -#endif - -#if STM32_UART_USE_UART5 && (!defined(STM32_UART_UART5_RX_DMA_STREAM) || \ - !defined(STM32_UART_UART5_TX_DMA_STREAM)) -#error "UART5 DMA streams not defined" -#endif - -#if STM32_UART_USE_USART6 && (!defined(STM32_UART_USART6_RX_DMA_STREAM) || \ - !defined(STM32_UART_USART6_TX_DMA_STREAM)) -#error "USART6 DMA streams not defined" -#endif - -#if STM32_UART_USE_UART7 && (!defined(STM32_UART_UART7_RX_DMA_STREAM) || \ - !defined(STM32_UART_UART7_TX_DMA_STREAM)) -#error "UART7 DMA streams not defined" -#endif - -#if STM32_UART_USE_UART8 && (!defined(STM32_UART_UART8_RX_DMA_STREAM) || \ - !defined(STM32_UART_UART8_TX_DMA_STREAM)) -#error "UART8 DMA streams not defined" -#endif - -/* Check on the validity of the assigned DMA channels.*/ -#if STM32_UART_USE_USART1 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_USART1_RX_DMA_STREAM, \ - STM32_USART1_RX_DMA_MSK) -#error "invalid DMA stream associated to USART1 RX" -#endif - -#if STM32_UART_USE_USART1 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_USART1_TX_DMA_STREAM, \ - STM32_USART1_TX_DMA_MSK) -#error "invalid DMA stream associated to USART1 TX" -#endif - -#if STM32_UART_USE_USART2 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_USART2_RX_DMA_STREAM, \ - STM32_USART2_RX_DMA_MSK) -#error "invalid DMA stream associated to USART2 RX" -#endif - -#if STM32_UART_USE_USART2 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_USART2_TX_DMA_STREAM, \ - STM32_USART2_TX_DMA_MSK) -#error "invalid DMA stream associated to USART2 TX" -#endif - -#if STM32_UART_USE_USART3 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_USART3_RX_DMA_STREAM, \ - STM32_USART3_RX_DMA_MSK) -#error "invalid DMA stream associated to USART3 RX" -#endif - -#if STM32_UART_USE_USART3 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_USART3_TX_DMA_STREAM, \ - STM32_USART3_TX_DMA_MSK) -#error "invalid DMA stream associated to USART3 TX" -#endif - -#if STM32_UART_USE_UART4 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_UART4_RX_DMA_STREAM, \ - STM32_UART4_RX_DMA_MSK) -#error "invalid DMA stream associated to UART4 RX" -#endif - -#if STM32_UART_USE_UART4 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_UART4_TX_DMA_STREAM, \ - STM32_UART4_TX_DMA_MSK) -#error "invalid DMA stream associated to UART4 TX" -#endif - -#if STM32_UART_USE_UART5 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_UART5_RX_DMA_STREAM, \ - STM32_UART5_RX_DMA_MSK) -#error "invalid DMA stream associated to UART5 RX" -#endif - -#if STM32_UART_USE_UART5 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_UART5_TX_DMA_STREAM, \ - STM32_UART5_TX_DMA_MSK) -#error "invalid DMA stream associated to UART5 TX" -#endif - -#if STM32_UART_USE_USART6 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_USART6_RX_DMA_STREAM, \ - STM32_USART6_RX_DMA_MSK) -#error "invalid DMA stream associated to USART6 RX" -#endif - -#if STM32_UART_USE_USART6 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_USART6_TX_DMA_STREAM, \ - STM32_USART6_TX_DMA_MSK) -#error "invalid DMA stream associated to USART6 TX" -#endif - -#if STM32_UART_USE_UART7 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_UART7_RX_DMA_STREAM, \ - STM32_UART7_RX_DMA_MSK) -#error "invalid DMA stream associated to UART7 RX" -#endif - -#if STM32_UART_USE_UART7 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_UART7_TX_DMA_STREAM, \ - STM32_UART7_TX_DMA_MSK) -#error "invalid DMA stream associated to UART7 TX" -#endif - -#if STM32_UART_USE_UART8 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_UART8_RX_DMA_STREAM, \ - STM32_UART8_RX_DMA_MSK) -#error "invalid DMA stream associated to UART8 RX" -#endif - -#if STM32_UART_USE_UART8 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_UART8_TX_DMA_STREAM, \ - STM32_UART8_TX_DMA_MSK) -#error "invalid DMA stream associated to UART8 TX" -#endif -#endif /* STM32_ADVANCED_DMA */ - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief UART driver condition flags type. - */ -typedef uint32_t uartflags_t; - -/** - * @brief Structure representing an UART driver. - */ -typedef struct UARTDriver UARTDriver; - -/** - * @brief Generic UART notification callback type. - * - * @param[in] uartp pointer to the @p UARTDriver object - */ -typedef void (*uartcb_t)(UARTDriver *uartp); - -/** - * @brief Character received UART notification callback type. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] c received character - */ -typedef void (*uartccb_t)(UARTDriver *uartp, uint16_t c); - -/** - * @brief Receive error UART notification callback type. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] e receive error mask - */ -typedef void (*uartecb_t)(UARTDriver *uartp, uartflags_t e); - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief End of transmission buffer callback. - */ - uartcb_t txend1_cb; - /** - * @brief Physical end of transmission callback. - */ - uartcb_t txend2_cb; - /** - * @brief Receive buffer filled callback. - */ - uartcb_t rxend_cb; - /** - * @brief Character received while out if the @p UART_RECEIVE state. - */ - uartccb_t rxchar_cb; - /** - * @brief Receive error callback. - */ - uartecb_t rxerr_cb; - /* End of the mandatory fields.*/ - /** - * @brief Bit rate. - */ - uint32_t speed; - /** - * @brief Initialization value for the CR1 register. - */ - uint32_t cr1; - /** - * @brief Initialization value for the CR2 register. - */ - uint32_t cr2; - /** - * @brief Initialization value for the CR3 register. - */ - uint32_t cr3; -} UARTConfig; - -/** - * @brief Structure representing an UART driver. - */ -struct UARTDriver { - /** - * @brief Driver state. - */ - uartstate_t state; - /** - * @brief Transmitter state. - */ - uarttxstate_t txstate; - /** - * @brief Receiver state. - */ - uartrxstate_t rxstate; - /** - * @brief Current configuration data. - */ - const UARTConfig *config; -#if (UART_USE_WAIT == TRUE) || defined(__DOXYGEN__) - /** - * @brief Synchronization flag for transmit operations. - */ - bool early; - /** - * @brief Waiting thread on RX. - */ - thread_reference_t threadrx; - /** - * @brief Waiting thread on TX. - */ - thread_reference_t threadtx; -#endif /* UART_USE_WAIT */ -#if (UART_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the peripheral. - */ - mutex_t mutex; -#endif /* UART_USE_MUTUAL_EXCLUSION */ -#if defined(UART_DRIVER_EXT_FIELDS) - UART_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the USART registers block. - */ - USART_TypeDef *usart; - /** - * @brief Clock frequency for the associated USART/UART. - */ - uint32_t clock; - /** - * @brief DMA mode bit mask. - */ - uint32_t dmamode; - /** - * @brief Receive DMA channel. - */ - const stm32_dma_stream_t *dmarx; - /** - * @brief Transmit DMA channel. - */ - const stm32_dma_stream_t *dmatx; - /** - * @brief Default receive buffer while into @p UART_RX_IDLE state. - */ - volatile uint16_t rxbuf; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_UART_USE_USART1 && !defined(__DOXYGEN__) -extern UARTDriver UARTD1; -#endif - -#if STM32_UART_USE_USART2 && !defined(__DOXYGEN__) -extern UARTDriver UARTD2; -#endif - -#if STM32_UART_USE_USART3 && !defined(__DOXYGEN__) -extern UARTDriver UARTD3; -#endif - -#if STM32_UART_USE_UART4 && !defined(__DOXYGEN__) -extern UARTDriver UARTD4; -#endif - -#if STM32_UART_USE_UART5 && !defined(__DOXYGEN__) -extern UARTDriver UARTD5; -#endif - -#if STM32_UART_USE_USART6 && !defined(__DOXYGEN__) -extern UARTDriver UARTD6; -#endif - -#if STM32_UART_USE_UART7 && !defined(__DOXYGEN__) -extern UARTDriver UARTD7; -#endif - -#if STM32_UART_USE_UART8 && !defined(__DOXYGEN__) -extern UARTDriver UARTD8; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void uart_lld_init(void); - void uart_lld_start(UARTDriver *uartp); - void uart_lld_stop(UARTDriver *uartp); - void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf); - size_t uart_lld_stop_send(UARTDriver *uartp); - void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf); - size_t uart_lld_stop_receive(UARTDriver *uartp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_UART */ - -#endif /* _UART_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/USBv1/stm32_usb.h b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/USBv1/stm32_usb.h deleted file mode 100644 index 33a89b3960..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/USBv1/stm32_usb.h +++ /dev/null @@ -1,266 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file stm32_usb.h - * @brief STM32 USB registers layout header. - * @note This file requires definitions from the ST STM32 header files - * stm32f10x.h or stm32l1xx.h. - * - * @addtogroup USB - * @{ - */ - -#ifndef _STM32_USB_H_ -#define _STM32_USB_H_ - -/** - * @brief Number of the available endpoints. - * @details This value does not include the endpoint 0 which is always present. - */ -#define USB_ENDOPOINTS_NUMBER 7 - -/** - * @brief Width of USB packet memory accesses. - */ -#if STM32_USB_ACCESS_SCHEME_2x16 -typedef uint16_t stm32_usb_pma_t; -#else -typedef uint32_t stm32_usb_pma_t; -#endif - -/** - * @brief USB registers block. - */ -typedef struct { - /** - * @brief Endpoint registers. - */ - volatile uint32_t EPR[USB_ENDOPOINTS_NUMBER + 1]; - /* - * @brief Reserved space. - */ - volatile uint32_t _r20[8]; - /* - * @brief Control Register. - */ - volatile uint32_t CNTR; - /* - * @brief Interrupt Status Register. - */ - volatile uint32_t ISTR; - /* - * @brief Frame Number Register. - */ - volatile uint32_t FNR; - /* - * @brief Device Address Register. - */ - volatile uint32_t DADDR; - /* - * @brief Buffer Table Address. - */ - volatile uint32_t BTABLE; - /* - * @brief LPM Control and Status Register. - */ - volatile uint32_t LPMCSR; -#if STM32_USB_HAS_BCDR - /* - * @brief Battery Charging Detector - */ - volatile uint32_t BCDR; -#endif -} stm32_usb_t; - -/** - * @brief USB descriptor registers block. - */ -typedef struct { - /** - * @brief TX buffer offset register. - */ - volatile stm32_usb_pma_t TXADDR0; - /** - * @brief TX counter register 0. - */ - volatile stm32_usb_pma_t TXCOUNT0; - /** - * @brief RX buffer offset register. - */ - volatile stm32_usb_pma_t RXADDR0; - /** - * @brief RX counter register 0. - */ - volatile stm32_usb_pma_t RXCOUNT0; -} stm32_usb_descriptor_t; - -/** - * @name Register aliases - * @{ - */ -#define RXCOUNT1 TXCOUNT0 -#define TXCOUNT1 RXCOUNT0 -#define RXADDR1 TXADDR0 -#define TXADDR1 RXADDR0 -/** @} */ - -/** - * @brief USB registers block numeric address. - */ -#if defined(USB_BASE) || defined(__DOXYGEN__) -#define STM32_USB_BASE USB_BASE -#else -#define STM32_USB_BASE (APB1PERIPH_BASE + 0x5C00) -#endif - -/** - * @brief USB RAM numeric address. - */ -#if defined(USB_PMAADDR) || defined(__DOXYGEN__) -#define STM32_USBRAM_BASE USB_PMAADDR -#else -#define STM32_USBRAM_BASE (APB1PERIPH_BASE + 0x6000) -#endif - -/** - * @brief Pointer to the USB registers block. - */ -#define STM32_USB ((stm32_usb_t *)STM32_USB_BASE) - -/** - * @brief Pointer to the USB RAM. - */ -#define STM32_USBRAM ((stm32_usb_pma_t *)STM32_USBRAM_BASE) - -/** - * @brief Mask of all the toggling bits in the EPR register. - */ -#define EPR_TOGGLE_MASK (EPR_STAT_TX_MASK | EPR_DTOG_TX | \ - EPR_STAT_RX_MASK | EPR_DTOG_RX | \ - EPR_SETUP) - -#define EPR_EA_MASK 0x000F -#define EPR_STAT_TX_MASK 0x0030 -#define EPR_STAT_TX_DIS 0x0000 -#define EPR_STAT_TX_STALL 0x0010 -#define EPR_STAT_TX_NAK 0x0020 -#define EPR_STAT_TX_VALID 0x0030 -#define EPR_DTOG_TX 0x0040 -#define EPR_SWBUF_RX EPR_DTOG_TX -#define EPR_CTR_TX 0x0080 -#define EPR_EP_KIND 0x0100 -#define EPR_EP_DBL_BUF EPR_EP_KIND -#define EPR_EP_STATUS_OUT EPR_EP_KIND -#define EPR_EP_TYPE_MASK 0x0600 -#define EPR_EP_TYPE_BULK 0x0000 -#define EPR_EP_TYPE_CONTROL 0x0200 -#define EPR_EP_TYPE_ISO 0x0400 -#define EPR_EP_TYPE_INTERRUPT 0x0600 -#define EPR_SETUP 0x0800 -#define EPR_STAT_RX_MASK 0x3000 -#define EPR_STAT_RX_DIS 0x0000 -#define EPR_STAT_RX_STALL 0x1000 -#define EPR_STAT_RX_NAK 0x2000 -#define EPR_STAT_RX_VALID 0x3000 -#define EPR_DTOG_RX 0x4000 -#define EPR_SWBUF_TX EPR_DTOG_RX -#define EPR_CTR_RX 0x8000 - -#define CNTR_FRES 0x0001 -#define CNTR_PDWN 0x0002 -#define CNTR_LP_MODE 0x0004 -#define CNTR_FSUSP 0x0008 -#define CNTR_RESUME 0x0010 -#define CNTR_ESOFM 0x0100 -#define CNTR_SOFM 0x0200 -#define CNTR_RESETM 0x0400 -#define CNTR_SUSPM 0x0800 -#define CNTR_WKUPM 0x1000 -#define CNTR_ERRM 0x2000 -#define CNTR_PMAOVRM 0x4000 -#define CNTR_CTRM 0x8000 - -#define ISTR_EP_ID_MASK 0x000F -#define ISTR_DIR 0x0010 -#define ISTR_ESOF 0x0100 -#define ISTR_SOF 0x0200 -#define ISTR_RESET 0x0400 -#define ISTR_SUSP 0x0800 -#define ISTR_WKUP 0x1000 -#define ISTR_ERR 0x2000 -#define ISTR_PMAOVR 0x4000 -#define ISTR_CTR 0x8000 - -#define FNR_FN_MASK 0x07FF -#define FNR_LSOF 0x1800 -#define FNR_LCK 0x2000 -#define FNR_RXDM 0x4000 -#define FNR_RXDP 0x8000 - -#define DADDR_ADD_MASK 0x007F -#define DADDR_EF 0x0080 - -#define RXCOUNT_COUNT_MASK 0x03FF -#define TXCOUNT_COUNT_MASK 0x03FF - -#define EPR_CTR_MASK (EPR_CTR_TX | EPR_CTR_RX) - -#define EPR_SET(ep, epr) \ - STM32_USB->EPR[ep] = ((epr) & ~EPR_TOGGLE_MASK) | EPR_CTR_MASK - -#define EPR_TOGGLE(ep, epr) \ - STM32_USB->EPR[ep] = (STM32_USB->EPR[ep] ^ ((epr) & EPR_TOGGLE_MASK)) \ - | EPR_CTR_MASK - -#define EPR_SET_STAT_RX(ep, epr) \ - STM32_USB->EPR[ep] = ((STM32_USB->EPR[ep] & \ - ~(EPR_TOGGLE_MASK & ~EPR_STAT_RX_MASK)) ^ \ - (epr)) | EPR_CTR_MASK - -#define EPR_SET_STAT_TX(ep, epr) \ - STM32_USB->EPR[ep] = ((STM32_USB->EPR[ep] & \ - ~(EPR_TOGGLE_MASK & ~EPR_STAT_TX_MASK)) ^ \ - (epr)) | EPR_CTR_MASK - -#define EPR_CLEAR_CTR_RX(ep) \ - STM32_USB->EPR[ep] = (STM32_USB->EPR[ep] & ~EPR_CTR_RX & ~EPR_TOGGLE_MASK)\ - | EPR_CTR_TX - -#define EPR_CLEAR_CTR_TX(ep) \ - STM32_USB->EPR[ep] = (STM32_USB->EPR[ep] & ~EPR_CTR_TX & ~EPR_TOGGLE_MASK)\ - | EPR_CTR_RX - -/** - * @brief Returns an endpoint descriptor pointer. - */ -#define USB_GET_DESCRIPTOR(ep) \ - ((stm32_usb_descriptor_t *)((uint32_t)STM32_USBRAM_BASE + \ - (uint32_t)STM32_USB->BTABLE + \ - (uint32_t)(ep) * \ - sizeof(stm32_usb_descriptor_t))) - -/** - * @brief Converts from a PMA address to a physical address. - */ -#define USB_ADDR2PTR(addr) \ - ((stm32_usb_pma_t *)((addr) * \ - (sizeof(stm32_usb_pma_t) / 2) + \ - STM32_USBRAM_BASE)) - -#endif /* _STM32_USB_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/USBv1/usb_lld.c b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/USBv1/usb_lld.c deleted file mode 100644 index ef06e151d0..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/USBv1/usb_lld.c +++ /dev/null @@ -1,863 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/USBv1/usb_lld.c - * @brief STM32 USB subsystem low level driver source. - * - * @addtogroup USB - * @{ - */ - -#include - -#include "hal.h" - -#if HAL_USE_USB || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define BTABLE_ADDR 0x0000 - -#define EPR_EP_TYPE_IS_ISO(bits) ((bits & EPR_EP_TYPE_MASK) == EPR_EP_TYPE_ISO) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief USB1 driver identifier.*/ -#if STM32_USB_USE_USB1 || defined(__DOXYGEN__) -USBDriver USBD1; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief EP0 state. - * @note It is an union because IN and OUT endpoints are never used at the - * same time for EP0. - */ -static union { - /** - * @brief IN EP0 state. - */ - USBInEndpointState in; - /** - * @brief OUT EP0 state. - */ - USBOutEndpointState out; -} ep0_state; - -/** - * @brief Buffer for the EP0 setup packets. - */ -static uint8_t ep0setup_buffer[8]; - -/** - * @brief EP0 initialization structure. - */ -static const USBEndpointConfig ep0config = { - USB_EP_MODE_TYPE_CTRL, - _usb_ep0setup, - _usb_ep0in, - _usb_ep0out, - 0x40, - 0x40, - &ep0_state.in, - &ep0_state.out, - 1, - ep0setup_buffer -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Resets the packet memory allocator. - * - * @param[in] usbp pointer to the @p USBDriver object - */ -static void usb_pm_reset(USBDriver *usbp) { - - /* The first 64 bytes are reserved for the descriptors table. The effective - available RAM for endpoint buffers is just 448 bytes.*/ - usbp->pmnext = 64; -} - -/** - * @brief Resets the packet memory allocator. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] size size of the packet buffer to allocate - */ -static uint32_t usb_pm_alloc(USBDriver *usbp, size_t size) { - uint32_t next; - - next = usbp->pmnext; - usbp->pmnext += (size + 1) & ~1; - osalDbgAssert(usbp->pmnext <= STM32_USB_PMA_SIZE, "PMA overflow"); - return next; -} - -/** - * @brief Reads from a dedicated packet buffer. - * - * @param[in] udp pointer to a @p stm32_usb_descriptor_t - * @param[out] buf buffer where to copy the packet data - * @return The size of the receivee packet. - * - * @notapi - */ -static size_t usb_packet_read_to_buffer(usbep_t ep, uint8_t *buf) { - size_t i, n; - stm32_usb_descriptor_t *udp = USB_GET_DESCRIPTOR(ep); - stm32_usb_pma_t *pmap = USB_ADDR2PTR(udp->RXADDR0); -#if STM32_USB_USE_ISOCHRONOUS - uint32_t epr = STM32_USB->EPR[ep]; - - /* Double buffering is always enabled for isochronous endpoints, and - although we overlap the two buffers for simplicity, we still need - to read from the right counter. The DTOG_RX bit indicates the buffer - that is currently in use by the USB peripheral, that is, the buffer - in which the next received packet will be stored, so we need to - read the counter of the OTHER buffer, which is where the last - received packet was stored.*/ - if (EPR_EP_TYPE_IS_ISO(epr) && !(epr & EPR_DTOG_RX)) - n = (size_t)udp->RXCOUNT1 & RXCOUNT_COUNT_MASK; - else - n = (size_t)udp->RXCOUNT0 & RXCOUNT_COUNT_MASK; -#else - n = (size_t)udp->RXCOUNT0 & RXCOUNT_COUNT_MASK; -#endif - - i = n; - -#if STM32_USB_USE_FAST_COPY - while (i >= 16) { - uint32_t w; - - w = *(pmap + 0); - *(buf + 0) = (uint8_t)w; - *(buf + 1) = (uint8_t)(w >> 8); - w = *(pmap + 1); - *(buf + 2) = (uint8_t)w; - *(buf + 3) = (uint8_t)(w >> 8); - w = *(pmap + 2); - *(buf + 4) = (uint8_t)w; - *(buf + 5) = (uint8_t)(w >> 8); - w = *(pmap + 3); - *(buf + 6) = (uint8_t)w; - *(buf + 7) = (uint8_t)(w >> 8); - w = *(pmap + 4); - *(buf + 8) = (uint8_t)w; - *(buf + 9) = (uint8_t)(w >> 8); - w = *(pmap + 5); - *(buf + 10) = (uint8_t)w; - *(buf + 11) = (uint8_t)(w >> 8); - w = *(pmap + 6); - *(buf + 12) = (uint8_t)w; - *(buf + 13) = (uint8_t)(w >> 8); - w = *(pmap + 7); - *(buf + 14) = (uint8_t)w; - *(buf + 15) = (uint8_t)(w >> 8); - - i -= 16; - buf += 16; - pmap += 8; - } -#endif /* STM32_USB_USE_FAST_COPY */ - - while (i >= 2) { - uint32_t w = *pmap++; - *buf++ = (uint8_t)w; - *buf++ = (uint8_t)(w >> 8); - i -= 2; - } - - if (i >= 1) { - *buf = (uint8_t)*pmap; - } - - return n; -} - -/** - * @brief Writes to a dedicated packet buffer. - * - * @param[in] ep endpoint number - * @param[in] buf buffer where to fetch the packet data - * @param[in] n maximum number of bytes to copy. This value must - * not exceed the maximum packet size for this endpoint. - * - * @notapi - */ -static void usb_packet_write_from_buffer(usbep_t ep, - const uint8_t *buf, - size_t n) { - stm32_usb_descriptor_t *udp = USB_GET_DESCRIPTOR(ep); - stm32_usb_pma_t *pmap = USB_ADDR2PTR(udp->TXADDR0); - int i = (int)n; - -#if STM32_USB_USE_ISOCHRONOUS - uint32_t epr = STM32_USB->EPR[ep]; - - /* Double buffering is always enabled for isochronous endpoints, and - although we overlap the two buffers for simplicity, we still need - to write to the right counter. The DTOG_TX bit indicates the buffer - that is currently in use by the USB peripheral, that is, the buffer - from which the next packet will be sent, so we need to write the - counter of that buffer.*/ - if (EPR_EP_TYPE_IS_ISO(epr) && (epr & EPR_DTOG_TX)) - udp->TXCOUNT1 = (stm32_usb_pma_t)n; - else - udp->TXCOUNT0 = (stm32_usb_pma_t)n; -#else - udp->TXCOUNT0 = (stm32_usb_pma_t)n; -#endif - -#if STM32_USB_USE_FAST_COPY - while (i >= 16) { - uint32_t w; - - w = *(buf + 0); - w |= *(buf + 1) << 8; - *(pmap + 0) = (stm32_usb_pma_t)w; - w = *(buf + 2); - w |= *(buf + 3) << 8; - *(pmap + 1) = (stm32_usb_pma_t)w; - w = *(buf + 4); - w |= *(buf + 5) << 8; - *(pmap + 2) = (stm32_usb_pma_t)w; - w = *(buf + 6); - w |= *(buf + 7) << 8; - *(pmap + 3) = (stm32_usb_pma_t)w; - w = *(buf + 8); - w |= *(buf + 9) << 8; - *(pmap + 4) = (stm32_usb_pma_t)w; - w = *(buf + 10); - w |= *(buf + 11) << 8; - *(pmap + 5) = (stm32_usb_pma_t)w; - w = *(buf + 12); - w |= *(buf + 13) << 8; - *(pmap + 6) = (stm32_usb_pma_t)w; - w = *(buf + 14); - w |= *(buf + 15) << 8; - *(pmap + 7) = (stm32_usb_pma_t)w; - - i -= 16; - buf += 16; - pmap += 8; - } -#endif /* STM32_USB_USE_FAST_COPY */ - - while (i > 0) { - uint32_t w; - - w = *buf++; - w |= *buf++ << 8; - *pmap++ = (stm32_usb_pma_t)w; - i -= 2; - } -} - -/** - * @brief Common ISR code, serves the EP-related interrupts. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -static void usb_serve_endpoints(USBDriver *usbp, uint32_t ep) { - size_t n; - uint32_t epr = STM32_USB->EPR[ep]; - const USBEndpointConfig *epcp = usbp->epc[ep]; - - if (epr & EPR_CTR_TX) { - /* IN endpoint, transmission.*/ - USBInEndpointState *isp = epcp->in_state; - - EPR_CLEAR_CTR_TX(ep); - - isp->txcnt += isp->txlast; - n = isp->txsize - isp->txcnt; - if (n > 0) { - /* Transfer not completed, there are more packets to send.*/ - if (n > epcp->in_maxsize) - n = epcp->in_maxsize; - - /* Writes the packet from the defined buffer.*/ - isp->txbuf += isp->txlast; - isp->txlast = n; - usb_packet_write_from_buffer(ep, isp->txbuf, n); - - /* Starting IN operation.*/ - EPR_SET_STAT_TX(ep, EPR_STAT_TX_VALID); - } - else { - /* Transfer completed, invokes the callback.*/ - _usb_isr_invoke_in_cb(usbp, ep); - } - } - if (epr & EPR_CTR_RX) { - /* OUT endpoint, receive.*/ - - EPR_CLEAR_CTR_RX(ep); - - if (epr & EPR_SETUP) { - /* Setup packets handling, setup packets are handled using a - specific callback.*/ - _usb_isr_invoke_setup_cb(usbp, ep); - } - else { - USBOutEndpointState *osp = epcp->out_state; - - /* Reads the packet into the defined buffer.*/ - n = usb_packet_read_to_buffer(ep, osp->rxbuf); - osp->rxbuf += n; - - /* Transaction data updated.*/ - osp->rxcnt += n; - osp->rxsize -= n; - osp->rxpkts -= 1; - - /* The transaction is completed if the specified number of packets - has been received or the current packet is a short packet.*/ - if ((n < epcp->out_maxsize) || (osp->rxpkts == 0)) { - /* Transfer complete, invokes the callback.*/ - _usb_isr_invoke_out_cb(usbp, ep); - } - else { - /* Transfer not complete, there are more packets to receive.*/ - EPR_SET_STAT_RX(ep, EPR_STAT_RX_VALID); - } - } - } -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if STM32_USB_USE_USB1 || defined(__DOXYGEN__) -#if STM32_USB1_HP_NUMBER != STM32_USB1_LP_NUMBER -#if STM32_USB_USE_ISOCHRONOUS -/** - * @brief USB high priority interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_USB1_HP_HANDLER) { - uint32_t istr; - USBDriver *usbp = &USBD1; - - OSAL_IRQ_PROLOGUE(); - - /* Endpoint events handling.*/ - istr = STM32_USB->ISTR; - while (istr & ISTR_CTR) { - usb_serve_endpoints(usbp, istr & ISTR_EP_ID_MASK); - istr = STM32_USB->ISTR; - } - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_USB_USE_ISOCHRONOUS */ -#endif /* STM32_USB1_LP_NUMBER != STM32_USB1_HP_NUMBER */ - -/** - * @brief USB low priority interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_USB1_LP_HANDLER) { - uint32_t istr; - USBDriver *usbp = &USBD1; - - OSAL_IRQ_PROLOGUE(); - - istr = STM32_USB->ISTR; - - /* USB bus reset condition handling.*/ - if (istr & ISTR_RESET) { - STM32_USB->ISTR = ~ISTR_RESET; - - _usb_reset(usbp); - } - - /* USB bus SUSPEND condition handling.*/ - if (istr & ISTR_SUSP) { - STM32_USB->CNTR |= CNTR_FSUSP; -#if STM32_USB_LOW_POWER_ON_SUSPEND - STM32_USB->CNTR |= CNTR_LP_MODE; -#endif - STM32_USB->ISTR = ~ISTR_SUSP; - - _usb_suspend(usbp); - } - - /* USB bus WAKEUP condition handling.*/ - if (istr & ISTR_WKUP) { - uint32_t fnr = STM32_USB->FNR; - if (!(fnr & FNR_RXDP)) { - STM32_USB->CNTR &= ~CNTR_FSUSP; - - _usb_wakeup(usbp); - } -#if STM32_USB_LOW_POWER_ON_SUSPEND - else { - /* Just noise, going back in SUSPEND mode, reference manual 22.4.5, - table 169.*/ - STM32_USB->CNTR |= CNTR_LP_MODE; - } -#endif - STM32_USB->ISTR = ~ISTR_WKUP; - } - - /* SOF handling.*/ - if (istr & ISTR_SOF) { - _usb_isr_invoke_sof_cb(usbp); - STM32_USB->ISTR = ~ISTR_SOF; - } - - /* Endpoint events handling.*/ - while (istr & ISTR_CTR) { - usb_serve_endpoints(usbp, istr & ISTR_EP_ID_MASK); - istr = STM32_USB->ISTR; - } - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_USB_USE_USB1 */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level USB driver initialization. - * - * @notapi - */ -void usb_lld_init(void) { - - /* Driver initialization.*/ - usbObjectInit(&USBD1); -} - -/** - * @brief Configures and activates the USB peripheral. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -void usb_lld_start(USBDriver *usbp) { - - if (usbp->state == USB_STOP) { - /* Clock activation.*/ -#if STM32_USB_USE_USB1 - if (&USBD1 == usbp) { - /* USB clock enabled.*/ - rccEnableUSB(FALSE); - /* Powers up the transceiver while holding the USB in reset state.*/ - STM32_USB->CNTR = CNTR_FRES; - /* Enabling the USB IRQ vectors, this also gives enough time to allow - the transceiver power up (1uS).*/ -#if STM32_USB1_HP_NUMBER != STM32_USB1_LP_NUMBER - nvicEnableVector(STM32_USB1_HP_NUMBER, STM32_USB_USB1_HP_IRQ_PRIORITY); -#endif - nvicEnableVector(STM32_USB1_LP_NUMBER, STM32_USB_USB1_LP_IRQ_PRIORITY); - /* Releases the USB reset.*/ - STM32_USB->CNTR = 0; - } -#endif - /* Reset procedure enforced on driver start.*/ - _usb_reset(usbp); - } -} - -/** - * @brief Deactivates the USB peripheral. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -void usb_lld_stop(USBDriver *usbp) { - - /* If in ready state then disables the USB clock.*/ - if (usbp->state == USB_STOP) { -#if STM32_USB_USE_USB1 - if (&USBD1 == usbp) { -#if STM32_USB1_HP_NUMBER != STM32_USB1_LP_NUMBER - nvicDisableVector(STM32_USB1_HP_NUMBER); -#endif - nvicDisableVector(STM32_USB1_LP_NUMBER); - STM32_USB->CNTR = CNTR_PDWN | CNTR_FRES; - rccDisableUSB(FALSE); - } -#endif - } -} - -/** - * @brief USB low level reset routine. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -void usb_lld_reset(USBDriver *usbp) { - uint32_t cntr; - - /* Post reset initialization.*/ - STM32_USB->BTABLE = BTABLE_ADDR; - STM32_USB->ISTR = 0; - STM32_USB->DADDR = DADDR_EF; - cntr = /*CNTR_ESOFM | */ CNTR_RESETM | CNTR_SUSPM | - CNTR_WKUPM | /*CNTR_ERRM | CNTR_PMAOVRM |*/ CNTR_CTRM; - /* The SOF interrupt is only enabled if a callback is defined for - this service because it is an high rate source.*/ - if (usbp->config->sof_cb != NULL) - cntr |= CNTR_SOFM; - STM32_USB->CNTR = cntr; - - /* Resets the packet memory allocator.*/ - usb_pm_reset(usbp); - - /* EP0 initialization.*/ - usbp->epc[0] = &ep0config; - usb_lld_init_endpoint(usbp, 0); -} - -/** - * @brief Sets the USB address. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -void usb_lld_set_address(USBDriver *usbp) { - - STM32_USB->DADDR = (uint32_t)(usbp->address) | DADDR_EF; -} - -/** - * @brief Enables an endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) { - uint16_t epr; - stm32_usb_descriptor_t *dp; - const USBEndpointConfig *epcp = usbp->epc[ep]; - - /* Setting the endpoint type. Note that isochronous endpoints cannot be - bidirectional because it uses double buffering and both transmit and - receive descriptor fields are used for either direction.*/ - switch (epcp->ep_mode & USB_EP_MODE_TYPE) { - case USB_EP_MODE_TYPE_ISOC: -#if STM32_USB_USE_ISOCHRONOUS - osalDbgAssert((epcp->in_state == NULL) || (epcp->out_state == NULL), - "isochronous EP cannot be IN and OUT"); - epr = EPR_EP_TYPE_ISO; - break; -#else - osalDbgAssert(false, "isochronous support disabled"); -#endif - case USB_EP_MODE_TYPE_BULK: - epr = EPR_EP_TYPE_BULK; - break; - case USB_EP_MODE_TYPE_INTR: - epr = EPR_EP_TYPE_INTERRUPT; - break; - default: - epr = EPR_EP_TYPE_CONTROL; - } - - dp = USB_GET_DESCRIPTOR(ep); - - /* IN endpoint handling.*/ - if (epcp->in_state != NULL) { - dp->TXCOUNT0 = 0; - dp->TXADDR0 = usb_pm_alloc(usbp, epcp->in_maxsize); - -#if STM32_USB_USE_ISOCHRONOUS - if (epr == EPR_EP_TYPE_ISO) { - epr |= EPR_STAT_TX_VALID; - dp->TXCOUNT1 = dp->TXCOUNT0; - dp->TXADDR1 = dp->TXADDR0; /* Both buffers overlapped.*/ - } - else { - epr |= EPR_STAT_TX_NAK; - } -#else - epr |= EPR_STAT_TX_NAK; -#endif - } - - /* OUT endpoint handling.*/ - if (epcp->out_state != NULL) { - uint16_t nblocks; - - /* Endpoint size and address initialization.*/ - if (epcp->out_maxsize > 62) - nblocks = (((((epcp->out_maxsize - 1) | 0x1f) + 1) / 32) << 10) | - 0x8000; - else - nblocks = ((((epcp->out_maxsize - 1) | 1) + 1) / 2) << 10; - dp->RXCOUNT0 = nblocks; - dp->RXADDR0 = usb_pm_alloc(usbp, epcp->out_maxsize); - -#if STM32_USB_USE_ISOCHRONOUS - if (epr == EPR_EP_TYPE_ISO) { - epr |= EPR_STAT_RX_VALID; - dp->RXCOUNT1 = dp->RXCOUNT0; - dp->RXADDR1 = dp->RXADDR0; /* Both buffers overlapped.*/ - } - else { - epr |= EPR_STAT_RX_NAK; - } -#else - epr |= EPR_STAT_RX_NAK; -#endif - } - - /* EPxR register setup.*/ - EPR_SET(ep, epr | ep); - EPR_TOGGLE(ep, epr); -} - -/** - * @brief Disables all the active endpoints except the endpoint zero. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -void usb_lld_disable_endpoints(USBDriver *usbp) { - unsigned i; - - /* Resets the packet memory allocator.*/ - usb_pm_reset(usbp); - - /* Disabling all endpoints.*/ - for (i = 1; i <= USB_ENDOPOINTS_NUMBER; i++) { - EPR_TOGGLE(i, 0); - EPR_SET(i, 0); - } -} - -/** - * @brief Returns the status of an OUT endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @return The endpoint status. - * @retval EP_STATUS_DISABLED The endpoint is not active. - * @retval EP_STATUS_STALLED The endpoint is stalled. - * @retval EP_STATUS_ACTIVE The endpoint is active. - * - * @notapi - */ -usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep) { - - (void)usbp; - switch (STM32_USB->EPR[ep] & EPR_STAT_RX_MASK) { - case EPR_STAT_RX_DIS: - return EP_STATUS_DISABLED; - case EPR_STAT_RX_STALL: - return EP_STATUS_STALLED; - default: - return EP_STATUS_ACTIVE; - } -} - -/** - * @brief Returns the status of an IN endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @return The endpoint status. - * @retval EP_STATUS_DISABLED The endpoint is not active. - * @retval EP_STATUS_STALLED The endpoint is stalled. - * @retval EP_STATUS_ACTIVE The endpoint is active. - * - * @notapi - */ -usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep) { - - (void)usbp; - switch (STM32_USB->EPR[ep] & EPR_STAT_TX_MASK) { - case EPR_STAT_TX_DIS: - return EP_STATUS_DISABLED; - case EPR_STAT_TX_STALL: - return EP_STATUS_STALLED; - default: - return EP_STATUS_ACTIVE; - } -} - -/** - * @brief Reads a setup packet from the dedicated packet buffer. - * @details This function must be invoked in the context of the @p setup_cb - * callback in order to read the received setup packet. - * @pre In order to use this function the endpoint must have been - * initialized as a control endpoint. - * @post The endpoint is ready to accept another packet. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @param[out] buf buffer where to copy the packet data - * - * @notapi - */ -void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) { - stm32_usb_pma_t *pmap; - stm32_usb_descriptor_t *udp; - uint32_t n; - - (void)usbp; - udp = USB_GET_DESCRIPTOR(ep); - pmap = USB_ADDR2PTR(udp->RXADDR0); - for (n = 0; n < 4; n++) { - *(uint16_t *)buf = (uint16_t)*pmap++; - buf += 2; - } -} - -/** - * @brief Starts a receive operation on an OUT endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_start_out(USBDriver *usbp, usbep_t ep) { - USBOutEndpointState *osp = usbp->epc[ep]->out_state; - - /* Transfer initialization.*/ - if (osp->rxsize == 0) /* Special case for zero sized packets.*/ - osp->rxpkts = 1; - else - osp->rxpkts = (uint16_t)((osp->rxsize + usbp->epc[ep]->out_maxsize - 1) / - usbp->epc[ep]->out_maxsize); - - EPR_SET_STAT_RX(ep, EPR_STAT_RX_VALID); -} - -/** - * @brief Starts a transmit operation on an IN endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_start_in(USBDriver *usbp, usbep_t ep) { - size_t n; - USBInEndpointState *isp = usbp->epc[ep]->in_state; - - /* Transfer initialization.*/ - n = isp->txsize; - if (n > (size_t)usbp->epc[ep]->in_maxsize) - n = (size_t)usbp->epc[ep]->in_maxsize; - - isp->txlast = n; - usb_packet_write_from_buffer(ep, isp->txbuf, n); - - EPR_SET_STAT_TX(ep, EPR_STAT_TX_VALID); -} - -/** - * @brief Brings an OUT endpoint in the stalled state. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_stall_out(USBDriver *usbp, usbep_t ep) { - - (void)usbp; - - EPR_SET_STAT_RX(ep, EPR_STAT_RX_STALL); -} - -/** - * @brief Brings an IN endpoint in the stalled state. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_stall_in(USBDriver *usbp, usbep_t ep) { - - (void)usbp; - - EPR_SET_STAT_TX(ep, EPR_STAT_TX_STALL); -} - -/** - * @brief Brings an OUT endpoint in the active state. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_clear_out(USBDriver *usbp, usbep_t ep) { - - (void)usbp; - - /* Makes sure to not put to NAK an endpoint that is already - transferring.*/ - if ((STM32_USB->EPR[ep] & EPR_STAT_RX_MASK) != EPR_STAT_RX_VALID) - EPR_SET_STAT_TX(ep, EPR_STAT_RX_NAK); -} - -/** - * @brief Brings an IN endpoint in the active state. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_clear_in(USBDriver *usbp, usbep_t ep) { - - (void)usbp; - - /* Makes sure to not put to NAK an endpoint that is already - transferring.*/ - if ((STM32_USB->EPR[ep] & EPR_STAT_TX_MASK) != EPR_STAT_TX_VALID) - EPR_SET_STAT_TX(ep, EPR_STAT_TX_NAK); -} - -#endif /* HAL_USE_USB */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/USBv1/usb_lld.h b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/USBv1/usb_lld.h deleted file mode 100644 index 2bce857ae1..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/USBv1/usb_lld.h +++ /dev/null @@ -1,486 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/USBv1/usb_lld.h - * @brief STM32 USB subsystem low level driver header. - * - * @addtogroup USB - * @{ - */ - -#ifndef _USB_LLD_H_ -#define _USB_LLD_H_ - -#if HAL_USE_USB || defined(__DOXYGEN__) - -#include "stm32_usb.h" - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Maximum endpoint address. - */ -#define USB_MAX_ENDPOINTS USB_ENDOPOINTS_NUMBER - -/** - * @brief Status stage handling method. - */ -#define USB_EP0_STATUS_STAGE USB_EP0_STATUS_STAGE_SW - -/** - * @brief This device requires the address change after the status packet. - */ -#define USB_SET_ADDRESS_MODE USB_LATE_SET_ADDRESS - -/** - * @brief Method for set address acknowledge. - */ -#define USB_SET_ADDRESS_ACK_HANDLING USB_SET_ADDRESS_ACK_SW - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief USB1 driver enable switch. - * @details If set to @p TRUE the support for USB1 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_USB_USE_USB1) || defined(__DOXYGEN__) -#define STM32_USB_USE_USB1 FALSE -#endif - -/** - * @brief Enables the USB device low power mode on suspend. - */ -#if !defined(STM32_USB_LOW_POWER_ON_SUSPEND) || defined(__DOXYGEN__) -#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE -#endif - -/** - * @brief USB1 interrupt priority level setting. - */ -#if (!defined(STM32_USB_USB1_HP_IRQ_PRIORITY) && \ - (STM32_USB1_HP_NUMBER != STM32_USB1_LP_NUMBER)) || defined(__DOXYGEN__) -#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 -#endif - -/** - * @brief USB1 interrupt priority level setting. - */ -#if !defined(STM32_USB_USB1_LP_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 -#endif - -/** - * @brief Enables isochronous support. - * @note Isochronous support requires special handling and this makes the - * code size increase significantly. - */ -#if !defined(STM32_USB_USE_ISOCHRONOUS) || defined(__DOXYGEN__) -#define STM32_USB_USE_ISOCHRONOUS FALSE -#endif - -/** - * @brief Use faster copy for packets. - * @note Makes the driver larger. - */ -#if !defined(STM32_USB_USE_FAST_COPY) || defined(__DOXYGEN__) -#define STM32_USB_USE_FAST_COPY FALSE -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_USB_USE_USB1 && !STM32_HAS_USB -#error "USB not present in the selected device" -#endif - -#if !STM32_USB_USE_USB1 -#error "USB driver activated but no USB peripheral assigned" -#endif - -#if STM32_USB_USE_USB1 && \ - (STM32_USB1_HP_NUMBER != STM32_USB1_LP_NUMBER) && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_USB_USB1_HP_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to USB HP" -#endif - -#if STM32_USB_USE_USB1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_USB_USB1_LP_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to USB LP" -#endif - -#if STM32_USBCLK != 48000000 -#error "the USB driver requires a 48MHz clock" -#endif - -#if !defined(STM32_USB1_HP_HANDLER) -#error "STM32_USB1_HP_HANDLER not defined" -#endif - -#if !defined(STM32_USB1_HP_NUMBER) -#error "STM32_USB1_HP_NUMBER not defined" -#endif - -#if !defined(STM32_USB1_LP_HANDLER) -#error "STM32_USB1_LP_HANDLER not defined" -#endif - -#if !defined(STM32_USB1_LP_NUMBER) -#error "STM32_USB1_LP_NUMBER not defined" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of an IN endpoint state structure. - */ -typedef struct { - /** - * @brief Requested transmit transfer size. - */ - size_t txsize; - /** - * @brief Transmitted bytes so far. - */ - size_t txcnt; - /** - * @brief Pointer to the transmission linear buffer. - */ - const uint8_t *txbuf; -#if (USB_USE_WAIT == TRUE) || defined(__DOXYGEN__) - /** - * @brief Waiting thread. - */ - thread_reference_t thread; -#endif - /* End of the mandatory fields.*/ - /** - * @brief Size of the last transmitted packet. - */ - size_t txlast; -} USBInEndpointState; - -/** - * @brief Type of an OUT endpoint state structure. - */ -typedef struct { - /** - * @brief Requested receive transfer size. - */ - size_t rxsize; - /** - * @brief Received bytes so far. - */ - size_t rxcnt; - /** - * @brief Pointer to the receive linear buffer. - */ - uint8_t *rxbuf; -#if (USB_USE_WAIT == TRUE) || defined(__DOXYGEN__) - /** - * @brief Waiting thread. - */ - thread_reference_t thread; -#endif - /* End of the mandatory fields.*/ - /** - * @brief Number of packets to receive. - */ - uint16_t rxpkts; -} USBOutEndpointState; - -/** - * @brief Type of an USB endpoint configuration structure. - * @note Platform specific restrictions may apply to endpoints. - */ -typedef struct { - /** - * @brief Type and mode of the endpoint. - */ - uint32_t ep_mode; - /** - * @brief Setup packet notification callback. - * @details This callback is invoked when a setup packet has been - * received. - * @post The application must immediately call @p usbReadPacket() in - * order to access the received packet. - * @note This field is only valid for @p USB_EP_MODE_TYPE_CTRL - * endpoints, it should be set to @p NULL for other endpoint - * types. - */ - usbepcallback_t setup_cb; - /** - * @brief IN endpoint notification callback. - * @details This field must be set to @p NULL if callback is not required. - */ - usbepcallback_t in_cb; - /** - * @brief OUT endpoint notification callback. - * @details This field must be set to @p NULL if callback is not required. - */ - usbepcallback_t out_cb; - /** - * @brief IN endpoint maximum packet size. - * @details This field must be set to zero if the IN endpoint is not used. - */ - uint16_t in_maxsize; - /** - * @brief OUT endpoint maximum packet size. - * @details This field must be set to zero if the OUT endpoint is not used. - */ - uint16_t out_maxsize; - /** - * @brief @p USBEndpointState associated to the IN endpoint. - * @details This field must be set to @p NULL if the IN endpoint is not - * used. - */ - USBInEndpointState *in_state; - /** - * @brief @p USBEndpointState associated to the OUT endpoint. - * @details This field must be set to @p NULL if the OUT endpoint is not - * used. - */ - USBOutEndpointState *out_state; - /* End of the mandatory fields.*/ - /** - * @brief Reserved field, not currently used. - * @note Initialize this field to 1 in order to be forward compatible. - */ - uint16_t ep_buffers; - /** - * @brief Pointer to a buffer for setup packets. - * @details Setup packets require a dedicated 8-bytes buffer, set this - * field to @p NULL for non-control endpoints. - */ - uint8_t *setup_buf; -} USBEndpointConfig; - -/** - * @brief Type of an USB driver configuration structure. - */ -typedef struct { - /** - * @brief USB events callback. - * @details This callback is invoked when an USB driver event is registered. - */ - usbeventcb_t event_cb; - /** - * @brief Device GET_DESCRIPTOR request callback. - * @note This callback is mandatory and cannot be set to @p NULL. - */ - usbgetdescriptor_t get_descriptor_cb; - /** - * @brief Requests hook callback. - * @details This hook allows to be notified of standard requests or to - * handle non standard requests. - */ - usbreqhandler_t requests_hook_cb; - /** - * @brief Start Of Frame callback. - */ - usbcallback_t sof_cb; - /* End of the mandatory fields.*/ -} USBConfig; - -/** - * @brief Structure representing an USB driver. - */ -struct USBDriver { - /** - * @brief Driver state. - */ - usbstate_t state; - /** - * @brief Current configuration data. - */ - const USBConfig *config; - /** - * @brief Bit map of the transmitting IN endpoints. - */ - uint16_t transmitting; - /** - * @brief Bit map of the receiving OUT endpoints. - */ - uint16_t receiving; - /** - * @brief Active endpoints configurations. - */ - const USBEndpointConfig *epc[USB_MAX_ENDPOINTS + 1]; - /** - * @brief Fields available to user, it can be used to associate an - * application-defined handler to an IN endpoint. - * @note The base index is one, the endpoint zero does not have a - * reserved element in this array. - */ - void *in_params[USB_MAX_ENDPOINTS]; - /** - * @brief Fields available to user, it can be used to associate an - * application-defined handler to an OUT endpoint. - * @note The base index is one, the endpoint zero does not have a - * reserved element in this array. - */ - void *out_params[USB_MAX_ENDPOINTS]; - /** - * @brief Endpoint 0 state. - */ - usbep0state_t ep0state; - /** - * @brief Next position in the buffer to be transferred through endpoint 0. - */ - uint8_t *ep0next; - /** - * @brief Number of bytes yet to be transferred through endpoint 0. - */ - size_t ep0n; - /** - * @brief Endpoint 0 end transaction callback. - */ - usbcallback_t ep0endcb; - /** - * @brief Setup packet buffer. - */ - uint8_t setup[8]; - /** - * @brief Current USB device status. - */ - uint16_t status; - /** - * @brief Assigned USB address. - */ - uint8_t address; - /** - * @brief Current USB device configuration. - */ - uint8_t configuration; - /** - * @brief State of the driver when a suspend happened. - */ - usbstate_t saved_state; -#if defined(USB_DRIVER_EXT_FIELDS) - USB_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the next address in the packet memory. - */ - uint32_t pmnext; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Returns the current frame number. - * - * @param[in] usbp pointer to the @p USBDriver object - * @return The current frame number. - * - * @notapi - */ -#define usb_lld_get_frame_number(usbp) (STM32_USB->FNR & FNR_FN_MASK) - -/** - * @brief Returns the exact size of a receive transaction. - * @details The received size can be different from the size specified in - * @p usbStartReceiveI() because the last packet could have a size - * different from the expected one. - * @pre The OUT endpoint must have been configured in transaction mode - * in order to use this function. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @return Received data size. - * - * @notapi - */ -#define usb_lld_get_transaction_size(usbp, ep) \ - ((usbp)->epc[ep]->out_state->rxcnt) - -#if STM32_USB_HAS_BCDR || defined(__DOXYGEN__) -/** - * @brief Connects the USB device. - * - * @api - */ -#if !defined(usb_lld_connect_bus) -#define usb_lld_connect_bus(usbp) (STM32_USB->BCDR |= USB_BCDR_DPPU) -#endif - -/** - * @brief Disconnect the USB device. - * - * @api - */ -#if !defined(usb_lld_disconnect_bus) -#define usb_lld_disconnect_bus(usbp) (STM32_USB->BCDR &= ~USB_BCDR_DPPU) -#endif -#endif /* STM32_USB_HAS_BCDR */ - -#if defined(STM32L1XX) -#if !defined(usb_lld_connect_bus) -#define usb_lld_connect_bus(usbp) (SYSCFG->PMC |= SYSCFG_PMC_USB_PU) -#endif - -#if !defined(usb_lld_disconnect_bus) -#define usb_lld_disconnect_bus(usbp) (SYSCFG->PMC &= ~SYSCFG_PMC_USB_PU) -#endif -#endif /* STM32L1XX */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_USB_USE_USB1 && !defined(__DOXYGEN__) -extern USBDriver USBD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void usb_lld_init(void); - void usb_lld_start(USBDriver *usbp); - void usb_lld_stop(USBDriver *usbp); - void usb_lld_reset(USBDriver *usbp); - void usb_lld_set_address(USBDriver *usbp); - void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep); - void usb_lld_disable_endpoints(USBDriver *usbp); - usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep); - usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep); - void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf); - void usb_lld_start_out(USBDriver *usbp, usbep_t ep); - void usb_lld_start_in(USBDriver *usbp, usbep_t ep); - void usb_lld_stall_out(USBDriver *usbp, usbep_t ep); - void usb_lld_stall_in(USBDriver *usbp, usbep_t ep); - void usb_lld_clear_out(USBDriver *usbp, usbep_t ep); - void usb_lld_clear_in(USBDriver *usbp, usbep_t ep); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_USB */ - -#endif /* _USB_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/xWDGv1/wdg_lld.c b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/xWDGv1/wdg_lld.c deleted file mode 100644 index 5d09841ff3..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/xWDGv1/wdg_lld.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file wdg_lld.c - * @brief WDG Driver subsystem low level driver source. - * - * @addtogroup WDG - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_WDG == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define KR_KEY_RELOAD 0xAAAAU -#define KR_KEY_ENABLE 0xCCCCU -#define KR_KEY_WRITE 0x5555U -#define KR_KEY_PROTECT 0x0000U - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -#if STM32_WDG_USE_IWDG || defined(__DOXYGEN__) -WDGDriver WDGD1; -#endif - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level WDG driver initialization. - * - * @notapi - */ -void wdg_lld_init(void) { - -#if STM32_WDG_USE_IWDG - WDGD1.state = WDG_STOP; - WDGD1.wdg = IWDG; -#endif -} - -/** - * @brief Configures and activates the WDG peripheral. - * - * @param[in] wdgp pointer to the @p WDGDriver object - * - * @notapi - */ -void wdg_lld_start(WDGDriver *wdgp) { - -#if STM32_IWDG_IS_WINDOWED - /* Enable IWDG and unlock for write.*/ - wdgp->wdg->KR = KR_KEY_ENABLE; - wdgp->wdg->KR = KR_KEY_WRITE; - - /* Write configuration.*/ - wdgp->wdg->PR = wdgp->config->pr; - wdgp->wdg->RLR = wdgp->config->rlr; - while (wdgp->wdg->SR != 0) - ; - - /* This also triggers a refresh.*/ - wdgp->wdg->WINR = wdgp->config->winr; -#else - /* Unlock IWDG.*/ - wdgp->wdg->KR = KR_KEY_WRITE; - - /* Write configuration.*/ - while (wdgp->wdg->SR != 0) - ; - wdgp->wdg->PR = wdgp->config->pr; - wdgp->wdg->RLR = wdgp->config->rlr; - - /* Start operations.*/ - wdgp->wdg->KR = KR_KEY_RELOAD; - wdgp->wdg->KR = KR_KEY_ENABLE; -#endif -} - -/** - * @brief Deactivates the WDG peripheral. - * - * @param[in] wdgp pointer to the @p WDGDriver object - * - * @api - */ -void wdg_lld_stop(WDGDriver *wdgp) { - - osalDbgAssert(wdgp->state == WDG_STOP, - "IWDG cannot be stopped once activated"); -} - -/** - * @brief Reloads WDG's counter. - * - * @param[in] wdgp pointer to the @p WDGDriver object - * - * @notapi - */ -void wdg_lld_reset(WDGDriver * wdgp) { - - wdgp->wdg->KR = KR_KEY_RELOAD; -} - -#endif /* HAL_USE_WDG == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/xWDGv1/wdg_lld.h b/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/xWDGv1/wdg_lld.h deleted file mode 100644 index f90290d403..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/LLD/xWDGv1/wdg_lld.h +++ /dev/null @@ -1,183 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file wdg_lld.h - * @brief WDG Driver subsystem low level driver header. - * - * @addtogroup WDG - * @{ - */ - -#ifndef _WDG_LLD_H_ -#define _WDG_LLD_H_ - -#if (HAL_USE_WDG == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name RLR register definitions - * @{ - */ -#define STM32_IWDG_RL_MASK (0x00000FFF << 0) -#define STM32_IWDG_RL(n) ((n) << 0) -/** @} */ - -/** - * @name PR register definitions - * @{ - */ -#define STM32_IWDG_PR_MASK (7 << 0) -#define STM32_IWDG_PR_4 0U -#define STM32_IWDG_PR_8 1U -#define STM32_IWDG_PR_16 2U -#define STM32_IWDG_PR_32 3U -#define STM32_IWDG_PR_64 4U -#define STM32_IWDG_PR_128 5U -#define STM32_IWDG_PR_256 6U -/** @} */ - -/** - * @name WINR register definitions - * @{ - */ -#define STM32_IWDG_WIN_MASK (0x00000FFF << 0) -#define STM32_IWDG_WIN(n) ((n) << 0) -#define STM32_IWDG_WIN_DISABLED STM32_IWDG_WIN(0x00000FFF) -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief IWDG driver enable switch. - * @details If set to @p TRUE the support for IWDG is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_WDG_USE_IWDG) || defined(__DOXYGEN__) -#define STM32_WDG_USE_IWDG FALSE -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_WDG_USE_IWDG && !STM32_HAS_IWDG -#error "IWDG not present in the selected device" -#endif - -#if !STM32_WDG_USE_IWDG -#error "WDG driver activated but no xWDG peripheral assigned" -#endif - -#if !defined(STM32_LSI_ENABLED) -#error "STM32_LSI_ENABLED not defined" -#endif - -#if (STM32_WDG_USE_IWDG == TRUE) && (STM32_LSI_ENABLED == FALSE) -#error "IWDG requires LSI clock" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a structure representing an WDG driver. - */ -typedef struct WDGDriver WDGDriver; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief Configuration of the IWDG_PR register. - * @details See the STM32 reference manual for details. - */ - uint32_t pr; - /** - * @brief Configuration of the IWDG_RLR register. - * @details See the STM32 reference manual for details. - */ - uint32_t rlr; -#if STM32_IWDG_IS_WINDOWED || defined(__DOXYGEN__) - /** - * @brief Configuration of the IWDG_WINR register. - * @details See the STM32 reference manual for details. - * @note This field is not present in F1, F2, F4, L1 sub-families. - */ - uint32_t winr; -#endif -} WDGConfig; - -/** - * @brief Structure representing an WDG driver. - */ -struct WDGDriver { - /** - * @brief Driver state. - */ - wdgstate_t state; - /** - * @brief Current configuration data. - */ - const WDGConfig *config; - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the IWDG registers block. - */ - IWDG_TypeDef *wdg; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_WDG_USE_IWDG && !defined(__DOXYGEN__) -extern WDGDriver WDGD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void wdg_lld_init(void); - void wdg_lld_start(WDGDriver *wdgp); - void wdg_lld_stop(WDGDriver *wdgp); - void wdg_lld_reset(WDGDriver *wdgp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_WDG == TRUE */ - -#endif /* _WDG_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/STM32F4xx/ext_lld_isr.c b/firmware/ChibiOS_16/os/hal/ports/STM32/STM32F4xx/ext_lld_isr.c deleted file mode 100644 index d291dee90e..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/STM32F4xx/ext_lld_isr.c +++ /dev/null @@ -1,407 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F4xx/ext_lld_isr.c - * @brief STM32F4xx/STM32F2xx EXT subsystem low level driver ISR code. - * - * @addtogroup EXT - * @{ - */ - -#include "hal.h" - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -#include "ext_lld_isr.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief EXTI[0] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector58) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 0); - EXTI->PR = pr; - if (pr & (1U << 0)) - EXTD1.config->channels[0].cb(&EXTD1, 0); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[1] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector5C) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 1); - EXTI->PR = pr; - if (pr & (1U << 1)) - EXTD1.config->channels[1].cb(&EXTD1, 1); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[2] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector60) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 2); - EXTI->PR = pr; - if (pr & (1U << 2)) - EXTD1.config->channels[2].cb(&EXTD1, 2); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[3] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector64) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 3); - EXTI->PR = pr; - if (pr & (1U << 3)) - EXTD1.config->channels[3].cb(&EXTD1, 3); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[4] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector68) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 4); - EXTI->PR = pr; - if (pr & (1U << 4)) - EXTD1.config->channels[4].cb(&EXTD1, 4); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[5]...EXTI[9] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector9C) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & ((1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) | - (1U << 9)); - EXTI->PR = pr; - if (pr & (1U << 5)) - EXTD1.config->channels[5].cb(&EXTD1, 5); - if (pr & (1U << 6)) - EXTD1.config->channels[6].cb(&EXTD1, 6); - if (pr & (1U << 7)) - EXTD1.config->channels[7].cb(&EXTD1, 7); - if (pr & (1U << 8)) - EXTD1.config->channels[8].cb(&EXTD1, 8); - if (pr & (1U << 9)) - EXTD1.config->channels[9].cb(&EXTD1, 9); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[10]...EXTI[15] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(VectorE0) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & ((1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) | - (1U << 14) | (1U << 15)); - EXTI->PR = pr; - if (pr & (1U << 10)) - EXTD1.config->channels[10].cb(&EXTD1, 10); - if (pr & (1U << 11)) - EXTD1.config->channels[11].cb(&EXTD1, 11); - if (pr & (1U << 12)) - EXTD1.config->channels[12].cb(&EXTD1, 12); - if (pr & (1U << 13)) - EXTD1.config->channels[13].cb(&EXTD1, 13); - if (pr & (1U << 14)) - EXTD1.config->channels[14].cb(&EXTD1, 14); - if (pr & (1U << 15)) - EXTD1.config->channels[15].cb(&EXTD1, 15); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[16] interrupt handler (PVD). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector44) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 16); - EXTI->PR = pr; - if (pr & (1U << 16)) - EXTD1.config->channels[16].cb(&EXTD1, 16); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[17] interrupt handler (RTC_ALARM). - * - * @isr - */ -OSAL_IRQ_HANDLER(VectorE4) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 17); - EXTI->PR = pr; - if (pr & (1U << 17)) - EXTD1.config->channels[17].cb(&EXTD1, 17); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[18] interrupt handler (OTG_FS_WKUP). - * - * @isr - */ -OSAL_IRQ_HANDLER(VectorE8) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 18); - EXTI->PR = pr; - if (pr & (1U << 18)) - EXTD1.config->channels[18].cb(&EXTD1, 18); - - OSAL_IRQ_EPILOGUE(); -} - -#if STM32_HAS_ETH || defined(__DOXYGEN__) -/** - * @brief EXTI[19] interrupt handler (ETH_WKUP). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector138) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 19); - EXTI->PR = pr; - if (pr & (1U << 19)) - EXTD1.config->channels[19].cb(&EXTD1, 19); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_HAS_ETH */ - -#if STM32_HAS_OTG2 || defined(__DOXYGEN__) -/** - * @brief EXTI[20] interrupt handler (OTG_HS_WKUP). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector170) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 20); - EXTI->PR = pr; - if (pr & (1U << 20)) - EXTD1.config->channels[20].cb(&EXTD1, 20); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_HAS_OTG2 */ - -#if !defined(STM32F401xx) -/** - * @brief EXTI[21] interrupt handler (TAMPER_STAMP). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector48) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 21); - EXTI->PR = pr; - if (pr & (1U << 21)) - EXTD1.config->channels[21].cb(&EXTD1, 21); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* !defined(STM32F401xx) */ - -/** - * @brief EXTI[22] interrupt handler (RTC_WKUP). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector4C) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 22); - EXTI->PR = pr; - if (pr & (1U << 22)) - EXTD1.config->channels[22].cb(&EXTD1, 22); - - OSAL_IRQ_EPILOGUE(); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Enables EXTI IRQ sources. - * - * @notapi - */ -void ext_lld_exti_irq_enable(void) { - - nvicEnableVector(EXTI0_IRQn, STM32_EXT_EXTI0_IRQ_PRIORITY); - nvicEnableVector(EXTI1_IRQn, STM32_EXT_EXTI1_IRQ_PRIORITY); - nvicEnableVector(EXTI2_IRQn, STM32_EXT_EXTI2_IRQ_PRIORITY); - nvicEnableVector(EXTI3_IRQn, STM32_EXT_EXTI3_IRQ_PRIORITY); - nvicEnableVector(EXTI4_IRQn, STM32_EXT_EXTI4_IRQ_PRIORITY); - nvicEnableVector(EXTI9_5_IRQn, STM32_EXT_EXTI5_9_IRQ_PRIORITY); - nvicEnableVector(EXTI15_10_IRQn, STM32_EXT_EXTI10_15_IRQ_PRIORITY); - nvicEnableVector(PVD_IRQn, STM32_EXT_EXTI16_IRQ_PRIORITY); - nvicEnableVector(RTC_Alarm_IRQn, STM32_EXT_EXTI17_IRQ_PRIORITY); - nvicEnableVector(OTG_FS_WKUP_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY); -#if STM32_HAS_ETH - nvicEnableVector(ETH_WKUP_IRQn, STM32_EXT_EXTI19_IRQ_PRIORITY); -#endif -#if STM32_HAS_OTG2 - nvicEnableVector(OTG_HS_WKUP_IRQn, STM32_EXT_EXTI20_IRQ_PRIORITY); -#endif -#if !defined(STM32F401xx) - nvicEnableVector(TAMP_STAMP_IRQn, STM32_EXT_EXTI21_IRQ_PRIORITY); -#endif /* !defined(STM32F401xx) */ - nvicEnableVector(RTC_WKUP_IRQn, STM32_EXT_EXTI22_IRQ_PRIORITY); -} - -/** - * @brief Disables EXTI IRQ sources. - * - * @notapi - */ -void ext_lld_exti_irq_disable(void) { - - nvicDisableVector(EXTI0_IRQn); - nvicDisableVector(EXTI1_IRQn); - nvicDisableVector(EXTI2_IRQn); - nvicDisableVector(EXTI3_IRQn); - nvicDisableVector(EXTI4_IRQn); - nvicDisableVector(EXTI9_5_IRQn); - nvicDisableVector(EXTI15_10_IRQn); - nvicDisableVector(PVD_IRQn); - nvicDisableVector(RTC_Alarm_IRQn); - nvicDisableVector(OTG_FS_WKUP_IRQn); -#if STM32_HAS_ETH - nvicDisableVector(ETH_WKUP_IRQn); -#endif -#if STM32_HAS_OTG2 - nvicDisableVector(OTG_HS_WKUP_IRQn); -#endif -#if !defined(STM32F401xx) - nvicDisableVector(TAMP_STAMP_IRQn); -#endif /* !defined(STM32F401xx) */ - nvicDisableVector(RTC_WKUP_IRQn); -} - -#endif /* HAL_USE_EXT */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/STM32F4xx/ext_lld_isr.h b/firmware/ChibiOS_16/os/hal/ports/STM32/STM32F4xx/ext_lld_isr.h deleted file mode 100644 index 8915e7595b..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/STM32F4xx/ext_lld_isr.h +++ /dev/null @@ -1,170 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F4xx/ext_lld_isr.h - * @brief STM32F4xx/STM32F2xx EXT subsystem low level driver ISR header. - * - * @addtogroup EXT - * @{ - */ - -#ifndef _EXT_LLD_ISR_H_ -#define _EXT_LLD_ISR_H_ - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief EXTI0 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI1 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI2 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI3 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI4 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI9..5 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI5_9_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI15..10 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI10_15_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI16 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI17 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI18 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI18_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI19 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI19_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI20 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI20_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI21 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI21_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI21_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI22 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI22_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI22_IRQ_PRIORITY 6 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void ext_lld_exti_irq_enable(void); - void ext_lld_exti_irq_disable(void); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_EXT */ - -#endif /* _EXT_LLD_ISR_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/STM32F4xx/hal_lld.c b/firmware/ChibiOS_16/os/hal/ports/STM32/STM32F4xx/hal_lld.c deleted file mode 100644 index 06ac23f39a..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/STM32F4xx/hal_lld.c +++ /dev/null @@ -1,278 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F4xx/hal_lld.c - * @brief STM32F4xx/STM32F2xx HAL subsystem low level driver source. - * - * @addtogroup HAL - * @{ - */ - -#include "hal.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief CMSIS system core clock variable. - * @note It is declared in system_stm32f4xx.h. - */ -uint32_t SystemCoreClock = STM32_HCLK; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Initializes the backup domain. - * @note WARNING! Changing clock source impossible without resetting - * of the whole BKP domain. - */ -static void hal_lld_backup_domain_init(void) { - - /* Backup domain access enabled and left open.*/ - PWR->CR |= PWR_CR_DBP; - - /* Reset BKP domain if different clock source selected.*/ - if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) { - /* Backup domain reset.*/ - RCC->BDCR = RCC_BDCR_BDRST; - RCC->BDCR = 0; - } - -#if STM32_LSE_ENABLED -#if defined(STM32_LSE_BYPASS) - /* LSE Bypass.*/ - RCC->BDCR |= RCC_BDCR_LSEON | RCC_BDCR_LSEBYP; -#else - /* No LSE Bypass.*/ - RCC->BDCR |= RCC_BDCR_LSEON; -#endif - while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) - ; /* Waits until LSE is stable. */ -#endif - -#if HAL_USE_RTC - /* If the backup domain hasn't been initialized yet then proceed with - initialization.*/ - if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) { - /* Selects clock source.*/ - RCC->BDCR |= STM32_RTCSEL; - - /* RTC clock enabled.*/ - RCC->BDCR |= RCC_BDCR_RTCEN; - } -#endif /* HAL_USE_RTC */ - -#if STM32_BKPRAM_ENABLE - rccEnableBKPSRAM(false); - - PWR->CSR |= PWR_CSR_BRE; - while ((PWR->CSR & PWR_CSR_BRR) == 0) - ; /* Waits until the regulator is stable */ -#else - PWR->CSR &= ~PWR_CSR_BRE; -#endif /* STM32_BKPRAM_ENABLE */ -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level HAL driver initialization. - * - * @notapi - */ -void hal_lld_init(void) { - - /* Reset of all peripherals. AHB3 is not reseted because it could have - been initialized in the board initialization file (board.c).*/ - rccResetAHB1(~0); - rccResetAHB2(~0); - rccResetAPB1(~RCC_APB1RSTR_PWRRST); - rccResetAPB2(~0); - - /* PWR clock enabled.*/ - rccEnablePWRInterface(FALSE); - - /* Initializes the backup domain.*/ - hal_lld_backup_domain_init(); - -#if defined(STM32_DMA_REQUIRED) - dmaInit(); -#endif - - /* Programmable voltage detector enable.*/ -#if STM32_PVD_ENABLE - PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK); -#endif /* STM32_PVD_ENABLE */ -} - -/** - * @brief STM32F2xx clocks and PLL initialization. - * @note All the involved constants come from the file @p board.h. - * @note This function should be invoked just after the system reset. - * - * @special - */ -void stm32_clock_init(void) { - -#if !STM32_NO_INIT - /* PWR clock enable.*/ - RCC->APB1ENR = RCC_APB1ENR_PWREN; - - /* PWR initialization.*/ -#if defined(STM32F4XX) || defined(__DOXYGEN__) - PWR->CR = STM32_VOS; -#else - PWR->CR = 0; -#endif - - /* HSI setup, it enforces the reset situation in order to handle possible - problems with JTAG probes and re-initializations.*/ - RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */ - while (!(RCC->CR & RCC_CR_HSIRDY)) - ; /* Wait until HSI is stable. */ - - /* HSI is selected as new source without touching the other fields in - CFGR. Clearing the register has to be postponed after HSI is the - new source.*/ - RCC->CFGR &= ~RCC_CFGR_SW; /* Reset SW */ - RCC->CFGR |= RCC_CFGR_SWS_HSI; /* Select HSI as internal*/ - while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) - ; /* Wait until HSI is selected. */ - - /* Registers finally cleared to reset values.*/ - RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */ - RCC->CFGR = 0; /* CFGR reset value. */ - -#if STM32_HSE_ENABLED - /* HSE activation.*/ -#if defined(STM32_HSE_BYPASS) - /* HSE Bypass.*/ - RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP; -#else - /* No HSE Bypass.*/ - RCC->CR |= RCC_CR_HSEON; -#endif - while ((RCC->CR & RCC_CR_HSERDY) == 0) - ; /* Waits until HSE is stable. */ -#endif - -#if STM32_LSI_ENABLED - /* LSI activation.*/ - RCC->CSR |= RCC_CSR_LSION; - while ((RCC->CSR & RCC_CSR_LSIRDY) == 0) - ; /* Waits until LSI is stable. */ -#endif - -#if STM32_ACTIVATE_PLL - /* PLL activation.*/ - RCC->PLLCFGR = STM32_PLLQ | STM32_PLLSRC | STM32_PLLP | STM32_PLLN | - STM32_PLLM; - RCC->CR |= RCC_CR_PLLON; - - /* Synchronization with voltage regulator stabilization.*/ -#if defined(STM32F4XX) - while ((PWR->CSR & PWR_CSR_VOSRDY) == 0) - ; /* Waits until power regulator is stable. */ - -#if STM32_OVERDRIVE_REQUIRED - /* Overdrive activation performed after activating the PLL in order to save - time as recommended in RM in "Entering Over-drive mode" paragraph.*/ - PWR->CR |= PWR_CR_ODEN; - while (!(PWR->CSR & PWR_CSR_ODRDY)) - ; - PWR->CR |= PWR_CR_ODSWEN; - while (!(PWR->CSR & PWR_CSR_ODSWRDY)) - ; -#endif /* STM32_OVERDRIVE_REQUIRED */ -#endif /* defined(STM32F4XX) */ - - /* Waiting for PLL lock.*/ - while (!(RCC->CR & RCC_CR_PLLRDY)) - ; -#endif /* STM32_OVERDRIVE_REQUIRED */ - -#if STM32_ACTIVATE_PLLI2S - /* PLLI2S activation.*/ - RCC->PLLI2SCFGR = STM32_PLLI2SR | STM32_PLLI2SN; - RCC->CR |= RCC_CR_PLLI2SON; - - /* Waiting for PLL lock.*/ - while (!(RCC->CR & RCC_CR_PLLI2SRDY)) - ; -#endif - -#if STM32_ACTIVATE_PLLSAI - /* PLLSAI activation.*/ - RCC->PLLSAICFGR = STM32_PLLSAIN | STM32_PLLSAIR | STM32_PLLSAIQ; - RCC->DCKCFGR = (RCC->DCKCFGR & ~RCC_DCKCFGR_PLLSAIDIVR) | STM32_PLLSAIR_POST; - RCC->CR |= RCC_CR_PLLSAION; - - /* Waiting for PLL lock.*/ - while (!(RCC->CR & RCC_CR_PLLSAIRDY)) - ; -#endif - - /* Other clock-related settings (dividers, MCO etc).*/ - RCC->CFGR = STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL | - STM32_I2SSRC | STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | - STM32_HPRE; - - /* Flash setup.*/ -#if defined(STM32_USE_REVISION_A_FIX) - /* Some old revisions of F4x MCUs randomly crashes with compiler - optimizations enabled AND flash caches enabled. */ - if ((DBGMCU->IDCODE == 0x20006411) && (SCB->CPUID == 0x410FC241)) - FLASH->ACR = FLASH_ACR_PRFTEN | STM32_FLASHBITS; - else - FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | - FLASH_ACR_DCEN | STM32_FLASHBITS; -#else - FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | - FLASH_ACR_DCEN | STM32_FLASHBITS; -#endif - - /* Switching to the configured clock source if it is different from HSI.*/ -#if (STM32_SW != STM32_SW_HSI) - RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */ - while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2)) - ; -#endif -#endif /* STM32_NO_INIT */ - - /* SYSCFG clock enabled here because it is a multi-functional unit shared - among multiple drivers.*/ - rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE); -} - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/STM32F4xx/hal_lld.h b/firmware/ChibiOS_16/os/hal/ports/STM32/STM32F4xx/hal_lld.h deleted file mode 100644 index df714762ac..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/STM32F4xx/hal_lld.h +++ /dev/null @@ -1,1552 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F4xx/hal_lld.h - * @brief STM32F4xx/STM32F2xx HAL subsystem low level driver header. - * @pre This module requires the following macros to be defined in the - * @p board.h file: - * - STM32_LSECLK. - * - STM32_LSE_BYPASS (optionally). - * - STM32_HSECLK. - * - STM32_HSE_BYPASS (optionally). - * - STM32_VDD (as hundredths of Volt). - * . - * One of the following macros must also be defined: - * - STM32F2XX for High-performance STM32 F-2 devices. - * - STM32F405xx, STM32F415xx, STM32F407xx, STM32F417xx for - * High-performance STM32 F-4 devices. - * - STM32F427xx, STM32F437xx, STM32F429xx, STM32F439xx for - * High-performance STM32 F-4 devices. - * - STM32F401xC, STM32F401xE for High-performance STM32 F-4 devices. - * - STM32F411xE for High-performance STM32 F-4 devices. - * - STM32F446xx for High-performance STM32 F-4 devices. - * . - * - * @addtogroup HAL - * @{ - */ - -#ifndef _HAL_LLD_H_ -#define _HAL_LLD_H_ - -#include "stm32_registry.h" - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Defines the support for realtime counters in the HAL. - */ -#define HAL_IMPLEMENTS_COUNTERS TRUE - -/** - * @name Platform identification macros - * @{ - */ -#if defined(STM32F439xx) || defined(__DOXYGEN__) -#define PLATFORM_NAME "STM32F439 High Performance with DSP and FPU" - -#elif defined(STM32F446xx) -#define PLATFORM_NAME "STM32F446 High Performance with DSP and FPU" - -#elif defined(STM32F429xx) -#define PLATFORM_NAME "STM32F429 High Performance with DSP and FPU" - -#elif defined(STM32F437xx) -#define PLATFORM_NAME "STM32F437 High Performance with DSP and FPU" - -#elif defined(STM32F427xx) -#define PLATFORM_NAME "STM32F427 High Performance with DSP and FPU" - -#elif defined(STM32F405xx) -#define PLATFORM_NAME "STM32F405 High Performance with DSP and FPU" - -#elif defined(STM32F415xx) -#define PLATFORM_NAME "STM32F415 High Performance with DSP and FPU" - -#elif defined(STM32F407xx) -#define PLATFORM_NAME "STM32F407 High Performance with DSP and FPU" - -#elif defined(STM32F417xx) -#define PLATFORM_NAME "STM32F417 High Performance with DSP and FPU" - -#elif defined(STM32F401xC) -#define PLATFORM_NAME "STM32F401xC High Performance with DSP and FPU" - -#elif defined(STM32F401xE) -#define PLATFORM_NAME "STM32F401xE High Performance with DSP and FPU" - -#elif defined(STM32F411xE) -#define PLATFORM_NAME "STM32F411xE High Performance with DSP and FPU" - -#elif defined(STM32F205xx) -#define PLATFORM_NAME "STM32F405 High Performance" - -#elif defined(STM32F215xx) -#define PLATFORM_NAME "STM32F415 High Performance" - -#elif defined(STM32F207xx) -#define PLATFORM_NAME "STM32F407 High Performance" - -#elif defined(STM32F217xx) -#define PLATFORM_NAME "STM32F417 High Performance" - -#else -#error "STM32F2xx/F4xx device not specified" -#endif -/** @} */ - -/** - * @name Absolute Maximum Ratings - * @{ - */ -#if defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F446xx) || defined(__DOXYGEN__) -/** - * @brief Absolute maximum system clock. - */ -#define STM32_SYSCLK_MAX 180000000 - -/** - * @brief Maximum HSE clock frequency. - */ -#define STM32_HSECLK_MAX 26000000 - -/** - * @brief Maximum HSE clock frequency using an external source. - */ -#define STM32_HSECLK_BYP_MAX 50000000 - -/** - * @brief Minimum HSE clock frequency. - */ -#define STM32_HSECLK_MIN 4000000 - -/** - * @brief Minimum HSE clock frequency. - */ -#define STM32_HSECLK_BYP_MIN 1000000 - -/** - * @brief Maximum LSE clock frequency. - */ -#define STM32_LSECLK_MAX 32768 - -/** - * @brief Maximum LSE clock frequency. - */ -#define STM32_LSECLK_BYP_MAX 1000000 - -/** - * @brief Minimum LSE clock frequency. - */ -#define STM32_LSECLK_MIN 32768 - -/** - * @brief Maximum PLLs input clock frequency. - */ -#define STM32_PLLIN_MAX 2100000 - -/** - * @brief Minimum PLLs input clock frequency. - */ -#define STM32_PLLIN_MIN 950000 - -/** - * @brief Maximum PLLs VCO clock frequency. - */ -#define STM32_PLLVCO_MAX 432000000 - -/** - * @brief Minimum PLLs VCO clock frequency. - */ -#define STM32_PLLVCO_MIN 192000000 - -/** - * @brief Maximum PLL output clock frequency. - */ -#define STM32_PLLOUT_MAX 180000000 - -/** - * @brief Minimum PLL output clock frequency. - */ -#define STM32_PLLOUT_MIN 24000000 - -/** - * @brief Maximum APB1 clock frequency. - */ -#define STM32_PCLK1_MAX (STM32_PLLOUT_MAX /4) - -/** - * @brief Maximum APB2 clock frequency. - */ -#define STM32_PCLK2_MAX (STM32_PLLOUT_MAX / 2) - -/** - * @brief Maximum SPI/I2S clock frequency. - */ -#define STM32_SPII2S_MAX 45000000 -#endif - -#if defined(STM32F40_41xxx) || defined(__DOXYGEN__) -#define STM32_SYSCLK_MAX 168000000 -#define STM32_HSECLK_MAX 26000000 -#define STM32_HSECLK_BYP_MAX 50000000 -#define STM32_HSECLK_MIN 4000000 -#define STM32_HSECLK_BYP_MIN 1000000 -#define STM32_LSECLK_MAX 32768 -#define STM32_LSECLK_BYP_MAX 1000000 -#define STM32_LSECLK_MIN 32768 -#define STM32_PLLIN_MAX 2100000 -#define STM32_PLLIN_MIN 950000 -#define STM32_PLLVCO_MAX 432000000 -#define STM32_PLLVCO_MIN 192000000 -#define STM32_PLLOUT_MAX 168000000 -#define STM32_PLLOUT_MIN 24000000 -#define STM32_PCLK1_MAX 42000000 -#define STM32_PCLK2_MAX 84000000 -#define STM32_SPII2S_MAX 42000000 -#endif - -#if defined(STM32F401xx) || defined(__DOXYGEN__) -#define STM32_SYSCLK_MAX 84000000 -#define STM32_HSECLK_MAX 26000000 -#define STM32_HSECLK_BYP_MAX 50000000 -#define STM32_HSECLK_MIN 4000000 -#define STM32_HSECLK_BYP_MIN 1000000 -#define STM32_LSECLK_MAX 32768 -#define STM32_LSECLK_BYP_MAX 1000000 -#define STM32_LSECLK_MIN 32768 -#define STM32_PLLIN_MAX 2100000 -#define STM32_PLLIN_MIN 950000 -#define STM32_PLLVCO_MAX 432000000 -#define STM32_PLLVCO_MIN 192000000 -#define STM32_PLLOUT_MAX 84000000 -#define STM32_PLLOUT_MIN 24000000 -#define STM32_PCLK1_MAX 42000000 -#define STM32_PCLK2_MAX 84000000 -#define STM32_SPII2S_MAX 42000000 -#endif - -#if defined(STM32F411xx) -#define STM32_SYSCLK_MAX 100000000 -#define STM32_HSECLK_MAX 26000000 -#define STM32_HSECLK_BYP_MAX 50000000 -#define STM32_HSECLK_MIN 4000000 -#define STM32_HSECLK_BYP_MIN 1000000 -#define STM32_LSECLK_MAX 32768 -#define STM32_LSECLK_BYP_MAX 1000000 -#define STM32_LSECLK_MIN 32768 -#define STM32_PLLIN_MAX 2100000 -#define STM32_PLLIN_MIN 950000 -#define STM32_PLLVCO_MAX 432000000 -#define STM32_PLLVCO_MIN 100000000 -#define STM32_PLLOUT_MAX 100000000 -#define STM32_PLLOUT_MIN 24000000 -#define STM32_PCLK1_MAX 50000000 -#define STM32_PCLK2_MAX 100000000 -#define STM32_SPII2S_MAX 50000000 -#endif - -#if defined(STM32F2XX) -#define STM32_SYSCLK_MAX 120000000 -#define STM32_HSECLK_MAX 26000000 -#define STM32_HSECLK_BYP_MAX 26000000 -#define STM32_HSECLK_MIN 1000000 -#define STM32_HSECLK_BYP_MIN 1000000 -#define STM32_LSECLK_MAX 32768 -#define STM32_LSECLK_BYP_MAX 1000000 -#define STM32_LSECLK_MIN 32768 -#define STM32_PLLIN_MAX 2000000 -#define STM32_PLLIN_MIN 950000 -#define STM32_PLLVCO_MAX 432000000 -#define STM32_PLLVCO_MIN 192000000 -#define STM32_PLLOUT_MAX 120000000 -#define STM32_PLLOUT_MIN 24000000 -#define STM32_PCLK1_MAX 30000000 -#define STM32_PCLK2_MAX 60000000 -#define STM32_SPII2S_MAX 30000000 -#endif -/** @} */ - -/** - * @name Internal clock sources - * @{ - */ -#define STM32_HSICLK 16000000 /**< High speed internal clock. */ -#define STM32_LSICLK 32000 /**< Low speed internal clock. */ -/** @} */ - -/** - * @name PWR_CR register bits definitions - * @{ - */ -#define STM32_VOS_SCALE3 0x00004000 -#define STM32_VOS_SCALE2 0x00008000 -#define STM32_VOS_SCALE1 0x0000C000 -#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */ -#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */ -#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */ -#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 2. */ -#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 3. */ -#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 4. */ -#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 5. */ -#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 6. */ -#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 7. */ -/** @} */ - -/** - * @name RCC_PLLCFGR register bits definitions - * @{ - */ -#define STM32_PLLP_MASK (3 << 16) /**< PLLP mask. */ -#define STM32_PLLP_DIV2 (0 << 16) /**< PLL clock divided by 2. */ -#define STM32_PLLP_DIV4 (1 << 16) /**< PLL clock divided by 4. */ -#define STM32_PLLP_DIV6 (2 << 16) /**< PLL clock divided by 6. */ -#define STM32_PLLP_DIV8 (3 << 16) /**< PLL clock divided by 8. */ - -#define STM32_PLLSRC_HSI (0 << 22) /**< PLL clock source is HSI. */ -#define STM32_PLLSRC_HSE (1 << 22) /**< PLL clock source is HSE. */ -/** @} */ - -/** - * @name RCC_CFGR register bits definitions - * @{ - */ -#define STM32_SW_MASK (3 << 0) /**< SW mask. */ -#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */ -#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */ -#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */ - -#define STM32_HPRE_MASK (15 << 4) /**< HPRE mask. */ -#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */ -#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */ -#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */ -#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */ -#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */ -#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */ -#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */ -#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */ -#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */ - -#define STM32_PPRE1_MASK (7 << 10) /**< PPRE1 mask. */ -#define STM32_PPRE1_DIV1 (0 << 10) /**< HCLK divided by 1. */ -#define STM32_PPRE1_DIV2 (4 << 10) /**< HCLK divided by 2. */ -#define STM32_PPRE1_DIV4 (5 << 10) /**< HCLK divided by 4. */ -#define STM32_PPRE1_DIV8 (6 << 10) /**< HCLK divided by 8. */ -#define STM32_PPRE1_DIV16 (7 << 10) /**< HCLK divided by 16. */ - -#define STM32_PPRE2_MASK (7 << 13) /**< PPRE2 mask. */ -#define STM32_PPRE2_DIV1 (0 << 13) /**< HCLK divided by 1. */ -#define STM32_PPRE2_DIV2 (4 << 13) /**< HCLK divided by 2. */ -#define STM32_PPRE2_DIV4 (5 << 13) /**< HCLK divided by 4. */ -#define STM32_PPRE2_DIV8 (6 << 13) /**< HCLK divided by 8. */ -#define STM32_PPRE2_DIV16 (7 << 13) /**< HCLK divided by 16. */ - -#define STM32_RTCPRE_MASK (31 << 16) /**< RTCPRE mask. */ - -#define STM32_MCO1SEL_MASK (3 << 21) /**< MCO1 mask. */ -#define STM32_MCO1SEL_HSI (0 << 21) /**< HSI clock on MCO1 pin. */ -#define STM32_MCO1SEL_LSE (1 << 21) /**< LSE clock on MCO1 pin. */ -#define STM32_MCO1SEL_HSE (2 << 21) /**< HSE clock on MCO1 pin. */ -#define STM32_MCO1SEL_PLL (3 << 21) /**< PLL clock on MCO1 pin. */ - -#define STM32_I2SSRC_MASK (1 << 23) /**< I2CSRC mask. */ -#define STM32_I2SSRC_PLLI2S (0 << 23) /**< I2SSRC is PLLI2S. */ -#define STM32_I2SSRC_CKIN (1 << 23) /**< I2S_CKIN is PLLI2S. */ - -#define STM32_MCO1PRE_MASK (7 << 24) /**< MCO1PRE mask. */ -#define STM32_MCO1PRE_DIV1 (0 << 24) /**< MCO1 divided by 1. */ -#define STM32_MCO1PRE_DIV2 (4 << 24) /**< MCO1 divided by 2. */ -#define STM32_MCO1PRE_DIV3 (5 << 24) /**< MCO1 divided by 3. */ -#define STM32_MCO1PRE_DIV4 (6 << 24) /**< MCO1 divided by 4. */ -#define STM32_MCO1PRE_DIV5 (7 << 24) /**< MCO1 divided by 5. */ - -#define STM32_MCO2PRE_MASK (7 << 27) /**< MCO2PRE mask. */ -#define STM32_MCO2PRE_DIV1 (0 << 27) /**< MCO2 divided by 1. */ -#define STM32_MCO2PRE_DIV2 (4 << 27) /**< MCO2 divided by 2. */ -#define STM32_MCO2PRE_DIV3 (5 << 27) /**< MCO2 divided by 3. */ -#define STM32_MCO2PRE_DIV4 (6 << 27) /**< MCO2 divided by 4. */ -#define STM32_MCO2PRE_DIV5 (7 << 27) /**< MCO2 divided by 5. */ - -#define STM32_MCO2SEL_MASK (3 << 30) /**< MCO2 mask. */ -#define STM32_MCO2SEL_SYSCLK (0 << 30) /**< SYSCLK clock on MCO2 pin. */ -#define STM32_MCO2SEL_PLLI2S (1 << 30) /**< PLLI2S clock on MCO2 pin. */ -#define STM32_MCO2SEL_HSE (2 << 30) /**< HSE clock on MCO2 pin. */ -#define STM32_MCO2SEL_PLL (3 << 30) /**< PLL clock on MCO2 pin. */ - -/** - * @name RCC_PLLI2SCFGR register bits definitions - * @{ - */ -#define STM32_PLLI2SN_MASK (511 << 6) /**< PLLI2SN mask. */ -#define STM32_PLLI2SR_MASK (7 << 28) /**< PLLI2SR mask. */ -/** @} */ - -/** - * @name RCC_BDCR register bits definitions - * @{ - */ -#define STM32_RTCSEL_MASK (3 << 8) /**< RTC source mask. */ -#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No RTC source. */ -#define STM32_RTCSEL_LSE (1 << 8) /**< RTC source is LSE. */ -#define STM32_RTCSEL_LSI (2 << 8) /**< RTC source is LSI. */ -#define STM32_RTCSEL_HSEDIV (3 << 8) /**< RTC source is HSE divided. */ -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief Disables the PWR/RCC initialization in the HAL. - */ -#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__) -#define STM32_NO_INIT FALSE -#endif - -/** - * @brief Enables or disables the programmable voltage detector. - */ -#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__) -#define STM32_PVD_ENABLE FALSE -#endif - -/** - * @brief Sets voltage level for programmable voltage detector. - */ -#if !defined(STM32_PLS) || defined(__DOXYGEN__) -#define STM32_PLS STM32_PLS_LEV0 -#endif - -/** - * @brief Enables the backup RAM regulator. - */ -#if !defined(STM32_BKPRAM_ENABLE) || defined(__DOXYGEN__) -#define STM32_BKPRAM_ENABLE FALSE -#endif - -/** - * @brief Enables or disables the HSI clock source. - */ -#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__) -#define STM32_HSI_ENABLED TRUE -#endif - -/** - * @brief Enables or disables the LSI clock source. - */ -#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__) -#define STM32_LSI_ENABLED FALSE -#endif - -/** - * @brief Enables or disables the HSE clock source. - */ -#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__) -#define STM32_HSE_ENABLED TRUE -#endif - -/** - * @brief Enables or disables the LSE clock source. - */ -#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__) -#define STM32_LSE_ENABLED FALSE -#endif - -/** - * @brief USB/SDIO clock setting. - */ -#if !defined(STM32_CLOCK48_REQUIRED) || defined(__DOXYGEN__) -#define STM32_CLOCK48_REQUIRED TRUE -#endif - -/** - * @brief Main clock source selection. - * @note If the selected clock source is not the PLL then the PLL is not - * initialized and started. - * @note The default value is calculated for a 168MHz system clock from - * an external 8MHz HSE clock. - */ -#if !defined(STM32_SW) || defined(__DOXYGEN__) -#define STM32_SW STM32_SW_PLL -#endif - -#if defined(STM32F4XX) || defined(__DOXYGEN__) -/** - * @brief Clock source for the PLLs. - * @note This setting has only effect if the PLL is selected as the - * system clock source. - * @note The default value is calculated for a 168MHz system clock from - * an external 8MHz HSE clock. - */ -#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__) -#define STM32_PLLSRC STM32_PLLSRC_HSE -#endif - -/** - * @brief PLLM divider value. - * @note The allowed values are 2..63. - * @note The default value is calculated for a 168MHz system clock from - * an external 8MHz HSE clock. - */ -#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLM_VALUE 8 -#endif - -/** - * @brief PLLN multiplier value. - * @note The allowed values are 192..432. - * @note The default value is calculated for a 168MHz system clock from - * an external 8MHz HSE clock. - */ -#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLN_VALUE 336 -#endif - -/** - * @brief PLLP divider value. - * @note The allowed values are 2, 4, 6, 8. - * @note The default value is calculated for a 168MHz system clock from - * an external 8MHz HSE clock. - */ -#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLP_VALUE 2 -#endif - -/** - * @brief PLLQ multiplier value. - * @note The allowed values are 2..15. - * @note The default value is calculated for a 168MHz system clock from - * an external 8MHz HSE clock. - */ -#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLQ_VALUE 7 -#endif - -#else /* !defined(STM32F4XX) */ -/** - * @brief Clock source for the PLLs. - * @note This setting has only effect if the PLL is selected as the - * system clock source. - * @note The default value is calculated for a 120MHz system clock from - * an external 8MHz HSE clock. - */ -#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__) -#define STM32_PLLSRC STM32_PLLSRC_HSE -#endif - -/** - * @brief PLLM divider value. - * @note The allowed values are 2..63. - * @note The default value is calculated for a 120MHz system clock from - * an external 8MHz HSE clock. - */ -#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLM_VALUE 8 -#endif - -/** - * @brief PLLN multiplier value. - * @note The allowed values are 192..432. - * @note The default value is calculated for a 120MHz system clock from - * an external 8MHz HSE clock. - */ -#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLN_VALUE 240 -#endif - -/** - * @brief PLLP divider value. - * @note The allowed values are 2, 4, 6, 8. - * @note The default value is calculated for a 120MHz system clock from - * an external 8MHz HSE clock. - */ -#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLP_VALUE 2 -#endif - -/** - * @brief PLLQ multiplier value. - * @note The allowed values are 2..15. - * @note The default value is calculated for a 120MHz system clock from - * an external 8MHz HSE clock. - */ -#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLQ_VALUE 5 -#endif -#endif /* !defined(STM32F4XX) */ - -/** - * @brief AHB prescaler value. - */ -#if !defined(STM32_HPRE) || defined(__DOXYGEN__) -#define STM32_HPRE STM32_HPRE_DIV1 -#endif - -/** - * @brief APB1 prescaler value. - */ -#if !defined(STM32_PPRE1) || defined(__DOXYGEN__) -#define STM32_PPRE1 STM32_PPRE1_DIV4 -#endif - -/** - * @brief APB2 prescaler value. - */ -#if !defined(STM32_PPRE2) || defined(__DOXYGEN__) -#define STM32_PPRE2 STM32_PPRE2_DIV2 -#endif - -/** - * @brief RTC clock source. - */ -#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__) -#define STM32_RTCSEL STM32_RTCSEL_LSE -#endif - -/** - * @brief RTC HSE prescaler value. - */ -#if !defined(STM32_RTCPRE_VALUE) || defined(__DOXYGEN__) -#define STM32_RTCPRE_VALUE 8 -#endif - -/** - * @brief MCO1 clock source value. - * @note The default value outputs HSI clock on MCO1 pin. - */ -#if !defined(STM32_MCO1SEL) || defined(__DOXYGEN__) -#define STM32_MCO1SEL STM32_MCO1SEL_HSI -#endif - -/** - * @brief MCO1 prescaler value. - * @note The default value outputs HSI clock on MCO1 pin. - */ -#if !defined(STM32_MCO1PRE) || defined(__DOXYGEN__) -#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 -#endif - -/** - * @brief MCO2 clock source value. - * @note The default value outputs SYSCLK / 5 on MCO2 pin. - */ -#if !defined(STM32_MCO2SEL) || defined(__DOXYGEN__) -#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK -#endif - -/** - * @brief MCO2 prescaler value. - * @note The default value outputs SYSCLK / 5 on MCO2 pin. - */ -#if !defined(STM32_MCO2PRE) || defined(__DOXYGEN__) -#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 -#endif - -/** - * @brief I2S clock source. - */ -#if !defined(STM32_I2SSRC) || defined(__DOXYGEN__) -#define STM32_I2SSRC STM32_I2SSRC_CKIN -#endif - -/** - * @brief PLLI2SN multiplier value. - * @note The allowed values are 192..432. - */ -#if !defined(STM32_PLLI2SN_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLI2SN_VALUE 192 -#endif - -/** - * @brief PLLI2SR multiplier value. - * @note The allowed values are 2..7. - */ -#if !defined(STM32_PLLI2SR_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLI2SR_VALUE 5 -#endif - -/** - * @brief PLLSAIQ value. - * @note The allowed values are 2..15. - */ -#if !defined(STM32_PLLSAIQ_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLSAIQ_VALUE 8 -#endif - -/** - * @brief PLLSAIQ value. - * @note The allowed values are 49..432. - */ -#if !defined(STM32_PLLSAIN_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLSAIN_VALUE 120 -#endif - -/** - * @brief PLLSAIQ value. - * @note The allowed values are 2..7. - */ -#if !defined(STM32_PLLSAIR_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLSAIR_VALUE 4 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if defined(STM32F4XX) || defined(__DOXYGEN__) -/* - * Configuration-related checks. - */ -#if !defined(STM32F4xx_MCUCONF) -#error "Using a wrong mcuconf.h file, STM32F4xx_MCUCONF not defined" -#endif - -#else /* !defined(STM32F4XX) */ -/* - * Configuration-related checks. - */ -#if !defined(STM32F2xx_MCUCONF) -#error "Using a wrong mcuconf.h file, STM32F2xx_MCUCONF not defined" -#endif -#endif /* !defined(STM32F4XX) */ - -/** - * @brief Maximum frequency thresholds and wait states for flash access. - * @note The values are valid for 2.7V to 3.6V supply range. - */ -#if defined(STM32F429_439xx) || defined(STM32F427_437xx) || \ - defined(STM32F40_41xxx) || defined(STM32F446xx) || \ - defined(__DOXYGEN__) -#if ((STM32_VDD >= 270) && (STM32_VDD <= 360)) || defined(__DOXYGEN__) -#define STM32_0WS_THRESHOLD 30000000 -#define STM32_1WS_THRESHOLD 60000000 -#define STM32_2WS_THRESHOLD 90000000 -#define STM32_3WS_THRESHOLD 120000000 -#define STM32_4WS_THRESHOLD 150000000 -#define STM32_5WS_THRESHOLD 180000000 -#define STM32_6WS_THRESHOLD 0 -#define STM32_7WS_THRESHOLD 0 -#define STM32_8WS_THRESHOLD 0 -#elif (STM32_VDD >= 240) && (STM32_VDD < 270) -#define STM32_0WS_THRESHOLD 24000000 -#define STM32_1WS_THRESHOLD 48000000 -#define STM32_2WS_THRESHOLD 72000000 -#define STM32_3WS_THRESHOLD 96000000 -#define STM32_4WS_THRESHOLD 120000000 -#define STM32_5WS_THRESHOLD 144000000 -#define STM32_6WS_THRESHOLD 168000000 -#define STM32_7WS_THRESHOLD 180000000 -#define STM32_8WS_THRESHOLD 0 -#elif (STM32_VDD >= 210) && (STM32_VDD < 240) -#define STM32_0WS_THRESHOLD 22000000 -#define STM32_1WS_THRESHOLD 44000000 -#define STM32_2WS_THRESHOLD 66000000 -#define STM32_3WS_THRESHOLD 88000000 -#define STM32_4WS_THRESHOLD 110000000 -#define STM32_5WS_THRESHOLD 132000000 -#define STM32_6WS_THRESHOLD 154000000 -#define STM32_7WS_THRESHOLD 176000000 -#define STM32_8WS_THRESHOLD 180000000 -#elif (STM32_VDD >= 180) && (STM32_VDD < 210) -#define STM32_0WS_THRESHOLD 20000000 -#define STM32_1WS_THRESHOLD 40000000 -#define STM32_2WS_THRESHOLD 60000000 -#define STM32_3WS_THRESHOLD 80000000 -#define STM32_4WS_THRESHOLD 100000000 -#define STM32_5WS_THRESHOLD 120000000 -#define STM32_6WS_THRESHOLD 140000000 -#define STM32_7WS_THRESHOLD 168000000 -#define STM32_8WS_THRESHOLD 0 -#else -#error "invalid VDD voltage specified" -#endif - -#elif defined(STM32F401xx) -#if (STM32_VDD >= 270) && (STM32_VDD <= 360) -#define STM32_0WS_THRESHOLD 30000000 -#define STM32_1WS_THRESHOLD 60000000 -#define STM32_2WS_THRESHOLD 84000000 -#define STM32_3WS_THRESHOLD 0 -#define STM32_4WS_THRESHOLD 0 -#define STM32_5WS_THRESHOLD 0 -#define STM32_6WS_THRESHOLD 0 -#define STM32_7WS_THRESHOLD 0 -#define STM32_8WS_THRESHOLD 0 -#elif (STM32_VDD >= 240) && (STM32_VDD < 270) -#define STM32_0WS_THRESHOLD 24000000 -#define STM32_1WS_THRESHOLD 48000000 -#define STM32_2WS_THRESHOLD 72000000 -#define STM32_3WS_THRESHOLD 84000000 -#define STM32_4WS_THRESHOLD 0 -#define STM32_5WS_THRESHOLD 0 -#define STM32_6WS_THRESHOLD 0 -#define STM32_7WS_THRESHOLD 0 -#define STM32_8WS_THRESHOLD 0 -#elif (STM32_VDD >= 210) && (STM32_VDD < 240) -#define STM32_0WS_THRESHOLD 18000000 -#define STM32_1WS_THRESHOLD 36000000 -#define STM32_2WS_THRESHOLD 54000000 -#define STM32_3WS_THRESHOLD 72000000 -#define STM32_4WS_THRESHOLD 84000000 -#define STM32_5WS_THRESHOLD 0 -#define STM32_6WS_THRESHOLD 0 -#define STM32_7WS_THRESHOLD 0 -#define STM32_8WS_THRESHOLD 0 -#elif (STM32_VDD >= 180) && (STM32_VDD < 210) -#define STM32_0WS_THRESHOLD 16000000 -#define STM32_1WS_THRESHOLD 32000000 -#define STM32_2WS_THRESHOLD 48000000 -#define STM32_3WS_THRESHOLD 64000000 -#define STM32_4WS_THRESHOLD 80000000 -#define STM32_5WS_THRESHOLD 84000000 -#define STM32_6WS_THRESHOLD 0 -#define STM32_7WS_THRESHOLD 0 -#define STM32_8WS_THRESHOLD 0 -#else -#error "invalid VDD voltage specified" -#endif - -#elif defined(STM32F411xx) -#if (STM32_VDD >= 270) && (STM32_VDD <= 360) -#define STM32_0WS_THRESHOLD 30000000 -#define STM32_1WS_THRESHOLD 64000000 -#define STM32_2WS_THRESHOLD 90000000 -#define STM32_3WS_THRESHOLD 100000000 -#define STM32_4WS_THRESHOLD 0 -#define STM32_5WS_THRESHOLD 0 -#define STM32_6WS_THRESHOLD 0 -#define STM32_7WS_THRESHOLD 0 -#define STM32_8WS_THRESHOLD 0 -#elif (STM32_VDD >= 240) && (STM32_VDD < 270) -#define STM32_0WS_THRESHOLD 24000000 -#define STM32_1WS_THRESHOLD 48000000 -#define STM32_2WS_THRESHOLD 72000000 -#define STM32_3WS_THRESHOLD 96000000 -#define STM32_4WS_THRESHOLD 100000000 -#define STM32_5WS_THRESHOLD 0 -#define STM32_6WS_THRESHOLD 0 -#define STM32_7WS_THRESHOLD 0 -#define STM32_8WS_THRESHOLD 0 -#elif (STM32_VDD >= 210) && (STM32_VDD < 240) -#define STM32_0WS_THRESHOLD 18000000 -#define STM32_1WS_THRESHOLD 36000000 -#define STM32_2WS_THRESHOLD 54000000 -#define STM32_3WS_THRESHOLD 72000000 -#define STM32_4WS_THRESHOLD 90000000 -#define STM32_5WS_THRESHOLD 100000000 -#define STM32_6WS_THRESHOLD 0 -#define STM32_7WS_THRESHOLD 0 -#define STM32_8WS_THRESHOLD 0 -#elif (STM32_VDD >= 171) && (STM32_VDD < 210) -#define STM32_0WS_THRESHOLD 16000000 -#define STM32_1WS_THRESHOLD 32000000 -#define STM32_2WS_THRESHOLD 48000000 -#define STM32_3WS_THRESHOLD 64000000 -#define STM32_4WS_THRESHOLD 80000000 -#define STM32_5WS_THRESHOLD 96000000 -#define STM32_6WS_THRESHOLD 100000000 -#define STM32_7WS_THRESHOLD 0 -#define STM32_8WS_THRESHOLD 0 -#else -#error "invalid VDD voltage specified" -#endif - -#else /* STM32F2XX */ -#if (STM32_VDD >= 270) && (STM32_VDD <= 360) -#define STM32_0WS_THRESHOLD 30000000 -#define STM32_1WS_THRESHOLD 60000000 -#define STM32_2WS_THRESHOLD 90000000 -#define STM32_3WS_THRESHOLD 120000000 -#define STM32_4WS_THRESHOLD 0 -#define STM32_5WS_THRESHOLD 0 -#define STM32_6WS_THRESHOLD 0 -#define STM32_7WS_THRESHOLD 0 -#elif (STM32_VDD >= 240) && (STM32_VDD < 270) -#define STM32_0WS_THRESHOLD 24000000 -#define STM32_1WS_THRESHOLD 48000000 -#define STM32_2WS_THRESHOLD 72000000 -#define STM32_3WS_THRESHOLD 96000000 -#define STM32_4WS_THRESHOLD 120000000 -#define STM32_5WS_THRESHOLD 0 -#define STM32_6WS_THRESHOLD 0 -#define STM32_7WS_THRESHOLD 0 -#elif (STM32_VDD >= 210) && (STM32_VDD < 240) -#define STM32_0WS_THRESHOLD 18000000 -#define STM32_1WS_THRESHOLD 36000000 -#define STM32_2WS_THRESHOLD 54000000 -#define STM32_3WS_THRESHOLD 72000000 -#define STM32_4WS_THRESHOLD 90000000 -#define STM32_5WS_THRESHOLD 108000000 -#define STM32_6WS_THRESHOLD 120000000 -#define STM32_7WS_THRESHOLD 0 -#elif (STM32_VDD >= 180) && (STM32_VDD < 210) -#define STM32_0WS_THRESHOLD 16000000 -#define STM32_1WS_THRESHOLD 32000000 -#define STM32_2WS_THRESHOLD 48000000 -#define STM32_3WS_THRESHOLD 64000000 -#define STM32_4WS_THRESHOLD 80000000 -#define STM32_5WS_THRESHOLD 96000000 -#define STM32_6WS_THRESHOLD 112000000 -#define STM32_7WS_THRESHOLD 120000000 -#else -#error "invalid VDD voltage specified" -#endif -#endif /* STM32F2XX */ - -/* - * HSI related checks. - */ -#if STM32_HSI_ENABLED -#else /* !STM32_HSI_ENABLED */ - -#if STM32_SW == STM32_SW_HSI -#error "HSI not enabled, required by STM32_SW" -#endif - -#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI) -#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC" -#endif - -#if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || \ - ((STM32_MCO1SEL == STM32_MCO1SEL_PLL) && \ - (STM32_PLLSRC == STM32_PLLSRC_HSI)) -#error "HSI not enabled, required by STM32_MCO1SEL" -#endif - -#if (STM32_MCO2SEL == STM32_MCO2SEL_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI) -#error "HSI not enabled, required by STM32_MCO2SEL" -#endif - -#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) && \ - (STM32_PLLSRC == STM32_PLLSRC_HSI) -#error "HSI not enabled, required by STM32_I2SSRC" -#endif - -#endif /* !STM32_HSI_ENABLED */ - -/* - * HSE related checks. - */ -#if STM32_HSE_ENABLED - -#if STM32_HSECLK == 0 -#error "HSE frequency not defined" -#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX) -#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)" -#endif - -#else /* !STM32_HSE_ENABLED */ - -#if STM32_SW == STM32_SW_HSE -#error "HSE not enabled, required by STM32_SW" -#endif - -#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE) -#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC" -#endif - -#if (STM32_MCO1SEL == STM32_MCO1SEL_HSE) || \ - ((STM32_MCO1SEL == STM32_MCO1SEL_PLL) && \ - (STM32_PLLSRC == STM32_PLLSRC_HSE)) -#error "HSE not enabled, required by STM32_MCO1SEL" -#endif - -#if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || \ - ((STM32_MCO2SEL == STM32_MCO2SEL_PLL) && \ - (STM32_PLLSRC == STM32_PLLSRC_HSE)) -#error "HSE not enabled, required by STM32_MCO2SEL" -#endif - -#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) && \ - (STM32_PLLSRC == STM32_PLLSRC_HSE) -#error "HSE not enabled, required by STM32_I2SSRC" -#endif - -#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV -#error "HSE not enabled, required by STM32_RTCSEL" -#endif - -#endif /* !STM32_HSE_ENABLED */ - -/* - * LSI related checks. - */ -#if STM32_LSI_ENABLED -#else /* !STM32_LSI_ENABLED */ - -#if STM32_RTCSEL == STM32_RTCSEL_LSI -#error "LSI not enabled, required by STM32_RTCSEL" -#endif - -#endif /* !STM32_LSI_ENABLED */ - -/* - * LSE related checks. - */ -#if STM32_LSE_ENABLED - -#if (STM32_LSECLK == 0) -#error "LSE frequency not defined" -#endif - -#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX) -#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)" -#endif - -#else /* !STM32_LSE_ENABLED */ - -#if STM32_RTCSEL == STM32_RTCSEL_LSE -#error "LSE not enabled, required by STM32_RTCSEL" -#endif - -#endif /* !STM32_LSE_ENABLED */ - -/** - * @brief STM32_PLLM field. - */ -#if ((STM32_PLLM_VALUE >= 2) && (STM32_PLLM_VALUE <= 63)) || \ - defined(__DOXYGEN__) -#define STM32_PLLM (STM32_PLLM_VALUE << 0) -#else -#error "invalid STM32_PLLM_VALUE value specified" -#endif - -/** - * @brief PLLs input clock frequency. - */ -#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) -#define STM32_PLLCLKIN (STM32_HSECLK / STM32_PLLM_VALUE) -#elif STM32_PLLSRC == STM32_PLLSRC_HSI -#define STM32_PLLCLKIN (STM32_HSICLK / STM32_PLLM_VALUE) -#else -#error "invalid STM32_PLLSRC value specified" -#endif - -/* - * PLLs input frequency range check. - */ -#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX) -#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)" -#endif - -/* - * PLL enable check. - */ -#if STM32_CLOCK48_REQUIRED || \ - (STM32_SW == STM32_SW_PLL) || \ - (STM32_MCO1SEL == STM32_MCO1SEL_PLL) || \ - (STM32_MCO2SEL == STM32_MCO2SEL_PLL) || \ - defined(__DOXYGEN__) -/** - * @brief PLL activation flag. - */ -#define STM32_ACTIVATE_PLL TRUE -#else -#define STM32_ACTIVATE_PLL FALSE -#endif - -/** - * @brief STM32_PLLN field. - */ -#if ((STM32_PLLN_VALUE >= 64) && (STM32_PLLN_VALUE <= 432)) || \ - defined(__DOXYGEN__) -#define STM32_PLLN (STM32_PLLN_VALUE << 6) -#else -#error "invalid STM32_PLLN_VALUE value specified" -#endif - -/** - * @brief STM32_PLLP field. - */ -#if (STM32_PLLP_VALUE == 2) || defined(__DOXYGEN__) -#define STM32_PLLP (0 << 16) -#elif STM32_PLLP_VALUE == 4 -#define STM32_PLLP (1 << 16) -#elif STM32_PLLP_VALUE == 6 -#define STM32_PLLP (2 << 16) -#elif STM32_PLLP_VALUE == 8 -#define STM32_PLLP (3 << 16) -#else -#error "invalid STM32_PLLP_VALUE value specified" -#endif - -/** - * @brief STM32_PLLQ field. - */ -#if ((STM32_PLLQ_VALUE >= 2) && (STM32_PLLQ_VALUE <= 15)) || \ - defined(__DOXYGEN__) -#define STM32_PLLQ (STM32_PLLQ_VALUE << 24) -#else -#error "invalid STM32_PLLQ_VALUE value specified" -#endif - -/** - * @brief PLL VCO frequency. - */ -#define STM32_PLLVCO (STM32_PLLCLKIN * STM32_PLLN_VALUE) - -/* - * PLL VCO frequency range check. - */ -#if (STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX) -#error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)" -#endif - -/** - * @brief PLL output clock frequency. - */ -#define STM32_PLLCLKOUT (STM32_PLLVCO / STM32_PLLP_VALUE) - -/* - * PLL output frequency range check. - */ -#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX) -#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)" -#endif - -/** - * @brief System clock source. - */ -#if STM32_NO_INIT || defined(__DOXYGEN__) -#define STM32_SYSCLK STM32_HSICLK -#elif (STM32_SW == STM32_SW_HSI) -#define STM32_SYSCLK STM32_HSICLK -#elif (STM32_SW == STM32_SW_HSE) -#define STM32_SYSCLK STM32_HSECLK -#elif (STM32_SW == STM32_SW_PLL) -#define STM32_SYSCLK STM32_PLLCLKOUT -#else -#error "invalid STM32_SW value specified" -#endif - -/* Check on the system clock.*/ -#if STM32_SYSCLK > STM32_SYSCLK_MAX -#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)" -#endif - -/* Calculating VOS settings, it is different for each sub-platform.*/ -#if defined(STM32F429_439xx) || defined(STM32F427_437xx) || \ - defined(STM32F446xx) || defined(__DOXYGEN__) -#if STM32_SYSCLK <= 120000000 -#define STM32_VOS STM32_VOS_SCALE3 -#define STM32_OVERDRIVE_REQUIRED FALSE -#elif STM32_SYSCLK <= 144000000 -#define STM32_VOS STM32_VOS_SCALE2 -#define STM32_OVERDRIVE_REQUIRED FALSE -#elif STM32_SYSCLK <= 168000000 -#define STM32_VOS STM32_VOS_SCALE1 -#define STM32_OVERDRIVE_REQUIRED FALSE -#else -#define STM32_VOS STM32_VOS_SCALE1 -#define STM32_OVERDRIVE_REQUIRED TRUE -#endif - -#elif defined(STM32F40_41xxx) -#if STM32_SYSCLK <= 144000000 -#define STM32_VOS STM32_VOS_SCALE2 -#else -#define STM32_VOS STM32_VOS_SCALE1 -#endif -#define STM32_OVERDRIVE_REQUIRED FALSE - -#elif defined(STM32F401xx) -#if STM32_SYSCLK <= 60000000 -#define STM32_VOS STM32_VOS_SCALE3 -#else -#define STM32_VOS STM32_VOS_SCALE2 -#endif -#define STM32_OVERDRIVE_REQUIRED FALSE - -#elif defined(STM32F411xx) -#if STM32_SYSCLK <= 64000000 -#define STM32_VOS STM32_VOS_SCALE3 -#elif STM32_SYSCLK <= 84000000 -#define STM32_VOS STM32_VOS_SCALE2 -#else -#define STM32_VOS STM32_VOS_SCALE1 -#endif -#define STM32_OVERDRIVE_REQUIRED FALSE - -#else /* STM32F2XX */ -#define STM32_OVERDRIVE_REQUIRED FALSE -#endif - -/** - * @brief AHB frequency. - */ -#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__) -#define STM32_HCLK (STM32_SYSCLK / 1) -#elif STM32_HPRE == STM32_HPRE_DIV2 -#define STM32_HCLK (STM32_SYSCLK / 2) -#elif STM32_HPRE == STM32_HPRE_DIV4 -#define STM32_HCLK (STM32_SYSCLK / 4) -#elif STM32_HPRE == STM32_HPRE_DIV8 -#define STM32_HCLK (STM32_SYSCLK / 8) -#elif STM32_HPRE == STM32_HPRE_DIV16 -#define STM32_HCLK (STM32_SYSCLK / 16) -#elif STM32_HPRE == STM32_HPRE_DIV64 -#define STM32_HCLK (STM32_SYSCLK / 64) -#elif STM32_HPRE == STM32_HPRE_DIV128 -#define STM32_HCLK (STM32_SYSCLK / 128) -#elif STM32_HPRE == STM32_HPRE_DIV256 -#define STM32_HCLK (STM32_SYSCLK / 256) -#elif STM32_HPRE == STM32_HPRE_DIV512 -#define STM32_HCLK (STM32_SYSCLK / 512) -#else -#error "invalid STM32_HPRE value specified" -#endif - -/* - * AHB frequency check. - */ -#if STM32_HCLK > STM32_SYSCLK_MAX -#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)" -#endif - -/** - * @brief APB1 frequency. - */ -#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) -#define STM32_PCLK1 (STM32_HCLK / 1) -#elif STM32_PPRE1 == STM32_PPRE1_DIV2 -#define STM32_PCLK1 (STM32_HCLK / 2) -#elif STM32_PPRE1 == STM32_PPRE1_DIV4 -#define STM32_PCLK1 (STM32_HCLK / 4) -#elif STM32_PPRE1 == STM32_PPRE1_DIV8 -#define STM32_PCLK1 (STM32_HCLK / 8) -#elif STM32_PPRE1 == STM32_PPRE1_DIV16 -#define STM32_PCLK1 (STM32_HCLK / 16) -#else -#error "invalid STM32_PPRE1 value specified" -#endif - -/* - * APB1 frequency check. - */ -#if STM32_PCLK1 > STM32_PCLK1_MAX -#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)" -#endif - -/** - * @brief APB2 frequency. - */ -#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) -#define STM32_PCLK2 (STM32_HCLK / 1) -#elif STM32_PPRE2 == STM32_PPRE2_DIV2 -#define STM32_PCLK2 (STM32_HCLK / 2) -#elif STM32_PPRE2 == STM32_PPRE2_DIV4 -#define STM32_PCLK2 (STM32_HCLK / 4) -#elif STM32_PPRE2 == STM32_PPRE2_DIV8 -#define STM32_PCLK2 (STM32_HCLK / 8) -#elif STM32_PPRE2 == STM32_PPRE2_DIV16 -#define STM32_PCLK2 (STM32_HCLK / 16) -#else -#error "invalid STM32_PPRE2 value specified" -#endif - -/* - * APB2 frequency check. - */ -#if STM32_PCLK2 > STM32_PCLK2_MAX -#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)" -#endif - -/* - * PLLI2S enable check. - */ -#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) || defined(__DOXYGEN__) -/** - * @brief PLLI2S activation flag. - */ -#define STM32_ACTIVATE_PLLI2S TRUE -#else -#define STM32_ACTIVATE_PLLI2S FALSE -#endif - -/** - * @brief STM32_PLLI2SN field. - */ -#if ((STM32_PLLI2SN_VALUE >= 192) && (STM32_PLLI2SN_VALUE <= 432)) || \ - defined(__DOXYGEN__) -#define STM32_PLLI2SN (STM32_PLLI2SN_VALUE << 6) -#else -#error "invalid STM32_PLLI2SN_VALUE value specified" -#endif - -/** - * @brief STM32_PLLI2SR field. - */ -#if ((STM32_PLLI2SR_VALUE >= 2) && (STM32_PLLI2SR_VALUE <= 7)) || \ - defined(__DOXYGEN__) -#define STM32_PLLI2SR (STM32_PLLI2SR_VALUE << 28) -#else -#error "invalid STM32_PLLI2SR_VALUE value specified" -#endif - -/** - * @brief PLLSAI activation flag. - */ -#define STM32_ACTIVATE_PLLSAI FALSE - -/** - * @brief STM32_PLLSAIN field. - */ -#if ((STM32_PLLSAIN_VALUE >= 49) && (STM32_PLLSAIN_VALUE <= 432)) || \ - defined(__DOXYGEN__) -#define STM32_PLLSAIN (STM32_PLLSAIN_VALUE << 6) -#else -#error "invalid STM32_PLLSAIN_VALUE value specified" -#endif - -/** - * @brief STM32_PLLSAIQ field. - */ -#if ((STM32_PLLSAIQ_VALUE >= 2) && (STM32_PLLSAIQ_VALUE <= 15)) || \ - defined(__DOXYGEN__) -#define STM32_PLLSAIQ (STM32_PLLSAIQ_VALUE << 24) -#else -#error "invalid STM32_PLLSAIR_VALUE value specified" -#endif - -/** - * @brief STM32_PLLSAIR field. - */ -#if ((STM32_PLLSAIR_VALUE >= 2) && (STM32_PLLSAIR_VALUE <= 7)) || \ - defined(__DOXYGEN__) -#define STM32_PLLSAIR (STM32_PLLSAIR_VALUE << 28) -#else -#error "invalid STM32_PLLSAIR_VALUE value specified" -#endif - -/** - * @brief PLL VCO frequency. - */ -#define STM32_PLLI2SVCO (STM32_PLLCLKIN * STM32_PLLI2SN_VALUE) - -/* - * PLLI2S VCO frequency range check. - */ -#if (STM32_PLLI2SVCO < STM32_PLLVCO_MIN) || \ - (STM32_PLLI2SVCO > STM32_PLLVCO_MAX) -#error "STM32_PLLI2SVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)" -#endif - -/** - * @brief PLLI2S output clock frequency. - */ -#define STM32_PLLI2SCLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SR_VALUE) - -/** - * @brief MCO1 divider clock. - */ -#if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || defined(__DOXYGEN__) -#define STM32_MCO1DIVCLK STM32_HSICLK -#elif STM32_MCO1SEL == STM32_MCO1SEL_LSE -#define STM32_MCO1DIVCLK STM32_LSECLK -#elif STM32_MCO1SEL == STM32_MCO1SEL_HSE -#define STM32_MCO1DIVCLK STM32_HSECLK -#elif STM32_MCO1SEL == STM32_MCO1SEL_PLL -#define STM32_MCO1DIVCLK STM32_PLLCLKOUT -#else -#error "invalid STM32_MCO1SEL value specified" -#endif - -/** - * @brief MCO1 output pin clock. - */ -#if (STM32_MCO1PRE == STM32_MCO1PRE_DIV1) || defined(__DOXYGEN__) -#define STM32_MCO1CLK STM32_MCO1DIVCLK -#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV2 -#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 2) -#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV3 -#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 3) -#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV4 -#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 4) -#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV5 -#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 5) -#else -#error "invalid STM32_MCO1PRE value specified" -#endif - -/** - * @brief MCO2 divider clock. - */ -#if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || defined(__DOXYGEN__) -#define STM32_MCO2DIVCLK STM32_HSECLK -#elif STM32_MCO2SEL == STM32_MCO2SEL_PLL -#define STM32_MCO2DIVCLK STM32_PLLCLKOUT -#elif STM32_MCO2SEL == STM32_MCO2SEL_SYSCLK -#define STM32_MCO2DIVCLK STM32_SYSCLK -#elif STM32_MCO2SEL == STM32_MCO2SEL_PLLI2S -#define STM32_MCO2DIVCLK STM32_PLLI2S -#else -#error "invalid STM32_MCO2SEL value specified" -#endif - -/** - * @brief MCO2 output pin clock. - */ -#if (STM32_MCO2PRE == STM32_MCO2PRE_DIV1) || defined(__DOXYGEN__) -#define STM32_MCO2CLK STM32_MCO2DIVCLK -#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV2 -#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 2) -#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV3 -#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 3) -#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV4 -#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 4) -#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV5 -#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 5) -#else -#error "invalid STM32_MCO2PRE value specified" -#endif - -/** - * @brief RTC HSE divider setting. - */ -#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \ - defined(__DOXYGEN__) -#define STM32_RTCPRE (STM32_RTCPRE_VALUE << 16) -#else -#error "invalid STM32_RTCPRE value specified" -#endif - -/** - * @brief HSE divider toward RTC clock. - */ -#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \ - defined(__DOXYGEN__) -#define STM32_HSEDIVCLK (STM32_HSECLK / STM32_RTCPRE_VALUE) -#else -#error "invalid STM32_RTCPRE value specified" -#endif - -/** - * @brief RTC clock. - */ -#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__) -#define STM32_RTCCLK 0 -#elif STM32_RTCSEL == STM32_RTCSEL_LSE -#define STM32_RTCCLK STM32_LSECLK -#elif STM32_RTCSEL == STM32_RTCSEL_LSI -#define STM32_RTCCLK STM32_LSICLK -#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV -#define STM32_RTCCLK STM32_HSEDIVCLK -#else -#error "invalid STM32_RTCSEL value specified" -#endif - -/** - * @brief 48MHz frequency. - */ -#if STM32_CLOCK48_REQUIRED || defined(__DOXYGEN__) -#define STM32_PLL48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE) -#else -#define STM32_PLL48CLK 0 -#endif - -/** - * @brief Clock of timers connected to APB1 - * (Timers 2, 3, 4, 5, 6, 7, 12, 13, 14). - */ -#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) -#define STM32_TIMCLK1 (STM32_PCLK1 * 1) -#else -#define STM32_TIMCLK1 (STM32_PCLK1 * 2) -#endif - -/** - * @brief Clock of timers connected to APB2 (Timers 1, 8, 9, 10, 11). - */ -#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) -#define STM32_TIMCLK2 (STM32_PCLK2 * 1) -#else -#define STM32_TIMCLK2 (STM32_PCLK2 * 2) -#endif - -/** - * @brief Flash settings. - */ -#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__) -#define STM32_FLASHBITS 0x00000000 -#elif STM32_HCLK <= STM32_1WS_THRESHOLD -#define STM32_FLASHBITS 0x00000001 -#elif STM32_HCLK <= STM32_2WS_THRESHOLD -#define STM32_FLASHBITS 0x00000002 -#elif STM32_HCLK <= STM32_3WS_THRESHOLD -#define STM32_FLASHBITS 0x00000003 -#elif STM32_HCLK <= STM32_4WS_THRESHOLD -#define STM32_FLASHBITS 0x00000004 -#elif STM32_HCLK <= STM32_5WS_THRESHOLD -#define STM32_FLASHBITS 0x00000005 -#elif STM32_HCLK <= STM32_6WS_THRESHOLD -#define STM32_FLASHBITS 0x00000006 -#elif STM32_HCLK <= STM32_7WS_THRESHOLD -#define STM32_FLASHBITS 0x00000007 -#else -#define STM32_FLASHBITS 0x00000008 -#endif - -/* There are differences in vector names in the various sub-families, - normalizing.*/ -#if 0 -#define TIM1_BRK_IRQn TIM1_BRK_TIM9_IRQn -#define TIM1_UP_IRQn TIM1_UP_TIM10_IRQn -#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM11_IRQn -#define TIM8_BRK_IRQn TIM8_BRK_TIM12_IRQn -#define TIM8_UP_IRQn TIM8_UP_TIM13_IRQn -#define TIM8_TRG_COM_IRQn TIM8_TRG_COM_TIM14_IRQn -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/* Various helpers.*/ -#include "nvic.h" -#include "stm32_isr.h" -#include "stm32_dma.h" -#include "stm32_rcc.h" - -#ifdef __cplusplus -extern "C" { -#endif - void hal_lld_init(void); - void stm32_clock_init(void); -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/STM32F4xx/platform.mk b/firmware/ChibiOS_16/os/hal/ports/STM32/STM32F4xx/platform.mk deleted file mode 100644 index e9ad3e4292..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/STM32F4xx/platform.mk +++ /dev/null @@ -1,107 +0,0 @@ -# List of all the STM32F2xx/STM32F4xx platform files. -ifeq ($(USE_SMART_BUILD),yes) -HALCONF := $(strip $(shell cat halconf.h | egrep -e "define")) - -PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ - $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/hal_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/st_lld.c -ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv2/adc_lld.c -endif -ifneq ($(findstring HAL_USE_CAN TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/can_lld.c -endif -ifneq ($(findstring HAL_USE_DAC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/dac_lld.c -endif -ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/ext_lld_isr.c -endif -ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c -endif -ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv1/i2c_lld.c -endif -ifneq ($(findstring HAL_USE_MAC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/MACv1/mac_lld.c -endif -ifneq ($(findstring HAL_USE_USB TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1/usb_lld.c -endif -ifneq ($(findstring HAL_USE_RTC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.c -endif -ifneq ($(findstring HAL_USE_I2S TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/i2s_lld.c -endif -ifneq ($(findstring HAL_USE_SDC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SDIOv1/sdc_lld.c -endif -ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/spi_lld.c -endif -ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c -endif -ifneq ($(findstring HAL_USE_ICU TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c -endif -ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c -endif -ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/serial_lld.c -endif -ifneq ($(findstring HAL_USE_UART TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/uart_lld.c -endif -ifneq ($(findstring HAL_USE_WDG TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/wdg_lld.c -endif -else -PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ - $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/hal_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/ext_lld_isr.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv2/adc_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/can_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/dac_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv1/i2c_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/MACv1/mac_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1/usb_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/SDIOv1/sdc_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/i2s_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/spi_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/st_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/serial_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/uart_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/wdg_lld.c -endif - -# Required include directories -PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \ - $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv2 \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1 \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1 \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv2 \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1 \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2 \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv1 \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/MACv1 \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1 \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2 \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/SDIOv1 \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1 \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1 \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1 \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1 diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/STM32F4xx/stm32_isr.h b/firmware/ChibiOS_16/os/hal/ports/STM32/STM32F4xx/stm32_isr.h deleted file mode 100644 index 61158ac99e..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/STM32F4xx/stm32_isr.h +++ /dev/null @@ -1,205 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F4xx/stm32_isr.h - * @brief ISR remapper driver header. - * - * @addtogroup STM32F4xx_ISR - * @{ - */ - -#ifndef _STM32_ISR_H_ -#define _STM32_ISR_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name ISR names and numbers remapping - * @{ - */ -/* - * CAN units. - */ -#define STM32_CAN1_TX_HANDLER Vector8C -#define STM32_CAN1_RX0_HANDLER Vector90 -#define STM32_CAN1_RX1_HANDLER Vector94 -#define STM32_CAN1_SCE_HANDLER Vector98 -#define STM32_CAN2_TX_HANDLER Vector13C -#define STM32_CAN2_RX0_HANDLER Vector140 -#define STM32_CAN2_RX1_HANDLER Vector144 -#define STM32_CAN2_SCE_HANDLER Vector148 - -#define STM32_CAN1_TX_NUMBER 19 -#define STM32_CAN1_RX0_NUMBER 20 -#define STM32_CAN1_RX1_NUMBER 21 -#define STM32_CAN1_SCE_NUMBER 22 -#define STM32_CAN2_TX_NUMBER 63 -#define STM32_CAN2_RX0_NUMBER 64 -#define STM32_CAN2_RX1_NUMBER 65 -#define STM32_CAN2_SCE_NUMBER 66 - -/* - * I2C units. - */ -#define STM32_I2C1_EVENT_HANDLER VectorBC -#define STM32_I2C1_ERROR_HANDLER VectorC0 -#define STM32_I2C1_EVENT_NUMBER 31 -#define STM32_I2C1_ERROR_NUMBER 32 - -#define STM32_I2C2_EVENT_HANDLER VectorC4 -#define STM32_I2C2_ERROR_HANDLER VectorC8 -#define STM32_I2C2_EVENT_NUMBER 33 -#define STM32_I2C2_ERROR_NUMBER 34 - -#define STM32_I2C3_EVENT_HANDLER Vector160 -#define STM32_I2C3_ERROR_HANDLER Vector164 -#define STM32_I2C3_EVENT_NUMBER 72 -#define STM32_I2C3_ERROR_NUMBER 73 - -/* - * OTG units. - */ -#define STM32_OTG1_HANDLER Vector14C -#define STM32_OTG2_HANDLER Vector174 -#define STM32_OTG2_EP1OUT_HANDLER Vector168 -#define STM32_OTG2_EP1IN_HANDLER Vector16C - -#define STM32_OTG1_NUMBER 67 -#define STM32_OTG2_NUMBER 77 -#define STM32_OTG2_EP1OUT_NUMBER 74 -#define STM32_OTG2_EP1IN_NUMBER 75 - -/* - * SDIO unit. - */ -#define STM32_SDIO_HANDLER Vector104 - -#define STM32_SDIO_NUMBER 49 - -/* - * TIM units. - */ -#define STM32_TIM1_UP_HANDLER VectorA4 -#define STM32_TIM1_CC_HANDLER VectorAC -#define STM32_TIM2_HANDLER VectorB0 -#define STM32_TIM3_HANDLER VectorB4 -#define STM32_TIM4_HANDLER VectorB8 -#define STM32_TIM5_HANDLER Vector108 -#define STM32_TIM6_HANDLER Vector118 -#define STM32_TIM7_HANDLER Vector11C -#define STM32_TIM8_UP_HANDLER VectorF0 -#define STM32_TIM8_CC_HANDLER VectorF8 -#define STM32_TIM9_HANDLER VectorA0 -#define STM32_TIM10_HANDLER VectorA4 /* Note: same as STM32_TIM1_UP */ -#define STM32_TIM11_HANDLER VectorA8 -#define STM32_TIM12_HANDLER VectorEC -#define STM32_TIM13_HANDLER VectorF0 /* Note: same as STM32_TIM8_UP */ -#define STM32_TIM14_HANDLER VectorF4 - -#define STM32_TIM1_UP_NUMBER 25 -#define STM32_TIM1_CC_NUMBER 27 -#define STM32_TIM2_NUMBER 28 -#define STM32_TIM3_NUMBER 29 -#define STM32_TIM4_NUMBER 30 -#define STM32_TIM5_NUMBER 50 -#define STM32_TIM6_NUMBER 54 -#define STM32_TIM7_NUMBER 55 -#define STM32_TIM8_UP_NUMBER 44 -#define STM32_TIM8_CC_NUMBER 46 -#define STM32_TIM9_NUMBER 24 -#define STM32_TIM10_NUMBER 25 /* Note: same as STM32_TIM1_UP */ -#define STM32_TIM11_NUMBER 26 -#define STM32_TIM12_NUMBER 43 -#define STM32_TIM13_NUMBER 44 /* Note: same as STM32_TIM8_UP */ -#define STM32_TIM14_NUMBER 45 - -/* - * USART units. - */ -#define STM32_USART1_HANDLER VectorD4 -#define STM32_USART2_HANDLER VectorD8 -#define STM32_USART3_HANDLER VectorDC -#define STM32_UART4_HANDLER Vector110 -#define STM32_UART5_HANDLER Vector114 -#define STM32_USART6_HANDLER Vector15C -#define STM32_UART7_HANDLER Vector188 -#define STM32_UART8_HANDLER Vector18C - -#define STM32_USART1_NUMBER 37 -#define STM32_USART2_NUMBER 38 -#define STM32_USART3_NUMBER 39 -#define STM32_UART4_NUMBER 52 -#define STM32_UART5_NUMBER 53 -#define STM32_USART6_NUMBER 71 -#define STM32_UART7_NUMBER 82 -#define STM32_UART8_NUMBER 83 - -/* - * Ethernet - */ -#define ETH_IRQHandler Vector134 - -/* - * FSMC - */ -#define STM32_FSMC_HANDLER Vector100 - -#define STM32_FSMC_NUMBER 48 - -/* - * LTDC - */ -#define STM32_LTDC_EV_HANDLER Vector1A0 -#define STM32_LTDC_ER_HANDLER Vector1A4 - -#define STM32_LTDC_EV_NUMBER 88 -#define STM32_LTDC_ER_NUMBER 89 - -/* - * DMA2D - */ -#define STM32_DMA2D_HANDLER Vector1A8 - -#define STM32_DMA2D_NUMBER 90 - -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#endif /* _STM32_ISR_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h b/firmware/ChibiOS_16/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h deleted file mode 100644 index f058001224..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h +++ /dev/null @@ -1,1614 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F4xx/stm32_rcc.h - * @brief RCC helper driver header. - * @note This file requires definitions from the ST header file - * @p stm32f4xx.h. - * - * @addtogroup STM32F4xx_RCC - * @{ - */ -#ifndef _STM32_RCC_ -#define _STM32_RCC_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Generic RCC operations - * @{ - */ -/** - * @brief Enables the clock of one or more peripheral on the APB1 bus. - * - * @param[in] mask APB1 peripherals mask - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableAPB1(mask, lp) { \ - RCC->APB1ENR |= (mask); \ - if (lp) \ - RCC->APB1LPENR |= (mask); \ -} - -/** - * @brief Disables the clock of one or more peripheral on the APB1 bus. - * - * @param[in] mask APB1 peripherals mask - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableAPB1(mask, lp) { \ - RCC->APB1ENR &= ~(mask); \ - if (lp) \ - RCC->APB1LPENR &= ~(mask); \ -} - -/** - * @brief Resets one or more peripheral on the APB1 bus. - * - * @param[in] mask APB1 peripherals mask - * - * @api - */ -#define rccResetAPB1(mask) { \ - RCC->APB1RSTR |= (mask); \ - RCC->APB1RSTR = 0; \ -} - -/** - * @brief Enables the clock of one or more peripheral on the APB2 bus. - * - * @param[in] mask APB2 peripherals mask - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableAPB2(mask, lp) { \ - RCC->APB2ENR |= (mask); \ - if (lp) \ - RCC->APB2LPENR |= (mask); \ -} - -/** - * @brief Disables the clock of one or more peripheral on the APB2 bus. - * - * @param[in] mask APB2 peripherals mask - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableAPB2(mask, lp) { \ - RCC->APB2ENR &= ~(mask); \ - if (lp) \ - RCC->APB2LPENR &= ~(mask); \ -} - -/** - * @brief Resets one or more peripheral on the APB2 bus. - * - * @param[in] mask APB2 peripherals mask - * - * @api - */ -#define rccResetAPB2(mask) { \ - RCC->APB2RSTR |= (mask); \ - RCC->APB2RSTR = 0; \ -} - -/** - * @brief Enables the clock of one or more peripheral on the AHB1 bus. - * - * @param[in] mask AHB1 peripherals mask - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableAHB1(mask, lp) { \ - RCC->AHB1ENR |= (mask); \ - if (lp) \ - RCC->AHB1LPENR |= (mask); \ -} - -/** - * @brief Disables the clock of one or more peripheral on the AHB1 bus. - * - * @param[in] mask AHB1 peripherals mask - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableAHB1(mask, lp) { \ - RCC->AHB1ENR &= ~(mask); \ - if (lp) \ - RCC->AHB1LPENR &= ~(mask); \ -} - -/** - * @brief Resets one or more peripheral on the AHB1 bus. - * - * @param[in] mask AHB1 peripherals mask - * - * @api - */ -#define rccResetAHB1(mask) { \ - RCC->AHB1RSTR |= (mask); \ - RCC->AHB1RSTR = 0; \ -} - -/** - * @brief Enables the clock of one or more peripheral on the AHB2 bus. - * - * @param[in] mask AHB2 peripherals mask - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableAHB2(mask, lp) { \ - RCC->AHB2ENR |= (mask); \ - if (lp) \ - RCC->AHB2LPENR |= (mask); \ -} - -/** - * @brief Disables the clock of one or more peripheral on the AHB2 bus. - * - * @param[in] mask AHB2 peripherals mask - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableAHB2(mask, lp) { \ - RCC->AHB2ENR &= ~(mask); \ - if (lp) \ - RCC->AHB2LPENR &= ~(mask); \ -} - -/** - * @brief Resets one or more peripheral on the AHB2 bus. - * - * @param[in] mask AHB2 peripherals mask - * - * @api - */ -#define rccResetAHB2(mask) { \ - RCC->AHB2RSTR |= (mask); \ - RCC->AHB2RSTR = 0; \ -} - -/** - * @brief Enables the clock of one or more peripheral on the AHB3 (FSMC) bus. - * - * @param[in] mask AHB3 peripherals mask - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableAHB3(mask, lp) { \ - RCC->AHB3ENR |= (mask); \ - if (lp) \ - RCC->AHB3LPENR |= (mask); \ -} - -/** - * @brief Disables the clock of one or more peripheral on the AHB3 (FSMC) bus. - * - * @param[in] mask AHB3 peripherals mask - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableAHB3(mask, lp) { \ - RCC->AHB3ENR &= ~(mask); \ - if (lp) \ - RCC->AHB3LPENR &= ~(mask); \ -} - -/** - * @brief Resets one or more peripheral on the AHB3 (FSMC) bus. - * - * @param[in] mask AHB3 peripherals mask - * - * @api - */ -#define rccResetAHB3(mask) { \ - RCC->AHB3RSTR |= (mask); \ - RCC->AHB3RSTR = 0; \ -} -/** @} */ - -/** - * @name ADC peripherals specific RCC operations - * @{ - */ -/** - * @brief Enables the ADC1 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp) - -/** - * @brief Disables the ADC1 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableADC1(lp) rccDisableAPB2(RCC_APB2ENR_ADC1EN, lp) - -/** - * @brief Resets the ADC1 peripheral. - * - * @api - */ -#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST) - -/** - * @brief Enables the ADC2 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableADC2(lp) rccEnableAPB2(RCC_APB2ENR_ADC2EN, lp) - -/** - * @brief Disables the ADC2 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableADC2(lp) rccDisableAPB2(RCC_APB2ENR_ADC2EN, lp) - -/** - * @brief Resets the ADC2 peripheral. - * - * @api - */ -#define rccResetADC2() rccResetAPB2(RCC_APB2RSTR_ADC2RST) - -/** - * @brief Enables the ADC3 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableADC3(lp) rccEnableAPB2(RCC_APB2ENR_ADC3EN, lp) - -/** - * @brief Disables the ADC3 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableADC3(lp) rccDisableAPB2(RCC_APB2ENR_ADC3EN, lp) - -/** - * @brief Resets the ADC3 peripheral. - * - * @api - */ -#define rccResetADC3() rccResetAPB2(RCC_APB2RSTR_ADC3RST) -/** @} */ - -/** - * @name DAC peripheral specific RCC operations - * @{ - */ -/** - * @brief Enables the DAC1 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableDAC1(lp) rccEnableAPB1(RCC_APB1ENR_DACEN, lp) - -/** - * @brief Disables the DAC1 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableDAC1(lp) rccDisableAPB1(RCC_APB1ENR_DACEN, lp) - -/** - * @brief Resets the DAC1 peripheral. - * - * @api - */ -#define rccResetDAC1() rccResetAPB1(RCC_APB1RSTR_DACRST) -/** @} */ - -/** - * @name DMA peripheral specific RCC operations - * @{ - */ -/** - * @brief Enables the DMA1 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableDMA1(lp) rccEnableAHB1(RCC_AHB1ENR_DMA1EN, lp) - -/** - * @brief Disables the DMA1 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableDMA1(lp) rccDisableAHB1(RCC_AHB1ENR_DMA1EN, lp) - -/** - * @brief Resets the DMA1 peripheral. - * - * @api - */ -#define rccResetDMA1() rccResetAHB1(RCC_AHB1RSTR_DMA1RST) - -/** - * @brief Enables the DMA2 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableDMA2(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2EN, lp) - -/** - * @brief Disables the DMA2 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableDMA2(lp) rccDisableAHB1(RCC_AHB1ENR_DMA2EN, lp) - -/** - * @brief Resets the DMA2 peripheral. - * - * @api - */ -#define rccResetDMA2() rccResetAHB1(RCC_AHB1RSTR_DMA2RST) -/** @} */ - -/** - * @name BKPSRAM specific RCC operations - * @{ - */ -/** - * @brief Enables the BKPSRAM peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableBKPSRAM(lp) rccEnableAHB1(RCC_AHB1ENR_BKPSRAMEN, lp) - -/** - * @brief Disables the BKPSRAM peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableBKPSRAM(lp) rccDisableAHB1(RCC_AHB1ENR_BKPSRAMEN, lp) -/** @} */ - -/** - * @name PWR interface specific RCC operations - * @{ - */ -/** - * @brief Enables the PWR interface clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp) - -/** - * @brief Disables PWR interface clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp) - -/** - * @brief Resets the PWR interface. - * - * @api - */ -#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST) -/** @} */ - -/** - * @name CAN peripherals specific RCC operations - * @{ - */ -/** - * @brief Enables the CAN1 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableCAN1(lp) rccEnableAPB1(RCC_APB1ENR_CAN1EN, lp) - -/** - * @brief Disables the CAN1 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableCAN1(lp) rccDisableAPB1(RCC_APB1ENR_CAN1EN, lp) - -/** - * @brief Resets the CAN1 peripheral. - * - * @api - */ -#define rccResetCAN1() rccResetAPB1(RCC_APB1RSTR_CAN1RST) - -/** - * @brief Enables the CAN2 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableCAN2(lp) rccEnableAPB1(RCC_APB1ENR_CAN2EN, lp) - -/** - * @brief Disables the CAN2 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableCAN2(lp) rccDisableAPB1(RCC_APB1ENR_CAN2EN, lp) - -/** - * @brief Resets the CAN2 peripheral. - * - * @api - */ -#define rccResetCAN2() rccResetAPB1(RCC_APB1RSTR_CAN2RST) -/** @} */ - -/** - * @name ETH peripheral specific RCC operations - * @{ - */ -/** - * @brief Enables the ETH peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableETH(lp) rccEnableAHB1(RCC_AHB1ENR_ETHMACEN | \ - RCC_AHB1ENR_ETHMACTXEN | \ - RCC_AHB1ENR_ETHMACRXEN, lp) - -/** - * @brief Disables the ETH peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableETH(lp) rccDisableAHB1(RCC_AHB1ENR_ETHMACEN | \ - RCC_AHB1ENR_ETHMACTXEN | \ - RCC_AHB1ENR_ETHMACRXEN, lp) - -/** - * @brief Resets the ETH peripheral. - * - * @api - */ -#define rccResetETH() rccResetAHB1(RCC_AHB1RSTR_ETHMACRST) -/** @} */ - -/** - * @name I2C peripherals specific RCC operations - * @{ - */ -/** - * @brief Enables the I2C1 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp) - -/** - * @brief Disables the I2C1 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableI2C1(lp) rccDisableAPB1(RCC_APB1ENR_I2C1EN, lp) - -/** - * @brief Resets the I2C1 peripheral. - * - * @api - */ -#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST) - -/** - * @brief Enables the I2C2 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp) - -/** - * @brief Disables the I2C2 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableI2C2(lp) rccDisableAPB1(RCC_APB1ENR_I2C2EN, lp) - -/** - * @brief Resets the I2C2 peripheral. - * - * @api - */ -#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST) - -/** - * @brief Enables the I2C3 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableI2C3(lp) rccEnableAPB1(RCC_APB1ENR_I2C3EN, lp) - -/** - * @brief Disables the I2C3 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableI2C3(lp) rccDisableAPB1(RCC_APB1ENR_I2C3EN, lp) - -/** - * @brief Resets the I2C3 peripheral. - * - * @api - */ -#define rccResetI2C3() rccResetAPB1(RCC_APB1RSTR_I2C3RST) -/** @} */ - -/** - * @name OTG peripherals specific RCC operations - * @{ - */ -/** - * @brief Enables the OTG_FS peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableOTG_FS(lp) rccEnableAHB2(RCC_AHB2ENR_OTGFSEN, lp) - -/** - * @brief Disables the OTG_FS peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableOTG_FS(lp) rccDisableAHB2(RCC_AHB2ENR_OTGFSEN, lp) - -/** - * @brief Resets the OTG_FS peripheral. - * - * @api - */ -#define rccResetOTG_FS() rccResetAHB2(RCC_AHB2RSTR_OTGFSRST) - -/** - * @brief Enables the OTG_HS peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableOTG_HS(lp) rccEnableAHB1(RCC_AHB1ENR_OTGHSEN, lp) - -/** - * @brief Disables the OTG_HS peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableOTG_HS(lp) rccDisableAHB1(RCC_AHB1ENR_OTGHSEN, lp) - -/** - * @brief Resets the OTG_HS peripheral. - * - * @api - */ -#define rccResetOTG_HS() rccResetAHB1(RCC_AHB1RSTR_OTGHRST) - -/** - * @brief Enables the OTG_HS peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableOTG_HSULPI(lp) rccEnableAHB1(RCC_AHB1ENR_OTGHSULPIEN, lp) - -/** - * @brief Disables the OTG_HS peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableOTG_HSULPI(lp) rccDisableAHB1(RCC_AHB1ENR_OTGHSULPIEN, lp) -/** @} */ - -/** - * @name SDIO peripheral specific RCC operations - * @{ - */ -/** - * @brief Enables the SDIO peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableSDIO(lp) rccEnableAPB2(RCC_APB2ENR_SDIOEN, lp) - -/** - * @brief Disables the SDIO peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableSDIO(lp) rccDisableAPB2(RCC_APB2ENR_SDIOEN, lp) - -/** - * @brief Resets the SDIO peripheral. - * @note Not supported in this family, does nothing. - * - * @api - */ -#define rccResetSDIO() rccResetAPB2(RCC_APB2RSTR_SDIORST) -/** @} */ - -/** - * @name SPI peripherals specific RCC operations - * @{ - */ -/** - * @brief Enables the SPI1 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp) - -/** - * @brief Disables the SPI1 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp) - -/** - * @brief Resets the SPI1 peripheral. - * - * @api - */ -#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST) - -/** - * @brief Enables the SPI2 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp) - -/** - * @brief Disables the SPI2 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableSPI2(lp) rccDisableAPB1(RCC_APB1ENR_SPI2EN, lp) - -/** - * @brief Resets the SPI2 peripheral. - * - * @api - */ -#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST) - -/** - * @brief Enables the SPI3 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableSPI3(lp) rccEnableAPB1(RCC_APB1ENR_SPI3EN, lp) - -/** - * @brief Disables the SPI3 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableSPI3(lp) rccDisableAPB1(RCC_APB1ENR_SPI3EN, lp) - -/** - * @brief Resets the SPI3 peripheral. - * - * @api - */ -#define rccResetSPI3() rccResetAPB1(RCC_APB1RSTR_SPI3RST) - -/** - * @brief Enables the SPI4 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableSPI4(lp) rccEnableAPB2(RCC_APB2ENR_SPI4EN, lp) - -/** - * @brief Disables the SPI4 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableSPI4(lp) rccDisableAPB2(RCC_APB2ENR_SPI4EN, lp) - -/** - * @brief Resets the SPI4 peripheral. - * - * @api - */ -#define rccResetSPI4() rccResetAPB2(RCC_APB2RSTR_SPI4RST) - -/** - * @brief Enables the SPI5 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableSPI5(lp) rccEnableAPB2(RCC_APB2ENR_SPI5EN, lp) - -/** - * @brief Disables the SPI5 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableSPI5(lp) rccDisableAPB2(RCC_APB2ENR_SPI5EN, lp) - -/** - * @brief Resets the SPI5 peripheral. - * - * @api - */ -#define rccResetSPI5() rccResetAPB2(RCC_APB2RSTR_SPI5RST) - -/** - * @brief Enables the SPI6 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableSPI6(lp) rccEnableAPB2(RCC_APB2ENR_SPI6EN, lp) - -/** - * @brief Disables the SPI6 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableSPI6(lp) rccDisableAPB2(RCC_APB2ENR_SPI6EN, lp) - -/** - * @brief Resets the SPI6 peripheral. - * - * @api - */ -#define rccResetSPI6() rccResetAPB2(RCC_APB2RSTR_SPI6RST) -/** @} */ - -/** - * @name TIM peripherals specific RCC operations - * @{ - */ -/** - * @brief Enables the TIM1 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp) - -/** - * @brief Disables the TIM1 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM1(lp) rccDisableAPB2(RCC_APB2ENR_TIM1EN, lp) - -/** - * @brief Resets the TIM1 peripheral. - * - * @api - */ -#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST) - -/** - * @brief Enables the TIM2 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp) - -/** - * @brief Disables the TIM2 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp) - -/** - * @brief Resets the TIM2 peripheral. - * - * @api - */ -#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST) - -/** - * @brief Enables the TIM3 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp) - -/** - * @brief Disables the TIM3 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp) - -/** - * @brief Resets the TIM3 peripheral. - * - * @api - */ -#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST) - -/** - * @brief Enables the TIM4 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM4(lp) rccEnableAPB1(RCC_APB1ENR_TIM4EN, lp) - -/** - * @brief Disables the TIM4 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM4(lp) rccDisableAPB1(RCC_APB1ENR_TIM4EN, lp) - -/** - * @brief Resets the TIM4 peripheral. - * - * @api - */ -#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST) - -/** - * @brief Enables the TIM5 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM5(lp) rccEnableAPB1(RCC_APB1ENR_TIM5EN, lp) - -/** - * @brief Disables the TIM5 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM5(lp) rccDisableAPB1(RCC_APB1ENR_TIM5EN, lp) - -/** - * @brief Resets the TIM5 peripheral. - * - * @api - */ -#define rccResetTIM5() rccResetAPB1(RCC_APB1RSTR_TIM5RST) - -/** - * @brief Enables the TIM6 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM6(lp) rccEnableAPB1(RCC_APB1ENR_TIM6EN, lp) - -/** - * @brief Disables the TIM6 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM6(lp) rccDisableAPB1(RCC_APB1ENR_TIM6EN, lp) - -/** - * @brief Resets the TIM6 peripheral. - * - * @api - */ -#define rccResetTIM6() rccResetAPB1(RCC_APB1RSTR_TIM6RST) - -/** - * @brief Enables the TIM7 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM7(lp) rccEnableAPB1(RCC_APB1ENR_TIM7EN, lp) - -/** - * @brief Disables the TIM7 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM7(lp) rccDisableAPB1(RCC_APB1ENR_TIM7EN, lp) - -/** - * @brief Resets the TIM7 peripheral. - * - * @api - */ -#define rccResetTIM7() rccResetAPB1(RCC_APB1RSTR_TIM7RST) - -/** - * @brief Enables the TIM8 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM8(lp) rccEnableAPB2(RCC_APB2ENR_TIM8EN, lp) - -/** - * @brief Disables the TIM8 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM8(lp) rccDisableAPB2(RCC_APB2ENR_TIM8EN, lp) - -/** - * @brief Resets the TIM8 peripheral. - * - * @api - */ -#define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST) - -/** - * @brief Enables the TIM9 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM9(lp) rccEnableAPB2(RCC_APB2ENR_TIM9EN, lp) - -/** - * @brief Disables the TIM9 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM9(lp) rccDisableAPB2(RCC_APB2ENR_TIM9EN, lp) - -/** - * @brief Resets the TIM9 peripheral. - * - * @api - */ -#define rccResetTIM9() rccResetAPB2(RCC_APB2RSTR_TIM9RST) - -/** - * @brief Enables the TIM10 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM10(lp) rccEnableAPB2(RCC_APB2ENR_TIM10EN, lp) - -/** - * @brief Disables the TIM10 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM10(lp) rccDisableAPB2(RCC_APB2ENR_TIM10EN, lp) - -/** - * @brief Resets the TIM10 peripheral. - * - * @api - */ -#define rccResetTIM10() rccResetAPB2(RCC_APB2RSTR_TIM10RST) - -/** - * @brief Enables the TIM11 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM11(lp) rccEnableAPB2(RCC_APB2ENR_TIM11EN, lp) - -/** - * @brief Disables the TIM11 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM11(lp) rccDisableAPB2(RCC_APB2ENR_TIM11EN, lp) - -/** - * @brief Resets the TIM11 peripheral. - * - * @api - */ -#define rccResetTIM11() rccResetAPB2(RCC_APB2RSTR_TIM11RST) - -/** - * @brief Enables the TIM12 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM12(lp) rccEnableAPB1(RCC_APB1ENR_TIM12EN, lp) - -/** - * @brief Disables the TIM12 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM12(lp) rccDisableAPB1(RCC_APB1ENR_TIM12EN, lp) - -/** - * @brief Resets the TIM12 peripheral. - * - * @api - */ -#define rccResetTIM12() rccResetAPB1(RCC_APB1RSTR_TIM12RST) - -/** - * @brief Enables the TIM13 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM13(lp) rccEnableAPB1(RCC_APB1ENR_TIM13EN, lp) - -/** - * @brief Disables the TIM13 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM13(lp) rccDisableAPB1(RCC_APB1ENR_TIM13EN, lp) - -/** - * @brief Resets the TIM13 peripheral. - * - * @api - */ -#define rccResetTIM13() rccResetAPB1(RCC_APB1RSTR_TIM13RST) - -/** - * @brief Enables the TIM14 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM14(lp) rccEnableAPB1(RCC_APB1ENR_TIM14EN, lp) - -/** - * @brief Disables the TIM14 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM14(lp) rccDisableAPB1(RCC_APB1ENR_TIM14EN, lp) - -/** - * @brief Resets the TIM14 peripheral. - * - * @api - */ -#define rccResetTIM14() rccResetAPB1(RCC_APB1RSTR_TIM14RST) -/** @} */ - -/** - * @name USART/UART peripherals specific RCC operations - * @{ - */ -/** - * @brief Enables the USART1 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp) - -/** - * @brief Disables the USART1 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp) - -/** - * @brief Resets the USART1 peripheral. - * - * @api - */ -#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST) - -/** - * @brief Enables the USART2 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp) - -/** - * @brief Disables the USART2 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableUSART2(lp) rccDisableAPB1(RCC_APB1ENR_USART2EN, lp) - -/** - * @brief Resets the USART2 peripheral. - * - * @api - */ -#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST) - -/** - * @brief Enables the USART3 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp) - -/** - * @brief Disables the USART3 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableUSART3(lp) rccDisableAPB1(RCC_APB1ENR_USART3EN, lp) - -/** - * @brief Resets the USART3 peripheral. - * - * @api - */ -#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST) - -/** - * @brief Enables the UART4 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableUART4(lp) rccEnableAPB1(RCC_APB1ENR_UART4EN, lp) - -/** - * @brief Disables the UART4 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableUART4(lp) rccDisableAPB1(RCC_APB1ENR_UART4EN, lp) - -/** - * @brief Resets the UART4 peripheral. - * - * @api - */ -#define rccResetUART4() rccResetAPB1(RCC_APB1RSTR_UART4RST) - -/** - * @brief Enables the UART5 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableUART5(lp) rccEnableAPB1(RCC_APB1ENR_UART5EN, lp) - -/** - * @brief Disables the UART5 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableUART5(lp) rccDisableAPB1(RCC_APB1ENR_UART5EN, lp) - -/** - * @brief Resets the UART5 peripheral. - * - * @api - */ -#define rccResetUART5() rccResetAPB1(RCC_APB1RSTR_UART5RST) - -/** - * @brief Enables the USART6 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableUSART6(lp) rccEnableAPB2(RCC_APB2ENR_USART6EN, lp) - -/** - * @brief Disables the USART6 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableUSART6(lp) rccDisableAPB2(RCC_APB2ENR_USART6EN, lp) - -/** - * @brief Resets the USART6 peripheral. - * - * @api - */ -#define rccResetUSART6() rccResetAPB2(RCC_APB2RSTR_USART6RST) - -/** - * @brief Enables the UART7 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableUART7(lp) rccEnableAPB1(RCC_APB1ENR_UART7EN, lp) - -/** - * @brief Disables the UART7 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableUART7(lp) rccDisableAPB1(RCC_APB1ENR_UART7EN, lp) - -/** - * @brief Resets the UART7 peripheral. - * - * @api - */ -#define rccResetUART7() rccResetAPB1(RCC_APB1RSTR_UART7RST) - -/** - * @brief Enables the UART8 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableUART8(lp) rccEnableAPB1(RCC_APB1ENR_UART8EN, lp) - -/** - * @brief Disables the UART8 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableUART8(lp) rccDisableAPB1(RCC_APB1ENR_UART8EN, lp) - -/** - * @brief Resets the UART8 peripheral. - * - * @api - */ -#define rccResetUART8() rccResetAPB1(RCC_APB1RSTR_UART8RST) -/** @} */ - -/** - * @name LTDC peripheral specific RCC operations - * @{ - */ -/** - * @brief Enables the LTDC peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableLTDC(lp) rccEnableAPB2(RCC_APB2ENR_LTDCEN, lp) - -/** - * @brief Disables the LTDC peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableLTDC(lp) rccDisableAPB2(RCC_APB2ENR_LTDCEN, lp) - -/** - * @brief Resets the LTDC peripheral. - * - * @api - */ -#define rccResetLTDC() rccResetAPB2(RCC_APB2RSTR_LTDCRST) - -/** - * @name DMA2D peripheral specific RCC operations - * @{ - */ -/** - * @brief Enables the DMA2D peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableDMA2D(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2DEN, lp) - -/** - * @brief Disables the DMA2D peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableDMA2D(lp) rccDisableAHB1(RCC_AHB1ENR_DMA2DEN, lp) - -/** - * @brief Resets the DMA2D peripheral. - * - * @api - */ -#define rccResetDMA2D() rccResetAHB1(RCC_AHB1RSTR_DMA2DRST) -/** @} */ - -/** - * @name FSMC peripherals specific RCC operations - * @{ - */ -/** - * @brief Enables the FSMC peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#if STM32_HAS_FSMC || defined(__DOXYGEN__) -#if STM32_FSMC_IS_FMC || defined(__DOXYGEN__) - #define rccEnableFSMC(lp) rccEnableAHB3(RCC_AHB3ENR_FMCEN, lp) -#else - #define rccEnableFSMC(lp) rccEnableAHB3(RCC_AHB3ENR_FSMCEN, lp) -#endif -#endif - -/** - * @brief Disables the FSMC peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#if STM32_HAS_FSMC || defined(__DOXYGEN__) -#if STM32_FSMC_IS_FMC || defined(__DOXYGEN__) - #define rccDisableFSMC(lp) rccDisableAHB3(RCC_AHB3ENR_FMCEN, lp) -#else - #define rccDisableFSMC(lp) rccDisableAHB3(RCC_AHB3ENR_FSMCEN, lp) -#endif -#endif - -/** - * @brief Resets the FSMC peripheral. - * - * @api - */ -#if STM32_HAS_FSMC || defined(__DOXYGEN__) -#if STM32_FSMC_IS_FMC || defined(__DOXYGEN__) - #define rccResetFSMC() rccResetAHB3(RCC_AHB3RSTR_FMCRST) -#else - #define rccResetFSMC() rccResetAHB3(RCC_AHB3RSTR_FSMCRST) -#endif -#endif -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif -#ifdef __cplusplus -} -#endif - -#endif /* _STM32_RCC_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/STM32/STM32F4xx/stm32_registry.h b/firmware/ChibiOS_16/os/hal/ports/STM32/STM32F4xx/stm32_registry.h deleted file mode 100644 index 2a3ccba80c..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/STM32/STM32F4xx/stm32_registry.h +++ /dev/null @@ -1,1686 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F4xx/stm32_registry.h - * @brief STM32F4xx capabilities registry. - * - * @addtogroup HAL - * @{ - */ - -#ifndef _STM32_REGISTRY_H_ -#define _STM32_REGISTRY_H_ - -#if defined(STM32F446xx) -#define STM32F4XX - -#elif defined(STM32F439xx) || defined(STM32F429xx) -#define STM32F429_439xx -#define STM32F4XX - -#elif defined(STM32F437xx) || defined(STM32F427xx) -#define STM32F427_437xx -#define STM32F4XX - -#elif defined(STM32F405xx) || defined(STM32F415xx) || \ - defined(STM32F407xx) || defined(STM32F417xx) -#define STM32F40_41xxx -#define STM32F4XX - -#elif defined(STM32F401xC) || defined(STM32F401xE) -#define STM32F401xx -#define STM32F4XX - -#elif defined(STM32F411xE) -#define STM32F411xx -#define STM32F4XX - -#elif defined(STM32F205xx) || defined(STM32F215xx) || \ - defined(STM32F207xx) || defined(STM32F217xx) -#define STM32F2XX - -#else -#error "STM32F2xx/F4xx device not specified" -#endif - -/*===========================================================================*/ -/* Platform capabilities. */ -/*===========================================================================*/ - -/** - * @name STM32F4xx/STM32F2xx capabilities - * @{ - */ - -/*===========================================================================*/ -/* STM32F446xx. */ -/*===========================================================================*/ -#if defined(STM32F446xx) -/* ADC attributes.*/ -#define STM32_ADC_HANDLER Vector88 -#define STM32_ADC_NUMBER 18 - -#define STM32_HAS_ADC1 TRUE -#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ - STM32_DMA_STREAM_ID_MSK(2, 4)) -#define STM32_ADC1_DMA_CHN 0x00000000 - -#define STM32_HAS_ADC2 TRUE -#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\ - STM32_DMA_STREAM_ID_MSK(2, 3)) -#define STM32_ADC2_DMA_CHN 0x00001100 - -#define STM32_HAS_ADC3 TRUE -#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ - STM32_DMA_STREAM_ID_MSK(2, 1)) -#define STM32_ADC3_DMA_CHN 0x00000022 - -#define STM32_HAS_ADC4 FALSE - -#define STM32_HAS_SDADC1 FALSE -#define STM32_HAS_SDADC2 FALSE -#define STM32_HAS_SDADC3 FALSE - -/* CAN attributes.*/ -#define STM32_HAS_CAN1 TRUE -#define STM32_HAS_CAN2 TRUE -#define STM32_CAN_MAX_FILTERS 28 - -/* DAC attributes.*/ -#define STM32_HAS_DAC1_CH1 TRUE -#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_DAC1_CH1_DMA_CHN 0x00700000 - -#define STM32_HAS_DAC1_CH2 TRUE -#define STM32_DAC1_CH2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_DAC1_CH2_DMA_CHN 0x07000000 - -#define STM32_HAS_DAC2_CH1 FALSE -#define STM32_HAS_DAC2_CH2 FALSE - -/* DMA attributes.*/ -#define STM32_ADVANCED_DMA TRUE -#define STM32_DMA_CACHE_HANDLING FALSE - -#define STM32_HAS_DMA1 TRUE -#define STM32_DMA1_CH0_HANDLER Vector6C -#define STM32_DMA1_CH1_HANDLER Vector70 -#define STM32_DMA1_CH2_HANDLER Vector74 -#define STM32_DMA1_CH3_HANDLER Vector78 -#define STM32_DMA1_CH4_HANDLER Vector7C -#define STM32_DMA1_CH5_HANDLER Vector80 -#define STM32_DMA1_CH6_HANDLER Vector84 -#define STM32_DMA1_CH7_HANDLER VectorFC -#define STM32_DMA1_CH0_NUMBER 11 -#define STM32_DMA1_CH1_NUMBER 12 -#define STM32_DMA1_CH2_NUMBER 13 -#define STM32_DMA1_CH3_NUMBER 14 -#define STM32_DMA1_CH4_NUMBER 15 -#define STM32_DMA1_CH5_NUMBER 16 -#define STM32_DMA1_CH6_NUMBER 17 -#define STM32_DMA1_CH7_NUMBER 47 - -#define STM32_HAS_DMA2 TRUE -#define STM32_DMA2_CH0_HANDLER Vector120 -#define STM32_DMA2_CH1_HANDLER Vector124 -#define STM32_DMA2_CH2_HANDLER Vector128 -#define STM32_DMA2_CH3_HANDLER Vector12C -#define STM32_DMA2_CH4_HANDLER Vector130 -#define STM32_DMA2_CH5_HANDLER Vector150 -#define STM32_DMA2_CH6_HANDLER Vector154 -#define STM32_DMA2_CH7_HANDLER Vector158 -#define STM32_DMA2_CH0_NUMBER 56 -#define STM32_DMA2_CH1_NUMBER 57 -#define STM32_DMA2_CH2_NUMBER 58 -#define STM32_DMA2_CH3_NUMBER 59 -#define STM32_DMA2_CH4_NUMBER 60 -#define STM32_DMA2_CH5_NUMBER 68 -#define STM32_DMA2_CH6_NUMBER 69 -#define STM32_DMA2_CH7_NUMBER 70 - -/* ETH attributes.*/ -#define STM32_HAS_ETH FALSE - -/* EXTI attributes.*/ -#define STM32_EXTI_NUM_LINES 23 -#define STM32_EXTI_IMR_MASK 0x00000000U - -/* GPIO attributes.*/ -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE TRUE -#define STM32_HAS_GPIOH TRUE -#define STM32_HAS_GPIOF TRUE -#define STM32_HAS_GPIOG TRUE -#define STM32_HAS_GPIOI FALSE -#define STM32_HAS_GPIOJ FALSE -#define STM32_HAS_GPIOK FALSE - -#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \ - RCC_AHB1ENR_GPIOBEN | \ - RCC_AHB1ENR_GPIOCEN | \ - RCC_AHB1ENR_GPIODEN | \ - RCC_AHB1ENR_GPIOEEN | \ - RCC_AHB1ENR_GPIOFEN | \ - RCC_AHB1ENR_GPIOGEN | \ - RCC_AHB1ENR_GPIOHEN) - -/* I2C attributes.*/ -#define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ - STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_I2C1_RX_DMA_CHN 0x00100001 -#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\ - STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_I2C1_TX_DMA_CHN 0x11000000 - -#define STM32_HAS_I2C2 TRUE -#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ - STM32_DMA_STREAM_ID_MSK(1, 3)) -#define STM32_I2C2_RX_DMA_CHN 0x00007700 -#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7) -#define STM32_I2C2_TX_DMA_CHN 0x70000000 - -#define STM32_HAS_I2C3 TRUE -#define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) -#define STM32_I2C3_RX_DMA_CHN 0x00000300 -#define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) -#define STM32_I2C3_TX_DMA_CHN 0x00030000 - -#define STM32_HAS_I2C4 FALSE - -/* RTC attributes.*/ -#define STM32_HAS_RTC TRUE -#define STM32_RTC_HAS_SUBSECONDS TRUE -#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE -#define STM32_RTC_NUM_ALARMS 2 -#define STM32_RTC_HAS_INTERRUPTS FALSE - -/* SDIO attributes.*/ -#define STM32_HAS_SDIO TRUE -#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ - STM32_DMA_STREAM_ID_MSK(2, 6)) -#define STM32_SDC_SDIO_DMA_CHN 0x04004000 - -/* SPI attributes.*/ -#define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_SUPPORTS_I2S FALSE -#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ - STM32_DMA_STREAM_ID_MSK(2, 2)) -#define STM32_SPI1_RX_DMA_CHN 0x00000303 -#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ - STM32_DMA_STREAM_ID_MSK(2, 5)) -#define STM32_SPI1_TX_DMA_CHN 0x00303000 - -#define STM32_HAS_SPI2 TRUE -#define STM32_SPI2_SUPPORTS_I2S TRUE -#define STM32_SPI2_I2S_FULLDUPLEX TRUE -#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) -#define STM32_SPI2_RX_DMA_CHN 0x00000000 -#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) -#define STM32_SPI2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI3 TRUE -#define STM32_SPI3_SUPPORTS_I2S TRUE -#define STM32_SPI3_I2S_FULLDUPLEX TRUE -#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ - STM32_DMA_STREAM_ID_MSK(1, 2)) -#define STM32_SPI3_RX_DMA_CHN 0x00000000 -#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\ - STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_SPI3_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI4 TRUE -#define STM32_SPI4_SUPPORTS_I2S FALSE -#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ - STM32_DMA_STREAM_ID_MSK(2, 3)) -#define STM32_SPI4_RX_DMA_CHN 0x00005004 -#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\ - STM32_DMA_STREAM_ID_MSK(2, 4)) -#define STM32_SPI4_TX_DMA_CHN 0x00050040 - -#define STM32_HAS_SPI5 FALSE -#define STM32_HAS_SPI6 FALSE - -/* TIM attributes.*/ -#define STM32_TIM_MAX_CHANNELS 4 - -#define STM32_HAS_TIM1 TRUE -#define STM32_TIM1_IS_32BITS FALSE -#define STM32_TIM1_CHANNELS 4 - -#define STM32_HAS_TIM2 TRUE -#define STM32_TIM2_IS_32BITS TRUE -#define STM32_TIM2_CHANNELS 4 - -#define STM32_HAS_TIM3 TRUE -#define STM32_TIM3_IS_32BITS FALSE -#define STM32_TIM3_CHANNELS 4 - -#define STM32_HAS_TIM4 TRUE -#define STM32_TIM4_IS_32BITS FALSE -#define STM32_TIM4_CHANNELS 4 - -#define STM32_HAS_TIM5 TRUE -#define STM32_TIM5_IS_32BITS TRUE -#define STM32_TIM5_CHANNELS 4 - -#define STM32_HAS_TIM6 TRUE -#define STM32_TIM6_IS_32BITS FALSE -#define STM32_TIM6_CHANNELS 0 - -#define STM32_HAS_TIM7 TRUE -#define STM32_TIM7_IS_32BITS FALSE -#define STM32_TIM7_CHANNELS 0 - -#define STM32_HAS_TIM8 TRUE -#define STM32_TIM8_IS_32BITS FALSE -#define STM32_TIM8_CHANNELS 6 - -#define STM32_HAS_TIM9 TRUE -#define STM32_TIM9_IS_32BITS FALSE -#define STM32_TIM9_CHANNELS 2 - -#define STM32_HAS_TIM10 TRUE -#define STM32_TIM10_IS_32BITS FALSE -#define STM32_TIM10_CHANNELS 2 - -#define STM32_HAS_TIM11 TRUE -#define STM32_TIM11_IS_32BITS FALSE -#define STM32_TIM11_CHANNELS 2 - -#define STM32_HAS_TIM12 TRUE -#define STM32_TIM12_IS_32BITS FALSE -#define STM32_TIM12_CHANNELS 2 - -#define STM32_HAS_TIM13 TRUE -#define STM32_TIM13_IS_32BITS FALSE -#define STM32_TIM13_CHANNELS 2 - -#define STM32_HAS_TIM14 TRUE -#define STM32_TIM14_IS_32BITS FALSE -#define STM32_TIM14_CHANNELS 2 - -#define STM32_HAS_TIM15 FALSE -#define STM32_HAS_TIM16 FALSE -#define STM32_HAS_TIM17 FALSE -#define STM32_HAS_TIM18 FALSE -#define STM32_HAS_TIM19 FALSE -#define STM32_HAS_TIM20 FALSE -#define STM32_HAS_TIM21 FALSE -#define STM32_HAS_TIM22 FALSE - -/* USART attributes.*/ -#define STM32_HAS_USART1 TRUE -#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\ - STM32_DMA_STREAM_ID_MSK(2, 5)) -#define STM32_USART1_RX_DMA_CHN 0x00400400 -#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7) -#define STM32_USART1_TX_DMA_CHN 0x40000000 - -#define STM32_HAS_USART2 TRUE -#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) -#define STM32_USART2_RX_DMA_CHN 0x00400000 -#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6) -#define STM32_USART2_TX_DMA_CHN 0x04000000 - -#define STM32_HAS_USART3 TRUE -#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1) -#define STM32_USART3_RX_DMA_CHN 0x00000040 -#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\ - STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_USART3_TX_DMA_CHN 0x00074000 - -#define STM32_HAS_UART4 TRUE -#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) -#define STM32_UART4_RX_DMA_CHN 0x00000400 -#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) -#define STM32_UART4_TX_DMA_CHN 0x00040000 - -#define STM32_HAS_UART5 TRUE -#define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0) -#define STM32_UART5_RX_DMA_CHN 0x00000004 -#define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7) -#define STM32_UART5_TX_DMA_CHN 0x40000000 - -#define STM32_HAS_USART6 TRUE -#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\ - STM32_DMA_STREAM_ID_MSK(2, 2)) -#define STM32_USART6_RX_DMA_CHN 0x00000550 -#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\ - STM32_DMA_STREAM_ID_MSK(2, 7)) -#define STM32_USART6_TX_DMA_CHN 0x55000000 - -#define STM32_HAS_UART7 FALSE -#define STM32_HAS_UART8 FALSE -#define STM32_HAS_LPUART1 FALSE - -/* USB attributes.*/ -#define STM32_OTG_STEPPING 2 -#define STM32_HAS_OTG1 TRUE -#define STM32_OTG1_ENDPOINTS 6 -#define STM32_HAS_OTG2 TRUE -#define STM32_OTG2_ENDPOINTS 8 - -#define STM32_HAS_USB FALSE - -/* IWDG attributes.*/ -#define STM32_HAS_IWDG TRUE -#define STM32_IWDG_IS_WINDOWED FALSE - -/* LTDC attributes.*/ -#define STM32_HAS_LTDC TRUE - -/* DMA2D attributes.*/ -#define STM32_HAS_DMA2D TRUE - -/* FSMC attributes.*/ -#define STM32_HAS_FSMC TRUE -#define STM32_FSMC_IS_FMC TRUE -#define STM32_FSMC_HANDLER Vector100 -#define STM32_FSMC_NUMBER 48 - -/* CRC attributes.*/ -#define STM32_HAS_CRC TRUE -#define STM32_CRC_PROGRAMMABLE FALSE - -#endif /* defined(STM32F446xx) */ - -/*===========================================================================*/ -/* STM32F439xx, STM32F429xx, STM32F437xx, STM32F427xx. */ -/*===========================================================================*/ -#if defined(STM32F429_439xx) || defined(STM32F427_437xx) || \ - defined(__DOXYGEN__) -/* ADC attributes.*/ -#define STM32_ADC_HANDLER Vector88 -#define STM32_ADC_NUMBER 18 - -#define STM32_HAS_ADC1 TRUE -#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ - STM32_DMA_STREAM_ID_MSK(2, 4)) -#define STM32_ADC1_DMA_CHN 0x00000000 - -#define STM32_HAS_ADC2 TRUE -#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\ - STM32_DMA_STREAM_ID_MSK(2, 3)) -#define STM32_ADC2_DMA_CHN 0x00001100 - -#define STM32_HAS_ADC3 TRUE -#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ - STM32_DMA_STREAM_ID_MSK(2, 1)) -#define STM32_ADC3_DMA_CHN 0x00000022 - -#define STM32_HAS_ADC4 FALSE - -#define STM32_HAS_SDADC1 FALSE -#define STM32_HAS_SDADC2 FALSE -#define STM32_HAS_SDADC3 FALSE - -/* CAN attributes.*/ -#define STM32_HAS_CAN1 TRUE -#define STM32_HAS_CAN2 TRUE -#define STM32_CAN_MAX_FILTERS 28 - -/* DAC attributes.*/ -#define STM32_HAS_DAC1_CH1 TRUE -#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_DAC1_CH1_DMA_CHN 0x00700000 - -#define STM32_HAS_DAC1_CH2 TRUE -#define STM32_DAC1_CH2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_DAC1_CH2_DMA_CHN 0x07000000 - -#define STM32_HAS_DAC2_CH1 FALSE -#define STM32_HAS_DAC2_CH2 FALSE - -/* DMA attributes.*/ -#define STM32_ADVANCED_DMA TRUE -#define STM32_DMA_CACHE_HANDLING FALSE - -#define STM32_HAS_DMA1 TRUE -#define STM32_DMA1_CH0_HANDLER Vector6C -#define STM32_DMA1_CH1_HANDLER Vector70 -#define STM32_DMA1_CH2_HANDLER Vector74 -#define STM32_DMA1_CH3_HANDLER Vector78 -#define STM32_DMA1_CH4_HANDLER Vector7C -#define STM32_DMA1_CH5_HANDLER Vector80 -#define STM32_DMA1_CH6_HANDLER Vector84 -#define STM32_DMA1_CH7_HANDLER VectorFC -#define STM32_DMA1_CH0_NUMBER 11 -#define STM32_DMA1_CH1_NUMBER 12 -#define STM32_DMA1_CH2_NUMBER 13 -#define STM32_DMA1_CH3_NUMBER 14 -#define STM32_DMA1_CH4_NUMBER 15 -#define STM32_DMA1_CH5_NUMBER 16 -#define STM32_DMA1_CH6_NUMBER 17 -#define STM32_DMA1_CH7_NUMBER 47 - -#define STM32_HAS_DMA2 TRUE -#define STM32_DMA2_CH0_HANDLER Vector120 -#define STM32_DMA2_CH1_HANDLER Vector124 -#define STM32_DMA2_CH2_HANDLER Vector128 -#define STM32_DMA2_CH3_HANDLER Vector12C -#define STM32_DMA2_CH4_HANDLER Vector130 -#define STM32_DMA2_CH5_HANDLER Vector150 -#define STM32_DMA2_CH6_HANDLER Vector154 -#define STM32_DMA2_CH7_HANDLER Vector158 -#define STM32_DMA2_CH0_NUMBER 56 -#define STM32_DMA2_CH1_NUMBER 57 -#define STM32_DMA2_CH2_NUMBER 58 -#define STM32_DMA2_CH3_NUMBER 59 -#define STM32_DMA2_CH4_NUMBER 60 -#define STM32_DMA2_CH5_NUMBER 68 -#define STM32_DMA2_CH6_NUMBER 69 -#define STM32_DMA2_CH7_NUMBER 70 - -/* ETH attributes.*/ -#define STM32_HAS_ETH TRUE -#define STM32_ETH_HANDLER Vector134 -#define STM32_ETH_NUMBER 61 - -/* EXTI attributes.*/ -#define STM32_EXTI_NUM_LINES 23 -#define STM32_EXTI_IMR_MASK 0x00000000U - -/* GPIO attributes.*/ -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE TRUE -#define STM32_HAS_GPIOH TRUE -#define STM32_HAS_GPIOF TRUE -#define STM32_HAS_GPIOG TRUE -#define STM32_HAS_GPIOI TRUE -#define STM32_HAS_GPIOJ FALSE -#define STM32_HAS_GPIOK FALSE -#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \ - RCC_AHB1ENR_GPIOBEN | \ - RCC_AHB1ENR_GPIOCEN | \ - RCC_AHB1ENR_GPIODEN | \ - RCC_AHB1ENR_GPIOEEN | \ - RCC_AHB1ENR_GPIOFEN | \ - RCC_AHB1ENR_GPIOGEN | \ - RCC_AHB1ENR_GPIOHEN | \ - RCC_AHB1ENR_GPIOIEN) - -/* I2C attributes.*/ -#define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ - STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_I2C1_RX_DMA_CHN 0x00100001 -#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\ - STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_I2C1_TX_DMA_CHN 0x11000000 - -#define STM32_HAS_I2C2 TRUE -#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ - STM32_DMA_STREAM_ID_MSK(1, 3)) -#define STM32_I2C2_RX_DMA_CHN 0x00007700 -#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7) -#define STM32_I2C2_TX_DMA_CHN 0x70000000 - -#define STM32_HAS_I2C3 TRUE -#define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) -#define STM32_I2C3_RX_DMA_CHN 0x00000300 -#define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) -#define STM32_I2C3_TX_DMA_CHN 0x00030000 - -#define STM32_HAS_I2C4 FALSE - -/* RTC attributes.*/ -#define STM32_HAS_RTC TRUE -#define STM32_RTC_HAS_SUBSECONDS TRUE -#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE -#define STM32_RTC_NUM_ALARMS 2 -#define STM32_RTC_HAS_INTERRUPTS FALSE - -/* SDIO attributes.*/ -#define STM32_HAS_SDIO TRUE -#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ - STM32_DMA_STREAM_ID_MSK(2, 6)) -#define STM32_SDC_SDIO_DMA_CHN 0x04004000 - -/* SPI attributes.*/ -#define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_SUPPORTS_I2S FALSE -#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ - STM32_DMA_STREAM_ID_MSK(2, 2)) -#define STM32_SPI1_RX_DMA_CHN 0x00000303 -#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ - STM32_DMA_STREAM_ID_MSK(2, 5)) -#define STM32_SPI1_TX_DMA_CHN 0x00303000 - -#define STM32_HAS_SPI2 TRUE -#define STM32_SPI2_SUPPORTS_I2S TRUE -#define STM32_SPI2_I2S_FULLDUPLEX TRUE -#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) -#define STM32_SPI2_RX_DMA_CHN 0x00000000 -#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) -#define STM32_SPI2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI3 TRUE -#define STM32_SPI3_SUPPORTS_I2S TRUE -#define STM32_SPI3_I2S_FULLDUPLEX TRUE -#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ - STM32_DMA_STREAM_ID_MSK(1, 2)) -#define STM32_SPI3_RX_DMA_CHN 0x00000000 -#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\ - STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_SPI3_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI4 TRUE -#define STM32_SPI4_SUPPORTS_I2S FALSE -#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ - STM32_DMA_STREAM_ID_MSK(2, 3)) -#define STM32_SPI4_RX_DMA_CHN 0x00005004 -#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\ - STM32_DMA_STREAM_ID_MSK(2, 4)) -#define STM32_SPI4_TX_DMA_CHN 0x00050040 - -#define STM32_HAS_SPI5 TRUE -#define STM32_SPI5_SUPPORTS_I2S FALSE -#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) | \ - STM32_DMA_STREAM_ID_MSK(2, 5)) -#define STM32_SPI5_RX_DMA_CHN 0x00702000 -#define STM32_SPI5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) | \ - STM32_DMA_STREAM_ID_MSK(2, 6)) -#define STM32_SPI5_TX_DMA_CHN 0x07020000 - -#define STM32_HAS_SPI6 TRUE -#define STM32_SPI6_SUPPORTS_I2S FALSE -#define STM32_SPI6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6)) -#define STM32_SPI6_RX_DMA_CHN 0x01000000 -#define STM32_SPI6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5)) -#define STM32_SPI6_TX_DMA_CHN 0x00100000 - -/* TIM attributes.*/ -#define STM32_TIM_MAX_CHANNELS 4 - -#define STM32_HAS_TIM1 TRUE -#define STM32_TIM1_IS_32BITS FALSE -#define STM32_TIM1_CHANNELS 4 - -#define STM32_HAS_TIM2 TRUE -#define STM32_TIM2_IS_32BITS TRUE -#define STM32_TIM2_CHANNELS 4 - -#define STM32_HAS_TIM3 TRUE -#define STM32_TIM3_IS_32BITS FALSE -#define STM32_TIM3_CHANNELS 4 - -#define STM32_HAS_TIM4 TRUE -#define STM32_TIM4_IS_32BITS FALSE -#define STM32_TIM4_CHANNELS 4 - -#define STM32_HAS_TIM5 TRUE -#define STM32_TIM5_IS_32BITS TRUE -#define STM32_TIM5_CHANNELS 4 - -#define STM32_HAS_TIM6 TRUE -#define STM32_TIM6_IS_32BITS FALSE -#define STM32_TIM6_CHANNELS 0 - -#define STM32_HAS_TIM7 TRUE -#define STM32_TIM7_IS_32BITS FALSE -#define STM32_TIM7_CHANNELS 0 - -#define STM32_HAS_TIM8 TRUE -#define STM32_TIM8_IS_32BITS FALSE -#define STM32_TIM8_CHANNELS 6 - -#define STM32_HAS_TIM9 TRUE -#define STM32_TIM9_IS_32BITS FALSE -#define STM32_TIM9_CHANNELS 2 - -#define STM32_HAS_TIM10 TRUE -#define STM32_TIM10_IS_32BITS FALSE -#define STM32_TIM10_CHANNELS 2 - -#define STM32_HAS_TIM11 TRUE -#define STM32_TIM11_IS_32BITS FALSE -#define STM32_TIM11_CHANNELS 2 - -#define STM32_HAS_TIM12 TRUE -#define STM32_TIM12_IS_32BITS FALSE -#define STM32_TIM12_CHANNELS 2 - -#define STM32_HAS_TIM13 TRUE -#define STM32_TIM13_IS_32BITS FALSE -#define STM32_TIM13_CHANNELS 2 - -#define STM32_HAS_TIM14 TRUE -#define STM32_TIM14_IS_32BITS FALSE -#define STM32_TIM14_CHANNELS 2 - -#define STM32_HAS_TIM15 FALSE -#define STM32_HAS_TIM16 FALSE -#define STM32_HAS_TIM17 FALSE -#define STM32_HAS_TIM18 FALSE -#define STM32_HAS_TIM19 FALSE -#define STM32_HAS_TIM20 FALSE -#define STM32_HAS_TIM21 FALSE -#define STM32_HAS_TIM22 FALSE - -/* USART attributes.*/ -#define STM32_HAS_USART1 TRUE -#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\ - STM32_DMA_STREAM_ID_MSK(2, 5)) -#define STM32_USART1_RX_DMA_CHN 0x00400400 -#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7) -#define STM32_USART1_TX_DMA_CHN 0x40000000 - -#define STM32_HAS_USART2 TRUE -#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) -#define STM32_USART2_RX_DMA_CHN 0x00400000 -#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6) -#define STM32_USART2_TX_DMA_CHN 0x04000000 - -#define STM32_HAS_USART3 TRUE -#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1) -#define STM32_USART3_RX_DMA_CHN 0x00000040 -#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\ - STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_USART3_TX_DMA_CHN 0x00074000 - -#define STM32_HAS_UART4 TRUE -#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) -#define STM32_UART4_RX_DMA_CHN 0x00000400 -#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) -#define STM32_UART4_TX_DMA_CHN 0x00040000 - -#define STM32_HAS_UART5 TRUE -#define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0) -#define STM32_UART5_RX_DMA_CHN 0x00000004 -#define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7) -#define STM32_UART5_TX_DMA_CHN 0x40000000 - -#define STM32_HAS_USART6 TRUE -#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\ - STM32_DMA_STREAM_ID_MSK(2, 2)) -#define STM32_USART6_RX_DMA_CHN 0x00000550 -#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\ - STM32_DMA_STREAM_ID_MSK(2, 7)) -#define STM32_USART6_TX_DMA_CHN 0x55000000 - -#define STM32_HAS_UART7 TRUE -#define STM32_UART7_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) -#define STM32_UART7_RX_DMA_CHN 0x00005000 -#define STM32_UART7_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1) -#define STM32_UART7_TX_DMA_CHN 0x00000050 - -#define STM32_HAS_UART8 TRUE -#define STM32_UART8_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6) -#define STM32_UART8_RX_DMA_CHN 0x05000000 -#define STM32_UART8_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0) -#define STM32_UART8_TX_DMA_CHN 0x00000005 - -#define STM32_HAS_LPUART1 FALSE - -/* USB attributes.*/ -#define STM32_OTG_STEPPING 1 -#define STM32_HAS_OTG1 TRUE -#define STM32_OTG1_ENDPOINTS 3 -#define STM32_HAS_OTG2 TRUE -#define STM32_OTG2_ENDPOINTS 5 - -#define STM32_HAS_USB FALSE - -/* IWDG attributes.*/ -#define STM32_HAS_IWDG TRUE -#define STM32_IWDG_IS_WINDOWED FALSE - -/* LTDC attributes.*/ -#define STM32_HAS_LTDC TRUE - -/* DMA2D attributes.*/ -#define STM32_HAS_DMA2D TRUE - -/* FSMC attributes.*/ -#define STM32_HAS_FSMC TRUE -#define STM32_FSMC_IS_FMC TRUE -#define STM32_FSMC_HANDLER Vector100 -#define STM32_FSMC_NUMBER 48 - -/* CRC attributes.*/ -#define STM32_HAS_CRC TRUE -#define STM32_CRC_PROGRAMMABLE FALSE - -#endif /* defined(STM32F429_439xx) || defined(STM32F427_437xx) */ - -/*===========================================================================*/ -/* STM32F405xx, STM32F415xx, STM32F407xx, STM32F417xx, STM32F205xx */ -/* STM32F215xx, STM32F207xx, STM32F217xx. */ -/*===========================================================================*/ -#if defined(STM32F40_41xxx) || defined(STM32F2XX) -/* ADC attributes.*/ -#define STM32_ADC_HANDLER Vector88 -#define STM32_ADC_NUMBER 18 - -#define STM32_HAS_ADC1 TRUE -#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ - STM32_DMA_STREAM_ID_MSK(2, 4)) -#define STM32_ADC1_DMA_CHN 0x00000000 - -#define STM32_HAS_ADC2 TRUE -#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\ - STM32_DMA_STREAM_ID_MSK(2, 3)) -#define STM32_ADC2_DMA_CHN 0x00001100 - -#define STM32_HAS_ADC3 TRUE -#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ - STM32_DMA_STREAM_ID_MSK(2, 1)) -#define STM32_ADC3_DMA_CHN 0x00000022 - -#define STM32_HAS_ADC4 FALSE - -#define STM32_HAS_SDADC1 FALSE -#define STM32_HAS_SDADC2 FALSE -#define STM32_HAS_SDADC3 FALSE - -/* CAN attributes.*/ -#define STM32_HAS_CAN1 TRUE -#define STM32_HAS_CAN2 TRUE -#define STM32_CAN_MAX_FILTERS 28 - -/* DAC attributes.*/ -#define STM32_HAS_DAC1_CH1 TRUE -#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_DAC1_CH1_DMA_CHN 0x00700000 - -#define STM32_HAS_DAC1_CH2 TRUE -#define STM32_DAC1_CH2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_DAC1_CH2_DMA_CHN 0x07000000 - -#define STM32_HAS_DAC2_CH1 FALSE -#define STM32_HAS_DAC2_CH2 FALSE - -/* DMA attributes.*/ -#define STM32_ADVANCED_DMA TRUE -#define STM32_DMA_CACHE_HANDLING FALSE - -#define STM32_HAS_DMA1 TRUE -#define STM32_DMA1_CH0_HANDLER Vector6C -#define STM32_DMA1_CH1_HANDLER Vector70 -#define STM32_DMA1_CH2_HANDLER Vector74 -#define STM32_DMA1_CH3_HANDLER Vector78 -#define STM32_DMA1_CH4_HANDLER Vector7C -#define STM32_DMA1_CH5_HANDLER Vector80 -#define STM32_DMA1_CH6_HANDLER Vector84 -#define STM32_DMA1_CH7_HANDLER VectorFC -#define STM32_DMA1_CH0_NUMBER 11 -#define STM32_DMA1_CH1_NUMBER 12 -#define STM32_DMA1_CH2_NUMBER 13 -#define STM32_DMA1_CH3_NUMBER 14 -#define STM32_DMA1_CH4_NUMBER 15 -#define STM32_DMA1_CH5_NUMBER 16 -#define STM32_DMA1_CH6_NUMBER 17 -#define STM32_DMA1_CH7_NUMBER 47 - -#define STM32_HAS_DMA2 TRUE -#define STM32_DMA2_CH0_HANDLER Vector120 -#define STM32_DMA2_CH1_HANDLER Vector124 -#define STM32_DMA2_CH2_HANDLER Vector128 -#define STM32_DMA2_CH3_HANDLER Vector12C -#define STM32_DMA2_CH4_HANDLER Vector130 -#define STM32_DMA2_CH5_HANDLER Vector150 -#define STM32_DMA2_CH6_HANDLER Vector154 -#define STM32_DMA2_CH7_HANDLER Vector158 -#define STM32_DMA2_CH0_NUMBER 56 -#define STM32_DMA2_CH1_NUMBER 57 -#define STM32_DMA2_CH2_NUMBER 58 -#define STM32_DMA2_CH3_NUMBER 59 -#define STM32_DMA2_CH4_NUMBER 60 -#define STM32_DMA2_CH5_NUMBER 68 -#define STM32_DMA2_CH6_NUMBER 69 -#define STM32_DMA2_CH7_NUMBER 70 - -/* ETH attributes.*/ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F205xx) || \ - defined(STM32F215xx) -#define STM32_HAS_ETH FALSE -#else -#define STM32_HAS_ETH TRUE -#define STM32_ETH_HANDLER Vector134 -#define STM32_ETH_NUMBER 61 -#endif - -/* EXTI attributes.*/ -#define STM32_EXTI_NUM_LINES 23 -#define STM32_EXTI_IMR_MASK 0x00000000U - -/* GPIO attributes.*/ -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE TRUE -#define STM32_HAS_GPIOH TRUE -#define STM32_HAS_GPIOF TRUE -#define STM32_HAS_GPIOG TRUE -#define STM32_HAS_GPIOI TRUE -#define STM32_HAS_GPIOJ FALSE -#define STM32_HAS_GPIOK FALSE -#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \ - RCC_AHB1ENR_GPIOBEN | \ - RCC_AHB1ENR_GPIOCEN | \ - RCC_AHB1ENR_GPIODEN | \ - RCC_AHB1ENR_GPIOEEN | \ - RCC_AHB1ENR_GPIOFEN | \ - RCC_AHB1ENR_GPIOGEN | \ - RCC_AHB1ENR_GPIOHEN | \ - RCC_AHB1ENR_GPIOIEN) - -/* I2C attributes.*/ -#define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ - STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_I2C1_RX_DMA_CHN 0x00100001 -#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\ - STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_I2C1_TX_DMA_CHN 0x11000000 - -#define STM32_HAS_I2C2 TRUE -#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ - STM32_DMA_STREAM_ID_MSK(1, 3)) -#define STM32_I2C2_RX_DMA_CHN 0x00007700 -#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7) -#define STM32_I2C2_TX_DMA_CHN 0x70000000 - -#define STM32_HAS_I2C3 TRUE -#define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) -#define STM32_I2C3_RX_DMA_CHN 0x00000300 -#define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) -#define STM32_I2C3_TX_DMA_CHN 0x00030000 - -#define STM32_HAS_I2C4 FALSE - -/* RTC attributes.*/ -#define STM32_HAS_RTC TRUE -#if !defined(STM32F2XX) -#define STM32_RTC_HAS_SUBSECONDS TRUE -#else -#define STM32_RTC_HAS_SUBSECONDS FALSE -#endif -#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE -#define STM32_RTC_NUM_ALARMS 2 -#define STM32_RTC_HAS_INTERRUPTS FALSE - -/* SDIO attributes.*/ -#define STM32_HAS_SDIO TRUE -#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ - STM32_DMA_STREAM_ID_MSK(2, 6)) -#define STM32_SDC_SDIO_DMA_CHN 0x04004000 - -/* SPI attributes.*/ -#define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_SUPPORTS_I2S FALSE -#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ - STM32_DMA_STREAM_ID_MSK(2, 2)) -#define STM32_SPI1_RX_DMA_CHN 0x00000303 -#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ - STM32_DMA_STREAM_ID_MSK(2, 5)) -#define STM32_SPI1_TX_DMA_CHN 0x00303000 - -#define STM32_HAS_SPI2 TRUE -#define STM32_SPI2_SUPPORTS_I2S TRUE -#define STM32_SPI2_I2S_FULLDUPLEX TRUE -#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) -#define STM32_SPI2_RX_DMA_CHN 0x00000000 -#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) -#define STM32_SPI2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI3 TRUE -#define STM32_SPI3_SUPPORTS_I2S TRUE -#define STM32_SPI3_I2S_FULLDUPLEX TRUE -#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ - STM32_DMA_STREAM_ID_MSK(1, 2)) -#define STM32_SPI3_RX_DMA_CHN 0x00000000 -#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\ - STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_SPI3_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI4 FALSE -#define STM32_HAS_SPI5 FALSE -#define STM32_HAS_SPI6 FALSE - -/* TIM attributes.*/ -#define STM32_TIM_MAX_CHANNELS 4 - -#define STM32_HAS_TIM1 TRUE -#define STM32_TIM1_IS_32BITS FALSE -#define STM32_TIM1_CHANNELS 4 - -#define STM32_HAS_TIM2 TRUE -#define STM32_TIM2_IS_32BITS TRUE -#define STM32_TIM2_CHANNELS 4 - -#define STM32_HAS_TIM3 TRUE -#define STM32_TIM3_IS_32BITS FALSE -#define STM32_TIM3_CHANNELS 4 - -#define STM32_HAS_TIM4 TRUE -#define STM32_TIM4_IS_32BITS FALSE -#define STM32_TIM4_CHANNELS 4 - -#define STM32_HAS_TIM5 TRUE -#define STM32_TIM5_IS_32BITS TRUE -#define STM32_TIM5_CHANNELS 4 - -#define STM32_HAS_TIM6 TRUE -#define STM32_TIM6_IS_32BITS FALSE -#define STM32_TIM6_CHANNELS 0 - -#define STM32_HAS_TIM7 TRUE -#define STM32_TIM7_IS_32BITS FALSE -#define STM32_TIM7_CHANNELS 0 - -#define STM32_HAS_TIM8 TRUE -#define STM32_TIM8_IS_32BITS FALSE -#define STM32_TIM8_CHANNELS 6 - -#define STM32_HAS_TIM9 TRUE -#define STM32_TIM9_IS_32BITS FALSE -#define STM32_TIM9_CHANNELS 2 - -#define STM32_HAS_TIM10 TRUE -#define STM32_TIM10_IS_32BITS FALSE -#define STM32_TIM10_CHANNELS 2 - -#define STM32_HAS_TIM11 TRUE -#define STM32_TIM11_IS_32BITS FALSE -#define STM32_TIM11_CHANNELS 2 - -#define STM32_HAS_TIM12 TRUE -#define STM32_TIM12_IS_32BITS FALSE -#define STM32_TIM12_CHANNELS 2 - -#define STM32_HAS_TIM13 TRUE -#define STM32_TIM13_IS_32BITS FALSE -#define STM32_TIM13_CHANNELS 2 - -#define STM32_HAS_TIM14 TRUE -#define STM32_TIM14_IS_32BITS FALSE -#define STM32_TIM14_CHANNELS 2 - -#define STM32_HAS_TIM15 FALSE -#define STM32_HAS_TIM16 FALSE -#define STM32_HAS_TIM17 FALSE -#define STM32_HAS_TIM18 FALSE -#define STM32_HAS_TIM19 FALSE -#define STM32_HAS_TIM20 FALSE -#define STM32_HAS_TIM21 FALSE -#define STM32_HAS_TIM22 FALSE - -/* USART attributes.*/ -#define STM32_HAS_USART1 TRUE -#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\ - STM32_DMA_STREAM_ID_MSK(2, 5)) -#define STM32_USART1_RX_DMA_CHN 0x00400400 -#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7) -#define STM32_USART1_TX_DMA_CHN 0x40000000 - -#define STM32_HAS_USART2 TRUE -#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) -#define STM32_USART2_RX_DMA_CHN 0x00400000 -#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6) -#define STM32_USART2_TX_DMA_CHN 0x04000000 - -#define STM32_HAS_USART3 TRUE -#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1) -#define STM32_USART3_RX_DMA_CHN 0x00000040 -#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\ - STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_USART3_TX_DMA_CHN 0x00074000 - -#define STM32_HAS_UART4 TRUE -#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) -#define STM32_UART4_RX_DMA_CHN 0x00000400 -#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) -#define STM32_UART4_TX_DMA_CHN 0x00040000 - -#define STM32_HAS_UART5 TRUE -#define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0) -#define STM32_UART5_RX_DMA_CHN 0x00000004 -#define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7) -#define STM32_UART5_TX_DMA_CHN 0x40000000 - -#define STM32_HAS_USART6 TRUE -#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\ - STM32_DMA_STREAM_ID_MSK(2, 2)) -#define STM32_USART6_RX_DMA_CHN 0x00000550 -#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\ - STM32_DMA_STREAM_ID_MSK(2, 7)) -#define STM32_USART6_TX_DMA_CHN 0x55000000 - -#define STM32_HAS_UART7 FALSE -#define STM32_HAS_UART8 FALSE -#define STM32_HAS_LPUART1 FALSE - -/* USB attributes.*/ -#define STM32_OTG_STEPPING 1 -#define STM32_HAS_OTG1 TRUE -#define STM32_OTG1_ENDPOINTS 3 -#define STM32_HAS_OTG2 TRUE -#define STM32_OTG2_ENDPOINTS 5 - -#define STM32_HAS_USB FALSE - -/* IWDG attributes.*/ -#define STM32_HAS_IWDG TRUE -#define STM32_IWDG_IS_WINDOWED FALSE - -/* LTDC attributes.*/ -#define STM32_HAS_LTDC FALSE - -/* DMA2D attributes.*/ -#define STM32_HAS_DMA2D FALSE - -/* FSMC attributes.*/ -#define STM32_HAS_FSMC TRUE -#define STM32_FSMC_IS_FMC FALSE - -/* CRC attributes.*/ -#define STM32_HAS_CRC TRUE -#define STM32_CRC_PROGRAMMABLE FALSE - -#endif /* defined(STM32F40_41xxx) || defined(STM32F2XX) */ - -/*===========================================================================*/ -/* STM32F401xx. */ -/*===========================================================================*/ -#if defined(STM32F401xx) -/* ADC attributes.*/ -#define STM32_ADC_HANDLER Vector88 -#define STM32_ADC_NUMBER 18 - -#define STM32_HAS_ADC1 TRUE -#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ - STM32_DMA_STREAM_ID_MSK(2, 4)) -#define STM32_ADC1_DMA_CHN 0x00000000 - -#define STM32_HAS_ADC2 TRUE -#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\ - STM32_DMA_STREAM_ID_MSK(2, 3)) -#define STM32_ADC2_DMA_CHN 0x00001100 - -#define STM32_HAS_ADC3 TRUE -#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ - STM32_DMA_STREAM_ID_MSK(2, 1)) -#define STM32_ADC3_DMA_CHN 0x00000022 - -#define STM32_HAS_ADC4 FALSE - -#define STM32_HAS_SDADC1 FALSE -#define STM32_HAS_SDADC2 FALSE -#define STM32_HAS_SDADC3 FALSE - -/* CAN attributes.*/ -#define STM32_HAS_CAN1 TRUE -#define STM32_HAS_CAN2 TRUE -#define STM32_CAN_MAX_FILTERS 28 - -/* DAC attributes.*/ -#define STM32_HAS_DAC1_CH1 FALSE -#define STM32_HAS_DAC1_CH2 FALSE -#define STM32_HAS_DAC2_CH1 FALSE -#define STM32_HAS_DAC2_CH2 FALSE - -/* DMA attributes.*/ -#define STM32_ADVANCED_DMA TRUE -#define STM32_DMA_CACHE_HANDLING FALSE - -#define STM32_HAS_DMA1 TRUE -#define STM32_DMA1_CH0_HANDLER Vector6C -#define STM32_DMA1_CH1_HANDLER Vector70 -#define STM32_DMA1_CH2_HANDLER Vector74 -#define STM32_DMA1_CH3_HANDLER Vector78 -#define STM32_DMA1_CH4_HANDLER Vector7C -#define STM32_DMA1_CH5_HANDLER Vector80 -#define STM32_DMA1_CH6_HANDLER Vector84 -#define STM32_DMA1_CH7_HANDLER VectorFC -#define STM32_DMA1_CH0_NUMBER 11 -#define STM32_DMA1_CH1_NUMBER 12 -#define STM32_DMA1_CH2_NUMBER 13 -#define STM32_DMA1_CH3_NUMBER 14 -#define STM32_DMA1_CH4_NUMBER 15 -#define STM32_DMA1_CH5_NUMBER 16 -#define STM32_DMA1_CH6_NUMBER 17 -#define STM32_DMA1_CH7_NUMBER 47 - -#define STM32_HAS_DMA2 TRUE -#define STM32_DMA2_CH0_HANDLER Vector120 -#define STM32_DMA2_CH1_HANDLER Vector124 -#define STM32_DMA2_CH2_HANDLER Vector128 -#define STM32_DMA2_CH3_HANDLER Vector12C -#define STM32_DMA2_CH4_HANDLER Vector130 -#define STM32_DMA2_CH5_HANDLER Vector150 -#define STM32_DMA2_CH6_HANDLER Vector154 -#define STM32_DMA2_CH7_HANDLER Vector158 -#define STM32_DMA2_CH0_NUMBER 56 -#define STM32_DMA2_CH1_NUMBER 57 -#define STM32_DMA2_CH2_NUMBER 58 -#define STM32_DMA2_CH3_NUMBER 59 -#define STM32_DMA2_CH4_NUMBER 60 -#define STM32_DMA2_CH5_NUMBER 68 -#define STM32_DMA2_CH6_NUMBER 69 -#define STM32_DMA2_CH7_NUMBER 70 - -/* ETH attributes.*/ -#define STM32_HAS_ETH FALSE - -/* EXTI attributes.*/ -#define STM32_EXTI_NUM_LINES 23 -#define STM32_EXTI_IMR_MASK 0x00000000U - -/* GPIO attributes.*/ -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE TRUE -#define STM32_HAS_GPIOH TRUE -#define STM32_HAS_GPIOF FALSE -#define STM32_HAS_GPIOG FALSE -#define STM32_HAS_GPIOI FALSE -#define STM32_HAS_GPIOJ FALSE -#define STM32_HAS_GPIOK FALSE -#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \ - RCC_AHB1ENR_GPIOBEN | \ - RCC_AHB1ENR_GPIOCEN | \ - RCC_AHB1ENR_GPIODEN | \ - RCC_AHB1ENR_GPIOEEN) - -/* I2C attributes.*/ -#define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ - STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_I2C1_RX_DMA_CHN 0x00100001 -#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\ - STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_I2C1_TX_DMA_CHN 0x11000000 - -#define STM32_HAS_I2C2 TRUE -#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ - STM32_DMA_STREAM_ID_MSK(1, 3)) -#define STM32_I2C2_RX_DMA_CHN 0x00007700 -#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7) -#define STM32_I2C2_TX_DMA_CHN 0x70000000 - -#define STM32_HAS_I2C3 TRUE -#define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) -#define STM32_I2C3_RX_DMA_CHN 0x00000300 -#define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) -#define STM32_I2C3_TX_DMA_CHN 0x00030000 - -#define STM32_HAS_I2C4 FALSE - -/* RTC attributes.*/ -#define STM32_HAS_RTC TRUE -#define STM32_RTC_HAS_SUBSECONDS TRUE -#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE -#define STM32_RTC_NUM_ALARMS 2 -#define STM32_RTC_HAS_INTERRUPTS FALSE - -/* SDIO attributes.*/ -#define STM32_HAS_SDIO TRUE -#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ - STM32_DMA_STREAM_ID_MSK(2, 6)) -#define STM32_SDC_SDIO_DMA_CHN 0x04004000 - -/* SPI attributes.*/ -#define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_SUPPORTS_I2S FALSE -#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ - STM32_DMA_STREAM_ID_MSK(2, 2)) -#define STM32_SPI1_RX_DMA_CHN 0x00000303 -#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ - STM32_DMA_STREAM_ID_MSK(2, 5)) -#define STM32_SPI1_TX_DMA_CHN 0x00303000 - -#define STM32_HAS_SPI2 TRUE -#define STM32_SPI2_SUPPORTS_I2S TRUE -#define STM32_SPI2_I2S_FULLDUPLEX TRUE -#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) -#define STM32_SPI2_RX_DMA_CHN 0x00000000 -#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) -#define STM32_SPI2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI3 TRUE -#define STM32_SPI3_SUPPORTS_I2S TRUE -#define STM32_SPI3_I2S_FULLDUPLEX TRUE -#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ - STM32_DMA_STREAM_ID_MSK(1, 2)) -#define STM32_SPI3_RX_DMA_CHN 0x00000000 -#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\ - STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_SPI3_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI4 TRUE -#define STM32_SPI4_SUPPORTS_I2S FALSE -#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ - STM32_DMA_STREAM_ID_MSK(2, 3)) -#define STM32_SPI4_RX_DMA_CHN 0x00005004 -#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\ - STM32_DMA_STREAM_ID_MSK(2, 4)) -#define STM32_SPI4_TX_DMA_CHN 0x00050040 - -#define STM32_HAS_SPI5 FALSE -#define STM32_HAS_SPI6 FALSE - -/* TIM attributes.*/ -#define STM32_TIM_MAX_CHANNELS 4 - -#define STM32_HAS_TIM1 TRUE -#define STM32_TIM1_IS_32BITS FALSE -#define STM32_TIM1_CHANNELS 4 - -#define STM32_HAS_TIM2 TRUE -#define STM32_TIM2_IS_32BITS TRUE -#define STM32_TIM2_CHANNELS 4 - -#define STM32_HAS_TIM3 TRUE -#define STM32_TIM3_IS_32BITS FALSE -#define STM32_TIM3_CHANNELS 4 - -#define STM32_HAS_TIM4 TRUE -#define STM32_TIM4_IS_32BITS FALSE -#define STM32_TIM4_CHANNELS 4 - -#define STM32_HAS_TIM5 TRUE -#define STM32_TIM5_IS_32BITS TRUE -#define STM32_TIM5_CHANNELS 4 - -#define STM32_HAS_TIM9 TRUE -#define STM32_TIM9_IS_32BITS FALSE -#define STM32_TIM9_CHANNELS 2 - -#define STM32_HAS_TIM10 TRUE -#define STM32_TIM10_IS_32BITS FALSE -#define STM32_TIM10_CHANNELS 2 - -#define STM32_HAS_TIM11 TRUE -#define STM32_TIM11_IS_32BITS FALSE -#define STM32_TIM11_CHANNELS 2 - -#define STM32_HAS_TIM6 FALSE -#define STM32_HAS_TIM7 FALSE -#define STM32_HAS_TIM8 FALSE -#define STM32_HAS_TIM12 FALSE -#define STM32_HAS_TIM13 FALSE -#define STM32_HAS_TIM14 FALSE -#define STM32_HAS_TIM15 FALSE -#define STM32_HAS_TIM16 FALSE -#define STM32_HAS_TIM17 FALSE -#define STM32_HAS_TIM18 FALSE -#define STM32_HAS_TIM19 FALSE -#define STM32_HAS_TIM20 FALSE -#define STM32_HAS_TIM21 FALSE -#define STM32_HAS_TIM22 FALSE - -/* USART attributes.*/ -#define STM32_HAS_USART1 TRUE -#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\ - STM32_DMA_STREAM_ID_MSK(2, 5)) -#define STM32_USART1_RX_DMA_CHN 0x00400400 -#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7) -#define STM32_USART1_TX_DMA_CHN 0x40000000 - -#define STM32_HAS_USART2 TRUE -#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) -#define STM32_USART2_RX_DMA_CHN 0x00400000 -#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6) -#define STM32_USART2_TX_DMA_CHN 0x04000000 - -#define STM32_HAS_USART3 FALSE -#define STM32_HAS_UART4 FALSE -#define STM32_HAS_UART5 FALSE - -#define STM32_HAS_USART6 TRUE -#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\ - STM32_DMA_STREAM_ID_MSK(2, 2)) -#define STM32_USART6_RX_DMA_CHN 0x00000550 -#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\ - STM32_DMA_STREAM_ID_MSK(2, 7)) -#define STM32_USART6_TX_DMA_CHN 0x55000000 - -#define STM32_HAS_UART7 FALSE -#define STM32_HAS_UART8 FALSE -#define STM32_HAS_LPUART1 FALSE - -/* USB attributes.*/ -#define STM32_OTG_STEPPING 1 -#define STM32_HAS_OTG1 TRUE -#define STM32_OTG1_ENDPOINTS 4 -#define STM32_HAS_OTG2 FALSE - -#define STM32_HAS_USB FALSE - -/* IWDG attributes.*/ -#define STM32_HAS_IWDG TRUE -#define STM32_IWDG_IS_WINDOWED FALSE - -/* LTDC attributes.*/ -#define STM32_HAS_LTDC FALSE - -/* DMA2D attributes.*/ -#define STM32_HAS_DMA2D FALSE - -/* FSMC attributes.*/ -#define STM32_HAS_FSMC FALSE - -/* CRC attributes.*/ -#define STM32_HAS_CRC TRUE -#define STM32_CRC_PROGRAMMABLE FALSE - -#endif /* defined(STM32F401xx) */ - -/*===========================================================================*/ -/* STM32F411xE. */ -/*===========================================================================*/ -#if defined(STM32F411xx) -/* ADC attributes.*/ -#define STM32_ADC_HANDLER Vector88 -#define STM32_ADC_NUMBER 18 - -#define STM32_HAS_ADC1 TRUE -#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ - STM32_DMA_STREAM_ID_MSK(2, 4)) -#define STM32_ADC1_DMA_CHN 0x00000000 - -#define STM32_HAS_ADC2 FALSE -#define STM32_HAS_ADC3 FALSE -#define STM32_HAS_ADC4 FALSE - -#define STM32_HAS_SDADC1 FALSE -#define STM32_HAS_SDADC2 FALSE -#define STM32_HAS_SDADC3 FALSE - -/* CAN attributes.*/ -#define STM32_HAS_CAN1 FALSE -#define STM32_HAS_CAN2 FALSE - -/* DAC attributes.*/ -#define STM32_HAS_DAC1_CH1 FALSE -#define STM32_HAS_DAC1_CH2 FALSE -#define STM32_HAS_DAC2_CH1 FALSE -#define STM32_HAS_DAC2_CH2 FALSE - -/* DMA attributes.*/ -#define STM32_ADVANCED_DMA TRUE -#define STM32_DMA_CACHE_HANDLING FALSE - -#define STM32_HAS_DMA1 TRUE -#define STM32_DMA1_CH0_HANDLER Vector6C -#define STM32_DMA1_CH1_HANDLER Vector70 -#define STM32_DMA1_CH2_HANDLER Vector74 -#define STM32_DMA1_CH3_HANDLER Vector78 -#define STM32_DMA1_CH4_HANDLER Vector7C -#define STM32_DMA1_CH5_HANDLER Vector80 -#define STM32_DMA1_CH6_HANDLER Vector84 -#define STM32_DMA1_CH7_HANDLER VectorFC -#define STM32_DMA1_CH0_NUMBER 11 -#define STM32_DMA1_CH1_NUMBER 12 -#define STM32_DMA1_CH2_NUMBER 13 -#define STM32_DMA1_CH3_NUMBER 14 -#define STM32_DMA1_CH4_NUMBER 15 -#define STM32_DMA1_CH5_NUMBER 16 -#define STM32_DMA1_CH6_NUMBER 17 -#define STM32_DMA1_CH7_NUMBER 47 - -#define STM32_HAS_DMA2 TRUE -#define STM32_DMA2_CH0_HANDLER Vector120 -#define STM32_DMA2_CH1_HANDLER Vector124 -#define STM32_DMA2_CH2_HANDLER Vector128 -#define STM32_DMA2_CH3_HANDLER Vector12C -#define STM32_DMA2_CH4_HANDLER Vector130 -#define STM32_DMA2_CH5_HANDLER Vector150 -#define STM32_DMA2_CH6_HANDLER Vector154 -#define STM32_DMA2_CH7_HANDLER Vector158 -#define STM32_DMA2_CH0_NUMBER 56 -#define STM32_DMA2_CH1_NUMBER 57 -#define STM32_DMA2_CH2_NUMBER 58 -#define STM32_DMA2_CH3_NUMBER 59 -#define STM32_DMA2_CH4_NUMBER 60 -#define STM32_DMA2_CH5_NUMBER 68 -#define STM32_DMA2_CH6_NUMBER 69 -#define STM32_DMA2_CH7_NUMBER 70 - -/* ETH attributes.*/ -#define STM32_HAS_ETH FALSE - -/* EXTI attributes.*/ -#define STM32_EXTI_NUM_LINES 23 -#define STM32_EXTI_IMR_MASK 0x00000000U - -/* GPIO attributes.*/ -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE TRUE -#define STM32_HAS_GPIOH TRUE -#define STM32_HAS_GPIOF FALSE -#define STM32_HAS_GPIOG FALSE -#define STM32_HAS_GPIOI FALSE -#define STM32_HAS_GPIOJ FALSE -#define STM32_HAS_GPIOK FALSE -#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \ - RCC_AHB1ENR_GPIOBEN | \ - RCC_AHB1ENR_GPIOCEN | \ - RCC_AHB1ENR_GPIODEN | \ - RCC_AHB1ENR_GPIOEEN | \ - RCC_AHB1ENR_GPIOHEN) - -/* I2C attributes.*/ -#define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ - STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_I2C1_RX_DMA_CHN 0x00100001 -#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\ - STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_I2C1_TX_DMA_CHN 0x11000000 - -#define STM32_HAS_I2C2 TRUE -#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ - STM32_DMA_STREAM_ID_MSK(1, 3)) -#define STM32_I2C2_RX_DMA_CHN 0x00007700 -#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7) -#define STM32_I2C2_TX_DMA_CHN 0x70000000 - -#define STM32_HAS_I2C3 TRUE -#define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) -#define STM32_I2C3_RX_DMA_CHN 0x00000300 -#define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) -#define STM32_I2C3_TX_DMA_CHN 0x00030000 - -#define STM32_HAS_I2C4 FALSE - -/* RTC attributes.*/ -#define STM32_HAS_RTC TRUE -#define STM32_RTC_HAS_SUBSECONDS TRUE -#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE -#define STM32_RTC_NUM_ALARMS 2 -#define STM32_RTC_HAS_INTERRUPTS FALSE - -/* SDIO attributes.*/ -#define STM32_HAS_SDIO TRUE -#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ - STM32_DMA_STREAM_ID_MSK(2, 6)) -#define STM32_SDC_SDIO_DMA_CHN 0x04004000 - -/* SPI attributes.*/ -#define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_SUPPORTS_I2S FALSE -#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ - STM32_DMA_STREAM_ID_MSK(2, 2)) -#define STM32_SPI1_RX_DMA_CHN 0x00000303 -#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ - STM32_DMA_STREAM_ID_MSK(2, 5)) -#define STM32_SPI1_TX_DMA_CHN 0x00303000 - -#define STM32_HAS_SPI2 TRUE -#define STM32_SPI2_SUPPORTS_I2S TRUE -#define STM32_SPI2_I2S_FULLDUPLEX TRUE -#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) -#define STM32_SPI2_RX_DMA_CHN 0x00000000 -#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) -#define STM32_SPI2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI3 TRUE -#define STM32_SPI3_SUPPORTS_I2S TRUE -#define STM32_SPI3_I2S_FULLDUPLEX TRUE -#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ - STM32_DMA_STREAM_ID_MSK(1, 2)) -#define STM32_SPI3_RX_DMA_CHN 0x00000000 -#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\ - STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_SPI3_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI4 TRUE -#define STM32_SPI4_SUPPORTS_I2S FALSE -#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ - STM32_DMA_STREAM_ID_MSK(2, 3)) -#define STM32_SPI4_RX_DMA_CHN 0x00005004 -#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\ - STM32_DMA_STREAM_ID_MSK(2, 4)) -#define STM32_SPI4_TX_DMA_CHN 0x00050040 - -#define STM32_HAS_SPI5 TRUE -#define STM32_SPI5_SUPPORTS_I2S FALSE -#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ - STM32_DMA_STREAM_ID_MSK(2, 5)) -#define STM32_SPI5_RX_DMA_CHN 0x00702000 -#define STM32_SPI5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) |\ - STM32_DMA_STREAM_ID_MSK(2, 6)) -#define STM32_SPI5_TX_DMA_CHN 0x07020000 - -#define STM32_HAS_SPI6 FALSE - -/* TIM attributes.*/ -#define STM32_TIM_MAX_CHANNELS 4 - -#define STM32_HAS_TIM1 TRUE -#define STM32_TIM1_IS_32BITS FALSE -#define STM32_TIM1_CHANNELS 4 - -#define STM32_HAS_TIM2 TRUE -#define STM32_TIM2_IS_32BITS TRUE -#define STM32_TIM2_CHANNELS 4 - -#define STM32_HAS_TIM3 TRUE -#define STM32_TIM3_IS_32BITS FALSE -#define STM32_TIM3_CHANNELS 4 - -#define STM32_HAS_TIM4 TRUE -#define STM32_TIM4_IS_32BITS FALSE -#define STM32_TIM4_CHANNELS 4 - -#define STM32_HAS_TIM5 TRUE -#define STM32_TIM5_IS_32BITS TRUE -#define STM32_TIM5_CHANNELS 4 - -#define STM32_HAS_TIM9 TRUE -#define STM32_TIM9_IS_32BITS FALSE -#define STM32_TIM9_CHANNELS 2 - -#define STM32_HAS_TIM10 TRUE -#define STM32_TIM10_IS_32BITS FALSE -#define STM32_TIM10_CHANNELS 2 - -#define STM32_HAS_TIM11 TRUE -#define STM32_TIM11_IS_32BITS FALSE -#define STM32_TIM11_CHANNELS 2 - -#define STM32_HAS_TIM6 FALSE -#define STM32_HAS_TIM7 FALSE -#define STM32_HAS_TIM8 FALSE -#define STM32_HAS_TIM12 FALSE -#define STM32_HAS_TIM13 FALSE -#define STM32_HAS_TIM14 FALSE -#define STM32_HAS_TIM15 FALSE -#define STM32_HAS_TIM16 FALSE -#define STM32_HAS_TIM17 FALSE -#define STM32_HAS_TIM18 FALSE -#define STM32_HAS_TIM19 FALSE -#define STM32_HAS_TIM20 FALSE -#define STM32_HAS_TIM21 FALSE -#define STM32_HAS_TIM22 FALSE - -/* USART attributes.*/ -#define STM32_HAS_USART1 TRUE -#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\ - STM32_DMA_STREAM_ID_MSK(2, 5)) -#define STM32_USART1_RX_DMA_CHN 0x00400400 -#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7) -#define STM32_USART1_TX_DMA_CHN 0x40000000 - -#define STM32_HAS_USART2 TRUE -#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) -#define STM32_USART2_RX_DMA_CHN 0x00400000 -#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6) -#define STM32_USART2_TX_DMA_CHN 0x04000000 - -#define STM32_HAS_USART3 FALSE -#define STM32_HAS_UART4 FALSE -#define STM32_HAS_UART5 FALSE - -#define STM32_HAS_USART6 TRUE -#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\ - STM32_DMA_STREAM_ID_MSK(2, 2)) -#define STM32_USART6_RX_DMA_CHN 0x00000550 -#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\ - STM32_DMA_STREAM_ID_MSK(2, 7)) -#define STM32_USART6_TX_DMA_CHN 0x55000000 - -#define STM32_HAS_UART7 FALSE -#define STM32_HAS_UART8 FALSE -#define STM32_HAS_LPUART1 FALSE - -/* USB attributes.*/ -#define STM32_OTG_STEPPING 1 -#define STM32_HAS_OTG1 TRUE -#define STM32_OTG1_ENDPOINTS 4 - -#define STM32_HAS_OTG2 FALSE -#define STM32_HAS_USB FALSE - -/* IWDG attributes.*/ -#define STM32_HAS_IWDG TRUE -#define STM32_IWDG_IS_WINDOWED FALSE - -/* LTDC attributes.*/ -#define STM32_HAS_LTDC FALSE - -/* DMA2D attributes.*/ -#define STM32_HAS_DMA2D FALSE - -/* FSMC attributes.*/ -#define STM32_HAS_FSMC FALSE - -/* CRC attributes.*/ -#define STM32_HAS_CRC TRUE -#define STM32_CRC_PROGRAMMABLE FALSE - -#endif /* defined(STM32F411xx) */ -/** @} */ - -#endif /* _STM32_REGISTRY_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/common/ARMCMx/mpu.h b/firmware/ChibiOS_16/os/hal/ports/common/ARMCMx/mpu.h deleted file mode 100644 index c461eb70bd..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/common/ARMCMx/mpu.h +++ /dev/null @@ -1,208 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file common/ARMCMx/mpu.h - * @brief Cortex-Mx MPU support macros and structures. - * - * @addtogroup COMMON_ARMCMx_MPU - * @{ - */ - -#ifndef _MPU_H_ -#define _MPU_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name MPU registers definitions - * @{ - */ -#define MPU_TYPE_SEPARATED (1U << 0U) -#define MPU_TYPE_DREGION(n) (((n) >> 8U) & 255U) -#define MPU_TYPE_IREGION(n) (((n) >> 16U) & 255U) - -#define MPU_CTRL_ENABLE (1U << 0U) -#define MPU_CTRL_HFNMIENA (1U << 1U) -#define MPU_CTRL_PRIVDEFENA (1U << 2U) - -#define MPU_RNR_REGION_MASK (255U << 0U) -#define MPU_RNR_REGION(n) ((n) << 0U) - -#define MPU_RBAR_REGION_MASK (15U << 0U) -#define MPU_RBAR_REGION(n) ((n) << 0U) -#define MPU_RBAR_VALID (1U << 4U) -#define MPU_RBAR_ADDR_MASK 0xFFFFFFE0U -#define MPU_RBAR_ADDR(n) ((n) << 5U) - -#define MPU_RASR_ENABLE (1U << 0U) -#define MPU_RASR_SIZE_MASK (31U << 1U) -#define MPU_RASR_SIZE(n) ((n) << 1U) -#define MPU_RASR_SIZE_32 MPU_RASR_SIZE(4U) -#define MPU_RASR_SIZE_64 MPU_RASR_SIZE(5U) -#define MPU_RASR_SIZE_128 MPU_RASR_SIZE(6U) -#define MPU_RASR_SIZE_256 MPU_RASR_SIZE(7U) -#define MPU_RASR_SIZE_512 MPU_RASR_SIZE(8U) -#define MPU_RASR_SIZE_1K MPU_RASR_SIZE(9U) -#define MPU_RASR_SIZE_2K MPU_RASR_SIZE(10U) -#define MPU_RASR_SIZE_4K MPU_RASR_SIZE(11U) -#define MPU_RASR_SIZE_8K MPU_RASR_SIZE(12U) -#define MPU_RASR_SIZE_16K MPU_RASR_SIZE(13U) -#define MPU_RASR_SIZE_32K MPU_RASR_SIZE(14U) -#define MPU_RASR_SIZE_64K MPU_RASR_SIZE(15U) -#define MPU_RASR_SIZE_128K MPU_RASR_SIZE(16U) -#define MPU_RASR_SIZE_256K MPU_RASR_SIZE(17U) -#define MPU_RASR_SIZE_512K MPU_RASR_SIZE(18U) -#define MPU_RASR_SIZE_1M MPU_RASR_SIZE(19U) -#define MPU_RASR_SIZE_2M MPU_RASR_SIZE(20U) -#define MPU_RASR_SIZE_4M MPU_RASR_SIZE(21U) -#define MPU_RASR_SIZE_8M MPU_RASR_SIZE(22U) -#define MPU_RASR_SIZE_16M MPU_RASR_SIZE(23U) -#define MPU_RASR_SIZE_32M MPU_RASR_SIZE(24U) -#define MPU_RASR_SIZE_64M MPU_RASR_SIZE(25U) -#define MPU_RASR_SIZE_128M MPU_RASR_SIZE(26U) -#define MPU_RASR_SIZE_256M MPU_RASR_SIZE(27U) -#define MPU_RASR_SIZE_512M MPU_RASR_SIZE(28U) -#define MPU_RASR_SIZE_1G MPU_RASR_SIZE(29U) -#define MPU_RASR_SIZE_2G MPU_RASR_SIZE(30U) -#define MPU_RASR_SIZE_4G MPU_RASR_SIZE(31U) -#define MPU_RASR_SRD_MASK (255U << 8U) -#define MPU_RASR_SRD(n) ((n) << 8U) -#define MPU_RASR_SRD_ALL (0U << 8U) -#define MPU_RASR_SRD_DISABLE_SUB0 (1U << 8U) -#define MPU_RASR_SRD_DISABLE_SUB1 (2U << 8U) -#define MPU_RASR_SRD_DISABLE_SUB2 (4U << 8U) -#define MPU_RASR_SRD_DISABLE_SUB3 (8U << 8U) -#define MPU_RASR_SRD_DISABLE_SUB4 (16U << 8U) -#define MPU_RASR_SRD_DISABLE_SUB5 (32U << 8U) -#define MPU_RASR_SRD_DISABLE_SUB6 (64U << 8U) -#define MPU_RASR_SRD_DISABLE_SUB7 (128U << 8U) -#define MPU_RASR_ATTR_B (1U << 16U) -#define MPU_RASR_ATTR_C (1U << 17U) -#define MPU_RASR_ATTR_S (1U << 18U) -#define MPU_RASR_ATTR_TEX_MASK (7U << 19U) -#define MPU_RASR_ATTR_TEX(n) ((n) << 19U) -#define MPU_RASR_ATTR_AP_MASK (7U << 24U) -#define MPU_RASR_ATTR_AP(n) ((n) << 24U) -#define MPU_RASR_ATTR_AP_NA_NA (0U << 24U) -#define MPU_RASR_ATTR_AP_RW_NA (1U << 24U) -#define MPU_RASR_ATTR_AP_RW_RO (2U << 24U) -#define MPU_RASR_ATTR_AP_RW_RW (3U << 24U) -#define MPU_RASR_ATTR_AP_RO_NA (5U << 24U) -#define MPU_RASR_ATTR_AP_RO_RO (6U << 24U) -#define MPU_RASR_ATTR_XN (1U << 28U) -/** @} */ - -/** - * @name Region attributes - * @{ - */ -#define MPU_RASR_ATTR_STRONGLY_ORDERED (MPU_RASR_ATTR_TEX(0)) -#define MPU_RASR_ATTR_SHARED_DEVICE (MPU_RASR_ATTR_TEX(0) | MPU_RASR_ATTR_B) -#define MPU_RASR_ATTR_CACHEABLE_WT_NWA (MPU_RASR_ATTR_TEX(0) | MPU_RASR_ATTR_C) -#define MPU_RASR_ATTR_CACHEABLE_WB_NWA (MPU_RASR_ATTR_TEX(0) | MPU_RASR_ATTR_B | MPU_RASR_ATTR_C) -#define MPU_RASR_ATTR_NON_CACHEABLE (MPU_RASR_ATTR_TEX(1)) -#define MPU_RASR_ATTR_CACHEABLE_WB_WA (MPU_RASR_ATTR_TEX(1) | MPU_RASR_ATTR_B | MPU_RASR_ATTR_C) -#define MPU_RASR_ATTR_NON_SHARED_DEVICE (MPU_RASR_ATTR_TEX(2)) -/** @} */ - -/** - * @name Region identifiers - * @{ - */ -#define MPU_REGION_0 0U -#define MPU_REGION_1 1U -#define MPU_REGION_2 2U -#define MPU_REGION_3 3U -#define MPU_REGION_4 4U -#define MPU_REGION_5 5U -#define MPU_REGION_6 6U -#define MPU_REGION_7 7U -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Enables the MPU. - * @note MEMFAULENA is enabled in SCB_SHCSR. - * - * @param[in] ctrl MPU control modes as defined in @p MPU_CTRL register, - * the enable bit is enforced - * - * @api - */ -#define mpuEnable(ctrl) { \ - MPU->CTRL = ((uint32_t)ctrl) | MPU_CTRL_ENABLE; \ - SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; \ -} - -/** - * @brief Disables the MPU. - * @note MEMFAULENA is disabled in SCB_SHCSR. - * - * @api - */ -#define mpuDisable() { \ - SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; \ - MPU->CTRL = 0; \ -} - -/** - * @brief Configures an MPU region. - * - * @param[in] region the region number - * @param[in] address start address of the region, note, there are alignment - * constraints - * @param[in] attribs attributes mask as defined in @p MPU_RASR register - * - * @api - */ -#define mpuConfigureRegion(region, addr, attribs) { \ - MPU->RNR = ((uint32_t)region); \ - MPU->RBAR = ((uint32_t)addr); \ - MPU->RASR = ((uint32_t)attribs); \ -} - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif -#ifdef __cplusplus -} -#endif - -#endif /* _MPU_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/common/ARMCMx/nvic.c b/firmware/ChibiOS_16/os/hal/ports/common/ARMCMx/nvic.c deleted file mode 100644 index 587b85399e..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/common/ARMCMx/nvic.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file common/ARMCMx/nvic.c - * @brief Cortex-Mx NVIC support code. - * - * @addtogroup COMMON_ARMCMx_NVIC - * @{ - */ - -#include "hal.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Sets the priority of an interrupt handler and enables it. - * - * @param[in] n the interrupt number - * @param[in] prio the interrupt priority - */ -void nvicEnableVector(uint32_t n, uint32_t prio) { - -#if defined(__CORE_CM0_H_GENERIC) - NVIC->IP[_IP_IDX(n)] = (NVIC->IP[_IP_IDX(n)] & ~(0xFFU << _BIT_SHIFT(n))) | - (NVIC_PRIORITY_MASK(prio) << _BIT_SHIFT(n)); -#else - NVIC->IP[n] = NVIC_PRIORITY_MASK(prio); -#endif - NVIC->ICPR[n >> 5U] = 1U << (n & 0x1FU); - NVIC->ISER[n >> 5U] = 1U << (n & 0x1FU); -} - -/** - * @brief Disables an interrupt handler. - * - * @param[in] n the interrupt number - */ -void nvicDisableVector(uint32_t n) { - - NVIC->ICER[n >> 5U] = 1U << (n & 0x1FU); -#if defined(__CORE_CM0_H_GENERIC) - NVIC->IP[_IP_IDX(n)] = NVIC->IP[_IP_IDX(n)] & ~(0xFFU << _BIT_SHIFT(n)); -#else - NVIC->IP[n] = 0U; -#endif -} - -/** - * @brief Changes the priority of a system handler. - * - * @param[in] handler the system handler number - * @param[in] prio the system handler priority - */ -void nvicSetSystemHandlerPriority(uint32_t handler, uint32_t prio) { - - osalDbgCheck(handler < 12U); - -#if defined(__CORE_CM0_H_GENERIC) - SCB->SHP[_SHP_IDX(handler)] = (SCB->SHP[_SHP_IDX(handler)] & ~(0xFFU << _BIT_SHIFT(handler))) | - (NVIC_PRIORITY_MASK(prio) << _BIT_SHIFT(handler)); -#elif defined(__CORE_CM7_H_GENERIC) - SCB->SHPR[handler] = NVIC_PRIORITY_MASK(prio); -#else - SCB->SHP[handler] = NVIC_PRIORITY_MASK(prio); -#endif -} - -/** - * @brief Clears a pending interrupt source. - * - * @param[in] n the interrupt number - */ -void nvicClearPending(uint32_t n) { - - NVIC->ICPR[n >> 5] = 1 << (n & 0x1F); -} - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/common/ARMCMx/nvic.h b/firmware/ChibiOS_16/os/hal/ports/common/ARMCMx/nvic.h deleted file mode 100644 index 56310c452a..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/common/ARMCMx/nvic.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file common/ARMCMx/nvic.h - * @brief Cortex-Mx NVIC support macros and structures. - * - * @addtogroup COMMON_ARMCMx_NVIC - * @{ - */ - -#ifndef _NVIC_H_ -#define _NVIC_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name System vectors numbers - * @{ - */ -#define HANDLER_MEM_MANAGE 0 /**< MEM MANAGE vector id. */ -#define HANDLER_BUS_FAULT 1 /**< BUS FAULT vector id. */ -#define HANDLER_USAGE_FAULT 2 /**< USAGE FAULT vector id. */ -#define HANDLER_RESERVED_3 3 -#define HANDLER_RESERVED_4 4 -#define HANDLER_RESERVED_5 5 -#define HANDLER_RESERVED_6 6 -#define HANDLER_SVCALL 7 /**< SVCALL vector id. */ -#define HANDLER_DEBUG_MONITOR 8 /**< DEBUG MONITOR vector id. */ -#define HANDLER_RESERVED_9 9 -#define HANDLER_PENDSV 10 /**< PENDSV vector id. */ -#define HANDLER_SYSTICK 11 /**< SYS TCK vector id. */ -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Priority level to priority mask conversion macro. - */ -#define NVIC_PRIORITY_MASK(prio) ((prio) << (8U - (unsigned)__NVIC_PRIO_BITS)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void nvicEnableVector(uint32_t n, uint32_t prio); - void nvicDisableVector(uint32_t n); - void nvicSetSystemHandlerPriority(uint32_t handler, uint32_t prio); - void nvicClearPending(uint32_t n); -#ifdef __cplusplus -} -#endif - -#endif /* _NVIC_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/simulator/console.c b/firmware/ChibiOS_16/os/hal/ports/simulator/console.c deleted file mode 100644 index d20fc249bc..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/simulator/console.c +++ /dev/null @@ -1,134 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file console.c - * @brief Simulator console driver code. - * @{ - */ - -#include - -#include "ch.h" -#include "hal.h" -#include "console.h" - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief Console driver 1. - */ -BaseChannel CD1; - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static size_t write(void *ip, const uint8_t *bp, size_t n) { - size_t ret; - - (void)ip; - - ret = fwrite(bp, 1, n, stdout); - fflush(stdout); - return ret; -} - -static size_t read(void *ip, uint8_t *bp, size_t n) { - - (void)ip; - - return fread(bp, 1, n, stdin); -} - -static msg_t put(void *ip, uint8_t b) { - - (void)ip; - - fputc(b, stdout); - fflush(stdout); - return MSG_OK; -} - -static msg_t get(void *ip) { - - (void)ip; - - return fgetc(stdin); -} - -static msg_t putt(void *ip, uint8_t b, systime_t time) { - - (void)ip; - (void)time; - - fputc(b, stdout); - fflush(stdout); - return MSG_OK; -} - -static msg_t gett(void *ip, systime_t time) { - - (void)ip; - (void)time; - - return fgetc(stdin); -} - -static size_t writet(void *ip, const uint8_t *bp, size_t n, systime_t time) { - size_t ret; - - (void)ip; - (void)time; - - ret = fwrite(bp, 1, n, stdout); - fflush(stdout); - return ret; -} - -static size_t readt(void *ip, uint8_t *bp, size_t n, systime_t time) { - - (void)ip; - (void)time; - - return fread(bp, 1, n, stdin); -} - -static const struct BaseChannelVMT vmt = { - write, read, put, get, - putt, gett, writet, readt -}; - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -void conInit(void) { - - CD1.vmt = &vmt; -} - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/simulator/console.h b/firmware/ChibiOS_16/os/hal/ports/simulator/console.h deleted file mode 100644 index 0bd0b3178b..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/simulator/console.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file console.h - * @brief Simulator console driver header. - * @{ - */ - -#ifndef _CONSOLE_H_ -#define _CONSOLE_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -extern BaseChannel CD1; - -#ifdef __cplusplus -extern "C" { -#endif - void conInit(void); -#ifdef __cplusplus -} -#endif - -#endif /* _CONSOLE_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/simulator/pal_lld.c b/firmware/ChibiOS_16/os/hal/ports/simulator/pal_lld.c deleted file mode 100644 index ebe455b0bf..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/simulator/pal_lld.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file pal_lld.c - * @brief Win32 simulator low level PAL driver code. - * - * @addtogroup WIN32_PAL - * @{ - */ - -#include "hal.h" - -#if HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief VIO1 simulated port. - */ -sim_vio_port_t vio_port_1; - -/** - * @brief VIO2 simulated port. - */ -sim_vio_port_t vio_port_2; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Pads mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * - * @param[in] port the port identifier - * @param[in] mask the group mask - * @param[in] mode the mode - * - * @note This function is not meant to be invoked directly by the application - * code. - * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output with high - * state. - * @note This function does not alter the @p PINSELx registers. Alternate - * functions setup must be handled by device-specific code. - */ -void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - iomode_t mode) { - - switch (mode) { - case PAL_MODE_RESET: - case PAL_MODE_INPUT: - port->dir &= ~mask; - break; - case PAL_MODE_UNCONNECTED: - port->latch |= mask; - case PAL_MODE_OUTPUT_PUSHPULL: - port->dir |= mask; - break; - } -} - -#endif /* HAL_USE_PAL */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/simulator/pal_lld.h b/firmware/ChibiOS_16/os/hal/ports/simulator/pal_lld.h deleted file mode 100644 index ff8a3680f2..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/simulator/pal_lld.h +++ /dev/null @@ -1,206 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file pal_lld.h - * @brief Win32 simulator low level PAL driver header. - * - * @addtogroup WIN32_PAL - * @{ - */ - -#ifndef _PAL_LLD_H_ -#define _PAL_LLD_H_ - -#if HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Unsupported modes and specific modes */ -/*===========================================================================*/ - -#undef PAL_MODE_INPUT_PULLUP -#undef PAL_MODE_INPUT_PULLDOWN -#undef PAL_MODE_OUTPUT_OPENDRAIN -#undef PAL_MODE_INPUT_ANALOG - -/*===========================================================================*/ -/* I/O Ports Types and constants. */ -/*===========================================================================*/ - -/** - * @brief VIO port structure. - */ -typedef struct { - /** - * @brief VIO_LATCH register. - * @details This register represents the output latch of the VIO port. - */ - uint32_t latch; - /** - * @brief VIO_PIN register. - * @details This register represents the logical level at the VIO port - * pin level. - */ - uint32_t pin; - /** - * @brief VIO_DIR register. - * @details Direction of the VIO port bits, 0=input, 1=output. - */ - uint32_t dir; -} sim_vio_port_t; - -/** - * @brief Virtual I/O ports static initializer. - * @details An instance of this structure must be passed to @p palInit() at - * system startup time in order to initialized the digital I/O - * subsystem. This represents only the initial setup, specific pads - * or whole ports can be reprogrammed at later time. - */ -typedef struct { - /** - * @brief Virtual port 1 setup data. - */ - sim_vio_port_t VP1Data; - /** - * @brief Virtual port 2 setup data. - */ - sim_vio_port_t VP2Data; -} PALConfig; - -/** - * @brief Width, in bits, of an I/O port. - */ -#define PAL_IOPORTS_WIDTH 32 - -/** - * @brief Whole port mask. - * @brief This macro specifies all the valid bits into a port. - */ -#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFF) - -/** - * @brief Digital I/O port sized unsigned type. - */ -typedef uint32_t ioportmask_t; - -/** - * @brief Digital I/O modes. - */ -typedef uint32_t iomode_t; - -/** - * @brief Port Identifier. - */ -typedef sim_vio_port_t *ioportid_t; - -/*===========================================================================*/ -/* I/O Ports Identifiers. */ -/*===========================================================================*/ - -/** - * @brief VIO port 1 identifier. - */ -#define IOPORT1 (&vio_port_1) - -/** - * @brief VIO port 2 identifier. - */ -#define IOPORT2 (&vio_port_2) - -/*===========================================================================*/ -/* Implementation, some of the following macros could be implemented as */ -/* functions, if so please put them in pal_lld.c. */ -/*===========================================================================*/ - -/** - * @brief Low level PAL subsystem initialization. - * - * @param[in] config architecture-dependent ports configuration - * - * @notapi - */ -#define pal_lld_init(config) \ - (vio_port_1 = (config)->VP1Data, \ - vio_port_2 = (config)->VP2Data) - -/** - * @brief Reads the physical I/O port states. - * - * @param[in] port port identifier - * @return The port bits. - * - * @notapi - */ -#define pal_lld_readport(port) ((port)->pin) - -/** - * @brief Reads the output latch. - * @details The purpose of this function is to read back the latched output - * value. - * - * @param[in] port port identifier - * @return The latched logical states. - * - * @notapi - */ -#define pal_lld_readlatch(port) ((port)->latch) - -/** - * @brief Writes a bits mask on a I/O port. - * - * @param[in] port port identifier - * @param[in] bits bits to be written on the specified port - * - * @notapi - */ -#define pal_lld_writeport(port, bits) ((port)->latch = (bits)) - -/** - * @brief Pads group mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] offset group bit offset within the port - * @param[in] mode group mode - * - * @notapi - */ -#define pal_lld_setgroupmode(port, mask, offset, mode) \ - _pal_lld_setgroupmode(port, mask << offset, mode) - -#if !defined(__DOXYGEN__) -extern sim_vio_port_t vio_port_1; -extern sim_vio_port_t vio_port_2; -extern const PALConfig pal_default_config; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - iomode_t mode); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_PAL */ - -#endif /* _PAL_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/simulator/st_lld.c b/firmware/ChibiOS_16/os/hal/ports/simulator/st_lld.c deleted file mode 100644 index a54712907a..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/simulator/st_lld.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file st_lld.c - * @brief PLATFORM ST subsystem low level driver source. - * - * @addtogroup ST - * @{ - */ - -#include "hal.h" - -#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level ST driver initialization. - * - * @notapi - */ -void st_lld_init(void) { -} - -#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/simulator/st_lld.h b/firmware/ChibiOS_16/os/hal/ports/simulator/st_lld.h deleted file mode 100644 index d89a9e8b90..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/simulator/st_lld.h +++ /dev/null @@ -1,141 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file st_lld.h - * @brief PLATFORM ST subsystem low level driver header. - * @details This header is designed to be include-able without having to - * include other files from the HAL. - * - * @addtogroup ST - * @{ - */ - -#ifndef _ST_LLD_H_ -#define _ST_LLD_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void st_lld_init(void); -#ifdef __cplusplus -} -#endif - -/*===========================================================================*/ -/* Driver inline functions. */ -/*===========================================================================*/ - -/** - * @brief Returns the time counter value. - * - * @return The counter value. - * - * @notapi - */ -static inline systime_t st_lld_get_counter(void) { - - return (systime_t)0; -} - -/** - * @brief Starts the alarm. - * @note Makes sure that no spurious alarms are triggered after - * this call. - * - * @param[in] time the time to be set for the first alarm - * - * @notapi - */ -static inline void st_lld_start_alarm(systime_t time) { - - (void)time; -} - -/** - * @brief Stops the alarm interrupt. - * - * @notapi - */ -static inline void st_lld_stop_alarm(void) { - -} - -/** - * @brief Sets the alarm time. - * - * @param[in] time the time to be set for the next alarm - * - * @notapi - */ -static inline void st_lld_set_alarm(systime_t time) { - - (void)time; -} - -/** - * @brief Returns the current alarm time. - * - * @return The currently set alarm time. - * - * @notapi - */ -static inline systime_t st_lld_get_alarm(void) { - - return (systime_t)0; -} - -/** - * @brief Determines if the alarm is active. - * - * @return The alarm status. - * @retval false if the alarm is not active. - * @retval true is the alarm is active - * - * @notapi - */ -static inline bool st_lld_is_alarm_active(void) { - - return false; -} - -#endif /* _ST_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/simulator/win32/hal_lld.c b/firmware/ChibiOS_16/os/hal/ports/simulator/win32/hal_lld.c deleted file mode 100644 index 9e3ae25859..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/simulator/win32/hal_lld.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_lld.c - * @brief WIN32 simulator HAL subsystem low level driver code. - * - * @addtogroup WIN32_HAL - * @{ - */ - -#include "hal.h" - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -static LARGE_INTEGER nextcnt; -static LARGE_INTEGER slice; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level HAL driver initialization. - */ -void hal_lld_init(void) { - WSADATA wsaData; - - /* Initialization.*/ - if (WSAStartup(2, &wsaData) != 0) { - printf("Unable to locate a winsock DLL\n"); - exit(1); - } - - printf("ChibiOS/RT simulator (Win32)\n"); - if (!QueryPerformanceFrequency(&slice)) { - printf("QueryPerformanceFrequency() error"); - exit(1); - } - slice.QuadPart /= CH_CFG_ST_FREQUENCY; - QueryPerformanceCounter(&nextcnt); - nextcnt.QuadPart += slice.QuadPart; - - fflush(stdout); -} - -/** - * @brief Interrupt simulation. - */ -void _sim_check_for_interrupts(void) { - LARGE_INTEGER n; - -#if HAL_USE_SERIAL - if (sd_lld_interrupt_pending()) { - _dbg_check_lock(); - if (chSchIsPreemptionRequired()) - chSchDoReschedule(); - _dbg_check_unlock(); - return; - } -#endif - - /* Interrupt Timer simulation (10ms interval).*/ - QueryPerformanceCounter(&n); - if (n.QuadPart > nextcnt.QuadPart) { - nextcnt.QuadPart += slice.QuadPart; - - CH_IRQ_PROLOGUE(); - - chSysLockFromISR(); - chSysTimerHandlerI(); - chSysUnlockFromISR(); - - CH_IRQ_EPILOGUE(); - - _dbg_check_lock(); - if (chSchIsPreemptionRequired()) - chSchDoReschedule(); - _dbg_check_unlock(); - } -} - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/simulator/win32/hal_lld.h b/firmware/ChibiOS_16/os/hal/ports/simulator/win32/hal_lld.h deleted file mode 100644 index ca409e58fd..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/simulator/win32/hal_lld.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_lld.h - * @brief WIN32 simulator HAL subsystem low level driver header. - * - * @addtogroup WIN32_HAL - * @{ - */ - -#ifndef _HAL_LLD_H_ -#define _HAL_LLD_H_ - -#include -#include - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Platform name. - */ -#define PLATFORM_NAME "Win32 Simulator" - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void hal_lld_init(void); - void _sim_check_for_interrupts(void); -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/simulator/win32/platform.mk b/firmware/ChibiOS_16/os/hal/ports/simulator/win32/platform.mk deleted file mode 100644 index 60e4dd803a..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/simulator/win32/platform.mk +++ /dev/null @@ -1,10 +0,0 @@ -# List of all the Win32 platform files. -PLATFORMSRC = ${CHIBIOS}/os/hal/ports/simulator/win32/hal_lld.c \ - ${CHIBIOS}/os/hal/ports/simulator/win32/serial_lld.c \ - ${CHIBIOS}/os/hal/ports/simulator/console.c \ - ${CHIBIOS}/os/hal/ports/simulator/pal_lld.c \ - ${CHIBIOS}/os/hal/ports/simulator/st_lld.c - -# Required include directories -PLATFORMINC = ${CHIBIOS}/os/hal/ports/simulator/win32 \ - ${CHIBIOS}/os/hal/ports/simulator diff --git a/firmware/ChibiOS_16/os/hal/ports/simulator/win32/serial_lld.c b/firmware/ChibiOS_16/os/hal/ports/simulator/win32/serial_lld.c deleted file mode 100644 index 04780cf934..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/simulator/win32/serial_lld.c +++ /dev/null @@ -1,282 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file serial_lld.c - * @brief Win32 simulator low level serial driver code. - * - * @addtogroup WIN32_SERIAL - * @{ - */ - -#include "hal.h" - -#if HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief Serial driver 1 identifier.*/ -#if USE_WIN32_SERIAL1 || defined(__DOXYGEN__) -SerialDriver SD1; -#endif -/** @brief Serial driver 2 identifier.*/ -#if USE_WIN32_SERIAL2 || defined(__DOXYGEN__) -SerialDriver SD2; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** @brief Driver default configuration.*/ -static const SerialConfig default_config = { -}; - -static u_long nb = 1; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void init(SerialDriver *sdp, uint16_t port) { - struct sockaddr_in sad; - struct protoent *prtp; - - if ((prtp = getprotobyname("tcp")) == NULL) { - printf("%s: Error mapping protocol name to protocol number\n", sdp->com_name); - goto abort; - } - - sdp->com_listen = socket(PF_INET, SOCK_STREAM, prtp->p_proto); - if (sdp->com_listen == INVALID_SOCKET) { - printf("%s: Error creating simulator socket\n", sdp->com_name); - goto abort; - } - - if (ioctlsocket(sdp->com_listen, FIONBIO, &nb) != 0) { - printf("%s: Unable to setup non blocking mode on socket\n", sdp->com_name); - goto abort; - } - - memset(&sad, 0, sizeof(sad)); - sad.sin_family = AF_INET; - sad.sin_addr.s_addr = INADDR_ANY; - sad.sin_port = htons(port); - if (bind(sdp->com_listen, (struct sockaddr *)&sad, sizeof(sad))) { - printf("%s: Error binding socket\n", sdp->com_name); - goto abort; - } - - if (listen(sdp->com_listen, 1) != 0) { - printf("%s: Error listening socket\n", sdp->com_name); - goto abort; - } - printf("Full Duplex Channel %s listening on port %d\n", sdp->com_name, port); - return; - -abort: - if (sdp->com_listen != INVALID_SOCKET) - closesocket(sdp->com_listen); - WSACleanup(); - exit(1); -} - -static bool connint(SerialDriver *sdp) { - - if (sdp->com_data == INVALID_SOCKET) { - struct sockaddr addr; - int addrlen = sizeof(addr); - - if ((sdp->com_data = accept(sdp->com_listen, &addr, &addrlen)) == INVALID_SOCKET) - return FALSE; - - if (ioctlsocket(sdp->com_data, FIONBIO, &nb) != 0) { - printf("%s: Unable to setup non blocking mode on data socket\n", sdp->com_name); - goto abort; - } - chSysLockFromISR(); - chnAddFlagsI(sdp, CHN_CONNECTED); - chSysUnlockFromISR(); - return TRUE; - } - return FALSE; -abort: - if (sdp->com_listen != INVALID_SOCKET) - closesocket(sdp->com_listen); - if (sdp->com_data != INVALID_SOCKET) - closesocket(sdp->com_data); - WSACleanup(); - exit(1); -} - -static bool inint(SerialDriver *sdp) { - - if (sdp->com_data != INVALID_SOCKET) { - int i; - uint8_t data[32]; - - /* - * Input. - */ - int n = recv(sdp->com_data, (char *)data, sizeof(data), 0); - switch (n) { - case 0: - closesocket(sdp->com_data); - sdp->com_data = INVALID_SOCKET; - chSysLockFromISR(); - chnAddFlagsI(sdp, CHN_DISCONNECTED); - chSysUnlockFromISR(); - return FALSE; - case SOCKET_ERROR: - if (WSAGetLastError() == WSAEWOULDBLOCK) - return FALSE; - closesocket(sdp->com_data); - sdp->com_data = INVALID_SOCKET; - return FALSE; - } - for (i = 0; i < n; i++) { - chSysLockFromISR(); - sdIncomingDataI(sdp, data[i]); - chSysUnlockFromISR(); - } - return TRUE; - } - return FALSE; -} - -static bool outint(SerialDriver *sdp) { - - if (sdp->com_data != INVALID_SOCKET) { - int n; - uint8_t data[1]; - - /* - * Input. - */ - chSysLockFromISR(); - n = sdRequestDataI(sdp); - chSysUnlockFromISR(); - if (n < 0) - return FALSE; - data[0] = (uint8_t)n; - n = send(sdp->com_data, (char *)data, sizeof(data), 0); - switch (n) { - case 0: - closesocket(sdp->com_data); - sdp->com_data = INVALID_SOCKET; - chSysLockFromISR(); - chnAddFlagsI(sdp, CHN_DISCONNECTED); - chSysUnlockFromISR(); - return FALSE; - case SOCKET_ERROR: - if (WSAGetLastError() == WSAEWOULDBLOCK) - return FALSE; - closesocket(sdp->com_data); - sdp->com_data = INVALID_SOCKET; - return FALSE; - } - return TRUE; - } - return FALSE; -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * Low level serial driver initialization. - */ -void sd_lld_init(void) { - -#if USE_WIN32_SERIAL1 - sdObjectInit(&SD1, NULL, NULL); - SD1.com_listen = INVALID_SOCKET; - SD1.com_data = INVALID_SOCKET; - SD1.com_name = "SD1"; -#endif - -#if USE_WIN32_SERIAL2 - sdObjectInit(&SD2, NULL, NULL); - SD2.com_listen = INVALID_SOCKET; - SD2.com_data = INVALID_SOCKET; - SD2.com_name = "SD2"; -#endif -} - -/** - * @brief Low level serial driver configuration and (re)start. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] config the architecture-dependent serial driver configuration. - * If this parameter is set to @p NULL then a default - * configuration is used. - */ -void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { - - if (config == NULL) - config = &default_config; - -#if USE_WIN32_SERIAL1 - if (sdp == &SD1) - init(&SD1, SD1_PORT); -#endif - -#if USE_WIN32_SERIAL2 - if (sdp == &SD2) - init(&SD2, SD2_PORT); -#endif -} - -/** - * @brief Low level serial driver stop. - * @details De-initializes the USART, stops the associated clock, resets the - * interrupt vector. - * - * @param[in] sdp pointer to a @p SerialDriver object - */ -void sd_lld_stop(SerialDriver *sdp) { - - (void)sdp; -} - -bool sd_lld_interrupt_pending(void) { - bool b = false; - - CH_IRQ_PROLOGUE(); - -#if USE_WIN32_SERIAL1 - b |= connint(&SD1) || inint(&SD1) || outint(&SD1); -#endif - -#if USE_WIN32_SERIAL2 - b |= connint(&SD2) || inint(&SD2) || outint(&SD2); -#endif - - CH_IRQ_EPILOGUE(); - - return b; -} - -#endif /* HAL_USE_SERIAL */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/ports/simulator/win32/serial_lld.h b/firmware/ChibiOS_16/os/hal/ports/simulator/win32/serial_lld.h deleted file mode 100644 index 839a063fcb..0000000000 --- a/firmware/ChibiOS_16/os/hal/ports/simulator/win32/serial_lld.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file serial_lld.h - * @brief Win32 simulator low level serial driver header. - * - * @addtogroup WIN32_SERIAL - * @{ - */ - -#ifndef _SERIAL_LLD_H_ -#define _SERIAL_LLD_H_ - -#if HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Serial buffers size. - * @details Configuration parameter, you can change the depth of the queue - * buffers depending on the requirements of your application. - */ -#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_BUFFERS_SIZE 1024 -#endif - -/** - * @brief SD1 driver enable switch. - * @details If set to @p TRUE the support for SD1 is included. - * @note The default is @p TRUE. - */ -#if !defined(USE_WIN32_SERIAL1) || defined(__DOXYGEN__) -#define USE_WIN32_SERIAL1 TRUE -#endif - -/** - * @brief SD2 driver enable switch. - * @details If set to @p TRUE the support for SD2 is included. - * @note The default is @p TRUE. - */ -#if !defined(USE_WIN32_SERIAL2) || defined(__DOXYGEN__) -#define USE_WIN32_SERIAL2 TRUE -#endif - -/** - * @brief Listen port for SD1. - */ -#if !defined(SD1_PORT) || defined(__DOXYGEN__) -#define SD1_PORT 29001 -#endif - -/** - * @brief Listen port for SD2. - */ -#if !defined(SD2_PORT) || defined(__DOXYGEN__) -#define SD2_PORT 29002 -#endif - -/*===========================================================================*/ -/* Unsupported event flags and custom events. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Generic Serial Driver configuration structure. - * @details An instance of this structure must be passed to @p sdStart() - * in order to configure and start a serial driver operations. - * @note This structure content is architecture dependent, each driver - * implementation defines its own version and the custom static - * initializers. - */ -typedef struct { -} SerialConfig; - -/** - * @brief @p SerialDriver specific data. - */ -#define _serial_driver_data \ - _base_asynchronous_channel_data \ - /* Driver state.*/ \ - sdstate_t state; \ - /* Input queue.*/ \ - input_queue_t iqueue; \ - /* Output queue.*/ \ - output_queue_t oqueue; \ - /* Input circular buffer.*/ \ - uint8_t ib[SERIAL_BUFFERS_SIZE]; \ - /* Output circular buffer.*/ \ - uint8_t ob[SERIAL_BUFFERS_SIZE]; \ - /* End of the mandatory fields.*/ \ - /* Listen socket for simulated serial port.*/ \ - SOCKET com_listen; \ - /* Data socket for simulated serial port.*/ \ - SOCKET com_data; \ - /* Port readable name.*/ \ - const char *com_name; - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if USE_WIN32_SERIAL1 && !defined(__DOXYGEN__) -extern SerialDriver SD1; -#endif -#if USE_WIN32_SERIAL2 && !defined(__DOXYGEN__) -extern SerialDriver SD2; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void sd_lld_init(void); - void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); - void sd_lld_stop(SerialDriver *sdp); - bool sd_lld_interrupt_pending(void); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_SERIAL */ - -#endif /* _SERIAL_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/src/adc.c b/firmware/ChibiOS_16/os/hal/src/adc.c deleted file mode 100644 index 1a3def3345..0000000000 --- a/firmware/ChibiOS_16/os/hal/src/adc.c +++ /dev/null @@ -1,321 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file adc.c - * @brief ADC Driver code. - * - * @addtogroup ADC - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_ADC == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief ADC Driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void adcInit(void) { - - adc_lld_init(); -} - -/** - * @brief Initializes the standard part of a @p ADCDriver structure. - * - * @param[out] adcp pointer to the @p ADCDriver object - * - * @init - */ -void adcObjectInit(ADCDriver *adcp) { - - adcp->state = ADC_STOP; - adcp->config = NULL; - adcp->samples = NULL; - adcp->depth = 0; - adcp->grpp = NULL; -#if ADC_USE_WAIT == TRUE - adcp->thread = NULL; -#endif -#if ADC_USE_MUTUAL_EXCLUSION == TRUE - osalMutexObjectInit(&adcp->mutex); -#endif -#if defined(ADC_DRIVER_EXT_INIT_HOOK) - ADC_DRIVER_EXT_INIT_HOOK(adcp); -#endif -} - -/** - * @brief Configures and activates the ADC peripheral. - * - * @param[in] adcp pointer to the @p ADCDriver object - * @param[in] config pointer to the @p ADCConfig object. Depending on - * the implementation the value can be @p NULL. - * - * @api - */ -void adcStart(ADCDriver *adcp, const ADCConfig *config) { - - osalDbgCheck(adcp != NULL); - - osalSysLock(); - osalDbgAssert((adcp->state == ADC_STOP) || (adcp->state == ADC_READY), - "invalid state"); - adcp->config = config; - adc_lld_start(adcp); - adcp->state = ADC_READY; - osalSysUnlock(); -} - -/** - * @brief Deactivates the ADC peripheral. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @api - */ -void adcStop(ADCDriver *adcp) { - - osalDbgCheck(adcp != NULL); - - osalSysLock(); - osalDbgAssert((adcp->state == ADC_STOP) || (adcp->state == ADC_READY), - "invalid state"); - adc_lld_stop(adcp); - adcp->state = ADC_STOP; - osalSysUnlock(); -} - -/** - * @brief Starts an ADC conversion. - * @details Starts an asynchronous conversion operation. - * @note The buffer is organized as a matrix of M*N elements where M is the - * channels number configured into the conversion group and N is the - * buffer depth. The samples are sequentially written into the buffer - * with no gaps. - * - * @param[in] adcp pointer to the @p ADCDriver object - * @param[in] grpp pointer to a @p ADCConversionGroup object - * @param[out] samples pointer to the samples buffer - * @param[in] depth buffer depth (matrix rows number). The buffer depth - * must be one or an even number. - * - * @api - */ -void adcStartConversion(ADCDriver *adcp, - const ADCConversionGroup *grpp, - adcsample_t *samples, - size_t depth) { - - osalSysLock(); - adcStartConversionI(adcp, grpp, samples, depth); - osalSysUnlock(); -} - -/** - * @brief Starts an ADC conversion. - * @details Starts an asynchronous conversion operation. - * @post The callbacks associated to the conversion group will be invoked - * on buffer fill and error events. - * @note The buffer is organized as a matrix of M*N elements where M is the - * channels number configured into the conversion group and N is the - * buffer depth. The samples are sequentially written into the buffer - * with no gaps. - * - * @param[in] adcp pointer to the @p ADCDriver object - * @param[in] grpp pointer to a @p ADCConversionGroup object - * @param[out] samples pointer to the samples buffer - * @param[in] depth buffer depth (matrix rows number). The buffer depth - * must be one or an even number. - * - * @iclass - */ -void adcStartConversionI(ADCDriver *adcp, - const ADCConversionGroup *grpp, - adcsample_t *samples, - size_t depth) { - - osalDbgCheckClassI(); - osalDbgCheck((adcp != NULL) && (grpp != NULL) && (samples != NULL) && - ((depth == 1U) || ((depth & 1U) == 0U))); - osalDbgAssert((adcp->state == ADC_READY) || - (adcp->state == ADC_COMPLETE) || - (adcp->state == ADC_ERROR), - "not ready"); - - adcp->samples = samples; - adcp->depth = depth; - adcp->grpp = grpp; - adcp->state = ADC_ACTIVE; - adc_lld_start_conversion(adcp); -} - -/** - * @brief Stops an ongoing conversion. - * @details This function stops the currently ongoing conversion and returns - * the driver in the @p ADC_READY state. If there was no conversion - * being processed then the function does nothing. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @api - */ -void adcStopConversion(ADCDriver *adcp) { - - osalDbgCheck(adcp != NULL); - - osalSysLock(); - osalDbgAssert((adcp->state == ADC_READY) || (adcp->state == ADC_ACTIVE), - "invalid state"); - if (adcp->state != ADC_READY) { - adc_lld_stop_conversion(adcp); - adcp->grpp = NULL; - adcp->state = ADC_READY; - _adc_reset_s(adcp); - } - osalSysUnlock(); -} - -/** - * @brief Stops an ongoing conversion. - * @details This function stops the currently ongoing conversion and returns - * the driver in the @p ADC_READY state. If there was no conversion - * being processed then the function does nothing. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @iclass - */ -void adcStopConversionI(ADCDriver *adcp) { - - osalDbgCheckClassI(); - osalDbgCheck(adcp != NULL); - osalDbgAssert((adcp->state == ADC_READY) || - (adcp->state == ADC_ACTIVE) || - (adcp->state == ADC_COMPLETE), - "invalid state"); - - if (adcp->state != ADC_READY) { - adc_lld_stop_conversion(adcp); - adcp->grpp = NULL; - adcp->state = ADC_READY; - _adc_reset_i(adcp); - } -} - -#if (ADC_USE_WAIT == TRUE) || defined(__DOXYGEN__) -/** - * @brief Performs an ADC conversion. - * @details Performs a synchronous conversion operation. - * @note The buffer is organized as a matrix of M*N elements where M is the - * channels number configured into the conversion group and N is the - * buffer depth. The samples are sequentially written into the buffer - * with no gaps. - * - * @param[in] adcp pointer to the @p ADCDriver object - * @param[in] grpp pointer to a @p ADCConversionGroup object - * @param[out] samples pointer to the samples buffer - * @param[in] depth buffer depth (matrix rows number). The buffer depth - * must be one or an even number. - * @return The operation result. - * @retval MSG_OK Conversion finished. - * @retval MSG_RESET The conversion has been stopped using - * @p acdStopConversion() or @p acdStopConversionI(), - * the result buffer may contain incorrect data. - * @retval MSG_TIMEOUT The conversion has been stopped because an hardware - * error. - * - * @api - */ -msg_t adcConvert(ADCDriver *adcp, - const ADCConversionGroup *grpp, - adcsample_t *samples, - size_t depth) { - msg_t msg; - - osalSysLock(); - osalDbgAssert(adcp->thread == NULL, "already waiting"); - adcStartConversionI(adcp, grpp, samples, depth); - msg = osalThreadSuspendS(&adcp->thread); - osalSysUnlock(); - return msg; -} -#endif /* ADC_USE_WAIT == TRUE */ - -#if (ADC_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__) -/** - * @brief Gains exclusive access to the ADC peripheral. - * @details This function tries to gain ownership to the ADC bus, if the bus - * is already being used then the invoking thread is queued. - * @pre In order to use this function the option - * @p ADC_USE_MUTUAL_EXCLUSION must be enabled. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @api - */ -void adcAcquireBus(ADCDriver *adcp) { - - osalDbgCheck(adcp != NULL); - - osalMutexLock(&adcp->mutex); -} - -/** - * @brief Releases exclusive access to the ADC peripheral. - * @pre In order to use this function the option - * @p ADC_USE_MUTUAL_EXCLUSION must be enabled. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @api - */ -void adcReleaseBus(ADCDriver *adcp) { - - osalDbgCheck(adcp != NULL); - - osalMutexUnlock(&adcp->mutex); -} -#endif /* ADC_USE_MUTUAL_EXCLUSION == TRUE */ - -#endif /* HAL_USE_ADC == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/src/can.c b/firmware/ChibiOS_16/os/hal/src/can.c deleted file mode 100644 index 268bc4a7e0..0000000000 --- a/firmware/ChibiOS_16/os/hal/src/can.c +++ /dev/null @@ -1,361 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file can.c - * @brief CAN Driver code. - * - * @addtogroup CAN - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_CAN == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief CAN Driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void canInit(void) { - - can_lld_init(); -} - -/** - * @brief Initializes the standard part of a @p CANDriver structure. - * - * @param[out] canp pointer to the @p CANDriver object - * - * @init - */ -void canObjectInit(CANDriver *canp) { - - canp->state = CAN_STOP; - canp->config = NULL; - osalThreadQueueObjectInit(&canp->txqueue); - osalThreadQueueObjectInit(&canp->rxqueue); - osalEventObjectInit(&canp->rxfull_event); - osalEventObjectInit(&canp->txempty_event); - osalEventObjectInit(&canp->error_event); -#if CAN_USE_SLEEP_MODE == TRUE - osalEventObjectInit(&canp->sleep_event); - osalEventObjectInit(&canp->wakeup_event); -#endif -} - -/** - * @brief Configures and activates the CAN peripheral. - * @note Activating the CAN bus can be a slow operation. - * @note Unlike other drivers it is not possible to restart the CAN - * driver without first stopping it using canStop(). - * - * @param[in] canp pointer to the @p CANDriver object - * @param[in] config pointer to the @p CANConfig object. Depending on - * the implementation the value can be @p NULL. - * - * @api - */ -void canStart(CANDriver *canp, const CANConfig *config) { - - osalDbgCheck(canp != NULL); - - osalSysLock(); - osalDbgAssert(canp->state == CAN_STOP, "invalid state"); - - /* Entering initialization mode. */ - canp->state = CAN_STARTING; - canp->config = config; - - /* Low level initialization, could be a slow process and sleeps could - be performed inside.*/ - can_lld_start(canp); - - /* The driver finally goes into the ready state.*/ - canp->state = CAN_READY; - osalSysUnlock(); -} - -/** - * @brief Deactivates the CAN peripheral. - * - * @param[in] canp pointer to the @p CANDriver object - * - * @api - */ -void canStop(CANDriver *canp) { - - osalDbgCheck(canp != NULL); - - osalSysLock(); - osalDbgAssert((canp->state == CAN_STOP) || (canp->state == CAN_READY), - "invalid state"); - - /* The low level driver is stopped.*/ - can_lld_stop(canp); - canp->state = CAN_STOP; - - /* Threads waiting on CAN APIs are notified that the driver has been - stopped in order to not have stuck threads.*/ - osalThreadDequeueAllI(&canp->rxqueue, MSG_RESET); - osalThreadDequeueAllI(&canp->txqueue, MSG_RESET); - osalOsRescheduleS(); - osalSysUnlock(); -} - -/** - * @brief Can frame transmission attempt. - * @details The specified frame is queued for transmission, if the hardware - * queue is full then the function fails. - * - * @param[in] canp pointer to the @p CANDriver object - * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox - * @param[in] ctfp pointer to the CAN frame to be transmitted - * @return The operation result. - * @retval false Frame transmitted. - * @retval true Mailbox full. - * - * @iclass - */ -bool canTryTransmitI(CANDriver *canp, - canmbx_t mailbox, - const CANTxFrame *ctfp) { - - osalDbgCheckClassI(); - osalDbgCheck((canp != NULL) && (ctfp != NULL) && - (mailbox <= (canmbx_t)CAN_TX_MAILBOXES)); - osalDbgAssert((canp->state == CAN_READY) || (canp->state == CAN_SLEEP), - "invalid state"); - - /* If the RX mailbox is full then the function fails.*/ - if (!can_lld_is_tx_empty(canp, mailbox)) { - return true; - } - - /* Transmitting frame.*/ - can_lld_transmit(canp, mailbox, ctfp); - - return false; -} - -/** - * @brief Can frame receive attempt. - * @details The function tries to fetch a frame from a mailbox. - * - * @param[in] canp pointer to the @p CANDriver object - * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox - * @param[out] crfp pointer to the buffer where the CAN frame is copied - * @return The operation result. - * @retval false Frame fetched. - * @retval true Mailbox empty. - * - * @iclass - */ -bool canTryReceiveI(CANDriver *canp, - canmbx_t mailbox, - CANRxFrame *crfp) { - - osalDbgCheckClassI(); - osalDbgCheck((canp != NULL) && (crfp != NULL) && - (mailbox <= (canmbx_t)CAN_RX_MAILBOXES)); - osalDbgAssert((canp->state == CAN_READY) || (canp->state == CAN_SLEEP), - "invalid state"); - - /* If the RX mailbox is empty then the function fails.*/ - if (!can_lld_is_rx_nonempty(canp, mailbox)) { - return true; - } - - /* Fetching the frame.*/ - can_lld_receive(canp, mailbox, crfp); - - return false; -} - -/** - * @brief Can frame transmission. - * @details The specified frame is queued for transmission, if the hardware - * queue is full then the invoking thread is queued. - * @note Trying to transmit while in sleep mode simply enqueues the thread. - * - * @param[in] canp pointer to the @p CANDriver object - * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox - * @param[in] ctfp pointer to the CAN frame to be transmitted - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation result. - * @retval MSG_OK the frame has been queued for transmission. - * @retval MSG_TIMEOUT The operation has timed out. - * @retval MSG_RESET The driver has been stopped while waiting. - * - * @api - */ -msg_t canTransmit(CANDriver *canp, - canmbx_t mailbox, - const CANTxFrame *ctfp, - systime_t timeout) { - - osalDbgCheck((canp != NULL) && (ctfp != NULL) && - (mailbox <= (canmbx_t)CAN_TX_MAILBOXES)); - - osalSysLock(); - osalDbgAssert((canp->state == CAN_READY) || (canp->state == CAN_SLEEP), - "invalid state"); - - /*lint -save -e9007 [13.5] Right side is supposed to be pure.*/ - while ((canp->state == CAN_SLEEP) || !can_lld_is_tx_empty(canp, mailbox)) { - /*lint -restore*/ - msg_t msg = osalThreadEnqueueTimeoutS(&canp->txqueue, timeout); - if (msg != MSG_OK) { - osalSysUnlock(); - return msg; - } - } - can_lld_transmit(canp, mailbox, ctfp); - osalSysUnlock(); - return MSG_OK; -} - -/** - * @brief Can frame receive. - * @details The function waits until a frame is received. - * @note Trying to receive while in sleep mode simply enqueues the thread. - * - * @param[in] canp pointer to the @p CANDriver object - * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox - * @param[out] crfp pointer to the buffer where the CAN frame is copied - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout (useful in an - * event driven scenario where a thread never blocks - * for I/O). - * - @a TIME_INFINITE no timeout. - * . - * @return The operation result. - * @retval MSG_OK a frame has been received and placed in the buffer. - * @retval MSG_TIMEOUT The operation has timed out. - * @retval MSG_RESET The driver has been stopped while waiting. - * - * @api - */ -msg_t canReceive(CANDriver *canp, - canmbx_t mailbox, - CANRxFrame *crfp, - systime_t timeout) { - - osalDbgCheck((canp != NULL) && (crfp != NULL) && - (mailbox <= (canmbx_t)CAN_RX_MAILBOXES)); - - osalSysLock(); - osalDbgAssert((canp->state == CAN_READY) || (canp->state == CAN_SLEEP), - "invalid state"); - - /*lint -save -e9007 [13.5] Right side is supposed to be pure.*/ - while ((canp->state == CAN_SLEEP) || !can_lld_is_rx_nonempty(canp, mailbox)) { - /*lint -restore*/ - msg_t msg = osalThreadEnqueueTimeoutS(&canp->rxqueue, timeout); - if (msg != MSG_OK) { - osalSysUnlock(); - return msg; - } - } - can_lld_receive(canp, mailbox, crfp); - osalSysUnlock(); - return MSG_OK; -} - -#if (CAN_USE_SLEEP_MODE == TRUE) || defined(__DOXYGEN__) -/** - * @brief Enters the sleep mode. - * @details This function puts the CAN driver in sleep mode and broadcasts - * the @p sleep_event event source. - * @pre In order to use this function the option @p CAN_USE_SLEEP_MODE must - * be enabled and the @p CAN_SUPPORTS_SLEEP mode must be supported - * by the low level driver. - * - * @param[in] canp pointer to the @p CANDriver object - * - * @api - */ -void canSleep(CANDriver *canp) { - - osalDbgCheck(canp != NULL); - - osalSysLock(); - osalDbgAssert((canp->state == CAN_READY) || (canp->state == CAN_SLEEP), - "invalid state"); - if (canp->state == CAN_READY) { - can_lld_sleep(canp); - canp->state = CAN_SLEEP; - osalEventBroadcastFlagsI(&canp->sleep_event, (eventflags_t)0); - osalOsRescheduleS(); - } - osalSysUnlock(); -} - -/** - * @brief Enforces leaving the sleep mode. - * @note The sleep mode is supposed to be usually exited automatically by - * an hardware event. - * - * @param[in] canp pointer to the @p CANDriver object - */ -void canWakeup(CANDriver *canp) { - - osalDbgCheck(canp != NULL); - - osalSysLock(); - osalDbgAssert((canp->state == CAN_READY) || (canp->state == CAN_SLEEP), - "invalid state"); - if (canp->state == CAN_SLEEP) { - can_lld_wakeup(canp); - canp->state = CAN_READY; - osalEventBroadcastFlagsI(&canp->wakeup_event, (eventflags_t)0); - osalOsRescheduleS(); - } - osalSysUnlock(); -} -#endif /* CAN_USE_SLEEP_MODE == TRUE */ - -#endif /* HAL_USE_CAN == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/src/dac.c b/firmware/ChibiOS_16/os/hal/src/dac.c deleted file mode 100644 index 8e45c28b37..0000000000 --- a/firmware/ChibiOS_16/os/hal/src/dac.c +++ /dev/null @@ -1,349 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file dac.c - * @brief DAC Driver code. - * - * @addtogroup DAC - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_DAC == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief DAC Driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void dacInit(void) { - - dac_lld_init(); -} - -/** - * @brief Initializes the standard part of a @p DACDriver structure. - * - * @param[out] dacp pointer to the @p DACDriver object - * - * @init - */ -void dacObjectInit(DACDriver *dacp) { - - dacp->state = DAC_STOP; - dacp->config = NULL; -#if DAC_USE_WAIT - dacp->thread = NULL; -#endif -#if DAC_USE_MUTUAL_EXCLUSION - osalMutexObjectInit(&dacp->mutex); -#endif -#if defined(DAC_DRIVER_EXT_INIT_HOOK) - DAC_DRIVER_EXT_INIT_HOOK(dacp); -#endif -} - -/** - * @brief Configures and activates the DAC peripheral. - * - * @param[in] dacp pointer to the @p DACDriver object - * @param[in] config pointer to the @p DACConfig object, it can be - * @p NULL if the low level driver implementation - * supports a default configuration - * - * @api - */ -void dacStart(DACDriver *dacp, const DACConfig *config) { - - osalDbgCheck(dacp != NULL); - - osalSysLock(); - - osalDbgAssert((dacp->state == DAC_STOP) || (dacp->state == DAC_READY), - "invalid state"); - - dacp->config = config; - dac_lld_start(dacp); - dacp->state = DAC_READY; - - osalSysUnlock(); -} - -/** - * @brief Deactivates the DAC peripheral. - * @note Deactivating the peripheral also enforces a release of the slave - * select line. - * - * @param[in] dacp pointer to the @p DACDriver object - * - * @api - */ -void dacStop(DACDriver *dacp) { - - osalDbgCheck(dacp != NULL); - - osalSysLock(); - - osalDbgAssert((dacp->state == DAC_STOP) || (dacp->state == DAC_READY), - "invalid state"); - - dac_lld_stop(dacp); - dacp->state = DAC_STOP; - - osalSysUnlock(); -} - -/** - * @brief Outputs a value directly on a DAC channel. - * - * @param[in] dacp pointer to the @p DACDriver object - * @param[in] channel DAC channel number - * @param[in] sample value to be output - * - * @xclass - */ -void dacPutChannelX(DACDriver *dacp, dacchannel_t channel, dacsample_t sample) { - - osalDbgCheck(channel < DAC_MAX_CHANNELS); - osalDbgAssert(dacp->state == DAC_READY, "invalid state"); - - dac_lld_put_channel(dacp, channel, sample); -} - -/** - * @brief Starts a DAC conversion. - * @details Starts an asynchronous conversion operation. - * @note The buffer is organized as a matrix of M*N elements where M is the - * channels number configured into the conversion group and N is the - * buffer depth. The samples are sequentially written into the buffer - * with no gaps. - * - * @param[in] dacp pointer to the @p DACDriver object - * @param[in] grpp pointer to a @p DACConversionGroup object - * @param[in] samples pointer to the samples buffer - * @param[in] depth buffer depth (matrix rows number). The buffer depth - * must be one or an even number. - * - * @api - */ -void dacStartConversion(DACDriver *dacp, - const DACConversionGroup *grpp, - const dacsample_t *samples, - size_t depth) { - - osalSysLock(); - dacStartConversionI(dacp, grpp, samples, depth); - osalSysUnlock(); -} - -/** - * @brief Starts a DAC conversion. - * @details Starts an asynchronous conversion operation. - * @post The callbacks associated to the conversion group will be invoked - * on buffer fill and error events. - * @note The buffer is organized as a matrix of M*N elements where M is the - * channels number configured into the conversion group and N is the - * buffer depth. The samples are sequentially written into the buffer - * with no gaps. - * - * @param[in] dacp pointer to the @p DACDriver object - * @param[in] grpp pointer to a @p DACConversionGroup object - * @param[in] samples pointer to the samples buffer - * @param[in] depth buffer depth (matrix rows number). The buffer depth - * must be one or an even number. - * - * @iclass - */ -void dacStartConversionI(DACDriver *dacp, - const DACConversionGroup *grpp, - const dacsample_t *samples, - size_t depth) { - - osalDbgCheckClassI(); - osalDbgCheck((dacp != NULL) && (grpp != NULL) && (samples != NULL) && - ((depth == 1) || ((depth & 1) == 0))); - osalDbgAssert((dacp->state == DAC_READY) || - (dacp->state == DAC_COMPLETE) || - (dacp->state == DAC_ERROR), - "not ready"); - - dacp->samples = samples; - dacp->depth = depth; - dacp->grpp = grpp; - dacp->state = DAC_ACTIVE; - dac_lld_start_conversion(dacp); -} - -/** - * @brief Stops an ongoing conversion. - * @details This function stops the currently ongoing conversion and returns - * the driver in the @p DAC_READY state. If there was no conversion - * being processed then the function does nothing. - * - * @param[in] dacp pointer to the @p DACDriver object - * - * @api - */ -void dacStopConversion(DACDriver *dacp) { - - osalDbgCheck(dacp != NULL); - - osalSysLock(); - - osalDbgAssert((dacp->state == DAC_READY) || - (dacp->state == DAC_ACTIVE), - "invalid state"); - - if (dacp->state != DAC_READY) { - dac_lld_stop_conversion(dacp); - dacp->grpp = NULL; - dacp->state = DAC_READY; - _dac_reset_s(dacp); - } - - osalSysUnlock(); -} - -/** - * @brief Stops an ongoing conversion. - * @details This function stops the currently ongoing conversion and returns - * the driver in the @p DAC_READY state. If there was no conversion - * being processed then the function does nothing. - * - * @param[in] dacp pointer to the @p DACDriver object - * - * @iclass - */ -void dacStopConversionI(DACDriver *dacp) { - - osalDbgCheckClassI(); - osalDbgCheck(dacp != NULL); - osalDbgAssert((dacp->state == DAC_READY) || - (dacp->state == DAC_ACTIVE) || - (dacp->state == DAC_COMPLETE), - "invalid state"); - - if (dacp->state != DAC_READY) { - dac_lld_stop_conversion(dacp); - dacp->grpp = NULL; - dacp->state = DAC_READY; - _dac_reset_i(dacp); - } -} - -#if (DAC_USE_WAIT == TRUE) || defined(__DOXYGEN__) -/** - * @brief Performs a DAC conversion. - * @details Performs a synchronous conversion operation. - * @note The buffer is organized as a matrix of M*N elements where M is the - * channels number configured into the conversion group and N is the - * buffer depth. The samples are sequentially written into the buffer - * with no gaps. - * - * @param[in] dacp pointer to the @p DACDriver object - * @param[in] grpp pointer to a @p DACConversionGroup object - * @param[out] samples pointer to the samples buffer - * @param[in] depth buffer depth (matrix rows number). The buffer depth - * must be one or an even number. - * @return The operation result. - * @retval MSG_OK Conversion finished. - * @retval MSG_RESET The conversion has been stopped using - * @p acdStopConversion() or @p acdStopConversionI(), - * the result buffer may contain incorrect data. - * @retval MSG_TIMEOUT The conversion has been stopped because an hardware - * error. - * - * @api - */ -msg_t dacConvert(DACDriver *dacp, - const DACConversionGroup *grpp, - const dacsample_t *samples, - size_t depth) { - msg_t msg; - - osalSysLock(); - - dacStartConversionI(dacp, grpp, samples, depth); - msg = osalThreadSuspendS(&dacp->thread); - - osalSysUnlock(); - return msg; -} -#endif /* DAC_USE_WAIT == TRUE */ - -#if (DAC_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__) -/** - * @brief Gains exclusive access to the DAC bus. - * @details This function tries to gain ownership to the DAC bus, if the bus - * is already being used then the invoking thread is queued. - * @pre In order to use this function the option @p DAC_USE_MUTUAL_EXCLUSION - * must be enabled. - * - * @param[in] dacp pointer to the @p DACDriver object - * - * @api - */ -void dacAcquireBus(DACDriver *dacp) { - - osalDbgCheck(dacp != NULL); - - osalMutexLock(&dacp->mutex); -} - -/** - * @brief Releases exclusive access to the DAC bus. - * @pre In order to use this function the option @p DAC_USE_MUTUAL_EXCLUSION - * must be enabled. - * - * @param[in] dacp pointer to the @p DACDriver object - * - * @api - */ -void dacReleaseBus(DACDriver *dacp) { - - osalDbgCheck(dacp != NULL); - - osalMutexUnlock(&dacp->mutex); -} -#endif /* DAC_USE_MUTUAL_EXCLUSION == TRUE */ - -#endif /* HAL_USE_DAC == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/src/ext.c b/firmware/ChibiOS_16/os/hal/src/ext.c deleted file mode 100644 index c7febdfc94..0000000000 --- a/firmware/ChibiOS_16/os/hal/src/ext.c +++ /dev/null @@ -1,202 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file ext.c - * @brief EXT Driver code. - * - * @addtogroup EXT - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_EXT == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief EXT Driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void extInit(void) { - - ext_lld_init(); -} - -/** - * @brief Initializes the standard part of a @p EXTDriver structure. - * - * @param[out] extp pointer to the @p EXTDriver object - * - * @init - */ -void extObjectInit(EXTDriver *extp) { - - extp->state = EXT_STOP; - extp->config = NULL; -} - -/** - * @brief Configures and activates the EXT peripheral. - * @post After activation all EXT channels are in the disabled state, - * use @p extChannelEnable() in order to activate them. - * - * @param[in] extp pointer to the @p EXTDriver object - * @param[in] config pointer to the @p EXTConfig object - * - * @api - */ -void extStart(EXTDriver *extp, const EXTConfig *config) { - - osalDbgCheck((extp != NULL) && (config != NULL)); - - osalSysLock(); - osalDbgAssert((extp->state == EXT_STOP) || (extp->state == EXT_ACTIVE), - "invalid state"); - extp->config = config; - ext_lld_start(extp); - extp->state = EXT_ACTIVE; - osalSysUnlock(); -} - -/** - * @brief Deactivates the EXT peripheral. - * - * @param[in] extp pointer to the @p EXTDriver object - * - * @api - */ -void extStop(EXTDriver *extp) { - - osalDbgCheck(extp != NULL); - - osalSysLock(); - osalDbgAssert((extp->state == EXT_STOP) || (extp->state == EXT_ACTIVE), - "invalid state"); - ext_lld_stop(extp); - extp->state = EXT_STOP; - osalSysUnlock(); -} - -/** - * @brief Enables an EXT channel. - * @pre The channel must not be in @p EXT_CH_MODE_DISABLED mode. - * - * @param[in] extp pointer to the @p EXTDriver object - * @param[in] channel channel to be enabled - * - * @api - */ -void extChannelEnable(EXTDriver *extp, expchannel_t channel) { - - osalDbgCheck((extp != NULL) && (channel < (expchannel_t)EXT_MAX_CHANNELS)); - - osalSysLock(); - osalDbgAssert((extp->state == EXT_ACTIVE) && - ((extp->config->channels[channel].mode & - EXT_CH_MODE_EDGES_MASK) != EXT_CH_MODE_DISABLED), - "invalid state"); - extChannelEnableI(extp, channel); - osalSysUnlock(); -} - -/** - * @brief Disables an EXT channel. - * @pre The channel must not be in @p EXT_CH_MODE_DISABLED mode. - * - * @param[in] extp pointer to the @p EXTDriver object - * @param[in] channel channel to be disabled - * - * @api - */ -void extChannelDisable(EXTDriver *extp, expchannel_t channel) { - - osalDbgCheck((extp != NULL) && (channel < (expchannel_t)EXT_MAX_CHANNELS)); - - osalSysLock(); - osalDbgAssert((extp->state == EXT_ACTIVE) && - ((extp->config->channels[channel].mode & - EXT_CH_MODE_EDGES_MASK) != EXT_CH_MODE_DISABLED), - "invalid state"); - extChannelDisableI(extp, channel); - osalSysUnlock(); -} - -/** - * @brief Changes the operation mode of a channel. - * @note This function attempts to write over the current configuration - * structure that must have been not declared constant. This - * violates the @p const qualifier in @p extStart() but it is - * intentional. - * @note This function cannot be used if the configuration structure is - * declared @p const. - * @note The effect of this function on constant configuration structures - * is not defined. - * - * @param[in] extp pointer to the @p EXTDriver object - * @param[in] channel channel to be changed - * @param[in] extcp new configuration for the channel - * - * @iclass - */ -void extSetChannelModeI(EXTDriver *extp, - expchannel_t channel, - const EXTChannelConfig *extcp) { - EXTChannelConfig *oldcp; - - osalDbgCheck((extp != NULL) && - (channel < (expchannel_t)EXT_MAX_CHANNELS) && - (extcp != NULL)); - - osalDbgAssert(extp->state == EXT_ACTIVE, "invalid state"); - - /* Note that here the access is enforced as non-const, known access - violation.*/ - /*lint -save -e9005 [11.8] Known issue, the driver needs rework here.*/ - oldcp = (EXTChannelConfig *)&extp->config->channels[channel]; - /*lint -restore*/ - - /* Overwriting the old channels configuration then the channel is - reconfigured by the low level driver.*/ - *oldcp = *extcp; - ext_lld_channel_enable(extp, channel); -} - -#endif /* HAL_USE_EXT == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/src/gpt.c b/firmware/ChibiOS_16/os/hal/src/gpt.c deleted file mode 100644 index fc76d190ef..0000000000 --- a/firmware/ChibiOS_16/os/hal/src/gpt.c +++ /dev/null @@ -1,262 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file gpt.c - * @brief GPT Driver code. - * - * @addtogroup GPT - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_GPT == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief GPT Driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void gptInit(void) { - - gpt_lld_init(); -} - -/** - * @brief Initializes the standard part of a @p GPTDriver structure. - * - * @param[out] gptp pointer to the @p GPTDriver object - * - * @init - */ -void gptObjectInit(GPTDriver *gptp) { - - gptp->state = GPT_STOP; - gptp->config = NULL; -} - -/** - * @brief Configures and activates the GPT peripheral. - * - * @param[in] gptp pointer to the @p GPTDriver object - * @param[in] config pointer to the @p GPTConfig object - * - * @api - */ -void gptStart(GPTDriver *gptp, const GPTConfig *config) { - - osalDbgCheck((gptp != NULL) && (config != NULL)); - - osalSysLock(); - osalDbgAssert((gptp->state == GPT_STOP) || (gptp->state == GPT_READY), - "invalid state"); - gptp->config = config; - gpt_lld_start(gptp); - gptp->state = GPT_READY; - osalSysUnlock(); -} - -/** - * @brief Deactivates the GPT peripheral. - * - * @param[in] gptp pointer to the @p GPTDriver object - * - * @api - */ -void gptStop(GPTDriver *gptp) { - - osalDbgCheck(gptp != NULL); - - osalSysLock(); - osalDbgAssert((gptp->state == GPT_STOP) || (gptp->state == GPT_READY), - "invalid state"); - gpt_lld_stop(gptp); - gptp->state = GPT_STOP; - osalSysUnlock(); -} - -/** - * @brief Changes the interval of GPT peripheral. - * @details This function changes the interval of a running GPT unit. - * @pre The GPT unit must be running in continuous mode. - * @post The GPT unit interval is changed to the new value. - * - * @param[in] gptp pointer to a @p GPTDriver object - * @param[in] interval new cycle time in timer ticks - * - * @api - */ -void gptChangeInterval(GPTDriver *gptp, gptcnt_t interval) { - - osalDbgCheck(gptp != NULL); - - osalSysLock(); - osalDbgAssert(gptp->state == GPT_CONTINUOUS, - "invalid state"); - gptChangeIntervalI(gptp, interval); - osalSysUnlock(); -} - -/** - * @brief Starts the timer in continuous mode. - * - * @param[in] gptp pointer to the @p GPTDriver object - * @param[in] interval period in ticks - * - * @api - */ -void gptStartContinuous(GPTDriver *gptp, gptcnt_t interval) { - - osalSysLock(); - gptStartContinuousI(gptp, interval); - osalSysUnlock(); -} - -/** - * @brief Starts the timer in continuous mode. - * - * @param[in] gptp pointer to the @p GPTDriver object - * @param[in] interval period in ticks - * - * @iclass - */ -void gptStartContinuousI(GPTDriver *gptp, gptcnt_t interval) { - - osalDbgCheckClassI(); - osalDbgCheck(gptp != NULL); - osalDbgAssert(gptp->state == GPT_READY, - "invalid state"); - - gptp->state = GPT_CONTINUOUS; - gpt_lld_start_timer(gptp, interval); -} - -/** - * @brief Starts the timer in one shot mode. - * - * @param[in] gptp pointer to the @p GPTDriver object - * @param[in] interval time interval in ticks - * - * @api - */ -void gptStartOneShot(GPTDriver *gptp, gptcnt_t interval) { - - osalSysLock(); - gptStartOneShotI(gptp, interval); - osalSysUnlock(); -} - -/** - * @brief Starts the timer in one shot mode. - * - * @param[in] gptp pointer to the @p GPTDriver object - * @param[in] interval time interval in ticks - * - * @api - */ -void gptStartOneShotI(GPTDriver *gptp, gptcnt_t interval) { - - osalDbgCheckClassI(); - osalDbgCheck(gptp != NULL); - osalDbgCheck(gptp->config->callback != NULL); - osalDbgAssert(gptp->state == GPT_READY, - "invalid state"); - - gptp->state = GPT_ONESHOT; - gpt_lld_start_timer(gptp, interval); -} - -/** - * @brief Stops the timer. - * - * @param[in] gptp pointer to the @p GPTDriver object - * - * @api - */ -void gptStopTimer(GPTDriver *gptp) { - - osalSysLock(); - gptStopTimerI(gptp); - osalSysUnlock(); -} - -/** - * @brief Stops the timer. - * - * @param[in] gptp pointer to the @p GPTDriver object - * - * @api - */ -void gptStopTimerI(GPTDriver *gptp) { - - osalDbgCheckClassI(); - osalDbgCheck(gptp != NULL); - osalDbgAssert((gptp->state == GPT_READY) || (gptp->state == GPT_CONTINUOUS) || - (gptp->state == GPT_ONESHOT), - "invalid state"); - - gptp->state = GPT_READY; - gpt_lld_stop_timer(gptp); -} - -/** - * @brief Starts the timer in one shot mode and waits for completion. - * @details This function specifically polls the timer waiting for completion - * in order to not have extra delays caused by interrupt servicing, - * this function is only recommended for short delays. - * @note The configured callback is not invoked when using this function. - * - * @param[in] gptp pointer to the @p GPTDriver object - * @param[in] interval time interval in ticks - * - * @api - */ -void gptPolledDelay(GPTDriver *gptp, gptcnt_t interval) { - - osalDbgAssert(gptp->state == GPT_READY, - "invalid state"); - - gptp->state = GPT_ONESHOT; - gpt_lld_polled_delay(gptp, interval); - gptp->state = GPT_READY; -} - -#endif /* HAL_USE_GPT == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/src/hal.c b/firmware/ChibiOS_16/os/hal/src/hal.c deleted file mode 100644 index 275c97f0dc..0000000000 --- a/firmware/ChibiOS_16/os/hal/src/hal.c +++ /dev/null @@ -1,144 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal.c - * @brief HAL subsystem code. - * - * @addtogroup HAL - * @{ - */ - -#include "hal.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief HAL initialization. - * @details This function invokes the low level initialization code then - * initializes all the drivers enabled in the HAL. Finally the - * board-specific initialization is performed by invoking - * @p boardInit() (usually defined in @p board.c). - * - * @init - */ -void halInit(void) { - - /* Initializes the OS Abstraction Layer.*/ - osalInit(); - - /* Platform low level initializations.*/ - hal_lld_init(); - -#if (HAL_USE_PAL == TRUE) || defined(__DOXYGEN__) - palInit(&pal_default_config); -#endif -#if (HAL_USE_ADC == TRUE) || defined(__DOXYGEN__) - adcInit(); -#endif -#if (HAL_USE_CAN == TRUE) || defined(__DOXYGEN__) - canInit(); -#endif -#if (HAL_USE_DAC == TRUE) || defined(__DOXYGEN__) - dacInit(); -#endif -#if (HAL_USE_EXT == TRUE) || defined(__DOXYGEN__) - extInit(); -#endif -#if (HAL_USE_GPT == TRUE) || defined(__DOXYGEN__) - gptInit(); -#endif -#if (HAL_USE_I2C == TRUE) || defined(__DOXYGEN__) - i2cInit(); -#endif -#if (HAL_USE_I2S == TRUE) || defined(__DOXYGEN__) - i2sInit(); -#endif -#if (HAL_USE_ICU == TRUE) || defined(__DOXYGEN__) - icuInit(); -#endif -#if (HAL_USE_MAC == TRUE) || defined(__DOXYGEN__) - macInit(); -#endif -#if (HAL_USE_PWM == TRUE) || defined(__DOXYGEN__) - pwmInit(); -#endif -#if (HAL_USE_SERIAL == TRUE) || defined(__DOXYGEN__) - sdInit(); -#endif -#if (HAL_USE_SDC == TRUE) || defined(__DOXYGEN__) - sdcInit(); -#endif -#if (HAL_USE_SPI == TRUE) || defined(__DOXYGEN__) - spiInit(); -#endif -#if (HAL_USE_UART == TRUE) || defined(__DOXYGEN__) - uartInit(); -#endif -#if (HAL_USE_USB == TRUE) || defined(__DOXYGEN__) - usbInit(); -#endif -#if (HAL_USE_MMC_SPI == TRUE) || defined(__DOXYGEN__) - mmcInit(); -#endif -#if (HAL_USE_SERIAL_USB == TRUE) || defined(__DOXYGEN__) - sduInit(); -#endif -#if (HAL_USE_RTC == TRUE) || defined(__DOXYGEN__) - rtcInit(); -#endif -#if (HAL_USE_WDG == TRUE) || defined(__DOXYGEN__) - wdgInit(); -#endif - - /* Community driver overlay initialization.*/ -#if defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) -#if (HAL_USE_COMMUNITY == TRUE) || defined(__DOXYGEN__) - halCommunityInit(); -#endif -#endif - - /* Board specific initialization.*/ - boardInit(); - -/* - * The ST driver is a special case, it is only initialized if the OSAL is - * configured to require it. - */ -#if OSAL_ST_MODE != OSAL_ST_MODE_NONE - stInit(); -#endif -} - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/src/hal_buffers.c b/firmware/ChibiOS_16/os/hal/src/hal_buffers.c deleted file mode 100644 index 0b8d70709f..0000000000 --- a/firmware/ChibiOS_16/os/hal/src/hal_buffers.c +++ /dev/null @@ -1,867 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_buffers.c - * @brief I/O Buffers code. - * - * @addtogroup HAL_BUFFERS - * @details Buffers Queues are used when there is the need to exchange - * fixed-length data buffers between ISRs and threads. - * On the ISR side data can be exchanged only using buffers, - * on the thread side data can be exchanged both using buffers and/or - * using an emulation of regular byte queues. - * There are several kind of buffers queues:
- * - Input queue, unidirectional queue where the writer is the - * ISR side and the reader is the thread side. - * - Output queue, unidirectional queue where the writer is the - * ISR side and the reader is the thread side. - * - Full duplex queue, bidirectional queue. Full duplex queues - * are implemented by pairing an input queue and an output queue - * together. - * . - * @{ - */ - -#include - -#include "hal.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Initializes an input buffers queue object. - * - * @param[out] ibqp pointer to the @p input_buffers_queue_t object - * @param[in] bp pointer to a memory area allocated for buffers - * @param[in] size buffers size - * @param[in] n number of buffers - * @param[in] infy callback called when a buffer is returned to the queue - * @param[in] link application defined pointer - * - * @init - */ -void ibqObjectInit(input_buffers_queue_t *ibqp, uint8_t *bp, - size_t size, size_t n, - bqnotify_t infy, void *link) { - - osalDbgCheck((ibqp != NULL) && (bp != NULL) && (size >= 2U)); - - osalThreadQueueObjectInit(&ibqp->waiting); - ibqp->bcounter = 0; - ibqp->brdptr = bp; - ibqp->bwrptr = bp; - ibqp->btop = bp + ((size + sizeof (size_t)) * n); - ibqp->bsize = size + sizeof (size_t); - ibqp->bn = n; - ibqp->buffers = bp; - ibqp->ptr = NULL; - ibqp->top = NULL; - ibqp->notify = infy; - ibqp->link = link; -} - -/** - * @brief Resets an input buffers queue. - * @details All the data in the input buffers queue is erased and lost, any - * waiting thread is resumed with status @p MSG_RESET. - * @note A reset operation can be used by a low level driver in order to - * obtain immediate attention from the high level layers. - * - * @param[in] ibqp pointer to the @p input_buffers_queue_t object - * - * @iclass - */ -void ibqResetI(input_buffers_queue_t *ibqp) { - - osalDbgCheckClassI(); - - ibqp->bcounter = 0; - ibqp->brdptr = ibqp->buffers; - ibqp->bwrptr = ibqp->buffers; - ibqp->ptr = NULL; - ibqp->top = NULL; - osalThreadDequeueAllI(&ibqp->waiting, MSG_RESET); -} - -/** - * @brief Gets the next empty buffer from the queue. - * @note The function always returns the same buffer if called repeatedly. - * - * @param[in] ibqp pointer to the @p input_buffers_queue_t object - * @return A pointer to the next buffer to be filled. - * @retval NULL if the queue is full. - * - * @iclass - */ -uint8_t *ibqGetEmptyBufferI(input_buffers_queue_t *ibqp) { - - osalDbgCheckClassI(); - - if (ibqIsFullI(ibqp)) { - return NULL; - } - - return ibqp->bwrptr + sizeof (size_t); -} - -/** - * @brief Posts a new filled buffer to the queue. - * - * @param[in] ibqp pointer to the @p input_buffers_queue_t object - * @param[in] size used size of the buffer, cannot be zero - * - * @iclass - */ -void ibqPostFullBufferI(input_buffers_queue_t *ibqp, size_t size) { - - osalDbgCheckClassI(); - - osalDbgCheck((size > 0U) && (size <= (ibqp->bsize - sizeof (size_t)))); - osalDbgAssert(!ibqIsFullI(ibqp), "buffers queue full"); - - /* Writing size field in the buffer.*/ - *((size_t *)ibqp->bwrptr) = size; - - /* Posting the buffer in the queue.*/ - ibqp->bcounter++; - ibqp->bwrptr += ibqp->bsize; - if (ibqp->bwrptr >= ibqp->btop) { - ibqp->bwrptr = ibqp->buffers; - } - - /* Waking up one waiting thread, if any.*/ - osalThreadDequeueNextI(&ibqp->waiting, MSG_OK); -} - -/** - * @brief Gets the next filled buffer from the queue. - * @note The function always acquires the same buffer if called repeatedly. - * @post After calling the function the fields @p ptr and @p top are set - * at beginning and end of the buffer data or @p NULL if the queue - * is empty. - * - * @param[in] ibqp pointer to the @p input_buffers_queue_t object - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval MSG_OK if a buffer has been acquired. - * @retval MSG_TIMEOUT if the specified time expired. - * @retval MSG_RESET if the queue has been reset. - * - * @api - */ -msg_t ibqGetFullBufferTimeout(input_buffers_queue_t *ibqp, - systime_t timeout) { - msg_t msg; - - osalSysLock(); - msg = ibqGetFullBufferTimeoutS(ibqp, timeout); - osalSysUnlock(); - - return msg; -} - - /** - * @brief Gets the next filled buffer from the queue. - * @note The function always acquires the same buffer if called repeatedly. - * @post After calling the function the fields @p ptr and @p top are set - * at beginning and end of the buffer data or @p NULL if the queue - * is empty. - * - * @param[in] ibqp pointer to the @p input_buffers_queue_t object - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval MSG_OK if a buffer has been acquired. - * @retval MSG_TIMEOUT if the specified time expired. - * @retval MSG_RESET if the queue has been reset. - * - * @sclass - */ - msg_t ibqGetFullBufferTimeoutS(input_buffers_queue_t *ibqp, - systime_t timeout) { - - osalDbgCheckClassS(); - - while (ibqIsEmptyI(ibqp)) { - msg_t msg = osalThreadEnqueueTimeoutS(&ibqp->waiting, timeout); - if (msg < MSG_OK) { - return msg; - } - } - - osalDbgAssert(!ibqIsEmptyI(ibqp), "still empty"); - - /* Setting up the "current" buffer and its boundary.*/ - ibqp->ptr = ibqp->brdptr + sizeof (size_t); - ibqp->top = ibqp->ptr + *((size_t *)ibqp->brdptr); - - return MSG_OK; -} - -/** - * @brief Releases the buffer back in the queue. - * @note The object callback is called after releasing the buffer. - * - * @param[in] ibqp pointer to the @p input_buffers_queue_t object - * - * @api - */ -void ibqReleaseEmptyBuffer(input_buffers_queue_t *ibqp) { - - osalSysLock(); - ibqReleaseEmptyBufferS(ibqp); - osalSysUnlock(); -} - - /** - * @brief Releases the buffer back in the queue. - * @note The object callback is called after releasing the buffer. - * - * @param[in] ibqp pointer to the @p input_buffers_queue_t object - * - * @sclass - */ - void ibqReleaseEmptyBufferS(input_buffers_queue_t *ibqp) { - - osalDbgCheckClassS(); - osalDbgAssert(!ibqIsEmptyI(ibqp), "buffers queue empty"); - - /* Freeing a buffer slot in the queue.*/ - ibqp->bcounter--; - ibqp->brdptr += ibqp->bsize; - if (ibqp->brdptr >= ibqp->btop) { - ibqp->brdptr = ibqp->buffers; - } - - /* No "current" buffer.*/ - ibqp->ptr = NULL; - - /* Notifying the buffer release.*/ - if (ibqp->notify != NULL) { - ibqp->notify(ibqp); - } -} - -/** - * @brief Input queue read with timeout. - * @details This function reads a byte value from an input queue. If - * the queue is empty then the calling thread is suspended until a - * new buffer arrives in the queue or a timeout occurs. - * - * @param[in] ibqp pointer to the @p input_buffers_queue_t object - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return A byte value from the queue. - * @retval MSG_TIMEOUT if the specified time expired. - * @retval MSG_RESET if the queue has been reset. - * - * @api - */ -msg_t ibqGetTimeout(input_buffers_queue_t *ibqp, systime_t timeout) { - msg_t msg; - - osalSysLock(); - - /* This condition indicates that a new buffer must be acquired.*/ - if (ibqp->ptr == NULL) { - msg = ibqGetFullBufferTimeoutS(ibqp, timeout); - if (msg != MSG_OK) { - osalSysUnlock(); - return msg; - } - } - - /* Next byte from the buffer.*/ - msg = (msg_t)*ibqp->ptr; - ibqp->ptr++; - - /* If the current buffer has been fully read then it is returned as - empty in the queue.*/ - if (ibqp->ptr >= ibqp->top) { - ibqReleaseEmptyBufferS(ibqp); - } - - osalSysUnlock(); - return msg; -} - -/** - * @brief Input queue read with timeout. - * @details The function reads data from an input queue into a buffer. - * The operation completes when the specified amount of data has been - * transferred or after the specified timeout or if the queue has - * been reset. - * - * @param[in] ibqp pointer to the @p input_buffers_queue_t object - * @param[out] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred, the - * value 0 is reserved - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The number of bytes effectively transferred. - * @retval 0 if a timeout occurred. - * - * @api - */ -size_t ibqReadTimeout(input_buffers_queue_t *ibqp, uint8_t *bp, - size_t n, systime_t timeout) { - size_t r = 0; - systime_t deadline; - - osalSysLock(); - - /* Time window for the whole operation.*/ - deadline = osalOsGetSystemTimeX() + timeout; - - while (true) { - size_t size; - - /* This condition indicates that a new buffer must be acquired.*/ - if (ibqp->ptr == NULL) { - msg_t msg; - - /* TIME_INFINITE and TIME_IMMEDIATE are handled differently, no - deadline.*/ - if ((timeout == TIME_INFINITE) || (timeout == TIME_IMMEDIATE)) { - msg = ibqGetFullBufferTimeoutS(ibqp, timeout); - } - else { - systime_t next_timeout = deadline - osalOsGetSystemTimeX(); - - /* Handling the case where the system time went past the deadline, - in this case next becomes a very high number because the system - time is an unsigned type.*/ - if (next_timeout > timeout) { - osalSysUnlock(); - return r; - } - msg = ibqGetFullBufferTimeoutS(ibqp, next_timeout); - } - - /* Anything except MSG_OK interrupts the operation.*/ - if (msg != MSG_OK) { - osalSysUnlock(); - return r; - } - } - - /* Size of the data chunk present in the current buffer.*/ - size = (size_t)ibqp->top - (size_t)ibqp->ptr; - if (size > (n - r)) { - size = n - r; - } - - /* Smaller chunks in order to not make the critical zone too long, - this impacts throughput however.*/ - if (size > 64U) { - /* Giving the compiler a chance to optimize for a fixed size move.*/ - memcpy(bp, ibqp->ptr, 64U); - bp += 64U; - ibqp->ptr += 64U; - r += 64U; - } - else { - memcpy(bp, ibqp->ptr, size); - bp += size; - ibqp->ptr += size; - r += size; - } - - /* Has the current data buffer been finished? if so then release it.*/ - if (ibqp->ptr >= ibqp->top) { - ibqReleaseEmptyBufferS(ibqp); - } - - /* Giving a preemption chance.*/ - osalSysUnlock(); - if (r >= n) { - return r; - } - osalSysLock(); - } -} - -/** - * @brief Initializes an output buffers queue object. - * - * @param[out] obqp pointer to the @p output_buffers_queue_t object - * @param[in] bp pointer to a memory area allocated for buffers - * @param[in] size buffers size - * @param[in] n number of buffers - * @param[in] onfy callback called when a buffer is posted in the queue - * @param[in] link application defined pointer - * - * @init - */ -void obqObjectInit(output_buffers_queue_t *obqp, uint8_t *bp, - size_t size, size_t n, - bqnotify_t onfy, void *link) { - - osalDbgCheck((obqp != NULL) && (bp != NULL) && (size >= 2U)); - - osalThreadQueueObjectInit(&obqp->waiting); - obqp->bcounter = n; - obqp->brdptr = bp; - obqp->bwrptr = bp; - obqp->btop = bp + ((size + sizeof (size_t)) * n); - obqp->bsize = size + sizeof (size_t); - obqp->bn = n; - obqp->buffers = bp; - obqp->ptr = NULL; - obqp->top = NULL; - obqp->notify = onfy; - obqp->link = link; -} - -/** - * @brief Resets an output buffers queue. - * @details All the data in the output buffers queue is erased and lost, any - * waiting thread is resumed with status @p MSG_RESET. - * @note A reset operation can be used by a low level driver in order to - * obtain immediate attention from the high level layers. - * - * @param[in] obqp pointer to the @p output_buffers_queue_t object - * - * @iclass - */ -void obqResetI(output_buffers_queue_t *obqp) { - - osalDbgCheckClassI(); - - obqp->bcounter = bqSizeX(obqp); - obqp->brdptr = obqp->buffers; - obqp->bwrptr = obqp->buffers; - obqp->ptr = NULL; - obqp->top = NULL; - osalThreadDequeueAllI(&obqp->waiting, MSG_RESET); -} - -/** - * @brief Gets the next filled buffer from the queue. - * @note The function always returns the same buffer if called repeatedly. - * - * @param[in] obqp pointer to the @p output_buffers_queue_t object - * @param[out] sizep pointer to the filled buffer size - * @return A pointer to the filled buffer. - * @retval NULL if the queue is empty. - * - * @iclass - */ -uint8_t *obqGetFullBufferI(output_buffers_queue_t *obqp, - size_t *sizep) { - - osalDbgCheckClassI(); - - if (obqIsEmptyI(obqp)) { - return NULL; - } - - /* Buffer size.*/ - *sizep = *((size_t *)obqp->brdptr); - - return obqp->brdptr + sizeof (size_t); -} - -/** - * @brief Releases the next filled buffer back in the queue. - * - * @param[in] obqp pointer to the @p output_buffers_queue_t object - * - * @iclass - */ -void obqReleaseEmptyBufferI(output_buffers_queue_t *obqp) { - - osalDbgCheckClassI(); - osalDbgAssert(!obqIsEmptyI(obqp), "buffers queue empty"); - - /* Freeing a buffer slot in the queue.*/ - obqp->bcounter++; - obqp->brdptr += obqp->bsize; - if (obqp->brdptr >= obqp->btop) { - obqp->brdptr = obqp->buffers; - } - - /* Waking up one waiting thread, if any.*/ - osalThreadDequeueNextI(&obqp->waiting, MSG_OK); -} - -/** - * @brief Gets the next empty buffer from the queue. - * @note The function always acquires the same buffer if called repeatedly. - * @post After calling the function the fields @p ptr and @p top are set - * at beginning and end of the buffer data or @p NULL if the queue - * is empty. - * - * @param[in] obqp pointer to the @p output_buffers_queue_t object - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval MSG_OK if a buffer has been acquired. - * @retval MSG_TIMEOUT if the specified time expired. - * @retval MSG_RESET if the queue has been reset. - * - * @api - */ -msg_t obqGetEmptyBufferTimeout(output_buffers_queue_t *obqp, - systime_t timeout) { - msg_t msg; - - osalSysLock(); - msg = obqGetEmptyBufferTimeoutS(obqp, timeout); - osalSysUnlock(); - - return msg; -} - - /** - * @brief Gets the next empty buffer from the queue. - * @note The function always acquires the same buffer if called repeatedly. - * @post After calling the function the fields @p ptr and @p top are set - * at beginning and end of the buffer data or @p NULL if the queue - * is empty. - * - * @param[in] obqp pointer to the @p output_buffers_queue_t object - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval MSG_OK if a buffer has been acquired. - * @retval MSG_TIMEOUT if the specified time expired. - * @retval MSG_RESET if the queue has been reset. - * - * @sclass - */ - msg_t obqGetEmptyBufferTimeoutS(output_buffers_queue_t *obqp, - systime_t timeout) { - - osalDbgCheckClassS(); - - while (obqIsFullI(obqp)) { - msg_t msg = osalThreadEnqueueTimeoutS(&obqp->waiting, timeout); - if (msg < MSG_OK) { - return msg; - } - } - - osalDbgAssert(!obqIsFullI(obqp), "still full"); - - /* Setting up the "current" buffer and its boundary.*/ - obqp->ptr = obqp->bwrptr + sizeof (size_t); - obqp->top = obqp->bwrptr + obqp->bsize; - - return MSG_OK; -} - -/** - * @brief Posts a new filled buffer to the queue. - * @note The object callback is called after releasing the buffer. - * - * @param[in] obqp pointer to the @p output_buffers_queue_t object - * @param[in] size used size of the buffer, cannot be zero - * - * @api - */ -void obqPostFullBuffer(output_buffers_queue_t *obqp, size_t size) { - - osalSysLock(); - obqPostFullBufferS(obqp, size); - osalSysUnlock(); -} - -/** - * @brief Posts a new filled buffer to the queue. - * @note The object callback is called after releasing the buffer. - * - * @param[in] obqp pointer to the @p output_buffers_queue_t object - * @param[in] size used size of the buffer, cannot be zero - * - * @sclass - */ -void obqPostFullBufferS(output_buffers_queue_t *obqp, size_t size) { - - osalDbgCheckClassS(); - osalDbgCheck((size > 0U) && (size <= (obqp->bsize - sizeof (size_t)))); - osalDbgAssert(!obqIsFullI(obqp), "buffers queue full"); - - /* Writing size field in the buffer.*/ - *((size_t *)obqp->bwrptr) = size; - - /* Posting the buffer in the queue.*/ - obqp->bcounter--; - obqp->bwrptr += obqp->bsize; - if (obqp->bwrptr >= obqp->btop) { - obqp->bwrptr = obqp->buffers; - } - - /* No "current" buffer.*/ - obqp->ptr = NULL; - - /* Notifying the buffer release.*/ - if (obqp->notify != NULL) { - obqp->notify(obqp); - } -} - -/** - * @brief Output queue write with timeout. - * @details This function writes a byte value to an output queue. If - * the queue is full then the calling thread is suspended until a - * new buffer is freed in the queue or a timeout occurs. - * - * @param[in] obqp pointer to the @p output_buffers_queue_t object - * @param[in] b byte value to be transferred - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return A byte value from the queue. - * @retval MSG_TIMEOUT if the specified time expired. - * @retval MSG_RESET if the queue has been reset. - * - * @api - */ -msg_t obqPutTimeout(output_buffers_queue_t *obqp, uint8_t b, - systime_t timeout) { - msg_t msg; - - osalSysLock(); - - /* This condition indicates that a new buffer must be acquired.*/ - if (obqp->ptr == NULL) { - msg = obqGetEmptyBufferTimeoutS(obqp, timeout); - if (msg != MSG_OK) { - osalSysUnlock(); - return msg; - } - } - - /* Writing the byte to the buffer.*/ - *obqp->ptr = b; - obqp->ptr++; - - /* If the current buffer has been fully written then it is posted as - full in the queue.*/ - if (obqp->ptr >= obqp->top) { - obqPostFullBufferS(obqp, obqp->bsize - sizeof (size_t)); - } - - osalSysUnlock(); - return MSG_OK; -} - -/** - * @brief Output queue write with timeout. - * @details The function writes data from a buffer to an output queue. The - * operation completes when the specified amount of data has been - * transferred or after the specified timeout or if the queue has - * been reset. - * - * @param[in] obqp pointer to the @p output_buffers_queue_t object - * @param[in] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred, the - * value 0 is reserved - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The number of bytes effectively transferred. - * @retval 0 if a timeout occurred. - * - * @api - */ -size_t obqWriteTimeout(output_buffers_queue_t *obqp, const uint8_t *bp, - size_t n, systime_t timeout) { - size_t w = 0; - systime_t deadline; - - osalSysLock(); - - /* Time window for the whole operation.*/ - deadline = osalOsGetSystemTimeX() + timeout; - - while (true) { - size_t size; - - /* This condition indicates that a new buffer must be acquired.*/ - if (obqp->ptr == NULL) { - msg_t msg; - - /* TIME_INFINITE and TIME_IMMEDIATE are handled differently, no - deadline.*/ - if ((timeout == TIME_INFINITE) || (timeout == TIME_IMMEDIATE)) { - msg = obqGetEmptyBufferTimeoutS(obqp, timeout); - } - else { - systime_t next_timeout = deadline - osalOsGetSystemTimeX(); - - /* Handling the case where the system time went past the deadline, - in this case next becomes a very high number because the system - time is an unsigned type.*/ - if (next_timeout > timeout) { - osalSysUnlock(); - return w; - } - msg = obqGetEmptyBufferTimeoutS(obqp, next_timeout); - } - - /* Anything except MSG_OK interrupts the operation.*/ - if (msg != MSG_OK) { - osalSysUnlock(); - return w; - } - } - - /* Size of the space available in the current buffer.*/ - size = (size_t)obqp->top - (size_t)obqp->ptr; - if (size > (n - w)) { - size = n - w; - } - - /* Smaller chunks in order to not make the critical zone too long, - this impacts throughput however.*/ - if (size > 64U) { - /* Giving the compiler a chance to optimize for a fixed size move.*/ - memcpy(obqp->ptr, bp, 64U); - bp += 64U; - obqp->ptr += 64U; - w += 64U; - } - else { - memcpy(obqp->ptr, bp, size); - bp += size; - obqp->ptr += size; - w += size; - } - - /* Has the current data buffer been finished? if so then release it.*/ - if (obqp->ptr >= obqp->top) { - obqPostFullBufferS(obqp, obqp->bsize - sizeof (size_t)); - } - - /* Giving a preemption chance.*/ - osalSysUnlock(); - if (w >= n) { - return w; - } - osalSysLock(); - } -} - -/** - * @brief Flushes the current, partially filled, buffer to the queue. - * @note The notification callback is not invoked because the function - * is meant to be called from ISR context. An operation status is - * returned instead. - * - * @param[in] obqp pointer to the @p output_buffers_queue_t object - * @return The operation status. - * @retval false if no new filled buffer has been posted to the queue. - * @retval true if a new filled buffer has been posted to the queue. - * - * @iclass - */ -bool obqTryFlushI(output_buffers_queue_t *obqp) { - - osalDbgCheckClassI(); - - /* If queue is empty and there is a buffer partially filled and - it is not being written.*/ - if (obqIsEmptyI(obqp) && (obqp->ptr != NULL)) { - size_t size = (size_t)obqp->ptr - ((size_t)obqp->bwrptr + sizeof (size_t)); - - if (size > 0U) { - - /* Writing size field in the buffer.*/ - *((size_t *)obqp->bwrptr) = size; - - /* Posting the buffer in the queue.*/ - obqp->bcounter--; - obqp->bwrptr += obqp->bsize; - if (obqp->bwrptr >= obqp->btop) { - obqp->bwrptr = obqp->buffers; - } - - /* No "current" buffer.*/ - obqp->ptr = NULL; - - return true; - } - } - return false; -} - -/** - * @brief Flushes the current, partially filled, buffer to the queue. - * - * @param[in] obqp pointer to the @p output_buffers_queue_t object - * - * @api - */ -void obqFlush(output_buffers_queue_t *obqp) { - - osalSysLock(); - - /* If there is a buffer partially filled and not being written.*/ - if (obqp->ptr != NULL) { - size_t size = (size_t)obqp->ptr - (size_t)obqp->bwrptr - sizeof (size_t); - - if (size > 0U) { - obqPostFullBufferS(obqp, size); - } - } - - osalSysUnlock(); -} -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/src/hal_mmcsd.c b/firmware/ChibiOS_16/os/hal/src/hal_mmcsd.c deleted file mode 100644 index 508e9ac1c8..0000000000 --- a/firmware/ChibiOS_16/os/hal/src/hal_mmcsd.c +++ /dev/null @@ -1,331 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_mmcsd.c - * @brief MMC/SD cards common code. - * - * @addtogroup MMCSD - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_MMC_SPI == TRUE) || (HAL_USE_SDC == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Gets a bit field from a words array. - * @note The bit zero is the LSb of the first word. - * - * @param[in] data pointer to the words array - * @param[in] end bit offset of the last bit of the field, inclusive - * @param[in] start bit offset of the first bit of the field, inclusive - * - * @return The bits field value, left aligned. - * - * @notapi - */ -uint32_t _mmcsd_get_slice(const uint32_t *data, - uint32_t end, - uint32_t start) { - unsigned startidx, endidx, startoff; - uint32_t endmask; - - osalDbgCheck((end >= start) && ((end - start) < 32U)); - - startidx = start / 32U; - startoff = start % 32U; - endidx = end / 32U; - endmask = ((uint32_t)1U << ((end % 32U) + 1U)) - 1U; - - /* One or two pieces?*/ - if (startidx < endidx) { - return (data[startidx] >> startoff) | /* Two pieces case. */ - ((data[endidx] & endmask) << (32U - startoff)); - } - return (data[startidx] & endmask) >> startoff; /* One piece case. */ -} - -/** - * @brief Extract card capacity from a CSD. - * @details The capacity is returned as number of available blocks. - * - * @param[in] csd the CSD record - * - * @return The card capacity. - * @retval 0 CSD format error - * - * @notapi - */ -uint32_t _mmcsd_get_capacity(const uint32_t *csd) { - uint32_t a, b, c; - - osalDbgCheck(NULL != csd); - - switch (_mmcsd_get_slice(csd, MMCSD_CSD_10_CSD_STRUCTURE_SLICE)) { - case 0: - /* CSD version 1.0 */ - a = _mmcsd_get_slice(csd, MMCSD_CSD_10_C_SIZE_SLICE); - b = _mmcsd_get_slice(csd, MMCSD_CSD_10_C_SIZE_MULT_SLICE); - c = _mmcsd_get_slice(csd, MMCSD_CSD_10_READ_BL_LEN_SLICE); - return ((a + 1U) << (b + 2U)) << (c - 9U); /* 2^9 == MMCSD_BLOCK_SIZE. */ - case 1: - /* CSD version 2.0.*/ - return 1024U * (_mmcsd_get_slice(csd, MMCSD_CSD_20_C_SIZE_SLICE) + 1U); - default: - /* Reserved value detected.*/ - break; - } - return 0U; -} - -/** - * @brief Extract MMC card capacity from EXT_CSD. - * @details The capacity is returned as number of available blocks. - * - * @param[in] ext_csd the extended CSD record - * - * @return The card capacity. - * - * @notapi - */ -uint32_t _mmcsd_get_capacity_ext(const uint8_t *ext_csd) { - - osalDbgCheck(NULL != ext_csd); - - return ((uint32_t)ext_csd[215] << 24U) + - ((uint32_t)ext_csd[214] << 16U) + - ((uint32_t)ext_csd[213] << 8U) + - (uint32_t)ext_csd[212]; -} - -/** - * @brief Unpacks SDC CID array in structure. - * - * @param[in] sdcp pointer to the @p MMCSDBlockDevice object - * @param[out] cidsdc pointer to the @p unpacked_sdc_cid_t object - * - * @notapi - */ -void _mmcsd_unpack_sdc_cid(const MMCSDBlockDevice *sdcp, - unpacked_sdc_cid_t *cidsdc) { - const uint32_t *cid; - - osalDbgCheck((NULL != sdcp) && (NULL != cidsdc)); - - cid = sdcp->cid; - cidsdc->crc = (uint8_t) _mmcsd_get_slice(cid, MMCSD_CID_SDC_CRC_SLICE); - cidsdc->mdt_y = (uint16_t)_mmcsd_get_slice(cid, MMCSD_CID_SDC_MDT_Y_SLICE) + - 2000U; - cidsdc->mdt_m = (uint8_t) _mmcsd_get_slice(cid, MMCSD_CID_SDC_MDT_M_SLICE); - cidsdc->mid = (uint8_t) _mmcsd_get_slice(cid, MMCSD_CID_SDC_MID_SLICE); - cidsdc->oid = (uint16_t)_mmcsd_get_slice(cid, MMCSD_CID_SDC_OID_SLICE); - cidsdc->pnm[4] = (char) _mmcsd_get_slice(cid, MMCSD_CID_SDC_PNM0_SLICE); - cidsdc->pnm[3] = (char) _mmcsd_get_slice(cid, MMCSD_CID_SDC_PNM1_SLICE); - cidsdc->pnm[2] = (char) _mmcsd_get_slice(cid, MMCSD_CID_SDC_PNM2_SLICE); - cidsdc->pnm[1] = (char) _mmcsd_get_slice(cid, MMCSD_CID_SDC_PNM3_SLICE); - cidsdc->pnm[0] = (char) _mmcsd_get_slice(cid, MMCSD_CID_SDC_PNM4_SLICE); - cidsdc->prv_n = (uint8_t) _mmcsd_get_slice(cid, MMCSD_CID_SDC_PRV_N_SLICE); - cidsdc->prv_m = (uint8_t) _mmcsd_get_slice(cid, MMCSD_CID_SDC_PRV_M_SLICE); - cidsdc->psn = _mmcsd_get_slice(cid, MMCSD_CID_SDC_PSN_SLICE); -} - -/** - * @brief Unpacks MMC CID array in structure. - * - * @param[in] sdcp pointer to the @p MMCSDBlockDevice object - * @param[out] cidmmc pointer to the @p unpacked_mmc_cid_t object - * - * @notapi - */ -void _mmcsd_unpack_mmc_cid(const MMCSDBlockDevice *sdcp, - unpacked_mmc_cid_t *cidmmc) { - const uint32_t *cid; - - osalDbgCheck((NULL != sdcp) && (NULL != cidmmc)); - - cid = sdcp->cid; - cidmmc->crc = (uint8_t) _mmcsd_get_slice(cid, MMCSD_CID_MMC_CRC_SLICE); - cidmmc->mdt_y = (uint16_t)_mmcsd_get_slice(cid, MMCSD_CID_MMC_MDT_Y_SLICE) + - 1997U; - cidmmc->mdt_m = (uint8_t) _mmcsd_get_slice(cid, MMCSD_CID_MMC_MDT_M_SLICE); - cidmmc->mid = (uint8_t) _mmcsd_get_slice(cid, MMCSD_CID_MMC_MID_SLICE); - cidmmc->oid = (uint16_t)_mmcsd_get_slice(cid, MMCSD_CID_MMC_OID_SLICE); - cidmmc->pnm[5] = (char) _mmcsd_get_slice(cid, MMCSD_CID_MMC_PNM0_SLICE); - cidmmc->pnm[4] = (char) _mmcsd_get_slice(cid, MMCSD_CID_MMC_PNM1_SLICE); - cidmmc->pnm[3] = (char) _mmcsd_get_slice(cid, MMCSD_CID_MMC_PNM2_SLICE); - cidmmc->pnm[2] = (char) _mmcsd_get_slice(cid, MMCSD_CID_MMC_PNM3_SLICE); - cidmmc->pnm[1] = (char) _mmcsd_get_slice(cid, MMCSD_CID_MMC_PNM4_SLICE); - cidmmc->pnm[0] = (char) _mmcsd_get_slice(cid, MMCSD_CID_MMC_PNM5_SLICE); - cidmmc->prv_n = (uint8_t) _mmcsd_get_slice(cid, MMCSD_CID_MMC_PRV_N_SLICE); - cidmmc->prv_m = (uint8_t) _mmcsd_get_slice(cid, MMCSD_CID_MMC_PRV_M_SLICE); - cidmmc->psn = _mmcsd_get_slice(cid, MMCSD_CID_MMC_PSN_SLICE); -} - -/** - * @brief Unpacks MMC CSD array in structure. - * - * @param[in] sdcp pointer to the @p MMCSDBlockDevice object - * @param[out] csdmmc pointer to the @p unpacked_mmc_csd_t object - * - * @notapi - */ -void _mmcsd_unpack_csd_mmc(const MMCSDBlockDevice *sdcp, - unpacked_mmc_csd_t *csdmmc) { - const uint32_t *csd; - - osalDbgCheck((NULL != sdcp) && (NULL != csdmmc)); - - csd = sdcp->csd; - csdmmc->c_size = (uint16_t)_mmcsd_get_slice(csd, MMCSD_CSD_MMC_C_SIZE_SLICE); - csdmmc->c_size_mult = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_C_SIZE_MULT_SLICE); - csdmmc->ccc = (uint16_t)_mmcsd_get_slice(csd, MMCSD_CSD_MMC_CCC_SLICE); - csdmmc->copy = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_COPY_SLICE); - csdmmc->crc = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_CRC_SLICE); - csdmmc->csd_structure = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_CSD_STRUCTURE_SLICE); - csdmmc->dsr_imp = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_DSR_IMP_SLICE); - csdmmc->ecc = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_ECC_SLICE); - csdmmc->erase_grp_mult = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_ERASE_GRP_MULT_SLICE); - csdmmc->erase_grp_size = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_ERASE_GRP_SIZE_SLICE); - csdmmc->file_format = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_FILE_FORMAT_SLICE); - csdmmc->file_format_grp = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_FILE_FORMAT_GRP_SLICE); - csdmmc->nsac = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_NSAC_SLICE); - csdmmc->perm_write_protect = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_PERM_WRITE_PROTECT_SLICE); - csdmmc->r2w_factor = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_R2W_FACTOR_SLICE); - csdmmc->read_bl_len = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_READ_BL_LEN_SLICE); - csdmmc->read_bl_partial = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_READ_BL_PARTIAL_SLICE); - csdmmc->read_blk_misalign = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_READ_BLK_MISALIGN_SLICE); - csdmmc->spec_vers = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_SPEC_VERS_SLICE); - csdmmc->taac = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_TAAC_SLICE); - csdmmc->tmp_write_protect = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_TMP_WRITE_PROTECT_SLICE); - csdmmc->tran_speed = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_TRAN_SPEED_SLICE); - csdmmc->vdd_r_curr_max = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_VDD_R_CURR_MAX_SLICE); - csdmmc->vdd_r_curr_min = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_VDD_R_CURR_MIN_SLICE); - csdmmc->vdd_w_curr_max = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_VDD_W_CURR_MAX_SLICE); - csdmmc->vdd_w_curr_min = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_VDD_W_CURR_MIN_SLICE); - csdmmc->wp_grp_enable = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_WP_GRP_ENABLE_SLICE); - csdmmc->wp_grp_size = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_WP_GRP_SIZE_SLICE); - csdmmc->write_bl_len = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_WRITE_BL_LEN_SLICE); - csdmmc->write_bl_partial = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_WRITE_BL_PARTIAL_SLICE); - csdmmc->write_blk_misalign = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_MMC_WRITE_BLK_MISALIGN_SLICE); -} - -/** - * @brief Unpacks SDC CSD v1.0 array in structure. - * - * @param[in] sdcp pointer to the @p MMCSDBlockDevice object - * @param[out] csd10 pointer to the @p unpacked_sdc_csd_10_t object - * - * @notapi - */ -void _mmcsd_unpack_csd_v10(const MMCSDBlockDevice *sdcp, - unpacked_sdc_csd_10_t *csd10) { - const uint32_t *csd; - - osalDbgCheck(NULL != sdcp); - - csd = sdcp->csd; - csd10->c_size = (uint16_t)_mmcsd_get_slice(csd, MMCSD_CSD_10_C_SIZE_SLICE); - csd10->c_size_mult = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_C_SIZE_MULT_SLICE); - csd10->ccc = (uint16_t)_mmcsd_get_slice(csd, MMCSD_CSD_10_CCC_SLICE); - csd10->copy = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_COPY_SLICE); - csd10->crc = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_CRC_SLICE); - csd10->csd_structure = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_CSD_STRUCTURE_SLICE); - csd10->dsr_imp = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_DSR_IMP_SLICE); - csd10->erase_blk_en = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_ERASE_BLK_EN_SLICE); - csd10->erase_sector_size = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_ERASE_SECTOR_SIZE_SLICE); - csd10->file_format = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_FILE_FORMAT_SLICE); - csd10->file_format_grp = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_FILE_FORMAT_GRP_SLICE); - csd10->nsac = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_NSAC_SLICE); - csd10->perm_write_protect = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_PERM_WRITE_PROTECT_SLICE); - csd10->r2w_factor = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_R2W_FACTOR_SLICE); - csd10->read_bl_len = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_READ_BL_LEN_SLICE); - csd10->read_bl_partial = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_READ_BL_PARTIAL_SLICE); - csd10->read_blk_misalign = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_READ_BLK_MISALIGN_SLICE); - csd10->taac = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_TAAC_SLICE); - csd10->tmp_write_protect = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_TMP_WRITE_PROTECT_SLICE); - csd10->tran_speed = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_TRANS_SPEED_SLICE); - csd10->wp_grp_enable = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_WP_GRP_ENABLE_SLICE); - csd10->wp_grp_size = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_WP_GRP_SIZE_SLICE); - csd10->write_bl_len = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_WRITE_BL_LEN_SLICE); - csd10->write_bl_partial = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_WRITE_BL_PARTIAL_SLICE); - csd10->write_blk_misalign = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_10_WRITE_BLK_MISALIGN_SLICE); -} - -/** - * @brief Unpacks SDC CSD v2.0 array in structure. - * - * @param[in] sdcp pointer to the @p MMCSDBlockDevice object - * @param[out] csd20 pointer to the @p unpacked_sdc_csd_20_t object - * - * @notapi - */ -void _mmcsd_unpack_csd_v20(const MMCSDBlockDevice *sdcp, - unpacked_sdc_csd_20_t *csd20) { - const uint32_t *csd; - - osalDbgCheck(NULL != sdcp); - - csd = sdcp->csd; - csd20->c_size = _mmcsd_get_slice(csd, MMCSD_CSD_20_C_SIZE_SLICE); - csd20->crc = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_CRC_SLICE); - csd20->ccc = (uint16_t)_mmcsd_get_slice(csd, MMCSD_CSD_20_CCC_SLICE); - csd20->copy = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_COPY_SLICE); - csd20->csd_structure = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_CSD_STRUCTURE_SLICE); - csd20->dsr_imp = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_DSR_IMP_SLICE); - csd20->erase_blk_en = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_ERASE_BLK_EN_SLICE); - csd20->file_format = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_FILE_FORMAT_SLICE); - csd20->file_format_grp = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_FILE_FORMAT_GRP_SLICE); - csd20->nsac = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_NSAC_SLICE); - csd20->perm_write_protect = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_PERM_WRITE_PROTECT_SLICE); - csd20->r2w_factor = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_R2W_FACTOR_SLICE); - csd20->read_bl_len = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_READ_BL_LEN_SLICE); - csd20->read_bl_partial = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_READ_BL_PARTIAL_SLICE); - csd20->read_blk_misalign = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_READ_BLK_MISALIGN_SLICE); - csd20->erase_sector_size = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_ERASE_SECTOR_SIZE_SLICE); - csd20->taac = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_TAAC_SLICE); - csd20->tmp_write_protect = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_TMP_WRITE_PROTECT_SLICE); - csd20->tran_speed = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_TRANS_SPEED_SLICE); - csd20->wp_grp_enable = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_WP_GRP_ENABLE_SLICE); - csd20->wp_grp_size = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_WP_GRP_SIZE_SLICE); - csd20->write_bl_len = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_WRITE_BL_LEN_SLICE); - csd20->write_bl_partial = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_WRITE_BL_PARTIAL_SLICE); - csd20->write_blk_misalign = (uint8_t) _mmcsd_get_slice(csd, MMCSD_CSD_20_WRITE_BLK_MISALIGN_SLICE); -} - -#endif /* (HAL_USE_MMC_SPI == TRUE) || (HAL_USE_SDC == TRUE) */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/src/hal_queues.c b/firmware/ChibiOS_16/os/hal/src/hal_queues.c deleted file mode 100644 index c8b8851b9c..0000000000 --- a/firmware/ChibiOS_16/os/hal/src/hal_queues.c +++ /dev/null @@ -1,417 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_queues.c - * @brief I/O Queues code. - * - * @addtogroup HAL_QUEUES - * @details Queues are mostly used in serial-like device drivers. - * Serial device drivers are usually designed to have a lower side - * (lower driver, it is usually an interrupt service routine) and an - * upper side (upper driver, accessed by the application threads).
- * There are several kind of queues:
- * - Input queue, unidirectional queue where the writer is the - * lower side and the reader is the upper side. - * - Output queue, unidirectional queue where the writer is the - * upper side and the reader is the lower side. - * - Full duplex queue, bidirectional queue. Full duplex queues - * are implemented by pairing an input queue and an output queue - * together. - * . - * @{ - */ - -#include "hal.h" - -#if !defined(_CHIBIOS_RT_) || (CH_CFG_USE_QUEUES == FALSE) || \ - defined(__DOXYGEN__) - -/** - * @brief Initializes an input queue. - * @details A Semaphore is internally initialized and works as a counter of - * the bytes contained in the queue. - * @note The callback is invoked from within the S-Locked system state. - * - * @param[out] iqp pointer to an @p input_queue_t structure - * @param[in] bp pointer to a memory area allocated as queue buffer - * @param[in] size size of the queue buffer - * @param[in] infy pointer to a callback function that is invoked when - * data is read from the queue. The value can be @p NULL. - * @param[in] link application defined pointer - * - * @init - */ -void iqObjectInit(input_queue_t *iqp, uint8_t *bp, size_t size, - qnotify_t infy, void *link) { - - osalThreadQueueObjectInit(&iqp->q_waiting); - iqp->q_counter = 0; - iqp->q_buffer = bp; - iqp->q_rdptr = bp; - iqp->q_wrptr = bp; - iqp->q_top = bp + size; - iqp->q_notify = infy; - iqp->q_link = link; -} - -/** - * @brief Resets an input queue. - * @details All the data in the input queue is erased and lost, any waiting - * thread is resumed with status @p Q_RESET. - * @note A reset operation can be used by a low level driver in order to - * obtain immediate attention from the high level layers. - * - * @param[in] iqp pointer to an @p input_queue_t structure - * - * @iclass - */ -void iqResetI(input_queue_t *iqp) { - - osalDbgCheckClassI(); - - iqp->q_rdptr = iqp->q_buffer; - iqp->q_wrptr = iqp->q_buffer; - iqp->q_counter = 0; - osalThreadDequeueAllI(&iqp->q_waiting, Q_RESET); -} - -/** - * @brief Input queue write. - * @details A byte value is written into the low end of an input queue. - * - * @param[in] iqp pointer to an @p input_queue_t structure - * @param[in] b the byte value to be written in the queue - * @return The operation status. - * @retval Q_OK if the operation has been completed with success. - * @retval Q_FULL if the queue is full and the operation cannot be - * completed. - * - * @iclass - */ -msg_t iqPutI(input_queue_t *iqp, uint8_t b) { - - osalDbgCheckClassI(); - - if (iqIsFullI(iqp)) { - return Q_FULL; - } - - iqp->q_counter++; - *iqp->q_wrptr++ = b; - if (iqp->q_wrptr >= iqp->q_top) { - iqp->q_wrptr = iqp->q_buffer; - } - - osalThreadDequeueNextI(&iqp->q_waiting, Q_OK); - - return Q_OK; -} - -/** - * @brief Input queue read with timeout. - * @details This function reads a byte value from an input queue. If the queue - * is empty then the calling thread is suspended until a byte arrives - * in the queue or a timeout occurs. - * @note The callback is invoked before reading the character from the - * buffer or before entering the state @p THD_STATE_WTQUEUE. - * - * @param[in] iqp pointer to an @p input_queue_t structure - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return A byte value from the queue. - * @retval Q_TIMEOUT if the specified time expired. - * @retval Q_RESET if the queue has been reset. - * - * @api - */ -msg_t iqGetTimeout(input_queue_t *iqp, systime_t timeout) { - uint8_t b; - - osalSysLock(); - if (iqp->q_notify != NULL) { - iqp->q_notify(iqp); - } - - while (iqIsEmptyI(iqp)) { - msg_t msg = osalThreadEnqueueTimeoutS(&iqp->q_waiting, timeout); - if (msg < Q_OK) { - osalSysUnlock(); - return msg; - } - } - - iqp->q_counter--; - b = *iqp->q_rdptr++; - if (iqp->q_rdptr >= iqp->q_top) { - iqp->q_rdptr = iqp->q_buffer; - } - osalSysUnlock(); - - return (msg_t)b; -} - -/** - * @brief Input queue read with timeout. - * @details The function reads data from an input queue into a buffer. The - * operation completes when the specified amount of data has been - * transferred or after the specified timeout or if the queue has - * been reset. - * @note The function is not atomic, if you need atomicity it is suggested - * to use a semaphore or a mutex for mutual exclusion. - * @note The callback is invoked before reading each character from the - * buffer or before entering the state @p THD_STATE_WTQUEUE. - * - * @param[in] iqp pointer to an @p input_queue_t structure - * @param[out] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred, the - * value 0 is reserved - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The number of bytes effectively transferred. - * - * @api - */ -size_t iqReadTimeout(input_queue_t *iqp, uint8_t *bp, - size_t n, systime_t timeout) { - qnotify_t nfy = iqp->q_notify; - size_t r = 0; - - osalDbgCheck(n > 0U); - - osalSysLock(); - while (true) { - if (nfy != NULL) { - nfy(iqp); - } - - while (iqIsEmptyI(iqp)) { - if (osalThreadEnqueueTimeoutS(&iqp->q_waiting, timeout) != Q_OK) { - osalSysUnlock(); - return r; - } - } - - iqp->q_counter--; - *bp++ = *iqp->q_rdptr++; - if (iqp->q_rdptr >= iqp->q_top) { - iqp->q_rdptr = iqp->q_buffer; - } - osalSysUnlock(); /* Gives a preemption chance in a controlled point.*/ - - r++; - if (--n == 0U) { - return r; - } - - osalSysLock(); - } -} - -/** - * @brief Initializes an output queue. - * @details A Semaphore is internally initialized and works as a counter of - * the free bytes in the queue. - * @note The callback is invoked from within the S-Locked system state. - * - * @param[out] oqp pointer to an @p output_queue_t structure - * @param[in] bp pointer to a memory area allocated as queue buffer - * @param[in] size size of the queue buffer - * @param[in] onfy pointer to a callback function that is invoked when - * data is written to the queue. The value can be @p NULL. - * @param[in] link application defined pointer - * - * @init - */ -void oqObjectInit(output_queue_t *oqp, uint8_t *bp, size_t size, - qnotify_t onfy, void *link) { - - osalThreadQueueObjectInit(&oqp->q_waiting); - oqp->q_counter = size; - oqp->q_buffer = bp; - oqp->q_rdptr = bp; - oqp->q_wrptr = bp; - oqp->q_top = bp + size; - oqp->q_notify = onfy; - oqp->q_link = link; -} - -/** - * @brief Resets an output queue. - * @details All the data in the output queue is erased and lost, any waiting - * thread is resumed with status @p Q_RESET. - * @note A reset operation can be used by a low level driver in order to - * obtain immediate attention from the high level layers. - * - * @param[in] oqp pointer to an @p output_queue_t structure - * - * @iclass - */ -void oqResetI(output_queue_t *oqp) { - - osalDbgCheckClassI(); - - oqp->q_rdptr = oqp->q_buffer; - oqp->q_wrptr = oqp->q_buffer; - oqp->q_counter = qSizeX(oqp); - osalThreadDequeueAllI(&oqp->q_waiting, Q_RESET); -} - -/** - * @brief Output queue write with timeout. - * @details This function writes a byte value to an output queue. If the queue - * is full then the calling thread is suspended until there is space - * in the queue or a timeout occurs. - * @note The callback is invoked after writing the character into the - * buffer. - * - * @param[in] oqp pointer to an @p output_queue_t structure - * @param[in] b the byte value to be written in the queue - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval Q_OK if the operation succeeded. - * @retval Q_TIMEOUT if the specified time expired. - * @retval Q_RESET if the queue has been reset. - * - * @api - */ -msg_t oqPutTimeout(output_queue_t *oqp, uint8_t b, systime_t timeout) { - - osalSysLock(); - while (oqIsFullI(oqp)) { - msg_t msg = osalThreadEnqueueTimeoutS(&oqp->q_waiting, timeout); - if (msg < Q_OK) { - osalSysUnlock(); - return msg; - } - } - - oqp->q_counter--; - *oqp->q_wrptr++ = b; - if (oqp->q_wrptr >= oqp->q_top) { - oqp->q_wrptr = oqp->q_buffer; - } - - if (oqp->q_notify != NULL) { - oqp->q_notify(oqp); - } - osalSysUnlock(); - - return Q_OK; -} - -/** - * @brief Output queue read. - * @details A byte value is read from the low end of an output queue. - * - * @param[in] oqp pointer to an @p output_queue_t structure - * @return The byte value from the queue. - * @retval Q_EMPTY if the queue is empty. - * - * @iclass - */ -msg_t oqGetI(output_queue_t *oqp) { - uint8_t b; - - osalDbgCheckClassI(); - - if (oqIsEmptyI(oqp)) { - return Q_EMPTY; - } - - oqp->q_counter++; - b = *oqp->q_rdptr++; - if (oqp->q_rdptr >= oqp->q_top) { - oqp->q_rdptr = oqp->q_buffer; - } - - osalThreadDequeueNextI(&oqp->q_waiting, Q_OK); - - return (msg_t)b; -} - -/** - * @brief Output queue write with timeout. - * @details The function writes data from a buffer to an output queue. The - * operation completes when the specified amount of data has been - * transferred or after the specified timeout or if the queue has - * been reset. - * @note The function is not atomic, if you need atomicity it is suggested - * to use a semaphore or a mutex for mutual exclusion. - * @note The callback is invoked after writing each character into the - * buffer. - * - * @param[in] oqp pointer to an @p output_queue_t structure - * @param[in] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred, the - * value 0 is reserved - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The number of bytes effectively transferred. - * - * @api - */ -size_t oqWriteTimeout(output_queue_t *oqp, const uint8_t *bp, - size_t n, systime_t timeout) { - qnotify_t nfy = oqp->q_notify; - size_t w = 0; - - osalDbgCheck(n > 0U); - - osalSysLock(); - while (true) { - while (oqIsFullI(oqp)) { - if (osalThreadEnqueueTimeoutS(&oqp->q_waiting, timeout) != Q_OK) { - osalSysUnlock(); - return w; - } - } - oqp->q_counter--; - *oqp->q_wrptr++ = *bp++; - if (oqp->q_wrptr >= oqp->q_top) { - oqp->q_wrptr = oqp->q_buffer; - } - - if (nfy != NULL) { - nfy(oqp); - } - osalSysUnlock(); /* Gives a preemption chance in a controlled point.*/ - - w++; - if (--n == 0U) { - return w; - } - - osalSysLock(); - } -} - -#endif /* !defined(_CHIBIOS_RT_) || (CH_USE_QUEUES == FALSE) */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/src/i2c.c b/firmware/ChibiOS_16/os/hal/src/i2c.c deleted file mode 100644 index 4914ff0e22..0000000000 --- a/firmware/ChibiOS_16/os/hal/src/i2c.c +++ /dev/null @@ -1,283 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Concepts and parts of this file have been contributed by Uladzimir Pylinsky - aka barthess. - */ - -/** - * @file i2c.c - * @brief I2C Driver code. - * - * @addtogroup I2C - * @{ - */ -#include "hal.h" - -#if (HAL_USE_I2C == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief I2C Driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void i2cInit(void) { - - i2c_lld_init(); -} - -/** - * @brief Initializes the standard part of a @p I2CDriver structure. - * - * @param[out] i2cp pointer to the @p I2CDriver object - * - * @init - */ -void i2cObjectInit(I2CDriver *i2cp) { - - i2cp->state = I2C_STOP; - i2cp->config = NULL; - -#if I2C_USE_MUTUAL_EXCLUSION == TRUE - osalMutexObjectInit(&i2cp->mutex); -#endif - -#if defined(I2C_DRIVER_EXT_INIT_HOOK) - I2C_DRIVER_EXT_INIT_HOOK(i2cp); -#endif -} - -/** - * @brief Configures and activates the I2C peripheral. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] config pointer to the @p I2CConfig object - * - * @api - */ -void i2cStart(I2CDriver *i2cp, const I2CConfig *config) { - - osalDbgCheck((i2cp != NULL) && (config != NULL)); - osalDbgAssert((i2cp->state == I2C_STOP) || (i2cp->state == I2C_READY) || - (i2cp->state == I2C_LOCKED), "invalid state"); - - osalSysLock(); - i2cp->config = config; - i2c_lld_start(i2cp); - i2cp->state = I2C_READY; - osalSysUnlock(); -} - -/** - * @brief Deactivates the I2C peripheral. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @api - */ -void i2cStop(I2CDriver *i2cp) { - - osalDbgCheck(i2cp != NULL); - osalDbgAssert((i2cp->state == I2C_STOP) || (i2cp->state == I2C_READY) || - (i2cp->state == I2C_LOCKED), "invalid state"); - - osalSysLock(); - i2c_lld_stop(i2cp); - i2cp->state = I2C_STOP; - osalSysUnlock(); -} - -/** - * @brief Returns the errors mask associated to the previous operation. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * @return The errors mask. - * - * @api - */ -i2cflags_t i2cGetErrors(I2CDriver *i2cp) { - - osalDbgCheck(i2cp != NULL); - - return i2c_lld_get_errors(i2cp); -} - -/** - * @brief Sends data via the I2C bus. - * @details Function designed to realize "read-through-write" transfer - * paradigm. If you want transmit data without any further read, - * than set @b rxbytes field to 0. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] addr slave device address (7 bits) without R/W bit - * @param[in] txbuf pointer to transmit buffer - * @param[in] txbytes number of bytes to be transmitted - * @param[out] rxbuf pointer to receive buffer - * @param[in] rxbytes number of bytes to be received, set it to 0 if - * you want transmit only - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_INFINITE no timeout. - * . - * - * @return The operation status. - * @retval MSG_OK if the function succeeded. - * @retval MSG_RESET if one or more I2C errors occurred, the errors can - * be retrieved using @p i2cGetErrors(). - * @retval MSG_TIMEOUT if a timeout occurred before operation end. - * - * @api - */ -msg_t i2cMasterTransmitTimeout(I2CDriver *i2cp, - i2caddr_t addr, - const uint8_t *txbuf, - size_t txbytes, - uint8_t *rxbuf, - size_t rxbytes, - systime_t timeout) { - msg_t rdymsg; - - osalDbgCheck((i2cp != NULL) && (addr != 0U) && - (txbytes > 0U) && (txbuf != NULL) && - ((rxbytes == 0U) || ((rxbytes > 0U) && (rxbuf != NULL))) && - (timeout != TIME_IMMEDIATE)); - - osalDbgAssert(i2cp->state == I2C_READY, "not ready"); - - osalSysLock(); - i2cp->errors = I2C_NO_ERROR; - i2cp->state = I2C_ACTIVE_TX; - rdymsg = i2c_lld_master_transmit_timeout(i2cp, addr, txbuf, txbytes, - rxbuf, rxbytes, timeout); - if (rdymsg == MSG_TIMEOUT) { - i2cp->state = I2C_LOCKED; - } - else { - i2cp->state = I2C_READY; - } - osalSysUnlock(); - return rdymsg; -} - -/** - * @brief Receives data from the I2C bus. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] addr slave device address (7 bits) without R/W bit - * @param[out] rxbuf pointer to receive buffer - * @param[in] rxbytes number of bytes to be received - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_INFINITE no timeout. - * . - * - * @return The operation status. - * @retval MSG_OK if the function succeeded. - * @retval MSG_RESET if one or more I2C errors occurred, the errors can - * be retrieved using @p i2cGetErrors(). - * @retval MSG_TIMEOUT if a timeout occurred before operation end. - * - * @api - */ -msg_t i2cMasterReceiveTimeout(I2CDriver *i2cp, - i2caddr_t addr, - uint8_t *rxbuf, - size_t rxbytes, - systime_t timeout){ - - msg_t rdymsg; - - osalDbgCheck((i2cp != NULL) && (addr != 0U) && - (rxbytes > 0U) && (rxbuf != NULL) && - (timeout != TIME_IMMEDIATE)); - - osalDbgAssert(i2cp->state == I2C_READY, "not ready"); - - osalSysLock(); - i2cp->errors = I2C_NO_ERROR; - i2cp->state = I2C_ACTIVE_RX; - rdymsg = i2c_lld_master_receive_timeout(i2cp, addr, rxbuf, rxbytes, timeout); - if (rdymsg == MSG_TIMEOUT) { - i2cp->state = I2C_LOCKED; - } - else { - i2cp->state = I2C_READY; - } - osalSysUnlock(); - return rdymsg; -} - -#if (I2C_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__) -/** - * @brief Gains exclusive access to the I2C bus. - * @details This function tries to gain ownership to the I2C bus, if the bus - * is already being used then the invoking thread is queued. - * @pre In order to use this function the option @p I2C_USE_MUTUAL_EXCLUSION - * must be enabled. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @api - */ -void i2cAcquireBus(I2CDriver *i2cp) { - - osalDbgCheck(i2cp != NULL); - - osalMutexLock(&i2cp->mutex); -} - -/** - * @brief Releases exclusive access to the I2C bus. - * @pre In order to use this function the option @p I2C_USE_MUTUAL_EXCLUSION - * must be enabled. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @api - */ -void i2cReleaseBus(I2CDriver *i2cp) { - - osalDbgCheck(i2cp != NULL); - - osalMutexUnlock(&i2cp->mutex); -} -#endif /* I2C_USE_MUTUAL_EXCLUSION == TRUE */ - -#endif /* HAL_USE_I2C == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/src/i2s.c b/firmware/ChibiOS_16/os/hal/src/i2s.c deleted file mode 100644 index 9692ad186b..0000000000 --- a/firmware/ChibiOS_16/os/hal/src/i2s.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file i2s.c - * @brief I2S Driver code. - * - * @addtogroup I2S - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_I2S == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief I2S Driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void i2sInit(void) { - - i2s_lld_init(); -} - -/** - * @brief Initializes the standard part of a @p I2SDriver structure. - * - * @param[out] i2sp pointer to the @p I2SDriver object - * - * @init - */ -void i2sObjectInit(I2SDriver *i2sp) { - - i2sp->state = I2S_STOP; - i2sp->config = NULL; -} - -/** - * @brief Configures and activates the I2S peripheral. - * - * @param[in] i2sp pointer to the @p I2SDriver object - * @param[in] config pointer to the @p I2SConfig object - * - * @api - */ -void i2sStart(I2SDriver *i2sp, const I2SConfig *config) { - - osalDbgCheck((i2sp != NULL) && (config != NULL)); - - osalSysLock(); - osalDbgAssert((i2sp->state == I2S_STOP) || (i2sp->state == I2S_READY), - "invalid state"); - i2sp->config = config; - i2s_lld_start(i2sp); - i2sp->state = I2S_READY; - osalSysUnlock(); -} - -/** - * @brief Deactivates the I2S peripheral. - * - * @param[in] i2sp pointer to the @p I2SDriver object - * - * @api - */ -void i2sStop(I2SDriver *i2sp) { - - osalDbgCheck(i2sp != NULL); - - osalSysLock(); - osalDbgAssert((i2sp->state == I2S_STOP) || (i2sp->state == I2S_READY), - "invalid state"); - i2s_lld_stop(i2sp); - i2sp->state = I2S_STOP; - osalSysUnlock(); -} - -/** - * @brief Starts a I2S data exchange. - * - * @param[in] i2sp pointer to the @p I2SDriver object - * - * @api - */ -void i2sStartExchange(I2SDriver *i2sp) { - - osalDbgCheck(i2sp != NULL); - - osalSysLock(); - osalDbgAssert(i2sp->state == I2S_READY, "not ready"); - i2sStartExchangeI(i2sp); - osalSysUnlock(); -} - -/** - * @brief Stops the ongoing data exchange. - * @details The ongoing data exchange, if any, is stopped, if the driver - * was not active the function does nothing. - * - * @param[in] i2sp pointer to the @p I2SDriver object - * - * @api - */ -void i2sStopExchange(I2SDriver *i2sp) { - - osalDbgCheck((i2sp != NULL)); - - osalSysLock(); - osalDbgAssert((i2sp->state == I2S_READY) || - (i2sp->state == I2S_ACTIVE) || - (i2sp->state == I2S_COMPLETE), - "invalid state"); - i2sStopExchangeI(i2sp); - osalSysUnlock(); -} - -#endif /* HAL_USE_I2S == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/src/icu.c b/firmware/ChibiOS_16/os/hal/src/icu.c deleted file mode 100644 index 0c98ccb545..0000000000 --- a/firmware/ChibiOS_16/os/hal/src/icu.c +++ /dev/null @@ -1,225 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file icu.c - * @brief ICU Driver code. - * - * @addtogroup ICU - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_ICU == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief ICU Driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void icuInit(void) { - - icu_lld_init(); -} - -/** - * @brief Initializes the standard part of a @p ICUDriver structure. - * - * @param[out] icup pointer to the @p ICUDriver object - * - * @init - */ -void icuObjectInit(ICUDriver *icup) { - - icup->state = ICU_STOP; - icup->config = NULL; -} - -/** - * @brief Configures and activates the ICU peripheral. - * - * @param[in] icup pointer to the @p ICUDriver object - * @param[in] config pointer to the @p ICUConfig object - * - * @api - */ -void icuStart(ICUDriver *icup, const ICUConfig *config) { - - osalDbgCheck((icup != NULL) && (config != NULL)); - - osalSysLock(); - osalDbgAssert((icup->state == ICU_STOP) || (icup->state == ICU_READY), - "invalid state"); - icup->config = config; - icu_lld_start(icup); - icup->state = ICU_READY; - osalSysUnlock(); -} - -/** - * @brief Deactivates the ICU peripheral. - * - * @param[in] icup pointer to the @p ICUDriver object - * - * @api - */ -void icuStop(ICUDriver *icup) { - - osalDbgCheck(icup != NULL); - - osalSysLock(); - osalDbgAssert((icup->state == ICU_STOP) || (icup->state == ICU_READY), - "invalid state"); - icu_lld_stop(icup); - icup->state = ICU_STOP; - osalSysUnlock(); -} - -/** - * @brief Starts the input capture. - * - * @param[in] icup pointer to the @p ICUDriver object - * - * @api - */ -void icuStartCapture(ICUDriver *icup) { - - osalDbgCheck(icup != NULL); - - osalSysLock(); - osalDbgAssert(icup->state == ICU_READY, "invalid state"); - icuStartCaptureI(icup); - osalSysUnlock(); -} - -/** - * @brief Waits for a completed capture. - * @note The operation could be performed in polled mode depending on. - * @note In order to use this function notifications must be disabled. - * @pre The driver must be in @p ICU_WAITING or @p ICU_ACTIVE states. - * @post After the capture is available the driver is in @p ICU_ACTIVE - * state. If a capture fails then the driver is in @p ICU_WAITING - * state. - * - * @param[in] icup pointer to the @p ICUDriver object - * @return The capture status. - * @retval false if the capture is successful. - * @retval true if a timer overflow occurred. - * - * @api - */ -bool icuWaitCapture(ICUDriver *icup) { - bool result; - - osalDbgCheck(icup != NULL); - - osalSysLock(); - osalDbgAssert((icup->state == ICU_WAITING) || (icup->state == ICU_ACTIVE), - "invalid state"); - osalDbgAssert(icuAreNotificationsEnabledX(icup) == false, - "notifications enabled"); - result = icu_lld_wait_capture(icup); - icup->state = result ? ICU_WAITING : ICU_ACTIVE; - osalSysUnlock(); - - return result; -} - -/** - * @brief Stops the input capture. - * - * @param[in] icup pointer to the @p ICUDriver object - * - * @api - */ -void icuStopCapture(ICUDriver *icup) { - - osalDbgCheck(icup != NULL); - - osalSysLock(); - osalDbgAssert((icup->state == ICU_READY) || (icup->state == ICU_WAITING) || - (icup->state == ICU_ACTIVE), - "invalid state"); - icuStopCaptureI(icup); - osalSysUnlock(); -} - -/** - * @brief Enables notifications. - * @pre The ICU unit must have been activated using @p icuStart(). - * @note If the notification is already enabled then the call has no effect. - * - * @param[in] icup pointer to the @p ICUDriver object - * - * @api - */ -void icuEnableNotifications(ICUDriver *icup) { - - osalDbgCheck(icup != NULL); - - osalSysLock(); - osalDbgAssert((icup->state == ICU_WAITING) || (icup->state == ICU_ACTIVE), - "invalid state"); - icuEnableNotificationsI(icup); - osalSysUnlock(); -} - -/** - * @brief Disables notifications. - * @pre The ICU unit must have been activated using @p icuStart(). - * @note If the notification is already disabled then the call has no effect. - * - * @param[in] icup pointer to the @p ICUDriver object - * - * @api - */ -void icuDisableNotifications(ICUDriver *icup) { - - osalDbgCheck(icup != NULL); - - osalSysLock(); - osalDbgAssert((icup->state == ICU_WAITING) || (icup->state == ICU_ACTIVE), - "invalid state"); - icuDisableNotificationsI(icup); - osalSysUnlock(); -} - -#endif /* HAL_USE_ICU == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/src/mac.c b/firmware/ChibiOS_16/os/hal/src/mac.c deleted file mode 100644 index 79e705c33f..0000000000 --- a/firmware/ChibiOS_16/os/hal/src/mac.c +++ /dev/null @@ -1,268 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file mac.c - * @brief MAC Driver code. - * - * @addtogroup MAC - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_MAC == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#if (MAC_USE_ZERO_COPY == TRUE) && (MAC_SUPPORTS_ZERO_COPY == FALSE) -#error "MAC_USE_ZERO_COPY not supported by this implementation" -#endif - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief MAC Driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void macInit(void) { - - mac_lld_init(); -} - -/** - * @brief Initialize the standard part of a @p MACDriver structure. - * - * @param[out] macp pointer to the @p MACDriver object - * - * @init - */ -void macObjectInit(MACDriver *macp) { - - macp->state = MAC_STOP; - macp->config = NULL; - osalThreadQueueObjectInit(&macp->tdqueue); - osalThreadQueueObjectInit(&macp->rdqueue); -#if MAC_USE_EVENTS == TRUE - osalEventObjectInit(&macp->rdevent); -#endif -} - -/** - * @brief Configures and activates the MAC peripheral. - * - * @param[in] macp pointer to the @p MACDriver object - * @param[in] config pointer to the @p MACConfig object - * - * @api - */ -void macStart(MACDriver *macp, const MACConfig *config) { - - osalDbgCheck((macp != NULL) && (config != NULL)); - - osalSysLock(); - osalDbgAssert(macp->state == MAC_STOP, - "invalid state"); - macp->config = config; - mac_lld_start(macp); - macp->state = MAC_ACTIVE; - osalSysUnlock(); -} - -/** - * @brief Deactivates the MAC peripheral. - * - * @param[in] macp pointer to the @p MACDriver object - * - * @api - */ -void macStop(MACDriver *macp) { - - osalDbgCheck(macp != NULL); - - osalSysLock(); - osalDbgAssert((macp->state == MAC_STOP) || (macp->state == MAC_ACTIVE), - "invalid state"); - mac_lld_stop(macp); - macp->state = MAC_STOP; - osalSysUnlock(); -} - -/** - * @brief Allocates a transmission descriptor. - * @details One of the available transmission descriptors is locked and - * returned. If a descriptor is not currently available then the - * invoking thread is queued until one is freed. - * - * @param[in] macp pointer to the @p MACDriver object - * @param[out] tdp pointer to a @p MACTransmitDescriptor structure - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval MSG_OK the descriptor was obtained. - * @retval MSG_TIMEOUT the operation timed out, descriptor not initialized. - * - * @api - */ -msg_t macWaitTransmitDescriptor(MACDriver *macp, - MACTransmitDescriptor *tdp, - systime_t timeout) { - msg_t msg; - systime_t now; - - osalDbgCheck((macp != NULL) && (tdp != NULL)); - osalDbgAssert(macp->state == MAC_ACTIVE, "not active"); - - while (((msg = mac_lld_get_transmit_descriptor(macp, tdp)) != MSG_OK) && - (timeout > (systime_t)0)) { - osalSysLock(); - now = osalOsGetSystemTimeX(); - msg = osalThreadEnqueueTimeoutS(&macp->tdqueue, timeout); - if (msg == MSG_TIMEOUT) { - osalSysUnlock(); - break; - } - if (timeout != TIME_INFINITE) { - timeout -= (osalOsGetSystemTimeX() - now); - } - osalSysUnlock(); - } - return msg; -} - -/** - * @brief Releases a transmit descriptor and starts the transmission of the - * enqueued data as a single frame. - * - * @param[in] tdp the pointer to the @p MACTransmitDescriptor structure - * - * @api - */ -void macReleaseTransmitDescriptor(MACTransmitDescriptor *tdp) { - - osalDbgCheck(tdp != NULL); - - mac_lld_release_transmit_descriptor(tdp); -} - -/** - * @brief Waits for a received frame. - * @details Stops until a frame is received and buffered. If a frame is - * not immediately available then the invoking thread is queued - * until one is received. - * - * @param[in] macp pointer to the @p MACDriver object - * @param[out] rdp pointer to a @p MACReceiveDescriptor structure - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval MSG_OK the descriptor was obtained. - * @retval MSG_TIMEOUT the operation timed out, descriptor not initialized. - * - * @api - */ -msg_t macWaitReceiveDescriptor(MACDriver *macp, - MACReceiveDescriptor *rdp, - systime_t timeout) { - msg_t msg; - systime_t now; - - osalDbgCheck((macp != NULL) && (rdp != NULL)); - osalDbgAssert(macp->state == MAC_ACTIVE, "not active"); - - while (((msg = mac_lld_get_receive_descriptor(macp, rdp)) != MSG_OK) && - (timeout > (systime_t)0)) { - osalSysLock(); - now = osalOsGetSystemTimeX(); - msg = osalThreadEnqueueTimeoutS(&macp->rdqueue, timeout); - if (msg == MSG_TIMEOUT) { - osalSysUnlock(); - break; - } - if (timeout != TIME_INFINITE) { - timeout -= (osalOsGetSystemTimeX() - now); - } - osalSysUnlock(); - } - return msg; -} - -/** - * @brief Releases a receive descriptor. - * @details The descriptor and its buffer are made available for more incoming - * frames. - * - * @param[in] rdp the pointer to the @p MACReceiveDescriptor structure - * - * @api - */ -void macReleaseReceiveDescriptor(MACReceiveDescriptor *rdp) { - - osalDbgCheck(rdp != NULL); - - mac_lld_release_receive_descriptor(rdp); -} - -/** - * @brief Updates and returns the link status. - * - * @param[in] macp pointer to the @p MACDriver object - * @return The link status. - * @retval true if the link is active. - * @retval false if the link is down. - * - * @api - */ -bool macPollLinkStatus(MACDriver *macp) { - - osalDbgCheck(macp != NULL); - osalDbgAssert(macp->state == MAC_ACTIVE, "not active"); - - return mac_lld_poll_link_status(macp); -} - -#endif /* HAL_USE_MAC == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/src/mmc_spi.c b/firmware/ChibiOS_16/os/hal/src/mmc_spi.c deleted file mode 100644 index 3be0b5d659..0000000000 --- a/firmware/ChibiOS_16/os/hal/src/mmc_spi.c +++ /dev/null @@ -1,918 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Parts of this file have been contributed by Matthias Blaicher. - */ - -/** - * @file mmc_spi.c - * @brief MMC over SPI driver code. - * - * @addtogroup MMC_SPI - * @{ - */ - -#include - -#include "hal.h" - -#if (HAL_USE_MMC_SPI == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/* Forward declarations required by mmc_vmt.*/ -static bool mmc_read(void *instance, uint32_t startblk, - uint8_t *buffer, uint32_t n); -static bool mmc_write(void *instance, uint32_t startblk, - const uint8_t *buffer, uint32_t n); - -/** - * @brief Virtual methods table. - */ -static const struct MMCDriverVMT mmc_vmt = { - (bool (*)(void *))mmc_lld_is_card_inserted, - (bool (*)(void *))mmc_lld_is_write_protected, - (bool (*)(void *))mmcConnect, - (bool (*)(void *))mmcDisconnect, - mmc_read, - mmc_write, - (bool (*)(void *))mmcSync, - (bool (*)(void *, BlockDeviceInfo *))mmcGetInfo -}; - -/** - * @brief Lookup table for CRC-7 ( based on polynomial x^7 + x^3 + 1). - */ -static const uint8_t crc7_lookup_table[256] = { - 0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f, 0x48, 0x41, 0x5a, 0x53, - 0x6c, 0x65, 0x7e, 0x77, 0x19, 0x10, 0x0b, 0x02, 0x3d, 0x34, 0x2f, 0x26, - 0x51, 0x58, 0x43, 0x4a, 0x75, 0x7c, 0x67, 0x6e, 0x32, 0x3b, 0x20, 0x29, - 0x16, 0x1f, 0x04, 0x0d, 0x7a, 0x73, 0x68, 0x61, 0x5e, 0x57, 0x4c, 0x45, - 0x2b, 0x22, 0x39, 0x30, 0x0f, 0x06, 0x1d, 0x14, 0x63, 0x6a, 0x71, 0x78, - 0x47, 0x4e, 0x55, 0x5c, 0x64, 0x6d, 0x76, 0x7f, 0x40, 0x49, 0x52, 0x5b, - 0x2c, 0x25, 0x3e, 0x37, 0x08, 0x01, 0x1a, 0x13, 0x7d, 0x74, 0x6f, 0x66, - 0x59, 0x50, 0x4b, 0x42, 0x35, 0x3c, 0x27, 0x2e, 0x11, 0x18, 0x03, 0x0a, - 0x56, 0x5f, 0x44, 0x4d, 0x72, 0x7b, 0x60, 0x69, 0x1e, 0x17, 0x0c, 0x05, - 0x3a, 0x33, 0x28, 0x21, 0x4f, 0x46, 0x5d, 0x54, 0x6b, 0x62, 0x79, 0x70, - 0x07, 0x0e, 0x15, 0x1c, 0x23, 0x2a, 0x31, 0x38, 0x41, 0x48, 0x53, 0x5a, - 0x65, 0x6c, 0x77, 0x7e, 0x09, 0x00, 0x1b, 0x12, 0x2d, 0x24, 0x3f, 0x36, - 0x58, 0x51, 0x4a, 0x43, 0x7c, 0x75, 0x6e, 0x67, 0x10, 0x19, 0x02, 0x0b, - 0x34, 0x3d, 0x26, 0x2f, 0x73, 0x7a, 0x61, 0x68, 0x57, 0x5e, 0x45, 0x4c, - 0x3b, 0x32, 0x29, 0x20, 0x1f, 0x16, 0x0d, 0x04, 0x6a, 0x63, 0x78, 0x71, - 0x4e, 0x47, 0x5c, 0x55, 0x22, 0x2b, 0x30, 0x39, 0x06, 0x0f, 0x14, 0x1d, - 0x25, 0x2c, 0x37, 0x3e, 0x01, 0x08, 0x13, 0x1a, 0x6d, 0x64, 0x7f, 0x76, - 0x49, 0x40, 0x5b, 0x52, 0x3c, 0x35, 0x2e, 0x27, 0x18, 0x11, 0x0a, 0x03, - 0x74, 0x7d, 0x66, 0x6f, 0x50, 0x59, 0x42, 0x4b, 0x17, 0x1e, 0x05, 0x0c, - 0x33, 0x3a, 0x21, 0x28, 0x5f, 0x56, 0x4d, 0x44, 0x7b, 0x72, 0x69, 0x60, - 0x0e, 0x07, 0x1c, 0x15, 0x2a, 0x23, 0x38, 0x31, 0x46, 0x4f, 0x54, 0x5d, - 0x62, 0x6b, 0x70, 0x79 -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static bool mmc_read(void *instance, uint32_t startblk, - uint8_t *buffer, uint32_t n) { - - if (mmcStartSequentialRead((MMCDriver *)instance, startblk)) { - return HAL_FAILED; - } - - while (n > 0U) { - if (mmcSequentialRead((MMCDriver *)instance, buffer)) { - return HAL_FAILED; - } - buffer += MMCSD_BLOCK_SIZE; - n--; - } - - if (mmcStopSequentialRead((MMCDriver *)instance)) { - return HAL_FAILED; - } - return HAL_SUCCESS; -} - -static bool mmc_write(void *instance, uint32_t startblk, - const uint8_t *buffer, uint32_t n) { - - if (mmcStartSequentialWrite((MMCDriver *)instance, startblk)) { - return HAL_FAILED; - } - - while (n > 0U) { - if (mmcSequentialWrite((MMCDriver *)instance, buffer)) { - return HAL_FAILED; - } - buffer += MMCSD_BLOCK_SIZE; - n--; - } - - if (mmcStopSequentialWrite((MMCDriver *)instance)) { - return HAL_FAILED; - } - return HAL_SUCCESS; -} - -/** - * @brief Calculate the MMC standard CRC-7 based on a lookup table. - * - * @param[in] crc start value for CRC - * @param[in] buffer pointer to data buffer - * @param[in] len length of data - * @return Calculated CRC - */ -static uint8_t crc7(uint8_t crc, const uint8_t *buffer, size_t len) { - - while (len > 0U) { - crc = crc7_lookup_table[(crc << 1) ^ (*buffer++)]; - len--; - } - return crc; -} - -/** - * @brief Waits an idle condition. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * - * @notapi - */ -static void wait(MMCDriver *mmcp) { - int i; - uint8_t buf[4]; - - for (i = 0; i < 16; i++) { - spiReceive(mmcp->config->spip, 1, buf); - if (buf[0] == 0xFFU) { - return; - } - } - /* Looks like it is a long wait.*/ - while (true) { - spiReceive(mmcp->config->spip, 1, buf); - if (buf[0] == 0xFFU) { - break; - } -#if MMC_NICE_WAITING == TRUE - /* Trying to be nice with the other threads.*/ - osalThreadSleepMilliseconds(1); -#endif - } -} - -/** - * @brief Sends a command header. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @param[in] cmd the command id - * @param[in] arg the command argument - * - * @notapi - */ -static void send_hdr(MMCDriver *mmcp, uint8_t cmd, uint32_t arg) { - uint8_t buf[6]; - - /* Wait for the bus to become idle if a write operation was in progress.*/ - wait(mmcp); - - buf[0] = (uint8_t)0x40U | cmd; - buf[1] = (uint8_t)(arg >> 24U); - buf[2] = (uint8_t)(arg >> 16U); - buf[3] = (uint8_t)(arg >> 8U); - buf[4] = (uint8_t)arg; - /* Calculate CRC for command header, shift to right position, add stop bit.*/ - buf[5] = ((crc7(0, buf, 5U) & 0x7FU) << 1U) | 0x01U; - - spiSend(mmcp->config->spip, 6, buf); -} - -/** - * @brief Receives a single byte response. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @return The response as an @p uint8_t value. - * @retval 0xFF timed out. - * - * @notapi - */ -static uint8_t recvr1(MMCDriver *mmcp) { - int i; - uint8_t r1[1]; - - for (i = 0; i < 9; i++) { - spiReceive(mmcp->config->spip, 1, r1); - if (r1[0] != 0xFFU) { - return r1[0]; - } - } - return 0xFFU; -} - -/** - * @brief Receives a three byte response. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @param[out] buffer pointer to four bytes wide buffer - * @return First response byte as an @p uint8_t value. - * @retval 0xFF timed out. - * - * @notapi - */ -static uint8_t recvr3(MMCDriver *mmcp, uint8_t* buffer) { - uint8_t r1; - - r1 = recvr1(mmcp); - spiReceive(mmcp->config->spip, 4, buffer); - - return r1; -} - -/** - * @brief Sends a command an returns a single byte response. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @param[in] cmd the command id - * @param[in] arg the command argument - * @return The response as an @p uint8_t value. - * @retval 0xFF timed out. - * - * @notapi - */ -static uint8_t send_command_R1(MMCDriver *mmcp, uint8_t cmd, uint32_t arg) { - uint8_t r1; - - spiSelect(mmcp->config->spip); - send_hdr(mmcp, cmd, arg); - r1 = recvr1(mmcp); - spiUnselect(mmcp->config->spip); - return r1; -} - -/** - * @brief Sends a command which returns a five bytes response (R3). - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @param[in] cmd the command id - * @param[in] arg the command argument - * @param[out] response pointer to four bytes wide uint8_t buffer - * @return The first byte of the response (R1) as an @p - * uint8_t value. - * @retval 0xFF timed out. - * - * @notapi - */ -static uint8_t send_command_R3(MMCDriver *mmcp, uint8_t cmd, uint32_t arg, - uint8_t *response) { - uint8_t r1; - - spiSelect(mmcp->config->spip); - send_hdr(mmcp, cmd, arg); - r1 = recvr3(mmcp, response); - spiUnselect(mmcp->config->spip); - return r1; -} - -/** - * @brief Reads the CSD. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @param[out] cmd command - * @param[out] cxd pointer to the CSD/CID buffer - * - * @return The operation status. - * @retval HAL_SUCCESS the operation succeeded. - * @retval HAL_FAILED the operation failed. - * - * @notapi - */ -static bool read_CxD(MMCDriver *mmcp, uint8_t cmd, uint32_t cxd[4]) { - unsigned i; - uint8_t *bp, buf[16]; - - spiSelect(mmcp->config->spip); - send_hdr(mmcp, cmd, 0); - if (recvr1(mmcp) != 0x00U) { - spiUnselect(mmcp->config->spip); - return HAL_FAILED; - } - - /* Wait for data availability.*/ - for (i = 0U; i < MMC_WAIT_DATA; i++) { - spiReceive(mmcp->config->spip, 1, buf); - if (buf[0] == 0xFEU) { - uint32_t *wp; - - spiReceive(mmcp->config->spip, 16, buf); - bp = buf; - for (wp = &cxd[3]; wp >= cxd; wp--) { - *wp = ((uint32_t)bp[0] << 24U) | ((uint32_t)bp[1] << 16U) | - ((uint32_t)bp[2] << 8U) | (uint32_t)bp[3]; - bp += 4; - } - - /* CRC ignored then end of transaction. */ - spiIgnore(mmcp->config->spip, 2); - spiUnselect(mmcp->config->spip); - - return HAL_SUCCESS; - } - } - return HAL_FAILED; -} - -/** - * @brief Waits that the card reaches an idle state. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * - * @notapi - */ -static void sync(MMCDriver *mmcp) { - uint8_t buf[1]; - - spiSelect(mmcp->config->spip); - while (true) { - spiReceive(mmcp->config->spip, 1, buf); - if (buf[0] == 0xFFU) { - break; - } -#if MMC_NICE_WAITING == TRUE - /* Trying to be nice with the other threads.*/ - osalThreadSleepMilliseconds(1); -#endif - } - spiUnselect(mmcp->config->spip); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief MMC over SPI driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void mmcInit(void) { - -} - -/** - * @brief Initializes an instance. - * - * @param[out] mmcp pointer to the @p MMCDriver object - * - * @init - */ -void mmcObjectInit(MMCDriver *mmcp) { - - mmcp->vmt = &mmc_vmt; - mmcp->state = BLK_STOP; - mmcp->config = NULL; - mmcp->block_addresses = false; -} - -/** - * @brief Configures and activates the MMC peripheral. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @param[in] config pointer to the @p MMCConfig object. - * - * @api - */ -void mmcStart(MMCDriver *mmcp, const MMCConfig *config) { - - osalDbgCheck((mmcp != NULL) && (config != NULL)); - osalDbgAssert((mmcp->state == BLK_STOP) || (mmcp->state == BLK_ACTIVE), - "invalid state"); - - mmcp->config = config; - mmcp->state = BLK_ACTIVE; -} - -/** - * @brief Disables the MMC peripheral. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * - * @api - */ -void mmcStop(MMCDriver *mmcp) { - - osalDbgCheck(mmcp != NULL); - osalDbgAssert((mmcp->state == BLK_STOP) || (mmcp->state == BLK_ACTIVE), - "invalid state"); - - spiStop(mmcp->config->spip); - mmcp->state = BLK_STOP; -} - -/** - * @brief Performs the initialization procedure on the inserted card. - * @details This function should be invoked when a card is inserted and - * brings the driver in the @p MMC_READY state where it is possible - * to perform read and write operations. - * @note It is possible to invoke this function from the insertion event - * handler. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * - * @return The operation status. - * @retval HAL_SUCCESS the operation succeeded and the driver is now - * in the @p MMC_READY state. - * @retval HAL_FAILED the operation failed. - * - * @api - */ -bool mmcConnect(MMCDriver *mmcp) { - unsigned i; - uint8_t r3[4]; - - osalDbgCheck(mmcp != NULL); - - osalDbgAssert((mmcp->state == BLK_ACTIVE) || (mmcp->state == BLK_READY), - "invalid state"); - - /* Connection procedure in progress.*/ - mmcp->state = BLK_CONNECTING; - mmcp->block_addresses = false; - - /* Slow clock mode and 128 clock pulses.*/ - spiStart(mmcp->config->spip, mmcp->config->lscfg); - spiIgnore(mmcp->config->spip, 16); - - /* SPI mode selection.*/ - i = 0; - while (true) { - if (send_command_R1(mmcp, MMCSD_CMD_GO_IDLE_STATE, 0) == 0x01U) { - break; - } - if (++i >= MMC_CMD0_RETRY) { - goto failed; - } - osalThreadSleepMilliseconds(10); - } - - /* Try to detect if this is a high capacity card and switch to block - addresses if possible. - This method is based on "How to support SDC Ver2 and high capacity cards" - by ElmChan.*/ - if (send_command_R3(mmcp, MMCSD_CMD_SEND_IF_COND, - MMCSD_CMD8_PATTERN, r3) != 0x05U) { - - /* Switch to SDHC mode.*/ - i = 0; - while (true) { - /*lint -save -e9007 [13.5] Side effect unimportant.*/ - if ((send_command_R1(mmcp, MMCSD_CMD_APP_CMD, 0) == 0x01U) && - (send_command_R3(mmcp, MMCSD_CMD_APP_OP_COND, 0x400001AAU, r3) == 0x00U)) { - /*lint -restore*/ - break; - } - - if (++i >= MMC_ACMD41_RETRY) { - goto failed; - } - osalThreadSleepMilliseconds(10); - } - - /* Execute dedicated read on OCR register */ - (void) send_command_R3(mmcp, MMCSD_CMD_READ_OCR, 0, r3); - - /* Check if CCS is set in response. Card operates in block mode if set.*/ - if ((r3[0] & 0x40U) != 0U) { - mmcp->block_addresses = true; - } - } - - /* Initialization.*/ - i = 0; - while (true) { - uint8_t b = send_command_R1(mmcp, MMCSD_CMD_INIT, 0); - if (b == 0x00U) { - break; - } - if (b != 0x01U) { - goto failed; - } - if (++i >= MMC_CMD1_RETRY) { - goto failed; - } - osalThreadSleepMilliseconds(10); - } - - /* Initialization complete, full speed.*/ - spiStart(mmcp->config->spip, mmcp->config->hscfg); - - /* Setting block size.*/ - if (send_command_R1(mmcp, MMCSD_CMD_SET_BLOCKLEN, - MMCSD_BLOCK_SIZE) != 0x00U) { - goto failed; - } - - /* Determine capacity.*/ - if (read_CxD(mmcp, MMCSD_CMD_SEND_CSD, mmcp->csd)) { - goto failed; - } - - mmcp->capacity = _mmcsd_get_capacity(mmcp->csd); - if (mmcp->capacity == 0U) { - goto failed; - } - - if (read_CxD(mmcp, MMCSD_CMD_SEND_CID, mmcp->cid)) { - goto failed; - } - - mmcp->state = BLK_READY; - return HAL_SUCCESS; - - /* Connection failed, state reset to BLK_ACTIVE.*/ -failed: - spiStop(mmcp->config->spip); - mmcp->state = BLK_ACTIVE; - return HAL_FAILED; -} - -/** - * @brief Brings the driver in a state safe for card removal. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @return The operation status. - * - * @retval HAL_SUCCESS the operation succeeded and the driver is now - * in the @p MMC_INSERTED state. - * @retval HAL_FAILED the operation failed. - * - * @api - */ -bool mmcDisconnect(MMCDriver *mmcp) { - - osalDbgCheck(mmcp != NULL); - - osalSysLock(); - osalDbgAssert((mmcp->state == BLK_ACTIVE) || (mmcp->state == BLK_READY), - "invalid state"); - if (mmcp->state == BLK_ACTIVE) { - osalSysUnlock(); - return HAL_SUCCESS; - } - mmcp->state = BLK_DISCONNECTING; - osalSysUnlock(); - - /* Wait for the pending write operations to complete.*/ - spiStart(mmcp->config->spip, mmcp->config->hscfg); - sync(mmcp); - - spiStop(mmcp->config->spip); - mmcp->state = BLK_ACTIVE; - return HAL_SUCCESS; -} - -/** - * @brief Starts a sequential read. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @param[in] startblk first block to read - * - * @return The operation status. - * @retval HAL_SUCCESS the operation succeeded. - * @retval HAL_FAILED the operation failed. - * - * @api - */ -bool mmcStartSequentialRead(MMCDriver *mmcp, uint32_t startblk) { - - osalDbgCheck(mmcp != NULL); - osalDbgAssert(mmcp->state == BLK_READY, "invalid state"); - - /* Read operation in progress.*/ - mmcp->state = BLK_READING; - - /* (Re)starting the SPI in case it has been reprogrammed externally, it can - happen if the SPI bus is shared among multiple peripherals.*/ - spiStart(mmcp->config->spip, mmcp->config->hscfg); - spiSelect(mmcp->config->spip); - - if (mmcp->block_addresses) { - send_hdr(mmcp, MMCSD_CMD_READ_MULTIPLE_BLOCK, startblk); - } - else { - send_hdr(mmcp, MMCSD_CMD_READ_MULTIPLE_BLOCK, startblk * MMCSD_BLOCK_SIZE); - } - - if (recvr1(mmcp) != 0x00U) { - spiStop(mmcp->config->spip); - mmcp->state = BLK_READY; - return HAL_FAILED; - } - return HAL_SUCCESS; -} - -/** - * @brief Reads a block within a sequential read operation. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @param[out] buffer pointer to the read buffer - * - * @return The operation status. - * @retval HAL_SUCCESS the operation succeeded. - * @retval HAL_FAILED the operation failed. - * - * @api - */ -bool mmcSequentialRead(MMCDriver *mmcp, uint8_t *buffer) { - unsigned i; - - osalDbgCheck((mmcp != NULL) && (buffer != NULL)); - - if (mmcp->state != BLK_READING) { - return HAL_FAILED; - } - - for (i = 0; i < MMC_WAIT_DATA; i++) { - spiReceive(mmcp->config->spip, 1, buffer); - if (buffer[0] == 0xFEU) { - spiReceive(mmcp->config->spip, MMCSD_BLOCK_SIZE, buffer); - /* CRC ignored. */ - spiIgnore(mmcp->config->spip, 2); - return HAL_SUCCESS; - } - } - /* Timeout.*/ - spiUnselect(mmcp->config->spip); - spiStop(mmcp->config->spip); - mmcp->state = BLK_READY; - return HAL_FAILED; -} - -/** - * @brief Stops a sequential read gracefully. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * - * @return The operation status. - * @retval HAL_SUCCESS the operation succeeded. - * @retval HAL_FAILED the operation failed. - * - * @api - */ -bool mmcStopSequentialRead(MMCDriver *mmcp) { - static const uint8_t stopcmd[] = { - (uint8_t)(0x40U | MMCSD_CMD_STOP_TRANSMISSION), 0, 0, 0, 0, 1, 0xFF - }; - - osalDbgCheck(mmcp != NULL); - - if (mmcp->state != BLK_READING) { - return HAL_FAILED; - } - - spiSend(mmcp->config->spip, sizeof(stopcmd), stopcmd); -/* result = recvr1(mmcp) != 0x00U;*/ - /* Note, ignored r1 response, it can be not zero, unknown issue.*/ - (void) recvr1(mmcp); - - /* Read operation finished.*/ - spiUnselect(mmcp->config->spip); - mmcp->state = BLK_READY; - return HAL_SUCCESS; -} - -/** - * @brief Starts a sequential write. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @param[in] startblk first block to write - * - * @return The operation status. - * @retval HAL_SUCCESS the operation succeeded. - * @retval HAL_FAILED the operation failed. - * - * @api - */ -bool mmcStartSequentialWrite(MMCDriver *mmcp, uint32_t startblk) { - - osalDbgCheck(mmcp != NULL); - osalDbgAssert(mmcp->state == BLK_READY, "invalid state"); - - /* Write operation in progress.*/ - mmcp->state = BLK_WRITING; - - spiStart(mmcp->config->spip, mmcp->config->hscfg); - spiSelect(mmcp->config->spip); - if (mmcp->block_addresses) { - send_hdr(mmcp, MMCSD_CMD_WRITE_MULTIPLE_BLOCK, startblk); - } - else { - send_hdr(mmcp, MMCSD_CMD_WRITE_MULTIPLE_BLOCK, - startblk * MMCSD_BLOCK_SIZE); - } - - if (recvr1(mmcp) != 0x00U) { - spiStop(mmcp->config->spip); - mmcp->state = BLK_READY; - return HAL_FAILED; - } - return HAL_SUCCESS; -} - -/** - * @brief Writes a block within a sequential write operation. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @param[out] buffer pointer to the write buffer - * - * @return The operation status. - * @retval HAL_SUCCESS the operation succeeded. - * @retval HAL_FAILED the operation failed. - * - * @api - */ -bool mmcSequentialWrite(MMCDriver *mmcp, const uint8_t *buffer) { - static const uint8_t start[] = {0xFF, 0xFC}; - uint8_t b[1]; - - osalDbgCheck((mmcp != NULL) && (buffer != NULL)); - - if (mmcp->state != BLK_WRITING) { - return HAL_FAILED; - } - - spiSend(mmcp->config->spip, sizeof(start), start); /* Data prologue. */ - spiSend(mmcp->config->spip, MMCSD_BLOCK_SIZE, buffer);/* Data. */ - spiIgnore(mmcp->config->spip, 2); /* CRC ignored. */ - spiReceive(mmcp->config->spip, 1, b); - if ((b[0] & 0x1FU) == 0x05U) { - wait(mmcp); - return HAL_SUCCESS; - } - - /* Error.*/ - spiUnselect(mmcp->config->spip); - spiStop(mmcp->config->spip); - mmcp->state = BLK_READY; - return HAL_FAILED; -} - -/** - * @brief Stops a sequential write gracefully. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * - * @return The operation status. - * @retval HAL_SUCCESS the operation succeeded. - * @retval HAL_FAILED the operation failed. - * - * @api - */ -bool mmcStopSequentialWrite(MMCDriver *mmcp) { - static const uint8_t stop[] = {0xFD, 0xFF}; - - osalDbgCheck(mmcp != NULL); - - if (mmcp->state != BLK_WRITING) { - return HAL_FAILED; - } - - spiSend(mmcp->config->spip, sizeof(stop), stop); - spiUnselect(mmcp->config->spip); - - /* Write operation finished.*/ - mmcp->state = BLK_READY; - return HAL_SUCCESS; -} - -/** - * @brief Waits for card idle condition. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * - * @return The operation status. - * @retval HAL_SUCCESS the operation succeeded. - * @retval HAL_FAILED the operation failed. - * - * @api - */ -bool mmcSync(MMCDriver *mmcp) { - - osalDbgCheck(mmcp != NULL); - - if (mmcp->state != BLK_READY) { - return HAL_FAILED; - } - - /* Synchronization operation in progress.*/ - mmcp->state = BLK_SYNCING; - - spiStart(mmcp->config->spip, mmcp->config->hscfg); - sync(mmcp); - - /* Synchronization operation finished.*/ - mmcp->state = BLK_READY; - return HAL_SUCCESS; -} - -/** - * @brief Returns the media info. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @param[out] bdip pointer to a @p BlockDeviceInfo structure - * - * @return The operation status. - * @retval HAL_SUCCESS the operation succeeded. - * @retval HAL_FAILED the operation failed. - * - * @api - */ -bool mmcGetInfo(MMCDriver *mmcp, BlockDeviceInfo *bdip) { - - osalDbgCheck((mmcp != NULL) && (bdip != NULL)); - - if (mmcp->state != BLK_READY) { - return HAL_FAILED; - } - - bdip->blk_num = mmcp->capacity; - bdip->blk_size = MMCSD_BLOCK_SIZE; - - return HAL_SUCCESS; -} - -/** - * @brief Erases blocks. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @param[in] startblk starting block number - * @param[in] endblk ending block number - * - * @return The operation status. - * @retval HAL_SUCCESS the operation succeeded. - * @retval HAL_FAILED the operation failed. - * - * @api - */ -bool mmcErase(MMCDriver *mmcp, uint32_t startblk, uint32_t endblk) { - - osalDbgCheck((mmcp != NULL)); - - /* Erase operation in progress.*/ - mmcp->state = BLK_WRITING; - - /* Handling command differences between HC and normal cards.*/ - if (!mmcp->block_addresses) { - startblk *= MMCSD_BLOCK_SIZE; - endblk *= MMCSD_BLOCK_SIZE; - } - - if (send_command_R1(mmcp, MMCSD_CMD_ERASE_RW_BLK_START, startblk) != 0x00U) { - goto failed; - } - - if (send_command_R1(mmcp, MMCSD_CMD_ERASE_RW_BLK_END, endblk) != 0x00U) { - goto failed; - } - - if (send_command_R1(mmcp, MMCSD_CMD_ERASE, 0) != 0x00U) { - goto failed; - } - - mmcp->state = BLK_READY; - return HAL_SUCCESS; - - /* Command failed, state reset to BLK_ACTIVE.*/ -failed: - spiStop(mmcp->config->spip); - mmcp->state = BLK_READY; - return HAL_FAILED; -} - -#endif /* HAL_USE_MMC_SPI == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/src/pal.c b/firmware/ChibiOS_16/os/hal/src/pal.c deleted file mode 100644 index 1e63b9eb4c..0000000000 --- a/firmware/ChibiOS_16/os/hal/src/pal.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file pal.c - * @brief I/O Ports Abstraction Layer code. - * - * @addtogroup PAL - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_PAL == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Read from an I/O bus. - * @note The operation is not guaranteed to be atomic on all the - * architectures, for atomicity and/or portability reasons you may - * need to enclose port I/O operations between @p osalSysLock() and - * @p osalSysUnlock(). - * @note The function internally uses the @p palReadGroup() macro. The use - * of this function is preferred when you value code size, readability - * and error checking over speed. - * @note The function can be called from any context. - * - * @param[in] bus the I/O bus, pointer to a @p IOBus structure - * @return The bus logical states. - * - * @special - */ -ioportmask_t palReadBus(IOBus *bus) { - - osalDbgCheck((bus != NULL) && (bus->offset < PAL_IOPORTS_WIDTH)); - - return palReadGroup(bus->portid, bus->mask, bus->offset); -} - -/** - * @brief Write to an I/O bus. - * @note The operation is not guaranteed to be atomic on all the - * architectures, for atomicity and/or portability reasons you may - * need to enclose port I/O operations between @p osalSysLock() and - * @p osalSysUnlock(). - * @note The default implementation is non atomic and not necessarily - * optimal. Low level drivers may optimize the function by using - * specific hardware or coding. - * @note The function can be called from any context. - * - * @param[in] bus the I/O bus, pointer to a @p IOBus structure - * @param[in] bits the bits to be written on the I/O bus. Values exceeding - * the bus width are masked so most significant bits are - * lost. - * - * @special - */ -void palWriteBus(IOBus *bus, ioportmask_t bits) { - - osalDbgCheck((bus != NULL) && (bus->offset < PAL_IOPORTS_WIDTH)); - - palWriteGroup(bus->portid, bus->mask, bus->offset, bits); -} - -/** - * @brief Programs a bus with the specified mode. - * @note The operation is not guaranteed to be atomic on all the - * architectures, for atomicity and/or portability reasons you may - * need to enclose port I/O operations between @p osalSysLock() and - * @p osalSysUnlock(). - * @note The default implementation is non atomic and not necessarily - * optimal. Low level drivers may optimize the function by using - * specific hardware or coding. - * @note The function can be called from any context. - * - * @param[in] bus the I/O bus, pointer to a @p IOBus structure - * @param[in] mode the mode - * - * @special - */ -void palSetBusMode(IOBus *bus, iomode_t mode) { - - osalDbgCheck((bus != NULL) && (bus->offset < PAL_IOPORTS_WIDTH)); - - palSetGroupMode(bus->portid, bus->mask, bus->offset, mode); -} - -#endif /* HAL_USE_PAL == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/src/pwm.c b/firmware/ChibiOS_16/os/hal/src/pwm.c deleted file mode 100644 index 5dcbb72237..0000000000 --- a/firmware/ChibiOS_16/os/hal/src/pwm.c +++ /dev/null @@ -1,309 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file pwm.c - * @brief PWM Driver code. - * - * @addtogroup PWM - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_PWM == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief PWM Driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void pwmInit(void) { - - pwm_lld_init(); -} - -/** - * @brief Initializes the standard part of a @p PWMDriver structure. - * - * @param[out] pwmp pointer to a @p PWMDriver object - * - * @init - */ -void pwmObjectInit(PWMDriver *pwmp) { - - pwmp->state = PWM_STOP; - pwmp->config = NULL; - pwmp->enabled = 0; - pwmp->channels = 0; -#if defined(PWM_DRIVER_EXT_INIT_HOOK) - PWM_DRIVER_EXT_INIT_HOOK(pwmp); -#endif -} - -/** - * @brief Configures and activates the PWM peripheral. - * @note Starting a driver that is already in the @p PWM_READY state - * disables all the active channels. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] config pointer to a @p PWMConfig object - * - * @api - */ -void pwmStart(PWMDriver *pwmp, const PWMConfig *config) { - - osalDbgCheck((pwmp != NULL) && (config != NULL)); - - osalSysLock(); - osalDbgAssert((pwmp->state == PWM_STOP) || (pwmp->state == PWM_READY), - "invalid state"); - pwmp->config = config; - pwmp->period = config->period; - pwm_lld_start(pwmp); - pwmp->enabled = 0; - pwmp->state = PWM_READY; - osalSysUnlock(); -} - -/** - * @brief Deactivates the PWM peripheral. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * - * @api - */ -void pwmStop(PWMDriver *pwmp) { - - osalDbgCheck(pwmp != NULL); - - osalSysLock(); - osalDbgAssert((pwmp->state == PWM_STOP) || (pwmp->state == PWM_READY), - "invalid state"); - pwm_lld_stop(pwmp); - pwmp->enabled = 0; - pwmp->state = PWM_STOP; - osalSysUnlock(); -} - -/** - * @brief Changes the period the PWM peripheral. - * @details This function changes the period of a PWM unit that has already - * been activated using @p pwmStart(). - * @pre The PWM unit must have been activated using @p pwmStart(). - * @post The PWM unit period is changed to the new value. - * @note If a period is specified that is shorter than the pulse width - * programmed in one of the channels then the behavior is not - * guaranteed. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] period new cycle time in ticks - * - * @api - */ -void pwmChangePeriod(PWMDriver *pwmp, pwmcnt_t period) { - - osalDbgCheck(pwmp != NULL); - - osalSysLock(); - osalDbgAssert(pwmp->state == PWM_READY, "invalid state"); - pwmChangePeriodI(pwmp, period); - osalSysUnlock(); -} - -/** - * @brief Enables a PWM channel. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @post The channel is active using the specified configuration. - * @note Depending on the hardware implementation this function has - * effect starting on the next cycle (recommended implementation) - * or immediately (fallback implementation). - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier (0...channels-1) - * @param[in] width PWM pulse width as clock pulses number - * - * @api - */ -void pwmEnableChannel(PWMDriver *pwmp, - pwmchannel_t channel, - pwmcnt_t width) { - - osalDbgCheck((pwmp != NULL) && (channel < pwmp->channels)); - - osalSysLock(); - - osalDbgAssert(pwmp->state == PWM_READY, "not ready"); - - pwmEnableChannelI(pwmp, channel, width); - - osalSysUnlock(); -} - -/** - * @brief Disables a PWM channel and its notification. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @post The channel is disabled and its output line returned to the - * idle state. - * @note Depending on the hardware implementation this function has - * effect starting on the next cycle (recommended implementation) - * or immediately (fallback implementation). - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier (0...channels-1) - * - * @api - */ -void pwmDisableChannel(PWMDriver *pwmp, pwmchannel_t channel) { - - osalDbgCheck((pwmp != NULL) && (channel < pwmp->channels)); - - osalSysLock(); - - osalDbgAssert(pwmp->state == PWM_READY, "not ready"); - - pwmDisableChannelI(pwmp, channel); - - osalSysUnlock(); -} - -/** - * @brief Enables the periodic activation edge notification. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @note If the notification is already enabled then the call has no effect. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * - * @api - */ -void pwmEnablePeriodicNotification(PWMDriver *pwmp) { - - osalDbgCheck(pwmp != NULL); - - osalSysLock(); - - osalDbgAssert(pwmp->state == PWM_READY, "not ready"); - osalDbgAssert(pwmp->config->callback != NULL, "undefined periodic callback"); - - pwmEnablePeriodicNotificationI(pwmp); - - osalSysUnlock(); -} - -/** - * @brief Disables the periodic activation edge notification. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @note If the notification is already disabled then the call has no effect. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * - * @api - */ -void pwmDisablePeriodicNotification(PWMDriver *pwmp) { - - osalDbgCheck(pwmp != NULL); - - osalSysLock(); - - osalDbgAssert(pwmp->state == PWM_READY, "not ready"); - osalDbgAssert(pwmp->config->callback != NULL, "undefined periodic callback"); - - pwmDisablePeriodicNotificationI(pwmp); - - osalSysUnlock(); -} - -/** - * @brief Enables a channel de-activation edge notification. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @pre The channel must have been activated using @p pwmEnableChannel(). - * @note If the notification is already enabled then the call has no effect. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier (0...channels-1) - * - * @api - */ -void pwmEnableChannelNotification(PWMDriver *pwmp, pwmchannel_t channel) { - - osalDbgCheck((pwmp != NULL) && (channel < pwmp->channels)); - - osalSysLock(); - - osalDbgAssert(pwmp->state == PWM_READY, "not ready"); - osalDbgAssert((pwmp->enabled & ((pwmchnmsk_t)1U << (pwmchnmsk_t)channel)) != 0U, - "channel not enabled"); - osalDbgAssert(pwmp->config->channels[channel].callback != NULL, - "undefined channel callback"); - - pwmEnableChannelNotificationI(pwmp, channel); - - osalSysUnlock(); -} - -/** - * @brief Disables a channel de-activation edge notification. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @pre The channel must have been activated using @p pwmEnableChannel(). - * @note If the notification is already disabled then the call has no effect. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier (0...channels-1) - * - * @api - */ -void pwmDisableChannelNotification(PWMDriver *pwmp, pwmchannel_t channel) { - - osalDbgCheck((pwmp != NULL) && (channel < pwmp->channels)); - - osalSysLock(); - - osalDbgAssert(pwmp->state == PWM_READY, "not ready"); - osalDbgAssert((pwmp->enabled & ((pwmchnmsk_t)1U << (pwmchnmsk_t)channel)) != 0U, - "channel not enabled"); - osalDbgAssert(pwmp->config->channels[channel].callback != NULL, - "undefined channel callback"); - - pwmDisableChannelNotificationI(pwmp, channel); - - osalSysUnlock(); -} - -#endif /* HAL_USE_PWM == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/src/rtc.c b/firmware/ChibiOS_16/os/hal/src/rtc.c deleted file mode 100644 index 34f5c1cb00..0000000000 --- a/firmware/ChibiOS_16/os/hal/src/rtc.c +++ /dev/null @@ -1,321 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Concepts and parts of this file have been contributed by Uladzimir Pylinsky - aka barthess. - */ - -/** - * @file rtc.c - * @brief RTC Driver code. - * - * @addtogroup RTC - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_RTC == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/* - * Lookup table with months' length - */ -static const uint8_t month_len[12] = { - 31, 30, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief RTC Driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void rtcInit(void) { - - rtc_lld_init(); -} - -/** - * @brief Initializes a generic RTC driver object. - * @details The HW dependent part of the initialization has to be performed - * outside, usually in the hardware initialization code. - * - * @param[out] rtcp pointer to RTC driver structure - * - * @init - */ -void rtcObjectInit(RTCDriver *rtcp) { - -#if RTC_HAS_STORAGE == TRUE - rtcp->vmt = &_rtc_lld_vmt; -#else - (void)rtcp; -#endif -} - -/** - * @brief Set current time. - * @note This function can be called from any context but limitations - * could be imposed by the low level implementation. It is - * guaranteed that the function can be called from thread - * context. - * @note The function can be reentrant or not reentrant depending on - * the low level implementation. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[in] timespec pointer to a @p RTCDateTime structure - * - * @special - */ -void rtcSetTime(RTCDriver *rtcp, const RTCDateTime *timespec) { - - osalDbgCheck((rtcp != NULL) && (timespec != NULL)); - - rtc_lld_set_time(rtcp, timespec); -} - -/** - * @brief Get current time. - * @note This function can be called from any context but limitations - * could be imposed by the low level implementation. It is - * guaranteed that the function can be called from thread - * context. - * @note The function can be reentrant or not reentrant depending on - * the low level implementation. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[out] timespec pointer to a @p RTCDateTime structure - * - * @special - */ -void rtcGetTime(RTCDriver *rtcp, RTCDateTime *timespec) { - - osalDbgCheck((rtcp != NULL) && (timespec != NULL)); - - rtc_lld_get_time(rtcp, timespec); -} - -#if (RTC_ALARMS > 0) || defined(__DOXYGEN__) -/** - * @brief Set alarm time. - * @note This function can be called from any context but limitations - * could be imposed by the low level implementation. It is - * guaranteed that the function can be called from thread - * context. - * @note The function can be reentrant or not reentrant depending on - * the low level implementation. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[in] alarm alarm identifier - * @param[in] alarmspec pointer to a @p RTCAlarm structure or @p NULL - * - * @special - */ -void rtcSetAlarm(RTCDriver *rtcp, - rtcalarm_t alarm, - const RTCAlarm *alarmspec) { - - osalDbgCheck((rtcp != NULL) && (alarm < (rtcalarm_t)RTC_ALARMS)); - - rtc_lld_set_alarm(rtcp, alarm, alarmspec); -} - -/** - * @brief Get current alarm. - * @note If an alarm has not been set then the returned alarm specification - * is not meaningful. - * @note This function can be called from any context but limitations - * could be imposed by the low level implementation. It is - * guaranteed that the function can be called from thread - * context. - * @note The function can be reentrant or not reentrant depending on - * the low level implementation. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[in] alarm alarm identifier - * @param[out] alarmspec pointer to a @p RTCAlarm structure - * - * @special - */ -void rtcGetAlarm(RTCDriver *rtcp, - rtcalarm_t alarm, - RTCAlarm *alarmspec) { - - osalDbgCheck((rtcp != NULL) && - (alarm < (rtcalarm_t)RTC_ALARMS) && - (alarmspec != NULL)); - - rtc_lld_get_alarm(rtcp, alarm, alarmspec); -} -#endif /* RTC_ALARMS > 0 */ - -#if (RTC_SUPPORTS_CALLBACKS == TRUE) || defined(__DOXYGEN__) -/** - * @brief Enables or disables RTC callbacks. - * @details This function enables or disables the callback, use a @p NULL - * pointer in order to disable it. - * @note This function can be called from any context but limitations - * could be imposed by the low level implementation. It is - * guaranteed that the function can be called from thread - * context. - * @note The function can be reentrant or not reentrant depending on - * the low level implementation. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[in] callback callback function pointer or @p NULL - * - * @special - */ -void rtcSetCallback(RTCDriver *rtcp, rtccb_t callback) { - - osalDbgCheck(rtcp != NULL); - - rtc_lld_set_callback(rtcp, callback); -} -#endif /* RTC_SUPPORTS_CALLBACKS == TRUE */ - -/** - * @brief Convert @p RTCDateTime to broken-down time structure. - * - * @param[in] timespec pointer to a @p RTCDateTime structure - * @param[out] timp pointer to a broken-down time structure - * @param[out] tv_msec pointer to milliseconds value or @p NULL - * - * @api - */ -void rtcConvertDateTimeToStructTm(const RTCDateTime *timespec, - struct tm *timp, - uint32_t *tv_msec) { - int sec; - - timp->tm_year = (int)timespec->year + (1980 - 1900); - timp->tm_mon = (int)timespec->month - 1; - timp->tm_mday = (int)timespec->day; - timp->tm_isdst = (int)timespec->dstflag; - timp->tm_wday = (int)timespec->dayofweek - 1; - - sec = (int)timespec->millisecond / 1000; - timp->tm_hour = sec / 3600; - sec %= 3600; - timp->tm_min = sec / 60; - timp->tm_sec = sec % 60; - - if (NULL != tv_msec) { - *tv_msec = (uint32_t)timespec->millisecond % 1000U; - } -} - -/** - * @brief Convert broken-down time structure to @p RTCDateTime. - * - * @param[in] timp pointer to a broken-down time structure - * @param[in] tv_msec milliseconds value - * @param[out] timespec pointer to a @p RTCDateTime structure - * - * @api - */ -void rtcConvertStructTmToDateTime(const struct tm *timp, - uint32_t tv_msec, - RTCDateTime *timespec) { - - /*lint -save -e9034 [10.4] Verified assignments to bit fields.*/ - timespec->year = (uint32_t)timp->tm_year - (1980U - 1900U); - timespec->month = (uint32_t)timp->tm_mon + 1U; - timespec->day = (uint32_t)timp->tm_mday; - timespec->dayofweek = (uint32_t)timp->tm_wday + 1U; - if (-1 == timp->tm_isdst) { - timespec->dstflag = 0U; /* set zero if dst is unknown */ - } - else { - timespec->dstflag = (uint32_t)timp->tm_isdst; - } - /*lint -restore*/ - /*lint -save -e9033 [10.8] Verified assignments to bit fields.*/ - timespec->millisecond = tv_msec + (uint32_t)(((timp->tm_hour * 3600) + - (timp->tm_min * 60) + - timp->tm_sec) * 1000); - /*lint -restore*/ -} - -/** - * @brief Get current time in format suitable for usage in FAT file system. - * @note The information about day of week and DST is lost in DOS - * format, the second field loses its least significant bit. - * - * @param[out] timespec pointer to a @p RTCDateTime structure - * @return FAT date/time value. - * - * @api - */ -uint32_t rtcConvertDateTimeToFAT(const RTCDateTime *timespec) { - uint32_t fattime; - uint32_t sec, min, hour, day, month; - - sec = timespec->millisecond / 1000U; - hour = sec / 3600U; - sec %= 3600U; - min = sec / 60U; - sec %= 60U; - day = timespec->day; - month = timespec->month; - - /* handle DST flag */ - if (1U == timespec->dstflag) { - hour += 1U; - if (hour == 24U) { - hour = 0U; - day += 1U; - if (day > month_len[month - 1U]) { - day = 1U; - month += 1U; - } - } - } - - fattime = sec >> 1U; - fattime |= min << 5U; - fattime |= hour << 11U; - fattime |= day << 16U; - fattime |= month << 21U; - fattime |= (uint32_t)timespec->year << 25U; - - return fattime; -} - -#endif /* HAL_USE_RTC == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/src/sdc.c b/firmware/ChibiOS_16/os/hal/src/sdc.c deleted file mode 100644 index 4d62f69929..0000000000 --- a/firmware/ChibiOS_16/os/hal/src/sdc.c +++ /dev/null @@ -1,1005 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file sdc.c - * @brief SDC Driver code. - * - * @addtogroup SDC - * @{ - */ - -#include - -#include "hal.h" - -#if (HAL_USE_SDC == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/** - * @brief MMC switch mode. - */ -typedef enum { - MMC_SWITCH_COMMAND_SET = 0, - MMC_SWITCH_SET_BITS = 1, - MMC_SWITCH_CLEAR_BITS = 2, - MMC_SWITCH_WRITE_BYTE = 3 -} mmc_switch_t; - -/** - * @brief SDC switch mode. - */ -typedef enum { - SD_SWITCH_CHECK = 0, - SD_SWITCH_SET = 1 -} sd_switch_t; - -/** - * @brief SDC switch function. - */ -typedef enum { - SD_SWITCH_FUNCTION_SPEED = 0, - SD_SWITCH_FUNCTION_CMD_SYSTEM = 1, - SD_SWITCH_FUNCTION_DRIVER_STRENGTH = 2, - SD_SWITCH_FUNCTION_CURRENT_LIMIT = 3 -} sd_switch_function_t; - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief Virtual methods table. - */ -static const struct SDCDriverVMT sdc_vmt = { - (bool (*)(void *))sdc_lld_is_card_inserted, - (bool (*)(void *))sdc_lld_is_write_protected, - (bool (*)(void *))sdcConnect, - (bool (*)(void *))sdcDisconnect, - (bool (*)(void *, uint32_t, uint8_t *, uint32_t))sdcRead, - (bool (*)(void *, uint32_t, const uint8_t *, uint32_t))sdcWrite, - (bool (*)(void *))sdcSync, - (bool (*)(void *, BlockDeviceInfo *))sdcGetInfo -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ -/** - * @brief Detects card mode. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @notapi - */ -static bool mode_detect(SDCDriver *sdcp) { - uint32_t resp[1]; - - /* V2.0 cards detection.*/ - if (!sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_SEND_IF_COND, - MMCSD_CMD8_PATTERN, resp)) { - sdcp->cardmode = SDC_MODE_CARDTYPE_SDV20; - /* Voltage verification.*/ - if (((resp[0] >> 8U) & 0xFU) != 1U) { - return HAL_FAILED; - } - if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_APP_CMD, 0, resp) || - MMCSD_R1_ERROR(resp[0])) { - return HAL_FAILED; - } - } - else { - /* MMC or SD V1.1 detection.*/ - if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_APP_CMD, 0, resp) || - MMCSD_R1_ERROR(resp[0])) { - sdcp->cardmode = SDC_MODE_CARDTYPE_MMC; - } - else { - sdcp->cardmode = SDC_MODE_CARDTYPE_SDV11; - - /* Reset error flag illegal command.*/ - sdc_lld_send_cmd_none(sdcp, MMCSD_CMD_GO_IDLE_STATE, 0); - } - } - - return HAL_SUCCESS; -} - -/** - * @brief Init procedure for MMC. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @notapi - */ -static bool mmc_init(SDCDriver *sdcp) { - uint32_t ocr; - unsigned i; - uint32_t resp[1]; - - ocr = 0xC0FF8000U; - i = 0; - while (true) { - if (sdc_lld_send_cmd_short(sdcp, MMCSD_CMD_INIT, ocr, resp)) { - return HAL_FAILED; - } - if ((resp[0] & 0x80000000U) != 0U) { - if ((resp[0] & 0x40000000U) != 0U) { - sdcp->cardmode |= SDC_MODE_HIGH_CAPACITY; - } - break; - } - if (++i >= (unsigned)SDC_INIT_RETRY) { - return HAL_FAILED; - } - osalThreadSleepMilliseconds(10); - } - - return HAL_SUCCESS; -} - -/** - * @brief Init procedure for SDC. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @notapi - */ -static bool sdc_init(SDCDriver *sdcp) { - unsigned i; - uint32_t ocr; - uint32_t resp[1]; - - if ((sdcp->cardmode & SDC_MODE_CARDTYPE_MASK) == SDC_MODE_CARDTYPE_SDV20) { - ocr = 0xC0100000U; - } - else { - ocr = 0x80100000U; - } - - i = 0; - while (true) { - if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_APP_CMD, 0, resp) || - MMCSD_R1_ERROR(resp[0])) { - return HAL_FAILED; - } - if (sdc_lld_send_cmd_short(sdcp, MMCSD_CMD_APP_OP_COND, ocr, resp)) { - return HAL_FAILED; - } - if ((resp[0] & 0x80000000U) != 0U) { - if ((resp[0] & 0x40000000U) != 0U) { - sdcp->cardmode |= SDC_MODE_HIGH_CAPACITY; - } - break; - } - if (++i >= (unsigned)SDC_INIT_RETRY) { - return HAL_FAILED; - } - osalThreadSleepMilliseconds(10); - } - - return HAL_SUCCESS; -} - -/** - * @brief Constructs CMD6 argument for MMC. - * - * @param[in] access EXT_CSD access mode - * @param[in] idx EXT_CSD byte number - * @param[in] value value to be written in target field - * @param[in] cmd_set switch current command set - * - * @return CMD6 argument. - * - * @notapi - */ -static uint32_t mmc_cmd6_construct(mmc_switch_t access, uint32_t idx, - uint32_t value, uint32_t cmd_set) { - - osalDbgAssert(idx <= 191U, "This field is not writable"); - osalDbgAssert(cmd_set < 8U, "This field has only 3 bits"); - - return ((uint32_t)access << 24U) | (idx << 16U) | (value << 8U) | cmd_set; -} - -/** - * @brief Constructs CMD6 argument for SDC. - * - * @param[in] mode switch/test mode - * @param[in] function function number to be switched - * @param[in] value value to be written in target function - * - * @return CMD6 argument. - * - * @notapi - */ -static uint32_t sdc_cmd6_construct(sd_switch_t mode, - sd_switch_function_t function, - uint32_t value) { - uint32_t ret = 0xFFFFFF; - - osalDbgAssert((value < 16U), "This field has only 4 bits"); - - ret &= ~((uint32_t)0xFU << ((uint32_t)function * 4U)); - ret |= value << ((uint32_t)function * 4U); - return ret | ((uint32_t)mode << 31U); -} - -/** - * @brief Extracts information from CMD6 answer. - * - * @param[in] function function number to be switched - * @param[in] buf buffer with answer - * - * @return extracted answer. - * - * @notapi - */ -static uint16_t sdc_cmd6_extract_info(sd_switch_function_t function, - const uint8_t *buf) { - - unsigned start = 12U - ((unsigned)function * 2U); - - return ((uint16_t)buf[start] << 8U) | (uint16_t)buf[start + 1U]; -} - -/** - * @brief Checks status after switching using CMD6. - * - * @param[in] function function number to be switched - * @param[in] buf buffer with answer - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @notapi - */ -static bool sdc_cmd6_check_status(sd_switch_function_t function, - const uint8_t *buf) { - - uint32_t tmp; - uint32_t status; - - tmp = ((uint32_t)buf[14] << 16U) | - ((uint32_t)buf[15] << 8U) | - (uint32_t)buf[16]; - status = (tmp >> ((uint32_t)function * 4U)) & 0xFU; - if (0xFU != status) { - return HAL_SUCCESS; - } - return HAL_FAILED; -} - -/** - * @brief Reads supported bus clock and switch SDC to appropriate mode. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[out] clk pointer to clock enum - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @notapi - */ -static bool sdc_detect_bus_clk(SDCDriver *sdcp, sdcbusclk_t *clk) { - uint32_t cmdarg; - const size_t N = 64; - uint8_t tmp[N]; - - /* Safe default.*/ - *clk = SDC_CLK_25MHz; - - /* Looks like only "high capacity" cards produce meaningful results during - this clock detection procedure.*/ - if (0U == _mmcsd_get_slice(sdcp->csd, MMCSD_CSD_10_CSD_STRUCTURE_SLICE)) { - *clk = SDC_CLK_25MHz; - return HAL_SUCCESS; - } - - /* Read switch functions' register.*/ - if (sdc_lld_read_special(sdcp, tmp, N, MMCSD_CMD_SWITCH, 0)) { - return HAL_FAILED; - } - - /* Check card capabilities parsing acquired data.*/ - if ((sdc_cmd6_extract_info(SD_SWITCH_FUNCTION_SPEED, tmp) & 2U) == 2U) { - /* Construct command to set the bus speed.*/ - cmdarg = sdc_cmd6_construct(SD_SWITCH_SET, SD_SWITCH_FUNCTION_SPEED, 1); - - /* Write constructed command and read operation status in single call.*/ - if (sdc_lld_read_special(sdcp, tmp, N, MMCSD_CMD_SWITCH, cmdarg)) { - return HAL_FAILED; - } - - /* Check card answer for success status bits.*/ - if (HAL_SUCCESS == sdc_cmd6_check_status(SD_SWITCH_FUNCTION_SPEED, tmp)) { - *clk = SDC_CLK_50MHz; - } - else { - *clk = SDC_CLK_25MHz; - } - } - - return HAL_SUCCESS; -} - -/** - * @brief Reads supported bus clock and switch MMC to appropriate mode. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[out] clk pointer to clock enum - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @notapi - */ -static bool mmc_detect_bus_clk(SDCDriver *sdcp, sdcbusclk_t *clk) { - uint32_t cmdarg; - uint32_t resp[1]; - uint8_t *scratchpad = sdcp->config->scratchpad; - - /* Safe default.*/ - *clk = SDC_CLK_25MHz; - - /* Use safe default when there is no space for data.*/ - if (NULL == scratchpad) { - return HAL_SUCCESS; - } - - cmdarg = mmc_cmd6_construct(MMC_SWITCH_WRITE_BYTE, 185, 1, 0); - if (!(sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_SWITCH, cmdarg, resp) || - MMCSD_R1_ERROR(resp[0]))) { - *clk = SDC_CLK_50MHz; - } - - return HAL_SUCCESS; -} - -/** - * @brief Reads supported bus clock and switch card to appropriate mode. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[out] clk pointer to clock enum - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @notapi - */ -static bool detect_bus_clk(SDCDriver *sdcp, sdcbusclk_t *clk) { - - if (SDC_MODE_CARDTYPE_MMC == (sdcp->cardmode & SDC_MODE_CARDTYPE_MASK)) { - return mmc_detect_bus_clk(sdcp, clk); - } - return sdc_detect_bus_clk(sdcp, clk); -} - -/** - * @brief Sets bus width for SDC. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @notapi - */ -static bool sdc_set_bus_width(SDCDriver *sdcp) { - uint32_t resp[1]; - - if (SDC_MODE_1BIT == sdcp->config->bus_width) { - /* Nothing to do. Bus is already in 1bit mode.*/ - return HAL_SUCCESS; - } - else if (SDC_MODE_4BIT == sdcp->config->bus_width) { - sdc_lld_set_bus_mode(sdcp, SDC_MODE_4BIT); - if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_APP_CMD, sdcp->rca, resp) || - MMCSD_R1_ERROR(resp[0])) { - return HAL_FAILED; - } - - if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_SET_BUS_WIDTH, 2, resp) || - MMCSD_R1_ERROR(resp[0])) { - return HAL_FAILED; - } - } - else { - /* SD card does not support 8bit bus.*/ - return HAL_FAILED; - } - - return HAL_SUCCESS; -} - -/** - * @brief Sets bus width for MMC. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @notapi - */ -static bool mmc_set_bus_width(SDCDriver *sdcp) { - uint32_t resp[1]; - uint32_t cmdarg = mmc_cmd6_construct(MMC_SWITCH_WRITE_BYTE, 183, 0, 0); - - switch(sdcp->config->bus_width){ - case SDC_MODE_1BIT: - /* Nothing to do. Bus is already in 1bit mode.*/ - return HAL_SUCCESS; - case SDC_MODE_4BIT: - cmdarg = mmc_cmd6_construct(MMC_SWITCH_WRITE_BYTE, 183, 1, 0); - break; - case SDC_MODE_8BIT: - cmdarg = mmc_cmd6_construct(MMC_SWITCH_WRITE_BYTE, 183, 2, 0); - break; - default: - osalDbgAssert(false, "unexpected case"); - break; - } - - sdc_lld_set_bus_mode(sdcp, sdcp->config->bus_width); - if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_SWITCH, cmdarg, resp) || - MMCSD_R1_ERROR(resp[0])) { - return HAL_FAILED; - } - - return HAL_SUCCESS; -} - -/** - * @brief Wait for the card to complete pending operations. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @notapi - */ -bool _sdc_wait_for_transfer_state(SDCDriver *sdcp) { - uint32_t resp[1]; - - while (true) { - if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_SEND_STATUS, - sdcp->rca, resp) || - MMCSD_R1_ERROR(resp[0])) { - return HAL_FAILED; - } - - switch (MMCSD_R1_STS(resp[0])) { - case MMCSD_STS_TRAN: - return HAL_SUCCESS; - case MMCSD_STS_DATA: - case MMCSD_STS_RCV: - case MMCSD_STS_PRG: -#if SDC_NICE_WAITING == TRUE - osalThreadSleepMilliseconds(1); -#endif - continue; - default: - /* The card should have been initialized so any other state is not - valid and is reported as an error.*/ - return HAL_FAILED; - } - } -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief SDC Driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void sdcInit(void) { - - sdc_lld_init(); -} - -/** - * @brief Initializes the standard part of a @p SDCDriver structure. - * - * @param[out] sdcp pointer to the @p SDCDriver object - * - * @init - */ -void sdcObjectInit(SDCDriver *sdcp) { - - sdcp->vmt = &sdc_vmt; - sdcp->state = BLK_STOP; - sdcp->errors = SDC_NO_ERROR; - sdcp->config = NULL; - sdcp->capacity = 0; -} - -/** - * @brief Configures and activates the SDC peripheral. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] config pointer to the @p SDCConfig object, can be @p NULL if - * the driver supports a default configuration or - * requires no configuration - * - * @api - */ -void sdcStart(SDCDriver *sdcp, const SDCConfig *config) { - - osalDbgCheck(sdcp != NULL); - - osalSysLock(); - osalDbgAssert((sdcp->state == BLK_STOP) || (sdcp->state == BLK_ACTIVE), - "invalid state"); - sdcp->config = config; - sdc_lld_start(sdcp); - sdcp->state = BLK_ACTIVE; - osalSysUnlock(); -} - -/** - * @brief Deactivates the SDC peripheral. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @api - */ -void sdcStop(SDCDriver *sdcp) { - - osalDbgCheck(sdcp != NULL); - - osalSysLock(); - osalDbgAssert((sdcp->state == BLK_STOP) || (sdcp->state == BLK_ACTIVE), - "invalid state"); - sdc_lld_stop(sdcp); - sdcp->state = BLK_STOP; - osalSysUnlock(); -} - -/** - * @brief Performs the initialization procedure on the inserted card. - * @details This function should be invoked when a card is inserted and - * brings the driver in the @p BLK_READY state where it is possible - * to perform read and write operations. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @api - */ -bool sdcConnect(SDCDriver *sdcp) { - uint32_t resp[1]; - sdcbusclk_t clk = SDC_CLK_25MHz; - - osalDbgCheck(sdcp != NULL); - osalDbgAssert((sdcp->state == BLK_ACTIVE) || (sdcp->state == BLK_READY), - "invalid state"); - - /* Connection procedure in progress.*/ - sdcp->state = BLK_CONNECTING; - - /* Card clock initialization.*/ - sdc_lld_start_clk(sdcp); - - /* Enforces the initial card state.*/ - sdc_lld_send_cmd_none(sdcp, MMCSD_CMD_GO_IDLE_STATE, 0); - - /* Detect card type.*/ - if (HAL_FAILED == mode_detect(sdcp)) { - goto failed; - } - - /* Perform specific initialization procedure.*/ - if ((sdcp->cardmode & SDC_MODE_CARDTYPE_MASK) == SDC_MODE_CARDTYPE_MMC) { - if (HAL_FAILED == mmc_init(sdcp)) { - goto failed; - } - } - else { - if (HAL_FAILED == sdc_init(sdcp)) { - goto failed; - } - } - - /* Reads CID.*/ - if (sdc_lld_send_cmd_long_crc(sdcp, MMCSD_CMD_ALL_SEND_CID, 0, sdcp->cid)) { - goto failed; - } - - /* Asks for the RCA.*/ - if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_SEND_RELATIVE_ADDR, - 0, &sdcp->rca)) { - goto failed; - } - - /* Reads CSD.*/ - if (sdc_lld_send_cmd_long_crc(sdcp, MMCSD_CMD_SEND_CSD, - sdcp->rca, sdcp->csd)) { - goto failed; - } - - /* Selects the card for operations.*/ - if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_SEL_DESEL_CARD, - sdcp->rca, resp)) { - goto failed; - } - - /* Switches to high speed.*/ - if (HAL_SUCCESS != detect_bus_clk(sdcp, &clk)) { - goto failed; - } - sdc_lld_set_data_clk(sdcp, clk); - - /* Reads extended CSD if needed and possible.*/ - if (SDC_MODE_CARDTYPE_MMC == (sdcp->cardmode & SDC_MODE_CARDTYPE_MASK)) { - - /* The card is a MMC, checking if it is a large device.*/ - if (_mmcsd_get_slice(sdcp->csd, MMCSD_CSD_MMC_CSD_STRUCTURE_SLICE) > 1U) { - uint8_t *ext_csd = sdcp->config->scratchpad; - - /* Size detection requires the buffer.*/ - if (NULL == ext_csd) { - goto failed; - } - - if(sdc_lld_read_special(sdcp, ext_csd, 512, MMCSD_CMD_SEND_EXT_CSD, 0)) { - goto failed; - } - - /* Capacity from the EXT_CSD.*/ - sdcp->capacity = _mmcsd_get_capacity_ext(ext_csd); - } - else { - /* Capacity from the normal CSD.*/ - sdcp->capacity = _mmcsd_get_capacity(sdcp->csd); - } - } - else { - /* The card is an SDC, capacity from the normal CSD.*/ - sdcp->capacity = _mmcsd_get_capacity(sdcp->csd); - } - - /* Block length fixed at 512 bytes.*/ - if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_SET_BLOCKLEN, - MMCSD_BLOCK_SIZE, resp) || - MMCSD_R1_ERROR(resp[0])) { - goto failed; - } - - /* Switches to wide bus mode.*/ - switch (sdcp->cardmode & SDC_MODE_CARDTYPE_MASK) { - case SDC_MODE_CARDTYPE_SDV11: - case SDC_MODE_CARDTYPE_SDV20: - if (HAL_FAILED == sdc_set_bus_width(sdcp)) { - goto failed; - } - break; - case SDC_MODE_CARDTYPE_MMC: - if (HAL_FAILED == mmc_set_bus_width(sdcp)) { - goto failed; - } - break; - default: - /* Unknown type.*/ - goto failed; - } - - /* Initialization complete.*/ - sdcp->state = BLK_READY; - return HAL_SUCCESS; - - /* Connection failed, state reset to BLK_ACTIVE.*/ -failed: - sdc_lld_stop_clk(sdcp); - sdcp->state = BLK_ACTIVE; - return HAL_FAILED; -} - -/** - * @brief Brings the driver in a state safe for card removal. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @api - */ -bool sdcDisconnect(SDCDriver *sdcp) { - - osalDbgCheck(sdcp != NULL); - - osalSysLock(); - osalDbgAssert((sdcp->state == BLK_ACTIVE) || (sdcp->state == BLK_READY), - "invalid state"); - if (sdcp->state == BLK_ACTIVE) { - osalSysUnlock(); - return HAL_SUCCESS; - } - sdcp->state = BLK_DISCONNECTING; - osalSysUnlock(); - - /* Waits for eventual pending operations completion.*/ - if (_sdc_wait_for_transfer_state(sdcp)) { - sdc_lld_stop_clk(sdcp); - sdcp->state = BLK_ACTIVE; - return HAL_FAILED; - } - - /* Card clock stopped.*/ - sdc_lld_stop_clk(sdcp); - sdcp->state = BLK_ACTIVE; - return HAL_SUCCESS; -} - -/** - * @brief Reads one or more blocks. - * @pre The driver must be in the @p BLK_READY state after a successful - * sdcConnect() invocation. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] startblk first block to read - * @param[out] buf pointer to the read buffer - * @param[in] n number of blocks to read - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @api - */ -bool sdcRead(SDCDriver *sdcp, uint32_t startblk, uint8_t *buf, uint32_t n) { - bool status; - - osalDbgCheck((sdcp != NULL) && (buf != NULL) && (n > 0U)); - osalDbgAssert(sdcp->state == BLK_READY, "invalid state"); - - if ((startblk + n - 1U) > sdcp->capacity){ - sdcp->errors |= SDC_OVERFLOW_ERROR; - return HAL_FAILED; - } - - /* Read operation in progress.*/ - sdcp->state = BLK_READING; - - status = sdc_lld_read(sdcp, startblk, buf, n); - - /* Read operation finished.*/ - sdcp->state = BLK_READY; - return status; -} - -/** - * @brief Writes one or more blocks. - * @pre The driver must be in the @p BLK_READY state after a successful - * sdcConnect() invocation. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] startblk first block to write - * @param[out] buf pointer to the write buffer - * @param[in] n number of blocks to write - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @api - */ -bool sdcWrite(SDCDriver *sdcp, uint32_t startblk, - const uint8_t *buf, uint32_t n) { - bool status; - - osalDbgCheck((sdcp != NULL) && (buf != NULL) && (n > 0U)); - osalDbgAssert(sdcp->state == BLK_READY, "invalid state"); - - if ((startblk + n - 1U) > sdcp->capacity){ - sdcp->errors |= SDC_OVERFLOW_ERROR; - return HAL_FAILED; - } - - /* Write operation in progress.*/ - sdcp->state = BLK_WRITING; - - status = sdc_lld_write(sdcp, startblk, buf, n); - - /* Write operation finished.*/ - sdcp->state = BLK_READY; - return status; -} - -/** - * @brief Returns the errors mask associated to the previous operation. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @return The errors mask. - * - * @api - */ -sdcflags_t sdcGetAndClearErrors(SDCDriver *sdcp) { - sdcflags_t flags; - - osalDbgCheck(sdcp != NULL); - osalDbgAssert(sdcp->state == BLK_READY, "invalid state"); - - osalSysLock(); - flags = sdcp->errors; - sdcp->errors = SDC_NO_ERROR; - osalSysUnlock(); - return flags; -} - -/** - * @brief Waits for card idle condition. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @return The operation status. - * @retval HAL_SUCCESS the operation succeeded. - * @retval HAL_FAILED the operation failed. - * - * @api - */ -bool sdcSync(SDCDriver *sdcp) { - bool result; - - osalDbgCheck(sdcp != NULL); - - if (sdcp->state != BLK_READY) { - return HAL_FAILED; - } - - /* Synchronization operation in progress.*/ - sdcp->state = BLK_SYNCING; - - result = sdc_lld_sync(sdcp); - - /* Synchronization operation finished.*/ - sdcp->state = BLK_READY; - return result; -} - -/** - * @brief Returns the media info. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[out] bdip pointer to a @p BlockDeviceInfo structure - * - * @return The operation status. - * @retval HAL_SUCCESS the operation succeeded. - * @retval HAL_FAILED the operation failed. - * - * @api - */ -bool sdcGetInfo(SDCDriver *sdcp, BlockDeviceInfo *bdip) { - - osalDbgCheck((sdcp != NULL) && (bdip != NULL)); - - if (sdcp->state != BLK_READY) { - return HAL_FAILED; - } - - bdip->blk_num = sdcp->capacity; - bdip->blk_size = MMCSD_BLOCK_SIZE; - - return HAL_SUCCESS; -} - -/** - * @brief Erases the supplied blocks. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] startblk starting block number - * @param[in] endblk ending block number - * - * @return The operation status. - * @retval HAL_SUCCESS the operation succeeded. - * @retval HAL_FAILED the operation failed. - * - * @api - */ -bool sdcErase(SDCDriver *sdcp, uint32_t startblk, uint32_t endblk) { - uint32_t resp[1]; - - osalDbgCheck((sdcp != NULL)); - osalDbgAssert(sdcp->state == BLK_READY, "invalid state"); - - /* Erase operation in progress.*/ - sdcp->state = BLK_WRITING; - - /* Handling command differences between HC and normal cards.*/ - if ((sdcp->cardmode & SDC_MODE_HIGH_CAPACITY) != 0U) { - startblk *= MMCSD_BLOCK_SIZE; - endblk *= MMCSD_BLOCK_SIZE; - } - - if (_sdc_wait_for_transfer_state(sdcp)) { - goto failed; - } - - if ((sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_ERASE_RW_BLK_START, - startblk, resp) != HAL_SUCCESS) || - MMCSD_R1_ERROR(resp[0])) { - goto failed; - } - - if ((sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_ERASE_RW_BLK_END, - endblk, resp) != HAL_SUCCESS) || - MMCSD_R1_ERROR(resp[0])) { - goto failed; - } - - if ((sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_ERASE, - 0, resp) != HAL_SUCCESS) || - MMCSD_R1_ERROR(resp[0])) { - goto failed; - } - - /* Quick sleep to allow it to transition to programming or receiving state */ - /* TODO: ??????????????????????????? */ - - /* Wait for it to return to transfer state to indicate it has finished erasing */ - if (_sdc_wait_for_transfer_state(sdcp)) { - goto failed; - } - - sdcp->state = BLK_READY; - return HAL_SUCCESS; - -failed: - sdcp->state = BLK_READY; - return HAL_FAILED; -} - -#endif /* HAL_USE_SDC == TRUE */ - -/** @} */ - diff --git a/firmware/ChibiOS_16/os/hal/src/serial.c b/firmware/ChibiOS_16/os/hal/src/serial.c deleted file mode 100644 index 87fe55e46a..0000000000 --- a/firmware/ChibiOS_16/os/hal/src/serial.c +++ /dev/null @@ -1,289 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file serial.c - * @brief Serial Driver code. - * - * @addtogroup SERIAL - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_SERIAL == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/* - * Interface implementation, the following functions just invoke the equivalent - * queue-level function or macro. - */ - -static size_t write(void *ip, const uint8_t *bp, size_t n) { - - return oqWriteTimeout(&((SerialDriver *)ip)->oqueue, bp, - n, TIME_INFINITE); -} - -static size_t read(void *ip, uint8_t *bp, size_t n) { - - return iqReadTimeout(&((SerialDriver *)ip)->iqueue, bp, - n, TIME_INFINITE); -} - -static msg_t put(void *ip, uint8_t b) { - - return oqPutTimeout(&((SerialDriver *)ip)->oqueue, b, TIME_INFINITE); -} - -static msg_t get(void *ip) { - - return iqGetTimeout(&((SerialDriver *)ip)->iqueue, TIME_INFINITE); -} - -static msg_t putt(void *ip, uint8_t b, systime_t timeout) { - - return oqPutTimeout(&((SerialDriver *)ip)->oqueue, b, timeout); -} - -static msg_t gett(void *ip, systime_t timeout) { - - return iqGetTimeout(&((SerialDriver *)ip)->iqueue, timeout); -} - -static size_t writet(void *ip, const uint8_t *bp, size_t n, systime_t timeout) { - - return oqWriteTimeout(&((SerialDriver *)ip)->oqueue, bp, n, timeout); -} - -static size_t readt(void *ip, uint8_t *bp, size_t n, systime_t timeout) { - - return iqReadTimeout(&((SerialDriver *)ip)->iqueue, bp, n, timeout); -} - -static const struct SerialDriverVMT vmt = { - write, read, put, get, - putt, gett, writet, readt -}; - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Serial Driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void sdInit(void) { - - sd_lld_init(); -} - -/** - * @brief Initializes a generic full duplex driver object. - * @details The HW dependent part of the initialization has to be performed - * outside, usually in the hardware initialization code. - * - * @param[out] sdp pointer to a @p SerialDriver structure - * @param[in] inotify pointer to a callback function that is invoked when - * some data is read from the Queue. The value can be - * @p NULL. - * @param[in] onotify pointer to a callback function that is invoked when - * some data is written in the Queue. The value can be - * @p NULL. - * - * @init - */ -void sdObjectInit(SerialDriver *sdp, qnotify_t inotify, qnotify_t onotify) { - - sdp->vmt = &vmt; - osalEventObjectInit(&sdp->event); - sdp->state = SD_STOP; - iqObjectInit(&sdp->iqueue, sdp->ib, SERIAL_BUFFERS_SIZE, inotify, sdp); - oqObjectInit(&sdp->oqueue, sdp->ob, SERIAL_BUFFERS_SIZE, onotify, sdp); -} - -/** - * @brief Configures and starts the driver. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] config the architecture-dependent serial driver configuration. - * If this parameter is set to @p NULL then a default - * configuration is used. - * - * @api - */ -void sdStart(SerialDriver *sdp, const SerialConfig *config) { - - osalDbgCheck(sdp != NULL); - - osalSysLock(); - osalDbgAssert((sdp->state == SD_STOP) || (sdp->state == SD_READY), - "invalid state"); - sd_lld_start(sdp, config); - sdp->state = SD_READY; - osalSysUnlock(); -} - -/** - * @brief Stops the driver. - * @details Any thread waiting on the driver's queues will be awakened with - * the message @p Q_RESET. - * - * @param[in] sdp pointer to a @p SerialDriver object - * - * @api - */ -void sdStop(SerialDriver *sdp) { - - osalDbgCheck(sdp != NULL); - - osalSysLock(); - osalDbgAssert((sdp->state == SD_STOP) || (sdp->state == SD_READY), - "invalid state"); - sd_lld_stop(sdp); - sdp->state = SD_STOP; - oqResetI(&sdp->oqueue); - iqResetI(&sdp->iqueue); - osalOsRescheduleS(); - osalSysUnlock(); -} - -/** - * @brief Handles incoming data. - * @details This function must be called from the input interrupt service - * routine in order to enqueue incoming data and generate the - * related events. - * @note The incoming data event is only generated when the input queue - * becomes non-empty. - * @note In order to gain some performance it is suggested to not use - * this function directly but copy this code directly into the - * interrupt service routine. - * - * @param[in] sdp pointer to a @p SerialDriver structure - * @param[in] b the byte to be written in the driver's Input Queue - * - * @iclass - */ -void sdIncomingDataI(SerialDriver *sdp, uint8_t b) { - - osalDbgCheckClassI(); - osalDbgCheck(sdp != NULL); - - if (iqIsEmptyI(&sdp->iqueue)) - chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE); - if (iqPutI(&sdp->iqueue, b) < Q_OK) - chnAddFlagsI(sdp, SD_OVERRUN_ERROR); -} - -/** - * @brief Handles outgoing data. - * @details Must be called from the output interrupt service routine in order - * to get the next byte to be transmitted. - * @note In order to gain some performance it is suggested to not use - * this function directly but copy this code directly into the - * interrupt service routine. - * - * @param[in] sdp pointer to a @p SerialDriver structure - * @return The byte value read from the driver's output queue. - * @retval Q_EMPTY if the queue is empty (the lower driver usually - * disables the interrupt source when this happens). - * - * @iclass - */ -msg_t sdRequestDataI(SerialDriver *sdp) { - msg_t b; - - osalDbgCheckClassI(); - osalDbgCheck(sdp != NULL); - - b = oqGetI(&sdp->oqueue); - if (b < Q_OK) - chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); - return b; -} - -/** - * @brief Direct output check on a @p SerialDriver. - * @note This function bypasses the indirect access to the channel and - * checks directly the output queue. This is faster but cannot - * be used to check different channels implementations. - * - * @param[in] sdp pointer to a @p SerialDriver structure - * @return The queue status. - * @retval false if the next write operation would not block. - * @retval true if the next write operation would block. - * - * @deprecated - * - * @api - */ -bool sdPutWouldBlock(SerialDriver *sdp) { - bool b; - - osalSysLock(); - b = oqIsFullI(&sdp->oqueue); - osalSysUnlock(); - - return b; -} - -/** - * @brief Direct input check on a @p SerialDriver. - * @note This function bypasses the indirect access to the channel and - * checks directly the input queue. This is faster but cannot - * be used to check different channels implementations. - * - * @param[in] sdp pointer to a @p SerialDriver structure - * @return The queue status. - * @retval false if the next write operation would not block. - * @retval true if the next write operation would block. - * - * @deprecated - * - * @api - */ -bool sdGetWouldBlock(SerialDriver *sdp) { - bool b; - - osalSysLock(); - b = iqIsEmptyI(&sdp->iqueue); - osalSysUnlock(); - - return b; -} - -#endif /* HAL_USE_SERIAL == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/src/serial_usb.c b/firmware/ChibiOS_16/os/hal/src/serial_usb.c deleted file mode 100644 index 0515da1751..0000000000 --- a/firmware/ChibiOS_16/os/hal/src/serial_usb.c +++ /dev/null @@ -1,501 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file serial_usb.c - * @brief Serial over USB Driver code. - * - * @addtogroup SERIAL_USB - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_SERIAL_USB == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/* - * Current Line Coding. - */ -static cdc_linecoding_t linecoding = { - {0x00, 0x96, 0x00, 0x00}, /* 38400. */ - LC_STOP_1, LC_PARITY_NONE, 8 -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static bool sdu_start_receive(SerialUSBDriver *sdup) { - uint8_t *buf; - - /* If the USB driver is not in the appropriate state then transactions - must not be started.*/ - if ((usbGetDriverStateI(sdup->config->usbp) != USB_ACTIVE) || - (sdup->state != SDU_READY)) { - return true; - } - - /* Checking if there is already a transaction ongoing on the endpoint.*/ - if (usbGetReceiveStatusI(sdup->config->usbp, sdup->config->bulk_in)) { - return true; - } - - /* Checking if there is a buffer ready for incoming data.*/ - buf = ibqGetEmptyBufferI(&sdup->ibqueue); - if (buf == NULL) { - return true; - } - - /* Buffer found, starting a new transaction.*/ - usbStartReceiveI(sdup->config->usbp, sdup->config->bulk_out, - buf, SERIAL_USB_BUFFERS_SIZE); - - return false; -} - -/* - * Interface implementation. - */ - -static size_t write(void *ip, const uint8_t *bp, size_t n) { - - if (usbGetDriverStateI(((SerialUSBDriver *)ip)->config->usbp) != USB_ACTIVE) { - return 0; - } - - return obqWriteTimeout(&((SerialUSBDriver *)ip)->obqueue, bp, - n, TIME_INFINITE); -} - -static size_t read(void *ip, uint8_t *bp, size_t n) { - - if (usbGetDriverStateI(((SerialUSBDriver *)ip)->config->usbp) != USB_ACTIVE) { - return 0; - } - - return ibqReadTimeout(&((SerialUSBDriver *)ip)->ibqueue, bp, - n, TIME_INFINITE); -} - -static msg_t put(void *ip, uint8_t b) { - - if (usbGetDriverStateI(((SerialUSBDriver *)ip)->config->usbp) != USB_ACTIVE) { - return MSG_RESET; - } - - return obqPutTimeout(&((SerialUSBDriver *)ip)->obqueue, b, TIME_INFINITE); -} - -static msg_t get(void *ip) { - - if (usbGetDriverStateI(((SerialUSBDriver *)ip)->config->usbp) != USB_ACTIVE) { - return MSG_RESET; - } - - return ibqGetTimeout(&((SerialUSBDriver *)ip)->ibqueue, TIME_INFINITE); -} - -static msg_t putt(void *ip, uint8_t b, systime_t timeout) { - - if (usbGetDriverStateI(((SerialUSBDriver *)ip)->config->usbp) != USB_ACTIVE) { - return MSG_RESET; - } - - return obqPutTimeout(&((SerialUSBDriver *)ip)->obqueue, b, timeout); -} - -static msg_t gett(void *ip, systime_t timeout) { - - if (usbGetDriverStateI(((SerialUSBDriver *)ip)->config->usbp) != USB_ACTIVE) { - return MSG_RESET; - } - - return ibqGetTimeout(&((SerialUSBDriver *)ip)->ibqueue, timeout); -} - -static size_t writet(void *ip, const uint8_t *bp, size_t n, systime_t timeout) { - - if (usbGetDriverStateI(((SerialUSBDriver *)ip)->config->usbp) != USB_ACTIVE) { - return 0; - } - - return obqWriteTimeout(&((SerialUSBDriver *)ip)->obqueue, bp, n, timeout); -} - -static size_t readt(void *ip, uint8_t *bp, size_t n, systime_t timeout) { - - if (usbGetDriverStateI(((SerialUSBDriver *)ip)->config->usbp) != USB_ACTIVE) { - return 0; - } - - return ibqReadTimeout(&((SerialUSBDriver *)ip)->ibqueue, bp, n, timeout); -} - -static const struct SerialUSBDriverVMT vmt = { - write, read, put, get, - putt, gett, writet, readt -}; - -/** - * @brief Notification of empty buffer released into the input buffers queue. - * - * @param[in] bqp the buffers queue pointer. - */ -static void ibnotify(io_buffers_queue_t *bqp) { - SerialUSBDriver *sdup = bqGetLinkX(bqp); - (void) sdu_start_receive(sdup); -} - -/** - * @brief Notification of filled buffer inserted into the output buffers queue. - * - * @param[in] bqp the buffers queue pointer. - */ -static void obnotify(io_buffers_queue_t *bqp) { - size_t n; - SerialUSBDriver *sdup = bqGetLinkX(bqp); - - /* If the USB driver is not in the appropriate state then transactions - must not be started.*/ - if ((usbGetDriverStateI(sdup->config->usbp) != USB_ACTIVE) || - (sdup->state != SDU_READY)) { - return; - } - - /* Checking if there is already a transaction ongoing on the endpoint.*/ - if (!usbGetTransmitStatusI(sdup->config->usbp, sdup->config->bulk_in)) { - /* Trying to get a full buffer.*/ - uint8_t *buf = obqGetFullBufferI(&sdup->obqueue, &n); - if (buf != NULL) { - /* Buffer found, starting a new transaction.*/ - usbStartTransmitI(sdup->config->usbp, sdup->config->bulk_in, buf, n); - } - } -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Serial Driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void sduInit(void) { -} - -/** - * @brief Initializes a generic full duplex driver object. - * @details The HW dependent part of the initialization has to be performed - * outside, usually in the hardware initialization code. - * - * @param[out] sdup pointer to a @p SerialUSBDriver structure - * - * @init - */ -void sduObjectInit(SerialUSBDriver *sdup) { - - sdup->vmt = &vmt; - osalEventObjectInit(&sdup->event); - sdup->state = SDU_STOP; - ibqObjectInit(&sdup->ibqueue, sdup->ib, - SERIAL_USB_BUFFERS_SIZE, SERIAL_USB_BUFFERS_NUMBER, - ibnotify, sdup); - obqObjectInit(&sdup->obqueue, sdup->ob, - SERIAL_USB_BUFFERS_SIZE, SERIAL_USB_BUFFERS_NUMBER, - obnotify, sdup); -} - -/** - * @brief Configures and starts the driver. - * - * @param[in] sdup pointer to a @p SerialUSBDriver object - * @param[in] config the serial over USB driver configuration - * - * @api - */ -void sduStart(SerialUSBDriver *sdup, const SerialUSBConfig *config) { - USBDriver *usbp = config->usbp; - - osalDbgCheck(sdup != NULL); - - osalSysLock(); - osalDbgAssert((sdup->state == SDU_STOP) || (sdup->state == SDU_READY), - "invalid state"); - usbp->in_params[config->bulk_in - 1U] = sdup; - usbp->out_params[config->bulk_out - 1U] = sdup; - if (config->int_in > 0U) { - usbp->in_params[config->int_in - 1U] = sdup; - } - sdup->config = config; - sdup->state = SDU_READY; - osalSysUnlock(); -} - -/** - * @brief Stops the driver. - * @details Any thread waiting on the driver's queues will be awakened with - * the message @p Q_RESET. - * - * @param[in] sdup pointer to a @p SerialUSBDriver object - * - * @api - */ -void sduStop(SerialUSBDriver *sdup) { - USBDriver *usbp = sdup->config->usbp; - - osalDbgCheck(sdup != NULL); - - osalSysLock(); - - osalDbgAssert((sdup->state == SDU_STOP) || (sdup->state == SDU_READY), - "invalid state"); - - /* Driver in stopped state.*/ - usbp->in_params[sdup->config->bulk_in - 1U] = NULL; - usbp->out_params[sdup->config->bulk_out - 1U] = NULL; - if (sdup->config->int_in > 0U) { - usbp->in_params[sdup->config->int_in - 1U] = NULL; - } - sdup->state = SDU_STOP; - - /* Enforces a disconnection.*/ - sduDisconnectI(sdup); - osalOsRescheduleS(); - - osalSysUnlock(); -} - -/** - * @brief USB device disconnection handler. - * @note If this function is not called from an ISR then an explicit call - * to @p osalOsRescheduleS() in necessary afterward. - * - * @param[in] sdup pointer to a @p SerialUSBDriver object - * - * @iclass - */ -void sduDisconnectI(SerialUSBDriver *sdup) { - - /* Queues reset in order to signal the driver stop to the application.*/ - chnAddFlagsI(sdup, CHN_DISCONNECTED); - ibqResetI(&sdup->ibqueue); - obqResetI(&sdup->obqueue); -} - -/** - * @brief USB device configured handler. - * - * @param[in] sdup pointer to a @p SerialUSBDriver object - * - * @iclass - */ -void sduConfigureHookI(SerialUSBDriver *sdup) { - - ibqResetI(&sdup->ibqueue); - obqResetI(&sdup->obqueue); - chnAddFlagsI(sdup, CHN_CONNECTED); - (void) sdu_start_receive(sdup); -} - -/** - * @brief Default requests hook. - * @details Applications wanting to use the Serial over USB driver can use - * this function as requests hook in the USB configuration. - * The following requests are emulated: - * - CDC_GET_LINE_CODING. - * - CDC_SET_LINE_CODING. - * - CDC_SET_CONTROL_LINE_STATE. - * . - * - * @param[in] usbp pointer to the @p USBDriver object - * @return The hook status. - * @retval true Message handled internally. - * @retval false Message not handled. - */ -bool sduRequestsHook(USBDriver *usbp) { - - if ((usbp->setup[0] & USB_RTYPE_TYPE_MASK) == USB_RTYPE_TYPE_CLASS) { - switch (usbp->setup[1]) { - case CDC_GET_LINE_CODING: - usbSetupTransfer(usbp, (uint8_t *)&linecoding, sizeof(linecoding), NULL); - return true; - case CDC_SET_LINE_CODING: - usbSetupTransfer(usbp, (uint8_t *)&linecoding, sizeof(linecoding), NULL); - return true; - case CDC_SET_CONTROL_LINE_STATE: - /* Nothing to do, there are no control lines.*/ - usbSetupTransfer(usbp, NULL, 0, NULL); - return true; - default: - return false; - } - } - return false; -} - -/** - * @brief SOF handler. - * @details The SOF interrupt is used for automatic flushing of incomplete - * buffers pending in the output queue. - * - * @param[in] sdup pointer to a @p SerialUSBDriver object - * - * @iclass - */ -void sduSOFHookI(SerialUSBDriver *sdup) { - - /* If the USB driver is not in the appropriate state then transactions - must not be started.*/ - if ((usbGetDriverStateI(sdup->config->usbp) != USB_ACTIVE) || - (sdup->state != SDU_READY)) { - return; - } - - /* If there is already a transaction ongoing then another one cannot be - started.*/ - if (usbGetTransmitStatusI(sdup->config->usbp, sdup->config->bulk_in)) { - return; - } - - /* Checking if there only a buffer partially filled, if so then it is - enforced in the queue and transmitted.*/ - if (obqTryFlushI(&sdup->obqueue)) { - size_t n; - uint8_t *buf = obqGetFullBufferI(&sdup->obqueue, &n); - - osalDbgAssert(buf != NULL, "queue is empty"); - - usbStartTransmitI(sdup->config->usbp, sdup->config->bulk_in, buf, n); - } -} - -/** - * @brief Default data transmitted callback. - * @details The application must use this function as callback for the IN - * data endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep IN endpoint number - */ -void sduDataTransmitted(USBDriver *usbp, usbep_t ep) { - uint8_t *buf; - size_t n; - SerialUSBDriver *sdup = usbp->in_params[ep - 1U]; - - if (sdup == NULL) { - return; - } - - osalSysLockFromISR(); - - /* Signaling that space is available in the output queue.*/ - chnAddFlagsI(sdup, CHN_OUTPUT_EMPTY); - - /* Freeing the buffer just transmitted, if it was not a zero size packet.*/ - if (usbp->epc[ep]->in_state->txsize > 0U) { - obqReleaseEmptyBufferI(&sdup->obqueue); - } - - /* Checking if there is a buffer ready for transmission.*/ - buf = obqGetFullBufferI(&sdup->obqueue, &n); - - if (buf != NULL) { - /* The endpoint cannot be busy, we are in the context of the callback, - so it is safe to transmit without a check.*/ - usbStartTransmitI(usbp, ep, buf, n); - } - else if ((usbp->epc[ep]->in_state->txsize > 0U) && - ((usbp->epc[ep]->in_state->txsize & - ((size_t)usbp->epc[ep]->in_maxsize - 1U)) == 0U)) { - /* Transmit zero sized packet in case the last one has maximum allowed - size. Otherwise the recipient may expect more data coming soon and - not return buffered data to app. See section 5.8.3 Bulk Transfer - Packet Size Constraints of the USB Specification document.*/ - usbStartTransmitI(usbp, ep, usbp->setup, 0); - - } - else { - /* Nothing to transmit.*/ - } - - osalSysUnlockFromISR(); -} - -/** - * @brief Default data received callback. - * @details The application must use this function as callback for the OUT - * data endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep OUT endpoint number - */ -void sduDataReceived(USBDriver *usbp, usbep_t ep) { - SerialUSBDriver *sdup = usbp->out_params[ep - 1U]; - if (sdup == NULL) { - return; - } - - osalSysLockFromISR(); - - /* Signaling that data is available in the input queue.*/ - chnAddFlagsI(sdup, CHN_INPUT_AVAILABLE); - - /* Posting the filled buffer in the queue.*/ - ibqPostFullBufferI(&sdup->ibqueue, - usbGetReceiveTransactionSizeX(sdup->config->usbp, - sdup->config->bulk_out)); - - /* The endpoint cannot be busy, we are in the context of the callback, - so a packet is in the buffer for sure. Trying to get a free buffer - for the next transaction.*/ - sdu_start_receive(sdup); - - osalSysUnlockFromISR(); -} - -/** - * @brief Default data received callback. - * @details The application must use this function as callback for the IN - * interrupt endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - */ -void sduInterruptTransmitted(USBDriver *usbp, usbep_t ep) { - - (void)usbp; - (void)ep; -} - -#endif /* HAL_USE_SERIAL_USB == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/src/spi.c b/firmware/ChibiOS_16/os/hal/src/spi.c deleted file mode 100644 index b80af4bd04..0000000000 --- a/firmware/ChibiOS_16/os/hal/src/spi.c +++ /dev/null @@ -1,416 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file spi.c - * @brief SPI Driver code. - * - * @addtogroup SPI - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_SPI == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief SPI Driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void spiInit(void) { - - spi_lld_init(); -} - -/** - * @brief Initializes the standard part of a @p SPIDriver structure. - * - * @param[out] spip pointer to the @p SPIDriver object - * - * @init - */ -void spiObjectInit(SPIDriver *spip) { - - spip->state = SPI_STOP; - spip->config = NULL; -#if SPI_USE_WAIT == TRUE - spip->thread = NULL; -#endif -#if SPI_USE_MUTUAL_EXCLUSION == TRUE - osalMutexObjectInit(&spip->mutex); -#endif -#if defined(SPI_DRIVER_EXT_INIT_HOOK) - SPI_DRIVER_EXT_INIT_HOOK(spip); -#endif -} - -/** - * @brief Configures and activates the SPI peripheral. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] config pointer to the @p SPIConfig object - * - * @api - */ -void spiStart(SPIDriver *spip, const SPIConfig *config) { - - osalDbgCheck((spip != NULL) && (config != NULL)); - - osalSysLock(); - osalDbgAssert((spip->state == SPI_STOP) || (spip->state == SPI_READY), - "invalid state"); - spip->config = config; - spi_lld_start(spip); - spip->state = SPI_READY; - osalSysUnlock(); -} - -/** - * @brief Deactivates the SPI peripheral. - * @note Deactivating the peripheral also enforces a release of the slave - * select line. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @api - */ -void spiStop(SPIDriver *spip) { - - osalDbgCheck(spip != NULL); - - osalSysLock(); - osalDbgAssert((spip->state == SPI_STOP) || (spip->state == SPI_READY), - "invalid state"); - spi_lld_stop(spip); - spip->state = SPI_STOP; - osalSysUnlock(); -} - -/** - * @brief Asserts the slave select signal and prepares for transfers. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @api - */ -void spiSelect(SPIDriver *spip) { - - osalDbgCheck(spip != NULL); - - osalSysLock(); - osalDbgAssert(spip->state == SPI_READY, "not ready"); - spiSelectI(spip); - osalSysUnlock(); -} - -/** - * @brief Deasserts the slave select signal. - * @details The previously selected peripheral is unselected. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @api - */ -void spiUnselect(SPIDriver *spip) { - - osalDbgCheck(spip != NULL); - - osalSysLock(); - osalDbgAssert(spip->state == SPI_READY, "not ready"); - spiUnselectI(spip); - osalSysUnlock(); -} - -/** - * @brief Ignores data on the SPI bus. - * @details This asynchronous function starts the transmission of a series of - * idle words on the SPI bus and ignores the received data. - * @pre A slave must have been selected using @p spiSelect() or - * @p spiSelectI(). - * @post At the end of the operation the configured callback is invoked. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be ignored - * - * @api - */ -void spiStartIgnore(SPIDriver *spip, size_t n) { - - osalDbgCheck((spip != NULL) && (n > 0U)); - - osalSysLock(); - osalDbgAssert(spip->state == SPI_READY, "not ready"); - spiStartIgnoreI(spip, n); - osalSysUnlock(); -} - -/** - * @brief Exchanges data on the SPI bus. - * @details This asynchronous function starts a simultaneous transmit/receive - * operation. - * @pre A slave must have been selected using @p spiSelect() or - * @p spiSelectI(). - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be exchanged - * @param[in] txbuf the pointer to the transmit buffer - * @param[out] rxbuf the pointer to the receive buffer - * - * @api - */ -void spiStartExchange(SPIDriver *spip, size_t n, - const void *txbuf, void *rxbuf) { - - osalDbgCheck((spip != NULL) && (n > 0U) && - (rxbuf != NULL) && (txbuf != NULL)); - - osalSysLock(); - osalDbgAssert(spip->state == SPI_READY, "not ready"); - spiStartExchangeI(spip, n, txbuf, rxbuf); - osalSysUnlock(); -} - -/** - * @brief Sends data over the SPI bus. - * @details This asynchronous function starts a transmit operation. - * @pre A slave must have been selected using @p spiSelect() or - * @p spiSelectI(). - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to send - * @param[in] txbuf the pointer to the transmit buffer - * - * @api - */ -void spiStartSend(SPIDriver *spip, size_t n, const void *txbuf) { - - osalDbgCheck((spip != NULL) && (n > 0U) && (txbuf != NULL)); - - osalSysLock(); - osalDbgAssert(spip->state == SPI_READY, "not ready"); - spiStartSendI(spip, n, txbuf); - osalSysUnlock(); -} - -/** - * @brief Receives data from the SPI bus. - * @details This asynchronous function starts a receive operation. - * @pre A slave must have been selected using @p spiSelect() or - * @p spiSelectI(). - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to receive - * @param[out] rxbuf the pointer to the receive buffer - * - * @api - */ -void spiStartReceive(SPIDriver *spip, size_t n, void *rxbuf) { - - osalDbgCheck((spip != NULL) && (n > 0U) && (rxbuf != NULL)); - - osalSysLock(); - osalDbgAssert(spip->state == SPI_READY, "not ready"); - spiStartReceiveI(spip, n, rxbuf); - osalSysUnlock(); -} - -#if (SPI_USE_WAIT == TRUE) || defined(__DOXYGEN__) -/** - * @brief Ignores data on the SPI bus. - * @details This synchronous function performs the transmission of a series of - * idle words on the SPI bus and ignores the received data. - * @pre In order to use this function the option @p SPI_USE_WAIT must be - * enabled. - * @pre In order to use this function the driver must have been configured - * without callbacks (@p end_cb = @p NULL). - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be ignored - * - * @api - */ -void spiIgnore(SPIDriver *spip, size_t n) { - - osalDbgCheck((spip != NULL) && (n > 0U)); - - osalSysLock(); - osalDbgAssert(spip->state == SPI_READY, "not ready"); - osalDbgAssert(spip->config->end_cb == NULL, "has callback"); - spiStartIgnoreI(spip, n); - (void) osalThreadSuspendS(&spip->thread); - osalSysUnlock(); -} - -/** - * @brief Exchanges data on the SPI bus. - * @details This synchronous function performs a simultaneous transmit/receive - * operation. - * @pre In order to use this function the option @p SPI_USE_WAIT must be - * enabled. - * @pre In order to use this function the driver must have been configured - * without callbacks (@p end_cb = @p NULL). - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be exchanged - * @param[in] txbuf the pointer to the transmit buffer - * @param[out] rxbuf the pointer to the receive buffer - * - * @api - */ -void spiExchange(SPIDriver *spip, size_t n, - const void *txbuf, void *rxbuf) { - - osalDbgCheck((spip != NULL) && (n > 0U) && - (rxbuf != NULL) && (txbuf != NULL)); - - osalSysLock(); - osalDbgAssert(spip->state == SPI_READY, "not ready"); - osalDbgAssert(spip->config->end_cb == NULL, "has callback"); - spiStartExchangeI(spip, n, txbuf, rxbuf); - (void) osalThreadSuspendS(&spip->thread); - osalSysUnlock(); -} - -/** - * @brief Sends data over the SPI bus. - * @details This synchronous function performs a transmit operation. - * @pre In order to use this function the option @p SPI_USE_WAIT must be - * enabled. - * @pre In order to use this function the driver must have been configured - * without callbacks (@p end_cb = @p NULL). - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to send - * @param[in] txbuf the pointer to the transmit buffer - * - * @api - */ -void spiSend(SPIDriver *spip, size_t n, const void *txbuf) { - - osalDbgCheck((spip != NULL) && (n > 0U) && (txbuf != NULL)); - - osalSysLock(); - osalDbgAssert(spip->state == SPI_READY, "not ready"); - osalDbgAssert(spip->config->end_cb == NULL, "has callback"); - spiStartSendI(spip, n, txbuf); - (void) osalThreadSuspendS(&spip->thread); - osalSysUnlock(); -} - -/** - * @brief Receives data from the SPI bus. - * @details This synchronous function performs a receive operation. - * @pre In order to use this function the option @p SPI_USE_WAIT must be - * enabled. - * @pre In order to use this function the driver must have been configured - * without callbacks (@p end_cb = @p NULL). - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to receive - * @param[out] rxbuf the pointer to the receive buffer - * - * @api - */ -void spiReceive(SPIDriver *spip, size_t n, void *rxbuf) { - - osalDbgCheck((spip != NULL) && (n > 0U) && (rxbuf != NULL)); - - osalSysLock(); - osalDbgAssert(spip->state == SPI_READY, "not ready"); - osalDbgAssert(spip->config->end_cb == NULL, "has callback"); - spiStartReceiveI(spip, n, rxbuf); - (void) osalThreadSuspendS(&spip->thread); - osalSysUnlock(); -} -#endif /* SPI_USE_WAIT == TRUE */ - -#if (SPI_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__) -/** - * @brief Gains exclusive access to the SPI bus. - * @details This function tries to gain ownership to the SPI bus, if the bus - * is already being used then the invoking thread is queued. - * @pre In order to use this function the option @p SPI_USE_MUTUAL_EXCLUSION - * must be enabled. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @api - */ -void spiAcquireBus(SPIDriver *spip) { - - osalDbgCheck(spip != NULL); - - osalMutexLock(&spip->mutex); -} - -/** - * @brief Releases exclusive access to the SPI bus. - * @pre In order to use this function the option @p SPI_USE_MUTUAL_EXCLUSION - * must be enabled. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @api - */ -void spiReleaseBus(SPIDriver *spip) { - - osalDbgCheck(spip != NULL); - - osalMutexUnlock(&spip->mutex); -} -#endif /* SPI_USE_MUTUAL_EXCLUSION == TRUE */ - -#endif /* HAL_USE_SPI == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/src/st.c b/firmware/ChibiOS_16/os/hal/src/st.c deleted file mode 100644 index 4ab7783ed1..0000000000 --- a/firmware/ChibiOS_16/os/hal/src/st.c +++ /dev/null @@ -1,130 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file st.c - * @brief ST Driver code. - * - * @addtogroup ST - * @{ - */ - -#include "hal.h" - -#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief ST Driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void stInit(void) { - - st_lld_init(); -} - - -/** - * @brief Starts the alarm. - * @note Makes sure that no spurious alarms are triggered after - * this call. - * @note This functionality is only available in free running mode, the - * behavior in periodic mode is undefined. - * - * @param[in] abstime the time to be set for the first alarm - * - * @api - */ -void stStartAlarm(systime_t abstime) { - - osalDbgAssert(stIsAlarmActive() == false, "already active"); - - st_lld_start_alarm(abstime); -} - -/** - * @brief Stops the alarm interrupt. - * @note This functionality is only available in free running mode, the - * behavior in periodic mode is undefined. - * - * @api - */ -void stStopAlarm(void) { - - st_lld_stop_alarm(); -} - -/** - * @brief Sets the alarm time. - * @note This functionality is only available in free running mode, the - * behavior in periodic mode is undefined. - * - * @param[in] abstime the time to be set for the next alarm - * - * @api - */ -void stSetAlarm(systime_t abstime) { - - osalDbgAssert(stIsAlarmActive() != false, "not active"); - - st_lld_set_alarm(abstime); -} - -/** - * @brief Returns the current alarm time. - * @note This functionality is only available in free running mode, the - * behavior in periodic mode is undefined. - * - * @return The currently set alarm time. - * - * @api - */ -systime_t stGetAlarm(void) { - - osalDbgAssert(stIsAlarmActive() != false, "not active"); - - return st_lld_get_alarm(); -} - -#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/src/uart.c b/firmware/ChibiOS_16/os/hal/src/uart.c deleted file mode 100644 index 029db1c4a1..0000000000 --- a/firmware/ChibiOS_16/os/hal/src/uart.c +++ /dev/null @@ -1,515 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file uart.c - * @brief UART Driver code. - * - * @addtogroup UART - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_UART == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief UART Driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void uartInit(void) { - - uart_lld_init(); -} - -/** - * @brief Initializes the standard part of a @p UARTDriver structure. - * - * @param[out] uartp pointer to the @p UARTDriver object - * - * @init - */ -void uartObjectInit(UARTDriver *uartp) { - - uartp->state = UART_STOP; - uartp->txstate = UART_TX_IDLE; - uartp->rxstate = UART_RX_IDLE; - uartp->config = NULL; -#if UART_USE_WAIT == TRUE - uartp->early = false; - uartp->threadrx = NULL; - uartp->threadtx = NULL; -#endif /* UART_USE_WAIT */ -#if UART_USE_MUTUAL_EXCLUSION == TRUE - osalMutexObjectInit(&uartp->mutex); -#endif /* UART_USE_MUTUAL_EXCLUSION */ - - /* Optional, user-defined initializer.*/ -#if defined(UART_DRIVER_EXT_INIT_HOOK) - UART_DRIVER_EXT_INIT_HOOK(uartp); -#endif -} - -/** - * @brief Configures and activates the UART peripheral. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] config pointer to the @p UARTConfig object - * - * @api - */ -void uartStart(UARTDriver *uartp, const UARTConfig *config) { - - osalDbgCheck((uartp != NULL) && (config != NULL)); - - osalSysLock(); - osalDbgAssert((uartp->state == UART_STOP) || (uartp->state == UART_READY), - "invalid state"); - - uartp->config = config; - uart_lld_start(uartp); - uartp->state = UART_READY; - osalSysUnlock(); -} - -/** - * @brief Deactivates the UART peripheral. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @api - */ -void uartStop(UARTDriver *uartp) { - - osalDbgCheck(uartp != NULL); - - osalSysLock(); - osalDbgAssert((uartp->state == UART_STOP) || (uartp->state == UART_READY), - "invalid state"); - - uart_lld_stop(uartp); - uartp->state = UART_STOP; - uartp->txstate = UART_TX_IDLE; - uartp->rxstate = UART_RX_IDLE; - osalSysUnlock(); -} - -/** - * @brief Starts a transmission on the UART peripheral. - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] n number of data frames to send - * @param[in] txbuf the pointer to the transmit buffer - * - * @api - */ -void uartStartSend(UARTDriver *uartp, size_t n, const void *txbuf) { - - osalDbgCheck((uartp != NULL) && (n > 0U) && (txbuf != NULL)); - - osalSysLock(); - osalDbgAssert(uartp->state == UART_READY, "is active"); - osalDbgAssert(uartp->txstate != UART_TX_ACTIVE, "tx active"); - - uart_lld_start_send(uartp, n, txbuf); - uartp->txstate = UART_TX_ACTIVE; - osalSysUnlock(); -} - -/** - * @brief Starts a transmission on the UART peripheral. - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * @note This function has to be invoked from a lock zone. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] n number of data frames to send - * @param[in] txbuf the pointer to the transmit buffer - * - * @iclass - */ -void uartStartSendI(UARTDriver *uartp, size_t n, const void *txbuf) { - - osalDbgCheckClassI(); - osalDbgCheck((uartp != NULL) && (n > 0U) && (txbuf != NULL)); - osalDbgAssert(uartp->state == UART_READY, "is active"); - osalDbgAssert(uartp->txstate != UART_TX_ACTIVE, "tx active"); - - uart_lld_start_send(uartp, n, txbuf); - uartp->txstate = UART_TX_ACTIVE; -} - -/** - * @brief Stops any ongoing transmission. - * @note Stopping a transmission also suppresses the transmission callbacks. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @return The number of data frames not transmitted by the - * stopped transmit operation. - * @retval 0 There was no transmit operation in progress. - * - * @api - */ -size_t uartStopSend(UARTDriver *uartp) { - size_t n; - - osalDbgCheck(uartp != NULL); - - osalSysLock(); - osalDbgAssert(uartp->state == UART_READY, "not active"); - - if (uartp->txstate == UART_TX_ACTIVE) { - n = uart_lld_stop_send(uartp); - uartp->txstate = UART_TX_IDLE; - } - else { - n = 0; - } - osalSysUnlock(); - - return n; -} - -/** - * @brief Stops any ongoing transmission. - * @note Stopping a transmission also suppresses the transmission callbacks. - * @note This function has to be invoked from a lock zone. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @return The number of data frames not transmitted by the - * stopped transmit operation. - * @retval 0 There was no transmit operation in progress. - * - * @iclass - */ -size_t uartStopSendI(UARTDriver *uartp) { - - osalDbgCheckClassI(); - osalDbgCheck(uartp != NULL); - osalDbgAssert(uartp->state == UART_READY, "not active"); - - if (uartp->txstate == UART_TX_ACTIVE) { - size_t n = uart_lld_stop_send(uartp); - uartp->txstate = UART_TX_IDLE; - return n; - } - return 0; -} - -/** - * @brief Starts a receive operation on the UART peripheral. - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] n number of data frames to receive - * @param[in] rxbuf the pointer to the receive buffer - * - * @api - */ -void uartStartReceive(UARTDriver *uartp, size_t n, void *rxbuf) { - - osalDbgCheck((uartp != NULL) && (n > 0U) && (rxbuf != NULL)); - - osalSysLock(); - osalDbgAssert(uartp->state == UART_READY, "is active"); - osalDbgAssert(uartp->rxstate != UART_RX_ACTIVE, "rx active"); - - uart_lld_start_receive(uartp, n, rxbuf); - uartp->rxstate = UART_RX_ACTIVE; - osalSysUnlock(); -} - -/** - * @brief Starts a receive operation on the UART peripheral. - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * @note This function has to be invoked from a lock zone. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] n number of data frames to receive - * @param[out] rxbuf the pointer to the receive buffer - * - * @iclass - */ -void uartStartReceiveI(UARTDriver *uartp, size_t n, void *rxbuf) { - - osalDbgCheckClassI(); - osalDbgCheck((uartp != NULL) && (n > 0U) && (rxbuf != NULL)); - osalDbgAssert(uartp->state == UART_READY, "is active"); - osalDbgAssert(uartp->rxstate != UART_RX_ACTIVE, "rx active"); - - uart_lld_start_receive(uartp, n, rxbuf); - uartp->rxstate = UART_RX_ACTIVE; -} - -/** - * @brief Stops any ongoing receive operation. - * @note Stopping a receive operation also suppresses the receive callbacks. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @return The number of data frames not received by the - * stopped receive operation. - * @retval 0 There was no receive operation in progress. - * - * @api - */ -size_t uartStopReceive(UARTDriver *uartp) { - size_t n; - - osalDbgCheck(uartp != NULL); - - osalSysLock(); - osalDbgAssert(uartp->state == UART_READY, "not active"); - - if (uartp->rxstate == UART_RX_ACTIVE) { - n = uart_lld_stop_receive(uartp); - uartp->rxstate = UART_RX_IDLE; - } - else { - n = 0; - } - osalSysUnlock(); - - return n; -} - -/** - * @brief Stops any ongoing receive operation. - * @note Stopping a receive operation also suppresses the receive callbacks. - * @note This function has to be invoked from a lock zone. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @return The number of data frames not received by the - * stopped receive operation. - * @retval 0 There was no receive operation in progress. - * - * @iclass - */ -size_t uartStopReceiveI(UARTDriver *uartp) { - - osalDbgCheckClassI(); - osalDbgCheck(uartp != NULL); - osalDbgAssert(uartp->state == UART_READY, "not active"); - - if (uartp->rxstate == UART_RX_ACTIVE) { - size_t n = uart_lld_stop_receive(uartp); - uartp->rxstate = UART_RX_IDLE; - return n; - } - return 0; -} - -#if (UART_USE_WAIT == TRUE) || defined(__DOXYGEN__) -/** - * @brief Performs a transmission on the UART peripheral. - * @note The function returns when the specified number of frames have been - * sent to the UART or on timeout. - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in,out] np number of data frames to transmit, on exit the number - * of frames actually transmitted - * @param[in] txbuf the pointer to the transmit buffer - * @param[in] timeout operation timeout - * @return The operation status. - * @retval MSG_OK if the operation completed successfully. - * @retval MSG_TIMEOUT if the operation timed out. - * - * @api - */ -msg_t uartSendTimeout(UARTDriver *uartp, size_t *np, - const void *txbuf, systime_t timeout) { - msg_t msg; - - osalDbgCheck((uartp != NULL) && (*np > 0U) && (txbuf != NULL)); - - osalSysLock(); - osalDbgAssert(uartp->state == UART_READY, "is active"); - osalDbgAssert(uartp->txstate != UART_TX_ACTIVE, "tx active"); - - /* Transmission start.*/ - uartp->early = true; - uart_lld_start_send(uartp, *np, txbuf); - uartp->txstate = UART_TX_ACTIVE; - - /* Waiting for result.*/ - msg = osalThreadSuspendTimeoutS(&uartp->threadtx, timeout); - if (msg != MSG_OK) { - *np = uartStopSendI(uartp); - } - osalSysUnlock(); - - return msg; -} - -/** - * @brief Performs a transmission on the UART peripheral. - * @note The function returns when the specified number of frames have been - * physically transmitted or on timeout. - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in,out] np number of data frames to transmit, on exit the number - * of frames actually transmitted - * @param[in] txbuf the pointer to the transmit buffer - * @param[in] timeout operation timeout - * @return The operation status. - * @retval MSG_OK if the operation completed successfully. - * @retval MSG_TIMEOUT if the operation timed out. - * - * @api - */ -msg_t uartSendFullTimeout(UARTDriver *uartp, size_t *np, - const void *txbuf, systime_t timeout) { - msg_t msg; - - osalDbgCheck((uartp != NULL) && (*np > 0U) && (txbuf != NULL)); - - osalSysLock(); - osalDbgAssert(uartp->state == UART_READY, "is active"); - osalDbgAssert(uartp->txstate != UART_TX_ACTIVE, "tx active"); - - /* Transmission start.*/ - uartp->early = false; - uart_lld_start_send(uartp, *np, txbuf); - uartp->txstate = UART_TX_ACTIVE; - - /* Waiting for result.*/ - msg = osalThreadSuspendTimeoutS(&uartp->threadtx, timeout); - if (msg != MSG_OK) { - *np = uartStopSendI(uartp); - } - osalSysUnlock(); - - return msg; -} - -/** - * @brief Performs a receive operation on the UART peripheral. - * @note The function returns when the specified number of frames have been - * received or on error/timeout. - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in,out] np number of data frames to receive, on exit the number - * of frames actually received - * @param[in] rxbuf the pointer to the receive buffer - * @param[in] timeout operation timeout - * - * @return The operation status. - * @retval MSG_OK if the operation completed successfully. - * @retval MSG_TIMEOUT if the operation timed out. - * @retval MSG_RESET in case of a receive error. - * - * @api - */ -msg_t uartReceiveTimeout(UARTDriver *uartp, size_t *np, - void *rxbuf, systime_t timeout) { - msg_t msg; - - osalDbgCheck((uartp != NULL) && (*np > 0U) && (rxbuf != NULL)); - - osalSysLock(); - osalDbgAssert(uartp->state == UART_READY, "is active"); - osalDbgAssert(uartp->rxstate != UART_RX_ACTIVE, "rx active"); - - /* Receive start.*/ - uart_lld_start_receive(uartp, *np, rxbuf); - uartp->rxstate = UART_RX_ACTIVE; - - /* Waiting for result.*/ - msg = osalThreadSuspendTimeoutS(&uartp->threadrx, timeout); - if (msg != MSG_OK) { - *np = uartStopReceiveI(uartp); - } - osalSysUnlock(); - - return msg; -} -#endif - -#if (UART_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__) -/** - * @brief Gains exclusive access to the UART bus. - * @details This function tries to gain ownership to the UART bus, if the bus - * is already being used then the invoking thread is queued. - * @pre In order to use this function the option @p UART_USE_MUTUAL_EXCLUSION - * must be enabled. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @api - */ -void uartAcquireBus(UARTDriver *uartp) { - - osalDbgCheck(uartp != NULL); - - osalMutexLock(&uartp->mutex); -} - -/** - * @brief Releases exclusive access to the UART bus. - * @pre In order to use this function the option @p UART_USE_MUTUAL_EXCLUSION - * must be enabled. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @api - */ -void uartReleaseBus(UARTDriver *uartp) { - - osalDbgCheck(uartp != NULL); - - osalMutexUnlock(&uartp->mutex); -} -#endif - -#endif /* HAL_USE_UART == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/src/usb.c b/firmware/ChibiOS_16/os/hal/src/usb.c deleted file mode 100644 index 7c8a23e0fc..0000000000 --- a/firmware/ChibiOS_16/os/hal/src/usb.c +++ /dev/null @@ -1,966 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file usb.c - * @brief USB Driver code. - * - * @addtogroup USB - * @{ - */ - -#include - -#include "hal.h" - -#if (HAL_USE_USB == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -static const uint8_t zero_status[] = {0x00, 0x00}; -static const uint8_t active_status[] ={0x00, 0x00}; -static const uint8_t halted_status[] = {0x01, 0x00}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static uint16_t get_hword(uint8_t *p) { - uint16_t hw; - - hw = (uint16_t)*p++; - hw |= (uint16_t)*p << 8U; - return hw; -} - -/** - * @brief SET ADDRESS transaction callback. - * - * @param[in] usbp pointer to the @p USBDriver object - */ -static void set_address(USBDriver *usbp) { - - usbp->address = usbp->setup[2]; - usb_lld_set_address(usbp); - _usb_isr_invoke_event_cb(usbp, USB_EVENT_ADDRESS); - usbp->state = USB_SELECTED; -} - -/** - * @brief Standard requests handler. - * @details This is the standard requests default handler, most standard - * requests are handled here, the user can override the standard - * handling using the @p requests_hook_cb hook in the - * @p USBConfig structure. - * - * @param[in] usbp pointer to the @p USBDriver object - * @return The request handling exit code. - * @retval false Request not recognized by the handler or error. - * @retval true Request handled. - */ -static bool default_handler(USBDriver *usbp) { - const USBDescriptor *dp; - - /* Decoding the request.*/ - switch ((((uint32_t)usbp->setup[0] & (USB_RTYPE_RECIPIENT_MASK | - USB_RTYPE_TYPE_MASK)) | - ((uint32_t)usbp->setup[1] << 8U))) { - case (uint32_t)USB_RTYPE_RECIPIENT_DEVICE | ((uint32_t)USB_REQ_GET_STATUS << 8): - /* Just returns the current status word.*/ - usbSetupTransfer(usbp, (uint8_t *)&usbp->status, 2, NULL); - return true; - case (uint32_t)USB_RTYPE_RECIPIENT_DEVICE | ((uint32_t)USB_REQ_CLEAR_FEATURE << 8): - /* Only the DEVICE_REMOTE_WAKEUP is handled here, any other feature - number is handled as an error.*/ - if (usbp->setup[2] == USB_FEATURE_DEVICE_REMOTE_WAKEUP) { - usbp->status &= ~2U; - usbSetupTransfer(usbp, NULL, 0, NULL); - return true; - } - return false; - case (uint32_t)USB_RTYPE_RECIPIENT_DEVICE | ((uint32_t)USB_REQ_SET_FEATURE << 8): - /* Only the DEVICE_REMOTE_WAKEUP is handled here, any other feature - number is handled as an error.*/ - if (usbp->setup[2] == USB_FEATURE_DEVICE_REMOTE_WAKEUP) { - usbp->status |= 2U; - usbSetupTransfer(usbp, NULL, 0, NULL); - return true; - } - return false; - case (uint32_t)USB_RTYPE_RECIPIENT_DEVICE | ((uint32_t)USB_REQ_SET_ADDRESS << 8): - /* The SET_ADDRESS handling can be performed here or postponed after - the status packed depending on the USB_SET_ADDRESS_MODE low - driver setting.*/ -#if USB_SET_ADDRESS_MODE == USB_EARLY_SET_ADDRESS - if ((usbp->setup[0] == USB_RTYPE_RECIPIENT_DEVICE) && - (usbp->setup[1] == USB_REQ_SET_ADDRESS)) { - set_address(usbp); - } - usbSetupTransfer(usbp, NULL, 0, NULL); -#else - usbSetupTransfer(usbp, NULL, 0, set_address); -#endif - return true; - case (uint32_t)USB_RTYPE_RECIPIENT_DEVICE | ((uint32_t)USB_REQ_GET_DESCRIPTOR << 8): - /* Handling descriptor requests from the host.*/ - dp = usbp->config->get_descriptor_cb(usbp, usbp->setup[3], - usbp->setup[2], - get_hword(&usbp->setup[4])); - if (dp == NULL) { - return false; - } - /*lint -save -e9005 [11.8] Removing const is fine.*/ - usbSetupTransfer(usbp, (uint8_t *)dp->ud_string, dp->ud_size, NULL); - /*lint -restore*/ - return true; - case (uint32_t)USB_RTYPE_RECIPIENT_DEVICE | ((uint32_t)USB_REQ_GET_CONFIGURATION << 8): - /* Returning the last selected configuration.*/ - usbSetupTransfer(usbp, &usbp->configuration, 1, NULL); - return true; - case (uint32_t)USB_RTYPE_RECIPIENT_DEVICE | ((uint32_t)USB_REQ_SET_CONFIGURATION << 8): - /* Handling configuration selection from the host only if it is different - from the current configuration.*/ - if (usbp->configuration != usbp->setup[2]) { - /* If the USB device is already active then we have to perform the clear - procedure on the current configuration.*/ - if (usbp->state == USB_ACTIVE) { - /* Current configuration cleared.*/ - osalSysLockFromISR (); - usbDisableEndpointsI(usbp); - osalSysUnlockFromISR (); - usbp->configuration = 0U; - usbp->state = USB_SELECTED; - _usb_isr_invoke_event_cb(usbp, USB_EVENT_UNCONFIGURED); - } - if (usbp->setup[2] != 0U) { - /* New configuration.*/ - usbp->configuration = usbp->setup[2]; - usbp->state = USB_ACTIVE; - _usb_isr_invoke_event_cb(usbp, USB_EVENT_CONFIGURED); - } - } - usbSetupTransfer(usbp, NULL, 0, NULL); - return true; - case (uint32_t)USB_RTYPE_RECIPIENT_INTERFACE | ((uint32_t)USB_REQ_GET_STATUS << 8): - case (uint32_t)USB_RTYPE_RECIPIENT_ENDPOINT | ((uint32_t)USB_REQ_SYNCH_FRAME << 8): - /* Just sending two zero bytes, the application can change the behavior - using a hook..*/ - /*lint -save -e9005 [11.8] Removing const is fine.*/ - usbSetupTransfer(usbp, (uint8_t *)zero_status, 2, NULL); - /*lint -restore*/ - return true; - case (uint32_t)USB_RTYPE_RECIPIENT_ENDPOINT | ((uint32_t)USB_REQ_GET_STATUS << 8): - /* Sending the EP status.*/ - if ((usbp->setup[4] & 0x80U) != 0U) { - switch (usb_lld_get_status_in(usbp, usbp->setup[4] & 0x0FU)) { - case EP_STATUS_STALLED: - /*lint -save -e9005 [11.8] Removing const is fine.*/ - usbSetupTransfer(usbp, (uint8_t *)halted_status, 2, NULL); - /*lint -restore*/ - return true; - case EP_STATUS_ACTIVE: - /*lint -save -e9005 [11.8] Removing const is fine.*/ - usbSetupTransfer(usbp, (uint8_t *)active_status, 2, NULL); - /*lint -restore*/ - return true; - case EP_STATUS_DISABLED: - default: - return false; - } - } - else { - switch (usb_lld_get_status_out(usbp, usbp->setup[4] & 0x0FU)) { - case EP_STATUS_STALLED: - /*lint -save -e9005 [11.8] Removing const is fine.*/ - usbSetupTransfer(usbp, (uint8_t *)halted_status, 2, NULL); - /*lint -restore*/ - return true; - case EP_STATUS_ACTIVE: - /*lint -save -e9005 [11.8] Removing const is fine.*/ - usbSetupTransfer(usbp, (uint8_t *)active_status, 2, NULL); - /*lint -restore*/ - return true; - case EP_STATUS_DISABLED: - default: - return false; - } - } - case (uint32_t)USB_RTYPE_RECIPIENT_ENDPOINT | ((uint32_t)USB_REQ_CLEAR_FEATURE << 8): - /* Only ENDPOINT_HALT is handled as feature.*/ - if (usbp->setup[2] != USB_FEATURE_ENDPOINT_HALT) { - return false; - } - /* Clearing the EP status, not valid for EP0, it is ignored in that case.*/ - if ((usbp->setup[4] & 0x0FU) != 0U) { - if ((usbp->setup[4] & 0x80U) != 0U) { - usb_lld_clear_in(usbp, usbp->setup[4] & 0x0FU); - } - else { - usb_lld_clear_out(usbp, usbp->setup[4] & 0x0FU); - } - } - usbSetupTransfer(usbp, NULL, 0, NULL); - return true; - case (uint32_t)USB_RTYPE_RECIPIENT_ENDPOINT | ((uint32_t)USB_REQ_SET_FEATURE << 8): - /* Only ENDPOINT_HALT is handled as feature.*/ - if (usbp->setup[2] != USB_FEATURE_ENDPOINT_HALT) { - return false; - } - /* Stalling the EP, not valid for EP0, it is ignored in that case.*/ - if ((usbp->setup[4] & 0x0FU) != 0U) { - if ((usbp->setup[4] & 0x80U) != 0U) { - usb_lld_stall_in(usbp, usbp->setup[4] & 0x0FU); - } - else { - usb_lld_stall_out(usbp, usbp->setup[4] & 0x0FU); - } - } - usbSetupTransfer(usbp, NULL, 0, NULL); - return true; - case (uint32_t)USB_RTYPE_RECIPIENT_DEVICE | ((uint32_t)USB_REQ_SET_DESCRIPTOR << 8): - case (uint32_t)USB_RTYPE_RECIPIENT_INTERFACE | ((uint32_t)USB_REQ_CLEAR_FEATURE << 8): - case (uint32_t)USB_RTYPE_RECIPIENT_INTERFACE | ((uint32_t)USB_REQ_SET_FEATURE << 8): - case (uint32_t)USB_RTYPE_RECIPIENT_INTERFACE | ((uint32_t)USB_REQ_GET_INTERFACE << 8): - case (uint32_t)USB_RTYPE_RECIPIENT_INTERFACE | ((uint32_t)USB_REQ_SET_INTERFACE << 8): - /* All the above requests are not handled here, if you need them then - use the hook mechanism and provide handling.*/ - default: - return false; - } -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief USB Driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void usbInit(void) { - - usb_lld_init(); -} - -/** - * @brief Initializes the standard part of a @p USBDriver structure. - * - * @param[out] usbp pointer to the @p USBDriver object - * - * @init - */ -void usbObjectInit(USBDriver *usbp) { - unsigned i; - - usbp->state = USB_STOP; - usbp->config = NULL; - for (i = 0; i < (unsigned)USB_MAX_ENDPOINTS; i++) { - usbp->in_params[i] = NULL; - usbp->out_params[i] = NULL; - } - usbp->transmitting = 0; - usbp->receiving = 0; -} - -/** - * @brief Configures and activates the USB peripheral. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] config pointer to the @p USBConfig object - * - * @api - */ -void usbStart(USBDriver *usbp, const USBConfig *config) { - unsigned i; - - osalDbgCheck((usbp != NULL) && (config != NULL)); - - osalSysLock(); - osalDbgAssert((usbp->state == USB_STOP) || (usbp->state == USB_READY), - "invalid state"); - usbp->config = config; - for (i = 0; i <= (unsigned)USB_MAX_ENDPOINTS; i++) { - usbp->epc[i] = NULL; - } - usb_lld_start(usbp); - usbp->state = USB_READY; - osalSysUnlock(); -} - -/** - * @brief Deactivates the USB peripheral. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @api - */ -void usbStop(USBDriver *usbp) { - unsigned i; - - osalDbgCheck(usbp != NULL); - - osalSysLock(); - - osalDbgAssert((usbp->state == USB_STOP) || (usbp->state == USB_READY) || - (usbp->state == USB_SELECTED) || (usbp->state == USB_ACTIVE) || - (usbp->state == USB_SUSPENDED), - "invalid state"); - - usb_lld_stop(usbp); - usbp->state = USB_STOP; - - /* Resetting all ongoing synchronous operations.*/ - for (i = 0; i <= (unsigned)USB_MAX_ENDPOINTS; i++) { -#if USB_USE_WAIT == TRUE - if (usbp->epc[i] != NULL) { - if (usbp->epc[i]->in_state != NULL) { - osalThreadResumeI(&usbp->epc[i]->in_state->thread, MSG_RESET); - } - if (usbp->epc[i]->out_state != NULL) { - osalThreadResumeI(&usbp->epc[i]->out_state->thread, MSG_RESET); - } - } -#endif - usbp->epc[i] = NULL; - } - osalOsRescheduleS(); - - osalSysUnlock(); -} - -/** - * @brief Enables an endpoint. - * @details This function enables an endpoint, both IN and/or OUT directions - * depending on the configuration structure. - * @note This function must be invoked in response of a SET_CONFIGURATION - * or SET_INTERFACE message. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @param[in] epcp the endpoint configuration - * - * @iclass - */ -void usbInitEndpointI(USBDriver *usbp, usbep_t ep, - const USBEndpointConfig *epcp) { - - osalDbgCheckClassI(); - osalDbgCheck((usbp != NULL) && (epcp != NULL)); - osalDbgAssert(usbp->state == USB_ACTIVE, - "invalid state"); - osalDbgAssert(usbp->epc[ep] == NULL, "already initialized"); - - /* Logically enabling the endpoint in the USBDriver structure.*/ - usbp->epc[ep] = epcp; - - /* Clearing the state structures, custom fields as well.*/ - if (epcp->in_state != NULL) { - memset(epcp->in_state, 0, sizeof(USBInEndpointState)); - } - if (epcp->out_state != NULL) { - memset(epcp->out_state, 0, sizeof(USBOutEndpointState)); - } - - /* Low level endpoint activation.*/ - usb_lld_init_endpoint(usbp, ep); -} - -/** - * @brief Disables all the active endpoints. - * @details This function disables all the active endpoints except the - * endpoint zero. - * @note This function must be invoked in response of a SET_CONFIGURATION - * message with configuration number zero. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @iclass - */ -void usbDisableEndpointsI(USBDriver *usbp) { - unsigned i; - - osalDbgCheckClassI(); - osalDbgCheck(usbp != NULL); - osalDbgAssert(usbp->state == USB_ACTIVE, "invalid state"); - - usbp->transmitting &= 1U; - usbp->receiving &= 1U; - - for (i = 1; i <= (unsigned)USB_MAX_ENDPOINTS; i++) { -#if USB_USE_WAIT == TRUE - /* Signaling the event to threads waiting on endpoints.*/ - if (usbp->epc[i] != NULL) { - if (usbp->epc[i]->in_state != NULL) { - osalThreadResumeI(&usbp->epc[i]->in_state->thread, MSG_RESET); - } - if (usbp->epc[i]->out_state != NULL) { - osalThreadResumeI(&usbp->epc[i]->out_state->thread, MSG_RESET); - } - } -#endif - usbp->epc[i] = NULL; - } - - /* Low level endpoints deactivation.*/ - usb_lld_disable_endpoints(usbp); -} - -/** - * @brief Starts a receive transaction on an OUT endpoint. - * @note This function is meant to be called from ISR context outside - * critical zones because there is a potentially slow operation - * inside. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @param[out] buf buffer where to copy the received data - * @param[in] n transaction size. It is recommended a multiple of - * the packet size because the excess is discarded. - * - * @iclass - */ -void usbStartReceiveI(USBDriver *usbp, usbep_t ep, - uint8_t *buf, size_t n) { - USBOutEndpointState *osp; - - osalDbgCheckClassI(); - osalDbgCheck((usbp != NULL) && (ep <= (usbep_t)USB_MAX_ENDPOINTS)); - osalDbgAssert(!usbGetReceiveStatusI(usbp, ep), "already receiving"); - - /* Marking the endpoint as active.*/ - usbp->receiving |= (uint16_t)((unsigned)1U << (unsigned)ep); - - /* Setting up the transfer.*/ - /*lint -save -e661 [18.1] pclint is confused by the check on ep.*/ - osp = usbp->epc[ep]->out_state; - /*lint -restore*/ - osp->rxbuf = buf; - osp->rxsize = n; - osp->rxcnt = 0; -#if USB_USE_WAIT == TRUE - osp->thread = NULL; -#endif - - /* Starting transfer.*/ - usb_lld_start_out(usbp, ep); -} - -/** - * @brief Starts a transmit transaction on an IN endpoint. - * @note This function is meant to be called from ISR context outside - * critical zones because there is a potentially slow operation - * inside. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @param[in] buf buffer where to fetch the data to be transmitted - * @param[in] n transaction size - * - * @iclass - */ -void usbStartTransmitI(USBDriver *usbp, usbep_t ep, - const uint8_t *buf, size_t n) { - USBInEndpointState *isp; - - osalDbgCheckClassI(); - osalDbgCheck((usbp != NULL) && (ep <= (usbep_t)USB_MAX_ENDPOINTS)); - osalDbgAssert(!usbGetTransmitStatusI(usbp, ep), "already transmitting"); - - /* Marking the endpoint as active.*/ - usbp->transmitting |= (uint16_t)((unsigned)1U << (unsigned)ep); - - /* Setting up the transfer.*/ - /*lint -save -e661 [18.1] pclint is confused by the check on ep.*/ - isp = usbp->epc[ep]->in_state; - /*lint -restore*/ - isp->txbuf = buf; - isp->txsize = n; - isp->txcnt = 0; -#if USB_USE_WAIT == TRUE - isp->thread = NULL; -#endif - - /* Starting transfer.*/ - usb_lld_start_in(usbp, ep); -} - -#if (USB_USE_WAIT == TRUE) || defined(__DOXYGEN__) -/** - * @brief Performs a receive transaction on an OUT endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @param[out] buf buffer where to copy the received data - * @param[in] n transaction size. It is recommended a multiple of - * the packet size because the excess is discarded. - * - * @return The received effective data size, it can be less than - * the amount specified. - * @retval MSG_RESET driver not in @p USB_ACTIVE state or the operation - * has been aborted by an USB reset or a transition to - * the @p USB_SUSPENDED state. - * - * @api - */ -msg_t usbReceive(USBDriver *usbp, usbep_t ep, uint8_t *buf, size_t n) { - msg_t msg; - - osalSysLock(); - - if (usbGetDriverStateI(usbp) != USB_ACTIVE) { - osalSysUnlock(); - return MSG_RESET; - } - - usbStartReceiveI(usbp, ep, buf, n); - msg = osalThreadSuspendS(&usbp->epc[ep]->out_state->thread); - osalSysUnlock(); - - return msg; -} - -/** - * @brief Performs a transmit transaction on an IN endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @param[in] buf buffer where to fetch the data to be transmitted - * @param[in] n transaction size - * - * @return The operation status. - * @retval MSG_OK operation performed successfully. - * @retval MSG_RESET driver not in @p USB_ACTIVE state or the operation - * has been aborted by an USB reset or a transition to - * the @p USB_SUSPENDED state. - * - * @api - */ -msg_t usbTransmit(USBDriver *usbp, usbep_t ep, const uint8_t *buf, size_t n) { - msg_t msg; - - osalSysLock(); - - if (usbGetDriverStateI(usbp) != USB_ACTIVE) { - osalSysUnlock(); - return MSG_RESET; - } - - usbStartTransmitI(usbp, ep, buf, n); - msg = osalThreadSuspendS(&usbp->epc[ep]->in_state->thread); - osalSysUnlock(); - - return msg; -} -#endif /* USB_USE_WAIT == TRUE */ - -/** - * @brief Stalls an OUT endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @return The operation status. - * @retval false Endpoint stalled. - * @retval true Endpoint busy, not stalled. - * - * @iclass - */ -bool usbStallReceiveI(USBDriver *usbp, usbep_t ep) { - - osalDbgCheckClassI(); - osalDbgCheck(usbp != NULL); - - if (usbGetReceiveStatusI(usbp, ep)) { - return true; - } - - usb_lld_stall_out(usbp, ep); - return false; -} - -/** - * @brief Stalls an IN endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @return The operation status. - * @retval false Endpoint stalled. - * @retval true Endpoint busy, not stalled. - * - * @iclass - */ -bool usbStallTransmitI(USBDriver *usbp, usbep_t ep) { - - osalDbgCheckClassI(); - osalDbgCheck(usbp != NULL); - - if (usbGetTransmitStatusI(usbp, ep)) { - return true; - } - - usb_lld_stall_in(usbp, ep); - return false; -} - -/** - * @brief USB reset routine. - * @details This function must be invoked when an USB bus reset condition is - * detected. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -void _usb_reset(USBDriver *usbp) { - unsigned i; - - /* State transition.*/ - usbp->state = USB_READY; - - /* Resetting internal state.*/ - usbp->status = 0; - usbp->address = 0; - usbp->configuration = 0; - usbp->transmitting = 0; - usbp->receiving = 0; - - /* Invalidates all endpoints into the USBDriver structure.*/ - for (i = 0; i <= (unsigned)USB_MAX_ENDPOINTS; i++) { -#if USB_USE_WAIT == TRUE - /* Signaling the event to threads waiting on endpoints.*/ - if (usbp->epc[i] != NULL) { - osalSysLockFromISR(); - if (usbp->epc[i]->in_state != NULL) { - osalThreadResumeI(&usbp->epc[i]->in_state->thread, MSG_RESET); - } - if (usbp->epc[i]->out_state != NULL) { - osalThreadResumeI(&usbp->epc[i]->out_state->thread, MSG_RESET); - } - osalSysUnlockFromISR(); - } -#endif - usbp->epc[i] = NULL; - } - - /* EP0 state machine initialization.*/ - usbp->ep0state = USB_EP0_WAITING_SETUP; - - /* Low level reset.*/ - usb_lld_reset(usbp); - - /* Notification of reset event.*/ - _usb_isr_invoke_event_cb(usbp, USB_EVENT_RESET); -} - -/** - * @brief USB suspend routine. - * @details This function must be invoked when an USB bus suspend condition is - * detected. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -void _usb_suspend(USBDriver *usbp) { - /* No state change, suspend always returns to previous state. */ - - /* State transition.*/ - usbp->saved_state = usbp->state; - usbp->state = USB_SUSPENDED; - - /* Notification of suspend event.*/ - _usb_isr_invoke_event_cb(usbp, USB_EVENT_SUSPEND); - - /* Signaling the event to threads waiting on endpoints.*/ -#if USB_USE_WAIT == TRUE - { - unsigned i; - - for (i = 0; i <= (unsigned)USB_MAX_ENDPOINTS; i++) { - if (usbp->epc[i] != NULL) { - osalSysLockFromISR(); - if (usbp->epc[i]->in_state != NULL) { - osalThreadResumeI(&usbp->epc[i]->in_state->thread, MSG_RESET); - } - if (usbp->epc[i]->out_state != NULL) { - osalThreadResumeI(&usbp->epc[i]->out_state->thread, MSG_RESET); - } - osalSysUnlockFromISR(); - } - } - } -#endif -} - -/** - * @brief USB wake-up routine. - * @details This function must be invoked when an USB bus wake-up condition is - * detected. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -void _usb_wakeup(USBDriver *usbp) { - - /* State transition, returning to the previous state.*/ - usbp->state = usbp->saved_state; - - /* Notification of suspend event.*/ - _usb_isr_invoke_event_cb(usbp, USB_EVENT_WAKEUP); -} - -/** - * @brief Default EP0 SETUP callback. - * @details This function is used by the low level driver as default handler - * for EP0 SETUP events. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number, always zero - * - * @notapi - */ -void _usb_ep0setup(USBDriver *usbp, usbep_t ep) { - size_t max; - - usbp->ep0state = USB_EP0_WAITING_SETUP; - usbReadSetup(usbp, ep, usbp->setup); - - /* First verify if the application has an handler installed for this - request.*/ - /*lint -save -e9007 [13.5] No side effects, it is intentional.*/ - if ((usbp->config->requests_hook_cb == NULL) || - !(usbp->config->requests_hook_cb(usbp))) { - /*lint -restore*/ - /* Invoking the default handler, if this fails then stalls the - endpoint zero as error.*/ - /*lint -save -e9007 [13.5] No side effects, it is intentional.*/ - if (((usbp->setup[0] & USB_RTYPE_TYPE_MASK) != USB_RTYPE_TYPE_STD) || - !default_handler(usbp)) { - /*lint -restore*/ - /* Error response, the state machine goes into an error state, the low - level layer will have to reset it to USB_EP0_WAITING_SETUP after - receiving a SETUP packet.*/ - usb_lld_stall_in(usbp, 0); - usb_lld_stall_out(usbp, 0); - _usb_isr_invoke_event_cb(usbp, USB_EVENT_STALLED); - usbp->ep0state = USB_EP0_ERROR; - return; - } - } -#if (USB_SET_ADDRESS_ACK_HANDLING == USB_SET_ADDRESS_ACK_HW) - if (usbp->setup[1] == USB_REQ_SET_ADDRESS) { - /* Zero-length packet sent by hardware */ - return; - } -#endif - /* Transfer preparation. The request handler must have populated - correctly the fields ep0next, ep0n and ep0endcb using the macro - usbSetupTransfer().*/ - max = (size_t)get_hword(&usbp->setup[6]); - /* The transfer size cannot exceed the specified amount.*/ - if (usbp->ep0n > max) { - usbp->ep0n = max; - } - if ((usbp->setup[0] & USB_RTYPE_DIR_MASK) == USB_RTYPE_DIR_DEV2HOST) { - /* IN phase.*/ - if (usbp->ep0n != 0U) { - /* Starts the transmit phase.*/ - usbp->ep0state = USB_EP0_TX; - osalSysLockFromISR(); - usbStartTransmitI(usbp, 0, usbp->ep0next, usbp->ep0n); - osalSysUnlockFromISR(); - } - else { - /* No transmission phase, directly receiving the zero sized status - packet.*/ - usbp->ep0state = USB_EP0_WAITING_STS; -#if (USB_EP0_STATUS_STAGE == USB_EP0_STATUS_STAGE_SW) - osalSysLockFromISR(); - usbStartReceiveI(usbp, 0, NULL, 0); - osalSysUnlockFromISR(); -#else - usb_lld_end_setup(usbp, ep); -#endif - } - } - else { - /* OUT phase.*/ - if (usbp->ep0n != 0U) { - /* Starts the receive phase.*/ - usbp->ep0state = USB_EP0_RX; - osalSysLockFromISR(); - usbStartReceiveI(usbp, 0, usbp->ep0next, usbp->ep0n); - osalSysUnlockFromISR(); - } - else { - /* No receive phase, directly sending the zero sized status - packet.*/ - usbp->ep0state = USB_EP0_SENDING_STS; -#if (USB_EP0_STATUS_STAGE == USB_EP0_STATUS_STAGE_SW) - osalSysLockFromISR(); - usbStartTransmitI(usbp, 0, NULL, 0); - osalSysUnlockFromISR(); -#else - usb_lld_end_setup(usbp, ep); -#endif - } - } -} - -/** - * @brief Default EP0 IN callback. - * @details This function is used by the low level driver as default handler - * for EP0 IN events. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number, always zero - * - * @notapi - */ -void _usb_ep0in(USBDriver *usbp, usbep_t ep) { - size_t max; - - (void)ep; - switch (usbp->ep0state) { - case USB_EP0_TX: - max = (size_t)get_hword(&usbp->setup[6]); - /* If the transmitted size is less than the requested size and it is a - multiple of the maximum packet size then a zero size packet must be - transmitted.*/ - if ((usbp->ep0n < max) && - ((usbp->ep0n % usbp->epc[0]->in_maxsize) == 0U)) { - osalSysLockFromISR(); - usbStartTransmitI(usbp, 0, NULL, 0); - osalSysUnlockFromISR(); - usbp->ep0state = USB_EP0_WAITING_TX0; - return; - } - /* Falls into, it is intentional.*/ - case USB_EP0_WAITING_TX0: - /* Transmit phase over, receiving the zero sized status packet.*/ - usbp->ep0state = USB_EP0_WAITING_STS; -#if (USB_EP0_STATUS_STAGE == USB_EP0_STATUS_STAGE_SW) - osalSysLockFromISR(); - usbStartReceiveI(usbp, 0, NULL, 0); - osalSysUnlockFromISR(); -#else - usb_lld_end_setup(usbp, ep); -#endif - return; - case USB_EP0_SENDING_STS: - /* Status packet sent, invoking the callback if defined.*/ - if (usbp->ep0endcb != NULL) { - usbp->ep0endcb(usbp); - } - usbp->ep0state = USB_EP0_WAITING_SETUP; - return; - case USB_EP0_WAITING_SETUP: - case USB_EP0_WAITING_STS: - case USB_EP0_RX: - /* All the above are invalid states in the IN phase.*/ - osalDbgAssert(false, "EP0 state machine error"); - /* Falling through is intentional.*/ - case USB_EP0_ERROR: - /* Error response, the state machine goes into an error state, the low - level layer will have to reset it to USB_EP0_WAITING_SETUP after - receiving a SETUP packet.*/ - usb_lld_stall_in(usbp, 0); - usb_lld_stall_out(usbp, 0); - _usb_isr_invoke_event_cb(usbp, USB_EVENT_STALLED); - usbp->ep0state = USB_EP0_ERROR; - return; - default: - osalDbgAssert(false, "EP0 state machine invalid state"); - } -} - -/** - * @brief Default EP0 OUT callback. - * @details This function is used by the low level driver as default handler - * for EP0 OUT events. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number, always zero - * - * @notapi - */ -void _usb_ep0out(USBDriver *usbp, usbep_t ep) { - - (void)ep; - switch (usbp->ep0state) { - case USB_EP0_RX: - /* Receive phase over, sending the zero sized status packet.*/ - usbp->ep0state = USB_EP0_SENDING_STS; -#if (USB_EP0_STATUS_STAGE == USB_EP0_STATUS_STAGE_SW) - osalSysLockFromISR(); - usbStartTransmitI(usbp, 0, NULL, 0); - osalSysUnlockFromISR(); -#else - usb_lld_end_setup(usbp, ep); -#endif - return; - case USB_EP0_WAITING_STS: - /* Status packet received, it must be zero sized, invoking the callback - if defined.*/ -#if (USB_EP0_STATUS_STAGE == USB_EP0_STATUS_STAGE_SW) - if (usbGetReceiveTransactionSizeX(usbp, 0) != 0U) { - break; - } -#endif - if (usbp->ep0endcb != NULL) { - usbp->ep0endcb(usbp); - } - usbp->ep0state = USB_EP0_WAITING_SETUP; - return; - case USB_EP0_WAITING_SETUP: - case USB_EP0_TX: - case USB_EP0_WAITING_TX0: - case USB_EP0_SENDING_STS: - /* All the above are invalid states in the IN phase.*/ - osalDbgAssert(false, "EP0 state machine error"); - /* Falling through is intentional.*/ - case USB_EP0_ERROR: - /* Error response, the state machine goes into an error state, the low - level layer will have to reset it to USB_EP0_WAITING_SETUP after - receiving a SETUP packet.*/ - usb_lld_stall_in(usbp, 0); - usb_lld_stall_out(usbp, 0); - _usb_isr_invoke_event_cb(usbp, USB_EVENT_STALLED); - usbp->ep0state = USB_EP0_ERROR; - return; - default: - osalDbgAssert(false, "EP0 state machine invalid state"); - } -} - -#endif /* HAL_USE_USB == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/src/wdg.c b/firmware/ChibiOS_16/os/hal/src/wdg.c deleted file mode 100644 index e1b59728b1..0000000000 --- a/firmware/ChibiOS_16/os/hal/src/wdg.c +++ /dev/null @@ -1,120 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file wdg.c - * @brief WDG Driver code. - * - * @addtogroup WDG - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_WDG == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief WDG Driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void wdgInit(void) { - - wdg_lld_init(); -} - -/** - * @brief Configures and activates the WDG peripheral. - * - * @param[in] wdgp pointer to the @p WDGDriver object - * @param[in] config pointer to the @p WDGConfig object - * - * @api - */ -void wdgStart(WDGDriver *wdgp, const WDGConfig *config) { - - osalDbgCheck((wdgp != NULL) && (config != NULL)); - - osalSysLock(); - osalDbgAssert((wdgp->state == WDG_STOP) || (wdgp->state == WDG_READY), - "invalid state"); - wdgp->config = config; - wdg_lld_start(wdgp); - wdgp->state = WDG_READY; - osalSysUnlock(); -} - -/** - * @brief Deactivates the WDG peripheral. - * - * @param[in] wdgp pointer to the @p WDGDriver object - * - * @api - */ -void wdgStop(WDGDriver *wdgp) { - - osalDbgCheck(wdgp != NULL); - - osalSysLock(); - osalDbgAssert((wdgp->state == WDG_STOP) || (wdgp->state == WDG_READY), - "invalid state"); - wdg_lld_stop(wdgp); - wdgp->state = WDG_STOP; - osalSysUnlock(); -} - -/** - * @brief Resets WDG's counter. - * - * @param[in] wdgp pointer to the @p WDGDriver object - * - * @api - */ -void wdgReset(WDGDriver *wdgp) { - - osalDbgCheck(wdgp != NULL); - - osalSysLock(); - osalDbgAssert(wdgp->state == WDG_READY, "not ready"); - wdgResetI(wdgp); - osalSysUnlock(); -} - -#endif /* HAL_USE_WDG == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/adc_lld.c b/firmware/ChibiOS_16/os/hal/templates/adc_lld.c deleted file mode 100644 index 12993d51d3..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/adc_lld.c +++ /dev/null @@ -1,141 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file adc_lld.c - * @brief PLATFORM ADC subsystem low level driver source. - * - * @addtogroup ADC - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_ADC == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief ADC1 driver identifier. - */ -#if (PLATFORM_ADC_USE_ADC1 == TRUE) || defined(__DOXYGEN__) -ADCDriver ADCD1; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level ADC driver initialization. - * - * @notapi - */ -void adc_lld_init(void) { - -#if PLATFORM_ADC_USE_ADC1 == TRUE - /* Driver initialization.*/ - adcObjectInit(&ADCD1); -#endif -} - -/** - * @brief Configures and activates the ADC peripheral. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_start(ADCDriver *adcp) { - - if (adcp->state == ADC_STOP) { - /* Enables the peripheral.*/ -#if PLATFORM_ADC_USE_ADC1 == TRUE - if (&ADCD1 == adcp) { - - } -#endif - } - /* Configures the peripheral.*/ - -} - -/** - * @brief Deactivates the ADC peripheral. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_stop(ADCDriver *adcp) { - - if (adcp->state == ADC_READY) { - /* Resets the peripheral.*/ - - /* Disables the peripheral.*/ -#if PLATFORM_ADC_USE_ADC1 == TRUE - if (&ADCD1 == adcp) { - - } -#endif - } -} - -/** - * @brief Starts an ADC conversion. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_start_conversion(ADCDriver *adcp) { - - (void)adcp; -} - -/** - * @brief Stops an ongoing conversion. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_stop_conversion(ADCDriver *adcp) { - - (void)adcp; -} - -#endif /* HAL_USE_ADC == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/adc_lld.h b/firmware/ChibiOS_16/os/hal/templates/adc_lld.h deleted file mode 100644 index 7c1e4fff5b..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/adc_lld.h +++ /dev/null @@ -1,211 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file adc_lld.h - * @brief PLATFORM ADC subsystem low level driver header. - * - * @addtogroup ADC - * @{ - */ - -#ifndef _ADC_LLD_H_ -#define _ADC_LLD_H_ - -#if (HAL_USE_ADC == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name PLATFORM configuration options - * @{ - */ -/** - * @brief ADC1 driver enable switch. - * @details If set to @p TRUE the support for ADC1 is included. - * @note The default is @p FALSE. - */ -#if !defined(PLATFORM_ADC_USE_ADC1) || defined(__DOXYGEN__) -#define PLATFORM_ADC_USE_ADC1 FALSE -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief ADC sample data type. - */ -typedef uint16_t adcsample_t; - -/** - * @brief Channels number in a conversion group. - */ -typedef uint16_t adc_channels_num_t; - -/** - * @brief Possible ADC failure causes. - * @note Error codes are architecture dependent and should not relied - * upon. - */ -typedef enum { - ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */ - ADC_ERR_OVERFLOW = 1, /**< ADC overflow condition. */ - ADC_ERR_AWD = 2 /**< Analog watchdog triggered. */ -} adcerror_t; - -/** - * @brief Type of a structure representing an ADC driver. - */ -typedef struct ADCDriver ADCDriver; - -/** - * @brief ADC notification callback type. - * - * @param[in] adcp pointer to the @p ADCDriver object triggering the - * callback - * @param[in] buffer pointer to the most recent samples data - * @param[in] n number of buffer rows available starting from @p buffer - */ -typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n); - -/** - * @brief ADC error callback type. - * - * @param[in] adcp pointer to the @p ADCDriver object triggering the - * callback - * @param[in] err ADC error code - */ -typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err); - -/** - * @brief Conversion group configuration structure. - * @details This implementation-dependent structure describes a conversion - * operation. - * @note The use of this configuration structure requires knowledge of - * PLATFORM ADC cell registers interface, please refer to the PLATFORM - * reference manual for details. - */ -typedef struct { - /** - * @brief Enables the circular buffer mode for the group. - */ - bool circular; - /** - * @brief Number of the analog channels belonging to the conversion group. - */ - adc_channels_num_t num_channels; - /** - * @brief Callback function associated to the group or @p NULL. - */ - adccallback_t end_cb; - /** - * @brief Error callback or @p NULL. - */ - adcerrorcallback_t error_cb; - /* End of the mandatory fields.*/ -} ADCConversionGroup; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - uint32_t dummy; -} ADCConfig; - -/** - * @brief Structure representing an ADC driver. - */ -struct ADCDriver { - /** - * @brief Driver state. - */ - adcstate_t state; - /** - * @brief Current configuration data. - */ - const ADCConfig *config; - /** - * @brief Current samples buffer pointer or @p NULL. - */ - adcsample_t *samples; - /** - * @brief Current samples buffer depth or @p 0. - */ - size_t depth; - /** - * @brief Current conversion group pointer or @p NULL. - */ - const ADCConversionGroup *grpp; -#if (ADC_USE_WAIT == TRUE) || defined(__DOXYGEN__) - /** - * @brief Waiting thread. - */ - thread_reference_t thread; -#endif -#if (ADC_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the peripheral. - */ - mutex_t mutex; -#endif -#if defined(ADC_DRIVER_EXT_FIELDS) - ADC_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if (PLATFORM_ADC_USE_ADC1 == TRUE) && !defined(__DOXYGEN__) -extern ADCDriver ADCD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void adc_lld_init(void); - void adc_lld_start(ADCDriver *adcp); - void adc_lld_stop(ADCDriver *adcp); - void adc_lld_start_conversion(ADCDriver *adcp); - void adc_lld_stop_conversion(ADCDriver *adcp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_ADC == TRUE */ - -#endif /* _ADC_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/can_lld.c b/firmware/ChibiOS_16/os/hal/templates/can_lld.c deleted file mode 100644 index 816e02dad0..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/can_lld.c +++ /dev/null @@ -1,242 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file can_lld.c - * @brief PLATFORM CAN subsystem low level driver source. - * - * @addtogroup CAN - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_CAN == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief CAN1 driver identifier. - */ -#if (PLATFORM_CAN_USE_CAN1 == TRUE) || defined(__DOXYGEN__) -CANDriver CAND1; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level CAN driver initialization. - * - * @notapi - */ -void can_lld_init(void) { - -#if PLATFORM_CAN_USE_CAN1 == TRUE - /* Driver initialization.*/ - canObjectInit(&CAND1); -#endif -} - -/** - * @brief Configures and activates the CAN peripheral. - * - * @param[in] canp pointer to the @p CANDriver object - * - * @notapi - */ -void can_lld_start(CANDriver *canp) { - - if (canp->state == CAN_STOP) { - /* Enables the peripheral.*/ -#if PLATFORM_CAN_USE_CAN1 == TRUE - if (&CAND1 == canp) { - - } -#endif - } - /* Configures the peripheral.*/ - -} - -/** - * @brief Deactivates the CAN peripheral. - * - * @param[in] canp pointer to the @p CANDriver object - * - * @notapi - */ -void can_lld_stop(CANDriver *canp) { - - if (canp->state == CAN_READY) { - /* Resets the peripheral.*/ - - /* Disables the peripheral.*/ -#if PLATFORM_CAN_USE_CAN1 == TRUE - if (&CAND1 == canp) { - - } -#endif - } -} - -/** - * @brief Determines whether a frame can be transmitted. - * - * @param[in] canp pointer to the @p CANDriver object - * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox - * - * @return The queue space availability. - * @retval FALSE no space in the transmit queue. - * @retval TRUE transmit slot available. - * - * @notapi - */ -bool can_lld_is_tx_empty(CANDriver *canp, canmbx_t mailbox) { - - (void)canp; - - switch (mailbox) { - case CAN_ANY_MAILBOX: - return false; - case 1: - return false; - case 2: - return false; - case 3: - return false; - default: - return false; - } -} - -/** - * @brief Inserts a frame into the transmit queue. - * - * @param[in] canp pointer to the @p CANDriver object - * @param[in] ctfp pointer to the CAN frame to be transmitted - * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox - * - * @notapi - */ -void can_lld_transmit(CANDriver *canp, - canmbx_t mailbox, - const CANTxFrame *ctfp) { - - (void)canp; - (void)mailbox; - (void)ctfp; - -} - -/** - * @brief Determines whether a frame has been received. - * - * @param[in] canp pointer to the @p CANDriver object - * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox - * - * @return The queue space availability. - * @retval FALSE no space in the transmit queue. - * @retval TRUE transmit slot available. - * - * @notapi - */ -bool can_lld_is_rx_nonempty(CANDriver *canp, canmbx_t mailbox) { - - (void)canp; - (void)mailbox; - - switch (mailbox) { - case CAN_ANY_MAILBOX: - return false; - case 1: - return false; - case 2: - return false; - default: - return false; - } -} - -/** - * @brief Receives a frame from the input queue. - * - * @param[in] canp pointer to the @p CANDriver object - * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox - * @param[out] crfp pointer to the buffer where the CAN frame is copied - * - * @notapi - */ -void can_lld_receive(CANDriver *canp, - canmbx_t mailbox, - CANRxFrame *crfp) { - - (void)canp; - (void)mailbox; - (void)crfp; - -} - -#if (CAN_USE_SLEEP_MODE == TRUE) || defined(__DOXYGEN__) -/** - * @brief Enters the sleep mode. - * - * @param[in] canp pointer to the @p CANDriver object - * - * @notapi - */ -void can_lld_sleep(CANDriver *canp) { - - (void)canp; - -} - -/** - * @brief Enforces leaving the sleep mode. - * - * @param[in] canp pointer to the @p CANDriver object - * - * @notapi - */ -void can_lld_wakeup(CANDriver *canp) { - - (void)canp; - -} -#endif /* CAN_USE_SLEEP_MOD == TRUEE */ - -#endif /* HAL_USE_CAN == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/can_lld.h b/firmware/ChibiOS_16/os/hal/templates/can_lld.h deleted file mode 100644 index bd05bde84c..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/can_lld.h +++ /dev/null @@ -1,228 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file can_lld.h - * @brief PLATFORM CAN subsystem low level driver header. - * - * @addtogroup CAN - * @{ - */ - -#ifndef _CAN_LLD_H_ -#define _CAN_LLD_H_ - -#if (HAL_USE_CAN == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Number of transmit mailboxes. - */ -#define CAN_TX_MAILBOXES 1 - -/** - * @brief Number of receive mailboxes. - */ -#define CAN_RX_MAILBOXES 1 - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name PLATFORM configuration options - * @{ - */ -/** - * @brief CAN1 driver enable switch. - * @details If set to @p TRUE the support for CAN1 is included. - * @note The default is @p FALSE. - */ -#if !defined(PLATFORM_CAN_USE_CAN1) || defined(__DOXYGEN__) -#define PLATFORM_CAN_USE_CAN1 FALSE -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a transmission mailbox index. - */ -typedef uint32_t canmbx_t; - -/** - * @brief CAN transmission frame. - * @note Accessing the frame data as word16 or word32 is not portable because - * machine data endianness, it can be still useful for a quick filling. - */ -typedef struct { - /*lint -save -e46 [6.1] Standard types are fine too.*/ - uint8_t DLC:4; /**< @brief Data length. */ - uint8_t RTR:1; /**< @brief Frame type. */ - uint8_t IDE:1; /**< @brief Identifier type. */ - union { - uint32_t SID:11; /**< @brief Standard identifier.*/ - uint32_t EID:29; /**< @brief Extended identifier.*/ - uint32_t _align1; - }; - /*lint -restore*/ - union { - uint8_t data8[8]; /**< @brief Frame data. */ - uint16_t data16[4]; /**< @brief Frame data. */ - uint32_t data32[2]; /**< @brief Frame data. */ - }; -} CANTxFrame; - -/** - * @brief CAN received frame. - * @note Accessing the frame data as word16 or word32 is not portable because - * machine data endianness, it can be still useful for a quick filling. - */ -typedef struct { - /*lint -save -e46 [6.1] Standard types are fine too.*/ - uint8_t FMI; /**< @brief Filter id. */ - uint16_t TIME; /**< @brief Time stamp. */ - uint8_t DLC:4; /**< @brief Data length. */ - uint8_t RTR:1; /**< @brief Frame type. */ - uint8_t IDE:1; /**< @brief Identifier type. */ - union { - uint32_t SID:11; /**< @brief Standard identifier.*/ - uint32_t EID:29; /**< @brief Extended identifier.*/ - uint32_t _align1; - }; - /*lint -restore*/ - union { - uint8_t data8[8]; /**< @brief Frame data. */ - uint16_t data16[4]; /**< @brief Frame data. */ - uint32_t data32[2]; /**< @brief Frame data. */ - }; -} CANRxFrame; - -/** - * @brief Driver configuration structure. - */ -typedef struct { - /* End of the mandatory fields.*/ - uint32_t dummy; -} CANConfig; - -/** - * @brief Structure representing an CAN driver. - */ -typedef struct { - /** - * @brief Driver state. - */ - canstate_t state; - /** - * @brief Current configuration data. - */ - const CANConfig *config; - /** - * @brief Transmission threads queue. - */ - threads_queue_t txqueue; - /** - * @brief Receive threads queue. - */ - threads_queue_t rxqueue; - /** - * @brief One or more frames become available. - * @note After broadcasting this event it will not be broadcasted again - * until the received frames queue has been completely emptied. It - * is not broadcasted for each received frame. It is - * responsibility of the application to empty the queue by - * repeatedly invoking @p chReceive() when listening to this event. - * This behavior minimizes the interrupt served by the system - * because CAN traffic. - * @note The flags associated to the listeners will indicate which - * receive mailboxes become non-empty. - */ - event_source_t rxfull_event; - /** - * @brief One or more transmission mailbox become available. - * @note The flags associated to the listeners will indicate which - * transmit mailboxes become empty. - * - */ - event_source_t txempty_event; - /** - * @brief A CAN bus error happened. - * @note The flags associated to the listeners will indicate the - * error(s) that have occurred. - */ - event_source_t error_event; -#if (CAN_USE_SLEEP_MODE == TRUE) || defined (__DOXYGEN__) - /** - * @brief Entering sleep state event. - */ - event_source_t sleep_event; - /** - * @brief Exiting sleep state event. - */ - event_source_t wakeup_event; -#endif - /* End of the mandatory fields.*/ -} CANDriver; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if (PLATFORM_CAN_USE_CAN1 == TRUE) && !defined(__DOXYGEN__) -extern CANDriver CAND1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void can_lld_init(void); - void can_lld_start(CANDriver *canp); - void can_lld_stop(CANDriver *canp); - bool can_lld_is_tx_empty(CANDriver *canp, canmbx_t mailbox); - void can_lld_transmit(CANDriver *canp, - canmbx_t mailbox, - const CANTxFrame *ctfp); - bool can_lld_is_rx_nonempty(CANDriver *canp, canmbx_t mailbox); - void can_lld_receive(CANDriver *canp, - canmbx_t mailbox, - CANRxFrame *crfp); -#if CAN_USE_SLEEP_MODE == TRUE - void can_lld_sleep(CANDriver *canp); - void can_lld_wakeup(CANDriver *canp); -#endif -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_CAN == TRUE */ - -#endif /* _CAN_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/dac_lld.c b/firmware/ChibiOS_16/os/hal/templates/dac_lld.c deleted file mode 100644 index 63fd6aa800..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/dac_lld.c +++ /dev/null @@ -1,170 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file dac_lld.c - * @brief PLATFORM DAC subsystem low level driver source. - * - * @addtogroup DAC - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_DAC == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief DAC1 driver identifier.*/ -#if (PLATFORM_DAC_USE_DAC1 == TRUE) || defined(__DOXYGEN__) -DACDriver DACD1; -#endif - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level DAC driver initialization. - * - * @notapi - */ -void dac_lld_init(void) { - -#if PLATFORM_DAC_USE_DAC1 == TRUE - dacObjectInit(&DACD1); -#endif -} - -/** - * @brief Configures and activates the DAC peripheral. - * - * @param[in] dacp pointer to the @p DACDriver object - * - * @notapi - */ -void dac_lld_start(DACDriver *dacp) { - - /* If the driver is in DAC_STOP state then a full initialization is - required.*/ - if (dacp->state == DAC_STOP) { - /* Enabling the clock source.*/ -#if PLATFORM_DAC_USE_DAC1 == TRUE - if (&DACD1 == dacp) { - - } -#endif - } -} - -/** - * @brief Deactivates the DAC peripheral. - * - * @param[in] dacp pointer to the @p DACDriver object - * - * @notapi - */ -void dac_lld_stop(DACDriver *dacp) { - - /* If in ready state then disables the DAC clock.*/ - if (dacp->state == DAC_READY) { - - /* Disabling DAC.*/ - dacp->params->dac->CR &= dacp->params->regmask; - -#if PLATFORM_DAC_USE_DAC1 == TRUE - if (&DACD1 == dacp) { - - } -#endif - } -} - -/** - * @brief Outputs a value directly on a DAC channel. - * - * @param[in] dacp pointer to the @p DACDriver object - * @param[in] channel DAC channel number - * @param[in] sample value to be output - * - * @api - */ -void dac_lld_put_channel(DACDriver *dacp, - dacchannel_t channel, - dacsample_t sample) { - - (void)dacp; - (void)channel; - (void)sample; -} - -/** - * @brief Starts a DAC conversion. - * @details Starts an asynchronous conversion operation. - * @note In @p DAC_DHRM_8BIT_RIGHT mode the parameters passed to the - * callback are wrong because two samples are packed in a single - * dacsample_t element. This will not be corrected, do not rely - * on those parameters. - * @note In @p DAC_DHRM_8BIT_RIGHT_DUAL mode two samples are treated - * as a single 16 bits sample and packed into a single dacsample_t - * element. The num_channels must be set to one in the group - * conversion configuration structure. - * - * @param[in] dacp pointer to the @p DACDriver object - * - * @notapi - */ -void dac_lld_start_conversion(DACDriver *dacp) { - - (void)dacp; -} - -/** - * @brief Stops an ongoing conversion. - * @details This function stops the currently ongoing conversion and returns - * the driver in the @p DAC_READY state. If there was no conversion - * being processed then the function does nothing. - * - * @param[in] dacp pointer to the @p DACDriver object - * - * @iclass - */ -void dac_lld_stop_conversion(DACDriver *dacp) { - - (void)dacp; -} - -#endif /* HAL_USE_DAC == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/dac_lld.h b/firmware/ChibiOS_16/os/hal/templates/dac_lld.h deleted file mode 100644 index 1d31cd39b5..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/dac_lld.h +++ /dev/null @@ -1,211 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file dac_lld.h - * @brief PLATFORM DAC subsystem low level driver header. - * - * @addtogroup DAC - * @{ - */ - -#ifndef _DAC_LLD_H_ -#define _DAC_LLD_H_ - -#if HAL_USE_DAC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Maximum number of DAC channels per unit. - */ -#define DAC_MAX_CHANNELS 2 - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief DAC1 CH1 driver enable switch. - * @details If set to @p TRUE the support for DAC1 channel 1 is included. - * @note The default is @p FALSE. - */ -#if !defined(PLATFORM_DAC_USE_DAC1) || defined(__DOXYGEN__) -#define PLATFORM_DAC_USE_DAC1 FALSE -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a DAC channel index. - */ -typedef uint32_t dacchannel_t; - -/** - * @brief Type of a structure representing an DAC driver. - */ -typedef struct DACDriver DACDriver; - -/** - * @brief Type representing a DAC sample. - */ -typedef uint16_t dacsample_t; - -/** - * @brief Possible DAC failure causes. - * @note Error codes are architecture dependent and should not relied - * upon. - */ -typedef enum { - DAC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */ - DAC_ERR_UNDERFLOW = 1 /**< DAC overflow condition. */ -} dacerror_t; - -/** - * @brief DAC notification callback type. - * - * @param[in] dacp pointer to the @p DACDriver object triggering the - * @param[in] buffer pointer to the next semi-buffer to be filled - * @param[in] n number of buffer rows available starting from @p buffer - * callback - */ -typedef void (*daccallback_t)(DACDriver *dacp, - const dacsample_t *buffer, - size_t n); - -/** - * @brief ADC error callback type. - * - * @param[in] dacp pointer to the @p DACDriver object triggering the - * callback - * @param[in] err ADC error code - */ -typedef void (*dacerrorcallback_t)(DACDriver *dacp, dacerror_t err); - -/** - * @brief DAC Conversion group structure. - */ -typedef struct { - /** - * @brief Number of DAC channels. - */ - uint32_t num_channels; - /** - * @brief Operation complete callback or @p NULL. - */ - daccallback_t end_cb; - /** - * @brief Error handling callback or @p NULL. - */ - dacerrorcallback_t error_cb; - /* End of the mandatory fields.*/ -} DACConversionGroup; - -/** - * @brief Driver configuration structure. - */ -typedef struct { - /* End of the mandatory fields.*/ - uint32_t dummy; -} DACConfig; - -/** - * @brief Structure representing a DAC driver. - */ -struct DACDriver { - /** - * @brief Driver state. - */ - dacstate_t state; - /** - * @brief Conversion group. - */ - const DACConversionGroup *grpp; - /** - * @brief Samples buffer pointer. - */ - const dacsample_t *samples; - /** - * @brief Samples buffer size. - */ - uint16_t depth; - /** - * @brief Current configuration data. - */ - const DACConfig *config; -#if DAC_USE_WAIT || defined(__DOXYGEN__) - /** - * @brief Waiting thread. - */ - thread_reference_t thread; -#endif /* DAC_USE_WAIT */ -#if DAC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the bus. - */ - mutex_t mutex; -#endif /* DAC_USE_MUTUAL_EXCLUSION */ -#if defined(DAC_DRIVER_EXT_FIELDS) - DAC_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if PLATFORM_DAC_USE_DAC1 && !defined(__DOXYGEN__) -extern DACDriver DACD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void dac_lld_init(void); - void dac_lld_start(DACDriver *dacp); - void dac_lld_stop(DACDriver *dacp); - void dac_lld_put_channel(DACDriver *dacp, - dacchannel_t channel, - dacsample_t sample); - void dac_lld_start_conversion(DACDriver *dacp); - void dac_lld_stop_conversion(DACDriver *dacp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_DAC */ - -#endif /* _DAC_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/ext_lld.c b/firmware/ChibiOS_16/os/hal/templates/ext_lld.c deleted file mode 100644 index 1437c33746..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/ext_lld.c +++ /dev/null @@ -1,147 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file ext_lld.c - * @brief PLATFORM EXT subsystem low level driver source. - * - * @addtogroup EXT - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_EXT == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief EXT1 driver identifier. - */ -#if (PLATFORM_EXT_USE_EXT1 == TRUE) || defined(__DOXYGEN__) -EXTDriver EXTD1; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level EXT driver initialization. - * - * @notapi - */ -void ext_lld_init(void) { - -#if PLATFORM_EXT_USE_EXT1 == TRUE - /* Driver initialization.*/ - extObjectInit(&EXTD1); -#endif -} - -/** - * @brief Configures and activates the EXT peripheral. - * - * @param[in] extp pointer to the @p EXTDriver object - * - * @notapi - */ -void ext_lld_start(EXTDriver *extp) { - - if (extp->state == EXT_STOP) { - /* Enables the peripheral.*/ -#if PLATFORM_EXT_USE_EXT1 == TRUE - if (&EXTD1 == extp) { - - } -#endif - } - /* Configures the peripheral.*/ - -} - -/** - * @brief Deactivates the EXT peripheral. - * - * @param[in] extp pointer to the @p EXTDriver object - * - * @notapi - */ -void ext_lld_stop(EXTDriver *extp) { - - if (extp->state == EXT_ACTIVE) { - /* Resets the peripheral.*/ - - /* Disables the peripheral.*/ -#if PLATFORM_EXT_USE_EXT1 == TRUE - if (&EXTD1 == extp) { - - } -#endif - } -} - -/** - * @brief Enables an EXT channel. - * - * @param[in] extp pointer to the @p EXTDriver object - * @param[in] channel channel to be enabled - * - * @notapi - */ -void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) { - - (void)extp; - (void)channel; - -} - -/** - * @brief Disables an EXT channel. - * - * @param[in] extp pointer to the @p EXTDriver object - * @param[in] channel channel to be disabled - * - * @notapi - */ -void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) { - - (void)extp; - (void)channel; - -} - -#endif /* HAL_USE_EXT == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/ext_lld.h b/firmware/ChibiOS_16/os/hal/templates/ext_lld.h deleted file mode 100644 index 5813c1e803..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/ext_lld.h +++ /dev/null @@ -1,150 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file ext_lld.h - * @brief PLATFORM EXT subsystem low level driver header. - * - * @addtogroup EXT - * @{ - */ - -#ifndef _EXT_LLD_H_ -#define _EXT_LLD_H_ - -#if (HAL_USE_EXT == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Available number of EXT channels. - */ -#define EXT_MAX_CHANNELS 20 - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name PLATFORM configuration options - * @{ - */ -/** - * @brief EXT driver enable switch. - * @details If set to @p TRUE the support for EXT1 is included. - * @note The default is @p FALSE. - */ -#if !defined(PLATFORM_EXT_USE_EXT1) || defined(__DOXYGEN__) -#define PLATFORM_EXT_USE_EXT1 FALSE -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief EXT channel identifier. - */ -typedef uint32_t expchannel_t; - -/** - * @brief Type of an EXT generic notification callback. - * - * @param[in] extp pointer to the @p EXPDriver object triggering the - * callback - */ -typedef void (*extcallback_t)(EXTDriver *extp, expchannel_t channel); - -/** - * @brief Channel configuration structure. - */ -typedef struct { - /** - * @brief Channel mode. - */ - uint32_t mode; - /** - * @brief Channel callback. - * @details In the STM32 implementation a @p NULL callback pointer is - * valid and configures the channel as an event sources instead - * of an interrupt source. - */ - extcallback_t cb; -} EXTChannelConfig; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief Channel configurations. - */ - EXTChannelConfig channels[EXT_MAX_CHANNELS]; - /* End of the mandatory fields.*/ -} EXTConfig; - -/** - * @brief Structure representing an EXT driver. - */ -struct EXTDriver { - /** - * @brief Driver state. - */ - extstate_t state; - /** - * @brief Current configuration data. - */ - const EXTConfig *config; - /* End of the mandatory fields.*/ -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if (PLATFORM_EXT_USE_EXT1 == TRUE) && !defined(__DOXYGEN__) -extern EXTDriver EXTD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void ext_lld_init(void); - void ext_lld_start(EXTDriver *extp); - void ext_lld_stop(EXTDriver *extp); - void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel); - void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_EXT == TRUE */ - -#endif /* _EXT_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/gpt_lld.c b/firmware/ChibiOS_16/os/hal/templates/gpt_lld.c deleted file mode 100644 index 51e0fd159b..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/gpt_lld.c +++ /dev/null @@ -1,163 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file gpt_lld.c - * @brief PLATFORM GPT subsystem low level driver source. - * - * @addtogroup GPT - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_GPT == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief GPTD1 driver identifier. - */ -#if (PLATFORM_GPT_USE_GPT1 == TRUE) || defined(__DOXYGEN__) -GPTDriver GPTD1; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level GPT driver initialization. - * - * @notapi - */ -void gpt_lld_init(void) { - -#if PLATFORM_GPT_USE_GPT1 == TRUE - /* Driver initialization.*/ - gptObjectInit(&GPTD1); -#endif -} - -/** - * @brief Configures and activates the GPT peripheral. - * - * @param[in] gptp pointer to the @p GPTDriver object - * - * @notapi - */ -void gpt_lld_start(GPTDriver *gptp) { - - if (gptp->state == GPT_STOP) { - /* Enables the peripheral.*/ -#if PLATFORM_GPT_USE_GPT1 == TRUE - if (&GPTD1 == gptp) { - - } -#endif - } - /* Configures the peripheral.*/ - -} - -/** - * @brief Deactivates the GPT peripheral. - * - * @param[in] gptp pointer to the @p GPTDriver object - * - * @notapi - */ -void gpt_lld_stop(GPTDriver *gptp) { - - if (gptp->state == GPT_READY) { - /* Resets the peripheral.*/ - - /* Disables the peripheral.*/ -#if PLATFORM_GPT_USE_GPT1 == TRUE - if (&GPTD1 == gptp) { - - } -#endif - } -} - -/** - * @brief Starts the timer in continuous mode. - * - * @param[in] gptp pointer to the @p GPTDriver object - * @param[in] interval period in ticks - * - * @notapi - */ -void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) { - - (void)gptp; - (void)interval; - -} - -/** - * @brief Stops the timer. - * - * @param[in] gptp pointer to the @p GPTDriver object - * - * @notapi - */ -void gpt_lld_stop_timer(GPTDriver *gptp) { - - (void)gptp; - -} - -/** - * @brief Starts the timer in one shot mode and waits for completion. - * @details This function specifically polls the timer waiting for completion - * in order to not have extra delays caused by interrupt servicing, - * this function is only recommended for short delays. - * - * @param[in] gptp pointer to the @p GPTDriver object - * @param[in] interval time interval in ticks - * - * @notapi - */ -void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) { - - (void)gptp; - (void)interval; - -} - -#endif /* HAL_USE_GPT == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/gpt_lld.h b/firmware/ChibiOS_16/os/hal/templates/gpt_lld.h deleted file mode 100644 index aebefb8651..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/gpt_lld.h +++ /dev/null @@ -1,154 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file gpt_lld.h - * @brief PLATFORM GPT subsystem low level driver header. - * - * @addtogroup GPT - * @{ - */ - -#ifndef _GPT_LLD_H_ -#define _GPT_LLD_H_ - -#if (HAL_USE_GPT == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name PLATFORM configuration options - * @{ - */ -/** - * @brief GPTD1 driver enable switch. - * @details If set to @p TRUE the support for GPTD1 is included. - * @note The default is @p FALSE. - */ -#if !defined(PLATFORM_GPT_USE_GPT1) || defined(__DOXYGEN__) -#define PLATFORM_GPT_USE_GPT1 FALSE -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief GPT frequency type. - */ -typedef uint32_t gptfreq_t; - -/** - * @brief GPT counter type. - */ -typedef uint16_t gptcnt_t; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief Timer clock in Hz. - * @note The low level can use assertions in order to catch invalid - * frequency specifications. - */ - gptfreq_t frequency; - /** - * @brief Timer callback pointer. - * @note This callback is invoked on GPT counter events. - */ - gptcallback_t callback; - /* End of the mandatory fields.*/ -} GPTConfig; - -/** - * @brief Structure representing a GPT driver. - */ -struct GPTDriver { - /** - * @brief Driver state. - */ - gptstate_t state; - /** - * @brief Current configuration data. - */ - const GPTConfig *config; -#if defined(GPT_DRIVER_EXT_FIELDS) - GPT_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Changes the interval of GPT peripheral. - * @details This function changes the interval of a running GPT unit. - * @pre The GPT unit must have been activated using @p gptStart(). - * @pre The GPT unit must have been running in continuous mode using - * @p gptStartContinuous(). - * @post The GPT unit interval is changed to the new value. - * @note The function has effect at the next cycle start. - * - * @param[in] gptp pointer to a @p GPTDriver object - * @param[in] interval new cycle time in timer ticks - * @notapi - */ -#define gpt_lld_change_interval(gptp, interval) { \ - (void)gptp; \ - (void)interval; \ -} - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if (PLATFORM_GPT_USE_GPT1 == TRUE) && !defined(__DOXYGEN__) -extern GPTDriver GPTD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void gpt_lld_init(void); - void gpt_lld_start(GPTDriver *gptp); - void gpt_lld_stop(GPTDriver *gptp); - void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval); - void gpt_lld_stop_timer(GPTDriver *gptp); - void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_GPT == TRUE */ - -#endif /* _GPT_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/hal_lld.c b/firmware/ChibiOS_16/os/hal/templates/hal_lld.c deleted file mode 100644 index 0d4bd42a5e..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/hal_lld.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_lld.c - * @brief PLATFORM HAL subsystem low level driver source. - * - * @addtogroup HAL - * @{ - */ - -#include "hal.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level HAL driver initialization. - * - * @notapi - */ -void hal_lld_init(void) { - -} - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/hal_lld.h b/firmware/ChibiOS_16/os/hal/templates/hal_lld.h deleted file mode 100644 index d95b98a3a7..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/hal_lld.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_lld.h - * @brief PLATFORM HAL subsystem low level driver header. - * - * @addtogroup HAL - * @{ - */ - -#ifndef _HAL_LLD_H_ -#define _HAL_LLD_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name Platform identification macros - * @{ - */ -#define PLATFORM_NAME "templates" -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name PLATFORM configuration options - * @{ - */ -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/* - * Configuration-related checks. - */ -#if !defined(PLATFORM_MCUCONF) -#error "Using a wrong mcuconf.h file, PLATFORM_MCUCONF not defined" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void hal_lld_init(void); -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/halconf.h b/firmware/ChibiOS_16/os/hal/templates/halconf.h deleted file mode 100644 index fc97ab8cd3..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/halconf.h +++ /dev/null @@ -1,429 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @details HAL configuration file, this file allows to enable or disable the - * various device drivers from your application. You may also use - * this file in order to override the device drivers default settings. - * - * @addtogroup HAL_CONF - * @{ - */ - -#ifndef _HALCONF_H_ -#define _HALCONF_H_ - -#include "mcuconf.h" - -/** - * @name Drivers enable switches - */ -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) -#define HAL_USE_PAL TRUE -#endif - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) -#define HAL_USE_ADC TRUE -#endif - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) -#define HAL_USE_CAN TRUE -#endif - -/** - * @brief Enables the DAC subsystem. - */ -#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) -#define HAL_USE_DAC FALSE -#endif - -/** - * @brief Enables the EXT subsystem. - */ -#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) -#define HAL_USE_EXT TRUE -#endif - -/** - * @brief Enables the GPT subsystem. - */ -#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) -#define HAL_USE_GPT TRUE -#endif - -/** - * @brief Enables the I2C subsystem. - */ -#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) -#define HAL_USE_I2C TRUE -#endif - -/** - * @brief Enables the I2S subsystem. - */ -#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) -#define HAL_USE_I2S TRUE -#endif - -/** - * @brief Enables the ICU subsystem. - */ -#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) -#define HAL_USE_ICU TRUE -#endif - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) -#define HAL_USE_MAC TRUE -#endif - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define HAL_USE_MMC_SPI TRUE -#endif - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) -#define HAL_USE_PWM TRUE -#endif - -/** - * @brief Enables the RTC subsystem. - */ -#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) -#define HAL_USE_RTC TRUE -#endif - -/** - * @brief Enables the SDC subsystem. - */ -#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) -#define HAL_USE_SDC TRUE -#endif - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL TRUE -#endif - -/** - * @brief Enables the SERIAL over USB subsystem. - */ -#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL_USB TRUE -#endif - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) -#define HAL_USE_SPI TRUE -#endif - -/** - * @brief Enables the UART subsystem. - */ -#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) -#define HAL_USE_UART TRUE -#endif - -/** - * @brief Enables the USB subsystem. - */ -#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) -#define HAL_USE_USB TRUE -#endif - -/** - * @brief Enables the WDG subsystem. - */ -#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) -#define HAL_USE_WDG TRUE -#endif -/** @} */ - -/*===========================================================================*/ -/** - * @name ADC driver related setting - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) -#define ADC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define ADC_USE_MUTUAL_EXCLUSION TRUE -#endif -/** @} */ - -/*===========================================================================*/ -/** - * @name CAN driver related setting - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Sleep mode related APIs inclusion switch. - */ -#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) -#define CAN_USE_SLEEP_MODE TRUE -#endif -/** @} */ - -/*===========================================================================*/ -/** - * @name I2C driver related setting - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Enables the mutual exclusion APIs on the I2C bus. - */ -#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define I2C_USE_MUTUAL_EXCLUSION TRUE -#endif -/** @} */ - -/*===========================================================================*/ -/** - * @name MAC driver related setting - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Enables an event sources for incoming packets. - */ -#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) -#define MAC_USE_ZERO_COPY TRUE -#endif - -/** - * @brief Enables an event sources for incoming packets. - */ -#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) -#define MAC_USE_EVENTS TRUE -#endif -/** @} */ - -/*===========================================================================*/ -/** - * @name MMC_SPI driver related setting - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - * This option is recommended also if the SPI driver does not - * use a DMA channel and heavily loads the CPU. - */ -#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) -#define MMC_NICE_WAITING TRUE -#endif -/** @} */ - -/*===========================================================================*/ -/** - * @name SDC driver related setting - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Number of initialization attempts before rejecting the card. - * @note Attempts are performed at 10mS intervals. - */ -#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) -#define SDC_INIT_RETRY 100 -#endif - -/** - * @brief Include support for MMC cards. - * @note MMC support is not yet implemented so this option must be kept - * at @p FALSE. - */ -#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) -#define SDC_MMC_SUPPORT TRUE -#endif - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - */ -#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) -#define SDC_NICE_WAITING TRUE -#endif -/** @} */ - -/*===========================================================================*/ -/** - * @name SERIAL driver related setting - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Default bit rate. - * @details Configuration parameter, this is the baud rate selected for the - * default configuration. - */ -#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SERIAL_DEFAULT_BITRATE 38400 -#endif - -/** - * @brief Serial buffers size. - * @details Configuration parameter, you can change the depth of the queue - * buffers depending on the requirements of your application. - * @note The default is 16 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_BUFFERS_SIZE 16 -#endif -/** @} */ - -/*===========================================================================*/ -/** - * @name SERIAL_USB driver related setting - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Serial over USB buffers size. - * @details Configuration parameter, the buffer size must be a multiple of - * the USB data endpoint maximum packet size. - * @note The default is 256 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_SIZE 256 -#endif - -/** - * @brief Serial over USB number of buffers. - * @note The default is 2 buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_NUMBER 2 -#endif -/** @} */ - -/*===========================================================================*/ -/** - * @name SPI driver related setting - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) -#define SPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define SPI_USE_MUTUAL_EXCLUSION TRUE -#endif -/** @} */ - -/*===========================================================================*/ -/** - * @name UART driver related setting - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) -#define UART_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define UART_USE_MUTUAL_EXCLUSION TRUE -#endif -/** @} */ - -/*===========================================================================*/ -/** - * @name USB driver related setting - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) -#define USB_USE_WAIT TRUE -#endif -/** @} */ - -#endif /* _HALCONF_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/i2c_lld.c b/firmware/ChibiOS_16/os/hal/templates/i2c_lld.c deleted file mode 100644 index 4856e27f6d..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/i2c_lld.c +++ /dev/null @@ -1,187 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file i2c_lld.c - * @brief PLATFORM I2C subsystem low level driver source. - * - * @addtogroup I2C - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_I2C == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief I2C1 driver identifier. - */ -#if (PLATFORM_I2C_USE_I2C1 == TRUE) || defined(__DOXYGEN__) -I2CDriver I2CD1; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level I2C driver initialization. - * - * @notapi - */ -void i2c_lld_init(void) { - -#if PLATFORM_I2C_USE_I2C1 == TRUE - i2cObjectInit(&I2CD1); -#endif -} - -/** - * @brief Configures and activates the I2C peripheral. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -void i2c_lld_start(I2CDriver *i2cp) { - - if (i2cp->state == I2C_STOP) { - /* Enables the peripheral.*/ -#if PLATFORM_I2C_USE_I2C1 == TRUE - if (&I2CD1 == i2cp) { - - } -#endif - } - -} - -/** - * @brief Deactivates the I2C peripheral. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -void i2c_lld_stop(I2CDriver *i2cp) { - - if (i2cp->state != I2C_STOP) { - - /* Disables the peripheral.*/ -#if PLATFORM_I2C_USE_I2C1 == TRUE - if (&I2CD1 == i2cp) { - - } -#endif - } -} - -/** - * @brief Receives data via the I2C bus as master. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] addr slave device address - * @param[out] rxbuf pointer to the receive buffer - * @param[in] rxbytes number of bytes to be received - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval MSG_OK if the function succeeded. - * @retval MSG_RESET if one or more I2C errors occurred, the errors can - * be retrieved using @p i2cGetErrors(). - * @retval MSG_TIMEOUT if a timeout occurred before operation end. After a - * timeout the driver must be stopped and restarted - * because the bus is in an uncertain state. - * - * @notapi - */ -msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, - uint8_t *rxbuf, size_t rxbytes, - systime_t timeout) { - - (void)i2cp; - (void)addr; - (void)rxbuf; - (void)rxbytes; - (void)timeout; - - return MSG_OK; -} - -/** - * @brief Transmits data via the I2C bus as master. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] addr slave device address - * @param[in] txbuf pointer to the transmit buffer - * @param[in] txbytes number of bytes to be transmitted - * @param[out] rxbuf pointer to the receive buffer - * @param[in] rxbytes number of bytes to be received - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval MSG_OK if the function succeeded. - * @retval MSG_RESET if one or more I2C errors occurred, the errors can - * be retrieved using @p i2cGetErrors(). - * @retval MSG_TIMEOUT if a timeout occurred before operation end. After a - * timeout the driver must be stopped and restarted - * because the bus is in an uncertain state. - * - * @notapi - */ -msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, - const uint8_t *txbuf, size_t txbytes, - uint8_t *rxbuf, size_t rxbytes, - systime_t timeout) { - - (void)i2cp; - (void)addr; - (void)txbuf; - (void)txbytes; - (void)rxbuf; - (void)rxbytes; - (void)timeout; - - return MSG_OK; -} - -#endif /* HAL_USE_I2C == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/i2c_lld.h b/firmware/ChibiOS_16/os/hal/templates/i2c_lld.h deleted file mode 100644 index 9125c44c6b..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/i2c_lld.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file i2c_lld.h - * @brief PLATFORM I2C subsystem low level driver header. - * - * @addtogroup I2C - * @{ - */ - -#ifndef _I2C_LLD_H_ -#define _I2C_LLD_H_ - -#if (HAL_USE_I2C == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name PLATFORM configuration options - * @{ - */ -/** - * @brief I2C1 driver enable switch. - * @details If set to @p TRUE the support for I2C1 is included. - * @note The default is @p FALSE. - */ -#if !defined(PLATFORM_I2C_USE_I2C1) || defined(__DOXYGEN__) -#define PLATFORM_I2C_USE_I2C1 FALSE -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type representing an I2C address. - */ -typedef uint16_t i2caddr_t; - -/** - * @brief Type of I2C Driver condition flags. - */ -typedef uint32_t i2cflags_t; - -/** - * @brief Type of I2C driver configuration structure. - * @note Implementations may extend this structure to contain more, - * architecture dependent, fields. - */ -typedef struct { - /* End of the mandatory fields.*/ - uint32_t dummy; -} I2CConfig; - -/** - * @brief Type of a structure representing an I2C driver. - */ -typedef struct I2CDriver I2CDriver; - -/** - * @brief Structure representing an I2C driver. - */ -struct I2CDriver { - /** - * @brief Driver state. - */ - i2cstate_t state; - /** - * @brief Current configuration data. - */ - const I2CConfig *config; - /** - * @brief Error flags. - */ - i2cflags_t errors; -#if (I2C_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__) - mutex_t mutex; -#endif -#if defined(I2C_DRIVER_EXT_FIELDS) - I2C_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Get errors from I2C driver. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -#define i2c_lld_get_errors(i2cp) ((i2cp)->errors) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if (PLATFORM_I2C_USE_I2C1 == TRUE) && !defined(__DOXYGEN__) -extern I2CDriver I2CD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void i2c_lld_init(void); - void i2c_lld_start(I2CDriver *i2cp); - void i2c_lld_stop(I2CDriver *i2cp); - msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, - const uint8_t *txbuf, size_t txbytes, - uint8_t *rxbuf, size_t rxbytes, - systime_t timeout); - msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, - uint8_t *rxbuf, size_t rxbytes, - systime_t timeout); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_I2C == TRUE */ - -#endif /* _I2C_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/i2s_lld.c b/firmware/ChibiOS_16/os/hal/templates/i2s_lld.c deleted file mode 100644 index d88a7453b1..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/i2s_lld.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file i2s_lld.c - * @brief PLATFORM I2S subsystem low level driver source. - * - * @addtogroup I2S - * @{ - */ - -#include "hal.h" - -#if HAL_USE_I2S || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief I2S2 driver identifier.*/ -#if PLATFORM_I2S_USE_I2S1 || defined(__DOXYGEN__) -I2SDriver I2SD1; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level I2S driver initialization. - * - * @notapi - */ -void i2s_lld_init(void) { - -#if PLATFORM_I2S_USE_I2S1 - i2sObjectInit(&I2SD1); -#endif -} - -/** - * @brief Configures and activates the I2S peripheral. - * - * @param[in] i2sp pointer to the @p I2SDriver object - * - * @notapi - */ -void i2s_lld_start(I2SDriver *i2sp) { - - /* If in stopped state then enables the SPI and DMA clocks.*/ - if (i2sp->state == I2S_STOP) { - -#if PLATFORM_I2S_USE_I2S1 - if (&I2SD1 == i2sp) { - - } -#endif -} - -/** - * @brief Deactivates the I2S peripheral. - * - * @param[in] i2sp pointer to the @p I2SDriver object - * - * @notapi - */ -void i2s_lld_stop(I2SDriver *i2sp) { - - /* If in ready state then disables the SPI clock.*/ - if (i2sp->state == I2S_READY) { -#if PLATFORM_I2S_USE_I2S1 - if (&I2SD1 == i2sp) { - - } -#endif - } -} - -/** - * @brief Starts a I2S data exchange. - * - * @param[in] i2sp pointer to the @p I2SDriver object - * - * @notapi - */ -void i2s_lld_start_exchange(I2SDriver *i2sp) { - - (void)i2sp; -} - -/** - * @brief Stops the ongoing data exchange. - * @details The ongoing data exchange, if any, is stopped, if the driver - * was not active the function does nothing. - * - * @param[in] i2sp pointer to the @p I2SDriver object - * - * @notapi - */ -void i2s_lld_stop_exchange(I2SDriver *i2sp) { - - (void)i2sp; -} - -#endif /* HAL_USE_I2S */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/i2s_lld.h b/firmware/ChibiOS_16/os/hal/templates/i2s_lld.h deleted file mode 100644 index 7e8fcfd4cf..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/i2s_lld.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file i2s_lld.h - * @brief PLATFORM I2S subsystem low level driver header. - * - * @addtogroup I2S - * @{ - */ - -#ifndef _I2S_LLD_H_ -#define _I2S_LLD_H_ - -#if (HAL_USE_I2S == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name PLATFORM configuration options - * @{ - */ -/** - * @brief I2SD1 driver enable switch. - * @details If set to @p TRUE the support for I2S1 is included. - * @note The default is @p FALSE. - */ -#if !defined(PLATFORM_I2S_USE_I2S1) || defined(__DOXYGEN__) -#define PLATFORM_I2S_USE_I2S1 FALSE -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a structure representing an I2S driver. - */ -typedef struct I2SDriver I2SDriver; - -/** - * @brief I2S notification callback type. - * - * @param[in] i2sp pointer to the @p I2SDriver object - * @param[in] offset offset in buffers of the data to read/write - * @param[in] n number of samples to read/write - */ -typedef void (*i2scallback_t)(I2SDriver *i2sp, size_t offset, size_t n); - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief Transmission buffer pointer. - * @note Can be @p NULL if TX is not required. - */ - const void *tx_buffer; - /** - * @brief Receive buffer pointer. - * @note Can be @p NULL if RX is not required. - */ - void *rx_buffer; - /** - * @brief TX and RX buffers size as number of samples. - */ - size_t size; - /** - * @brief Callback function called during streaming. - */ - i2scallback_t end_cb; - /* End of the mandatory fields.*/ -} I2SConfig; - -/** - * @brief Structure representing an I2S driver. - */ -struct I2SDriver { - /** - * @brief Driver state. - */ - i2sstate_t state; - /** - * @brief Current configuration data. - */ - const I2SConfig *config; - /* End of the mandatory fields.*/ -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if (PLATFORM_I2S_USE_I2S1 == TRUE) && !defined(__DOXYGEN__) -extern I2SDriver I2SD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void i2s_lld_init(void); - void i2s_lld_start(I2SDriver *i2sp); - void i2s_lld_stop(I2SDriver *i2sp); - void i2s_lld_start_exchange(I2SDriver *i2sp); - void i2s_lld_stop_exchange(I2SDriver *i2sp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_I2S == TRUE */ - -#endif /* _I2S_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/icu_lld.c b/firmware/ChibiOS_16/os/hal/templates/icu_lld.c deleted file mode 100644 index 95990a389f..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/icu_lld.c +++ /dev/null @@ -1,185 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file icu_lld.c - * @brief PLATFORM ADC subsystem low level driver source. - * - * @addtogroup ICU - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_ICU == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief ICUD1 driver identifier. - * @note The driver ICUD1 allocates the complex timer TIM1 when enabled. - */ -#if (PLATFORM_ICU_USE_ICU1 == TRUE) || defined(__DOXYGEN__) -ICUDriver ICUD1; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level ICU driver initialization. - * - * @notapi - */ -void icu_lld_init(void) { - -#if PLATFORM_ICU_USE_ICU1 == TRUE - /* Driver initialization.*/ - icuObjectInit(&ICUD1); -#endif -} - -/** - * @brief Configures and activates the ICU peripheral. - * - * @param[in] icup pointer to the @p ICUDriver object - * - * @notapi - */ -void icu_lld_start(ICUDriver *icup) { - - if (icup->state == ICU_STOP) { - /* Clock activation and timer reset.*/ -#if PLATFORM_ICU_USE_ICU1 == TRUE - if (&ICUD1 == icup) { - - } -#endif - } -} - -/** - * @brief Deactivates the ICU peripheral. - * - * @param[in] icup pointer to the @p ICUDriver object - * - * @notapi - */ -void icu_lld_stop(ICUDriver *icup) { - - if (icup->state == ICU_READY) { - /* Clock deactivation.*/ -#if PLATFORM_ICU_USE_ICU1 == TRUE - if (&ICUD1 == icup) { - - } -#endif - } -} - -/** - * @brief Starts the input capture. - * - * @param[in] icup pointer to the @p ICUDriver object - * - * @notapi - */ -void icu_lld_start_capture(ICUDriver *icup) { - - (void)icup; -} - -/** - * @brief Waits for a completed capture. - * @note The operation is performed in polled mode. - * @note In order to use this function notifications must be disabled. - * - * @param[in] icup pointer to the @p ICUDriver object - * @return The capture status. - * @retval false if the capture is successful. - * @retval true if a timer overflow occurred. - * - * @notapi - */ -bool icu_lld_wait_capture(ICUDriver *icup) { - - (void)icup; - - return false; -} - -/** - * @brief Stops the input capture. - * - * @param[in] icup pointer to the @p ICUDriver object - * - * @notapi - */ -void icu_lld_stop_capture(ICUDriver *icup) { - - (void)icup; -} - -/** - * @brief Enables notifications. - * @pre The ICU unit must have been activated using @p icuStart(). - * @note If the notification is already enabled then the call has no effect. - * - * @param[in] icup pointer to the @p ICUDriver object - * - * @api - */ -void icu_lld_enable_notifications(ICUDriver *icup) { - - (void)icup; -} - -/** - * @brief Disables notifications. - * @pre The ICU unit must have been activated using @p icuStart(). - * @note If the notification is already disabled then the call has no effect. - * - * @param[in] icup pointer to the @p ICUDriver object - * - * @api - */ -void icu_lld_disable_notifications(ICUDriver *icup) { - - (void)icup; -} - -#endif /* HAL_USE_ICU == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/icu_lld.h b/firmware/ChibiOS_16/os/hal/templates/icu_lld.h deleted file mode 100644 index 344b55e021..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/icu_lld.h +++ /dev/null @@ -1,193 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file icu_lld.h - * @brief PLATFORM ICU subsystem low level driver header. - * - * @addtogroup ICU - * @{ - */ - -#ifndef _ICU_LLD_H_ -#define _ICU_LLD_H_ - -#if (HAL_USE_ICU == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name PLATFORM configuration options - * @{ - */ -/** - * @brief ICUD1 driver enable switch. - * @details If set to @p TRUE the support for ICUD1 is included. - * @note The default is @p FALSE. - */ -#if !defined(PLATFORM_ICU_USE_ICU1) || defined(__DOXYGEN__) -#define PLATFORM_ICU_USE_ICU1 FALSE -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief ICU driver mode. - */ -typedef enum { - ICU_INPUT_ACTIVE_HIGH = 0, /**< Trigger on rising edge. */ - ICU_INPUT_ACTIVE_LOW = 1 /**< Trigger on falling edge. */ -} icumode_t; - -/** - * @brief ICU frequency type. - */ -typedef uint32_t icufreq_t; - -/** - * @brief ICU counter type. - */ -typedef uint32_t icucnt_t; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief Driver mode. - */ - icumode_t mode; - /** - * @brief Timer clock in Hz. - * @note The low level can use assertions in order to catch invalid - * frequency specifications. - */ - icufreq_t frequency; - /** - * @brief Callback for pulse width measurement. - */ - icucallback_t width_cb; - /** - * @brief Callback for cycle period measurement. - */ - icucallback_t period_cb; - /** - * @brief Callback for timer overflow. - */ - icucallback_t overflow_cb; - /* End of the mandatory fields.*/ -} ICUConfig; - -/** - * @brief Structure representing an ICU driver. - */ -struct ICUDriver { - /** - * @brief Driver state. - */ - icustate_t state; - /** - * @brief Current configuration data. - */ - const ICUConfig *config; -#if defined(ICU_DRIVER_EXT_FIELDS) - ICU_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Returns the width of the latest pulse. - * @details The pulse width is defined as number of ticks between the start - * edge and the stop edge. - * - * @param[in] icup pointer to the @p ICUDriver object - * @return The number of ticks. - * - * @notapi - */ -#define icu_lld_get_width(icup) 0 - -/** - * @brief Returns the width of the latest cycle. - * @details The cycle width is defined as number of ticks between a start - * edge and the next start edge. - * - * @param[in] icup pointer to the @p ICUDriver object - * @return The number of ticks. - * - * @notapi - */ -#define icu_lld_get_period(icup) 0 - -/** - * @brief Check on notifications status. - * - * @param[in] icup pointer to the @p ICUDriver object - * @return The notifications status. - * @retval false if notifications are not enabled. - * @retval true if notifications are enabled. - * - * @notapi - */ -#define icu_lld_are_notifications_enabled(icup) false - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if (PLATFORM_ICU_USE_ICU1 == TRUE) && !defined(__DOXYGEN__) -extern ICUDriver ICUD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void icu_lld_init(void); - void icu_lld_start(ICUDriver *icup); - void icu_lld_stop(ICUDriver *icup); - void icu_lld_start_capture(ICUDriver *icup); - bool icu_lld_wait_capture(ICUDriver *icup); - void icu_lld_stop_capture(ICUDriver *icup); - void icu_lld_enable_notifications(ICUDriver *icup); - void icu_lld_disable_notifications(ICUDriver *icup); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_ICU == TRUE */ - -#endif /* _ICU_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/mac_lld.c b/firmware/ChibiOS_16/os/hal/templates/mac_lld.c deleted file mode 100644 index da04da42f6..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/mac_lld.c +++ /dev/null @@ -1,313 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file mac_lld.c - * @brief PLATFORM MAC subsystem low level driver source. - * - * @addtogroup MAC - * @{ - */ - -#include - -#include "hal.h" - -#if (HAL_USE_MAC == TRUE) || defined(__DOXYGEN__) - -#include "mii.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief MAC1 driver identifier. - */ -#if (PLATFORM_MAC_USE_MAC1 == TRUE) || defined(__DOXYGEN__) -MACDriver ETHD1; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level MAC initialization. - * - * @notapi - */ -void mac_lld_init(void) { - -#if PLATFORM_MAC_USE_MAC1 == TRUE - /* Driver initialization.*/ - macObjectInit(&MACD1); -#endif -} - -/** - * @brief Configures and activates the MAC peripheral. - * - * @param[in] macp pointer to the @p MACDriver object - * - * @notapi - */ -void mac_lld_start(MACDriver *macp) { - - if (macp->state == MAC_STOP) { - /* Enables the peripheral.*/ -#if PLATFORM_MAC_USE_MAC1 == TRUE - if (&MACD1 == macp) { - - } -#endif - } - /* Configures the peripheral.*/ - -} - -/** - * @brief Deactivates the MAC peripheral. - * - * @param[in] macp pointer to the @p MACDriver object - * - * @notapi - */ -void mac_lld_stop(MACDriver *macp) { - - if (macp->state != MAC_STOP) { - /* Resets the peripheral.*/ - - /* Disables the peripheral.*/ -#if PLATFORM_MAC_USE_MAC1 == TRUE - if (&MACD1 == macp) { - - } -#endif - } -} - -/** - * @brief Returns a transmission descriptor. - * @details One of the available transmission descriptors is locked and - * returned. - * - * @param[in] macp pointer to the @p MACDriver object - * @param[out] tdp pointer to a @p MACTransmitDescriptor structure - * @return The operation status. - * @retval MSG_OK the descriptor has been obtained. - * @retval MSG_TIMEOUT descriptor not available. - * - * @notapi - */ -msg_t mac_lld_get_transmit_descriptor(MACDriver *macp, - MACTransmitDescriptor *tdp) { - - (void)macp; - (void)tdp; - - return MSG_OK; -} - -/** - * @brief Releases a transmit descriptor and starts the transmission of the - * enqueued data as a single frame. - * - * @param[in] tdp the pointer to the @p MACTransmitDescriptor structure - * - * @notapi - */ -void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) { - - (void)tdp; - -} - -/** - * @brief Returns a receive descriptor. - * - * @param[in] macp pointer to the @p MACDriver object - * @param[out] rdp pointer to a @p MACReceiveDescriptor structure - * @return The operation status. - * @retval MSG_OK the descriptor has been obtained. - * @retval MSG_TIMEOUT descriptor not available. - * - * @notapi - */ -msg_t mac_lld_get_receive_descriptor(MACDriver *macp, - MACReceiveDescriptor *rdp) { - - (void)macp; - (void)rdp; - - return MSG_OK; -} - -/** - * @brief Releases a receive descriptor. - * @details The descriptor and its buffer are made available for more incoming - * frames. - * - * @param[in] rdp the pointer to the @p MACReceiveDescriptor structure - * - * @notapi - */ -void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp) { - - (void)rdp; - -} - -/** - * @brief Updates and returns the link status. - * - * @param[in] macp pointer to the @p MACDriver object - * @return The link status. - * @retval true if the link is active. - * @retval false if the link is down. - * - * @notapi - */ -bool mac_lld_poll_link_status(MACDriver *macp) { - - (void)macp; - - return false; -} - -/** - * @brief Writes to a transmit descriptor's stream. - * - * @param[in] tdp pointer to a @p MACTransmitDescriptor structure - * @param[in] buf pointer to the buffer containing the data to be - * written - * @param[in] size number of bytes to be written - * @return The number of bytes written into the descriptor's - * stream, this value can be less than the amount - * specified in the parameter @p size if the maximum - * frame size is reached. - * - * @notapi - */ -size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp, - uint8_t *buf, - size_t size) { - - (void)tdp; - (void)buf; - - return size; -} - -/** - * @brief Reads from a receive descriptor's stream. - * - * @param[in] rdp pointer to a @p MACReceiveDescriptor structure - * @param[in] buf pointer to the buffer that will receive the read data - * @param[in] size number of bytes to be read - * @return The number of bytes read from the descriptor's - * stream, this value can be less than the amount - * specified in the parameter @p size if there are - * no more bytes to read. - * - * @notapi - */ -size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp, - uint8_t *buf, - size_t size) { - - (void)rdp; - (void)buf; - - return size; -} - -#if (MAC_USE_ZERO_COPY == TRUE) || defined(__DOXYGEN__) -/** - * @brief Returns a pointer to the next transmit buffer in the descriptor - * chain. - * @note The API guarantees that enough buffers can be requested to fill - * a whole frame. - * - * @param[in] tdp pointer to a @p MACTransmitDescriptor structure - * @param[in] size size of the requested buffer. Specify the frame size - * on the first call then scale the value down subtracting - * the amount of data already copied into the previous - * buffers. - * @param[out] sizep pointer to variable receiving the buffer size, it is - * zero when the last buffer has already been returned. - * Note that a returned size lower than the amount - * requested means that more buffers must be requested - * in order to fill the frame data entirely. - * @return Pointer to the returned buffer. - * @retval NULL if the buffer chain has been entirely scanned. - * - * @notapi - */ -uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp, - size_t size, - size_t *sizep) { - - (void)tdp; - (void)size; - (void)sizep; - - return NULL; -} - -/** - * @brief Returns a pointer to the next receive buffer in the descriptor - * chain. - * @note The API guarantees that the descriptor chain contains a whole - * frame. - * - * @param[in] rdp pointer to a @p MACReceiveDescriptor structure - * @param[out] sizep pointer to variable receiving the buffer size, it is - * zero when the last buffer has already been returned. - * @return Pointer to the returned buffer. - * @retval NULL if the buffer chain has been entirely scanned. - * - * @notapi - */ -const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp, - size_t *sizep) { - - (void)rdp; - (void)sizep; - - return NULL; -} -#endif /* MAC_USE_ZERO_COPY == TRUE */ - -#endif /* HAL_USE_MAC == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/mac_lld.h b/firmware/ChibiOS_16/os/hal/templates/mac_lld.h deleted file mode 100644 index 90e38dc0a3..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/mac_lld.h +++ /dev/null @@ -1,181 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file mac_lld.h - * @brief PLATFORM MAC subsystem low level driver header. - * - * @addtogroup MAC - * @{ - */ - -#ifndef _MAC_LLD_H_ -#define _MAC_LLD_H_ - -#if (HAL_USE_MAC == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief This implementation supports the zero-copy mode API. - */ -#define MAC_SUPPORTS_ZERO_COPY TRUE - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name PLATFORM configuration options - * @{ - */ -/** - * @brief MAC driver enable switch. - * @details If set to @p TRUE the support for MAC1 is included. - * @note The default is @p FALSE. - */ -#if !defined(PLATFORM_MAC_USE_MAC1) || defined(__DOXYGEN__) -#define PLATFORM_MAC_USE_MAC1 FALSE -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver configuration structure. - */ -typedef struct { - /** - * @brief MAC address. - */ - uint8_t *mac_address; - /* End of the mandatory fields.*/ -} MACConfig; - -/** - * @brief Structure representing a MAC driver. - */ -struct MACDriver { - /** - * @brief Driver state. - */ - macstate_t state; - /** - * @brief Current configuration data. - */ - const MACConfig *config; - /** - * @brief Transmit semaphore. - */ - threads_queue_t tdqueue; - /** - * @brief Receive semaphore. - */ - threads_queue_t rdqueue; -#if (MAC_USE_EVENTS == TRUE) || defined(__DOXYGEN__) - /** - * @brief Receive event. - */ - event_source_t rdevent; -#endif - /* End of the mandatory fields.*/ -}; - -/** - * @brief Structure representing a transmit descriptor. - */ -typedef struct { - /** - * @brief Current write offset. - */ - size_t offset; - /** - * @brief Available space size. - */ - size_t size; - /* End of the mandatory fields.*/ -} MACTransmitDescriptor; - -/** - * @brief Structure representing a receive descriptor. - */ -typedef struct { - /** - * @brief Current read offset. - */ - size_t offset; - /** - * @brief Available data size. - */ - size_t size; - /* End of the mandatory fields.*/ -} MACReceiveDescriptor; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if (PLATFORM_MAC_USE_MAC1 == TRUE) && !defined(__DOXYGEN__) -extern MACDriver ETHD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void mac_lld_init(void); - void mac_lld_start(MACDriver *macp); - void mac_lld_stop(MACDriver *macp); - msg_t mac_lld_get_transmit_descriptor(MACDriver *macp, - MACTransmitDescriptor *tdp); - void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp); - msg_t mac_lld_get_receive_descriptor(MACDriver *macp, - MACReceiveDescriptor *rdp); - void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp); - bool mac_lld_poll_link_status(MACDriver *macp); - size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp, - uint8_t *buf, - size_t size); - size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp, - uint8_t *buf, - size_t size); -#if MAC_USE_ZERO_COPY == TRUE - uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp, - size_t size, - size_t *sizep); - const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp, - size_t *sizep); -#endif -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_MAC == TRUE */ - -#endif /* _MAC_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/mcuconf.h b/firmware/ChibiOS_16/os/hal/templates/mcuconf.h deleted file mode 100644 index e59cbdc435..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/mcuconf.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef _MCUCONF_H_ -#define _MCUCONF_H_ - -/* - * Platform drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the whole - * driver is enabled in halconf.h. - */ - -#define PLATFORM_MCUCONF - -#endif /* _MCUCONF_H_ */ diff --git a/firmware/ChibiOS_16/os/hal/templates/osal/osal.c b/firmware/ChibiOS_16/os/hal/templates/osal/osal.c deleted file mode 100644 index a00203096c..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/osal/osal.c +++ /dev/null @@ -1,411 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file osal.c - * @brief OSAL module code. - * - * @addtogroup OSAL - * @{ - */ - -#include "osal.h" - -/*===========================================================================*/ -/* Module local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -/** - * @brief Pointer to a halt error message. - * @note The message is meant to be retrieved by the debugger after the - * system halt caused by an unexpected error. - */ -const char *osal_halt_msg; - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -/** - * @brief OSAL module initialization. - * - * @api - */ -void osalInit(void) { - -} - -/** - * @brief System halt with error message. - * - * @param[in] reason the halt message pointer - * - * @api - */ -#if !defined(__DOXYGEN__) -__attribute__((weak, noreturn)) -#endif -void osalSysHalt(const char *reason) { - - osalSysDisable(); - osal_halt_msg = reason; - while (true) { - } -} - -/** - * @brief Polled delay. - * @note The real delay is always few cycles in excess of the specified - * value. - * - * @param[in] cycles number of cycles - * - * @xclass - */ -void osalSysPolledDelayX(rtcnt_t cycles) { - - (void)cycles; -} - -/** - * @brief System timer handler. - * @details The handler is used for scheduling and Virtual Timers management. - * - * @iclass - */ -void osalOsTimerHandlerI(void) { - - osalDbgCheckClassI(); -} - -/** - * @brief Checks if a reschedule is required and performs it. - * @note I-Class functions invoked from thread context must not reschedule - * by themselves, an explicit reschedule using this function is - * required in this scenario. - * @note Not implemented in this simplified OSAL. - * - * @sclass - */ -void osalOsRescheduleS(void) { - -} - -/** - * @brief Current system time. - * @details Returns the number of system ticks since the @p osalInit() - * invocation. - * @note The counter can reach its maximum and then restart from zero. - * @note This function can be called from any context but its atomicity - * is not guaranteed on architectures whose word size is less than - * @p systime_t size. - * - * @return The system time in ticks. - * - * @xclass - */ -systime_t osalOsGetSystemTimeX(void) { - - return (systime_t)0; -} - -/** - * @brief Suspends the invoking thread for the specified time. - * - * @param[in] time the delay in system ticks, the special values are - * handled as follow: - * - @a TIME_INFINITE is allowed but interpreted as a - * normal time specification. - * - @a TIME_IMMEDIATE this value is not allowed. - * . - * - * @sclass - */ -void osalThreadSleepS(systime_t time) { - - (void)time; -} - -/** - * @brief Suspends the invoking thread for the specified time. - * - * @param[in] time the delay in system ticks, the special values are - * handled as follow: - * - @a TIME_INFINITE is allowed but interpreted as a - * normal time specification. - * - @a TIME_IMMEDIATE this value is not allowed. - * . - * - * @api - */ -void osalThreadSleep(systime_t time) { - - (void)time; -} - -/** - * @brief Sends the current thread sleeping and sets a reference variable. - * @note This function must reschedule, it can only be called from thread - * context. - * - * @param[in] trp a pointer to a thread reference object - * @return The wake up message. - * - * @sclass - */ -msg_t osalThreadSuspendS(thread_reference_t *trp) { - - osalDbgCheck(trp != NULL); - - return MSG_OK; -} - -/** - * @brief Sends the current thread sleeping and sets a reference variable. - * @note This function must reschedule, it can only be called from thread - * context. - * - * @param[in] trp a pointer to a thread reference object - * @param[in] timeout the timeout in system ticks, the special values are - * handled as follow: - * - @a TIME_INFINITE the thread enters an infinite sleep - * state. - * - @a TIME_IMMEDIATE the thread is not enqueued and - * the function returns @p MSG_TIMEOUT as if a timeout - * occurred. - * . - * @return The wake up message. - * @retval MSG_TIMEOUT if the operation timed out. - * - * @sclass - */ -msg_t osalThreadSuspendTimeoutS(thread_reference_t *trp, systime_t timeout) { - - osalDbgCheck(trp != NULL); - - (void)timeout; - - return MSG_OK; -} - -/** - * @brief Wakes up a thread waiting on a thread reference object. - * @note This function must not reschedule because it can be called from - * ISR context. - * - * @param[in] trp a pointer to a thread reference object - * @param[in] msg the message code - * - * @iclass - */ -void osalThreadResumeI(thread_reference_t *trp, msg_t msg) { - - osalDbgCheck(trp != NULL); - - (void)msg; -} - -/** - * @brief Wakes up a thread waiting on a thread reference object. - * @note This function must reschedule, it can only be called from thread - * context. - * - * @param[in] trp a pointer to a thread reference object - * @param[in] msg the message code - * - * @iclass - */ -void osalThreadResumeS(thread_reference_t *trp, msg_t msg) { - - osalDbgCheck(trp != NULL); - - (void)msg; -} - -/** - * @brief Enqueues the caller thread. - * @details The caller thread is enqueued and put to sleep until it is - * dequeued or the specified timeouts expires. - * - * @param[in] tqp pointer to the threads queue object - * @param[in] timeout the timeout in system ticks, the special values are - * handled as follow: - * - @a TIME_INFINITE the thread enters an infinite sleep - * state. - * - @a TIME_IMMEDIATE the thread is not enqueued and - * the function returns @p MSG_TIMEOUT as if a timeout - * occurred. - * . - * @return The message from @p osalQueueWakeupOneI() or - * @p osalQueueWakeupAllI() functions. - * @retval MSG_TIMEOUT if the thread has not been dequeued within the - * specified timeout or if the function has been - * invoked with @p TIME_IMMEDIATE as timeout - * specification. - * - * @sclass - */ -msg_t osalThreadEnqueueTimeoutS(threads_queue_t *tqp, systime_t timeout) { - - osalDbgCheck(tqp != NULL); - - (void)timeout; - - return MSG_OK; -} - -/** - * @brief Dequeues and wakes up one thread from the queue, if any. - * - * @param[in] tqp pointer to the threads queue object - * @param[in] msg the message code - * - * @iclass - */ -void osalThreadDequeueNextI(threads_queue_t *tqp, msg_t msg) { - - osalDbgCheck(tqp != NULL); - - (void)msg; -} - -/** - * @brief Dequeues and wakes up all threads from the queue. - * - * @param[in] tqp pointer to the threads queue object - * @param[in] msg the message code - * - * @iclass - */ -void osalThreadDequeueAllI(threads_queue_t *tqp, msg_t msg) { - - (void)tqp; - (void)msg; -} - -/** - * @brief Add flags to an event source object. - * - * @param[in] esp pointer to the event flags object - * @param[in] flags flags to be ORed to the flags mask - * - * @iclass - */ -void osalEventBroadcastFlagsI(event_source_t *esp, eventflags_t flags) { - - osalDbgCheck(esp != NULL); - - esp->flags |= flags; - if (esp->cb != NULL) { - esp->cb(esp); - } -} - -/** - * @brief Add flags to an event source object. - * - * @param[in] esp pointer to the event flags object - * @param[in] flags flags to be ORed to the flags mask - * - * @iclass - */ -void osalEventBroadcastFlags(event_source_t *esp, eventflags_t flags) { - - osalDbgCheck(esp != NULL); - - osalSysLock(); - osalEventBroadcastFlagsI(esp, flags); - osalSysUnlock(); -} - -/** - * @brief Event callback setup. - * @note The callback is invoked from ISR context and can - * only invoke I-Class functions. The callback is meant - * to wakeup the task that will handle the event by - * calling @p osalEventGetAndClearFlagsI(). - * @note This function is not part of the OSAL API and is provided - * exclusively as an example and for convenience. - * - * @param[in] esp pointer to the event flags object - * @param[in] cb pointer to the callback function - * @param[in] param parameter to be passed to the callback function - * - * @api - */ -void osalEventSetCallback(event_source_t *esp, - eventcallback_t cb, - void *param) { - - osalDbgCheck(esp != NULL); - - esp->cb = cb; - esp->param = param; -} - -/** - * @brief Locks the specified mutex. - * @post The mutex is locked and inserted in the per-thread stack of owned - * mutexes. - * - * @param[in,out] mp pointer to the @p mutex_t object - * - * @api - */ -void osalMutexLock(mutex_t *mp) { - - osalDbgCheck(mp != NULL); - - *mp = 1; -} - -/** - * @brief Unlocks the specified mutex. - * @note The HAL guarantees to release mutex in reverse lock order. The - * mutex being unlocked is guaranteed to be the last locked mutex - * by the invoking thread. - * The implementation can rely on this behavior and eventually - * ignore the @p mp parameter which is supplied in order to support - * those OSes not supporting a stack of the owned mutexes. - * - * @param[in,out] mp pointer to the @p mutex_t object - * - * @api - */ -void osalMutexUnlock(mutex_t *mp) { - - osalDbgCheck(mp != NULL); - - *mp = 0; -} - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/osal/osal.h b/firmware/ChibiOS_16/os/hal/templates/osal/osal.h deleted file mode 100644 index ed3e98f1b8..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/osal/osal.h +++ /dev/null @@ -1,648 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file osal.h - * @brief OSAL module header. - * - * @addtogroup OSAL - * @{ - */ - -#ifndef _OSAL_H_ -#define _OSAL_H_ - -#include -#include -#include - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @name Common constants - * @{ - */ -#if !defined(FALSE) || defined(__DOXYGEN__) -#define FALSE 0 -#endif - -#if !defined(TRUE) || defined(__DOXYGEN__) -#define TRUE 1 -#endif - -#define OSAL_SUCCESS false -#define OSAL_FAILED true -/** @} */ - -/** - * @name Messages - * @{ - */ -#define MSG_OK (msg_t)0 -#define MSG_RESET (msg_t)-1 -#define MSG_TIMEOUT (msg_t)-2 -/** @} */ - - -/** - * @name Special time constants - * @{ - */ -#define TIME_IMMEDIATE ((systime_t)0) -#define TIME_INFINITE ((systime_t)-1) -/** @} */ - -/** - * @name Systick modes. - * @{ - */ -#define OSAL_ST_MODE_NONE 0 -#define OSAL_ST_MODE_PERIODIC 1 -#define OSAL_ST_MODE_FREERUNNING 2 -/** @} */ - -/** - * @name Systick parameters. - * @{ - */ -/** - * @brief Size in bits of the @p systick_t type. - */ -#define OSAL_ST_RESOLUTION 32 - -/** - * @brief Required systick frequency or resolution. - */ -#define OSAL_ST_FREQUENCY 1000 - -/** - * @brief Systick mode required by the underlying OS. - */ -#define OSAL_ST_MODE OSAL_ST_MODE_PERIODIC -/** @} */ - -/** - * @name IRQ-related constants - * @{ - */ -/** - * @brief Total priority levels. - * @brief Implementation not mandatory. - */ -#define OSAL_IRQ_PRIORITY_LEVELS 16U - -/** - * @brief Highest IRQ priority for HAL drivers. - * @brief Implementation not mandatory. - */ -#define OSAL_IRQ_MAXIMUM_PRIORITY 0U -/** @} */ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Enables OSAL assertions. - */ -#if !defined(OSAL_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define OSAL_DBG_ENABLE_ASSERTS FALSE -#endif - -/** - * @brief Enables OSAL functions parameters checks. - */ -#if !defined(OSAL_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define OSAL_DBG_ENABLE_CHECKS FALSE -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a system status word. - */ -typedef uint32_t syssts_t; - -/** - * @brief Type of a message. - */ -typedef int32_t msg_t; - -/** - * @brief Type of system time counter. - */ -typedef uint32_t systime_t; - -/** - * @brief Type of realtime counter. - */ -typedef uint32_t rtcnt_t; - -/** - * @brief Type of a thread reference. - */ -typedef void * thread_reference_t; - -/** - * @brief Type of an event flags object. - * @note The content of this structure is not part of the API and should - * not be relied upon. Implementers may define this structure in - * an entirely different way. - * @note Retrieval and clearing of the flags are not defined in this - * API and are implementation-dependent. - */ -typedef struct event_source event_source_t; - -/** - * @brief Type of an event source callback. - * @note This type is not part of the OSAL API and is provided - * exclusively as an example and for convenience. - */ -typedef void (*eventcallback_t)(event_source_t *esp); - -/** - * @brief Type of an event flags mask. - */ -typedef uint32_t eventflags_t; - -/** - * @brief Events source object. - * @note The content of this structure is not part of the API and should - * not be relied upon. Implementers may define this structure in - * an entirely different way. - * @note Retrieval and clearing of the flags are not defined in this - * API and are implementation-dependent. - */ -struct event_source { - volatile eventflags_t flags; /**< @brief Stored event flags. */ - eventcallback_t cb; /**< @brief Event source callback. */ - void *param; /**< @brief User defined field. */ -}; - -/** - * @brief Type of a mutex. - * @note If the OS does not support mutexes or there is no OS then them - * mechanism can be simulated. - */ -typedef uint32_t mutex_t; - -/** - * @brief Type of a thread queue. - * @details A thread queue is a queue of sleeping threads, queued threads - * can be dequeued one at time or all together. - * @note If the OSAL is implemented on a bare metal machine without RTOS - * then the queue can be implemented as a single thread reference. - */ -typedef struct { - thread_reference_t tr; -} threads_queue_t; - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @name Debug related macros - * @{ - */ -/** - * @brief Condition assertion. - * @details If the condition check fails then the OSAL panics with a - * message and halts. - * @note The condition is tested only if the @p OSAL_ENABLE_ASSERTIONS - * switch is enabled. - * @note The remark string is not currently used except for putting a - * comment in the code about the assertion. - * - * @param[in] c the condition to be verified to be true - * @param[in] remark a remark string - * - * @api - */ -#define osalDbgAssert(c, remark) do { \ - /*lint -save -e506 -e774 [2.1, 14.3] Can be a constant by design.*/ \ - if (OSAL_DBG_ENABLE_ASSERTS != FALSE) { \ - if (!(c)) { \ - /*lint -restore*/ \ - osalSysHalt(__func__); \ - } \ - } \ -} while (false) - - -/** - * @brief Function parameters check. - * @details If the condition check fails then the OSAL panics and halts. - * @note The condition is tested only if the @p OSAL_ENABLE_CHECKS switch - * is enabled. - * - * @param[in] c the condition to be verified to be true - * - * @api - */ -#define osalDbgCheck(c) do { \ - /*lint -save -e506 -e774 [2.1, 14.3] Can be a constant by design.*/ \ - if (OSAL_DBG_ENABLE_CHECKS != FALSE) { \ - if (!(c)) { \ - /*lint -restore*/ \ - osalSysHalt(__func__); \ - } \ - } \ -} while (false) - - -/** - * @brief I-Class state check. - * @note Implementation is optional. - */ -#define osalDbgCheckClassI() - -/** - * @brief S-Class state check. - * @note Implementation is optional. - */ -#define osalDbgCheckClassS() -/** @} */ - -/** - * @name IRQ service routines wrappers - * @{ - */ -/** - * @brief Priority level verification macro. - */ -#define OSAL_IRQ_IS_VALID_PRIORITY(n) \ - (((n) >= OSAL_IRQ_MAXIMUM_PRIORITY) && ((n) < OSAL_IRQ_PRIORITY_LEVELS)) - -/** - * @brief IRQ prologue code. - * @details This macro must be inserted at the start of all IRQ handlers. - */ -#define OSAL_IRQ_PROLOGUE() - -/** - * @brief IRQ epilogue code. - * @details This macro must be inserted at the end of all IRQ handlers. - */ -#define OSAL_IRQ_EPILOGUE() - -/** - * @brief IRQ handler function declaration. - * @details This macro hides the details of an ISR function declaration. - * - * @param[in] id a vector name as defined in @p vectors.s - */ -#define OSAL_IRQ_HANDLER(id) void id(void) -/** @} */ - -/** - * @name Time conversion utilities - * @{ - */ -/** - * @brief Seconds to system ticks. - * @details Converts from seconds to system ticks number. - * @note The result is rounded upward to the next tick boundary. - * - * @param[in] sec number of seconds - * @return The number of ticks. - * - * @api - */ -#define OSAL_S2ST(sec) \ - ((systime_t)((uint32_t)(sec) * (uint32_t)OSAL_ST_FREQUENCY)) - -/** - * @brief Milliseconds to system ticks. - * @details Converts from milliseconds to system ticks number. - * @note The result is rounded upward to the next tick boundary. - * - * @param[in] msec number of milliseconds - * @return The number of ticks. - * - * @api - */ -#define OSAL_MS2ST(msec) \ - ((systime_t)((((((uint32_t)(msec)) * \ - ((uint32_t)OSAL_ST_FREQUENCY)) - 1UL) / 1000UL) + 1UL)) - -/** - * @brief Microseconds to system ticks. - * @details Converts from microseconds to system ticks number. - * @note The result is rounded upward to the next tick boundary. - * - * @param[in] usec number of microseconds - * @return The number of ticks. - * - * @api - */ -#define OSAL_US2ST(usec) \ - ((systime_t)((((((uint32_t)(usec)) * \ - ((uint32_t)OSAL_ST_FREQUENCY)) - 1UL) / 1000000UL) + 1UL)) -/** @} */ - -/** - * @name Time conversion utilities for the realtime counter - * @{ - */ -/** - * @brief Seconds to realtime counter. - * @details Converts from seconds to realtime counter cycles. - * @note The macro assumes that @p freq >= @p 1. - * - * @param[in] freq clock frequency, in Hz, of the realtime counter - * @param[in] sec number of seconds - * @return The number of cycles. - * - * @api - */ -#define OSAL_S2RTC(freq, sec) ((freq) * (sec)) - -/** - * @brief Milliseconds to realtime counter. - * @details Converts from milliseconds to realtime counter cycles. - * @note The result is rounded upward to the next millisecond boundary. - * @note The macro assumes that @p freq >= @p 1000. - * - * @param[in] freq clock frequency, in Hz, of the realtime counter - * @param[in] msec number of milliseconds - * @return The number of cycles. - * - * @api - */ -#define OSAL_MS2RTC(freq, msec) (rtcnt_t)((((freq) + 999UL) / 1000UL) * (msec)) - -/** - * @brief Microseconds to realtime counter. - * @details Converts from microseconds to realtime counter cycles. - * @note The result is rounded upward to the next microsecond boundary. - * @note The macro assumes that @p freq >= @p 1000000. - * - * @param[in] freq clock frequency, in Hz, of the realtime counter - * @param[in] usec number of microseconds - * @return The number of cycles. - * - * @api - */ -#define OSAL_US2RTC(freq, usec) (rtcnt_t)((((freq) + 999999UL) / 1000000UL) * (usec)) -/** @} */ - -/** - * @name Sleep macros using absolute time - * @{ - */ -/** - * @brief Delays the invoking thread for the specified number of seconds. - * @note The specified time is rounded up to a value allowed by the real - * system tick clock. - * @note The maximum specifiable value is implementation dependent. - * - * @param[in] sec time in seconds, must be different from zero - * - * @api - */ -#define osalThreadSleepSeconds(sec) osalThreadSleep(OSAL_S2ST(sec)) - -/** - * @brief Delays the invoking thread for the specified number of - * milliseconds. - * @note The specified time is rounded up to a value allowed by the real - * system tick clock. - * @note The maximum specifiable value is implementation dependent. - * - * @param[in] msec time in milliseconds, must be different from zero - * - * @api - */ -#define osalThreadSleepMilliseconds(msec) osalThreadSleep(OSAL_MS2ST(msec)) - -/** - * @brief Delays the invoking thread for the specified number of - * microseconds. - * @note The specified time is rounded up to a value allowed by the real - * system tick clock. - * @note The maximum specifiable value is implementation dependent. - * - * @param[in] usec time in microseconds, must be different from zero - * - * @api - */ -#define osalThreadSleepMicroseconds(usec) osalThreadSleep(OSAL_US2ST(usec)) -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -extern const char *osal_halt_msg; - -#ifdef __cplusplus -extern "C" { -#endif - void osalInit(void); - void osalSysHalt(const char *reason); - void osalSysPolledDelayX(rtcnt_t cycles); - void osalOsTimerHandlerI(void); - void osalOsRescheduleS(void); - systime_t osalOsGetSystemTimeX(void); - void osalThreadSleepS(systime_t time); - void osalThreadSleep(systime_t time); - msg_t osalThreadSuspendS(thread_reference_t *trp); - msg_t osalThreadSuspendTimeoutS(thread_reference_t *trp, systime_t timeout); - void osalThreadResumeI(thread_reference_t *trp, msg_t msg); - void osalThreadResumeS(thread_reference_t *trp, msg_t msg); - msg_t osalThreadEnqueueTimeoutS(threads_queue_t *tqp, systime_t timeout); - void osalThreadDequeueNextI(threads_queue_t *tqp, msg_t msg); - void osalThreadDequeueAllI(threads_queue_t *tqp, msg_t msg); - void osalEventBroadcastFlagsI(event_source_t *esp, eventflags_t flags); - void osalEventBroadcastFlags(event_source_t *esp, eventflags_t flags); - void osalEventSetCallback(event_source_t *esp, - eventcallback_t cb, - void *param); - void osalMutexLock(mutex_t *mp); - void osalMutexUnlock(mutex_t *mp); -#ifdef __cplusplus -} -#endif - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -/** - * @brief Disables interrupts globally. - * - * @special - */ -static inline void osalSysDisable(void) { - -} - -/** - * @brief Enables interrupts globally. - * - * @special - */ -static inline void osalSysEnable(void) { - -} - -/** - * @brief Enters a critical zone from thread context. - * @note This function cannot be used for reentrant critical zones. - * - * @special - */ -static inline void osalSysLock(void) { - -} - -/** - * @brief Leaves a critical zone from thread context. - * @note This function cannot be used for reentrant critical zones. - * - * @special - */ -static inline void osalSysUnlock(void) { - -} - -/** - * @brief Enters a critical zone from ISR context. - * @note This function cannot be used for reentrant critical zones. - * - * @special - */ -static inline void osalSysLockFromISR(void) { - -} - -/** - * @brief Leaves a critical zone from ISR context. - * @note This function cannot be used for reentrant critical zones. - * - * @special - */ -static inline void osalSysUnlockFromISR(void) { - -} - -/** - * @brief Returns the execution status and enters a critical zone. - * @details This functions enters into a critical zone and can be called - * from any context. Because its flexibility it is less efficient - * than @p chSysLock() which is preferable when the calling context - * is known. - * @post The system is in a critical zone. - * - * @return The previous system status, the encoding of this - * status word is architecture-dependent and opaque. - * - * @xclass - */ -static inline syssts_t osalSysGetStatusAndLockX(void) { - - return (syssts_t)0; -} - -/** - * @brief Restores the specified execution status and leaves a critical zone. - * @note A call to @p chSchRescheduleS() is automatically performed - * if exiting the critical zone and if not in ISR context. - * - * @param[in] sts the system status to be restored. - * - * @xclass - */ -static inline void osalSysRestoreStatusX(syssts_t sts) { - - (void)sts; -} - -/** - * @brief Checks if the specified time is within the specified time window. - * @note When start==end then the function returns always true because the - * whole time range is specified. - * @note This function can be called from any context. - * - * @param[in] time the time to be verified - * @param[in] start the start of the time window (inclusive) - * @param[in] end the end of the time window (non inclusive) - * @retval true current time within the specified time window. - * @retval false current time not within the specified time window. - * - * @xclass - */ -static inline bool osalOsIsTimeWithinX(systime_t time, - systime_t start, - systime_t end) { - - return (bool)((time - start) < (end - start)); -} - -/** - * @brief Initializes a threads queue object. - * - * @param[out] tqp pointer to the threads queue object - * - * @init - */ -static inline void osalThreadQueueObjectInit(threads_queue_t *tqp) { - - osalDbgCheck(tqp != NULL); -} - -/** - * @brief Initializes an event flags object. - * - * @param[out] esp pointer to the event flags object - * - * @init - */ -static inline void osalEventObjectInit(event_source_t *esp) { - - osalDbgCheck(esp != NULL); - - esp->flags = (eventflags_t)0; - esp->cb = NULL; - esp->param = NULL; -} - -/** - * @brief Initializes s @p mutex_t object. - * - * @param[out] mp pointer to the @p mutex_t object - * - * @init - */ -static inline void osalMutexObjectInit(mutex_t *mp) { - - osalDbgCheck(mp != NULL); - - *mp = 0; -} - -#endif /* _OSAL_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/osal/osal.mk b/firmware/ChibiOS_16/os/hal/templates/osal/osal.mk deleted file mode 100644 index 3cea5361ed..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/osal/osal.mk +++ /dev/null @@ -1,5 +0,0 @@ -# OSAL files. -OSALSRC += ${CHIBIOS}/os/hal/templates/osal/osal.c - -# Required include directories -OSALINC += ${CHIBIOS}/os/hal/templates/osal diff --git a/firmware/ChibiOS_16/os/hal/templates/pal_lld.c b/firmware/ChibiOS_16/os/hal/templates/pal_lld.c deleted file mode 100644 index b5ccca6a06..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/pal_lld.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file pal_lld.c - * @brief PLATFORM PAL subsystem low level driver source. - * - * @addtogroup PAL - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_PAL == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief STM32 I/O ports configuration. - * @details Ports A-D(E, F, G, H) clocks enabled. - * - * @param[in] config the STM32 ports configuration - * - * @notapi - */ -void _pal_lld_init(const PALConfig *config) { - - (void)config; - -} - -/** - * @brief Pads mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * - * @param[in] port the port identifier - * @param[in] mask the group mask - * @param[in] mode the mode - * - * @notapi - */ -void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - iomode_t mode) { - - (void)port; - (void)mask; - (void)mode; - -} - -#endif /* HAL_USE_PAL == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/pal_lld.h b/firmware/ChibiOS_16/os/hal/templates/pal_lld.h deleted file mode 100644 index 1ce2086315..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/pal_lld.h +++ /dev/null @@ -1,422 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file pal_lld.h - * @brief PLATFORM PAL subsystem low level driver header. - * - * @addtogroup PAL - * @{ - */ - -#ifndef _PAL_LLD_H_ -#define _PAL_LLD_H_ - -#if (HAL_USE_PAL == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Unsupported modes and specific modes */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* I/O Ports Types and constants. */ -/*===========================================================================*/ - -/** - * @name Port related definitions - * @{ - */ -/** - * @brief Width, in bits, of an I/O port. - */ -#define PAL_IOPORTS_WIDTH 16U - -/** - * @brief Whole port mask. - * @details This macro specifies all the valid bits into a port. - */ -#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFU) -/** @} */ - -/** - * @name Line handling macros - * @{ - */ -/** - * @brief Forms a line identifier. - * @details A port/pad pair are encoded into an @p ioline_t type. The encoding - * of this type is platform-dependent. - */ -#define PAL_LINE(port, pad) \ - ((ioline_t)((uint32_t)(port)) | ((uint32_t)(pad))) - -/** - * @brief Decodes a port identifier from a line identifier. - */ -#define PAL_PORT(line) \ - ((stm32_gpio_t *)(((uint32_t)(line)) & 0xFFFFFFF0U)) - -/** - * @brief Decodes a pad identifier from a line identifier. - */ -#define PAL_PAD(line) \ - ((uint32_t)((uint32_t)(line) & 0x0000000FU)) - -/** - * @brief Value identifying an invalid line. - */ -#define PAL_NOLINE 0U -/** @} */ - -/** - * @brief Generic I/O ports static initializer. - * @details An instance of this structure must be passed to @p palInit() at - * system startup time in order to initialized the digital I/O - * subsystem. This represents only the initial setup, specific pads - * or whole ports can be reprogrammed at later time. - * @note Implementations may extend this structure to contain more, - * architecture dependent, fields. - */ -typedef struct { - -} PALConfig; - -/** - * @brief Digital I/O port sized unsigned type. - */ -typedef uint32_t ioportmask_t; - -/** - * @brief Digital I/O modes. - */ -typedef uint32_t iomode_t; - -/** - * @brief Type of an I/O line. - */ -typedef uint32_t ioline_t; - -/** - * @brief Port Identifier. - * @details This type can be a scalar or some kind of pointer, do not make - * any assumption about it, use the provided macros when populating - * variables of this type. - */ -typedef uint32_t ioportid_t; - -/*===========================================================================*/ -/* I/O Ports Identifiers. */ -/*===========================================================================*/ - -/** - * @brief First I/O port identifier. - * @details Low level drivers can define multiple ports, it is suggested to - * use this naming convention. - */ -#define IOPORT1 0 - -/*===========================================================================*/ -/* Implementation, some of the following macros could be implemented as */ -/* functions, if so please put them in pal_lld.c. */ -/*===========================================================================*/ - -/** - * @brief Low level PAL subsystem initialization. - * - * @param[in] config architecture-dependent ports configuration - * - * @notapi - */ -#define pal_lld_init(config) _pal_lld_init(config) - -/** - * @brief Reads the physical I/O port states. - * - * @param[in] port port identifier - * @return The port bits. - * - * @notapi - */ -#define pal_lld_readport(port) 0U - -/** - * @brief Reads the output latch. - * @details The purpose of this function is to read back the latched output - * value. - * - * @param[in] port port identifier - * @return The latched logical states. - * - * @notapi - */ -#define pal_lld_readlatch(port) 0U - -/** - * @brief Writes a bits mask on a I/O port. - * - * @param[in] port port identifier - * @param[in] bits bits to be written on the specified port - * - * @notapi - */ -#define pal_lld_writeport(port, bits) \ - do { \ - (void)port; \ - (void)bits; \ - } while (false) - - -/** - * @brief Sets a bits mask on a I/O port. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] bits bits to be ORed on the specified port - * - * @notapi - */ -#define pal_lld_setport(port, bits) \ - do { \ - (void)port; \ - (void)bits; \ - } while (false) - - -/** - * @brief Clears a bits mask on a I/O port. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] bits bits to be cleared on the specified port - * - * @notapi - */ -#define pal_lld_clearport(port, bits) \ - do { \ - (void)port; \ - (void)bits; \ - } while (false) - - -/** - * @brief Toggles a bits mask on a I/O port. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] bits bits to be XORed on the specified port - * - * @notapi - */ -#define pal_lld_toggleport(port, bits) \ - do { \ - (void)port; \ - (void)bits; \ - } while (false) - - -/** - * @brief Reads a group of bits. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] offset group bit offset within the port - * @return The group logical states. - * - * @notapi - */ -#define pal_lld_readgroup(port, mask, offset) 0U - -/** - * @brief Writes a group of bits. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] offset group bit offset within the port - * @param[in] bits bits to be written. Values exceeding the group width - * are masked. - * - * @notapi - */ -#define pal_lld_writegroup(port, mask, offset, bits) \ - do { \ - (void)port; \ - (void)mask; \ - (void)offset; \ - (void)bits; \ - } while (false) - -/** - * @brief Pads group mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * @note Programming an unknown or unsupported mode is silently ignored. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] offset group bit offset within the port - * @param[in] mode group mode - * - * @notapi - */ -#define pal_lld_setgroupmode(port, mask, offset, mode) \ - _pal_lld_setgroupmode(port, mask << offset, mode) - -/** - * @brief Reads a logical state from an I/O pad. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * @return The logical state. - * @retval PAL_LOW low logical state. - * @retval PAL_HIGH high logical state. - * - * @notapi - */ -#define pal_lld_readpad(port, pad) PAL_LOW - -/** - * @brief Writes a logical state on an output pad. - * @note This function is not meant to be invoked directly by the - * application code. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * @param[in] bit logical value, the value must be @p PAL_LOW or - * @p PAL_HIGH - * - * @notapi - */ -#define pal_lld_writepad(port, pad, bit) \ - do { \ - (void)port; \ - (void)pad; \ - (void)bit; \ - } while (false) - -/** - * @brief Sets a pad logical state to @p PAL_HIGH. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * - * @notapi - */ -#define pal_lld_setpad(port, pad) \ - do { \ - (void)port; \ - (void)pad; \ - } while (false) - - -/** - * @brief Clears a pad logical state to @p PAL_LOW. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * - * @notapi - */ -#define pal_lld_clearpad(port, pad) \ - do { \ - (void)port; \ - (void)pad; \ - } while (false) - - -/** - * @brief Toggles a pad logical state. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * - * @notapi - */ -#define pal_lld_togglepad(port, pad) \ - do { \ - (void)port; \ - (void)pad; \ - } while (false) - - -/** - * @brief Pad mode setup. - * @details This function programs a pad with the specified mode. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * @note Programming an unknown or unsupported mode is silently ignored. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * @param[in] mode pad mode - * - * @notapi - */ -#define pal_lld_setpadmode(port, pad, mode) \ - do { \ - (void)port; \ - (void)pad; \ - (void)mode; \ - } while (false) - - -#if !defined(__DOXYGEN__) -extern const PALConfig pal_default_config; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void _pal_lld_init(const PALConfig *config); - void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - iomode_t mode); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_PAL == TRUE */ - -#endif /* _PAL_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/platform.mk b/firmware/ChibiOS_16/os/hal/templates/platform.mk deleted file mode 100644 index 8058226786..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/platform.mk +++ /dev/null @@ -1,20 +0,0 @@ -# List of all the template platform files. -PLATFORMSRC = ${CHIBIOS}/os/hal/templates/hal_lld.c \ - ${CHIBIOS}/os/hal/templates/adc_lld.c \ - ${CHIBIOS}/os/hal/templates/can_lld.c \ - ${CHIBIOS}/os/hal/templates/dac_lld.c \ - ${CHIBIOS}/os/hal/templates/ext_lld.c \ - ${CHIBIOS}/os/hal/templates/gpt_lld.c \ - ${CHIBIOS}/os/hal/templates/i2c_lld.c \ - ${CHIBIOS}/os/hal/templates/icu_lld.c \ - ${CHIBIOS}/os/hal/templates/mac_lld.c \ - ${CHIBIOS}/os/hal/templates/pal_lld.c \ - ${CHIBIOS}/os/hal/templates/pwm_lld.c \ - ${CHIBIOS}/os/hal/templates/sdc_lld.c \ - ${CHIBIOS}/os/hal/templates/serial_lld.c \ - ${CHIBIOS}/os/hal/templates/spi_lld.c \ - ${CHIBIOS}/os/hal/templates/uart_lld.c \ - ${CHIBIOS}/os/hal/templates/usb_lld.c - -# Required include directories -PLATFORMINC = ${CHIBIOS}/os/hal/templates diff --git a/firmware/ChibiOS_16/os/hal/templates/pwm_lld.c b/firmware/ChibiOS_16/os/hal/templates/pwm_lld.c deleted file mode 100644 index e09d3fdc40..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/pwm_lld.c +++ /dev/null @@ -1,220 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file pwm_lld.c - * @brief PLATFORM PWM subsystem low level driver source. - * - * @addtogroup PWM - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_PWM == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief PWMD1 driver identifier. - * @note The driver PWMD1 allocates the complex timer TIM1 when enabled. - */ -#if (PLATFORM_PWM_USE_PWM1 == TRUE) || defined(__DOXYGEN__) -PWMDriver PWMD1; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level PWM driver initialization. - * - * @notapi - */ -void pwm_lld_init(void) { - -#if PLATFORM_PWM_USE_PWM1 == TRUE - /* Driver initialization.*/ - pwmObjectInit(&PWMD1); -#endif -} - -/** - * @brief Configures and activates the PWM peripheral. - * @note Starting a driver that is already in the @p PWM_READY state - * disables all the active channels. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * - * @notapi - */ -void pwm_lld_start(PWMDriver *pwmp) { - - if (pwmp->state == PWM_STOP) { - /* Clock activation and timer reset.*/ -#if PLATFORM_PWM_USE_PWM1 == TRUE - if (&PWMD1 == pwmp) { - - } -#endif - } -} - -/** - * @brief Deactivates the PWM peripheral. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * - * @notapi - */ -void pwm_lld_stop(PWMDriver *pwmp) { - - /* If in ready state then disables the PWM clock.*/ - if (pwmp->state == PWM_READY) { -#if PLATFORM_PWM_USE_PWM1 == TRUE - if (&PWMD1 == pwmp) { - - } -#endif - } -} - -/** - * @brief Enables a PWM channel. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @post The channel is active using the specified configuration. - * @note The function has effect at the next cycle start. - * @note Channel notification is not enabled. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier (0...channels-1) - * @param[in] width PWM pulse width as clock pulses number - * - * @notapi - */ -void pwm_lld_enable_channel(PWMDriver *pwmp, - pwmchannel_t channel, - pwmcnt_t width) { - - (void)pwmp; - (void)channel; - (void)width; -} - -/** - * @brief Disables a PWM channel and its notification. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @post The channel is disabled and its output line returned to the - * idle state. - * @note The function has effect at the next cycle start. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier (0...channels-1) - * - * @notapi - */ -void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) { - - (void)pwmp; - (void)channel; -} - -/** - * @brief Enables the periodic activation edge notification. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @note If the notification is already enabled then the call has no effect. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * - * @notapi - */ -void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) { - - (void)pwmp; -} - -/** - * @brief Disables the periodic activation edge notification. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @note If the notification is already disabled then the call has no effect. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * - * @notapi - */ -void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) { - - (void)pwmp; -} - -/** - * @brief Enables a channel de-activation edge notification. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @pre The channel must have been activated using @p pwmEnableChannel(). - * @note If the notification is already enabled then the call has no effect. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier (0...channels-1) - * - * @notapi - */ -void pwm_lld_enable_channel_notification(PWMDriver *pwmp, - pwmchannel_t channel) { - - (void)pwmp; - (void)channel; -} - -/** - * @brief Disables a channel de-activation edge notification. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @pre The channel must have been activated using @p pwmEnableChannel(). - * @note If the notification is already disabled then the call has no effect. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier (0...channels-1) - * - * @notapi - */ -void pwm_lld_disable_channel_notification(PWMDriver *pwmp, - pwmchannel_t channel) { - - (void)pwmp; - (void)channel; -} - -#endif /* HAL_USE_PWM == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/pwm_lld.h b/firmware/ChibiOS_16/os/hal/templates/pwm_lld.h deleted file mode 100644 index db8ecf946b..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/pwm_lld.h +++ /dev/null @@ -1,215 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file pwm_lld.h - * @brief PLATFORM PWM subsystem low level driver header. - * - * @addtogroup PWM - * @{ - */ - -#ifndef _PWM_LLD_H_ -#define _PWM_LLD_H_ - -#if (HAL_USE_PWM == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Number of PWM channels per PWM driver. - */ -#define PWM_CHANNELS 4 - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name PLATFORM configuration options - * @{ - */ -/** - * @brief PWMD1 driver enable switch. - * @details If set to @p TRUE the support for PWM1 is included. - * @note The default is @p FALSE. - */ -#if !defined(PLATFORM_PWM_USE_PWM1) || defined(__DOXYGEN__) -#define PLATFORM_PWM_USE_PWM1 FALSE -#endif -/** @} */ - -/*===========================================================================*/ -/* Configuration checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a PWM mode. - */ -typedef uint32_t pwmmode_t; - -/** - * @brief Type of a PWM channel. - */ -typedef uint8_t pwmchannel_t; - -/** - * @brief Type of a channels mask. - */ -typedef uint32_t pwmchnmsk_t; - -/** - * @brief Type of a PWM counter. - */ -typedef uint32_t pwmcnt_t; - -/** - * @brief Type of a PWM driver channel configuration structure. - */ -typedef struct { - /** - * @brief Channel active logic level. - */ - pwmmode_t mode; - /** - * @brief Channel callback pointer. - * @note This callback is invoked on the channel compare event. If set to - * @p NULL then the callback is disabled. - */ - pwmcallback_t callback; - /* End of the mandatory fields.*/ -} PWMChannelConfig; - -/** - * @brief Type of a PWM driver configuration structure. - */ -typedef struct { - /** - * @brief Timer clock in Hz. - * @note The low level can use assertions in order to catch invalid - * frequency specifications. - */ - uint32_t frequency; - /** - * @brief PWM period in ticks. - * @note The low level can use assertions in order to catch invalid - * period specifications. - */ - pwmcnt_t period; - /** - * @brief Periodic callback pointer. - * @note This callback is invoked on PWM counter reset. If set to - * @p NULL then the callback is disabled. - */ - pwmcallback_t callback; - /** - * @brief Channels configurations. - */ - PWMChannelConfig channels[PWM_CHANNELS]; - /* End of the mandatory fields.*/ -} PWMConfig; - -/** - * @brief Structure representing a PWM driver. - */ -struct PWMDriver { - /** - * @brief Driver state. - */ - pwmstate_t state; - /** - * @brief Current driver configuration data. - */ - const PWMConfig *config; - /** - * @brief Current PWM period in ticks. - */ - pwmcnt_t period; - /** - * @brief Mask of the enabled channels. - */ - pwmchnmsk_t enabled; - /** - * @brief Number of channels in this instance. - */ - pwmchannel_t channels; -#if defined(PWM_DRIVER_EXT_FIELDS) - PWM_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Changes the period the PWM peripheral. - * @details This function changes the period of a PWM unit that has already - * been activated using @p pwmStart(). - * @pre The PWM unit must have been activated using @p pwmStart(). - * @post The PWM unit period is changed to the new value. - * @note The function has effect at the next cycle start. - * @note If a period is specified that is shorter than the pulse width - * programmed in one of the channels then the behavior is not - * guaranteed. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] period new cycle time in ticks - * - * @notapi - */ -#define pwm_lld_change_period(pwmp, period) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if (PLATFORM_PWM_USE_PWM1 == TRUE) && !defined(__DOXYGEN__) -extern PWMDriver PWMD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void pwm_lld_init(void); - void pwm_lld_start(PWMDriver *pwmp); - void pwm_lld_stop(PWMDriver *pwmp); - void pwm_lld_enable_channel(PWMDriver *pwmp, - pwmchannel_t channel, - pwmcnt_t width); - void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel); - void pwm_lld_enable_periodic_notification(PWMDriver *pwmp); - void pwm_lld_disable_periodic_notification(PWMDriver *pwmp); - void pwm_lld_enable_channel_notification(PWMDriver *pwmp, - pwmchannel_t channel); - void pwm_lld_disable_channel_notification(PWMDriver *pwmp, - pwmchannel_t channel); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_PWM == TRUE */ - -#endif /* _PWM_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/rtc_lld.c b/firmware/ChibiOS_16/os/hal/templates/rtc_lld.c deleted file mode 100644 index a3fc5cc23f..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/rtc_lld.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Concepts and parts of this file have been contributed by Uladzimir Pylinsky - aka barthess. - */ - -/** - * @file rtc_lld.c - * @brief PLATFORM RTC subsystem low level driver source. - * - * @addtogroup RTC - * @{ - */ - -#include "hal.h" - -#if HAL_USE_RTC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief RTC driver identifier. - */ -RTCDriver RTCD1; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Enable access to registers. - * - * @notapi - */ -void rtc_lld_init(void) { - - /* RTC object initialization.*/ - rtcObjectInit(&RTCD1); -} - -/** - * @brief Set current time. - * @note Fractional part will be silently ignored. There is no possibility - * to set it on PLATFORM platform. - * @note The function can be called from any context. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[in] timespec pointer to a @p RTCDateTime structure - * - * @notapi - */ -void rtc_lld_set_time(RTCDriver *rtcp, const RTCDateTime *timespec) { - - (void)rtcp; - (void)timespec; -} - -/** - * @brief Get current time. - * @note The function can be called from any context. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[out] timespec pointer to a @p RTCDateTime structure - * - * @notapi - */ -void rtc_lld_get_time(RTCDriver *rtcp, RTCDateTime *timespec) { - - (void)rtcp; - (void)timespec; -} - -#if (RTC_ALARMS > 0) || defined(__DOXYGEN__) -/** - * @brief Set alarm time. - * @note Default value after BKP domain reset for both comparators is 0. - * @note Function does not performs any checks of alarm time validity. - * @note The function can be called from any context. - * - * @param[in] rtcp pointer to RTC driver structure. - * @param[in] alarm alarm identifier. Can be 1 or 2. - * @param[in] alarmspec pointer to a @p RTCAlarm structure. - * - * @notapi - */ -void rtc_lld_set_alarm(RTCDriver *rtcp, - rtcalarm_t alarm, - const RTCAlarm *alarmspec) { - - (void)rtcp; - (void)alarm; - (void)alarmspec; -} - -/** - * @brief Get alarm time. - * @note The function can be called from any context. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[in] alarm alarm identifier - * @param[out] alarmspec pointer to a @p RTCAlarm structure - * - * @notapi - */ -void rtc_lld_get_alarm(RTCDriver *rtcp, - rtcalarm_t alarm, - RTCAlarm *alarmspec) { - - (void)rtcp; - (void)alarm; - (void)alarmspec; -} -#endif /* RTC_ALARMS > 0 */ - -#endif /* HAL_USE_RTC */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/rtc_lld.h b/firmware/ChibiOS_16/os/hal/templates/rtc_lld.h deleted file mode 100644 index 4c20f2e116..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/rtc_lld.h +++ /dev/null @@ -1,182 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Concepts and parts of this file have been contributed by Uladzimir Pylinsky - aka barthess. - */ - -/** - * @file rtc_lld.h - * @brief PLATFORM RTC subsystem low level driver header. - * - * @addtogroup RTC - * @{ - */ - -#ifndef _RTC_LLD_H_ -#define _RTC_LLD_H_ - -#if (HAL_USE_RTC == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name Implementation capabilities - */ -/** - * @brief Callback support int the driver. - */ -#define RTC_SUPPORTS_CALLBACKS TRUE - -/** - * @brief Number of alarms available. - */ -#define RTC_ALARMS 2 - -/** - * @brief Presence of a local persistent storage. - */ -#define RTC_HAS_STORAGE FALSE -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name PLATFORM configuration options - * @{ - */ -/** - * @brief RTCD1 driver enable switch. - * @details If set to @p TRUE the support for RTC1 is included. - * @note The default is @p FALSE. - */ -#if !defined(PLATFORM_RTC_USE_RTC1) || defined(__DOXYGEN__) -#define PLATFORM_RTC_USE_RTC1 FALSE -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief FileStream specific methods. - */ -#define _rtc_driver_methods \ - _file_stream_methods - -/** - * @brief Type of an RTC alarm number. - */ -typedef uint32_t rtcalarm_t; - -#if (RTC_SUPPORTS_CALLBACKS == TRUE) || defined(__DOXYGEN__) -/** - * @brief Type of an RTC event. - */ -typedef enum { - RTC_EVENT_SECOND = 0 /** Triggered every second. */ -} rtcevent_t; - -/** - * @brief Type of a generic RTC callback. - */ -typedef void (*rtccb_t)(RTCDriver *rtcp, rtcevent_t event); -#endif - -/** - * @brief Type of a structure representing an RTC alarm time stamp. - */ -typedef struct { - /* End of the mandatory fields.*/ - uint32_t dummy; -} RTCAlarm; - -#if (RTC_HAS_STORAGE == TRUE) || defined(__DOXYGEN__) -/** - * @extends FileStream - * - * @brief @p RTCDriver virtual methods table. - */ -struct RTCDriverVMT { - _rtc_driver_methods -}; -#endif - -/** - * @brief Structure representing an RTC driver. - */ -struct RTCDriver { -#if (RTC_HAS_STORAGE == TRUE) || defined(__DOXYGEN__) - /** - * @brief Virtual Methods Table. - */ - const struct RTCDriverVMT *vmt; -#endif - /* End of the mandatory fields.*/ - uint32_t dummy; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if (PLATFORM_RTC_USE_RTC1 == TRUE) && !defined(__DOXYGEN__) -extern RTCDriver RTCD1; -#endif - -#if (RTC_HAS_STORAGE == TRUE) && !defined(__DOXYGEN__) -extern struct RTCDriverVMT _rtc_lld_vmt; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void rtc_lld_init(void); - void rtc_lld_set_time(RTCDriver *rtcp, const RTCDateTime *timespec); - void rtc_lld_get_time(RTCDriver *rtcp, RTCDateTime *timespec); -#if RTC_ALARMS > 0 - void rtc_lld_set_alarm(RTCDriver *rtcp, - rtcalarm_t alarm, - const RTCAlarm *alarmspec); - void rtc_lld_get_alarm(RTCDriver *rtcp, - rtcalarm_t alarm, - RTCAlarm *alarmspec); -#endif -#if RTC_SUPPORTS_CALLBACKS == TRUE - void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback); -#endif -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_RTC == TRUE */ - -#endif /* _RTC_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/sdc_lld.c b/firmware/ChibiOS_16/os/hal/templates/sdc_lld.c deleted file mode 100644 index c55dca790f..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/sdc_lld.c +++ /dev/null @@ -1,328 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file sdc_lld.c - * @brief PLATFORM SDC subsystem low level driver source. - * - * @addtogroup SDC - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_SDC == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief SDCD1 driver identifier. - */ -#if (PLATFORM_SDC_USE_SDC1 == TRUE) || defined(__DOXYGEN__) -SDCDriver SDCD1; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level SDC driver initialization. - * - * @notapi - */ -void sdc_lld_init(void) { - -#if PLATFORM_SDC_USE_SDC1 == TRUE - sdcObjectInit(&SDCD1); -#endif -} - -/** - * @brief Configures and activates the SDC peripheral. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @notapi - */ -void sdc_lld_start(SDCDriver *sdcp) { - - if (sdcp->state == BLK_STOP) { - - } -} - -/** - * @brief Deactivates the SDC peripheral. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @notapi - */ -void sdc_lld_stop(SDCDriver *sdcp) { - - if (sdcp->state != BLK_STOP) { - - } -} - -/** - * @brief Starts the SDIO clock and sets it to init mode (400kHz or less). - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @notapi - */ -void sdc_lld_start_clk(SDCDriver *sdcp) { - - (void)sdcp; -} - -/** - * @brief Sets the SDIO clock to data mode (25MHz or less). - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] clk the clock mode - * - * @notapi - */ -void sdc_lld_set_data_clk(SDCDriver *sdcp, sdcbusclk_t clk) { - - (void)sdcp; - (void)clk; -} - -/** - * @brief Stops the SDIO clock. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @notapi - */ -void sdc_lld_stop_clk(SDCDriver *sdcp) { - - (void)sdcp; -} - -/** - * @brief Switches the bus to 4 bits mode. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] mode bus mode - * - * @notapi - */ -void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode) { - - (void)sdcp; - - switch (mode) { - case SDC_MODE_1BIT: - - break; - case SDC_MODE_4BIT: - - break; - case SDC_MODE_8BIT: - - break; - default: - osalDbgAssert(false, "invalid bus mode"); - break; - } -} - -/** - * @brief Sends an SDIO command with no response expected. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] cmd card command - * @param[in] arg command argument - * - * @notapi - */ -void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg) { - - (void)sdcp; - (void)cmd; - (void)arg; -} - -/** - * @brief Sends an SDIO command with a short response expected. - * @note The CRC is not verified. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] cmd card command - * @param[in] arg command argument - * @param[out] resp pointer to the response buffer (one word) - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @notapi - */ -bool sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, - uint32_t *resp) { - - (void)sdcp; - (void)cmd; - (void)arg; - (void)resp; - - return HAL_SUCCESS; -} - -/** - * @brief Sends an SDIO command with a short response expected and CRC. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] cmd card command - * @param[in] arg command argument - * @param[out] resp pointer to the response buffer (one word) - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @notapi - */ -bool sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, - uint32_t *resp) { - - (void)sdcp; - (void)cmd; - (void)arg; - (void)resp; - - return HAL_SUCCESS; -} - -/** - * @brief Sends an SDIO command with a long response expected and CRC. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] cmd card command - * @param[in] arg command argument - * @param[out] resp pointer to the response buffer (four words) - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @notapi - */ -bool sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, - uint32_t *resp) { - - (void)sdcp; - (void)cmd; - (void)arg; - (void)resp; - - return HAL_SUCCESS; -} - -/** - * @brief Reads one or more blocks. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] startblk first block to read - * @param[out] buf pointer to the read buffer - * @param[in] n number of blocks to read - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @notapi - */ -bool sdc_lld_read(SDCDriver *sdcp, uint32_t startblk, - uint8_t *buf, uint32_t n) { - - (void)sdcp; - (void)startblk; - (void)buf; - (void)n; - - return HAL_SUCCESS; -} - -/** - * @brief Writes one or more blocks. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] startblk first block to write - * @param[out] buf pointer to the write buffer - * @param[in] n number of blocks to write - * - * @return The operation status. - * @retval HAL_SUCCESS operation succeeded. - * @retval HAL_FAILED operation failed. - * - * @notapi - */ -bool sdc_lld_write(SDCDriver *sdcp, uint32_t startblk, - const uint8_t *buf, uint32_t n) { - - (void)sdcp; - (void)startblk; - (void)buf; - (void)n; - - return HAL_SUCCESS; -} - -/** - * @brief Waits for card idle condition. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @return The operation status. - * @retval HAL_SUCCESS the operation succeeded. - * @retval HAL_FAILED the operation failed. - * - * @api - */ -bool sdc_lld_sync(SDCDriver *sdcp) { - - (void)sdcp; - - return HAL_SUCCESS; -} - -#endif /* HAL_USE_SDC == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/sdc_lld.h b/firmware/ChibiOS_16/os/hal/templates/sdc_lld.h deleted file mode 100644 index 1b395888b4..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/sdc_lld.h +++ /dev/null @@ -1,184 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file sdc_lld.h - * @brief PLATFORM SDC subsystem low level driver header. - * - * @addtogroup SDC - * @{ - */ - -#ifndef _SDC_LLD_H_ -#define _SDC_LLD_H_ - -#if (HAL_USE_SDC == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name PLATFORM configuration options - * @{ - */ -/** - * @brief PWMD1 driver enable switch. - * @details If set to @p TRUE the support for PWM1 is included. - * @note The default is @p FALSE. - */ -#if !defined(PLATFORM_SDC_USE_SDC1) || defined(__DOXYGEN__) -#define PLATFORM_SDC_USE_SDC1 FALSE -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of card flags. - */ -typedef uint32_t sdcmode_t; - -/** - * @brief SDC Driver condition flags type. - */ -typedef uint32_t sdcflags_t; - -/** - * @brief Type of a structure representing an SDC driver. - */ -typedef struct SDCDriver SDCDriver; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief Working area for memory consuming operations. - * @note It is mandatory for detecting MMC cards bigger than 2GB else it - * can be @p NULL. - * @note Memory pointed by this buffer is only used by @p sdcConnect(), - * afterward it can be reused for other purposes. - */ - uint8_t *scratchpad; - /** - * @brief Bus width. - */ - sdcbusmode_t bus_width; - /* End of the mandatory fields.*/ -} SDCConfig; - -/** - * @brief @p SDCDriver specific methods. - */ -#define _sdc_driver_methods \ - _mmcsd_block_device_methods - -/** - * @extends MMCSDBlockDeviceVMT - * - * @brief @p SDCDriver virtual methods table. - */ -struct SDCDriverVMT { - _sdc_driver_methods -}; - -/** - * @brief Structure representing an SDC driver. - */ -struct SDCDriver { - /** - * @brief Virtual Methods Table. - */ - const struct SDCDriverVMT *vmt; - _mmcsd_block_device_data - /** - * @brief Current configuration data. - */ - const SDCConfig *config; - /** - * @brief Various flags regarding the mounted card. - */ - sdcmode_t cardmode; - /** - * @brief Errors flags. - */ - sdcflags_t errors; - /** - * @brief Card RCA. - */ - uint32_t rca; - /* End of the mandatory fields.*/ -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if (PLATFORM_SDC_USE_SDC1 == TRUE) && !defined(__DOXYGEN__) -extern SDCDriver SDCD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void sdc_lld_init(void); - void sdc_lld_start(SDCDriver *sdcp); - void sdc_lld_stop(SDCDriver *sdcp); - void sdc_lld_start_clk(SDCDriver *sdcp); - void sdc_lld_set_data_clk(SDCDriver *sdcp, sdcbusclk_t clk); - void sdc_lld_stop_clk(SDCDriver *sdcp); - void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode); - void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg); - bool sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, - uint32_t *resp); - bool sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, - uint32_t *resp); - bool sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, - uint32_t *resp); - bool sdc_lld_read_special(SDCDriver *sdcp, uint8_t *buf, size_t bytes, - uint8_t cmd, uint32_t argument); - bool sdc_lld_read(SDCDriver *sdcp, uint32_t startblk, - uint8_t *buf, uint32_t n); - bool sdc_lld_write(SDCDriver *sdcp, uint32_t startblk, - const uint8_t *buf, uint32_t n); - bool sdc_lld_sync(SDCDriver *sdcp); - bool sdc_lld_is_card_inserted(SDCDriver *sdcp); - bool sdc_lld_is_write_protected(SDCDriver *sdcp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_SDC == TRUE */ - -#endif /* _SDC_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/serial_lld.c b/firmware/ChibiOS_16/os/hal/templates/serial_lld.c deleted file mode 100644 index e949f89a48..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/serial_lld.c +++ /dev/null @@ -1,127 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file serial_lld.c - * @brief PLATFORM serial subsystem low level driver source. - * - * @addtogroup SERIAL - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_SERIAL == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief USART1 serial driver identifier.*/ -#if (PLATFORM_SERIAL_USE_USART1 == TRUE) || defined(__DOXYGEN__) -SerialDriver SD1; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief Driver default configuration. - */ -static const SerialConfig default_config = { - 38400 -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level serial driver initialization. - * - * @notapi - */ -void sd_lld_init(void) { - -#if PLATFORM_SERIAL_USE_USART1 == TRUE - sdObjectInit(&SD1, NULL, notify1); -#endif -} - -/** - * @brief Low level serial driver configuration and (re)start. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] config the architecture-dependent serial driver configuration. - * If this parameter is set to @p NULL then a default - * configuration is used. - * - * @notapi - */ -void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { - - if (config == NULL) { - config = &default_config; - } - - - if (sdp->state == SD_STOP) { -#if PLATFORM_SERIAL_USE_USART1 == TRUE - if (&SD1 == sdp) { - - } -#endif - } - /* Configures the peripheral.*/ - (void)config; /* Warning suppression, remove this.*/ -} - -/** - * @brief Low level serial driver stop. - * @details De-initializes the USART, stops the associated clock, resets the - * interrupt vector. - * - * @param[in] sdp pointer to a @p SerialDriver object - * - * @notapi - */ -void sd_lld_stop(SerialDriver *sdp) { - - if (sdp->state == SD_READY) { -#if PLATFORM_SERIAL_USE_USART1 == TRUE - if (&SD1 == sdp) { - - } -#endif - } -} - -#endif /* HAL_USE_SERIAL == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/serial_lld.h b/firmware/ChibiOS_16/os/hal/templates/serial_lld.h deleted file mode 100644 index cb9ebfa059..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/serial_lld.h +++ /dev/null @@ -1,119 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file serial_lld.h - * @brief PLATFORM serial subsystem low level driver header. - * - * @addtogroup SERIAL - * @{ - */ - -#ifndef _SERIAL_LLD_H_ -#define _SERIAL_LLD_H_ - -#if (HAL_USE_SERIAL == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name PLATFORM configuration options - * @{ - */ -/** - * @brief USART1 driver enable switch. - * @details If set to @p TRUE the support for USART1 is included. - * @note The default is @p FALSE. - */ -#if !defined(PLATFORM_SERIAL_USE_USART1) || defined(__DOXYGEN__) -#define PLATFORM_SERIAL_USE_USART1 FALSE -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief PLATFORM Serial Driver configuration structure. - * @details An instance of this structure must be passed to @p sdStart() - * in order to configure and start a serial driver operations. - * @note This structure content is architecture dependent, each driver - * implementation defines its own version and the custom static - * initializers. - */ -typedef struct { - /** - * @brief Bit rate. - */ - uint32_t speed; - /* End of the mandatory fields.*/ -} SerialConfig; - -/** - * @brief @p SerialDriver specific data. - */ -#define _serial_driver_data \ - _base_asynchronous_channel_data \ - /* Driver state.*/ \ - sdstate_t state; \ - /* Input queue.*/ \ - input_queue_t iqueue; \ - /* Output queue.*/ \ - output_queue_t oqueue; \ - /* Input circular buffer.*/ \ - uint8_t ib[SERIAL_BUFFERS_SIZE]; \ - /* Output circular buffer.*/ \ - uint8_t ob[SERIAL_BUFFERS_SIZE]; \ - /* End of the mandatory fields.*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if (PLATFORM_SERIAL_USE_USART1 == TRUE) && !defined(__DOXYGEN__) -extern SerialDriver SD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void sd_lld_init(void); - void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); - void sd_lld_stop(SerialDriver *sdp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_SERIAL == TRUE */ - -#endif /* _SERIAL_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/spi_lld.c b/firmware/ChibiOS_16/os/hal/templates/spi_lld.c deleted file mode 100644 index c396562b72..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/spi_lld.c +++ /dev/null @@ -1,247 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file spi_lld.c - * @brief PLATFORM SPI subsystem low level driver source. - * - * @addtogroup SPI - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_SPI == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief SPI1 driver identifier. - */ -#if (PLATFORM_SPI_USE_SPI1 == TRUE) || defined(__DOXYGEN__) -SPIDriver SPID1; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level SPI driver initialization. - * - * @notapi - */ -void spi_lld_init(void) { - -#if PLATFORM_SPI_USE_SPI1 == TRUE - /* Driver initialization.*/ - spiObjectInit(&SPID1); -#endif -} - -/** - * @brief Configures and activates the SPI peripheral. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_start(SPIDriver *spip) { - - if (spip->state == SPI_STOP) { - /* Enables the peripheral.*/ -#if PLATFORM_SPI_USE_SPI1 == TRUE - if (&SPID1 == spip) { - - } -#endif - } - /* Configures the peripheral.*/ - -} - -/** - * @brief Deactivates the SPI peripheral. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_stop(SPIDriver *spip) { - - if (spip->state == SPI_READY) { - /* Disables the peripheral.*/ -#if PLATFORM_SPI_USE_SPI1 == TRUE - if (&SPID1 == spip) { - - } -#endif - } -} - -/** - * @brief Asserts the slave select signal and prepares for transfers. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_select(SPIDriver *spip) { - - (void)spip; - -} - -/** - * @brief Deasserts the slave select signal. - * @details The previously selected peripheral is unselected. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_unselect(SPIDriver *spip) { - - (void)spip; - -} - -/** - * @brief Ignores data on the SPI bus. - * @details This asynchronous function starts the transmission of a series of - * idle words on the SPI bus and ignores the received data. - * @post At the end of the operation the configured callback is invoked. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be ignored - * - * @notapi - */ -void spi_lld_ignore(SPIDriver *spip, size_t n) { - - (void)spip; - (void)n; - -} - -/** - * @brief Exchanges data on the SPI bus. - * @details This asynchronous function starts a simultaneous transmit/receive - * operation. - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be exchanged - * @param[in] txbuf the pointer to the transmit buffer - * @param[out] rxbuf the pointer to the receive buffer - * - * @notapi - */ -void spi_lld_exchange(SPIDriver *spip, size_t n, - const void *txbuf, void *rxbuf) { - - (void)spip; - (void)n; - (void)txbuf; - (void)rxbuf; - -} - -/** - * @brief Sends data over the SPI bus. - * @details This asynchronous function starts a transmit operation. - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to send - * @param[in] txbuf the pointer to the transmit buffer - * - * @notapi - */ -void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { - - (void)spip; - (void)n; - (void)txbuf; - -} - -/** - * @brief Receives data from the SPI bus. - * @details This asynchronous function starts a receive operation. - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to receive - * @param[out] rxbuf the pointer to the receive buffer - * - * @notapi - */ -void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { - - (void)spip; - (void)n; - (void)rxbuf; - -} - -/** - * @brief Exchanges one frame using a polled wait. - * @details This synchronous function exchanges one frame using a polled - * synchronization method. This function is useful when exchanging - * small amount of data on high speed channels, usually in this - * situation is much more efficient just wait for completion using - * polling than suspending the thread waiting for an interrupt. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] frame the data frame to send over the SPI bus - * @return The received data frame from the SPI bus. - */ -uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) { - - (void)spip; - (void)frame; - - return 0; -} - -#endif /* HAL_USE_SPI == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/spi_lld.h b/firmware/ChibiOS_16/os/hal/templates/spi_lld.h deleted file mode 100644 index 425ac89253..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/spi_lld.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file spi_lld.h - * @brief PLATFORM SPI subsystem low level driver header. - * - * @addtogroup SPI - * @{ - */ - -#ifndef _SPI_LLD_H_ -#define _SPI_LLD_H_ - -#if (HAL_USE_SPI == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name PLATFORM configuration options - * @{ - */ -/** - * @brief SPI1 driver enable switch. - * @details If set to @p TRUE the support for SPI1 is included. - * @note The default is @p FALSE. - */ -#if !defined(PLATFORM_SPI_USE_SPI1) || defined(__DOXYGEN__) -#define PLATFORM_SPI_USE_SPI1 FALSE -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a structure representing an SPI driver. - */ -typedef struct SPIDriver SPIDriver; - -/** - * @brief SPI notification callback type. - * - * @param[in] spip pointer to the @p SPIDriver object triggering the - * callback - */ -typedef void (*spicallback_t)(SPIDriver *spip); - -/** - * @brief Driver configuration structure. - * @note Implementations may extend this structure to contain more, - * architecture dependent, fields. - */ -typedef struct { - /** - * @brief Operation complete callback or @p NULL. - */ - spicallback_t end_cb; - /* End of the mandatory fields.*/ -} SPIConfig; - -/** - * @brief Structure representing an SPI driver. - * @note Implementations may extend this structure to contain more, - * architecture dependent, fields. - */ -struct SPIDriver { - /** - * @brief Driver state. - */ - spistate_t state; - /** - * @brief Current configuration data. - */ - const SPIConfig *config; -#if (SPI_USE_WAIT == TRUE) || defined(__DOXYGEN__) - /** - * @brief Waiting thread. - */ - thread_reference_t thread; -#endif -#if (SPI_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the peripheral. - */ - mutex_t mutex; -#endif -#if defined(SPI_DRIVER_EXT_FIELDS) - SPI_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if (PLATFORM_SPI_USE_SPI1 == TRUE) && !defined(__DOXYGEN__) -extern SPIDriver SPID1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void spi_lld_init(void); - void spi_lld_start(SPIDriver *spip); - void spi_lld_stop(SPIDriver *spip); - void spi_lld_select(SPIDriver *spip); - void spi_lld_unselect(SPIDriver *spip); - void spi_lld_ignore(SPIDriver *spip, size_t n); - void spi_lld_exchange(SPIDriver *spip, size_t n, - const void *txbuf, void *rxbuf); - void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); - void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); - uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_SPI == TRUE */ - -#endif /* _SPI_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/st_lld.c b/firmware/ChibiOS_16/os/hal/templates/st_lld.c deleted file mode 100644 index a54712907a..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/st_lld.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file st_lld.c - * @brief PLATFORM ST subsystem low level driver source. - * - * @addtogroup ST - * @{ - */ - -#include "hal.h" - -#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level ST driver initialization. - * - * @notapi - */ -void st_lld_init(void) { -} - -#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/st_lld.h b/firmware/ChibiOS_16/os/hal/templates/st_lld.h deleted file mode 100644 index 94529e8889..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/st_lld.h +++ /dev/null @@ -1,141 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file st_lld.h - * @brief PLATFORM ST subsystem low level driver header. - * @details This header is designed to be include-able without having to - * include other files from the HAL. - * - * @addtogroup ST - * @{ - */ - -#ifndef _ST_LLD_H_ -#define _ST_LLD_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void st_lld_init(void); -#ifdef __cplusplus -} -#endif - -/*===========================================================================*/ -/* Driver inline functions. */ -/*===========================================================================*/ - -/** - * @brief Returns the time counter value. - * - * @return The counter value. - * - * @notapi - */ -static inline systime_t st_lld_get_counter(void) { - - return (systime_t)0; -} - -/** - * @brief Starts the alarm. - * @note Makes sure that no spurious alarms are triggered after - * this call. - * - * @param[in] abstime the time to be set for the first alarm - * - * @notapi - */ -static inline void st_lld_start_alarm(systime_t abstime) { - - (void)abstime; -} - -/** - * @brief Stops the alarm interrupt. - * - * @notapi - */ -static inline void st_lld_stop_alarm(void) { - -} - -/** - * @brief Sets the alarm time. - * - * @param[in] abstime the time to be set for the next alarm - * - * @notapi - */ -static inline void st_lld_set_alarm(systime_t abstime) { - - (void)abstime; -} - -/** - * @brief Returns the current alarm time. - * - * @return The currently set alarm time. - * - * @notapi - */ -static inline systime_t st_lld_get_alarm(void) { - - return (systime_t)0; -} - -/** - * @brief Determines if the alarm is active. - * - * @return The alarm status. - * @retval false if the alarm is not active. - * @retval true is the alarm is active - * - * @notapi - */ -static inline bool st_lld_is_alarm_active(void) { - - return false; -} - -#endif /* _ST_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/uart_lld.c b/firmware/ChibiOS_16/os/hal/templates/uart_lld.c deleted file mode 100644 index 7a2e895a50..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/uart_lld.c +++ /dev/null @@ -1,191 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file uart_lld.c - * @brief PLATFORM UART subsystem low level driver source. - * - * @addtogroup UART - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_UART == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief UART1 driver identifier. - */ -#if (PLATFORM_UART_USE_UART1 == TRUE) || defined(__DOXYGEN__) -UARTDriver UARTD1; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level UART driver initialization. - * - * @notapi - */ -void uart_lld_init(void) { - -#if PLATFORM_UART_USE_UART1 == TRUE - /* Driver initialization.*/ - uartObjectInit(&UARTD1); -#endif -} - -/** - * @brief Configures and activates the UART peripheral. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @notapi - */ -void uart_lld_start(UARTDriver *uartp) { - - if (uartp->state == UART_STOP) { - /* Enables the peripheral.*/ -#if PLATFORM_UART_USE_UART1 == TRUE - if (&UARTD1 == uartp) { - - } -#endif - } - /* Configures the peripheral.*/ - -} - -/** - * @brief Deactivates the UART peripheral. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @notapi - */ -void uart_lld_stop(UARTDriver *uartp) { - - if (uartp->state == UART_READY) { - /* Resets the peripheral.*/ - - /* Disables the peripheral.*/ -#if PLATFORM_UART_USE_UART1 == TRUE - if (&UARTD1 == uartp) { - - } -#endif - } -} - -/** - * @brief Starts a transmission on the UART peripheral. - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] n number of data frames to send - * @param[in] txbuf the pointer to the transmit buffer - * - * @notapi - */ -void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) { - - (void)uartp; - (void)n; - (void)txbuf; - -} - -/** - * @brief Stops any ongoing transmission. - * @note Stopping a transmission also suppresses the transmission callbacks. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @return The number of data frames not transmitted by the - * stopped transmit operation. - * - * @notapi - */ -size_t uart_lld_stop_send(UARTDriver *uartp) { - - (void)uartp; - - return 0; -} - -/** - * @brief Starts a receive operation on the UART peripheral. - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] n number of data frames to send - * @param[out] rxbuf the pointer to the receive buffer - * - * @notapi - */ -void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) { - - (void)uartp; - (void)n; - (void)rxbuf; - -} - -/** - * @brief Stops any ongoing receive operation. - * @note Stopping a receive operation also suppresses the receive callbacks. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @return The number of data frames not received by the - * stopped receive operation. - * - * @notapi - */ -size_t uart_lld_stop_receive(UARTDriver *uartp) { - - (void)uartp; - - return 0; -} - -#endif /* HAL_USE_UART == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/uart_lld.h b/firmware/ChibiOS_16/os/hal/templates/uart_lld.h deleted file mode 100644 index d334a68f91..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/uart_lld.h +++ /dev/null @@ -1,202 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file uart_lld.h - * @brief PLATFORM UART subsystem low level driver header. - * - * @addtogroup UART - * @{ - */ - -#ifndef _UART_LLD_H_ -#define _UART_LLD_H_ - -#if (HAL_USE_UART == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name PLATFORM configuration options - * @{ - */ -/** - * @brief UART driver enable switch. - * @details If set to @p TRUE the support for UART1 is included. - * @note The default is @p FALSE. - */ -#if !defined(PLATFORM_UART_USE_UART1) || defined(__DOXYGEN__) -#define PLATFORM_UART_USE_UART1 FALSE -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief UART driver condition flags type. - */ -typedef uint32_t uartflags_t; - -/** - * @brief Type of structure representing an UART driver. - */ -typedef struct UARTDriver UARTDriver; - -/** - * @brief Generic UART notification callback type. - * - * @param[in] uartp pointer to the @p UARTDriver object - */ -typedef void (*uartcb_t)(UARTDriver *uartp); - -/** - * @brief Character received UART notification callback type. - * - * @param[in] uartp pointer to the @p UARTDriver object triggering the - * callback - * @param[in] c received character - */ -typedef void (*uartccb_t)(UARTDriver *uartp, uint16_t c); - -/** - * @brief Receive error UART notification callback type. - * - * @param[in] uartp pointer to the @p UARTDriver object triggering the - * callback - * @param[in] e receive error mask - */ -typedef void (*uartecb_t)(UARTDriver *uartp, uartflags_t e); - -/** - * @brief Driver configuration structure. - * @note Implementations may extend this structure to contain more, - * architecture dependent, fields. - */ -typedef struct { - /** - * @brief End of transmission buffer callback. - */ - uartcb_t txend1_cb; - /** - * @brief Physical end of transmission callback. - */ - uartcb_t txend2_cb; - /** - * @brief Receive buffer filled callback. - */ - uartcb_t rxend_cb; - /** - * @brief Character received while out if the @p UART_RECEIVE state. - */ - uartccb_t rxchar_cb; - /** - * @brief Receive error callback. - */ - uartecb_t rxerr_cb; - /* End of the mandatory fields.*/ -} UARTConfig; - -/** - * @brief Structure representing an UART driver. - * @note Implementations may extend this structure to contain more, - * architecture dependent, fields. - */ -struct UARTDriver { - /** - * @brief Driver state. - */ - uartstate_t state; - /** - * @brief Transmitter state. - */ - uarttxstate_t txstate; - /** - * @brief Receiver state. - */ - uartrxstate_t rxstate; - /** - * @brief Current configuration data. - */ - const UARTConfig *config; -#if (UART_USE_WAIT == TRUE) || defined(__DOXYGEN__) - /** - * @brief Synchronization flag for transmit operations. - */ - bool early; - /** - * @brief Waiting thread on RX. - */ - thread_reference_t threadrx; - /** - * @brief Waiting thread on TX. - */ - thread_reference_t threadtx; -#endif /* UART_USE_WAIT */ -#if (UART_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the peripheral. - */ - mutex_t mutex; -#endif /* UART_USE_MUTUAL_EXCLUSION */ -#if defined(UART_DRIVER_EXT_FIELDS) - UART_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if (PLATFORM_UART_USE_UART1 == TRUE) && !defined(__DOXYGEN__) -extern UARTDriver UARTD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void uart_lld_init(void); - void uart_lld_start(UARTDriver *uartp); - void uart_lld_stop(UARTDriver *uartp); - void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf); - size_t uart_lld_stop_send(UARTDriver *uartp); - void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf); - size_t uart_lld_stop_receive(UARTDriver *uartp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_UART == TRUE */ - -#endif /* _UART_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/usb_lld.c b/firmware/ChibiOS_16/os/hal/templates/usb_lld.c deleted file mode 100644 index eda8b2546e..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/usb_lld.c +++ /dev/null @@ -1,390 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file usb_lld.c - * @brief PLATFORM USB subsystem low level driver source. - * - * @addtogroup USB - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_USB == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief USB1 driver identifier. - */ -#if (PLATFORM_USB_USE_USB1 == TRUE) || defined(__DOXYGEN__) -USBDriver USBD1; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief EP0 state. - * @note It is an union because IN and OUT endpoints are never used at the - * same time for EP0. - */ -static union { - /** - * @brief IN EP0 state. - */ - USBInEndpointState in; - /** - * @brief OUT EP0 state. - */ - USBOutEndpointState out; -} ep0_state; - -/** - * @brief EP0 initialization structure. - */ -static const USBEndpointConfig ep0config = { - USB_EP_MODE_TYPE_CTRL, - _usb_ep0setup, - _usb_ep0in, - _usb_ep0out, - 0x40, - 0x40, - &ep0_state.in, - &ep0_state.out -}; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers and threads. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level USB driver initialization. - * - * @notapi - */ -void usb_lld_init(void) { - -#if PLATFORM_USB_USE_USB1 == TRUE - /* Driver initialization.*/ - usbObjectInit(&USBD1); -#endif -} - -/** - * @brief Configures and activates the USB peripheral. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -void usb_lld_start(USBDriver *usbp) { - - if (usbp->state == USB_STOP) { - /* Enables the peripheral.*/ -#if PLATFORM_USB_USE_USB1 == TRUE - if (&USBD1 == usbp) { - - } -#endif - } - /* Configures the peripheral.*/ - -} - -/** - * @brief Deactivates the USB peripheral. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -void usb_lld_stop(USBDriver *usbp) { - - if (usbp->state == USB_READY) { - /* Resets the peripheral.*/ - - /* Disables the peripheral.*/ -#if PLATFORM_USB_USE_USB1 == TRUE - if (&USBD1 == usbp) { - - } -#endif - } -} - -/** - * @brief USB low level reset routine. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -void usb_lld_reset(USBDriver *usbp) { - - /* Post reset initialization.*/ - - /* EP0 initialization.*/ - usbp->epc[0] = &ep0config; - usb_lld_init_endpoint(usbp, 0); -} - -/** - * @brief Sets the USB address. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -void usb_lld_set_address(USBDriver *usbp) { - - (void)usbp; - -} - -/** - * @brief Enables an endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) { - - (void)usbp; - (void)ep; - -} - -/** - * @brief Disables all the active endpoints except the endpoint zero. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -void usb_lld_disable_endpoints(USBDriver *usbp) { - - (void)usbp; - -} - -/** - * @brief Returns the status of an OUT endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @return The endpoint status. - * @retval EP_STATUS_DISABLED The endpoint is not active. - * @retval EP_STATUS_STALLED The endpoint is stalled. - * @retval EP_STATUS_ACTIVE The endpoint is active. - * - * @notapi - */ -usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep) { - - (void)usbp; - (void)ep; - - return EP_STATUS_DISABLED; -} - -/** - * @brief Returns the status of an IN endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @return The endpoint status. - * @retval EP_STATUS_DISABLED The endpoint is not active. - * @retval EP_STATUS_STALLED The endpoint is stalled. - * @retval EP_STATUS_ACTIVE The endpoint is active. - * - * @notapi - */ -usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep) { - - (void)usbp; - (void)ep; - - return EP_STATUS_DISABLED; -} - -/** - * @brief Reads a setup packet from the dedicated packet buffer. - * @details This function must be invoked in the context of the @p setup_cb - * callback in order to read the received setup packet. - * @pre In order to use this function the endpoint must have been - * initialized as a control endpoint. - * @post The endpoint is ready to accept another packet. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @param[out] buf buffer where to copy the packet data - * - * @notapi - */ -void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) { - - (void)usbp; - (void)ep; - (void)buf; - -} - -/** - * @brief Prepares for a receive operation. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep) { - - (void)usbp; - (void)ep; - -} - -/** - * @brief Prepares for a transmit operation. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep) { - - (void)usbp; - (void)ep; - -} - -/** - * @brief Starts a receive operation on an OUT endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_start_out(USBDriver *usbp, usbep_t ep) { - - (void)usbp; - (void)ep; - -} - -/** - * @brief Starts a transmit operation on an IN endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_start_in(USBDriver *usbp, usbep_t ep) { - - (void)usbp; - (void)ep; - -} - -/** - * @brief Brings an OUT endpoint in the stalled state. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_stall_out(USBDriver *usbp, usbep_t ep) { - - (void)usbp; - (void)ep; - -} - -/** - * @brief Brings an IN endpoint in the stalled state. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_stall_in(USBDriver *usbp, usbep_t ep) { - - (void)usbp; - (void)ep; - -} - -/** - * @brief Brings an OUT endpoint in the active state. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_clear_out(USBDriver *usbp, usbep_t ep) { - - (void)usbp; - (void)ep; - -} - -/** - * @brief Brings an IN endpoint in the active state. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_clear_in(USBDriver *usbp, usbep_t ep) { - - (void)usbp; - (void)ep; - -} - -#endif /* HAL_USE_USB == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/usb_lld.h b/firmware/ChibiOS_16/os/hal/templates/usb_lld.h deleted file mode 100644 index 2d8091b8ac..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/usb_lld.h +++ /dev/null @@ -1,376 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file usb_lld.h - * @brief PLATFORM USB subsystem low level driver header. - * - * @addtogroup USB - * @{ - */ - -#ifndef _USB_LLD_H_ -#define _USB_LLD_H_ - -#if (HAL_USE_USB == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Maximum endpoint address. - */ -#define USB_MAX_ENDPOINTS 4 - -/** - * @brief Status stage handling method. - */ -#define USB_EP0_STATUS_STAGE USB_EP0_STATUS_STAGE_SW - -/** - * @brief The address can be changed immediately upon packet reception. - */ -#define USB_SET_ADDRESS_MODE USB_LATE_SET_ADDRESS - -/** - * @brief Method for set address acknowledge. - */ -#define USB_SET_ADDRESS_ACK_HANDLING USB_SET_ADDRESS_ACK_SW - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name PLATFORM configuration options - * @{ - */ -/** - * @brief USB driver enable switch. - * @details If set to @p TRUE the support for USB1 is included. - * @note The default is @p FALSE. - */ -#if !defined(PLATFORM_USB_USE_USB1) || defined(__DOXYGEN__) -#define PLATFORM_USB_USE_USB1 FALSE -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of an IN endpoint state structure. - */ -typedef struct { - /** - * @brief Requested transmit transfer size. - */ - size_t txsize; - /** - * @brief Transmitted bytes so far. - */ - size_t txcnt; - /** - * @brief Pointer to the transmission linear buffer. - */ - const uint8_t *txbuf; -#if (USB_USE_WAIT == TRUE) || defined(__DOXYGEN__) - /** - * @brief Waiting thread. - */ - thread_reference_t thread; -#endif - /* End of the mandatory fields.*/ -} USBInEndpointState; - -/** - * @brief Type of an OUT endpoint state structure. - */ -typedef struct { - /** - * @brief Requested receive transfer size. - */ - size_t rxsize; - /** - * @brief Received bytes so far. - */ - size_t rxcnt; - /** - * @brief Pointer to the receive linear buffer. - */ - uint8_t *rxbuf; -#if (USB_USE_WAIT == TRUE) || defined(__DOXYGEN__) - /** - * @brief Waiting thread. - */ - thread_reference_t thread; -#endif - /* End of the mandatory fields.*/ -} USBOutEndpointState; - -/** - * @brief Type of an USB endpoint configuration structure. - * @note Platform specific restrictions may apply to endpoints. - */ -typedef struct { - /** - * @brief Type and mode of the endpoint. - */ - uint32_t ep_mode; - /** - * @brief Setup packet notification callback. - * @details This callback is invoked when a setup packet has been - * received. - * @post The application must immediately call @p usbReadPacket() in - * order to access the received packet. - * @note This field is only valid for @p USB_EP_MODE_TYPE_CTRL - * endpoints, it should be set to @p NULL for other endpoint - * types. - */ - usbepcallback_t setup_cb; - /** - * @brief IN endpoint notification callback. - * @details This field must be set to @p NULL if the IN endpoint is not - * used. - */ - usbepcallback_t in_cb; - /** - * @brief OUT endpoint notification callback. - * @details This field must be set to @p NULL if the OUT endpoint is not - * used. - */ - usbepcallback_t out_cb; - /** - * @brief IN endpoint maximum packet size. - * @details This field must be set to zero if the IN endpoint is not - * used. - */ - uint16_t in_maxsize; - /** - * @brief OUT endpoint maximum packet size. - * @details This field must be set to zero if the OUT endpoint is not - * used. - */ - uint16_t out_maxsize; - /** - * @brief @p USBEndpointState associated to the IN endpoint. - * @details This structure maintains the state of the IN endpoint. - */ - USBInEndpointState *in_state; - /** - * @brief @p USBEndpointState associated to the OUT endpoint. - * @details This structure maintains the state of the OUT endpoint. - */ - USBOutEndpointState *out_state; - /* End of the mandatory fields.*/ -} USBEndpointConfig; - -/** - * @brief Type of an USB driver configuration structure. - */ -typedef struct { - /** - * @brief USB events callback. - * @details This callback is invoked when an USB driver event is registered. - */ - usbeventcb_t event_cb; - /** - * @brief Device GET_DESCRIPTOR request callback. - * @note This callback is mandatory and cannot be set to @p NULL. - */ - usbgetdescriptor_t get_descriptor_cb; - /** - * @brief Requests hook callback. - * @details This hook allows to be notified of standard requests or to - * handle non standard requests. - */ - usbreqhandler_t requests_hook_cb; - /** - * @brief Start Of Frame callback. - */ - usbcallback_t sof_cb; - /* End of the mandatory fields.*/ -} USBConfig; - -/** - * @brief Structure representing an USB driver. - */ -struct USBDriver { - /** - * @brief Driver state. - */ - usbstate_t state; - /** - * @brief Current configuration data. - */ - const USBConfig *config; - /** - * @brief Bit map of the transmitting IN endpoints. - */ - uint16_t transmitting; - /** - * @brief Bit map of the receiving OUT endpoints. - */ - uint16_t receiving; - /** - * @brief Active endpoints configurations. - */ - const USBEndpointConfig *epc[USB_MAX_ENDPOINTS + 1]; - /** - * @brief Fields available to user, it can be used to associate an - * application-defined handler to an IN endpoint. - * @note The base index is one, the endpoint zero does not have a - * reserved element in this array. - */ - void *in_params[USB_MAX_ENDPOINTS]; - /** - * @brief Fields available to user, it can be used to associate an - * application-defined handler to an OUT endpoint. - * @note The base index is one, the endpoint zero does not have a - * reserved element in this array. - */ - void *out_params[USB_MAX_ENDPOINTS]; - /** - * @brief Endpoint 0 state. - */ - usbep0state_t ep0state; - /** - * @brief Next position in the buffer to be transferred through endpoint 0. - */ - uint8_t *ep0next; - /** - * @brief Number of bytes yet to be transferred through endpoint 0. - */ - size_t ep0n; - /** - * @brief Endpoint 0 end transaction callback. - */ - usbcallback_t ep0endcb; - /** - * @brief Setup packet buffer. - */ - uint8_t setup[8]; - /** - * @brief Current USB device status. - */ - uint16_t status; - /** - * @brief Assigned USB address. - */ - uint8_t address; - /** - * @brief Current USB device configuration. - */ - uint8_t configuration; - /** - * @brief State of the driver when a suspend happened. - */ - usbstate_t saved_state; -#if defined(USB_DRIVER_EXT_FIELDS) - USB_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Returns the current frame number. - * - * @param[in] usbp pointer to the @p USBDriver object - * @return The current frame number. - * - * @notapi - */ -#define usb_lld_get_frame_number(usbp) 0 - -/** - * @brief Returns the exact size of a receive transaction. - * @details The received size can be different from the size specified in - * @p usbStartReceiveI() because the last packet could have a size - * different from the expected one. - * @pre The OUT endpoint must have been configured in transaction mode - * in order to use this function. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @return Received data size. - * - * @notapi - */ -#define usb_lld_get_transaction_size(usbp, ep) \ - ((usbp)->epc[ep]->out_state->rxcnt) - -/** - * @brief Connects the USB device. - * - * @api - */ -#define usb_lld_connect_bus(usbp) - -/** - * @brief Disconnect the USB device. - * - * @api - */ -#define usb_lld_disconnect_bus(usbp) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if (PLATFORM_USB_USE_USB1 == TRUE) && !defined(__DOXYGEN__) -extern USBDriver USBD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void usb_lld_init(void); - void usb_lld_start(USBDriver *usbp); - void usb_lld_stop(USBDriver *usbp); - void usb_lld_reset(USBDriver *usbp); - void usb_lld_set_address(USBDriver *usbp); - void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep); - void usb_lld_disable_endpoints(USBDriver *usbp); - usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep); - usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep); - void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf); - void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep); - void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep); - void usb_lld_start_out(USBDriver *usbp, usbep_t ep); - void usb_lld_start_in(USBDriver *usbp, usbep_t ep); - void usb_lld_stall_out(USBDriver *usbp, usbep_t ep); - void usb_lld_stall_in(USBDriver *usbp, usbep_t ep); - void usb_lld_clear_out(USBDriver *usbp, usbep_t ep); - void usb_lld_clear_in(USBDriver *usbp, usbep_t ep); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_USB == TRUE */ - -#endif /* _USB_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/wdg_lld.c b/firmware/ChibiOS_16/os/hal/templates/wdg_lld.c deleted file mode 100644 index 7e2e88aa12..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/wdg_lld.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file templates/wdg_lld.c - * @brief WDG Driver subsystem low level driver source template. - * - * @addtogroup WDG - * @{ - */ - -#include "hal.h" - -#if HAL_USE_WDG || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -#if STM32_WDG_USE_WDG1 || defined(__DOXYGEN__) -WDGDriver WDGD1; -#endif - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level WDG driver initialization. - * - * @notapi - */ -void wdg_lld_init(void) { - -} - -/** - * @brief Configures and activates the WDG peripheral. - * - * @param[in] wdgp pointer to the @p WDGDriver object - * - * @notapi - */ -void wdg_lld_start(WDGDriver *wdgp) { - -} - -/** - * @brief Deactivates the WDG peripheral. - * - * @param[in] wdgp pointer to the @p WDGDriver object - * - * @api - */ -void wdg_lld_stop(WDGDriver *wdgp) { - -} - -/** - * @brief Reloads WDG's counter. - * - * @param[in] wdgp pointer to the @p WDGDriver object - * - * @notapi - */ -void wdg_lld_reset(WDGDriver * wdgp) { - -} - -#endif /* HAL_USE_WDG */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/hal/templates/wdg_lld.h b/firmware/ChibiOS_16/os/hal/templates/wdg_lld.h deleted file mode 100644 index 0ba5748105..0000000000 --- a/firmware/ChibiOS_16/os/hal/templates/wdg_lld.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file templates/wdg_lld.h - * @brief WDG Driver subsystem low level driver header template. - * - * @addtogroup WDG - * @{ - */ - -#ifndef _WDG_LLD_H_ -#define _WDG_LLD_H_ - -#if (HAL_USE_WDG == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief WDG1 driver enable switch. - * @note The default is @p FALSE. - */ -#if !defined(PLATFORM_WDG_USE_WDG1) || defined(__DOXYGEN__) -#define PLATFORM_WDG_USE_WDG1 FALSE -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a structure representing an WDG driver. - */ -typedef struct WDGDriver WDGDriver; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { -} WDGConfig; - -/** - * @brief Structure representing an WDG driver. - */ -struct WDGDriver { - /** - * @brief Driver state. - */ - wdgstate_t state; - /** - * @brief Current configuration data. - */ - const WDGConfig *config; - /* End of the mandatory fields.*/ -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if (PLATFORM_WDG_USE_WDG1 == TRUE) && !defined(__DOXYGEN__) -extern WDGDriver WDGD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void wdg_lld_init(void); - void wdg_lld_start(WDGDriver *wdgp); - void wdg_lld_stop(WDGDriver *wdgp); - void wdg_lld_reset(WDGDriver *wdgp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_WDG == TRUE */ - -#endif /* _WDG_LLD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/nil/dox/nil.dox b/firmware/ChibiOS_16/os/nil/dox/nil.dox deleted file mode 100644 index 77f8a99fc3..0000000000 --- a/firmware/ChibiOS_16/os/nil/dox/nil.dox +++ /dev/null @@ -1,50 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @defgroup NIL NIL Kernel - * @details The kernel is the portable part of ChibiOS/NIL, this section - * documents the various kernel subsystems. - */ - -/** - * @defgroup NIL_CONFIG Configuration - * @ingroup NIL - */ - -/** - * @defgroup NIL_TYPES Kernel Types - * @ingroup NIL - */ - -/** - * @defgroup NIL_KERNEL API - * @ingroup NIL - */ - -/** - * @defgroup NIL_CORE Port Layer - * @ingroup NIL - */ - -/** - * @defgroup NIL_TIMER Timer Interface - * @ingroup NIL - */ - diff --git a/firmware/ChibiOS_16/os/nil/include/nil.h b/firmware/ChibiOS_16/os/nil/include/nil.h deleted file mode 100644 index c40db2d9cb..0000000000 --- a/firmware/ChibiOS_16/os/nil/include/nil.h +++ /dev/null @@ -1,1003 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file nil.h - * @brief Nil RTOS main header file. - * @details This header includes all the required kernel headers so it is the - * only header you usually need to include in your application. - * - * @addtogroup NIL_KERNEL - * @{ - */ - -#ifndef _NIL_H_ -#define _NIL_H_ - -/** - * @brief Type of a structure representing a thread. - * @note It is required as an early definition. - */ -typedef struct nil_thread thread_t; - -#include "nilconf.h" -#include "niltypes.h" -#include "nilcore.h" - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @brief ChibiOS/NIL identification macro. - */ -#define _CHIBIOS_NIL_ - -/** - * @brief Stable release flag. - */ -#define CH_KERNEL_STABLE 1 - -/** - * @name ChibiOS/NIL version identification - * @{ - */ -/** - * @brief Kernel version string. - */ -#define CH_KERNEL_VERSION "1.1.3" - -/** - * @brief Kernel version major number. - */ -#define CH_KERNEL_MAJOR 1 - -/** - * @brief Kernel version minor number. - */ -#define CH_KERNEL_MINOR 1 - -/** - * @brief Kernel version patch number. - */ -#define CH_KERNEL_PATCH 3 -/** @} */ - -/** - * @name Wakeup messages - * @{ - */ -#define MSG_OK (msg_t)0 /**< @brief OK wakeup message. */ -#define MSG_TIMEOUT (msg_t)-1 /**< @brief Wake-up caused by - a timeout condition. */ -#define MSG_RESET (msg_t)-2 /**< @brief Wake-up caused by - a reset condition. */ -/** @} */ - -/** - * @name Special time constants - * @{ - */ -/** - * @brief Zero time specification for some functions with a timeout - * specification. - * @note Not all functions accept @p TIME_IMMEDIATE as timeout parameter, - * see the specific function documentation. - */ -#define TIME_IMMEDIATE ((systime_t)-1) - -/** - * @brief Infinite time specification for all functions with a timeout - * specification. - */ -#define TIME_INFINITE ((systime_t)0) -/** @} */ - -/** - * @name Thread state related macros - * @{ - */ -#define NIL_STATE_READY (tstate_t)0 /**< @brief Thread ready or - executing. */ -#define NIL_STATE_SLEEPING (tstate_t)1 /**< @brief Thread sleeping. */ -#define NIL_STATE_SUSP (tstate_t)2 /**< @brief Thread suspended. */ -#define NIL_STATE_WTSEM (tstate_t)3 /**< @brief On semaphore. */ -#define NIL_STATE_WTOREVT (tstate_t)4 /**< @brief Waiting for events. */ -#define NIL_THD_IS_READY(tr) ((tr)->state == NIL_STATE_READY) -#define NIL_THD_IS_SLEEPING(tr) ((tr)->state == NIL_STATE_SLEEPING) -#define NIL_THD_IS_SUSP(tr) ((tr)->state == NIL_STATE_SUSP) -#define NIL_THD_IS_WTSEM(tr) ((tr)->state == NIL_STATE_WTSEM) -#define NIL_THD_IS_WTOREVT(tr) ((tr)->state == NIL_STATE_WTOREVT) -/** @} */ - -/** - * @name Events related macros - * @{ - */ -/** - * @brief All events allowed mask. - */ -#define ALL_EVENTS ((eventmask_t)-1) - -/** - * @brief Returns an event mask from an event identifier. - */ -#define EVENT_MASK(eid) ((eventmask_t)(1 << (eid))) -/** @} */ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Number of user threads in the application. - * @note This number is not inclusive of the idle thread which is - * implicitly handled. - */ -#if !defined(NIL_CFG_NUM_THREADS) || defined(__DOXYGEN__) -#define NIL_CFG_NUM_THREADS 2 -#endif - -/** - * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(NIL_CFG_ST_RESOLUTION) || defined(__DOXYGEN__) -#define NIL_CFG_ST_RESOLUTION 32 -#endif - -/** - * @brief System tick frequency. - * @note This value together with the @p NIL_CFG_ST_RESOLUTION - * option defines the maximum amount of time allowed for - * timeouts. - */ -#if !defined(NIL_CFG_ST_FREQUENCY) || defined(__DOXYGEN__) -#define NIL_CFG_ST_FREQUENCY 100 -#endif - -/** - * @brief Time delta constant for the tick-less mode. - * @note If this value is zero then the system uses the classic - * periodic tick. This value represents the minimum number - * of ticks that is safe to specify in a timeout directive. - * The value one is not valid, timeouts are rounded up to - * this value. - */ -#if !defined(NIL_CFG_ST_TIMEDELTA) || defined(__DOXYGEN__) -#define NIL_CFG_ST_TIMEDELTA 0 -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(NIL_CFG_USE_EVENTS) || defined(__DOXYGEN__) -#define NIL_CFG_USE_EVENTS TRUE -#endif - -/** - * @brief System assertions. - */ -#if !defined(NIL_CFG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define NIL_CFG_ENABLE_ASSERTS FALSE -#endif - -/** - * @brief Stack check. - */ -#if !defined(NIL_CFG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define NIL_CFG_ENABLE_STACK_CHECK FALSE -#endif - -/** - * @brief System initialization hook. - */ -#if !defined(NIL_CFG_SYSTEM_INIT_HOOK) || defined(__DOXYGEN__) -#define NIL_CFG_SYSTEM_INIT_HOOK() {} -#endif - -/** - * @brief Threads descriptor structure extension. - * @details User fields added to the end of the @p thread_t structure. - */ -#if !defined(NIL_CFG_THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define NIL_CFG_THREAD_EXT_FIELDS -#endif - -/** - * @brief Threads initialization hook. - */ -#if !defined(NIL_CFG_THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) -#define NIL_CFG_THREAD_EXT_INIT_HOOK(tr) {} -#endif - -/** - * @brief Idle thread enter hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to activate a power saving mode. - */ -#if !defined(NIL_CFG_IDLE_ENTER_HOOK) || defined(__DOXYGEN__) -#define NIL_CFG_IDLE_ENTER_HOOK() {} -#endif - -/** - * @brief Idle thread leave hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to deactivate a power saving mode. - */ -#if !defined(NIL_CFG_IDLE_LEAVE_HOOK) || defined(__DOXYGEN__) -#define NIL_CFG_IDLE_LEAVE_HOOK() {} -#endif - -/** - * @brief System halt hook. - */ -#if !defined(NIL_CFG_SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) -#define NIL_CFG_SYSTEM_HALT_HOOK(reason) {} -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if NIL_CFG_NUM_THREADS < 1 -#error "at least one thread must be defined" -#endif - -#if NIL_CFG_NUM_THREADS > 12 -#error "Nil is not recommended for thread-intensive applications, consider" \ - "ChibiOS/RT instead" -#endif - -#if (NIL_CFG_ST_RESOLUTION != 16) && (NIL_CFG_ST_RESOLUTION != 32) -#error "invalid NIL_CFG_ST_RESOLUTION specified, must be 16 or 32" -#endif - -#if NIL_CFG_ST_FREQUENCY <= 0 -#error "invalid NIL_CFG_ST_FREQUENCY specified, must be greated than zero" -#endif - -#if (NIL_CFG_ST_TIMEDELTA < 0) || (NIL_CFG_ST_TIMEDELTA == 1) -#error "invalid NIL_CFG_ST_TIMEDELTA specified, must " \ - "be zero or greater than one" -#endif - -#if (NIL_CFG_ENABLE_ASSERTS == TRUE) || (NIL_CFG_ENABLE_STACK_CHECK == TRUE) -#define NIL_DBG_ENABLED TRUE -#else -#define NIL_DBG_ENABLED FALSE -#endif - -/** Boundaries of the idle thread boundaries, only required if stack checking - is enabled.*/ -#if (NIL_CFG_ENABLE_STACK_CHECK == TRUE) || defined(__DOXYGEN__) -extern stkalign_t __main_thread_stack_base__, __main_thread_stack_end__; - -#define THD_IDLE_BASE (&__main_thread_stack_base__) -#define THD_IDLE_END (&__main_thread_stack_end__) -#else -#define THD_IDLE_BASE NULL -#define THD_IDLE_END NULL -#endif - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of internal context structure. - */ -typedef struct port_intctx intctx_t; - -/** - * @brief Type of a structure representing a semaphore. - */ -typedef struct nil_semaphore semaphore_t; - -/** - * @brief Structure representing a counting semaphore. - */ -struct nil_semaphore { - volatile cnt_t cnt; /**< @brief Semaphore counter. */ -}; - -/** - * @brief Thread function. - */ -typedef void (*tfunc_t)(void *p); - -/** - * @brief Type of a structure representing a thread static configuration. - */ -typedef struct nil_thread_cfg thread_config_t; - -/** - * @brief Structure representing a thread static configuration. - */ -struct nil_thread_cfg { - stkalign_t *wbase; /**< @brief Thread working area base. */ - stkalign_t *wend; /**< @brief Thread working area end. */ - const char *namep; /**< @brief Thread name, for debugging. */ - tfunc_t funcp; /**< @brief Thread function. */ - void *arg; /**< @brief Thread function argument. */ -}; - -/** - * @brief Type of a thread reference. - */ -typedef thread_t * thread_reference_t; - -/** - * @brief Structure representing a thread. - */ -struct nil_thread { - intctx_t *ctxp; /**< @brief Pointer to internal context. */ - tstate_t state; /**< @brief Thread state. */ - /* Note, the following union contains a pointer while the thread is in a - sleeping state (!NIL_THD_IS_READY()) else contains the wake-up message.*/ - union { - msg_t msg; /**< @brief Wake-up message. */ - void *p; /**< @brief Generic pointer. */ - thread_reference_t *trp; /**< @brief Pointer to thread reference. */ - semaphore_t *semp; /**< @brief Pointer to semaphore. */ -#if (NIL_CFG_USE_EVENTS == TRUE) || defined(__DOXYGEN__) - eventmask_t ewmask; /**< @brief Enabled events mask. */ -#endif - } u1; - volatile systime_t timeout;/**< @brief Timeout counter, zero - if disabled. */ -#if (NIL_CFG_USE_EVENTS == TRUE) || defined(__DOXYGEN__) - eventmask_t epmask; /**< @brief Pending events mask. */ -#endif -#if (NIL_CFG_ENABLE_STACK_CHECK == TRUE) || defined(__DOXYGEN__) - stkalign_t *stklim;/**< @brief Thread stack boundary. */ -#endif - /* Optional extra fields.*/ - NIL_CFG_THREAD_EXT_FIELDS -}; - -/** - * @brief Type of a structure representing the system. - */ -typedef struct nil_system nil_system_t; - -/** - * @brief System data structure. - * @note This structure contain all the data areas used by the OS except - * stacks. - */ -struct nil_system { - /** - * @brief Pointer to the running thread. - */ - thread_t *current; - /** - * @brief Pointer to the next thread to be executed. - * @note This pointer must point at the same thread pointed by @p current - * or to an higher priority thread if a switch is required. - */ - thread_t *next; -#if (NIL_CFG_ST_TIMEDELTA == 0) || defined(__DOXYGEN__) - /** - * @brief System time. - */ - volatile systime_t systime; -#endif -#if (NIL_CFG_ST_TIMEDELTA > 0) || defined(__DOXYGEN__) - /** - * @brief System time of the last tick event. - */ - systime_t lasttime; - /** - * @brief Time of the next scheduled tick event. - */ - systime_t nexttime; -#endif - /** - * @brief Thread structures for all the defined threads. - */ - thread_t threads[NIL_CFG_NUM_THREADS + 1]; -#if (NIL_DBG_ENABLED == TRUE) || defined(__DOXYGEN__) - /** - * @brief Panic message. - * @note This field is only present if some debug options have been - * activated. - * @note Accesses to this pointer must never be optimized out so the - * field itself is declared volatile. - */ - const char * volatile dbg_panic_msg; -#endif -}; - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @name Threads tables definition macros - * @{ - */ -/** - * @brief Start of user threads table. - */ -#define THD_TABLE_BEGIN \ - const thread_config_t nil_thd_configs[NIL_CFG_NUM_THREADS + 1] = { - -/** - * @brief Entry of user threads table - */ -#define THD_TABLE_ENTRY(wap, name, funcp, arg) \ - {wap, ((stkalign_t *)(wap)) + (sizeof (wap) / sizeof(stkalign_t)), \ - name, funcp, arg}, - -/** - * @brief End of user threads table. - */ -#define THD_TABLE_END \ - {THD_IDLE_BASE, THD_IDLE_END, "idle", NULL, NULL} \ -}; -/** @} */ - -/** - * @name Working Areas and Alignment - */ -/** - * @brief Enforces a correct alignment for a stack area size value. - * - * @param[in] n the stack size to be aligned to the next stack - * alignment boundary - * @return The aligned stack size. - * - * @api - */ -#define THD_ALIGN_STACK_SIZE(n) \ - ((((n) - 1U) | (sizeof(stkalign_t) - 1U)) + 1U) - -/** - * @brief Calculates the total Working Area size. - * - * @param[in] n the stack size to be assigned to the thread - * @return The total used memory in bytes. - * - * @api - */ -#define THD_WORKING_AREA_SIZE(n) \ - THD_ALIGN_STACK_SIZE(PORT_WA_SIZE(n)) - -/** - * @brief Static working area allocation. - * @details This macro is used to allocate a static thread working area - * aligned as both position and size. - * - * @param[in] s the name to be assigned to the stack array - * @param[in] n the stack size to be assigned to the thread - * - * @api - */ -#define THD_WORKING_AREA(s, n) \ - stkalign_t s[THD_WORKING_AREA_SIZE(n) / sizeof(stkalign_t)] -/** @} */ - -/** - * @name Threads abstraction macros - */ -/** - * @brief Thread declaration macro. - * @note Thread declarations should be performed using this macro because - * the port layer could define optimizations for thread functions. - */ -#define THD_FUNCTION(tname, arg) PORT_THD_FUNCTION(tname, arg) -/** @} */ - -/** - * @name ISRs abstraction macros - */ -/** - * @brief Priority level validation macro. - * @details This macro determines if the passed value is a valid priority - * level for the underlying architecture. - * - * @param[in] prio the priority level - * @return Priority range result. - * @retval false if the priority is invalid or if the architecture - * does not support priorities. - * @retval true if the priority is valid. - */ -#if defined(PORT_IRQ_IS_VALID_PRIORITY) || defined(__DOXYGEN__) -#define CH_IRQ_IS_VALID_PRIORITY(prio) \ - PORT_IRQ_IS_VALID_PRIORITY(prio) -#else -#define CH_IRQ_IS_VALID_PRIORITY(prio) false -#endif - -/** - * @brief Priority level validation macro. - * @details This macro determines if the passed value is a valid priority - * level that cannot preempt the kernel critical zone. - * - * @param[in] prio the priority level - * @return Priority range result. - * @retval false if the priority is invalid or if the architecture - * does not support priorities. - * @retval true if the priority is valid. - */ -#if defined(PORT_IRQ_IS_VALID_KERNEL_PRIORITY) || defined(__DOXYGEN__) -#define CH_IRQ_IS_VALID_KERNEL_PRIORITY(prio) \ - PORT_IRQ_IS_VALID_KERNEL_PRIORITY(prio) -#else -#define CH_IRQ_IS_VALID_KERNEL_PRIORITY(prio) false -#endif - -/** - * @brief IRQ handler enter code. - * @note Usually IRQ handlers functions are also declared naked. - * @note On some architectures this macro can be empty. - * - * @special - */ -#define CH_IRQ_PROLOGUE() PORT_IRQ_PROLOGUE() - -/** - * @brief IRQ handler exit code. - * @note Usually IRQ handlers function are also declared naked. - * - * @special - */ -#define CH_IRQ_EPILOGUE() PORT_IRQ_EPILOGUE() - -/** - * @brief Standard normal IRQ handler declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - * - * @special - */ -#define CH_IRQ_HANDLER(id) PORT_IRQ_HANDLER(id) -/** @} */ - -/** - * @name Fast ISRs abstraction macros - */ -/** - * @brief Standard fast IRQ handler declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - * @note Not all architectures support fast interrupts. - * - * @special - */ -#define CH_FAST_IRQ_HANDLER(id) PORT_FAST_IRQ_HANDLER(id) -/** @} */ - -/** - * @name Time conversion utilities - * @{ - */ -/** - * @brief Seconds to system ticks. - * @details Converts from seconds to system ticks number. - * @note The result is rounded upward to the next tick boundary. - * - * @param[in] sec number of seconds - * @return The number of ticks. - * - * @api - */ -#define S2ST(sec) \ - ((systime_t)((uint32_t)(sec) * (uint32_t)NIL_CFG_ST_FREQUENCY)) - -/** - * @brief Milliseconds to system ticks. - * @details Converts from milliseconds to system ticks number. - * @note The result is rounded upward to the next tick boundary. - * - * @param[in] msec number of milliseconds - * @return The number of ticks. - * - * @api - */ -#define MS2ST(msec) \ - ((systime_t)(((((uint32_t)(msec)) * \ - ((uint32_t)NIL_CFG_ST_FREQUENCY)) + 999UL) / 1000UL)) - -/** - * @brief Microseconds to system ticks. - * @details Converts from microseconds to system ticks number. - * @note The result is rounded upward to the next tick boundary. - * - * @param[in] usec number of microseconds - * @return The number of ticks. - * - * @api - */ -#define US2ST(usec) \ - ((systime_t)(((((uint32_t)(usec)) * \ - ((uint32_t)NIL_CFG_ST_FREQUENCY)) + 999999UL) / 1000000UL)) -/** @} */ - -/** - * @name Time conversion utilities for the realtime counter - * @{ - */ -/** - * @brief Seconds to realtime counter. - * @details Converts from seconds to realtime counter cycles. - * @note The macro assumes that @p freq >= @p 1. - * - * @param[in] freq clock frequency, in Hz, of the realtime counter - * @param[in] sec number of seconds - * @return The number of cycles. - * - * @api - */ -#define S2RTC(freq, sec) ((freq) * (sec)) - -/** - * @brief Milliseconds to realtime counter. - * @details Converts from milliseconds to realtime counter cycles. - * @note The result is rounded upward to the next millisecond boundary. - * @note The macro assumes that @p freq >= @p 1000. - * - * @param[in] freq clock frequency, in Hz, of the realtime counter - * @param[in] msec number of milliseconds - * @return The number of cycles. - * - * @api - */ -#define MS2RTC(freq, msec) (rtcnt_t)((((freq) + 999UL) / 1000UL) * (msec)) - -/** - * @brief Microseconds to realtime counter. - * @details Converts from microseconds to realtime counter cycles. - * @note The result is rounded upward to the next microsecond boundary. - * @note The macro assumes that @p freq >= @p 1000000. - * - * @param[in] freq clock frequency, in Hz, of the realtime counter - * @param[in] usec number of microseconds - * @return The number of cycles. - * - * @api - */ -#define US2RTC(freq, usec) (rtcnt_t)((((freq) + 999999UL) / 1000000UL) * (usec)) -/** @} */ - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Returns the current value of the system real time counter. - * @note This function is only available if the port layer supports the - * option @p PORT_SUPPORTS_RT. - * - * @return The value of the system realtime counter of - * type rtcnt_t. - * - * @xclass - */ -#if (PORT_SUPPORTS_RT == TRUE) || defined(__DOXYGEN__) -#define chSysGetRealtimeCounterX() (rtcnt_t)port_rt_get_counter_value() -#endif - -/** - * @brief Enters the kernel lock mode. - * - * @special - */ -#define chSysDisable() port_disable() - -/** - * @brief Enters the kernel lock mode. - * - * @special - */ -#define chSysEnable() port_enable() - -/** - * @brief Enters the kernel lock state. - * - * @special - */ -#define chSysLock() port_lock() - -/** - * @brief Leaves the kernel lock state. - * - * @special - */ -#define chSysUnlock() port_unlock() - -/** - * @brief Enters the kernel lock state from within an interrupt handler. - * @note This API may do nothing on some architectures, it is required - * because on ports that support preemptable interrupt handlers - * it is required to raise the interrupt mask to the same level of - * the system mutual exclusion zone.
- * It is good practice to invoke this API before invoking any I-class - * syscall from an interrupt handler. - * @note This API must be invoked exclusively from interrupt handlers. - * - * @special - */ -#define chSysLockFromISR() port_lock_from_isr() - -/** - * @brief Leaves the kernel lock state from within an interrupt handler. - * - * @note This API may do nothing on some architectures, it is required - * because on ports that support preemptable interrupt handlers - * it is required to raise the interrupt mask to the same level of - * the system mutual exclusion zone.
- * It is good practice to invoke this API after invoking any I-class - * syscall from an interrupt handler. - * @note This API must be invoked exclusively from interrupt handlers. - * - * @special - */ -#define chSysUnlockFromISR() port_unlock_from_isr() - -/** - * @brief Evaluates if a reschedule is required. - * - * @retval true if there is a thread that must go in running state - * immediately. - * @retval false if preemption is not required. - * - * @iclass - */ -#define chSchIsRescRequiredI() ((bool)(nil.current != nil.next)) - -/** - * @brief Returns a pointer to the current @p thread_t. - * - * @xclass - */ -#define chThdGetSelfX() nil.current - -/** - * @brief Delays the invoking thread for the specified number of seconds. - * @note The specified time is rounded up to a value allowed by the real - * system clock. - * @note The maximum specified value is implementation dependent. - * - * @param[in] sec time in seconds, must be different from zero - * - * @api - */ -#define chThdSleepSeconds(sec) chThdSleep(S2ST(sec)) - -/** - * @brief Delays the invoking thread for the specified number of - * milliseconds. - * @note The specified time is rounded up to a value allowed by the real - * system clock. - * @note The maximum specified value is implementation dependent. - * - * @param[in] msec time in milliseconds, must be different from zero - * - * @api - */ -#define chThdSleepMilliseconds(msec) chThdSleep(MS2ST(msec)) - -/** - * @brief Delays the invoking thread for the specified number of - * microseconds. - * @note The specified time is rounded up to a value allowed by the real - * system clock. - * @note The maximum specified value is implementation dependent. - * - * @param[in] usec time in microseconds, must be different from zero - * - * @api - */ -#define chThdSleepMicroseconds(usec) chThdSleep(US2ST(usec)) - -/** - * @brief Suspends the invoking thread for the specified time. - * - * @param[in] timeout the delay in system ticks - * - * @sclass - */ -#define chThdSleepS(timeout) (void) chSchGoSleepTimeoutS(NIL_STATE_SLEEPING, timeout) - -/** - * @brief Suspends the invoking thread until the system time arrives to the - * specified value. - * - * @param[in] abstime absolute system time - * - * @sclass - */ -#define chThdSleepUntilS(abstime) \ - (void) chSchGoSleepTimeoutS(NIL_STATE_SLEEPING, (abstime) - \ - chVTGetSystemTimeX()) - -/** - * @brief Initializes a semaphore with the specified counter value. - * - * @param[out] sp pointer to a @p semaphore_t structure - * @param[in] n initial value of the semaphore counter. Must be - * non-negative. - * - * @init - */ -#define chSemObjectInit(sp, n) ((sp)->cnt = n) - -/** - * @brief Performs a wait operation on a semaphore. - * - * @param[in] sp pointer to a @p semaphore_t structure - * @return A message specifying how the invoking thread has been - * released from the semaphore. - * @retval CH_MSG_OK if the thread has not stopped on the semaphore or the - * semaphore has been signaled. - * @retval CH_MSG_RST if the semaphore has been reset using @p chSemReset(). - * - * @api - */ -#define chSemWait(sp) chSemWaitTimeout(sp, TIME_INFINITE) - -/** - * @brief Performs a wait operation on a semaphore. - * - * @param[in] sp pointer to a @p semaphore_t structure - * @return A message specifying how the invoking thread has been - * released from the semaphore. - * @retval CH_MSG_OK if the thread has not stopped on the semaphore or the - * semaphore has been signaled. - * @retval CH_MSG_RST if the semaphore has been reset using @p chSemReset(). - * - * @sclass - */ -#define chSemWaitS(sp) chSemWaitTimeoutS(sp, TIME_INFINITE) - -/** - * @brief Returns the semaphore counter current value. - * - * @iclass - */ -#define chSemGetCounterI(sp) ((sp)->cnt) - -/** - * @brief Current system time. - * @details Returns the number of system ticks since the @p chSysInit() - * invocation. - * @note The counter can reach its maximum and then restart from zero. - * @note This function can be called from any context but its atomicity - * is not guaranteed on architectures whose word size is less than - * @p systime_t size. - * - * @return The system time in ticks. - * - * @xclass - */ -#if (NIL_CFG_ST_TIMEDELTA == 0) || defined(__DOXYGEN__) -#define chVTGetSystemTimeX() (nil.systime) -#else -#define chVTGetSystemTimeX() port_timer_get_time() -#endif - -/** - * @brief Returns the elapsed time since the specified start time. - * - * @param[in] start start time - * @return The elapsed time. - * - * @xclass - */ -#define chVTTimeElapsedSinceX(start) \ - ((systime_t)(chVTGetSystemTimeX() - (start))) - -/** - * @brief Checks if the specified time is within the specified time window. - * @note When start==end then the function returns always true because the - * whole time range is specified. - * @note This function can be called from any context. - * - * @param[in] time the time to be verified - * @param[in] start the start of the time window (inclusive) - * @param[in] end the end of the time window (non inclusive) - * @retval true current time within the specified time window. - * @retval false current time not within the specified time window. - * - * @xclass - */ -#define chVTIsTimeWithinX(time, start, end) \ - ((bool)((systime_t)((time) - (start)) < (systime_t)((end) - (start)))) - -/** - * @brief Condition assertion. - * @details If the condition check fails then the kernel panics with a - * message and halts. - * @note The condition is tested only if the @p NIL_CFG_ENABLE_ASSERTS - * switch is specified in @p nilconf.h else the macro does nothing. - * @note The remark string is not currently used except for putting a - * comment in the code about the assertion. - * - * @param[in] c the condition to be verified to be true - * @param[in] r a remark string - * - * @api - */ -#if !defined(chDbgAssert) -#define chDbgAssert(c, r) do { \ - /*lint -save -e506 -e774 [2.1, 14.3] Can be a constant by design.*/ \ - if (NIL_CFG_ENABLE_ASSERTS != FALSE) { \ - if (!(c)) { \ - /*lint -restore*/ \ - chSysHalt(__func__); \ - } \ - } \ -} while (false) -#endif /* !defined(chDbgAssert) */ -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -extern nil_system_t nil; -extern const thread_config_t nil_thd_configs[NIL_CFG_NUM_THREADS + 1]; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void chSysInit(void); - void chSysHalt(const char *reason); - void chSysTimerHandlerI(void); - void chSysUnconditionalLock(void); - void chSysUnconditionalUnlock(void); - syssts_t chSysGetStatusAndLockX(void); - bool chSysIsCounterWithinX(rtcnt_t cnt, rtcnt_t start, rtcnt_t end); - void chSysPolledDelayX(rtcnt_t cycles); - void chSysRestoreStatusX(syssts_t sts); - thread_t *chSchReadyI(thread_t *tp, msg_t msg); - void chSchRescheduleS(void); - msg_t chSchGoSleepTimeoutS(tstate_t newstate, systime_t timeout); - msg_t chThdSuspendTimeoutS(thread_reference_t *trp, systime_t timeout); - void chThdResumeI(thread_reference_t *trp, msg_t msg); - void chThdSleep(systime_t timeout); - void chThdSleepUntil(systime_t abstime); - msg_t chSemWaitTimeout(semaphore_t *sp, systime_t timeout); - msg_t chSemWaitTimeoutS(semaphore_t *sp, systime_t timeout); - void chSemSignal(semaphore_t *sp); - void chSemSignalI(semaphore_t *sp); - void chSemReset(semaphore_t *sp, cnt_t n); - void chSemResetI(semaphore_t *sp, cnt_t n); -#if NIL_CFG_USE_EVENTS == TRUE - void chEvtSignal(thread_t *tp, eventmask_t mask); - void chEvtSignalI(thread_t *tp, eventmask_t mask); - eventmask_t chEvtWaitAnyTimeout(eventmask_t mask, systime_t timeout); - eventmask_t chEvtWaitAnyTimeoutS(eventmask_t mask, systime_t timeout); -#endif -#ifdef __cplusplus -} -#endif - -#endif /* _NIL_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/nil/nil.mk b/firmware/ChibiOS_16/os/nil/nil.mk deleted file mode 100644 index 17ee6a06ff..0000000000 --- a/firmware/ChibiOS_16/os/nil/nil.mk +++ /dev/null @@ -1,5 +0,0 @@ -# List of all the ChibiOS/NIL kernel files. -KERNSRC = ${CHIBIOS}/os/nil/src/nil.c - -# Required include directories -KERNINC = ${CHIBIOS}/os/nil/include diff --git a/firmware/ChibiOS_16/os/nil/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk b/firmware/ChibiOS_16/os/nil/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk deleted file mode 100644 index f890d1899a..0000000000 --- a/firmware/ChibiOS_16/os/nil/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk +++ /dev/null @@ -1,8 +0,0 @@ -# List of the ChibiOS/NIL ARMv6M generic port files. -PORTSRC = $(CHIBIOS)/os/nil/ports/ARMCMx/nilcore.c \ - $(CHIBIOS)/os/nil/ports/ARMCMx/nilcore_v6m.c - -PORTASM = $(CHIBIOS)/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v6m.s - -PORTINC = $(CHIBIOS)/os/nil/ports/ARMCMx \ - $(CHIBIOS)/os/nil/ports/ARMCMx/compilers/GCC diff --git a/firmware/ChibiOS_16/os/nil/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk b/firmware/ChibiOS_16/os/nil/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk deleted file mode 100644 index fed58c5979..0000000000 --- a/firmware/ChibiOS_16/os/nil/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +++ /dev/null @@ -1,8 +0,0 @@ -# List of the ChibiOS/NIL ARMv7M generic port files. -PORTSRC = $(CHIBIOS)/os/nil/ports/ARMCMx/nilcore.c \ - $(CHIBIOS)/os/nil/ports/ARMCMx/nilcore_v7m.c - -PORTASM = $(CHIBIOS)/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v7m.s - -PORTINC = $(CHIBIOS)/os/nil/ports/ARMCMx \ - $(CHIBIOS)/os/nil/ports/ARMCMx/compilers/GCC diff --git a/firmware/ChibiOS_16/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v6m.s b/firmware/ChibiOS_16/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v6m.s deleted file mode 100644 index 098e52b136..0000000000 --- a/firmware/ChibiOS_16/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v6m.s +++ /dev/null @@ -1,124 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file ARMCMx/compilers/GCC/nilcoreasm_v6m.s - * @brief ARMv6-M architecture port low level code. - * - * @addtogroup ARMCMx_GCC_CORE - * @{ - */ - -#if !defined(FALSE) || defined(__DOXYGEN__) -#define FALSE 0 -#endif - -#if !defined(TRUE) || defined(__DOXYGEN__) -#define TRUE 1 -#endif - -#define _FROM_ASM_ -#include "nilconf.h" -#include "nilcore.h" - -#if !defined(__DOXYGEN__) - - .set CONTEXT_OFFSET, 0 - .set SCB_ICSR, 0xE000ED04 - .set ICSR_PENDSVSET, 0x10000000 - .set ICSR_NMIPENDSET, 0x80000000 - - .cpu cortex-m0 - .fpu softvfp - - .thumb - .text - -/*--------------------------------------------------------------------------* - * Performs a context switch between two threads. - *--------------------------------------------------------------------------*/ - .thumb_func - .globl _port_switch -_port_switch: - push {r4, r5, r6, r7, lr} - mov r4, r8 - mov r5, r9 - mov r6, r10 - mov r7, r11 - push {r4, r5, r6, r7} - - mov r3, sp - str r3, [r1, #CONTEXT_OFFSET] - ldr r3, [r0, #CONTEXT_OFFSET] - mov sp, r3 - - pop {r4, r5, r6, r7} - mov r8, r4 - mov r9, r5 - mov r10, r6 - mov r11, r7 - pop {r4, r5, r6, r7, pc} - -/*--------------------------------------------------------------------------* - * Start a thread by invoking its work function. - * - * Threads execution starts here, the code leaves the system critical zone - * and then jumps into the thread function passed in register R4. The - * register R5 contains the thread parameter. The function chThdExit() is - * called on thread function return. - *--------------------------------------------------------------------------*/ - .thumb_func - .globl _port_thread_start -_port_thread_start: - cpsie i - mov r0, r5 - blx r4 - mov r3, #0 - bl chSysHalt - -/*--------------------------------------------------------------------------* - * Post-IRQ switch code. - * - * Exception handlers return here for context switching. - *--------------------------------------------------------------------------*/ - .thumb_func - .globl _port_switch_from_isr -_port_switch_from_isr: - bl chSchRescheduleS - .globl _port_exit_from_isr -_port_exit_from_isr: - ldr r2, .L2 - ldr r3, .L3 - str r3, [r2, #0] -#if CORTEX_ALTERNATE_SWITCH - cpsie i -#endif -.L1: b .L1 - - .align 2 -.L2: .word SCB_ICSR -#if CORTEX_ALTERNATE_SWITCH -.L3: .word ICSR_PENDSVSET -#else -.L3: .word ICSR_NMIPENDSET -#endif - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v7m.s b/firmware/ChibiOS_16/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v7m.s deleted file mode 100644 index 17991d33e4..0000000000 --- a/firmware/ChibiOS_16/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v7m.s +++ /dev/null @@ -1,130 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file ARMCMx/compilers/GCC/nilcoreasm_v7m.s - * @brief ARMv7-M architecture port low level code. - * - * @addtogroup ARMCMx_GCC_CORE - * @{ - */ - -#if !defined(FALSE) || defined(__DOXYGEN__) -#define FALSE 0 -#endif - -#if !defined(TRUE) || defined(__DOXYGEN__) -#define TRUE 1 -#endif - -#define _FROM_ASM_ -#include "nilconf.h" -#include "nilcore.h" - -#if !defined(__DOXYGEN__) - - .set CONTEXT_OFFSET, 0 - .set SCB_ICSR, 0xE000ED04 - .set ICSR_PENDSVSET, 0x10000000 - - .syntax unified - .cpu cortex-m4 -#if CORTEX_USE_FPU - .fpu fpv4-sp-d16 -#else - .fpu softvfp -#endif - - .thumb - .text - -/*--------------------------------------------------------------------------* - * Performs a context switch between two threads. - *--------------------------------------------------------------------------*/ - .thumb_func - .globl _port_switch -_port_switch: - push {r4, r5, r6, r7, r8, r9, r10, r11, lr} -#if CORTEX_USE_FPU - vpush {s16-s31} -#endif - - str sp, [r1, #CONTEXT_OFFSET] -#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) && \ - ((CORTEX_MODEL == 3) || (CORTEX_MODEL == 4)) - /* Workaround for ARM errata 752419, only applied if - condition exists for it to be triggered.*/ - ldr r3, [r0, #CONTEXT_OFFSET] - mov sp, r3 -#else - ldr sp, [r0, #CONTEXT_OFFSET] -#endif - -#if CORTEX_USE_FPU - vpop {s16-s31} -#endif - pop {r4, r5, r6, r7, r8, r9, r10, r11, pc} - -/*--------------------------------------------------------------------------* - * Start a thread by invoking its work function. - * - * Threads execution starts here, the code leaves the system critical zone - * and then jumps into the thread function passed in register R4. The - * register R5 contains the thread parameter. The function chThdExit() is - * called on thread function return. - *--------------------------------------------------------------------------*/ - .thumb_func - .globl _port_thread_start -_port_thread_start: -#if !CORTEX_SIMPLIFIED_PRIORITY - movs r3, #0 - msr BASEPRI, r3 -#else /* CORTEX_SIMPLIFIED_PRIORITY */ - cpsie i -#endif /* CORTEX_SIMPLIFIED_PRIORITY */ - mov r0, r5 - blx r4 - mov r3, #0 - bl chSysHalt - -/*--------------------------------------------------------------------------* - * Post-IRQ switch code. - * - * Exception handlers return here for context switching. - *--------------------------------------------------------------------------*/ - .thumb_func - .globl _port_switch_from_isr -_port_switch_from_isr: - bl chSchRescheduleS - .globl _port_exit_from_isr -_port_exit_from_isr: -#if CORTEX_SIMPLIFIED_PRIORITY - movw r3, #:lower16:SCB_ICSR - movt r3, #:upper16:SCB_ICSR - mov r2, ICSR_PENDSVSET - str r2, [r3, #0] - cpsie i -#else /* !CORTEX_SIMPLIFIED_PRIORITY */ - svc #0 -#endif /* !CORTEX_SIMPLIFIED_PRIORITY */ -.L1: b .L1 - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/nil/ports/ARMCMx/compilers/GCC/niltypes.h b/firmware/ChibiOS_16/os/nil/ports/ARMCMx/compilers/GCC/niltypes.h deleted file mode 100644 index f9461f6eeb..0000000000 --- a/firmware/ChibiOS_16/os/nil/ports/ARMCMx/compilers/GCC/niltypes.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file ARMCMx/compilers/GCC/niltypes.h - * @brief ARM Cortex-Mx port system types. - * - * @addtogroup ARMCMx_GCC_CORE - * @{ - */ - -#ifndef _NILTYPES_H_ -#define _NILTYPES_H_ - -#include -#include -#include - -/** - * @name Common constants - */ -/** - * @brief Generic 'false' boolean constant. - */ -#if !defined(FALSE) || defined(__DOXYGEN__) -#define FALSE 0 -#endif - -/** - * @brief Generic 'true' boolean constant. - */ -#if !defined(TRUE) || defined(__DOXYGEN__) -#define TRUE 1 -#endif -/** @} */ - -typedef uint32_t syssts_t; /**< System status word. */ -typedef uint32_t rtcnt_t; /**< Realtime counter. */ -typedef uint8_t tstate_t; /**< Thread state. */ -typedef int32_t msg_t; /**< Inter-thread message. */ -typedef uint32_t eventmask_t; /**< Mask of event identifiers. */ -typedef int32_t cnt_t; /**< Generic signed counter. */ -typedef uint32_t ucnt_t; /**< Generic unsigned counter. */ - -/** - * @brief Type of system time. - */ -#if (NIL_CFG_ST_RESOLUTION == 32) || defined(__DOXYGEN__) -typedef uint32_t systime_t; -#else -typedef uint16_t systime_t; -#endif - -/** - * @brief ROM constant modifier. - * @note It is set to use the "const" keyword in this port. - */ -#define ROMCONST const - -/** - * @brief Makes functions not inlineable. - * @note If the compiler does not support such attribute then the - * realtime counter precision could be degraded. - */ -#define NOINLINE __attribute__((noinline)) - -/** - * @brief Optimized thread function declaration macro. - */ -#define PORT_THD_FUNCTION(tname, arg) \ - __attribute__((noreturn)) void tname(void *arg) - -/** - * @brief Packed variable specifier. - */ -#define PACKED_VAR __attribute__((packed)) - -#endif /* _NILTYPES_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/nil/ports/ARMCMx/nilcore.c b/firmware/ChibiOS_16/os/nil/ports/ARMCMx/nilcore.c deleted file mode 100644 index 45ea1fb871..0000000000 --- a/firmware/ChibiOS_16/os/nil/ports/ARMCMx/nilcore.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file ARMCMx/nilcore.c - * @brief ARM Cortex-Mx port code. - * - * @addtogroup ARMCMx_CORE - * @{ - */ - -#include "nil.h" - -/*===========================================================================*/ -/* Module local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/nil/ports/ARMCMx/nilcore.h b/firmware/ChibiOS_16/os/nil/ports/ARMCMx/nilcore.h deleted file mode 100644 index a45e5fe7a4..0000000000 --- a/firmware/ChibiOS_16/os/nil/ports/ARMCMx/nilcore.h +++ /dev/null @@ -1,204 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file ARMCMx/nilcore.h - * @brief ARM Cortex-Mx port macros and structures. - * - * @addtogroup ARMCMx_CORE - * @{ - */ - -#ifndef _NILCORE_H_ -#define _NILCORE_H_ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @name Architecture and Compiler - * @{ - */ -/** - * @brief Macro defining a generic ARM architecture. - */ -#define PORT_ARCHITECTURE_ARM - -/* The following code is not processed when the file is included from an - asm module because those intrinsic macros are not necessarily defined - by the assembler too.*/ -#if !defined(_FROM_ASM_) - -/** - * @brief Compiler name and version. - */ -#if defined(__GNUC__) || defined(__DOXYGEN__) -#define PORT_COMPILER_NAME "GCC " __VERSION__ - -#elif defined(__ICCARM__) -#define PORT_COMPILER_NAME "IAR" - -#elif defined(__CC_ARM) -#define PORT_COMPILER_NAME "RVCT" - -#else -#error "unsupported compiler" -#endif - -#endif /* !defined(_FROM_ASM_) */ - -/** @} */ - -/* Inclusion of the Cortex-Mx implementation specific parameters.*/ -#include "cmparams.h" - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Enables an alternative timer implementation. - * @details Usually the port uses a timer interface defined in the file - * @p nilcore_timer.h, if this option is enabled then the file - * @p nilcore_timer_alt.h is included instead. - */ -#if !defined(PORT_USE_ALT_TIMER) -#define PORT_USE_ALT_TIMER FALSE -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/* The following code is not processed when the file is included from an - asm module.*/ -#if !defined(_FROM_ASM_) - -/** - * @brief Type of a generic ARM register. - */ -typedef void *regarm_t; - -/** - * @brief Type of stack and memory alignment enforcement. - * @note In this architecture the stack alignment is enforced to 64 bits, - * 32 bits alignment is supported by hardware but deprecated by ARM, - * the implementation choice is to not offer the option. - */ -typedef uint64_t stkalign_t; - -/* The following declarations are there just for Doxygen documentation, the - real declarations are inside the sub-headers being specific for the - sub-architectures.*/ -#if defined(__DOXYGEN__) -/** - * @brief Interrupt saved context. - * @details This structure represents the stack frame saved during a - * preemption-capable interrupt handler. - * @note It is implemented to match the Cortex-Mx exception context. - */ -struct port_extctx {}; - -/** - * @brief System saved context. - * @details This structure represents the inner stack frame during a context - * switch. - */ -struct port_intctx {}; -#endif /* defined(__DOXYGEN__) */ - -#endif /* !defined(_FROM_ASM_) */ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @brief Total priority levels. - */ -#define CORTEX_PRIORITY_LEVELS (1U << CORTEX_PRIORITY_BITS) - -/** - * @brief Minimum priority level. - * @details This minimum priority level is calculated from the number of - * priority bits supported by the specific Cortex-Mx implementation. - */ -#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1) - -/** - * @brief Maximum priority level. - * @details The maximum allowed priority level is always zero. - */ -#define CORTEX_MAXIMUM_PRIORITY 0U - -/** - * @brief Priority level to priority mask conversion macro. - */ -#define CORTEX_PRIO_MASK(n) \ - ((n) << (8U - (unsigned)CORTEX_PRIORITY_BITS)) - -/** - * @brief Priority level verification macro. - */ -#define PORT_IRQ_IS_VALID_PRIORITY(n) \ - (((n) >= 0U) && ((n) < CORTEX_PRIORITY_LEVELS)) - -/** - * @brief Priority level verification macro. - */ -#define PORT_IRQ_IS_VALID_KERNEL_PRIORITY(n) \ - (((n) >= CORTEX_MAX_KERNEL_PRIORITY) && ((n) < CORTEX_PRIORITY_LEVELS)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -/* Includes the sub-architecture-specific part.*/ -#if (CORTEX_MODEL == 0) || (CORTEX_MODEL == 1) -#include "nilcore_v6m.h" -#elif (CORTEX_MODEL == 3) || (CORTEX_MODEL == 4) || (CORTEX_MODEL == 7) -#include "nilcore_v7m.h" -#else -#error "unknown Cortex-M variant" -#endif - -#if !defined(_FROM_ASM_) - -#if NIL_CFG_ST_TIMEDELTA > 0 -#if PORT_USE_ALT_TIMER == FALSE -#include "nilcore_timer.h" -#else /* PORT_USE_ALT_TIMER != FALSE */ -#include "nilcore_timer_alt.h" -#endif /* PORT_USE_ALT_TIMER != FALSE */ -#endif /* NIL_CFG_ST_TIMEDELTA > 0 */ - -#endif /* !defined(_FROM_ASM_) */ - -#endif /* _NILCORE_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/nil/ports/ARMCMx/nilcore_timer.h b/firmware/ChibiOS_16/os/nil/ports/ARMCMx/nilcore_timer.h deleted file mode 100644 index 0812e50955..0000000000 --- a/firmware/ChibiOS_16/os/nil/ports/ARMCMx/nilcore_timer.h +++ /dev/null @@ -1,124 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file ARMCMx/nilcore_timer.h - * @brief System timer header file. - * - * @addtogroup ARMCMx_TIMER - * @{ - */ - -#ifndef _NILCORE_TIMER_H_ -#define _NILCORE_TIMER_H_ - -/* This is the only header in the HAL designed to be include-able alone.*/ -#include "st.h" - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -/** - * @brief Starts the alarm. - * @note Makes sure that no spurious alarms are triggered after - * this call. - * - * @param[in] time the time to be set for the first alarm - * - * @notapi - */ -static inline void port_timer_start_alarm(systime_t time) { - - stStartAlarm(time); -} - -/** - * @brief Stops the alarm interrupt. - * - * @notapi - */ -static inline void port_timer_stop_alarm(void) { - - stStopAlarm(); -} - -/** - * @brief Sets the alarm time. - * - * @param[in] time the time to be set for the next alarm - * - * @notapi - */ -static inline void port_timer_set_alarm(systime_t time) { - - stSetAlarm(time); -} - -/** - * @brief Returns the system time. - * - * @return The system time. - * - * @notapi - */ -static inline systime_t port_timer_get_time(void) { - - return stGetCounter(); -} - -/** - * @brief Returns the current alarm time. - * - * @return The currently set alarm time. - * - * @notapi - */ -static inline systime_t port_timer_get_alarm(void) { - - return stGetAlarm(); -} - -#endif /* _NILCORE_TIMER_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/nil/ports/ARMCMx/nilcore_v6m.c b/firmware/ChibiOS_16/os/nil/ports/ARMCMx/nilcore_v6m.c deleted file mode 100644 index 51fd4987dc..0000000000 --- a/firmware/ChibiOS_16/os/nil/ports/ARMCMx/nilcore_v6m.c +++ /dev/null @@ -1,147 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file nilcore_v6m.c - * @brief ARMv6-M architecture port code. - * - * @addtogroup ARMCMx_V6M_CORE - * @{ - */ - -#include "nil.h" - -/*===========================================================================*/ -/* Module local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module interrupt handlers. */ -/*===========================================================================*/ - -#if (CORTEX_ALTERNATE_SWITCH == FALSE) || defined(__DOXYGEN__) -/** - * @brief NMI vector. - * @details The NMI vector is used for exception mode re-entering after a - * context switch. - */ -/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/ -void NMI_Handler(void) { -/*lint -restore*/ - - /* The port_extctx structure is pointed by the PSP register.*/ - struct port_extctx *ctxp = (struct port_extctx *)__get_PSP(); - - /* Discarding the current exception context and positioning the stack to - point to the real one.*/ - ctxp++; - - /* Writing back the modified PSP value.*/ - __set_PSP((uint32_t)ctxp); - - /* Restoring the normal interrupts status.*/ - port_unlock_from_isr(); -} -#endif /* !CORTEX_ALTERNATE_SWITCH */ - -#if (CORTEX_ALTERNATE_SWITCH == TRUE) || defined(__DOXYGEN__) -/** - * @brief PendSV vector. - * @details The PendSV vector is used for exception mode re-entering after a - * context switch. - */ -/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/ -void PendSV_Handler(void) { -/*lint -restore*/ - - /* The port_extctx structure is pointed by the PSP register.*/ - struct port_extctx *ctxp = (struct port_extctx *)__get_PSP(); - - /* Discarding the current exception context and positioning the stack to - point to the real one.*/ - ctxp++; - - /* Writing back the modified PSP value.*/ - __set_PSP((uint32_t)ctxp); -} -#endif /* CORTEX_ALTERNATE_SWITCH */ - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -/** - * @brief IRQ epilogue code. - * - * @param[in] lr value of the @p LR register on ISR entry - */ -void _port_irq_epilogue(regarm_t lr) { - - if (lr != (regarm_t)0xFFFFFFF1U) { - struct port_extctx *ctxp; - - port_lock_from_isr(); - - /* The extctx structure is pointed by the PSP register.*/ - ctxp = (struct port_extctx *)__get_PSP(); - - /* Adding an artificial exception return context, there is no need to - populate it fully.*/ - ctxp--; - - /* Writing back the modified PSP value.*/ - __set_PSP((uint32_t)ctxp); - - /* Setting up a fake XPSR register value.*/ - ctxp->xpsr = (regarm_t)0x01000000; - - /* The exit sequence is different depending on if a preemption is - required or not.*/ - if (chSchIsRescRequiredI()) { - /* Preemption is required we need to enforce a context switch.*/ - ctxp->pc = (regarm_t)_port_switch_from_isr; - } - else { - /* Preemption not required, we just need to exit the exception - atomically.*/ - ctxp->pc = (regarm_t)_port_exit_from_isr; - } - - /* Note, returning without unlocking is intentional, this is done in - order to keep the rest of the context switch atomic.*/ - } -} - -/** @} */ diff --git a/firmware/ChibiOS_16/os/nil/ports/ARMCMx/nilcore_v6m.h b/firmware/ChibiOS_16/os/nil/ports/ARMCMx/nilcore_v6m.h deleted file mode 100644 index f55d4c2559..0000000000 --- a/firmware/ChibiOS_16/os/nil/ports/ARMCMx/nilcore_v6m.h +++ /dev/null @@ -1,406 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chcore_v6m.h - * @brief ARMv6-M architecture port macros and structures. - * - * @addtogroup ARMCMx_V6M_CORE - * @{ - */ - -#ifndef _CHCORE_V6M_H_ -#define _CHCORE_V6M_H_ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @brief This port does not support a realtime counter. - */ -#define PORT_SUPPORTS_RT FALSE - -/** - * @brief PendSV priority level. - * @note This priority is enforced to be equal to @p 0, - * this handler always has the highest priority that cannot preempt - * the kernel. - */ -#define CORTEX_PRIORITY_PENDSV 0 - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Stack size for the system idle thread. - * @details This size depends on the idle thread implementation, usually - * the idle thread should take no more space than those reserved - * by @p PORT_INT_REQUIRED_STACK. - * @note In this port it is set to 16 because the idle thread does have - * a stack frame when compiling without optimizations. You may - * reduce this value to zero when compiling with optimizations. - */ -#if !defined(PORT_IDLE_THREAD_STACK_SIZE) -#define PORT_IDLE_THREAD_STACK_SIZE 16 -#endif - -/** - * @brief Per-thread stack overhead for interrupts servicing. - * @details This constant is used in the calculation of the correct working - * area size. - * @note In this port this value is conservatively set to 32 because the - * function @p chSchDoReschedule() can have a stack frame, especially - * with compiler optimizations disabled. The value can be reduced - * when compiler optimizations are enabled. - */ -#if !defined(PORT_INT_REQUIRED_STACK) -#define PORT_INT_REQUIRED_STACK 32 -#endif - -/** - * @brief Enables the use of the WFI instruction in the idle thread loop. - */ -#if !defined(CORTEX_ENABLE_WFI_IDLE) -#define CORTEX_ENABLE_WFI_IDLE FALSE -#endif - -/** - * @brief Alternate preemption method. - * @details Activating this option will make the Kernel use the PendSV - * handler for preemption instead of the NMI handler. - */ -#ifndef CORTEX_ALTERNATE_SWITCH -#define CORTEX_ALTERNATE_SWITCH FALSE -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/** - * @name Architecture and Compiler - * @{ - */ -#if ((CORTEX_MODEL == 0) && !defined(__CORE_CM0PLUS_H_DEPENDANT)) || \ - defined(__DOXYGEN__) -/** - * @brief Macro defining the specific ARM architecture. - */ -#define PORT_ARCHITECTURE_ARM_v6M - -/** - * @brief Name of the implemented architecture. - */ -#define PORT_ARCHITECTURE_NAME "ARMv6-M" - -/** - * @brief Name of the architecture variant. - */ -#define PORT_CORE_VARIANT_NAME "Cortex-M0" - -#elif (CORTEX_MODEL == 0) && defined(__CORE_CM0PLUS_H_DEPENDANT) -#define PORT_ARCHITECTURE_ARM_v6M -#define PORT_ARCHITECTURE_NAME "ARMv6-M" -#define PORT_CORE_VARIANT_NAME "Cortex-M0+" -#endif - -/** - * @brief Port-specific information string. - */ -#if (CORTEX_ALTERNATE_SWITCH == FALSE) || defined(__DOXYGEN__) -#define PORT_INFO "Preemption through NMI" -#else -#define PORT_INFO "Preemption through PendSV" -#endif -/** @} */ - -/** - * @brief Maximum usable priority for normal ISRs. - */ -#if (CORTEX_ALTERNATE_SWITCH == TRUE) || defined(__DOXYGEN__) -#define CORTEX_MAX_KERNEL_PRIORITY 1 -#else -#define CORTEX_MAX_KERNEL_PRIORITY 0 -#endif - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -#if !defined(_FROM_ASM_) - - /* The documentation of the following declarations is in chconf.h in order - to not have duplicated structure names into the documentation.*/ -#if !defined(__DOXYGEN__) -struct port_extctx { - regarm_t r0; - regarm_t r1; - regarm_t r2; - regarm_t r3; - regarm_t r12; - regarm_t lr_thd; - regarm_t pc; - regarm_t xpsr; -}; - -struct port_intctx { - regarm_t r8; - regarm_t r9; - regarm_t r10; - regarm_t r11; - regarm_t r4; - regarm_t r5; - regarm_t r6; - regarm_t r7; - regarm_t lr; -}; -#endif /* !defined(__DOXYGEN__) */ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @brief Platform dependent thread stack setup. - * @details This code usually setup the context switching frame represented - * by an @p port_intctx structure. - */ -#define PORT_SETUP_CONTEXT(tp, wend, pf, arg) { \ - (tp)->ctxp = (struct port_intctx *)((uint8_t *)(wend) - \ - sizeof(struct port_intctx)); \ - (tp)->ctxp->r4 = (regarm_t)(pf); \ - (tp)->ctxp->r5 = (regarm_t)(arg); \ - (tp)->ctxp->lr = (regarm_t)_port_thread_start; \ -} - -/** - * @brief Computes the thread working area global size. - * @note There is no need to perform alignments in this macro. - */ -#define PORT_WA_SIZE(n) (sizeof(struct port_intctx) + \ - sizeof(struct port_extctx) + \ - ((size_t)(n)) + ((size_t)(PORT_INT_REQUIRED_STACK))) - -/** - * @brief IRQ prologue code. - * @details This macro must be inserted at the start of all IRQ handlers - * enabled to invoke system APIs. - */ -#if defined(__GNUC__) || defined(__DOXYGEN__) -#define PORT_IRQ_PROLOGUE() \ - regarm_t _saved_lr = (regarm_t)__builtin_return_address(0) -#elif defined(__ICCARM__) -#define PORT_IRQ_PROLOGUE() \ - regarm_t _saved_lr = (regarm_t)__get_LR() -#elif defined(__CC_ARM) -#define PORT_IRQ_PROLOGUE() \ - regarm_t _saved_lr = (regarm_t)__return_address() -#endif - -/** - * @brief IRQ epilogue code. - * @details This macro must be inserted at the end of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_EPILOGUE() _port_irq_epilogue(_saved_lr) - -/** - * @brief IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_IRQ_HANDLER(id) void id(void) - -/** - * @brief Fast IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_FAST_IRQ_HANDLER(id) void id(void) - -/** - * @brief Performs a context switch between two threads. - * @details This is the most critical code in any port, this function - * is responsible for the context switch between 2 threads. - * @note The implementation of this code affects directly the context - * switch performance so optimize here as much as you can. - * - * @param[in] ntp the thread to be switched in - * @param[in] otp the thread to be switched out - */ -#if (NIL_CFG_ENABLE_STACK_CHECK == FALSE) || defined(__DOXYGEN__) -#define port_switch(ntp, otp) _port_switch(ntp, otp) -#else -#define port_switch(ntp, otp) { \ - struct port_intctx *r13 = (struct port_intctx *)__get_PSP(); \ - if ((stkalign_t *)(r13 - 1) < (otp)->stklim) { \ - chSysHalt("stack overflow"); \ - } \ - _port_switch(ntp, otp); \ -} -#endif - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void _port_irq_epilogue(regarm_t lr); - void _port_switch_from_isr(void); - void _port_exit_from_isr(void); - void _port_switch(thread_t *ntp, thread_t *otp); - void _port_thread_start(void); -#ifdef __cplusplus -} -#endif - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -/** - * @brief Port-related initialization code. - */ -static inline void port_init(void) { - - NVIC_SetPriority(PendSV_IRQn, CORTEX_PRIORITY_PENDSV); -} - -/** - * @brief Returns a word encoding the current interrupts status. - * - * @return The interrupts status. - */ -static inline syssts_t port_get_irq_status(void) { - - return (syssts_t)__get_PRIMASK(); -} - -/** - * @brief Checks the interrupt status. - * - * @param[in] sts the interrupt status word - * - * @return The interrupt status. - * @retvel false the word specified a disabled interrupts status. - * @retvel true the word specified an enabled interrupts status. - */ -static inline bool port_irq_enabled(syssts_t sts) { - - return (sts & (syssts_t)1) == (syssts_t)0; -} - -/** - * @brief Determines the current execution context. - * - * @return The execution context. - * @retval false not running in ISR mode. - * @retval true running in ISR mode. - */ -static inline bool port_is_isr_context(void) { - - return (bool)((__get_IPSR() & 0x1FFU) != 0U); -} - -/** - * @brief Kernel-lock action. - * @details In this port this function disables interrupts globally. - */ -static inline void port_lock(void) { - - __disable_irq(); -} - -/** - * @brief Kernel-unlock action. - * @details In this port this function enables interrupts globally. - */ -static inline void port_unlock(void) { - - __enable_irq(); -} - -/** - * @brief Kernel-lock action from an interrupt handler. - * @details In this port this function disables interrupts globally. - * @note Same as @p port_lock() in this port. - */ -static inline void port_lock_from_isr(void) { - - port_lock(); -} - -/** - * @brief Kernel-unlock action from an interrupt handler. - * @details In this port this function enables interrupts globally. - * @note Same as @p port_lock() in this port. - */ -static inline void port_unlock_from_isr(void) { - - port_unlock(); -} - -/** - * @brief Disables all the interrupt sources. - */ -static inline void port_disable(void) { - - __disable_irq(); -} - -/** - * @brief Disables the interrupt sources below kernel-level priority. - */ -static inline void port_suspend(void) { - - __disable_irq(); -} - -/** - * @brief Enables all the interrupt sources. - */ -static inline void port_enable(void) { - - __enable_irq(); -} - -/** - * @brief Enters an architecture-dependent IRQ-waiting mode. - * @details The function is meant to return when an interrupt becomes pending. - * The simplest implementation is an empty function or macro but this - * would not take advantage of architecture-specific power saving - * modes. - * @note Implemented as an inlined @p WFI instruction. - */ -static inline void port_wait_for_interrupt(void) { - -#if CORTEX_ENABLE_WFI_IDLE == TRUE - __WFI(); -#endif -} - -#endif /* _FROM_ASM_ */ - -#endif /* _CHCORE_V6M_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/nil/ports/ARMCMx/nilcore_v7m.c b/firmware/ChibiOS_16/os/nil/ports/ARMCMx/nilcore_v7m.c deleted file mode 100644 index 9eba74ecbc..0000000000 --- a/firmware/ChibiOS_16/os/nil/ports/ARMCMx/nilcore_v7m.c +++ /dev/null @@ -1,165 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file nilcore_v7m.c - * @brief ARMv7-M architecture port code. - * - * @addtogroup ARMCMx_V7M_CORE - * @{ - */ - -#include "nil.h" - -/*===========================================================================*/ -/* Module local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module interrupt handlers. */ -/*===========================================================================*/ - -#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__) -/** - * @brief SVC vector. - * @details The SVC vector is used for exception mode re-entering after a - * context switch. - * @note The PendSV vector is only used in advanced kernel mode. - */ -/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/ -void SVC_Handler(void) { -/*lint -restore*/ - struct port_extctx *ctxp; - -#if CORTEX_USE_FPU == TRUE - /* Enforcing unstacking of the FP part of the context.*/ - FPU->FPCCR &= ~FPU_FPCCR_LSPACT_Msk; -#endif - - /* The port_extctx structure is pointed by the PSP register.*/ - ctxp = (struct port_extctx *)__get_PSP(); - - /* Discarding the current exception context and positioning the stack to - point to the real one.*/ - ctxp++; - - /* Restoring real position of the original stack frame.*/ - __set_PSP((uint32_t)ctxp); - - /* Restoring the normal interrupts status.*/ - port_unlock_from_isr(); -} -#endif /* CORTEX_SIMPLIFIED_PRIORITY == FALSE */ - -#if (CORTEX_SIMPLIFIED_PRIORITY == TRUE) || defined(__DOXYGEN__) -/** - * @brief PendSV vector. - * @details The PendSV vector is used for exception mode re-entering after a - * context switch. - * @note The PendSV vector is only used in compact kernel mode. - */ -/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/ -void PendSV_Handler(void) { -/*lint -restore*/ - struct port_extctx *ctxp; - -#if CORTEX_USE_FPU == TRUE - /* Enforcing unstacking of the FP part of the context.*/ - FPU->FPCCR &= ~FPU_FPCCR_LSPACT_Msk; -#endif - - /* The port_extctx structure is pointed by the PSP register.*/ - ctxp = (struct port_extctx *)__get_PSP(); - - /* Discarding the current exception context and positioning the stack to - point to the real one.*/ - ctxp++; - - /* Writing back the modified PSP value.*/ - __set_PSP((uint32_t)ctxp); -} -#endif /* CORTEX_SIMPLIFIED_PRIORITY == TRUE */ - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -/** - * @brief Exception exit redirection to _port_switch_from_isr(). - */ -void _port_irq_epilogue(void) { - - port_lock_from_isr(); - if ((SCB->ICSR & SCB_ICSR_RETTOBASE_Msk) != 0U) { - struct port_extctx *ctxp; - -#if CORTEX_USE_FPU == TRUE - /* Enforcing a lazy FPU state save by accessing the FPCSR register.*/ - (void) __get_FPSCR(); -#endif - - /* The port_extctx structure is pointed by the PSP register.*/ - ctxp = (struct port_extctx *)__get_PSP(); - - /* Adding an artificial exception return context, there is no need to - populate it fully.*/ - ctxp--; - - /* Setting up a fake XPSR register value.*/ - ctxp->xpsr = (regarm_t)0x01000000; - - /* Writing back the modified PSP value.*/ - __set_PSP((uint32_t)ctxp); - - /* The exit sequence is different depending on if a preemption is - required or not.*/ - if (chSchIsRescRequiredI()) { - /* Preemption is required we need to enforce a context switch.*/ - ctxp->pc = (regarm_t)_port_switch_from_isr; - } - else { - /* Preemption not required, we just need to exit the exception - atomically.*/ - ctxp->pc = (regarm_t)_port_exit_from_isr; - } - - /* Note, returning without unlocking is intentional, this is done in - order to keep the rest of the context switch atomic.*/ - return; - } - port_unlock_from_isr(); -} - -/** @} */ diff --git a/firmware/ChibiOS_16/os/nil/ports/ARMCMx/nilcore_v7m.h b/firmware/ChibiOS_16/os/nil/ports/ARMCMx/nilcore_v7m.h deleted file mode 100644 index c1cf18d9ef..0000000000 --- a/firmware/ChibiOS_16/os/nil/ports/ARMCMx/nilcore_v7m.h +++ /dev/null @@ -1,576 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chcore_v7m.h - * @brief ARMv7-M architecture port macros and structures. - * - * @addtogroup ARMCMx_V7M_CORE - * @{ - */ - -#ifndef _NILCORE_V7M_H_ -#define _NILCORE_V7M_H_ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @brief This port supports a realtime counter. - */ -#define PORT_SUPPORTS_RT TRUE - -/** - * @brief Disabled value for BASEPRI register. - */ -#define CORTEX_BASEPRI_DISABLED 0U - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Stack size for the system idle thread. - * @details This size depends on the idle thread implementation, usually - * the idle thread should take no more space than those reserved - * by @p PORT_INT_REQUIRED_STACK. - * @note In this port it is set to 16 because the idle thread does have - * a stack frame when compiling without optimizations. You may - * reduce this value to zero when compiling with optimizations. - */ -#if !defined(PORT_IDLE_THREAD_STACK_SIZE) || defined(__DOXYGEN__) -#define PORT_IDLE_THREAD_STACK_SIZE 16 -#endif - -/** - * @brief Per-thread stack overhead for interrupts servicing. - * @details This constant is used in the calculation of the correct working - * area size. - * @note In this port this value is conservatively set to 32 because the - * function @p chSchDoReschedule() can have a stack frame, especially - * with compiler optimizations disabled. The value can be reduced - * when compiler optimizations are enabled. - */ -#if !defined(PORT_INT_REQUIRED_STACK) || defined(__DOXYGEN__) -#define PORT_INT_REQUIRED_STACK 32 -#endif - -/** - * @brief Enables the use of the WFI instruction in the idle thread loop. - */ -#if !defined(CORTEX_ENABLE_WFI_IDLE) -#define CORTEX_ENABLE_WFI_IDLE FALSE -#endif - -/** - * @brief FPU support in context switch. - * @details Activating this option activates the FPU support in the kernel. - */ -#if !defined(CORTEX_USE_FPU) -#define CORTEX_USE_FPU CORTEX_HAS_FPU -#elif (CORTEX_USE_FPU == TRUE) && (CORTEX_HAS_FPU == FALSE) -/* This setting requires an FPU presence check in case it is externally - redefined.*/ -#error "the selected core does not have an FPU" -#endif - -/** - * @brief Simplified priority handling flag. - * @details Activating this option makes the Kernel work in compact mode. - * In compact mode interrupts are disabled globally instead of - * raising the priority mask to some intermediate level. - */ -#if !defined(CORTEX_SIMPLIFIED_PRIORITY) -#define CORTEX_SIMPLIFIED_PRIORITY FALSE -#endif - -/** - * @brief SVCALL handler priority. - * @note The default SVCALL handler priority is defaulted to - * @p CORTEX_MAXIMUM_PRIORITY+1, this reserves the - * @p CORTEX_MAXIMUM_PRIORITY priority level as fast interrupts - * priority level. - */ -#if !defined(CORTEX_PRIORITY_SVCALL) -#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1U) -#elif !PORT_IRQ_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL) -/* If it is externally redefined then better perform a validity check on it.*/ -#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL" -#endif - -/** - * @brief NVIC VTOR initialization expression. - */ -#if !defined(CORTEX_VTOR_INIT) || defined(__DOXYGEN__) -#define CORTEX_VTOR_INIT 0x00000000U -#endif - -/** - * @brief NVIC PRIGROUP initialization expression. - * @details The default assigns all available priority bits as preemption - * priority with no sub-priority. - */ -#if !defined(CORTEX_PRIGROUP_INIT) || defined(__DOXYGEN__) -#define CORTEX_PRIGROUP_INIT (7 - CORTEX_PRIORITY_BITS) -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/** - * @name Architecture and Compiler - * @{ - */ -#if (CORTEX_MODEL == 3) || defined(__DOXYGEN__) -/** - * @brief Macro defining the specific ARM architecture. - */ -#define PORT_ARCHITECTURE_ARM_v7M - -/** - * @brief Name of the implemented architecture. - */ -#define PORT_ARCHITECTURE_NAME "ARMv7-M" - -/** - * @brief Name of the architecture variant. - */ -#define PORT_CORE_VARIANT_NAME "Cortex-M3" - -#elif (CORTEX_MODEL == 4) -#define PORT_ARCHITECTURE_ARM_v7ME -#define PORT_ARCHITECTURE_NAME "ARMv7E-M" -#if CORTEX_USE_FPU -#define PORT_CORE_VARIANT_NAME "Cortex-M4F" -#else -#define PORT_CORE_VARIANT_NAME "Cortex-M4" -#endif - -#elif (CORTEX_MODEL == 7) -#define PORT_ARCHITECTURE_ARM_v7ME -#define PORT_ARCHITECTURE_NAME "ARMv7E-M" -#if CORTEX_USE_FPU -#define PORT_CORE_VARIANT_NAME "Cortex-M7F" -#else -#define PORT_CORE_VARIANT_NAME "Cortex-M7" -#endif -#endif - -/** - * @brief Port-specific information string. - */ -#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__) -#define PORT_INFO "Advanced kernel mode" -#else -#define PORT_INFO "Compact kernel mode" -#endif -/** @} */ - -#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__) -/** - * @brief Maximum usable priority for normal ISRs. - */ -#define CORTEX_MAX_KERNEL_PRIORITY (CORTEX_PRIORITY_SVCALL + 1U) - -/** - * @brief BASEPRI level within kernel lock. - */ -#define CORTEX_BASEPRI_KERNEL \ - CORTEX_PRIO_MASK(CORTEX_MAX_KERNEL_PRIORITY) -#else - -#define CORTEX_MAX_KERNEL_PRIORITY 0U -#endif - -/** - * @brief PendSV priority level. - * @note This priority is enforced to be equal to - * @p CORTEX_MAX_KERNEL_PRIORITY, this handler always have the - * highest priority that cannot preempt the kernel. - */ -#define CORTEX_PRIORITY_PENDSV CORTEX_MAX_KERNEL_PRIORITY - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/* The following code is not processed when the file is included from an - asm module.*/ -#if !defined(_FROM_ASM_) - -/* The documentation of the following declarations is in chconf.h in order - to not have duplicated structure names into the documentation.*/ -#if !defined(__DOXYGEN__) -struct port_extctx { - regarm_t r0; - regarm_t r1; - regarm_t r2; - regarm_t r3; - regarm_t r12; - regarm_t lr_thd; - regarm_t pc; - regarm_t xpsr; -#if CORTEX_USE_FPU - regarm_t s0; - regarm_t s1; - regarm_t s2; - regarm_t s3; - regarm_t s4; - regarm_t s5; - regarm_t s6; - regarm_t s7; - regarm_t s8; - regarm_t s9; - regarm_t s10; - regarm_t s11; - regarm_t s12; - regarm_t s13; - regarm_t s14; - regarm_t s15; - regarm_t fpscr; - regarm_t reserved; -#endif /* CORTEX_USE_FPU */ -}; - -struct port_intctx { -#if CORTEX_USE_FPU - regarm_t s16; - regarm_t s17; - regarm_t s18; - regarm_t s19; - regarm_t s20; - regarm_t s21; - regarm_t s22; - regarm_t s23; - regarm_t s24; - regarm_t s25; - regarm_t s26; - regarm_t s27; - regarm_t s28; - regarm_t s29; - regarm_t s30; - regarm_t s31; -#endif /* CORTEX_USE_FPU */ - regarm_t r4; - regarm_t r5; - regarm_t r6; - regarm_t r7; - regarm_t r8; - regarm_t r9; - regarm_t r10; - regarm_t r11; - regarm_t lr; -}; -#endif /* !defined(__DOXYGEN__) */ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @brief Platform dependent part of the @p chThdCreateI() API. - * @details This code usually setup the context switching frame represented - * by an @p port_intctx structure. - */ -#define PORT_SETUP_CONTEXT(tp, wend, pf, arg) { \ - (tp)->ctxp = (struct port_intctx *)((uint8_t *)(wend) - \ - sizeof(struct port_intctx)); \ - (tp)->ctxp->r4 = (regarm_t)(pf); \ - (tp)->ctxp->r5 = (regarm_t)(arg); \ - (tp)->ctxp->lr = (regarm_t)_port_thread_start; \ -} - -/** - * @brief Computes the thread working area global size. - * @note There is no need to perform alignments in this macro. - */ -#define PORT_WA_SIZE(n) (sizeof(struct port_intctx) + \ - sizeof(struct port_extctx) + \ - ((size_t)(n)) + ((size_t)(PORT_INT_REQUIRED_STACK))) - -/** - * @brief IRQ prologue code. - * @details This macro must be inserted at the start of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_PROLOGUE() - -/** - * @brief IRQ epilogue code. - * @details This macro must be inserted at the end of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_EPILOGUE() _port_irq_epilogue() - -/** - * @brief IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_IRQ_HANDLER(id) void id(void) - -/** - * @brief Fast IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_FAST_IRQ_HANDLER(id) void id(void) - -/** - * @brief Performs a context switch between two threads. - * @details This is the most critical code in any port, this function - * is responsible for the context switch between 2 threads. - * @note The implementation of this code affects directly the context - * switch performance so optimize here as much as you can. - * - * @param[in] ntp the thread to be switched in - * @param[in] otp the thread to be switched out - */ -#if (NIL_CFG_ENABLE_STACK_CHECK == FALSE) || defined(__DOXYGEN__) -#define port_switch(ntp, otp) _port_switch(ntp, otp) -#else -#define port_switch(ntp, otp) { \ - struct port_intctx *r13 = (struct port_intctx *)__get_PSP(); \ - if ((stkalign_t *)(r13 - 1) < (otp)->stklim) { \ - chSysHalt("stack overflow"); \ - } \ - _port_switch(ntp, otp); \ -} -#endif - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void _port_irq_epilogue(void); - void _port_switch(thread_t *ntp, thread_t *otp); - void _port_thread_start(void); - void _port_switch_from_isr(void); - void _port_exit_from_isr(void); -#ifdef __cplusplus -} -#endif - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -/** - * @brief Port-related initialization code. - */ -static inline void port_init(void) { - - /* Initialization of the vector table and priority related settings.*/ - SCB->VTOR = CORTEX_VTOR_INIT; - - /* Initializing priority grouping.*/ - NVIC_SetPriorityGrouping(CORTEX_PRIGROUP_INIT); - - /* DWT cycle counter enable.*/ - CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; -#if CORTEX_MODEL == 7 - DWT->LAR = 0xC5ACCE55U; -#endif - DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; - - /* Initialization of the system vectors used by the port.*/ -#if CORTEX_SIMPLIFIED_PRIORITY == FALSE - NVIC_SetPriority(SVCall_IRQn, CORTEX_PRIORITY_SVCALL); -#endif - NVIC_SetPriority(PendSV_IRQn, CORTEX_PRIORITY_PENDSV); -} - -/** - * @brief Returns a word encoding the current interrupts status. - * - * @return The interrupts status. - */ -static inline syssts_t port_get_irq_status(void) { - syssts_t sts; - -#if CORTEX_SIMPLIFIED_PRIORITY == FALSE - sts = (syssts_t)__get_BASEPRI(); -#else /* CORTEX_SIMPLIFIED_PRIORITY */ - sts = (syssts_t)__get_PRIMASK(); -#endif /* CORTEX_SIMPLIFIED_PRIORITY */ - return sts; -} - -/** - * @brief Checks the interrupt status. - * - * @param[in] sts the interrupt status word - * - * @return The interrupt status. - * @retvel false the word specified a disabled interrupts status. - * @retvel true the word specified an enabled interrupts status. - */ -static inline bool port_irq_enabled(syssts_t sts) { - -#if CORTEX_SIMPLIFIED_PRIORITY == FALSE - return sts == (syssts_t)CORTEX_BASEPRI_DISABLED; -#else /* CORTEX_SIMPLIFIED_PRIORITY */ - return (sts & (syssts_t)1) == (syssts_t)0; -#endif /* CORTEX_SIMPLIFIED_PRIORITY */ -} - -/** - * @brief Determines the current execution context. - * - * @return The execution context. - * @retval false not running in ISR mode. - * @retval true running in ISR mode. - */ -static inline bool port_is_isr_context(void) { - - return (bool)((__get_IPSR() & 0x1FFU) != 0U); -} - -/** - * @brief Kernel-lock action. - * @details In this port this function raises the base priority to kernel - * level. - */ -static inline void port_lock(void) { - -#if CORTEX_SIMPLIFIED_PRIORITY == FALSE -#if defined(__CM7_REV) -#if __CM7_REV == 0 - __disable_irq(); -#endif -#endif - __set_BASEPRI(CORTEX_BASEPRI_KERNEL); -#if defined(__CM7_REV) -#if __CM7_REV == 0 - __enable_irq(); -#endif -#endif -#else /* CORTEX_SIMPLIFIED_PRIORITY */ - __disable_irq(); -#endif /* CORTEX_SIMPLIFIED_PRIORITY */ -} - -/** - * @brief Kernel-unlock action. - * @details In this port this function lowers the base priority to user - * level. - */ -static inline void port_unlock(void) { - -#if CORTEX_SIMPLIFIED_PRIORITY == FALSE - __set_BASEPRI(CORTEX_BASEPRI_DISABLED); -#else /* CORTEX_SIMPLIFIED_PRIORITY */ - __enable_irq(); -#endif /* CORTEX_SIMPLIFIED_PRIORITY */ -} - -/** - * @brief Kernel-lock action from an interrupt handler. - * @details In this port this function raises the base priority to kernel - * level. - * @note Same as @p port_lock() in this port. - */ -static inline void port_lock_from_isr(void) { - - port_lock(); -} - -/** - * @brief Kernel-unlock action from an interrupt handler. - * @details In this port this function lowers the base priority to user - * level. - * @note Same as @p port_unlock() in this port. - */ -static inline void port_unlock_from_isr(void) { - - port_unlock(); -} - -/** - * @brief Disables all the interrupt sources. - * @note In this port it disables all the interrupt sources by raising - * the priority mask to level 0. - */ -static inline void port_disable(void) { - - __disable_irq(); -} - -/** - * @brief Disables the interrupt sources below kernel-level priority. - * @note Interrupt sources above kernel level remains enabled. - * @note In this port it raises/lowers the base priority to kernel level. - */ -static inline void port_suspend(void) { - -#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__) - __set_BASEPRI(CORTEX_BASEPRI_KERNEL); - __enable_irq(); -#else - __disable_irq(); -#endif -} - -/** - * @brief Enables all the interrupt sources. - * @note In this port it lowers the base priority to user level. - */ -static inline void port_enable(void) { - -#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__) - __set_BASEPRI(CORTEX_BASEPRI_DISABLED); -#endif - __enable_irq(); -} - -/** - * @brief Enters an architecture-dependent IRQ-waiting mode. - * @details The function is meant to return when an interrupt becomes pending. - * The simplest implementation is an empty function or macro but this - * would not take advantage of architecture-specific power saving - * modes. - * @note Implemented as an inlined @p WFI instruction. - */ -static inline void port_wait_for_interrupt(void) { - -#if CORTEX_ENABLE_WFI_IDLE == TRUE - __WFI(); -#endif -} - -/** - * @brief Returns the current value of the realtime counter. - * - * @return The realtime counter value. - */ -static inline rtcnt_t port_rt_get_counter_value(void) { - - return DWT->CYCCNT; -} - -#endif /* !defined(_FROM_ASM_) */ - -#endif /* _NILCORE_V7M_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/nil/ports/AVR/compilers/GCC/mk/port.mk b/firmware/ChibiOS_16/os/nil/ports/AVR/compilers/GCC/mk/port.mk deleted file mode 100644 index e057e158a0..0000000000 --- a/firmware/ChibiOS_16/os/nil/ports/AVR/compilers/GCC/mk/port.mk +++ /dev/null @@ -1,7 +0,0 @@ -# List of the ChibiOS/RT AVR port files. -PORTSRC = ${CHIBIOS}/os/nil/ports/AVR/nilcore.c - -PORTASM = - -PORTINC = ${CHIBIOS}/os/nil/ports/AVR \ - ${CHIBIOS}/os/nil/ports/AVR/compilers/GCC diff --git a/firmware/ChibiOS_16/os/nil/ports/AVR/compilers/GCC/niltypes.h b/firmware/ChibiOS_16/os/nil/ports/AVR/compilers/GCC/niltypes.h deleted file mode 100644 index 33c1c67cfd..0000000000 --- a/firmware/ChibiOS_16/os/nil/ports/AVR/compilers/GCC/niltypes.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file AVR/compilers/GCC/niltypes.h - * @brief AVR port system types. - * - * @addtogroup AVR_CORE - * @{ - */ - -#ifndef _NILTYPES_H_ -#define _NILTYPES_H_ - -#include -#include -#include - -/** - * @name Common constants - */ -/** - * @brief Generic 'false' boolean constant. - */ -#if !defined(FALSE) || defined(__DOXYGEN__) -#define FALSE 0 -#endif - -/** - * @brief Generic 'true' boolean constant. - */ -#if !defined(TRUE) || defined(__DOXYGEN__) -#define TRUE (!FALSE) -#endif -/** @} */ - -typedef uint8_t syssts_t; /**< System status word. */ -typedef uint16_t rtcnt_t; /**< Realtime counter. */ -typedef uint8_t tstate_t; /**< Thread state. */ -typedef int16_t msg_t; /**< Inter-thread message. */ -typedef uint8_t eventmask_t; /**< Mask of event identifiers. */ -typedef int8_t cnt_t; /**< Generic signed counter. */ -typedef uint8_t ucnt_t; /**< Generic unsigned counter. */ - -/** - * @brief Type of system time. - */ -#if (NIL_CFG_ST_RESOLUTION == 32) || defined(__DOXYGEN__) -typedef uint32_t systime_t; -#else -typedef uint16_t systime_t; -#endif - -/** - * @brief ROM constant modifier. - * @note It is set to use the "const" keyword in this port. - */ -#define ROMCONST const - -/** - * @brief Makes functions not inlineable. - * @note If the compiler does not support such attribute then the - * realtime counter precision could be degraded. - */ -#define NOINLINE __attribute__((noinline)) - -/** - * @brief Optimized thread function declaration macro. - */ -#define PORT_THD_FUNCTION(tname, arg) \ - __attribute__((noreturn)) void tname(void *arg) - -/** - * @brief Packed variable specifier. - */ -#define PACKED_VAR __attribute__((packed)) - -#endif /* _NILTYPES_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/nil/ports/AVR/nilcore.c b/firmware/ChibiOS_16/os/nil/ports/AVR/nilcore.c deleted file mode 100644 index f39703df70..0000000000 --- a/firmware/ChibiOS_16/os/nil/ports/AVR/nilcore.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file AVR/nilcore.c - * @brief AVR port code. - * - * @addtogroup AVR_CORE - * @{ - */ - -#include "nil.h" - -/*===========================================================================*/ -/* Module local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -/** - * @brief Performs a context switch between two threads. - * @details This is the most critical code in any port, this function - * is responsible for the context switch between 2 threads. - * @note The implementation of this code affects directly the context - * switch performance so optimize here as much as you can. - * @note The function is declared as a weak symbol, it is possible to - * redefine it in your application code. - * - * @param[in] ntp the thread to be switched in - * @param[in] otp the thread to be switched out - */ -#if !defined(__DOXYGEN__) -__attribute__((naked, weak)) -#endif -void _port_switch(thread_t *ntp, thread_t *otp) { - - asm volatile ("push r2"); - asm volatile ("push r3"); - asm volatile ("push r4"); - asm volatile ("push r5"); - asm volatile ("push r6"); - asm volatile ("push r7"); - asm volatile ("push r8"); - asm volatile ("push r9"); - asm volatile ("push r10"); - asm volatile ("push r11"); - asm volatile ("push r12"); - asm volatile ("push r13"); - asm volatile ("push r14"); - asm volatile ("push r15"); - asm volatile ("push r16"); - asm volatile ("push r17"); - asm volatile ("push r28"); - asm volatile ("push r29"); - - asm volatile ("movw r30, r22"); - asm volatile ("in r0, 0x3d"); - asm volatile ("std Z+0, r0"); - asm volatile ("in r0, 0x3e"); - asm volatile ("std Z+1, r0"); - - asm volatile ("movw r30, r24"); - asm volatile ("ldd r0, Z+0"); - asm volatile ("out 0x3d, r0"); - asm volatile ("ldd r0, Z+1"); - asm volatile ("out 0x3e, r0"); - - asm volatile ("pop r29"); - asm volatile ("pop r28"); - asm volatile ("pop r17"); - asm volatile ("pop r16"); - asm volatile ("pop r15"); - asm volatile ("pop r14"); - asm volatile ("pop r13"); - asm volatile ("pop r12"); - asm volatile ("pop r11"); - asm volatile ("pop r10"); - asm volatile ("pop r9"); - asm volatile ("pop r8"); - asm volatile ("pop r7"); - asm volatile ("pop r6"); - asm volatile ("pop r5"); - asm volatile ("pop r4"); - asm volatile ("pop r3"); - asm volatile ("pop r2"); - asm volatile ("ret"); -} - -/** - * @brief Start a thread by invoking its work function. - * @details If the work function returns @p chThdExit() is automatically - * invoked. - */ -void _port_thread_start(void) { - - chSysUnlock(); - asm volatile ("movw r24, r4"); - asm volatile ("movw r30, r2"); - asm volatile ("icall"); - chSysHalt(0); -} - -/** @} */ diff --git a/firmware/ChibiOS_16/os/nil/ports/AVR/nilcore.h b/firmware/ChibiOS_16/os/nil/ports/AVR/nilcore.h deleted file mode 100644 index fbe992a9ea..0000000000 --- a/firmware/ChibiOS_16/os/nil/ports/AVR/nilcore.h +++ /dev/null @@ -1,418 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file AVR/nilcore.h - * @brief AVR port macros and structures. - * - * @addtogroup AVR_CORE - * @{ - */ - -#ifndef _NILCORE_H_ -#define _NILCORE_H_ - -#include -#include - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @name Architecture and Compiler - * @{ - */ -/** - * @brief Macro defining the port architecture. - */ -#define PORT_ARCHITECTURE_AVR - -/** - * @brief Name of the implemented architecture. - */ -#define PORT_ARCHITECTURE_NAME "AVR" - -/** - * @brief Name of the architecture variant. - */ -#define PORT_CORE_VARIANT_NAME "MegaAVR" - -/** - * @brief Compiler name and version. - */ -#if defined(__GNUC__) || defined(__DOXYGEN__) -#define PORT_COMPILER_NAME "GCC " __VERSION__ - -#else -#error "unsupported compiler" -#endif - -/** - * @brief Port-specific information string. - */ -#define PORT_INFO "16 bits code addressing" - -/** - * @brief This port supports a realtime counter. - */ -#define PORT_SUPPORTS_RT FALSE -/** @} */ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Stack size for the system idle thread. - * @details This size depends on the idle thread implementation, usually - * the idle thread should take no more space than those reserved - * by @p PORT_INT_REQUIRED_STACK. - * @note In this port it is set to 8. - */ -#if !defined(PORT_IDLE_THREAD_STACK_SIZE) || defined(__DOXYGEN__) -#define PORT_IDLE_THREAD_STACK_SIZE 8 -#endif - -/** - * @brief Per-thread stack overhead for interrupts servicing. - * @details This constant is used in the calculation of the correct working - * area size. - * @note In this port the default is 32 bytes per thread. - */ -#if !defined(PORT_INT_REQUIRED_STACK) || defined(__DOXYGEN__) -#define PORT_INT_REQUIRED_STACK 32 -#endif - -/** - * @brief Enables an alternative timer implementation. - * @details Usually the port uses a timer interface defined in the file - * @p nilcore_timer.h, if this option is enabled then the file - * @p nilcore_timer_alt.h is included instead. - */ -#if !defined(PORT_USE_ALT_TIMER) -#define PORT_USE_ALT_TIMER FALSE -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/* The following code is not processed when the file is included from an - asm module.*/ -#if !defined(_FROM_ASM_) - -/** - * @brief Type of stack and memory alignment enforcement. - */ -typedef uint8_t stkalign_t; - -/** - * @brief System saved context. - * @details This structure represents the inner stack frame during a context - * switching. - */ -struct port_intctx { - uint8_t _next; - uint8_t r29; - uint8_t r28; - uint8_t r17; - uint8_t r16; - uint8_t r15; - uint8_t r14; - uint8_t r13; - uint8_t r12; - uint8_t r11; - uint8_t r10; - uint8_t r9; - uint8_t r8; - uint8_t r7; - uint8_t r6; - uint8_t r5; - uint8_t r4; - uint8_t r3; - uint8_t r2; -#ifdef __AVR_3_BYTE_PC__ - uint8_t pcx; -#endif - uint8_t pcl; - uint8_t pch; -}; - -#endif /* !defined(_FROM_ASM_) */ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @brief Platform dependent thread stack setup. - * @details This code usually setup the context switching frame represented - * by an @p port_intctx structure. - */ -#ifdef __AVR_3_BYTE_PC__ -#define PORT_SETUP_CONTEXT(tp, wend, pf, arg) { \ - (tp)->ctxp = (struct port_intctx*)(((uint8_t *)(wend)) - \ - sizeof(struct port_intctx)); \ - (tp)->ctxp->r2 = (int)pf; \ - (tp)->ctxp->r3 = (int)pf >> 8; \ - (tp)->ctxp->r4 = (int)arg; \ - (tp)->ctxp->r5 = (int)arg >> 8; \ - (tp)->ctxp->pcx = (int)0; \ - (tp)->ctxp->pcl = (int)_port_thread_start >> 8; \ - (tp)->ctxp->pch = (int)_port_thread_start; \ -} -#else /* __AVR_3_BYTE_PC__ */ -#define PORT_SETUP_CONTEXT(tp, wend, pf, arg) { \ - (tp)->ctxp = (struct port_intctx*)(((uint8_t *)(wend)) - \ - sizeof(struct port_intctx)); \ - (tp)->ctxp->r2 = (int)pf; \ - (tp)->ctxp->r3 = (int)pf >> 8; \ - (tp)->ctxp->r4 = (int)arg; \ - (tp)->ctxp->r5 = (int)arg >> 8; \ - (tp)->ctxp->pcl = (int)_port_thread_start >> 8; \ - (tp)->ctxp->pch = (int)_port_thread_start; \ -} -#endif /* __AVR_3_BYTE_PC__ */ -/** - * @brief Computes the thread working area global size. - * @note There is no need to perform alignments in this macro. - */ -#define PORT_WA_SIZE(n) ((sizeof(struct port_intctx) - 1) + \ - (n) + (PORT_INT_REQUIRED_STACK)) - -/** - * @brief IRQ prologue code. - * @details This macro must be inserted at the start of all IRQ handlers - * enabled to invoke system APIs. - * @note This code tricks the compiler to save all the specified registers - * by "touching" them. - */ -#define PORT_IRQ_PROLOGUE() { \ - asm ("" : : : "r18", "r19", "r20", "r21", "r22", "r23", "r24", \ - "r25", "r26", "r27", "r30", "r31"); \ -} - -/** - * @brief IRQ epilogue code. - * @details This macro must be inserted at the end of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_EPILOGUE() chSchRescheduleS() - -/** - * @brief IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_IRQ_HANDLER(id) ISR(id) - -/** - * @brief Fast IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_FAST_IRQ_HANDLER(id) ISR(id) - -/** - * @brief Performs a context switch between two threads. - * @details This is the most critical code in any port, this function - * is responsible for the context switch between 2 threads. - * @note The implementation of this code affects directly the context - * switch performance so optimize here as much as you can. - * - * @param[in] ntp the thread to be switched in - * @param[in] otp the thread to be switched out - */ -#define port_switch(ntp, otp) _port_switch(ntp, otp) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/* The following code is not processed when the file is included from an - asm module.*/ -#if !defined(_FROM_ASM_) - -#ifdef __cplusplus -extern "C" { -#endif - void _port_irq_epilogue(void); - void _port_switch(thread_t *ntp, thread_t *otp); - void _port_thread_start(void); -#ifdef __cplusplus -} -#endif - -#endif /* !defined(_FROM_ASM_) */ - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -/* The following code is not processed when the file is included from an - asm module.*/ -#if !defined(_FROM_ASM_) - -/** - * @brief Port-related initialization code. - */ -static inline void port_init(void) { - -} - -/** - * @brief Returns a word encoding the current interrupts status. - * - * @return The interrupts status. - */ -static inline syssts_t port_get_irq_status(void) { - - return 0; -} - -/** - * @brief Checks the interrupt status. - * - * @param[in] sts the interrupt status word - * - * @return The interrupt status. - * @retvel false the word specified a disabled interrupts status. - * @retvel true the word specified an enabled interrupts status. - */ -static inline bool port_irq_enabled(syssts_t sts) { - - return false; -} - -/** - * @brief Determines the current execution context. - * - * @return The execution context. - * @retval false not running in ISR mode. - * @retval true running in ISR mode. - */ -static inline bool port_is_isr_context(void) { - - return false; -} - -/** - * @brief Kernel-lock action. - */ -static inline void port_lock(void) { - - asm volatile ("cli" : : : "memory"); -} - -/** - * @brief Kernel-unlock action. - */ -static inline void port_unlock(void) { - - asm volatile ("sei" : : : "memory"); -} - -/** - * @brief Kernel-lock action from an interrupt handler. - * @note This function is empty in this port. - */ -static inline void port_lock_from_isr(void) { - -} - -/** - * @brief Kernel-unlock action from an interrupt handler. - * @note This function is empty in this port. - */ -static inline void port_unlock_from_isr(void) { - -} - -/** - * @brief Disables all the interrupt sources. - */ -static inline void port_disable(void) { - - asm volatile ("cli" : : : "memory"); -} - -/** - * @brief Disables the interrupt sources below kernel-level priority. - */ -static inline void port_suspend(void) { - - asm volatile ("cli" : : : "memory"); -} - -/** - * @brief Enables all the interrupt sources. - */ -static inline void port_enable(void) { - - asm volatile ("sei" : : : "memory"); -} - -/** - * @brief Enters an architecture-dependent IRQ-waiting mode. - * @details The function is meant to return when an interrupt becomes pending. - * The simplest implementation is an empty function or macro but this - * would not take advantage of architecture-specific power saving - * modes. - */ -static inline void port_wait_for_interrupt(void) { - - asm volatile ("sleep" : : : "memory"); -} - -/** - * @brief Returns the current value of the realtime counter. - * - * @return The realtime counter value. - */ -static inline rtcnt_t port_rt_get_counter_value(void) { - - return 0; -} - -#endif /* !defined(_FROM_ASM_) */ - -/*===========================================================================*/ -/* Module late inclusions. */ -/*===========================================================================*/ - -#if !defined(_FROM_ASM_) - -#if NIL_CFG_ST_TIMEDELTA > 0 -#if !PORT_USE_ALT_TIMER -#include "nilcore_timer.h" -#else /* PORT_USE_ALT_TIMER */ -#include "nilcore_timer_alt.h" -#endif /* PORT_USE_ALT_TIMER */ -#endif /* NIL_CFG_ST_TIMEDELTA > 0 */ - -#endif /* !defined(_FROM_ASM_) */ - -#endif /* _NILCORE_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/nil/ports/AVR/nilcore_timer.h b/firmware/ChibiOS_16/os/nil/ports/AVR/nilcore_timer.h deleted file mode 100644 index b6bf158813..0000000000 --- a/firmware/ChibiOS_16/os/nil/ports/AVR/nilcore_timer.h +++ /dev/null @@ -1,124 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file AVR/nilcore_timer.h - * @brief System timer header file. - * - * @addtogroup AVR_TIMER - * @{ - */ - -#ifndef _NILCORE_TIMER_H_ -#define _NILCORE_TIMER_H_ - -/* This is the only header in the HAL designed to be include-able alone.*/ -#include "st.h" - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -/** - * @brief Starts the alarm. - * @note Makes sure that no spurious alarms are triggered after - * this call. - * - * @param[in] time the time to be set for the first alarm - * - * @notapi - */ -static inline void port_timer_start_alarm(systime_t time) { - - stStartAlarm(time); -} - -/** - * @brief Stops the alarm interrupt. - * - * @notapi - */ -static inline void port_timer_stop_alarm(void) { - - stStopAlarm(); -} - -/** - * @brief Sets the alarm time. - * - * @param[in] time the time to be set for the next alarm - * - * @notapi - */ -static inline void port_timer_set_alarm(systime_t time) { - - stSetAlarm(time); -} - -/** - * @brief Returns the system time. - * - * @return The system time. - * - * @notapi - */ -static inline systime_t port_timer_get_time(void) { - - return stGetCounter(); -} - -/** - * @brief Returns the current alarm time. - * - * @return The currently set alarm time. - * - * @notapi - */ -static inline systime_t port_timer_get_alarm(void) { - - return stGetAlarm(); -} - -#endif /* _NILCORE_TIMER_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/nil/ports/e200/compilers/GCC/ivor.s b/firmware/ChibiOS_16/os/nil/ports/e200/compilers/GCC/ivor.s deleted file mode 100644 index 9e3c974536..0000000000 --- a/firmware/ChibiOS_16/os/nil/ports/e200/compilers/GCC/ivor.s +++ /dev/null @@ -1,234 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file ivor.s - * @brief Kernel ISRs. - * - * @addtogroup PPC_GCC_CORE - * @{ - */ - -#if !defined(FALSE) || defined(__DOXYGEN__) -#define FALSE 0 -#endif - -#if !defined(TRUE) || defined(__DOXYGEN__) -#define TRUE 1 -#endif - -/* - * Imports the PPC configuration headers. - */ -#define _FROM_ASM_ -#include "nilconf.h" -#include "nilcore.h" - -#if !defined(__DOXYGEN__) - - .section .handlers, "ax" - -#if PPC_SUPPORTS_DECREMENTER - /* - * _IVOR10 handler (Book-E decrementer). - */ - .align 4 - .globl _IVOR10 - .type _IVOR10, @function -_IVOR10: - /* Saving the external context (port_extctx structure).*/ - stwu %sp, -80(%sp) -#if PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI - e_stmvsrrw 8(%sp) /* Saves PC, MSR. */ - e_stmvsprw 16(%sp) /* Saves CR, LR, CTR, XER. */ - e_stmvgprw 32(%sp) /* Saves GPR0, GPR3...GPR12. */ -#else /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */ - stw %r0, 32(%sp) /* Saves GPR0. */ - mfSRR0 %r0 - stw %r0, 8(%sp) /* Saves PC. */ - mfSRR1 %r0 - stw %r0, 12(%sp) /* Saves MSR. */ - mfCR %r0 - stw %r0, 16(%sp) /* Saves CR. */ - mfLR %r0 - stw %r0, 20(%sp) /* Saves LR. */ - mfCTR %r0 - stw %r0, 24(%sp) /* Saves CTR. */ - mfXER %r0 - stw %r0, 28(%sp) /* Saves XER. */ - stw %r3, 36(%sp) /* Saves GPR3...GPR12. */ - stw %r4, 40(%sp) - stw %r5, 44(%sp) - stw %r6, 48(%sp) - stw %r7, 52(%sp) - stw %r8, 56(%sp) - stw %r9, 60(%sp) - stw %r10, 64(%sp) - stw %r11, 68(%sp) - stw %r12, 72(%sp) -#endif /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */ - - /* Increasing the SPGR0 register.*/ - mfspr %r0, 272 - eaddi %r0, %r0, 1 - mtspr 272, %r0 - - /* Reset DIE bit in TSR register.*/ - lis %r3, 0x0800 /* DIS bit mask. */ - mtspr 336, %r3 /* TSR register. */ - - /* Restoring pre-IRQ MSR register value.*/ - mfSRR1 %r0 -#if !PPC_USE_IRQ_PREEMPTION - /* No preemption, keeping EE disabled.*/ - se_bclri %r0, 16 /* EE = bit 16. */ -#endif - mtMSR %r0 - - /* System tick handler invocation.*/ - bl chSysTimerHandlerI - -#if PPC_USE_IRQ_PREEMPTION - /* Prevents preemption again.*/ - wrteei 0 -#endif - - /* Jumps to the common IVOR epilogue code.*/ - b _ivor_exit -#endif /* PPC_SUPPORTS_DECREMENTER */ - - /* - * _IVOR4 handler (Book-E external interrupt). - */ - .align 4 - .globl _IVOR4 - .type _IVOR4, @function -_IVOR4: - /* Saving the external context (port_extctx structure).*/ - stwu %sp, -80(%sp) -#if PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI - e_stmvsrrw 8(%sp) /* Saves PC, MSR. */ - e_stmvsprw 16(%sp) /* Saves CR, LR, CTR, XER. */ - e_stmvgprw 32(%sp) /* Saves GPR0, GPR3...GPR12. */ -#else /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */ - stw %r0, 32(%sp) /* Saves GPR0. */ - mfSRR0 %r0 - stw %r0, 8(%sp) /* Saves PC. */ - mfSRR1 %r0 - stw %r0, 12(%sp) /* Saves MSR. */ - mfCR %r0 - stw %r0, 16(%sp) /* Saves CR. */ - mfLR %r0 - stw %r0, 20(%sp) /* Saves LR. */ - mfCTR %r0 - stw %r0, 24(%sp) /* Saves CTR. */ - mfXER %r0 - stw %r0, 28(%sp) /* Saves XER. */ - stw %r3, 36(%sp) /* Saves GPR3...GPR12. */ - stw %r4, 40(%sp) - stw %r5, 44(%sp) - stw %r6, 48(%sp) - stw %r7, 52(%sp) - stw %r8, 56(%sp) - stw %r9, 60(%sp) - stw %r10, 64(%sp) - stw %r11, 68(%sp) - stw %r12, 72(%sp) -#endif /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */ - - /* Increasing the SPGR0 register.*/ - mfspr %r0, 272 - eaddi %r0, %r0, 1 - mtspr 272, %r0 - - /* Software vector address from the INTC register.*/ - lis %r3, INTC_IACKR_ADDR@h - ori %r3, %r3, INTC_IACKR_ADDR@l - lwz %r3, 0(%r3) /* IACKR register value. */ - lwz %r3, 0(%r3) - mtCTR %r3 /* Software handler address. */ - - /* Restoring pre-IRQ MSR register value.*/ - mfSRR1 %r0 -#if !PPC_USE_IRQ_PREEMPTION - /* No preemption, keeping EE disabled.*/ - se_bclri %r0, 16 /* EE = bit 16. */ -#endif - mtMSR %r0 - - /* Exectes the software handler.*/ - bctrl - -#if PPC_USE_IRQ_PREEMPTION - /* Prevents preemption again.*/ - wrteei 0 -#endif - - /* Informs the INTC that the interrupt has been served.*/ - mbar 0 - lis %r3, INTC_EOIR_ADDR@h - ori %r3, %r3, INTC_EOIR_ADDR@l - stw %r3, 0(%r3) /* Writing any value should do. */ - - /* Common IVOR epilogue code, context restore.*/ - .globl _ivor_exit -_ivor_exit: - /* Decreasing the SPGR0 register.*/ - mfspr %r0, 272 - eaddi %r0, %r0, -1 - mtspr 272, %r0 - - bl chSchRescheduleS - - /* Restoring the external context.*/ -#if PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI - e_lmvgprw 32(%sp) /* Restores GPR0, GPR3...GPR12. */ - e_lmvsprw 16(%sp) /* Restores CR, LR, CTR, XER. */ - e_lmvsrrw 8(%sp) /* Restores PC, MSR. */ -#else /*!(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */ - lwz %r3, 36(%sp) /* Restores GPR3...GPR12. */ - lwz %r4, 40(%sp) - lwz %r5, 44(%sp) - lwz %r6, 48(%sp) - lwz %r7, 52(%sp) - lwz %r8, 56(%sp) - lwz %r9, 60(%sp) - lwz %r10, 64(%sp) - lwz %r11, 68(%sp) - lwz %r12, 72(%sp) - lwz %r0, 8(%sp) - mtSRR0 %r0 /* Restores PC. */ - lwz %r0, 12(%sp) - mtSRR1 %r0 /* Restores MSR. */ - lwz %r0, 16(%sp) - mtCR %r0 /* Restores CR. */ - lwz %r0, 20(%sp) - mtLR %r0 /* Restores LR. */ - lwz %r0, 24(%sp) - mtCTR %r0 /* Restores CTR. */ - lwz %r0, 28(%sp) - mtXER %r0 /* Restores XER. */ - lwz %r0, 32(%sp) /* Restores GPR0. */ -#endif /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */ - addi %sp, %sp, 80 /* Back to the previous frame. */ - rfi - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/nil/ports/e200/compilers/GCC/mk/port_spc560bcxx.mk b/firmware/ChibiOS_16/os/nil/ports/e200/compilers/GCC/mk/port_spc560bcxx.mk deleted file mode 100644 index e4cb9085d1..0000000000 --- a/firmware/ChibiOS_16/os/nil/ports/e200/compilers/GCC/mk/port_spc560bcxx.mk +++ /dev/null @@ -1,14 +0,0 @@ -# List of the ChibiOS/NIL e200z0 SPC560BCxx port files. -PORTSRC = ${CHIBIOS}/os/nil/ports/e200/nilcore.c - -PORTASM = $(CHIBIOS)/os/common/ports/e200/devices/SPC560BCxx/boot.s \ - $(CHIBIOS)/os/common/ports/e200/compilers/GCC/vectors.s \ - $(CHIBIOS)/os/common/ports/e200/compilers/GCC/crt0.s \ - $(CHIBIOS)/os/nil/ports/e200/compilers/GCC/ivor.s - -PORTINC = ${CHIBIOS}/os/common/ports/e200/compilers/GCC \ - ${CHIBIOS}/os/common/ports/e200/devices/SPC560BCxx \ - ${CHIBIOS}/os/nil/ports/e200 \ - ${CHIBIOS}/os/nil/ports/e200/compilers/GCC - -PORTLD = ${CHIBIOS}/os/common/ports/e200/compilers/GCC/ld diff --git a/firmware/ChibiOS_16/os/nil/ports/e200/compilers/GCC/mk/port_spc560bxx.mk b/firmware/ChibiOS_16/os/nil/ports/e200/compilers/GCC/mk/port_spc560bxx.mk deleted file mode 100644 index 81df8226d9..0000000000 --- a/firmware/ChibiOS_16/os/nil/ports/e200/compilers/GCC/mk/port_spc560bxx.mk +++ /dev/null @@ -1,14 +0,0 @@ -# List of the ChibiOS/NIL e200z0 SPC560Bxx port files. -PORTSRC = ${CHIBIOS}/os/nil/ports/e200/nilcore.c - -PORTASM = $(CHIBIOS)/os/common/ports/e200/devices/SPC560Bxx/boot.s \ - $(CHIBIOS)/os/common/ports/e200/compilers/GCC/vectors.s \ - $(CHIBIOS)/os/common/ports/e200/compilers/GCC/crt0.s \ - $(CHIBIOS)/os/nil/ports/e200/compilers/GCC/ivor.s - -PORTINC = ${CHIBIOS}/os/common/ports/e200/compilers/GCC \ - ${CHIBIOS}/os/common/ports/e200/devices/SPC560Bxx \ - ${CHIBIOS}/os/nil/ports/e200 \ - ${CHIBIOS}/os/nil/ports/e200/compilers/GCC - -PORTLD = ${CHIBIOS}/os/common/ports/e200/compilers/GCC/ld diff --git a/firmware/ChibiOS_16/os/nil/ports/e200/compilers/GCC/mk/port_spc560dxx.mk b/firmware/ChibiOS_16/os/nil/ports/e200/compilers/GCC/mk/port_spc560dxx.mk deleted file mode 100644 index 8b7a659310..0000000000 --- a/firmware/ChibiOS_16/os/nil/ports/e200/compilers/GCC/mk/port_spc560dxx.mk +++ /dev/null @@ -1,14 +0,0 @@ -# List of the ChibiOS/NIL e200z0 SPC560Dxx port files. -PORTSRC = ${CHIBIOS}/os/nil/ports/e200/nilcore.c - -PORTASM = $(CHIBIOS)/os/common/ports/e200/devices/SPC560Dxx/boot.s \ - $(CHIBIOS)/os/common/ports/e200/compilers/GCC/vectors.s \ - $(CHIBIOS)/os/common/ports/e200/compilers/GCC/crt0.s \ - $(CHIBIOS)/os/nil/ports/e200/compilers/GCC/ivor.s - -PORTINC = ${CHIBIOS}/os/common/ports/e200/compilers/GCC \ - ${CHIBIOS}/os/common/ports/e200/devices/SPC560Dxx \ - ${CHIBIOS}/os/nil/ports/e200 \ - ${CHIBIOS}/os/nil/ports/e200/compilers/GCC - -PORTLD = ${CHIBIOS}/os/common/ports/e200/compilers/GCC/ld diff --git a/firmware/ChibiOS_16/os/nil/ports/e200/compilers/GCC/mk/port_spc560pxx.mk b/firmware/ChibiOS_16/os/nil/ports/e200/compilers/GCC/mk/port_spc560pxx.mk deleted file mode 100644 index 68eee6455b..0000000000 --- a/firmware/ChibiOS_16/os/nil/ports/e200/compilers/GCC/mk/port_spc560pxx.mk +++ /dev/null @@ -1,14 +0,0 @@ -# List of the ChibiOS/NIL e200z0 SPC560Pxx port files. -PORTSRC = ${CHIBIOS}/os/nil/ports/e200/nilcore.c - -PORTASM = $(CHIBIOS)/os/common/ports/e200/devices/SPC560Pxx/boot.s \ - $(CHIBIOS)/os/common/ports/e200/compilers/GCC/vectors.s \ - $(CHIBIOS)/os/common/ports/e200/compilers/GCC/crt0.s \ - $(CHIBIOS)/os/nil/ports/e200/compilers/GCC/ivor.s - -PORTINC = ${CHIBIOS}/os/common/ports/e200/compilers/GCC \ - ${CHIBIOS}/os/common/ports/e200/devices/SPC560Pxx \ - ${CHIBIOS}/os/nil/ports/e200 \ - ${CHIBIOS}/os/nil/ports/e200/compilers/GCC - -PORTLD = ${CHIBIOS}/os/common/ports/e200/compilers/GCC/ld diff --git a/firmware/ChibiOS_16/os/nil/ports/e200/compilers/GCC/mk/port_spc563mxx.mk b/firmware/ChibiOS_16/os/nil/ports/e200/compilers/GCC/mk/port_spc563mxx.mk deleted file mode 100644 index bb654ecdc9..0000000000 --- a/firmware/ChibiOS_16/os/nil/ports/e200/compilers/GCC/mk/port_spc563mxx.mk +++ /dev/null @@ -1,14 +0,0 @@ -# List of the ChibiOS/NIL e200z3 SPC563Mxx port files. -PORTSRC = ${CHIBIOS}/os/nil/ports/e200/nilcore.c - -PORTASM = $(CHIBIOS)/os/common/ports/e200/devices/SPC563Mxx/boot.s \ - $(CHIBIOS)/os/common/ports/e200/compilers/GCC/vectors.s \ - $(CHIBIOS)/os/common/ports/e200/compilers/GCC/crt0.s \ - $(CHIBIOS)/os/nil/ports/e200/compilers/GCC/ivor.s - -PORTINC = ${CHIBIOS}/os/common/ports/e200/compilers/GCC \ - ${CHIBIOS}/os/common/ports/e200/devices/SPC563Mxx \ - ${CHIBIOS}/os/nil/ports/e200 \ - ${CHIBIOS}/os/nil/ports/e200/compilers/GCC - -PORTLD = ${CHIBIOS}/os/common/ports/e200/compilers/GCC/ld diff --git a/firmware/ChibiOS_16/os/nil/ports/e200/compilers/GCC/mk/port_spc564axx.mk b/firmware/ChibiOS_16/os/nil/ports/e200/compilers/GCC/mk/port_spc564axx.mk deleted file mode 100644 index ffd0147f46..0000000000 --- a/firmware/ChibiOS_16/os/nil/ports/e200/compilers/GCC/mk/port_spc564axx.mk +++ /dev/null @@ -1,14 +0,0 @@ -# List of the ChibiOS/NIL e200z4 SPC564Axx port files. -PORTSRC = ${CHIBIOS}/os/nil/ports/e200/nilcore.c - -PORTASM = $(CHIBIOS)/os/common/ports/e200/devices/SPC564Axx/boot.s \ - $(CHIBIOS)/os/common/ports/e200/compilers/GCC/vectors.s \ - $(CHIBIOS)/os/common/ports/e200/compilers/GCC/crt0.s \ - $(CHIBIOS)/os/nil/ports/e200/compilers/GCC/ivor.s - -PORTINC = ${CHIBIOS}/os/common/ports/e200/compilers/GCC \ - ${CHIBIOS}/os/common/ports/e200/devices/SPC564Axx \ - ${CHIBIOS}/os/nil/ports/e200 \ - ${CHIBIOS}/os/nil/ports/e200/compilers/GCC - -PORTLD = ${CHIBIOS}/os/common/ports/e200/compilers/GCC/ld diff --git a/firmware/ChibiOS_16/os/nil/ports/e200/compilers/GCC/mk/port_spc56ecxx.mk b/firmware/ChibiOS_16/os/nil/ports/e200/compilers/GCC/mk/port_spc56ecxx.mk deleted file mode 100644 index 218b2b505a..0000000000 --- a/firmware/ChibiOS_16/os/nil/ports/e200/compilers/GCC/mk/port_spc56ecxx.mk +++ /dev/null @@ -1,14 +0,0 @@ -# List of the ChibiOS/NIL e200z4 SPC56ECxx port files. -PORTSRC = ${CHIBIOS}/os/nil/ports/e200/nilcore.c - -PORTASM = $(CHIBIOS)/os/common/ports/e200/devices/SPC56ECxx/boot.s \ - $(CHIBIOS)/os/common/ports/e200/compilers/GCC/vectors.s \ - $(CHIBIOS)/os/common/ports/e200/compilers/GCC/crt0.s \ - $(CHIBIOS)/os/nil/ports/e200/compilers/GCC/ivor.s - -PORTINC = ${CHIBIOS}/os/common/ports/e200/compilers/GCC \ - ${CHIBIOS}/os/common/ports/e200/devices/SPC56ECxx \ - ${CHIBIOS}/os/nil/ports/e200 \ - ${CHIBIOS}/os/nil/ports/e200/compilers/GCC - -PORTLD = ${CHIBIOS}/os/common/ports/e200/compilers/GCC/ld diff --git a/firmware/ChibiOS_16/os/nil/ports/e200/compilers/GCC/mk/port_spc56elxx.mk b/firmware/ChibiOS_16/os/nil/ports/e200/compilers/GCC/mk/port_spc56elxx.mk deleted file mode 100644 index 5e8bf216de..0000000000 --- a/firmware/ChibiOS_16/os/nil/ports/e200/compilers/GCC/mk/port_spc56elxx.mk +++ /dev/null @@ -1,14 +0,0 @@ -# List of the ChibiOS/NIL e200z4 SPC56ELxx port files. -PORTSRC = ${CHIBIOS}/os/nil/ports/e200/nilcore.c - -PORTASM = $(CHIBIOS)/os/common/ports/e200/devices/SPC56ELxx/boot.s \ - $(CHIBIOS)/os/common/ports/e200/compilers/GCC/vectors.s \ - $(CHIBIOS)/os/common/ports/e200/compilers/GCC/crt0.s \ - $(CHIBIOS)/os/nil/ports/e200/compilers/GCC/ivor.s - -PORTINC = ${CHIBIOS}/os/common/ports/e200/compilers/GCC \ - ${CHIBIOS}/os/common/ports/e200/devices/SPC56ELxx \ - ${CHIBIOS}/os/nil/ports/e200 \ - ${CHIBIOS}/os/nil/ports/e200/compilers/GCC - -PORTLD = ${CHIBIOS}/os/common/ports/e200/compilers/GCC/ld diff --git a/firmware/ChibiOS_16/os/nil/ports/e200/compilers/GCC/mk/port_spc57emxx.mk b/firmware/ChibiOS_16/os/nil/ports/e200/compilers/GCC/mk/port_spc57emxx.mk deleted file mode 100644 index ecac513e52..0000000000 --- a/firmware/ChibiOS_16/os/nil/ports/e200/compilers/GCC/mk/port_spc57emxx.mk +++ /dev/null @@ -1,14 +0,0 @@ -# List of the ChibiOS/NIL e200z4 SPC57EMxx port files. -PORTSRC = ${CHIBIOS}/os/nil/ports/e200/nilcore.c - -PORTASM = $(CHIBIOS)/os/common/ports/e200/devices/SPC57EMxx/boot.s \ - $(CHIBIOS)/os/common/ports/e200/compilers/GCC/vectors.s \ - $(CHIBIOS)/os/common/ports/e200/compilers/GCC/crt0.s \ - $(CHIBIOS)/os/nil/ports/e200/compilers/GCC/ivor.s - -PORTINC = ${CHIBIOS}/os/common/ports/e200/compilers/GCC \ - ${CHIBIOS}/os/common/ports/e200/devices/SPC57EMxx \ - ${CHIBIOS}/os/nil/ports/e200 \ - ${CHIBIOS}/os/nil/ports/e200/compilers/GCC - -PORTLD = ${CHIBIOS}/os/common/ports/e200/compilers/GCC/ld diff --git a/firmware/ChibiOS_16/os/nil/ports/e200/compilers/GCC/niltypes.h b/firmware/ChibiOS_16/os/nil/ports/e200/compilers/GCC/niltypes.h deleted file mode 100644 index b4fc98b2e8..0000000000 --- a/firmware/ChibiOS_16/os/nil/ports/e200/compilers/GCC/niltypes.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file e200/compilers/GCC/niltypes.h - * @brief Power e200 port system types. - * - * @addtogroup PPC_GCC_CORE - * @{ - */ - -#ifndef _NILTYPES_H_ -#define _NILTYPES_H_ - -#include -#include -#include - -/** - * @name Common constants - */ -/** - * @brief Generic 'false' boolean constant. - */ -#if !defined(FALSE) || defined(__DOXYGEN__) -#define FALSE 0 -#endif - -/** - * @brief Generic 'true' boolean constant. - */ -#if !defined(TRUE) || defined(__DOXYGEN__) -#define TRUE (!FALSE) -#endif -/** @} */ - -typedef uint32_t syssts_t; /**< System status word. */ -typedef uint32_t rtcnt_t; /**< Realtime counter. */ -typedef uint8_t tstate_t; /**< Thread state. */ -typedef int32_t msg_t; /**< Inter-thread message. */ -typedef uint32_t eventmask_t; /**< Mask of event identifiers. */ -typedef int32_t cnt_t; /**< Generic signed counter. */ -typedef uint32_t ucnt_t; /**< Generic unsigned counter. */ - -/** - * @brief Type of system time. - */ -#if (NIL_CFG_ST_RESOLUTION == 32) || defined(__DOXYGEN__) -typedef uint32_t systime_t; -#else -typedef uint16_t systime_t; -#endif - -/** - * @brief ROM constant modifier. - * @note It is set to use the "const" keyword in this port. - */ -#define ROMCONST const - -/** - * @brief Makes functions not inlineable. - * @note If the compiler does not support such attribute then the - * realtime counter precision could be degraded. - */ -#define NOINLINE __attribute__((noinline)) - -/** - * @brief Optimized thread function declaration macro. - */ -#define PORT_THD_FUNCTION(tname, arg) \ - __attribute__((noreturn)) void tname(void *arg) - -/** - * @brief Packed variable specifier. - */ -#define PACKED_VAR __attribute__((packed)) - -#endif /* _NILTYPES_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/nil/ports/e200/nilcore.c b/firmware/ChibiOS_16/os/nil/ports/e200/nilcore.c deleted file mode 100644 index 377fec0988..0000000000 --- a/firmware/ChibiOS_16/os/nil/ports/e200/nilcore.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file templates/nilcore.c - * @brief Port code. - * - * @addtogroup NIL_CORE - * @{ - */ - -#include "nil.h" - -/*===========================================================================*/ -/* Module local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -/** - * @brief Performs a context switch between two threads. - * @details This is the most critical code in any port, this function - * is responsible for the context switch between 2 threads. - * @note The implementation of this code affects directly the context - * switch performance so optimize here as much as you can. - */ -#if !defined(__DOXYGEN__) -__attribute__((naked)) -#endif -void port_dummy1(void) { - - asm (".global _port_switch"); - asm ("_port_switch:"); - asm ("subi %sp, %sp, 80"); /* Size of the intctx structure. */ - asm ("mflr %r0"); - asm ("stw %r0, 84(%sp)"); /* LR into the caller frame. */ - asm ("mfcr %r0"); - asm ("stw %r0, 0(%sp)"); /* CR. */ - asm ("stmw %r14, 4(%sp)"); /* GPR14...GPR31. */ - - asm ("stw %sp, 0(%r4)"); /* Store swapped-out stack. */ - asm ("lwz %sp, 0(%r3)"); /* Load swapped-in stack. */ - - asm ("lmw %r14, 4(%sp)"); /* GPR14...GPR31. */ - asm ("lwz %r0, 0(%sp)"); /* CR. */ - asm ("mtcr %r0"); - asm ("lwz %r0, 84(%sp)"); /* LR from the caller frame. */ - asm ("mtlr %r0"); - asm ("addi %sp, %sp, 80"); /* Size of the intctx structure. */ - asm ("blr"); -} - -/** - * @brief Start a thread by invoking its work function. - * @details If the work function returns @p chThdExit() is automatically - * invoked. - */ -#if !defined(__DOXYGEN__) -__attribute__((naked)) -#endif -void port_dummy2(void) { - - asm (".global _port_thread_start"); - asm ("_port_thread_start:"); - chSysUnlock(); - asm ("mr %r3, %r31"); /* Thread parameter. */ - asm ("mtctr %r30"); - asm ("bctrl"); /* Invoke thread function. */ - asm ("li %r0, 0"); - asm ("bl chSysHalt"); /* Thread termination on exit. */ -} - -/** @} */ diff --git a/firmware/ChibiOS_16/os/nil/ports/e200/nilcore.h b/firmware/ChibiOS_16/os/nil/ports/e200/nilcore.h deleted file mode 100644 index dc7947d393..0000000000 --- a/firmware/ChibiOS_16/os/nil/ports/e200/nilcore.h +++ /dev/null @@ -1,555 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file templates/nilcore.h - * @brief Port macros and structures. - * - * @addtogroup NIL_CORE - * @{ - */ - -#ifndef _NILCORE_H_ -#define _NILCORE_H_ - -#include "intc.h" - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @name Architecture and Compiler - * @{ - */ -/** - * @brief Macro defining an PPC architecture. - */ -#define PORT_ARCHITECTURE_PPC - -/** - * @brief Macro defining the specific PPC architecture. - */ -#define PORT_ARCHITECTURE_PPC_E200 - -/** - * @brief Name of the implemented architecture. - */ -#define PORT_ARCHITECTURE_NAME "Power Architecture" - -/** - * @brief Compiler name and version. - */ -#if defined(__GNUC__) || defined(__DOXYGEN__) -#define PORT_COMPILER_NAME "GCC " __VERSION__ - -#else -#error "unsupported compiler" -#endif - -/** - * @brief This port supports a realtime counter. - */ -#define PORT_SUPPORTS_RT FALSE -/** @} */ - -/** - * @name E200 core variants - * @{ - */ -#define PPC_VARIANT_e200z0 200 -#define PPC_VARIANT_e200z2 202 -#define PPC_VARIANT_e200z3 203 -#define PPC_VARIANT_e200z4 204 -/** @} */ - -/* Inclusion of the PPC implementation specific parameters.*/ -#include "ppcparams.h" -#include "vectors.h" - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Per-thread stack overhead for interrupts servicing. - * @details This constant is used in the calculation of the correct working - * area size. - */ -#if !defined(PORT_INT_REQUIRED_STACK) || defined(__DOXYGEN__) -#define PORT_INT_REQUIRED_STACK 256 -#endif - -/** - * @brief Enables an alternative timer implementation. - * @details Usually the port uses a timer interface defined in the file - * @p nilcore_timer.h, if this option is enabled then the file - * @p nilcore_timer_alt.h is included instead. - */ -#if !defined(PORT_USE_ALT_TIMER) || defined(__DOXYGEN__) -#define PORT_USE_ALT_TIMER FALSE -#endif - -/** - * @brief Use VLE instruction set. - * @note This parameter is usually set in the Makefile. - */ -#if !defined(PPC_USE_VLE) || defined(__DOXYGEN__) -#define PPC_USE_VLE TRUE -#endif - -/** - * @brief Enables the use of the @p WFI instruction. - */ -#if !defined(PPC_ENABLE_WFI_IDLE) || defined(__DOXYGEN__) -#define PPC_ENABLE_WFI_IDLE FALSE -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if PPC_USE_VLE && !PPC_SUPPORTS_VLE -#error "the selected MCU does not support VLE instructions set" -#endif - -#if !PPC_USE_VLE && !PPC_SUPPORTS_BOOKE -#error "the selected MCU does not support BookE instructions set" -#endif - -/** - * @brief Name of the architecture variant. - */ -#if (PPC_VARIANT == PPC_VARIANT_e200z0) || defined(__DOXYGEN__) -#define PORT_CORE_VARIANT_NAME "e200z0" -#elif PPC_VARIANT == PPC_VARIANT_e200z2 -#define PORT_CORE_VARIANT_NAME "e200z2" -#elif PPC_VARIANT == PPC_VARIANT_e200z3 -#define PORT_CORE_VARIANT_NAME "e200z3" -#elif PPC_VARIANT == PPC_VARIANT_e200z4 -#define PORT_CORE_VARIANT_NAME "e200z4" -#else -#error "unknown or unsupported PowerPC variant specified" -#endif - -/** - * @brief Port-specific information string. - */ -#if PPC_USE_VLE -#define PORT_INFO "VLE mode" -#else -#define PORT_INFO "Book-E mode" -#endif - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/* The following code is not processed when the file is included from an - asm module.*/ -#if !defined(_FROM_ASM_) - -/** - * @brief Type of stack and memory alignment enforcement. - */ -typedef uint64_t stkalign_t; - -/** - * @brief Generic PPC register. - */ -typedef void *regppc_t; - -/** - * @brief Mandatory part of a stack frame. - */ -struct port_eabi_frame { - uint32_t slink; /**< Stack back link. */ - uint32_t shole; /**< Stack hole for LR storage. */ -}; - -/** - * @brief Interrupt saved context. - * @details This structure represents the stack frame saved during a - * preemption-capable interrupt handler. - * @note R2 and R13 are not saved because those are assumed to be immutable - * during the system life cycle. - */ -struct port_extctx { - struct port_eabi_frame frame; - /* Start of the e_stmvsrrw frame (offset 8).*/ - regppc_t pc; - regppc_t msr; - /* Start of the e_stmvsprw frame (offset 16).*/ - regppc_t cr; - regppc_t lr; - regppc_t ctr; - regppc_t xer; - /* Start of the e_stmvgprw frame (offset 32).*/ - regppc_t r0; - regppc_t r3; - regppc_t r4; - regppc_t r5; - regppc_t r6; - regppc_t r7; - regppc_t r8; - regppc_t r9; - regppc_t r10; - regppc_t r11; - regppc_t r12; - regppc_t padding; - }; - -/** - * @brief System saved context. - * @details This structure represents the inner stack frame during a context - * switching. - * @note R2 and R13 are not saved because those are assumed to be immutable - * during the system life cycle. - * @note LR is stored in the caller context so it is not present in this - * structure. - */ -struct port_intctx { - regppc_t cr; /* Part of it is not volatile... */ - regppc_t r14; - regppc_t r15; - regppc_t r16; - regppc_t r17; - regppc_t r18; - regppc_t r19; - regppc_t r20; - regppc_t r21; - regppc_t r22; - regppc_t r23; - regppc_t r24; - regppc_t r25; - regppc_t r26; - regppc_t r27; - regppc_t r28; - regppc_t r29; - regppc_t r30; - regppc_t r31; - regppc_t padding; -}; - -#endif /* !defined(_FROM_ASM_) */ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @brief Platform dependent thread stack setup. - * @details This code usually setup the context switching frame represented - * by an @p port_intctx structure. - */ -#define PORT_SETUP_CONTEXT(tp, wend, pf, arg) { \ - uint8_t *sp = (uint8_t *)(wend) - \ - sizeof(struct port_eabi_frame); \ - ((struct port_eabi_frame *)sp)->slink = 0; \ - ((struct port_eabi_frame *)sp)->shole = (uint32_t)_port_thread_start; \ - (tp)->ctxp = (struct port_intctx *)(sp - sizeof(struct port_intctx)); \ - (tp)->ctxp->r31 = (regppc_t)(arg); \ - (tp)->ctxp->r30 = (regppc_t)(pf); \ -} - -/** - * @brief Computes the thread working area global size. - * @note There is no need to perform alignments in this macro. - */ -#define PORT_WA_SIZE(n) (sizeof(struct port_intctx) + \ - sizeof(struct port_extctx) + \ - (n) + (PORT_INT_REQUIRED_STACK)) - -/** - * @brief IRQ prologue code. - * @details This macro must be inserted at the start of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_PROLOGUE() - -/** - * @brief IRQ epilogue code. - * @details This macro must be inserted at the end of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_EPILOGUE() - -/** - * @brief IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_IRQ_HANDLER(id) void id(void) - -/** - * @brief Fast IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_FAST_IRQ_HANDLER(id) void id(void) - -/** - * @brief Priority level verification macro. - */ -#define PORT_IRQ_IS_VALID_PRIORITY(n) \ - (((n) >= 0U) && ((n) < INTC_PRIORITY_LEVELS)) - -/** - * @brief Priority level verification macro. - */ -#define PORT_IRQ_IS_VALID_KERNEL_PRIORITY(n) \ - (((n) >= 0U) && ((n) < INTC_PRIORITY_LEVELS)) - -/** - * @brief Performs a context switch between two threads. - * @details This is the most critical code in any port, this function - * is responsible for the context switch between 2 threads. - * @note The implementation of this code affects directly the context - * switch performance so optimize here as much as you can. - * - * @param[in] ntp the thread to be switched in - * @param[in] otp the thread to be switched out - */ -#if !NIL_CFG_ENABLE_STACK_CHECK || defined(__DOXYGEN__) -#define port_switch(ntp, otp) _port_switch(ntp, otp) -#else -#define port_switch(ntp, otp) { \ - register struct port_intctx *sp asm ("%r1"); \ - if ((stkalign_t *)(sp - 1) < otp->stklim) \ - chSysHalt("stack overflow"); \ - _port_switch(ntp, otp); \ -} -#endif - -/** - * @brief Writes to a special register. - * - * @param[in] spr special register number - * @param[in] val value to be written, must be an automatic variable - */ -#define port_write_spr(spr, val) \ - asm volatile ("mtspr %[p0], %[p1]" : : [p0] "n" (spr), [p1] "r" (val)) - -/** - * @brief Writes to a special register. - * - * @param[in] spr special register number - * @param[in] val returned value, must be an automatic variable - */ -#define port_read_spr(spr, val) \ - asm volatile ("mfspr %[p0], %[p1]" : [p0] "=r" (val) : [p1] "n" (spr)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/* The following code is not processed when the file is included from an - asm module.*/ -#if !defined(_FROM_ASM_) - -#ifdef __cplusplus -extern "C" { -#endif - void _port_switch(thread_t *ntp, thread_t *otp); - void _port_thread_start(void); -#ifdef __cplusplus -} -#endif - -#endif /* !defined(_FROM_ASM_) */ - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -/* The following code is not processed when the file is included from an - asm module.*/ -#if !defined(_FROM_ASM_) - -/** - * @brief Port-related initialization code. - */ -static inline void port_init(void) { - uint32_t n; - unsigned i; - - /* Initializing the SPRG0 register to zero, it is required for interrupts - handling.*/ - n = 0; - port_write_spr(272, n); - -#if PPC_SUPPORTS_IVORS - /* The CPU supports IVOR registers, the kernel requires IVOR4 and IVOR10 - and the initialization is performed here.*/ - asm volatile ("li %%r3, _IVOR4@l \t\n" - "mtIVOR4 %%r3 \t\n" - "li %%r3, _IVOR10@l \t\n" - "mtIVOR10 %%r3" : : : "r3", "memory"); -#endif - - /* INTC initialization, software vector mode, 4 bytes vectors, starting - at priority 0.*/ - INTC_BCR = 0; - for (i = 0; i < PPC_CORE_NUMBER; i++) { - INTC_CPR(i) = 0; - INTC_IACKR(i) = (uint32_t)_vectors; - } -} - -/** - * @brief Returns a word encoding the current interrupts status. - * - * @return The interrupts status. - */ -static inline syssts_t port_get_irq_status(void) { - uint32_t sts; - - asm volatile ("mfmsr %[p0]" : [p0] "=r" (sts) :); - return sts; -} - -/** - * @brief Checks the interrupt status. - * - * @param[in] sts the interrupt status word - * - * @return The interrupt status. - * @retvel false the word specified a disabled interrupts status. - * @retvel true the word specified an enabled interrupts status. - */ -static inline bool port_irq_enabled(syssts_t sts) { - - return (bool)((sts & (1 << 15)) != 0); -} - -/** - * @brief Determines the current execution context. - * - * @return The execution context. - * @retval false not running in ISR mode. - * @retval true running in ISR mode. - */ -static inline bool port_is_isr_context(void) { - uint32_t sprg0; - - /* The SPRG0 register is increased before entering interrupt handlers and - decreased at the end.*/ - port_read_spr(272, sprg0); - return (bool)(sprg0 > 0); -} - -/** - * @brief Kernel-lock action. - */ -static inline void port_lock(void) { - - asm volatile ("wrteei 0" : : : "memory"); -} - -/** - * @brief Kernel-unlock action. - */ -static inline void port_unlock(void) { - - asm volatile("wrteei 1" : : : "memory"); -} - -/** - * @brief Kernel-lock action from an interrupt handler. - */ -static inline void port_lock_from_isr(void) { - -} - -/** - * @brief Kernel-unlock action from an interrupt handler. - */ -static inline void port_unlock_from_isr(void) { - -} - -/** - * @brief Disables all the interrupt sources. - */ -static inline void port_disable(void) { - - asm volatile ("wrteei 0" : : : "memory"); -} - -/** - * @brief Disables the interrupt sources below kernel-level priority. - */ -static inline void port_suspend(void) { - - asm volatile ("wrteei 0" : : : "memory"); -} - -/** - * @brief Enables all the interrupt sources. - */ -static inline void port_enable(void) { - - asm volatile ("wrteei 1" : : : "memory"); -} - -/** - * @brief Enters an architecture-dependent IRQ-waiting mode. - * @details The function is meant to return when an interrupt becomes pending. - * The simplest implementation is an empty function or macro but this - * would not take advantage of architecture-specific power saving - * modes. - */ -static inline void port_wait_for_interrupt(void) { - -#if PPC_ENABLE_WFI_IDLE - asm volatile ("wait" : : : "memory"); -#endif -} - -/** - * @brief Returns the current value of the realtime counter. - * - * @return The realtime counter value. - */ -static inline rtcnt_t port_rt_get_counter_value(void) { - - return 0; -} - -#endif /* !defined(_FROM_ASM_) */ - -/*===========================================================================*/ -/* Module late inclusions. */ -/*===========================================================================*/ - -#if !defined(_FROM_ASM_) - -#if NIL_CFG_ST_TIMEDELTA > 0 -#if !PORT_USE_ALT_TIMER -#include "nilcore_timer.h" -#else /* PORT_USE_ALT_TIMER */ -#include "nilcore_timer_alt.h" -#endif /* PORT_USE_ALT_TIMER */ -#endif /* NIL_CFG_ST_TIMEDELTA > 0 */ - -#endif /* !defined(_FROM_ASM_) */ - -#endif /* _NILCORE_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/nil/src/nil.c b/firmware/ChibiOS_16/os/nil/src/nil.c deleted file mode 100644 index e95c79de36..0000000000 --- a/firmware/ChibiOS_16/os/nil/src/nil.c +++ /dev/null @@ -1,832 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file nil.c - * @brief Nil RTOS main source file. - * - * @addtogroup NIL_KERNEL - * @{ - */ - -#include "nil.h" - -/*===========================================================================*/ -/* Module local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -/** - * @brief System data structures. - */ -nil_system_t nil; - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -/** - * @brief Initializes the kernel. - * @details Initializes the kernel structures, the current instructions flow - * becomes the idle thread upon return. The idle thread must not - * invoke any kernel primitive able to change state to not runnable. - * @note This function assumes that the @p nil global variable has been - * zeroed by the runtime environment. If this is not the case then - * make sure to clear it before calling this function. - * - * @special - */ -void chSysInit(void) { - thread_t *tp; - const thread_config_t *tcp; - - /* Port layer initialization.*/ - port_init(); - - /* System initialization hook.*/ - NIL_CFG_SYSTEM_INIT_HOOK(); - - /* Iterates through the list of defined threads.*/ - tp = &nil.threads[0]; - tcp = nil_thd_configs; - while (tp < &nil.threads[NIL_CFG_NUM_THREADS]) { -#if NIL_CFG_ENABLE_STACK_CHECK - tp->stklim = (stkalign_t *)tcp->wbase; -#endif - - /* Port dependent thread initialization.*/ - PORT_SETUP_CONTEXT(tp, tcp->wend, tcp->funcp, tcp->arg); - - /* Initialization hook.*/ - NIL_CFG_THREAD_EXT_INIT_HOOK(tp); - - tp++; - tcp++; - } - -#if NIL_CFG_ENABLE_STACK_CHECK - /* The idle thread is a special case because its stack is set up by the - runtime environment.*/ - tp->stklim = THD_IDLE_BASE; -#endif - - /* Runs the highest priority thread, the current one becomes the idle - thread.*/ - nil.current = nil.next = nil.threads; - port_switch(nil.current, tp); - - /* Interrupts enabled for the idle thread.*/ - chSysEnable(); -} - -/** - * @brief Halts the system. - * @details This function is invoked by the operating system when an - * unrecoverable error is detected, for example because a programming - * error in the application code that triggers an assertion while - * in debug mode. - * @note Can be invoked from any system state. - * - * @param[in] reason pointer to an error string - * - * @special - */ -void chSysHalt(const char *reason) { - - port_disable(); - -#if NIL_DBG_ENABLED - nil.dbg_panic_msg = reason; -#else - (void)reason; -#endif - - NIL_CFG_SYSTEM_HALT_HOOK(reason); - - /* Harmless infinite loop.*/ - while (true) { - } -} - -/** - * @brief Time management handler. - * @note This handler has to be invoked by a periodic ISR in order to - * reschedule the waiting threads. - * - * @iclass - */ -void chSysTimerHandlerI(void) { - -#if NIL_CFG_ST_TIMEDELTA == 0 - thread_t *tp = &nil.threads[0]; - nil.systime++; - do { - /* Is the thread in a wait state with timeout?.*/ - if (tp->timeout > (systime_t)0) { - - chDbgAssert(!NIL_THD_IS_READY(tp), "is ready"); - - /* Did the timer reach zero?*/ - if (--tp->timeout == (systime_t)0) { - /* Timeout on semaphores requires a special handling because the - semaphore counter must be incremented.*/ - /*lint -save -e9013 [15.7] There is no else because it is not needed.*/ - if (NIL_THD_IS_WTSEM(tp)) { - tp->u1.semp->cnt++; - } - else if (NIL_THD_IS_SUSP(tp)) { - *tp->u1.trp = NULL; - } - /*lint -restore*/ - (void) chSchReadyI(tp, MSG_TIMEOUT); - } - } - /* Lock released in order to give a preemption chance on those - architectures supporting IRQ preemption.*/ - chSysUnlockFromISR(); - tp++; - chSysLockFromISR(); - } while (tp < &nil.threads[NIL_CFG_NUM_THREADS]); -#else - thread_t *tp = &nil.threads[0]; - systime_t next = (systime_t)0; - - chDbgAssert(nil.nexttime == port_timer_get_alarm(), "time mismatch"); - - do { - /* Is the thread in a wait state with timeout?.*/ - if (tp->timeout > (systime_t)0) { - - chDbgAssert(!NIL_THD_IS_READY(tp), "is ready"); - chDbgAssert(tp->timeout >= (nil.nexttime - nil.lasttime), "skipped one"); - - tp->timeout -= nil.nexttime - nil.lasttime; - if (tp->timeout == (systime_t)0) { - /* Timeout on semaphores requires a special handling because the - semaphore counter must be incremented.*/ - /*lint -save -e9013 [15.7] There is no else because it is not needed.*/ - if (NIL_THD_IS_WTSEM(tp)) { - tp->u1.semp->cnt++; - } - else if (NIL_THD_IS_SUSP(tp)) { - *tp->u1.trp = NULL; - } - /*lint -restore*/ - (void) chSchReadyI(tp, MSG_TIMEOUT); - } - else { - if (tp->timeout <= (systime_t)(next - (systime_t)1)) { - next = tp->timeout; - } - } - } - /* Lock released in order to give a preemption chance on those - architectures supporting IRQ preemption.*/ - chSysUnlockFromISR(); - tp++; - chSysLockFromISR(); - } while (tp < &nil.threads[NIL_CFG_NUM_THREADS]); - nil.lasttime = nil.nexttime; - if (next > (systime_t)0) { - nil.nexttime += next; - port_timer_set_alarm(nil.nexttime); - } - else { - /* No tick event needed.*/ - port_timer_stop_alarm(); - } -#endif -} - -/** - * @brief Unconditionally enters the kernel lock state. - * @note Can be called without previous knowledge of the current lock state. - * The final state is "s-locked". - * - * @special - */ -void chSysUnconditionalLock(void) { - - if (port_irq_enabled(port_get_irq_status())) { - chSysLock(); - } -} - -/** - * @brief Unconditionally leaves the kernel lock state. - * @note Can be called without previous knowledge of the current lock state. - * The final state is "normal". - * - * @special - */ -void chSysUnconditionalUnlock(void) { - - if (!port_irq_enabled(port_get_irq_status())) { - chSysUnlock(); - } -} - -/** - * @brief Returns the execution status and enters a critical zone. - * @details This functions enters into a critical zone and can be called - * from any context. Because its flexibility it is less efficient - * than @p chSysLock() which is preferable when the calling context - * is known. - * @post The system is in a critical zone. - * - * @return The previous system status, the encoding of this - * status word is architecture-dependent and opaque. - * - * @xclass - */ -syssts_t chSysGetStatusAndLockX(void) { - - syssts_t sts = port_get_irq_status(); - if (port_irq_enabled(sts)) { - if (port_is_isr_context()) { - chSysLockFromISR(); - } - else { - chSysLock(); - } - } - return sts; -} - -/** - * @brief Restores the specified execution status and leaves a critical zone. - * @note A call to @p chSchRescheduleS() is automatically performed - * if exiting the critical zone and if not in ISR context. - * - * @param[in] sts the system status to be restored. - * - * @xclass - */ -void chSysRestoreStatusX(syssts_t sts) { - - if (port_irq_enabled(sts)) { - if (port_is_isr_context()) { - chSysUnlockFromISR(); - } - else { - chSchRescheduleS(); - chSysUnlock(); - } - } -} - -#if (PORT_SUPPORTS_RT == TRUE) || defined(__DOXYGEN__) -/** - * @brief Realtime window test. - * @details This function verifies if the current realtime counter value - * lies within the specified range or not. The test takes care - * of the realtime counter wrapping to zero on overflow. - * @note When start==end then the function returns always true because the - * whole time range is specified. - * @note This function is only available if the port layer supports the - * option @p PORT_SUPPORTS_RT. - * - * @param[in] cnt the counter value to be tested - * @param[in] start the start of the time window (inclusive) - * @param[in] end the end of the time window (non inclusive) - * @retval true current time within the specified time window. - * @retval false current time not within the specified time window. - * - * @xclass - */ -bool chSysIsCounterWithinX(rtcnt_t cnt, rtcnt_t start, rtcnt_t end) { - - return (bool)((cnt - start) < (end - start)); -} - -/** - * @brief Polled delay. - * @note The real delay is always few cycles in excess of the specified - * value. - * @note This function is only available if the port layer supports the - * option @p PORT_SUPPORTS_RT. - * - * @param[in] cycles number of cycles - * - * @xclass - */ -void chSysPolledDelayX(rtcnt_t cycles) { - rtcnt_t start = chSysGetRealtimeCounterX(); - rtcnt_t end = start + cycles; - - while (chSysIsCounterWithinX(chSysGetRealtimeCounterX(), start, end)) { - } -} -#endif /* PORT_SUPPORTS_RT == TRUE */ - -/** - * @brief Makes the specified thread ready for execution. - * - * @param[in] tp pointer to the @p thread_t object - * @param[in] msg the wakeup message - * - * @return The same reference passed as parameter. - */ -thread_t *chSchReadyI(thread_t *tp, msg_t msg) { - - chDbgAssert((tp >= nil.threads) && - (tp < &nil.threads[NIL_CFG_NUM_THREADS]), - "pointer out of range"); - chDbgAssert(!NIL_THD_IS_READY(tp), "already ready"); - chDbgAssert(nil.next <= nil.current, "priority ordering"); - - tp->u1.msg = msg; - tp->state = NIL_STATE_READY; - tp->timeout = (systime_t)0; - if (tp < nil.next) { - nil.next = tp; - } - return tp; -} - -/** - * @brief Reschedules if needed. - * - * @sclass - */ -void chSchRescheduleS(void) { - - if (chSchIsRescRequiredI()) { - thread_t *otp = nil.current; - - nil.current = nil.next; - if (otp == &nil.threads[NIL_CFG_NUM_THREADS]) { - NIL_CFG_IDLE_LEAVE_HOOK(); - } - port_switch(nil.next, otp); - } -} - -/** - * @brief Puts the current thread to sleep into the specified state with - * timeout specification. - * @details The thread goes into a sleeping state, if it is not awakened - * explicitly within the specified system time then it is forcibly - * awakened with a @p NIL_MSG_TMO low level message. - * - * @param[in] newstate the new thread state or a semaphore pointer - * @param[in] timeout the number of ticks before the operation timeouts. - * the following special values are allowed: - * - @a TIME_INFINITE no timeout. - * . - * @return The wakeup message. - * @retval NIL_MSG_TMO if a timeout occurred. - * - * @sclass - */ -msg_t chSchGoSleepTimeoutS(tstate_t newstate, systime_t timeout) { - thread_t *ntp, *otp = nil.current; - - chDbgAssert(otp != &nil.threads[NIL_CFG_NUM_THREADS], - "idle cannot sleep"); - - /* Storing the wait object for the current thread.*/ - otp->state = newstate; - -#if NIL_CFG_ST_TIMEDELTA > 0 - if (timeout != TIME_INFINITE) { - systime_t abstime; - - /* TIMEDELTA makes sure to have enough time to reprogram the timer - before the free-running timer counter reaches the selected timeout.*/ - if (timeout < (systime_t)NIL_CFG_ST_TIMEDELTA) { - timeout = (systime_t)NIL_CFG_ST_TIMEDELTA; - } - - /* Absolute time of the timeout event.*/ - abstime = chVTGetSystemTimeX() + timeout; - - if (nil.lasttime == nil.nexttime) { - /* Special case, first thread asking for a timeout.*/ - port_timer_start_alarm(abstime); - nil.nexttime = abstime; - } - else { - /* Special case, there are already other threads with a timeout - activated, evaluating the order.*/ - if (chVTIsTimeWithinX(abstime, nil.lasttime, nil.nexttime)) { - port_timer_set_alarm(abstime); - nil.nexttime = abstime; - } - } - - /* Timeout settings.*/ - otp->timeout = abstime - nil.lasttime; - } -#else - - /* Timeout settings.*/ - otp->timeout = timeout; -#endif - - /* Scanning the whole threads array.*/ - ntp = nil.threads; - while (true) { - /* Is this thread ready to execute?*/ - if (NIL_THD_IS_READY(ntp)) { - nil.current = nil.next = ntp; - if (ntp == &nil.threads[NIL_CFG_NUM_THREADS]) { - NIL_CFG_IDLE_ENTER_HOOK(); - } - port_switch(ntp, otp); - return nil.current->u1.msg; - } - - /* Points to the next thread in lowering priority order.*/ - ntp++; - chDbgAssert(ntp <= &nil.threads[NIL_CFG_NUM_THREADS], - "pointer out of range"); - } -} - -/** - * @brief Sends the current thread sleeping and sets a reference variable. - * @note This function must reschedule, it can only be called from thread - * context. - * - * @param[in] trp a pointer to a thread reference object - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_INFINITE no timeout. - * . - * @return The wake up message. - * - * @sclass - */ -msg_t chThdSuspendTimeoutS(thread_reference_t *trp, systime_t timeout) { - - chDbgAssert(*trp == NULL, "not NULL"); - - *trp = nil.current; - nil.current->u1.trp = trp; - return chSchGoSleepTimeoutS(NIL_STATE_SUSP, timeout); -} - -/** - * @brief Wakes up a thread waiting on a thread reference object. - * @note This function must not reschedule because it can be called from - * ISR context. - * - * @param[in] trp a pointer to a thread reference object - * @param[in] msg the message code - * - * @iclass - */ -void chThdResumeI(thread_reference_t *trp, msg_t msg) { - - if (*trp != NULL) { - thread_reference_t tr = *trp; - - chDbgAssert(NIL_THD_IS_SUSP(tr), "not suspended"); - - *trp = NULL; - (void) chSchReadyI(tr, msg); - } -} - -/** - * @brief Suspends the invoking thread for the specified time. - * - * @param[in] timeout the delay in system ticks - * - * @api - */ -void chThdSleep(systime_t timeout) { - - chSysLock(); - chThdSleepS(timeout); - chSysUnlock(); -} - -/** - * @brief Suspends the invoking thread until the system time arrives to the - * specified value. - * - * @param[in] abstime absolute system time - * - * @api - */ -void chThdSleepUntil(systime_t abstime) { - - chSysLock(); - chThdSleepUntilS(abstime); - chSysUnlock(); -} - -/** - * @brief Performs a wait operation on a semaphore with timeout specification. - * - * @param[in] sp pointer to a @p semaphore_t structure - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return A message specifying how the invoking thread has been - * released from the semaphore. - * @retval NIL_MSG_OK if the thread has not stopped on the semaphore or the - * semaphore has been signaled. - * @retval NIL_MSG_RST if the semaphore has been reset using @p chSemReset(). - * @retval NIL_MSG_TMO if the semaphore has not been signaled or reset within - * the specified timeout. - * - * @api - */ -msg_t chSemWaitTimeout(semaphore_t *sp, systime_t timeout) { - msg_t msg; - - chSysLock(); - msg = chSemWaitTimeoutS(sp, timeout); - chSysUnlock(); - - return msg; -} - -/** - * @brief Performs a wait operation on a semaphore with timeout specification. - * - * @param[in] sp pointer to a @p semaphore_t structure - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return A message specifying how the invoking thread has been - * released from the semaphore. - * @retval NIL_MSG_OK if the thread has not stopped on the semaphore or the - * semaphore has been signaled. - * @retval NIL_MSG_RST if the semaphore has been reset using @p chSemReset(). - * @retval NIL_MSG_TMO if the semaphore has not been signaled or reset within - * the specified timeout. - * - * @sclass - */ -msg_t chSemWaitTimeoutS(semaphore_t *sp, systime_t timeout) { - - /* Note, the semaphore counter is a volatile variable so accesses are - manually optimized.*/ - cnt_t cnt = sp->cnt; - if (cnt <= (cnt_t)0) { - if (TIME_IMMEDIATE == timeout) { - return MSG_TIMEOUT; - } - sp->cnt = cnt - (cnt_t)1; - nil.current->u1.semp = sp; - return chSchGoSleepTimeoutS(NIL_STATE_WTSEM, timeout); - } - sp->cnt = cnt - (cnt_t)1; - return MSG_OK; -} - -/** - * @brief Performs a signal operation on a semaphore. - * - * @param[in] sp pointer to a @p semaphore_t structure - * - * @api - */ -void chSemSignal(semaphore_t *sp) { - - chSysLock(); - chSemSignalI(sp); - chSchRescheduleS(); - chSysUnlock(); -} - -/** - * @brief Performs a signal operation on a semaphore. - * @post This function does not reschedule so a call to a rescheduling - * function must be performed before unlocking the kernel. Note that - * interrupt handlers always reschedule on exit so an explicit - * reschedule must not be performed in ISRs. - * - * @param[in] sp pointer to a @p semaphore_t structure - * - * @iclass - */ -void chSemSignalI(semaphore_t *sp) { - - if (++sp->cnt <= (cnt_t)0) { - thread_reference_t tr = nil.threads; - while (true) { - /* Is this thread waiting on this semaphore?*/ - if (tr->u1.semp == sp) { - - chDbgAssert(NIL_THD_IS_WTSEM(tr), "not waiting"); - - (void) chSchReadyI(tr, MSG_OK); - return; - } - tr++; - - chDbgAssert(tr < &nil.threads[NIL_CFG_NUM_THREADS], - "pointer out of range"); - } - } -} - -/** - * @brief Performs a reset operation on the semaphore. - * @post After invoking this function all the threads waiting on the - * semaphore, if any, are released and the semaphore counter is set - * to the specified, non negative, value. - * - * @param[in] sp pointer to a @p semaphore_t structure - * @param[in] n the new value of the semaphore counter. The value must - * be non-negative. - * - * @api - */ -void chSemReset(semaphore_t *sp, cnt_t n) { - - chSysLock(); - chSemResetI(sp, n); - chSchRescheduleS(); - chSysUnlock(); -} - -/** - * @brief Performs a reset operation on the semaphore. - * @post After invoking this function all the threads waiting on the - * semaphore, if any, are released and the semaphore counter is set - * to the specified, non negative, value. - * @post This function does not reschedule so a call to a rescheduling - * function must be performed before unlocking the kernel. Note that - * interrupt handlers always reschedule on exit so an explicit - * reschedule must not be performed in ISRs. - * - * @param[in] sp pointer to a @p semaphore_t structure - * @param[in] n the new value of the semaphore counter. The value must - * be non-negative. - * - * @iclass - */ -void chSemResetI(semaphore_t *sp, cnt_t n) { - thread_t *tp; - cnt_t cnt; - - cnt = sp->cnt; - sp->cnt = n; - tp = nil.threads; - while (cnt < (cnt_t)0) { - - chDbgAssert(tp < &nil.threads[NIL_CFG_NUM_THREADS], - "pointer out of range"); - - /* Is this thread waiting on this semaphore?*/ - if (tp->u1.semp == sp) { - - chDbgAssert(NIL_THD_IS_WTSEM(tp), "not waiting"); - - cnt++; - (void) chSchReadyI(tp, MSG_RESET); - } - tp++; - } -} - -#if (NIL_CFG_USE_EVENTS == TRUE) || defined(__DOXYGEN__) -/** - * @brief Adds a set of event flags directly to the specified @p thread_t. - * - * @param[in] tp the thread to be signaled - * @param[in] mask the event flags set to be ORed - * - * @api - */ -void chEvtSignal(thread_t *tp, eventmask_t mask) { - - chSysLock(); - chEvtSignalI(tp, mask); - chSchRescheduleS(); - chSysUnlock(); -} - -/** - * @brief Adds a set of event flags directly to the specified @p thread_t. - * @post This function does not reschedule so a call to a rescheduling - * function must be performed before unlocking the kernel. Note that - * interrupt handlers always reschedule on exit so an explicit - * reschedule must not be performed in ISRs. - * - * @param[in] tp the thread to be signaled - * @param[in] mask the event flags set to be ORed - * - * @iclass - */ -void chEvtSignalI(thread_t *tp, eventmask_t mask) { - - tp->epmask |= mask; - if (NIL_THD_IS_WTOREVT(tp) && - ((tp->epmask & tp->u1.ewmask) != (eventmask_t)0)) { - (void) chSchReadyI(tp, MSG_OK); - } -} - -/** - * @brief Waits for any of the specified events. - * @details The function waits for any event among those specified in - * @p mask to become pending then the events are cleared and - * returned. - * - * @param[in] mask mask of the event flags that the function should wait - * for, @p ALL_EVENTS enables all the events - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The mask of the served and cleared events. - * @retval 0 if the operation has timed out. - * - * @api - */ -eventmask_t chEvtWaitAnyTimeout(eventmask_t mask, systime_t timeout) { - eventmask_t m; - - chSysLock(); - m = chEvtWaitAnyTimeoutS(mask, timeout); - chSysUnlock(); - - return m; -} - -/** - * @brief Waits for any of the specified events. - * @details The function waits for any event among those specified in - * @p mask to become pending then the events are cleared and - * returned. - * - * @param[in] mask mask of the event flags that the function should wait - * for, @p ALL_EVENTS enables all the events - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The mask of the served and cleared events. - * @retval 0 if the operation has timed out. - * - * @sclass - */ -eventmask_t chEvtWaitAnyTimeoutS(eventmask_t mask, systime_t timeout) { - thread_t *ctp = nil.current; - eventmask_t m; - - if ((m = (ctp->epmask & mask)) == (eventmask_t)0) { - if (TIME_IMMEDIATE == timeout) { - chSysUnlock(); - - return (eventmask_t)0; - } - ctp->u1.ewmask = mask; - if (chSchGoSleepTimeoutS(NIL_STATE_WTOREVT, timeout) < MSG_OK) { - chSysUnlock(); - - return (eventmask_t)0; - } - m = ctp->epmask & mask; - } - ctp->epmask &= ~m; - - return m; -} -#endif /* NIL_CFG_USE_EVENTS == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/nil/templates/nilconf.h b/firmware/ChibiOS_16/os/nil/templates/nilconf.h deleted file mode 100644 index 6f70809bb0..0000000000 --- a/firmware/ChibiOS_16/os/nil/templates/nilconf.h +++ /dev/null @@ -1,179 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file nilconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup NIL_CONFIG - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef _NILCONF_H_ -#define _NILCONF_H_ - -/*===========================================================================*/ -/** - * @name Kernel parameters and options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Number of user threads in the application. - * @note This number is not inclusive of the idle thread which is - * Implicitly handled. - */ -#define NIL_CFG_NUM_THREADS 1 - -/** @} */ - -/*===========================================================================*/ -/** - * @name System timer settings - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. - */ -#define NIL_CFG_ST_RESOLUTION 32 - -/** - * @brief System tick frequency. - * @note This value together with the @p NIL_CFG_ST_RESOLUTION - * option defines the maximum amount of time allowed for - * timeouts. - */ -#define NIL_CFG_ST_FREQUENCY 50000 - -/** - * @brief Time delta constant for the tick-less mode. - * @note If this value is zero then the system uses the classic - * periodic tick. This value represents the minimum number - * of ticks that is safe to specify in a timeout directive. - * The value one is not valid, timeouts are rounded up to - * this value. - */ -#define NIL_CFG_ST_TIMEDELTA 2 - -/** @} */ - -/*===========================================================================*/ -/** - * @name Subsystem options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#define NIL_CFG_USE_EVENTS TRUE - -/** @} */ - -/*===========================================================================*/ -/** - * @name Debug options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System assertions. - */ -#define NIL_CFG_ENABLE_ASSERTS FALSE - -/** - * @brief Stack check. - */ -#define NIL_CFG_ENABLE_STACK_CHECK FALSE - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel hooks - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System initialization hook. - */ -#if !defined(NIL_CFG_SYSTEM_INIT_HOOK) || defined(__DOXYGEN__) -#define NIL_CFG_SYSTEM_INIT_HOOK() { \ -} -#endif - -/** - * @brief Threads descriptor structure extension. - * @details User fields added to the end of the @p thread_t structure. - */ -#define NIL_CFG_THREAD_EXT_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief Threads initialization hook. - */ -#define NIL_CFG_THREAD_EXT_INIT_HOOK(tr) { \ - /* Add custom threads initialization code here.*/ \ -} - -/** - * @brief Idle thread enter hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to activate a power saving mode. - */ -#define NIL_CFG_IDLE_ENTER_HOOK() { \ -} - -/** - * @brief Idle thread leave hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to deactivate a power saving mode. - */ -#define NIL_CFG_IDLE_LEAVE_HOOK() { \ -} - -/** - * @brief System halt hook. - */ -#if !defined(NIL_CFG_SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) -#define NIL_CFG_SYSTEM_HALT_HOOK(reason) { \ -} -#endif - -/** @} */ - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in nilcore.h). */ -/*===========================================================================*/ - -#endif /* _NILCONF_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/nil/templates/nilcore.c b/firmware/ChibiOS_16/os/nil/templates/nilcore.c deleted file mode 100644 index a6196c06f2..0000000000 --- a/firmware/ChibiOS_16/os/nil/templates/nilcore.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file templates/nilcore.c - * @brief Port code. - * - * @addtogroup NIL_CORE - * @{ - */ - -#include "nil.h" - -/*===========================================================================*/ -/* Module local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/nil/templates/nilcore.h b/firmware/ChibiOS_16/os/nil/templates/nilcore.h deleted file mode 100644 index ca8ea11f8e..0000000000 --- a/firmware/ChibiOS_16/os/nil/templates/nilcore.h +++ /dev/null @@ -1,379 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file templates/nilcore.h - * @brief Port macros and structures. - * - * @addtogroup NIL_CORE - * @{ - */ - -#ifndef _NILCORE_H_ -#define _NILCORE_H_ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @name Architecture and Compiler - * @{ - */ -/** - * @brief Macro defining the port architecture. - */ -#define PORT_ARCHITECTURE_XXX - -/** - * @brief Name of the implemented architecture. - */ -#define PORT_ARCHITECTURE_NAME "XXX" - -/** - * @brief Name of the architecture variant. - */ -#define PORT_CORE_VARIANT_NAME "XXXX-Y" - -/** - * @brief Compiler name and version. - */ -#if defined(__GNUC__) || defined(__DOXYGEN__) -#define PORT_COMPILER_NAME "GCC " __VERSION__ - -#else -#error "unsupported compiler" -#endif - -/** - * @brief Port-specific information string. - */ -#define PORT_INFO "port description" - -/** - * @brief This port supports a realtime counter. - */ -#define PORT_SUPPORTS_RT FALSE -/** @} */ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Per-thread stack overhead for interrupts servicing. - * @details This constant is used in the calculation of the correct working - * area size. - */ -#if !defined(PORT_INT_REQUIRED_STACK) || defined(__DOXYGEN__) -#define PORT_INT_REQUIRED_STACK 32 -#endif - -/** - * @brief Enables an alternative timer implementation. - * @details Usually the port uses a timer interface defined in the file - * @p nilcore_timer.h, if this option is enabled then the file - * @p nilcore_timer_alt.h is included instead. - */ -#if !defined(PORT_USE_ALT_TIMER) -#define PORT_USE_ALT_TIMER FALSE -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/* The following code is not processed when the file is included from an - asm module.*/ -#if !defined(_FROM_ASM_) - -/** - * @brief Type of stack and memory alignment enforcement. - */ -typedef uint64_t stkalign_t; - -/** - * @brief Interrupt saved context. - * @details This structure represents the stack frame saved during a - * preemption-capable interrupt handler. - */ -struct port_extctx { - uint32_t reg1; - uint32_t reg2; -}; - -/** - * @brief System saved context. - * @details This structure represents the inner stack frame during a context - * switch. - */ -struct port_intctx { - uint32_t reg3; - uint32_t reg4; -}; - -#endif /* !defined(_FROM_ASM_) */ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @brief Platform dependent thread stack setup. - * @details This code usually setup the context switching frame represented - * by an @p port_intctx structure. - */ -#define PORT_SETUP_CONTEXT(tp, wend, pf, arg) do { \ - (void)(tp); \ - (void)(wend); \ - (void)(pf); \ - (void)(arg); \ -} while (false) - -/** - * @brief Computes the thread working area global size. - * @note There is no need to perform alignments in this macro. - */ -#define PORT_WA_SIZE(n) (sizeof(struct port_intctx) + \ - sizeof(struct port_extctx) + \ - (size_t)(n) + \ - (size_t)(PORT_INT_REQUIRED_STACK)) - -/** - * @brief Priority level verification macro. - */ -#define PORT_IRQ_IS_VALID_PRIORITY(n) false - -/** - * @brief Priority level verification macro. - */ -#define PORT_IRQ_IS_VALID_KERNEL_PRIORITY(n) false - -/** - * @brief IRQ prologue code. - * @details This macro must be inserted at the start of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_PROLOGUE() - -/** - * @brief IRQ epilogue code. - * @details This macro must be inserted at the end of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_EPILOGUE() _port_irq_epilogue() - -/** - * @brief IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_IRQ_HANDLER(id) void id(void) - -/** - * @brief Fast IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_FAST_IRQ_HANDLER(id) void id(void) - -/** - * @brief Performs a context switch between two threads. - * @details This is the most critical code in any port, this function - * is responsible for the context switch between 2 threads. - * @note The implementation of this code affects directly the context - * switch performance so optimize here as much as you can. - * - * @param[in] ntp the thread to be switched in - * @param[in] otp the thread to be switched out - */ -#define port_switch(ntp, otp) do { \ - (void)ntp; \ - (void)otp; \ - /*_port_switch(ntp, otp)*/ \ -} while (false) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/* The following code is not processed when the file is included from an - asm module.*/ -#if !defined(_FROM_ASM_) - -#ifdef __cplusplus -extern "C" { -#endif - void _port_irq_epilogue(void); - void _port_switch(thread_t *ntp, thread_t *otp); - void _port_thread_start(void); -#ifdef __cplusplus -} -#endif - -#endif /* !defined(_FROM_ASM_) */ - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -/* The following code is not processed when the file is included from an - asm module.*/ -#if !defined(_FROM_ASM_) - -/** - * @brief Port-related initialization code. - */ -static inline void port_init(void) { - -} - -/** - * @brief Returns a word encoding the current interrupts status. - * - * @return The interrupts status. - */ -static inline syssts_t port_get_irq_status(void) { - - return (syssts_t)0; -} - -/** - * @brief Checks the interrupt status. - * - * @param[in] sts the interrupt status word - * - * @return The interrupt status. - * @retval false the word specified a disabled interrupts status. - * @retval true the word specified an enabled interrupts status. - */ -static inline bool port_irq_enabled(syssts_t sts) { - - (void)sts; - - return false; -} - -/** - * @brief Determines the current execution context. - * - * @return The execution context. - * @retval false not running in ISR mode. - * @retval true running in ISR mode. - */ -static inline bool port_is_isr_context(void) { - - return false; -} - -/** - * @brief Kernel-lock action. - */ -static inline void port_lock(void) { - -} - -/** - * @brief Kernel-unlock action. - */ -static inline void port_unlock(void) { - -} - -/** - * @brief Kernel-lock action from an interrupt handler. - */ -static inline void port_lock_from_isr(void) { - -} - -/** - * @brief Kernel-unlock action from an interrupt handler. - */ -static inline void port_unlock_from_isr(void) { - -} - -/** - * @brief Disables all the interrupt sources. - */ -static inline void port_disable(void) { - -} - -/** - * @brief Disables the interrupt sources below kernel-level priority. - */ -static inline void port_suspend(void) { - -} - -/** - * @brief Enables all the interrupt sources. - */ -static inline void port_enable(void) { - -} - -/** - * @brief Enters an architecture-dependent IRQ-waiting mode. - * @details The function is meant to return when an interrupt becomes pending. - * The simplest implementation is an empty function or macro but this - * would not take advantage of architecture-specific power saving - * modes. - */ -static inline void port_wait_for_interrupt(void) { - -} - -/** - * @brief Returns the current value of the realtime counter. - * - * @return The realtime counter value. - */ -static inline rtcnt_t port_rt_get_counter_value(void) { - - return (rtcnt_t)0; -} - -#endif /* !defined(_FROM_ASM_) */ - -/*===========================================================================*/ -/* Module late inclusions. */ -/*===========================================================================*/ - -#if !defined(_FROM_ASM_) - -#if NIL_CFG_ST_TIMEDELTA > 0 -#if PORT_USE_ALT_TIMER == FALSE -#include "nilcore_timer.h" -#else -#include "nilcore_timer_alt.h" -#endif -#endif /* NIL_CFG_ST_TIMEDELTA > 0 */ - -#endif /* !defined(_FROM_ASM_) */ - -#endif /* _NILCORE_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/nil/templates/nilcore_timer.h b/firmware/ChibiOS_16/os/nil/templates/nilcore_timer.h deleted file mode 100644 index e22ccd9a0e..0000000000 --- a/firmware/ChibiOS_16/os/nil/templates/nilcore_timer.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file templates/nilcore_timer.h - * @brief System timer header file. - * - * @addtogroup NIL_TIMER - * @{ - */ - -#ifndef _NILCORE_TIMER_H_ -#define _NILCORE_TIMER_H_ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -/** - * @brief Starts the alarm. - * @note Makes sure that no spurious alarms are triggered after - * this call. - * - * @param[in] abstime the time to be set for the first alarm - * - * @notapi - */ -static inline void port_timer_start_alarm(systime_t abstime) { - - (void)abstime; -} - -/** - * @brief Stops the alarm interrupt. - * - * @notapi - */ -static inline void port_timer_stop_alarm(void) { - -} - -/** - * @brief Sets the alarm time. - * - * @param[in] abstime the time to be set for the next alarm - * - * @notapi - */ -static inline void port_timer_set_alarm(systime_t abstime) { - - (void)abstime; -} - -/** - * @brief Returns the system time. - * - * @return The system time. - * - * @notapi - */ -static inline systime_t port_timer_get_time(void) { - - return (systime_t)0; -} - -/** - * @brief Returns the current alarm time. - * - * @return The currently set alarm time. - * - * @notapi - */ -static inline systime_t port_timer_get_alarm(void) { - - return (systime_t)0; -} - -#endif /* _NILCORE_TIMER_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/nil/templates/niltypes.h b/firmware/ChibiOS_16/os/nil/templates/niltypes.h deleted file mode 100644 index 2a9c9f2fcc..0000000000 --- a/firmware/ChibiOS_16/os/nil/templates/niltypes.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file templates/niltypes.h - * @brief Port system types. - * - * @addtogroup NIL_TYPES - * @{ - */ - -#ifndef _NILTYPES_H_ -#define _NILTYPES_H_ - -#include -#include -#include - -/** - * @name Common constants - */ -/** - * @brief Generic 'false' boolean constant. - */ -#if !defined(FALSE) || defined(__DOXYGEN__) -#define FALSE 0 -#endif - -/** - * @brief Generic 'true' boolean constant. - */ -#if !defined(TRUE) || defined(__DOXYGEN__) -#define TRUE 1 -#endif -/** @} */ - -typedef uint32_t syssts_t; /**< System status word. */ -typedef uint32_t rtcnt_t; /**< Realtime counter. */ -typedef uint8_t tstate_t; /**< Thread state. */ -typedef int32_t msg_t; /**< Inter-thread message. */ -typedef uint32_t eventmask_t; /**< Mask of event identifiers. */ -typedef int32_t cnt_t; /**< Generic signed counter. */ -typedef uint32_t ucnt_t; /**< Generic unsigned counter. */ - -/** - * @brief Type of system time. - */ -#if (NIL_CFG_ST_RESOLUTION == 32) || defined(__DOXYGEN__) -typedef uint32_t systime_t; -#else -typedef uint16_t systime_t; -#endif - -/** - * @brief ROM constant modifier. - * @note It is set to use the "const" keyword in this port. - */ -#define ROMCONST const - -/** - * @brief Makes functions not inlineable. - * @note If the compiler does not support such attribute then the - * realtime counter precision could be degraded. - */ -#define NOINLINE __attribute__((noinline)) - -/** - * @brief Optimized thread function declaration macro. - */ -#define PORT_THD_FUNCTION(tname, arg) \ - __attribute__((noreturn)) void tname(void *arg) - -/** - * @brief Packed variable specifier. - */ -#define PACKED_VAR __attribute__((packed)) - -#endif /* _NILTYPES_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/readme.txt b/firmware/ChibiOS_16/os/readme.txt deleted file mode 100644 index 91827ecc93..0000000000 --- a/firmware/ChibiOS_16/os/readme.txt +++ /dev/null @@ -1,29 +0,0 @@ -***************************************************************************** -*** ChibiOS products directory organization *** -***************************************************************************** - ---{root} - Distribution directory. - +--os/ - ChibiOS products, this directory. - | +--rt/ - ChibiOS/RT product. - | | +--include/ - RT kernel headers. - | | +--src/ - RT kernel sources. - | | +--templates/ - RT kernel port template files. - | | +--ports/ - RT kernel port files. - | | +--osal/ - RT kernel OSAL module for HAL interface. - | +--nil/ - ChibiOS/NIL product. - | | +--include/ - Nil kernel headers. - | | +--src/ - Nil kernel sources. - | | +--templates/ - Nil kernel port template files. - | | +--ports/ - Nil kernel port files. - | | +--osal/ - Nil kernel OSAL module for HAL interface. - | +--hal/ - ChibiOS/HAL product. - | | +--include/ - HAL high level headers. - | | +--src/ - HAL high level sources. - | | +--templates/ - HAL port template files. - | | +--ports/ - HAL port files (low level drivers implementations). - | | +--boards/ - HAL board files. - | +--common/ - Files used by multiple ChibiOS products. - | | +--ports - Common port files for various architectures and - | | compilers. - | +--various/ - Various portable support files. - | +--ext/ - Vendor files used by ChibiOS products. diff --git a/firmware/ChibiOS_16/os/rt/dox/rt.dox b/firmware/ChibiOS_16/os/rt/dox/rt.dox deleted file mode 100644 index f4a2f11aba..0000000000 --- a/firmware/ChibiOS_16/os/rt/dox/rt.dox +++ /dev/null @@ -1,175 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @defgroup kernel RT Kernel - * @details The kernel is the portable part of ChibiOS/RT, this section - * documents the various kernel subsystems. - */ - -/** - * @defgroup kernel_info Version Numbers and Identification - * @ingroup kernel - */ - -/** - * @defgroup config Configuration - * @ingroup kernel - */ - -/** - * @defgroup types Kernel Types - * @ingroup kernel - */ - -/** - * @defgroup base Base Kernel Services - * @details Base kernel services, the base subsystems are always included in - * the OS builds. - * @ingroup kernel - */ - -/** - * @defgroup system System Management - * @ingroup base - */ - -/** - * @defgroup scheduler Scheduler - * @ingroup base - */ - -/** - * @defgroup threads Threads - * @ingroup base - */ - -/** - * @defgroup time Time and Virtual Timers - * @ingroup base - */ - -/** - * @defgroup synchronization Synchronization - * @details Synchronization services. - * @ingroup kernel - */ - -/** - * @defgroup semaphores Counting Semaphores - * @ingroup synchronization - */ - -/** - * @defgroup binary_semaphores Binary Semaphores - * @ingroup synchronization - */ - -/** - * @defgroup mutexes Mutexes - * @ingroup synchronization - */ - -/** - * @defgroup condvars Condition Variables - * @ingroup synchronization - */ - -/** - * @defgroup events Event Flags - * @ingroup synchronization - */ - -/** - * @defgroup messages Synchronous Messages - * @ingroup synchronization - */ - -/** - * @defgroup mailboxes Mailboxes - * @ingroup synchronization - */ - -/** - * @defgroup io_queues I/O Queues - * @ingroup synchronization - */ - -/** - * @defgroup memory Memory Management - * @details Memory Management services. - * @ingroup kernel - */ - -/** - * @defgroup memcore Core Memory Manager - * @ingroup memory - */ - -/** - * @defgroup heaps Heaps - * @ingroup memory - */ - -/** - * @defgroup pools Memory Pools - * @ingroup memory - */ - -/** - * @defgroup dynamic_threads Dynamic Threads - * @ingroup memory - */ - - /** - * @defgroup streams Streams and Files - * @details Stream and Files interfaces. - * @ingroup kernel - */ - -/** - * @defgroup data_streams Abstract Sequential Streams - * @ingroup streams - */ - -/** - * @defgroup registry Registry - * @ingroup kernel - */ - -/** - * @defgroup debug Debug - * @ingroup kernel - */ - -/** - * @defgroup time_measurement Time Measurement - * @ingroup kernel - */ - -/** - * @defgroup statistics Statistics - * @ingroup kernel - */ - -/** - * @defgroup core Port Layer - * @ingroup kernel - */ - diff --git a/firmware/ChibiOS_16/os/rt/include/ch.h b/firmware/ChibiOS_16/os/rt/include/ch.h deleted file mode 100644 index 4715a233b2..0000000000 --- a/firmware/ChibiOS_16/os/rt/include/ch.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file ch.h - * @brief ChibiOS/RT main include file. - * @details This header includes all the required kernel headers so it is the - * only kernel header you usually want to include in your application. - * - * @addtogroup kernel_info - * @details Kernel related info. - * @{ - */ - -#ifndef _CH_H_ -#define _CH_H_ - -/** - * @brief ChibiOS/RT identification macro. - */ -#define _CHIBIOS_RT_ - -/** - * @brief Stable release flag. - */ -#define CH_KERNEL_STABLE 1 - -/** - * @name ChibiOS/RT version identification - * @{ - */ -/** - * @brief Kernel version string. - */ -#define CH_KERNEL_VERSION "3.1.5" - -/** - * @brief Kernel version major number. - */ -#define CH_KERNEL_MAJOR 3 - -/** - * @brief Kernel version minor number. - */ -#define CH_KERNEL_MINOR 1 - -/** - * @brief Kernel version patch number. - */ -#define CH_KERNEL_PATCH 5 -/** @} */ - -/* Core headers.*/ -#include "chtypes.h" -#include "chconf.h" -#include "chlicense.h" -#include "chsystypes.h" -#include "chcore.h" -#include "chdebug.h" -#include "chtm.h" -#include "chstats.h" -#include "chschd.h" -#include "chsys.h" -#include "chvt.h" -#include "chthreads.h" - -/* Optional subsystems headers.*/ -#include "chregistry.h" -#include "chsem.h" -#include "chbsem.h" -#include "chmtx.h" -#include "chcond.h" -#include "chevents.h" -#include "chmsg.h" -#include "chmboxes.h" -#include "chmemcore.h" -#include "chheap.h" -#include "chmempools.h" -#include "chdynamic.h" -#include "chqueues.h" -#include "chstreams.h" - -#endif /* _CH_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/include/chbsem.h b/firmware/ChibiOS_16/os/rt/include/chbsem.h deleted file mode 100644 index 70000803ca..0000000000 --- a/firmware/ChibiOS_16/os/rt/include/chbsem.h +++ /dev/null @@ -1,311 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chbsem.h - * @brief Binary semaphores structures and macros. - * - * @addtogroup binary_semaphores - * @details Binary semaphores related APIs and services. - *

Operation mode

- * Binary semaphores are implemented as a set of inline functions - * that use the existing counting semaphores primitives. The - * difference between counting and binary semaphores is that the - * counter of binary semaphores is not allowed to grow above the - * value 1. Repeated signal operation are ignored. A binary - * semaphore can thus have only two defined states: - * - Taken, when its counter has a value of zero or lower - * than zero. A negative number represent the number of threads - * queued on the binary semaphore. - * - Not taken, when its counter has a value of one. - * . - * Binary semaphores are different from mutexes because there is no - * concept of ownership, a binary semaphore can be taken by a - * thread and signaled by another thread or an interrupt handler, - * mutexes can only be taken and released by the same thread. Another - * difference is that binary semaphores, unlike mutexes, do not - * implement the priority inheritance protocol.
- * In order to use the binary semaphores APIs the - * @p CH_CFG_USE_SEMAPHORES option must be enabled in @p chconf.h. - * @{ - */ - -#ifndef _CHBSEM_H_ -#define _CHBSEM_H_ - -#if (CH_CFG_USE_SEMAPHORES == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/** - * @extends semaphore_t - * - * @brief Binary semaphore type. - */ -typedef struct { - semaphore_t bs_sem; -} binary_semaphore_t; - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @brief Data part of a static semaphore initializer. - * @details This macro should be used when statically initializing a semaphore - * that is part of a bigger structure. - * - * @param[in] name the name of the semaphore variable - * @param[in] taken the semaphore initial state - */ -#define _BSEMAPHORE_DATA(name, taken) \ - {_SEMAPHORE_DATA(name.bs_sem, ((taken) ? 0 : 1))} - -/** - * @brief Static semaphore initializer. - * @details Statically initialized semaphores require no explicit - * initialization using @p chBSemInit(). - * - * @param[in] name the name of the semaphore variable - * @param[in] taken the semaphore initial state - */ -#define BSEMAPHORE_DECL(name, taken) \ - binary_semaphore_t name = _BSEMAPHORE_DATA(name, taken) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -/** - * @brief Initializes a binary semaphore. - * - * @param[out] bsp pointer to a @p binary_semaphore_t structure - * @param[in] taken initial state of the binary semaphore: - * - @a false, the initial state is not taken. - * - @a true, the initial state is taken. - * . - * - * @init - */ -static inline void chBSemObjectInit(binary_semaphore_t *bsp, bool taken) { - - chSemObjectInit(&bsp->bs_sem, taken ? (cnt_t)0 : (cnt_t)1); -} - -/** - * @brief Wait operation on the binary semaphore. - * - * @param[in] bsp pointer to a @p binary_semaphore_t structure - * @return A message specifying how the invoking thread has been - * released from the semaphore. - * @retval MSG_OK if the binary semaphore has been successfully taken. - * @retval MSG_RESET if the binary semaphore has been reset using - * @p bsemReset(). - * - * @api - */ -static inline msg_t chBSemWait(binary_semaphore_t *bsp) { - - return chSemWait(&bsp->bs_sem); -} - -/** - * @brief Wait operation on the binary semaphore. - * - * @param[in] bsp pointer to a @p binary_semaphore_t structure - * @return A message specifying how the invoking thread has been - * released from the semaphore. - * @retval MSG_OK if the binary semaphore has been successfully taken. - * @retval MSG_RESET if the binary semaphore has been reset using - * @p bsemReset(). - * - * @sclass - */ -static inline msg_t chBSemWaitS(binary_semaphore_t *bsp) { - - chDbgCheckClassS(); - - return chSemWaitS(&bsp->bs_sem); -} - -/** - * @brief Wait operation on the binary semaphore. - * - * @param[in] bsp pointer to a @p binary_semaphore_t structure - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return A message specifying how the invoking thread has been - * released from the semaphore. - * @retval MSG_OK if the binary semaphore has been successfully taken. - * @retval MSG_RESET if the binary semaphore has been reset using - * @p bsemReset(). - * @retval MSG_TIMEOUT if the binary semaphore has not been signaled or reset - * within the specified timeout. - * - * @sclass - */ -static inline msg_t chBSemWaitTimeoutS(binary_semaphore_t *bsp, - systime_t time) { - - chDbgCheckClassS(); - - return chSemWaitTimeoutS(&bsp->bs_sem, time); -} - -/** - * @brief Wait operation on the binary semaphore. - * - * @param[in] bsp pointer to a @p binary_semaphore_t structure - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return A message specifying how the invoking thread has been - * released from the semaphore. - * @retval MSG_OK if the binary semaphore has been successfully taken. - * @retval MSG_RESET if the binary semaphore has been reset using - * @p bsemReset(). - * @retval MSG_TIMEOUT if the binary semaphore has not been signaled or reset - * within the specified timeout. - * - * @api - */ -static inline msg_t chBSemWaitTimeout(binary_semaphore_t *bsp, - systime_t time) { - - return chSemWaitTimeout(&bsp->bs_sem, time); -} - -/** - * @brief Reset operation on the binary semaphore. - * @note The released threads can recognize they were waked up by a reset - * rather than a signal because the @p bsemWait() will return - * @p MSG_RESET instead of @p MSG_OK. - * @note This function does not reschedule. - * - * @param[in] bsp pointer to a @p binary_semaphore_t structure - * @param[in] taken new state of the binary semaphore - * - @a false, the new state is not taken. - * - @a true, the new state is taken. - * . - * - * @iclass - */ -static inline void chBSemResetI(binary_semaphore_t *bsp, bool taken) { - - chDbgCheckClassI(); - - chSemResetI(&bsp->bs_sem, taken ? (cnt_t)0 : (cnt_t)1); -} - -/** - * @brief Reset operation on the binary semaphore. - * @note The released threads can recognize they were waked up by a reset - * rather than a signal because the @p bsemWait() will return - * @p MSG_RESET instead of @p MSG_OK. - * - * @param[in] bsp pointer to a @p binary_semaphore_t structure - * @param[in] taken new state of the binary semaphore - * - @a false, the new state is not taken. - * - @a true, the new state is taken. - * . - * - * @api - */ -static inline void chBSemReset(binary_semaphore_t *bsp, bool taken) { - - chSemReset(&bsp->bs_sem, taken ? (cnt_t)0 : (cnt_t)1); -} - -/** - * @brief Performs a signal operation on a binary semaphore. - * @note This function does not reschedule. - * - * @param[in] bsp pointer to a @p binary_semaphore_t structure - * - * @iclass - */ -static inline void chBSemSignalI(binary_semaphore_t *bsp) { - - chDbgCheckClassI(); - - if (bsp->bs_sem.s_cnt < (cnt_t)1) { - chSemSignalI(&bsp->bs_sem); - } -} - -/** - * @brief Performs a signal operation on a binary semaphore. - * - * @param[in] bsp pointer to a @p binary_semaphore_t structure - * - * @api - */ -static inline void chBSemSignal(binary_semaphore_t *bsp) { - - chSysLock(); - chBSemSignalI(bsp); - chSchRescheduleS(); - chSysUnlock(); -} - -/** - * @brief Returns the binary semaphore current state. - * - * @param[in] bsp pointer to a @p binary_semaphore_t structure - * @return The binary semaphore current state. - * @retval false if the binary semaphore is not taken. - * @retval true if the binary semaphore is taken. - * - * @iclass - */ -static inline bool chBSemGetStateI(binary_semaphore_t *bsp) { - - chDbgCheckClassI(); - - return (bsp->bs_sem.s_cnt > (cnt_t)0) ? false : true; -} - -#endif /* CH_CFG_USE_SEMAPHORES == TRUE */ - -#endif /* _CHBSEM_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/include/chcond.h b/firmware/ChibiOS_16/os/rt/include/chcond.h deleted file mode 100644 index ed0e41dd0f..0000000000 --- a/firmware/ChibiOS_16/os/rt/include/chcond.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ -/* - Concepts and parts of this file have been contributed by Leon Woestenberg. - */ - -/** - * @file chcond.h - * @brief Condition Variables macros and structures. - * - * @addtogroup condvars - * @{ - */ - -#ifndef _CHCOND_H_ -#define _CHCOND_H_ - -#if (CH_CFG_USE_CONDVARS == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if CH_CFG_USE_MUTEXES == FALSE -#error "CH_CFG_USE_CONDVARS requires CH_CFG_USE_MUTEXES" -#endif - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/** - * @brief condition_variable_t structure. - */ -typedef struct condition_variable { - threads_queue_t c_queue; /**< @brief Condition variable - threads queue. */ -} condition_variable_t; - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @brief Data part of a static condition variable initializer. - * @details This macro should be used when statically initializing a condition - * variable that is part of a bigger structure. - * - * @param[in] name the name of the condition variable - */ -#define _CONDVAR_DATA(name) {_THREADS_QUEUE_DATA(name.c_queue)} - -/** - * @brief Static condition variable initializer. - * @details Statically initialized condition variables require no explicit - * initialization using @p chCondInit(). - * - * @param[in] name the name of the condition variable - */ -#define CONDVAR_DECL(name) condition_variable_t name = _CONDVAR_DATA(name) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void chCondObjectInit(condition_variable_t *cp); - void chCondSignal(condition_variable_t *cp); - void chCondSignalI(condition_variable_t *cp); - void chCondBroadcast(condition_variable_t *cp); - void chCondBroadcastI(condition_variable_t *cp); - msg_t chCondWait(condition_variable_t *cp); - msg_t chCondWaitS(condition_variable_t *cp); -#if CH_CFG_USE_CONDVARS_TIMEOUT == TRUE - msg_t chCondWaitTimeout(condition_variable_t *cp, systime_t time); - msg_t chCondWaitTimeoutS(condition_variable_t *cp, systime_t time); -#endif -#ifdef __cplusplus -} -#endif - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -#endif /* CH_CFG_USE_CONDVARS == TRUE */ - -#endif /* _CHCOND_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/include/chcustomer.h b/firmware/ChibiOS_16/os/rt/include/chcustomer.h deleted file mode 100644 index 2f9c17fb47..0000000000 --- a/firmware/ChibiOS_16/os/rt/include/chcustomer.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chcustomer.h - * @brief Customer-related info. - * - * @addtogroup customer - * @{ - */ - -#ifndef _CHCUSTOMER_H_ -#define _CHCUSTOMER_H_ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @brief Customer readable identifier. - */ -#define CH_CUSTOMER_ID_STRING "Santa, North Pole" - -/** - * @brief Customer code. - */ -#define CH_CUSTOMER_ID_CODE "xxxx-yyyy" - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -#endif /* _CHCUSTOMER_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/include/chdebug.h b/firmware/ChibiOS_16/os/rt/include/chdebug.h deleted file mode 100644 index 20c0091416..0000000000 --- a/firmware/ChibiOS_16/os/rt/include/chdebug.h +++ /dev/null @@ -1,239 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chdebug.h - * @brief Debug macros and structures. - * - * @addtogroup debug - * @{ - */ - -#ifndef _CHDEBUG_H_ -#define _CHDEBUG_H_ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Debug related settings - * @{ - */ -/** - * @brief Trace buffer entries. - */ -#ifndef CH_DBG_TRACE_BUFFER_SIZE -#define CH_DBG_TRACE_BUFFER_SIZE 64 -#endif - -/** - * @brief Fill value for thread stack area in debug mode. - */ -#ifndef CH_DBG_STACK_FILL_VALUE -#define CH_DBG_STACK_FILL_VALUE 0x55 -#endif - -/** - * @brief Fill value for thread area in debug mode. - * @note The chosen default value is 0xFF in order to make evident which - * thread fields were not initialized when inspecting the memory with - * a debugger. A uninitialized field is not an error in itself but it - * better to know it. - */ -#ifndef CH_DBG_THREAD_FILL_VALUE -#define CH_DBG_THREAD_FILL_VALUE 0xFF -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -#if (CH_DBG_ENABLE_TRACE == TRUE) || defined(__DOXYGEN__) -/** - * @brief Trace buffer record. - */ -typedef struct { - /** - * @brief Time of the switch event. - */ - systime_t se_time; - /** - * @brief Switched in thread. - */ - thread_t *se_tp; - /** - * @brief Object where going to sleep. - */ - void *se_wtobjp; - /** - * @brief Switched out thread state. - */ - uint8_t se_state; -} ch_swc_event_t; - -/** - * @brief Trace buffer header. - */ -typedef struct { - /** - * @brief Trace buffer size (entries). - */ - unsigned tb_size; - /** - * @brief Pointer to the buffer front. - */ - ch_swc_event_t *tb_ptr; - /** - * @brief Ring buffer. - */ - ch_swc_event_t tb_buffer[CH_DBG_TRACE_BUFFER_SIZE]; -} ch_trace_buffer_t; -#endif /* CH_DBG_ENABLE_TRACE */ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -#if CH_DBG_SYSTEM_STATE_CHECK == TRUE -#define _dbg_enter_lock() (ch.dbg.lock_cnt = (cnt_t)1) -#define _dbg_leave_lock() (ch.dbg.lock_cnt = (cnt_t)0) -#endif - -/* When the state checker feature is disabled then the following functions - are replaced by an empty macro.*/ -#if CH_DBG_SYSTEM_STATE_CHECK == FALSE -#define _dbg_enter_lock() -#define _dbg_leave_lock() -#define _dbg_check_disable() -#define _dbg_check_suspend() -#define _dbg_check_enable() -#define _dbg_check_lock() -#define _dbg_check_unlock() -#define _dbg_check_lock_from_isr() -#define _dbg_check_unlock_from_isr() -#define _dbg_check_enter_isr() -#define _dbg_check_leave_isr() -#define chDbgCheckClassI() -#define chDbgCheckClassS() -#endif - -/* When the trace feature is disabled this function is replaced by an empty - macro.*/ -#if CH_DBG_ENABLE_TRACE == FALSE -#define _dbg_trace(otp) -#endif - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Function parameters check. - * @details If the condition check fails then the kernel panics and halts. - * @note The condition is tested only if the @p CH_DBG_ENABLE_CHECKS switch - * is specified in @p chconf.h else the macro does nothing. - * - * @param[in] c the condition to be verified to be true - * - * @api - */ -#if !defined(chDbgCheck) -#define chDbgCheck(c) do { \ - /*lint -save -e506 -e774 [2.1, 14.3] Can be a constant by design.*/ \ - if (CH_DBG_ENABLE_CHECKS != FALSE) { \ - if (!(c)) { \ - /*lint -restore*/ \ - chSysHalt(__func__); \ - } \ - } \ -} while (false) -#endif /* !defined(chDbgCheck) */ - -/** - * @brief Condition assertion. - * @details If the condition check fails then the kernel panics with a - * message and halts. - * @note The condition is tested only if the @p CH_DBG_ENABLE_ASSERTS switch - * is specified in @p chconf.h else the macro does nothing. - * @note The remark string is not currently used except for putting a - * comment in the code about the assertion. - * - * @param[in] c the condition to be verified to be true - * @param[in] r a remark string - * - * @api - */ -#if !defined(chDbgAssert) -#define chDbgAssert(c, r) do { \ - /*lint -save -e506 -e774 [2.1, 14.3] Can be a constant by design.*/ \ - if (CH_DBG_ENABLE_ASSERTS != FALSE) { \ - if (!(c)) { \ - /*lint -restore*/ \ - chSysHalt(__func__); \ - } \ - } \ -} while (false) -#endif /* !defined(chDbgAssert) */ -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif -#if CH_DBG_SYSTEM_STATE_CHECK == TRUE - void _dbg_check_disable(void); - void _dbg_check_suspend(void); - void _dbg_check_enable(void); - void _dbg_check_lock(void); - void _dbg_check_unlock(void); - void _dbg_check_lock_from_isr(void); - void _dbg_check_unlock_from_isr(void); - void _dbg_check_enter_isr(void); - void _dbg_check_leave_isr(void); - void chDbgCheckClassI(void); - void chDbgCheckClassS(void); -#endif -#if (CH_DBG_ENABLE_TRACE == TRUE) || defined(__DOXYGEN__) - void _dbg_trace_init(void); - void _dbg_trace(thread_t *otp); -#endif -#ifdef __cplusplus -} -#endif - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -#endif /* _CHDEBUG_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/include/chdynamic.h b/firmware/ChibiOS_16/os/rt/include/chdynamic.h deleted file mode 100644 index 55dd84a45e..0000000000 --- a/firmware/ChibiOS_16/os/rt/include/chdynamic.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chdynamic.h - * @brief Dynamic threads macros and structures. - * - * @addtogroup dynamic_threads - * @{ - */ - -#ifndef _CHDYNAMIC_H_ -#define _CHDYNAMIC_H_ - -#if (CH_CFG_USE_DYNAMIC == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/* - * Module dependencies check. - */ -#if CH_CFG_USE_WAITEXIT == FALSE -#error "CH_CFG_USE_DYNAMIC requires CH_CFG_USE_WAITEXIT" -#endif - -#if (CH_CFG_USE_HEAP == FALSE) && (CH_CFG_USE_MEMPOOLS == FALSE) -#error "CH_CFG_USE_DYNAMIC requires CH_CFG_USE_HEAP and/or CH_CFG_USE_MEMPOOLS" -#endif - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/* - * Dynamic threads APIs. - */ -#ifdef __cplusplus -extern "C" { -#endif - thread_t *chThdAddRef(thread_t *tp); - void chThdRelease(thread_t *tp); -#if CH_CFG_USE_HEAP == TRUE - thread_t *chThdCreateFromHeap(memory_heap_t *heapp, size_t size, - tprio_t prio, tfunc_t pf, void *arg); -#endif -#if CH_CFG_USE_MEMPOOLS == TRUE - thread_t *chThdCreateFromMemoryPool(memory_pool_t *mp, tprio_t prio, - tfunc_t pf, void *arg); -#endif -#ifdef __cplusplus -} -#endif - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -#endif /* CH_CFG_USE_DYNAMIC == TRUE */ - -#endif /* _CHDYNAMIC_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/include/chevents.h b/firmware/ChibiOS_16/os/rt/include/chevents.h deleted file mode 100644 index 6db662cfc8..0000000000 --- a/firmware/ChibiOS_16/os/rt/include/chevents.h +++ /dev/null @@ -1,263 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ -/* - Concepts and parts of this file have been contributed by Scott (skute). - */ - -/** - * @file chevents.h - * @brief Events macros and structures. - * - * @addtogroup events - * @{ - */ - -#ifndef _CHEVENTS_H_ -#define _CHEVENTS_H_ - -#if (CH_CFG_USE_EVENTS == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -typedef struct event_listener event_listener_t; - -/** - * @brief Event Listener structure. - */ -struct event_listener { - event_listener_t *el_next; /**< @brief Next Event Listener - registered on the event - source. */ - thread_t *el_listener; /**< @brief Thread interested in the - event source. */ - eventmask_t el_events; /**< @brief Events to be set in - the listening thread. */ - eventflags_t el_flags; /**< @brief Flags added to the listener - by the event source. */ - eventflags_t el_wflags; /**< @brief Flags that this listener - interested in. */ -}; - -/** - * @brief Event Source structure. - */ -typedef struct event_source { - event_listener_t *es_next; /**< @brief First Event Listener - registered on the Event - Source. */ -} event_source_t; - -/** - * @brief Event Handler callback function. - */ -typedef void (*evhandler_t)(eventid_t id); - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @brief All events allowed mask. - */ -#define ALL_EVENTS ((eventmask_t)-1) - -/** - * @brief Returns an event mask from an event identifier. - */ -#define EVENT_MASK(eid) ((eventmask_t)1 << (eventmask_t)(eid)) - -/** - * @brief Data part of a static event source initializer. - * @details This macro should be used when statically initializing an event - * source that is part of a bigger structure. - * @param name the name of the event source variable - */ -#define _EVENTSOURCE_DATA(name) {(void *)(&name)} - -/** - * @brief Static event source initializer. - * @details Statically initialized event sources require no explicit - * initialization using @p chEvtInit(). - * - * @param name the name of the event source variable - */ -#define EVENTSOURCE_DECL(name) event_source_t name = _EVENTSOURCE_DATA(name) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void chEvtRegisterMaskWithFlags(event_source_t *esp, - event_listener_t *elp, - eventmask_t events, - eventflags_t wflags); - void chEvtUnregister(event_source_t *esp, event_listener_t *elp); - eventmask_t chEvtGetAndClearEvents(eventmask_t events); - eventmask_t chEvtAddEvents(eventmask_t events); - eventflags_t chEvtGetAndClearFlags(event_listener_t *elp); - eventflags_t chEvtGetAndClearFlagsI(event_listener_t *elp); - void chEvtSignal(thread_t *tp, eventmask_t events); - void chEvtSignalI(thread_t *tp, eventmask_t events); - void chEvtBroadcastFlags(event_source_t *esp, eventflags_t flags); - void chEvtBroadcastFlagsI(event_source_t *esp, eventflags_t flags); - void chEvtDispatch(const evhandler_t *handlers, eventmask_t events); -#if (CH_CFG_OPTIMIZE_SPEED == TRUE) || (CH_CFG_USE_EVENTS_TIMEOUT == FALSE) - eventmask_t chEvtWaitOne(eventmask_t events); - eventmask_t chEvtWaitAny(eventmask_t events); - eventmask_t chEvtWaitAll(eventmask_t events); -#endif -#if CH_CFG_USE_EVENTS_TIMEOUT == TRUE - eventmask_t chEvtWaitOneTimeout(eventmask_t events, systime_t time); - eventmask_t chEvtWaitAnyTimeout(eventmask_t events, systime_t time); - eventmask_t chEvtWaitAllTimeout(eventmask_t events, systime_t time); -#endif -#ifdef __cplusplus -} -#endif - -#if (CH_CFG_OPTIMIZE_SPEED == FALSE) && (CH_CFG_USE_EVENTS_TIMEOUT == TRUE) -#define chEvtWaitOne(mask) chEvtWaitOneTimeout(mask, TIME_INFINITE) -#define chEvtWaitAny(mask) chEvtWaitAnyTimeout(mask, TIME_INFINITE) -#define chEvtWaitAll(mask) chEvtWaitAllTimeout(mask, TIME_INFINITE) -#endif - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -/** - * @brief Initializes an Event Source. - * @note This function can be invoked before the kernel is initialized - * because it just prepares a @p event_source_t structure. - * - * @param[in] esp pointer to the @p event_source_t structure - * - * @init - */ -static inline void chEvtObjectInit(event_source_t *esp) { - - esp->es_next = (event_listener_t *)esp; -} - -/** - * @brief Registers an Event Listener on an Event Source. - * @details Once a thread has registered as listener on an event source it - * will be notified of all events broadcasted there. - * @note Multiple Event Listeners can specify the same bits to be ORed to - * different threads. - * - * @param[in] esp pointer to the @p event_source_t structure - * @param[out] elp pointer to the @p event_listener_t structure - * @param[in] events the mask of events to be ORed to the thread when - * the event source is broadcasted - * - * @api - */ -static inline void chEvtRegisterMask(event_source_t *esp, - event_listener_t *elp, - eventmask_t events) { - - chEvtRegisterMaskWithFlags(esp, elp, events, (eventflags_t)-1); -} - -/** - * @brief Registers an Event Listener on an Event Source. - * @note Multiple Event Listeners can use the same event identifier, the - * listener will share the callback function. - * - * @param[in] esp pointer to the @p event_source_t structure - * @param[out] elp pointer to the @p event_listener_t structure - * @param[in] event numeric identifier assigned to the Event Listener. - * The value must range between zero and the size, in bit, - * of the @p eventmask_t type minus one. - * - * @api - */ -static inline void chEvtRegister(event_source_t *esp, - event_listener_t *elp, - eventid_t event) { - - chEvtRegisterMask(esp, elp, EVENT_MASK(event)); -} - -/** - * @brief Verifies if there is at least one @p event_listener_t registered. - * - * @param[in] esp pointer to the @p event_source_t structure - * @return The event source status. - * - * @iclass - */ -static inline bool chEvtIsListeningI(event_source_t *esp) { - - return (bool)(esp != (event_source_t *)esp->es_next); -} - -/** - * @brief Signals all the Event Listeners registered on the specified Event - * Source. - * - * @param[in] esp pointer to the @p event_source_t structure - * - * @api - */ -static inline void chEvtBroadcast(event_source_t *esp) { - - chEvtBroadcastFlags(esp, (eventflags_t)0); -} - -/** - * @brief Signals all the Event Listeners registered on the specified Event - * Source. - * @post This function does not reschedule so a call to a rescheduling - * function must be performed before unlocking the kernel. Note that - * interrupt handlers always reschedule on exit so an explicit - * reschedule must not be performed in ISRs. - * - * @param[in] esp pointer to the @p event_source_t structure - * - * @iclass - */ -static inline void chEvtBroadcastI(event_source_t *esp) { - - chEvtBroadcastFlagsI(esp, (eventflags_t)0); -} - -#endif /* CH_CFG_USE_EVENTS == TRUE */ - -#endif /* _CHEVENTS_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/include/chheap.h b/firmware/ChibiOS_16/os/rt/include/chheap.h deleted file mode 100644 index e2faecceaa..0000000000 --- a/firmware/ChibiOS_16/os/rt/include/chheap.h +++ /dev/null @@ -1,118 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chheap.h - * @brief Heaps macros and structures. - * - * @addtogroup heaps - * @{ - */ - -#ifndef _CHHEAP_H_ -#define _CHHEAP_H_ - -#if (CH_CFG_USE_HEAP == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if CH_CFG_USE_MEMCORE == FALSE -#error "CH_CFG_USE_HEAP requires CH_CFG_USE_MEMCORE" -#endif - -#if (CH_CFG_USE_MUTEXES == FALSE) && (CH_CFG_USE_SEMAPHORES == FALSE) -#error "CH_CFG_USE_HEAP requires CH_CFG_USE_MUTEXES and/or CH_CFG_USE_SEMAPHORES" -#endif - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a memory heap. - */ -typedef struct memory_heap memory_heap_t; - -/** - * @brief Memory heap block header. - */ -union heap_header { - stkalign_t align; - struct { - union { - union heap_header *next; /**< @brief Next block in free list. */ - memory_heap_t *heap; /**< @brief Block owner heap. */ - } u; /**< @brief Overlapped fields. */ - size_t size; /**< @brief Size of the memory block. */ - } h; -}; - -/** - * @brief Structure describing a memory heap. - */ -struct memory_heap { - memgetfunc_t h_provider; /**< @brief Memory blocks provider for - this heap. */ - union heap_header h_free; /**< @brief Free blocks list header. */ -#if CH_CFG_USE_MUTEXES == TRUE - mutex_t h_mtx; /**< @brief Heap access mutex. */ -#else - semaphore_t h_sem; /**< @brief Heap access semaphore. */ -#endif -}; - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void _heap_init(void); - void chHeapObjectInit(memory_heap_t *heapp, void *buf, size_t size); - void *chHeapAlloc(memory_heap_t *heapp, size_t size); - void chHeapFree(void *p); - size_t chHeapStatus(memory_heap_t *heapp, size_t *sizep); -#ifdef __cplusplus -} -#endif - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -#endif /* CH_CFG_USE_HEAP == TRUE */ - -#endif /* _CHHEAP_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/include/chlicense.h b/firmware/ChibiOS_16/os/rt/include/chlicense.h deleted file mode 100644 index 6e0db66e93..0000000000 --- a/firmware/ChibiOS_16/os/rt/include/chlicense.h +++ /dev/null @@ -1,245 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chlicense.h - * @brief License Module macros and structures. - * - * @addtogroup license - * @{ - */ - -#ifndef _CHLICENSE_H_ -#define _CHLICENSE_H_ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @name Allowed Features Levels - * @{ - */ -#define CH_FEATURES_BASIC 0 -#define CH_FEATURES_INTERMEDIATE 1 -#define CH_FEATURES_FULL 2 -/** @} */ - -/** - * @name Deployment Options - */ -#define CH_DEPLOY_UNLIMITED -1 -#define CH_DEPLOY_NONE 0 -/** @} */ - -/** - * @name Licensing Options - * @{ - */ -#define CH_LICENSE_GPL 0 -#define CH_LICENSE_GPL_EXCEPTION 1 -#define CH_LICENSE_COMMERCIAL_FREE 2 -#define CH_LICENSE_COMMERCIAL_DEVELOPER 3 -#define CH_LICENSE_COMMERCIAL_FULL 4 -#define CH_LICENSE_PARTNER 5 -/** @} */ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Current license. - * @note This setting is reserved to the copyright owner. - * @note Changing this setting invalidates the license. - * @note The license statement in the source headers is valid, applicable - * and binding regardless this setting. - */ -#define CH_LICENSE CH_LICENSE_GPL - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if (CH_LICENSE == CH_LICENSE_GPL) || defined(__DOXYGEN__) -/** - * @brief License identification string. - * @details This string identifies the license in a machine-readable - * format. - */ -#define CH_LICENSE_TYPE_STRING "GNU General Public License 3 (GPL3)" - -/** - * @brief Customer identification string. - * @details This information is only available for registered commercial users. - */ -#define CH_LICENSE_ID_STRING "N/A" - -/** - * @brief Customer code. - * @details This information is only available for registered commercial users. - */ -#define CH_LICENSE_ID_CODE "N/A" - -/** - * @brief Code modifiability restrictions. - * @details This setting defines if the source code is user-modifiable or not. - */ -#define CH_LICENSE_MODIFIABLE_CODE TRUE - -/** - * @brief Code functionality restrictions. - * @details This setting defines which features are available under the - * current licensing scheme. The possible settings are: - * - @p CH_FEATURES_FULL if all features are available. - * - @p CH_FEATURES_INTERMEDIATE means that the following - * functionalities are disabled: - * - High Resolution mode. - * - Time Measurement. - * - Statistics. - * . - * - @p CH_FEATURES_BASIC means that the following functionalities - * are disabled: - * - High Resolution mode. - * - Time Measurement. - * - Statistics. - * - Tickless mode. - * - Recursive Mutexes. - * - Condition Variables. - * - Dynamic threading. - * . - * . - */ -#define CH_LICENSE_FEATURES CH_FEATURES_FULL - -/** - * @brief Code deploy restrictions. - * @details This is the per-core deploy limit allowed under the current - * license scheme. - */ -#define CH_LICENSE_MAX_DEPLOY CH_DEPLOY_UNLIMITED - -#elif CH_LICENSE == CH_LICENSE_GPL_EXCEPTION -#define CH_LICENSE_TYPE_STRING "GNU General Public License 3 (GPL3) + Exception" -#define CH_LICENSE_ID_STRING "N/A" -#define CH_LICENSE_ID_CODE "N/A" -#define CH_LICENSE_MODIFIABLE_CODE FALSE -#define CH_LICENSE_FEATURES CH_FEATURES_BASIC -#define CH_LICENSE_MAX_DEPLOY CH_DEPLOY_UNLIMITED - -#elif CH_LICENSE == CH_LICENSE_COMMERCIAL_FREE -#define CH_LICENSE_TYPE_STRING "Zero Cost Registered License" -#define CH_LICENSE_ID_STRING "N/A" -#define CH_LICENSE_ID_CODE "2015-0000" -#define CH_LICENSE_MODIFIABLE_CODE FALSE -#define CH_LICENSE_FEATURES CH_FEATURES_INTERMEDIATE -#define CH_LICENSE_MAX_DEPLOY 500 - -#elif CH_LICENSE == CH_LICENSE_COMMERCIAL_DEVELOPER -#include "chcustomer.h" -#define CH_LICENSE_TYPE_STRING "Developer-Only Commercial License" -#define CH_LICENSE_ID_STRING CH_CUSTOMER_ID_STRING -#define CH_LICENSE_ID_CODE CH_CUSTOMER_ID_CODE -#define CH_LICENSE_MODIFIABLE_CODE TRUE -#define CH_LICENSE_FEATURES CH_FEATURES_FULL -#define CH_LICENSE_DEPLOY_LIMIT 5000 - -#elif CH_LICENSE == CH_LICENSE_COMMERCIAL_FULL -#include "chcustomer.h" -#define CH_LICENSE_TYPE_STRING "Full Commercial License" -#define CH_LICENSE_ID_STRING CH_CUSTOMER_ID_STRING -#define CH_LICENSE_ID_CODE CH_CUSTOMER_ID_CODE -#define CH_LICENSE_MODIFIABLE_CODE TRUE -#define CH_LICENSE_FEATURES CH_FEATURES_FULL -#define CH_LICENSE_MAX_DEPLOY CH_DEPLOY_UNLIMITED - -#elif CH_LICENSE == CH_LICENSE_PARTNER -#include "chpartner.h" -#define CH_LICENSE_TYPE_STRING "Partners Special Commercial License" -#define CH_LICENSE_ID_STRING CH_PARTNER_ID_STRING -#define CH_LICENSE_ID_CODE CH_PARTNER_ID_CODE -#define CH_LICENSE_MODIFIABLE_CODE CH_PARTNER_MODIFIABLE_CODE -#define CH_LICENSE_FEATURES CH_PARTNER_FEATURES_FULL -#define CH_LICENSE_MAX_DEPLOY CH_PARTNER_MAX_DEPLOY - -#else -#error "invalid licensing option" -#endif - -/* Checks on the enabled features.*/ -#if CH_LICENSE_FEATURES == CH_FEATURES_FULL - /* No restrictions in full mode.*/ - -#elif (CH_LICENSE_FEATURES == CH_FEATURES_INTERMEDIATE) || \ - (CH_LICENSE_FEATURES == CH_FEATURES_BASIC) - /* Restrictions in basic and intermediate modes.*/ - #if CH_CFG_ST_TIMEDELTA > 2 - #error "CH_CFG_ST_TIMEDELTA > 2, High Resolution Time functionality restricted" - #endif - - #if CH_DBG_STATISTICS == TRUE - #error "CH_DBG_STATISTICS == TRUE, Statistics functionality restricted" - #endif - - #if CH_LICENSE_FEATURES == CH_FEATURES_BASIC - /* Restrictions in basic mode.*/ - #if CH_CFG_ST_TIMEDELTA > 0 - #error "CH_CFG_ST_TIMEDELTA > 0, Tick-Less functionality restricted" - #endif - - #if CH_CFG_USE_TM == TRUE - #error "CH_CFG_USE_TM == TRUE, Time Measurement functionality restricted" - #endif - - #if CH_CFG_USE_MUTEXES_RECURSIVE == TRUE - #error "CH_CFG_USE_MUTEXES_RECURSIVE == TRUE, Recursive Mutexes functionality restricted" - #endif - - #if CH_CFG_USE_CONDVARS == TRUE - #error "CH_CFG_USE_CONDVARS == TRUE, Condition Variables functionality restricted" - #endif - - #if CH_CFG_USE_DYNAMIC == TRUE - #error "CH_CFG_USE_DYNAMIC == TRUE, Dynamic Threads functionality restricted" - #endif - #endif /* CH_LICENSE_FEATURES == CH_FEATURES_BASIC */ - -#else - #error "invalid feature settings" -#endif - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -#endif /* _CHLICENSE_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/include/chmboxes.h b/firmware/ChibiOS_16/os/rt/include/chmboxes.h deleted file mode 100644 index 6dfc556b76..0000000000 --- a/firmware/ChibiOS_16/os/rt/include/chmboxes.h +++ /dev/null @@ -1,207 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chmboxes.h - * @brief Mailboxes macros and structures. - * - * @addtogroup mailboxes - * @{ - */ - -#ifndef _CHMBOXES_H_ -#define _CHMBOXES_H_ - -#if (CH_CFG_USE_MAILBOXES == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if CH_CFG_USE_SEMAPHORES == FALSE -#error "CH_CFG_USE_MAILBOXES requires CH_CFG_USE_SEMAPHORES" -#endif - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Structure representing a mailbox object. - */ -typedef struct { - msg_t *mb_buffer; /**< @brief Pointer to the mailbox - buffer. */ - msg_t *mb_top; /**< @brief Pointer to the location - after the buffer. */ - msg_t *mb_wrptr; /**< @brief Write pointer. */ - msg_t *mb_rdptr; /**< @brief Read pointer. */ - semaphore_t mb_fullsem; /**< @brief Full counter - @p semaphore_t. */ - semaphore_t mb_emptysem; /**< @brief Empty counter - @p semaphore_t. */ -} mailbox_t; - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @brief Data part of a static mailbox initializer. - * @details This macro should be used when statically initializing a - * mailbox that is part of a bigger structure. - * - * @param[in] name the name of the mailbox variable - * @param[in] buffer pointer to the mailbox buffer area - * @param[in] size size of the mailbox buffer area - */ -#define _MAILBOX_DATA(name, buffer, size) { \ - (msg_t *)(buffer), \ - (msg_t *)(buffer) + size, \ - (msg_t *)(buffer), \ - (msg_t *)(buffer), \ - _SEMAPHORE_DATA(name.mb_fullsem, 0), \ - _SEMAPHORE_DATA(name.mb_emptysem, size), \ -} - -/** - * @brief Static mailbox initializer. - * @details Statically initialized mailboxes require no explicit - * initialization using @p chMBInit(). - * - * @param[in] name the name of the mailbox variable - * @param[in] buffer pointer to the mailbox buffer area - * @param[in] size size of the mailbox buffer area - */ -#define MAILBOX_DECL(name, buffer, size) \ - mailbox_t name = _MAILBOX_DATA(name, buffer, size) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void chMBObjectInit(mailbox_t *mbp, msg_t *buf, cnt_t n); - void chMBReset(mailbox_t *mbp); - void chMBResetI(mailbox_t *mbp); - msg_t chMBPost(mailbox_t *mbp, msg_t msg, systime_t timeout); - msg_t chMBPostS(mailbox_t *mbp, msg_t msg, systime_t timeout); - msg_t chMBPostI(mailbox_t *mbp, msg_t msg); - msg_t chMBPostAhead(mailbox_t *mbp, msg_t msg, systime_t timeout); - msg_t chMBPostAheadS(mailbox_t *mbp, msg_t msg, systime_t timeout); - msg_t chMBPostAheadI(mailbox_t *mbp, msg_t msg); - msg_t chMBFetch(mailbox_t *mbp, msg_t *msgp, systime_t timeout); - msg_t chMBFetchS(mailbox_t *mbp, msg_t *msgp, systime_t timeout); - msg_t chMBFetchI(mailbox_t *mbp, msg_t *msgp); -#ifdef __cplusplus -} -#endif - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -/** - * @brief Returns the mailbox buffer size. - * - * @param[in] mbp the pointer to an initialized mailbox_t object - * @return The size of the mailbox. - * - * @iclass - */ -static inline size_t chMBGetSizeI(mailbox_t *mbp) { - - /*lint -save -e9033 [10.8] Perfectly safe pointers - arithmetic.*/ - return (size_t)(mbp->mb_top - mbp->mb_buffer); - /*lint -restore*/ -} - -/** - * @brief Returns the number of free message slots into a mailbox. - * @note Can be invoked in any system state but if invoked out of a locked - * state then the returned value may change after reading. - * @note The returned value can be less than zero when there are waiting - * threads on the internal semaphore. - * - * @param[in] mbp the pointer to an initialized mailbox_t object - * @return The number of empty message slots. - * - * @iclass - */ -static inline cnt_t chMBGetFreeCountI(mailbox_t *mbp) { - - chDbgCheckClassI(); - - return chSemGetCounterI(&mbp->mb_emptysem); -} - -/** - * @brief Returns the number of used message slots into a mailbox. - * @note Can be invoked in any system state but if invoked out of a locked - * state then the returned value may change after reading. - * @note The returned value can be less than zero when there are waiting - * threads on the internal semaphore. - * - * @param[in] mbp the pointer to an initialized mailbox_t object - * @return The number of queued messages. - * - * @iclass - */ -static inline cnt_t chMBGetUsedCountI(mailbox_t *mbp) { - - chDbgCheckClassI(); - - return chSemGetCounterI(&mbp->mb_fullsem); -} - -/** - * @brief Returns the next message in the queue without removing it. - * @pre A message must be waiting in the queue for this function to work - * or it would return garbage. The correct way to use this macro is - * to use @p chMBGetFullCountI() and then use this macro, all within - * a lock state. - * - * @param[in] mbp the pointer to an initialized mailbox_t object - * @return The next message in queue. - * - * @iclass - */ -static inline msg_t chMBPeekI(mailbox_t *mbp) { - - chDbgCheckClassI(); - - return *mbp->mb_rdptr; -} - -#endif /* CH_CFG_USE_MAILBOXES == TRUE */ - -#endif /* _CHMBOXES_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/include/chmemcore.h b/firmware/ChibiOS_16/os/rt/include/chmemcore.h deleted file mode 100644 index 6fddcf0e47..0000000000 --- a/firmware/ChibiOS_16/os/rt/include/chmemcore.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chmemcore.h - * @brief Core memory manager macros and structures. - * - * @addtogroup memcore - * @{ - */ - -#ifndef _CHMEMCORE_H_ -#define _CHMEMCORE_H_ - -#if (CH_CFG_USE_MEMCORE == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Memory get function. - */ -typedef void *(*memgetfunc_t)(size_t size); - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @name Alignment support macros - */ -/** - * @brief Alignment size constant. - */ -#define MEM_ALIGN_SIZE sizeof(stkalign_t) - -/** - * @brief Alignment mask constant. - */ -#define MEM_ALIGN_MASK (MEM_ALIGN_SIZE - 1U) - -/** - * @brief Alignment helper macro. - */ -#define MEM_ALIGN_PREV(p) ((size_t)(p) & ~MEM_ALIGN_MASK) - -/** - * @brief Alignment helper macro. - */ -#define MEM_ALIGN_NEXT(p) MEM_ALIGN_PREV((size_t)(p) + MEM_ALIGN_MASK) - -/** - * @brief Returns whatever a pointer or memory size is aligned to - * the type @p stkalign_t. - */ -#define MEM_IS_ALIGNED(p) (((size_t)(p) & MEM_ALIGN_MASK) == 0U) -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void _core_init(void); - void *chCoreAlloc(size_t size); - void *chCoreAllocI(size_t size); - size_t chCoreGetStatusX(void); -#ifdef __cplusplus -} -#endif - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -#endif /* CH_CFG_USE_MEMCORE == TRUE */ - -#endif /* _CHMEMCORE_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/include/chmempools.h b/firmware/ChibiOS_16/os/rt/include/chmempools.h deleted file mode 100644 index 889d532f2f..0000000000 --- a/firmware/ChibiOS_16/os/rt/include/chmempools.h +++ /dev/null @@ -1,168 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chmempools.h - * @brief Memory Pools macros and structures. - * - * @addtogroup pools - * @{ - */ - -#ifndef _CHMEMPOOLS_H_ -#define _CHMEMPOOLS_H_ - -#if (CH_CFG_USE_MEMPOOLS == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if CH_CFG_USE_MEMCORE == FALSE -#error "CH_CFG_USE_MEMPOOLS requires CH_CFG_USE_MEMCORE" -#endif - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Memory pool free object header. - */ -struct pool_header { - struct pool_header *ph_next; /**< @brief Pointer to the next pool - header in the list. */ -}; - -/** - * @brief Memory pool descriptor. - */ -typedef struct { - struct pool_header *mp_next; /**< @brief Pointer to the header. */ - size_t mp_object_size; /**< @brief Memory pool objects - size. */ - memgetfunc_t mp_provider; /**< @brief Memory blocks provider - for this pool. */ -} memory_pool_t; - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @brief Data part of a static memory pool initializer. - * @details This macro should be used when statically initializing a - * memory pool that is part of a bigger structure. - * - * @param[in] name the name of the memory pool variable - * @param[in] size size of the memory pool contained objects - * @param[in] provider memory provider function for the memory pool - */ -#define _MEMORYPOOL_DATA(name, size, provider) \ - {NULL, size, provider} - -/** - * @brief Static memory pool initializer in hungry mode. - * @details Statically initialized memory pools require no explicit - * initialization using @p chPoolInit(). - * - * @param[in] name the name of the memory pool variable - * @param[in] size size of the memory pool contained objects - * @param[in] provider memory provider function for the memory pool or @p NULL - * if the pool is not allowed to grow automatically - */ -#define MEMORYPOOL_DECL(name, size, provider) \ - memory_pool_t name = _MEMORYPOOL_DATA(name, size, provider) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void chPoolObjectInit(memory_pool_t *mp, size_t size, memgetfunc_t provider); - void chPoolLoadArray(memory_pool_t *mp, void *p, size_t n); - void *chPoolAllocI(memory_pool_t *mp); - void *chPoolAlloc(memory_pool_t *mp); - void chPoolFreeI(memory_pool_t *mp, void *objp); - void chPoolFree(memory_pool_t *mp, void *objp); -#ifdef __cplusplus -} -#endif - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -/** - * @brief Adds an object to a memory pool. - * @pre The memory pool must be already been initialized. - * @pre The added object must be of the right size for the specified - * memory pool. - * @pre The added object must be memory aligned to the size of - * @p stkalign_t type. - * @note This function is just an alias for @p chPoolFree() and has been - * added for clarity. - * - * @param[in] mp pointer to a @p memory_pool_t structure - * @param[in] objp the pointer to the object to be added - * - * @api - */ -static inline void chPoolAdd(memory_pool_t *mp, void *objp) { - - chPoolFree(mp, objp); -} - -/** - * @brief Adds an object to a memory pool. - * @pre The memory pool must be already been initialized. - * @pre The added object must be of the right size for the specified - * memory pool. - * @pre The added object must be memory aligned to the size of - * @p stkalign_t type. - * @note This function is just an alias for @p chPoolFree() and has been - * added for clarity. - * - * @param[in] mp pointer to a @p memory_pool_t structure - * @param[in] objp the pointer to the object to be added - * - * @iclass - */ -static inline void chPoolAddI(memory_pool_t *mp, void *objp) { - - chDbgCheckClassI(); - - chPoolFreeI(mp, objp); -} - -#endif /* CH_CFG_USE_MEMPOOLS == TRUE */ - -#endif /* _CHMEMPOOLS_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/include/chmsg.h b/firmware/ChibiOS_16/os/rt/include/chmsg.h deleted file mode 100644 index f89d10eaac..0000000000 --- a/firmware/ChibiOS_16/os/rt/include/chmsg.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chmsg.h - * @brief Messages macros and structures. - * - * @addtogroup messages - * @{ - */ - -#ifndef _CHMSG_H_ -#define _CHMSG_H_ - -#if (CH_CFG_USE_MESSAGES == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - msg_t chMsgSend(thread_t *tp, msg_t msg); - thread_t * chMsgWait(void); - void chMsgRelease(thread_t *tp, msg_t msg); -#ifdef __cplusplus -} -#endif - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/** - * @brief Evaluates to @p true if the thread has pending messages. - * - * @param[in] tp pointer to the thread - * @return The pending messages status. - * - * @iclass - */ -static inline bool chMsgIsPendingI(thread_t *tp) { - - chDbgCheckClassI(); - - return (bool)(tp->p_msgqueue.p_next != (thread_t *)&tp->p_msgqueue); -} - -/** - * @brief Returns the message carried by the specified thread. - * @pre This function must be invoked immediately after exiting a call - * to @p chMsgWait(). - * - * @param[in] tp pointer to the thread - * @return The message carried by the sender. - * - * @api - */ -static inline msg_t chMsgGet(thread_t *tp) { - - return tp->p_msg; -} - -/** - * @brief Releases the thread waiting on top of the messages queue. - * @pre Invoke this function only after a message has been received - * using @p chMsgWait(). - * - * @param[in] tp pointer to the thread - * @param[in] msg message to be returned to the sender - * - * @sclass - */ -static inline void chMsgReleaseS(thread_t *tp, msg_t msg) { - - chDbgCheckClassS(); - - chSchWakeupS(tp, msg); -} - -#endif /* CH_CFG_USE_MESSAGES == TRUE */ - -#endif /* _CHMSG_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/include/chmtx.h b/firmware/ChibiOS_16/os/rt/include/chmtx.h deleted file mode 100644 index f7a4c7fae2..0000000000 --- a/firmware/ChibiOS_16/os/rt/include/chmtx.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chmtx.h - * @brief Mutexes macros and structures. - * - * @addtogroup mutexes - * @{ - */ - -#ifndef _CHMTX_H_ -#define _CHMTX_H_ - -#if (CH_CFG_USE_MUTEXES == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a mutex structure. - */ -typedef struct ch_mutex mutex_t; - -/** - * @brief Mutex structure. - */ -struct ch_mutex { - threads_queue_t m_queue; /**< @brief Queue of the threads sleeping - on this mutex. */ - thread_t *m_owner; /**< @brief Owner @p thread_t pointer or - @p NULL. */ - mutex_t *m_next; /**< @brief Next @p mutex_t into an - owner-list or @p NULL. */ -#if (CH_CFG_USE_MUTEXES_RECURSIVE == TRUE) || defined(__DOXYGEN__) - cnt_t m_cnt; /**< @brief Mutex recursion counter. */ -#endif -}; - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @brief Data part of a static mutex initializer. - * @details This macro should be used when statically initializing a mutex - * that is part of a bigger structure. - * - * @param[in] name the name of the mutex variable - */ -#if (CH_CFG_USE_MUTEXES_RECURSIVE == TRUE) || defined(__DOXYGEN__) -#define _MUTEX_DATA(name) {_THREADS_QUEUE_DATA(name.m_queue), NULL, NULL, 0} -#else -#define _MUTEX_DATA(name) {_THREADS_QUEUE_DATA(name.m_queue), NULL, NULL} -#endif - -/** - * @brief Static mutex initializer. - * @details Statically initialized mutexes require no explicit initialization - * using @p chMtxInit(). - * - * @param[in] name the name of the mutex variable - */ -#define MUTEX_DECL(name) mutex_t name = _MUTEX_DATA(name) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void chMtxObjectInit(mutex_t *mp); - void chMtxLock(mutex_t *mp); - void chMtxLockS(mutex_t *mp); - bool chMtxTryLock(mutex_t *mp); - bool chMtxTryLockS(mutex_t *mp); - void chMtxUnlock(mutex_t *mp); - void chMtxUnlockS(mutex_t *mp); - void chMtxUnlockAll(void); -#ifdef __cplusplus -} -#endif - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -/** - * @brief Returns @p true if the mutex queue contains at least a waiting - * thread. - * - * @param[out] mp pointer to a @p mutex_t structure - * @return The mutex queue status. - * - * @deprecated - * @sclass - */ -static inline bool chMtxQueueNotEmptyS(mutex_t *mp) { - - chDbgCheckClassS(); - - return queue_notempty(&mp->m_queue); -} - -/** - * @brief Returns the next mutex in the mutexes stack of the current thread. - * - * @return A pointer to the next mutex in the stack. - * @retval NULL if the stack is empty. - * - * @sclass - */ -static inline mutex_t *chMtxGetNextMutexS(void) { - - return chThdGetSelfX()->p_mtxlist; -} - -#endif /* CH_CFG_USE_MUTEXES == TRUE */ - -#endif /* _CHMTX_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/include/chqueues.h b/firmware/ChibiOS_16/os/rt/include/chqueues.h deleted file mode 100644 index de427d777b..0000000000 --- a/firmware/ChibiOS_16/os/rt/include/chqueues.h +++ /dev/null @@ -1,437 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chqueues.h - * @brief I/O Queues macros and structures. - * - * @addtogroup io_queues - * @{ - */ - -#ifndef _CHQUEUES_H_ -#define _CHQUEUES_H_ - -#if (CH_CFG_USE_QUEUES == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @name Queue functions returned status value - * @{ - */ -#define Q_OK MSG_OK /**< @brief Operation successful. */ -#define Q_TIMEOUT MSG_TIMEOUT /**< @brief Timeout condition. */ -#define Q_RESET MSG_RESET /**< @brief Queue has been reset. */ -#define Q_EMPTY (msg_t)-3 /**< @brief Queue empty. */ -#define Q_FULL (msg_t)-4 /**< @brief Queue full, */ -/** @} */ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a generic I/O queue structure. - */ -typedef struct io_queue io_queue_t; - -/** @brief Queue notification callback type.*/ -typedef void (*qnotify_t)(io_queue_t *qp); - -/** - * @brief Generic I/O queue structure. - * @details This structure represents a generic Input or Output asymmetrical - * queue. The queue is asymmetrical because one end is meant to be - * accessed from a thread context, and thus can be blocking, the other - * end is accessible from interrupt handlers or from within a kernel - * lock zone (see I-Locked and S-Locked states in - * @ref system_states) and is non-blocking. - */ -struct io_queue { - threads_queue_t q_waiting; /**< @brief Queue of waiting threads. */ - volatile size_t q_counter; /**< @brief Resources counter. */ - uint8_t *q_buffer; /**< @brief Pointer to the queue buffer.*/ - uint8_t *q_top; /**< @brief Pointer to the first location - after the buffer. */ - uint8_t *q_wrptr; /**< @brief Write pointer. */ - uint8_t *q_rdptr; /**< @brief Read pointer. */ - qnotify_t q_notify; /**< @brief Data notification callback. */ - void *q_link; /**< @brief Application defined field. */ -}; - -/** - * @extends io_queue_t - * - * @brief Type of an input queue structure. - * @details This structure represents a generic asymmetrical input queue. - * Writing to the queue is non-blocking and can be performed from - * interrupt handlers or from within a kernel lock zone (see - * I-Locked and S-Locked states in @ref system_states). - * Reading the queue can be a blocking operation and is supposed to - * be performed by a system thread. - */ -typedef io_queue_t input_queue_t; - -/** - * @extends io_queue_t - * - * @brief Type of an output queue structure. - * @details This structure represents a generic asymmetrical output queue. - * Reading from the queue is non-blocking and can be performed from - * interrupt handlers or from within a kernel lock zone (see - * I-Locked and S-Locked states in @ref system_states). - * Writing the queue can be a blocking operation and is supposed to - * be performed by a system thread. - */ -typedef io_queue_t output_queue_t; - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @brief Data part of a static input queue initializer. - * @details This macro should be used when statically initializing an - * input queue that is part of a bigger structure. - * - * @param[in] name the name of the input queue variable - * @param[in] buffer pointer to the queue buffer area - * @param[in] size size of the queue buffer area - * @param[in] inotify input notification callback pointer - * @param[in] link application defined pointer - */ -#define _INPUTQUEUE_DATA(name, buffer, size, inotify, link) { \ - _THREADS_QUEUE_DATA(name), \ - 0U, \ - (uint8_t *)(buffer), \ - (uint8_t *)(buffer) + (size), \ - (uint8_t *)(buffer), \ - (uint8_t *)(buffer), \ - (inotify), \ - (link) \ -} - -/** - * @brief Static input queue initializer. - * @details Statically initialized input queues require no explicit - * initialization using @p chIQInit(). - * - * @param[in] name the name of the input queue variable - * @param[in] buffer pointer to the queue buffer area - * @param[in] size size of the queue buffer area - * @param[in] inotify input notification callback pointer - * @param[in] link application defined pointer - */ -#define INPUTQUEUE_DECL(name, buffer, size, inotify, link) \ - input_queue_t name = _INPUTQUEUE_DATA(name, buffer, size, inotify, link) - -/** - * @brief Data part of a static output queue initializer. - * @details This macro should be used when statically initializing an - * output queue that is part of a bigger structure. - * - * @param[in] name the name of the output queue variable - * @param[in] buffer pointer to the queue buffer area - * @param[in] size size of the queue buffer area - * @param[in] onotify output notification callback pointer - * @param[in] link application defined pointer - */ -#define _OUTPUTQUEUE_DATA(name, buffer, size, onotify, link) { \ - _THREADS_QUEUE_DATA(name), \ - (size), \ - (uint8_t *)(buffer), \ - (uint8_t *)(buffer) + (size), \ - (uint8_t *)(buffer), \ - (uint8_t *)(buffer), \ - (onotify), \ - (link) \ -} - -/** - * @brief Static output queue initializer. - * @details Statically initialized output queues require no explicit - * initialization using @p chOQInit(). - * - * @param[in] name the name of the output queue variable - * @param[in] buffer pointer to the queue buffer area - * @param[in] size size of the queue buffer area - * @param[in] onotify output notification callback pointer - * @param[in] link application defined pointer - */ -#define OUTPUTQUEUE_DECL(name, buffer, size, onotify, link) \ - output_queue_t name = _OUTPUTQUEUE_DATA(name, buffer, size, onotify, link) - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Returns the queue's buffer size. - * - * @param[in] qp pointer to a @p io_queue_t structure - * @return The buffer size. - * - * @xclass - */ -#define chQSizeX(qp) \ - /*lint -save -e9033 [10.8] The cast is safe.*/ \ - ((size_t)((qp)->q_top - (qp)->q_buffer)) \ - /*lint -restore*/ - -/** - * @brief Queue space. - * @details Returns the used space if used on an input queue or the empty - * space if used on an output queue. - * - * @param[in] qp pointer to a @p io_queue_t structure - * @return The buffer space. - * - * @iclass - */ -#define chQSpaceI(qp) ((qp)->q_counter) - -/** - * @brief Returns the queue application-defined link. - * - * @param[in] qp pointer to a @p io_queue_t structure - * @return The application-defined link. - * - * @xclass - */ -#define chQGetLinkX(qp) ((qp)->q_link) -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void chIQObjectInit(input_queue_t *iqp, uint8_t *bp, size_t size, - qnotify_t infy, void *link); - void chIQResetI(input_queue_t *iqp); - msg_t chIQPutI(input_queue_t *iqp, uint8_t b); - msg_t chIQGetTimeout(input_queue_t *iqp, systime_t timeout); - size_t chIQReadTimeout(input_queue_t *iqp, uint8_t *bp, - size_t n, systime_t timeout); - - void chOQObjectInit(output_queue_t *oqp, uint8_t *bp, size_t size, - qnotify_t onfy, void *link); - void chOQResetI(output_queue_t *oqp); - msg_t chOQPutTimeout(output_queue_t *oqp, uint8_t b, systime_t timeout); - msg_t chOQGetI(output_queue_t *oqp); - size_t chOQWriteTimeout(output_queue_t *oqp, const uint8_t *bp, - size_t n, systime_t timeout); -#ifdef __cplusplus -} -#endif - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -/** - * @brief Returns the filled space into an input queue. - * - * @param[in] iqp pointer to an @p input_queue_t structure - * @return The number of full bytes in the queue. - * @retval 0 if the queue is empty. - * - * @iclass - */ -static inline size_t chIQGetFullI(input_queue_t *iqp) { - - chDbgCheckClassI(); - - return (size_t)chQSpaceI(iqp); -} - -/** - * @brief Returns the empty space into an input queue. - * - * @param[in] iqp pointer to an @p input_queue_t structure - * @return The number of empty bytes in the queue. - * @retval 0 if the queue is full. - * - * @iclass - */ -static inline size_t chIQGetEmptyI(input_queue_t *iqp) { - - chDbgCheckClassI(); - - return (size_t)(chQSizeX(iqp) - chQSpaceI(iqp)); -} - -/** - * @brief Evaluates to @p true if the specified input queue is empty. - * - * @param[in] iqp pointer to an @p input_queue_t structure - * @return The queue status. - * @retval false if the queue is not empty. - * @retval true if the queue is empty. - * - * @iclass - */ -static inline bool chIQIsEmptyI(input_queue_t *iqp) { - - chDbgCheckClassI(); - - return (bool)(chQSpaceI(iqp) == 0U); -} - -/** - * @brief Evaluates to @p true if the specified input queue is full. - * - * @param[in] iqp pointer to an @p input_queue_t structure - * @return The queue status. - * @retval false if the queue is not full. - * @retval true if the queue is full. - * - * @iclass - */ -static inline bool chIQIsFullI(input_queue_t *iqp) { - - chDbgCheckClassI(); - - /*lint -save -e9007 [13.5] No side effects.*/ - return (bool)((iqp->q_wrptr == iqp->q_rdptr) && (iqp->q_counter != 0U)); - /*lint -restore*/ -} - -/** - * @brief Input queue read. - * @details This function reads a byte value from an input queue. If the queue - * is empty then the calling thread is suspended until a byte arrives - * in the queue. - * - * @param[in] iqp pointer to an @p input_queue_t structure - * @return A byte value from the queue. - * @retval Q_RESET if the queue has been reset. - * - * @api - */ -static inline msg_t chIQGet(input_queue_t *iqp) { - - return chIQGetTimeout(iqp, TIME_INFINITE); -} - -/** - * @brief Returns the filled space into an output queue. - * - * @param[in] oqp pointer to an @p output_queue_t structure - * @return The number of full bytes in the queue. - * @retval 0 if the queue is empty. - * - * @iclass - */ -static inline size_t chOQGetFullI(output_queue_t *oqp) { - - chDbgCheckClassI(); - - return (size_t)(chQSizeX(oqp) - chQSpaceI(oqp)); -} - -/** - * @brief Returns the empty space into an output queue. - * - * @param[in] oqp pointer to an @p output_queue_t structure - * @return The number of empty bytes in the queue. - * @retval 0 if the queue is full. - * - * @iclass - */ -static inline size_t chOQGetEmptyI(output_queue_t *oqp) { - - chDbgCheckClassI(); - - return (size_t)chQSpaceI(oqp); -} - -/** - * @brief Evaluates to @p true if the specified output queue is empty. - * - * @param[in] oqp pointer to an @p output_queue_t structure - * @return The queue status. - * @retval false if the queue is not empty. - * @retval true if the queue is empty. - * - * @iclass - */ -static inline bool chOQIsEmptyI(output_queue_t *oqp) { - - chDbgCheckClassI(); - - /*lint -save -e9007 [13.5] No side effects.*/ - return (bool)((oqp->q_wrptr == oqp->q_rdptr) && (oqp->q_counter != 0U)); - /*lint -restore*/ -} - -/** - * @brief Evaluates to @p true if the specified output queue is full. - * - * @param[in] oqp pointer to an @p output_queue_t structure - * @return The queue status. - * @retval false if the queue is not full. - * @retval true if the queue is full. - * - * @iclass - */ -static inline bool chOQIsFullI(output_queue_t *oqp) { - - chDbgCheckClassI(); - - return (bool)(chQSpaceI(oqp) == 0U); -} - -/** - * @brief Output queue write. - * @details This function writes a byte value to an output queue. If the queue - * is full then the calling thread is suspended until there is space - * in the queue. - * - * @param[in] oqp pointer to an @p output_queue_t structure - * @param[in] b the byte value to be written in the queue - * @return The operation status. - * @retval Q_OK if the operation succeeded. - * @retval Q_RESET if the queue has been reset. - * - * @api - */ -static inline msg_t chOQPut(output_queue_t *oqp, uint8_t b) { - - return chOQPutTimeout(oqp, b, TIME_INFINITE); -} - -#endif /* CH_CFG_USE_QUEUES == TRUE */ - -#endif /* _CHQUEUES_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/include/chregistry.h b/firmware/ChibiOS_16/os/rt/include/chregistry.h deleted file mode 100644 index 036cc378ec..0000000000 --- a/firmware/ChibiOS_16/os/rt/include/chregistry.h +++ /dev/null @@ -1,184 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chregistry.h - * @brief Threads registry macros and structures. - * - * @addtogroup registry - * @{ - */ - -#ifndef _CHREGISTRY_H_ -#define _CHREGISTRY_H_ - -#if (CH_CFG_USE_REGISTRY == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/** - * @brief ChibiOS/RT memory signature record. - */ -typedef struct { - char ch_identifier[4]; /**< @brief Always set to "main". */ - uint8_t ch_zero; /**< @brief Must be zero. */ - uint8_t ch_size; /**< @brief Size of this structure. */ - uint16_t ch_version; /**< @brief Encoded ChibiOS/RT version. */ - uint8_t ch_ptrsize; /**< @brief Size of a pointer. */ - uint8_t ch_timesize; /**< @brief Size of a @p systime_t. */ - uint8_t ch_threadsize; /**< @brief Size of a @p thread_t. */ - uint8_t cf_off_prio; /**< @brief Offset of @p p_prio field. */ - uint8_t cf_off_ctx; /**< @brief Offset of @p p_ctx field. */ - uint8_t cf_off_newer; /**< @brief Offset of @p p_newer field. */ - uint8_t cf_off_older; /**< @brief Offset of @p p_older field. */ - uint8_t cf_off_name; /**< @brief Offset of @p p_name field. */ - uint8_t cf_off_stklimit; /**< @brief Offset of @p p_stklimit - field. */ - uint8_t cf_off_state; /**< @brief Offset of @p p_state field. */ - uint8_t cf_off_flags; /**< @brief Offset of @p p_flags field. */ - uint8_t cf_off_refs; /**< @brief Offset of @p p_refs field. */ - uint8_t cf_off_preempt; /**< @brief Offset of @p p_preempt - field. */ - uint8_t cf_off_time; /**< @brief Offset of @p p_time field. */ -} chdebug_t; - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @brief Removes a thread from the registry list. - * @note This macro is not meant for use in application code. - * - * @param[in] tp thread to remove from the registry - */ -#define REG_REMOVE(tp) { \ - (tp)->p_older->p_newer = (tp)->p_newer; \ - (tp)->p_newer->p_older = (tp)->p_older; \ -} - -/** - * @brief Adds a thread to the registry list. - * @note This macro is not meant for use in application code. - * - * @param[in] tp thread to add to the registry - */ -#define REG_INSERT(tp) { \ - (tp)->p_newer = (thread_t *)&ch.rlist; \ - (tp)->p_older = ch.rlist.r_older; \ - (tp)->p_older->p_newer = (tp); \ - ch.rlist.r_older = (tp); \ -} - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - extern ROMCONST chdebug_t ch_debug; - thread_t *chRegFirstThread(void); - thread_t *chRegNextThread(thread_t *tp); -#ifdef __cplusplus -} -#endif - -#endif /* CH_CFG_USE_REGISTRY == TRUE */ - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -/** - * @brief Sets the current thread name. - * @pre This function only stores the pointer to the name if the option - * @p CH_CFG_USE_REGISTRY is enabled else no action is performed. - * - * @param[in] name thread name as a zero terminated string - * - * @api - */ -static inline void chRegSetThreadName(const char *name) { - -#if CH_CFG_USE_REGISTRY == TRUE - ch.rlist.r_current->p_name = name; -#else - (void)name; -#endif -} - -/** - * @brief Returns the name of the specified thread. - * @pre This function only returns the pointer to the name if the option - * @p CH_CFG_USE_REGISTRY is enabled else @p NULL is returned. - * - * @param[in] tp pointer to the thread - * - * @return Thread name as a zero terminated string. - * @retval NULL if the thread name has not been set. - * - */ -static inline const char *chRegGetThreadNameX(thread_t *tp) { - -#if CH_CFG_USE_REGISTRY == TRUE - return tp->p_name; -#else - (void)tp; - return NULL; -#endif -} - -/** - * @brief Changes the name of the specified thread. - * @pre This function only stores the pointer to the name if the option - * @p CH_CFG_USE_REGISTRY is enabled else no action is performed. - * - * @param[in] tp pointer to the thread - * @param[in] name thread name as a zero terminated string - * - * @xclass - */ -static inline void chRegSetThreadNameX(thread_t *tp, const char *name) { - -#if CH_CFG_USE_REGISTRY == TRUE - tp->p_name = name; -#else - (void)tp; - (void)name; -#endif -} - -#endif /* _CHREGISTRY_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/include/chschd.h b/firmware/ChibiOS_16/os/rt/include/chschd.h deleted file mode 100644 index aa9e0d329d..0000000000 --- a/firmware/ChibiOS_16/os/rt/include/chschd.h +++ /dev/null @@ -1,781 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chschd.h - * @brief Scheduler macros and structures. - * - * @addtogroup scheduler - * @{ - */ - -#ifndef _CHSCHD_H_ -#define _CHSCHD_H_ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @name Wakeup status codes - * @{ - */ -#define MSG_OK (msg_t)0 /**< @brief Normal wakeup message. */ -#define MSG_TIMEOUT (msg_t)-1 /**< @brief Wakeup caused by a timeout - condition. */ -#define MSG_RESET (msg_t)-2 /**< @brief Wakeup caused by a reset - condition. */ -/** @} */ - -/** - * @name Priority constants - * @{ - */ -#define NOPRIO (tprio_t)0 /**< @brief Ready list header - priority. */ -#define IDLEPRIO (tprio_t)1 /**< @brief Idle priority. */ -#define LOWPRIO (tprio_t)2 /**< @brief Lowest priority. */ -#define NORMALPRIO (tprio_t)64 /**< @brief Normal priority. */ -#define HIGHPRIO (tprio_t)127 /**< @brief Highest priority. */ -#define ABSPRIO (tprio_t)255 /**< @brief Greatest priority. */ -/** @} */ - -/** - * @name Thread states - * @{ - */ -#define CH_STATE_READY (tstate_t)0 /**< @brief Waiting on the - ready list. */ -#define CH_STATE_CURRENT (tstate_t)1 /**< @brief Currently running. */ -#define CH_STATE_WTSTART (tstate_t)2 /**< @brief Just created. */ -#define CH_STATE_SUSPENDED (tstate_t)3 /**< @brief Suspended state. */ -#define CH_STATE_QUEUED (tstate_t)4 /**< @brief On an I/O queue. */ -#define CH_STATE_WTSEM (tstate_t)5 /**< @brief On a semaphore. */ -#define CH_STATE_WTMTX (tstate_t)6 /**< @brief On a mutex. */ -#define CH_STATE_WTCOND (tstate_t)7 /**< @brief On a cond.variable.*/ -#define CH_STATE_SLEEPING (tstate_t)8 /**< @brief Sleeping. */ -#define CH_STATE_WTEXIT (tstate_t)9 /**< @brief Waiting a thread. */ -#define CH_STATE_WTOREVT (tstate_t)10 /**< @brief One event. */ -#define CH_STATE_WTANDEVT (tstate_t)11 /**< @brief Several events. */ -#define CH_STATE_SNDMSGQ (tstate_t)12 /**< @brief Sending a message, - in queue. */ -#define CH_STATE_SNDMSG (tstate_t)13 /**< @brief Sent a message, - waiting answer. */ -#define CH_STATE_WTMSG (tstate_t)14 /**< @brief Waiting for a - message. */ -#define CH_STATE_FINAL (tstate_t)15 /**< @brief Thread terminated. */ - -/** - * @brief Thread states as array of strings. - * @details Each element in an array initialized with this macro can be - * indexed using the numeric thread state values. - */ -#define CH_STATE_NAMES \ - "READY", "CURRENT", "WTSTART", "SUSPENDED", "QUEUED", "WTSEM", "WTMTX", \ - "WTCOND", "SLEEPING", "WTEXIT", "WTOREVT", "WTANDEVT", "SNDMSGQ", \ - "SNDMSG", "WTMSG", "FINAL" -/** @} */ - -/** - * @name Thread flags and attributes - * @{ - */ -#define CH_FLAG_MODE_MASK (tmode_t)3U /**< @brief Thread memory mode - mask. */ -#define CH_FLAG_MODE_STATIC (tmode_t)0U /**< @brief Static thread. */ -#define CH_FLAG_MODE_HEAP (tmode_t)1U /**< @brief Thread allocated - from a Memory Heap. */ -#define CH_FLAG_MODE_MPOOL (tmode_t)2U /**< @brief Thread allocated - from a Memory Pool. */ -#define CH_FLAG_TERMINATE (tmode_t)4U /**< @brief Termination requested - flag. */ -/** @} */ - -/** - * @name Working Areas and Alignment - */ -/** - * @brief Enforces a correct alignment for a stack area size value. - * - * @param[in] n the stack size to be aligned to the next stack - * alignment boundary - * @return The aligned stack size. - * - * @api - */ -#define THD_ALIGN_STACK_SIZE(n) \ - (((((size_t)(n)) - 1U) | (sizeof(stkalign_t) - 1U)) + 1U) - -/** - * @brief Calculates the total Working Area size. - * - * @param[in] n the stack size to be assigned to the thread - * @return The total used memory in bytes. - * - * @api - */ -#define THD_WORKING_AREA_SIZE(n) \ - THD_ALIGN_STACK_SIZE(sizeof(thread_t) + PORT_WA_SIZE(n)) - -/** - * @brief Static working area allocation. - * @details This macro is used to allocate a static thread working area - * aligned as both position and size. - * - * @param[in] s the name to be assigned to the stack array - * @param[in] n the stack size to be assigned to the thread - * - * @api - */ -#define THD_WORKING_AREA(s, n) \ - stkalign_t s[THD_WORKING_AREA_SIZE(n) / sizeof(stkalign_t)] -/** @} */ - -/** - * @name Threads abstraction macros - */ -/** - * @brief Thread declaration macro. - * @note Thread declarations should be performed using this macro because - * the port layer could define optimizations for thread functions. - */ -#define THD_FUNCTION(tname, arg) PORT_THD_FUNCTION(tname, arg) -/** @} */ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Generic threads single link list, it works like a stack. - */ -struct ch_threads_list { - thread_t *p_next; /**< @brief Next in the list/queue. */ -}; - -/** - * @brief Generic threads bidirectional linked list header and element. - */ -struct ch_threads_queue { - thread_t *p_next; /**< @brief Next in the list/queue. */ - thread_t *p_prev; /**< @brief Previous in the queue. */ -}; - -/** - * @brief Structure representing a thread. - * @note Not all the listed fields are always needed, by switching off some - * not needed ChibiOS/RT subsystems it is possible to save RAM space - * by shrinking this structure. - */ -struct ch_thread { - thread_t *p_next; /**< @brief Next in the list/queue. */ - /* End of the fields shared with the threads_list_t structure.*/ - thread_t *p_prev; /**< @brief Previous in the queue. */ - /* End of the fields shared with the threads_queue_t structure.*/ - tprio_t p_prio; /**< @brief Thread priority. */ - struct context p_ctx; /**< @brief Processor context. */ -#if (CH_CFG_USE_REGISTRY == TRUE) || defined(__DOXYGEN__) - thread_t *p_newer; /**< @brief Newer registry element. */ - thread_t *p_older; /**< @brief Older registry element. */ -#endif - /* End of the fields shared with the ReadyList structure. */ -#if (CH_CFG_USE_REGISTRY == TRUE) || defined(__DOXYGEN__) - /** - * @brief Thread name or @p NULL. - */ - const char *p_name; -#endif -#if (CH_DBG_ENABLE_STACK_CHECK == TRUE) || defined(__DOXYGEN__) - /** - * @brief Thread stack boundary. - */ - stkalign_t *p_stklimit; -#endif - /** - * @brief Current thread state. - */ - tstate_t p_state; - /** - * @brief Various thread flags. - */ - tmode_t p_flags; -#if (CH_CFG_USE_DYNAMIC == TRUE) || defined(__DOXYGEN__) - /** - * @brief References to this thread. - */ - trefs_t p_refs; -#endif - /** - * @brief Number of ticks remaining to this thread. - */ -#if (CH_CFG_TIME_QUANTUM > 0) || defined(__DOXYGEN__) - tslices_t p_preempt; -#endif -#if (CH_DBG_THREADS_PROFILING == TRUE) || defined(__DOXYGEN__) - /** - * @brief Thread consumed time in ticks. - * @note This field can overflow. - */ - volatile systime_t p_time; -#endif - /** - * @brief State-specific fields. - * @note All the fields declared in this union are only valid in the - * specified state or condition and are thus volatile. - */ - union { - /** - * @brief Thread wakeup code. - * @note This field contains the low level message sent to the thread - * by the waking thread or interrupt handler. The value is valid - * after exiting the @p chSchWakeupS() function. - */ - msg_t rdymsg; - /** - * @brief Thread exit code. - * @note The thread termination code is stored in this field in order - * to be retrieved by the thread performing a @p chThdWait() on - * this thread. - */ - msg_t exitcode; - /** - * @brief Pointer to a generic "wait" object. - * @note This field is used to get a generic pointer to a synchronization - * object and is valid when the thread is in one of the wait - * states. - */ - void *wtobjp; - /** - * @brief Pointer to a generic thread reference object. - * @note This field is used to get a pointer to a synchronization - * object and is valid when the thread is in @p CH_STATE_SUSPENDED - * state. - */ - thread_reference_t *wttrp; -#if (CH_CFG_USE_SEMAPHORES == TRUE) || defined(__DOXYGEN__) - /** - * @brief Pointer to a generic semaphore object. - * @note This field is used to get a pointer to a synchronization - * object and is valid when the thread is in @p CH_STATE_WTSEM - * state. - */ - struct ch_semaphore *wtsemp; -#endif -#if (CH_CFG_USE_MUTEXES == TRUE) || defined(__DOXYGEN__) - /** - * @brief Pointer to a generic mutex object. - * @note This field is used to get a pointer to a synchronization - * object and is valid when the thread is in @p CH_STATE_WTMTX - * state. - */ - struct ch_mutex *wtmtxp; -#endif -#if (CH_CFG_USE_EVENTS == TRUE) || defined(__DOXYGEN__) - /** - * @brief Enabled events mask. - * @note This field is only valid while the thread is in the - * @p CH_STATE_WTOREVT or @p CH_STATE_WTANDEVT states. - */ - eventmask_t ewmask; -#endif - } p_u; -#if (CH_CFG_USE_WAITEXIT == TRUE) || defined(__DOXYGEN__) - /** - * @brief Termination waiting list. - */ - threads_list_t p_waiting; -#endif -#if (CH_CFG_USE_MESSAGES == TRUE) || defined(__DOXYGEN__) - /** - * @brief Messages queue. - */ - threads_queue_t p_msgqueue; - /** - * @brief Thread message. - */ - msg_t p_msg; -#endif -#if (CH_CFG_USE_EVENTS == TRUE) || defined(__DOXYGEN__) - /** - * @brief Pending events mask. - */ - eventmask_t p_epending; -#endif -#if (CH_CFG_USE_MUTEXES == TRUE) || defined(__DOXYGEN__) - /** - * @brief List of the mutexes owned by this thread. - * @note The list is terminated by a @p NULL in this field. - */ - struct ch_mutex *p_mtxlist; - /** - * @brief Thread's own, non-inherited, priority. - */ - tprio_t p_realprio; -#endif -#if ((CH_CFG_USE_DYNAMIC == TRUE) && (CH_CFG_USE_MEMPOOLS == TRUE)) || \ - defined(__DOXYGEN__) - /** - * @brief Memory Pool where the thread workspace is returned. - */ - void *p_mpool; -#endif -#if (CH_DBG_STATISTICS == TRUE) || defined(__DOXYGEN__) - /** - * @brief Thread statistics. - */ - time_measurement_t p_stats; -#endif -#if defined(CH_CFG_THREAD_EXTRA_FIELDS) - /* Extra fields defined in chconf.h.*/ - CH_CFG_THREAD_EXTRA_FIELDS -#endif -}; - -/** - * @extends virtual_timers_list_t - * - * @brief Virtual Timer descriptor structure. - */ -struct ch_virtual_timer { - virtual_timer_t *vt_next; /**< @brief Next timer in the list. */ - virtual_timer_t *vt_prev; /**< @brief Previous timer in the list. */ - systime_t vt_delta; /**< @brief Time delta before timeout. */ - vtfunc_t vt_func; /**< @brief Timer callback function - pointer. */ - void *vt_par; /**< @brief Timer callback function - parameter. */ -}; - -/** - * @brief Virtual timers list header. - * @note The timers list is implemented as a double link bidirectional list - * in order to make the unlink time constant, the reset of a virtual - * timer is often used in the code. - */ -struct ch_virtual_timers_list { - virtual_timer_t *vt_next; /**< @brief Next timer in the delta - list. */ - virtual_timer_t *vt_prev; /**< @brief Last timer in the delta - list. */ - systime_t vt_delta; /**< @brief Must be initialized to -1. */ -#if (CH_CFG_ST_TIMEDELTA == 0) || defined(__DOXYGEN__) - volatile systime_t vt_systime; /**< @brief System Time counter. */ -#endif -#if (CH_CFG_ST_TIMEDELTA > 0) || defined(__DOXYGEN__) - /** - * @brief System time of the last tick event. - */ - systime_t vt_lasttime;/**< @brief System time of the last - tick event. */ -#endif -}; - -/** - * @extends threads_queue_t - */ -struct ch_ready_list { - threads_queue_t r_queue; /**< @brief Threads queue. */ - tprio_t r_prio; /**< @brief This field must be - initialized to zero. */ - struct context r_ctx; /**< @brief Not used, present because - offsets. */ -#if (CH_CFG_USE_REGISTRY == TRUE) || defined(__DOXYGEN__) - thread_t *r_newer; /**< @brief Newer registry element. */ - thread_t *r_older; /**< @brief Older registry element. */ -#endif - /* End of the fields shared with the thread_t structure.*/ - thread_t *r_current; /**< @brief The currently running - thread. */ -}; - -/** - * @brief System debug data structure. - */ -struct ch_system_debug { - /** - * @brief Pointer to the panic message. - * @details This pointer is meant to be accessed through the debugger, it is - * written once and then the system is halted. - * @note Accesses to this pointer must never be optimized out so the - * field itself is declared volatile. - */ - const char * volatile panic_msg; -#if (CH_DBG_SYSTEM_STATE_CHECK == TRUE) || defined(__DOXYGEN__) - /** - * @brief ISR nesting level. - */ - cnt_t isr_cnt; - /** - * @brief Lock nesting level. - */ - cnt_t lock_cnt; -#endif -#if (CH_DBG_ENABLE_TRACE == TRUE) || defined(__DOXYGEN__) - /** - * @brief Public trace buffer. - */ - ch_trace_buffer_t trace_buffer; -#endif -}; - -/** - * @brief System data structure. - * @note This structure contain all the data areas used by the OS except - * stacks. - */ -struct ch_system { - /** - * @brief Ready list header. - */ - ready_list_t rlist; - /** - * @brief Virtual timers delta list header. - */ - virtual_timers_list_t vtlist; - /** - * @brief System debug. - */ - system_debug_t dbg; - /** - * @brief Main thread descriptor. - */ - thread_t mainthread; -#if (CH_CFG_USE_TM == TRUE) || defined(__DOXYGEN__) - /** - * @brief Time measurement calibration data. - */ - tm_calibration_t tm; -#endif -#if (CH_DBG_STATISTICS == TRUE) || defined(__DOXYGEN__) - /** - * @brief Global kernel statistics. - */ - kernel_stats_t kernel_stats; -#endif -#if (CH_CFG_NO_IDLE_THREAD == FALSE) || defined(__DOXYGEN__) - /** - * @brief Idle thread working area. - */ - THD_WORKING_AREA(idle_thread_wa, PORT_IDLE_THREAD_STACK_SIZE); -#endif -}; - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @brief Returns the priority of the first thread on the given ready list. - * - * @notapi - */ -#define firstprio(rlp) ((rlp)->p_next->p_prio) - -/** - * @brief Current thread pointer access macro. - * @note This macro is not meant to be used in the application code but - * only from within the kernel, use the @p chThdSelf() API instead. - * @note It is forbidden to use this macro in order to change the pointer - * (currp = something), use @p setcurrp() instead. - */ -#define currp ch.rlist.r_current - -/** - * @brief Current thread pointer change macro. - * @note This macro is not meant to be used in the application code but - * only from within the kernel. - * - * @notapi - */ -#define setcurrp(tp) (currp = (tp)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -extern ch_system_t ch; -#endif - -/* - * Scheduler APIs. - */ -#ifdef __cplusplus -extern "C" { -#endif - void _scheduler_init(void); - thread_t *chSchReadyI(thread_t *tp); - void chSchGoSleepS(tstate_t newstate); - msg_t chSchGoSleepTimeoutS(tstate_t newstate, systime_t time); - void chSchWakeupS(thread_t *ntp, msg_t msg); - void chSchRescheduleS(void); - bool chSchIsPreemptionRequired(void); - void chSchDoRescheduleBehind(void); - void chSchDoRescheduleAhead(void); - void chSchDoReschedule(void); -#if CH_CFG_OPTIMIZE_SPEED == FALSE - void queue_prio_insert(thread_t *tp, threads_queue_t *tqp); - void queue_insert(thread_t *tp, threads_queue_t *tqp); - thread_t *queue_fifo_remove(threads_queue_t *tqp); - thread_t *queue_lifo_remove(threads_queue_t *tqp); - thread_t *queue_dequeue(thread_t *tp); - void list_insert(thread_t *tp, threads_list_t *tlp); - thread_t *list_remove(threads_list_t *tlp); -#endif /* CH_CFG_OPTIMIZE_SPEED == FALSE */ -#ifdef __cplusplus -} -#endif - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -/** - * @brief Threads list initialization. - * - * @param[in] tlp pointer to the threads list object - * - * @notapi - */ -static inline void list_init(threads_list_t *tlp) { - - tlp->p_next = (thread_t *)tlp; -} - -/** - * @brief Evaluates to @p true if the specified threads list is empty. - * - * @param[in] tlp pointer to the threads list object - * @return The status of the list. - * - * @notapi - */ -static inline bool list_isempty(threads_list_t *tlp) { - - return (bool)(tlp->p_next == (thread_t *)tlp); -} - -/** - * @brief Evaluates to @p true if the specified threads list is not empty. - * - * @param[in] tlp pointer to the threads list object - * @return The status of the list. - * - * @notapi - */ -static inline bool list_notempty(threads_list_t *tlp) { - - return (bool)(tlp->p_next != (thread_t *)tlp); -} - -/** - * @brief Threads queue initialization. - * - * @param[in] tqp pointer to the threads queue object - * - * @notapi - */ -static inline void queue_init(threads_queue_t *tqp) { - - tqp->p_next = (thread_t *)tqp; - tqp->p_prev = (thread_t *)tqp; -} - -/** - * @brief Evaluates to @p true if the specified threads queue is empty. - * - * @param[in] tqp pointer to the threads queue object - * @return The status of the queue. - * - * @notapi - */ -static inline bool queue_isempty(const threads_queue_t *tqp) { - - return (bool)(tqp->p_next == (const thread_t *)tqp); -} - -/** - * @brief Evaluates to @p true if the specified threads queue is not empty. - * - * @param[in] tqp pointer to the threads queue object - * @return The status of the queue. - * - * @notapi - */ -static inline bool queue_notempty(const threads_queue_t *tqp) { - - return (bool)(tqp->p_next != (const thread_t *)tqp); -} - -/* If the performance code path has been chosen then all the following - functions are inlined into the various kernel modules.*/ -#if CH_CFG_OPTIMIZE_SPEED == TRUE -static inline void list_insert(thread_t *tp, threads_list_t *tlp) { - - tp->p_next = tlp->p_next; - tlp->p_next = tp; -} - -static inline thread_t *list_remove(threads_list_t *tlp) { - - thread_t *tp = tlp->p_next; - tlp->p_next = tp->p_next; - - return tp; -} - -static inline void queue_prio_insert(thread_t *tp, threads_queue_t *tqp) { - - thread_t *cp = (thread_t *)tqp; - do { - cp = cp->p_next; - } while ((cp != (thread_t *)tqp) && (cp->p_prio >= tp->p_prio)); - tp->p_next = cp; - tp->p_prev = cp->p_prev; - tp->p_prev->p_next = tp; - cp->p_prev = tp; -} - -static inline void queue_insert(thread_t *tp, threads_queue_t *tqp) { - - tp->p_next = (thread_t *)tqp; - tp->p_prev = tqp->p_prev; - tp->p_prev->p_next = tp; - tqp->p_prev = tp; -} - -static inline thread_t *queue_fifo_remove(threads_queue_t *tqp) { - thread_t *tp = tqp->p_next; - - tqp->p_next = tp->p_next; - tqp->p_next->p_prev = (thread_t *)tqp; - - return tp; -} - -static inline thread_t *queue_lifo_remove(threads_queue_t *tqp) { - thread_t *tp = tqp->p_prev; - - tqp->p_prev = tp->p_prev; - tqp->p_prev->p_next = (thread_t *)tqp; - - return tp; -} - -static inline thread_t *queue_dequeue(thread_t *tp) { - - tp->p_prev->p_next = tp->p_next; - tp->p_next->p_prev = tp->p_prev; - - return tp; -} -#endif /* CH_CFG_OPTIMIZE_SPEED == TRUE */ - -/** - * @brief Determines if the current thread must reschedule. - * @details This function returns @p true if there is a ready thread with - * higher priority. - * - * @return The priorities situation. - * @retval false if rescheduling is not necessary. - * @retval true if there is a ready thread at higher priority. - * - * @iclass - */ -static inline bool chSchIsRescRequiredI(void) { - - chDbgCheckClassI(); - - return firstprio(&ch.rlist.r_queue) > currp->p_prio; -} - -/** - * @brief Determines if yielding is possible. - * @details This function returns @p true if there is a ready thread with - * equal or higher priority. - * - * @return The priorities situation. - * @retval false if yielding is not possible. - * @retval true if there is a ready thread at equal or higher priority. - * - * @sclass - */ -static inline bool chSchCanYieldS(void) { - - chDbgCheckClassS(); - - return firstprio(&ch.rlist.r_queue) >= currp->p_prio; -} - -/** - * @brief Yields the time slot. - * @details Yields the CPU control to the next thread in the ready list with - * equal or higher priority, if any. - * - * @sclass - */ -static inline void chSchDoYieldS(void) { - - chDbgCheckClassS(); - - if (chSchCanYieldS()) { - chSchDoRescheduleBehind(); - } -} - -/** - * @brief Inline-able preemption code. - * @details This is the common preemption code, this function must be invoked - * exclusively from the port layer. - * - * @special - */ -static inline void chSchPreemption(void) { - tprio_t p1 = firstprio(&ch.rlist.r_queue); - tprio_t p2 = currp->p_prio; - -#if CH_CFG_TIME_QUANTUM > 0 - if (currp->p_preempt > (tslices_t)0) { - if (p1 > p2) { - chSchDoRescheduleAhead(); - } - } - else { - if (p1 >= p2) { - chSchDoRescheduleBehind(); - } - } -#else /* CH_CFG_TIME_QUANTUM == 0 */ - if (p1 > p2) { - chSchDoRescheduleAhead(); - } -#endif /* CH_CFG_TIME_QUANTUM == 0 */ -} - -#endif /* _CHSCHD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/include/chsem.h b/firmware/ChibiOS_16/os/rt/include/chsem.h deleted file mode 100644 index faf58b0ac6..0000000000 --- a/firmware/ChibiOS_16/os/rt/include/chsem.h +++ /dev/null @@ -1,160 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chsem.h - * @brief Semaphores macros and structures. - * - * @addtogroup semaphores - * @{ - */ - -#ifndef _CHSEM_H_ -#define _CHSEM_H_ - -#if (CH_CFG_USE_SEMAPHORES == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Semaphore structure. - */ -typedef struct ch_semaphore { - threads_queue_t s_queue; /**< @brief Queue of the threads sleeping - on this semaphore. */ - cnt_t s_cnt; /**< @brief The semaphore counter. */ -} semaphore_t; - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @brief Data part of a static semaphore initializer. - * @details This macro should be used when statically initializing a semaphore - * that is part of a bigger structure. - * - * @param[in] name the name of the semaphore variable - * @param[in] n the counter initial value, this value must be - * non-negative - */ -#define _SEMAPHORE_DATA(name, n) {_THREADS_QUEUE_DATA(name.s_queue), n} - -/** - * @brief Static semaphore initializer. - * @details Statically initialized semaphores require no explicit - * initialization using @p chSemInit(). - * - * @param[in] name the name of the semaphore variable - * @param[in] n the counter initial value, this value must be - * non-negative - */ -#define SEMAPHORE_DECL(name, n) semaphore_t name = _SEMAPHORE_DATA(name, n) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void chSemObjectInit(semaphore_t *sp, cnt_t n); - void chSemReset(semaphore_t *sp, cnt_t n); - void chSemResetI(semaphore_t *sp, cnt_t n); - msg_t chSemWait(semaphore_t *sp); - msg_t chSemWaitS(semaphore_t *sp); - msg_t chSemWaitTimeout(semaphore_t *sp, systime_t time); - msg_t chSemWaitTimeoutS(semaphore_t *sp, systime_t time); - void chSemSignal(semaphore_t *sp); - void chSemSignalI(semaphore_t *sp); - void chSemAddCounterI(semaphore_t *sp, cnt_t n); - msg_t chSemSignalWait(semaphore_t *sps, semaphore_t *spw); -#ifdef __cplusplus -} -#endif - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -/** - * @brief Decreases the semaphore counter. - * @details This macro can be used when the counter is known to be positive. - * - * @param[in] sp pointer to a @p semaphore_t structure - * - * @iclass - */ -static inline void chSemFastWaitI(semaphore_t *sp) { - - chDbgCheckClassI(); - - sp->s_cnt--; -} - -/** - * @brief Increases the semaphore counter. - * @details This macro can be used when the counter is known to be not - * negative. - * - * @param[in] sp pointer to a @p semaphore_t structure - * - * @iclass - */ -static inline void chSemFastSignalI(semaphore_t *sp) { - - chDbgCheckClassI(); - - sp->s_cnt++; -} - -/** - * @brief Returns the semaphore counter current value. - * - * @param[in] sp pointer to a @p semaphore_t structure - * @return The semaphore counter value. - * - * @iclass - */ -static inline cnt_t chSemGetCounterI(semaphore_t *sp) { - - chDbgCheckClassI(); - - return sp->s_cnt; -} - -#endif /* CH_CFG_USE_SEMAPHORES == TRUE */ - -#endif /* _CHSEM_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/include/chstats.h b/firmware/ChibiOS_16/os/rt/include/chstats.h deleted file mode 100644 index bdc47529fd..0000000000 --- a/firmware/ChibiOS_16/os/rt/include/chstats.h +++ /dev/null @@ -1,105 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chstats.h - * @brief Statistics module macros and structures. - * - * @addtogroup statistics - * @{ - */ - -#ifndef _CHSTATS_H_ -#define _CHSTATS_H_ - -#if (CH_DBG_STATISTICS == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -#if CH_CFG_USE_TM == FALSE -#error "CH_DBG_STATISTICS requires CH_CFG_USE_TM" -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a kernel statistics structure. - */ -typedef struct { - ucnt_t n_irq; /**< @brief Number of IRQs. */ - ucnt_t n_ctxswc; /**< @brief Number of context switches. */ - time_measurement_t m_crit_thd; /**< @brief Measurement of threads - critical zones duration. */ - time_measurement_t m_crit_isr; /**< @brief Measurement of ISRs critical - zones duration. */ -} kernel_stats_t; - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void _stats_init(void); - void _stats_increase_irq(void); - void _stats_ctxswc(thread_t *ntp, thread_t *otp); - void _stats_start_measure_crit_thd(void); - void _stats_stop_measure_crit_thd(void); - void _stats_start_measure_crit_isr(void); - void _stats_stop_measure_crit_isr(void); -#ifdef __cplusplus -} -#endif - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -#else /* CH_DBG_STATISTICS == FALSE */ - -/* Stub functions for when the statistics module is disabled. */ -#define _stats_increase_irq() -#define _stats_ctxswc(old, new) -#define _stats_start_measure_crit_thd() -#define _stats_stop_measure_crit_thd() -#define _stats_start_measure_crit_isr() -#define _stats_stop_measure_crit_isr() - -#endif /* CH_DBG_STATISTICS == FALSE */ - -#endif /* _CHSTATS_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/include/chstreams.h b/firmware/ChibiOS_16/os/rt/include/chstreams.h deleted file mode 100644 index ec83c5530e..0000000000 --- a/firmware/ChibiOS_16/os/rt/include/chstreams.h +++ /dev/null @@ -1,146 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chstreams.h - * @brief Data streams. - * @details This header defines abstract interfaces useful to access generic - * data streams in a standardized way. - * - * @addtogroup data_streams - * @details This module define an abstract interface for generic data streams. - * Note that no code is present, just abstract interfaces-like - * structures, you should look at the system as to a set of - * abstract C++ classes (even if written in C). This system - * has then advantage to make the access to data streams - * independent from the implementation logic.
- * The stream interface can be used as base class for high level - * object types such as files, sockets, serial ports, pipes etc. - * @{ - */ - -#ifndef _CHSTREAMS_H_ -#define _CHSTREAMS_H_ - -/** - * @brief BaseSequentialStream specific methods. - */ -#define _base_sequential_stream_methods \ - /* Stream write buffer method.*/ \ - size_t (*write)(void *instance, const uint8_t *bp, size_t n); \ - /* Stream read buffer method.*/ \ - size_t (*read)(void *instance, uint8_t *bp, size_t n); \ - /* Channel put method, blocking.*/ \ - msg_t (*put)(void *instance, uint8_t b); \ - /* Channel get method, blocking.*/ \ - msg_t (*get)(void *instance); \ - -/** - * @brief @p BaseSequentialStream specific data. - * @note It is empty because @p BaseSequentialStream is only an interface - * without implementation. - */ -#define _base_sequential_stream_data - -/** - * @brief @p BaseSequentialStream virtual methods table. - */ -struct BaseSequentialStreamVMT { - _base_sequential_stream_methods -}; - -/** - * @brief Base stream class. - * @details This class represents a generic blocking unbuffered sequential - * data stream. - */ -typedef struct { - /** @brief Virtual Methods Table.*/ - const struct BaseSequentialStreamVMT *vmt; - _base_sequential_stream_data -} BaseSequentialStream; - -/** - * @name Macro Functions (BaseSequentialStream) - * @{ - */ -/** - * @brief Sequential Stream write. - * @details The function writes data from a buffer to a stream. - * - * @param[in] ip pointer to a @p BaseSequentialStream or derived class - * @param[in] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred - * @return The number of bytes transferred. The return value can - * be less than the specified number of bytes if an - * end-of-file condition has been met. - * - * @api - */ -#define chSequentialStreamWrite(ip, bp, n) ((ip)->vmt->write(ip, bp, n)) - -/** - * @brief Sequential Stream read. - * @details The function reads data from a stream into a buffer. - * - * @param[in] ip pointer to a @p BaseSequentialStream or derived class - * @param[out] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred - * @return The number of bytes transferred. The return value can - * be less than the specified number of bytes if an - * end-of-file condition has been met. - * - * @api - */ -#define chSequentialStreamRead(ip, bp, n) ((ip)->vmt->read(ip, bp, n)) - -/** - * @brief Sequential Stream blocking byte write. - * @details This function writes a byte value to a channel. If the channel - * is not ready to accept data then the calling thread is suspended. - * - * @param[in] ip pointer to a @p BaseSequentialStream or derived class - * @param[in] b the byte value to be written to the channel - * - * @return The operation status. - * @retval Q_OK if the operation succeeded. - * @retval Q_RESET if an end-of-file condition has been met. - * - * @api - */ -#define chSequentialStreamPut(ip, b) ((ip)->vmt->put(ip, b)) - -/** - * @brief Sequential Stream blocking byte read. - * @details This function reads a byte value from a channel. If the data - * is not available then the calling thread is suspended. - * - * @param[in] ip pointer to a @p BaseSequentialStream or derived class - * - * @return A byte value from the queue. - * @retval Q_RESET if an end-of-file condition has been met. - * - * @api - */ -#define chSequentialStreamGet(ip) ((ip)->vmt->get(ip)) -/** @} */ - -#endif /* _CHSTREAMS_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/include/chsys.h b/firmware/ChibiOS_16/os/rt/include/chsys.h deleted file mode 100644 index 46b52ed493..0000000000 --- a/firmware/ChibiOS_16/os/rt/include/chsys.h +++ /dev/null @@ -1,462 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chsys.h - * @brief System related macros and structures. - * - * @addtogroup system - * @{ - */ - -#ifndef _CHSYS_H_ -#define _CHSYS_H_ - -/*lint -sem(chSysHalt, r_no)*/ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @name Masks of executable integrity checks. - * @{ - */ -#define CH_INTEGRITY_RLIST 1U -#define CH_INTEGRITY_VTLIST 2U -#define CH_INTEGRITY_REGISTRY 4U -#define CH_INTEGRITY_PORT 8U -/** @} */ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @name ISRs abstraction macros - */ -/** - * @brief Priority level validation macro. - * @details This macro determines if the passed value is a valid priority - * level for the underlying architecture. - * - * @param[in] prio the priority level - * @return Priority range result. - * @retval false if the priority is invalid or if the architecture - * does not support priorities. - * @retval true if the priority is valid. - */ -#if defined(PORT_IRQ_IS_VALID_PRIORITY) || defined(__DOXYGEN__) -#define CH_IRQ_IS_VALID_PRIORITY(prio) \ - PORT_IRQ_IS_VALID_PRIORITY(prio) -#else -#define CH_IRQ_IS_VALID_PRIORITY(prio) false -#endif - -/** - * @brief Priority level validation macro. - * @details This macro determines if the passed value is a valid priority - * level that cannot preempt the kernel critical zone. - * - * @param[in] prio the priority level - * @return Priority range result. - * @retval false if the priority is invalid or if the architecture - * does not support priorities. - * @retval true if the priority is valid. - */ -#if defined(PORT_IRQ_IS_VALID_KERNEL_PRIORITY) || defined(__DOXYGEN__) -#define CH_IRQ_IS_VALID_KERNEL_PRIORITY(prio) \ - PORT_IRQ_IS_VALID_KERNEL_PRIORITY(prio) -#else -#define CH_IRQ_IS_VALID_KERNEL_PRIORITY(prio) false -#endif - -/** - * @brief IRQ handler enter code. - * @note Usually IRQ handlers functions are also declared naked. - * @note On some architectures this macro can be empty. - * - * @special - */ -#define CH_IRQ_PROLOGUE() \ - PORT_IRQ_PROLOGUE(); \ - _stats_increase_irq(); \ - _dbg_check_enter_isr() - -/** - * @brief IRQ handler exit code. - * @note Usually IRQ handlers function are also declared naked. - * @note This macro usually performs the final reschedule by using - * @p chSchIsPreemptionRequired() and @p chSchDoReschedule(). - * - * @special - */ -#define CH_IRQ_EPILOGUE() \ - _dbg_check_leave_isr(); \ - PORT_IRQ_EPILOGUE() - -/** - * @brief Standard normal IRQ handler declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - * - * @special - */ -#define CH_IRQ_HANDLER(id) PORT_IRQ_HANDLER(id) -/** @} */ - -/** - * @name Fast ISRs abstraction macros - */ -/** - * @brief Standard fast IRQ handler declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - * @note Not all architectures support fast interrupts. - * - * @special - */ -#define CH_FAST_IRQ_HANDLER(id) PORT_FAST_IRQ_HANDLER(id) -/** @} */ - -/** - * @name Time conversion utilities for the realtime counter - * @{ - */ -/** - * @brief Seconds to realtime counter. - * @details Converts from seconds to realtime counter cycles. - * @note The macro assumes that @p freq >= @p 1. - * - * @param[in] freq clock frequency, in Hz, of the realtime counter - * @param[in] sec number of seconds - * @return The number of cycles. - * - * @api - */ -#define S2RTC(freq, sec) ((freq) * (sec)) - -/** - * @brief Milliseconds to realtime counter. - * @details Converts from milliseconds to realtime counter cycles. - * @note The result is rounded upward to the next millisecond boundary. - * @note The macro assumes that @p freq >= @p 1000. - * - * @param[in] freq clock frequency, in Hz, of the realtime counter - * @param[in] msec number of milliseconds - * @return The number of cycles. - * - * @api - */ -#define MS2RTC(freq, msec) (rtcnt_t)((((freq) + 999UL) / 1000UL) * (msec)) - -/** - * @brief Microseconds to realtime counter. - * @details Converts from microseconds to realtime counter cycles. - * @note The result is rounded upward to the next microsecond boundary. - * @note The macro assumes that @p freq >= @p 1000000. - * - * @param[in] freq clock frequency, in Hz, of the realtime counter - * @param[in] usec number of microseconds - * @return The number of cycles. - * - * @api - */ -#define US2RTC(freq, usec) (rtcnt_t)((((freq) + 999999UL) / 1000000UL) * (usec)) - -/** - * @brief Realtime counter cycles to seconds. - * @details Converts from realtime counter cycles number to seconds. - * @note The result is rounded up to the next second boundary. - * @note The macro assumes that @p freq >= @p 1. - * - * @param[in] freq clock frequency, in Hz, of the realtime counter - * @param[in] n number of cycles - * @return The number of seconds. - * - * @api - */ -#define RTC2S(freq, n) ((((n) - 1UL) / (freq)) + 1UL) - -/** - * @brief Realtime counter cycles to milliseconds. - * @details Converts from realtime counter cycles number to milliseconds. - * @note The result is rounded up to the next millisecond boundary. - * @note The macro assumes that @p freq >= @p 1000. - * - * @param[in] freq clock frequency, in Hz, of the realtime counter - * @param[in] n number of cycles - * @return The number of milliseconds. - * - * @api - */ -#define RTC2MS(freq, n) ((((n) - 1UL) / ((freq) / 1000UL)) + 1UL) - -/** - * @brief Realtime counter cycles to microseconds. - * @details Converts from realtime counter cycles number to microseconds. - * @note The result is rounded up to the next microsecond boundary. - * @note The macro assumes that @p freq >= @p 1000000. - * - * @param[in] freq clock frequency, in Hz, of the realtime counter - * @param[in] n number of cycles - * @return The number of microseconds. - * - * @api - */ -#define RTC2US(freq, n) ((((n) - 1UL) / ((freq) / 1000000UL)) + 1UL) -/** @} */ - -/** - * @brief Returns the current value of the system real time counter. - * @note This function is only available if the port layer supports the - * option @p PORT_SUPPORTS_RT. - * - * @return The value of the system realtime counter of - * type rtcnt_t. - * - * @xclass - */ -#if (PORT_SUPPORTS_RT == TRUE) || defined(__DOXYGEN__) -#define chSysGetRealtimeCounterX() (rtcnt_t)port_rt_get_counter_value() -#endif - -/** - * @brief Performs a context switch. - * @note Not a user function, it is meant to be invoked by the scheduler - * itself or from within the port layer. - * - * @param[in] ntp the thread to be switched in - * @param[in] otp the thread to be switched out - * - * @special - */ -#define chSysSwitch(ntp, otp) { \ - \ - _dbg_trace(otp); \ - _stats_ctxswc(ntp, otp); \ - CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp); \ - port_switch(ntp, otp); \ -} - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void chSysInit(void); - void chSysHalt(const char *reason); - bool chSysIntegrityCheckI(unsigned testmask); - void chSysTimerHandlerI(void); - syssts_t chSysGetStatusAndLockX(void); - void chSysRestoreStatusX(syssts_t sts); -#if PORT_SUPPORTS_RT - bool chSysIsCounterWithinX(rtcnt_t cnt, rtcnt_t start, rtcnt_t end); - void chSysPolledDelayX(rtcnt_t cycles); -#endif -#ifdef __cplusplus -} -#endif - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -/** - * @brief Raises the system interrupt priority mask to the maximum level. - * @details All the maskable interrupt sources are disabled regardless their - * hardware priority. - * @note Do not invoke this API from within a kernel lock. - * - * @special - */ -static inline void chSysDisable(void) { - - port_disable(); - _dbg_check_disable(); -} - -/** - * @brief Raises the system interrupt priority mask to system level. - * @details The interrupt sources that should not be able to preempt the kernel - * are disabled, interrupt sources with higher priority are still - * enabled. - * @note Do not invoke this API from within a kernel lock. - * @note This API is no replacement for @p chSysLock(), the @p chSysLock() - * could do more than just disable the interrupts. - * - * @special - */ -static inline void chSysSuspend(void) { - - port_suspend(); - _dbg_check_suspend(); -} - -/** - * @brief Lowers the system interrupt priority mask to user level. - * @details All the interrupt sources are enabled. - * @note Do not invoke this API from within a kernel lock. - * @note This API is no replacement for @p chSysUnlock(), the - * @p chSysUnlock() could do more than just enable the interrupts. - * - * @special - */ -static inline void chSysEnable(void) { - - _dbg_check_enable(); - port_enable(); -} - -/** - * @brief Enters the kernel lock state. - * - * @special - */ -static inline void chSysLock(void) { - - port_lock(); - _stats_start_measure_crit_thd(); - _dbg_check_lock(); -} - -/** - * @brief Leaves the kernel lock state. - * - * @special - */ -static inline void chSysUnlock(void) { - - _dbg_check_unlock(); - _stats_stop_measure_crit_thd(); - - /* The following condition can be triggered by the use of i-class functions - in a critical section not followed by a chSchResceduleS(), this means - that the current thread has a lower priority than the next thread in - the ready list.*/ - chDbgAssert((ch.rlist.r_queue.p_next == (thread_t *)&ch.rlist.r_queue) || - (ch.rlist.r_current->p_prio >= ch.rlist.r_queue.p_next->p_prio), - "priority order violation"); - - port_unlock(); -} - -/** - * @brief Enters the kernel lock state from within an interrupt handler. - * @note This API may do nothing on some architectures, it is required - * because on ports that support preemptable interrupt handlers - * it is required to raise the interrupt mask to the same level of - * the system mutual exclusion zone.
- * It is good practice to invoke this API before invoking any I-class - * syscall from an interrupt handler. - * @note This API must be invoked exclusively from interrupt handlers. - * - * @special - */ -static inline void chSysLockFromISR(void) { - - port_lock_from_isr(); - _stats_start_measure_crit_isr(); - _dbg_check_lock_from_isr(); -} - -/** - * @brief Leaves the kernel lock state from within an interrupt handler. - * - * @note This API may do nothing on some architectures, it is required - * because on ports that support preemptable interrupt handlers - * it is required to raise the interrupt mask to the same level of - * the system mutual exclusion zone.
- * It is good practice to invoke this API after invoking any I-class - * syscall from an interrupt handler. - * @note This API must be invoked exclusively from interrupt handlers. - * - * @special - */ -static inline void chSysUnlockFromISR(void) { - - _dbg_check_unlock_from_isr(); - _stats_stop_measure_crit_isr(); - port_unlock_from_isr(); -} - -/** - * @brief Unconditionally enters the kernel lock state. - * @note Can be called without previous knowledge of the current lock state. - * The final state is "s-locked". - * - * @special - */ -static inline void chSysUnconditionalLock(void) { - - if (port_irq_enabled(port_get_irq_status())) { - chSysLock(); - } -} - -/** - * @brief Unconditionally leaves the kernel lock state. - * @note Can be called without previous knowledge of the current lock state. - * The final state is "normal". - * - * @special - */ -static inline void chSysUnconditionalUnlock(void) { - - if (!port_irq_enabled(port_get_irq_status())) { - chSysUnlock(); - } -} - -#if (CH_CFG_NO_IDLE_THREAD == FALSE) || defined(__DOXYGEN__) -/** - * @brief Returns a pointer to the idle thread. - * @pre In order to use this function the option @p CH_CFG_NO_IDLE_THREAD - * must be disabled. - * @note The reference counter of the idle thread is not incremented but - * it is not strictly required being the idle thread a static - * object. - * - * @return Pointer to the idle thread. - * - * @xclass - */ -static inline thread_t *chSysGetIdleThreadX(void) { - - return ch.rlist.r_queue.p_prev; -} -#endif /* CH_CFG_NO_IDLE_THREAD == FALSE */ - -#endif /* _CHSYS_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/include/chsystypes.h b/firmware/ChibiOS_16/os/rt/include/chsystypes.h deleted file mode 100644 index d06367d1cc..0000000000 --- a/firmware/ChibiOS_16/os/rt/include/chsystypes.h +++ /dev/null @@ -1,136 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chsystypes.h - * @brief System types header. - * - * @addtogroup scheduler - * @{ - */ - -#ifndef _CHSYSTYPES_H_ -#define _CHSYSTYPES_H_ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of system time. - */ -#if (CH_CFG_ST_RESOLUTION == 32) || defined(__DOXYGEN__) -typedef uint32_t systime_t; -#elif CH_CFG_ST_RESOLUTION == 16 -typedef uint16_t systime_t; -#else -#error "invalid CH_CFG_ST_RESOLUTION setting" -#endif - -/** - * @extends threads_queue_t - * - * @brief Type of a thread structure. - */ -typedef struct ch_thread thread_t; - -/** - * @brief Type of a thread reference. - */ -typedef thread_t * thread_reference_t; - -/** - * @brief Type of a generic threads single link list, it works like a stack. - */ -typedef struct ch_threads_list threads_list_t; - -/** - * @extends threads_list_t - * - * @brief Type of a generic threads bidirectional linked list header and element. - */ -typedef struct ch_threads_queue threads_queue_t; - -/** - * @extends threads_queue_t - * - * @brief Type of a ready list header. - */ -typedef struct ch_ready_list ready_list_t; - -/** - * @brief Type of a Virtual Timer callback function. - */ -typedef void (*vtfunc_t)(void *p); - -/** - * @brief Type of a Virtual Timer structure. - */ -typedef struct ch_virtual_timer virtual_timer_t; - -/** - * @brief Type of virtual timers list header. - */ -typedef struct ch_virtual_timers_list virtual_timers_list_t; - -/** - * @brief Type of a system debug structure. - */ -typedef struct ch_system_debug system_debug_t; - -/** - * @brief Type of system data structure. - */ -typedef struct ch_system ch_system_t; - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -#endif /* _CHSYSTYPES_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/include/chthreads.h b/firmware/ChibiOS_16/os/rt/include/chthreads.h deleted file mode 100644 index 8be08b4be9..0000000000 --- a/firmware/ChibiOS_16/os/rt/include/chthreads.h +++ /dev/null @@ -1,326 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chthreads.h - * @brief Threads module macros and structures. - * - * @addtogroup threads - * @{ - */ - -#ifndef _CHTHREADS_H_ -#define _CHTHREADS_H_ - -/*lint -sem(chThdExit, r_no) -sem(chThdExitS, r_no)*/ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Thread function. - */ -typedef void (*tfunc_t)(void *p); - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @name Threads queues - */ -/** - * @brief Data part of a static threads queue object initializer. - * @details This macro should be used when statically initializing a threads - * queue that is part of a bigger structure. - * - * @param[in] name the name of the threads queue variable - */ -#define _THREADS_QUEUE_DATA(name) {(thread_t *)&name, (thread_t *)&name} - -/** - * @brief Static threads queue object initializer. - * @details Statically initialized threads queues require no explicit - * initialization using @p queue_init(). - * - * @param[in] name the name of the threads queue variable - */ -#define _THREADS_QUEUE_DECL(name) \ - threads_queue_t name = _THREADS_QUEUE_DATA(name) -/** @} */ - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Delays the invoking thread for the specified number of seconds. - * @note The specified time is rounded up to a value allowed by the real - * system tick clock. - * @note The maximum specifiable value is implementation dependent. - * - * @param[in] sec time in seconds, must be different from zero - * - * @api - */ -#define chThdSleepSeconds(sec) chThdSleep(S2ST(sec)) - -/** - * @brief Delays the invoking thread for the specified number of - * milliseconds. - * @note The specified time is rounded up to a value allowed by the real - * system tick clock. - * @note The maximum specifiable value is implementation dependent. - * - * @param[in] msec time in milliseconds, must be different from zero - * - * @api - */ -#define chThdSleepMilliseconds(msec) chThdSleep(MS2ST(msec)) - -/** - * @brief Delays the invoking thread for the specified number of - * microseconds. - * @note The specified time is rounded up to a value allowed by the real - * system tick clock. - * @note The maximum specifiable value is implementation dependent. - * - * @param[in] usec time in microseconds, must be different from zero - * - * @api - */ -#define chThdSleepMicroseconds(usec) chThdSleep(US2ST(usec)) -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - thread_t *_thread_init(thread_t *tp, tprio_t prio); -#if CH_DBG_FILL_THREADS == TRUE - void _thread_memfill(uint8_t *startp, uint8_t *endp, uint8_t v); -#endif - thread_t *chThdCreateI(void *wsp, size_t size, - tprio_t prio, tfunc_t pf, void *arg); - thread_t *chThdCreateStatic(void *wsp, size_t size, - tprio_t prio, tfunc_t pf, void *arg); - thread_t *chThdStart(thread_t *tp); - tprio_t chThdSetPriority(tprio_t newprio); - msg_t chThdSuspendS(thread_reference_t *trp); - msg_t chThdSuspendTimeoutS(thread_reference_t *trp, systime_t timeout); - void chThdResumeI(thread_reference_t *trp, msg_t msg); - void chThdResumeS(thread_reference_t *trp, msg_t msg); - void chThdResume(thread_reference_t *trp, msg_t msg); - msg_t chThdEnqueueTimeoutS(threads_queue_t *tqp, systime_t timeout); - void chThdDequeueNextI(threads_queue_t *tqp, msg_t msg); - void chThdDequeueAllI(threads_queue_t *tqp, msg_t msg); - void chThdTerminate(thread_t *tp); - void chThdSleep(systime_t time); - void chThdSleepUntil(systime_t time); - systime_t chThdSleepUntilWindowed(systime_t prev, systime_t next); - void chThdYield(void); - void chThdExit(msg_t msg); - void chThdExitS(msg_t msg); -#if CH_CFG_USE_WAITEXIT == TRUE - msg_t chThdWait(thread_t *tp); -#endif -#ifdef __cplusplus -} -#endif - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - - /** - * @brief Returns a pointer to the current @p thread_t. - * - * @return A pointer to the current thread. - * - * @xclass - */ -static inline thread_t *chThdGetSelfX(void) { - - return ch.rlist.r_current; -} - -/** - * @brief Returns the current thread priority. - * @note Can be invoked in any context. - * - * @return The current thread priority. - * - * @xclass - */ -static inline tprio_t chThdGetPriorityX(void) { - - return chThdGetSelfX()->p_prio; -} - -/** - * @brief Returns the number of ticks consumed by the specified thread. - * @note This function is only available when the - * @p CH_DBG_THREADS_PROFILING configuration option is enabled. - * - * @param[in] tp pointer to the thread - * @return The number of consumed system ticks. - * - * @xclass - */ -#if (CH_DBG_THREADS_PROFILING == TRUE) || defined(__DOXYGEN__) -static inline systime_t chThdGetTicksX(thread_t *tp) { - - return tp->p_time; -} -#endif - -/** - * @brief Verifies if the specified thread is in the @p CH_STATE_FINAL state. - * - * @param[in] tp pointer to the thread - * @retval true thread terminated. - * @retval false thread not terminated. - * - * @xclass - */ -static inline bool chThdTerminatedX(thread_t *tp) { - - return (bool)(tp->p_state == CH_STATE_FINAL); -} - -/** - * @brief Verifies if the current thread has a termination request pending. - * - * @retval true termination request pending. - * @retval false termination request not pending. - * - * @xclass - */ -static inline bool chThdShouldTerminateX(void) { - - return (bool)((chThdGetSelfX()->p_flags & CH_FLAG_TERMINATE) != (tmode_t)0); -} - -/** - * @brief Resumes a thread created with @p chThdCreateI(). - * - * @param[in] tp pointer to the thread - * @return The pointer to the @p thread_t structure allocated for - * the thread into the working space area. - * - * @iclass - */ -static inline thread_t *chThdStartI(thread_t *tp) { - - chDbgAssert(tp->p_state == CH_STATE_WTSTART, "wrong state"); - - return chSchReadyI(tp); -} - -/** - * @brief Suspends the invoking thread for the specified time. - * - * @param[in] time the delay in system ticks, the special values are - * handled as follow: - * - @a TIME_INFINITE the thread enters an infinite sleep - * state. - * - @a TIME_IMMEDIATE this value is not allowed. - * . - * - * @sclass - */ -static inline void chThdSleepS(systime_t time) { - - chDbgCheck(time != TIME_IMMEDIATE); - - (void) chSchGoSleepTimeoutS(CH_STATE_SLEEPING, time); -} - -/** - * @brief Initializes a threads queue object. - * - * @param[out] tqp pointer to the threads queue object - * - * @init - */ -static inline void chThdQueueObjectInit(threads_queue_t *tqp) { - - queue_init(tqp); -} - -/** - * @brief Evaluates to @p true if the specified queue is empty. - * - * @param[out] tqp pointer to the threads queue object - * @return The queue status. - * @retval false if the queue is not empty. - * @retval true if the queue is empty. - * - * @iclass - */ -static inline bool chThdQueueIsEmptyI(threads_queue_t *tqp) { - - chDbgCheckClassI(); - - return queue_isempty(tqp); -} - -/** - * @brief Dequeues and wakes up one thread from the threads queue object. - * @details Dequeues one thread from the queue without checking if the queue - * is empty. - * @pre The queue must contain at least an object. - * - * @param[in] tqp pointer to the threads queue object - * @param[in] msg the message code - * - * @iclass - */ -static inline void chThdDoDequeueNextI(threads_queue_t *tqp, msg_t msg) { - thread_t *tp; - - chDbgAssert(queue_notempty(tqp), "empty queue"); - - tp = queue_fifo_remove(tqp); - - chDbgAssert(tp->p_state == CH_STATE_QUEUED, "invalid state"); - - tp->p_u.rdymsg = msg; - (void) chSchReadyI(tp); -} - -#endif /* _CHTHREADS_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/include/chtm.h b/firmware/ChibiOS_16/os/rt/include/chtm.h deleted file mode 100644 index 6c5409a4b4..0000000000 --- a/firmware/ChibiOS_16/os/rt/include/chtm.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chtm.h - * @brief Time Measurement module macros and structures. - * - * @addtogroup time_measurement - * @{ - */ - -#ifndef _CHTM_H_ -#define _CHTM_H_ - -#if (CH_CFG_USE_TM == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if PORT_SUPPORTS_RT == FALSE -#error "CH_CFG_USE_TM requires PORT_SUPPORTS_RT" -#endif - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a time measurement calibration data. - */ -typedef struct { - /** - * @brief Measurement calibration value. - */ - rtcnt_t offset; -} tm_calibration_t; - -/** - * @brief Type of a Time Measurement object. - * @note The maximum measurable time period depends on the implementation - * of the realtime counter and its clock frequency. - * @note The measurement is not 100% cycle-accurate, it can be in excess - * of few cycles depending on the compiler and target architecture. - * @note Interrupts can affect measurement if the measurement is performed - * with interrupts enabled. - */ -typedef struct { - rtcnt_t best; /**< @brief Best measurement. */ - rtcnt_t worst; /**< @brief Worst measurement. */ - rtcnt_t last; /**< @brief Last measurement. */ - ucnt_t n; /**< @brief Number of measurements. */ - rttime_t cumulative; /**< @brief Cumulative measurement. */ -} time_measurement_t; - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void _tm_init(void); - void chTMObjectInit(time_measurement_t *tmp); - NOINLINE void chTMStartMeasurementX(time_measurement_t *tmp); - NOINLINE void chTMStopMeasurementX(time_measurement_t *tmp); - NOINLINE void chTMChainMeasurementToX(time_measurement_t *tmp1, - time_measurement_t *tmp2); -#ifdef __cplusplus -} -#endif - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -#endif /* CH_CFG_USE_TM == TRUE */ - -#endif /* _CHTM_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/include/chvt.h b/firmware/ChibiOS_16/os/rt/include/chvt.h deleted file mode 100644 index 535e8420df..0000000000 --- a/firmware/ChibiOS_16/os/rt/include/chvt.h +++ /dev/null @@ -1,591 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chvt.h - * @brief Time and Virtual Timers module macros and structures. - * - * @addtogroup time - * @{ - */ - -#ifndef _CHVT_H_ -#define _CHVT_H_ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @name Special time constants - * @{ - */ -/** - * @brief Zero time specification for some functions with a timeout - * specification. - * @note Not all functions accept @p TIME_IMMEDIATE as timeout parameter, - * see the specific function documentation. - */ -#define TIME_IMMEDIATE ((systime_t)0) - -/** - * @brief Infinite time specification for all functions with a timeout - * specification. - * @note Not all functions accept @p TIME_INFINITE as timeout parameter, - * see the specific function documentation. - */ -#define TIME_INFINITE ((systime_t)-1) -/** @} */ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if (CH_CFG_ST_RESOLUTION != 16) && (CH_CFG_ST_RESOLUTION != 32) -#error "invalid CH_CFG_ST_RESOLUTION specified, must be 16 or 32" -#endif - -#if CH_CFG_ST_FREQUENCY <= 0 -#error "invalid CH_CFG_ST_FREQUENCY specified, must be greater than zero" -#endif - -#if (CH_CFG_ST_TIMEDELTA < 0) || (CH_CFG_ST_TIMEDELTA == 1) -#error "invalid CH_CFG_ST_TIMEDELTA specified, must " \ - "be zero or greater than one" -#endif - -#if (CH_CFG_ST_TIMEDELTA > 0) && (CH_CFG_TIME_QUANTUM > 0) -#error "CH_CFG_TIME_QUANTUM not supported in tickless mode" -#endif - -#if (CH_CFG_ST_TIMEDELTA > 0) && (CH_DBG_THREADS_PROFILING == TRUE) -#error "CH_DBG_THREADS_PROFILING not supported in tickless mode" -#endif - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @name Time conversion utilities - * @{ - */ -/** - * @brief Seconds to system ticks. - * @details Converts from seconds to system ticks number. - * @note The result is rounded upward to the next tick boundary. - * - * @param[in] sec number of seconds - * @return The number of ticks. - * - * @api - */ -#define S2ST(sec) \ - ((systime_t)((uint32_t)(sec) * (uint32_t)CH_CFG_ST_FREQUENCY)) - -/** - * @brief Milliseconds to system ticks. - * @details Converts from milliseconds to system ticks number. - * @note The result is rounded upward to the next tick boundary. - * - * @param[in] msec number of milliseconds - * @return The number of ticks. - * - * @api - */ -#define MS2ST(msec) \ - ((systime_t)(((((uint32_t)(msec)) * \ - ((uint32_t)CH_CFG_ST_FREQUENCY)) + 999UL) / 1000UL)) - -/** - * @brief Microseconds to system ticks. - * @details Converts from microseconds to system ticks number. - * @note The result is rounded upward to the next tick boundary. - * - * @param[in] usec number of microseconds - * @return The number of ticks. - * - * @api - */ -#define US2ST(usec) \ - ((systime_t)(((((uint32_t)(usec)) * \ - ((uint32_t)CH_CFG_ST_FREQUENCY)) + 999999UL) / 1000000UL)) - -/** - * @brief System ticks to seconds. - * @details Converts from system ticks number to seconds. - * @note The result is rounded up to the next second boundary. - * - * @param[in] n number of system ticks - * @return The number of seconds. - * - * @api - */ -#define ST2S(n) (((n) + CH_CFG_ST_FREQUENCY - 1UL) / CH_CFG_ST_FREQUENCY) - -/** - * @brief System ticks to milliseconds. - * @details Converts from system ticks number to milliseconds. - * @note The result is rounded up to the next millisecond boundary. - * - * @param[in] n number of system ticks - * @return The number of milliseconds. - * - * @api - */ -#define ST2MS(n) (((n) * 1000UL + CH_CFG_ST_FREQUENCY - 1UL) / \ - CH_CFG_ST_FREQUENCY) - -/** - * @brief System ticks to microseconds. - * @details Converts from system ticks number to microseconds. - * @note The result is rounded up to the next microsecond boundary. - * - * @param[in] n number of system ticks - * @return The number of microseconds. - * - * @api - */ -#define ST2US(n) (((n) * 1000000UL + CH_CFG_ST_FREQUENCY - 1UL) / \ - CH_CFG_ST_FREQUENCY) -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/* - * Virtual Timers APIs. - */ -#ifdef __cplusplus -extern "C" { -#endif - void _vt_init(void); - void chVTDoSetI(virtual_timer_t *vtp, systime_t delay, - vtfunc_t vtfunc, void *par); - void chVTDoResetI(virtual_timer_t *vtp); -#ifdef __cplusplus -} -#endif - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -/** - * @brief Initializes a @p virtual_timer_t object. - * @note Initializing a timer object is not strictly required because - * the function @p chVTSetI() initializes the object too. This - * function is only useful if you need to perform a @p chVTIsArmed() - * check before calling @p chVTSetI(). - * - * @param[out] vtp the @p virtual_timer_t structure pointer - * - * @init - */ -static inline void chVTObjectInit(virtual_timer_t *vtp) { - - vtp->vt_func = NULL; -} - -/** - * @brief Current system time. - * @details Returns the number of system ticks since the @p chSysInit() - * invocation. - * @note The counter can reach its maximum and then restart from zero. - * @note This function can be called from any context but its atomicity - * is not guaranteed on architectures whose word size is less than - * @p systime_t size. - * - * @return The system time in ticks. - * - * @xclass - */ -static inline systime_t chVTGetSystemTimeX(void) { - -#if CH_CFG_ST_TIMEDELTA == 0 - return ch.vtlist.vt_systime; -#else /* CH_CFG_ST_TIMEDELTA > 0 */ - return port_timer_get_time(); -#endif /* CH_CFG_ST_TIMEDELTA > 0 */ -} - -/** - * @brief Current system time. - * @details Returns the number of system ticks since the @p chSysInit() - * invocation. - * @note The counter can reach its maximum and then restart from zero. - * - * @return The system time in ticks. - * - * @api - */ -static inline systime_t chVTGetSystemTime(void) { - systime_t systime; - - chSysLock(); - systime = chVTGetSystemTimeX(); - chSysUnlock(); - - return systime; -} - -/** - * @brief Returns the elapsed time since the specified start time. - * - * @param[in] start start time - * @return The elapsed time. - * - * @xclass - */ -static inline systime_t chVTTimeElapsedSinceX(systime_t start) { - - return chVTGetSystemTimeX() - start; -} - -/** - * @brief Checks if the specified time is within the specified time window. - * @note When start==end then the function returns always true because the - * whole time range is specified. - * @note This function can be called from any context. - * - * @param[in] time the time to be verified - * @param[in] start the start of the time window (inclusive) - * @param[in] end the end of the time window (non inclusive) - * @retval true current time within the specified time window. - * @retval false current time not within the specified time window. - * - * @xclass - */ -static inline bool chVTIsTimeWithinX(systime_t time, - systime_t start, - systime_t end) { - - return (bool)((systime_t)(time - start) < (systime_t)(end - start)); -} - -/** - * @brief Checks if the current system time is within the specified time - * window. - * @note When start==end then the function returns always true because the - * whole time range is specified. - * - * @param[in] start the start of the time window (inclusive) - * @param[in] end the end of the time window (non inclusive) - * @retval true current time within the specified time window. - * @retval false current time not within the specified time window. - * - * @xclass - */ -static inline bool chVTIsSystemTimeWithinX(systime_t start, systime_t end) { - - return chVTIsTimeWithinX(chVTGetSystemTimeX(), start, end); -} - -/** - * @brief Checks if the current system time is within the specified time - * window. - * @note When start==end then the function returns always true because the - * whole time range is specified. - * - * @param[in] start the start of the time window (inclusive) - * @param[in] end the end of the time window (non inclusive) - * @retval true current time within the specified time window. - * @retval false current time not within the specified time window. - * - * @api - */ -static inline bool chVTIsSystemTimeWithin(systime_t start, systime_t end) { - - return chVTIsTimeWithinX(chVTGetSystemTime(), start, end); -} - -/** - * @brief Returns the time interval until the next timer event. - * @note The return value is not perfectly accurate and can report values - * in excess of @p CH_CFG_ST_TIMEDELTA ticks. - * @note The interval returned by this function is only meaningful if - * more timers are not added to the list until the returned time. - * - * @param[out] timep pointer to a variable that will contain the time - * interval until the next timer elapses. This pointer - * can be @p NULL if the information is not required. - * @return The time, in ticks, until next time event. - * @retval false if the timers list is empty. - * @retval true if the timers list contains at least one timer. - * - * @iclass - */ -static inline bool chVTGetTimersStateI(systime_t *timep) { - - chDbgCheckClassI(); - - if (&ch.vtlist == (virtual_timers_list_t *)ch.vtlist.vt_next) { - return false; - } - - if (timep != NULL) { -#if CH_CFG_ST_TIMEDELTA == 0 - *timep = ch.vtlist.vt_next->vt_delta; -#else - *timep = ch.vtlist.vt_lasttime + ch.vtlist.vt_next->vt_delta + - CH_CFG_ST_TIMEDELTA - chVTGetSystemTimeX(); -#endif - } - - return true; -} - -/** - * @brief Returns @p true if the specified timer is armed. - * @pre The timer must have been initialized using @p chVTObjectInit() - * or @p chVTDoSetI(). - * - * @param[in] vtp the @p virtual_timer_t structure pointer - * @return true if the timer is armed. - * - * @iclass - */ -static inline bool chVTIsArmedI(virtual_timer_t *vtp) { - - chDbgCheckClassI(); - - return (bool)(vtp->vt_func != NULL); -} - -/** - * @brief Returns @p true if the specified timer is armed. - * @pre The timer must have been initialized using @p chVTObjectInit() - * or @p chVTDoSetI(). - * - * @param[in] vtp the @p virtual_timer_t structure pointer - * @return true if the timer is armed. - * - * @api - */ -static inline bool chVTIsArmed(virtual_timer_t *vtp) { - bool b; - - chSysLock(); - b = chVTIsArmedI(vtp); - chSysUnlock(); - - return b; -} - -/** - * @brief Disables a Virtual Timer. - * @note The timer is first checked and disabled only if armed. - * @pre The timer must have been initialized using @p chVTObjectInit() - * or @p chVTDoSetI(). - * - * @param[in] vtp the @p virtual_timer_t structure pointer - * - * @iclass - */ -static inline void chVTResetI(virtual_timer_t *vtp) { - - if (chVTIsArmedI(vtp)) { - chVTDoResetI(vtp); - } -} - -/** - * @brief Disables a Virtual Timer. - * @note The timer is first checked and disabled only if armed. - * @pre The timer must have been initialized using @p chVTObjectInit() - * or @p chVTDoSetI(). - * - * @param[in] vtp the @p virtual_timer_t structure pointer - * - * @api - */ -static inline void chVTReset(virtual_timer_t *vtp) { - - chSysLock(); - chVTResetI(vtp); - chSysUnlock(); -} - -/** - * @brief Enables a virtual timer. - * @details If the virtual timer was already enabled then it is re-enabled - * using the new parameters. - * @pre The timer must have been initialized using @p chVTObjectInit() - * or @p chVTDoSetI(). - * - * @param[in] vtp the @p virtual_timer_t structure pointer - * @param[in] delay the number of ticks before the operation timeouts, the - * special values are handled as follow: - * - @a TIME_INFINITE is allowed but interpreted as a - * normal time specification. - * - @a TIME_IMMEDIATE this value is not allowed. - * . - * @param[in] vtfunc the timer callback function. After invoking the - * callback the timer is disabled and the structure can - * be disposed or reused. - * @param[in] par a parameter that will be passed to the callback - * function - * - * @iclass - */ -static inline void chVTSetI(virtual_timer_t *vtp, systime_t delay, - vtfunc_t vtfunc, void *par) { - - chVTResetI(vtp); - chVTDoSetI(vtp, delay, vtfunc, par); -} - -/** - * @brief Enables a virtual timer. - * @details If the virtual timer was already enabled then it is re-enabled - * using the new parameters. - * @pre The timer must have been initialized using @p chVTObjectInit() - * or @p chVTDoSetI(). - * - * @param[in] vtp the @p virtual_timer_t structure pointer - * @param[in] delay the number of ticks before the operation timeouts, the - * special values are handled as follow: - * - @a TIME_INFINITE is allowed but interpreted as a - * normal time specification. - * - @a TIME_IMMEDIATE this value is not allowed. - * . - * @param[in] vtfunc the timer callback function. After invoking the - * callback the timer is disabled and the structure can - * be disposed or reused. - * @param[in] par a parameter that will be passed to the callback - * function - * - * @api - */ -static inline void chVTSet(virtual_timer_t *vtp, systime_t delay, - vtfunc_t vtfunc, void *par) { - - chSysLock(); - chVTSetI(vtp, delay, vtfunc, par); - chSysUnlock(); -} - -/** - * @brief Virtual timers ticker. - * @note The system lock is released before entering the callback and - * re-acquired immediately after. It is callback's responsibility - * to acquire the lock if needed. This is done in order to reduce - * interrupts jitter when many timers are in use. - * - * @iclass - */ -static inline void chVTDoTickI(void) { - - chDbgCheckClassI(); - -#if CH_CFG_ST_TIMEDELTA == 0 - ch.vtlist.vt_systime++; - if (&ch.vtlist != (virtual_timers_list_t *)ch.vtlist.vt_next) { - /* The list is not empty, processing elements on top.*/ - --ch.vtlist.vt_next->vt_delta; - while (ch.vtlist.vt_next->vt_delta == (systime_t)0) { - virtual_timer_t *vtp; - vtfunc_t fn; - - vtp = ch.vtlist.vt_next; - fn = vtp->vt_func; - vtp->vt_func = NULL; - vtp->vt_next->vt_prev = (virtual_timer_t *)&ch.vtlist; - ch.vtlist.vt_next = vtp->vt_next; - chSysUnlockFromISR(); - fn(vtp->vt_par); - chSysLockFromISR(); - } - } -#else /* CH_CFG_ST_TIMEDELTA > 0 */ - virtual_timer_t *vtp; - systime_t now, delta; - - /* First timer to be processed.*/ - vtp = ch.vtlist.vt_next; - now = chVTGetSystemTimeX(); - - /* All timers within the time window are triggered and removed, - note that the loop is stopped by the timers header having - "ch.vtlist.vt_delta == (systime_t)-1" which is greater than - all deltas.*/ - while (vtp->vt_delta <= (systime_t)(now - ch.vtlist.vt_lasttime)) { - vtfunc_t fn; - - /* The "last time" becomes this timer's expiration time.*/ - ch.vtlist.vt_lasttime += vtp->vt_delta; - - vtp->vt_next->vt_prev = (virtual_timer_t *)&ch.vtlist; - ch.vtlist.vt_next = vtp->vt_next; - fn = vtp->vt_func; - vtp->vt_func = NULL; - - /* if the list becomes empty then the timer is stopped.*/ - if (ch.vtlist.vt_next == (virtual_timer_t *)&ch.vtlist) { - port_timer_stop_alarm(); - } - - /* Leaving the system critical zone in order to execute the callback - and in order to give a preemption chance to higher priority - interrupts.*/ - chSysUnlockFromISR(); - - /* The callback is invoked outside the kernel critical zone.*/ - fn(vtp->vt_par); - - /* Re-entering the critical zone in order to continue the exploration - of the list.*/ - chSysLockFromISR(); - - /* Next element in the list, the current time could have advanced so - recalculating the time window.*/ - vtp = ch.vtlist.vt_next; - now = chVTGetSystemTimeX(); - } - - /* if the list is empty, nothing else to do.*/ - if (ch.vtlist.vt_next == (virtual_timer_t *)&ch.vtlist) { - return; - } - - /* Recalculating the next alarm time.*/ - delta = ch.vtlist.vt_lasttime + vtp->vt_delta - now; - if (delta < (systime_t)CH_CFG_ST_TIMEDELTA) { - delta = (systime_t)CH_CFG_ST_TIMEDELTA; - } - port_timer_set_alarm(now + delta); - - chDbgAssert((chVTGetSystemTimeX() - ch.vtlist.vt_lasttime) <= - (now + delta - ch.vtlist.vt_lasttime), - "exceeding delta"); -#endif /* CH_CFG_ST_TIMEDELTA > 0 */ -} - -#endif /* _CHVT_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/ports/ARM/chcore.c b/firmware/ChibiOS_16/os/rt/ports/ARM/chcore.c deleted file mode 100644 index e5cf059f3b..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/ARM/chcore.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file ARM/chcore.c - * @brief ARM port code. - * - * @addtogroup ARM_CORE - * @{ - */ - -#include "ch.h" - -/*===========================================================================*/ -/* Module local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/ports/ARM/chcore.h b/firmware/ChibiOS_16/os/rt/ports/ARM/chcore.h deleted file mode 100644 index 358b891c2a..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/ARM/chcore.h +++ /dev/null @@ -1,531 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file ARM/chcore.h - * @brief ARM7/9 architecture port macros and structures. - * - * @addtogroup ARM_CORE - * @{ - */ - -#ifndef _CHCORE_H_ -#define _CHCORE_H_ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @name Architecture and Compiler - * @{ - */ -/** - * @brief Macro defining a generic ARM architecture. - */ -#define PORT_ARCHITECTURE_ARM - -/* The following code is not processed when the file is included from an - asm module because those intrinsic macros are not necessarily defined - by the assembler too.*/ -#if !defined(_FROM_ASM_) - -/** - * @brief Compiler name and version. - */ -#if defined(__GNUC__) || defined(__DOXYGEN__) -#define PORT_COMPILER_NAME "GCC " __VERSION__ - -#else -#error "unsupported compiler" -#endif - -#endif /* !defined(_FROM_ASM_) */ -/** @} */ - -/** - * @name ARM variants - * @{ - */ -#define ARM_CORE_ARM7TDMI 7 -#define ARM_CORE_ARM9 9 -#define ARM_CORE_CORTEX_A8 108 -#define ARM_CORE_CORTEX_A9 109 -/** @} */ - -/* Inclusion of the ARM implementation specific parameters.*/ -#include "armparams.h" - -/** - * @brief This port supports a realtime counter. - */ -#define PORT_SUPPORTS_RT FALSE - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Enables an alternative timer implementation. - * @details Usually the port uses a timer interface defined in the file - * @p chcore_timer.h, if this option is enabled then the file - * @p chcore_timer_alt.h is included instead. - */ -#if !defined(PORT_USE_ALT_TIMER) -#define PORT_USE_ALT_TIMER FALSE -#endif - -/** - * @brief Stack size for the system idle thread. - * @details This size depends on the idle thread implementation, usually - * the idle thread should take no more space than those reserved - * by @p PORT_INT_REQUIRED_STACK. - * @note In this port it is set to 32 because the idle thread does have - * a stack frame when compiling without optimizations. You may - * reduce this value to zero when compiling with optimizations. - */ -#if !defined(PORT_IDLE_THREAD_STACK_SIZE) || defined(__DOXYGEN__) -#define PORT_IDLE_THREAD_STACK_SIZE 32 -#endif - -/** - * @brief Per-thread stack overhead for interrupts servicing. - * @details This constant is used in the calculation of the correct working - * area size. - */ -#if !defined(PORT_INT_REQUIRED_STACK) || defined(__DOXYGEN__) -#define PORT_INT_REQUIRED_STACK 32 -#endif - -/** - * @brief If enabled allows the idle thread to enter a low power mode. - */ -#ifndef ARM_ENABLE_WFI_IDLE -#define ARM_ENABLE_WFI_IDLE FALSE -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/* The following code is not processed when the file is included from an - asm module.*/ -#if !defined(_FROM_ASM_) - -/* ARM core check.*/ -#if (ARM_CORE == ARM_CORE_ARM7TDMI) || defined(__DOXYGEN__) -#define PORT_ARCHITECTURE_ARM_ARM7 -#define PORT_ARCHITECTURE_NAME "ARMv4T" -#define PORT_CORE_VARIANT_NAME "ARM7" - -#elif ARM_CORE == ARM_CORE_ARM9 -#define PORT_ARCHITECTURE_ARM_ARM9 -#define PORT_ARCHITECTURE_NAME "ARMv5T" -#define PORT_CORE_VARIANT_NAME "ARM9" - -#elif ARM_CORE == ARM_CORE_CORTEX_A8 -#define PORT_ARCHITECTURE_ARM_CORTEXA8 -#define PORT_ARCHITECTURE_NAME "ARMv7" -#define PORT_CORE_VARIANT_NAME "ARM Cortex-A8" - -#elif ARM_CORE == ARM_CORE_CORTEX_A9 -#define PORT_ARCHITECTURE_ARM_CORTEXA9 -#define PORT_ARCHITECTURE_NAME "ARMv7" -#define PORT_CORE_VARIANT_NAME "ARM Cortex-A9" - -#else -#error "unknown or unsupported ARM core" -#endif - -#if defined(THUMB_PRESENT) -#if defined(THUMB_NO_INTERWORKING) -#define PORT_INFO "Pure THUMB mode" -#else -#define PORT_INFO "Interworking mode" -#endif -#else -#define PORT_INFO "Pure ARM mode" -#endif - -#endif /* !defined(_FROM_ASM_) */ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/* The following code is not processed when the file is included from an - asm module.*/ -#if !defined(_FROM_ASM_) - -/** - * @brief Type of stack and memory alignment enforcement. - * @note In this architecture the stack alignment is enforced to 64 bits. - */ -typedef uint64_t stkalign_t; - -/** - * @brief Generic ARM register. - */ -typedef void *regarm_t; - -/** - * @brief Interrupt saved context. - * @details This structure represents the stack frame saved during an - * interrupt handler. - */ -struct port_extctx { - regarm_t spsr_irq; - regarm_t lr_irq; - regarm_t r0; - regarm_t r1; - regarm_t r2; - regarm_t r3; - regarm_t r12; - regarm_t lr_usr; -}; - -/** - * @brief System saved context. - * @details This structure represents the inner stack frame during a context - * switch. - */ -struct port_intctx { - regarm_t r4; - regarm_t r5; - regarm_t r6; - regarm_t r7; - regarm_t r8; - regarm_t r9; - regarm_t r10; - regarm_t r11; - regarm_t lr; -}; - -/** - * @brief Platform dependent part of the @p thread_t structure. - * @details In this port the structure just holds a pointer to the - * @p port_intctx structure representing the stack pointer - * at context switch time. - */ -struct context { - struct port_intctx *r13; -}; - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @brief Platform dependent part of the @p chThdCreateI() API. - * @details This code usually setup the context switching frame represented - * by an @p port_intctx structure. - */ -#define PORT_SETUP_CONTEXT(tp, workspace, wsize, pf, arg) { \ - (tp)->p_ctx.r13 = (struct port_intctx *)((uint8_t *)(workspace) + \ - (wsize) - \ - sizeof(struct port_intctx)); \ - (tp)->p_ctx.r13->r4 = (regarm_t)(pf); \ - (tp)->p_ctx.r13->r5 = (regarm_t)(arg); \ - (tp)->p_ctx.r13->lr = (regarm_t)(_port_thread_start); \ -} - -/** - * @brief Computes the thread working area global size. - * @note There is no need to perform alignments in this macro. - */ -#define PORT_WA_SIZE(n) (sizeof(struct port_intctx) + \ - sizeof(struct port_extctx) + \ - ((size_t)(n)) + ((size_t)(PORT_INT_REQUIRED_STACK))) - -/** - * @brief Priority level verification macro. - * @todo Add the required parameters to armparams.h. - */ -#define PORT_IRQ_IS_VALID_PRIORITY(n) false - -/** - * @brief IRQ prologue code. - * @details This macro must be inserted at the start of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_PROLOGUE() - -/** - * @brief IRQ epilogue code. - * @details This macro must be inserted at the end of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_EPILOGUE() return chSchIsPreemptionRequired() - -/** - * @brief IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_IRQ_HANDLER(id) bool id(void) - -/** - * @brief Fast IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_FAST_IRQ_HANDLER(id) \ - __attribute__((interrupt("FIQ"))) void id(void) - -/** - * @brief Performs a context switch between two threads. - * @details This is the most critical code in any port, this function - * is responsible for the context switch between 2 threads. - * @note The implementation of this code affects directly the context - * switch performance so optimize here as much as you can. - * @note Implemented as inlined code for performance reasons. - * - * @param[in] ntp the thread to be switched in - * @param[in] otp the thread to be switched out - */ -#if defined(THUMB) - -#if CH_DBG_ENABLE_STACK_CHECK == TRUE -#define port_switch(ntp, otp) { \ - register struct port_intctx *r13 asm ("r13"); \ - if ((stkalign_t *)(r13 - 1) < otp->p_stklimit) \ - chSysHalt("stack overflow"); \ - _port_switch_thumb(ntp, otp); \ -} -#else -#define port_switch(ntp, otp) _port_switch_thumb(ntp, otp) -#endif - -#else /* !defined(THUMB) */ - -#if CH_DBG_ENABLE_STACK_CHECK == TRUE -#define port_switch(ntp, otp) { \ - register struct port_intctx *r13 asm ("r13"); \ - if ((stkalign_t *)(r13 - 1) < otp->p_stklimit) \ - chSysHalt("stack overflow"); \ - _port_switch_arm(ntp, otp); \ -} -#else -#define port_switch(ntp, otp) _port_switch_arm(ntp, otp) -#endif - -#endif /* !defined(THUMB) */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif -#if defined(THUMB_PRESENT) - syssts_t _port_get_cpsr(void); -#endif -#if defined(THUMB) - void _port_switch_thumb(thread_t *ntp, thread_t *otp); -#else - void _port_switch_arm(thread_t *ntp, thread_t *otp); -#endif - void _port_thread_start(void); -#ifdef __cplusplus -} -#endif - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -/** - * @brief Port-related initialization code. - */ -static inline void port_init(void) { - -} - -/** - * @brief Returns a word encoding the current interrupts status. - * - * @return The interrupts status. - */ -static inline syssts_t port_get_irq_status(void) { - syssts_t sts; - -#if defined(THUMB) - sts = _port_get_cpsr(); -#else - __asm volatile ("mrs %[p0], CPSR" : [p0] "=r" (sts) :); -#endif - /*lint -save -e530 [9.1] Asm instruction not seen by lint.*/ - return sts; - /*lint -restore*/ -} - -/** - * @brief Checks the interrupt status. - * - * @param[in] sts the interrupt status word - * - * @return The interrupt status. - * @retvel false the word specified a disabled interrupts status. - * @retvel true the word specified an enabled interrupts status. - */ -static inline bool port_irq_enabled(syssts_t sts) { - - return (sts & (syssts_t)0x80) == (syssts_t)0; -} - -/** - * @brief Determines the current execution context. - * - * @return The execution context. - * @retval false not running in ISR mode. - * @retval true running in ISR mode. - */ -static inline bool port_is_isr_context(void) { - syssts_t sts; - -#if defined(THUMB) - sts = _port_get_cpsr(); -#else - __asm volatile ("mrs %[p0], CPSR" : [p0] "=r" (sts) :); -#endif - - /*lint -save -e530 [9.1] Asm instruction not seen by lint.*/ - return (sts & (syssts_t)0x1F) == (syssts_t)0x12; - /*lint -restore*/ -} - -/** - * @brief Kernel-lock action. - * @details In this port it disables the IRQ sources and keeps FIQ sources - * enabled. - */ -static inline void port_lock(void) { - -#if defined(THUMB) - __asm volatile ("bl _port_lock_thumb" : : : "r3", "lr", "memory"); -#else - __asm volatile ("msr CPSR_c, #0x9F" : : : "memory"); -#endif -} - -/** - * @brief Kernel-unlock action. - * @details In this port it enables both the IRQ and FIQ sources. - */ -static inline void port_unlock(void) { - -#if defined(THUMB) - __asm volatile ("bl _port_unlock_thumb" : : : "r3", "lr", "memory"); -#else - __asm volatile ("msr CPSR_c, #0x1F" : : : "memory"); -#endif -} - -/** - * @brief Kernel-lock action from an interrupt handler. - * @note Empty in this port. - */ -static inline void port_lock_from_isr(void) { - -} - -/** - * @brief Kernel-unlock action from an interrupt handler. - * @note Empty in this port. - */ -static inline void port_unlock_from_isr(void) { - -} - -/** - * @brief Disables all the interrupt sources. - * @details In this port it disables both the IRQ and FIQ sources. - * @note Implements a workaround for spurious interrupts taken from the NXP - * LPC214x datasheet. - */ -static inline void port_disable(void) { - -#if defined(THUMB) - __asm volatile ("bl _port_disable_thumb" : : : "r3", "lr", "memory"); -#else - __asm volatile ("mrs r3, CPSR \n\t" - "orr r3, #0x80 \n\t" - "msr CPSR_c, r3 \n\t" - "orr r3, #0x40 \n\t" - "msr CPSR_c, r3" : : : "r3", "memory"); -#endif -} - -/** - * @brief Disables the interrupt sources below kernel-level priority. - * @note Interrupt sources above kernel level remains enabled. - * @note In this port it disables the IRQ sources and enables the - * FIQ sources. - */ -static inline void port_suspend(void) { - -#if defined(THUMB) - __asm volatile ("bl _port_suspend_thumb" : : : "r3", "lr", "memory"); -#else - __asm volatile ("msr CPSR_c, #0x9F" : : : "memory"); -#endif -} - -/** - * @brief Enables all the interrupt sources. - * @note In this port it enables both the IRQ and FIQ sources. - */ -static inline void port_enable(void) { - -#if defined(THUMB) - __asm volatile ("bl _port_enable_thumb" : : : "r3", "lr", "memory"); -#else - __asm volatile ("msr CPSR_c, #0x1F" : : : "memory"); -#endif -} - -/** - * @brief Enters an architecture-dependent IRQ-waiting mode. - * @details The function is meant to return when an interrupt becomes pending. - * The simplest implementation is an empty function or macro but this - * would not take advantage of architecture-specific power saving - * modes. - * @note Implemented as an inlined @p WFI instruction. - */ -static inline void port_wait_for_interrupt(void) { - -#if ARM_ENABLE_WFI_IDLE == TRUE - ARM_WFI_IMPL; -#endif -} - -#if CH_CFG_ST_TIMEDELTA > 0 -#if PORT_USE_ALT_TIMER == FALSE -#include "chcore_timer.h" -#else /* PORT_USE_ALT_TIMER */ -#include "chcore_timer_alt.h" -#endif /* PORT_USE_ALT_TIMER */ -#endif /* CH_CFG_ST_TIMEDELTA > 0 */ - -#endif /* !defined(_FROM_ASM_) */ - -#endif /* _CHCORE_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/ports/ARM/chcore_timer.h b/firmware/ChibiOS_16/os/rt/ports/ARM/chcore_timer.h deleted file mode 100644 index e2c55219f0..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/ARM/chcore_timer.h +++ /dev/null @@ -1,124 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chcore_timer.h - * @brief System timer header file. - * - * @addtogroup ARM_TIMER - * @{ - */ - -#ifndef _CHCORE_TIMER_H_ -#define _CHCORE_TIMER_H_ - -/* This is the only header in the HAL designed to be include-able alone.*/ -#include "st.h" - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -/** - * @brief Starts the alarm. - * @note Makes sure that no spurious alarms are triggered after - * this call. - * - * @param[in] time the time to be set for the first alarm - * - * @notapi - */ -static inline void port_timer_start_alarm(systime_t time) { - - stStartAlarm(time); -} - -/** - * @brief Stops the alarm interrupt. - * - * @notapi - */ -static inline void port_timer_stop_alarm(void) { - - stStopAlarm(); -} - -/** - * @brief Sets the alarm time. - * - * @param[in] time the time to be set for the next alarm - * - * @notapi - */ -static inline void port_timer_set_alarm(systime_t time) { - - stSetAlarm(time); -} - -/** - * @brief Returns the system time. - * - * @return The system time. - * - * @notapi - */ -static inline systime_t port_timer_get_time(void) { - - return stGetCounter(); -} - -/** - * @brief Returns the current alarm time. - * - * @return The currently set alarm time. - * - * @notapi - */ -static inline systime_t port_timer_get_alarm(void) { - - return stGetAlarm(); -} - -#endif /* _CHCORE_TIMER_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/ports/ARM/compilers/GCC/chcoreasm.s b/firmware/ChibiOS_16/os/rt/ports/ARM/compilers/GCC/chcoreasm.s deleted file mode 100644 index af740187f9..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/ARM/compilers/GCC/chcoreasm.s +++ /dev/null @@ -1,278 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file ARM/compilers/GCC/chcoreasm.s - * @brief ARM architecture port low level code. - * - * @addtogroup ARM_CORE - * @{ - */ - -#define _FROM_ASM_ -#include "chconf.h" -#include "armparams.h" - -#define FALSE 0 -#define TRUE 1 - -#if !defined(__DOXYGEN__) - - .set MODE_USR, 0x10 - .set MODE_FIQ, 0x11 - .set MODE_IRQ, 0x12 - .set MODE_SVC, 0x13 - .set MODE_ABT, 0x17 - .set MODE_UND, 0x1B - .set MODE_SYS, 0x1F - - .equ I_BIT, 0x80 - .equ F_BIT, 0x40 - - .text - -/* - * The following functions are only present if there is THUMB code in - * the system. - */ -#if defined(THUMB_PRESENT) - .balign 16 - .code 16 - .thumb_func - .global _port_get_cpsr -_port_get_cpsr: - mov r0, pc - bx r0 -.code 32 - mrs r0, CPSR - bx lr - - .balign 16 - .code 16 - .thumb_func - .global _port_disable_thumb -_port_disable_thumb: - mov r3, pc - bx r3 -.code 32 - mrs r3, CPSR - orr r3, #I_BIT - msr CPSR_c, r3 - orr r3, #F_BIT - msr CPSR_c, r3 - bx lr - - .balign 16 - .code 16 - .thumb_func - .global _port_suspend_thumb -_port_suspend_thumb: - // Goes into _port_unlock_thumb - - .code 16 - .global _port_lock_thumb -_port_lock_thumb: - mov r3, pc - bx r3 - .code 32 - msr CPSR_c, #MODE_SYS | I_BIT - bx lr - - .balign 16 - .code 16 - .thumb_func - .global _port_enable_thumb -_port_enable_thumb: - // Goes into _port_unlock_thumb - - .code 16 - .global _port_unlock_thumb -_port_unlock_thumb: - mov r3, pc - bx r3 - .code 32 - msr CPSR_c, #MODE_SYS - bx lr -#endif /* defined(THUMB_PRESENT) */ - - .balign 16 -#if defined(THUMB_PRESENT) - .code 16 - .thumb_func - .global _port_switch_thumb -_port_switch_thumb: - mov r2, pc - bx r2 - // Goes into _port_switch_arm in ARM mode -#endif /* defined(THUMB_PRESENT) */ - - .code 32 - .global _port_switch_arm -_port_switch_arm: - stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr} - str sp, [r1, #12] - ldr sp, [r0, #12] -#if defined(THUMB_PRESENT) - ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr} - bx lr -#else /* !defined(THUMB_PRESENT)T */ - ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc} -#endif /* !defined(THUMB_PRESENT) */ - -/* - * Common IRQ code. It expects a macro ARM_IRQ_VECTOR_REG with the address - * of a register holding the address of the ISR to be invoked, the ISR - * then returns in the common epilogue code where the context switch will - * be performed, if required. - * System stack frame structure after a context switch in the - * interrupt handler: - * - * High +------------+ - * | LR_USR | -+ - * | r12 | | - * | r3 | | - * | r2 | | External context: IRQ handler frame - * | r1 | | - * | r0 | | - * | LR_IRQ | | (user code return address) - * | PSR_USR | -+ (user code status) - * | .... | <- chSchDoReschedule() stack frame, optimize it for space - * | LR | -+ (system code return address) - * | r11 | | - * | r10 | | - * | r9 | | - * | r8 | | Internal context: chSysSwitch() frame - * | r7 | | - * | r6 | | - * | r5 | | - * SP-> | r4 | -+ - * Low +------------+ - */ - .balign 16 - .code 32 - .global Irq_Handler -Irq_Handler: - stmfd sp!, {r0-r3, r12, lr} - ldr r0, =ARM_IRQ_VECTOR_REG - ldr r0, [r0] -#if !defined(THUMB_NO_INTERWORKING) - ldr lr, =_irq_ret_arm // ISR return point. - bx r0 // Calling the ISR. -_irq_ret_arm: -#else /* defined(THUMB_NO_INTERWORKING) */ - add r1, pc, #1 - bx r1 - .code 16 - bl _bxr0 // Calling the ISR. - mov lr, pc - bx lr - .code 32 -#endif /* defined(THUMB_NO_INTERWORKING) */ - cmp r0, #0 - ldmfd sp!, {r0-r3, r12, lr} - subeqs pc, lr, #4 // No reschedule, returns. - - // Now the frame is created in the system stack, the IRQ - // stack is empty. - msr CPSR_c, #MODE_SYS | I_BIT - stmfd sp!, {r0-r3, r12, lr} - msr CPSR_c, #MODE_IRQ | I_BIT - mrs r0, SPSR - mov r1, lr - msr CPSR_c, #MODE_SYS | I_BIT - stmfd sp!, {r0, r1} // Push R0=SPSR, R1=LR_IRQ. - - // Context switch. -#if defined(THUMB_NO_INTERWORKING) - add r0, pc, #1 - bx r0 - .code 16 -#if CH_DBG_SYSTEM_STATE_CHECK - bl _dbg_check_lock -#endif - bl chSchDoReschedule -#if CH_DBG_SYSTEM_STATE_CHECK - bl _dbg_check_unlock -#endif - mov lr, pc - bx lr - .code 32 -#else /* !defined(THUMB_NO_INTERWORKING) */ -#if CH_DBG_SYSTEM_STATE_CHECK - bl _dbg_check_lock -#endif - bl chSchDoReschedule -#if CH_DBG_SYSTEM_STATE_CHECK - bl _dbg_check_unlock -#endif -#endif /* !defined(THUMB_NO_INTERWORKING) */ - - // Re-establish the IRQ conditions again. - ldmfd sp!, {r0, r1} // Pop R0=SPSR, R1=LR_IRQ. - msr CPSR_c, #MODE_IRQ | I_BIT - msr SPSR_fsxc, r0 - mov lr, r1 - msr CPSR_c, #MODE_SYS | I_BIT - ldmfd sp!, {r0-r3, r12, lr} - msr CPSR_c, #MODE_IRQ | I_BIT - subs pc, lr, #4 -#if defined(THUMB_NO_INTERWORKING) - .code 16 -_bxr0: bx r0 -#endif - -/* - * Threads trampoline code. - * NOTE: The threads always start in ARM mode and then switches to the - * thread-function mode. - */ - .balign 16 - .code 32 - .globl _port_thread_start -_port_thread_start: -#if defined(THUMB_NO_INTERWORKING) - add r0, pc, #1 - bx r0 - .code 16 -#if CH_DBG_SYSTEM_STATE_CHECK - bl _dbg_check_unlock -#endif - bl _port_unlock_thumb - mov r0, r5 - bl _bxr4 - bl chThdExit -_zombies: b _zombies -_bxr4: bx r4 - -#else /* !defined(THUMB_NO_INTERWORKING) */ -#if CH_DBG_SYSTEM_STATE_CHECK - bl _dbg_check_unlock -#endif - msr CPSR_c, #MODE_SYS - mov r0, r5 - mov lr, pc - bx r4 - mov r0, #0 /* MSG_OK */ - bl chThdExit -_zombies: b _zombies -#endif /* !defined(THUMB_NO_INTERWORKING) */ - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/ports/ARM/compilers/GCC/chtypes.h b/firmware/ChibiOS_16/os/rt/ports/ARM/compilers/GCC/chtypes.h deleted file mode 100644 index 3423b0d558..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/ARM/compilers/GCC/chtypes.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file ARM/compilers/GCC/chtypes.h - * @brief ARM port system types. - * - * @addtogroup ARM_GCC_CORE - * @{ - */ - -#ifndef _CHTYPES_H_ -#define _CHTYPES_H_ - -#include -#include -#include - -/** - * @name Common constants - */ -/** - * @brief Generic 'false' boolean constant. - */ -#if !defined(FALSE) || defined(__DOXYGEN__) -#define FALSE 0 -#endif - -/** - * @brief Generic 'true' boolean constant. - */ -#if !defined(TRUE) || defined(__DOXYGEN__) -#define TRUE 1 -#endif -/** @} */ - -/** - * @name Kernel types - * @{ - */ -typedef uint32_t rtcnt_t; /**< Realtime counter. */ -typedef uint64_t rttime_t; /**< Realtime accumulator. */ -typedef uint32_t syssts_t; /**< System status word. */ -typedef uint8_t tmode_t; /**< Thread flags. */ -typedef uint8_t tstate_t; /**< Thread state. */ -typedef uint8_t trefs_t; /**< Thread references counter. */ -typedef uint8_t tslices_t; /**< Thread time slices counter.*/ -typedef uint32_t tprio_t; /**< Thread priority. */ -typedef int32_t msg_t; /**< Inter-thread message. */ -typedef int32_t eventid_t; /**< Numeric event identifier. */ -typedef uint32_t eventmask_t; /**< Mask of event identifiers. */ -typedef uint32_t eventflags_t; /**< Mask of event flags. */ -typedef int32_t cnt_t; /**< Generic signed counter. */ -typedef uint32_t ucnt_t; /**< Generic unsigned counter. */ -/** @} */ - -/** - * @brief ROM constant modifier. - * @note It is set to use the "const" keyword in this port. - */ -#define ROMCONST const - -/** - * @brief Makes functions not inlineable. - * @note If the compiler does not support such attribute then the - * realtime counter precision could be degraded. - */ -#define NOINLINE __attribute__((noinline)) - -/** - * @brief Optimized thread function declaration macro. - */ -#define PORT_THD_FUNCTION(tname, arg) void tname(void *arg) - -/** - * @brief Packed variable specifier. - */ -#define PACKED_VAR __attribute__((packed)) - -#endif /* _CHTYPES_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/ports/ARM/compilers/GCC/mk/port_generic.mk b/firmware/ChibiOS_16/os/rt/ports/ARM/compilers/GCC/mk/port_generic.mk deleted file mode 100644 index 1026370533..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/ARM/compilers/GCC/mk/port_generic.mk +++ /dev/null @@ -1,7 +0,0 @@ -# List of the ChibiOS/RT ARM generic port files. -PORTSRC = ${CHIBIOS}/os/rt/ports/ARM/chcore.c - -PORTASM = $(CHIBIOS)/os/rt/ports/ARM/compilers/GCC/chcoreasm.s - -PORTINC = ${CHIBIOS}/os/rt/ports/ARM \ - ${CHIBIOS}/os/rt/ports/ARM/compilers/GCC diff --git a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/chcore.c b/firmware/ChibiOS_16/os/rt/ports/ARMCMx/chcore.c deleted file mode 100644 index 04e1a196cf..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/chcore.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file ARMCMx/chcore.c - * @brief ARM Cortex-Mx port code. - * - * @addtogroup ARMCMx_CORE - * @{ - */ - -#include "ch.h" - -/*===========================================================================*/ -/* Module local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/chcore.h b/firmware/ChibiOS_16/os/rt/ports/ARMCMx/chcore.h deleted file mode 100644 index d710566c8e..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/chcore.h +++ /dev/null @@ -1,214 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file ARMCMx/chcore.h - * @brief ARM Cortex-Mx port macros and structures. - * - * @addtogroup ARMCMx_CORE - * @{ - */ - -#ifndef _CHCORE_H_ -#define _CHCORE_H_ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @name Architecture and Compiler - * @{ - */ -/** - * @brief Macro defining a generic ARM architecture. - */ -#define PORT_ARCHITECTURE_ARM - -/* The following code is not processed when the file is included from an - asm module because those intrinsic macros are not necessarily defined - by the assembler too.*/ -#if !defined(_FROM_ASM_) - -/** - * @brief Compiler name and version. - */ -#if defined(__GNUC__) || defined(__DOXYGEN__) -#define PORT_COMPILER_NAME "GCC " __VERSION__ - -#elif defined(__ICCARM__) -#define PORT_COMPILER_NAME "IAR" - -#elif defined(__CC_ARM) -#define PORT_COMPILER_NAME "RVCT" - -#else -#error "unsupported compiler" -#endif - -#endif /* !defined(_FROM_ASM_) */ - -/** @} */ - -/* Inclusion of the Cortex-Mx implementation specific parameters.*/ -#include "cmparams.h" - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Enables an alternative timer implementation. - * @details Usually the port uses a timer interface defined in the file - * @p chcore_timer.h, if this option is enabled then the file - * @p chcore_timer_alt.h is included instead. - */ -#if !defined(PORT_USE_ALT_TIMER) -#define PORT_USE_ALT_TIMER FALSE -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/* The following code is not processed when the file is included from an - asm module.*/ -#if !defined(_FROM_ASM_) - -/** - * @brief Type of a generic ARM register. - */ -typedef void *regarm_t; - -/** - * @brief Type of stack and memory alignment enforcement. - * @note In this architecture the stack alignment is enforced to 64 bits, - * 32 bits alignment is supported by hardware but deprecated by ARM, - * the implementation choice is to not offer the option. - */ -typedef uint64_t stkalign_t; - -/* The following declarations are there just for Doxygen documentation, the - real declarations are inside the sub-headers being specific for the - sub-architectures.*/ -#if defined(__DOXYGEN__) -/** - * @brief Interrupt saved context. - * @details This structure represents the stack frame saved during a - * preemption-capable interrupt handler. - * @note It is implemented to match the Cortex-Mx exception context. - */ -struct port_extctx {}; - -/** - * @brief System saved context. - * @details This structure represents the inner stack frame during a context - * switch. - */ -struct port_intctx {}; -#endif /* defined(__DOXYGEN__) */ - -/** - * @brief Platform dependent part of the @p thread_t structure. - * @details In this port the structure just holds a pointer to the - * @p port_intctx structure representing the stack pointer - * at context switch time. - */ -struct context { - struct port_intctx *r13; -}; - -#endif /* !defined(_FROM_ASM_) */ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @brief Total priority levels. - */ -#define CORTEX_PRIORITY_LEVELS (1U << CORTEX_PRIORITY_BITS) - -/** - * @brief Minimum priority level. - * @details This minimum priority level is calculated from the number of - * priority bits supported by the specific Cortex-Mx implementation. - */ -#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1) - -/** - * @brief Maximum priority level. - * @details The maximum allowed priority level is always zero. - */ -#define CORTEX_MAXIMUM_PRIORITY 0U - -/** - * @brief Priority level to priority mask conversion macro. - */ -#define CORTEX_PRIO_MASK(n) \ - ((n) << (8U - (unsigned)CORTEX_PRIORITY_BITS)) - -/** - * @brief Priority level verification macro. - */ -#define PORT_IRQ_IS_VALID_PRIORITY(n) \ - (((n) >= 0U) && ((n) < CORTEX_PRIORITY_LEVELS)) - -/** - * @brief Priority level verification macro. - */ -#define PORT_IRQ_IS_VALID_KERNEL_PRIORITY(n) \ - (((n) >= CORTEX_MAX_KERNEL_PRIORITY) && ((n) < CORTEX_PRIORITY_LEVELS)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -/* Includes the sub-architecture-specific part.*/ -#if (CORTEX_MODEL == 0) || (CORTEX_MODEL == 1) -#include "chcore_v6m.h" -#elif (CORTEX_MODEL == 3) || (CORTEX_MODEL == 4) || (CORTEX_MODEL == 7) -#include "chcore_v7m.h" -#else -#error "unknown Cortex-M variant" -#endif - -#if !defined(_FROM_ASM_) - -#if CH_CFG_ST_TIMEDELTA > 0 -#if PORT_USE_ALT_TIMER == FALSE -#include "chcore_timer.h" -#else /* PORT_USE_ALT_TIMER != FALSE */ -#include "chcore_timer_alt.h" -#endif /* PORT_USE_ALT_TIMER != FALSE */ -#endif /* CH_CFG_ST_TIMEDELTA > 0 */ - -#endif /* !defined(_FROM_ASM_) */ - -#endif /* _CHCORE_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/chcore_timer.h b/firmware/ChibiOS_16/os/rt/ports/ARMCMx/chcore_timer.h deleted file mode 100644 index f437b2d0e7..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/chcore_timer.h +++ /dev/null @@ -1,124 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chcore_timer.h - * @brief System timer header file. - * - * @addtogroup ARMCMx_TIMER - * @{ - */ - -#ifndef _CHCORE_TIMER_H_ -#define _CHCORE_TIMER_H_ - -/* This is the only header in the HAL designed to be include-able alone.*/ -#include "st.h" - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -/** - * @brief Starts the alarm. - * @note Makes sure that no spurious alarms are triggered after - * this call. - * - * @param[in] time the time to be set for the first alarm - * - * @notapi - */ -static inline void port_timer_start_alarm(systime_t time) { - - stStartAlarm(time); -} - -/** - * @brief Stops the alarm interrupt. - * - * @notapi - */ -static inline void port_timer_stop_alarm(void) { - - stStopAlarm(); -} - -/** - * @brief Sets the alarm time. - * - * @param[in] time the time to be set for the next alarm - * - * @notapi - */ -static inline void port_timer_set_alarm(systime_t time) { - - stSetAlarm(time); -} - -/** - * @brief Returns the system time. - * - * @return The system time. - * - * @notapi - */ -static inline systime_t port_timer_get_time(void) { - - return stGetCounter(); -} - -/** - * @brief Returns the current alarm time. - * - * @return The currently set alarm time. - * - * @notapi - */ -static inline systime_t port_timer_get_alarm(void) { - - return stGetAlarm(); -} - -#endif /* _CHCORE_TIMER_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/chcore_v6m.c b/firmware/ChibiOS_16/os/rt/ports/ARMCMx/chcore_v6m.c deleted file mode 100644 index 831d7ba1e5..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/chcore_v6m.c +++ /dev/null @@ -1,147 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chcore_v6m.c - * @brief ARMv6-M architecture port code. - * - * @addtogroup ARMCMx_V6M_CORE - * @{ - */ - -#include "ch.h" - -/*===========================================================================*/ -/* Module local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module interrupt handlers. */ -/*===========================================================================*/ - -#if (CORTEX_ALTERNATE_SWITCH == FALSE) || defined(__DOXYGEN__) -/** - * @brief NMI vector. - * @details The NMI vector is used for exception mode re-entering after a - * context switch. - */ -/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/ -void NMI_Handler(void) { -/*lint -restore*/ - - /* The port_extctx structure is pointed by the PSP register.*/ - struct port_extctx *ctxp = (struct port_extctx *)__get_PSP(); - - /* Discarding the current exception context and positioning the stack to - point to the real one.*/ - ctxp++; - - /* Writing back the modified PSP value.*/ - __set_PSP((uint32_t)ctxp); - - /* Restoring the normal interrupts status.*/ - port_unlock_from_isr(); -} -#endif /* !CORTEX_ALTERNATE_SWITCH */ - -#if (CORTEX_ALTERNATE_SWITCH == TRUE) || defined(__DOXYGEN__) -/** - * @brief PendSV vector. - * @details The PendSV vector is used for exception mode re-entering after a - * context switch. - */ -/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/ -void PendSV_Handler(void) { -/*lint -restore*/ - - /* The port_extctx structure is pointed by the PSP register.*/ - struct port_extctx *ctxp = (struct port_extctx *)__get_PSP(); - - /* Discarding the current exception context and positioning the stack to - point to the real one.*/ - ctxp++; - - /* Writing back the modified PSP value.*/ - __set_PSP((uint32_t)ctxp); -} -#endif /* CORTEX_ALTERNATE_SWITCH */ - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -/** - * @brief IRQ epilogue code. - * - * @param[in] lr value of the @p LR register on ISR entry - */ -void _port_irq_epilogue(regarm_t lr) { - - if (lr != (regarm_t)0xFFFFFFF1U) { - struct port_extctx *ctxp; - - port_lock_from_isr(); - - /* The extctx structure is pointed by the PSP register.*/ - ctxp = (struct port_extctx *)__get_PSP(); - - /* Adding an artificial exception return context, there is no need to - populate it fully.*/ - ctxp--; - - /* Writing back the modified PSP value.*/ - __set_PSP((uint32_t)ctxp); - - /* Setting up a fake XPSR register value.*/ - ctxp->xpsr = (regarm_t)0x01000000; - - /* The exit sequence is different depending on if a preemption is - required or not.*/ - if (chSchIsPreemptionRequired()) { - /* Preemption is required we need to enforce a context switch.*/ - ctxp->pc = (regarm_t)_port_switch_from_isr; - } - else { - /* Preemption not required, we just need to exit the exception - atomically.*/ - ctxp->pc = (regarm_t)_port_exit_from_isr; - } - - /* Note, returning without unlocking is intentional, this is done in - order to keep the rest of the context switch atomic.*/ - } -} - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/chcore_v6m.h b/firmware/ChibiOS_16/os/rt/ports/ARMCMx/chcore_v6m.h deleted file mode 100644 index 76d6a2e9cd..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/chcore_v6m.h +++ /dev/null @@ -1,407 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chcore_v6m.h - * @brief ARMv6-M architecture port macros and structures. - * - * @addtogroup ARMCMx_V6M_CORE - * @{ - */ - -#ifndef _CHCORE_V6M_H_ -#define _CHCORE_V6M_H_ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @brief This port does not support a realtime counter. - */ -#define PORT_SUPPORTS_RT FALSE - -/** - * @brief PendSV priority level. - * @note This priority is enforced to be equal to @p 0, - * this handler always has the highest priority that cannot preempt - * the kernel. - */ -#define CORTEX_PRIORITY_PENDSV 0 - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Stack size for the system idle thread. - * @details This size depends on the idle thread implementation, usually - * the idle thread should take no more space than those reserved - * by @p PORT_INT_REQUIRED_STACK. - * @note In this port it is set to 16 because the idle thread does have - * a stack frame when compiling without optimizations. You may - * reduce this value to zero when compiling with optimizations. - */ -#if !defined(PORT_IDLE_THREAD_STACK_SIZE) -#define PORT_IDLE_THREAD_STACK_SIZE 16 -#endif - -/** - * @brief Per-thread stack overhead for interrupts servicing. - * @details This constant is used in the calculation of the correct working - * area size. - * @note In this port this value is conservatively set to 64 because the - * function @p chSchDoReschedule() can have a stack frame, especially - * with compiler optimizations disabled. The value can be reduced - * when compiler optimizations are enabled. - */ -#if !defined(PORT_INT_REQUIRED_STACK) -#define PORT_INT_REQUIRED_STACK 64 -#endif - -/** - * @brief Enables the use of the WFI instruction in the idle thread loop. - */ -#if !defined(CORTEX_ENABLE_WFI_IDLE) -#define CORTEX_ENABLE_WFI_IDLE FALSE -#endif - -/** - * @brief Alternate preemption method. - * @details Activating this option will make the Kernel use the PendSV - * handler for preemption instead of the NMI handler. - */ -#ifndef CORTEX_ALTERNATE_SWITCH -#define CORTEX_ALTERNATE_SWITCH FALSE -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/** - * @name Architecture and Compiler - * @{ - */ -#if ((CORTEX_MODEL == 0) && !defined(__CORE_CM0PLUS_H_DEPENDANT)) || \ - defined(__DOXYGEN__) -/** - * @brief Macro defining the specific ARM architecture. - */ -#define PORT_ARCHITECTURE_ARM_v6M - -/** - * @brief Name of the implemented architecture. - */ -#define PORT_ARCHITECTURE_NAME "ARMv6-M" - -/** - * @brief Name of the architecture variant. - */ -#define PORT_CORE_VARIANT_NAME "Cortex-M0" - -#elif (CORTEX_MODEL == 0) && defined(__CORE_CM0PLUS_H_DEPENDANT) -#define PORT_ARCHITECTURE_ARM_v6M -#define PORT_ARCHITECTURE_NAME "ARMv6-M" -#define PORT_CORE_VARIANT_NAME "Cortex-M0+" -#endif - -/** - * @brief Port-specific information string. - */ -#if (CORTEX_ALTERNATE_SWITCH == FALSE) || defined(__DOXYGEN__) -#define PORT_INFO "Preemption through NMI" -#else -#define PORT_INFO "Preemption through PendSV" -#endif -/** @} */ - -/** - * @brief Maximum usable priority for normal ISRs. - */ -#if (CORTEX_ALTERNATE_SWITCH == TRUE) || defined(__DOXYGEN__) -#define CORTEX_MAX_KERNEL_PRIORITY 1 -#else -#define CORTEX_MAX_KERNEL_PRIORITY 0 -#endif - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -#if !defined(_FROM_ASM_) - - /* The documentation of the following declarations is in chconf.h in order - to not have duplicated structure names into the documentation.*/ -#if !defined(__DOXYGEN__) -struct port_extctx { - regarm_t r0; - regarm_t r1; - regarm_t r2; - regarm_t r3; - regarm_t r12; - regarm_t lr_thd; - regarm_t pc; - regarm_t xpsr; -}; - -struct port_intctx { - regarm_t r8; - regarm_t r9; - regarm_t r10; - regarm_t r11; - regarm_t r4; - regarm_t r5; - regarm_t r6; - regarm_t r7; - regarm_t lr; -}; -#endif /* !defined(__DOXYGEN__) */ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @brief Platform dependent part of the @p chThdCreateI() API. - * @details This code usually setup the context switching frame represented - * by an @p port_intctx structure. - */ -#define PORT_SETUP_CONTEXT(tp, workspace, wsize, pf, arg) { \ - (tp)->p_ctx.r13 = (struct port_intctx *)((uint8_t *)(workspace) + \ - (wsize) - \ - sizeof(struct port_intctx)); \ - (tp)->p_ctx.r13->r4 = (regarm_t)(pf); \ - (tp)->p_ctx.r13->r5 = (regarm_t)(arg); \ - (tp)->p_ctx.r13->lr = (regarm_t)_port_thread_start; \ -} - -/** - * @brief Computes the thread working area global size. - * @note There is no need to perform alignments in this macro. - */ -#define PORT_WA_SIZE(n) (sizeof(struct port_intctx) + \ - sizeof(struct port_extctx) + \ - ((size_t)(n)) + ((size_t)(PORT_INT_REQUIRED_STACK))) - -/** - * @brief IRQ prologue code. - * @details This macro must be inserted at the start of all IRQ handlers - * enabled to invoke system APIs. - */ -#if defined(__GNUC__) || defined(__DOXYGEN__) -#define PORT_IRQ_PROLOGUE() \ - regarm_t _saved_lr = (regarm_t)__builtin_return_address(0) -#elif defined(__ICCARM__) -#define PORT_IRQ_PROLOGUE() \ - regarm_t _saved_lr = (regarm_t)__get_LR() -#elif defined(__CC_ARM) -#define PORT_IRQ_PROLOGUE() \ - regarm_t _saved_lr = (regarm_t)__return_address() -#endif - -/** - * @brief IRQ epilogue code. - * @details This macro must be inserted at the end of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_EPILOGUE() _port_irq_epilogue(_saved_lr) - -/** - * @brief IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_IRQ_HANDLER(id) void id(void) - -/** - * @brief Fast IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_FAST_IRQ_HANDLER(id) void id(void) - -/** - * @brief Performs a context switch between two threads. - * @details This is the most critical code in any port, this function - * is responsible for the context switch between 2 threads. - * @note The implementation of this code affects directly the context - * switch performance so optimize here as much as you can. - * - * @param[in] ntp the thread to be switched in - * @param[in] otp the thread to be switched out - */ -#if (CH_DBG_ENABLE_STACK_CHECK == FALSE) || defined(__DOXYGEN__) -#define port_switch(ntp, otp) _port_switch(ntp, otp) -#else -#define port_switch(ntp, otp) { \ - struct port_intctx *r13 = (struct port_intctx *)__get_PSP(); \ - if ((stkalign_t *)(r13 - 1) < (otp)->p_stklimit) { \ - chSysHalt("stack overflow"); \ - } \ - _port_switch(ntp, otp); \ -} -#endif - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void _port_irq_epilogue(regarm_t lr); - void _port_switch(thread_t *ntp, thread_t *otp); - void _port_thread_start(void); - void _port_switch_from_isr(void); - void _port_exit_from_isr(void); -#ifdef __cplusplus -} -#endif - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -/** - * @brief Port-related initialization code. - */ -static inline void port_init(void) { - - NVIC_SetPriority(PendSV_IRQn, CORTEX_PRIORITY_PENDSV); -} - -/** - * @brief Returns a word encoding the current interrupts status. - * - * @return The interrupts status. - */ -static inline syssts_t port_get_irq_status(void) { - - return (syssts_t)__get_PRIMASK(); -} - -/** - * @brief Checks the interrupt status. - * - * @param[in] sts the interrupt status word - * - * @return The interrupt status. - * @retvel false the word specified a disabled interrupts status. - * @retvel true the word specified an enabled interrupts status. - */ -static inline bool port_irq_enabled(syssts_t sts) { - - return (sts & (syssts_t)1) == (syssts_t)0; -} - -/** - * @brief Determines the current execution context. - * - * @return The execution context. - * @retval false not running in ISR mode. - * @retval true running in ISR mode. - */ -static inline bool port_is_isr_context(void) { - - return (bool)((__get_IPSR() & 0x1FFU) != 0U); -} - -/** - * @brief Kernel-lock action. - * @details In this port this function disables interrupts globally. - */ -static inline void port_lock(void) { - - __disable_irq(); -} - -/** - * @brief Kernel-unlock action. - * @details In this port this function enables interrupts globally. - */ -static inline void port_unlock(void) { - - __enable_irq(); -} - -/** - * @brief Kernel-lock action from an interrupt handler. - * @details In this port this function disables interrupts globally. - * @note Same as @p port_lock() in this port. - */ -static inline void port_lock_from_isr(void) { - - port_lock(); -} - -/** - * @brief Kernel-unlock action from an interrupt handler. - * @details In this port this function enables interrupts globally. - * @note Same as @p port_lock() in this port. - */ -static inline void port_unlock_from_isr(void) { - - port_unlock(); -} - -/** - * @brief Disables all the interrupt sources. - */ -static inline void port_disable(void) { - - __disable_irq(); -} - -/** - * @brief Disables the interrupt sources below kernel-level priority. - */ -static inline void port_suspend(void) { - - __disable_irq(); -} - -/** - * @brief Enables all the interrupt sources. - */ -static inline void port_enable(void) { - - __enable_irq(); -} - -/** - * @brief Enters an architecture-dependent IRQ-waiting mode. - * @details The function is meant to return when an interrupt becomes pending. - * The simplest implementation is an empty function or macro but this - * would not take advantage of architecture-specific power saving - * modes. - * @note Implemented as an inlined @p WFI instruction. - */ -static inline void port_wait_for_interrupt(void) { - -#if CORTEX_ENABLE_WFI_IDLE == TRUE - __WFI(); -#endif -} - -#endif /* _FROM_ASM_ */ - -#endif /* _CHCORE_V6M_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/chcore_v7m.c b/firmware/ChibiOS_16/os/rt/ports/ARMCMx/chcore_v7m.c deleted file mode 100644 index a1a6f8e2b3..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/chcore_v7m.c +++ /dev/null @@ -1,168 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chcore_v7m.c - * @brief ARMv7-M architecture port code. - * - * @addtogroup ARMCMx_V7M_CORE - * @{ - */ - -#include "ch.h" - -/*===========================================================================*/ -/* Module local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module interrupt handlers. */ -/*===========================================================================*/ - -#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__) -/** - * @brief SVC vector. - * @details The SVC vector is used for exception mode re-entering after a - * context switch. - * @note The PendSV vector is only used in advanced kernel mode. - */ -/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/ -void SVC_Handler(void) { -/*lint -restore*/ - struct port_extctx *ctxp; - -#if CORTEX_USE_FPU - /* Enforcing unstacking of the FP part of the context.*/ - FPU->FPCCR &= ~FPU_FPCCR_LSPACT_Msk; -#endif - - /* The port_extctx structure is pointed by the PSP register.*/ - ctxp = (struct port_extctx *)__get_PSP(); - - /* Discarding the current exception context and positioning the stack to - point to the real one.*/ - ctxp++; - - /* Restoring real position of the original stack frame.*/ - __set_PSP((uint32_t)ctxp); - - /* Restoring the normal interrupts status.*/ - port_unlock_from_isr(); -} -#endif /* CORTEX_SIMPLIFIED_PRIORITY == FALSE */ - -#if (CORTEX_SIMPLIFIED_PRIORITY == TRUE) || defined(__DOXYGEN__) -/** - * @brief PendSV vector. - * @details The PendSV vector is used for exception mode re-entering after a - * context switch. - * @note The PendSV vector is only used in compact kernel mode. - */ -/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/ -void PendSV_Handler(void) { -/*lint -restore*/ - struct port_extctx *ctxp; - -#if CORTEX_USE_FPU - /* Enforcing unstacking of the FP part of the context.*/ - FPU->FPCCR &= ~FPU_FPCCR_LSPACT_Msk; -#endif - - /* The port_extctx structure is pointed by the PSP register.*/ - ctxp = (struct port_extctx *)__get_PSP(); - - /* Discarding the current exception context and positioning the stack to - point to the real one.*/ - ctxp++; - - /* Writing back the modified PSP value.*/ - __set_PSP((uint32_t)ctxp); -} -#endif /* CORTEX_SIMPLIFIED_PRIORITY == TRUE */ - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -/** - * @brief Exception exit redirection to _port_switch_from_isr(). - */ -void _port_irq_epilogue(void) { - - port_lock_from_isr(); - if ((SCB->ICSR & SCB_ICSR_RETTOBASE_Msk) != 0U) { - struct port_extctx *ctxp; - -#if CORTEX_USE_FPU == TRUE - /* Enforcing a lazy FPU state save by accessing the FPCSR register.*/ - (void) __get_FPSCR(); -#endif - - /* The port_extctx structure is pointed by the PSP register.*/ - ctxp = (struct port_extctx *)__get_PSP(); - - /* Adding an artificial exception return context, there is no need to - populate it fully.*/ - ctxp--; - - /* Setting up a fake XPSR register value.*/ - ctxp->xpsr = (regarm_t)0x01000000; -#if CORTEX_USE_FPU == TRUE - ctxp->fpscr = (regarm_t)FPU->FPDSCR; -#endif - - /* Writing back the modified PSP value.*/ - __set_PSP((uint32_t)ctxp); - - /* The exit sequence is different depending on if a preemption is - required or not.*/ - if (chSchIsPreemptionRequired()) { - /* Preemption is required we need to enforce a context switch.*/ - ctxp->pc = (regarm_t)_port_switch_from_isr; - } - else { - /* Preemption not required, we just need to exit the exception - atomically.*/ - ctxp->pc = (regarm_t)_port_exit_from_isr; - } - - /* Note, returning without unlocking is intentional, this is done in - order to keep the rest of the context switch atomic.*/ - return; - } - port_unlock_from_isr(); -} - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/chcore_v7m.h b/firmware/ChibiOS_16/os/rt/ports/ARMCMx/chcore_v7m.h deleted file mode 100644 index e02183f227..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/chcore_v7m.h +++ /dev/null @@ -1,577 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chcore_v7m.h - * @brief ARMv7-M architecture port macros and structures. - * - * @addtogroup ARMCMx_V7M_CORE - * @{ - */ - -#ifndef _CHCORE_V7M_H_ -#define _CHCORE_V7M_H_ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @brief This port supports a realtime counter. - */ -#define PORT_SUPPORTS_RT TRUE - -/** - * @brief Disabled value for BASEPRI register. - */ -#define CORTEX_BASEPRI_DISABLED 0U - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Stack size for the system idle thread. - * @details This size depends on the idle thread implementation, usually - * the idle thread should take no more space than those reserved - * by @p PORT_INT_REQUIRED_STACK. - * @note In this port it is set to 16 because the idle thread does have - * a stack frame when compiling without optimizations. You may - * reduce this value to zero when compiling with optimizations. - */ -#if !defined(PORT_IDLE_THREAD_STACK_SIZE) || defined(__DOXYGEN__) -#define PORT_IDLE_THREAD_STACK_SIZE 16 -#endif - -/** - * @brief Per-thread stack overhead for interrupts servicing. - * @details This constant is used in the calculation of the correct working - * area size. - * @note In this port this value is conservatively set to 64 because the - * function @p chSchDoReschedule() can have a stack frame, especially - * with compiler optimizations disabled. The value can be reduced - * when compiler optimizations are enabled. - */ -#if !defined(PORT_INT_REQUIRED_STACK) || defined(__DOXYGEN__) -#define PORT_INT_REQUIRED_STACK 64 -#endif - -/** - * @brief Enables the use of the WFI instruction in the idle thread loop. - */ -#if !defined(CORTEX_ENABLE_WFI_IDLE) -#define CORTEX_ENABLE_WFI_IDLE FALSE -#endif - -/** - * @brief FPU support in context switch. - * @details Activating this option activates the FPU support in the kernel. - */ -#if !defined(CORTEX_USE_FPU) -#define CORTEX_USE_FPU CORTEX_HAS_FPU -#elif (CORTEX_USE_FPU == TRUE) && (CORTEX_HAS_FPU == FALSE) -/* This setting requires an FPU presence check in case it is externally - redefined.*/ -#error "the selected core does not have an FPU" -#endif - -/** - * @brief Simplified priority handling flag. - * @details Activating this option makes the Kernel work in compact mode. - * In compact mode interrupts are disabled globally instead of - * raising the priority mask to some intermediate level. - */ -#if !defined(CORTEX_SIMPLIFIED_PRIORITY) -#define CORTEX_SIMPLIFIED_PRIORITY FALSE -#endif - -/** - * @brief SVCALL handler priority. - * @note The default SVCALL handler priority is defaulted to - * @p CORTEX_MAXIMUM_PRIORITY+1, this reserves the - * @p CORTEX_MAXIMUM_PRIORITY priority level as fast interrupts - * priority level. - */ -#if !defined(CORTEX_PRIORITY_SVCALL) -#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1U) -#elif !PORT_IRQ_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL) -/* If it is externally redefined then better perform a validity check on it.*/ -#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL" -#endif - -/** - * @brief NVIC VTOR initialization expression. - */ -#if !defined(CORTEX_VTOR_INIT) || defined(__DOXYGEN__) -#define CORTEX_VTOR_INIT 0x00000000U -#endif - -/** - * @brief NVIC PRIGROUP initialization expression. - * @details The default assigns all available priority bits as preemption - * priority with no sub-priority. - */ -#if !defined(CORTEX_PRIGROUP_INIT) || defined(__DOXYGEN__) -#define CORTEX_PRIGROUP_INIT (7 - CORTEX_PRIORITY_BITS) -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/** - * @name Architecture and Compiler - * @{ - */ -#if (CORTEX_MODEL == 3) || defined(__DOXYGEN__) -/** - * @brief Macro defining the specific ARM architecture. - */ -#define PORT_ARCHITECTURE_ARM_v7M - -/** - * @brief Name of the implemented architecture. - */ -#define PORT_ARCHITECTURE_NAME "ARMv7-M" - -/** - * @brief Name of the architecture variant. - */ -#define PORT_CORE_VARIANT_NAME "Cortex-M3" - -#elif (CORTEX_MODEL == 4) -#define PORT_ARCHITECTURE_ARM_v7ME -#define PORT_ARCHITECTURE_NAME "ARMv7E-M" -#if CORTEX_USE_FPU -#define PORT_CORE_VARIANT_NAME "Cortex-M4F" -#else -#define PORT_CORE_VARIANT_NAME "Cortex-M4" -#endif - -#elif (CORTEX_MODEL == 7) -#define PORT_ARCHITECTURE_ARM_v7ME -#define PORT_ARCHITECTURE_NAME "ARMv7E-M" -#if CORTEX_USE_FPU -#define PORT_CORE_VARIANT_NAME "Cortex-M7F" -#else -#define PORT_CORE_VARIANT_NAME "Cortex-M7" -#endif -#endif - -/** - * @brief Port-specific information string. - */ -#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__) -#define PORT_INFO "Advanced kernel mode" -#else -#define PORT_INFO "Compact kernel mode" -#endif -/** @} */ - -#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__) -/** - * @brief Maximum usable priority for normal ISRs. - */ -#define CORTEX_MAX_KERNEL_PRIORITY (CORTEX_PRIORITY_SVCALL + 1U) - -/** - * @brief BASEPRI level within kernel lock. - */ -#define CORTEX_BASEPRI_KERNEL \ - CORTEX_PRIO_MASK(CORTEX_MAX_KERNEL_PRIORITY) -#else - -#define CORTEX_MAX_KERNEL_PRIORITY 0U -#endif - -/** - * @brief PendSV priority level. - * @note This priority is enforced to be equal to - * @p CORTEX_MAX_KERNEL_PRIORITY, this handler always have the - * highest priority that cannot preempt the kernel. - */ -#define CORTEX_PRIORITY_PENDSV CORTEX_MAX_KERNEL_PRIORITY - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/* The following code is not processed when the file is included from an - asm module.*/ -#if !defined(_FROM_ASM_) - -/* The documentation of the following declarations is in chconf.h in order - to not have duplicated structure names into the documentation.*/ -#if !defined(__DOXYGEN__) -struct port_extctx { - regarm_t r0; - regarm_t r1; - regarm_t r2; - regarm_t r3; - regarm_t r12; - regarm_t lr_thd; - regarm_t pc; - regarm_t xpsr; -#if CORTEX_USE_FPU - regarm_t s0; - regarm_t s1; - regarm_t s2; - regarm_t s3; - regarm_t s4; - regarm_t s5; - regarm_t s6; - regarm_t s7; - regarm_t s8; - regarm_t s9; - regarm_t s10; - regarm_t s11; - regarm_t s12; - regarm_t s13; - regarm_t s14; - regarm_t s15; - regarm_t fpscr; - regarm_t reserved; -#endif /* CORTEX_USE_FPU */ -}; - -struct port_intctx { -#if CORTEX_USE_FPU - regarm_t s16; - regarm_t s17; - regarm_t s18; - regarm_t s19; - regarm_t s20; - regarm_t s21; - regarm_t s22; - regarm_t s23; - regarm_t s24; - regarm_t s25; - regarm_t s26; - regarm_t s27; - regarm_t s28; - regarm_t s29; - regarm_t s30; - regarm_t s31; -#endif /* CORTEX_USE_FPU */ - regarm_t r4; - regarm_t r5; - regarm_t r6; - regarm_t r7; - regarm_t r8; - regarm_t r9; - regarm_t r10; - regarm_t r11; - regarm_t lr; -}; -#endif /* !defined(__DOXYGEN__) */ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @brief Platform dependent part of the @p chThdCreateI() API. - * @details This code usually setup the context switching frame represented - * by an @p port_intctx structure. - */ -#define PORT_SETUP_CONTEXT(tp, workspace, wsize, pf, arg) { \ - (tp)->p_ctx.r13 = (struct port_intctx *)((uint8_t *)(workspace) + \ - (size_t)(wsize) - \ - sizeof(struct port_intctx)); \ - (tp)->p_ctx.r13->r4 = (regarm_t)(pf); \ - (tp)->p_ctx.r13->r5 = (regarm_t)(arg); \ - (tp)->p_ctx.r13->lr = (regarm_t)_port_thread_start; \ -} - -/** - * @brief Computes the thread working area global size. - * @note There is no need to perform alignments in this macro. - */ -#define PORT_WA_SIZE(n) (sizeof(struct port_intctx) + \ - sizeof(struct port_extctx) + \ - ((size_t)(n)) + ((size_t)(PORT_INT_REQUIRED_STACK))) - -/** - * @brief IRQ prologue code. - * @details This macro must be inserted at the start of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_PROLOGUE() - -/** - * @brief IRQ epilogue code. - * @details This macro must be inserted at the end of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_EPILOGUE() _port_irq_epilogue() - -/** - * @brief IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_IRQ_HANDLER(id) void id(void) - -/** - * @brief Fast IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_FAST_IRQ_HANDLER(id) void id(void) - -/** - * @brief Performs a context switch between two threads. - * @details This is the most critical code in any port, this function - * is responsible for the context switch between 2 threads. - * @note The implementation of this code affects directly the context - * switch performance so optimize here as much as you can. - * - * @param[in] ntp the thread to be switched in - * @param[in] otp the thread to be switched out - */ -#if (CH_DBG_ENABLE_STACK_CHECK == FALSE) || defined(__DOXYGEN__) -#define port_switch(ntp, otp) _port_switch(ntp, otp) -#else -#define port_switch(ntp, otp) { \ - struct port_intctx *r13 = (struct port_intctx *)__get_PSP(); \ - if ((stkalign_t *)(r13 - 1) < (otp)->p_stklimit) { \ - chSysHalt("stack overflow"); \ - } \ - _port_switch(ntp, otp); \ -} -#endif - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void _port_irq_epilogue(void); - void _port_switch(thread_t *ntp, thread_t *otp); - void _port_thread_start(void); - void _port_switch_from_isr(void); - void _port_exit_from_isr(void); -#ifdef __cplusplus -} -#endif - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -/** - * @brief Port-related initialization code. - */ -static inline void port_init(void) { - - /* Initialization of the vector table and priority related settings.*/ - SCB->VTOR = CORTEX_VTOR_INIT; - - /* Initializing priority grouping.*/ - NVIC_SetPriorityGrouping(CORTEX_PRIGROUP_INIT); - - /* DWT cycle counter enable, note, the M7 requires DWT unlocking.*/ - CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; -#if CORTEX_MODEL == 7 - DWT->LAR = 0xC5ACCE55U; -#endif - DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; - - /* Initialization of the system vectors used by the port.*/ -#if CORTEX_SIMPLIFIED_PRIORITY == FALSE - NVIC_SetPriority(SVCall_IRQn, CORTEX_PRIORITY_SVCALL); -#endif - NVIC_SetPriority(PendSV_IRQn, CORTEX_PRIORITY_PENDSV); -} - -/** - * @brief Returns a word encoding the current interrupts status. - * - * @return The interrupts status. - */ -static inline syssts_t port_get_irq_status(void) { - syssts_t sts; - -#if CORTEX_SIMPLIFIED_PRIORITY == FALSE - sts = (syssts_t)__get_BASEPRI(); -#else /* CORTEX_SIMPLIFIED_PRIORITY */ - sts = (syssts_t)__get_PRIMASK(); -#endif /* CORTEX_SIMPLIFIED_PRIORITY */ - return sts; -} - -/** - * @brief Checks the interrupt status. - * - * @param[in] sts the interrupt status word - * - * @return The interrupt status. - * @retvel false the word specified a disabled interrupts status. - * @retvel true the word specified an enabled interrupts status. - */ -static inline bool port_irq_enabled(syssts_t sts) { - -#if CORTEX_SIMPLIFIED_PRIORITY == FALSE - return sts == (syssts_t)CORTEX_BASEPRI_DISABLED; -#else /* CORTEX_SIMPLIFIED_PRIORITY */ - return (sts & (syssts_t)1) == (syssts_t)0; -#endif /* CORTEX_SIMPLIFIED_PRIORITY */ -} - -/** - * @brief Determines the current execution context. - * - * @return The execution context. - * @retval false not running in ISR mode. - * @retval true running in ISR mode. - */ -static inline bool port_is_isr_context(void) { - - return (bool)((__get_IPSR() & 0x1FFU) != 0U); -} - -/** - * @brief Kernel-lock action. - * @details In this port this function raises the base priority to kernel - * level. - */ -static inline void port_lock(void) { - -#if CORTEX_SIMPLIFIED_PRIORITY == FALSE -#if defined(__CM7_REV) -#if __CM7_REV <= 1 - __disable_irq(); -#endif -#endif - __set_BASEPRI(CORTEX_BASEPRI_KERNEL); -#if defined(__CM7_REV) -#if __CM7_REV <= 1 - __enable_irq(); -#endif -#endif -#else /* CORTEX_SIMPLIFIED_PRIORITY */ - __disable_irq(); -#endif /* CORTEX_SIMPLIFIED_PRIORITY */ -} - -/** - * @brief Kernel-unlock action. - * @details In this port this function lowers the base priority to user - * level. - */ -static inline void port_unlock(void) { - -#if CORTEX_SIMPLIFIED_PRIORITY == FALSE - __set_BASEPRI(CORTEX_BASEPRI_DISABLED); -#else /* CORTEX_SIMPLIFIED_PRIORITY */ - __enable_irq(); -#endif /* CORTEX_SIMPLIFIED_PRIORITY */ -} - -/** - * @brief Kernel-lock action from an interrupt handler. - * @details In this port this function raises the base priority to kernel - * level. - * @note Same as @p port_lock() in this port. - */ -static inline void port_lock_from_isr(void) { - - port_lock(); -} - -/** - * @brief Kernel-unlock action from an interrupt handler. - * @details In this port this function lowers the base priority to user - * level. - * @note Same as @p port_unlock() in this port. - */ -static inline void port_unlock_from_isr(void) { - - port_unlock(); -} - -/** - * @brief Disables all the interrupt sources. - * @note In this port it disables all the interrupt sources by raising - * the priority mask to level 0. - */ -static inline void port_disable(void) { - - __disable_irq(); -} - -/** - * @brief Disables the interrupt sources below kernel-level priority. - * @note Interrupt sources above kernel level remains enabled. - * @note In this port it raises/lowers the base priority to kernel level. - */ -static inline void port_suspend(void) { - -#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__) - __set_BASEPRI(CORTEX_BASEPRI_KERNEL); - __enable_irq(); -#else - __disable_irq(); -#endif -} - -/** - * @brief Enables all the interrupt sources. - * @note In this port it lowers the base priority to user level. - */ -static inline void port_enable(void) { - -#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__) - __set_BASEPRI(CORTEX_BASEPRI_DISABLED); -#endif - __enable_irq(); -} - -/** - * @brief Enters an architecture-dependent IRQ-waiting mode. - * @details The function is meant to return when an interrupt becomes pending. - * The simplest implementation is an empty function or macro but this - * would not take advantage of architecture-specific power saving - * modes. - * @note Implemented as an inlined @p WFI instruction. - */ -static inline void port_wait_for_interrupt(void) { - -#if CORTEX_ENABLE_WFI_IDLE == TRUE - __WFI(); -#endif -} - -/** - * @brief Returns the current value of the realtime counter. - * - * @return The realtime counter value. - */ -static inline rtcnt_t port_rt_get_counter_value(void) { - - return DWT->CYCCNT; -} - -#endif /* !defined(_FROM_ASM_) */ - -#endif /* _CHCORE_V7M_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/cmsis_os/cmsis_os.c b/firmware/ChibiOS_16/os/rt/ports/ARMCMx/cmsis_os/cmsis_os.c deleted file mode 100644 index 285611718c..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/cmsis_os/cmsis_os.c +++ /dev/null @@ -1,554 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ -/* - Concepts and parts of this file have been contributed by Andre R. - */ - -/** - * @file cmsis_os.c - * @brief CMSIS RTOS module code. - * - * @addtogroup CMSIS_OS - * @{ - */ - -#include "cmsis_os.h" -#include - -/*===========================================================================*/ -/* Module local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -int32_t cmsis_os_started; - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -static memory_pool_t sempool; -static semaphore_t semaphores[CMSIS_CFG_NUM_SEMAPHORES]; - -static memory_pool_t timpool; -static struct os_timer_cb timers[CMSIS_CFG_NUM_TIMERS]; - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -/** - * @brief Virtual timers common callback. - */ -static void timer_cb(void const *arg) { - - osTimerId timer_id = (osTimerId)arg; - timer_id->ptimer(timer_id->argument); - if (timer_id->type == osTimerPeriodic) { - chSysLockFromISR(); - chVTDoSetI(&timer_id->vt, MS2ST(timer_id->millisec), - (vtfunc_t)timer_cb, timer_id); - chSysUnlockFromISR(); - } -} - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -/** - * @brief Kernel initialization. - */ -osStatus osKernelInitialize(void) { - - cmsis_os_started = 0; - - chSysInit(); - chThdSetPriority(HIGHPRIO); - - chPoolObjectInit(&sempool, sizeof(semaphore_t), chCoreAlloc); - chPoolLoadArray(&sempool, semaphores, CMSIS_CFG_NUM_SEMAPHORES); - - chPoolObjectInit(&timpool, sizeof(virtual_timer_t), chCoreAlloc); - chPoolLoadArray(&timpool, timers, CMSIS_CFG_NUM_TIMERS); - - return osOK; -} - -/** - * @brief Kernel start. - */ -osStatus osKernelStart(void) { - - cmsis_os_started = 1; - - chThdSetPriority(NORMALPRIO); - - return osOK; -} - -/** - * @brief Creates a thread. - */ -osThreadId osThreadCreate(const osThreadDef_t *thread_def, void *argument) { - size_t size; - - size = thread_def->stacksize == 0 ? CMSIS_CFG_DEFAULT_STACK : - thread_def->stacksize; - return (osThreadId)chThdCreateFromHeap(0, - THD_WORKING_AREA_SIZE(size), - NORMALPRIO+thread_def->tpriority, - (tfunc_t)thread_def->pthread, - argument); -} - -/** - * @brief Thread termination. - * @note The thread is not really terminated but asked to terminate which - * is not compliant. - */ -osStatus osThreadTerminate(osThreadId thread_id) { - - if (thread_id == osThreadGetId()) { - /* Note, no memory will be recovered unless a cleaner thread is - implemented using the registry.*/ - chThdExit(0); - } - chThdTerminate(thread_id); - chThdWait((thread_t *)thread_id); - - return osOK; -} - -/** - * @brief Change thread priority. - * @note This can interfere with the priority inheritance mechanism. - */ -osStatus osThreadSetPriority(osThreadId thread_id, osPriority newprio) { - osPriority oldprio; - thread_t * tp = (thread_t *)thread_id; - - chSysLock(); - - /* Changing priority.*/ -#if CH_CFG_USE_MUTEXES - oldprio = (osPriority)tp->p_realprio; - if ((tp->p_prio == tp->p_realprio) || ((tprio_t)newprio > tp->p_prio)) - tp->p_prio = (tprio_t)newprio; - tp->p_realprio = (tprio_t)newprio; -#else - oldprio = tp->p_prio; - tp->p_prio = (tprio_t)newprio; -#endif - - /* The following states need priority queues reordering.*/ - switch (tp->p_state) { -#if CH_CFG_USE_MUTEXES | \ - CH_CFG_USE_CONDVARS | \ - (CH_CFG_USE_SEMAPHORES && CH_CFG_USE_SEMAPHORES_PRIORITY) | \ - (CH_CFG_USE_MESSAGES && CH_CFG_USE_MESSAGES_PRIORITY) -#if CH_CFG_USE_MUTEXES - case CH_STATE_WTMTX: -#endif -#if CH_CFG_USE_CONDVARS - case CH_STATE_WTCOND: -#endif -#if CH_CFG_USE_SEMAPHORES && CH_CFG_USE_SEMAPHORES_PRIORITY - case CH_STATE_WTSEM: -#endif -#if CH_CFG_USE_MESSAGES && CH_CFG_USE_MESSAGES_PRIORITY - case CH_STATE_SNDMSGQ: -#endif - /* Re-enqueues tp with its new priority on the queue.*/ - queue_prio_insert(queue_dequeue(tp), - (threads_queue_t *)tp->p_u.wtobjp); - break; -#endif - case CH_STATE_READY: -#if CH_DBG_ENABLE_ASSERTS - /* Prevents an assertion in chSchReadyI().*/ - tp->p_state = CH_STATE_CURRENT; -#endif - /* Re-enqueues tp with its new priority on the ready list.*/ - chSchReadyI(queue_dequeue(tp)); - break; - } - - /* Rescheduling.*/ - chSchRescheduleS(); - - chSysUnlock(); - - return oldprio; -} - -/** - * @brief Create a timer. - */ -osTimerId osTimerCreate(const osTimerDef_t *timer_def, - os_timer_type type, - void *argument) { - - osTimerId timer = chPoolAlloc(&timpool); - chVTObjectInit(&timer->vt); - timer->ptimer = timer_def->ptimer; - timer->type = type; - timer->argument = argument; - return timer; -} - -/** - * @brief Start a timer. - */ -osStatus osTimerStart(osTimerId timer_id, uint32_t millisec) { - - if ((millisec == 0) || (millisec == osWaitForever)) - return osErrorValue; - - timer_id->millisec = millisec; - chVTSet(&timer_id->vt, MS2ST(millisec), (vtfunc_t)timer_cb, timer_id); - - return osOK; -} - -/** - * @brief Stop a timer. - */ -osStatus osTimerStop(osTimerId timer_id) { - - chVTReset(&timer_id->vt); - - return osOK; -} - -/** - * @brief Delete a timer. - */ -osStatus osTimerDelete(osTimerId timer_id) { - - chVTReset(&timer_id->vt); - chPoolFree(&timpool, (void *)timer_id); - - return osOK; -} - -/** - * @brief Send signals. - */ -int32_t osSignalSet(osThreadId thread_id, int32_t signals) { - int32_t oldsignals; - - syssts_t sts = chSysGetStatusAndLockX(); - oldsignals = (int32_t)thread_id->p_epending; - chEvtSignalI((thread_t *)thread_id, (eventmask_t)signals); - chSysRestoreStatusX(sts); - - return oldsignals; -} - -/** - * @brief Clear signals. - */ -int32_t osSignalClear(osThreadId thread_id, int32_t signals) { - eventmask_t m; - - chSysLock(); - - m = thread_id->p_epending & (eventmask_t)signals; - thread_id->p_epending &= ~(eventmask_t)signals; - - chSysUnlock(); - - return (int32_t)m; -} - -/** - * @brief Wait for signals. - */ -osEvent osSignalWait(int32_t signals, uint32_t millisec) { - osEvent event; - systime_t timeout = ((millisec == 0) || (millisec == osWaitForever)) ? - TIME_INFINITE : MS2ST(millisec); - - if (signals == 0) - event.value.signals = (uint32_t)chEvtWaitAnyTimeout(ALL_EVENTS, timeout); - else - event.value.signals = (uint32_t)chEvtWaitAllTimeout((eventmask_t)signals, - timeout); - - /* Type of event.*/ - if (event.value.signals == 0) - event.status = osEventTimeout; - else - event.status = osEventSignal; - - return event; -} - -/** - * @brief Create a semaphore. - * @note @p semaphore_def is not used. - * @note Can involve memory allocation. - */ -osSemaphoreId osSemaphoreCreate(const osSemaphoreDef_t *semaphore_def, - int32_t count) { - - (void)semaphore_def; - - semaphore_t *sem = chPoolAlloc(&sempool); - chSemObjectInit(sem, (cnt_t)count); - return sem; -} - -/** - * @brief Wait on a semaphore. - */ -int32_t osSemaphoreWait(osSemaphoreId semaphore_id, uint32_t millisec) { - systime_t timeout = ((millisec == 0) || (millisec == osWaitForever)) ? - TIME_INFINITE : MS2ST(millisec); - - msg_t msg = chSemWaitTimeout((semaphore_t *)semaphore_id, timeout); - switch (msg) { - case MSG_OK: - return osOK; - case MSG_TIMEOUT: - return osErrorTimeoutResource; - } - return osErrorResource; -} - -/** - * @brief Release a semaphore. - */ -osStatus osSemaphoreRelease(osSemaphoreId semaphore_id) { - - syssts_t sts = chSysGetStatusAndLockX(); - chSemSignalI((semaphore_t *)semaphore_id); - chSysRestoreStatusX(sts); - - return osOK; -} - -/** - * @brief Deletes a semaphore. - * @note After deletion there could be references in the system to a - * non-existent semaphore. - */ -osStatus osSemaphoreDelete(osSemaphoreId semaphore_id) { - - chSemReset((semaphore_t *)semaphore_id, 0); - chPoolFree(&sempool, (void *)semaphore_id); - - return osOK; -} - -/** - * @brief Create a mutex. - * @note @p mutex_def is not used. - * @note Can involve memory allocation. - */ -osMutexId osMutexCreate(const osMutexDef_t *mutex_def) { - - (void)mutex_def; - - binary_semaphore_t *mtx = chPoolAlloc(&sempool); - chBSemObjectInit(mtx, false); - return mtx; -} - -/** - * @brief Wait on a mutex. - */ -osStatus osMutexWait(osMutexId mutex_id, uint32_t millisec) { - systime_t timeout = ((millisec == 0) || (millisec == osWaitForever)) ? - TIME_INFINITE : MS2ST(millisec); - - msg_t msg = chBSemWaitTimeout((binary_semaphore_t *)mutex_id, timeout); - switch (msg) { - case MSG_OK: - return osOK; - case MSG_TIMEOUT: - return osErrorTimeoutResource; - } - return osErrorResource; -} - -/** - * @brief Release a mutex. - */ -osStatus osMutexRelease(osMutexId mutex_id) { - - syssts_t sts = chSysGetStatusAndLockX(); - chBSemSignalI((binary_semaphore_t *)mutex_id); - chSysRestoreStatusX(sts); - - return osOK; -} - -/** - * @brief Deletes a mutex. - * @note After deletion there could be references in the system to a - * non-existent semaphore. - */ -osStatus osMutexDelete(osMutexId mutex_id) { - - chSemReset((semaphore_t *)mutex_id, 0); - chPoolFree(&sempool, (void *)mutex_id); - - return osOK; -} - -/** - * @brief Create a memory pool. - * @note The pool is not really created because it is allocated statically, - * this function just re-initializes it. - */ -osPoolId osPoolCreate(const osPoolDef_t *pool_def) { - - chPoolObjectInit(pool_def->pool, (size_t)pool_def->item_sz, NULL); - chPoolLoadArray(pool_def->pool, pool_def->items, (size_t)pool_def->pool_sz); - - return (osPoolId)pool_def->pool; -} - -/** - * @brief Allocate an object. - */ -void *osPoolAlloc(osPoolId pool_id) { - void *object; - - syssts_t sts = chSysGetStatusAndLockX(); - object = chPoolAllocI((memory_pool_t *)pool_id); - chSysRestoreStatusX(sts); - - return object; -} - -/** - * @brief Allocate an object clearing it. - */ -void *osPoolCAlloc(osPoolId pool_id) { - void *object; - - object = chPoolAllocI((memory_pool_t *)pool_id); - memset(object, 0, pool_id->mp_object_size); - return object; -} - -/** - * @brief Free an object. - */ -osStatus osPoolFree(osPoolId pool_id, void *block) { - - syssts_t sts = chSysGetStatusAndLockX(); - chPoolFreeI((memory_pool_t *)pool_id, block); - chSysRestoreStatusX(sts); - - return osOK; -} - -/** - * @brief Create a message queue. - * @note The queue is not really created because it is allocated statically, - * this function just re-initializes it. - */ -osMessageQId osMessageCreate(const osMessageQDef_t *queue_def, - osThreadId thread_id) { - - /* Ignoring this parameter for now.*/ - (void)thread_id; - - if (queue_def->item_sz > sizeof (msg_t)) - return NULL; - - chMBObjectInit(queue_def->mailbox, - queue_def->items, - (size_t)queue_def->queue_sz); - - return (osMessageQId) queue_def->mailbox; -} - -/** - * @brief Put a message in the queue. - */ -osStatus osMessagePut(osMessageQId queue_id, - uint32_t info, - uint32_t millisec) { - msg_t msg; - systime_t timeout = ((millisec == 0) || (millisec == osWaitForever)) ? - TIME_INFINITE : MS2ST(millisec); - - if (port_is_isr_context()) { - - /* Waiting makes no sense in ISRs so any value except "immediate" - makes no sense.*/ - if (millisec != 0) - return osErrorValue; - - chSysLockFromISR(); - msg = chMBPostI((mailbox_t *)queue_id, (msg_t)info); - chSysUnlockFromISR(); - } - else - msg = chMBPost((mailbox_t *)queue_id, (msg_t)info, timeout); - - return msg == MSG_OK ? osOK : osEventTimeout; -} - -/** - * @brief Get a message from the queue. - */ -osEvent osMessageGet(osMessageQId queue_id, - uint32_t millisec) { - msg_t msg; - osEvent event; - systime_t timeout = ((millisec == 0) || (millisec == osWaitForever)) ? - TIME_INFINITE : MS2ST(millisec); - - event.def.message_id = queue_id; - - if (port_is_isr_context()) { - - /* Waiting makes no sense in ISRs so any value except "immediate" - makes no sense.*/ - if (millisec != 0) { - event.status = osErrorValue; - return event; - } - - chSysLockFromISR(); - msg = chMBFetchI((mailbox_t *)queue_id, (msg_t*)&event.value.v); - chSysUnlockFromISR(); - } - else { - msg = chMBFetch((mailbox_t *)queue_id, (msg_t*)&event.value.v, timeout); - } - - /* Returned event type.*/ - event.status = msg == MSG_OK ? osEventMessage : osEventTimeout; - return event; -} - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/cmsis_os/cmsis_os.h b/firmware/ChibiOS_16/os/rt/ports/ARMCMx/cmsis_os/cmsis_os.h deleted file mode 100644 index 0512be3b62..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/cmsis_os/cmsis_os.h +++ /dev/null @@ -1,520 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ -/* - Concepts and parts of this file have been contributed by Andre R. - */ - -/** - * @file cmsis_os.h - * @brief CMSIS RTOS module macros and structures. - * - * @addtogroup CMSIS_OS - * @{ - */ - -#ifndef _CMSIS_OS_H_ -#define _CMSIS_OS_H_ - -#include "ch.h" - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @brief API version. - */ -#define osCMSIS 0x10002 - -/** - * @brief Kernel version. - */ -#define osKernelSystemId "KERNEL V1.00" - -/** - * @brief ChibiOS/RT version encoded for CMSIS. - */ -#define osCMSIS_KERNEL ((CH_KERNEL_MAJOR << 16) | \ - (CH_KERNEL_MINOR << 8) | \ - (CH_KERNEL_PATCH)) - -/** - * @name CMSIS Capabilities - * @{ - */ -#define osFeature_MainThread 1 -#define osFeature_Pool 1 -#define osFeature_MailQ 0 -#define osFeature_MessageQ 1 -#define osFeature_Signals 24 -#define osFeature_Semaphore ((1U << 31) - 1U) -#define osFeature_Wait 0 -#define osFeature_SysTick 1 -/**< @} */ - -/** - * @brief Wait forever specification for timeouts. - */ -#define osWaitForever TIME_INFINITE - -/** - * @brief System tick frequency. - */ -#define osKernelSysTickFrequency CH_CFG_ST_FREQUENCY - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Number of pre-allocated static semaphores/mutexes. - */ -#if !defined(CMSIS_CFG_DEFAULT_STACK) -#define CMSIS_CFG_DEFAULT_STACK 256 -#endif - -/** - * @brief Number of pre-allocated static semaphores/mutexes. - */ -#if !defined(CMSIS_CFG_NUM_SEMAPHORES) -#define CMSIS_CFG_NUM_SEMAPHORES 4 -#endif - -/** - * @brief Number of pre-allocated static timers. - */ -#if !defined(CMSIS_CFG_NUM_TIMERS) -#define CMSIS_CFG_NUM_TIMERS 4 -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !CH_CFG_USE_MEMPOOLS -#error "CMSIS RTOS requires CH_CFG_USE_MEMPOOLS" -#endif - -#if !CH_CFG_USE_EVENTS -#error "CMSIS RTOS requires CH_CFG_USE_EVENTS" -#endif - -#if !CH_CFG_USE_EVENTS_TIMEOUT -#error "CMSIS RTOS requires CH_CFG_USE_EVENTS_TIMEOUT" -#endif - -#if !CH_CFG_USE_SEMAPHORES -#error "CMSIS RTOS requires CH_CFG_USE_SEMAPHORES" -#endif - -#if !CH_CFG_USE_DYNAMIC -#error "CMSIS RTOS requires CH_CFG_USE_DYNAMIC" -#endif - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of priority levels. - */ -typedef enum { - osPriorityIdle = -3, - osPriorityLow = -2, - osPriorityBelowNormal = -1, - osPriorityNormal = 0, - osPriorityAboveNormal = +1, - osPriorityHigh = +2, - osPriorityRealtime = +3, - osPriorityError = 0x84 -} osPriority; - -/** - * @brief Type of error codes. - */ -typedef enum { - osOK = 0, - osEventSignal = 0x08, - osEventMessage = 0x10, - osEventMail = 0x20, - osEventTimeout = 0x40, - osErrorParameter = 0x80, - osErrorResource = 0x81, - osErrorTimeoutResource = 0xC1, - osErrorISR = 0x82, - osErrorISRRecursive = 0x83, - osErrorPriority = 0x84, - osErrorNoMemory = 0x85, - osErrorValue = 0x86, - osErrorOS = 0xFF, - os_status_reserved = 0x7FFFFFFF -} osStatus; - -/** - * @brief Type of a timer mode. - */ -typedef enum { - osTimerOnce = 0, - osTimerPeriodic = 1 -} os_timer_type; - -/** - * @brief Type of thread functions. - */ -typedef void (*os_pthread) (void const *argument); - -/** - * @brief Type of timer callback. - */ -typedef void (*os_ptimer) (void const *argument); - -/** - * @brief Type of pointer to thread control block. - */ -typedef thread_t *osThreadId; - -/** - * @brief Type of pointer to timer control block. - */ -typedef struct os_timer_cb { - virtual_timer_t vt; - os_timer_type type; - os_ptimer ptimer; - void *argument; - uint32_t millisec; -} *osTimerId; - -/** - * @brief Type of pointer to mutex control block. - */ -typedef binary_semaphore_t *osMutexId; - -/** - * @brief Type of pointer to semaphore control block. - */ -typedef semaphore_t *osSemaphoreId; - -/** - * @brief Type of pointer to memory pool control block. - */ -typedef memory_pool_t *osPoolId; - -/** - * @brief Type of pointer to message queue control block. - */ -typedef struct mailbox *osMessageQId; - -/** - * @brief Type of an event. - */ -typedef struct { - osStatus status; - union { - uint32_t v; - void *p; - int32_t signals; - } value; - union { -/* osMailQId mail_id;*/ - osMessageQId message_id; - } def; -} osEvent; - -/** - * @brief Type of a thread definition block. - */ -typedef struct os_thread_def { - os_pthread pthread; - osPriority tpriority; - uint32_t stacksize; -} osThreadDef_t; - -/** - * @brief Type of a timer definition block. - */ -typedef struct os_timer_def { - os_ptimer ptimer; -} osTimerDef_t; - -/** - * @brief Type of a mutex definition block. - */ -typedef struct os_mutex_def { - uint32_t dummy; -} osMutexDef_t; - -/** - * @brief Type of a semaphore definition block. - */ -typedef struct os_semaphore_def { - uint32_t dummy; -} osSemaphoreDef_t; - -/** - * @brief Type of a memory pool definition block. - */ -typedef struct os_pool_def { - uint32_t pool_sz; - uint32_t item_sz; - memory_pool_t *pool; - void *items; -} osPoolDef_t; - -/** - * @brief Type of a message queue definition block. - */ -typedef struct os_messageQ_def { - uint32_t queue_sz; - uint32_t item_sz; - mailbox_t *mailbox; - void *items; -} osMessageQDef_t; - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @brief Convert a microseconds value to a RTOS kernel system timer value. - */ -#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * \ - (osKernelSysTickFrequency)) / \ - 1000000) - -/** - * @brief Create a Thread definition. - */ -#if defined(osObjectsExternal) -#define osThreadDef(name, priority, instances, stacksz) \ - extern const osThreadDef_t os_thread_def_##name -#else -#define osThreadDef(name, priority, stacksz) \ -const osThreadDef_t os_thread_def_##name = { \ - (name), \ - (priority), \ - (stacksz) \ -} -#endif - -/** - * @brief Access a Thread definition. - */ -#define osThread(name) &os_thread_def_##name - -/** - * @brief Define a Timer object. - */ -#if defined(osObjectsExternal) -#define osTimerDef(name, function) \ - extern const osTimerDef_t os_timer_def_##name -#else -#define osTimerDef(name, function) \ -const osTimerDef_t os_timer_def_##name = { \ - (function) \ -} -#endif - -/** - * @brief Access a Timer definition. - */ -#define osTimer(name) &os_timer_def_##name - -/** - * @brief Define a Mutex. - */ -#if defined(osObjectsExternal) -#define osMutexDef(name) extern const osMutexDef_t os_mutex_def_##name -#else -#define osMutexDef(name) const osMutexDef_t os_mutex_def_##name = {0} -#endif - -/** - * @brief Access a Mutex definition. - */ -#define osMutex(name) &os_mutex_def_##name - -/** - * @brief Define a Semaphore. - */ -#if defined(osObjectsExternal) -#define osSemaphoreDef(name) \ - extern const osSemaphoreDef_t os_semaphore_def_##name -#else // define the object -#define osSemaphoreDef(name) \ - const osSemaphoreDef_t os_semaphore_def_##name = {0} -#endif - -/** - * @brief Access a Semaphore definition. - */ -#define osSemaphore(name) &os_semaphore_def_##name - -/** - * @brief Define a Memory Pool. - */ -#if defined(osObjectsExternal) -#define osPoolDef(name, no, type) \ - extern const osPoolDef_t os_pool_def_##name -#else -#define osPoolDef(name, no, type) \ -static const type os_pool_buf_##name[no]; \ -static memory_pool_t os_pool_obj_##name; \ -const osPoolDef_t os_pool_def_##name = { \ - (no), \ - sizeof (type), \ - (void *)&os_pool_obj_##name, \ - (void *)&os_pool_buf_##name[0] \ -} -#endif - -/** - * @brief Access a Memory Pool definition. - */ -#define osPool(name) &os_pool_def_##name - -/** - * @brief Define a Message Queue. - */ -#if defined(osObjectsExternal) -#define osMessageQDef(name, queue_sz, type) \ - extern const osMessageQDef_t os_messageQ_def_##name -#else -#define osMessageQDef(name, queue_sz, type) \ -static const msg_t os_messageQ_buf_##name[queue_sz]; \ -static mailbox_t os_messageQ_obj_##name; \ -const osMessageQDef_t os_messageQ_def_##name = { \ - (queue_sz), \ - sizeof (type), \ - (void *)&os_messageQ_obj_##name, \ - (void *)&os_messageQ_buf_##name[0] \ -} -#endif - -/** - * @brief Access a Message Queue definition. - */ -#define osMessageQ(name) &os_messageQ_def_##name - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -extern int32_t cmsis_os_started; - -#ifdef __cplusplus -extern "C" { -#endif - osStatus osKernelInitialize(void); - osStatus osKernelStart(void); - osThreadId osThreadCreate(const osThreadDef_t *thread_def, void *argument); - osStatus osThreadTerminate(osThreadId thread_id); - osStatus osThreadSetPriority(osThreadId thread_id, osPriority newprio); - /*osEvent osWait(uint32_t millisec);*/ - osTimerId osTimerCreate(const osTimerDef_t *timer_def, - os_timer_type type, - void *argument); - osStatus osTimerStart(osTimerId timer_id, uint32_t millisec); - osStatus osTimerStop(osTimerId timer_id); - osStatus osTimerDelete(osTimerId timer_id); - int32_t osSignalSet(osThreadId thread_id, int32_t signals); - int32_t osSignalClear(osThreadId thread_id, int32_t signals); - osEvent osSignalWait(int32_t signals, uint32_t millisec); - osSemaphoreId osSemaphoreCreate(const osSemaphoreDef_t *semaphore_def, - int32_t count); - int32_t osSemaphoreWait(osSemaphoreId semaphore_id, uint32_t millisec); - osStatus osSemaphoreRelease(osSemaphoreId semaphore_id); - osStatus osSemaphoreDelete(osSemaphoreId semaphore_id); - osMutexId osMutexCreate(const osMutexDef_t *mutex_def); - osStatus osMutexWait(osMutexId mutex_id, uint32_t millisec); - osStatus osMutexRelease(osMutexId mutex_id); - osStatus osMutexDelete(osMutexId mutex_id); - osPoolId osPoolCreate(const osPoolDef_t *pool_def); - void *osPoolAlloc(osPoolId pool_id); - void *osPoolCAlloc(osPoolId pool_id); - osStatus osPoolFree(osPoolId pool_id, void *block); - osMessageQId osMessageCreate(const osMessageQDef_t *queue_def, - osThreadId thread_id); - osStatus osMessagePut(osMessageQId queue_id, - uint32_t info, - uint32_t millisec); - osEvent osMessageGet(osMessageQId queue_id, - uint32_t millisec); -#ifdef __cplusplus -} -#endif - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -/** - * @brief To be or not to be. - */ -static inline int32_t osKernelRunning(void) { - - return cmsis_os_started; -} - -/** - * @brief System ticks since start. - */ -static inline uint32_t osKernelSysTick(void) { - - return (uint32_t)chVTGetSystemTimeX(); -} - -/** - * @brief Returns the current thread. - */ -static inline osThreadId osThreadGetId(void) { - - return (osThreadId)chThdGetSelfX(); -} - -/** - * @brief Thread time slice yield. - */ -static inline osStatus osThreadYield(void) { - - chThdYield(); - - return osOK; -} - -/** - * @brief Returns priority of a thread. - */ -static inline osPriority osThreadGetPriority(osThreadId thread_id) { - - return (osPriority)(NORMALPRIO - thread_id->p_prio); -} - -/** - * @brief Thread delay in milliseconds. - */ -static inline osStatus osDelay(uint32_t millisec) { - - chThdSleepMilliseconds(millisec); - - return osOK; -} - -#endif /* _CMSIS_OS_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/cmsis_os/cmsis_os.mk b/firmware/ChibiOS_16/os/rt/ports/ARMCMx/cmsis_os/cmsis_os.mk deleted file mode 100644 index ba8dbcb2a7..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/cmsis_os/cmsis_os.mk +++ /dev/null @@ -1,4 +0,0 @@ -# List of the ChibiOS/RT CMSIS RTOS wrapper. -CMSISRTOSSRC = ${CHIBIOS}/os/rt/ports/ARMCMx/cmsis_os/cmsis_os.c - -CMSISRTOSINC = ${CHIBIOS}/os/rt/ports/ARMCMx/cmsis_os diff --git a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v6m.s b/firmware/ChibiOS_16/os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v6m.s deleted file mode 100644 index 080b2aa206..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v6m.s +++ /dev/null @@ -1,142 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file compilers/GCC/chcoreasm_v6m.s - * @brief ARMv6-M architecture port low level code. - * - * @addtogroup ARMCMx_GCC_CORE - * @{ - */ - -#if !defined(FALSE) || defined(__DOXYGEN__) -#define FALSE 0 -#endif - -#if !defined(TRUE) || defined(__DOXYGEN__) -#define TRUE 1 -#endif - -#define _FROM_ASM_ -#include "chconf.h" -#include "chcore.h" - -#if !defined(__DOXYGEN__) - - .set CONTEXT_OFFSET, 12 - .set SCB_ICSR, 0xE000ED04 - .set ICSR_PENDSVSET, 0x10000000 - .set ICSR_NMIPENDSET, 0x80000000 - - .cpu cortex-m0 - .fpu softvfp - - .thumb - .text - -/*--------------------------------------------------------------------------* - * Performs a context switch between two threads. - *--------------------------------------------------------------------------*/ - .thumb_func - .globl _port_switch -_port_switch: - push {r4, r5, r6, r7, lr} - mov r4, r8 - mov r5, r9 - mov r6, r10 - mov r7, r11 - push {r4, r5, r6, r7} - - mov r3, sp - str r3, [r1, #CONTEXT_OFFSET] - ldr r3, [r0, #CONTEXT_OFFSET] - mov sp, r3 - - pop {r4, r5, r6, r7} - mov r8, r4 - mov r9, r5 - mov r10, r6 - mov r11, r7 - pop {r4, r5, r6, r7, pc} - -/*--------------------------------------------------------------------------* - * Start a thread by invoking its work function. - * - * Threads execution starts here, the code leaves the system critical zone - * and then jumps into the thread function passed in register R4. The - * register R5 contains the thread parameter. The function chThdExit() is - * called on thread function return. - *--------------------------------------------------------------------------*/ - .thumb_func - .globl _port_thread_start -_port_thread_start: -#if CH_DBG_SYSTEM_STATE_CHECK - bl _dbg_check_unlock -#endif -#if CH_DBG_STATISTICS - bl _stats_stop_measure_crit_thd -#endif - cpsie i - mov r0, r5 - blx r4 - movs r0, #0 /* MSG_OK */ - bl chThdExit - -/*--------------------------------------------------------------------------* - * Post-IRQ switch code. - * - * Exception handlers return here for context switching. - *--------------------------------------------------------------------------*/ - .thumb_func - .globl _port_switch_from_isr -_port_switch_from_isr: -#if CH_DBG_STATISTICS - bl _stats_start_measure_crit_thd -#endif -#if CH_DBG_SYSTEM_STATE_CHECK - bl _dbg_check_lock -#endif - bl chSchDoReschedule -#if CH_DBG_SYSTEM_STATE_CHECK - bl _dbg_check_unlock -#endif -#if CH_DBG_STATISTICS - bl _stats_stop_measure_crit_thd -#endif - .globl _port_exit_from_isr -_port_exit_from_isr: - ldr r2, .L2 - ldr r3, .L3 - str r3, [r2, #0] -#if CORTEX_ALTERNATE_SWITCH - cpsie i -#endif -.L1: b .L1 - - .align 2 -.L2: .word SCB_ICSR -#if CORTEX_ALTERNATE_SWITCH -.L3: .word ICSR_PENDSVSET -#else -.L3: .word ICSR_NMIPENDSET -#endif - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.s b/firmware/ChibiOS_16/os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.s deleted file mode 100644 index a47274ef01..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.s +++ /dev/null @@ -1,148 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file compilers/GCC/chcoreasm_v7m.s - * @brief ARMv7-M architecture port low level code. - * - * @addtogroup ARMCMx_GCC_CORE - * @{ - */ - -#if !defined(FALSE) || defined(__DOXYGEN__) -#define FALSE 0 -#endif - -#if !defined(TRUE) || defined(__DOXYGEN__) -#define TRUE 1 -#endif - -#define _FROM_ASM_ -#include "chconf.h" -#include "chcore.h" - -#if !defined(__DOXYGEN__) - - .set CONTEXT_OFFSET, 12 - .set SCB_ICSR, 0xE000ED04 - .set ICSR_PENDSVSET, 0x10000000 - - .syntax unified - .cpu cortex-m4 -#if CORTEX_USE_FPU - .fpu fpv4-sp-d16 -#else - .fpu softvfp -#endif - - .thumb - .text - -/*--------------------------------------------------------------------------* - * Performs a context switch between two threads. - *--------------------------------------------------------------------------*/ - .thumb_func - .globl _port_switch -_port_switch: - push {r4, r5, r6, r7, r8, r9, r10, r11, lr} -#if CORTEX_USE_FPU - vpush {s16-s31} -#endif - - str sp, [r1, #CONTEXT_OFFSET] -#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) && \ - ((CORTEX_MODEL == 3) || (CORTEX_MODEL == 4)) - /* Workaround for ARM errata 752419, only applied if - condition exists for it to be triggered.*/ - ldr r3, [r0, #CONTEXT_OFFSET] - mov sp, r3 -#else - ldr sp, [r0, #CONTEXT_OFFSET] -#endif - -#if CORTEX_USE_FPU - vpop {s16-s31} -#endif - pop {r4, r5, r6, r7, r8, r9, r10, r11, pc} - -/*--------------------------------------------------------------------------* - * Start a thread by invoking its work function. - * - * Threads execution starts here, the code leaves the system critical zone - * and then jumps into the thread function passed in register R4. The - * register R5 contains the thread parameter. The function chThdExit() is - * called on thread function return. - *--------------------------------------------------------------------------*/ - .thumb_func - .globl _port_thread_start -_port_thread_start: -#if CH_DBG_SYSTEM_STATE_CHECK - bl _dbg_check_unlock -#endif -#if CH_DBG_STATISTICS - bl _stats_stop_measure_crit_thd -#endif -#if CORTEX_SIMPLIFIED_PRIORITY - cpsie i -#else - movs r3, #0 /* CORTEX_BASEPRI_DISABLED */ - msr BASEPRI, r3 -#endif - mov r0, r5 - blx r4 - movs r0, #0 /* MSG_OK */ - bl chThdExit - -/*--------------------------------------------------------------------------* - * Post-IRQ switch code. - * - * Exception handlers return here for context switching. - *--------------------------------------------------------------------------*/ - .thumb_func - .globl _port_switch_from_isr -_port_switch_from_isr: -#if CH_DBG_STATISTICS - bl _stats_start_measure_crit_thd -#endif -#if CH_DBG_SYSTEM_STATE_CHECK - bl _dbg_check_lock -#endif - bl chSchDoReschedule -#if CH_DBG_SYSTEM_STATE_CHECK - bl _dbg_check_unlock -#endif -#if CH_DBG_STATISTICS - bl _stats_stop_measure_crit_thd -#endif - .globl _port_exit_from_isr -_port_exit_from_isr: -#if CORTEX_SIMPLIFIED_PRIORITY - movw r3, #:lower16:SCB_ICSR - movt r3, #:upper16:SCB_ICSR - mov r2, ICSR_PENDSVSET - str r2, [r3, #0] - cpsie i -#else /* !CORTEX_SIMPLIFIED_PRIORITY */ - svc #0 -#endif /* !CORTEX_SIMPLIFIED_PRIORITY */ -.L1: b .L1 - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/compilers/GCC/chtypes.h b/firmware/ChibiOS_16/os/rt/ports/ARMCMx/compilers/GCC/chtypes.h deleted file mode 100644 index e64ae06992..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/compilers/GCC/chtypes.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file ARMCMx/compilers/GCC/chtypes.h - * @brief ARM Cortex-Mx port system types. - * - * @addtogroup ARMCMx_GCC_CORE - * @{ - */ - -#ifndef _CHTYPES_H_ -#define _CHTYPES_H_ - -#include -#include -#include - -/** - * @name Common constants - */ -/** - * @brief Generic 'false' boolean constant. - */ -#if !defined(FALSE) || defined(__DOXYGEN__) -#define FALSE 0 -#endif - -/** - * @brief Generic 'true' boolean constant. - */ -#if !defined(TRUE) || defined(__DOXYGEN__) -#define TRUE 1 -#endif -/** @} */ - -/** - * @name Kernel types - * @{ - */ -typedef uint32_t rtcnt_t; /**< Realtime counter. */ -typedef uint64_t rttime_t; /**< Realtime accumulator. */ -typedef uint32_t syssts_t; /**< System status word. */ -typedef uint8_t tmode_t; /**< Thread flags. */ -typedef uint8_t tstate_t; /**< Thread state. */ -typedef uint8_t trefs_t; /**< Thread references counter. */ -typedef uint8_t tslices_t; /**< Thread time slices counter.*/ -typedef uint32_t tprio_t; /**< Thread priority. */ -typedef int32_t msg_t; /**< Inter-thread message. */ -typedef int32_t eventid_t; /**< Numeric event identifier. */ -typedef uint32_t eventmask_t; /**< Mask of event identifiers. */ -typedef uint32_t eventflags_t; /**< Mask of event flags. */ -typedef int32_t cnt_t; /**< Generic signed counter. */ -typedef uint32_t ucnt_t; /**< Generic unsigned counter. */ -/** @} */ - -/** - * @brief ROM constant modifier. - * @note It is set to use the "const" keyword in this port. - */ -#define ROMCONST const - -/** - * @brief Makes functions not inlineable. - * @note If the compiler does not support such attribute then the - * realtime counter precision could be degraded. - */ -#define NOINLINE __attribute__((noinline)) - -/** - * @brief Optimized thread function declaration macro. - */ -#define PORT_THD_FUNCTION(tname, arg) void tname(void *arg) - -/** - * @brief Packed variable specifier. - */ -#define PACKED_VAR __attribute__((packed)) - -#endif /* _CHTYPES_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk b/firmware/ChibiOS_16/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk deleted file mode 100644 index e520e54757..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk +++ /dev/null @@ -1,8 +0,0 @@ -# List of the ChibiOS/RT Cortex-M0 STM32F0xx port files. -PORTSRC = $(CHIBIOS)/os/rt/ports/ARMCMx/chcore.c \ - $(CHIBIOS)/os/rt/ports/ARMCMx/chcore_v6m.c - -PORTASM = $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v6m.s - -PORTINC = $(CHIBIOS)/os/rt/ports/ARMCMx \ - $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC diff --git a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk b/firmware/ChibiOS_16/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk deleted file mode 100644 index f8ee94d453..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +++ /dev/null @@ -1,8 +0,0 @@ -# List of the ChibiOS/RT ARMv7M generic port files. -PORTSRC = $(CHIBIOS)/os/rt/ports/ARMCMx/chcore.c \ - $(CHIBIOS)/os/rt/ports/ARMCMx/chcore_v7m.c - -PORTASM = $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.s - -PORTINC = $(CHIBIOS)/os/rt/ports/ARMCMx \ - $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC diff --git a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/compilers/IAR/chcoreasm_v6m.s b/firmware/ChibiOS_16/os/rt/ports/ARMCMx/compilers/IAR/chcoreasm_v6m.s deleted file mode 100644 index 066bf0a83c..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/compilers/IAR/chcoreasm_v6m.s +++ /dev/null @@ -1,142 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file compilers/IAR/chcoreasm_v6m.s - * @brief ARMv6-M architecture port low level code. - * - * @addtogroup ARMCMx_IAR_CORE - * @{ - */ - -#if !defined(FALSE) || defined(__DOXYGEN__) -#define FALSE 0 -#endif - -#if !defined(TRUE) || defined(__DOXYGEN__) -#define TRUE 1 -#endif - -#define _FROM_ASM_ -#include "chconf.h" -#include "chcore.h" - -#if !defined(__DOXYGEN__) - - MODULE ?chcoreasm_v6m - - AAPCS INTERWORK, VFP_COMPATIBLE - PRESERVE8 - -CONTEXT_OFFSET SET 12 -SCB_ICSR SET 0xE000ED04 - - SECTION .text:CODE:NOROOT(2) - - EXTERN chThdExit - EXTERN chSchDoReschedule -#if CH_DBG_STATISTICS - EXTERN _stats_start_measure_crit_thd - EXTERN _stats_stop_measure_crit_thd -#endif -#if CH_DBG_SYSTEM_STATE_CHECK - EXTERN _dbg_check_unlock - EXTERN _dbg_check_lock -#endif - - THUMB - -/* - * Performs a context switch between two threads. - */ - PUBLIC _port_switch -_port_switch: - push {r4, r5, r6, r7, lr} - mov r4, r8 - mov r5, r9 - mov r6, r10 - mov r7, r11 - push {r4, r5, r6, r7} - mov r3, sp - str r3, [r1, #CONTEXT_OFFSET] - ldr r3, [r0, #CONTEXT_OFFSET] - mov sp, r3 - pop {r4, r5, r6, r7} - mov r8, r4 - mov r9, r5 - mov r10, r6 - mov r11, r7 - pop {r4, r5, r6, r7, pc} - -/* - * Start a thread by invoking its work function. - * If the work function returns @p chThdExit() is automatically invoked. - */ - PUBLIC _port_thread_start -_port_thread_start: -#if CH_DBG_SYSTEM_STATE_CHECK - bl _dbg_check_unlock -#endif -#if CH_DBG_STATISTICS - bl _stats_stop_measure_crit_thd -#endif - cpsie i - mov r0, r5 - blx r4 - bl chThdExit - -/* - * Post-IRQ switch code. - * Exception handlers return here for context switching. - */ - PUBLIC _port_switch_from_isr - PUBLIC _port_exit_from_isr -_port_switch_from_isr: -#if CH_DBG_STATISTICS - bl _stats_start_measure_crit_thd -#endif -#if CH_DBG_SYSTEM_STATE_CHECK - bl _dbg_check_lock -#endif - bl chSchDoReschedule -#if CH_DBG_SYSTEM_STATE_CHECK - bl _dbg_check_unlock -#endif -#if CH_DBG_STATISTICS - bl _stats_stop_measure_crit_thd -#endif -_port_exit_from_isr: - ldr r2, =SCB_ICSR - movs r3, #128 -#if CORTEX_ALTERNATE_SWITCH - lsls r3, r3, #21 - str r3, [r2, #0] - cpsie i -#else - lsls r3, r3, #24 - str r3, [r2, #0] -#endif -waithere: - b waithere - - END - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/compilers/IAR/chcoreasm_v7m.s b/firmware/ChibiOS_16/os/rt/ports/ARMCMx/compilers/IAR/chcoreasm_v7m.s deleted file mode 100644 index 9bb4f2ab72..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/compilers/IAR/chcoreasm_v7m.s +++ /dev/null @@ -1,150 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file compilers/IAR/chcoreasm_v7m.s - * @brief ARMv7-M architecture port low level code. - * - * @addtogroup ARMCMx_IAR_CORE - * @{ - */ - -#if !defined(FALSE) || defined(__DOXYGEN__) -#define FALSE 0 -#endif - -#if !defined(TRUE) || defined(__DOXYGEN__) -#define TRUE 1 -#endif - -#define _FROM_ASM_ -#include "chconf.h" -#include "chcore.h" - -#if !defined(__DOXYGEN__) - - MODULE ?chcoreasm_v7m - - AAPCS INTERWORK, VFP_COMPATIBLE - PRESERVE8 - -CONTEXT_OFFSET SET 12 -SCB_ICSR SET 0xE000ED04 -ICSR_PENDSVSET SET 0x10000000 - - SECTION .text:CODE:NOROOT(2) - - EXTERN chThdExit - EXTERN chSchDoReschedule -#if CH_DBG_STATISTICS - EXTERN _stats_start_measure_crit_thd - EXTERN _stats_stop_measure_crit_thd -#endif -#if CH_DBG_SYSTEM_STATE_CHECK - EXTERN _dbg_check_unlock - EXTERN _dbg_check_lock -#endif - - THUMB - -/* - * Performs a context switch between two threads. - */ - PUBLIC _port_switch -_port_switch: - push {r4, r5, r6, r7, r8, r9, r10, r11, lr} -#if CORTEX_USE_FPU - vpush {s16-s31} -#endif - - str sp, [r1, #CONTEXT_OFFSET] -#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) && \ - ((CORTEX_MODEL == 3) || (CORTEX_MODEL == 4)) - /* Workaround for ARM errata 752419, only applied if - condition exists for it to be triggered.*/ - ldr r3, [r0, #CONTEXT_OFFSET] - mov sp, r3 -#else - ldr sp, [r0, #CONTEXT_OFFSET] -#endif - -#if CORTEX_USE_FPU - vpop {s16-s31} -#endif - pop {r4, r5, r6, r7, r8, r9, r10, r11, pc} - -/* - * Start a thread by invoking its work function. - * If the work function returns @p chThdExit() is automatically invoked. - */ - PUBLIC _port_thread_start -_port_thread_start: -#if CH_DBG_SYSTEM_STATE_CHECK - bl _dbg_check_unlock -#endif -#if CH_DBG_STATISTICS - bl _stats_stop_measure_crit_thd -#endif -#if CORTEX_SIMPLIFIED_PRIORITY - cpsie i -#else - movs r3, #0 /* CORTEX_BASEPRI_DISABLED */ - msr BASEPRI, r3 -#endif - mov r0, r5 - blx r4 - bl chThdExit - -/* - * Post-IRQ switch code. - * Exception handlers return here for context switching. - */ - PUBLIC _port_switch_from_isr - PUBLIC _port_exit_from_isr -_port_switch_from_isr: -#if CH_DBG_STATISTICS - bl _stats_start_measure_crit_thd -#endif -#if CH_DBG_SYSTEM_STATE_CHECK - bl _dbg_check_lock -#endif - bl chSchDoReschedule -#if CH_DBG_SYSTEM_STATE_CHECK - bl _dbg_check_unlock -#endif -#if CH_DBG_STATISTICS - bl _stats_stop_measure_crit_thd -#endif -_port_exit_from_isr: -#if CORTEX_SIMPLIFIED_PRIORITY - mov r3, #LWRD SCB_ICSR - movt r3, #HWRD SCB_ICSR - mov r2, #ICSR_PENDSVSET - str r2, [r3] - cpsie i -#else - svc #0 -#endif -.L3: b .L3 - - END - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/compilers/IAR/chtypes.h b/firmware/ChibiOS_16/os/rt/ports/ARMCMx/compilers/IAR/chtypes.h deleted file mode 100644 index 673e603cad..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/compilers/IAR/chtypes.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file ARMCMx/compilers/IAR/chtypes.h - * @brief ARM Cortex-Mx port system types. - * - * @addtogroup ARMCMx_IAR_CORE - * @{ - */ - -#ifndef _CHTYPES_H_ -#define _CHTYPES_H_ - -#include -#include -#include - -/** - * @name Common constants - */ -/** - * @brief Generic 'false' boolean constant. - */ -#if !defined(FALSE) || defined(__DOXYGEN__) -#define FALSE 0 -#endif - -/** - * @brief Generic 'true' boolean constant. - */ -#if !defined(TRUE) || defined(__DOXYGEN__) -#define TRUE (!FALSE) -#endif -/** @} */ - -/** - * @name Kernel types - * @{ - */ -typedef uint32_t rtcnt_t; /**< Realtime counter. */ -typedef uint64_t rttime_t; /**< Realtime accumulator. */ -typedef uint32_t syssts_t; /**< System status word. */ -typedef uint8_t tmode_t; /**< Thread flags. */ -typedef uint8_t tstate_t; /**< Thread state. */ -typedef uint8_t trefs_t; /**< Thread references counter. */ -typedef uint8_t tslices_t; /**< Thread time slices counter.*/ -typedef uint32_t tprio_t; /**< Thread priority. */ -typedef int32_t msg_t; /**< Inter-thread message. */ -typedef int32_t eventid_t; /**< Numeric event identifier. */ -typedef uint32_t eventmask_t; /**< Mask of event identifiers. */ -typedef uint32_t eventflags_t; /**< Mask of event flags. */ -typedef int32_t cnt_t; /**< Generic signed counter. */ -typedef uint32_t ucnt_t; /**< Generic unsigned counter. */ -/** @} */ - -/** - * @brief ROM constant modifier. - * @note It is set to use the "const" keyword in this port. - */ -#define ROMCONST const - -/** - * @brief Makes functions not inlineable. - * @note If the compiler does not support such attribute then the - * realtime counter precision could be degraded. - */ -#define NOINLINE - -/** - * @brief Optimized thread function declaration macro. - */ -#define PORT_THD_FUNCTION(tname, arg) void tname(void *arg) - -/** - * @brief Packed variable specifier. - */ -#define PACKED_VAR __packed - -#endif /* _CHTYPES_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/compilers/RVCT/chcoreasm_v6m.s b/firmware/ChibiOS_16/os/rt/ports/ARMCMx/compilers/RVCT/chcoreasm_v6m.s deleted file mode 100644 index eb5ffc283d..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/compilers/RVCT/chcoreasm_v6m.s +++ /dev/null @@ -1,139 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file compilers/RVCT/chcoreasm_v6m.s - * @brief ARMv6-M architecture port low level code. - * - * @addtogroup ARMCMx_RVCT_CORE - * @{ - */ - -#if !defined(FALSE) || defined(__DOXYGEN__) -#define FALSE 0 -#endif - -#if !defined(TRUE) || defined(__DOXYGEN__) -#define TRUE 1 -#endif - -#define _FROM_ASM_ -#include "chconf.h" -#include "chcore.h" - -#if !defined(__DOXYGEN__) - -CONTEXT_OFFSET EQU 12 -SCB_ICSR EQU 0xE000ED04 - - PRESERVE8 - THUMB - AREA |.text|, CODE, READONLY - - IMPORT chThdExit - IMPORT chSchDoReschedule -#if CH_DBG_STATISTICS - IMPORT _stats_start_measure_crit_thd - IMPORT _stats_stop_measure_crit_thd -#endif -#if CH_DBG_SYSTEM_STATE_CHECK - IMPORT _dbg_check_unlock - IMPORT _dbg_check_lock -#endif - -/* - * Performs a context switch between two threads. - */ - EXPORT _port_switch -_port_switch PROC - push {r4, r5, r6, r7, lr} - mov r4, r8 - mov r5, r9 - mov r6, r10 - mov r7, r11 - push {r4, r5, r6, r7} - mov r3, sp - str r3, [r1, #CONTEXT_OFFSET] - ldr r3, [r0, #CONTEXT_OFFSET] - mov sp, r3 - pop {r4, r5, r6, r7} - mov r8, r4 - mov r9, r5 - mov r10, r6 - mov r11, r7 - pop {r4, r5, r6, r7, pc} - ENDP - -/* - * Start a thread by invoking its work function. - * If the work function returns @p chThdExit() is automatically invoked. - */ - EXPORT _port_thread_start -_port_thread_start PROC -#if CH_DBG_SYSTEM_STATE_CHECK - bl _dbg_check_unlock -#endif -#if CH_DBG_STATISTICS - bl _stats_stop_measure_crit_thd -#endif - cpsie i - mov r0, r5 - blx r4 - bl chThdExit - ENDP - -/* - * Post-IRQ switch code. - * Exception handlers return here for context switching. - */ - EXPORT _port_switch_from_isr - EXPORT _port_exit_from_isr -_port_switch_from_isr PROC -#if CH_DBG_STATISTICS - bl _stats_start_measure_crit_thd -#endif -#if CH_DBG_SYSTEM_STATE_CHECK - bl _dbg_check_lock -#endif - bl chSchDoReschedule -#if CH_DBG_SYSTEM_STATE_CHECK - bl _dbg_check_unlock -#endif -#if CH_DBG_STATISTICS - bl _stats_stop_measure_crit_thd -#endif -_port_exit_from_isr - ldr r2, =SCB_ICSR - movs r3, #128 -#if CORTEX_ALTERNATE_SWITCH - lsls r3, r3, #21 - str r3, [r2, #0] - cpsie i -#else - lsls r3, r3, #24 - str r3, [r2, #0] -#endif -waithere b waithere - ENDP - - END - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/compilers/RVCT/chcoreasm_v7m.s b/firmware/ChibiOS_16/os/rt/ports/ARMCMx/compilers/RVCT/chcoreasm_v7m.s deleted file mode 100644 index fdd703e710..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/compilers/RVCT/chcoreasm_v7m.s +++ /dev/null @@ -1,148 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file compilers/RVCT/chcoreasm_v7m.s - * @brief ARMv7-M architecture port low level code. - * - * @addtogroup ARMCMx_RVCT_CORE - * @{ - */ - -#if !defined(FALSE) || defined(__DOXYGEN__) -#define FALSE 0 -#endif - -#if !defined(TRUE) || defined(__DOXYGEN__) -#define TRUE 1 -#endif - -#define _FROM_ASM_ -#include "chconf.h" -#include "chcore.h" - -#if !defined(__DOXYGEN__) - -CONTEXT_OFFSET EQU 12 -SCB_ICSR EQU 0xE000ED04 -ICSR_PENDSVSET EQU 0x10000000 - - PRESERVE8 - THUMB - AREA |.text|, CODE, READONLY - - IMPORT chThdExit - IMPORT chSchDoReschedule -#if CH_DBG_STATISTICS - IMPORT _stats_start_measure_crit_thd - IMPORT _stats_stop_measure_crit_thd -#endif -#if CH_DBG_SYSTEM_STATE_CHECK - IMPORT _dbg_check_unlock - IMPORT _dbg_check_lock -#endif - -/* - * Performs a context switch between two threads. - */ - EXPORT _port_switch -_port_switch PROC - push {r4, r5, r6, r7, r8, r9, r10, r11, lr} -#if CORTEX_USE_FPU - vpush {s16-s31} -#endif - - str sp, [r1, #CONTEXT_OFFSET] -#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) && \ - ((CORTEX_MODEL == 3) || (CORTEX_MODEL == 4)) - /* Workaround for ARM errata 752419, only applied if - condition exists for it to be triggered.*/ - ldr r3, [r0, #CONTEXT_OFFSET] - mov sp, r3 -#else - ldr sp, [r0, #CONTEXT_OFFSET] -#endif - -#if CORTEX_USE_FPU - vpop {s16-s31} -#endif - pop {r4, r5, r6, r7, r8, r9, r10, r11, pc} - ENDP - -/* - * Start a thread by invoking its work function. - * If the work function returns @p chThdExit() is automatically invoked. - */ - EXPORT _port_thread_start -_port_thread_start PROC -#if CH_DBG_SYSTEM_STATE_CHECK - bl _dbg_check_unlock -#endif -#if CH_DBG_STATISTICS - bl _stats_stop_measure_crit_thd -#endif -#if CORTEX_SIMPLIFIED_PRIORITY - cpsie i -#else - movs r3, #0 /* CORTEX_BASEPRI_DISABLED */ - msr BASEPRI, r3 -#endif - mov r0, r5 - blx r4 - bl chThdExit - ENDP - -/* - * Post-IRQ switch code. - * Exception handlers return here for context switching. - */ - EXPORT _port_switch_from_isr - EXPORT _port_exit_from_isr -_port_switch_from_isr PROC -#if CH_DBG_STATISTICS - bl _stats_start_measure_crit_thd -#endif -#if CH_DBG_SYSTEM_STATE_CHECK - bl _dbg_check_lock -#endif - bl chSchDoReschedule -#if CH_DBG_SYSTEM_STATE_CHECK - bl _dbg_check_unlock -#endif -#if CH_DBG_STATISTICS - bl _stats_stop_measure_crit_thd -#endif -_port_exit_from_isr -#if CORTEX_SIMPLIFIED_PRIORITY - mov r3, #SCB_ICSR :AND: 0xFFFF - movt r3, #SCB_ICSR :SHR: 16 - mov r2, #ICSR_PENDSVSET - str r2, [r3, #0] - cpsie i -#else - svc #0 -#endif -waithere b waithere - ENDP - - END - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/compilers/RVCT/chtypes.h b/firmware/ChibiOS_16/os/rt/ports/ARMCMx/compilers/RVCT/chtypes.h deleted file mode 100644 index f11c1db318..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/ARMCMx/compilers/RVCT/chtypes.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file ARMCMx/compilers/RVCT/chtypes.h - * @brief ARM Cortex-Mx port system types. - * - * @addtogroup ARMCMx_RVCT_CORE - * @{ - */ - -#ifndef _CHTYPES_H_ -#define _CHTYPES_H_ - -#include -#include -#include - -/** - * @name Common constants - */ -/** - * @brief Generic 'false' boolean constant. - */ -#if !defined(FALSE) || defined(__DOXYGEN__) -#define FALSE 0 -#endif - -/** - * @brief Generic 'true' boolean constant. - */ -#if !defined(TRUE) || defined(__DOXYGEN__) -#define TRUE (!FALSE) -#endif -/** @} */ - -/** - * @name Kernel types - * @{ - */ -typedef uint32_t rtcnt_t; /**< Realtime counter. */ -typedef uint64_t rttime_t; /**< Realtime accumulator. */ -typedef uint32_t syssts_t; /**< System status word. */ -typedef uint8_t tmode_t; /**< Thread flags. */ -typedef uint8_t tstate_t; /**< Thread state. */ -typedef uint8_t trefs_t; /**< Thread references counter. */ -typedef uint8_t tslices_t; /**< Thread time slices counter.*/ -typedef uint32_t tprio_t; /**< Thread priority. */ -typedef int32_t msg_t; /**< Inter-thread message. */ -typedef int32_t eventid_t; /**< Numeric event identifier. */ -typedef uint32_t eventmask_t; /**< Mask of event identifiers. */ -typedef uint32_t eventflags_t; /**< Mask of event flags. */ -typedef int32_t cnt_t; /**< Generic signed counter. */ -typedef uint32_t ucnt_t; /**< Generic unsigned counter. */ -/** @} */ - -/** - * @brief ROM constant modifier. - * @note It is set to use the "const" keyword in this port. - */ -#define ROMCONST const - -/** - * @brief Makes functions not inlineable. - * @note If the compiler does not support such attribute then the - * realtime counter precision could be degraded. - */ -#define NOINLINE - -/** - * @brief Optimized thread function declaration macro. - */ -#define PORT_THD_FUNCTION(tname, arg) void tname(void *arg) - -/** - * @brief Packed variable specifier. - */ -#define PACKED_VAR __packed - -#endif /* _CHTYPES_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/ports/AVR/chcore.c b/firmware/ChibiOS_16/os/rt/ports/AVR/chcore.c deleted file mode 100644 index 575138737f..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/AVR/chcore.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file AVR/chcore.c - * @brief AVR architecture port code. - * - * @addtogroup AVR_CORE - * @{ - */ - -#include "ch.h" - -/** - * @brief Performs a context switch between two threads. - * @details This is the most critical code in any port, this function - * is responsible for the context switch between 2 threads. - * @note The implementation of this code affects directly the context - * switch performance so optimize here as much as you can. - * @note The function is declared as a weak symbol, it is possible to - * redefine it in your application code. - * - * @param[in] ntp the thread to be switched in - * @param[in] otp the thread to be switched out - */ -#if !defined(__DOXYGEN__) -__attribute__((naked, weak)) -#endif -void port_switch(thread_t *ntp, thread_t *otp) { - - asm volatile ("push r2"); - asm volatile ("push r3"); - asm volatile ("push r4"); - asm volatile ("push r5"); - asm volatile ("push r6"); - asm volatile ("push r7"); - asm volatile ("push r8"); - asm volatile ("push r9"); - asm volatile ("push r10"); - asm volatile ("push r11"); - asm volatile ("push r12"); - asm volatile ("push r13"); - asm volatile ("push r14"); - asm volatile ("push r15"); - asm volatile ("push r16"); - asm volatile ("push r17"); - asm volatile ("push r28"); - asm volatile ("push r29"); - - asm volatile ("movw r30, r22"); - asm volatile ("in r0, 0x3d"); - asm volatile ("std Z+5, r0"); - asm volatile ("in r0, 0x3e"); - asm volatile ("std Z+6, r0"); - - asm volatile ("movw r30, r24"); - asm volatile ("ldd r0, Z+5"); - asm volatile ("out 0x3d, r0"); - asm volatile ("ldd r0, Z+6"); - asm volatile ("out 0x3e, r0"); - - asm volatile ("pop r29"); - asm volatile ("pop r28"); - asm volatile ("pop r17"); - asm volatile ("pop r16"); - asm volatile ("pop r15"); - asm volatile ("pop r14"); - asm volatile ("pop r13"); - asm volatile ("pop r12"); - asm volatile ("pop r11"); - asm volatile ("pop r10"); - asm volatile ("pop r9"); - asm volatile ("pop r8"); - asm volatile ("pop r7"); - asm volatile ("pop r6"); - asm volatile ("pop r5"); - asm volatile ("pop r4"); - asm volatile ("pop r3"); - asm volatile ("pop r2"); - asm volatile ("ret"); -} - -/** - * @brief Halts the system. - * @details This function is invoked by the operating system when an - * unrecoverable error is detected (for example because a programming - * error in the application code that triggers an assertion while in - * debug mode). - * @note The function is declared as a weak symbol, it is possible to - * redefine it in your application code. - */ -#if !defined(__DOXYGEN__) -__attribute__((weak)) -#endif -void port_halt(void) { - - port_disable(); - while (TRUE) { - } -} - -/** - * @brief Start a thread by invoking its work function. - * @details If the work function returns @p chThdExit() is automatically - * invoked. - */ -void _port_thread_start(void) { - - chSysUnlock(); - asm volatile ("movw r24, r4"); - asm volatile ("movw r30, r2"); - asm volatile ("icall"); - asm volatile ("call chThdExit"); -} - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/ports/AVR/chcore.h b/firmware/ChibiOS_16/os/rt/ports/AVR/chcore.h deleted file mode 100644 index 42275548b5..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/AVR/chcore.h +++ /dev/null @@ -1,390 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file AVR/chcore.h - * @brief AVR architecture port macros and structures. - * - * @addtogroup AVR_CORE - * @{ - */ - -#ifndef _CHCORE_H_ -#define _CHCORE_H_ - -#include -#include - -#if CH_DBG_ENABLE_STACK_CHECK -#error "option CH_DBG_ENABLE_STACK_CHECK not supported by this port" -#endif - -/** - * @brief If enabled allows the idle thread to enter a low power mode. - */ -#ifndef ENABLE_WFI_IDLE -#define ENABLE_WFI_IDLE 0 -#endif - -/** - * @brief Macro defining the AVR architecture. - */ -#define PORT_ARCHITECTURE_AVR - -/** - * @brief Name of the implemented architecture. - */ -#define PORT_ARCHITECTURE_NAME "AVR" - -/** - * @brief Name of the architecture variant (optional). - */ -#define PORT_CORE_VARIANT_NAME "MegaAVR" - -/** - * @brief Name of the compiler supported by this port. - */ -#define PORT_COMPILER_NAME "GCC " __VERSION__ - -/** - * @brief Port-specific information string. - */ -#define PORT_INFO "None" - -/** - * @brief This port supports a realtime counter. - */ -#define PORT_SUPPORTS_RT FALSE - -/** - * @brief 8 bits stack and memory alignment enforcement. - */ -typedef uint8_t stkalign_t; - -/** - * @brief Interrupt saved context. - * @details This structure represents the stack frame saved during a - * preemption-capable interrupt handler. - * @note The field @p _next is not part of the context, it represents the - * offset of the structure relative to the stack pointer. - */ -struct port_extctx { - uint8_t _next; - uint8_t r31; - uint8_t r30; - uint8_t r27; - uint8_t r26; - uint8_t r25; - uint8_t r24; - uint8_t r23; - uint8_t r22; - uint8_t r21; - uint8_t r20; - uint8_t r19; - uint8_t r18; - uint8_t sr; - uint8_t r1; - uint8_t r0; -#ifdef __AVR_3_BYTE_PC__ - uint8_t pcx; -#endif - uint16_t pc; -}; - -/** - * @brief System saved context. - * @details This structure represents the inner stack frame during a context - * switching. - * @note The field @p _next is not part of the context, it represents the - * offset of the structure relative to the stack pointer. - */ -struct port_intctx { - uint8_t _next; - uint8_t r29; - uint8_t r28; - uint8_t r17; - uint8_t r16; - uint8_t r15; - uint8_t r14; - uint8_t r13; - uint8_t r12; - uint8_t r11; - uint8_t r10; - uint8_t r9; - uint8_t r8; - uint8_t r7; - uint8_t r6; - uint8_t r5; - uint8_t r4; - uint8_t r3; - uint8_t r2; -#ifdef __AVR_3_BYTE_PC__ - uint8_t pcx; -#endif - uint8_t pcl; - uint8_t pch; -}; - -/** - * @brief Platform dependent part of the @p thread_t structure. - * @details In the AVR port this structure just holds a pointer to the - * @p port_intctx structure representing the stack pointer at the time - * of the context switch. - */ -struct context { - struct port_intctx *sp; -}; - -/** - * @brief Platform dependent part of the @p chThdCreateI() API. - * @details This code usually setup the context switching frame represented - * by an @p port_intctx structure. - */ -#ifdef __AVR_3_BYTE_PC__ -#define PORT_SETUP_CONTEXT(tp, workspace, wsize, pf, arg) { \ - tp->p_ctx.sp = (struct port_intctx*)((uint8_t *)workspace + wsize - \ - sizeof(struct port_intctx)); \ - tp->p_ctx.sp->r2 = (int)pf; \ - tp->p_ctx.sp->r3 = (int)pf >> 8; \ - tp->p_ctx.sp->r4 = (int)arg; \ - tp->p_ctx.sp->r5 = (int)arg >> 8; \ - tp->p_ctx.sp->pcx = (int)0; \ - tp->p_ctx.sp->pcl = (int)_port_thread_start >> 8; \ - tp->p_ctx.sp->pch = (int)_port_thread_start; \ -} -#else /* __AVR_3_BYTE_PC__ */ -#define PORT_SETUP_CONTEXT(tp, workspace, wsize, pf, arg) { \ - tp->p_ctx.sp = (struct port_intctx*)((uint8_t *)workspace + wsize - \ - sizeof(struct port_intctx)); \ - tp->p_ctx.sp->r2 = (int)pf; \ - tp->p_ctx.sp->r3 = (int)pf >> 8; \ - tp->p_ctx.sp->r4 = (int)arg; \ - tp->p_ctx.sp->r5 = (int)arg >> 8; \ - tp->p_ctx.sp->pcl = (int)_port_thread_start >> 8; \ - tp->p_ctx.sp->pch = (int)_port_thread_start; \ -} -#endif /* __AVR_3_BYTE_PC__ */ - -/** - * @brief Stack size for the system idle thread. - * @details This size depends on the idle thread implementation, usually - * the idle thread should take no more space than those reserved - * by @p PORT_INT_REQUIRED_STACK. - * @note In this port it is set to 8. - */ -#if !defined(PORT_IDLE_THREAD_STACK_SIZE) || defined(__DOXYGEN__) -#define PORT_IDLE_THREAD_STACK_SIZE 8 -#endif - -/** - * @brief Per-thread stack overhead for interrupts servicing. - * @details This constant is used in the calculation of the correct working - * area size. - * This value can be zero on those architecture where there is a - * separate interrupt stack and the stack space between @p port_intctx - * and @p port_extctx is known to be zero. - * @note In this port the default is 32 bytes per thread. - */ -#if !defined(PORT_INT_REQUIRED_STACK) || defined(__DOXYGEN__) -#define PORT_INT_REQUIRED_STACK 32 -#endif - -/** - * @brief Enforces a correct alignment for a stack area size value. - */ -#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) - -/** - * @brief Computes the thread working area global size. - */ -#define PORT_WA_SIZE(n) STACK_ALIGN(sizeof(thread_t) + \ - (sizeof(struct port_intctx) - 1) + \ - (sizeof(struct port_extctx) - 1) + \ - (n) + (PORT_INT_REQUIRED_STACK)) - -/** - * @brief Static working area allocation. - * @details This macro is used to allocate a static thread working area - * aligned as both position and size. - */ -#define WORKING_AREA(s, n) stkalign_t s[PORT_WA_SIZE(n) / sizeof(stkalign_t)] - -/** - * @brief IRQ prologue code. - * @details This macro must be inserted at the start of all IRQ handlers - * enabled to invoke system APIs. - * @note This code tricks the compiler to save all the specified registers - * by "touching" them. - */ -#define PORT_IRQ_PROLOGUE() { \ - asm ("" : : : "r18", "r19", "r20", "r21", "r22", "r23", "r24", \ - "r25", "r26", "r27", "r30", "r31"); \ -} - -/** - * @brief IRQ epilogue code. - * @details This macro must be inserted at the end of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_EPILOGUE() { \ - _dbg_check_lock(); \ - if (chSchIsPreemptionRequired()) \ - chSchDoReschedule(); \ - _dbg_check_unlock(); \ -} - -/** - * @brief IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_IRQ_HANDLER(id) ISR(id) - -/** - * @brief Port-related initialization code. - * @note This function is empty in this port. - */ -#define port_init() - -/** - * @brief Returns a word encoding the current interrupts status. - * - * @return The interrupts status. - */ -static inline syssts_t port_get_irq_status(void) { - - return SREG; -} - -/** - * @brief Checks the interrupt status. - * - * @param[in] sts the interrupt status word - * - * @return The interrupt status. - * @retvel false the word specified a disabled interrupts status. - * @retvel true the word specified an enabled interrupts status. - */ -static inline bool port_irq_enabled(syssts_t sts) { - - return (bool)((sts & 0x80) != 0); -} - -/** - * @brief Determines the current execution context. - * - * @return The execution context. - * @retval false not running in ISR mode. - * @retval true running in ISR mode. - */ -static inline bool port_is_isr_context(void) { - - //TODO: is there any way to determine this? - return false; -} - -/** - * @brief Kernel-lock action. - * @details Usually this function just disables interrupts but may perform more - * actions. - * @note Implemented as global interrupt disable. - */ -#define port_lock() asm volatile ("cli" : : : "memory") - -/** - * @brief Kernel-unlock action. - * @details Usually this function just enables interrupts but may perform more - * actions. - * @note Implemented as global interrupt enable. - */ -#define port_unlock() asm volatile ("sei" : : : "memory") - -/** - * @brief Kernel-lock action from an interrupt handler. - * @details This function is invoked before invoking I-class APIs from - * interrupt handlers. The implementation is architecture dependent, - * in its simplest form it is void. - * @note This function is empty in this port. - */ -#define port_lock_from_isr() - -/** - * @brief Kernel-unlock action from an interrupt handler. - * @details This function is invoked after invoking I-class APIs from interrupt - * handlers. The implementation is architecture dependent, in its - * simplest form it is void. - * @note This function is empty in this port. - */ -#define port_unlock_from_isr() - -/** - * @brief Disables all the interrupt sources. - * @note Of course non-maskable interrupt sources are not included. - * @note Implemented as global interrupt disable. - */ -#define port_disable() asm volatile ("cli" : : : "memory") - -/** - * @brief Disables the interrupt sources below kernel-level priority. - * @note Interrupt sources above kernel level remains enabled. - * @note Same as @p port_disable() in this port, there is no difference - * between the two states. - */ -#define port_suspend() asm volatile ("cli" : : : "memory") - -/** - * @brief Enables all the interrupt sources. - * @note Implemented as global interrupt enable. - */ -#define port_enable() asm volatile ("sei" : : : "memory") - -/** - * @brief Enters an architecture-dependent IRQ-waiting mode. - * @details The function is meant to return when an interrupt becomes pending. - * The simplest implementation is an empty function or macro but this - * would not take advantage of architecture-specific power saving - * modes. - * @note This port function is implemented as inlined code for performance - * reasons. - */ -#if ENABLE_WFI_IDLE != 0 -#define port_wait_for_interrupt() { \ - asm volatile ("sleep" : : : "memory"); \ -} -#else -#define port_wait_for_interrupt() -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void port_switch(thread_t *ntp, thread_t *otp); - void port_halt(void); - void _port_thread_start(void); -#ifdef __cplusplus -} -#endif - -#if CH_CFG_ST_TIMEDELTA > 0 -#include "chcore_timer.h" -#endif - -#endif /* _CHCORE_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/ports/AVR/chcore_timer.h b/firmware/ChibiOS_16/os/rt/ports/AVR/chcore_timer.h deleted file mode 100644 index 3a2ecec039..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/AVR/chcore_timer.h +++ /dev/null @@ -1,124 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file AVR/chcore_timer.h - * @brief System timer header file. - * - * @addtogroup AVR_TIMER - * @{ - */ - -#ifndef _CHCORE_TIMER_H_ -#define _CHCORE_TIMER_H_ - -/* This is the only header in the HAL designed to be include-able alone.*/ -#include "st.h" - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -/** - * @brief Starts the alarm. - * @note Makes sure that no spurious alarms are triggered after - * this call. - * - * @param[in] time the time to be set for the first alarm - * - * @notapi - */ -static inline void port_timer_start_alarm(systime_t time) { - - stStartAlarm(time); -} - -/** - * @brief Stops the alarm interrupt. - * - * @notapi - */ -static inline void port_timer_stop_alarm(void) { - - stStopAlarm(); -} - -/** - * @brief Sets the alarm time. - * - * @param[in] time the time to be set for the next alarm - * - * @notapi - */ -static inline void port_timer_set_alarm(systime_t time) { - - stSetAlarm(time); -} - -/** - * @brief Returns the system time. - * - * @return The system time. - * - * @notapi - */ -static inline systime_t port_timer_get_time(void) { - - return stGetCounter(); -} - -/** - * @brief Returns the current alarm time. - * - * @return The currently set alarm time. - * - * @notapi - */ -static inline systime_t port_timer_get_alarm(void) { - - return stGetAlarm(); -} - -#endif /* _CHCORE_TIMER_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/ports/AVR/compilers/GCC/chtypes.h b/firmware/ChibiOS_16/os/rt/ports/AVR/compilers/GCC/chtypes.h deleted file mode 100644 index 90d596d7da..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/AVR/compilers/GCC/chtypes.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file AVR/compilers/GCC/chtypes.h - * @brief AVR architecture port system types. - * - * @addtogroup AVR_CORE - * @{ - */ - -#ifndef _CHTYPES_H_ -#define _CHTYPES_H_ - -#include -#include -#include - -/** - * @name Common constants - */ -/** - * @brief Generic 'false' boolean constant. - */ -#if !defined(FALSE) || defined(__DOXYGEN__) -#define FALSE 0 -#endif - -/** - * @brief Generic 'true' boolean constant. - */ -#if !defined(TRUE) || defined(__DOXYGEN__) -#define TRUE (!FALSE) -#endif -/** @} */ - -typedef bool bool_t; /**< Fast boolean type. */ -typedef uint8_t syssts_t; /**< System status word. */ -typedef uint8_t tmode_t; /**< Thread flags. */ -typedef uint8_t tstate_t; /**< Thread state. */ -typedef uint8_t trefs_t; /**< Thread references counter. */ -typedef uint8_t tslices_t; /**< Thread time slices counter. */ -typedef uint8_t tprio_t; /**< Thread priority. */ -typedef int16_t msg_t; /**< Inter-thread message. */ -typedef uint8_t eventid_t; /**< Event Id. */ -typedef uint8_t eventmask_t; /**< Event mask. */ -typedef uint8_t eventflags_t; /**< Event flags. */ -typedef int8_t cnt_t; /**< Resources counter. */ - -/** - * @brief ROM constant modifier. - * @note It is set to use the "const" keyword in this port. - */ -#define ROMCONST const - -/** - * @brief Makes functions not inlineable. - * @note If the compiler does not support such attribute then the - * realtime counter precision could be degraded. - */ -#define NOINLINE __attribute__((noinline)) - -/** - * @brief Optimized thread function declaration macro. - */ -#define PORT_THD_FUNCTION(tname, arg) void tname(void *arg) - -/** - * @brief Packed variable specifier. - */ -#define PACKED_VAR __attribute__((packed)) - -#endif /* _CHTYPES_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/ports/AVR/compilers/GCC/mk/port.mk b/firmware/ChibiOS_16/os/rt/ports/AVR/compilers/GCC/mk/port.mk deleted file mode 100644 index b0f4d713c2..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/AVR/compilers/GCC/mk/port.mk +++ /dev/null @@ -1,7 +0,0 @@ -# List of the ChibiOS/RT AVR port files. -PORTSRC = ${CHIBIOS}/os/rt/ports/AVR/chcore.c - -PORTASM = - -PORTINC = ${CHIBIOS}/os/rt/ports/AVR \ - ${CHIBIOS}/os/rt/ports/AVR/compilers/GCC diff --git a/firmware/ChibiOS_16/os/rt/ports/SIMIA32/chcore.c b/firmware/ChibiOS_16/os/rt/ports/SIMIA32/chcore.c deleted file mode 100644 index 6a17026945..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/SIMIA32/chcore.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file SIMIA32/chcore.c - * @brief Simulator on IA32 port code. - * - * @addtogroup SIMIA32_GCC_CORE - * @{ - */ - -#include - -#include "ch.h" - -/*===========================================================================*/ -/* Module local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -bool port_isr_context_flag; -syssts_t port_irq_sts; - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -/** - * Performs a context switch between two threads. - * @param otp the thread to be switched out - * @param ntp the thread to be switched in - */ -__attribute__((used)) -static void __dummy(thread_t *ntp, thread_t *otp) { - (void)ntp; (void)otp; - - asm volatile ( -#if defined(WIN32) - ".globl @port_switch@8 \n\t" - "@port_switch@8:" -#elif defined(__APPLE__) - ".globl _port_switch \n\t" - "_port_switch:" -#else - ".globl port_switch \n\t" - "port_switch:" -#endif - "push %ebp \n\t" - "push %esi \n\t" - "push %edi \n\t" - "push %ebx \n\t" - "movl %esp, 12(%edx) \n\t" - "movl 12(%ecx), %esp \n\t" - "pop %ebx \n\t" - "pop %edi \n\t" - "pop %esi \n\t" - "pop %ebp \n\t" - "ret"); -} - -/** - * @brief Start a thread by invoking its work function. - * @details If the work function returns @p chThdExit() is automatically - * invoked. - */ -__attribute__((cdecl, noreturn)) -void _port_thread_start(msg_t (*pf)(void *), void *p) { - - chSysUnlock(); - pf(p); - chThdExit(0); - while(1); -} - -/** - * @brief Returns the current value of the realtime counter. - * - * @return The realtime counter value. - */ -rtcnt_t port_rt_get_counter_value(void) { - LARGE_INTEGER n; - - QueryPerformanceCounter(&n); - - return (rtcnt_t)(n.QuadPart / 1000LL); -} - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/ports/SIMIA32/chcore.h b/firmware/ChibiOS_16/os/rt/ports/SIMIA32/chcore.h deleted file mode 100644 index a2345f5a51..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/SIMIA32/chcore.h +++ /dev/null @@ -1,381 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file SIMIA32/chcore.h - * @brief Simulator on IA32 port macros and structures. - * - * @addtogroup SIMIA32_GCC_CORE - * @{ - */ - -#ifndef _CHCORE_H_ -#define _CHCORE_H_ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * Macro defining the a simulated architecture into x86. - */ -#define PORT_ARCHITECTURE_SIMIA32 - -/** - * Name of the implemented architecture. - */ -#define PORT_ARCHITECTURE_NAME "Simulator" - -/** - * @brief Name of the architecture variant (optional). - */ -#define PORT_CORE_VARIANT_NAME "x86 (integer only)" - -/** - * @brief Name of the compiler supported by this port. - */ -#define PORT_COMPILER_NAME "GCC " __VERSION__ - -/** - * @brief Port-specific information string. - */ -#define PORT_INFO "No preemption" - -/** - * @brief This port supports a realtime counter. - */ -#define PORT_SUPPORTS_RT TRUE - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Stack size for the system idle thread. - * @details This size depends on the idle thread implementation, usually - * the idle thread should take no more space than those reserved - * by @p PORT_INT_REQUIRED_STACK. - */ -#ifndef PORT_IDLE_THREAD_STACK_SIZE -#define PORT_IDLE_THREAD_STACK_SIZE 256 -#endif - -/** - * @brief Per-thread stack overhead for interrupts servicing. - * @details This constant is used in the calculation of the correct working - * area size. - */ -#ifndef PORT_INT_REQUIRED_STACK -#define PORT_INT_REQUIRED_STACK 16384 -#endif - -/** - * @brief Enables an alternative timer implementation. - * @details Usually the port uses a timer interface defined in the file - * @p chcore_timer.h, if this option is enabled then the file - * @p chcore_timer_alt.h is included instead. - */ -#if !defined(PORT_USE_ALT_TIMER) -#define PORT_USE_ALT_TIMER FALSE -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if CH_DBG_ENABLE_STACK_CHECK -#error "option CH_DBG_ENABLE_STACK_CHECK not supported by this port" -#endif - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/** - * @brief 16 bytes stack and memory alignment enforcement. - */ -typedef struct { - uint8_t a[16]; -} stkalign_t __attribute__((aligned(16))); - -/** - * @brief Type of a generic x86 register. - */ -typedef void *regx86; - -/** - * @brief Interrupt saved context. - * @details This structure represents the stack frame saved during a - * preemption-capable interrupt handler. - */ -struct port_extctx { -}; - -/** - * @brief System saved context. - * @details This structure represents the inner stack frame during a context - * switch. - */ -struct port_intctx { - regx86 ebx; - regx86 edi; - regx86 esi; - regx86 ebp; - regx86 eip; -}; - -/** - * @brief Platform dependent part of the @p thread_t structure. - * @details In this port the structure just holds a pointer to the - * @p port_intctx structure representing the stack pointer - * at context switch time. - */ -struct context { - struct port_intctx *esp; -}; - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -#define APUSH(p, a) do { \ - (p) -= sizeof(void *); \ - *(void **)(p) = (void*)(a); \ -} while (false) - -/* Darwin requires the stack to be aligned to a 16-byte boundary at - * the time of a call instruction (in case the called function needs - * to save MMX registers). This aligns to 'mod' module 16, so that we'll end - * up with the right alignment after pushing the args. */ -#define AALIGN(p, mask, mod) \ - p = (void *)((((uint32_t)(p) - (uint32_t)(mod)) & ~(uint32_t)(mask)) + (uint32_t)(mod)) \ - -/** - * @brief Platform dependent part of the @p chThdCreateI() API. - * @details This code usually setup the context switching frame represented - * by an @p port_intctx structure. - */ -#define PORT_SETUP_CONTEXT(tp, workspace, wsize, pf, arg) { \ - /*lint -save -e611 -e9033 -e9074 -e9087 [10.8, 11.1, 11.3] Valid casts.*/ \ - uint8_t *esp = (uint8_t *)workspace + wsize; \ - APUSH(esp, 0); \ - uint8_t *savebp = esp; \ - AALIGN(esp, 15, 8); \ - APUSH(esp, arg); \ - APUSH(esp, pf); \ - APUSH(esp, 0); \ - esp -= sizeof(struct port_intctx); \ - ((struct port_intctx *)esp)->eip = (void *)_port_thread_start; \ - ((struct port_intctx *)esp)->ebx = NULL; \ - ((struct port_intctx *)esp)->edi = NULL; \ - ((struct port_intctx *)esp)->esi = NULL; \ - ((struct port_intctx *)esp)->ebp = (void *)savebp; \ - (tp)->p_ctx.esp = (struct port_intctx *)esp; \ - /*lint -restore*/ \ -} - - /** - * @brief Computes the thread working area global size. - * @note There is no need to perform alignments in this macro. - */ -#define PORT_WA_SIZE(n) ((sizeof(void *) * 4U) + \ - sizeof(struct port_intctx) + \ - ((size_t)(n)) + \ - ((size_t)(PORT_INT_REQUIRED_STACK))) - -/** - * @brief IRQ prologue code. - * @details This macro must be inserted at the start of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_PROLOGUE() { \ - port_isr_context_flag = true; \ -} - -/** - * @brief IRQ epilogue code. - * @details This macro must be inserted at the end of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_EPILOGUE() { \ - port_isr_context_flag = false; \ -} - -/** - * @brief IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_IRQ_HANDLER(id) void id(void) - -/** - * @brief Fast IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_FAST_IRQ_HANDLER(id) void id(void) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -extern bool port_isr_context_flag; -extern syssts_t port_irq_sts; - -#ifdef __cplusplus -extern "C" { -#endif - /*lint -save -e950 [Dir-2.1] Non-ANSI keywords are fine in the port layer.*/ - __attribute__((fastcall)) void port_switch(thread_t *ntp, thread_t *otp); - __attribute__((cdecl, noreturn)) void _port_thread_start(msg_t (*pf)(void *p), - void *p); - /*lint -restore*/ - rtcnt_t port_rt_get_counter_value(void); - void _sim_check_for_interrupts(void); -#ifdef __cplusplus -} -#endif - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -/** - * @brief Port-related initialization code. - */ -static inline void port_init(void) { - - port_irq_sts = (syssts_t)0; - port_isr_context_flag = false; -} - -/** - * @brief Returns a word encoding the current interrupts status. - * - * @return The interrupts status. - */ -static inline syssts_t port_get_irq_status(void) { - - return port_irq_sts; -} - -/** - * @brief Checks the interrupt status. - * - * @param[in] sts the interrupt status word - * - * @return The interrupt status. - * @retvel false the word specified a disabled interrupts status. - * @retvel true the word specified an enabled interrupts status. - */ -static inline bool port_irq_enabled(syssts_t sts) { - - return sts == (syssts_t)0; -} - -/** - * @brief Determines the current execution context. - * - * @return The execution context. - * @retval false not running in ISR mode. - * @retval true running in ISR mode. - */ -static inline bool port_is_isr_context(void) { - - return port_isr_context_flag; -} - -/** - * @brief Kernel-lock action. - * @details In this port this function disables interrupts globally. - */ -static inline void port_lock(void) { - - port_irq_sts = (syssts_t)1; -} - -/** - * @brief Kernel-unlock action. - * @details In this port this function enables interrupts globally. - */ -static inline void port_unlock(void) { - - port_irq_sts = (syssts_t)0; -} - -/** - * @brief Kernel-lock action from an interrupt handler. - * @details In this port this function disables interrupts globally. - * @note Same as @p port_lock() in this port. - */ -static inline void port_lock_from_isr(void) { - - port_irq_sts = (syssts_t)1; -} - -/** - * @brief Kernel-unlock action from an interrupt handler. - * @details In this port this function enables interrupts globally. - * @note Same as @p port_lock() in this port. - */ -static inline void port_unlock_from_isr(void) { - - port_irq_sts = (syssts_t)0; -} - -/** - * @brief Disables all the interrupt sources. - */ -static inline void port_disable(void) { - - port_irq_sts = (syssts_t)1; -} - -/** - * @brief Disables the interrupt sources below kernel-level priority. - */ -static inline void port_suspend(void) { - - port_irq_sts = (syssts_t)1; -} - -/** - * @brief Enables all the interrupt sources. - */ -static inline void port_enable(void) { - - port_irq_sts = (syssts_t)0; -} - -/** - * @brief Enters an architecture-dependent IRQ-waiting mode. - * @details The function is meant to return when an interrupt becomes pending. - * The simplest implementation is an empty function or macro but this - * would not take advantage of architecture-specific power saving - * modes. - * @note Implemented as an inlined @p WFI instruction. - */ -static inline void port_wait_for_interrupt(void) { - - _sim_check_for_interrupts(); -} - -#endif /* _CHCORE_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/ports/SIMIA32/compilers/GCC/chtypes.h b/firmware/ChibiOS_16/os/rt/ports/SIMIA32/compilers/GCC/chtypes.h deleted file mode 100644 index b65b066d8f..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/SIMIA32/compilers/GCC/chtypes.h +++ /dev/null @@ -1,110 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file SIMIA32/compilers/GCC/chtypes.h - * @brief Simulator on IA32 port system types. - * - * @addtogroup SIMIA32_GCC_CORE - * @{ - */ - -#ifndef _CHTYPES_H_ -#define _CHTYPES_H_ - -#include -#include -#include - -/** - * @name Common constants - */ -/** - * @brief Generic 'false' boolean constant. - */ -#if !defined(FALSE) || defined(__DOXYGEN__) -#define FALSE 0 -#endif - -/** - * @brief Generic 'true' boolean constant. - */ -#if !defined(TRUE) || defined(__DOXYGEN__) -#define TRUE 1 -#endif -/** @} */ - -/** - * @name Derived generic types - * @{ - */ -typedef volatile int8_t vint8_t; /**< Volatile signed 8 bits. */ -typedef volatile uint8_t vuint8_t; /**< Volatile unsigned 8 bits. */ -typedef volatile int16_t vint16_t; /**< Volatile signed 16 bits. */ -typedef volatile uint16_t vuint16_t; /**< Volatile unsigned 16 bits. */ -typedef volatile int32_t vint32_t; /**< Volatile signed 32 bits. */ -typedef volatile uint32_t vuint32_t; /**< Volatile unsigned 32 bits. */ -/** @} */ - -/** - * @name Kernel types - * @{ - */ -typedef uint32_t rtcnt_t; /**< Realtime counter. */ -typedef uint64_t rttime_t; /**< Realtime accumulator. */ -typedef uint32_t syssts_t; /**< System status word. */ -typedef uint8_t tmode_t; /**< Thread flags. */ -typedef uint8_t tstate_t; /**< Thread state. */ -typedef uint8_t trefs_t; /**< Thread references counter. */ -typedef uint8_t tslices_t; /**< Thread time slices counter.*/ -typedef uint32_t tprio_t; /**< Thread priority. */ -typedef int32_t msg_t; /**< Inter-thread message. */ -typedef int32_t eventid_t; /**< Numeric event identifier. */ -typedef uint32_t eventmask_t; /**< Mask of event identifiers. */ -typedef uint32_t eventflags_t; /**< Mask of event flags. */ -typedef int32_t cnt_t; /**< Generic signed counter. */ -typedef uint32_t ucnt_t; /**< Generic unsigned counter. */ -/** @} */ - -/** - * @brief ROM constant modifier. - * @note It is set to use the "const" keyword in this port. - */ -#define ROMCONST const - -/** - * @brief Makes functions not inlineable. - * @note If the compiler does not support such attribute then the - * realtime counter precision could be degraded. - */ -#define NOINLINE __attribute__((noinline)) - -/** - * @brief Optimized thread function declaration macro. - */ -#define PORT_THD_FUNCTION(tname, arg) void tname(void *arg) - -/** - * @brief Packed variable specifier. - */ -#define PACKED_VAR __attribute__((packed)) - -#endif /* _CHTYPES_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/ports/SIMIA32/compilers/GCC/port.mk b/firmware/ChibiOS_16/os/rt/ports/SIMIA32/compilers/GCC/port.mk deleted file mode 100644 index 30e23e6c81..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/SIMIA32/compilers/GCC/port.mk +++ /dev/null @@ -1,7 +0,0 @@ -# List of the ChibiOS/RT SIMIA32 port files. -PORTSRC = ${CHIBIOS}/os/rt/ports/SIMIA32/chcore.c - -PORTASM = - -PORTINC = ${CHIBIOS}/os/rt/ports/SIMIA32/compilers/GCC \ - ${CHIBIOS}/os/rt/ports/SIMIA32 diff --git a/firmware/ChibiOS_16/os/rt/ports/e200/chcore.c b/firmware/ChibiOS_16/os/rt/ports/e200/chcore.c deleted file mode 100644 index 17a84ced33..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/e200/chcore.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file e200/chcore.c - * @brief Power e200 port code. - * - * @addtogroup PPC_CORE - * @{ - */ - -#include "ch.h" - -/*===========================================================================*/ -/* Module local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/ports/e200/chcore.h b/firmware/ChibiOS_16/os/rt/ports/e200/chcore.h deleted file mode 100644 index 3efb037196..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/e200/chcore.h +++ /dev/null @@ -1,599 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file PPC/chcore.h - * @brief Power e200 port macros and structures. - * - * @addtogroup PPC_CORE - * @{ - */ - -#ifndef _CHCORE_H_ -#define _CHCORE_H_ - -#include "intc.h" - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @name Architecture and Compiler - * @{ - */ -/** - * @brief Macro defining an PPC architecture. - */ -#define PORT_ARCHITECTURE_PPC - -/** - * @brief Macro defining the specific PPC architecture. - */ -#define PORT_ARCHITECTURE_PPC_E200 - -/** - * @brief Name of the implemented architecture. - */ -#define PORT_ARCHITECTURE_NAME "Power Architecture" - -/** - * @brief Compiler name and version. - */ -#if defined(__GNUC__) || defined(__DOXYGEN__) -#define PORT_COMPILER_NAME "GCC " __VERSION__ - -#elif defined(__MWERKS__) -#define PORT_COMPILER_NAME "CW" - -#else -#error "unsupported compiler" -#endif - -/** - * @brief This port supports a realtime counter. - */ -#define PORT_SUPPORTS_RT FALSE -/** @} */ - -/** - * @name E200 core variants - * @{ - */ -#define PPC_VARIANT_e200z0 200 -#define PPC_VARIANT_e200z2 202 -#define PPC_VARIANT_e200z3 203 -#define PPC_VARIANT_e200z4 204 -/** @} */ - -/* Inclusion of the PPC implementation specific parameters.*/ -#include "ppcparams.h" -#include "vectors.h" - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Stack size for the system idle thread. - * @details This size depends on the idle thread implementation, usually - * the idle thread should take no more space than those reserved - * by @p PORT_INT_REQUIRED_STACK. - * @note In this port it is set to 32 because the idle thread does have - * a stack frame when compiling without optimizations. You may - * reduce this value to zero when compiling with optimizations. - */ -#if !defined(PORT_IDLE_THREAD_STACK_SIZE) || defined(__DOXYGEN__) -#define PORT_IDLE_THREAD_STACK_SIZE 32 -#endif - -/** - * @brief Per-thread stack overhead for interrupts servicing. - * @details This constant is used in the calculation of the correct working - * area size. - * @note In this port this value is conservatively is set to 256 because - * there is no separate interrupts stack (yet). - */ -#if !defined(PORT_INT_REQUIRED_STACK) || defined(__DOXYGEN__) -#define PORT_INT_REQUIRED_STACK 256 -#endif - -/** - * @brief Enables an alternative timer implementation. - * @details Usually the port uses a timer interface defined in the file - * @p chcore_timer.h, if this option is enabled then the file - * @p chcore_timer_alt.h is included instead. - */ -#if !defined(PORT_USE_ALT_TIMER) || defined(__DOXYGEN__) -#define PORT_USE_ALT_TIMER FALSE -#endif - -/** - * @brief Use VLE instruction set. - * @note This parameter is usually set in the Makefile. - */ -#if !defined(PPC_USE_VLE) || defined(__DOXYGEN__) -#define PPC_USE_VLE TRUE -#endif - -/** - * @brief Enables the use of the @p WFI instruction. - */ -#if !defined(PPC_ENABLE_WFI_IDLE) || defined(__DOXYGEN__) -#define PPC_ENABLE_WFI_IDLE FALSE -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if PPC_USE_VLE && !PPC_SUPPORTS_VLE -#error "the selected MCU does not support VLE instructions set" -#endif - -#if !PPC_USE_VLE && !PPC_SUPPORTS_BOOKE -#error "the selected MCU does not support BookE instructions set" -#endif - -/** - * @brief Name of the architecture variant. - */ -#if (PPC_VARIANT == PPC_VARIANT_e200z0) || defined(__DOXYGEN__) -#define PORT_CORE_VARIANT_NAME "e200z0" -#elif PPC_VARIANT == PPC_VARIANT_e200z2 -#define PORT_CORE_VARIANT_NAME "e200z2" -#elif PPC_VARIANT == PPC_VARIANT_e200z3 -#define PORT_CORE_VARIANT_NAME "e200z3" -#elif PPC_VARIANT == PPC_VARIANT_e200z4 -#define PORT_CORE_VARIANT_NAME "e200z4" -#else -#error "unknown or unsupported PowerPC variant specified" -#endif - -/** - * @brief Port-specific information string. - */ -#if PPC_USE_VLE -#define PORT_INFO "VLE mode" -#else -#define PORT_INFO "Book-E mode" -#endif - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/* The following code is not processed when the file is included from an - asm module.*/ -#if !defined(_FROM_ASM_) - -/** - * @brief Type of stack and memory alignment enforcement. - * @note In this architecture the stack alignment is enforced to 64 bits. - */ -typedef uint64_t stkalign_t; - -/** - * @brief Generic PPC register. - */ -typedef void *regppc_t; - -/** - * @brief Mandatory part of a stack frame. - */ -struct port_eabi_frame { - uint32_t slink; /**< Stack back link. */ - uint32_t shole; /**< Stack hole for LR storage. */ -}; - -/** - * @brief Interrupt saved context. - * @details This structure represents the stack frame saved during a - * preemption-capable interrupt handler. - * @note R2 and R13 are not saved because those are assumed to be immutable - * during the system life cycle. - */ -struct port_extctx { - struct port_eabi_frame frame; - /* Start of the e_stmvsrrw frame (offset 8).*/ - regppc_t pc; - regppc_t msr; - /* Start of the e_stmvsprw frame (offset 16).*/ - regppc_t cr; - regppc_t lr; - regppc_t ctr; - regppc_t xer; - /* Start of the e_stmvgprw frame (offset 32).*/ - regppc_t r0; - regppc_t r3; - regppc_t r4; - regppc_t r5; - regppc_t r6; - regppc_t r7; - regppc_t r8; - regppc_t r9; - regppc_t r10; - regppc_t r11; - regppc_t r12; - regppc_t padding; - }; - -/** - * @brief System saved context. - * @details This structure represents the inner stack frame during a context - * switching. - * @note R2 and R13 are not saved because those are assumed to be immutable - * during the system life cycle. - * @note LR is stored in the caller context so it is not present in this - * structure. - */ -struct port_intctx { - regppc_t cr; /* Part of it is not volatile... */ - regppc_t r14; - regppc_t r15; - regppc_t r16; - regppc_t r17; - regppc_t r18; - regppc_t r19; - regppc_t r20; - regppc_t r21; - regppc_t r22; - regppc_t r23; - regppc_t r24; - regppc_t r25; - regppc_t r26; - regppc_t r27; - regppc_t r28; - regppc_t r29; - regppc_t r30; - regppc_t r31; - regppc_t padding; -}; - -/** - * @brief Platform dependent part of the @p thread_t structure. - * @details This structure usually contains just the saved stack pointer - * defined as a pointer to a @p port_intctx structure. - */ -struct context { - struct port_intctx *sp; -}; - -#endif /* !defined(_FROM_ASM_) */ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @brief Platform dependent part of the @p chThdCreateI() API. - * @details This code usually setup the context switching frame represented - * by an @p port_intctx structure. - */ -#define PORT_SETUP_CONTEXT(tp, workspace, wsize, pf, arg) { \ - uint8_t *sp = (uint8_t *)(workspace) + \ - (wsize) - \ - sizeof(struct port_eabi_frame); \ - ((struct port_eabi_frame *)sp)->slink = 0; \ - ((struct port_eabi_frame *)sp)->shole = (uint32_t)_port_thread_start; \ - (tp)->p_ctx.sp = (struct port_intctx *)(sp - sizeof(struct port_intctx)); \ - (tp)->p_ctx.sp->r31 = (regppc_t)(arg); \ - (tp)->p_ctx.sp->r30 = (regppc_t)(pf); \ -} - -/** - * @brief Computes the thread working area global size. - * @note There is no need to perform alignments in this macro. - */ -#define PORT_WA_SIZE(n) (sizeof(struct port_intctx) + \ - sizeof(struct port_extctx) + \ - ((size_t)(n)) + ((size_t)(PORT_INT_REQUIRED_STACK))) - -/** - * @brief IRQ prologue code. - * @details This macro must be inserted at the start of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_PROLOGUE() - -/** - * @brief IRQ epilogue code. - * @details This macro must be inserted at the end of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_EPILOGUE() - -/** - * @brief IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_IRQ_HANDLER(id) void id(void) - -/** - * @brief Fast IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_FAST_IRQ_HANDLER(id) void id(void) - -/** - * @brief Priority level verification macro. - */ -#define PORT_IRQ_IS_VALID_PRIORITY(n) \ - (((n) >= 0U) && ((n) < INTC_PRIORITY_LEVELS)) - -/** - * @brief Priority level verification macro. - */ -#define PORT_IRQ_IS_VALID_KERNEL_PRIORITY(n) \ - (((n) >= 0U) && ((n) < INTC_PRIORITY_LEVELS)) - -/** - * @brief Performs a context switch between two threads. - * @details This is the most critical code in any port, this function - * is responsible for the context switch between 2 threads. - * @note The implementation of this code affects directly the context - * switch performance so optimize here as much as you can. - * - * @param[in] ntp the thread to be switched in - * @param[in] otp the thread to be switched out - */ -#if !CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__) -#define port_switch(ntp, otp) _port_switch(ntp, otp) -#else -#define port_switch(ntp, otp) { \ - register struct port_intctx *sp asm ("%r1"); \ - if ((stkalign_t *)(sp - 1) < otp->p_stklimit) \ - chSysHalt("stack overflow"); \ - _port_switch(ntp, otp); \ -} -#endif - -/** - * @brief Writes to a special register. - * - * @param[in] spr special register number - * @param[in] val value to be written, must be an automatic variable - */ -#define port_write_spr(spr, val) \ - asm volatile ("mtspr %[p0], %[p1]" : : [p0] "n" (spr), [p1] "r" (val)) - -/** - * @brief Writes to a special register. - * - * @param[in] spr special register number - * @param[in] val returned value, must be an automatic variable - */ -#define port_read_spr(spr, val) \ - asm volatile ("mfspr %[p0], %[p1]" : [p0] "=r" (val) : [p1] "n" (spr)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/* The following code is not processed when the file is included from an - asm module.*/ -#if !defined(_FROM_ASM_) - -#ifdef __cplusplus -extern "C" { -#endif - void _port_switch(thread_t *ntp, thread_t *otp); - void _port_thread_start(void); -#ifdef __cplusplus -} -#endif - -#endif /* !defined(_FROM_ASM_) */ - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -/* The following code is not processed when the file is included from an - asm module.*/ -#if !defined(_FROM_ASM_) - -/** - * @brief Kernel port layer initialization. - * @details IVOR4 and IVOR10 initialization. - */ -static inline void port_init(void) { - uint32_t n; - unsigned i; - - /* Initializing the SPRG0 register to zero, it is required for interrupts - handling.*/ - n = 0; - port_write_spr(272, n); - -#if PPC_SUPPORTS_IVORS - { - /* The CPU supports IVOR registers, the kernel requires IVOR4 and IVOR10 - and the initialization is performed here.*/ - extern void _IVOR4(void); - port_write_spr(404, _IVOR4); - -#if PPC_SUPPORTS_DECREMENTER - extern void _IVOR10(void); - port_write_spr(410, _IVOR10); -#endif - } -#endif - - /* INTC initialization, software vector mode, 4 bytes vectors, starting - at priority 0.*/ - INTC_BCR = 0; - for (i = 0; i < PPC_CORE_NUMBER; i++) { - INTC_CPR(i) = 0; - INTC_IACKR(i) = (uint32_t)_vectors; - } -} - -/** - * @brief Returns a word encoding the current interrupts status. - * - * @return The interrupts status. - */ -static inline syssts_t port_get_irq_status(void) { - uint32_t sts; - - asm volatile ("mfmsr %[p0]" : [p0] "=r" (sts) :); - return sts; -} - -/** - * @brief Checks the interrupt status. - * - * @param[in] sts the interrupt status word - * - * @return The interrupt status. - * @retvel false the word specified a disabled interrupts status. - * @retvel true the word specified an enabled interrupts status. - */ -static inline bool port_irq_enabled(syssts_t sts) { - - return (bool)((sts & (1 << 15)) != 0); -} - -/** - * @brief Determines the current execution context. - * - * @return The execution context. - * @retval false not running in ISR mode. - * @retval true running in ISR mode. - */ -static inline bool port_is_isr_context(void) { - uint32_t sprg0; - - /* The SPRG0 register is increased before entering interrupt handlers and - decreased at the end.*/ - port_read_spr(272, sprg0); - return (bool)(sprg0 > 0); -} - -/** - * @brief Kernel-lock action. - * @note Implemented as global interrupt disable. - */ -static inline void port_lock(void) { - - asm volatile ("wrteei 0" : : : "memory"); -} - -/** - * @brief Kernel-unlock action. - * @note Implemented as global interrupt enable. - */ -static inline void port_unlock(void) { - - asm volatile("wrteei 1" : : : "memory"); -} - -/** - * @brief Kernel-lock action from an interrupt handler. - * @note Implementation not needed. - */ -static inline void port_lock_from_isr(void) { - -} - -/** - * @brief Kernel-unlock action from an interrupt handler. - * @note Implementation not needed. - */ -static inline void port_unlock_from_isr(void) { - -} - -/** - * @brief Disables all the interrupt sources. - * @note Implemented as global interrupt disable. - */ -static inline void port_disable(void) { - - asm volatile ("wrteei 0" : : : "memory"); -} - -/** - * @brief Disables the interrupt sources below kernel-level priority. - * @note Same as @p port_disable() in this port, there is no difference - * between the two states. - */ -static inline void port_suspend(void) { - - asm volatile ("wrteei 0" : : : "memory"); -} - -/** - * @brief Enables all the interrupt sources. - * @note Implemented as global interrupt enable. - */ -static inline void port_enable(void) { - - asm volatile ("wrteei 1" : : : "memory"); -} - -/** - * @brief Enters an architecture-dependent IRQ-waiting mode. - * @details The function is meant to return when an interrupt becomes pending. - * The simplest implementation is an empty function or macro but this - * would not take advantage of architecture-specific power saving - * modes. - * @note Implemented as an inlined @p wait instruction. - */ -static inline void port_wait_for_interrupt(void) { - -#if PPC_ENABLE_WFI_IDLE - asm volatile ("wait" : : : "memory"); -#endif -} - -/** - * @brief Returns the current value of the realtime counter. - * - * @return The realtime counter value. - */ -static inline rtcnt_t port_rt_get_counter_value(void) { - - return 0; -} - -#endif /* !defined(_FROM_ASM_) */ - -/*===========================================================================*/ -/* Module late inclusions. */ -/*===========================================================================*/ - -#if !defined(_FROM_ASM_) - -#if CH_CFG_ST_TIMEDELTA > 0 -#if !PORT_USE_ALT_TIMER -#include "chcore_timer.h" -#else /* PORT_USE_ALT_TIMER */ -#include "chcore_timer_alt.h" -#endif /* PORT_USE_ALT_TIMER */ -#endif /* CH_CFG_ST_TIMEDELTA > 0 */ - -#endif /* !defined(_FROM_ASM_) */ - -#endif /* _CHCORE_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/ports/e200/compilers/CW/chcoreasm.s b/firmware/ChibiOS_16/os/rt/ports/e200/compilers/CW/chcoreasm.s deleted file mode 100644 index 8a6a00634c..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/e200/compilers/CW/chcoreasm.s +++ /dev/null @@ -1,105 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file e200/compilers/GCC/chcoreasm.s - * @brief Power Architecture port low level code. - * - * @addtogroup PPC_GCC_CORE - * @{ - */ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -#if !defined(FALSE) || defined(__DOXYGEN__) -#define FALSE 0 -#endif - -#if !defined(TRUE) || defined(__DOXYGEN__) -#define TRUE 1 -#endif - -/*===========================================================================*/ -/* Code section. */ -/*===========================================================================*/ - -/* - * Imports the PPC configuration headers. - */ -#define _FROM_ASM_ -#include "chconf.h" -#include "chcore.h" - -#if !defined(__DOXYGEN__) - - .extern chThdExit - -#if PPC_USE_VLE == TRUE - .section .text_vle, 16 - - .align 2 - .globl _port_switch - .type _port_switch, @function -_port_switch: - e_subi r1, r1, 80 - se_mflr r0 - e_stw r0, 84(r1) - mfcr r0 - se_stw r0, 0(r1) - e_stmw r14, 4(r1) - - se_stw r1, 12(r4) - se_lwz r1, 12(r3) - - e_lmw r14, 4(r1) - se_lwz r0, 0(r1) - mtcr r0 - e_lwz r0, 84(r1) - se_mtlr r0 - e_addi r1, r1, 80 - se_blr - - .align 2 - .globl _port_thread_start - .type _port_thread_start, @function -_port_thread_start: -#if CH_DBG_SYSTEM_STATE_CHECK - bl _dbg_check_unlock -#endif -#if CH_DBG_STATISTICS - bl _stats_stop_measure_crit_thd -#endif - wrteei 1 - mr r3, r31 - mtctr r30 - se_bctrl - se_li r0, 0 - e_bl chThdExit - -#else /* PPC_USE_VLE == FALSE */ - -#error "non-VLE mode not yet implemented" - -#endif /* PPC_USE_VLE == FALSE */ - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/ports/e200/compilers/CW/chtypes.h b/firmware/ChibiOS_16/os/rt/ports/e200/compilers/CW/chtypes.h deleted file mode 100644 index 604b83eb0c..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/e200/compilers/CW/chtypes.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file e200/compilers/CW/chtypes.h - * @brief Power e200 port system types. - * - * @addtogroup PPC_CW_CORE - * @{ - */ - -#ifndef _CHTYPES_H_ -#define _CHTYPES_H_ - -#include -#include -#include - -/** - * @name Common constants - */ -/** - * @brief Generic 'false' boolean constant. - */ -#if !defined(FALSE) || defined(__DOXYGEN__) -#define FALSE 0 -#endif - -/** - * @brief Generic 'true' boolean constant. - */ -#if !defined(TRUE) || defined(__DOXYGEN__) -#define TRUE 1 -#endif -/** @} */ - -/** - * @name Kernel types - * @{ - */ -typedef uint32_t rtcnt_t; /**< Realtime counter. */ -typedef uint64_t rttime_t; /**< Realtime accumulator. */ -typedef uint32_t syssts_t; /**< System status word. */ -typedef uint8_t tmode_t; /**< Thread flags. */ -typedef uint8_t tstate_t; /**< Thread state. */ -typedef uint8_t trefs_t; /**< Thread references counter. */ -typedef uint8_t tslices_t; /**< Thread time slices counter.*/ -typedef uint32_t tprio_t; /**< Thread priority. */ -typedef int32_t msg_t; /**< Inter-thread message. */ -typedef int32_t eventid_t; /**< Numeric event identifier. */ -typedef uint32_t eventmask_t; /**< Mask of event identifiers. */ -typedef uint32_t eventflags_t; /**< Mask of event flags. */ -typedef int32_t cnt_t; /**< Generic signed counter. */ -typedef uint32_t ucnt_t; /**< Generic unsigned counter. */ -/** @} */ - -/** - * @brief ROM constant modifier. - * @note It is set to use the "const" keyword in this port. - */ -#define ROMCONST const - -/** - * @brief Makes functions not inlineable. - * @note If the compiler does not support such attribute then the - * realtime counter precision could be degraded. - */ -#define NOINLINE __attribute__((noinline)) - -/** - * @brief Optimized thread function declaration macro. - */ -#define PORT_THD_FUNCTION(tname, arg) void tname(void *arg) - -#endif /* _CHTYPES_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/ports/e200/compilers/CW/ivor.s b/firmware/ChibiOS_16/os/rt/ports/e200/compilers/CW/ivor.s deleted file mode 100644 index 48f282c6aa..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/e200/compilers/CW/ivor.s +++ /dev/null @@ -1,204 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file ivor.s - * @brief Kernel ISRs. - * - * @addtogroup PPC_CORE - * @{ - */ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -#if !defined(FALSE) || defined(__DOXYGEN__) -#define FALSE 0 -#endif - -#if !defined(TRUE) || defined(__DOXYGEN__) -#define TRUE 1 -#endif - -/*===========================================================================*/ -/* Code section. */ -/*===========================================================================*/ - -/* - * Imports the PPC configuration headers. - */ -#define _FROM_ASM_ -#include "chconf.h" -#include "chcore.h" - -#if !defined(__DOXYGEN__) - - .extern _stats_start_measure_crit_thd - .extern _stats_stop_measure_crit_thd - .extern _dbg_check_lock - .extern _dbg_check_unlock - .extern chSchIsPreemptionRequired - .extern chSchDoReschedule - .extern chSysTimerHandlerI - - .section .handlers, text_vle - -#if PPC_USE_VLE == TRUE - -#if PPC_SUPPORTS_DECREMENTER - /* - * _IVOR10 handler (Book-E decrementer). - */ - .align 16 - .globl _IVOR10 - .type _IVOR10, @function -_IVOR10: - /* Saving the external context (port_extctx structure).*/ - e_stwu r1, -80(r1) - e_stmvsrrw 8(r1) /* Saves PC, MSR. */ - e_stmvsprw 16(r1) /* Saves CR, LR, CTR, XER. */ - e_stmvgprw 32(r1) /* Saves GPR0, GPR3...GPR12. */ - - /* Increasing the SPGR0 register.*/ - mfspr r0, 272 - se_addi r0, 1 - mtspr 272, r0 - - /* Reset DIE bit in TSR register.*/ - e_lis r3, 0x0800 /* DIS bit mask. */ - mtspr 336, r3 /* TSR register. */ - - /* Restoring pre-IRQ MSR register value.*/ - mfSRR1 r0 -#if !PPC_USE_IRQ_PREEMPTION - /* No preemption, keeping EE disabled.*/ - se_bclri r0, 16 /* EE = bit 16. */ -#endif - mtMSR r0 - -#if CH_DBG_SYSTEM_STATE_CHECK - bl _dbg_check_enter_isr - bl _dbg_check_lock_from_isr -#endif - /* System tick handler invocation.*/ - e_bl chSysTimerHandlerI -#if CH_DBG_SYSTEM_STATE_CHECK - bl _dbg_check_unlock_from_isr - bl _dbg_check_leave_isr -#endif - -#if PPC_USE_IRQ_PREEMPTION - /* Prevents preemption again.*/ - wrteei 0 -#endif - - /* Jumps to the common IVOR epilogue code.*/ - se_b _ivor_exit -#endif /* PPC_SUPPORTS_DECREMENTER */ - - /* - * _IVOR4 handler (Book-E external interrupt). - */ - .align 16 - .globl _IVOR4 - .type _IVOR4, @function -_IVOR4: - /* Saving the external context (port_extctx structure).*/ - e_stwu r1, -80(r1) - e_stmvsrrw 8(r1) /* Saves PC, MSR. */ - e_stmvsprw 16(r1) /* Saves CR, LR, CTR, XER. */ - e_stmvgprw 32(r1) /* Saves GPR0, GPR3...GPR12. */ - - /* Increasing the SPGR0 register.*/ - mfspr r0, 272 - se_addi r0, 1 - mtspr 272, r0 - - /* Software vector address from the INTC register.*/ - e_lis r3, INTC_IACKR_ADDR@h - e_or2i r3, INTC_IACKR_ADDR@l /* IACKR register address. */ - se_lwz r3, 0(r3) /* IACKR register value. */ - se_lwz r3, 0(r3) - mtCTR r3 /* Software handler address. */ - - /* Restoring pre-IRQ MSR register value.*/ - mfSRR1 r0 -#if !PPC_USE_IRQ_PREEMPTION - /* No preemption, keeping EE disabled.*/ - se_bclri r0, 16 /* EE = bit 16. */ -#endif - mtMSR r0 - - /* Exectes the software handler.*/ - se_bctrl - -#if PPC_USE_IRQ_PREEMPTION - /* Prevents preemption again.*/ - wrteei 0 -#endif - - /* Informs the INTC that the interrupt has been served.*/ - mbar 0 - e_lis r3, INTC_EOIR_ADDR@h - e_or2i r3, INTC_EOIR_ADDR@l - se_stw r3, 0(r3) /* Writing any value should do. */ - - /* Common IVOR epilogue code, context restore.*/ - .globl _ivor_exit -_ivor_exit: - /* Decreasing the SPGR0 register.*/ - mfspr r0, 272 - se_subi r0, 1 - mtspr 272, r0 - -#if CH_DBG_STATISTICS - e_bl _stats_start_measure_crit_thd -#endif -#if CH_DBG_SYSTEM_STATE_CHECK - e_bl _dbg_check_lock -#endif - e_bl chSchIsPreemptionRequired - e_cmpli cr0, r3, 0 - se_beq .noresch - e_bl chSchDoReschedule -.noresch: -#if CH_DBG_SYSTEM_STATE_CHECK - e_bl _dbg_check_unlock -#endif -#if CH_DBG_STATISTICS - e_bl _stats_stop_measure_crit_thd -#endif - - /* Restoring the external context.*/ - e_lmvgprw 32(r1) /* Restores GPR0, GPR3...GPR12. */ - e_lmvsprw 16(r1) /* Restores CR, LR, CTR, XER. */ - e_lmvsrrw 8(r1) /* Restores PC, MSR. */ - e_addi r1, r1, 80 /* Back to the previous frame. */ - se_rfi - -#else /* PPC_USE_VLE == FALSE */ - -#error "non-VLE mode not yet implemented" - -#endif /* PPC_USE_VLE == FALSE */ - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/ports/e200/compilers/GCC/chcoreasm.s b/firmware/ChibiOS_16/os/rt/ports/e200/compilers/GCC/chcoreasm.s deleted file mode 100644 index 48e1ddbe63..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/e200/compilers/GCC/chcoreasm.s +++ /dev/null @@ -1,97 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file e200/compilers/GCC/chcoreasm.s - * @brief Power Architecture port low level code. - * - * @addtogroup PPC_GCC_CORE - * @{ - */ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -#if !defined(FALSE) || defined(__DOXYGEN__) -#define FALSE 0 -#endif - -#if !defined(TRUE) || defined(__DOXYGEN__) -#define TRUE 1 -#endif - -/*===========================================================================*/ -/* Code section. */ -/*===========================================================================*/ - -#define _FROM_ASM_ -#include "chconf.h" -#include "chcore.h" - -#if !defined(__DOXYGEN__) - -#if PPC_USE_VLE == TRUE - .section .text_vle, "ax" -#else - .section .text, "ax" -#endif - - .align 2 - .globl _port_switch - .type _port_switch, @function -_port_switch: - subi %sp, %sp, 80 - mflr %r0 - stw %r0, 84(%sp) - mfcr %r0 - stw %r0, 0(%sp) - stmw %r14, 4(%sp) - - stw %sp, 12(%r4) - lwz %sp, 12(%r3) - - lmw %r14, 4(%sp) - lwz %r0, 0(%sp) - mtcr %r0 - lwz %r0, 84(%sp) - mtlr %r0 - addi %sp, %sp, 80 - blr - - .align 2 - .globl _port_thread_start - .type _port_thread_start, @function -_port_thread_start: -#if CH_DBG_SYSTEM_STATE_CHECK - bl _dbg_check_unlock -#endif -#if CH_DBG_STATISTICS - bl _stats_stop_measure_crit_thd -#endif - wrteei 1 - mr %r3, %r31 - mtctr %r30 - bctrl - li %r0, 0 - bl chThdExit - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/ports/e200/compilers/GCC/chtypes.h b/firmware/ChibiOS_16/os/rt/ports/e200/compilers/GCC/chtypes.h deleted file mode 100644 index 248d5a1710..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/e200/compilers/GCC/chtypes.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file e200/compilers/GCC/chtypes.h - * @brief Power e200 port system types. - * - * @addtogroup PPC_GCC_CORE - * @{ - */ - -#ifndef _CHTYPES_H_ -#define _CHTYPES_H_ - -#include -#include -#include - -/** - * @name Common constants - */ -/** - * @brief Generic 'false' boolean constant. - */ -#if !defined(FALSE) || defined(__DOXYGEN__) -#define FALSE 0 -#endif - -/** - * @brief Generic 'true' boolean constant. - */ -#if !defined(TRUE) || defined(__DOXYGEN__) -#define TRUE 1 -#endif -/** @} */ - -/** - * @name Kernel types - * @{ - */ -typedef uint32_t rtcnt_t; /**< Realtime counter. */ -typedef uint64_t rttime_t; /**< Realtime accumulator. */ -typedef uint32_t syssts_t; /**< System status word. */ -typedef uint8_t tmode_t; /**< Thread flags. */ -typedef uint8_t tstate_t; /**< Thread state. */ -typedef uint8_t trefs_t; /**< Thread references counter. */ -typedef uint8_t tslices_t; /**< Thread time slices counter.*/ -typedef uint32_t tprio_t; /**< Thread priority. */ -typedef int32_t msg_t; /**< Inter-thread message. */ -typedef int32_t eventid_t; /**< Numeric event identifier. */ -typedef uint32_t eventmask_t; /**< Mask of event identifiers. */ -typedef uint32_t eventflags_t; /**< Mask of event flags. */ -typedef int32_t cnt_t; /**< Generic signed counter. */ -typedef uint32_t ucnt_t; /**< Generic unsigned counter. */ -/** @} */ - -/** - * @brief ROM constant modifier. - * @note It is set to use the "const" keyword in this port. - */ -#define ROMCONST const - -/** - * @brief Makes functions not inlineable. - * @note If the compiler does not support such attribute then the - * realtime counter precision could be degraded. - */ -#define NOINLINE __attribute__((noinline)) - -/** - * @brief Optimized thread function declaration macro. - */ -#define PORT_THD_FUNCTION(tname, arg) void tname(void *arg) - -#endif /* _CHTYPES_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/ports/e200/compilers/GCC/ivor.s b/firmware/ChibiOS_16/os/rt/ports/e200/compilers/GCC/ivor.s deleted file mode 100644 index 206c9f78b6..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/e200/compilers/GCC/ivor.s +++ /dev/null @@ -1,258 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file ivor.s - * @brief Kernel ISRs. - * - * @addtogroup PPC_CORE - * @{ - */ - -#if !defined(FALSE) || defined(__DOXYGEN__) -#define FALSE 0 -#endif - -#if !defined(TRUE) || defined(__DOXYGEN__) -#define TRUE 1 -#endif - -/* - * Imports the PPC configuration headers. - */ -#define _FROM_ASM_ -#include "chconf.h" -#include "chcore.h" - -#if !defined(__DOXYGEN__) - - .section .handlers, "ax" - -#if PPC_SUPPORTS_DECREMENTER - /* - * _IVOR10 handler (Book-E decrementer). - */ - .align 4 - .globl _IVOR10 - .type _IVOR10, @function -_IVOR10: - /* Saving the external context (port_extctx structure).*/ - stwu %sp, -80(%sp) -#if PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI - e_stmvsrrw 8(%sp) /* Saves PC, MSR. */ - e_stmvsprw 16(%sp) /* Saves CR, LR, CTR, XER. */ - e_stmvgprw 32(%sp) /* Saves GPR0, GPR3...GPR12. */ -#else /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */ - stw %r0, 32(%sp) /* Saves GPR0. */ - mfSRR0 %r0 - stw %r0, 8(%sp) /* Saves PC. */ - mfSRR1 %r0 - stw %r0, 12(%sp) /* Saves MSR. */ - mfCR %r0 - stw %r0, 16(%sp) /* Saves CR. */ - mfLR %r0 - stw %r0, 20(%sp) /* Saves LR. */ - mfCTR %r0 - stw %r0, 24(%sp) /* Saves CTR. */ - mfXER %r0 - stw %r0, 28(%sp) /* Saves XER. */ - stw %r3, 36(%sp) /* Saves GPR3...GPR12. */ - stw %r4, 40(%sp) - stw %r5, 44(%sp) - stw %r6, 48(%sp) - stw %r7, 52(%sp) - stw %r8, 56(%sp) - stw %r9, 60(%sp) - stw %r10, 64(%sp) - stw %r11, 68(%sp) - stw %r12, 72(%sp) -#endif /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */ - - /* Increasing the SPGR0 register.*/ - mfspr %r0, 272 - eaddi %r0, %r0, 1 - mtspr 272, %r0 - - /* Reset DIE bit in TSR register.*/ - lis %r3, 0x0800 /* DIS bit mask. */ - mtspr 336, %r3 /* TSR register. */ - - /* Restoring pre-IRQ MSR register value.*/ - mfSRR1 %r0 -#if !PPC_USE_IRQ_PREEMPTION - /* No preemption, keeping EE disabled.*/ - se_bclri %r0, 16 /* EE = bit 16. */ -#endif - mtMSR %r0 - -#if CH_DBG_SYSTEM_STATE_CHECK - bl _dbg_check_enter_isr - bl _dbg_check_lock_from_isr -#endif - /* System tick handler invocation.*/ - bl chSysTimerHandlerI -#if CH_DBG_SYSTEM_STATE_CHECK - bl _dbg_check_unlock_from_isr - bl _dbg_check_leave_isr -#endif - -#if PPC_USE_IRQ_PREEMPTION - /* Prevents preemption again.*/ - wrteei 0 -#endif - - /* Jumps to the common IVOR epilogue code.*/ - b _ivor_exit -#endif /* PPC_SUPPORTS_DECREMENTER */ - - /* - * _IVOR4 handler (Book-E external interrupt). - */ - .align 4 - .globl _IVOR4 - .type _IVOR4, @function -_IVOR4: - /* Saving the external context (port_extctx structure).*/ - stwu %sp, -80(%sp) -#if PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI - e_stmvsrrw 8(%sp) /* Saves PC, MSR. */ - e_stmvsprw 16(%sp) /* Saves CR, LR, CTR, XER. */ - e_stmvgprw 32(%sp) /* Saves GPR0, GPR3...GPR12. */ -#else /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */ - stw %r0, 32(%sp) /* Saves GPR0. */ - mfSRR0 %r0 - stw %r0, 8(%sp) /* Saves PC. */ - mfSRR1 %r0 - stw %r0, 12(%sp) /* Saves MSR. */ - mfCR %r0 - stw %r0, 16(%sp) /* Saves CR. */ - mfLR %r0 - stw %r0, 20(%sp) /* Saves LR. */ - mfCTR %r0 - stw %r0, 24(%sp) /* Saves CTR. */ - mfXER %r0 - stw %r0, 28(%sp) /* Saves XER. */ - stw %r3, 36(%sp) /* Saves GPR3...GPR12. */ - stw %r4, 40(%sp) - stw %r5, 44(%sp) - stw %r6, 48(%sp) - stw %r7, 52(%sp) - stw %r8, 56(%sp) - stw %r9, 60(%sp) - stw %r10, 64(%sp) - stw %r11, 68(%sp) - stw %r12, 72(%sp) -#endif /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */ - - /* Increasing the SPGR0 register.*/ - mfspr %r0, 272 - eaddi %r0, %r0, 1 - mtspr 272, %r0 - - /* Software vector address from the INTC register.*/ - lis %r3, INTC_IACKR_ADDR@h - ori %r3, %r3, INTC_IACKR_ADDR@l /* IACKR register address. */ - lwz %r3, 0(%r3) /* IACKR register value. */ - lwz %r3, 0(%r3) - mtCTR %r3 /* Software handler address. */ - - /* Restoring pre-IRQ MSR register value.*/ - mfSRR1 %r0 -#if !PPC_USE_IRQ_PREEMPTION - /* No preemption, keeping EE disabled.*/ - se_bclri %r0, 16 /* EE = bit 16. */ -#endif - mtMSR %r0 - - /* Exectes the software handler.*/ - bctrl - -#if PPC_USE_IRQ_PREEMPTION - /* Prevents preemption again.*/ - wrteei 0 -#endif - - /* Informs the INTC that the interrupt has been served.*/ - mbar 0 - lis %r3, INTC_EOIR_ADDR@h - ori %r3, %r3, INTC_EOIR_ADDR@l - stw %r3, 0(%r3) /* Writing any value should do. */ - - /* Common IVOR epilogue code, context restore.*/ - .globl _ivor_exit -_ivor_exit: - /* Decreasing the SPGR0 register.*/ - mfspr %r0, 272 - eaddi %r0, %r0, -1 - mtspr 272, %r0 - -#if CH_DBG_STATISTICS - bl _stats_start_measure_crit_thd -#endif -#if CH_DBG_SYSTEM_STATE_CHECK - bl _dbg_check_lock -#endif - bl chSchIsPreemptionRequired - cmpli cr0, %r3, 0 - beq cr0, .noresch - bl chSchDoReschedule -.noresch: -#if CH_DBG_SYSTEM_STATE_CHECK - bl _dbg_check_unlock -#endif -#if CH_DBG_STATISTICS - bl _stats_stop_measure_crit_thd -#endif - - /* Restoring the external context.*/ -#if PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI - e_lmvgprw 32(%sp) /* Restores GPR0, GPR3...GPR12. */ - e_lmvsprw 16(%sp) /* Restores CR, LR, CTR, XER. */ - e_lmvsrrw 8(%sp) /* Restores PC, MSR. */ -#else /*!(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */ - lwz %r3, 36(%sp) /* Restores GPR3...GPR12. */ - lwz %r4, 40(%sp) - lwz %r5, 44(%sp) - lwz %r6, 48(%sp) - lwz %r7, 52(%sp) - lwz %r8, 56(%sp) - lwz %r9, 60(%sp) - lwz %r10, 64(%sp) - lwz %r11, 68(%sp) - lwz %r12, 72(%sp) - lwz %r0, 8(%sp) - mtSRR0 %r0 /* Restores PC. */ - lwz %r0, 12(%sp) - mtSRR1 %r0 /* Restores MSR. */ - lwz %r0, 16(%sp) - mtCR %r0 /* Restores CR. */ - lwz %r0, 20(%sp) - mtLR %r0 /* Restores LR. */ - lwz %r0, 24(%sp) - mtCTR %r0 /* Restores CTR. */ - lwz %r0, 28(%sp) - mtXER %r0 /* Restores XER. */ - lwz %r0, 32(%sp) /* Restores GPR0. */ -#endif /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */ - addi %sp, %sp, 80 /* Back to the previous frame. */ - rfi - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/ports/e200/compilers/GCC/mk/port.mk b/firmware/ChibiOS_16/os/rt/ports/e200/compilers/GCC/mk/port.mk deleted file mode 100644 index 97b911f4a7..0000000000 --- a/firmware/ChibiOS_16/os/rt/ports/e200/compilers/GCC/mk/port.mk +++ /dev/null @@ -1,8 +0,0 @@ -# List of the ChibiOS/RT e200 generic port files. -PORTSRC = $(CHIBIOS)/os/rt/ports/e200/chcore.c - -PORTASM = $(CHIBIOS)/os/rt/ports/e200/compilers/GCC/ivor.s \ - $(CHIBIOS)/os/rt/ports/e200/compilers/GCC/chcoreasm.s - -PORTINC = $(CHIBIOS)/os/rt/ports/e200 \ - $(CHIBIOS)/os/rt/ports/e200/compilers/GCC diff --git a/firmware/ChibiOS_16/os/rt/rt.mk b/firmware/ChibiOS_16/os/rt/rt.mk deleted file mode 100644 index 14cd31b5bc..0000000000 --- a/firmware/ChibiOS_16/os/rt/rt.mk +++ /dev/null @@ -1,76 +0,0 @@ -# List of all the ChibiOS/RT kernel files, there is no need to remove the files -# from this list, you can disable parts of the kernel by editing chconf.h. -ifeq ($(USE_SMART_BUILD),yes) -CHCONF := $(strip $(shell cat chconf.h | egrep -e "define")) - -KERNSRC := $(CHIBIOS)/os/rt/src/chsys.c \ - $(CHIBIOS)/os/rt/src/chdebug.c \ - $(CHIBIOS)/os/rt/src/chvt.c \ - $(CHIBIOS)/os/rt/src/chschd.c \ - $(CHIBIOS)/os/rt/src/chthreads.c -ifneq ($(findstring CH_CFG_USE_TM TRUE,$(CHCONF)),) -KERNSRC += $(CHIBIOS)/os/rt/src/chtm.c -endif -ifneq ($(findstring CH_DBG_STATISTICS TRUE,$(CHCONF)),) -KERNSRC += $(CHIBIOS)/os/rt/src/chstats.c -endif -ifneq ($(findstring CH_CFG_USE_DYNAMIC TRUE,$(CHCONF)),) -KERNSRC += $(CHIBIOS)/os/rt/src/chdynamic.c -endif -ifneq ($(findstring CH_CFG_USE_REGISTRY TRUE,$(CHCONF)),) -KERNSRC += $(CHIBIOS)/os/rt/src/chregistry.c -endif -ifneq ($(findstring CH_CFG_USE_SEMAPHORES TRUE,$(CHCONF)),) -KERNSRC += $(CHIBIOS)/os/rt/src/chsem.c -endif -ifneq ($(findstring CH_CFG_USE_MUTEXES TRUE,$(CHCONF)),) -KERNSRC += $(CHIBIOS)/os/rt/src/chmtx.c -endif -ifneq ($(findstring CH_CFG_USE_CONDVARS TRUE,$(CHCONF)),) -KERNSRC += $(CHIBIOS)/os/rt/src/chcond.c -endif -ifneq ($(findstring CH_CFG_USE_EVENTS TRUE,$(CHCONF)),) -KERNSRC += $(CHIBIOS)/os/rt/src/chevents.c -endif -ifneq ($(findstring CH_CFG_USE_MESSAGES TRUE,$(CHCONF)),) -KERNSRC += $(CHIBIOS)/os/rt/src/chmsg.c -endif -ifneq ($(findstring CH_CFG_USE_MAILBOXES TRUE,$(CHCONF)),) -KERNSRC += $(CHIBIOS)/os/rt/src/chmboxes.c -endif -ifneq ($(findstring CH_CFG_USE_QUEUES TRUE,$(CHCONF)),) -KERNSRC += $(CHIBIOS)/os/rt/src/chqueues.c -endif -ifneq ($(findstring CH_CFG_USE_MEMCORE TRUE,$(CHCONF)),) -KERNSRC += $(CHIBIOS)/os/rt/src/chmemcore.c -endif -ifneq ($(findstring CH_CFG_USE_HEAP TRUE,$(CHCONF)),) -KERNSRC += $(CHIBIOS)/os/rt/src/chheap.c -endif -ifneq ($(findstring CH_CFG_USE_MEMPOOLS TRUE,$(CHCONF)),) -KERNSRC += $(CHIBIOS)/os/rt/src/chmempools.c -endif -else -KERNSRC = $(CHIBIOS)/os/rt/src/chsys.c \ - $(CHIBIOS)/os/rt/src/chdebug.c \ - $(CHIBIOS)/os/rt/src/chvt.c \ - $(CHIBIOS)/os/rt/src/chschd.c \ - $(CHIBIOS)/os/rt/src/chthreads.c \ - $(CHIBIOS)/os/rt/src/chtm.c \ - $(CHIBIOS)/os/rt/src/chstats.c \ - $(CHIBIOS)/os/rt/src/chdynamic.c \ - $(CHIBIOS)/os/rt/src/chregistry.c \ - $(CHIBIOS)/os/rt/src/chsem.c \ - $(CHIBIOS)/os/rt/src/chmtx.c \ - $(CHIBIOS)/os/rt/src/chcond.c \ - $(CHIBIOS)/os/rt/src/chevents.c \ - $(CHIBIOS)/os/rt/src/chmsg.c \ - $(CHIBIOS)/os/rt/src/chmboxes.c \ - $(CHIBIOS)/os/rt/src/chqueues.c \ - $(CHIBIOS)/os/rt/src/chmemcore.c \ - $(CHIBIOS)/os/rt/src/chheap.c \ - $(CHIBIOS)/os/rt/src/chmempools.c -endif - -# Required include directories -KERNINC = $(CHIBIOS)/os/rt/include diff --git a/firmware/ChibiOS_16/os/rt/src/chcond.c b/firmware/ChibiOS_16/os/rt/src/chcond.c deleted file mode 100644 index 731e4ce998..0000000000 --- a/firmware/ChibiOS_16/os/rt/src/chcond.c +++ /dev/null @@ -1,323 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ -/* - Concepts and parts of this file have been contributed by Leon Woestenberg. - */ - -/** - * @file chcond.c - * @brief Condition Variables code. - * - * @addtogroup condvars - * @details This module implements the Condition Variables mechanism. Condition - * variables are an extensions to the mutex subsystem and cannot - * work alone. - *

Operation mode

- * The condition variable is a synchronization object meant to be - * used inside a zone protected by a mutex. Mutexes and condition - * variables together can implement a Monitor construct. - * @pre In order to use the condition variable APIs the @p CH_CFG_USE_CONDVARS - * option must be enabled in @p chconf.h. - * @{ - */ - -#include "ch.h" - -#if (CH_CFG_USE_CONDVARS == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Module local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -/** - * @brief Initializes s @p condition_variable_t structure. - * - * @param[out] cp pointer to a @p condition_variable_t structure - * - * @init - */ -void chCondObjectInit(condition_variable_t *cp) { - - chDbgCheck(cp != NULL); - - queue_init(&cp->c_queue); -} - -/** - * @brief Signals one thread that is waiting on the condition variable. - * - * @param[in] cp pointer to the @p condition_variable_t structure - * - * @api - */ -void chCondSignal(condition_variable_t *cp) { - - chDbgCheck(cp != NULL); - - chSysLock(); - if (queue_notempty(&cp->c_queue)) { - chSchWakeupS(queue_fifo_remove(&cp->c_queue), MSG_OK); - } - chSysUnlock(); -} - -/** - * @brief Signals one thread that is waiting on the condition variable. - * @post This function does not reschedule so a call to a rescheduling - * function must be performed before unlocking the kernel. Note that - * interrupt handlers always reschedule on exit so an explicit - * reschedule must not be performed in ISRs. - * - * @param[in] cp pointer to the @p condition_variable_t structure - * - * @iclass - */ -void chCondSignalI(condition_variable_t *cp) { - - chDbgCheckClassI(); - chDbgCheck(cp != NULL); - - if (queue_notempty(&cp->c_queue)) { - thread_t *tp = queue_fifo_remove(&cp->c_queue); - tp->p_u.rdymsg = MSG_OK; - (void) chSchReadyI(tp); - } -} - -/** - * @brief Signals all threads that are waiting on the condition variable. - * - * @param[in] cp pointer to the @p condition_variable_t structure - * - * @api - */ -void chCondBroadcast(condition_variable_t *cp) { - - chSysLock(); - chCondBroadcastI(cp); - chSchRescheduleS(); - chSysUnlock(); -} - -/** - * @brief Signals all threads that are waiting on the condition variable. - * @post This function does not reschedule so a call to a rescheduling - * function must be performed before unlocking the kernel. Note that - * interrupt handlers always reschedule on exit so an explicit - * reschedule must not be performed in ISRs. - * - * @param[in] cp pointer to the @p condition_variable_t structure - * - * @iclass - */ -void chCondBroadcastI(condition_variable_t *cp) { - - chDbgCheckClassI(); - chDbgCheck(cp != NULL); - - /* Empties the condition variable queue and inserts all the threads into the - ready list in FIFO order. The wakeup message is set to @p MSG_RESET in - order to make a chCondBroadcast() detectable from a chCondSignal().*/ - while (queue_notempty(&cp->c_queue)) { - chSchReadyI(queue_fifo_remove(&cp->c_queue))->p_u.rdymsg = MSG_RESET; - } -} - -/** - * @brief Waits on the condition variable releasing the mutex lock. - * @details Releases the currently owned mutex, waits on the condition - * variable, and finally acquires the mutex again. All the sequence - * is performed atomically. - * @pre The invoking thread must have at least one owned mutex. - * - * @param[in] cp pointer to the @p condition_variable_t structure - * @return A message specifying how the invoking thread has been - * released from the condition variable. - * @retval MSG_OK if the condition variable has been signaled using - * @p chCondSignal(). - * @retval MSG_RESET if the condition variable has been signaled using - * @p chCondBroadcast(). - * - * @api - */ -msg_t chCondWait(condition_variable_t *cp) { - msg_t msg; - - chSysLock(); - msg = chCondWaitS(cp); - chSysUnlock(); - return msg; -} - -/** - * @brief Waits on the condition variable releasing the mutex lock. - * @details Releases the currently owned mutex, waits on the condition - * variable, and finally acquires the mutex again. All the sequence - * is performed atomically. - * @pre The invoking thread must have at least one owned mutex. - * - * @param[in] cp pointer to the @p condition_variable_t structure - * @return A message specifying how the invoking thread has been - * released from the condition variable. - * @retval MSG_OK if the condition variable has been signaled using - * @p chCondSignal(). - * @retval MSG_RESET if the condition variable has been signaled using - * @p chCondBroadcast(). - * - * @sclass - */ -msg_t chCondWaitS(condition_variable_t *cp) { - thread_t *ctp = currp; - mutex_t *mp; - msg_t msg; - - chDbgCheckClassS(); - chDbgCheck(cp != NULL); - chDbgAssert(ctp->p_mtxlist != NULL, "not owning a mutex"); - - /* Getting "current" mutex and releasing it.*/ - mp = chMtxGetNextMutexS(); - chMtxUnlockS(mp); - - /* Start waiting on the condition variable, on exit the mutex is taken - again.*/ - ctp->p_u.wtobjp = cp; - queue_prio_insert(ctp, &cp->c_queue); - chSchGoSleepS(CH_STATE_WTCOND); - msg = ctp->p_u.rdymsg; - chMtxLockS(mp); - - return msg; -} - -#if (CH_CFG_USE_CONDVARS_TIMEOUT == TRUE) || defined(__DOXYGEN__) -/** - * @brief Waits on the condition variable releasing the mutex lock. - * @details Releases the currently owned mutex, waits on the condition - * variable, and finally acquires the mutex again. All the sequence - * is performed atomically. - * @pre The invoking thread must have at least one owned mutex. - * @pre The configuration option @p CH_CFG_USE_CONDVARS_TIMEOUT must be enabled - * in order to use this function. - * @post Exiting the function because a timeout does not re-acquire the - * mutex, the mutex ownership is lost. - * - * @param[in] cp pointer to the @p condition_variable_t structure - * @param[in] time the number of ticks before the operation timeouts, the - * special values are handled as follow: - * - @a TIME_INFINITE no timeout. - * - @a TIME_IMMEDIATE this value is not allowed. - * . - * @return A message specifying how the invoking thread has been - * released from the condition variable. - * @retval MSG_OK if the condition variable has been signaled using - * @p chCondSignal(). - * @retval MSG_RESET if the condition variable has been signaled using - * @p chCondBroadcast(). - * @retval MSG_TIMEOUT if the condition variable has not been signaled within - * the specified timeout. - * - * @api - */ -msg_t chCondWaitTimeout(condition_variable_t *cp, systime_t time) { - msg_t msg; - - chSysLock(); - msg = chCondWaitTimeoutS(cp, time); - chSysUnlock(); - - return msg; -} - -/** - * @brief Waits on the condition variable releasing the mutex lock. - * @details Releases the currently owned mutex, waits on the condition - * variable, and finally acquires the mutex again. All the sequence - * is performed atomically. - * @pre The invoking thread must have at least one owned mutex. - * @pre The configuration option @p CH_CFG_USE_CONDVARS_TIMEOUT must be enabled - * in order to use this function. - * @post Exiting the function because a timeout does not re-acquire the - * mutex, the mutex ownership is lost. - * - * @param[in] cp pointer to the @p condition_variable_t structure - * @param[in] time the number of ticks before the operation timeouts, the - * special values are handled as follow: - * - @a TIME_INFINITE no timeout. - * - @a TIME_IMMEDIATE this value is not allowed. - * . - * @return A message specifying how the invoking thread has been - * released from the condition variable. - * @retval MSG_OK if the condition variable has been signaled using - * @p chCondSignal(). - * @retval MSG_RESET if the condition variable has been signaled using - * @p chCondBroadcast(). - * @retval MSG_TIMEOUT if the condition variable has not been signaled within - * the specified timeout. - * - * @sclass - */ -msg_t chCondWaitTimeoutS(condition_variable_t *cp, systime_t time) { - mutex_t *mp; - msg_t msg; - - chDbgCheckClassS(); - chDbgCheck((cp != NULL) && (time != TIME_IMMEDIATE)); - chDbgAssert(currp->p_mtxlist != NULL, "not owning a mutex"); - - /* Getting "current" mutex and releasing it.*/ - mp = chMtxGetNextMutexS(); - chMtxUnlockS(mp); - - /* Start waiting on the condition variable, on exit the mutex is taken - again.*/ - currp->p_u.wtobjp = cp; - queue_prio_insert(currp, &cp->c_queue); - msg = chSchGoSleepTimeoutS(CH_STATE_WTCOND, time); - if (msg != MSG_TIMEOUT) { - chMtxLockS(mp); - } - - return msg; -} -#endif /* CH_CFG_USE_CONDVARS_TIMEOUT == TRUE */ - -#endif /* CH_CFG_USE_CONDVARS == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/src/chdebug.c b/firmware/ChibiOS_16/os/rt/src/chdebug.c deleted file mode 100644 index 3f5485fff2..0000000000 --- a/firmware/ChibiOS_16/os/rt/src/chdebug.c +++ /dev/null @@ -1,290 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chdebug.c - * @brief ChibiOS/RT Debug code. - * - * @addtogroup debug - * @details Debug APIs and services: - * - Runtime system state and call protocol check. The following - * panic messages can be generated: - * - SV#1, misplaced @p chSysDisable(). - * - Called from an ISR. - * - Called from a critical zone. - * . - * - SV#2, misplaced @p chSysSuspend() - * - Called from an ISR. - * - Called from a critical zone. - * . - * - SV#3, misplaced @p chSysEnable(). - * - Called from an ISR. - * - Called from a critical zone. - * . - * - SV#4, misplaced @p chSysLock(). - * - Called from an ISR. - * - Called from a critical zone. - * . - * - SV#5, misplaced @p chSysUnlock(). - * - Called from an ISR. - * - Not called from a critical zone. - * . - * - SV#6, misplaced @p chSysLockFromISR(). - * - Not called from an ISR. - * - Called from a critical zone. - * . - * - SV#7, misplaced @p chSysUnlockFromISR(). - * - Not called from an ISR. - * - Not called from a critical zone. - * . - * - SV#8, misplaced @p CH_IRQ_PROLOGUE(). - * - Not called at ISR begin. - * - Called from a critical zone. - * . - * - SV#9, misplaced @p CH_IRQ_EPILOGUE(). - * - @p CH_IRQ_PROLOGUE() missing. - * - Not called at ISR end. - * - Called from a critical zone. - * . - * - SV#10, misplaced I-class function. - * - I-class function not called from within a critical zone. - * . - * - SV#11, misplaced S-class function. - * - S-class function not called from within a critical zone. - * - Called from an ISR. - * . - * - Trace buffer. - * - Parameters check. - * - Kernel assertions. - * - Kernel panics. - * . - * @note Stack checks are not implemented in this module but in the port - * layer in an architecture-dependent way. - * @{ - */ - -#include "ch.h" - -/*===========================================================================*/ -/* Module local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -#if (CH_DBG_SYSTEM_STATE_CHECK == TRUE) || defined(__DOXYGEN__) -/** - * @brief Guard code for @p chSysDisable(). - * - * @notapi - */ -void _dbg_check_disable(void) { - - if ((ch.dbg.isr_cnt != (cnt_t)0) || (ch.dbg.lock_cnt != (cnt_t)0)) { - chSysHalt("SV#1"); - } -} - -/** - * @brief Guard code for @p chSysSuspend(). - * - * @notapi - */ -void _dbg_check_suspend(void) { - - if ((ch.dbg.isr_cnt != (cnt_t)0) || (ch.dbg.lock_cnt != (cnt_t)0)) { - chSysHalt("SV#2"); - } -} - -/** - * @brief Guard code for @p chSysEnable(). - * - * @notapi - */ -void _dbg_check_enable(void) { - - if ((ch.dbg.isr_cnt != (cnt_t)0) || (ch.dbg.lock_cnt != (cnt_t)0)) { - chSysHalt("SV#3"); - } -} - -/** - * @brief Guard code for @p chSysLock(). - * - * @notapi - */ -void _dbg_check_lock(void) { - - if ((ch.dbg.isr_cnt != (cnt_t)0) || (ch.dbg.lock_cnt != (cnt_t)0)) { - chSysHalt("SV#4"); - } - _dbg_enter_lock(); -} - -/** - * @brief Guard code for @p chSysUnlock(). - * - * @notapi - */ -void _dbg_check_unlock(void) { - - if ((ch.dbg.isr_cnt != (cnt_t)0) || (ch.dbg.lock_cnt <= (cnt_t)0)) { - chSysHalt("SV#5"); - } - _dbg_leave_lock(); -} - -/** - * @brief Guard code for @p chSysLockFromIsr(). - * - * @notapi - */ -void _dbg_check_lock_from_isr(void) { - - if ((ch.dbg.isr_cnt <= (cnt_t)0) || (ch.dbg.lock_cnt != (cnt_t)0)) { - chSysHalt("SV#6"); - } - _dbg_enter_lock(); -} - -/** - * @brief Guard code for @p chSysUnlockFromIsr(). - * - * @notapi - */ -void _dbg_check_unlock_from_isr(void) { - - if ((ch.dbg.isr_cnt <= (cnt_t)0) || (ch.dbg.lock_cnt <= (cnt_t)0)) { - chSysHalt("SV#7"); - } - _dbg_leave_lock(); -} - -/** - * @brief Guard code for @p CH_IRQ_PROLOGUE(). - * - * @notapi - */ -void _dbg_check_enter_isr(void) { - - port_lock_from_isr(); - if ((ch.dbg.isr_cnt < (cnt_t)0) || (ch.dbg.lock_cnt != (cnt_t)0)) { - chSysHalt("SV#8"); - } - ch.dbg.isr_cnt++; - port_unlock_from_isr(); -} - -/** - * @brief Guard code for @p CH_IRQ_EPILOGUE(). - * - * @notapi - */ -void _dbg_check_leave_isr(void) { - - port_lock_from_isr(); - if ((ch.dbg.isr_cnt <= (cnt_t)0) || (ch.dbg.lock_cnt != (cnt_t)0)) { - chSysHalt("SV#9"); - } - ch.dbg.isr_cnt--; - port_unlock_from_isr(); -} - -/** - * @brief I-class functions context check. - * @details Verifies that the system is in an appropriate state for invoking - * an I-class API function. A panic is generated if the state is - * not compatible. - * - * @api - */ -void chDbgCheckClassI(void) { - - if ((ch.dbg.isr_cnt < (cnt_t)0) || (ch.dbg.lock_cnt <= (cnt_t)0)) { - chSysHalt("SV#10"); - } -} - -/** - * @brief S-class functions context check. - * @details Verifies that the system is in an appropriate state for invoking - * an S-class API function. A panic is generated if the state is - * not compatible. - * - * @api - */ -void chDbgCheckClassS(void) { - - if ((ch.dbg.isr_cnt != (cnt_t)0) || (ch.dbg.lock_cnt <= (cnt_t)0)) { - chSysHalt("SV#11"); - } -} - -#endif /* CH_DBG_SYSTEM_STATE_CHECK == TRUE */ - -#if (CH_DBG_ENABLE_TRACE == TRUE) || defined(__DOXYGEN__) -/** - * @brief Trace circular buffer subsystem initialization. - * @note Internal use only. - */ -void _dbg_trace_init(void) { - - ch.dbg.trace_buffer.tb_size = CH_DBG_TRACE_BUFFER_SIZE; - ch.dbg.trace_buffer.tb_ptr = &ch.dbg.trace_buffer.tb_buffer[0]; -} - -/** - * @brief Inserts in the circular debug trace buffer a context switch record. - * - * @param[in] otp the thread being switched out - * - * @notapi - */ -void _dbg_trace(thread_t *otp) { - - ch.dbg.trace_buffer.tb_ptr->se_time = chVTGetSystemTimeX(); - ch.dbg.trace_buffer.tb_ptr->se_tp = currp; - ch.dbg.trace_buffer.tb_ptr->se_wtobjp = otp->p_u.wtobjp; - ch.dbg.trace_buffer.tb_ptr->se_state = (uint8_t)otp->p_state; - if (++ch.dbg.trace_buffer.tb_ptr >= - &ch.dbg.trace_buffer.tb_buffer[CH_DBG_TRACE_BUFFER_SIZE]) { - ch.dbg.trace_buffer.tb_ptr = &ch.dbg.trace_buffer.tb_buffer[0]; - } -} -#endif /* CH_DBG_ENABLE_TRACE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/src/chdynamic.c b/firmware/ChibiOS_16/os/rt/src/chdynamic.c deleted file mode 100644 index d956eb05b6..0000000000 --- a/firmware/ChibiOS_16/os/rt/src/chdynamic.c +++ /dev/null @@ -1,240 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chdynamic.c - * @brief Dynamic threads code. - * - * @addtogroup dynamic_threads - * @details Dynamic threads related APIs and services. - * @{ - */ - -#include "ch.h" - -#if (CH_CFG_USE_DYNAMIC == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Module local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -/** - * @brief Adds a reference to a thread object. - * @pre The configuration option @p CH_CFG_USE_DYNAMIC must be enabled in - * order to use this function. - * - * @param[in] tp pointer to the thread - * @return The same thread pointer passed as parameter - * representing the new reference. - * - * @api - */ -thread_t *chThdAddRef(thread_t *tp) { - - chSysLock(); - chDbgAssert(tp->p_refs < (trefs_t)255, "too many references"); - tp->p_refs++; - chSysUnlock(); - - return tp; -} - -/** - * @brief Releases a reference to a thread object. - * @details If the references counter reaches zero and the thread - * is in the @p CH_STATE_FINAL state then the thread's memory is - * returned to the proper allocator. - * @pre The configuration option @p CH_CFG_USE_DYNAMIC must be enabled in - * order to use this function. - * @note Static threads are not affected. - * - * @param[in] tp pointer to the thread - * - * @api - */ -void chThdRelease(thread_t *tp) { - trefs_t refs; - - chSysLock(); - chDbgAssert(tp->p_refs > (trefs_t)0, "not referenced"); - tp->p_refs--; - refs = tp->p_refs; - - /* If the references counter reaches zero and the thread is in its - terminated state then the memory can be returned to the proper - allocator. Of course static threads are not affected.*/ - if ((refs == (trefs_t)0) && (tp->p_state == CH_STATE_FINAL)) { - switch (tp->p_flags & CH_FLAG_MODE_MASK) { -#if CH_CFG_USE_HEAP == TRUE - case CH_FLAG_MODE_HEAP: -#if CH_CFG_USE_REGISTRY == TRUE - REG_REMOVE(tp); -#endif - chSysUnlock(); - chHeapFree(tp); - return; -#endif -#if CH_CFG_USE_MEMPOOLS == TRUE - case CH_FLAG_MODE_MPOOL: -#if CH_CFG_USE_REGISTRY == TRUE - REG_REMOVE(tp); -#endif - chSysUnlock(); - chPoolFree(tp->p_mpool, tp); - return; -#endif - default: - /* Nothing to do for static threads, those are removed from the - registry on exit.*/ - break; - } - } - chSysUnlock(); -} - -#if (CH_CFG_USE_HEAP == TRUE) || defined(__DOXYGEN__) -/** - * @brief Creates a new thread allocating the memory from the heap. - * @pre The configuration options @p CH_CFG_USE_DYNAMIC and - * @p CH_CFG_USE_HEAP must be enabled in order to use this function. - * @note A thread can terminate by calling @p chThdExit() or by simply - * returning from its main function. - * @note The memory allocated for the thread is not released when the thread - * terminates but when a @p chThdWait() is performed. - * - * @param[in] heapp heap from which allocate the memory or @p NULL for the - * default heap - * @param[in] size size of the working area to be allocated - * @param[in] prio the priority level for the new thread - * @param[in] pf the thread function - * @param[in] arg an argument passed to the thread function. It can be - * @p NULL. - * @return The pointer to the @p thread_t structure allocated for - * the thread into the working space area. - * @retval NULL if the memory cannot be allocated. - * - * @api - */ -thread_t *chThdCreateFromHeap(memory_heap_t *heapp, size_t size, - tprio_t prio, tfunc_t pf, void *arg) { - void *wsp; - thread_t *tp; - - wsp = chHeapAlloc(heapp, size); - if (wsp == NULL) { - return NULL; - } - -#if CH_DBG_FILL_THREADS == TRUE - _thread_memfill((uint8_t *)wsp, - (uint8_t *)wsp + sizeof(thread_t), - CH_DBG_THREAD_FILL_VALUE); - _thread_memfill((uint8_t *)wsp + sizeof(thread_t), - (uint8_t *)wsp + size, - CH_DBG_STACK_FILL_VALUE); -#endif - - chSysLock(); - tp = chThdCreateI(wsp, size, prio, pf, arg); - tp->p_flags = CH_FLAG_MODE_HEAP; - chSchWakeupS(tp, MSG_OK); - chSysUnlock(); - - return tp; -} -#endif /* CH_CFG_USE_HEAP == TRUE */ - -#if (CH_CFG_USE_MEMPOOLS == TRUE) || defined(__DOXYGEN__) -/** - * @brief Creates a new thread allocating the memory from the specified - * memory pool. - * @pre The configuration options @p CH_CFG_USE_DYNAMIC and - * @p CH_CFG_USE_MEMPOOLS must be enabled in order to use this - * function. - * @note A thread can terminate by calling @p chThdExit() or by simply - * returning from its main function. - * @note The memory allocated for the thread is not released when the thread - * terminates but when a @p chThdWait() is performed. - * - * @param[in] mp pointer to the memory pool object - * @param[in] prio the priority level for the new thread - * @param[in] pf the thread function - * @param[in] arg an argument passed to the thread function. It can be - * @p NULL. - * @return The pointer to the @p thread_t structure allocated for - * the thread into the working space area. - * @retval NULL if the memory pool is empty. - * - * @api - */ -thread_t *chThdCreateFromMemoryPool(memory_pool_t *mp, tprio_t prio, - tfunc_t pf, void *arg) { - void *wsp; - thread_t *tp; - - chDbgCheck(mp != NULL); - - wsp = chPoolAlloc(mp); - if (wsp == NULL) { - return NULL; - } - -#if CH_DBG_FILL_THREADS == TRUE - _thread_memfill((uint8_t *)wsp, - (uint8_t *)wsp + sizeof(thread_t), - CH_DBG_THREAD_FILL_VALUE); - _thread_memfill((uint8_t *)wsp + sizeof(thread_t), - (uint8_t *)wsp + mp->mp_object_size, - CH_DBG_STACK_FILL_VALUE); -#endif - - chSysLock(); - tp = chThdCreateI(wsp, mp->mp_object_size, prio, pf, arg); - tp->p_flags = CH_FLAG_MODE_MPOOL; - tp->p_mpool = mp; - chSchWakeupS(tp, MSG_OK); - chSysUnlock(); - - return tp; -} -#endif /* CH_CFG_USE_MEMPOOLS == TRUE */ - -#endif /* CH_CFG_USE_DYNAMIC == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/src/chevents.c b/firmware/ChibiOS_16/os/rt/src/chevents.c deleted file mode 100644 index d2cd06a5fe..0000000000 --- a/firmware/ChibiOS_16/os/rt/src/chevents.c +++ /dev/null @@ -1,587 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ -/* - Concepts and parts of this file have been contributed by Scott (skute). - */ - -/** - * @file chevents.c - * @brief Events code. - * - * @addtogroup events - * @details Event Flags, Event Sources and Event Listeners. - *

Operation mode

- * Each thread has a mask of pending events inside its - * @p thread_t structure. - * Operations defined for events: - * - Wait, the invoking thread goes to sleep until a certain - * AND/OR combination of events become pending. - * - Clear, a mask of events is cleared from the pending - * events, the cleared events mask is returned (only the - * events that were actually pending and then cleared). - * - Signal, an events mask is directly ORed to the mask of the - * signaled thread. - * - Broadcast, each thread registered on an Event Source is - * signaled with the events specified in its Event Listener. - * - Dispatch, an events mask is scanned and for each bit set - * to one an associated handler function is invoked. Bit masks are - * scanned from bit zero upward. - * . - * An Event Source is a special object that can be "broadcasted" by - * a thread or an interrupt service routine. Broadcasting an Event - * Source has the effect that all the threads registered on the - * Event Source will be signaled with an events mask.
- * An unlimited number of Event Sources can exists in a system and - * each thread can be listening on an unlimited number of - * them. - * @pre In order to use the Events APIs the @p CH_CFG_USE_EVENTS option must be - * enabled in @p chconf.h. - * @post Enabling events requires 1-4 (depending on the architecture) - * extra bytes in the @p thread_t structure. - * @{ - */ - -#include "ch.h" - -#if (CH_CFG_USE_EVENTS == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Module local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -/** - * @brief Registers an Event Listener on an Event Source. - * @details Once a thread has registered as listener on an event source it - * will be notified of all events broadcasted there. - * @note Multiple Event Listeners can specify the same bits to be ORed to - * different threads. - * - * @param[in] esp pointer to the @p event_source_t structure - * @param[in] elp pointer to the @p event_listener_t structure - * @param[in] events events to be ORed to the thread when - * the event source is broadcasted - * @param[in] wflags mask of flags the listening thread is interested in - * - * @api - */ -void chEvtRegisterMaskWithFlags(event_source_t *esp, - event_listener_t *elp, - eventmask_t events, - eventflags_t wflags) { - - chDbgCheck((esp != NULL) && (elp != NULL)); - - chSysLock(); - elp->el_next = esp->es_next; - esp->es_next = elp; - elp->el_listener = currp; - elp->el_events = events; - elp->el_flags = (eventflags_t)0; - elp->el_wflags = wflags; - chSysUnlock(); -} - -/** - * @brief Unregisters an Event Listener from its Event Source. - * @note If the event listener is not registered on the specified event - * source then the function does nothing. - * @note For optimal performance it is better to perform the unregister - * operations in inverse order of the register operations (elements - * are found on top of the list). - * - * @param[in] esp pointer to the @p event_source_t structure - * @param[in] elp pointer to the @p event_listener_t structure - * - * @api - */ -void chEvtUnregister(event_source_t *esp, event_listener_t *elp) { - event_listener_t *p; - - chDbgCheck((esp != NULL) && (elp != NULL)); - - /*lint -save -e9087 -e740 [11.3, 1.3] Cast required by list handling.*/ - p = (event_listener_t *)esp; - /*lint -restore*/ - chSysLock(); - /*lint -save -e9087 -e740 [11.3, 1.3] Cast required by list handling.*/ - while (p->el_next != (event_listener_t *)esp) { - /*lint -restore*/ - if (p->el_next == elp) { - p->el_next = elp->el_next; - break; - } - p = p->el_next; - } - chSysUnlock(); -} - -/** - * @brief Clears the pending events specified in the events mask. - * - * @param[in] events the events to be cleared - * @return The pending events that were cleared. - * - * @api - */ -eventmask_t chEvtGetAndClearEvents(eventmask_t events) { - eventmask_t m; - - chSysLock(); - m = currp->p_epending & events; - currp->p_epending &= ~events; - chSysUnlock(); - - return m; -} - -/** - * @brief Adds (OR) a set of events to the current thread, this is - * @b much faster than using @p chEvtBroadcast() or @p chEvtSignal(). - * - * @param[in] events the events to be added - * @return The current pending events. - * - * @api - */ -eventmask_t chEvtAddEvents(eventmask_t events) { - - chSysLock(); - currp->p_epending |= events; - events = currp->p_epending; - chSysUnlock(); - - return events; -} - -/** - * @brief Signals all the Event Listeners registered on the specified Event - * Source. - * @details This function variants ORs the specified event flags to all the - * threads registered on the @p event_source_t in addition to the - * event flags specified by the threads themselves in the - * @p event_listener_t objects. - * @post This function does not reschedule so a call to a rescheduling - * function must be performed before unlocking the kernel. Note that - * interrupt handlers always reschedule on exit so an explicit - * reschedule must not be performed in ISRs. - * - * @param[in] esp pointer to the @p event_source_t structure - * @param[in] flags the flags set to be added to the listener flags mask - * - * @iclass - */ -void chEvtBroadcastFlagsI(event_source_t *esp, eventflags_t flags) { - event_listener_t *elp; - - chDbgCheckClassI(); - chDbgCheck(esp != NULL); - - elp = esp->es_next; - /*lint -save -e9087 -e740 [11.3, 1.3] Cast required by list handling.*/ - while (elp != (event_listener_t *)esp) { - /*lint -restore*/ - elp->el_flags |= flags; - /* When flags == 0 the thread will always be signaled because the - source does not emit any flag.*/ - if ((flags == (eventflags_t)0) || - ((elp->el_flags & elp->el_wflags) != (eventflags_t)0)) { - chEvtSignalI(elp->el_listener, elp->el_events); - } - elp = elp->el_next; - } -} - -/** - * @brief Returns the flags associated to an @p event_listener_t. - * @details The flags are returned and the @p event_listener_t flags mask is - * cleared. - * - * @param[in] elp pointer to the @p event_listener_t structure - * @return The flags added to the listener by the associated - * event source. - * - * @api - */ -eventflags_t chEvtGetAndClearFlags(event_listener_t *elp) { - eventflags_t flags; - - chSysLock(); - flags = elp->el_flags; - elp->el_flags = (eventflags_t)0; - chSysUnlock(); - - return flags; -} - -/** - * @brief Adds a set of event flags directly to the specified @p thread_t. - * - * @param[in] tp the thread to be signaled - * @param[in] events the events set to be ORed - * - * @api - */ -void chEvtSignal(thread_t *tp, eventmask_t events) { - - chDbgCheck(tp != NULL); - - chSysLock(); - chEvtSignalI(tp, events); - chSchRescheduleS(); - chSysUnlock(); -} - -/** - * @brief Adds a set of event flags directly to the specified @p thread_t. - * @post This function does not reschedule so a call to a rescheduling - * function must be performed before unlocking the kernel. Note that - * interrupt handlers always reschedule on exit so an explicit - * reschedule must not be performed in ISRs. - * - * @param[in] tp the thread to be signaled - * @param[in] events the events set to be ORed - * - * @iclass - */ -void chEvtSignalI(thread_t *tp, eventmask_t events) { - - chDbgCheckClassI(); - chDbgCheck(tp != NULL); - - tp->p_epending |= events; - /* Test on the AND/OR conditions wait states.*/ - if (((tp->p_state == CH_STATE_WTOREVT) && - ((tp->p_epending & tp->p_u.ewmask) != (eventmask_t)0)) || - ((tp->p_state == CH_STATE_WTANDEVT) && - ((tp->p_epending & tp->p_u.ewmask) == tp->p_u.ewmask))) { - tp->p_u.rdymsg = MSG_OK; - (void) chSchReadyI(tp); - } -} - -/** - * @brief Signals all the Event Listeners registered on the specified Event - * Source. - * @details This function variants ORs the specified event flags to all the - * threads registered on the @p event_source_t in addition to the - * event flags specified by the threads themselves in the - * @p event_listener_t objects. - * - * @param[in] esp pointer to the @p event_source_t structure - * @param[in] flags the flags set to be added to the listener flags mask - * - * @api - */ -void chEvtBroadcastFlags(event_source_t *esp, eventflags_t flags) { - - chSysLock(); - chEvtBroadcastFlagsI(esp, flags); - chSchRescheduleS(); - chSysUnlock(); -} - -/** - * @brief Returns the flags associated to an @p event_listener_t. - * @details The flags are returned and the @p event_listener_t flags mask is - * cleared. - * - * @param[in] elp pointer to the @p event_listener_t structure - * @return The flags added to the listener by the associated - * event source. - * - * @iclass - */ -eventflags_t chEvtGetAndClearFlagsI(event_listener_t *elp) { - eventflags_t flags; - - flags = elp->el_flags; - elp->el_flags = (eventflags_t)0; - - return flags; -} - -/** - * @brief Invokes the event handlers associated to an event flags mask. - * - * @param[in] events mask of events to be dispatched - * @param[in] handlers an array of @p evhandler_t. The array must have size - * equal to the number of bits in eventmask_t. - * - * @api - */ -void chEvtDispatch(const evhandler_t *handlers, eventmask_t events) { - eventid_t eid; - - chDbgCheck(handlers != NULL); - - eid = (eventid_t)0; - while (events != (eventmask_t)0) { - if ((events & EVENT_MASK(eid)) != (eventmask_t)0) { - chDbgAssert(handlers[eid] != NULL, "null handler"); - events &= ~EVENT_MASK(eid); - handlers[eid](eid); - } - eid++; - } -} - -#if (CH_CFG_OPTIMIZE_SPEED == TRUE) || \ - (CH_CFG_USE_EVENTS_TIMEOUT == FALSE) || \ - defined(__DOXYGEN__) -/** - * @brief Waits for exactly one of the specified events. - * @details The function waits for one event among those specified in - * @p events to become pending then the event is cleared and returned. - * @note One and only one event is served in the function, the one with the - * lowest event id. The function is meant to be invoked into a loop in - * order to serve all the pending events.
- * This means that Event Listeners with a lower event identifier have - * an higher priority. - * - * @param[in] events events that the function should wait - * for, @p ALL_EVENTS enables all the events - * @return The mask of the lowest event id served and cleared. - * - * @api - */ -eventmask_t chEvtWaitOne(eventmask_t events) { - thread_t *ctp = currp; - eventmask_t m; - - chSysLock(); - m = ctp->p_epending & events; - if (m == (eventmask_t)0) { - ctp->p_u.ewmask = events; - chSchGoSleepS(CH_STATE_WTOREVT); - m = ctp->p_epending & events; - } - m ^= m & (m - (eventmask_t)1); - ctp->p_epending &= ~m; - chSysUnlock(); - - return m; -} - -/** - * @brief Waits for any of the specified events. - * @details The function waits for any event among those specified in - * @p events to become pending then the events are cleared and - * returned. - * - * @param[in] events events that the function should wait - * for, @p ALL_EVENTS enables all the events - * @return The mask of the served and cleared events. - * - * @api - */ -eventmask_t chEvtWaitAny(eventmask_t events) { - thread_t *ctp = currp; - eventmask_t m; - - chSysLock(); - m = ctp->p_epending & events; - if (m == (eventmask_t)0) { - ctp->p_u.ewmask = events; - chSchGoSleepS(CH_STATE_WTOREVT); - m = ctp->p_epending & events; - } - ctp->p_epending &= ~m; - chSysUnlock(); - - return m; -} - -/** - * @brief Waits for all the specified events. - * @details The function waits for all the events specified in @p events to - * become pending then the events are cleared and returned. - * - * @param[in] events events that the function should wait - * for, @p ALL_EVENTS requires all the events - * @return The mask of the served and cleared events. - * - * @api - */ -eventmask_t chEvtWaitAll(eventmask_t events) { - thread_t *ctp = currp; - - chSysLock(); - if ((ctp->p_epending & events) != events) { - ctp->p_u.ewmask = events; - chSchGoSleepS(CH_STATE_WTANDEVT); - } - ctp->p_epending &= ~events; - chSysUnlock(); - - return events; -} -#endif /* CH_CFG_OPTIMIZE_SPEED || !CH_CFG_USE_EVENTS_TIMEOUT */ - -#if (CH_CFG_USE_EVENTS_TIMEOUT == TRUE) || defined(__DOXYGEN__) -/** - * @brief Waits for exactly one of the specified events. - * @details The function waits for one event among those specified in - * @p events to become pending then the event is cleared and returned. - * @note One and only one event is served in the function, the one with the - * lowest event id. The function is meant to be invoked into a loop - * in order to serve all the pending events.
- * This means that Event Listeners with a lower event identifier have - * an higher priority. - * - * @param[in] events events that the function should wait - * for, @p ALL_EVENTS enables all the events - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The mask of the lowest event id served and cleared. - * @retval 0 if the operation has timed out. - * - * @api - */ -eventmask_t chEvtWaitOneTimeout(eventmask_t events, systime_t time) { - thread_t *ctp = currp; - eventmask_t m; - - chSysLock(); - m = ctp->p_epending & events; - if (m == (eventmask_t)0) { - if (TIME_IMMEDIATE == time) { - chSysUnlock(); - return (eventmask_t)0; - } - ctp->p_u.ewmask = events; - if (chSchGoSleepTimeoutS(CH_STATE_WTOREVT, time) < MSG_OK) { - chSysUnlock(); - return (eventmask_t)0; - } - m = ctp->p_epending & events; - } - m ^= m & (m - (eventmask_t)1); - ctp->p_epending &= ~m; - chSysUnlock(); - - return m; -} - -/** - * @brief Waits for any of the specified events. - * @details The function waits for any event among those specified in - * @p events to become pending then the events are cleared and - * returned. - * - * @param[in] events events that the function should wait - * for, @p ALL_EVENTS enables all the events - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The mask of the served and cleared events. - * @retval 0 if the operation has timed out. - * - * @api - */ -eventmask_t chEvtWaitAnyTimeout(eventmask_t events, systime_t time) { - thread_t *ctp = currp; - eventmask_t m; - - chSysLock(); - m = ctp->p_epending & events; - if (m == (eventmask_t)0) { - if (TIME_IMMEDIATE == time) { - chSysUnlock(); - return (eventmask_t)0; - } - ctp->p_u.ewmask = events; - if (chSchGoSleepTimeoutS(CH_STATE_WTOREVT, time) < MSG_OK) { - chSysUnlock(); - return (eventmask_t)0; - } - m = ctp->p_epending & events; - } - ctp->p_epending &= ~m; - chSysUnlock(); - - return m; -} - -/** - * @brief Waits for all the specified events. - * @details The function waits for all the events specified in @p events to - * become pending then the events are cleared and returned. - * - * @param[in] events events that the function should wait - * for, @p ALL_EVENTS requires all the events - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The mask of the served and cleared events. - * @retval 0 if the operation has timed out. - * - * @api - */ -eventmask_t chEvtWaitAllTimeout(eventmask_t events, systime_t time) { - thread_t *ctp = currp; - - chSysLock(); - if ((ctp->p_epending & events) != events) { - if (TIME_IMMEDIATE == time) { - chSysUnlock(); - return (eventmask_t)0; - } - ctp->p_u.ewmask = events; - if (chSchGoSleepTimeoutS(CH_STATE_WTANDEVT, time) < MSG_OK) { - chSysUnlock(); - return (eventmask_t)0; - } - } - ctp->p_epending &= ~events; - chSysUnlock(); - - return events; -} -#endif /* CH_CFG_USE_EVENTS_TIMEOUT == TRUE */ - -#endif /* CH_CFG_USE_EVENTS == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/src/chheap.c b/firmware/ChibiOS_16/os/rt/src/chheap.c deleted file mode 100644 index 0a8b37b965..0000000000 --- a/firmware/ChibiOS_16/os/rt/src/chheap.c +++ /dev/null @@ -1,294 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chheap.c - * @brief Heaps code. - * - * @addtogroup heaps - * @details Heap Allocator related APIs. - *

Operation mode

- * The heap allocator implements a first-fit strategy and its APIs - * are functionally equivalent to the usual @p malloc() and @p free() - * library functions. The main difference is that the OS heap APIs - * are guaranteed to be thread safe.
- * @pre In order to use the heap APIs the @p CH_CFG_USE_HEAP option must - * be enabled in @p chconf.h. - * @{ - */ - -#include "ch.h" - -#if (CH_CFG_USE_HEAP == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Module local definitions. */ -/*===========================================================================*/ - -/* - * Defaults on the best synchronization mechanism available. - */ -#if (CH_CFG_USE_MUTEXES == TRUE) || defined(__DOXYGEN__) -#define H_LOCK(h) chMtxLock(&(h)->h_mtx) -#define H_UNLOCK(h) chMtxUnlock(&(h)->h_mtx) -#else -#define H_LOCK(h) (void) chSemWait(&(h)->h_sem) -#define H_UNLOCK(h) chSemSignal(&(h)->h_sem) -#endif - -#define LIMIT(p) \ - /*lint -save -e9087 [11.3] Safe cast.*/ \ - (union heap_header *)((uint8_t *)(p) + \ - sizeof(union heap_header) + (p)->h.size) \ - /*lint -restore*/ - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -/** - * @brief Default heap descriptor. - */ -static memory_heap_t default_heap; - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -/** - * @brief Initializes the default heap. - * - * @notapi - */ -void _heap_init(void) { - - default_heap.h_provider = chCoreAlloc; - default_heap.h_free.h.u.next = NULL; - default_heap.h_free.h.size = 0; -#if (CH_CFG_USE_MUTEXES == TRUE) || defined(__DOXYGEN__) - chMtxObjectInit(&default_heap.h_mtx); -#else - chSemObjectInit(&default_heap.h_sem, (cnt_t)1); -#endif -} - -/** - * @brief Initializes a memory heap from a static memory area. - * @pre Both the heap buffer base and the heap size must be aligned to - * the @p stkalign_t type size. - * - * @param[out] heapp pointer to the memory heap descriptor to be initialized - * @param[in] buf heap buffer base - * @param[in] size heap size - * - * @init - */ -void chHeapObjectInit(memory_heap_t *heapp, void *buf, size_t size) { - union heap_header *hp = buf; - - chDbgCheck(MEM_IS_ALIGNED(buf) && MEM_IS_ALIGNED(size)); - - heapp->h_provider = NULL; - heapp->h_free.h.u.next = hp; - heapp->h_free.h.size = 0; - hp->h.u.next = NULL; - hp->h.size = size - sizeof(union heap_header); -#if (CH_CFG_USE_MUTEXES == TRUE) || defined(__DOXYGEN__) - chMtxObjectInit(&heapp->h_mtx); -#else - chSemObjectInit(&heapp->h_sem, (cnt_t)1); -#endif -} - -/** - * @brief Allocates a block of memory from the heap by using the first-fit - * algorithm. - * @details The allocated block is guaranteed to be properly aligned for a - * pointer data type (@p stkalign_t). - * - * @param[in] heapp pointer to a heap descriptor or @p NULL in order to - * access the default heap. - * @param[in] size the size of the block to be allocated. Note that the - * allocated block may be a bit bigger than the requested - * size for alignment and fragmentation reasons. - * @return A pointer to the allocated block. - * @retval NULL if the block cannot be allocated. - * - * @api - */ -void *chHeapAlloc(memory_heap_t *heapp, size_t size) { - union heap_header *qp, *hp, *fp; - - if (heapp == NULL) { - heapp = &default_heap; - } - - size = MEM_ALIGN_NEXT(size); - qp = &heapp->h_free; - - H_LOCK(heapp); - while (qp->h.u.next != NULL) { - hp = qp->h.u.next; - if (hp->h.size >= size) { - if (hp->h.size < (size + sizeof(union heap_header))) { - /* Gets the whole block even if it is slightly bigger than the - requested size because the fragment would be too small to be - useful.*/ - qp->h.u.next = hp->h.u.next; - } - else { - /* Block bigger enough, must split it.*/ - /*lint -save -e9087 [11.3] Safe cast.*/ - fp = (void *)((uint8_t *)(hp) + sizeof(union heap_header) + size); - /*lint -restore*/ - fp->h.u.next = hp->h.u.next; - fp->h.size = (hp->h.size - sizeof(union heap_header)) - size; - qp->h.u.next = fp; - hp->h.size = size; - } - hp->h.u.heap = heapp; - H_UNLOCK(heapp); - - /*lint -save -e9087 [11.3] Safe cast.*/ - return (void *)(hp + 1); - /*lint -restore*/ - } - qp = hp; - } - H_UNLOCK(heapp); - - /* More memory is required, tries to get it from the associated provider - else fails.*/ - if (heapp->h_provider != NULL) { - hp = heapp->h_provider(size + sizeof(union heap_header)); - if (hp != NULL) { - hp->h.u.heap = heapp; - hp->h.size = size; - hp++; - - /*lint -save -e9087 [11.3] Safe cast.*/ - return (void *)hp; - /*lint -restore*/ - } - } - - return NULL; -} - -/** - * @brief Frees a previously allocated memory block. - * - * @param[in] p pointer to the memory block to be freed - * - * @api - */ -void chHeapFree(void *p) { - union heap_header *qp, *hp; - memory_heap_t *heapp; - - chDbgCheck(p != NULL); - - /*lint -save -e9087 [11.3] Safe cast.*/ - hp = (union heap_header *)p - 1; - /*lint -restore*/ - heapp = hp->h.u.heap; - qp = &heapp->h_free; - - H_LOCK(heapp); - while (true) { - chDbgAssert((hp < qp) || (hp >= LIMIT(qp)), "within free block"); - - if (((qp == &heapp->h_free) || (hp > qp)) && - ((qp->h.u.next == NULL) || (hp < qp->h.u.next))) { - /* Insertion after qp.*/ - hp->h.u.next = qp->h.u.next; - qp->h.u.next = hp; - /* Verifies if the newly inserted block should be merged.*/ - if (LIMIT(hp) == hp->h.u.next) { - /* Merge with the next block.*/ - hp->h.size += hp->h.u.next->h.size + sizeof(union heap_header); - hp->h.u.next = hp->h.u.next->h.u.next; - } - if ((LIMIT(qp) == hp)) { - /* Merge with the previous block.*/ - qp->h.size += hp->h.size + sizeof(union heap_header); - qp->h.u.next = hp->h.u.next; - } - break; - } - qp = qp->h.u.next; - } - H_UNLOCK(heapp); - - return; -} - -/** - * @brief Reports the heap status. - * @note This function is meant to be used in the test suite, it should - * not be really useful for the application code. - * - * @param[in] heapp pointer to a heap descriptor or @p NULL in order to - * access the default heap. - * @param[in] sizep pointer to a variable that will receive the total - * fragmented free space - * @return The number of fragments in the heap. - * - * @api - */ -size_t chHeapStatus(memory_heap_t *heapp, size_t *sizep) { - union heap_header *qp; - size_t n, sz; - - if (heapp == NULL) { - heapp = &default_heap; - } - - H_LOCK(heapp); - sz = 0; - n = 0; - qp = &heapp->h_free; - while (qp->h.u.next != NULL) { - sz += qp->h.u.next->h.size; - n++; - qp = qp->h.u.next; - } - if (sizep != NULL) { - *sizep = sz; - } - H_UNLOCK(heapp); - - return n; -} - -#endif /* CH_CFG_USE_HEAP == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/src/chmboxes.c b/firmware/ChibiOS_16/os/rt/src/chmboxes.c deleted file mode 100644 index 432be5dc22..0000000000 --- a/firmware/ChibiOS_16/os/rt/src/chmboxes.c +++ /dev/null @@ -1,434 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chmboxes.c - * @brief Mailboxes code. - * - * @addtogroup mailboxes - * @details Asynchronous messages. - *

Operation mode

- * A mailbox is an asynchronous communication mechanism.
- * Operations defined for mailboxes: - * - Post: Posts a message on the mailbox in FIFO order. - * - Post Ahead: Posts a message on the mailbox with urgent - * priority. - * - Fetch: A message is fetched from the mailbox and removed - * from the queue. - * - Reset: The mailbox is emptied and all the stored messages - * are lost. - * . - * A message is a variable of type msg_t that is guaranteed to have - * the same size of and be compatible with (data) pointers (anyway an - * explicit cast is needed). - * If larger messages need to be exchanged then a pointer to a - * structure can be posted in the mailbox but the posting side has - * no predefined way to know when the message has been processed. A - * possible approach is to allocate memory (from a memory pool for - * example) from the posting side and free it on the fetching side. - * Another approach is to set a "done" flag into the structure pointed - * by the message. - * @pre In order to use the mailboxes APIs the @p CH_CFG_USE_MAILBOXES option - * must be enabled in @p chconf.h. - * @{ - */ - -#include "ch.h" - -#if (CH_CFG_USE_MAILBOXES == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -/** - * @brief Initializes a @p mailbox_t object. - * - * @param[out] mbp the pointer to the @p mailbox_t structure to be - * initialized - * @param[in] buf pointer to the messages buffer as an array of @p msg_t - * @param[in] n number of elements in the buffer array - * - * @init - */ -void chMBObjectInit(mailbox_t *mbp, msg_t *buf, cnt_t n) { - - chDbgCheck((mbp != NULL) && (buf != NULL) && (n > (cnt_t)0)); - - mbp->mb_buffer = buf; - mbp->mb_rdptr = buf; - mbp->mb_wrptr = buf; - mbp->mb_top = &buf[n]; - chSemObjectInit(&mbp->mb_emptysem, n); - chSemObjectInit(&mbp->mb_fullsem, (cnt_t)0); -} - -/** - * @brief Resets a @p mailbox_t object. - * @details All the waiting threads are resumed with status @p MSG_RESET and - * the queued messages are lost. - * - * @param[in] mbp the pointer to an initialized @p mailbox_t object - * - * @api - */ -void chMBReset(mailbox_t *mbp) { - - chSysLock(); - chMBResetI(mbp); - chSchRescheduleS(); - chSysUnlock(); -} - -/** - * @brief Resets a @p mailbox_t object. - * @details All the waiting threads are resumed with status @p MSG_RESET and - * the queued messages are lost. - * - * @param[in] mbp the pointer to an initialized @p mailbox_t object - * - * @api - */ -void chMBResetI(mailbox_t *mbp) { - - chDbgCheckClassI(); - chDbgCheck(mbp != NULL); - - mbp->mb_wrptr = mbp->mb_buffer; - mbp->mb_rdptr = mbp->mb_buffer; - chSemResetI(&mbp->mb_emptysem, (cnt_t)(mbp->mb_top - mbp->mb_buffer)); - chSemResetI(&mbp->mb_fullsem, (cnt_t)0); -} - -/** - * @brief Posts a message into a mailbox. - * @details The invoking thread waits until a empty slot in the mailbox becomes - * available or the specified time runs out. - * - * @param[in] mbp the pointer to an initialized @p mailbox_t object - * @param[in] msg the message to be posted on the mailbox - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval MSG_OK if a message has been correctly posted. - * @retval MSG_RESET if the mailbox has been reset while waiting. - * @retval MSG_TIMEOUT if the operation has timed out. - * - * @api - */ -msg_t chMBPost(mailbox_t *mbp, msg_t msg, systime_t timeout) { - msg_t rdymsg; - - chSysLock(); - rdymsg = chMBPostS(mbp, msg, timeout); - chSysUnlock(); - - return rdymsg; -} - -/** - * @brief Posts a message into a mailbox. - * @details The invoking thread waits until a empty slot in the mailbox becomes - * available or the specified time runs out. - * - * @param[in] mbp the pointer to an initialized @p mailbox_t object - * @param[in] msg the message to be posted on the mailbox - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval MSG_OK if a message has been correctly posted. - * @retval MSG_RESET if the mailbox has been reset while waiting. - * @retval MSG_TIMEOUT if the operation has timed out. - * - * @sclass - */ -msg_t chMBPostS(mailbox_t *mbp, msg_t msg, systime_t timeout) { - msg_t rdymsg; - - chDbgCheckClassS(); - chDbgCheck(mbp != NULL); - - rdymsg = chSemWaitTimeoutS(&mbp->mb_emptysem, timeout); - if (rdymsg == MSG_OK) { - *mbp->mb_wrptr++ = msg; - if (mbp->mb_wrptr >= mbp->mb_top) { - mbp->mb_wrptr = mbp->mb_buffer; - } - chSemSignalI(&mbp->mb_fullsem); - chSchRescheduleS(); - } - - return rdymsg; -} - -/** - * @brief Posts a message into a mailbox. - * @details This variant is non-blocking, the function returns a timeout - * condition if the queue is full. - * - * @param[in] mbp the pointer to an initialized @p mailbox_t object - * @param[in] msg the message to be posted on the mailbox - * @return The operation status. - * @retval MSG_OK if a message has been correctly posted. - * @retval MSG_TIMEOUT if the mailbox is full and the message cannot be - * posted. - * - * @iclass - */ -msg_t chMBPostI(mailbox_t *mbp, msg_t msg) { - - chDbgCheckClassI(); - chDbgCheck(mbp != NULL); - - if (chSemGetCounterI(&mbp->mb_emptysem) <= (cnt_t)0) { - return MSG_TIMEOUT; - } - - chSemFastWaitI(&mbp->mb_emptysem); - *mbp->mb_wrptr++ = msg; - if (mbp->mb_wrptr >= mbp->mb_top) { - mbp->mb_wrptr = mbp->mb_buffer; - } - chSemSignalI(&mbp->mb_fullsem); - - return MSG_OK; -} - -/** - * @brief Posts an high priority message into a mailbox. - * @details The invoking thread waits until a empty slot in the mailbox becomes - * available or the specified time runs out. - * - * @param[in] mbp the pointer to an initialized @p mailbox_t object - * @param[in] msg the message to be posted on the mailbox - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval MSG_OK if a message has been correctly posted. - * @retval MSG_RESET if the mailbox has been reset while waiting. - * @retval MSG_TIMEOUT if the operation has timed out. - * - * @api - */ -msg_t chMBPostAhead(mailbox_t *mbp, msg_t msg, systime_t timeout) { - msg_t rdymsg; - - chSysLock(); - rdymsg = chMBPostAheadS(mbp, msg, timeout); - chSysUnlock(); - - return rdymsg; -} - -/** - * @brief Posts an high priority message into a mailbox. - * @details The invoking thread waits until a empty slot in the mailbox becomes - * available or the specified time runs out. - * - * @param[in] mbp the pointer to an initialized @p mailbox_t object - * @param[in] msg the message to be posted on the mailbox - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval MSG_OK if a message has been correctly posted. - * @retval MSG_RESET if the mailbox has been reset while waiting. - * @retval MSG_TIMEOUT if the operation has timed out. - * - * @sclass - */ -msg_t chMBPostAheadS(mailbox_t *mbp, msg_t msg, systime_t timeout) { - msg_t rdymsg; - - chDbgCheckClassS(); - chDbgCheck(mbp != NULL); - - rdymsg = chSemWaitTimeoutS(&mbp->mb_emptysem, timeout); - if (rdymsg == MSG_OK) { - if (--mbp->mb_rdptr < mbp->mb_buffer) { - mbp->mb_rdptr = mbp->mb_top - 1; - } - *mbp->mb_rdptr = msg; - chSemSignalI(&mbp->mb_fullsem); - chSchRescheduleS(); - } - - return rdymsg; -} - -/** - * @brief Posts an high priority message into a mailbox. - * @details This variant is non-blocking, the function returns a timeout - * condition if the queue is full. - * - * @param[in] mbp the pointer to an initialized @p mailbox_t object - * @param[in] msg the message to be posted on the mailbox - * @return The operation status. - * @retval MSG_OK if a message has been correctly posted. - * @retval MSG_TIMEOUT if the mailbox is full and the message cannot be - * posted. - * - * @iclass - */ -msg_t chMBPostAheadI(mailbox_t *mbp, msg_t msg) { - - chDbgCheckClassI(); - chDbgCheck(mbp != NULL); - - if (chSemGetCounterI(&mbp->mb_emptysem) <= (cnt_t)0) { - return MSG_TIMEOUT; - } - chSemFastWaitI(&mbp->mb_emptysem); - if (--mbp->mb_rdptr < mbp->mb_buffer) { - mbp->mb_rdptr = mbp->mb_top - 1; - } - *mbp->mb_rdptr = msg; - chSemSignalI(&mbp->mb_fullsem); - - return MSG_OK; -} - -/** - * @brief Retrieves a message from a mailbox. - * @details The invoking thread waits until a message is posted in the mailbox - * or the specified time runs out. - * - * @param[in] mbp the pointer to an initialized @p mailbox_t object - * @param[out] msgp pointer to a message variable for the received message - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval MSG_OK if a message has been correctly fetched. - * @retval MSG_RESET if the mailbox has been reset while waiting. - * @retval MSG_TIMEOUT if the operation has timed out. - * - * @api - */ -msg_t chMBFetch(mailbox_t *mbp, msg_t *msgp, systime_t timeout) { - msg_t rdymsg; - - chSysLock(); - rdymsg = chMBFetchS(mbp, msgp, timeout); - chSysUnlock(); - - return rdymsg; -} - -/** - * @brief Retrieves a message from a mailbox. - * @details The invoking thread waits until a message is posted in the mailbox - * or the specified time runs out. - * - * @param[in] mbp the pointer to an initialized @p mailbox_t object - * @param[out] msgp pointer to a message variable for the received message - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval MSG_OK if a message has been correctly fetched. - * @retval MSG_RESET if the mailbox has been reset while waiting. - * @retval MSG_TIMEOUT if the operation has timed out. - * - * @sclass - */ -msg_t chMBFetchS(mailbox_t *mbp, msg_t *msgp, systime_t timeout) { - msg_t rdymsg; - - chDbgCheckClassS(); - chDbgCheck((mbp != NULL) && (msgp != NULL)); - - rdymsg = chSemWaitTimeoutS(&mbp->mb_fullsem, timeout); - if (rdymsg == MSG_OK) { - *msgp = *mbp->mb_rdptr++; - if (mbp->mb_rdptr >= mbp->mb_top) { - mbp->mb_rdptr = mbp->mb_buffer; - } - chSemSignalI(&mbp->mb_emptysem); - chSchRescheduleS(); - } - - return rdymsg; -} - -/** - * @brief Retrieves a message from a mailbox. - * @details This variant is non-blocking, the function returns a timeout - * condition if the queue is empty. - * - * @param[in] mbp the pointer to an initialized @p mailbox_t object - * @param[out] msgp pointer to a message variable for the received message - * @return The operation status. - * @retval MSG_OK if a message has been correctly fetched. - * @retval MSG_TIMEOUT if the mailbox is empty and a message cannot be - * fetched. - * - * @iclass - */ -msg_t chMBFetchI(mailbox_t *mbp, msg_t *msgp) { - - chDbgCheckClassI(); - chDbgCheck((mbp != NULL) && (msgp != NULL)); - - if (chSemGetCounterI(&mbp->mb_fullsem) <= (cnt_t)0) { - return MSG_TIMEOUT; - } - chSemFastWaitI(&mbp->mb_fullsem); - *msgp = *mbp->mb_rdptr++; - if (mbp->mb_rdptr >= mbp->mb_top) { - mbp->mb_rdptr = mbp->mb_buffer; - } - chSemSignalI(&mbp->mb_emptysem); - - return MSG_OK; -} -#endif /* CH_CFG_USE_MAILBOXES == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/src/chmemcore.c b/firmware/ChibiOS_16/os/rt/src/chmemcore.c deleted file mode 100644 index b15c2607c6..0000000000 --- a/firmware/ChibiOS_16/os/rt/src/chmemcore.c +++ /dev/null @@ -1,163 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chmemcore.c - * @brief Core memory manager code. - * - * @addtogroup memcore - * @details Core Memory Manager related APIs and services. - *

Operation mode

- * The core memory manager is a simplified allocator that only - * allows to allocate memory blocks without the possibility to - * free them.
- * This allocator is meant as a memory blocks provider for the - * other allocators such as: - * - C-Runtime allocator (through a compiler specific adapter module). - * - Heap allocator (see @ref heaps). - * - Memory pools allocator (see @ref pools). - * . - * By having a centralized memory provider the various allocators - * can coexist and share the main memory.
- * This allocator, alone, is also useful for very simple - * applications that just require a simple way to get memory - * blocks. - * @pre In order to use the core memory manager APIs the @p CH_CFG_USE_MEMCORE - * option must be enabled in @p chconf.h. - * @{ - */ - -#include "ch.h" - -#if (CH_CFG_USE_MEMCORE == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -static uint8_t *nextmem; -static uint8_t *endmem; - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level memory manager initialization. - * - * @notapi - */ -void _core_init(void) { -#if CH_CFG_MEMCORE_SIZE == 0 - extern uint8_t __heap_base__[]; - extern uint8_t __heap_end__[]; - - /*lint -save -e9033 [10.8] Required cast operations.*/ - nextmem = (uint8_t *)MEM_ALIGN_NEXT(__heap_base__); - endmem = (uint8_t *)MEM_ALIGN_PREV(__heap_end__); - /*lint restore*/ -#else - static stkalign_t buffer[MEM_ALIGN_NEXT(CH_CFG_MEMCORE_SIZE) / - MEM_ALIGN_SIZE]; - - nextmem = (uint8_t *)&buffer[0]; - endmem = (uint8_t *)&buffer[MEM_ALIGN_NEXT(CH_CFG_MEMCORE_SIZE) / - MEM_ALIGN_SIZE]; -#endif -} - -/** - * @brief Allocates a memory block. - * @details The size of the returned block is aligned to the alignment - * type so it is not possible to allocate less - * than MEM_ALIGN_SIZE. - * - * @param[in] size the size of the block to be allocated - * @return A pointer to the allocated memory block. - * @retval NULL allocation failed, core memory exhausted. - * - * @api - */ -void *chCoreAlloc(size_t size) { - void *p; - - chSysLock(); - p = chCoreAllocI(size); - chSysUnlock(); - - return p; -} - -/** - * @brief Allocates a memory block. - * @details The size of the returned block is aligned to the alignment - * type so it is not possible to allocate less than - * MEM_ALIGN_SIZE. - * - * @param[in] size the size of the block to be allocated. - * @return A pointer to the allocated memory block. - * @retval NULL allocation failed, core memory exhausted. - * - * @iclass - */ -void *chCoreAllocI(size_t size) { - void *p; - - chDbgCheckClassI(); - - size = MEM_ALIGN_NEXT(size); - /*lint -save -e9033 [10.8] The cast is safe.*/ - if ((size_t)(endmem - nextmem) < size) { - /*lint -restore*/ - return NULL; - } - p = nextmem; - nextmem += size; - - return p; -} - -/** - * @brief Core memory status. - * - * @return The size, in bytes, of the free core memory. - * - * @xclass - */ -size_t chCoreGetStatusX(void) { - - /*lint -save -e9033 [10.8] The cast is safe.*/ - return (size_t)(endmem - nextmem); - /*lint -restore*/ -} -#endif /* CH_CFG_USE_MEMCORE == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/src/chmempools.c b/firmware/ChibiOS_16/os/rt/src/chmempools.c deleted file mode 100644 index 176a320686..0000000000 --- a/firmware/ChibiOS_16/os/rt/src/chmempools.c +++ /dev/null @@ -1,202 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chmempools.c - * @brief Memory Pools code. - * - * @addtogroup pools - * @details Memory Pools related APIs and services. - *

Operation mode

- * The Memory Pools APIs allow to allocate/free fixed size objects in - * constant time and reliably without memory fragmentation - * problems.
- * Memory Pools do not enforce any alignment constraint on the - * contained object however the objects must be properly aligned - * to contain a pointer to void. - * @pre In order to use the memory pools APIs the @p CH_CFG_USE_MEMPOOLS option - * must be enabled in @p chconf.h. - * @{ - */ - -#include "ch.h" - -#if (CH_CFG_USE_MEMPOOLS == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -/** - * @brief Initializes an empty memory pool. - * - * @param[out] mp pointer to a @p memory_pool_t structure - * @param[in] size the size of the objects contained in this memory pool, - * the minimum accepted size is the size of a pointer to - * void. - * @param[in] provider memory provider function for the memory pool or - * @p NULL if the pool is not allowed to grow - * automatically - * - * @init - */ -void chPoolObjectInit(memory_pool_t *mp, size_t size, memgetfunc_t provider) { - - chDbgCheck((mp != NULL) && (size >= sizeof(void *))); - - mp->mp_next = NULL; - mp->mp_object_size = size; - mp->mp_provider = provider; -} - -/** - * @brief Loads a memory pool with an array of static objects. - * @pre The memory pool must be already been initialized. - * @pre The array elements must be of the right size for the specified - * memory pool. - * @post The memory pool contains the elements of the input array. - * - * @param[in] mp pointer to a @p memory_pool_t structure - * @param[in] p pointer to the array first element - * @param[in] n number of elements in the array - * - * @api - */ -void chPoolLoadArray(memory_pool_t *mp, void *p, size_t n) { - - chDbgCheck((mp != NULL) && (n != 0U)); - - while (n != 0U) { - chPoolAdd(mp, p); - /*lint -save -e9087 [11.3] Safe cast.*/ - p = (void *)(((uint8_t *)p) + mp->mp_object_size); - /*lint -restore*/ - n--; - } -} - -/** - * @brief Allocates an object from a memory pool. - * @pre The memory pool must be already been initialized. - * - * @param[in] mp pointer to a @p memory_pool_t structure - * @return The pointer to the allocated object. - * @retval NULL if pool is empty. - * - * @iclass - */ -void *chPoolAllocI(memory_pool_t *mp) { - void *objp; - - chDbgCheckClassI(); - chDbgCheck(mp != NULL); - - objp = mp->mp_next; - /*lint -save -e9013 [15.7] There is no else because it is not needed.*/ - if (objp != NULL) { - mp->mp_next = mp->mp_next->ph_next; - } - else if (mp->mp_provider != NULL) { - objp = mp->mp_provider(mp->mp_object_size); - } - /*lint -restore*/ - - return objp; -} - -/** - * @brief Allocates an object from a memory pool. - * @pre The memory pool must be already been initialized. - * - * @param[in] mp pointer to a @p memory_pool_t structure - * @return The pointer to the allocated object. - * @retval NULL if pool is empty. - * - * @api - */ -void *chPoolAlloc(memory_pool_t *mp) { - void *objp; - - chSysLock(); - objp = chPoolAllocI(mp); - chSysUnlock(); - - return objp; -} - -/** - * @brief Releases an object into a memory pool. - * @pre The memory pool must be already been initialized. - * @pre The freed object must be of the right size for the specified - * memory pool. - * @pre The object must be properly aligned to contain a pointer to void. - * - * @param[in] mp pointer to a @p memory_pool_t structure - * @param[in] objp the pointer to the object to be released - * - * @iclass - */ -void chPoolFreeI(memory_pool_t *mp, void *objp) { - struct pool_header *php = objp; - - chDbgCheckClassI(); - chDbgCheck((mp != NULL) && (objp != NULL)); - - php->ph_next = mp->mp_next; - mp->mp_next = php; -} - -/** - * @brief Releases an object into a memory pool. - * @pre The memory pool must be already been initialized. - * @pre The freed object must be of the right size for the specified - * memory pool. - * @pre The object must be properly aligned to contain a pointer to void. - * - * @param[in] mp pointer to a @p memory_pool_t structure - * @param[in] objp the pointer to the object to be released - * - * @api - */ -void chPoolFree(memory_pool_t *mp, void *objp) { - - chSysLock(); - chPoolFreeI(mp, objp); - chSysUnlock(); -} - -#endif /* CH_CFG_USE_MEMPOOLS == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/src/chmsg.c b/firmware/ChibiOS_16/os/rt/src/chmsg.c deleted file mode 100644 index 4a2f218df7..0000000000 --- a/firmware/ChibiOS_16/os/rt/src/chmsg.c +++ /dev/null @@ -1,154 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chmsg.c - * @brief Messages code. - * - * @addtogroup messages - * @details Synchronous inter-thread messages APIs and services. - *

Operation Mode

- * Synchronous messages are an easy to use and fast IPC mechanism, - * threads can both act as message servers and/or message clients, - * the mechanism allows data to be carried in both directions. Note - * that messages are not copied between the client and server threads - * but just a pointer passed so the exchange is very time - * efficient.
- * Messages are scalar data types of type @p msg_t that are guaranteed - * to be size compatible with data pointers. Note that on some - * architectures function pointers can be larger that @p msg_t.
- * Messages are usually processed in FIFO order but it is possible to - * process them in priority order by enabling the - * @p CH_CFG_USE_MESSAGES_PRIORITY option in @p chconf.h.
- * @pre In order to use the message APIs the @p CH_CFG_USE_MESSAGES option - * must be enabled in @p chconf.h. - * @post Enabling messages requires 6-12 (depending on the architecture) - * extra bytes in the @p thread_t structure. - * @{ - */ - -#include "ch.h" - -#if (CH_CFG_USE_MESSAGES == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -#if CH_CFG_USE_MESSAGES_PRIORITY == TRUE -#define msg_insert(tp, qp) queue_prio_insert(tp, qp) -#else -#define msg_insert(tp, qp) queue_insert(tp, qp) -#endif - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -/** - * @brief Sends a message to the specified thread. - * @details The sender is stopped until the receiver executes a - * @p chMsgRelease()after receiving the message. - * - * @param[in] tp the pointer to the thread - * @param[in] msg the message - * @return The answer message from @p chMsgRelease(). - * - * @api - */ -msg_t chMsgSend(thread_t *tp, msg_t msg) { - thread_t *ctp = currp; - - chDbgCheck(tp != NULL); - - chSysLock(); - ctp->p_msg = msg; - ctp->p_u.wtobjp = &tp->p_msgqueue; - msg_insert(ctp, &tp->p_msgqueue); - if (tp->p_state == CH_STATE_WTMSG) { - (void) chSchReadyI(tp); - } - chSchGoSleepS(CH_STATE_SNDMSGQ); - msg = ctp->p_u.rdymsg; - chSysUnlock(); - - return msg; -} - -/** - * @brief Suspends the thread and waits for an incoming message. - * @post After receiving a message the function @p chMsgGet() must be - * called in order to retrieve the message and then @p chMsgRelease() - * must be invoked in order to acknowledge the reception and send - * the answer. - * @note If the message is a pointer then you can assume that the data - * pointed by the message is stable until you invoke @p chMsgRelease() - * because the sending thread is suspended until then. - * - * @return A reference to the thread carrying the message. - * - * @api - */ -thread_t *chMsgWait(void) { - thread_t *tp; - - chSysLock(); - if (!chMsgIsPendingI(currp)) { - chSchGoSleepS(CH_STATE_WTMSG); - } - tp = queue_fifo_remove(&currp->p_msgqueue); - tp->p_state = CH_STATE_SNDMSG; - chSysUnlock(); - - return tp; -} - -/** - * @brief Releases a sender thread specifying a response message. - * @pre Invoke this function only after a message has been received - * using @p chMsgWait(). - * - * @param[in] tp pointer to the thread - * @param[in] msg message to be returned to the sender - * - * @api - */ -void chMsgRelease(thread_t *tp, msg_t msg) { - - chSysLock(); - chDbgAssert(tp->p_state == CH_STATE_SNDMSG, "invalid state"); - chMsgReleaseS(tp, msg); - chSysUnlock(); -} - -#endif /* CH_CFG_USE_MESSAGES == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/src/chmtx.c b/firmware/ChibiOS_16/os/rt/src/chmtx.c deleted file mode 100644 index e30db8db27..0000000000 --- a/firmware/ChibiOS_16/os/rt/src/chmtx.c +++ /dev/null @@ -1,518 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chmtx.c - * @brief Mutexes code. - * - * @addtogroup mutexes - * @details Mutexes related APIs and services. - *

Operation mode

- * A mutex is a threads synchronization object that can be in two - * distinct states: - * - Not owned (unlocked). - * - Owned by a thread (locked). - * . - * Operations defined for mutexes: - * - Lock: The mutex is checked, if the mutex is not owned by - * some other thread then it is associated to the locking thread - * else the thread is queued on the mutex in a list ordered by - * priority. - * - Unlock: The mutex is released by the owner and the highest - * priority thread waiting in the queue, if any, is resumed and made - * owner of the mutex. - * . - *

Constraints

- * In ChibiOS/RT the Unlock operations must always be performed - * in lock-reverse order. This restriction both improves the - * performance and is required for an efficient implementation - * of the priority inheritance mechanism.
- * Operating under this restriction also ensures that deadlocks - * are no possible. - * - *

Recursive mode

- * By default mutexes are not recursive, this mean that it is not - * possible to take a mutex already owned by the same thread. - * It is possible to enable the recursive behavior by enabling the - * option @p CH_CFG_USE_MUTEXES_RECURSIVE. - * - *

The priority inversion problem

- * The mutexes in ChibiOS/RT implements the full priority - * inheritance mechanism in order handle the priority inversion - * problem.
- * When a thread is queued on a mutex, any thread, directly or - * indirectly, holding the mutex gains the same priority of the - * waiting thread (if their priority was not already equal or higher). - * The mechanism works with any number of nested mutexes and any - * number of involved threads. The algorithm complexity (worst case) - * is N with N equal to the number of nested mutexes. - * @pre In order to use the mutex APIs the @p CH_CFG_USE_MUTEXES option - * must be enabled in @p chconf.h. - * @post Enabling mutexes requires 5-12 (depending on the architecture) - * extra bytes in the @p thread_t structure. - * @{ - */ - -#include "ch.h" - -#if (CH_CFG_USE_MUTEXES == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -/** - * @brief Initializes s @p mutex_t structure. - * - * @param[out] mp pointer to a @p mutex_t structure - * - * @init - */ -void chMtxObjectInit(mutex_t *mp) { - - chDbgCheck(mp != NULL); - - queue_init(&mp->m_queue); - mp->m_owner = NULL; -#if CH_CFG_USE_MUTEXES_RECURSIVE == TRUE - mp->m_cnt = (cnt_t)0; -#endif -} - -/** - * @brief Locks the specified mutex. - * @post The mutex is locked and inserted in the per-thread stack of owned - * mutexes. - * - * @param[in] mp pointer to the @p mutex_t structure - * - * @api - */ -void chMtxLock(mutex_t *mp) { - - chSysLock(); - chMtxLockS(mp); - chSysUnlock(); -} - -/** - * @brief Locks the specified mutex. - * @post The mutex is locked and inserted in the per-thread stack of owned - * mutexes. - * - * @param[in] mp pointer to the @p mutex_t structure - * - * @sclass - */ -void chMtxLockS(mutex_t *mp) { - thread_t *ctp = currp; - - chDbgCheckClassS(); - chDbgCheck(mp != NULL); - - /* Is the mutex already locked? */ - if (mp->m_owner != NULL) { -#if CH_CFG_USE_MUTEXES_RECURSIVE == TRUE - - chDbgAssert(mp->m_cnt >= (cnt_t)1, "counter is not positive"); - - /* If the mutex is already owned by this thread, the counter is increased - and there is no need of more actions.*/ - if (mp->m_owner == ctp) { - mp->m_cnt++; - } - else { -#endif - /* Priority inheritance protocol; explores the thread-mutex dependencies - boosting the priority of all the affected threads to equal the - priority of the running thread requesting the mutex.*/ - thread_t *tp = mp->m_owner; - - /* Does the running thread have higher priority than the mutex - owning thread? */ - while (tp->p_prio < ctp->p_prio) { - /* Make priority of thread tp match the running thread's priority.*/ - tp->p_prio = ctp->p_prio; - - /* The following states need priority queues reordering.*/ - switch (tp->p_state) { - case CH_STATE_WTMTX: - /* Re-enqueues the mutex owner with its new priority.*/ - queue_prio_insert(queue_dequeue(tp), &tp->p_u.wtmtxp->m_queue); - tp = tp->p_u.wtmtxp->m_owner; - /*lint -e{9042} [16.1] Continues the while.*/ - continue; -#if (CH_CFG_USE_CONDVARS == TRUE) || \ - ((CH_CFG_USE_SEMAPHORES == TRUE) && \ - (CH_CFG_USE_SEMAPHORES_PRIORITY == TRUE)) || \ - ((CH_CFG_USE_MESSAGES == TRUE) && \ - (CH_CFG_USE_MESSAGES_PRIORITY == TRUE)) -#if CH_CFG_USE_CONDVARS == TRUE - case CH_STATE_WTCOND: -#endif -#if (CH_CFG_USE_SEMAPHORES == TRUE) && \ - (CH_CFG_USE_SEMAPHORES_PRIORITY == TRUE) - case CH_STATE_WTSEM: -#endif -#if (CH_CFG_USE_MESSAGES == TRUE) && (CH_CFG_USE_MESSAGES_PRIORITY == TRUE) - case CH_STATE_SNDMSGQ: -#endif - /* Re-enqueues tp with its new priority on the queue.*/ - queue_prio_insert(queue_dequeue(tp), &tp->p_u.wtmtxp->m_queue); - break; -#endif - case CH_STATE_READY: -#if CH_DBG_ENABLE_ASSERTS == TRUE - /* Prevents an assertion in chSchReadyI().*/ - tp->p_state = CH_STATE_CURRENT; -#endif - /* Re-enqueues tp with its new priority on the ready list.*/ - (void) chSchReadyI(queue_dequeue(tp)); - break; - default: - /* Nothing to do for other states.*/ - break; - } - break; - } - - /* Sleep on the mutex.*/ - queue_prio_insert(ctp, &mp->m_queue); - ctp->p_u.wtmtxp = mp; - chSchGoSleepS(CH_STATE_WTMTX); - - /* It is assumed that the thread performing the unlock operation assigns - the mutex to this thread.*/ - chDbgAssert(mp->m_owner == ctp, "not owner"); - chDbgAssert(ctp->p_mtxlist == mp, "not owned"); -#if CH_CFG_USE_MUTEXES_RECURSIVE == TRUE - chDbgAssert(mp->m_cnt == (cnt_t)1, "counter is not one"); - } -#endif - } - else { -#if CH_CFG_USE_MUTEXES_RECURSIVE == TRUE - chDbgAssert(mp->m_cnt == (cnt_t)0, "counter is not zero"); - - mp->m_cnt++; -#endif - /* It was not owned, inserted in the owned mutexes list.*/ - mp->m_owner = ctp; - mp->m_next = ctp->p_mtxlist; - ctp->p_mtxlist = mp; - } -} - -/** - * @brief Tries to lock a mutex. - * @details This function attempts to lock a mutex, if the mutex is already - * locked by another thread then the function exits without waiting. - * @post The mutex is locked and inserted in the per-thread stack of owned - * mutexes. - * @note This function does not have any overhead related to the - * priority inheritance mechanism because it does not try to - * enter a sleep state. - * - * @param[in] mp pointer to the @p mutex_t structure - * @return The operation status. - * @retval true if the mutex has been successfully acquired - * @retval false if the lock attempt failed. - * - * @api - */ -bool chMtxTryLock(mutex_t *mp) { - bool b; - - chSysLock(); - b = chMtxTryLockS(mp); - chSysUnlock(); - - return b; -} - -/** - * @brief Tries to lock a mutex. - * @details This function attempts to lock a mutex, if the mutex is already - * taken by another thread then the function exits without waiting. - * @post The mutex is locked and inserted in the per-thread stack of owned - * mutexes. - * @note This function does not have any overhead related to the - * priority inheritance mechanism because it does not try to - * enter a sleep state. - * - * @param[in] mp pointer to the @p mutex_t structure - * @return The operation status. - * @retval true if the mutex has been successfully acquired - * @retval false if the lock attempt failed. - * - * @sclass - */ -bool chMtxTryLockS(mutex_t *mp) { - - chDbgCheckClassS(); - chDbgCheck(mp != NULL); - - if (mp->m_owner != NULL) { -#if CH_CFG_USE_MUTEXES_RECURSIVE == TRUE - - chDbgAssert(mp->m_cnt >= (cnt_t)1, "counter is not positive"); - - if (mp->m_owner == currp) { - mp->m_cnt++; - return true; - } -#endif - return false; - } -#if CH_CFG_USE_MUTEXES_RECURSIVE == TRUE - - chDbgAssert(mp->m_cnt == (cnt_t)0, "counter is not zero"); - - mp->m_cnt++; -#endif - mp->m_owner = currp; - mp->m_next = currp->p_mtxlist; - currp->p_mtxlist = mp; - return true; -} - -/** - * @brief Unlocks the specified mutex. - * @note Mutexes must be unlocked in reverse lock order. Violating this - * rules will result in a panic if assertions are enabled. - * @pre The invoking thread must have at least one owned mutex. - * @post The mutex is unlocked and removed from the per-thread stack of - * owned mutexes. - * - * @param[in] mp pointer to the @p mutex_t structure - * - * @api - */ -void chMtxUnlock(mutex_t *mp) { - thread_t *ctp = currp; - mutex_t *lmp; - - chDbgCheck(mp != NULL); - - chSysLock(); - - chDbgAssert(ctp->p_mtxlist != NULL, "owned mutexes list empty"); - chDbgAssert(ctp->p_mtxlist->m_owner == ctp, "ownership failure"); -#if CH_CFG_USE_MUTEXES_RECURSIVE == TRUE - chDbgAssert(mp->m_cnt >= (cnt_t)1, "counter is not positive"); - - if (--mp->m_cnt == (cnt_t)0) { -#endif - - chDbgAssert(ctp->p_mtxlist == mp, "not next in list"); - - /* Removes the top mutex from the thread's owned mutexes list and marks - it as not owned. Note, it is assumed to be the same mutex passed as - parameter of this function.*/ - ctp->p_mtxlist = mp->m_next; - - /* If a thread is waiting on the mutex then the fun part begins.*/ - if (chMtxQueueNotEmptyS(mp)) { - thread_t *tp; - - /* Recalculates the optimal thread priority by scanning the owned - mutexes list.*/ - tprio_t newprio = ctp->p_realprio; - lmp = ctp->p_mtxlist; - while (lmp != NULL) { - /* If the highest priority thread waiting in the mutexes list has a - greater priority than the current thread base priority then the - final priority will have at least that priority.*/ - if (chMtxQueueNotEmptyS(lmp) && - (lmp->m_queue.p_next->p_prio > newprio)) { - newprio = lmp->m_queue.p_next->p_prio; - } - lmp = lmp->m_next; - } - - /* Assigns to the current thread the highest priority among all the - waiting threads.*/ - ctp->p_prio = newprio; - - /* Awakens the highest priority thread waiting for the unlocked mutex and - assigns the mutex to it.*/ -#if CH_CFG_USE_MUTEXES_RECURSIVE == TRUE - mp->m_cnt = (cnt_t)1; -#endif - tp = queue_fifo_remove(&mp->m_queue); - mp->m_owner = tp; - mp->m_next = tp->p_mtxlist; - tp->p_mtxlist = mp; - - /* Note, not using chSchWakeupS() becuase that function expects the - current thread to have the higher or equal priority than the ones - in the ready list. This is not necessarily true here because we - just changed priority.*/ - (void) chSchReadyI(tp); - chSchRescheduleS(); - } - else { - mp->m_owner = NULL; - } -#if CH_CFG_USE_MUTEXES_RECURSIVE == TRUE - } -#endif - - chSysUnlock(); -} - -/** - * @brief Unlocks the specified mutex. - * @note Mutexes must be unlocked in reverse lock order. Violating this - * rules will result in a panic if assertions are enabled. - * @pre The invoking thread must have at least one owned mutex. - * @post The mutex is unlocked and removed from the per-thread stack of - * owned mutexes. - * @post This function does not reschedule so a call to a rescheduling - * function must be performed before unlocking the kernel. - * - * @param[in] mp pointer to the @p mutex_t structure - * - * @sclass - */ -void chMtxUnlockS(mutex_t *mp) { - thread_t *ctp = currp; - mutex_t *lmp; - - chDbgCheckClassS(); - chDbgCheck(mp != NULL); - - chDbgAssert(ctp->p_mtxlist != NULL, "owned mutexes list empty"); - chDbgAssert(ctp->p_mtxlist->m_owner == ctp, "ownership failure"); -#if CH_CFG_USE_MUTEXES_RECURSIVE == TRUE - chDbgAssert(mp->m_cnt >= (cnt_t)1, "counter is not positive"); - - if (--mp->m_cnt == (cnt_t)0) { -#endif - - chDbgAssert(ctp->p_mtxlist == mp, "not next in list"); - - /* Removes the top mutex from the thread's owned mutexes list and marks - it as not owned. Note, it is assumed to be the same mutex passed as - parameter of this function.*/ - ctp->p_mtxlist = mp->m_next; - - /* If a thread is waiting on the mutex then the fun part begins.*/ - if (chMtxQueueNotEmptyS(mp)) { - thread_t *tp; - - /* Recalculates the optimal thread priority by scanning the owned - mutexes list.*/ - tprio_t newprio = ctp->p_realprio; - lmp = ctp->p_mtxlist; - while (lmp != NULL) { - /* If the highest priority thread waiting in the mutexes list has a - greater priority than the current thread base priority then the - final priority will have at least that priority.*/ - if (chMtxQueueNotEmptyS(lmp) && - (lmp->m_queue.p_next->p_prio > newprio)) { - newprio = lmp->m_queue.p_next->p_prio; - } - lmp = lmp->m_next; - } - - /* Assigns to the current thread the highest priority among all the - waiting threads.*/ - ctp->p_prio = newprio; - - /* Awakens the highest priority thread waiting for the unlocked mutex and - assigns the mutex to it.*/ -#if CH_CFG_USE_MUTEXES_RECURSIVE == TRUE - mp->m_cnt = (cnt_t)1; -#endif - tp = queue_fifo_remove(&mp->m_queue); - mp->m_owner = tp; - mp->m_next = tp->p_mtxlist; - tp->p_mtxlist = mp; - (void) chSchReadyI(tp); - } - else { - mp->m_owner = NULL; - } -#if CH_CFG_USE_MUTEXES_RECURSIVE == TRUE - } -#endif -} - -/** - * @brief Unlocks all mutexes owned by the invoking thread. - * @post The stack of owned mutexes is emptied and all the found - * mutexes are unlocked. - * @note This function is MUCH MORE efficient than releasing the - * mutexes one by one and not just because the call overhead, - * this function does not have any overhead related to the priority - * inheritance mechanism. - * - * @api - */ -void chMtxUnlockAll(void) { - thread_t *ctp = currp; - - chSysLock(); - if (ctp->p_mtxlist != NULL) { - do { - mutex_t *mp = ctp->p_mtxlist; - ctp->p_mtxlist = mp->m_next; - if (chMtxQueueNotEmptyS(mp)) { -#if CH_CFG_USE_MUTEXES_RECURSIVE == TRUE - mp->m_cnt = (cnt_t)1; -#endif - thread_t *tp = queue_fifo_remove(&mp->m_queue); - mp->m_owner = tp; - mp->m_next = tp->p_mtxlist; - tp->p_mtxlist = mp; - (void) chSchReadyI(tp); - } - else { -#if CH_CFG_USE_MUTEXES_RECURSIVE == TRUE - mp->m_cnt = (cnt_t)0; -#endif - mp->m_owner = NULL; - } - } while (ctp->p_mtxlist != NULL); - ctp->p_prio = ctp->p_realprio; - chSchRescheduleS(); - } - chSysUnlock(); -} - -#endif /* CH_CFG_USE_MUTEXES == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/src/chqueues.c b/firmware/ChibiOS_16/os/rt/src/chqueues.c deleted file mode 100644 index aba717d795..0000000000 --- a/firmware/ChibiOS_16/os/rt/src/chqueues.c +++ /dev/null @@ -1,446 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chqueues.c - * @brief I/O Queues code. - * - * @addtogroup io_queues - * @details ChibiOS/RT queues are mostly used in serial-like device drivers. - * The device drivers are usually designed to have a lower side - * (lower driver, it is usually an interrupt service routine) and an - * upper side (upper driver, accessed by the application threads).
- * There are several kind of queues:
- * - Input queue, unidirectional queue where the writer is the - * lower side and the reader is the upper side. - * - Output queue, unidirectional queue where the writer is the - * upper side and the reader is the lower side. - * - Full duplex queue, bidirectional queue. Full duplex queues - * are implemented by pairing an input queue and an output queue - * together. - * . - * @pre In order to use the I/O queues the @p CH_CFG_USE_QUEUES option must - * be enabled in @p chconf.h. - * @{ - */ - -#include "ch.h" - -#if (CH_CFG_USE_QUEUES == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Module local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -/** - * @brief Initializes an input queue. - * @details A Semaphore is internally initialized and works as a counter of - * the bytes contained in the queue. - * @note The callback is invoked from within the S-Locked system state, - * see @ref system_states. - * - * @param[out] iqp pointer to an @p input_queue_t structure - * @param[in] bp pointer to a memory area allocated as queue buffer - * @param[in] size size of the queue buffer - * @param[in] infy pointer to a callback function that is invoked when - * data is read from the queue. The value can be @p NULL. - * @param[in] link application defined pointer - * - * @init - */ -void chIQObjectInit(input_queue_t *iqp, uint8_t *bp, size_t size, - qnotify_t infy, void *link) { - - chThdQueueObjectInit(&iqp->q_waiting); - iqp->q_counter = 0; - iqp->q_buffer = bp; - iqp->q_rdptr = bp; - iqp->q_wrptr = bp; - iqp->q_top = bp + size; - iqp->q_notify = infy; - iqp->q_link = link; -} - -/** - * @brief Resets an input queue. - * @details All the data in the input queue is erased and lost, any waiting - * thread is resumed with status @p Q_RESET. - * @note A reset operation can be used by a low level driver in order to - * obtain immediate attention from the high level layers. - * - * @param[in] iqp pointer to an @p input_queue_t structure - * - * @iclass - */ -void chIQResetI(input_queue_t *iqp) { - - chDbgCheckClassI(); - - iqp->q_rdptr = iqp->q_buffer; - iqp->q_wrptr = iqp->q_buffer; - iqp->q_counter = 0; - chThdDequeueAllI(&iqp->q_waiting, Q_RESET); -} - -/** - * @brief Input queue write. - * @details A byte value is written into the low end of an input queue. - * - * @param[in] iqp pointer to an @p input_queue_t structure - * @param[in] b the byte value to be written in the queue - * @return The operation status. - * @retval Q_OK if the operation has been completed with success. - * @retval Q_FULL if the queue is full and the operation cannot be - * completed. - * - * @iclass - */ -msg_t chIQPutI(input_queue_t *iqp, uint8_t b) { - - chDbgCheckClassI(); - - if (chIQIsFullI(iqp)) { - return Q_FULL; - } - - iqp->q_counter++; - *iqp->q_wrptr++ = b; - if (iqp->q_wrptr >= iqp->q_top) { - iqp->q_wrptr = iqp->q_buffer; - } - - chThdDequeueNextI(&iqp->q_waiting, Q_OK); - - return Q_OK; -} - -/** - * @brief Input queue read with timeout. - * @details This function reads a byte value from an input queue. If the queue - * is empty then the calling thread is suspended until a byte arrives - * in the queue or a timeout occurs. - * @note The callback is invoked before reading the character from the - * buffer or before entering the state @p CH_STATE_WTQUEUE. - * - * @param[in] iqp pointer to an @p input_queue_t structure - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return A byte value from the queue. - * @retval Q_TIMEOUT if the specified time expired. - * @retval Q_RESET if the queue has been reset. - * - * @api - */ -msg_t chIQGetTimeout(input_queue_t *iqp, systime_t timeout) { - uint8_t b; - - chSysLock(); - if (iqp->q_notify != NULL) { - iqp->q_notify(iqp); - } - - while (chIQIsEmptyI(iqp)) { - msg_t msg = chThdEnqueueTimeoutS(&iqp->q_waiting, timeout); - if (msg < Q_OK) { - chSysUnlock(); - return msg; - } - } - - iqp->q_counter--; - b = *iqp->q_rdptr++; - if (iqp->q_rdptr >= iqp->q_top) { - iqp->q_rdptr = iqp->q_buffer; - } - chSysUnlock(); - - return (msg_t)b; -} - -/** - * @brief Input queue read with timeout. - * @details The function reads data from an input queue into a buffer. The - * operation completes when the specified amount of data has been - * transferred or after the specified timeout or if the queue has - * been reset. - * @note The function is not atomic, if you need atomicity it is suggested - * to use a semaphore or a mutex for mutual exclusion. - * @note The callback is invoked before reading each character from the - * buffer or before entering the state @p CH_STATE_WTQUEUE. - * - * @param[in] iqp pointer to an @p input_queue_t structure - * @param[out] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred, the - * value 0 is reserved - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The number of bytes effectively transferred. - * - * @api - */ -size_t chIQReadTimeout(input_queue_t *iqp, uint8_t *bp, - size_t n, systime_t timeout) { - qnotify_t nfy = iqp->q_notify; - size_t r = 0; - - chDbgCheck(n > 0U); - - chSysLock(); - while (true) { - if (nfy != NULL) { - nfy(iqp); - } - - while (chIQIsEmptyI(iqp)) { - if (chThdEnqueueTimeoutS(&iqp->q_waiting, timeout) != Q_OK) { - chSysUnlock(); - return r; - } - } - - iqp->q_counter--; - *bp++ = *iqp->q_rdptr++; - if (iqp->q_rdptr >= iqp->q_top) { - iqp->q_rdptr = iqp->q_buffer; - } - chSysUnlock(); /* Gives a preemption chance in a controlled point.*/ - - r++; - if (--n == 0U) { - return r; - } - - chSysLock(); - } -} - -/** - * @brief Initializes an output queue. - * @details A Semaphore is internally initialized and works as a counter of - * the free bytes in the queue. - * @note The callback is invoked from within the S-Locked system state, - * see @ref system_states. - * - * @param[out] oqp pointer to an @p output_queue_t structure - * @param[in] bp pointer to a memory area allocated as queue buffer - * @param[in] size size of the queue buffer - * @param[in] onfy pointer to a callback function that is invoked when - * data is written to the queue. The value can be @p NULL. - * @param[in] link application defined pointer - * - * @init - */ -void chOQObjectInit(output_queue_t *oqp, uint8_t *bp, size_t size, - qnotify_t onfy, void *link) { - - chThdQueueObjectInit(&oqp->q_waiting); - oqp->q_counter = size; - oqp->q_buffer = bp; - oqp->q_rdptr = bp; - oqp->q_wrptr = bp; - oqp->q_top = bp + size; - oqp->q_notify = onfy; - oqp->q_link = link; -} - -/** - * @brief Resets an output queue. - * @details All the data in the output queue is erased and lost, any waiting - * thread is resumed with status @p Q_RESET. - * @note A reset operation can be used by a low level driver in order to - * obtain immediate attention from the high level layers. - * - * @param[in] oqp pointer to an @p output_queue_t structure - * - * @iclass - */ -void chOQResetI(output_queue_t *oqp) { - - chDbgCheckClassI(); - - oqp->q_rdptr = oqp->q_buffer; - oqp->q_wrptr = oqp->q_buffer; - oqp->q_counter = chQSizeX(oqp); - chThdDequeueAllI(&oqp->q_waiting, Q_RESET); -} - -/** - * @brief Output queue write with timeout. - * @details This function writes a byte value to an output queue. If the queue - * is full then the calling thread is suspended until there is space - * in the queue or a timeout occurs. - * @note The callback is invoked after writing the character into the - * buffer. - * - * @param[in] oqp pointer to an @p output_queue_t structure - * @param[in] b the byte value to be written in the queue - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval Q_OK if the operation succeeded. - * @retval Q_TIMEOUT if the specified time expired. - * @retval Q_RESET if the queue has been reset. - * - * @api - */ -msg_t chOQPutTimeout(output_queue_t *oqp, uint8_t b, systime_t timeout) { - - chSysLock(); - while (chOQIsFullI(oqp)) { - msg_t msg = chThdEnqueueTimeoutS(&oqp->q_waiting, timeout); - if (msg < Q_OK) { - chSysUnlock(); - return msg; - } - } - - oqp->q_counter--; - *oqp->q_wrptr++ = b; - if (oqp->q_wrptr >= oqp->q_top) { - oqp->q_wrptr = oqp->q_buffer; - } - - if (oqp->q_notify != NULL) { - oqp->q_notify(oqp); - } - chSysUnlock(); - - return Q_OK; -} - -/** - * @brief Output queue read. - * @details A byte value is read from the low end of an output queue. - * - * @param[in] oqp pointer to an @p output_queue_t structure - * @return The byte value from the queue. - * @retval Q_EMPTY if the queue is empty. - * - * @iclass - */ -msg_t chOQGetI(output_queue_t *oqp) { - uint8_t b; - - chDbgCheckClassI(); - - if (chOQIsEmptyI(oqp)) { - return Q_EMPTY; - } - - oqp->q_counter++; - b = *oqp->q_rdptr++; - if (oqp->q_rdptr >= oqp->q_top) { - oqp->q_rdptr = oqp->q_buffer; - } - - chThdDequeueNextI(&oqp->q_waiting, Q_OK); - - return (msg_t)b; -} - -/** - * @brief Output queue write with timeout. - * @details The function writes data from a buffer to an output queue. The - * operation completes when the specified amount of data has been - * transferred or after the specified timeout or if the queue has - * been reset. - * @note The function is not atomic, if you need atomicity it is suggested - * to use a semaphore or a mutex for mutual exclusion. - * @note The callback is invoked after writing each character into the - * buffer. - * - * @param[in] oqp pointer to an @p output_queue_t structure - * @param[in] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred, the - * value 0 is reserved - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The number of bytes effectively transferred. - * - * @api - */ -size_t chOQWriteTimeout(output_queue_t *oqp, const uint8_t *bp, - size_t n, systime_t timeout) { - qnotify_t nfy = oqp->q_notify; - size_t w = 0; - - chDbgCheck(n > 0U); - - chSysLock(); - while (true) { - while (chOQIsFullI(oqp)) { - if (chThdEnqueueTimeoutS(&oqp->q_waiting, timeout) != Q_OK) { - chSysUnlock(); - return w; - } - } - - oqp->q_counter--; - *oqp->q_wrptr++ = *bp++; - if (oqp->q_wrptr >= oqp->q_top) { - oqp->q_wrptr = oqp->q_buffer; - } - - if (nfy != NULL) { - nfy(oqp); - } - chSysUnlock(); /* Gives a preemption chance in a controlled point.*/ - - w++; - if (--n == 0U) { - return w; - } - chSysLock(); - } -} -#endif /* CH_CFG_USE_QUEUES == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/src/chregistry.c b/firmware/ChibiOS_16/os/rt/src/chregistry.c deleted file mode 100644 index 666b35568a..0000000000 --- a/firmware/ChibiOS_16/os/rt/src/chregistry.c +++ /dev/null @@ -1,181 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chregistry.c - * @brief Threads registry code. - * - * @addtogroup registry - * @details Threads Registry related APIs and services. - *

Operation mode

- * The Threads Registry is a double linked list that holds all the - * active threads in the system.
- * Operations defined for the registry: - * - First, returns the first, in creation order, active thread - * in the system. - * - Next, returns the next, in creation order, active thread - * in the system. - * . - * The registry is meant to be mainly a debug feature, for example, - * using the registry a debugger can enumerate the active threads - * in any given moment or the shell can print the active threads - * and their state.
- * Another possible use is for centralized threads memory management, - * terminating threads can pulse an event source and an event handler - * can perform a scansion of the registry in order to recover the - * memory. - * @pre In order to use the threads registry the @p CH_CFG_USE_REGISTRY - * option must be enabled in @p chconf.h. - * @{ - */ -#include "ch.h" - -#if (CH_CFG_USE_REGISTRY == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -#define _offsetof(st, m) \ - /*lint -save -e9005 -e9033 -e413 [11.8, 10.8 1.3] Normal pointers - arithmetic, it is safe.*/ \ - ((size_t)((char *)&((st *)0)->m - (char *)0)) \ - /*lint -restore*/ - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -/* - * OS signature in ROM plus debug-related information. - */ -ROMCONST chdebug_t ch_debug = { - {'m', 'a', 'i', 'n'}, - (uint8_t)0, - (uint8_t)sizeof (chdebug_t), - (uint16_t)(((unsigned)CH_KERNEL_MAJOR << 11U) | - ((unsigned)CH_KERNEL_MINOR << 6U) | - ((unsigned)CH_KERNEL_PATCH << 0U)), - (uint8_t)sizeof (void *), - (uint8_t)sizeof (systime_t), - (uint8_t)sizeof (thread_t), - (uint8_t)_offsetof(thread_t, p_prio), - (uint8_t)_offsetof(thread_t, p_ctx), - (uint8_t)_offsetof(thread_t, p_newer), - (uint8_t)_offsetof(thread_t, p_older), - (uint8_t)_offsetof(thread_t, p_name), -#if CH_DBG_ENABLE_STACK_CHECK == TRUE - (uint8_t)_offsetof(thread_t, p_stklimit), -#else - (uint8_t)0, -#endif - (uint8_t)_offsetof(thread_t, p_state), - (uint8_t)_offsetof(thread_t, p_flags), -#if CH_CFG_USE_DYNAMIC == TRUE - (uint8_t)_offsetof(thread_t, p_refs), -#else - (uint8_t)0, -#endif -#if CH_CFG_TIME_QUANTUM > 0 - (uint8_t)_offsetof(thread_t, p_preempt), -#else - (uint8_t)0, -#endif -#if CH_DBG_THREADS_PROFILING == TRUE - (uint8_t)_offsetof(thread_t, p_time) -#else - (uint8_t)0 -#endif -}; - -/** - * @brief Returns the first thread in the system. - * @details Returns the most ancient thread in the system, usually this is - * the main thread unless it terminated. A reference is added to the - * returned thread in order to make sure its status is not lost. - * @note This function cannot return @p NULL because there is always at - * least one thread in the system. - * - * @return A reference to the most ancient thread. - * - * @api - */ -thread_t *chRegFirstThread(void) { - thread_t *tp; - - chSysLock(); - tp = ch.rlist.r_newer; -#if CH_CFG_USE_DYNAMIC == TRUE - tp->p_refs++; -#endif - chSysUnlock(); - - return tp; -} - -/** - * @brief Returns the thread next to the specified one. - * @details The reference counter of the specified thread is decremented and - * the reference counter of the returned thread is incremented. - * - * @param[in] tp pointer to the thread - * @return A reference to the next thread. - * @retval NULL if there is no next thread. - * - * @api - */ -thread_t *chRegNextThread(thread_t *tp) { - thread_t *ntp; - - chSysLock(); - ntp = tp->p_newer; - /*lint -save -e9087 -e740 [11.3, 1.3] Cast required by list handling.*/ - if (ntp == (thread_t *)&ch.rlist) { - /*lint -restore*/ - ntp = NULL; - } -#if CH_CFG_USE_DYNAMIC == TRUE - else { - chDbgAssert(ntp->p_refs < (trefs_t)255, "too many references"); - ntp->p_refs++; - } -#endif - chSysUnlock(); -#if CH_CFG_USE_DYNAMIC == TRUE - chThdRelease(tp); -#endif - - return ntp; -} - -#endif /* CH_CFG_USE_REGISTRY == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/src/chschd.c b/firmware/ChibiOS_16/os/rt/src/chschd.c deleted file mode 100644 index edf70e8e3f..0000000000 --- a/firmware/ChibiOS_16/os/rt/src/chschd.c +++ /dev/null @@ -1,542 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chschd.c - * @brief Scheduler code. - * - * @addtogroup scheduler - * @details This module provides the default portable scheduler code. - * @{ - */ - -#include "ch.h" - -/*===========================================================================*/ -/* Module local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -/** - * @brief System data structures. - */ -ch_system_t ch; - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -/** - * @brief Scheduler initialization. - * - * @notapi - */ -void _scheduler_init(void) { - - queue_init(&ch.rlist.r_queue); - ch.rlist.r_prio = NOPRIO; -#if CH_CFG_USE_REGISTRY == TRUE - ch.rlist.r_newer = (thread_t *)&ch.rlist; - ch.rlist.r_older = (thread_t *)&ch.rlist; -#endif -} - -#if (CH_CFG_OPTIMIZE_SPEED == FALSE) || defined(__DOXYGEN__) -/** - * @brief Inserts a thread into a priority ordered queue. - * @note The insertion is done by scanning the list from the highest - * priority toward the lowest. - * - * @param[in] tp the pointer to the thread to be inserted in the list - * @param[in] tqp the pointer to the threads list header - * - * @notapi - */ -void queue_prio_insert(thread_t *tp, threads_queue_t *tqp) { - - thread_t *cp = (thread_t *)tqp; - do { - cp = cp->p_next; - } while ((cp != (thread_t *)tqp) && (cp->p_prio >= tp->p_prio)); - tp->p_next = cp; - tp->p_prev = cp->p_prev; - tp->p_prev->p_next = tp; - cp->p_prev = tp; -} - -/** - * @brief Inserts a thread into a queue. - * - * @param[in] tp the pointer to the thread to be inserted in the list - * @param[in] tqp the pointer to the threads list header - * - * @notapi - */ -void queue_insert(thread_t *tp, threads_queue_t *tqp) { - - tp->p_next = (thread_t *)tqp; - tp->p_prev = tqp->p_prev; - tp->p_prev->p_next = tp; - tqp->p_prev = tp; -} - -/** - * @brief Removes the first-out thread from a queue and returns it. - * @note If the queue is priority ordered then this function returns the - * thread with the highest priority. - * - * @param[in] tqp the pointer to the threads list header - * @return The removed thread pointer. - * - * @notapi - */ -thread_t *queue_fifo_remove(threads_queue_t *tqp) { - thread_t *tp = tqp->p_next; - - tqp->p_next = tp->p_next; - tqp->p_next->p_prev = (thread_t *)tqp; - - return tp; -} - -/** - * @brief Removes the last-out thread from a queue and returns it. - * @note If the queue is priority ordered then this function returns the - * thread with the lowest priority. - * - * @param[in] tqp the pointer to the threads list header - * @return The removed thread pointer. - * - * @notapi - */ -thread_t *queue_lifo_remove(threads_queue_t *tqp) { - thread_t *tp = tqp->p_prev; - - tqp->p_prev = tp->p_prev; - tqp->p_prev->p_next = (thread_t *)tqp; - - return tp; -} - -/** - * @brief Removes a thread from a queue and returns it. - * @details The thread is removed from the queue regardless of its relative - * position and regardless the used insertion method. - * - * @param[in] tp the pointer to the thread to be removed from the queue - * @return The removed thread pointer. - * - * @notapi - */ -thread_t *queue_dequeue(thread_t *tp) { - - tp->p_prev->p_next = tp->p_next; - tp->p_next->p_prev = tp->p_prev; - - return tp; -} - -/** - * @brief Pushes a thread_t on top of a stack list. - * - * @param[in] tp the pointer to the thread to be inserted in the list - * @param[in] tlp the pointer to the threads list header - * - * @notapi - */ -void list_insert(thread_t *tp, threads_list_t *tlp) { - - tp->p_next = tlp->p_next; - tlp->p_next = tp; -} - -/** - * @brief Pops a thread from the top of a stack list and returns it. - * @pre The list must be non-empty before calling this function. - * - * @param[in] tlp the pointer to the threads list header - * @return The removed thread pointer. - * - * @notapi - */ -thread_t *list_remove(threads_list_t *tlp) { - - thread_t *tp = tlp->p_next; - tlp->p_next = tp->p_next; - - return tp; -} -#endif /* CH_CFG_OPTIMIZE_SPEED */ - -/** - * @brief Inserts a thread in the Ready List. - * @details The thread is positioned behind all threads with higher or equal - * priority. - * @pre The thread must not be already inserted in any list through its - * @p p_next and @p p_prev or list corruption would occur. - * @post This function does not reschedule so a call to a rescheduling - * function must be performed before unlocking the kernel. Note that - * interrupt handlers always reschedule on exit so an explicit - * reschedule must not be performed in ISRs. - * - * @param[in] tp the thread to be made ready - * @return The thread pointer. - * - * @iclass - */ -thread_t *chSchReadyI(thread_t *tp) { - thread_t *cp; - - chDbgCheckClassI(); - chDbgCheck(tp != NULL); - chDbgAssert((tp->p_state != CH_STATE_READY) && - (tp->p_state != CH_STATE_FINAL), - "invalid state"); - - tp->p_state = CH_STATE_READY; - cp = (thread_t *)&ch.rlist.r_queue; - do { - cp = cp->p_next; - } while (cp->p_prio >= tp->p_prio); - /* Insertion on p_prev.*/ - tp->p_next = cp; - tp->p_prev = cp->p_prev; - tp->p_prev->p_next = tp; - cp->p_prev = tp; - - return tp; -} - -/** - * @brief Puts the current thread to sleep into the specified state. - * @details The thread goes into a sleeping state. The possible - * @ref thread_states are defined into @p threads.h. - * - * @param[in] newstate the new thread state - * - * @sclass - */ -void chSchGoSleepS(tstate_t newstate) { - thread_t *otp; - - chDbgCheckClassS(); - - otp = currp; - otp->p_state = newstate; -#if CH_CFG_TIME_QUANTUM > 0 - /* The thread is renouncing its remaining time slices so it will have a new - time quantum when it will wakeup.*/ - otp->p_preempt = (tslices_t)CH_CFG_TIME_QUANTUM; -#endif - setcurrp(queue_fifo_remove(&ch.rlist.r_queue)); -#if defined(CH_CFG_IDLE_ENTER_HOOK) - if (currp->p_prio == IDLEPRIO) { - CH_CFG_IDLE_ENTER_HOOK(); - } -#endif - currp->p_state = CH_STATE_CURRENT; - chSysSwitch(currp, otp); -} - -/* - * Timeout wakeup callback. - */ -static void wakeup(void *p) { - thread_t *tp = (thread_t *)p; - - chSysLockFromISR(); - switch (tp->p_state) { - case CH_STATE_READY: - /* Handling the special case where the thread has been made ready by - another thread with higher priority.*/ - chSysUnlockFromISR(); - return; - case CH_STATE_SUSPENDED: - *tp->p_u.wttrp = NULL; - break; -#if CH_CFG_USE_SEMAPHORES == TRUE - case CH_STATE_WTSEM: - chSemFastSignalI(tp->p_u.wtsemp); - /* Falls into, intentional. */ -#endif -#if (CH_CFG_USE_CONDVARS == TRUE) && (CH_CFG_USE_CONDVARS_TIMEOUT == TRUE) - case CH_STATE_WTCOND: -#endif - case CH_STATE_QUEUED: - /* States requiring dequeuing.*/ - (void) queue_dequeue(tp); - break; - default: - /* Any other state, nothing to do.*/ - break; - } - tp->p_u.rdymsg = MSG_TIMEOUT; - (void) chSchReadyI(tp); - chSysUnlockFromISR(); -} - -/** - * @brief Puts the current thread to sleep into the specified state with - * timeout specification. - * @details The thread goes into a sleeping state, if it is not awakened - * explicitly within the specified timeout then it is forcibly - * awakened with a @p MSG_TIMEOUT low level message. The possible - * @ref thread_states are defined into @p threads.h. - * - * @param[in] newstate the new thread state - * @param[in] time the number of ticks before the operation timeouts, the - * special values are handled as follow: - * - @a TIME_INFINITE the thread enters an infinite sleep - * state, this is equivalent to invoking - * @p chSchGoSleepS() but, of course, less efficient. - * - @a TIME_IMMEDIATE this value is not allowed. - * . - * @return The wakeup message. - * @retval MSG_TIMEOUT if a timeout occurs. - * - * @sclass - */ -msg_t chSchGoSleepTimeoutS(tstate_t newstate, systime_t time) { - - chDbgCheckClassS(); - - if (TIME_INFINITE != time) { - virtual_timer_t vt; - - chVTDoSetI(&vt, time, wakeup, currp); - chSchGoSleepS(newstate); - if (chVTIsArmedI(&vt)) { - chVTDoResetI(&vt); - } - } - else { - chSchGoSleepS(newstate); - } - - return currp->p_u.rdymsg; -} - -/** - * @brief Wakes up a thread. - * @details The thread is inserted into the ready list or immediately made - * running depending on its relative priority compared to the current - * thread. - * @pre The thread must not be already inserted in any list through its - * @p p_next and @p p_prev or list corruption would occur. - * @note It is equivalent to a @p chSchReadyI() followed by a - * @p chSchRescheduleS() but much more efficient. - * @note The function assumes that the current thread has the highest - * priority. - * - * @param[in] ntp the thread to be made ready - * @param[in] msg the wakeup message - * - * @sclass - */ -void chSchWakeupS(thread_t *ntp, msg_t msg) { - - chDbgCheckClassS(); - - chDbgAssert((ch.rlist.r_queue.p_next == (thread_t *)&ch.rlist.r_queue) || - (ch.rlist.r_current->p_prio >= ch.rlist.r_queue.p_next->p_prio), - "priority order violation"); - - /* Storing the message to be retrieved by the target thread when it will - restart execution.*/ - ntp->p_u.rdymsg = msg; - - /* If the waken thread has a not-greater priority than the current - one then it is just inserted in the ready list else it made - running immediately and the invoking thread goes in the ready - list instead.*/ - if (ntp->p_prio <= currp->p_prio) { - (void) chSchReadyI(ntp); - } - else { - thread_t *otp = chSchReadyI(currp); - setcurrp(ntp); -#if defined(CH_CFG_IDLE_LEAVE_HOOK) - if (otp->p_prio == IDLEPRIO) { - CH_CFG_IDLE_LEAVE_HOOK(); - } -#endif - ntp->p_state = CH_STATE_CURRENT; - chSysSwitch(ntp, otp); - } -} - -/** - * @brief Performs a reschedule if a higher priority thread is runnable. - * @details If a thread with a higher priority than the current thread is in - * the ready list then make the higher priority thread running. - * - * @sclass - */ -void chSchRescheduleS(void) { - - chDbgCheckClassS(); - - if (chSchIsRescRequiredI()) { - chSchDoRescheduleAhead(); - } -} - -/** - * @brief Evaluates if preemption is required. - * @details The decision is taken by comparing the relative priorities and - * depending on the state of the round robin timeout counter. - * @note Not a user function, it is meant to be invoked by the scheduler - * itself or from within the port layer. - * - * @retval true if there is a thread that must go in running state - * immediately. - * @retval false if preemption is not required. - * - * @special - */ -bool chSchIsPreemptionRequired(void) { - tprio_t p1 = firstprio(&ch.rlist.r_queue); - tprio_t p2 = currp->p_prio; - -#if CH_CFG_TIME_QUANTUM > 0 - /* If the running thread has not reached its time quantum, reschedule only - if the first thread on the ready queue has a higher priority. - Otherwise, if the running thread has used up its time quantum, reschedule - if the first thread on the ready queue has equal or higher priority.*/ - return (currp->p_preempt > (tslices_t)0) ? (p1 > p2) : (p1 >= p2); -#else - /* If the round robin preemption feature is not enabled then performs a - simpler comparison.*/ - return p1 > p2; -#endif -} - -/** - * @brief Switches to the first thread on the runnable queue. - * @details The current thread is positioned in the ready list behind all - * threads having the same priority. The thread regains its time - * quantum. - * @note Not a user function, it is meant to be invoked by the scheduler - * itself or from within the port layer. - * - * @special - */ -void chSchDoRescheduleBehind(void) { - thread_t *otp; - - otp = currp; - /* Picks the first thread from the ready queue and makes it current.*/ - setcurrp(queue_fifo_remove(&ch.rlist.r_queue)); -#if defined(CH_CFG_IDLE_LEAVE_HOOK) - if (otp->p_prio == IDLEPRIO) { - CH_CFG_IDLE_LEAVE_HOOK(); - } -#endif - currp->p_state = CH_STATE_CURRENT; -#if CH_CFG_TIME_QUANTUM > 0 - otp->p_preempt = (tslices_t)CH_CFG_TIME_QUANTUM; -#endif - (void) chSchReadyI(otp); - chSysSwitch(currp, otp); -} - -/** - * @brief Switches to the first thread on the runnable queue. - * @details The current thread is positioned in the ready list ahead of all - * threads having the same priority. - * @note Not a user function, it is meant to be invoked by the scheduler - * itself or from within the port layer. - * - * @special - */ -void chSchDoRescheduleAhead(void) { - thread_t *otp, *cp; - - otp = currp; - /* Picks the first thread from the ready queue and makes it current.*/ - setcurrp(queue_fifo_remove(&ch.rlist.r_queue)); -#if defined(CH_CFG_IDLE_LEAVE_HOOK) - if (otp->p_prio == IDLEPRIO) { - CH_CFG_IDLE_LEAVE_HOOK(); - } -#endif - currp->p_state = CH_STATE_CURRENT; - - otp->p_state = CH_STATE_READY; - cp = (thread_t *)&ch.rlist.r_queue; - do { - cp = cp->p_next; - } while (cp->p_prio > otp->p_prio); - /* Insertion on p_prev.*/ - otp->p_next = cp; - otp->p_prev = cp->p_prev; - otp->p_prev->p_next = otp; - cp->p_prev = otp; - - chSysSwitch(currp, otp); -} - -/** - * @brief Switches to the first thread on the runnable queue. - * @details The current thread is positioned in the ready list behind or - * ahead of all threads having the same priority depending on - * if it used its whole time slice. - * @note Not a user function, it is meant to be invoked by the scheduler - * itself or from within the port layer. - * - * @special - */ -void chSchDoReschedule(void) { - -#if CH_CFG_TIME_QUANTUM > 0 - /* If CH_CFG_TIME_QUANTUM is enabled then there are two different scenarios - to handle on preemption: time quantum elapsed or not.*/ - if (currp->p_preempt == (tslices_t)0) { - /* The thread consumed its time quantum so it is enqueued behind threads - with same priority level, however, it acquires a new time quantum.*/ - chSchDoRescheduleBehind(); - } - else { - /* The thread didn't consume all its time quantum so it is put ahead of - threads with equal priority and does not acquire a new time quantum.*/ - chSchDoRescheduleAhead(); - } -#else /* !(CH_CFG_TIME_QUANTUM > 0) */ - /* If the round-robin mechanism is disabled then the thread goes always - ahead of its peers.*/ - chSchDoRescheduleAhead(); -#endif /* !(CH_CFG_TIME_QUANTUM > 0) */ -} - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/src/chsem.c b/firmware/ChibiOS_16/os/rt/src/chsem.c deleted file mode 100644 index 5c0f35ce0d..0000000000 --- a/firmware/ChibiOS_16/os/rt/src/chsem.c +++ /dev/null @@ -1,411 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chsem.c - * @brief Semaphores code. - * - * @addtogroup semaphores - * @details Semaphores related APIs and services. - *

Operation mode

- * Semaphores are a flexible synchronization primitive, ChibiOS/RT - * implements semaphores in their "counting semaphores" variant as - * defined by Edsger Dijkstra plus several enhancements like: - * - Wait operation with timeout. - * - Reset operation. - * - Atomic wait+signal operation. - * - Return message from the wait operation (OK, RESET, TIMEOUT). - * . - * The binary semaphores variant can be easily implemented using - * counting semaphores.
- * Operations defined for semaphores: - * - Signal: The semaphore counter is increased and if the - * result is non-positive then a waiting thread is removed from - * the semaphore queue and made ready for execution. - * - Wait: The semaphore counter is decreased and if the result - * becomes negative the thread is queued in the semaphore and - * suspended. - * - Reset: The semaphore counter is reset to a non-negative - * value and all the threads in the queue are released. - * . - * Semaphores can be used as guards for mutual exclusion zones - * (note that mutexes are recommended for this kind of use) but - * also have other uses, queues guards and counters for example.
- * Semaphores usually use a FIFO queuing strategy but it is possible - * to make them order threads by priority by enabling - * @p CH_CFG_USE_SEMAPHORES_PRIORITY in @p chconf.h. - * @pre In order to use the semaphore APIs the @p CH_CFG_USE_SEMAPHORES - * option must be enabled in @p chconf.h. - * @{ - */ - -#include "ch.h" - -#if (CH_CFG_USE_SEMAPHORES == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -#if CH_CFG_USE_SEMAPHORES_PRIORITY == TRUE -#define sem_insert(tp, qp) queue_prio_insert(tp, qp) -#else -#define sem_insert(tp, qp) queue_insert(tp, qp) -#endif - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -/** - * @brief Initializes a semaphore with the specified counter value. - * - * @param[out] sp pointer to a @p semaphore_t structure - * @param[in] n initial value of the semaphore counter. Must be - * non-negative. - * - * @init - */ -void chSemObjectInit(semaphore_t *sp, cnt_t n) { - - chDbgCheck((sp != NULL) && (n >= (cnt_t)0)); - - queue_init(&sp->s_queue); - sp->s_cnt = n; -} - -/** - * @brief Performs a reset operation on the semaphore. - * @post After invoking this function all the threads waiting on the - * semaphore, if any, are released and the semaphore counter is set - * to the specified, non negative, value. - * @note The released threads can recognize they were waked up by a reset - * rather than a signal because the @p chSemWait() will return - * @p MSG_RESET instead of @p MSG_OK. - * - * @param[in] sp pointer to a @p semaphore_t structure - * @param[in] n the new value of the semaphore counter. The value must - * be non-negative. - * - * @api - */ -void chSemReset(semaphore_t *sp, cnt_t n) { - - chSysLock(); - chSemResetI(sp, n); - chSchRescheduleS(); - chSysUnlock(); -} - -/** - * @brief Performs a reset operation on the semaphore. - * @post After invoking this function all the threads waiting on the - * semaphore, if any, are released and the semaphore counter is set - * to the specified, non negative, value. - * @post This function does not reschedule so a call to a rescheduling - * function must be performed before unlocking the kernel. Note that - * interrupt handlers always reschedule on exit so an explicit - * reschedule must not be performed in ISRs. - * @note The released threads can recognize they were waked up by a reset - * rather than a signal because the @p chSemWait() will return - * @p MSG_RESET instead of @p MSG_OK. - * - * @param[in] sp pointer to a @p semaphore_t structure - * @param[in] n the new value of the semaphore counter. The value must - * be non-negative. - * - * @iclass - */ -void chSemResetI(semaphore_t *sp, cnt_t n) { - cnt_t cnt; - - chDbgCheckClassI(); - chDbgCheck((sp != NULL) && (n >= (cnt_t)0)); - chDbgAssert(((sp->s_cnt >= (cnt_t)0) && queue_isempty(&sp->s_queue)) || - ((sp->s_cnt < (cnt_t)0) && queue_notempty(&sp->s_queue)), - "inconsistent semaphore"); - - cnt = sp->s_cnt; - sp->s_cnt = n; - while (++cnt <= (cnt_t)0) { - chSchReadyI(queue_lifo_remove(&sp->s_queue))->p_u.rdymsg = MSG_RESET; - } -} - -/** - * @brief Performs a wait operation on a semaphore. - * - * @param[in] sp pointer to a @p semaphore_t structure - * @return A message specifying how the invoking thread has been - * released from the semaphore. - * @retval MSG_OK if the thread has not stopped on the semaphore or the - * semaphore has been signaled. - * @retval MSG_RESET if the semaphore has been reset using @p chSemReset(). - * - * @api - */ -msg_t chSemWait(semaphore_t *sp) { - msg_t msg; - - chSysLock(); - msg = chSemWaitS(sp); - chSysUnlock(); - - return msg; -} - -/** - * @brief Performs a wait operation on a semaphore. - * - * @param[in] sp pointer to a @p semaphore_t structure - * @return A message specifying how the invoking thread has been - * released from the semaphore. - * @retval MSG_OK if the thread has not stopped on the semaphore or the - * semaphore has been signaled. - * @retval MSG_RESET if the semaphore has been reset using @p chSemReset(). - * - * @sclass - */ -msg_t chSemWaitS(semaphore_t *sp) { - - chDbgCheckClassS(); - chDbgCheck(sp != NULL); - chDbgAssert(((sp->s_cnt >= (cnt_t)0) && queue_isempty(&sp->s_queue)) || - ((sp->s_cnt < (cnt_t)0) && queue_notempty(&sp->s_queue)), - "inconsistent semaphore"); - - if (--sp->s_cnt < (cnt_t)0) { - currp->p_u.wtsemp = sp; - sem_insert(currp, &sp->s_queue); - chSchGoSleepS(CH_STATE_WTSEM); - - return currp->p_u.rdymsg; - } - - return MSG_OK; -} - -/** - * @brief Performs a wait operation on a semaphore with timeout specification. - * - * @param[in] sp pointer to a @p semaphore_t structure - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return A message specifying how the invoking thread has been - * released from the semaphore. - * @retval MSG_OK if the thread has not stopped on the semaphore or the - * semaphore has been signaled. - * @retval MSG_RESET if the semaphore has been reset using @p chSemReset(). - * @retval MSG_TIMEOUT if the semaphore has not been signaled or reset within - * the specified timeout. - * - * @api - */ -msg_t chSemWaitTimeout(semaphore_t *sp, systime_t time) { - msg_t msg; - - chSysLock(); - msg = chSemWaitTimeoutS(sp, time); - chSysUnlock(); - - return msg; -} - -/** - * @brief Performs a wait operation on a semaphore with timeout specification. - * - * @param[in] sp pointer to a @p semaphore_t structure - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return A message specifying how the invoking thread has been - * released from the semaphore. - * @retval MSG_OK if the thread has not stopped on the semaphore or the - * semaphore has been signaled. - * @retval MSG_RESET if the semaphore has been reset using @p chSemReset(). - * @retval MSG_TIMEOUT if the semaphore has not been signaled or reset within - * the specified timeout. - * - * @sclass - */ -msg_t chSemWaitTimeoutS(semaphore_t *sp, systime_t time) { - - chDbgCheckClassS(); - chDbgCheck(sp != NULL); - chDbgAssert(((sp->s_cnt >= (cnt_t)0) && queue_isempty(&sp->s_queue)) || - ((sp->s_cnt < (cnt_t)0) && queue_notempty(&sp->s_queue)), - "inconsistent semaphore"); - - if (--sp->s_cnt < (cnt_t)0) { - if (TIME_IMMEDIATE == time) { - sp->s_cnt++; - - return MSG_TIMEOUT; - } - currp->p_u.wtsemp = sp; - sem_insert(currp, &sp->s_queue); - - return chSchGoSleepTimeoutS(CH_STATE_WTSEM, time); - } - - return MSG_OK; -} - -/** - * @brief Performs a signal operation on a semaphore. - * - * @param[in] sp pointer to a @p semaphore_t structure - * - * @api - */ -void chSemSignal(semaphore_t *sp) { - - chDbgCheck(sp != NULL); - chDbgAssert(((sp->s_cnt >= (cnt_t)0) && queue_isempty(&sp->s_queue)) || - ((sp->s_cnt < (cnt_t)0) && queue_notempty(&sp->s_queue)), - "inconsistent semaphore"); - - chSysLock(); - if (++sp->s_cnt <= (cnt_t)0) { - chSchWakeupS(queue_fifo_remove(&sp->s_queue), MSG_OK); - } - chSysUnlock(); -} - -/** - * @brief Performs a signal operation on a semaphore. - * @post This function does not reschedule so a call to a rescheduling - * function must be performed before unlocking the kernel. Note that - * interrupt handlers always reschedule on exit so an explicit - * reschedule must not be performed in ISRs. - * - * @param[in] sp pointer to a @p semaphore_t structure - * - * @iclass - */ -void chSemSignalI(semaphore_t *sp) { - - chDbgCheckClassI(); - chDbgCheck(sp != NULL); - chDbgAssert(((sp->s_cnt >= (cnt_t)0) && queue_isempty(&sp->s_queue)) || - ((sp->s_cnt < (cnt_t)0) && queue_notempty(&sp->s_queue)), - "inconsistent semaphore"); - - if (++sp->s_cnt <= (cnt_t)0) { - /* Note, it is done this way in order to allow a tail call on - chSchReadyI().*/ - thread_t *tp = queue_fifo_remove(&sp->s_queue); - tp->p_u.rdymsg = MSG_OK; - (void) chSchReadyI(tp); - } -} - -/** - * @brief Adds the specified value to the semaphore counter. - * @post This function does not reschedule so a call to a rescheduling - * function must be performed before unlocking the kernel. Note that - * interrupt handlers always reschedule on exit so an explicit - * reschedule must not be performed in ISRs. - * - * @param[in] sp pointer to a @p semaphore_t structure - * @param[in] n value to be added to the semaphore counter. The value - * must be positive. - * - * @iclass - */ -void chSemAddCounterI(semaphore_t *sp, cnt_t n) { - - chDbgCheckClassI(); - chDbgCheck((sp != NULL) && (n > (cnt_t)0)); - chDbgAssert(((sp->s_cnt >= (cnt_t)0) && queue_isempty(&sp->s_queue)) || - ((sp->s_cnt < (cnt_t)0) && queue_notempty(&sp->s_queue)), - "inconsistent semaphore"); - - while (n > (cnt_t)0) { - if (++sp->s_cnt <= (cnt_t)0) { - chSchReadyI(queue_fifo_remove(&sp->s_queue))->p_u.rdymsg = MSG_OK; - } - n--; - } -} - -/** - * @brief Performs atomic signal and wait operations on two semaphores. - * - * @param[in] sps pointer to a @p semaphore_t structure to be signaled - * @param[in] spw pointer to a @p semaphore_t structure to wait on - * @return A message specifying how the invoking thread has been - * released from the semaphore. - * @retval MSG_OK if the thread has not stopped on the semaphore or the - * semaphore has been signaled. - * @retval MSG_RESET if the semaphore has been reset using @p chSemReset(). - * - * @api - */ -msg_t chSemSignalWait(semaphore_t *sps, semaphore_t *spw) { - msg_t msg; - - chDbgCheck((sps != NULL) && (spw != NULL)); - chDbgAssert(((sps->s_cnt >= (cnt_t)0) && queue_isempty(&sps->s_queue)) || - ((sps->s_cnt < (cnt_t)0) && queue_notempty(&sps->s_queue)), - "inconsistent semaphore"); - chDbgAssert(((spw->s_cnt >= (cnt_t)0) && queue_isempty(&spw->s_queue)) || - ((spw->s_cnt < (cnt_t)0) && queue_notempty(&spw->s_queue)), - "inconsistent semaphore"); - - chSysLock(); - if (++sps->s_cnt <= (cnt_t)0) { - chSchReadyI(queue_fifo_remove(&sps->s_queue))->p_u.rdymsg = MSG_OK; - } - if (--spw->s_cnt < (cnt_t)0) { - thread_t *ctp = currp; - sem_insert(ctp, &spw->s_queue); - ctp->p_u.wtsemp = spw; - chSchGoSleepS(CH_STATE_WTSEM); - msg = ctp->p_u.rdymsg; - } - else { - chSchRescheduleS(); - msg = MSG_OK; - } - chSysUnlock(); - - return msg; -} - -#endif /* CH_CFG_USE_SEMAPHORES == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/src/chstats.c b/firmware/ChibiOS_16/os/rt/src/chstats.c deleted file mode 100644 index 549203e746..0000000000 --- a/firmware/ChibiOS_16/os/rt/src/chstats.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chstats.c - * @brief Statistics module code. - * - * @addtogroup statistics - * @details Statistics services. - * @{ - */ - -#include "ch.h" - -#if (CH_DBG_STATISTICS == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Module local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -/** - * @brief Initializes the statistics module. - * - * @init - */ -void _stats_init(void) { - - ch.kernel_stats.n_irq = (ucnt_t)0; - ch.kernel_stats.n_ctxswc = (ucnt_t)0; - chTMObjectInit(&ch.kernel_stats.m_crit_thd); - chTMObjectInit(&ch.kernel_stats.m_crit_isr); -} - -/** - * @brief Increases the IRQ counter. - */ -void _stats_increase_irq(void) { - - port_lock_from_isr(); - ch.kernel_stats.n_irq++; - port_unlock_from_isr(); -} - -/** - * @brief Updates context switch related statistics. - * - * @param[in] ntp the thread to be switched in - * @param[in] otp the thread to be switched out - */ -void _stats_ctxswc(thread_t *ntp, thread_t *otp) { - - ch.kernel_stats.n_ctxswc++; - chTMChainMeasurementToX(&otp->p_stats, &ntp->p_stats); -} - -/** - * @brief Starts the measurement of a thread critical zone. - */ -void _stats_start_measure_crit_thd(void) { - - chTMStartMeasurementX(&ch.kernel_stats.m_crit_thd); -} - -/** - * @brief Stops the measurement of a thread critical zone. - */ -void _stats_stop_measure_crit_thd(void) { - - chTMStopMeasurementX(&ch.kernel_stats.m_crit_thd); -} - -/** - * @brief Starts the measurement of an ISR critical zone. - */ -void _stats_start_measure_crit_isr(void) { - - chTMStartMeasurementX(&ch.kernel_stats.m_crit_isr); -} - -/** - * @brief Stops the measurement of an ISR critical zone. - */ -void _stats_stop_measure_crit_isr(void) { - - chTMStopMeasurementX(&ch.kernel_stats.m_crit_isr); -} - -#endif /* CH_DBG_STATISTICS == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/src/chsys.c b/firmware/ChibiOS_16/os/rt/src/chsys.c deleted file mode 100644 index 494aacff35..0000000000 --- a/firmware/ChibiOS_16/os/rt/src/chsys.c +++ /dev/null @@ -1,426 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chsys.c - * @brief System related code. - * - * @addtogroup system - * @details System related APIs and services: - * - Initialization. - * - Locks. - * - Interrupt Handling. - * - Power Management. - * - Abnormal Termination. - * - Realtime counter. - * . - * @{ - */ - -#include "ch.h" - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -#if (CH_CFG_NO_IDLE_THREAD == FALSE) || defined(__DOXYGEN__) -/** - * @brief This function implements the idle thread infinite loop. - * @details The function puts the processor in the lowest power mode capable - * to serve interrupts.
- * The priority is internally set to the minimum system value so - * that this thread is executed only if there are no other ready - * threads in the system. - * - * @param[in] p the thread parameter, unused in this scenario - */ -static void _idle_thread(void *p) { - - (void)p; - - while (true) { - /*lint -save -e522 [2.2] Apparently no side effects because it contains - an asm instruction.*/ - port_wait_for_interrupt(); - /*lint -restore*/ - CH_CFG_IDLE_LOOP_HOOK(); - } -} -#endif /* CH_CFG_NO_IDLE_THREAD == FALSE */ - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -/** - * @brief ChibiOS/RT initialization. - * @details After executing this function the current instructions stream - * becomes the main thread. - * @pre Interrupts must disabled before invoking this function. - * @post The main thread is created with priority @p NORMALPRIO and - * interrupts are enabled. - * - * @special - */ -void chSysInit(void) { -#if CH_DBG_ENABLE_STACK_CHECK == TRUE - extern stkalign_t __main_thread_stack_base__; -#endif - - port_init(); - _scheduler_init(); - _vt_init(); -#if CH_CFG_USE_TM == TRUE - _tm_init(); -#endif -#if CH_CFG_USE_MEMCORE == TRUE - _core_init(); -#endif -#if CH_CFG_USE_HEAP == TRUE - _heap_init(); -#endif -#if CH_DBG_STATISTICS == TRUE - _stats_init(); -#endif -#if CH_DBG_ENABLE_TRACE == TRUE - _dbg_trace_init(); -#endif - -#if CH_CFG_NO_IDLE_THREAD == FALSE - /* Now this instructions flow becomes the main thread.*/ - setcurrp(_thread_init(&ch.mainthread, NORMALPRIO)); -#else - /* Now this instructions flow becomes the idle thread.*/ - setcurrp(_thread_init(&ch.mainthread, IDLEPRIO)); -#endif - - currp->p_state = CH_STATE_CURRENT; -#if CH_DBG_ENABLE_STACK_CHECK == TRUE - /* This is a special case because the main thread thread_t structure is not - adjacent to its stack area.*/ - currp->p_stklimit = &__main_thread_stack_base__; -#endif - -#if CH_DBG_STATISTICS == TRUE - /* Starting measurement for this thread.*/ - chTMStartMeasurementX(&currp->p_stats); -#endif - - chSysEnable(); - -#if CH_CFG_USE_REGISTRY == TRUE - /* Note, &ch_debug points to the string "main" if the registry is - active.*/ - chRegSetThreadName((const char *)&ch_debug); -#endif - -#if CH_CFG_NO_IDLE_THREAD == FALSE - { - /* This thread has the lowest priority in the system, its role is just to - serve interrupts in its context while keeping the lowest energy saving - mode compatible with the system status.*/ - thread_t *tp = chThdCreateStatic(ch.idle_thread_wa, - sizeof(ch.idle_thread_wa), - IDLEPRIO, - (tfunc_t)_idle_thread, - NULL); - chRegSetThreadNameX(tp, "idle"); - } -#endif -} - -/** - * @brief Halts the system. - * @details This function is invoked by the operating system when an - * unrecoverable error is detected, for example because a programming - * error in the application code that triggers an assertion while - * in debug mode. - * @note Can be invoked from any system state. - * - * @param[in] reason pointer to an error string - * - * @special - */ -void chSysHalt(const char *reason) { - - port_disable(); - -#if defined(CH_CFG_SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) - CH_CFG_SYSTEM_HALT_HOOK(reason); -#endif - - /* Pointing to the passed message.*/ - ch.dbg.panic_msg = reason; - - /* Harmless infinite loop.*/ - while (true) { - } -} - -/** - * @brief System integrity check. - * @details Performs an integrity check of the important ChibiOS/RT data - * structures. - * @note The appropriate action in case of failure is to halt the system - * before releasing the critical zone. - * @note If the system is corrupted then one possible outcome of this - * function is an exception caused by @p NULL or corrupted pointers - * in list elements. Exception vectors must be monitored as well. - * @note This function is not used internally, it is up to the - * application to define if and where to perform system - * checking. - * @note Performing all tests at once can be a slow operation and can - * degrade the system response time. It is suggested to execute - * one test at time and release the critical zone in between tests. - * - * @param[in] testmask Each bit in this mask is associated to a test to be - * performed. - * @return The test result. - * @retval false The test succeeded. - * @retval true Test failed. - * - * @iclass - */ -bool chSysIntegrityCheckI(unsigned testmask) { - cnt_t n; - - chDbgCheckClassI(); - - /* Ready List integrity check.*/ - if ((testmask & CH_INTEGRITY_RLIST) != 0U) { - thread_t *tp; - - /* Scanning the ready list forward.*/ - n = (cnt_t)0; - tp = ch.rlist.r_queue.p_next; - while (tp != (thread_t *)&ch.rlist.r_queue) { - n++; - tp = tp->p_next; - } - - /* Scanning the ready list backward.*/ - tp = ch.rlist.r_queue.p_prev; - while (tp != (thread_t *)&ch.rlist.r_queue) { - n--; - tp = tp->p_prev; - } - - /* The number of elements must match.*/ - if (n != (cnt_t)0) { - return true; - } - } - - /* Timers list integrity check.*/ - if ((testmask & CH_INTEGRITY_VTLIST) != 0U) { - virtual_timer_t * vtp; - - /* Scanning the timers list forward.*/ - n = (cnt_t)0; - vtp = ch.vtlist.vt_next; - while (vtp != (virtual_timer_t *)&ch.vtlist) { - n++; - vtp = vtp->vt_next; - } - - /* Scanning the timers list backward.*/ - vtp = ch.vtlist.vt_prev; - while (vtp != (virtual_timer_t *)&ch.vtlist) { - n--; - vtp = vtp->vt_prev; - } - - /* The number of elements must match.*/ - if (n != (cnt_t)0) { - return true; - } - } - -#if CH_CFG_USE_REGISTRY == TRUE - if ((testmask & CH_INTEGRITY_REGISTRY) != 0U) { - thread_t *tp; - - /* Scanning the ready list forward.*/ - n = (cnt_t)0; - tp = ch.rlist.r_newer; - while (tp != (thread_t *)&ch.rlist) { - n++; - tp = tp->p_newer; - } - - /* Scanning the ready list backward.*/ - tp = ch.rlist.r_older; - while (tp != (thread_t *)&ch.rlist) { - n--; - tp = tp->p_older; - } - - /* The number of elements must match.*/ - if (n != (cnt_t)0) { - return true; - } - } -#endif /* CH_CFG_USE_REGISTRY == TRUE */ - -#if defined(PORT_INTEGRITY_CHECK) - if ((testmask & CH_INTEGRITY_PORT) != 0U) { - PORT_INTEGRITY_CHECK(); - } -#endif - - return false; -} - -/** - * @brief Handles time ticks for round robin preemption and timer increments. - * @details Decrements the remaining time quantum of the running thread - * and preempts it when the quantum is used up. Increments system - * time and manages the timers. - * @note The frequency of the timer determines the system tick granularity - * and, together with the @p CH_CFG_TIME_QUANTUM macro, the round robin - * interval. - * - * @iclass - */ -void chSysTimerHandlerI(void) { - - chDbgCheckClassI(); - -#if CH_CFG_TIME_QUANTUM > 0 - /* Running thread has not used up quantum yet? */ - if (currp->p_preempt > (tslices_t)0) { - /* Decrement remaining quantum.*/ - currp->p_preempt--; - } -#endif -#if CH_DBG_THREADS_PROFILING == TRUE - currp->p_time++; -#endif - chVTDoTickI(); -#if defined(CH_CFG_SYSTEM_TICK_HOOK) - CH_CFG_SYSTEM_TICK_HOOK(); -#endif -} - -/** - * @brief Returns the execution status and enters a critical zone. - * @details This functions enters into a critical zone and can be called - * from any context. Because its flexibility it is less efficient - * than @p chSysLock() which is preferable when the calling context - * is known. - * @post The system is in a critical zone. - * - * @return The previous system status, the encoding of this - * status word is architecture-dependent and opaque. - * - * @xclass - */ -syssts_t chSysGetStatusAndLockX(void) { - - syssts_t sts = port_get_irq_status(); - if (port_irq_enabled(sts)) { - if (port_is_isr_context()) { - chSysLockFromISR(); - } - else { - chSysLock(); - } - } - return sts; -} - -/** - * @brief Restores the specified execution status and leaves a critical zone. - * @note A call to @p chSchRescheduleS() is automatically performed - * if exiting the critical zone and if not in ISR context. - * - * @param[in] sts the system status to be restored. - * - * @xclass - */ -void chSysRestoreStatusX(syssts_t sts) { - - if (port_irq_enabled(sts)) { - if (port_is_isr_context()) { - chSysUnlockFromISR(); - } - else { - chSchRescheduleS(); - chSysUnlock(); - } - } -} - -#if (PORT_SUPPORTS_RT == TRUE) || defined(__DOXYGEN__) -/** - * @brief Realtime window test. - * @details This function verifies if the current realtime counter value - * lies within the specified range or not. The test takes care - * of the realtime counter wrapping to zero on overflow. - * @note When start==end then the function returns always true because the - * whole time range is specified. - * @note This function is only available if the port layer supports the - * option @p PORT_SUPPORTS_RT. - * - * @param[in] cnt the counter value to be tested - * @param[in] start the start of the time window (inclusive) - * @param[in] end the end of the time window (non inclusive) - * @retval true current time within the specified time window. - * @retval false current time not within the specified time window. - * - * @xclass - */ -bool chSysIsCounterWithinX(rtcnt_t cnt, rtcnt_t start, rtcnt_t end) { - - return (bool)((cnt - start) < (end - start)); -} - -/** - * @brief Polled delay. - * @note The real delay is always few cycles in excess of the specified - * value. - * @note This function is only available if the port layer supports the - * option @p PORT_SUPPORTS_RT. - * - * @param[in] cycles number of cycles - * - * @xclass - */ -void chSysPolledDelayX(rtcnt_t cycles) { - rtcnt_t start = chSysGetRealtimeCounterX(); - rtcnt_t end = start + cycles; - - while (chSysIsCounterWithinX(chSysGetRealtimeCounterX(), start, end)) { - } -} -#endif /* PORT_SUPPORTS_RT == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/src/chthreads.c b/firmware/ChibiOS_16/os/rt/src/chthreads.c deleted file mode 100644 index 9e6349a8da..0000000000 --- a/firmware/ChibiOS_16/os/rt/src/chthreads.c +++ /dev/null @@ -1,685 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chthreads.c - * @brief Threads code. - * - * @addtogroup threads - * @details Threads related APIs and services. - *

Operation mode

- * A thread is an abstraction of an independent instructions flow. - * In ChibiOS/RT a thread is represented by a "C" function owning - * a processor context, state informations and a dedicated stack - * area. In this scenario static variables are shared among all - * threads while automatic variables are local to the thread.
- * Operations defined for threads: - * - Create, a thread is started on the specified thread - * function. This operation is available in multiple variants, - * both static and dynamic. - * - Exit, a thread terminates by returning from its top - * level function or invoking a specific API, the thread can - * return a value that can be retrieved by other threads. - * - Wait, a thread waits for the termination of another - * thread and retrieves its return value. - * - Resume, a thread created in suspended state is started. - * - Sleep, the execution of a thread is suspended for the - * specified amount of time or the specified future absolute time - * is reached. - * - SetPriority, a thread changes its own priority level. - * - Yield, a thread voluntarily renounces to its time slot. - * . - * The threads subsystem is implicitly included in kernel however - * some of its part may be excluded by disabling them in @p chconf.h, - * see the @p CH_CFG_USE_WAITEXIT and @p CH_CFG_USE_DYNAMIC configuration - * options. - * @{ - */ - -#include "ch.h" - -/*===========================================================================*/ -/* Module local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -/** - * @brief Initializes a thread structure. - * @note This is an internal functions, do not use it in application code. - * - * @param[in] tp pointer to the thread - * @param[in] prio the priority level for the new thread - * @return The same thread pointer passed as parameter. - * - * @notapi - */ -thread_t *_thread_init(thread_t *tp, tprio_t prio) { - - tp->p_prio = prio; - tp->p_state = CH_STATE_WTSTART; - tp->p_flags = CH_FLAG_MODE_STATIC; -#if CH_CFG_TIME_QUANTUM > 0 - tp->p_preempt = (tslices_t)CH_CFG_TIME_QUANTUM; -#endif -#if CH_CFG_USE_MUTEXES == TRUE - tp->p_realprio = prio; - tp->p_mtxlist = NULL; -#endif -#if CH_CFG_USE_EVENTS == TRUE - tp->p_epending = (eventmask_t)0; -#endif -#if CH_DBG_THREADS_PROFILING == TRUE - tp->p_time = (systime_t)0; -#endif -#if CH_CFG_USE_DYNAMIC == TRUE - tp->p_refs = (trefs_t)1; -#endif -#if CH_CFG_USE_REGISTRY == TRUE - tp->p_name = NULL; - REG_INSERT(tp); -#endif -#if CH_CFG_USE_WAITEXIT == TRUE - list_init(&tp->p_waiting); -#endif -#if CH_CFG_USE_MESSAGES == TRUE - queue_init(&tp->p_msgqueue); -#endif -#if CH_DBG_ENABLE_STACK_CHECK == TRUE - tp->p_stklimit = (stkalign_t *)(tp + 1); -#endif -#if CH_DBG_STATISTICS == TRUE - chTMObjectInit(&tp->p_stats); -#endif -#if defined(CH_CFG_THREAD_INIT_HOOK) - CH_CFG_THREAD_INIT_HOOK(tp); -#endif - return tp; -} - -#if (CH_DBG_FILL_THREADS == TRUE) || defined(__DOXYGEN__) -/** - * @brief Memory fill utility. - * - * @param[in] startp first address to fill - * @param[in] endp last address to fill +1 - * @param[in] v filler value - * - * @notapi - */ -void _thread_memfill(uint8_t *startp, uint8_t *endp, uint8_t v) { - - while (startp < endp) { - *startp++ = v; - } -} -#endif /* CH_DBG_FILL_THREADS */ - -/** - * @brief Creates a new thread into a static memory area. - * @details The new thread is initialized but not inserted in the ready list, - * the initial state is @p CH_STATE_WTSTART. - * @post The initialized thread can be subsequently started by invoking - * @p chThdStart(), @p chThdStartI() or @p chSchWakeupS() - * depending on the execution context. - * @note A thread can terminate by calling @p chThdExit() or by simply - * returning from its main function. - * @note Threads created using this function do not obey to the - * @p CH_DBG_FILL_THREADS debug option because it would keep - * the kernel locked for too much time. - * - * @param[out] wsp pointer to a working area dedicated to the thread stack - * @param[in] size size of the working area - * @param[in] prio the priority level for the new thread - * @param[in] pf the thread function - * @param[in] arg an argument passed to the thread function. It can be - * @p NULL. - * @return The pointer to the @p thread_t structure allocated for - * the thread into the working space area. - * - * @iclass - */ -thread_t *chThdCreateI(void *wsp, size_t size, - tprio_t prio, tfunc_t pf, void *arg) { - /* The thread structure is laid out in the lower part of the thread - workspace.*/ - thread_t *tp = wsp; - - chDbgCheckClassI(); - chDbgCheck((wsp != NULL) && (size >= THD_WORKING_AREA_SIZE(0)) && - (prio <= HIGHPRIO) && (pf != NULL)); - - PORT_SETUP_CONTEXT(tp, wsp, size, pf, arg); - - return _thread_init(tp, prio); -} - -/** - * @brief Creates a new thread into a static memory area. - * @note A thread can terminate by calling @p chThdExit() or by simply - * returning from its main function. - * - * @param[out] wsp pointer to a working area dedicated to the thread stack - * @param[in] size size of the working area - * @param[in] prio the priority level for the new thread - * @param[in] pf the thread function - * @param[in] arg an argument passed to the thread function. It can be - * @p NULL. - * @return The pointer to the @p thread_t structure allocated for - * the thread into the working space area. - * - * @api - */ -thread_t *chThdCreateStatic(void *wsp, size_t size, - tprio_t prio, tfunc_t pf, void *arg) { - thread_t *tp; - -#if CH_DBG_FILL_THREADS == TRUE - _thread_memfill((uint8_t *)wsp, - (uint8_t *)wsp + sizeof(thread_t), - CH_DBG_THREAD_FILL_VALUE); - _thread_memfill((uint8_t *)wsp + sizeof(thread_t), - (uint8_t *)wsp + size, - CH_DBG_STACK_FILL_VALUE); -#endif - - chSysLock(); - tp = chThdCreateI(wsp, size, prio, pf, arg); - chSchWakeupS(tp, MSG_OK); - chSysUnlock(); - - return tp; -} - -/** - * @brief Resumes a thread created with @p chThdCreateI(). - * - * @param[in] tp pointer to the thread - * @return The pointer to the @p thread_t structure allocated for - * the thread into the working space area. - * - * @api - */ -thread_t *chThdStart(thread_t *tp) { - - chSysLock(); - tp = chThdStartI(tp); - chSysUnlock(); - - return tp; -} - -/** - * @brief Changes the running thread priority level then reschedules if - * necessary. - * @note The function returns the real thread priority regardless of the - * current priority that could be higher than the real priority - * because the priority inheritance mechanism. - * - * @param[in] newprio the new priority level of the running thread - * @return The old priority level. - * - * @api - */ -tprio_t chThdSetPriority(tprio_t newprio) { - tprio_t oldprio; - - chDbgCheck(newprio <= HIGHPRIO); - - chSysLock(); -#if CH_CFG_USE_MUTEXES == TRUE - oldprio = currp->p_realprio; - if ((currp->p_prio == currp->p_realprio) || (newprio > currp->p_prio)) { - currp->p_prio = newprio; - } - currp->p_realprio = newprio; -#else - oldprio = currp->p_prio; - currp->p_prio = newprio; -#endif - chSchRescheduleS(); - chSysUnlock(); - - return oldprio; -} - -/** - * @brief Requests a thread termination. - * @pre The target thread must be written to invoke periodically - * @p chThdShouldTerminate() and terminate cleanly if it returns - * @p true. - * @post The specified thread will terminate after detecting the termination - * condition. - * - * @param[in] tp pointer to the thread - * - * @api - */ -void chThdTerminate(thread_t *tp) { - - chSysLock(); - tp->p_flags |= CH_FLAG_TERMINATE; - chSysUnlock(); -} - -/** - * @brief Suspends the invoking thread for the specified time. - * - * @param[in] time the delay in system ticks, the special values are - * handled as follow: - * - @a TIME_INFINITE the thread enters an infinite sleep - * state. - * - @a TIME_IMMEDIATE this value is not allowed. - * . - * - * @api - */ -void chThdSleep(systime_t time) { - - chSysLock(); - chThdSleepS(time); - chSysUnlock(); -} - -/** - * @brief Suspends the invoking thread until the system time arrives to the - * specified value. - * @note The function has no concept of "past", all specifiable times - * are in the future, this means that if you call this function - * exceeding your calculated intervals then the function will - * return in a far future time, not immediately. - * @see chThdSleepUntilWindowed() - * - * @param[in] time absolute system time - * - * @api - */ -void chThdSleepUntil(systime_t time) { - - chSysLock(); - time -= chVTGetSystemTimeX(); - if (time > (systime_t)0) { - chThdSleepS(time); - } - chSysUnlock(); -} - -/** - * @brief Suspends the invoking thread until the system time arrives to the - * specified value. - * @note The system time is assumed to be between @p prev and @p time - * else the call is assumed to have been called outside the - * allowed time interval, in this case no sleep is performed. - * @see chThdSleepUntil() - * - * @param[in] prev absolute system time of the previous deadline - * @param[in] next absolute system time of the next deadline - * @return the @p next parameter - * - * @api - */ -systime_t chThdSleepUntilWindowed(systime_t prev, systime_t next) { - systime_t time; - - chSysLock(); - time = chVTGetSystemTimeX(); - if (chVTIsTimeWithinX(time, prev, next)) { - chThdSleepS(next - time); - } - chSysUnlock(); - - return next; -} - -/** - * @brief Yields the time slot. - * @details Yields the CPU control to the next thread in the ready list with - * equal priority, if any. - * - * @api - */ -void chThdYield(void) { - - chSysLock(); - chSchDoYieldS(); - chSysUnlock(); -} - -/** - * @brief Terminates the current thread. - * @details The thread goes in the @p CH_STATE_FINAL state holding the - * specified exit status code, other threads can retrieve the - * exit status code by invoking the function @p chThdWait(). - * @post Eventual code after this function will never be executed, - * this function never returns. The compiler has no way to - * know this so do not assume that the compiler would remove - * the dead code. - * - * @param[in] msg thread exit code - * - * @api - */ -void chThdExit(msg_t msg) { - - chSysLock(); - chThdExitS(msg); - /* The thread never returns here.*/ -} - -/** - * @brief Terminates the current thread. - * @details The thread goes in the @p CH_STATE_FINAL state holding the - * specified exit status code, other threads can retrieve the - * exit status code by invoking the function @p chThdWait(). - * @post Eventual code after this function will never be executed, - * this function never returns. The compiler has no way to - * know this so do not assume that the compiler would remove - * the dead code. - * - * @param[in] msg thread exit code - * - * @sclass - */ -void chThdExitS(msg_t msg) { - thread_t *tp = currp; - - tp->p_u.exitcode = msg; -#if defined(CH_CFG_THREAD_EXIT_HOOK) - CH_CFG_THREAD_EXIT_HOOK(tp); -#endif -#if CH_CFG_USE_WAITEXIT == TRUE - while (list_notempty(&tp->p_waiting)) { - (void) chSchReadyI(list_remove(&tp->p_waiting)); - } -#endif -#if CH_CFG_USE_REGISTRY == TRUE - /* Static threads are immediately removed from the registry because - there is no memory to recover.*/ - if ((tp->p_flags & CH_FLAG_MODE_MASK) == CH_FLAG_MODE_STATIC) { - REG_REMOVE(tp); - } -#endif - chSchGoSleepS(CH_STATE_FINAL); - - /* The thread never returns here.*/ - chDbgAssert(false, "zombies apocalypse"); -} - -#if (CH_CFG_USE_WAITEXIT == TRUE) || defined(__DOXYGEN__) -/** - * @brief Blocks the execution of the invoking thread until the specified - * thread terminates then the exit code is returned. - * @details This function waits for the specified thread to terminate then - * decrements its reference counter, if the counter reaches zero then - * the thread working area is returned to the proper allocator.
- * The memory used by the exited thread is handled in different ways - * depending on the API that spawned the thread: - * - If the thread was spawned by @p chThdCreateStatic() or by - * @p chThdCreateI() then nothing happens and the thread working - * area is not released or modified in any way. This is the - * default, totally static, behavior. - * - If the thread was spawned by @p chThdCreateFromHeap() then - * the working area is returned to the system heap. - * - If the thread was spawned by @p chThdCreateFromMemoryPool() - * then the working area is returned to the owning memory pool. - * . - * @pre The configuration option @p CH_CFG_USE_WAITEXIT must be enabled in - * order to use this function. - * @post Enabling @p chThdWait() requires 2-4 (depending on the - * architecture) extra bytes in the @p thread_t structure. - * @post After invoking @p chThdWait() the thread pointer becomes invalid - * and must not be used as parameter for further system calls. - * @note If @p CH_CFG_USE_DYNAMIC is not specified this function just waits for - * the thread termination, no memory allocators are involved. - * - * @param[in] tp pointer to the thread - * @return The exit code from the terminated thread. - * - * @api - */ -msg_t chThdWait(thread_t *tp) { - msg_t msg; - - chDbgCheck(tp != NULL); - - chSysLock(); - chDbgAssert(tp != currp, "waiting self"); -#if CH_CFG_USE_DYNAMIC == TRUE - chDbgAssert(tp->p_refs > (trefs_t)0, "not referenced"); -#endif - if (tp->p_state != CH_STATE_FINAL) { - list_insert(currp, &tp->p_waiting); - chSchGoSleepS(CH_STATE_WTEXIT); - } - msg = tp->p_u.exitcode; - chSysUnlock(); - -#if CH_CFG_USE_DYNAMIC == TRUE - /* Releasing a lock if it is a dynamic thread.*/ - chThdRelease(tp); -#endif - - return msg; -} -#endif /* CH_CFG_USE_WAITEXIT */ - -/** - * @brief Sends the current thread sleeping and sets a reference variable. - * @note This function must reschedule, it can only be called from thread - * context. - * - * @param[in] trp a pointer to a thread reference object - * @return The wake up message. - * - * @sclass - */ -msg_t chThdSuspendS(thread_reference_t *trp) { - thread_t *tp = chThdGetSelfX(); - - chDbgAssert(*trp == NULL, "not NULL"); - - *trp = tp; - tp->p_u.wttrp = trp; - chSchGoSleepS(CH_STATE_SUSPENDED); - - return chThdGetSelfX()->p_u.rdymsg; -} - -/** - * @brief Sends the current thread sleeping and sets a reference variable. - * @note This function must reschedule, it can only be called from thread - * context. - * - * @param[in] trp a pointer to a thread reference object - * @param[in] timeout the timeout in system ticks, the special values are - * handled as follow: - * - @a TIME_INFINITE the thread enters an infinite sleep - * state. - * - @a TIME_IMMEDIATE the thread is not enqueued and - * the function returns @p MSG_TIMEOUT as if a timeout - * occurred. - * . - * @return The wake up message. - * @retval MSG_TIMEOUT if the operation timed out. - * - * @sclass - */ -msg_t chThdSuspendTimeoutS(thread_reference_t *trp, systime_t timeout) { - thread_t *tp = chThdGetSelfX(); - - chDbgAssert(*trp == NULL, "not NULL"); - - if (TIME_IMMEDIATE == timeout) { - return MSG_TIMEOUT; - } - - *trp = tp; - tp->p_u.wttrp = trp; - - return chSchGoSleepTimeoutS(CH_STATE_SUSPENDED, timeout); -} - -/** - * @brief Wakes up a thread waiting on a thread reference object. - * @note This function must not reschedule because it can be called from - * ISR context. - * - * @param[in] trp a pointer to a thread reference object - * @param[in] msg the message code - * - * @iclass - */ -void chThdResumeI(thread_reference_t *trp, msg_t msg) { - - if (*trp != NULL) { - thread_t *tp = *trp; - - chDbgAssert(tp->p_state == CH_STATE_SUSPENDED, - "not THD_STATE_SUSPENDED"); - - *trp = NULL; - tp->p_u.rdymsg = msg; - (void) chSchReadyI(tp); - } -} - -/** - * @brief Wakes up a thread waiting on a thread reference object. - * @note This function must reschedule, it can only be called from thread - * context. - * - * @param[in] trp a pointer to a thread reference object - * @param[in] msg the message code - * - * @iclass - */ -void chThdResumeS(thread_reference_t *trp, msg_t msg) { - - if (*trp != NULL) { - thread_t *tp = *trp; - - chDbgAssert(tp->p_state == CH_STATE_SUSPENDED, - "not THD_STATE_SUSPENDED"); - - *trp = NULL; - chSchWakeupS(tp, msg); - } -} - -/** - * @brief Wakes up a thread waiting on a thread reference object. - * @note This function must reschedule, it can only be called from thread - * context. - * - * @param[in] trp a pointer to a thread reference object - * @param[in] msg the message code - * - * @api - */ -void chThdResume(thread_reference_t *trp, msg_t msg) { - - chSysLock(); - chThdResumeS(trp, msg); - chSysUnlock(); -} - -/** - * @brief Enqueues the caller thread on a threads queue object. - * @details The caller thread is enqueued and put to sleep until it is - * dequeued or the specified timeouts expires. - * - * @param[in] tqp pointer to the threads queue object - * @param[in] timeout the timeout in system ticks, the special values are - * handled as follow: - * - @a TIME_INFINITE the thread enters an infinite sleep - * state. - * - @a TIME_IMMEDIATE the thread is not enqueued and - * the function returns @p MSG_TIMEOUT as if a timeout - * occurred. - * . - * @return The message from @p osalQueueWakeupOneI() or - * @p osalQueueWakeupAllI() functions. - * @retval MSG_TIMEOUT if the thread has not been dequeued within the - * specified timeout or if the function has been - * invoked with @p TIME_IMMEDIATE as timeout - * specification. - * - * @sclass - */ -msg_t chThdEnqueueTimeoutS(threads_queue_t *tqp, systime_t timeout) { - - if (TIME_IMMEDIATE == timeout) { - return MSG_TIMEOUT; - } - - queue_insert(currp, tqp); - - return chSchGoSleepTimeoutS(CH_STATE_QUEUED, timeout); -} - -/** - * @brief Dequeues and wakes up one thread from the threads queue object, - * if any. - * - * @param[in] tqp pointer to the threads queue object - * @param[in] msg the message code - * - * @iclass - */ -void chThdDequeueNextI(threads_queue_t *tqp, msg_t msg) { - - if (queue_notempty(tqp)) { - chThdDoDequeueNextI(tqp, msg); - } -} - -/** - * @brief Dequeues and wakes up all threads from the threads queue object. - * - * @param[in] tqp pointer to the threads queue object - * @param[in] msg the message code - * - * @iclass - */ -void chThdDequeueAllI(threads_queue_t *tqp, msg_t msg) { - - while (queue_notempty(tqp)) { - chThdDoDequeueNextI(tqp, msg); - } -} - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/src/chtm.c b/firmware/ChibiOS_16/os/rt/src/chtm.c deleted file mode 100644 index 7cafa703ab..0000000000 --- a/firmware/ChibiOS_16/os/rt/src/chtm.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chtm.c - * @brief Time Measurement module code. - * - * @addtogroup time_measurement - * @details Time Measurement APIs and services. - * @{ - */ - -#include "ch.h" - -#if (CH_CFG_USE_TM == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Module local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -static inline void tm_stop(time_measurement_t *tmp, - rtcnt_t now, - rtcnt_t offset) { - - tmp->n++; - tmp->last = (now - tmp->last) - offset; - tmp->cumulative += (rttime_t)tmp->last; - if (tmp->last > tmp->worst) { - tmp->worst = tmp->last; - } - if (tmp->last < tmp->best) { - tmp->best = tmp->last; - } -} - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -/** - * @brief Initializes the time measurement unit. - * - * @init - */ -void _tm_init(void) { - time_measurement_t tm; - - /* Time Measurement subsystem calibration, it does a null measurement - and calculates the call overhead which is subtracted to real - measurements.*/ - ch.tm.offset = (rtcnt_t)0; - chTMObjectInit(&tm); - chTMStartMeasurementX(&tm); - chTMStopMeasurementX(&tm); - ch.tm.offset = tm.last; -} - -/** - * @brief Initializes a @p TimeMeasurement object. - * - * @param[out] tmp pointer to a @p TimeMeasurement structure - * - * @init - */ -void chTMObjectInit(time_measurement_t *tmp) { - - tmp->best = (rtcnt_t)-1; - tmp->worst = (rtcnt_t)0; - tmp->last = (rtcnt_t)0; - tmp->n = (ucnt_t)0; - tmp->cumulative = (rttime_t)0; -} - -/** - * @brief Starts a measurement. - * @pre The @p time_measurement_t structure must be initialized. - * - * @param[in,out] tmp pointer to a @p TimeMeasurement structure - * - * @xclass - */ -NOINLINE void chTMStartMeasurementX(time_measurement_t *tmp) { - - tmp->last = chSysGetRealtimeCounterX(); -} - -/** - * @brief Stops a measurement. - * @pre The @p time_measurement_t structure must be initialized. - * - * @param[in,out] tmp pointer to a @p time_measurement_t structure - * - * @xclass - */ -NOINLINE void chTMStopMeasurementX(time_measurement_t *tmp) { - - tm_stop(tmp, chSysGetRealtimeCounterX(), ch.tm.offset); -} - -/** - * @brief Stops a measurement and chains to the next one using the same time - * stamp. - * - * @param[in,out] tmp1 pointer to the @p time_measurement_t structure to be - * stopped - * @param[in,out] tmp2 pointer to the @p time_measurement_t structure to be - * started - * - * - * @xclass - */ -NOINLINE void chTMChainMeasurementToX(time_measurement_t *tmp1, - time_measurement_t *tmp2) { - - /* Starts new measurement.*/ - tmp2->last = chSysGetRealtimeCounterX(); - - /* Stops previous measurement using the same time stamp.*/ - tm_stop(tmp1, tmp2->last, (rtcnt_t)0); -} - -#endif /* CH_CFG_USE_TM == TRUE */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/src/chvt.c b/firmware/ChibiOS_16/os/rt/src/chvt.c deleted file mode 100644 index 2edc4f4f1c..0000000000 --- a/firmware/ChibiOS_16/os/rt/src/chvt.c +++ /dev/null @@ -1,270 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chvt.c - * @brief Time and Virtual Timers module code. - * - * @addtogroup time - * @details Time and Virtual Timers related APIs and services. - * @{ - */ - -#include "ch.h" - -/*===========================================================================*/ -/* Module local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -/** - * @brief Virtual Timers initialization. - * @note Internal use only. - * - * @notapi - */ -void _vt_init(void) { - - ch.vtlist.vt_next = (virtual_timer_t *)&ch.vtlist; - ch.vtlist.vt_prev = (virtual_timer_t *)&ch.vtlist; - ch.vtlist.vt_delta = (systime_t)-1; -#if CH_CFG_ST_TIMEDELTA == 0 - ch.vtlist.vt_systime = (systime_t)0; -#else /* CH_CFG_ST_TIMEDELTA > 0 */ - ch.vtlist.vt_lasttime = (systime_t)0; -#endif /* CH_CFG_ST_TIMEDELTA > 0 */ -} - -/** - * @brief Enables a virtual timer. - * @details The timer is enabled and programmed to trigger after the delay - * specified as parameter. - * @pre The timer must not be already armed before calling this function. - * @note The callback function is invoked from interrupt context. - * - * @param[out] vtp the @p virtual_timer_t structure pointer - * @param[in] delay the number of ticks before the operation timeouts, the - * special values are handled as follow: - * - @a TIME_INFINITE is allowed but interpreted as a - * normal time specification. - * - @a TIME_IMMEDIATE this value is not allowed. - * . - * @param[in] vtfunc the timer callback function. After invoking the - * callback the timer is disabled and the structure can - * be disposed or reused. - * @param[in] par a parameter that will be passed to the callback - * function - * - * @iclass - */ -void chVTDoSetI(virtual_timer_t *vtp, systime_t delay, - vtfunc_t vtfunc, void *par) { - virtual_timer_t *p; - systime_t delta; - - chDbgCheckClassI(); - chDbgCheck((vtp != NULL) && (vtfunc != NULL) && (delay != TIME_IMMEDIATE)); - - vtp->vt_par = par; - vtp->vt_func = vtfunc; - -#if CH_CFG_ST_TIMEDELTA > 0 - { - systime_t now = chVTGetSystemTimeX(); - - /* If the requested delay is lower than the minimum safe delta then it - is raised to the minimum safe value.*/ - if (delay < (systime_t)CH_CFG_ST_TIMEDELTA) { - delay = (systime_t)CH_CFG_ST_TIMEDELTA; - } - - /* Special case where the timers list is empty.*/ - if (&ch.vtlist == (virtual_timers_list_t *)ch.vtlist.vt_next) { - - /* The delta list is empty, the current time becomes the new - delta list base time, the timer is inserted.*/ - ch.vtlist.vt_lasttime = now; - ch.vtlist.vt_next = vtp; - ch.vtlist.vt_prev = vtp; - vtp->vt_next = (virtual_timer_t *)&ch.vtlist; - vtp->vt_prev = (virtual_timer_t *)&ch.vtlist; - vtp->vt_delta = delay; - - /* Being the first element in the list the alarm timer is started.*/ - port_timer_start_alarm(ch.vtlist.vt_lasttime + delay); - - return; - } - - /* Pointer to the first element in the delta list, which is non-empty.*/ - p = ch.vtlist.vt_next; - - /* Delay as delta from 'lasttime'. Note, it can overflow and the value - becomes lower than 'now'.*/ - delta = now - ch.vtlist.vt_lasttime + delay; - - if (delta < now - ch.vtlist.vt_lasttime) { - /* Scenario where a very large delay excedeed the numeric range, it - requires a special handling. We need to skip the first element and - adjust the delta to wrap back in the previous numeric range.*/ - delta -= p->vt_delta; - p = p->vt_next; - } - else if (delta < p->vt_delta) { - /* A small delay that will become the first element in the delta list - and next deadline.*/ - port_timer_set_alarm(ch.vtlist.vt_lasttime + delta); - } - } -#else /* CH_CFG_ST_TIMEDELTA == 0 */ - /* Delta is initially equal to the specified delay.*/ - delta = delay; - - /* Pointer to the first element in the delta list.*/ - p = ch.vtlist.vt_next; -#endif /* CH_CFG_ST_TIMEDELTA == 0 */ - - /* The delta list is scanned in order to find the correct position for - this timer. */ - while (p->vt_delta < delta) { - delta -= p->vt_delta; - p = p->vt_next; - } - - /* The timer is inserted in the delta list.*/ - vtp->vt_next = p; - vtp->vt_prev = vtp->vt_next->vt_prev; - vtp->vt_prev->vt_next = vtp; - p->vt_prev = vtp; - vtp->vt_delta = delta - - /* Special case when the timer is in last position in the list, the - value in the header must be restored.*/; - p->vt_delta -= delta; - ch.vtlist.vt_delta = (systime_t)-1; -} - -/** - * @brief Disables a Virtual Timer. - * @pre The timer must be in armed state before calling this function. - * - * @param[in] vtp the @p virtual_timer_t structure pointer - * - * @iclass - */ -void chVTDoResetI(virtual_timer_t *vtp) { - - chDbgCheckClassI(); - chDbgCheck(vtp != NULL); - chDbgAssert(vtp->vt_func != NULL, "timer not set or already triggered"); - -#if CH_CFG_ST_TIMEDELTA == 0 - - /* The delta of the timer is added to the next timer.*/ - vtp->vt_next->vt_delta += vtp->vt_delta; - - /* Removing the element from the delta list.*/ - vtp->vt_prev->vt_next = vtp->vt_next; - vtp->vt_next->vt_prev = vtp->vt_prev; - vtp->vt_func = NULL; - - /* The above code changes the value in the header when the removed element - is the last of the list, restoring it.*/ - ch.vtlist.vt_delta = (systime_t)-1; -#else /* CH_CFG_ST_TIMEDELTA > 0 */ - systime_t nowdelta, delta; - - /* If the timer is not the first of the list then it is simply unlinked - else the operation is more complex.*/ - if (ch.vtlist.vt_next != vtp) { - /* Removing the element from the delta list.*/ - vtp->vt_prev->vt_next = vtp->vt_next; - vtp->vt_next->vt_prev = vtp->vt_prev; - vtp->vt_func = NULL; - - /* Adding delta to the next element, if it is not the last one.*/ - if (&ch.vtlist != (virtual_timers_list_t *)vtp->vt_next) - vtp->vt_next->vt_delta += vtp->vt_delta; - - return; - } - - /* Removing the first timer from the list.*/ - ch.vtlist.vt_next = vtp->vt_next; - ch.vtlist.vt_next->vt_prev = (virtual_timer_t *)&ch.vtlist; - vtp->vt_func = NULL; - - /* If the list become empty then the alarm timer is stopped and done.*/ - if (&ch.vtlist == (virtual_timers_list_t *)ch.vtlist.vt_next) { - port_timer_stop_alarm(); - - return; - } - - /* The delta of the removed timer is added to the new first timer.*/ - ch.vtlist.vt_next->vt_delta += vtp->vt_delta; - - /* If the new first timer has a delta of zero then the alarm is not - modified, the already programmed alarm will serve it.*/ -/* if (ch.vtlist.vt_next->vt_delta == 0) { - return; - }*/ - - /* Distance in ticks between the last alarm event and current time.*/ - nowdelta = chVTGetSystemTimeX() - ch.vtlist.vt_lasttime; - - /* If the current time surpassed the time of the next element in list - then the event interrupt is already pending, just return.*/ - if (nowdelta >= ch.vtlist.vt_next->vt_delta) { - return; - } - - /* Distance from the next scheduled event and now.*/ - delta = ch.vtlist.vt_next->vt_delta - nowdelta; - - /* Making sure to not schedule an event closer than CH_CFG_ST_TIMEDELTA - ticks from now.*/ - if (delta < (systime_t)CH_CFG_ST_TIMEDELTA) { - delta = (systime_t)CH_CFG_ST_TIMEDELTA; - } - - port_timer_set_alarm(ch.vtlist.vt_lasttime + nowdelta + delta); -#endif /* CH_CFG_ST_TIMEDELTA > 0 */ -} - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/templates/chconf.h b/firmware/ChibiOS_16/os/rt/templates/chconf.h deleted file mode 100644 index 8a2aea10e2..0000000000 --- a/firmware/ChibiOS_16/os/rt/templates/chconf.h +++ /dev/null @@ -1,498 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef _CHCONF_H_ -#define _CHCONF_H_ - -/*===========================================================================*/ -/** - * @name System timers settings - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. - */ -#define CH_CFG_ST_RESOLUTION 32 - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#define CH_CFG_ST_FREQUENCY 10000 - -/** - * @brief Time delta constant for the tick-less mode. - * @note If this value is zero then the system uses the classic - * periodic tick. This value represents the minimum number - * of ticks that is safe to specify in a timeout directive. - * The value one is not valid, timeouts are rounded up to - * this value. - */ -#define CH_CFG_ST_TIMEDELTA 2 - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel parameters and options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - * @note The round robin preemption is not supported in tickless mode and - * must be set to zero in that case. - */ -#define CH_CFG_TIME_QUANTUM 0 - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_CFG_USE_MEMCORE. - */ -#define CH_CFG_MEMCORE_SIZE 0 - -/** - * @brief Idle thread automatic spawn suppression. - * @details When this option is activated the function @p chSysInit() - * does not spawn the idle thread. The application @p main() - * function becomes the idle thread and must implement an - * infinite loop. - */ -#define CH_CFG_NO_IDLE_THREAD FALSE - -/** @} */ - -/*===========================================================================*/ -/** - * @name Performance options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#define CH_CFG_OPTIMIZE_SPEED TRUE - -/** @} */ - -/*===========================================================================*/ -/** - * @name Subsystem options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Time Measurement APIs. - * @details If enabled then the time measurement APIs are included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#define CH_CFG_USE_TM TRUE - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#define CH_CFG_USE_REGISTRY TRUE - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#define CH_CFG_USE_WAITEXIT TRUE - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#define CH_CFG_USE_SEMAPHORES TRUE - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#define CH_CFG_USE_MUTEXES TRUE - -/** - * @brief Enables recursive behavior on mutexes. - * @note Recursive mutexes are heavier and have an increased - * memory footprint. - * - * @note The default is @p FALSE. - */ -#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#define CH_CFG_USE_CONDVARS TRUE - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_CONDVARS. - */ -#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#define CH_CFG_USE_EVENTS TRUE - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_EVENTS. - */ -#define CH_CFG_USE_EVENTS_TIMEOUT TRUE - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#define CH_CFG_USE_MESSAGES TRUE - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_MESSAGES. - */ -#define CH_CFG_USE_MESSAGES_PRIORITY FALSE - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#define CH_CFG_USE_MAILBOXES TRUE - -/** - * @brief I/O Queues APIs. - * @details If enabled then the I/O queues APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#define CH_CFG_USE_QUEUES TRUE - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#define CH_CFG_USE_MEMCORE TRUE - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or - * @p CH_CFG_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#define CH_CFG_USE_HEAP TRUE - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#define CH_CFG_USE_MEMPOOLS TRUE - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_WAITEXIT. - * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. - */ -#define CH_CFG_USE_DYNAMIC TRUE - -/** @} */ - -/*===========================================================================*/ -/** - * @name Debug options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Debug option, kernel statistics. - * - * @note The default is @p FALSE. - */ -#define CH_DBG_STATISTICS FALSE - -/** - * @brief Debug option, system state check. - * @details If enabled the correct call protocol for system APIs is checked - * at runtime. - * - * @note The default is @p FALSE. - */ -#define CH_DBG_SYSTEM_STATE_CHECK FALSE - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#define CH_DBG_ENABLE_CHECKS FALSE - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#define CH_DBG_ENABLE_ASSERTS FALSE - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the context switch circular trace buffer is - * activated. - * - * @note The default is @p FALSE. - */ -#define CH_DBG_ENABLE_TRACE FALSE - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#define CH_DBG_ENABLE_STACK_CHECK FALSE - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#define CH_DBG_FILL_THREADS FALSE - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p thread_t structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p FALSE. - * @note This debug option is not currently compatible with the - * tickless mode. - */ -#define CH_DBG_THREADS_PROFILING FALSE - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel hooks - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Threads descriptor structure extension. - * @details User fields added to the end of the @p thread_t structure. - */ -#define CH_CFG_THREAD_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p chThdInit() API. - * - * @note It is invoked from within @p chThdInit() and implicitly from all - * the threads creation APIs. - */ -#define CH_CFG_THREAD_INIT_HOOK(tp) { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. - */ -#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ - /* Add threads finalization code here.*/ \ -} - -/** - * @brief Context switch hook. - * @details This hook is invoked just before switching between threads. - */ -#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ - /* Context switch code here.*/ \ -} - -/** - * @brief Idle thread enter hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to activate a power saving mode. - */ -#define CH_CFG_IDLE_ENTER_HOOK() { \ -} - -/** - * @brief Idle thread leave hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to deactivate a power saving mode. - */ -#define CH_CFG_IDLE_LEAVE_HOOK() { \ -} - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#define CH_CFG_IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} - -/** - * @brief System tick event hook. - * @details This hook is invoked in the system tick handler immediately - * after processing the virtual timers queue. - */ -#define CH_CFG_SYSTEM_TICK_HOOK() { \ - /* System tick event code here.*/ \ -} - -/** - * @brief System halt hook. - * @details This hook is invoked in case to a system halting error before - * the system is halted. - */ -#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ - /* System halt code here.*/ \ -} - -/** @} */ - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* _CHCONF_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/templates/chcore.c b/firmware/ChibiOS_16/os/rt/templates/chcore.c deleted file mode 100644 index 2b6af6e97c..0000000000 --- a/firmware/ChibiOS_16/os/rt/templates/chcore.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file templates/chcore.c - * @brief Port related template code. - * @details This file is a template of the system driver functions provided by - * a port. Some of the following functions may be implemented as - * macros in chcore.h if the implementer decides that there is an - * advantage in doing so, for example because performance concerns. - * - * @addtogroup core - * @details Non portable code templates. - * @{ - */ - -#include "ch.h" - -/*===========================================================================*/ -/* Module local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -/** - * @brief Port-related initialization code. - * @note This function is usually empty. - */ -void _port_init(void) { -} - -/** - * @brief Performs a context switch between two threads. - * @details This is the most critical code in any port, this function - * is responsible for the context switch between 2 threads. - * @note The implementation of this code affects directly the context - * switch performance so optimize here as much as you can. - * - * @param[in] ntp the thread to be switched in - * @param[in] otp the thread to be switched out - */ -void _port_switch(thread_t *ntp, thread_t *otp) { -} - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/templates/chcore.h b/firmware/ChibiOS_16/os/rt/templates/chcore.h deleted file mode 100644 index 10284d9611..0000000000 --- a/firmware/ChibiOS_16/os/rt/templates/chcore.h +++ /dev/null @@ -1,411 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file templates/chcore.h - * @brief Port related template macros and structures. - * @details This file is a template of the system driver macros provided by - * a port. - * - * @addtogroup core - * @{ - */ - -#ifndef _CHCORE_H_ -#define _CHCORE_H_ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @name Architecture and Compiler - * @{ - */ -/** - * @brief Macro defining an XXX architecture. - */ -#define PORT_ARCHITECTURE_XXX - -/** - * @brief Macro defining the specific XXX architecture. - */ -#define PORT_ARCHITECTURE_XXX_YYY - -/** - * @brief Name of the implemented architecture. - */ -#define PORT_ARCHITECTURE_NAME "XXX Architecture" - -/** - * @brief Compiler name and version. - */ -#if defined(__GNUC__) || defined(__DOXYGEN__) -#define PORT_COMPILER_NAME "GCC " __VERSION__ - -#else -#error "unsupported compiler" -#endif - -/** - * @brief This port supports a realtime counter. - */ -#define PORT_SUPPORTS_RT FALSE - -/** - * @brief Port-specific information string. - */ -#define PORT_INFO "no info" -/** @} */ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Stack size for the system idle thread. - * @details This size depends on the idle thread implementation, usually - * the idle thread should take no more space than those reserved - * by @p PORT_INT_REQUIRED_STACK. - */ -#if !defined(PORT_IDLE_THREAD_STACK_SIZE) || defined(__DOXYGEN__) -#define PORT_IDLE_THREAD_STACK_SIZE 32 -#endif - -/** - * @brief Per-thread stack overhead for interrupts servicing. - * @details This constant is used in the calculation of the correct working - * area size. - */ -#if !defined(PORT_INT_REQUIRED_STACK) || defined(__DOXYGEN__) -#define PORT_INT_REQUIRED_STACK 256 -#endif - -/** - * @brief Enables an alternative timer implementation. - * @details Usually the port uses a timer interface defined in the file - * @p chcore_timer.h, if this option is enabled then the file - * @p chcore_timer_alt.h is included instead. - */ -#if !defined(PORT_USE_ALT_TIMER) -#define PORT_USE_ALT_TIMER FALSE -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/* The following code is not processed when the file is included from an - asm module.*/ -#if !defined(_FROM_ASM_) - -/** - * @brief Type of stack and memory alignment enforcement. - * @note In this architecture the stack alignment is enforced to 64 bits. - */ -typedef uint64_t stkalign_t; - -/** - * @brief Interrupt saved context. - * @details This structure represents the stack frame saved during a - * preemption-capable interrupt handler. - * @note R2 and R13 are not saved because those are assumed to be immutable - * during the system life cycle. - */ -struct port_extctx { - }; - -/** - * @brief System saved context. - * @details This structure represents the inner stack frame during a context - * switching. - * @note R2 and R13 are not saved because those are assumed to be immutable - * during the system life cycle. - * @note LR is stored in the caller context so it is not present in this - * structure. - */ -struct port_intctx { -}; - -/** - * @brief Platform dependent part of the @p thread_t structure. - * @details This structure usually contains just the saved stack pointer - * defined as a pointer to a @p port_intctx structure. - */ -struct context { - struct port_intctx *sp; -}; - -#endif /* !defined(_FROM_ASM_) */ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @brief Platform dependent part of the @p chThdCreateI() API. - * @details This code usually setup the context switching frame represented - * by an @p port_intctx structure. - */ -#define PORT_SETUP_CONTEXT(tp, workspace, wsize, pf, arg) { \ -} - -/** - * @brief Computes the thread working area global size. - * @note There is no need to perform alignments in this macro. - */ -#define PORT_WA_SIZE(n) (sizeof(struct port_intctx) + \ - sizeof(struct port_extctx) + \ - ((size_t)(n)) + ((size_t)(PORT_INT_REQUIRED_STACK))) - -/** - * @brief Priority level verification macro. - */ -#define PORT_IRQ_IS_VALID_PRIORITY(n) false - -/** - * @brief Priority level verification macro. - */ -#define PORT_IRQ_IS_VALID_KERNEL_PRIORITY(n) false - -/** - * @brief IRQ prologue code. - * @details This macro must be inserted at the start of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_PROLOGUE() - -/** - * @brief IRQ epilogue code. - * @details This macro must be inserted at the end of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_EPILOGUE() - -/** - * @brief IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_IRQ_HANDLER(id) void id(void) - -/** - * @brief Fast IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_FAST_IRQ_HANDLER(id) void id(void) - -/** - * @brief Performs a context switch between two threads. - * @details This is the most critical code in any port, this function - * is responsible for the context switch between 2 threads. - * @note The implementation of this code affects directly the context - * switch performance so optimize here as much as you can. - * - * @param[in] ntp the thread to be switched in - * @param[in] otp the thread to be switched out - */ -#if !CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__) -#define port_switch(ntp, otp) _port_switch(ntp, otp) -#else -#define port_switch(ntp, otp) { \ - register struct port_intctx *sp asm ("%r1"); \ - if ((stkalign_t *)(sp - 1) < otp->p_stklimit) \ - chSysHalt("stack overflow"); \ - _port_switch(ntp, otp); \ -} -#endif - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/* The following code is not processed when the file is included from an - asm module.*/ -#if !defined(_FROM_ASM_) - -#ifdef __cplusplus -extern "C" { -#endif - void _port_init(void); - void _port_switch(thread_t *ntp, thread_t *otp); -#ifdef __cplusplus -} -#endif - -#endif /* !defined(_FROM_ASM_) */ - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -/* The following code is not processed when the file is included from an - asm module.*/ -#if !defined(_FROM_ASM_) - -/** - * @brief Returns a word encoding the current interrupts status. - * - * @return The interrupts status. - */ -static inline syssts_t port_get_irq_status(void) { - - return 0; -} - -/** - * @brief Checks the interrupt status. - * - * @param[in] sts the interrupt status word - * - * @return The interrupt status. - * @retval false the word specified a disabled interrupts status. - * @retval true the word specified an enabled interrupts status. - */ -static inline bool port_irq_enabled(syssts_t sts) { - - (void)sts; - - return false; -} - -/** - * @brief Determines the current execution context. - * - * @return The execution context. - * @retval false not running in ISR mode. - * @retval true running in ISR mode. - */ -static inline bool port_is_isr_context(void) { - - return false; -} - -/** - * @brief Kernel-lock action. - * @details Usually this function just disables interrupts but may perform more - * actions. - */ -static inline void port_lock(void) { - -} - -/** - * @brief Kernel-unlock action. - * @details Usually this function just enables interrupts but may perform more - * actions. - */ -static inline void port_unlock(void) { - -} - -/** - * @brief Kernel-lock action from an interrupt handler. - * @details This function is invoked before invoking I-class APIs from - * interrupt handlers. The implementation is architecture dependent, - * in its simplest form it is void. - */ -static inline void port_lock_from_isr(void) { - -} - -/** - * @brief Kernel-unlock action from an interrupt handler. - * @details This function is invoked after invoking I-class APIs from interrupt - * handlers. The implementation is architecture dependent, in its - * simplest form it is void. - */ -static inline void port_unlock_from_isr(void) { - -} - -/** - * @brief Disables all the interrupt sources. - * @note Of course non-maskable interrupt sources are not included. - */ -static inline void port_disable(void) { - -} - -/** - * @brief Disables the interrupt sources below kernel-level priority. - * @note Interrupt sources above kernel level remains enabled. - */ -static inline void port_suspend(void) { - -} - -/** - * @brief Enables all the interrupt sources. - */ -static inline void port_enable(void) { - -} - -/** - * @brief Enters an architecture-dependent IRQ-waiting mode. - * @details The function is meant to return when an interrupt becomes pending. - * The simplest implementation is an empty function or macro but this - * would not take advantage of architecture-specific power saving - * modes. - */ -static inline void port_wait_for_interrupt(void) { - -#if PPC_ENABLE_WFI_IDLE -#endif -} - -/** - * @brief Returns the current value of the realtime counter. - * - * @return The realtime counter value. - */ -static inline rtcnt_t port_rt_get_counter_value(void) { - - return 0; -} - -#endif /* !defined(_FROM_ASM_) */ - -/*===========================================================================*/ -/* Module late inclusions. */ -/*===========================================================================*/ - -/* The following code is not processed when the file is included from an - asm module.*/ -#if !defined(_FROM_ASM_) - -#if CH_CFG_ST_TIMEDELTA > 0 -#if !PORT_USE_ALT_TIMER -#include "chcore_timer.h" -#else /* PORT_USE_ALT_TIMER */ -#include "chcore_timer_alt.h" -#endif /* PORT_USE_ALT_TIMER */ -#endif /* CH_CFG_ST_TIMEDELTA > 0 */ - -#endif /* !defined(_FROM_ASM_) */ - -#endif /* _CHCORE_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/templates/chtypes.h b/firmware/ChibiOS_16/os/rt/templates/chtypes.h deleted file mode 100644 index d09b8f473e..0000000000 --- a/firmware/ChibiOS_16/os/rt/templates/chtypes.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file templates/chtypes.h - * @brief System types template. - * @details The types defined in this file may change depending on the target - * architecture. You may also try to optimize the size of the various - * types in order to privilege size or performance, be careful in - * doing so. - * - * @addtogroup types - * @{ - */ - -#ifndef _CHTYPES_H_ -#define _CHTYPES_H_ - -#include -#include -#include - -/** - * @name Common constants - */ -/** - * @brief Generic 'false' boolean constant. - */ -#if !defined(FALSE) || defined(__DOXYGEN__) -#define FALSE 0 -#endif - -/** - * @brief Generic 'true' boolean constant. - */ -#if !defined(TRUE) || defined(__DOXYGEN__) -#define TRUE (!FALSE) -#endif -/** @} */ - -/** - * @name Kernel types - * @{ - */ -typedef uint32_t rtcnt_t; /**< Realtime counter. */ -typedef uint64_t rttime_t; /**< Realtime accumulator. */ -typedef uint32_t syssts_t; /**< System status word. */ -typedef uint8_t tmode_t; /**< Thread flags. */ -typedef uint8_t tstate_t; /**< Thread state. */ -typedef uint8_t trefs_t; /**< Thread references counter. */ -typedef uint8_t tslices_t; /**< Thread time slices counter.*/ -typedef uint32_t tprio_t; /**< Thread priority. */ -typedef int32_t msg_t; /**< Inter-thread message. */ -typedef int32_t eventid_t; /**< Numeric event identifier. */ -typedef uint32_t eventmask_t; /**< Mask of event identifiers. */ -typedef uint32_t eventflags_t; /**< Mask of event flags. */ -typedef int32_t cnt_t; /**< Generic signed counter. */ -typedef uint32_t ucnt_t; /**< Generic unsigned counter. */ -/** @} */ - -/** - * @brief ROM constant modifier. - * @note It is set to use the "const" keyword in this port. - */ -#define ROMCONST const - -/** - * @brief Makes functions not inlineable. - * @note If the compiler does not support such attribute then the - * realtime counter precision could be degraded. - */ -#define NOINLINE __attribute__((noinline)) - -/** - * @brief Optimized thread function declaration macro. - */ -#define PORT_THD_FUNCTION(tname, arg) msg_t tname(void *arg) - -/** - * @brief Packed variable specifier. - */ -#define PACKED_VAR __attribute__((packed)) - -#endif /* _CHTYPES_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/templates/meta/module.c b/firmware/ChibiOS_16/os/rt/templates/meta/module.c deleted file mode 100644 index c7f28c9dfb..0000000000 --- a/firmware/ChibiOS_16/os/rt/templates/meta/module.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chXxx.c - * @brief XXX module code. - * - * @addtogroup XXX - * @{ - */ - -#include "ch.h" - -#if CH_CFG_USE_XXX || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Module local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -/** - * @brief XXX Module initialization. - * @note This function is implicitly invoked on system initialization, - * there is no need to explicitly initialize the module. - * - * @notapi - */ -void _xxx_init(void) { - -} - -/** - * @brief Initializes a @p xxx_t object. - * - * @param[out] xxxp pointer to the @p xxx_t object - * - * @init - */ -void chXxxObjectInit(xxx_t *xxxp) { - -} - -#endif /* CH_CFG_USE_XXX */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/rt/templates/meta/module.h b/firmware/ChibiOS_16/os/rt/templates/meta/module.h deleted file mode 100644 index 9e02aa8cce..0000000000 --- a/firmware/ChibiOS_16/os/rt/templates/meta/module.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. - - This file is part of ChibiOS. - - ChibiOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file chXxx.h - * @brief XXX Module macros and structures. - * - * @addtogroup XXX - * @{ - */ - -#ifndef _CHXXX_H_ -#define _CHXXX_H_ - -#include "ch.h" - -#if CH_CFG_USE_XXX || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void chXxxInit(void); - void chXxxObjectInit(xxx_t *xxxp); -#ifdef __cplusplus -} -#endif - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -#endif /* CH_CFG_USE_XXX */ - -#endif /* _CHXXX_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/various/cpp_wrappers/ch.cpp b/firmware/ChibiOS_16/os/various/cpp_wrappers/ch.cpp deleted file mode 100644 index 4f197434ac..0000000000 --- a/firmware/ChibiOS_16/os/various/cpp_wrappers/ch.cpp +++ /dev/null @@ -1,704 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/** - * @file ch.cpp - * @brief C++ wrapper code. - * - * @addtogroup cpp_library - * @{ - */ - -#include "ch.hpp" - -namespace chibios_rt { - - /*------------------------------------------------------------------------* - * chibios_rt::Timer * - *------------------------------------------------------------------------*/ - - void Timer::setI(systime_t time, vtfunc_t vtfunc, void *par) { - - chVTSetI(&timer_ref, time, vtfunc, par); - } - - void Timer::resetI() { - - if (chVTIsArmedI(&timer_ref)) - chVTDoResetI(&timer_ref); - } - - bool Timer::isArmedI(void) { - - return chVTIsArmedI(&timer_ref); - } - - /*------------------------------------------------------------------------* - * chibios_rt::ThreadStayPoint * - *------------------------------------------------------------------------*/ - - msg_t ThreadStayPoint::suspendS(void) { - - return chThdSuspendS(&thread_ref); - } - - msg_t ThreadStayPoint::suspendS(systime_t timeout) { - - return chThdSuspendTimeoutS(&thread_ref, timeout); - } - - void ThreadStayPoint::resumeI(msg_t msg) { - - chThdResumeI(&thread_ref, msg); - } - - void ThreadStayPoint::resumeS(msg_t msg) { - - chThdResumeS(&thread_ref, msg); - } - - /*------------------------------------------------------------------------* - * chibios_rt::ThreadReference * - *------------------------------------------------------------------------*/ - - void ThreadReference::stop(void) { - - chSysHalt("invoked unimplemented method stop()"); - } - - void ThreadReference::requestTerminate(void) { - - chDbgAssert(thread_ref != NULL, - "not referenced"); - - chThdTerminate(thread_ref); - } - -#if CH_CFG_USE_WAITEXIT - msg_t ThreadReference::wait(void) { - - chDbgAssert(thread_ref != NULL, - "not referenced"); - - msg_t msg = chThdWait(thread_ref); - thread_ref = NULL; - return msg; - } -#endif /* CH_CFG_USE_WAITEXIT */ - -#if CH_CFG_USE_MESSAGES - msg_t ThreadReference::sendMessage(msg_t msg) { - - chDbgAssert(thread_ref != NULL, - "not referenced"); - - return chMsgSend(thread_ref, msg); - } - - bool ThreadReference::isPendingMessage(void) { - - chDbgAssert(thread_ref != NULL, - "not referenced"); - - return chMsgIsPendingI(thread_ref); - } - - msg_t ThreadReference::getMessage(void) { - - chDbgAssert(thread_ref != NULL, - "not referenced"); - - return chMsgGet(thread_ref); - } - - void ThreadReference::releaseMessage(msg_t msg) { - - chDbgAssert(thread_ref != NULL, - "not referenced"); - - chMsgRelease(thread_ref, msg); - } -#endif /* CH_CFG_USE_MESSAGES */ - -#if CH_CFG_USE_EVENTS - void ThreadReference::signalEvents(eventmask_t mask) { - - chDbgAssert(thread_ref != NULL, - "not referenced"); - - chEvtSignal(thread_ref, mask); - } - - void ThreadReference::signalEventsI(eventmask_t mask) { - - chDbgAssert(thread_ref != NULL, - "not referenced"); - - chEvtSignalI(thread_ref, mask); - } -#endif /* CH_CFG_USE_EVENTS */ - -#if CH_CFG_USE_DYNAMIC -#endif /* CH_CFG_USE_DYNAMIC */ - - /*------------------------------------------------------------------------* - * chibios_rt::BaseThread * - *------------------------------------------------------------------------*/ - BaseThread::BaseThread() : ThreadReference(NULL) { - - } - - void BaseThread::main(void) { - - } - - ThreadReference BaseThread::start(tprio_t prio) { - - (void)prio; - - return *this; - } - - void _thd_start(void *arg) { - - ((BaseThread *)arg)->main(); - } - - void BaseThread::setName(const char *tname) { - - chRegSetThreadName(tname); - } - - tprio_t BaseThread::setPriority(tprio_t newprio) { - - return chThdSetPriority(newprio); - } - - void BaseThread::exit(msg_t msg) { - - chThdExit(msg); - } - - void BaseThread::exitS(msg_t msg) { - - chThdExitS(msg); - } - - bool BaseThread::shouldTerminate(void) { - - return chThdShouldTerminateX(); - } - - void BaseThread::sleep(systime_t interval){ - - chThdSleep(interval); - } - - void BaseThread::sleepUntil(systime_t time) { - - chThdSleepUntil(time); - } - - void BaseThread::yield(void) { - - chThdYield(); - } - -#if CH_CFG_USE_MESSAGES - ThreadReference BaseThread::waitMessage(void) { - - ThreadReference tr(chMsgWait()); - return tr; - } -#endif /* CH_CFG_USE_MESSAGES */ - -#if CH_CFG_USE_EVENTS - eventmask_t BaseThread::getAndClearEvents(eventmask_t mask) { - - return chEvtGetAndClearEvents(mask); - } - - eventmask_t BaseThread::addEvents(eventmask_t mask) { - - return chEvtAddEvents(mask); - } - - eventmask_t BaseThread::waitOneEvent(eventmask_t ewmask) { - - return chEvtWaitOne(ewmask); - } - - eventmask_t BaseThread::waitAnyEvent(eventmask_t ewmask) { - - return chEvtWaitAny(ewmask); - } - - eventmask_t BaseThread::waitAllEvents(eventmask_t ewmask) { - - return chEvtWaitAll(ewmask); - } - -#if CH_CFG_USE_EVENTS_TIMEOUT - eventmask_t BaseThread::waitOneEventTimeout(eventmask_t ewmask, - systime_t time) { - - return chEvtWaitOneTimeout(ewmask, time); - } - - eventmask_t BaseThread::waitAnyEventTimeout(eventmask_t ewmask, - systime_t time) { - - return chEvtWaitAnyTimeout(ewmask, time); - } - - eventmask_t BaseThread::waitAllEventsTimeout(eventmask_t ewmask, - systime_t time) { - - return chEvtWaitAllTimeout(ewmask, time); - } -#endif /* CH_CFG_USE_EVENTS_TIMEOUT */ - - void BaseThread::dispatchEvents(const evhandler_t handlers[], - eventmask_t mask) { - - chEvtDispatch(handlers, mask); - } -#endif /* CH_CFG_USE_EVENTS */ - -#if CH_CFG_USE_MUTEXES - void BaseThread::unlockMutex(Mutex *mp) { - - chMtxUnlock(&mp->mutex); - } - - void BaseThread::unlockMutexS(Mutex *mp) { - - chMtxUnlockS(&mp->mutex); - } - - void BaseThread::unlockAllMutexes(void) { - - chMtxUnlockAll(); - } -#endif /* CH_CFG_USE_MUTEXES */ - -#if CH_CFG_USE_SEMAPHORES - /*------------------------------------------------------------------------* - * chibios_rt::CounterSemaphore * - *------------------------------------------------------------------------*/ - CounterSemaphore::CounterSemaphore(cnt_t n) { - - chSemObjectInit(&sem, n); - } - - void CounterSemaphore::reset(cnt_t n) { - - chSemReset(&sem, n); - } - - void CounterSemaphore::resetI(cnt_t n) { - - chSemResetI(&sem, n); - } - - msg_t CounterSemaphore::wait(void) { - - return chSemWait(&sem); - } - - msg_t CounterSemaphore::waitS(void) { - - return chSemWaitS(&sem); - } - - msg_t CounterSemaphore::wait(systime_t time) { - - return chSemWaitTimeout(&sem, time); - } - - msg_t CounterSemaphore::waitS(systime_t time) { - - return chSemWaitTimeoutS(&sem, time); - } - - void CounterSemaphore::signal(void) { - - chSemSignal(&sem); - } - - void CounterSemaphore::signalI(void) { - - chSemSignalI(&sem); - } - - void CounterSemaphore::addCounterI(cnt_t n) { - - chSemAddCounterI(&sem, n); - } - - cnt_t CounterSemaphore::getCounterI(void) { - - return chSemGetCounterI(&sem); - } - - msg_t CounterSemaphore::signalWait(CounterSemaphore *ssem, - CounterSemaphore *wsem) { - - return chSemSignalWait(&ssem->sem, &wsem->sem); - } - - /*------------------------------------------------------------------------* - * chibios_rt::BinarySemaphore * - *------------------------------------------------------------------------*/ - BinarySemaphore::BinarySemaphore(bool taken) { - - chBSemObjectInit(&bsem, taken); - } - - msg_t BinarySemaphore::wait(void) { - - return chBSemWait(&bsem); - } - - msg_t BinarySemaphore::waitS(void) { - - return chBSemWaitS(&bsem); - } - - msg_t BinarySemaphore::wait(systime_t time) { - - return chBSemWaitTimeout(&bsem, time); - } - - msg_t BinarySemaphore::waitS(systime_t time) { - - return chBSemWaitTimeoutS(&bsem, time); - } - - void BinarySemaphore::reset(bool taken) { - - chBSemReset(&bsem, taken); - } - - void BinarySemaphore::resetI(bool taken) { - - chBSemResetI(&bsem, taken); - } - - void BinarySemaphore::signal(void) { - - chBSemSignal(&bsem); - } - - void BinarySemaphore::signalI(void) { - - chBSemSignalI(&bsem); - } - - bool BinarySemaphore::getStateI(void) { - - return (bool)chBSemGetStateI(&bsem); - } -#endif /* CH_CFG_USE_SEMAPHORES */ - -#if CH_CFG_USE_MUTEXES - /*------------------------------------------------------------------------* - * chibios_rt::Mutex * - *------------------------------------------------------------------------*/ - Mutex::Mutex(void) { - - chMtxObjectInit(&mutex); - } - - bool Mutex::tryLock(void) { - - return chMtxTryLock(&mutex); - } - - bool Mutex::tryLockS(void) { - - return chMtxTryLockS(&mutex); - } - - void Mutex::lock(void) { - - chMtxLock(&mutex); - } - - void Mutex::lockS(void) { - - chMtxLockS(&mutex); - } - - void Mutex::unlock(void) { - - chMtxUnlock(&mutex); - } - - void Mutex::unlockS(void) { - - chMtxUnlockS(&mutex); - } - -#if CH_CFG_USE_CONDVARS - /*------------------------------------------------------------------------* - * chibios_rt::CondVar * - *------------------------------------------------------------------------*/ - CondVar::CondVar(void) { - - chCondObjectInit(&condvar); - } - - void CondVar::signal(void) { - - chCondSignal(&condvar); - } - - void CondVar::signalI(void) { - - chCondSignalI(&condvar); - } - - void CondVar::broadcast(void) { - - chCondBroadcast(&condvar); - } - - void CondVar::broadcastI(void) { - - chCondBroadcastI(&condvar); - } - - msg_t CondVar::wait(void) { - - return chCondWait(&condvar); - } - - msg_t CondVar::waitS(void) { - - return chCondWaitS(&condvar); - } - -#if CH_CFG_USE_CONDVARS_TIMEOUT - msg_t CondVar::wait(systime_t time) { - - return chCondWaitTimeout(&condvar, time); - } -#endif /* CH_CFG_USE_CONDVARS_TIMEOUT */ -#endif /* CH_CFG_USE_CONDVARS */ -#endif /* CH_CFG_USE_MUTEXES */ - -#if CH_CFG_USE_EVENTS - /*------------------------------------------------------------------------* - * chibios_rt::EvtListener * - *------------------------------------------------------------------------*/ - eventflags_t EvtListener::getAndClearFlags(void) { - - return chEvtGetAndClearFlags(&ev_listener); - } - - eventflags_t EvtListener::getAndClearFlagsI(void) { - - return chEvtGetAndClearFlagsI(&ev_listener); - } - - /*------------------------------------------------------------------------* - * chibios_rt::EvtSource * - *------------------------------------------------------------------------*/ - EvtSource::EvtSource(void) { - - chEvtObjectInit(&ev_source); - } - - void EvtSource::registerOne(chibios_rt::EvtListener *elp, - eventid_t eid) { - - chEvtRegister(&ev_source, &elp->ev_listener, eid); - } - - void EvtSource::registerMask(chibios_rt::EvtListener *elp, - eventmask_t emask) { - - chEvtRegisterMask(&ev_source, &elp->ev_listener, emask); - } - - void EvtSource::unregister(chibios_rt::EvtListener *elp) { - - chEvtUnregister(&ev_source, &elp->ev_listener); - } - - void EvtSource::broadcastFlags(eventflags_t flags) { - - chEvtBroadcastFlags(&ev_source, flags); - } - - void EvtSource::broadcastFlagsI(eventflags_t flags) { - - chEvtBroadcastFlagsI(&ev_source, flags); - } -#endif /* CH_CFG_USE_EVENTS */ - -#if CH_CFG_USE_QUEUES - /*------------------------------------------------------------------------* - * chibios_rt::InQueue * - *------------------------------------------------------------------------*/ - InQueue::InQueue(uint8_t *bp, size_t size, qnotify_t infy, void *link) { - - chIQObjectInit(&iq, bp, size, infy, link); - } - - size_t InQueue::getFullI(void) { - - return chIQGetFullI(&iq); - } - - size_t InQueue::getEmptyI(void) { - - return chIQGetEmptyI(&iq); - } - - bool InQueue::isEmptyI(void) { - - return (bool)chIQIsEmptyI(&iq); - } - - bool InQueue::isFullI(void) { - - return (bool)chIQIsFullI(&iq); - } - - void InQueue::resetI(void) { - - chIQResetI(&iq); - } - - msg_t InQueue::putI(uint8_t b) { - - return chIQPutI(&iq, b); - } - - msg_t InQueue::get() { - - return chIQGet(&iq); - } - - msg_t InQueue::get(systime_t time) { - - return chIQGetTimeout(&iq, time); - } - - size_t InQueue::read(uint8_t *bp, size_t n, systime_t time) { - - return chIQReadTimeout(&iq, bp, n, time); - } - - /*------------------------------------------------------------------------* - * chibios_rt::OutQueue * - *------------------------------------------------------------------------*/ - OutQueue::OutQueue(uint8_t *bp, size_t size, qnotify_t onfy, void *link) { - - chOQObjectInit(&oq, bp, size, onfy, link); - } - - size_t OutQueue::getFullI(void) { - - return chOQGetFullI(&oq); - } - - size_t OutQueue::getEmptyI(void) { - - return chOQGetEmptyI(&oq); - } - - bool OutQueue::isEmptyI(void) { - - return (bool)chOQIsEmptyI(&oq); - } - - bool OutQueue::isFullI(void) { - - return (bool)chOQIsFullI(&oq); - } - - void OutQueue::resetI(void) { - - chOQResetI(&oq); - } - - msg_t OutQueue::put(uint8_t b) { - - return chOQPut(&oq, b); - } - - msg_t OutQueue::put(uint8_t b, systime_t time) { - - return chOQPutTimeout(&oq, b, time); - } - - msg_t OutQueue::getI(void) { - - return chOQGetI(&oq); - } - - size_t OutQueue::write(const uint8_t *bp, size_t n, systime_t time) { - - return chOQWriteTimeout(&oq, bp, n, time); - } -#endif /* CH_CFG_USE_QUEUES */ - -#if CH_CFG_USE_MEMPOOLS - /*------------------------------------------------------------------------* - * chibios_rt::MemoryPool * - *------------------------------------------------------------------------*/ - MemoryPool::MemoryPool(size_t size, memgetfunc_t provider) { - - chPoolObjectInit(&pool, size, provider); - } - - MemoryPool::MemoryPool(size_t size, memgetfunc_t provider, void* p, size_t n) { - - chPoolObjectInit(&pool, size, provider); - chPoolLoadArray(&pool, p, n); - } - - - void MemoryPool::loadArray(void *p, size_t n) { - - chPoolLoadArray(&pool, p, n); - } - - void *MemoryPool::allocI(void) { - - return chPoolAllocI(&pool); - } - - void *MemoryPool::alloc(void) { - - return chPoolAlloc(&pool); - } - - void MemoryPool::free(void *objp) { - - chPoolFree(&pool, objp); - } - - void MemoryPool::freeI(void *objp) { - - chPoolFreeI(&pool, objp); - } -#endif /* CH_CFG_USE_MEMPOOLS */ -} - -/** @} */ diff --git a/firmware/ChibiOS_16/os/various/cpp_wrappers/ch.hpp b/firmware/ChibiOS_16/os/various/cpp_wrappers/ch.hpp deleted file mode 100644 index b7004d14df..0000000000 --- a/firmware/ChibiOS_16/os/various/cpp_wrappers/ch.hpp +++ /dev/null @@ -1,2466 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file ch.hpp - * @brief C++ wrapper classes and definitions. - * - * @addtogroup cpp_library - * @{ - */ - -#include - -#ifndef _CH_HPP_ -#define _CH_HPP_ - -/** - * @brief ChibiOS-RT kernel-related classes and interfaces. - */ -namespace chibios_rt { - - /* Forward declarations */ - class Mutex; - - /*------------------------------------------------------------------------* - * chibios_rt::System * - *------------------------------------------------------------------------*/ - /** - * @brief Class encapsulating the base system functionalities. - */ - class System { - public: - /** - * @brief ChibiOS/RT initialization. - * @details After executing this function the current instructions stream - * becomes the main thread. - * @pre Interrupts must be still disabled when @p chSysInit() is invoked - * and are internally enabled. - * @post The main thread is created with priority @p NORMALPRIO. - * @note This function has special, architecture-dependent, requirements, - * see the notes into the various port reference manuals. - * - * @special - */ - static inline void init(void) { - - chSysInit(); - } - - /** - * @brief Halts the system. - * @details This function is invoked by the operating system when an - * unrecoverable error is detected, for example because a programming - * error in the application code that triggers an assertion while - * in debug mode. - * @note Can be invoked from any system state. - * - * @param[in] reason pointer to an error string - * - * @special - */ - static inline void halt(const char *reason) { - - chSysHalt(reason); - } - - /** - * @brief System integrity check. - * @details Performs an integrity check of the important ChibiOS/RT data - * structures. - * @note The appropriate action in case of failure is to halt the system - * before releasing the critical zone. - * @note If the system is corrupted then one possible outcome of this - * function is an exception caused by @p NULL or corrupted pointers - * in list elements. Exception vectors must be monitored as well. - * @note This function is not used internally, it is up to the - * application to define if and where to perform system - * checking. - * @note Performing all tests at once can be a slow operation and can - * degrade the system response time. It is suggested to execute - * one test at time and release the critical zone in between tests. - * - * @param[in] testmask Each bit in this mask is associated to a test to be - * performed. - * @return The test result. - * @retval false The test succeeded. - * @retval true Test failed. - * - * @iclass - */ - static inline bool integrityCheckI(unsigned int testmask) { - - return chSysIntegrityCheckI(testmask); - } - - /** - * @brief Enters the kernel lock mode. - * - * @special - */ - static inline void lock(void) { - - chSysLock(); - } - - /** - * @brief Leaves the kernel lock mode. - * - * @special - */ - static inline void unlock(void) { - - chSysUnlock(); - } - - /** - * @brief Enters the kernel lock mode from within an interrupt handler. - * @note This API may do nothing on some architectures, it is required - * because on ports that support preemptable interrupt handlers - * it is required to raise the interrupt mask to the same level of - * the system mutual exclusion zone.
- * It is good practice to invoke this API before invoking any I-class - * syscall from an interrupt handler. - * @note This API must be invoked exclusively from interrupt handlers. - * - * @special - */ - static inline void lockFromIsr(void) { - - chSysLockFromISR(); - } - - /** - * @brief Leaves the kernel lock mode from within an interrupt handler. - * - * @note This API may do nothing on some architectures, it is required - * because on ports that support preemptable interrupt handlers - * it is required to raise the interrupt mask to the same level of - * the system mutual exclusion zone.
- * It is good practice to invoke this API after invoking any I-class - * syscall from an interrupt handler. - * @note This API must be invoked exclusively from interrupt handlers. - * - * @special - */ - static inline void unlockFromIsr(void) { - - chSysUnlockFromISR(); - } - - /** - * @brief Returns the system time as system ticks. - * @note The system tick time interval is implementation dependent. - * - * @return The system time. - * - * @api - */ - static inline systime_t getTime(void) { - - return chVTGetSystemTime(); - } - - /** - * @brief Returns the system time as system ticks. - * @note The system tick time interval is implementation dependent. - * - * @return The system time. - * - * @xclass - */ - static inline systime_t getTimeX(void) { - - return chVTGetSystemTimeX(); - } - - /** - * @brief Checks if the current system time is within the specified time - * window. - * @note When start==end then the function returns always true because the - * whole time range is specified. - * - * @param[in] start the start of the time window (inclusive) - * @param[in] end the end of the time window (non inclusive) - * @retval true current time within the specified time window. - * @retval false current time not within the specified time window. - * - * @api - */ - static inline bool isSystemTimeWithin(systime_t start, systime_t end) { - - return chVTIsSystemTimeWithin(start, end); - } - }; - -#if CH_CFG_USE_MEMCORE || defined(__DOXYGEN__) - /*------------------------------------------------------------------------* - * chibios_rt::Core * - *------------------------------------------------------------------------*/ - /** - * @brief Class encapsulating the base system functionalities. - */ - class Core { - public: - - /** - * @brief Allocates a memory block. - * @details The size of the returned block is aligned to the alignment - * type so it is not possible to allocate less - * than MEM_ALIGN_SIZE. - * - * @param[in] size the size of the block to be allocated - * @return A pointer to the allocated memory block. - * @retval NULL allocation failed, core memory exhausted. - * - * @api - */ - static inline void *alloc(size_t size) { - - return chCoreAlloc(size); - } - - /** - * @brief Allocates a memory block. - * @details The size of the returned block is aligned to the alignment - * type so it is not possible to allocate less than - * MEM_ALIGN_SIZE. - * - * @param[in] size the size of the block to be allocated. - * @return A pointer to the allocated memory block. - * @retval NULL allocation failed, core memory exhausted. - * - * @iclass - */ - static inline void *allocI(size_t size) { - - return chCoreAllocI(size); - } - - /** - * @brief Core memory status. - * - * @return The size, in bytes, of the free core memory. - * - * @xclass - */ - static inline size_t getStatusX(void) { - - return chCoreGetStatusX(); - } - }; -#endif /* CH_CFG_USE_MEMCORE */ - - /*------------------------------------------------------------------------* - * chibios_rt::Timer * - *------------------------------------------------------------------------*/ - /** - * @brief Timer class. - */ - class Timer { - public: - /** - * @brief Embedded @p VirtualTimer structure. - */ - ::virtual_timer_t timer_ref; - - /** - * @brief Enables a virtual timer. - * @note The associated function is invoked from interrupt context. - * - * @param[in] time the number of ticks before the operation timeouts, - * the special values are handled as follow: - * - @a TIME_INFINITE is allowed but interpreted as a - * normal time specification. - * - @a TIME_IMMEDIATE this value is not allowed. - * . - * @param[in] vtfunc the timer callback function. After invoking the - * callback the timer is disabled and the structure - * can be disposed or reused. - * @param[in] par a parameter that will be passed to the callback - * function - * - * @iclass - */ - inline void setI(systime_t time, vtfunc_t vtfunc, void *par); - - /** - * @brief Resets the timer, if armed. - * - * @iclass - */ - inline void resetI(); - - /** - * @brief Returns the timer status. - * - * @retval TRUE The timer is armed. - * @retval FALSE The timer already fired its callback. - * - * @iclass - */ - inline bool isArmedI(void); - }; - - /*------------------------------------------------------------------------* - * chibios_rt::ThreadStayPoint * - *------------------------------------------------------------------------*/ - /** - * @brief Thread suspension point class. - * @details This class encapsulates a reference to a suspended thread. - */ - class ThreadStayPoint { - public: - /** - * @brief Pointer to the system thread. - */ - ::thread_reference_t thread_ref; - - /** - * @brief Suspends the current thread on the reference. - * @details The suspended thread becomes the referenced thread. It is - * possible to use this method only if the thread reference - * was set to @p NULL. - * - * @return The incoming message. - * - * @sclass - */ - inline msg_t suspendS(void); - - /** - * @brief Suspends the current thread on the reference with timeout. - * @details The suspended thread becomes the referenced thread. It is - * possible to use this method only if the thread reference - * was set to @p NULL. - * - * - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return A message specifying how the invoking thread has - * been released from the semaphore. - * @retval MSG_OK if the binary semaphore has been successfully - * taken. - * @retval MSG_RESET if the binary semaphore has been reset using - * @p bsemReset(). - * @retval MSG_TIMEOUT if the binary semaphore has not been signaled - * or reset within the specified timeout. - * - * @sclass - */ - inline msg_t suspendS(systime_t timeout); - - /** - * @brief Resumes the currently referenced thread, if any. - * - * @param[in] msg the wakeup message - * - * @iclass - */ - inline void resumeI(msg_t msg); - - /** - * @brief Resumes the currently referenced thread, if any. - * - * @param[in] msg the wakeup message - * - * @sclass - */ - inline void resumeS(msg_t msg); - }; - - /*------------------------------------------------------------------------* - * chibios_rt::ThreadReference * - *------------------------------------------------------------------------*/ - /** - * @brief Thread reference class. - * @details This class encapsulates a reference to a system thread. All - * operations involving another thread are performed through - * an object of this type. - */ - class ThreadReference { - public: - /** - * @brief Pointer to the system thread. - */ - ::thread_t *thread_ref; - - /** - * @brief Thread reference constructor. - * - * @param[in] tp the target thread. This parameter can be - * @p NULL if the thread is not known at - * creation time. - * - * @init - */ - ThreadReference(thread_t *tp) : thread_ref(tp) { - - }; - - /** - * @brief Stops the thread. - * @note The implementation is left to descendant classes and is - * optional. - */ - virtual void stop(void); - - /** - * @brief Requests a thread termination. - * @pre The target thread must be written to invoke periodically - * @p chThdShouldTerminate() and terminate cleanly if it returns - * @p TRUE. - * @post The specified thread will terminate after detecting the - * termination condition. - * - * @api - */ - void requestTerminate(void); - -#if CH_CFG_USE_WAITEXIT || defined(__DOXYGEN__) - /** - * @brief Blocks the execution of the invoking thread until the specified - * thread terminates then the exit code is returned. - * @details This function waits for the specified thread to terminate then - * decrements its reference counter, if the counter reaches zero - * then the thread working area is returned to the proper - * allocator.
- * The memory used by the exited thread is handled in different - * ways depending on the API that spawned the thread: - * - If the thread was spawned by @p chThdCreateStatic() or by - * @p chThdCreateI() then nothing happens and the thread working - * area is not released or modified in any way. This is the - * default, totally static, behavior. - * - If the thread was spawned by @p chThdCreateFromHeap() then - * the working area is returned to the system heap. - * - If the thread was spawned by @p chThdCreateFromMemoryPool() - * then the working area is returned to the owning memory pool. - * . - * @pre The configuration option @p CH_USE_WAITEXIT must be enabled in - * order to use this function. - * @post Enabling @p chThdWait() requires 2-4 (depending on the - * architecture) extra bytes in the @p Thread structure. - * @post After invoking @p chThdWait() the thread pointer becomes - * invalid and must not be used as parameter for further system - * calls. - * @note If @p CH_USE_DYNAMIC is not specified this function just waits - * for the thread termination, no memory allocators are involved. - * - * @return The exit code from the terminated thread. - * - * @api - */ - msg_t wait(void); -#endif /* CH_CFG_USE_WAITEXIT */ - -#if CH_CFG_USE_MESSAGES || defined(__DOXYGEN__) - /** - * @brief Sends a message to the thread and returns the answer. - * - * @param[in] msg the sent message - * @return The returned message. - * - * @api - */ - msg_t sendMessage(msg_t msg); - - /** - * @brief Returns true if there is at least one message in queue. - * - * @retval true A message is waiting in queue. - * @retval false A message is not waiting in queue. - * - * @api - */ - bool isPendingMessage(void); - - /** - * @brief Returns an enqueued message or @p NULL. - * - * @return The incoming message. - * - * @api - */ - msg_t getMessage(void); - - /** - * @brief Releases the next message in queue with a reply. - * - * @param[in] msg the answer message - * - * @api - */ - void releaseMessage(msg_t msg); -#endif /* CH_CFG_USE_MESSAGES */ - -#if CH_CFG_USE_EVENTS || defined(__DOXYGEN__) - /** - * @brief Adds a set of event flags directly to specified @p Thread. - * - * @param[in] mask the event flags set to be ORed - * - * @api - */ - void signalEvents(eventmask_t mask); - - /** - * @brief Adds a set of event flags directly to specified @p Thread. - * - * @param[in] mask the event flags set to be ORed - * - * @iclass - */ - void signalEventsI(eventmask_t mask); -#endif /* CH_CFG_USE_EVENTS */ - -#if CH_CFG_USE_DYNAMIC || defined(__DOXYGEN__) -#endif /* CH_CFG_USE_DYNAMIC */ - }; - - /*------------------------------------------------------------------------* - * chibios_rt::BaseThread * - *------------------------------------------------------------------------*/ - /** - * @brief Abstract base class for a ChibiOS/RT thread. - * @details The thread body is the virtual function @p Main(). - */ - class BaseThread : public ThreadReference { - public: - /** - * @brief BaseThread constructor. - * - * @init - */ - BaseThread(void); - - /** - * @brief Thread body function. - * - * @return The exit message. - * - * @api - */ - virtual void main(void); - - /** - * @brief Creates and starts a system thread. - * - * @param[in] prio thread priority - * @return A reference to the created thread with - * reference counter set to one. - * - * @api - */ - virtual ThreadReference start(tprio_t prio); - - /** - * @brief Sets the current thread name. - * @pre This function only stores the pointer to the name if the option - * @p CH_USE_REGISTRY is enabled else no action is performed. - * - * @param[in] tname thread name as a zero terminated string - * - * @api - */ - static void setName(const char *tname); - - /** - * @brief Changes the running thread priority level then reschedules if - * necessary. - * @note The function returns the real thread priority regardless of the - * current priority that could be higher than the real priority - * because the priority inheritance mechanism. - * - * @param[in] newprio the new priority level of the running thread - * @return The old priority level. - * - * @api - */ - static tprio_t setPriority(tprio_t newprio); - - /** - * @brief Terminates the current thread. - * @details The thread goes in the @p THD_STATE_FINAL state holding the - * specified exit status code, other threads can retrieve the - * exit status code by invoking the function @p chThdWait(). - * @post Eventual code after this function will never be executed, - * this function never returns. The compiler has no way to - * know this so do not assume that the compiler would remove - * the dead code. - * - * @param[in] msg thread exit code - * - * @api - */ - static void exit(msg_t msg); - - /** - * @brief Terminates the current thread. - * @details The thread goes in the @p THD_STATE_FINAL state holding the - * specified exit status code, other threads can retrieve the - * exit status code by invoking the function @p chThdWait(). - * @post Eventual code after this function will never be executed, - * this function never returns. The compiler has no way to - * know this so do not assume that the compiler would remove - * the dead code. - * - * @param[in] msg thread exit code - * - * @sclass - */ - static void exitS(msg_t msg); - - /** - * @brief Verifies if the current thread has a termination request - * pending. - * @note Can be invoked in any context. - * - * @retval TRUE termination request pending. - * @retval FALSE termination request not pending. - * - * @special - */ - static bool shouldTerminate(void); - - /** - * @brief Suspends the invoking thread for the specified time. - * - * @param[in] interval the delay in system ticks, the special values are - * handled as follow: - * - @a TIME_INFINITE the thread enters an infinite - * sleep state. - * - @a TIME_IMMEDIATE this value is not allowed. - * . - * - * @api - */ - static void sleep(systime_t interval); - - /** - * @brief Suspends the invoking thread until the system time arrives to - * the specified value. - * - * @param[in] time absolute system time - * - * @api - */ - static void sleepUntil(systime_t time); - - /** - * @brief Yields the time slot. - * @details Yields the CPU control to the next thread in the ready list - * with equal priority, if any. - * - * @api - */ - static void yield(void); - -#if CH_CFG_USE_MESSAGES || defined(__DOXYGEN__) - /** - * @brief Waits for a message. - * - * @return The sender thread. - * - * @api - */ - static ThreadReference waitMessage(void); -#endif /* CH_CFG_USE_MESSAGES */ - -#if CH_CFG_USE_EVENTS || defined(__DOXYGEN__) - /** - * @brief Clears the pending events specified in the mask. - * - * @param[in] mask the events to be cleared - * @return The pending events that were cleared. - * - * @api - */ - static eventmask_t getAndClearEvents(eventmask_t mask); - - /** - * @brief Adds (OR) a set of event flags on the current thread, this is - * @b much faster than using @p chEvtBroadcast() or - * @p chEvtSignal(). - * - * @param[in] mask the event flags to be added - * @return The current pending events mask. - * - * @api - */ - static eventmask_t addEvents(eventmask_t mask); - - /** - * @brief Waits for a single event. - * @details A pending event among those specified in @p ewmask is selected, - * cleared and its mask returned. - * @note One and only one event is served in the function, the one with - * the lowest event id. The function is meant to be invoked into - * a loop in order to serve all the pending events.
- * This means that Event Listeners with a lower event identifier - * have an higher priority. - * - * @param[in] ewmask mask of the events that the function should - * wait for, @p ALL_EVENTS enables all the events - * @return The mask of the lowest id served and cleared - * event. - * - * @api - */ - static eventmask_t waitOneEvent(eventmask_t ewmask); - - /** - * @brief Waits for any of the specified events. - * @details The function waits for any event among those specified in - * @p ewmask to become pending then the events are cleared and - * returned. - * - * @param[in] ewmask mask of the events that the function should - * wait for, @p ALL_EVENTS enables all the events - * @return The mask of the served and cleared events. - * - * @api - */ - static eventmask_t waitAnyEvent(eventmask_t ewmask); - - /** - * @brief Waits for all the specified event flags then clears them. - * @details The function waits for all the events specified in @p ewmask - * to become pending then the events are cleared and returned. - * - * @param[in] ewmask mask of the event ids that the function should - * wait for - * @return The mask of the served and cleared events. - * - * @api - */ - static eventmask_t waitAllEvents(eventmask_t ewmask); - -#if CH_CFG_USE_EVENTS_TIMEOUT || defined(__DOXYGEN__) - /** - * @brief Waits for a single event. - * @details A pending event among those specified in @p ewmask is selected, - * cleared and its mask returned. - * @note One and only one event is served in the function, the one with - * the lowest event id. The function is meant to be invoked into - * a loop in order to serve all the pending events.
- * This means that Event Listeners with a lower event identifier - * have an higher priority. - * - * @param[in] ewmask mask of the events that the function should - * wait for, @p ALL_EVENTS enables all the events - * - * @param[in] time the number of ticks before the operation - * timouts - * @return The mask of the lowest id served and cleared - * event. - * @retval 0 if the specified timeout expired. - * - * @api - */ - static eventmask_t waitOneEventTimeout(eventmask_t ewmask, - systime_t time); - - /** - * @brief Waits for any of the specified events. - * @details The function waits for any event among those specified in - * @p ewmask to become pending then the events are cleared and - * returned. - * - * @param[in] ewmask mask of the events that the function should - * wait for, @p ALL_EVENTS enables all the events - * @param[in] time the number of ticks before the operation - * timouts - * @return The mask of the served and cleared events. - * @retval 0 if the specified timeout expired. - * - * @api - */ - static eventmask_t waitAnyEventTimeout(eventmask_t ewmask, - systime_t time); - - /** - * @brief Waits for all the specified event flags then clears them. - * @details The function waits for all the events specified in @p ewmask - * to become pending then the events are cleared and returned. - * - * @param[in] ewmask mask of the event ids that the function should - * wait for - * @param[in] time the number of ticks before the operation - * timouts - * @return The mask of the served and cleared events. - * @retval 0 if the specified timeout expired. - * - * @api - */ - static eventmask_t waitAllEventsTimeout(eventmask_t ewmask, - systime_t time); -#endif /* CH_CFG_USE_EVENTS_TIMEOUT */ - - /** - * @brief Invokes the event handlers associated to an event flags mask. - * - * @param[in] mask mask of the event flags to be dispatched - * @param[in] handlers an array of @p evhandler_t. The array must have - * size equal to the number of bits in eventmask_t. - * - * @api - */ - static void dispatchEvents(const evhandler_t handlers[], - eventmask_t mask); -#endif /* CH_CFG_USE_EVENTS */ - -#if CH_CFG_USE_MUTEXES || defined(__DOXYGEN__) - /** - * @brief Unlocks the next owned mutex in reverse lock order. - * @pre The invoking thread must have at least one owned mutex. - * @post The mutex is unlocked and removed from the per-thread stack of - * owned mutexes. - * - * @return A pointer to the unlocked mutex. - * - * @api - */ - static void unlockMutex(Mutex *mp); - - /** - * @brief Unlocks the next owned mutex in reverse lock order. - * @pre The invoking thread must have at least one owned mutex. - * @post The mutex is unlocked and removed from the per-thread stack of - * owned mutexes. - * @post This function does not reschedule so a call to a rescheduling - * function must be performed before unlocking the kernel. - * - * @return A pointer to the unlocked mutex. - * - * @sclass - */ - static void unlockMutexS(Mutex *mp); - - /** - * @brief Unlocks all the mutexes owned by the invoking thread. - * @post The stack of owned mutexes is emptied and all the found - * mutexes are unlocked. - * @note This function is MUCH MORE efficient than releasing the - * mutexes one by one and not just because the call overhead, - * this function does not have any overhead related to the - * priority inheritance mechanism. - * - * @api - */ - static void unlockAllMutexes(void); -#endif /* CH_CFG_USE_MUTEXES */ - }; - - /*------------------------------------------------------------------------* - * chibios_rt::BaseStaticThread * - *------------------------------------------------------------------------*/ - /** - * @brief Static threads template class. - * @details This class introduces static working area allocation. - * - * @param N the working area size for the thread class - */ - template - class BaseStaticThread : public BaseThread { - protected: - THD_WORKING_AREA(wa, N); - - public: - /** - * @brief Thread constructor. - * @details The thread object is initialized but the thread is not - * started here. - * - * @init - */ - BaseStaticThread(void) : BaseThread() { - - } - - /** - * @brief Creates and starts a system thread. - * - * @param[in] prio thread priority - * @return A reference to the created thread with - * reference counter set to one. - * - * @api - */ - virtual ThreadReference start(tprio_t prio) { - void _thd_start(void *arg); - - thread_ref = chThdCreateStatic(wa, sizeof(wa), prio, _thd_start, this); - return *this; - } - }; - -#if CH_CFG_USE_SEMAPHORES || defined(__DOXYGEN__) - /*------------------------------------------------------------------------* - * chibios_rt::CounterSemaphore * - *------------------------------------------------------------------------*/ - /** - * @brief Class encapsulating a semaphore. - */ - class CounterSemaphore { - public: - /** - * @brief Embedded @p ::Semaphore structure. - */ - ::semaphore_t sem; - - /** - * @brief CounterSemaphore constructor. - * @details The embedded @p ::Semaphore structure is initialized. - * - * @param[in] n the semaphore counter value, must be greater - * or equal to zero - * - * @init - */ - CounterSemaphore(cnt_t n); - - /** - * @brief Performs a reset operation on the semaphore. - * @post After invoking this function all the threads waiting on the - * semaphore, if any, are released and the semaphore counter is - * set to the specified, non negative, value. - * @note The released threads can recognize they were waked up by a - * reset rather than a signal because the @p chSemWait() will - * return @p MSG_RESET instead of @p MSG_OK. - * - * @param[in] n the new value of the semaphore counter. The value - * must be non-negative. - * - * @api - */ - void reset(cnt_t n); - - /** - * @brief Performs a reset operation on the semaphore. - * @post After invoking this function all the threads waiting on the - * semaphore, if any, are released and the semaphore counter is - * set to the specified, non negative, value. - * @post This function does not reschedule so a call to a rescheduling - * function must be performed before unlocking the kernel. Note - * that interrupt handlers always reschedule on exit so an - * explicit reschedule must not be performed in ISRs. - * @note The released threads can recognize they were waked up by a - * reset rather than a signal because the @p chSemWait() will - * return @p MSG_RESET instead of @p MSG_OK. - * - * @param[in] n the new value of the semaphore counter. The value - * must be non-negative. - * - * @iclass - */ - void resetI(cnt_t n); - - /** - * @brief Performs a wait operation on a semaphore. - * - * @return A message specifying how the invoking thread has - * been released from the semaphore. - * @retval MSG_OK if the thread has not stopped on the semaphore or - * the semaphore has been signaled. - * @retval MSG_RESET if the semaphore has been reset using - * @p chSemReset(). - * - * @api - */ - msg_t wait(void); - - /** - * @brief Performs a wait operation on a semaphore. - * - * @return A message specifying how the invoking thread has - * been released from the semaphore. - * @retval MSG_OK if the thread has not stopped on the semaphore or - * the semaphore has been signaled. - * @retval MSG_RESET if the semaphore has been reset using - * @p chSemReset(). - * - * @sclass - */ - msg_t waitS(void); - - /** - * @brief Performs a wait operation on a semaphore with timeout - * specification. - * - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return A message specifying how the invoking thread has - * been released from the semaphore. - * @retval MSG_OK if the thread has not stopped on the semaphore or - * the semaphore has been signaled. - * @retval MSG_RESET if the semaphore has been reset using - * @p chSemReset(). - * @retval MSG_TIMEOUT if the semaphore has not been signaled or reset - * within the specified timeout. - * - * @api - */ - msg_t wait(systime_t time); - - /** - * @brief Performs a wait operation on a semaphore with timeout - * specification. - * - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return A message specifying how the invoking thread has - * been released from the semaphore. - * @retval MSG_OK if the thread has not stopped on the semaphore or - * the semaphore has been signaled. - * @retval MSG_RESET if the semaphore has been reset using - * @p chSemReset(). - * @retval MSG_TIMEOUT if the semaphore has not been signaled or reset - * within the specified timeout. - * - * @sclass - */ - msg_t waitS(systime_t time); - - /** - * @brief Performs a signal operation on a semaphore. - * - * @api - */ - void signal(void); - - /** - * @brief Performs a signal operation on a semaphore. - * @post This function does not reschedule so a call to a rescheduling - * function must be performed before unlocking the kernel. Note - * that interrupt handlers always reschedule on exit so an - * explicit reschedule must not be performed in ISRs. - * - * @iclass - */ - void signalI(void); - - /** - * @brief Adds the specified value to the semaphore counter. - * @post This function does not reschedule so a call to a rescheduling - * function must be performed before unlocking the kernel. Note - * that interrupt handlers always reschedule on exit so an explicit - * reschedule must not be performed in ISRs. - * - * @param[in] n value to be added to the semaphore counter. The - * value must be positive. - * - * @iclass - */ - void addCounterI(cnt_t n); - - /** - * @brief Returns the semaphore counter value. - * - * @return The semaphore counter value. - * - * @iclass - */ - cnt_t getCounterI(void); - - /** - * @brief Atomic signal and wait operations. - * - * @param[in] ssem @p Semaphore object to be signaled - * @param[in] wsem @p Semaphore object to wait on - * @return A message specifying how the invoking thread - * has been released from the semaphore. - * @retval MSG_OK if the thread has not stopped on the semaphore - * or the semaphore has been signaled. - * @retval MSG_RESET if the semaphore has been reset using - * @p chSemReset(). - * - * @api - */ - static msg_t signalWait(CounterSemaphore *ssem, - CounterSemaphore *wsem); - }; - /*------------------------------------------------------------------------* - * chibios_rt::BinarySemaphore * - *------------------------------------------------------------------------*/ - /** - * @brief Class encapsulating a binary semaphore. - */ - class BinarySemaphore { - public: - /** - * @brief Embedded @p ::Semaphore structure. - */ - ::binary_semaphore_t bsem; - - /** - * @brief BinarySemaphore constructor. - * @details The embedded @p ::BinarySemaphore structure is initialized. - * - * @param[in] taken initial state of the binary semaphore: - * - @a false, the initial state is not taken. - * - @a true, the initial state is taken. - * . - * - * @init - */ - BinarySemaphore(bool taken); - - /** - * @brief Wait operation on the binary semaphore. - * - * @return A message specifying how the invoking thread has - * been released from the semaphore. - * @retval MSG_OK if the binary semaphore has been successfully - * taken. - * @retval MSG_RESET if the binary semaphore has been reset using - * @p bsemReset(). - * - * @api - */ - msg_t wait(void); - - /** - * @brief Wait operation on the binary semaphore. - * - * @return A message specifying how the invoking thread has - * been released from the semaphore. - * @retval MSG_OK if the binary semaphore has been successfully - * taken. - * @retval MSG_RESET if the binary semaphore has been reset using - * @p bsemReset(). - * - * @sclass - */ - msg_t waitS(void); - - /** - * @brief Wait operation on the binary semaphore. - * - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return A message specifying how the invoking thread has - * been released from the semaphore. - * @retval MSG_OK if the binary semaphore has been successfully - * taken. - * @retval MSG_RESET if the binary semaphore has been reset using - * @p bsemReset(). - * @retval MSG_TIMEOUT if the binary semaphore has not been signaled - * or reset within the specified timeout. - * - * @api - */ - msg_t wait(systime_t time); - - /** - * @brief Wait operation on the binary semaphore. - * - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return A message specifying how the invoking thread has - * been released from the semaphore. - * @retval MSG_OK if the binary semaphore has been successfully - * taken. - * @retval MSG_RESET if the binary semaphore has been reset using - * @p bsemReset(). - * @retval MSG_TIMEOUT if the binary semaphore has not been signaled - * or reset within the specified timeout. - * - * @sclass - */ - msg_t waitS(systime_t time); - - /** - * @brief Reset operation on the binary semaphore. - * @note The released threads can recognize they were waked up by a - * reset rather than a signal because the @p bsemWait() will - * return @p MSG_RESET instead of @p MSG_OK. - * - * @param[in] taken new state of the binary semaphore - * - @a FALSE, the new state is not taken. - * - @a TRUE, the new state is taken. - * . - * - * @api - */ - void reset(bool taken); - - /** - * @brief Reset operation on the binary semaphore. - * @note The released threads can recognize they were waked up by a - * reset rather than a signal because the @p bsemWait() will - * return @p MSG_RESET instead of @p MSG_OK. - * @note This function does not reschedule. - * - * @param[in] taken new state of the binary semaphore - * - @a FALSE, the new state is not taken. - * - @a TRUE, the new state is taken. - * . - * - * @iclass - */ - void resetI(bool taken); - - /** - * @brief Performs a signal operation on a binary semaphore. - * - * @api - */ - void signal(void); - - /** - * @brief Performs a signal operation on a binary semaphore. - * @note This function does not reschedule. - * - * @iclass - */ - void signalI(void); - - /** - * @brief Returns the binary semaphore current state. - * - * @return The binary semaphore current state. - * @retval false if the binary semaphore is not taken. - * @retval true if the binary semaphore is taken. - * - * @iclass - */ - bool getStateI(void); -}; -#endif /* CH_CFG_USE_SEMAPHORES */ - -#if CH_CFG_USE_MUTEXES || defined(__DOXYGEN__) - /*------------------------------------------------------------------------* - * chibios_rt::Mutex * - *------------------------------------------------------------------------*/ - /** - * @brief Class encapsulating a mutex. - */ - class Mutex { - public: - /** - * @brief Embedded @p ::Mutex structure. - */ - ::mutex_t mutex; - - /** - * @brief Mutex object constructor. - * @details The embedded @p ::Mutex structure is initialized. - * - * @init - */ - Mutex(void); - - /** - * @brief Tries to lock a mutex. - * @details This function attempts to lock a mutex, if the mutex is already - * locked by another thread then the function exits without - * waiting. - * @post The mutex is locked and inserted in the per-thread stack of - * owned mutexes. - * @note This function does not have any overhead related to the - * priority inheritance mechanism because it does not try to - * enter a sleep state. - * - * @return The operation status. - * @retval TRUE if the mutex has been successfully acquired - * @retval FALSE if the lock attempt failed. - * - * @api - */ - bool tryLock(void); - - /** - * @brief Tries to lock a mutex. - * @details This function attempts to lock a mutex, if the mutex is already - * taken by another thread then the function exits without - * waiting. - * @post The mutex is locked and inserted in the per-thread stack of - * owned mutexes. - * @note This function does not have any overhead related to the - * priority inheritance mechanism because it does not try to - * enter a sleep state. - * - * @return The operation status. - * @retval TRUE if the mutex has been successfully acquired - * @retval FALSE if the lock attempt failed. - * - * @sclass - */ - bool tryLockS(void); - - /** - * @brief Locks the specified mutex. - * @post The mutex is locked and inserted in the per-thread stack of - * owned mutexes. - * - * @api - */ - void lock(void); - - /** - * @brief Locks the specified mutex. - * @post The mutex is locked and inserted in the per-thread stack of - * owned mutexes. - * - * @sclass - */ - void lockS(void); - - /** - * @brief Unlocks the next owned mutex in reverse lock order. - * @pre The invoking thread must have at least one owned mutex. - * @post The mutex is unlocked and removed from the per-thread stack of - * owned mutexes. - * - * @api - */ - void unlock(void); - - /** - * @brief Unlocks the next owned mutex in reverse lock order. - * @pre The invoking thread must have at least one owned mutex. - * @post The mutex is unlocked and removed from the per-thread stack of - * owned mutexes. - * @post This function does not reschedule so a call to a rescheduling - * function must be performed before unlocking the kernel. - * - * @sclass - */ - void unlockS(void); - }; - -#if CH_CFG_USE_CONDVARS || defined(__DOXYGEN__) - /*------------------------------------------------------------------------* - * chibios_rt::CondVar * - *------------------------------------------------------------------------*/ - /** - * @brief Class encapsulating a conditional variable. - */ - class CondVar { - public: - /** - * @brief Embedded @p ::CondVar structure. - */ - ::condition_variable_t condvar; - - /** - * @brief CondVar object constructor. - * @details The embedded @p ::CondVar structure is initialized. - * - * @init - */ - CondVar(void); - - /** - * @brief Signals one thread that is waiting on the condition variable. - * - * @api - */ - void signal(void); - - /** - * @brief Signals one thread that is waiting on the condition variable. - * @post This function does not reschedule so a call to a rescheduling - * function must be performed before unlocking the kernel. Note - * that interrupt handlers always reschedule on exit so an - * explicit reschedule must not be performed in ISRs. - * - * @iclass - */ - void signalI(void); - - /** - * @brief Signals all threads that are waiting on the condition variable. - * - * @api - */ - void broadcast(void); - - /** - * @brief Signals all threads that are waiting on the condition variable. - * @post This function does not reschedule so a call to a rescheduling - * function must be performed before unlocking the kernel. Note - * that interrupt handlers always reschedule on exit so an - * explicit reschedule must not be performed in ISRs. - * - * @iclass - */ - void broadcastI(void); - - /** - * @brief Waits on the condition variable releasing the mutex lock. - * @details Releases the currently owned mutex, waits on the condition - * variable, and finally acquires the mutex again. All the - * sequence is performed atomically. - * @pre The invoking thread must have at least one owned mutex. - * - * @return A message specifying how the invoking thread has - * been released from the condition variable. - * @retval MSG_OK if the condvar has been signaled using - * @p chCondSignal(). - * @retval MSG_RESET if the condvar has been signaled using - * @p chCondBroadcast(). - * - * @api - */ - msg_t wait(void); - - /** - * @brief Waits on the condition variable releasing the mutex lock. - * @details Releases the currently owned mutex, waits on the condition - * variable, and finally acquires the mutex again. All the - * sequence is performed atomically. - * @pre The invoking thread must have at least one owned mutex. - * - * @return A message specifying how the invoking thread has - * been released from the condition variable. - * @retval MSG_OK if the condvar has been signaled using - * @p chCondSignal(). - * @retval MSG_RESET if the condvar has been signaled using - * @p chCondBroadcast(). - * - * @sclass - */ - msg_t waitS(void); - -#if CH_CFG_USE_CONDVARS_TIMEOUT || defined(__DOXYGEN__) - /** - * @brief Waits on the CondVar while releasing the controlling mutex. - * - * @param[in] time the number of ticks before the operation fails - * @return The wakep mode. - * @retval MSG_OK if the condvar was signaled using - * @p chCondSignal(). - * @retval MSG_RESET if the condvar was signaled using - * @p chCondBroadcast(). - * @retval MSG_TIMEOUT if the condvar was not signaled within the - * specified timeout. - * - * @api - */ - msg_t wait(systime_t time); -#endif /* CH_CFG_USE_CONDVARS_TIMEOUT */ - }; -#endif /* CH_CFG_USE_CONDVARS */ -#endif /* CH_CFG_USE_MUTEXES */ - -#if CH_CFG_USE_EVENTS || defined(__DOXYGEN__) - /*------------------------------------------------------------------------* - * chibios_rt::EvtListener * - *------------------------------------------------------------------------*/ - /** - * @brief Class encapsulating an event listener. - */ - class EvtListener { - public: - /** - * @brief Embedded @p ::EventListener structure. - */ - ::event_listener_t ev_listener; - - /** - * @brief Returns the pending flags from the listener and clears them. - * - * @return The flags added to the listener by the - * associated event source. - * - * @api - */ - eventflags_t getAndClearFlags(void); - - /** - * @brief Returns the flags associated to an @p EventListener. - * @details The flags are returned and the @p EventListener flags mask is - * cleared. - * - * @return The flags added to the listener by the associated - * event source. - * - * @iclass - */ - eventflags_t getAndClearFlagsI(void); - }; - - /*------------------------------------------------------------------------* - * chibios_rt::EvtSource * - *------------------------------------------------------------------------*/ - /** - * @brief Class encapsulating an event source. - */ - class EvtSource { - public: - /** - * @brief Embedded @p ::EventSource structure. - */ - ::event_source_t ev_source; - - /** - * @brief EvtSource object constructor. - * @details The embedded @p ::EventSource structure is initialized. - * - * @init - */ - EvtSource(void); - - /** - * @brief Registers a listener on the event source. - * - * @param[in] elp pointer to the @p EvtListener object - * @param[in] eid numeric identifier assigned to the Event - * Listener - * - * @api - */ - void registerOne(chibios_rt::EvtListener *elp, eventid_t eid); - - /** - * @brief Registers an Event Listener on an Event Source. - * @note Multiple Event Listeners can specify the same bits to be added. - * - * @param[in] elp pointer to the @p EvtListener object - * @param[in] emask the mask of event flags to be pended to the - * thread when the event source is broadcasted - * - * @api - */ - void registerMask(chibios_rt::EvtListener *elp, eventmask_t emask); - - /** - * @brief Unregisters a listener. - * @details The specified listeners is no more signaled by the event - * source. - * - * @param[in] elp the listener to be unregistered - * - * @api - */ - void unregister(chibios_rt::EvtListener *elp); - - /** - * @brief Broadcasts on an event source. - * @details All the listeners registered on the event source are signaled - * and the flags are added to the listener's flags mask. - * - * @param[in] flags the flags set to be added to the listener - * flags mask - * - * @api - */ - void broadcastFlags(eventflags_t flags); - - /** - * @brief Broadcasts on an event source. - * @details All the listeners registered on the event source are signaled - * and the flags are added to the listener's flags mask. - * - * @param[in] flags the flags set to be added to the listener - * flags mask - * - * @iclass - */ - void broadcastFlagsI(eventflags_t flags); - }; -#endif /* CH_CFG_USE_EVENTS */ - -#if CH_CFG_USE_QUEUES || defined(__DOXYGEN__) - /*------------------------------------------------------------------------* - * chibios_rt::InQueue * - *------------------------------------------------------------------------*/ - /** - * @brief Class encapsulating an input queue. - */ - class InQueue { - private: - /** - * @brief Embedded @p ::InputQueue structure. - */ - ::input_queue_t iq; - - public: - /** - * @brief InQueue constructor. - * - * @param[in] bp pointer to a memory area allocated as queue buffer - * @param[in] size size of the queue buffer - * @param[in] infy pointer to a callback function that is invoked when - * data is read from the queue. The value can be - * @p NULL. - * @param[in] link application defined pointer - * - * @init - */ - InQueue(uint8_t *bp, size_t size, qnotify_t infy, void *link); - - /** - * @brief Returns the filled space into an input queue. - * - * @return The number of full bytes in the queue. - * @retval 0 if the queue is empty. - * - * @iclass - */ - size_t getFullI(void); - - /** - * @brief Returns the empty space into an input queue. - * - * @return The number of empty bytes in the queue. - * @retval 0 if the queue is full. - * - * @iclass - */ - size_t getEmptyI(void); - - /** - * @brief Evaluates to @p TRUE if the specified input queue is empty. - * - * @return The queue status. - * @retval false if the queue is not empty. - * @retval true if the queue is empty. - * - * @iclass - */ - bool isEmptyI(void); - - /** - * @brief Evaluates to @p TRUE if the specified input queue is full. - * - * @return The queue status. - * @retval FALSE if the queue is not full. - * @retval TRUE if the queue is full. - * - * @iclass - */ - bool isFullI(void); - - /** - * @brief Resets an input queue. - * @details All the data in the input queue is erased and lost, any waiting - * thread is resumed with status @p Q_RESET. - * @note A reset operation can be used by a low level driver in order to - * obtain immediate attention from the high level layers. - * @iclass - */ - void resetI(void); - - /** - * @brief Input queue write. - * @details A byte value is written into the low end of an input queue. - * - * @param[in] b the byte value to be written in the queue - * @return The operation status. - * @retval Q_OK if the operation has been completed with success. - * @retval Q_FULL if the queue is full and the operation cannot be - * completed. - * - * @iclass - */ - msg_t putI(uint8_t b); - - /** - * @brief Input queue read. - * @details This function reads a byte value from an input queue. If the - * queue is empty then the calling thread is suspended until a - * byte arrives in the queue. - * - * @return A byte value from the queue. - * @retval Q_RESET if the queue has been reset. - * - * @api - */ - msg_t get(); - - /** - * @brief Input queue read with timeout. - * @details This function reads a byte value from an input queue. If the - * queue is empty then the calling thread is suspended until a - * byte arrives in the queue or a timeout occurs. - * @note The callback is invoked before reading the character from the - * buffer or before entering the state @p THD_STATE_WTQUEUE. - * - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return A byte value from the queue. - * @retval Q_TIMEOUT if the specified time expired. - * @retval Q_RESET if the queue has been reset. - * - * @api - */ - msg_t get(systime_t time); - - /** - * @brief Input queue read with timeout. - * @details The function reads data from an input queue into a buffer. The - * operation completes when the specified amount of data has been - * transferred or after the specified timeout or if the queue has - * been reset. - * @note The function is not atomic, if you need atomicity it is - * suggested to use a semaphore or a mutex for mutual exclusion. - * @note The callback is invoked before reading each character from the - * buffer or before entering the state @p THD_STATE_WTQUEUE. - * - * @param[out] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred, the - * value 0 is reserved - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The number of bytes effectively transferred. - * - * @api - */ - size_t read(uint8_t *bp, size_t n, systime_t time); - }; - - /*------------------------------------------------------------------------* - * chibios_rt::InQueueBuffer * - *------------------------------------------------------------------------*/ - /** - * @brief Template class encapsulating an input queue and its buffer. - * - * @param N size of the input queue - */ - template - class InQueueBuffer : public InQueue { - private: - uint8_t iq_buf[N]; - - public: - /** - * @brief InQueueBuffer constructor. - * - * @param[in] infy input notify callback function - * @param[in] link parameter to be passed to the callback - * - * @init - */ - InQueueBuffer(qnotify_t infy, void *link) : InQueue(iq_buf, N, - infy, link) { - } - }; - - /*------------------------------------------------------------------------* - * chibios_rt::OutQueue * - *------------------------------------------------------------------------*/ - /** - * @brief Class encapsulating an output queue. - */ - class OutQueue { - private: - /** - * @brief Embedded @p ::OutputQueue structure. - */ - ::output_queue_t oq; - - public: - /** - * @brief OutQueue constructor. - * - * @param[in] bp pointer to a memory area allocated as queue buffer - * @param[in] size size of the queue buffer - * @param[in] onfy pointer to a callback function that is invoked when - * data is written to the queue. The value can be - * @p NULL. - * @param[in] link application defined pointer - * - * @init - */ - OutQueue(uint8_t *bp, size_t size, qnotify_t onfy, void *link); - - /** - * @brief Returns the filled space into an output queue. - * - * @return The number of full bytes in the queue. - * @retval 0 if the queue is empty. - * - * @iclass - */ - size_t getFullI(void); - - /** - * @brief Returns the empty space into an output queue. - * - * @return The number of empty bytes in the queue. - * @retval 0 if the queue is full. - * - * @iclass - */ - size_t getEmptyI(void); - - /** - * @brief Evaluates to @p TRUE if the specified output queue is empty. - * - * @return The queue status. - * @retval false if the queue is not empty. - * @retval true if the queue is empty. - * - * @iclass - */ - bool isEmptyI(void); - - /** - * @brief Evaluates to @p TRUE if the specified output queue is full. - * - * @return The queue status. - * @retval FALSE if the queue is not full. - * @retval TRUE if the queue is full. - * - * @iclass - */ - bool isFullI(void); - - /** - * @brief Resets an output queue. - * @details All the data in the output queue is erased and lost, any - * waiting thread is resumed with status @p Q_RESET. - * @note A reset operation can be used by a low level driver in order - * to obtain immediate attention from the high level layers. - * - * @iclass - */ - void resetI(void); - - /** - * @brief Output queue write. - * @details This function writes a byte value to an output queue. If the - * queue is full then the calling thread is suspended until there - * is space in the queue. - * - * @param[in] b the byte value to be written in the queue - * @return The operation status. - * @retval Q_OK if the operation succeeded. - * @retval Q_RESET if the queue has been reset. - * - * @api - */ - msg_t put(uint8_t b); - - /** - * @brief Output queue write with timeout. - * @details This function writes a byte value to an output queue. If the - * queue is full then the calling thread is suspended until there - * is space in the queue or a timeout occurs. - * @note The callback is invoked after writing the character into the - * buffer. - * - * @param[in] b the byte value to be written in the queue - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval Q_OK if the operation succeeded. - * @retval Q_TIMEOUT if the specified time expired. - * @retval Q_RESET if the queue has been reset. - * - * @api - */ - msg_t put(uint8_t b, systime_t time); - - /** - * @brief Output queue read. - * @details A byte value is read from the low end of an output queue. - * - * @return The byte value from the queue. - * @retval Q_EMPTY if the queue is empty. - * - * @iclass - */ - msg_t getI(void); - - /** - * @brief Output queue write with timeout. - * @details The function writes data from a buffer to an output queue. The - * operation completes when the specified amount of data has been - * transferred or after the specified timeout or if the queue has - * been reset. - * @note The function is not atomic, if you need atomicity it is - * suggested to use a semaphore or a mutex for mutual exclusion. - * @note The callback is invoked after writing each character into the - * buffer. - * - * @param[out] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred, the - * value 0 is reserved - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The number of bytes effectively transferred. - * - * @api - */ - size_t write(const uint8_t *bp, size_t n, systime_t time); -}; - - /*------------------------------------------------------------------------* - * chibios_rt::OutQueueBuffer * - *------------------------------------------------------------------------*/ - /** - * @brief Template class encapsulating an output queue and its buffer. - * - * @param N size of the output queue - */ - template - class OutQueueBuffer : public OutQueue { - private: - uint8_t oq_buf[N]; - - public: - /** - * @brief OutQueueBuffer constructor. - * - * @param[in] onfy output notify callback function - * @param[in] link parameter to be passed to the callback - * - * @init - */ - OutQueueBuffer(qnotify_t onfy, void *link) : OutQueue(oq_buf, N, - onfy, link) { - } - }; -#endif /* CH_CFG_USE_QUEUES */ - -#if CH_CFG_USE_MAILBOXES || defined(__DOXYGEN__) - /*------------------------------------------------------------------------* - * chibios_rt::Mailbox * - *------------------------------------------------------------------------*/ - /** - * @brief Base mailbox class. - * - * @param T type of objects that mailbox able to handle - */ - template - class MailboxBase { - public: - - /** - * @brief Embedded @p ::Mailbox structure. - */ - ::mailbox_t mb; - - /** - * @brief Mailbox constructor. - * @details The embedded @p ::Mailbox structure is initialized. - * - * @param[in] buf pointer to the messages buffer as an array of - * @p msg_t - * @param[in] n number of elements in the buffer array - * - * @init - */ - MailboxBase(msg_t *buf, cnt_t n) { - - chMBObjectInit(&mb, buf, n); - } - - /** - * @brief Resets a Mailbox object. - * @details All the waiting threads are resumed with status @p MSG_RESET - * and the queued messages are lost. - * - * @api - */ - void reset(void) { - - chMBReset(&mb); - } - - /** - * @brief Posts a message into a mailbox. - * @details The invoking thread waits until a empty slot in the mailbox - * becomes available or the specified time runs out. - * - * @param[in] msg the message to be posted on the mailbox - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval MSG_OK if a message has been correctly posted. - * @retval MSG_RESET if the mailbox has been reset while waiting. - * @retval MSG_TIMEOUT if the operation has timed out. - * - * @api - */ - msg_t post(T msg, systime_t time) { - - return chMBPost(&mb, reinterpret_cast(msg), time); - } - - /** - * @brief Posts a message into a mailbox. - * @details The invoking thread waits until a empty slot in the mailbox - * becomes available or the specified time runs out. - * - * @param[in] msg the message to be posted on the mailbox - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval MSG_OK if a message has been correctly posted. - * @retval MSG_RESET if the mailbox has been reset while waiting. - * @retval MSG_TIMEOUT if the operation has timed out. - * - * @sclass - */ - msg_t postS(T msg, systime_t time) { - - return chMBPostS(&mb, reinterpret_cast(msg), time); - } - - /** - * @brief Posts a message into a mailbox. - * @details This variant is non-blocking, the function returns a timeout - * condition if the queue is full. - * - * @param[in] msg the message to be posted on the mailbox - * @return The operation status. - * @retval MSG_OK if a message has been correctly posted. - * @retval MSG_TIMEOUT if the mailbox is full and the message cannot be - * posted. - * - * @iclass - */ - msg_t postI(T msg) { - - return chMBPostI(&mb, reinterpret_cast(msg)); - } - - /** - * @brief Posts an high priority message into a mailbox. - * @details The invoking thread waits until a empty slot in the mailbox - * becomes available or the specified time runs out. - * - * @param[in] msg the message to be posted on the mailbox - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval MSG_OK if a message has been correctly posted. - * @retval MSG_RESET if the mailbox has been reset while waiting. - * @retval MSG_TIMEOUT if the operation has timed out. - * - * @api - */ - msg_t postAhead(T msg, systime_t time) { - - return chMBPostAhead(&mb, reinterpret_cast(msg), time); - } - - /** - * @brief Posts an high priority message into a mailbox. - * @details The invoking thread waits until a empty slot in the mailbox - * becomes available or the specified time runs out. - * - * @param[in] msg the message to be posted on the mailbox - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval MSG_OK if a message has been correctly posted. - * @retval MSG_RESET if the mailbox has been reset while waiting. - * @retval MSG_TIMEOUT if the operation has timed out. - * - * @sclass - */ - msg_t postAheadS(T msg, systime_t time) { - - return chMBPostAheadS(&mb, reinterpret_cast(msg), time); - } - - /** - * @brief Posts an high priority message into a mailbox. - * @details This variant is non-blocking, the function returns a timeout - * condition if the queue is full. - * - * @param[in] msg the message to be posted on the mailbox - * @return The operation status. - * @retval MSG_OK if a message has been correctly posted. - * @retval MSG_TIMEOUT if the mailbox is full and the message cannot be - * posted. - * - * @iclass - */ - msg_t postAheadI(T msg) { - - return chMBPostAheadI(&mb, reinterpret_cast(msg)); - } - - /** - * @brief Retrieves a message from a mailbox. - * @details The invoking thread waits until a message is posted in the - * mailbox or the specified time runs out. - * - * @param[out] msgp pointer to a message variable for the received - * @param[in] time message the number of ticks before the operation - * timeouts, the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval MSG_OK if a message has been correctly fetched. - * @retval MSG_RESET if the mailbox has been reset while waiting. - * @retval MSG_TIMEOUT if the operation has timed out. - * - * @api - */ - msg_t fetch(T *msgp, systime_t time) { - - return chMBFetch(&mb, reinterpret_cast(msgp), time); - } - - /** - * @brief Retrieves a message from a mailbox. - * @details The invoking thread waits until a message is posted in the - * mailbox or the specified time runs out. - * - * @param[out] msgp pointer to a message variable for the received - * @param[in] time message the number of ticks before the operation - * timeouts, the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval MSG_OK if a message has been correctly fetched. - * @retval MSG_RESET if the mailbox has been reset while waiting. - * @retval MSG_TIMEOUT if the operation has timed out. - * - * @sclass - */ - msg_t fetchS(T *msgp, systime_t time) { - - return chMBFetchS(&mb, reinterpret_cast(msgp), time); - } - - /** - * @brief Retrieves a message from a mailbox. - * @details This variant is non-blocking, the function returns a timeout - * condition if the queue is empty. - * - * @param[out] msgp pointer to a message variable for the received - * message - * @return The operation status. - * @retval MSG_OK if a message has been correctly fetched. - * @retval MSG_TIMEOUT if the mailbox is empty and a message cannot be - * fetched. - * - * @iclass - */ - msg_t fetchI(T *msgp) { - - return chMBFetchI(&mb, reinterpret_cast(msgp)); - } - - /** - * @brief Returns the number of free message slots into a mailbox. - * @note Can be invoked in any system state but if invoked out of a - * locked state then the returned value may change after reading. - * @note The returned value can be less than zero when there are waiting - * threads on the internal semaphore. - * - * @return The number of empty message slots. - * - * @iclass - */ - cnt_t getFreeCountI(void) { - - return chMBGetFreeCountI(&mb); - } - - /** - * @brief Returns the number of used message slots into a mailbox. - * @note Can be invoked in any system state but if invoked out of a - * locked state then the returned value may change after reading. - * @note The returned value can be less than zero when there are waiting - * threads on the internal semaphore. - * - * @return The number of queued messages. - * - * @iclass - */ - cnt_t getUsedCountI(void) { - - return chMBGetUsedCountI(&mb); - } - }; - - /*------------------------------------------------------------------------* - * chibios_rt::Mailbox * - *------------------------------------------------------------------------*/ - /** - * @brief Template class encapsulating a mailbox and its messages buffer. - * - * @param N length of the mailbox buffer - */ - template - class Mailbox : public MailboxBase { - private: - msg_t mb_buf[N]; - - public: - /** - * @brief Mailbox constructor. - * - * @init - */ - Mailbox(void) : - MailboxBase(mb_buf, (cnt_t)(sizeof mb_buf / sizeof (msg_t))) { - } - }; -#endif /* CH_CFG_USE_MAILBOXES */ - -#if CH_CFG_USE_MEMPOOLS || defined(__DOXYGEN__) - /*------------------------------------------------------------------------* - * chibios_rt::MemoryPool * - *------------------------------------------------------------------------*/ - /** - * @brief Class encapsulating a mailbox. - */ - class MemoryPool { - public: - /** - * @brief Embedded @p ::MemoryPool structure. - */ - ::memory_pool_t pool; - - /** - * @brief MemoryPool constructor. - * - * @param[in] size the size of the objects contained in this memory - * pool, the minimum accepted size is the size of - * a pointer to void. - * @param[in] provider memory provider function for the memory pool or - * @p NULL if the pool is not allowed to grow - * automatically - * - * @init - */ - MemoryPool(size_t size, memgetfunc_t provider); - - /** - * @brief MemoryPool constructor. - * - * @param[in] size the size of the objects contained in this memory - * pool, the minimum accepted size is the size of - * a pointer to void. - * @param[in] provider memory provider function for the memory pool or - * @p NULL if the pool is not allowed to grow - * automatically - * @param[in] p pointer to the array first element - * @param[in] n number of elements in the array - * - * @init - */ - MemoryPool(size_t size, memgetfunc_t provider, void* p, size_t n); - - /** - * @brief Loads a memory pool with an array of static objects. - * @pre The memory pool must be already been initialized. - * @pre The array elements must be of the right size for the specified - * memory pool. - * @post The memory pool contains the elements of the input array. - * - * @param[in] p pointer to the array first element - * @param[in] n number of elements in the array - * - * @api - */ - void loadArray(void *p, size_t n); - - /** - * @brief Allocates an object from a memory pool. - * @pre The memory pool must be already been initialized. - * - * @return The pointer to the allocated object. - * @retval NULL if pool is empty. - * - * @iclass - */ - void *allocI(void); - - /** - * @brief Allocates an object from a memory pool. - * @pre The memory pool must be already been initialized. - * - * @return The pointer to the allocated object. - * @retval NULL if pool is empty. - * - * @api - */ - void *alloc(void); - - /** - * @brief Releases an object into a memory pool. - * @pre The memory pool must be already been initialized. - * @pre The freed object must be of the right size for the specified - * memory pool. - * @pre The object must be properly aligned to contain a pointer to - * void. - * - * @param[in] objp the pointer to the object to be released - * - * @iclass - */ - void free(void *objp); - - /** - * @brief Adds an object to a memory pool. - * @pre The memory pool must be already been initialized. - * @pre The added object must be of the right size for the specified - * memory pool. - * @pre The added object must be memory aligned to the size of - * @p stkalign_t type. - * @note This function is just an alias for @p chPoolFree() and has been - * added for clarity. - * - * @param[in] objp the pointer to the object to be added - * - * @iclass - */ - void freeI(void *objp); - }; - - /*------------------------------------------------------------------------* - * chibios_rt::ObjectsPool * - *------------------------------------------------------------------------*/ - /** - * @brief Template class encapsulating a memory pool and its elements. - */ - template - class ObjectsPool : public MemoryPool { - private: - /* The buffer is declared as an array of pointers to void for two - reasons: - 1) The objects must be properly aligned to hold a pointer as - first field. - 2) There is no need to invoke constructors for object that are - into the pool.*/ - void *pool_buf[(N * sizeof (T)) / sizeof (void *)]; - - public: - /** - * @brief ObjectsPool constructor. - * - * @init - */ - ObjectsPool(void) : MemoryPool(sizeof (T), NULL) { - - loadArray(pool_buf, N); - } - }; -#endif /* CH_CFG_USE_MEMPOOLS */ - - /*------------------------------------------------------------------------* - * chibios_rt::BaseSequentialStreamInterface * - *------------------------------------------------------------------------*/ - /** - * @brief Interface of a ::BaseSequentialStream. - * @note You can cast a ::BaseSequentialStream to this interface and use - * it, the memory layout is the same. - */ - class BaseSequentialStreamInterface { - public: - /** - * @brief Sequential Stream write. - * @details The function writes data from a buffer to a stream. - * - * @param[in] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred - * @return The number of bytes transferred. The return value - * can be less than the specified number of bytes if - * an end-of-file condition has been met. - * - * @api - */ - virtual size_t write(const uint8_t *bp, size_t n) = 0; - - /** - * @brief Sequential Stream read. - * @details The function reads data from a stream into a buffer. - * - * @param[out] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred - * @return The number of bytes transferred. The return value - * can be less than the specified number of bytes if - * an end-of-file condition has been met. - * - * @api - */ - virtual size_t read(uint8_t *bp, size_t n) = 0; - - /** - * @brief Sequential Stream blocking byte write. - * @details This function writes a byte value to a channel. If the channel - * is not ready to accept data then the calling thread is - * suspended. - * - * @param[in] b the byte value to be written to the channel - * - * @return The operation status. - * @retval Q_OK if the operation succeeded. - * @retval Q_RESET if an end-of-file condition has been met. - * - * @api - */ - virtual msg_t put(uint8_t b) = 0; - - /** - * @brief Sequential Stream blocking byte read. - * @details This function reads a byte value from a channel. If the data - * is not available then the calling thread is suspended. - * - * @return A byte value from the queue. - * @retval Q_RESET if an end-of-file condition has been met. - * - * @api - */ - virtual msg_t get(void) = 0; - }; -} - -#endif /* _CH_HPP_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/various/cpp_wrappers/chcpp.mk b/firmware/ChibiOS_16/os/various/cpp_wrappers/chcpp.mk deleted file mode 100644 index 169c555b86..0000000000 --- a/firmware/ChibiOS_16/os/various/cpp_wrappers/chcpp.mk +++ /dev/null @@ -1,5 +0,0 @@ -# C++ wrapper files. -CHCPPSRC = ${CHIBIOS}/os/various/cpp_wrappers/ch.cpp \ - ${CHIBIOS}/os/various/cpp_wrappers/syscalls_cpp.cpp - -CHCPPINC = ${CHIBIOS}/os/various/cpp_wrappers diff --git a/firmware/ChibiOS_16/os/various/cpp_wrappers/syscalls_cpp.cpp b/firmware/ChibiOS_16/os/various/cpp_wrappers/syscalls_cpp.cpp deleted file mode 100644 index 486461a766..0000000000 --- a/firmware/ChibiOS_16/os/various/cpp_wrappers/syscalls_cpp.cpp +++ /dev/null @@ -1,41 +0,0 @@ -#include -#include - -#include "osal.h" - -#include "syscalls_cpp.hpp" - -#ifdef __cplusplus -extern "C" { -#endif - -void _exit(int status){ - (void) status; - osalSysHalt("Unrealized"); - while(TRUE){} -} - -pid_t _getpid(void){ - return 1; -} - -#undef errno -extern int errno; -int _kill(int pid, int sig) { - (void)pid; - (void)sig; - errno = EINVAL; - return -1; -} - -void _open_r(void){ - return; -} - -void __cxa_pure_virtual() { - osalSysHalt("Pure virtual function call."); -} - -#ifdef __cplusplus -} -#endif diff --git a/firmware/ChibiOS_16/os/various/cpp_wrappers/syscalls_cpp.hpp b/firmware/ChibiOS_16/os/various/cpp_wrappers/syscalls_cpp.hpp deleted file mode 100644 index cd78a9c5d6..0000000000 --- a/firmware/ChibiOS_16/os/various/cpp_wrappers/syscalls_cpp.hpp +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef SYSCALLS_CPP_HPP_ -#define SYSCALLS_CPP_HPP_ - -/* The ABI requires a 32-bit type.*/ -typedef int __guard; - -int __cxa_guard_acquire(__guard *); -void __cxa_guard_release (__guard *); -void __cxa_guard_abort (__guard *); - -void *__dso_handle = NULL; - -#endif /* SYSCALLS_CPP_HPP_ */ diff --git a/firmware/ChibiOS_16/os/various/devices_lib/accel/lis302dl.c b/firmware/ChibiOS_16/os/various/devices_lib/accel/lis302dl.c deleted file mode 100644 index c63047410f..0000000000 --- a/firmware/ChibiOS_16/os/various/devices_lib/accel/lis302dl.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file lis302dl.c - * @brief LIS302DL MEMS interface module through SPI code. - * - * @addtogroup lis302dl - * @{ - */ - -#include "hal.h" -#include "lis302dl.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -static uint8_t txbuf[2]; -static uint8_t rxbuf[2]; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Reads a register value. - * @pre The SPI interface must be initialized and the driver started. - * - * @param[in] spip pointer to the SPI initerface - * @param[in] reg register number - * @return The register value. - */ -uint8_t lis302dlReadRegister(SPIDriver *spip, uint8_t reg) { - - spiSelect(spip); - txbuf[0] = 0x80 | reg; - txbuf[1] = 0xff; - spiExchange(spip, 2, txbuf, rxbuf); - spiUnselect(spip); - return rxbuf[1]; -} - -/** - * @brief Writes a value into a register. - * @pre The SPI interface must be initialized and the driver started. - * - * @param[in] spip pointer to the SPI initerface - * @param[in] reg register number - * @param[in] value the value to be written - */ -void lis302dlWriteRegister(SPIDriver *spip, uint8_t reg, uint8_t value) { - - switch (reg) { - default: - /* Reserved register must not be written, according to the datasheet - this could permanently damage the device.*/ - osalDbgAssert(FALSE, "reserved register"); - case LIS302DL_WHO_AM_I: - case LIS302DL_HP_FILTER_RESET: - case LIS302DL_STATUS_REG: - case LIS302DL_OUTX: - case LIS302DL_OUTY: - case LIS302DL_OUTZ: - case LIS302DL_FF_WU_SRC1: - case LIS302DL_FF_WU_SRC2: - case LIS302DL_CLICK_SRC: - /* Read only registers cannot be written, the command is ignored.*/ - return; - case LIS302DL_CTRL_REG1: - case LIS302DL_CTRL_REG2: - case LIS302DL_CTRL_REG3: - case LIS302DL_FF_WU_CFG1: - case LIS302DL_FF_WU_THS1: - case LIS302DL_FF_WU_DURATION1: - case LIS302DL_FF_WU_CFG2: - case LIS302DL_FF_WU_THS2: - case LIS302DL_FF_WU_DURATION2: - case LIS302DL_CLICK_CFG: - case LIS302DL_CLICK_THSY_X: - case LIS302DL_CLICK_THSZ: - case LIS302DL_CLICK_TIMELIMIT: - case LIS302DL_CLICK_LATENCY: - case LIS302DL_CLICK_WINDOW: - spiSelect(spip); - txbuf[0] = reg; - txbuf[1] = value; - spiSend(spip, 2, txbuf); - spiUnselect(spip); - } -} - -/** @} */ diff --git a/firmware/ChibiOS_16/os/various/devices_lib/accel/lis302dl.dox b/firmware/ChibiOS_16/os/various/devices_lib/accel/lis302dl.dox deleted file mode 100644 index b5b9c5797f..0000000000 --- a/firmware/ChibiOS_16/os/various/devices_lib/accel/lis302dl.dox +++ /dev/null @@ -1,26 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @defgroup lis302dl Interface module for LIS302DL MEMS - * - * @brief Interface module for LIS302DL MEMS. - * @details This module implements a generic interface for the LIS302DL - * STMicroelectronics MEMS device. The communication is performed - * through a standard SPI driver. - * - * @ingroup accel - */ diff --git a/firmware/ChibiOS_16/os/various/devices_lib/accel/lis302dl.h b/firmware/ChibiOS_16/os/various/devices_lib/accel/lis302dl.h deleted file mode 100644 index 036a3472da..0000000000 --- a/firmware/ChibiOS_16/os/various/devices_lib/accel/lis302dl.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file lis302dl.h - * @brief LIS302DL MEMS interface module through SPI header. - * - * @addtogroup lis302dl - * @{ - */ - -#ifndef _LIS302DL_H_ -#define _LIS302DL_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name LIS302DL register names - * @{ - */ -#define LIS302DL_WHO_AM_I 0x0F -#define LIS302DL_CTRL_REG1 0x20 -#define LIS302DL_CTRL_REG2 0x21 -#define LIS302DL_CTRL_REG3 0x22 -#define LIS302DL_HP_FILTER_RESET 0x23 -#define LIS302DL_STATUS_REG 0x27 -#define LIS302DL_OUTX 0x29 -#define LIS302DL_OUTY 0x2B -#define LIS302DL_OUTZ 0x2D -#define LIS302DL_FF_WU_CFG1 0x30 -#define LIS302DL_FF_WU_SRC1 0x31 -#define LIS302DL_FF_WU_THS1 0x32 -#define LIS302DL_FF_WU_DURATION1 0x33 -#define LIS302DL_FF_WU_CFG2 0x34 -#define LIS302DL_FF_WU_SRC2 0x35 -#define LIS302DL_FF_WU_THS2 0x36 -#define LIS302DL_FF_WU_DURATION2 0x37 -#define LIS302DL_CLICK_CFG 0x38 -#define LIS302DL_CLICK_SRC 0x39 -#define LIS302DL_CLICK_THSY_X 0x3B -#define LIS302DL_CLICK_THSZ 0x3C -#define LIS302DL_CLICK_TIMELIMIT 0x3D -#define LIS302DL_CLICK_LATENCY 0x3E -#define LIS302DL_CLICK_WINDOW 0x3F -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - uint8_t lis302dlReadRegister(SPIDriver *spip, uint8_t reg); - void lis302dlWriteRegister(SPIDriver *spip, uint8_t reg, uint8_t value); -#ifdef __cplusplus -} -#endif - -#endif /* _LIS302DL_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/various/devices_lib/lcd/lcd3310.c b/firmware/ChibiOS_16/os/various/devices_lib/lcd/lcd3310.c deleted file mode 100644 index 4c098ca13d..0000000000 --- a/firmware/ChibiOS_16/os/various/devices_lib/lcd/lcd3310.c +++ /dev/null @@ -1,310 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file lcd3310.c - * @brief Nokia 3310 LCD interface module through SPI code. - * - * @addtogroup lcd3310 - * @{ - */ - -#include "ch.h" -#include "hal.h" -#include "lcd3310.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -const uint8_t Fonts8x5 [][LCD3310_FONT_X_SIZE] = -{ - { 0x00, 0x00, 0x00, 0x00, 0x00 }, /* space */ - { 0x00, 0x00, 0x2f, 0x00, 0x00 }, /* ! */ - { 0x00, 0x07, 0x00, 0x07, 0x00 }, /* " */ - { 0x14, 0x7f, 0x14, 0x7f, 0x14 }, /* # */ - { 0x24, 0x2a, 0x7f, 0x2a, 0x12 }, /* $ */ - { 0xc4, 0xc8, 0x10, 0x26, 0x46 }, /* % */ - { 0x36, 0x49, 0x55, 0x22, 0x50 }, /* & */ - { 0x00, 0x05, 0x03, 0x00, 0x00 }, /* ' */ - { 0x00, 0x1c, 0x22, 0x41, 0x00 }, /* ( */ - { 0x00, 0x41, 0x22, 0x1c, 0x00 }, /* ) */ - { 0x14, 0x08, 0x3E, 0x08, 0x14 }, /* * */ - { 0x08, 0x08, 0x3E, 0x08, 0x08 }, /* + */ - { 0x00, 0x00, 0x50, 0x30, 0x00 }, /* , */ - { 0x10, 0x10, 0x10, 0x10, 0x10 }, /* - */ - { 0x00, 0x60, 0x60, 0x00, 0x00 }, /* . */ - { 0x20, 0x10, 0x08, 0x04, 0x02 }, /* / */ - { 0x3E, 0x51, 0x49, 0x45, 0x3E }, /* 0 */ - { 0x00, 0x42, 0x7F, 0x40, 0x00 }, /* 1 */ - { 0x42, 0x61, 0x51, 0x49, 0x46 }, /* 2 */ - { 0x21, 0x41, 0x45, 0x4B, 0x31 }, /* 3 */ - { 0x18, 0x14, 0x12, 0x7F, 0x10 }, /* 4 */ - { 0x27, 0x45, 0x45, 0x45, 0x39 }, /* 5 */ - { 0x3C, 0x4A, 0x49, 0x49, 0x30 }, /* 6 */ - { 0x01, 0x71, 0x09, 0x05, 0x03 }, /* 7 */ - { 0x36, 0x49, 0x49, 0x49, 0x36 }, /* 8 */ - { 0x06, 0x49, 0x49, 0x29, 0x1E }, /* 9 */ - { 0x00, 0x36, 0x36, 0x00, 0x00 }, /* : */ - { 0x00, 0x56, 0x36, 0x00, 0x00 }, /* ; */ - { 0x08, 0x14, 0x22, 0x41, 0x00 }, /* < */ - { 0x14, 0x14, 0x14, 0x14, 0x14 }, /* = */ - { 0x00, 0x41, 0x22, 0x14, 0x08 }, /* > */ - { 0x02, 0x01, 0x51, 0x09, 0x06 }, /* ? */ - { 0x32, 0x49, 0x59, 0x51, 0x3E }, /* @ */ - { 0x7E, 0x11, 0x11, 0x11, 0x7E }, /* A */ - { 0x7F, 0x49, 0x49, 0x49, 0x36 }, /* B */ - { 0x3E, 0x41, 0x41, 0x41, 0x22 }, /* C */ - { 0x7F, 0x41, 0x41, 0x22, 0x1C }, /* D */ - { 0x7F, 0x49, 0x49, 0x49, 0x41 }, /* E */ - { 0x7F, 0x09, 0x09, 0x09, 0x01 }, /* F */ - { 0x3E, 0x41, 0x49, 0x49, 0x7A }, /* G */ - { 0x7F, 0x08, 0x08, 0x08, 0x7F }, /* H */ - { 0x00, 0x41, 0x7F, 0x41, 0x00 }, /* I */ - { 0x20, 0x40, 0x41, 0x3F, 0x01 }, /* J */ - { 0x7F, 0x08, 0x14, 0x22, 0x41 }, /* K */ - { 0x7F, 0x40, 0x40, 0x40, 0x40 }, /* L */ - { 0x7F, 0x02, 0x0C, 0x02, 0x7F }, /* M */ - { 0x7F, 0x04, 0x08, 0x10, 0x7F }, /* N */ - { 0x3E, 0x41, 0x41, 0x41, 0x3E }, /* O */ - { 0x7F, 0x09, 0x09, 0x09, 0x06 }, /* P */ - { 0x3E, 0x41, 0x51, 0x21, 0x5E }, /* Q */ - { 0x7F, 0x09, 0x19, 0x29, 0x46 }, /* R */ - { 0x46, 0x49, 0x49, 0x49, 0x31 }, /* S */ - { 0x01, 0x01, 0x7F, 0x01, 0x01 }, /* T */ - { 0x3F, 0x40, 0x40, 0x40, 0x3F }, /* U */ - { 0x1F, 0x20, 0x40, 0x20, 0x1F }, /* V */ - { 0x3F, 0x40, 0x38, 0x40, 0x3F }, /* W */ - { 0x63, 0x14, 0x08, 0x14, 0x63 }, /* X */ - { 0x07, 0x08, 0x70, 0x08, 0x07 }, /* Y */ - { 0x61, 0x51, 0x49, 0x45, 0x43 }, /* Z */ - { 0x00, 0x7F, 0x41, 0x41, 0x00 }, /* [ */ - { 0x55, 0x2A, 0x55, 0x2A, 0x55 }, /* \ */ - { 0x00, 0x41, 0x41, 0x7F, 0x00 }, /* ] */ - { 0x04, 0x02, 0x01, 0x02, 0x04 }, /* ^ */ - { 0x40, 0x40, 0x40, 0x40, 0x40 }, /* _ */ - { 0x00, 0x01, 0x02, 0x04, 0x00 }, /* ' */ - { 0x20, 0x54, 0x54, 0x54, 0x78 }, /* a */ - { 0x7F, 0x48, 0x44, 0x44, 0x38 }, /* b */ - { 0x38, 0x44, 0x44, 0x44, 0x20 }, /* c */ - { 0x38, 0x44, 0x44, 0x48, 0x7F }, /* d */ - { 0x38, 0x54, 0x54, 0x54, 0x18 }, /* e */ - { 0x08, 0x7E, 0x09, 0x01, 0x02 }, /* f */ - { 0x0C, 0x52, 0x52, 0x52, 0x3E }, /* g */ - { 0x7F, 0x08, 0x04, 0x04, 0x78 }, /* h */ - { 0x00, 0x44, 0x7D, 0x40, 0x00 }, /* i */ - { 0x20, 0x40, 0x44, 0x3D, 0x00 }, /* j */ - { 0x7F, 0x10, 0x28, 0x44, 0x00 }, /* k */ - { 0x00, 0x41, 0x7F, 0x40, 0x00 }, /* l */ - { 0x7C, 0x04, 0x18, 0x04, 0x78 }, /* m */ - { 0x7C, 0x08, 0x04, 0x04, 0x78 }, /* n */ - { 0x38, 0x44, 0x44, 0x44, 0x38 }, /* o */ - { 0x7C, 0x14, 0x14, 0x14, 0x08 }, /* p */ - { 0x08, 0x14, 0x14, 0x18, 0x7C }, /* q */ - { 0x7C, 0x08, 0x04, 0x04, 0x08 }, /* r */ - { 0x48, 0x54, 0x54, 0x54, 0x20 }, /* s */ - { 0x04, 0x3F, 0x44, 0x40, 0x20 }, /* t */ - { 0x3C, 0x40, 0x40, 0x20, 0x7C }, /* u */ - { 0x1C, 0x20, 0x40, 0x20, 0x1C }, /* v */ - { 0x3C, 0x40, 0x30, 0x40, 0x3C }, /* w */ - { 0x44, 0x28, 0x10, 0x28, 0x44 }, /* x */ - { 0x0C, 0x50, 0x50, 0x50, 0x3C }, /* y */ - { 0x44, 0x64, 0x54, 0x4C, 0x44 }, /* z */ - { 0x00, 0x08, 0x36, 0x41, 0x00 }, /* { */ - { 0x00, 0x00, 0x7F, 0x00, 0x00 }, /* | */ - { 0x00, 0x41, 0x36, 0x08, 0x00 }, /* } */ -}; - - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief LCD driver initialization. - * @pre The SPI interface must be initialized and the driver started. - * - * @param[in] spip pointer to the SPI interface - * - */ -void lcd3310Init(SPIDriver *spip) { - - /* Reset LCD */ - palClearPad(LCD3310_RES_PORT, LCD3310_RES_PIN); - chThdSleepMilliseconds(15); - palSetPad(LCD3310_RES_PORT, LCD3310_RES_PIN); - chThdSleepMilliseconds(15); - - /* Send configuration commands to LCD */ - lcd3310WriteByte(spip, 0x21, LCD3310_SEND_CMD); /* LCD extended commands */ - lcd3310WriteByte(spip, 0xC8, LCD3310_SEND_CMD); /* Set LCD Vop (Contrast) */ - lcd3310WriteByte(spip, 0x05, LCD3310_SEND_CMD); /* Set start line S6 to 1 TLS8204 */ - lcd3310WriteByte(spip, 0x40, LCD3310_SEND_CMD); /* Set start line S[5:0] to 0x00 TLS8204 */ - lcd3310WriteByte(spip, 0x12, LCD3310_SEND_CMD); /* LCD bias mode 1:68. */ - lcd3310WriteByte(spip, 0x20, LCD3310_SEND_CMD); /* LCD standard Commands, horizontal addressing mode. */ - lcd3310WriteByte(spip, 0x08, LCD3310_SEND_CMD); /* LCD blank */ - lcd3310WriteByte(spip, 0x0C, LCD3310_SEND_CMD); /* LCD in normal mode. */ - - lcd3310Clear(spip); /* Clear LCD */ -} - -/** - * @brief Write byte to LCD driver. - * @pre The LCD driver must be initialized. - * - * @param[in] spip pointer to the SPI interface - * @param[in] data data to write - * @param[in] cd select between command or data - */ -void lcd3310WriteByte(SPIDriver *spip, uint8_t data, uint8_t cd) { - - spiSelect(spip); - - if(cd == LCD3310_SEND_DATA) { - palSetPad(LCD3310_DC_PORT, LCD3310_DC_PIN); - } - else { - palClearPad(LCD3310_DC_PORT, LCD3310_DC_PIN); - } - - spiSend(spip, 1, &data); // change to normal spi send - spiUnselect(spip); -} - -/** - * @brief Clear LCD - * @pre The LCD driver must be initialized. - * - * @param[in] spip pointer to the SPI interface - */ -void lcd3310Clear(SPIDriver *spip) { // ok - - uint32_t i, j; - - for (i = 0; i < LCD3310_Y_RES/LCD3310_FONT_Y_SIZE; i++) { - lcd3310SetPosXY(spip, 0, i); - for (j = 0; j < LCD3310_X_RES; j++) - lcd3310WriteByte(spip, 0x00, LCD3310_SEND_DATA); - } - -} - -/** - * @brief Set position - * @pre The LCD driver must be initialized. - * - * @param[in] spip pointer to the SPI interface - * @param[in] x column address in LCD DDRAM, 0 to 83 - * @param[in] y page address in LCD DDRAM, 0 to 5 - */ -void lcd3310SetPosXY(SPIDriver *spip, uint8_t x, uint8_t y) { - - if (y > LCD3310_Y_RES/LCD3310_FONT_Y_SIZE) return; - if (x > LCD3310_X_RES) return; - - lcd3310WriteByte(spip, 0x80 | x, LCD3310_SEND_CMD); /* Set x position */ - lcd3310WriteByte(spip, 0x40 | y, LCD3310_SEND_CMD); /* Set y position */ - -} - -/** - * @brief Write char - * @pre The LCD driver must be initialized. - * - * @param[in] spip pointer to the SPI interface - * @param[in] ch char - */ -void lcd3310WriteChar(SPIDriver *spip, uint8_t ch) { - - uint8_t i; - - for ( i = 0; i < LCD3310_FONT_X_SIZE; i++ ){ - lcd3310WriteByte(spip, Fonts8x5[ch - 32][i], LCD3310_SEND_DATA); - } - -} - -/** - * @brief Set LCD contrast. - * @pre The LCD driver must be initialized. - * - * @param[in] spip pointer to the SPI interface - * @param[in] contrast LCD contrast value - */ -void lcd3310Contrast (SPIDriver *spip, uint8_t contrast) { - - lcd3310WriteByte(spip, 0x21, LCD3310_SEND_CMD); /* LCD Extended Commands */ - lcd3310WriteByte(spip, 0x80 | contrast, LCD3310_SEND_CMD); /* Set LCD Vop (Contrast) */ - lcd3310WriteByte(spip, 0x20, LCD3310_SEND_CMD); /* LCD Standard Commands, horizontal addressing mode */ -} - - -/** - * @brief Write text - * @pre The LCD driver must be initialized. - * - * @param[in] spip pointer to the SPI interface - * @param[in] strp pointer to text - */ -void lcd3310WriteText(SPIDriver *spip, const uint8_t * strp) { - - while ( *strp ) { - lcd3310WriteChar(spip, *strp); - strp++; - } -} - -/** - * @brief Rotate text - * @pre The LCD driver must be initialized. - * - * @param[in] spip pointer to the SPI interface - * @param[in] strp pointer to text - * @param[in] offset text offset - */ -void lcd3310RotateText(SPIDriver *spip, const uint8_t * strp, uint8_t offset) { - - uint8_t i; - uint8_t n; - uint8_t m; - - for(n = 0; strp[n] != '\0'; n++); /* Count number of char */ - - if (offset >= n) - return; - - for (i = 0; i < LCD3310_X_RES/LCD3310_FONT_X_SIZE; i++) { - m = i + offset; - if ( m < n) - lcd3310WriteChar(spip, strp[m]); - else - lcd3310WriteChar(spip, strp[m - n]); - } -} - -/** @} */ diff --git a/firmware/ChibiOS_16/os/various/devices_lib/lcd/lcd3310.h b/firmware/ChibiOS_16/os/various/devices_lib/lcd/lcd3310.h deleted file mode 100644 index 8d1733d301..0000000000 --- a/firmware/ChibiOS_16/os/various/devices_lib/lcd/lcd3310.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file lcd3310.h - * @brief Nokia 3310 LCD interface module through SPI code. - * - * @addtogroup lcd3310 - * @{ - */ - -#ifndef _LCD3310_H_ -#define _LCD3310_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#define LCD3310_X_RES 84 -#define LCD3310_Y_RES 48 - -#define LCD3310_FONT_X_SIZE 5 -#define LCD3310_FONT_Y_SIZE 8 - -#define LCD3310_SEND_CMD 0 -#define LCD3310_SEND_DATA 1 - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !defined(LCD3310_RES_PIN) -#error "LCD3310_RES_PIN not defined!!!" -#endif - -#if !defined(LCD3310_RES_PORT) -#error "LCD3310_RES_PORT not defined!!!" -#endif - -#if !defined(LCD3310_DC_PIN) -#error "LCD3310_DC_PIN not defined!!!" -#endif - -#if!defined(LCD3310_DC_PORT) -#error "LCD3310_DC_PORT not defined!!!" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void lcd3310Init(SPIDriver *spip); - void lcd3310WriteByte(SPIDriver *spip, uint8_t data, uint8_t cd); - void lcd3310Contrast(SPIDriver *spip, uint8_t contrast); - void lcd3310Clear(SPIDriver *spip); - void lcd3310SetPosXY(SPIDriver *spip, uint8_t x, uint8_t y); - void lcd3310WriteChar (SPIDriver *spip, uint8_t ch); - void lcd3310WriteText(SPIDriver *spip, const uint8_t * strp); - void lcd3310RotateText(SPIDriver *spip, const uint8_t * strp, uint8_t offset); -#ifdef __cplusplus -} -#endif - -#endif /* _LCD3310_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/various/evtimer.c b/firmware/ChibiOS_16/os/various/evtimer.c deleted file mode 100644 index 03162f958f..0000000000 --- a/firmware/ChibiOS_16/os/various/evtimer.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file evtimer.c - * @brief Events Generator Timer code. - * - * @addtogroup event_timer - * @{ - */ - -#include "ch.h" -#include "evtimer.h" - -/*===========================================================================*/ -/* Module local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module local functions. */ -/*===========================================================================*/ - -static void tmrcb(void *p) { - event_timer_t *etp = p; - - chSysLockFromISR(); - chEvtBroadcastI(&etp->et_es); - chVTDoSetI(&etp->et_vt, etp->et_interval, tmrcb, etp); - chSysUnlockFromISR(); -} - -/*===========================================================================*/ -/* Module exported functions. */ -/*===========================================================================*/ - -/** - * @brief Initializes an @p event_timer_t structure. - * - * @param[out] etp the @p event_timer_t structure to be initialized - * @param[in] time the interval in system ticks - */ -void evtObjectInit(event_timer_t *etp, systime_t time) { - - chEvtObjectInit(&etp->et_es); - chVTObjectInit(&etp->et_vt); - etp->et_interval = time; -} - -/** - * @brief Starts the timer - * @details If the timer was already running then the function has no effect. - * - * @param[in] etp pointer to an initialized @p event_timer_t structure. - */ -void evtStart(event_timer_t *etp) { - - chVTSet(&etp->et_vt, etp->et_interval, tmrcb, etp); -} - -/** @} */ diff --git a/firmware/ChibiOS_16/os/various/evtimer.h b/firmware/ChibiOS_16/os/various/evtimer.h deleted file mode 100644 index bc62640fcf..0000000000 --- a/firmware/ChibiOS_16/os/various/evtimer.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file evtimer.h - * @brief Events Generator Timer structures and macros. - * - * @addtogroup event_timer - * @{ - */ - -#ifndef _EVTIMER_H_ -#define _EVTIMER_H_ - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/* - * Module dependencies check. - */ -#if !CH_CFG_USE_EVENTS -#error "Event Timers require CH_CFG_USE_EVENTS" -#endif - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a event timer structure. - */ -typedef struct { - virtual_timer_t et_vt; - event_source_t et_es; - systime_t et_interval; -} event_timer_t; - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void evtObjectInit(event_timer_t *etp, systime_t time); - void evtStart(event_timer_t *etp); -#ifdef __cplusplus -} -#endif - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -/** - * @brief Stops the timer. - * @details If the timer was already stopped then the function has no effect. - * - * @param[in] etp pointer to an initialized @p event_timer_t structure. - */ -static inline void vevtStop(event_timer_t *etp) { - - chVTReset(&etp->et_vt); -} - -#endif /* _EVTIMER_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/various/fatfs_bindings/fatfs.mk b/firmware/ChibiOS_16/os/various/fatfs_bindings/fatfs.mk deleted file mode 100644 index 5fbd2e9c10..0000000000 --- a/firmware/ChibiOS_16/os/various/fatfs_bindings/fatfs.mk +++ /dev/null @@ -1,7 +0,0 @@ -# FATFS files. -FATFSSRC = ${CHIBIOS}/os/various/fatfs_bindings/fatfs_diskio.c \ - ${CHIBIOS}/os/various/fatfs_bindings/fatfs_syscall.c \ - ${CHIBIOS}/ext/fatfs/src/ff.c \ - ${CHIBIOS}/ext/fatfs/src/option/unicode.c - -FATFSINC = ${CHIBIOS}/ext/fatfs/src diff --git a/firmware/ChibiOS_16/os/various/fatfs_bindings/fatfs_diskio.c b/firmware/ChibiOS_16/os/various/fatfs_bindings/fatfs_diskio.c deleted file mode 100644 index 122b33374b..0000000000 --- a/firmware/ChibiOS_16/os/various/fatfs_bindings/fatfs_diskio.c +++ /dev/null @@ -1,254 +0,0 @@ -/*-----------------------------------------------------------------------*/ -/* Low level disk I/O module skeleton for FatFs (C)ChaN, 2007 */ -/*-----------------------------------------------------------------------*/ -/* This is a stub disk I/O module that acts as front end of the existing */ -/* disk I/O modules and attach it to FatFs module with common interface. */ -/*-----------------------------------------------------------------------*/ - -#include "hal.h" -#include "ffconf.h" -#include "diskio.h" - -#if HAL_USE_MMC_SPI && HAL_USE_SDC -#error "cannot specify both MMC_SPI and SDC drivers" -#endif - -#if HAL_USE_MMC_SPI -extern MMCDriver MMCD1; -#elif HAL_USE_SDC -extern SDCDriver SDCD1; -#else -#error "MMC_SPI or SDC driver must be specified" -#endif - -#if HAL_USE_RTC -extern RTCDriver RTCD1; -#endif - -/*-----------------------------------------------------------------------*/ -/* Correspondence between physical drive number and physical drive. */ - -#define MMC 0 -#define SDC 0 - - - -/*-----------------------------------------------------------------------*/ -/* Inidialize a Drive */ - -DSTATUS disk_initialize ( - BYTE pdrv /* Physical drive nmuber (0..) */ -) -{ - DSTATUS stat; - - switch (pdrv) { -#if HAL_USE_MMC_SPI - case MMC: - stat = 0; - /* It is initialized externally, just reads the status.*/ - if (blkGetDriverState(&MMCD1) != BLK_READY) - stat |= STA_NOINIT; - if (mmcIsWriteProtected(&MMCD1)) - stat |= STA_PROTECT; - return stat; -#else - case SDC: - stat = 0; - /* It is initialized externally, just reads the status.*/ - if (blkGetDriverState(&SDCD1) != BLK_READY) - stat |= STA_NOINIT; - if (sdcIsWriteProtected(&SDCD1)) - stat |= STA_PROTECT; - return stat; -#endif - } - return STA_NOINIT; -} - - - -/*-----------------------------------------------------------------------*/ -/* Return Disk Status */ - -DSTATUS disk_status ( - BYTE pdrv /* Physical drive nmuber (0..) */ -) -{ - DSTATUS stat; - - switch (pdrv) { -#if HAL_USE_MMC_SPI - case MMC: - stat = 0; - /* It is initialized externally, just reads the status.*/ - if (blkGetDriverState(&MMCD1) != BLK_READY) - stat |= STA_NOINIT; - if (mmcIsWriteProtected(&MMCD1)) - stat |= STA_PROTECT; - return stat; -#else - case SDC: - stat = 0; - /* It is initialized externally, just reads the status.*/ - if (blkGetDriverState(&SDCD1) != BLK_READY) - stat |= STA_NOINIT; - if (sdcIsWriteProtected(&SDCD1)) - stat |= STA_PROTECT; - return stat; -#endif - } - return STA_NOINIT; -} - - - -/*-----------------------------------------------------------------------*/ -/* Read Sector(s) */ - -DRESULT disk_read ( - BYTE pdrv, /* Physical drive nmuber (0..) */ - BYTE *buff, /* Data buffer to store read data */ - DWORD sector, /* Sector address (LBA) */ - UINT count /* Number of sectors to read (1..255) */ -) -{ - switch (pdrv) { -#if HAL_USE_MMC_SPI - case MMC: - if (blkGetDriverState(&MMCD1) != BLK_READY) - return RES_NOTRDY; - if (mmcStartSequentialRead(&MMCD1, sector)) - return RES_ERROR; - while (count > 0) { - if (mmcSequentialRead(&MMCD1, buff)) - return RES_ERROR; - buff += MMCSD_BLOCK_SIZE; - count--; - } - if (mmcStopSequentialRead(&MMCD1)) - return RES_ERROR; - return RES_OK; -#else - case SDC: - if (blkGetDriverState(&SDCD1) != BLK_READY) - return RES_NOTRDY; - if (sdcRead(&SDCD1, sector, buff, count)) - return RES_ERROR; - return RES_OK; -#endif - } - return RES_PARERR; -} - - - -/*-----------------------------------------------------------------------*/ -/* Write Sector(s) */ - -#if _USE_WRITE -DRESULT disk_write ( - BYTE pdrv, /* Physical drive nmuber (0..) */ - const BYTE *buff, /* Data to be written */ - DWORD sector, /* Sector address (LBA) */ - UINT count /* Number of sectors to write (1..255) */ -) -{ - switch (pdrv) { -#if HAL_USE_MMC_SPI - case MMC: - if (blkGetDriverState(&MMCD1) != BLK_READY) - return RES_NOTRDY; - if (mmcIsWriteProtected(&MMCD1)) - return RES_WRPRT; - if (mmcStartSequentialWrite(&MMCD1, sector)) - return RES_ERROR; - while (count > 0) { - if (mmcSequentialWrite(&MMCD1, buff)) - return RES_ERROR; - buff += MMCSD_BLOCK_SIZE; - count--; - } - if (mmcStopSequentialWrite(&MMCD1)) - return RES_ERROR; - return RES_OK; -#else - case SDC: - if (blkGetDriverState(&SDCD1) != BLK_READY) - return RES_NOTRDY; - if (sdcWrite(&SDCD1, sector, buff, count)) - return RES_ERROR; - return RES_OK; -#endif - } - return RES_PARERR; -} -#endif /* _USE_WRITE */ - - - -/*-----------------------------------------------------------------------*/ -/* Miscellaneous Functions */ - -#if _USE_IOCTL -DRESULT disk_ioctl ( - BYTE pdrv, /* Physical drive nmuber (0..) */ - BYTE cmd, /* Control code */ - void *buff /* Buffer to send/receive control data */ -) -{ - switch (pdrv) { -#if HAL_USE_MMC_SPI - case MMC: - switch (cmd) { - case CTRL_SYNC: - return RES_OK; - case GET_SECTOR_SIZE: - *((WORD *)buff) = MMCSD_BLOCK_SIZE; - return RES_OK; -#if _USE_ERASE - case CTRL_ERASE_SECTOR: - mmcErase(&MMCD1, *((DWORD *)buff), *((DWORD *)buff + 1)); - return RES_OK; -#endif - default: - return RES_PARERR; - } -#else - case SDC: - switch (cmd) { - case CTRL_SYNC: - return RES_OK; - case GET_SECTOR_COUNT: - *((DWORD *)buff) = mmcsdGetCardCapacity(&SDCD1); - return RES_OK; - case GET_SECTOR_SIZE: - *((WORD *)buff) = MMCSD_BLOCK_SIZE; - return RES_OK; - case GET_BLOCK_SIZE: - *((DWORD *)buff) = 256; /* 512b blocks in one erase block */ - return RES_OK; -#if _USE_ERASE - case CTRL_ERASE_SECTOR: - sdcErase(&SDCD1, *((DWORD *)buff), *((DWORD *)buff + 1)); - return RES_OK; -#endif - default: - return RES_PARERR; - } -#endif - } - return RES_PARERR; -} -#endif /* _USE_IOCTL */ - -DWORD get_fattime(void) { -#if HAL_USE_RTC - RTCDateTime timespec; - - rtcGetTime(&RTCD1, ×pec); - return rtcConvertDateTimeToFAT(×pec); -#else - return ((uint32_t)0 | (1 << 16)) | (1 << 21); /* wrong but valid time */ -#endif -} diff --git a/firmware/ChibiOS_16/os/various/fatfs_bindings/fatfs_syscall.c b/firmware/ChibiOS_16/os/various/fatfs_bindings/fatfs_syscall.c deleted file mode 100644 index d8022e273d..0000000000 --- a/firmware/ChibiOS_16/os/various/fatfs_bindings/fatfs_syscall.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/*------------------------------------------------------------------------*/ -/* Sample code of OS dependent controls for FatFs R0.08b */ -/* (C)ChaN, 2011 */ -/*------------------------------------------------------------------------*/ - -#include "hal.h" -#include "ff.h" - -#if _FS_REENTRANT -/*------------------------------------------------------------------------*/ -/* Static array of Synchronization Objects */ -/*------------------------------------------------------------------------*/ -static semaphore_t ff_sem[_VOLUMES]; - -/*------------------------------------------------------------------------*/ -/* Create a Synchronization Object */ -/*------------------------------------------------------------------------*/ -int ff_cre_syncobj(BYTE vol, _SYNC_t *sobj) { - - *sobj = &ff_sem[vol]; - chSemObjectInit(*sobj, 1); - return TRUE; -} - -/*------------------------------------------------------------------------*/ -/* Delete a Synchronization Object */ -/*------------------------------------------------------------------------*/ -int ff_del_syncobj(_SYNC_t sobj) { - - chSemReset(sobj, 0); - return TRUE; -} - -/*------------------------------------------------------------------------*/ -/* Request Grant to Access the Volume */ -/*------------------------------------------------------------------------*/ -int ff_req_grant(_SYNC_t sobj) { - - msg_t msg = chSemWaitTimeout(sobj, (systime_t)_FS_TIMEOUT); - return msg == MSG_OK; -} - -/*------------------------------------------------------------------------*/ -/* Release Grant to Access the Volume */ -/*------------------------------------------------------------------------*/ -void ff_rel_grant(_SYNC_t sobj) { - - chSemSignal(sobj); -} -#endif /* _FS_REENTRANT */ - -#if _USE_LFN == 3 /* LFN with a working buffer on the heap */ -/*------------------------------------------------------------------------*/ -/* Allocate a memory block */ -/*------------------------------------------------------------------------*/ -void *ff_memalloc(UINT size) { - - return chHeapAlloc(NULL, size); -} - -/*------------------------------------------------------------------------*/ -/* Free a memory block */ -/*------------------------------------------------------------------------*/ -void ff_memfree(void *mblock) { - - chHeapFree(mblock); -} -#endif /* _USE_LFN == 3 */ diff --git a/firmware/ChibiOS_16/os/various/fatfs_bindings/readme.txt b/firmware/ChibiOS_16/os/various/fatfs_bindings/readme.txt deleted file mode 100644 index ef546e5aee..0000000000 --- a/firmware/ChibiOS_16/os/various/fatfs_bindings/readme.txt +++ /dev/null @@ -1,6 +0,0 @@ -This directory contains the ChibiOS/RT "official" bindings with the FatFS -library by ChaN: http://elm-chan.org - -In order to use FatFS within ChibiOS/RT project, unzip FatFS under -./ext/fatfs then include $(CHIBIOS)/os/various/fatfs_bindings/fatfs.mk -in your makefile. diff --git a/firmware/ChibiOS_16/os/various/lwip_bindings/arch/cc.h b/firmware/ChibiOS_16/os/various/lwip_bindings/arch/cc.h deleted file mode 100644 index c00400665d..0000000000 --- a/firmware/ChibiOS_16/os/various/lwip_bindings/arch/cc.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - * **** This file incorporates work covered by the following copyright and **** - * **** permission notice: **** - * - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#ifndef __CC_H__ -#define __CC_H__ - -#include - -typedef uint8_t u8_t; -typedef int8_t s8_t; -typedef uint16_t u16_t; -typedef int16_t s16_t; -typedef uint32_t u32_t; -typedef int32_t s32_t; -typedef uint32_t mem_ptr_t; - -#define PACK_STRUCT_STRUCT __attribute__((packed)) - -#define LWIP_PLATFORM_DIAG(x) -#define LWIP_PLATFORM_ASSERT(x) { \ - osalSysHalt(x); \ -} - -#ifndef BYTE_ORDER -#define BYTE_ORDER LITTLE_ENDIAN -#endif - -#define LWIP_PROVIDE_ERRNO - -#endif /* __CC_H__ */ diff --git a/firmware/ChibiOS_16/os/various/lwip_bindings/arch/perf.h b/firmware/ChibiOS_16/os/various/lwip_bindings/arch/perf.h deleted file mode 100644 index 84ed8bd2aa..0000000000 --- a/firmware/ChibiOS_16/os/various/lwip_bindings/arch/perf.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - * **** This file incorporates work covered by the following copyright and **** - * **** permission notice: **** - * - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#ifndef __PERF_H__ -#define __PERF_H__ - -#define PERF_START -#define PERF_STOP(x) - -#endif /* __PERF_H__ */ diff --git a/firmware/ChibiOS_16/os/various/lwip_bindings/arch/sys_arch.c b/firmware/ChibiOS_16/os/various/lwip_bindings/arch/sys_arch.c deleted file mode 100644 index f8a8e5899f..0000000000 --- a/firmware/ChibiOS_16/os/various/lwip_bindings/arch/sys_arch.c +++ /dev/null @@ -1,257 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - * **** This file incorporates work covered by the following copyright and **** - * **** permission notice: **** - * - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -// see http://lwip.wikia.com/wiki/Porting_for_an_OS for instructions - -#include "hal.h" - -#include "lwip/opt.h" -#include "lwip/mem.h" -#include "lwip/sys.h" -#include "lwip/stats.h" - -#include "arch/cc.h" -#include "arch/sys_arch.h" - -void sys_init(void) { - -} - -err_t sys_sem_new(sys_sem_t *sem, u8_t count) { - - *sem = chHeapAlloc(NULL, sizeof(semaphore_t)); - if (*sem == 0) { - SYS_STATS_INC(sem.err); - return ERR_MEM; - } - else { - chSemObjectInit(*sem, (cnt_t)count); - SYS_STATS_INC_USED(sem); - return ERR_OK; - } -} - -void sys_sem_free(sys_sem_t *sem) { - - chHeapFree(*sem); - *sem = SYS_SEM_NULL; - SYS_STATS_DEC(sem.used); -} - -void sys_sem_signal(sys_sem_t *sem) { - - chSemSignal(*sem); -} - -/* CHIBIOS FIX: specific variant of this call to be called from within - a lock.*/ -void sys_sem_signal_S(sys_sem_t *sem) { - - chSemSignalI(*sem); - chSchRescheduleS(); -} - -u32_t sys_arch_sem_wait(sys_sem_t *sem, u32_t timeout) { - systime_t tmo, start, remaining; - - osalSysLock(); - tmo = timeout > 0 ? MS2ST((systime_t)timeout) : TIME_INFINITE; - start = osalOsGetSystemTimeX(); - if (chSemWaitTimeoutS(*sem, tmo) != MSG_OK) { - osalSysUnlock(); - return SYS_ARCH_TIMEOUT; - } - remaining = osalOsGetSystemTimeX() - start; - osalSysUnlock(); - return (u32_t)ST2MS(remaining); -} - -int sys_sem_valid(sys_sem_t *sem) { - return *sem != SYS_SEM_NULL; -} - -// typically called within lwIP after freeing a semaphore -// to make sure the pointer is not left pointing to invalid data -void sys_sem_set_invalid(sys_sem_t *sem) { - *sem = SYS_SEM_NULL; -} - -err_t sys_mbox_new(sys_mbox_t *mbox, int size) { - - *mbox = chHeapAlloc(NULL, sizeof(mailbox_t) + sizeof(msg_t) * size); - if (*mbox == 0) { - SYS_STATS_INC(mbox.err); - return ERR_MEM; - } - else { - chMBObjectInit(*mbox, (void *)(((uint8_t *)*mbox) + sizeof(mailbox_t)), size); - SYS_STATS_INC(mbox.used); - return ERR_OK; - } -} - -void sys_mbox_free(sys_mbox_t *mbox) { - cnt_t tmpcnt; - - osalSysLock(); - tmpcnt = chMBGetUsedCountI(*mbox); - osalSysUnlock(); - - if (tmpcnt != 0) { - // If there are messages still present in the mailbox when the mailbox - // is deallocated, it is an indication of a programming error in lwIP - // and the developer should be notified. - SYS_STATS_INC(mbox.err); - chMBReset(*mbox); - } - chHeapFree(*mbox); - *mbox = SYS_MBOX_NULL; - SYS_STATS_DEC(mbox.used); -} - -void sys_mbox_post(sys_mbox_t *mbox, void *msg) { - - chMBPost(*mbox, (msg_t)msg, TIME_INFINITE); -} - -err_t sys_mbox_trypost(sys_mbox_t *mbox, void *msg) { - - if (chMBPost(*mbox, (msg_t)msg, TIME_IMMEDIATE) == MSG_TIMEOUT) { - SYS_STATS_INC(mbox.err); - return ERR_MEM; - } - return ERR_OK; -} - -u32_t sys_arch_mbox_fetch(sys_mbox_t *mbox, void **msg, u32_t timeout) { - systime_t tmo, start, remaining; - - osalSysLock(); - tmo = timeout > 0 ? MS2ST((systime_t)timeout) : TIME_INFINITE; - start = osalOsGetSystemTimeX(); - if (chMBFetchS(*mbox, (msg_t *)msg, tmo) != MSG_OK) { - osalSysUnlock(); - return SYS_ARCH_TIMEOUT; - } - remaining = osalOsGetSystemTimeX() - start; - osalSysUnlock(); - return (u32_t)ST2MS(remaining); -} - -u32_t sys_arch_mbox_tryfetch(sys_mbox_t *mbox, void **msg) { - - if (chMBFetch(*mbox, (msg_t *)msg, TIME_IMMEDIATE) == MSG_TIMEOUT) - return SYS_MBOX_EMPTY; - return 0; -} - -int sys_mbox_valid(sys_mbox_t *mbox) { - return *mbox != SYS_MBOX_NULL; -} - -// typically called within lwIP after freeing an mbox -// to make sure the pointer is not left pointing to invalid data -void sys_mbox_set_invalid(sys_mbox_t *mbox) { - *mbox = SYS_MBOX_NULL; -} - -sys_thread_t sys_thread_new(const char *name, lwip_thread_fn thread, - void *arg, int stacksize, int prio) { - size_t wsz; - void *wsp; - syssts_t sts; - thread_t *tp; - - (void)name; - wsz = THD_WORKING_AREA_SIZE(stacksize); - wsp = chCoreAlloc(wsz); - if (wsp == NULL) - return NULL; - -#if CH_DBG_FILL_THREADS == TRUE - _thread_memfill((uint8_t *)wsp, - (uint8_t *)wsp + sizeof(thread_t), - CH_DBG_THREAD_FILL_VALUE); - _thread_memfill((uint8_t *)wsp + sizeof(thread_t), - (uint8_t *)wsp + wsz, - CH_DBG_STACK_FILL_VALUE); -#endif - - sts = chSysGetStatusAndLockX(); - tp = chThdCreateI(wsp, wsz, prio, (tfunc_t)thread, arg); - chRegSetThreadNameX(tp, name); - chThdStartI(tp); - chSysRestoreStatusX(sts); - - return (sys_thread_t)tp; -} - -sys_prot_t sys_arch_protect(void) { - - return chSysGetStatusAndLockX(); -} - -void sys_arch_unprotect(sys_prot_t pval) { - - osalSysRestoreStatusX((syssts_t)pval); -} - -u32_t sys_now(void) { - -#if OSAL_ST_FREQUENCY == 1000 - return (u32_t)osalOsGetSystemTimeX(); -#elif (OSAL_ST_FREQUENCY / 1000) >= 1 && (OSAL_ST_FREQUENCY % 1000) == 0 - return ((u32_t)osalOsGetSystemTimeX() - 1) / (OSAL_ST_FREQUENCY / 1000) + 1; -#elif (1000 / OSAL_ST_FREQUENCY) >= 1 && (1000 % OSAL_ST_FREQUENCY) == 0 - return ((u32_t)osalOsGetSystemTimeX() - 1) * (1000 / OSAL_ST_FREQUENCY) + 1; -#else - return (u32_t)(((u64_t)(osalOsGetSystemTimeX() - 1) * 1000) / OSAL_ST_FREQUENCY) + 1; -#endif -} diff --git a/firmware/ChibiOS_16/os/various/lwip_bindings/arch/sys_arch.h b/firmware/ChibiOS_16/os/various/lwip_bindings/arch/sys_arch.h deleted file mode 100644 index b9df06c230..0000000000 --- a/firmware/ChibiOS_16/os/various/lwip_bindings/arch/sys_arch.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - * **** This file incorporates work covered by the following copyright and **** - * **** permission notice: **** - * - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include - -#ifndef __SYS_ARCH_H__ -#define __SYS_ARCH_H__ - -typedef semaphore_t * sys_sem_t; -typedef mailbox_t * sys_mbox_t; -typedef thread_t * sys_thread_t; -typedef syssts_t sys_prot_t; - -#define SYS_MBOX_NULL (mailbox_t *)0 -#define SYS_THREAD_NULL (thread_t *)0 -#define SYS_SEM_NULL (semaphore_t *)0 - -/* let sys.h use binary semaphores for mutexes */ -#define LWIP_COMPAT_MUTEX 1 - -#endif /* __SYS_ARCH_H__ */ diff --git a/firmware/ChibiOS_16/os/various/lwip_bindings/lwip.mk b/firmware/ChibiOS_16/os/various/lwip_bindings/lwip.mk deleted file mode 100644 index d6ea6716ad..0000000000 --- a/firmware/ChibiOS_16/os/various/lwip_bindings/lwip.mk +++ /dev/null @@ -1,54 +0,0 @@ -# List of the required lwIP files. -LWIP = ${CHIBIOS}/ext/lwip - -LWBINDSRC = \ - $(CHIBIOS)/os/various/lwip_bindings/lwipthread.c \ - $(CHIBIOS)/os/various/lwip_bindings/arch/sys_arch.c - -LWNETIFSRC = \ - ${LWIP}/src/netif/etharp.c - -LWCORESRC = \ - ${LWIP}/src/core/dhcp.c \ - ${LWIP}/src/core/dns.c \ - ${LWIP}/src/core/init.c \ - ${LWIP}/src/core/mem.c \ - ${LWIP}/src/core/memp.c \ - ${LWIP}/src/core/netif.c \ - ${LWIP}/src/core/pbuf.c \ - ${LWIP}/src/core/raw.c \ - ${LWIP}/src/core/stats.c \ - ${LWIP}/src/core/sys.c \ - ${LWIP}/src/core/tcp.c \ - ${LWIP}/src/core/tcp_in.c \ - ${LWIP}/src/core/tcp_out.c \ - ${LWIP}/src/core/udp.c - -LWIPV4SRC = \ - ${LWIP}/src/core/ipv4/autoip.c \ - ${LWIP}/src/core/ipv4/icmp.c \ - ${LWIP}/src/core/ipv4/igmp.c \ - ${LWIP}/src/core/ipv4/inet.c \ - ${LWIP}/src/core/ipv4/inet_chksum.c \ - ${LWIP}/src/core/ipv4/ip.c \ - ${LWIP}/src/core/ipv4/ip_addr.c \ - ${LWIP}/src/core/ipv4/ip_frag.c \ - ${LWIP}/src/core/def.c \ - ${LWIP}/src/core/timers.c - -LWAPISRC = \ - ${LWIP}/src/api/api_lib.c \ - ${LWIP}/src/api/api_msg.c \ - ${LWIP}/src/api/err.c \ - ${LWIP}/src/api/netbuf.c \ - ${LWIP}/src/api/netdb.c \ - ${LWIP}/src/api/netifapi.c \ - ${LWIP}/src/api/sockets.c \ - ${LWIP}/src/api/tcpip.c - -LWSRC = $(LWBINDSRC) $(LWNETIFSRC) $(LWCORESRC) $(LWIPV4SRC) $(LWAPISRC) - -LWINC = \ - $(CHIBIOS)/os/various/lwip_bindings \ - ${LWIP}/src/include \ - ${LWIP}/src/include/ipv4 diff --git a/firmware/ChibiOS_16/os/various/lwip_bindings/lwipthread.c b/firmware/ChibiOS_16/os/various/lwip_bindings/lwipthread.c deleted file mode 100644 index 32316595e0..0000000000 --- a/firmware/ChibiOS_16/os/various/lwip_bindings/lwipthread.c +++ /dev/null @@ -1,340 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - * **** This file incorporates work covered by the following copyright and **** - * **** permission notice: **** - * - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -/** - * @file lwipthread.c - * @brief LWIP wrapper thread code. - * @addtogroup LWIP_THREAD - * @{ - */ - -#include "hal.h" -#include "evtimer.h" - -#include "lwipthread.h" - -#include "lwip/opt.h" - -#include "lwip/def.h" -#include "lwip/mem.h" -#include "lwip/pbuf.h" -#include "lwip/sys.h" -#include -#include -#include -#include "netif/etharp.h" -#include "netif/ppp_oe.h" - -#if LWIP_DHCP -#include -#endif - -#define PERIODIC_TIMER_ID 1 -#define FRAME_RECEIVED_ID 2 - -/* - * Suspension point for initialization procedure. - */ -thread_reference_t lwip_trp = NULL; - -/* - * Stack area for the LWIP-MAC thread. - */ -static THD_WORKING_AREA(wa_lwip_thread, LWIP_THREAD_STACK_SIZE); - -/* - * Initialization. - */ -static void low_level_init(struct netif *netif) { - /* set MAC hardware address length */ - netif->hwaddr_len = ETHARP_HWADDR_LEN; - - /* maximum transfer unit */ - netif->mtu = 1500; - - /* device capabilities */ - /* don't set NETIF_FLAG_ETHARP if this device is not an Ethernet one */ - netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP; - - /* Do whatever else is needed to initialize interface. */ -} - -/* - * Transmits a frame. - */ -static err_t low_level_output(struct netif *netif, struct pbuf *p) { - struct pbuf *q; - MACTransmitDescriptor td; - - (void)netif; - if (macWaitTransmitDescriptor(ÐD1, &td, MS2ST(LWIP_SEND_TIMEOUT)) != MSG_OK) - return ERR_TIMEOUT; - -#if ETH_PAD_SIZE - pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */ -#endif - - /* Iterates through the pbuf chain. */ - for(q = p; q != NULL; q = q->next) - macWriteTransmitDescriptor(&td, (uint8_t *)q->payload, (size_t)q->len); - macReleaseTransmitDescriptor(&td); - -#if ETH_PAD_SIZE - pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */ -#endif - - LINK_STATS_INC(link.xmit); - - return ERR_OK; -} - -/* - * Receives a frame. - */ -static struct pbuf *low_level_input(struct netif *netif) { - MACReceiveDescriptor rd; - struct pbuf *p, *q; - u16_t len; - - (void)netif; - if (macWaitReceiveDescriptor(ÐD1, &rd, TIME_IMMEDIATE) == MSG_OK) { - len = (u16_t)rd.size; - -#if ETH_PAD_SIZE - len += ETH_PAD_SIZE; /* allow room for Ethernet padding */ -#endif - - /* We allocate a pbuf chain of pbufs from the pool. */ - p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL); - - if (p != NULL) { - -#if ETH_PAD_SIZE - pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */ -#endif - - /* Iterates through the pbuf chain. */ - for(q = p; q != NULL; q = q->next) - macReadReceiveDescriptor(&rd, (uint8_t *)q->payload, (size_t)q->len); - macReleaseReceiveDescriptor(&rd); - -#if ETH_PAD_SIZE - pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */ -#endif - - LINK_STATS_INC(link.recv); - } - else { - macReleaseReceiveDescriptor(&rd); - LINK_STATS_INC(link.memerr); - LINK_STATS_INC(link.drop); - } - return p; - } - return NULL; -} - -/* - * Initialization. - */ -static err_t ethernetif_init(struct netif *netif) { -#if LWIP_NETIF_HOSTNAME - /* Initialize interface hostname */ - netif->hostname = "lwip"; -#endif /* LWIP_NETIF_HOSTNAME */ - - /* - * Initialize the snmp variables and counters inside the struct netif. - * The last argument should be replaced with your link speed, in units - * of bits per second. - */ - NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, LWIP_LINK_SPEED); - - netif->state = NULL; - netif->name[0] = LWIP_IFNAME0; - netif->name[1] = LWIP_IFNAME1; - /* We directly use etharp_output() here to save a function call. - * You can instead declare your own function an call etharp_output() - * from it if you have to do some checks before sending (e.g. if link - * is available...) */ - netif->output = etharp_output; - netif->linkoutput = low_level_output; - - /* initialize the hardware */ - low_level_init(netif); - - return ERR_OK; -} - -/** - * @brief LWIP handling thread. - * - * @param[in] p pointer to a @p lwipthread_opts structure or @p NULL - * @return The function does not return. - */ -static THD_FUNCTION(lwip_thread, p) { - event_timer_t evt; - event_listener_t el0, el1; - struct ip_addr ip, gateway, netmask; - static struct netif thisif; - static const MACConfig mac_config = {thisif.hwaddr}; - - chRegSetThreadName("lwipthread"); - - /* Initializes the thing.*/ - tcpip_init(NULL, NULL); - - /* TCP/IP parameters, runtime or compile time.*/ - if (p) { - struct lwipthread_opts *opts = p; - unsigned i; - - for (i = 0; i < 6; i++) - thisif.hwaddr[i] = opts->macaddress[i]; - ip.addr = opts->address; - gateway.addr = opts->gateway; - netmask.addr = opts->netmask; - } - else { - thisif.hwaddr[0] = LWIP_ETHADDR_0; - thisif.hwaddr[1] = LWIP_ETHADDR_1; - thisif.hwaddr[2] = LWIP_ETHADDR_2; - thisif.hwaddr[3] = LWIP_ETHADDR_3; - thisif.hwaddr[4] = LWIP_ETHADDR_4; - thisif.hwaddr[5] = LWIP_ETHADDR_5; - LWIP_IPADDR(&ip); - LWIP_GATEWAY(&gateway); - LWIP_NETMASK(&netmask); - } - macStart(ÐD1, &mac_config); - netif_add(&thisif, &ip, &netmask, &gateway, NULL, ethernetif_init, tcpip_input); - - netif_set_default(&thisif); - netif_set_up(&thisif); - - /* Setup event sources.*/ - evtObjectInit(&evt, LWIP_LINK_POLL_INTERVAL); - evtStart(&evt); - chEvtRegisterMask(&evt.et_es, &el0, PERIODIC_TIMER_ID); - chEvtRegisterMask(macGetReceiveEventSource(ÐD1), &el1, FRAME_RECEIVED_ID); - chEvtAddEvents(PERIODIC_TIMER_ID | FRAME_RECEIVED_ID); - - /* Resumes the caller and goes to the final priority.*/ - chThdResume(&lwip_trp, MSG_OK); - chThdSetPriority(LWIP_THREAD_PRIORITY); - - while (true) { - eventmask_t mask = chEvtWaitAny(ALL_EVENTS); - if (mask & PERIODIC_TIMER_ID) { - bool current_link_status = macPollLinkStatus(ÐD1); - if (current_link_status != netif_is_link_up(&thisif)) { - if (current_link_status) { - tcpip_callback_with_block((tcpip_callback_fn) netif_set_link_up, - &thisif, 0); -#if LWIP_DHCP - dhcp_start(&thisif); -#endif - } - else { - tcpip_callback_with_block((tcpip_callback_fn) netif_set_link_down, - &thisif, 0); -#if LWIP_DHCP - dhcp_stop(&thisif); -#endif - } - } - } - if (mask & FRAME_RECEIVED_ID) { - struct pbuf *p; - while ((p = low_level_input(&thisif)) != NULL) { - struct eth_hdr *ethhdr = p->payload; - switch (htons(ethhdr->type)) { - /* IP or ARP packet? */ - case ETHTYPE_IP: - case ETHTYPE_ARP: -#if PPPOE_SUPPORT - /* PPPoE packet? */ - case ETHTYPE_PPPOEDISC: - case ETHTYPE_PPPOE: -#endif /* PPPOE_SUPPORT */ - /* full packet send to tcpip_thread to process */ - if (thisif.input(p, &thisif) == ERR_OK) - break; - LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_input: IP input error\n")); - default: - pbuf_free(p); - } - } - } - } -} - -/** - * @brief Initializes the lwIP subsystem. - * @note The function exits after the initialization is finished. - * - * @param[in] opts pointer to the configuration structure, if @p NULL - * then the static configuration is used. - */ -void lwipInit(const lwipthread_opts_t *opts) { - - /* Creating the lwIP thread (it changes priority internally).*/ - chThdCreateStatic(wa_lwip_thread, sizeof (wa_lwip_thread), - chThdGetPriorityX() - 1, lwip_thread, (void *)opts); - - /* Waiting for the lwIP thread complete initialization. Note, - this thread reaches the thread reference object first because - the relative priorities.*/ - chSysLock(); - chThdSuspendS(&lwip_trp); - chSysUnlock(); -} - -/** @} */ diff --git a/firmware/ChibiOS_16/os/various/lwip_bindings/lwipthread.h b/firmware/ChibiOS_16/os/various/lwip_bindings/lwipthread.h deleted file mode 100644 index 471785e59a..0000000000 --- a/firmware/ChibiOS_16/os/various/lwip_bindings/lwipthread.h +++ /dev/null @@ -1,161 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file lwipthread.h - * @brief LWIP wrapper thread macros and structures. - * @addtogroup LWIP_THREAD - * @{ - */ - -#ifndef _LWIPTHREAD_H_ -#define _LWIPTHREAD_H_ - -#include - -/** - * @brief lwIP thread priority. - */ -#ifndef LWIP_THREAD_PRIORITY -#define LWIP_THREAD_PRIORITY LOWPRIO -#endif - -/** - * @brief lwIP thread stack size. - */ -#if !defined(LWIP_THREAD_STACK_SIZE) || defined(__DOXYGEN__) -#define LWIP_THREAD_STACK_SIZE 576 -#endif - -/** - * @brief Link poll interval. - */ -#if !defined(LWIP_LINK_POLL_INTERVAL) || defined(__DOXYGEN__) -#define LWIP_LINK_POLL_INTERVAL S2ST(5) -#endif - -/** - * @brief IP Address. - */ -#if !defined(LWIP_IPADDR) || defined(__DOXYGEN__) -#define LWIP_IPADDR(p) IP4_ADDR(p, 192, 168, 1, 10) -#endif - -/** - * @brief IP Gateway. - */ -#if !defined(LWIP_GATEWAY) || defined(__DOXYGEN__) -#define LWIP_GATEWAY(p) IP4_ADDR(p, 192, 168, 1, 1) -#endif - -/** - * @brief IP netmask. - */ -#if !defined(LWIP_NETMASK) || defined(__DOXYGEN__) -#define LWIP_NETMASK(p) IP4_ADDR(p, 255, 255, 255, 0) -#endif - -/** - * @brief Transmission timeout. - */ -#if !defined(LWIP_SEND_TIMEOUT) || defined(__DOXYGEN__) -#define LWIP_SEND_TIMEOUT 50 -#endif - -/** - * @brief Link speed. - */ -#if !defined(LWIP_LINK_SPEED) || defined(__DOXYGEN__) -#define LWIP_LINK_SPEED 100000000 -#endif - -/** - * @brief MAC Address byte 0. - */ -#if !defined(LWIP_ETHADDR_0) || defined(__DOXYGEN__) -#define LWIP_ETHADDR_0 0xC2 -#endif - -/** - * @brief MAC Address byte 1. - */ -#if !defined(LWIP_ETHADDR_1) || defined(__DOXYGEN__) -#define LWIP_ETHADDR_1 0xAF -#endif - -/** - * @brief MAC Address byte 2. - */ -#if !defined(LWIP_ETHADDR_2) || defined(__DOXYGEN__) -#define LWIP_ETHADDR_2 0x51 -#endif - -/** - * @brief MAC Address byte 3. - */ -#if !defined(LWIP_ETHADDR_3) || defined(__DOXYGEN__) -#define LWIP_ETHADDR_3 0x03 -#endif - -/** - * @brief MAC Address byte 4. - */ -#if !defined(LWIP_ETHADDR_4) || defined(__DOXYGEN__) -#define LWIP_ETHADDR_4 0xCF -#endif - -/** - * @brief MAC Address byte 5. - */ -#if !defined(LWIP_ETHADDR_5) || defined(__DOXYGEN__) -#define LWIP_ETHADDR_5 0x46 -#endif - -/** - * @brief Interface name byte 0. - */ -#if !defined(LWIP_IFNAME0) || defined(__DOXYGEN__) -#define LWIP_IFNAME0 'm' -#endif - -/** - * @brief Interface name byte 1. - */ -#if !defined(LWIP_IFNAME1) || defined(__DOXYGEN__) -#define LWIP_IFNAME1 's' -#endif - -/** - * @brief Runtime TCP/IP settings. - */ -typedef struct lwipthread_opts { - uint8_t *macaddress; - uint32_t address; - uint32_t netmask; - uint32_t gateway; -} lwipthread_opts_t; - -#ifdef __cplusplus -extern "C" { -#endif - void lwipInit(const lwipthread_opts_t *opts); -#ifdef __cplusplus -} -#endif - -#endif /* _LWIPTHREAD_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/various/lwip_bindings/readme.txt b/firmware/ChibiOS_16/os/various/lwip_bindings/readme.txt deleted file mode 100644 index f2a88982a4..0000000000 --- a/firmware/ChibiOS_16/os/various/lwip_bindings/readme.txt +++ /dev/null @@ -1,6 +0,0 @@ -This directory contains the ChibiOS/RT "official" bindings with the lwIP -TCP/IP stack: http://savannah.nongnu.org/projects/lwip - -In order to use lwIP within ChibiOS/RT project, unzip lwIP under -./ext/lwip-1.4.0 then include $(CHIBIOS)/os/various/lwip_bindings/lwip.mk -in your makefile. diff --git a/firmware/ChibiOS_16/os/various/shell.c b/firmware/ChibiOS_16/os/various/shell.c deleted file mode 100644 index 07c02390bb..0000000000 --- a/firmware/ChibiOS_16/os/various/shell.c +++ /dev/null @@ -1,303 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file shell.c - * @brief Simple CLI shell code. - * - * @addtogroup SHELL - * @{ - */ - -#include - -#include "ch.h" -#include "hal.h" -#include "shell.h" -#include "chprintf.h" - -/** - * @brief Shell termination event source. - */ -event_source_t shell_terminated; - -static char *_strtok(char *str, const char *delim, char **saveptr) { - char *token; - if (str) - *saveptr = str; - token = *saveptr; - - if (!token) - return NULL; - - token += strspn(token, delim); - *saveptr = strpbrk(token, delim); - if (*saveptr) - *(*saveptr)++ = '\0'; - - return *token ? token : NULL; -} - -static void usage(BaseSequentialStream *chp, char *p) { - - chprintf(chp, "Usage: %s\r\n", p); -} - -static void list_commands(BaseSequentialStream *chp, const ShellCommand *scp) { - - while (scp->sc_name != NULL) { - chprintf(chp, "%s ", scp->sc_name); - scp++; - } -} - -static void cmd_info(BaseSequentialStream *chp, int argc, char *argv[]) { - - (void)argv; - if (argc > 0) { - usage(chp, "info"); - return; - } - - chprintf(chp, "Kernel: %s\r\n", CH_KERNEL_VERSION); -#ifdef PORT_COMPILER_NAME - chprintf(chp, "Compiler: %s\r\n", PORT_COMPILER_NAME); -#endif - chprintf(chp, "Architecture: %s\r\n", PORT_ARCHITECTURE_NAME); -#ifdef PORT_CORE_VARIANT_NAME - chprintf(chp, "Core Variant: %s\r\n", PORT_CORE_VARIANT_NAME); -#endif -#ifdef PORT_INFO - chprintf(chp, "Port Info: %s\r\n", PORT_INFO); -#endif -#ifdef PLATFORM_NAME - chprintf(chp, "Platform: %s\r\n", PLATFORM_NAME); -#endif -#ifdef BOARD_NAME - chprintf(chp, "Board: %s\r\n", BOARD_NAME); -#endif -#ifdef __DATE__ -#ifdef __TIME__ - chprintf(chp, "Build time: %s%s%s\r\n", __DATE__, " - ", __TIME__); -#endif -#endif -} - -static void cmd_systime(BaseSequentialStream *chp, int argc, char *argv[]) { - - (void)argv; - if (argc > 0) { - usage(chp, "systime"); - return; - } - chprintf(chp, "%lu\r\n", (unsigned long)chVTGetSystemTime()); -} - -/** - * @brief Array of the default commands. - */ -static const ShellCommand local_commands[] = { - {"info", cmd_info}, - {"systime", cmd_systime}, - {NULL, NULL} -}; - -static bool cmdexec(const ShellCommand *scp, BaseSequentialStream *chp, - char *name, int argc, char *argv[]) { - - while (scp->sc_name != NULL) { - if (strcmp(scp->sc_name, name) == 0) { - scp->sc_function(chp, argc, argv); - return false; - } - scp++; - } - return true; -} - -/** - * @brief Shell thread function. - * - * @param[in] p pointer to a @p BaseSequentialStream object - */ -static THD_FUNCTION(shell_thread, p) { - int n; - BaseSequentialStream *chp = ((ShellConfig *)p)->sc_channel; - const ShellCommand *scp = ((ShellConfig *)p)->sc_commands; - char *lp, *cmd, *tokp, line[SHELL_MAX_LINE_LENGTH]; - char *args[SHELL_MAX_ARGUMENTS + 1]; - - chRegSetThreadName("shell"); - chprintf(chp, "\r\nChibiOS/RT Shell\r\n"); - while (true) { - chprintf(chp, "ch> "); - if (shellGetLine(chp, line, sizeof(line))) { - chprintf(chp, "\r\nlogout"); - break; - } - lp = _strtok(line, " \t", &tokp); - cmd = lp; - n = 0; - while ((lp = _strtok(NULL, " \t", &tokp)) != NULL) { - if (n >= SHELL_MAX_ARGUMENTS) { - chprintf(chp, "too many arguments\r\n"); - cmd = NULL; - break; - } - args[n++] = lp; - } - args[n] = NULL; - if (cmd != NULL) { - if (strcmp(cmd, "exit") == 0) { - if (n > 0) { - usage(chp, "exit"); - continue; - } - break; - } - else if (strcmp(cmd, "help") == 0) { - if (n > 0) { - usage(chp, "help"); - continue; - } - chprintf(chp, "Commands: help exit "); - list_commands(chp, local_commands); - if (scp != NULL) - list_commands(chp, scp); - chprintf(chp, "\r\n"); - } - else if (cmdexec(local_commands, chp, cmd, n, args) && - ((scp == NULL) || cmdexec(scp, chp, cmd, n, args))) { - chprintf(chp, "%s", cmd); - chprintf(chp, " ?\r\n"); - } - } - } - shellExit(MSG_OK); -} - -/** - * @brief Shell manager initialization. - * - * @api - */ -void shellInit(void) { - - chEvtObjectInit(&shell_terminated); -} - -/** - * @brief Terminates the shell. - * @note Must be invoked from the command handlers. - * @note Does not return. - * - * @param[in] msg shell exit code - * - * @api - */ -void shellExit(msg_t msg) { - - /* Atomically broadcasting the event source and terminating the thread, - there is not a chSysUnlock() because the thread terminates upon return.*/ - chSysLock(); - chEvtBroadcastI(&shell_terminated); - chThdExitS(msg); -} - -/** - * @brief Spawns a new shell. - * @pre @p CH_CFG_USE_HEAP and @p CH_CFG_USE_DYNAMIC must be enabled. - * - * @param[in] scp pointer to a @p ShellConfig object - * @param[in] size size of the shell working area to be allocated - * @param[in] prio priority level for the new shell - * @return A pointer to the shell thread. - * @retval NULL thread creation failed because memory allocation. - * - * @api - */ -#if CH_CFG_USE_HEAP && CH_CFG_USE_DYNAMIC -thread_t *shellCreate(const ShellConfig *scp, size_t size, tprio_t prio) { - - return chThdCreateFromHeap(NULL, size, prio, shell_thread, (void *)scp); -} -#endif - -/** - * @brief Create statically allocated shell thread. - * - * @param[in] scp pointer to a @p ShellConfig object - * @param[in] wsp pointer to a working area dedicated to the shell thread stack - * @param[in] size size of the shell working area - * @param[in] prio priority level for the new shell - * @return A pointer to the shell thread. - * - * @api - */ -thread_t *shellCreateStatic(const ShellConfig *scp, void *wsp, - size_t size, tprio_t prio) { - - return chThdCreateStatic(wsp, size, prio, shell_thread, (void *)scp); -} - -/** - * @brief Reads a whole line from the input channel. - * - * @param[in] chp pointer to a @p BaseSequentialStream object - * @param[in] line pointer to the line buffer - * @param[in] size buffer maximum length - * @return The operation status. - * @retval true the channel was reset or CTRL-D pressed. - * @retval false operation successful. - * - * @api - */ -bool shellGetLine(BaseSequentialStream *chp, char *line, unsigned size) { - char *p = line; - - while (true) { - char c; - - if (chSequentialStreamRead(chp, (uint8_t *)&c, 1) == 0) - return true; - if (c == 4) { - chprintf(chp, "^D"); - return true; - } - if ((c == 8) || (c == 127)) { - if (p != line) { - chSequentialStreamPut(chp, 0x08); - chSequentialStreamPut(chp, 0x20); - chSequentialStreamPut(chp, 0x08); - p--; - } - continue; - } - if (c == '\r') { - chprintf(chp, "\r\n"); - *p = 0; - return false; - } - if (c < 0x20) - continue; - if (p < line + size - 1) { - chSequentialStreamPut(chp, c); - *p++ = (char)c; - } - } -} - -/** @} */ diff --git a/firmware/ChibiOS_16/os/various/shell.h b/firmware/ChibiOS_16/os/various/shell.h deleted file mode 100644 index bdafba5c8f..0000000000 --- a/firmware/ChibiOS_16/os/various/shell.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file shell.h - * @brief Simple CLI shell header. - * - * @addtogroup SHELL - * @{ - */ - -#ifndef _SHELL_H_ -#define _SHELL_H_ - -/** - * @brief Shell maximum input line length. - */ -#if !defined(SHELL_MAX_LINE_LENGTH) || defined(__DOXYGEN__) -#define SHELL_MAX_LINE_LENGTH 64 -#endif - -/** - * @brief Shell maximum arguments per command. - */ -#if !defined(SHELL_MAX_ARGUMENTS) || defined(__DOXYGEN__) -#define SHELL_MAX_ARGUMENTS 4 -#endif - -/** - * @brief Command handler function type. - */ -typedef void (*shellcmd_t)(BaseSequentialStream *chp, int argc, char *argv[]); - -/** - * @brief Custom command entry type. - */ -typedef struct { - const char *sc_name; /**< @brief Command name. */ - shellcmd_t sc_function; /**< @brief Command function. */ -} ShellCommand; - -/** - * @brief Shell descriptor type. - */ -typedef struct { - BaseSequentialStream *sc_channel; /**< @brief I/O channel associated - to the shell. */ - const ShellCommand *sc_commands; /**< @brief Shell extra commands - table. */ -} ShellConfig; - -#if !defined(__DOXYGEN__) -extern event_source_t shell_terminated; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void shellInit(void); - void shellExit(msg_t msg); -#if CH_CFG_USE_HEAP && CH_CFG_USE_DYNAMIC - thread_t *shellCreate(const ShellConfig *scp, size_t size, tprio_t prio); -#endif - thread_t *shellCreateStatic(const ShellConfig *scp, void *wsp, - size_t size, tprio_t prio); - bool shellGetLine(BaseSequentialStream *chp, char *line, unsigned size); -#ifdef __cplusplus -} -#endif - -#endif /* _SHELL_H_ */ - -/** @} */ diff --git a/firmware/ChibiOS_16/os/various/syscalls.c b/firmware/ChibiOS_16/os/various/syscalls.c deleted file mode 100644 index 1b16dda362..0000000000 --- a/firmware/ChibiOS_16/os/various/syscalls.c +++ /dev/null @@ -1,179 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* -* **** This file incorporates work covered by the following copyright and **** -* **** permission notice: **** -* -* Copyright (c) 2009 by Michael Fischer. All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* 1. Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* 3. Neither the name of the author nor the names of its contributors may -* be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL -* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -* SUCH DAMAGE. -* -**************************************************************************** -* History: -* -* 28.03.09 mifi First Version, based on the original syscall.c from -* newlib version 1.17.0 -* 17.08.09 gdisirio Modified the file for use under ChibiOS/RT -* 15.11.09 gdisirio Added read and write handling -****************************************************************************/ - -#include -#include -#include -#include -#include - -#include "ch.h" -#if defined(STDOUT_SD) || defined(STDIN_SD) -#include "hal.h" -#endif - -/***************************************************************************/ - -__attribute__((used)) -int _read_r(struct _reent *r, int file, char * ptr, int len) -{ - (void)r; -#if defined(STDIN_SD) - if (!len || (file != 0)) { - __errno_r(r) = EINVAL; - return -1; - } - len = sdRead(&STDIN_SD, (uint8_t *)ptr, (size_t)len); - return len; -#else - (void)file; - (void)ptr; - (void)len; - __errno_r(r) = EINVAL; - return -1; -#endif -} - -/***************************************************************************/ - -__attribute__((used)) -int _lseek_r(struct _reent *r, int file, int ptr, int dir) -{ - (void)r; - (void)file; - (void)ptr; - (void)dir; - - return 0; -} - -/***************************************************************************/ - -__attribute__((used)) -int _write_r(struct _reent *r, int file, char * ptr, int len) -{ - (void)r; - (void)file; - (void)ptr; -#if defined(STDOUT_SD) - if (file != 1) { - __errno_r(r) = EINVAL; - return -1; - } - sdWrite(&STDOUT_SD, (uint8_t *)ptr, (size_t)len); -#endif - return len; -} - -/***************************************************************************/ - -__attribute__((used)) -int _close_r(struct _reent *r, int file) -{ - (void)r; - (void)file; - - return 0; -} - -/***************************************************************************/ - -__attribute__((used)) -caddr_t _sbrk_r(struct _reent *r, int incr) -{ -#if CH_CFG_USE_MEMCORE - void *p; - - chDbgCheck(incr >= 0); - - p = chCoreAlloc((size_t)incr); - if (p == NULL) { - __errno_r(r) = ENOMEM; - return (caddr_t)-1; - } - return (caddr_t)p; -#else - (void)incr; - __errno_r(r) = ENOMEM; - return (caddr_t)-1; -#endif -} - -/***************************************************************************/ - -__attribute__((used)) -int _fstat_r(struct _reent *r, int file, struct stat * st) -{ - (void)r; - (void)file; - - memset(st, 0, sizeof(*st)); - st->st_mode = S_IFCHR; - return 0; -} - -/***************************************************************************/ - -__attribute__((used)) -int _isatty_r(struct _reent *r, int fd) -{ - (void)r; - (void)fd; - - return 1; -} - -/*** EOF ***/ diff --git a/firmware/ChibiOS_16/os/various/various.dox b/firmware/ChibiOS_16/os/various/various.dox deleted file mode 100644 index d27684a418..0000000000 --- a/firmware/ChibiOS_16/os/various/various.dox +++ /dev/null @@ -1,81 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @defgroup various Various - * - * @brief Utilities Library. - * @details This is a collection of useful library code that is not part of - * the base kernel services. - *

Notes

- * The library code does not follow the same naming convention of the - * system APIs in order to make very clear that it is not "core" code.
- * The main difference is that library code is not formally tested in the - * test suite but through usage in the various demo applications. - */ - -/** - * @defgroup cpp_library C++ Wrapper - * - * @brief C++ wrapper module. - * @details This module allows to use the ChibiOS/RT functionalities - * from C++ as classes and objects rather the traditional "C" APIs. - * - * @ingroup various - */ - -/** - * @defgroup memory_streams Memory Streams - * - * @brief Memory Streams. - * @details This module allows to use a memory area (RAM or ROM) using a - * @ref data_streams interface. - * - * @ingroup various - */ - -/** - * @defgroup event_timer Periodic Events Timer - * - * @brief Periodic Event Timer. - * @details This timer generates an event at regular intervals. The - * listening threads can use the event to perform time related - * activities. Multiple threads can listen to the same timer. - * - * @ingroup various - */ - -/** - * @defgroup SHELL Command Shell - * - * @brief Small extendible command line shell. - * @details This module implements a generic extendible command line interface. - * The CLI just requires an I/O channel (@p BaseChannel), more - * commands can be added to the shell using the configuration - * structure. - * - * @ingroup various - */ - -/** - * @defgroup chprintf System formatted print - * - * @brief System formatted print service. - * @details This module implements printf()-like function able to send data - * to any module implementing a @p BaseSequentialStream interface. - * - * @ingroup various - */ diff --git a/firmware/ChibiOS_16/readme.txt b/firmware/ChibiOS_16/readme.txt deleted file mode 100644 index b8f3bf6844..0000000000 --- a/firmware/ChibiOS_16/readme.txt +++ /dev/null @@ -1,489 +0,0 @@ -***************************************************************************** -*** Files Organization *** -***************************************************************************** - ---{root} - ChibiOS/RT directory. - +--readme.txt - This file. - +--documentation.html - Shortcut to the web documentation page. - +--license.txt - GPL license text. - +--demos/ - Demo projects, one directory per platform. - +--docs/ - Documentation. - | +--common/ - Documentation common build resources. - | +--hal/ - Builders for HAL. - | | +--Doxyfile_* - Doxygen project files (required for rebuild). - | | +--html/ - Local HTML documentation (after rebuild). - | | +--reports/ - Test reports. - | | +--rsc/ - Documentation resource files (required for rebuild). - | | +--src/ - Documentation source files (required for rebuild). - | | +--Doxyfile_* - Doxygen project files (required for rebuild). - | | +--index.html - Local documentation access (after rebuild). - | +--nil/ - Builders for NIL. - | | +--Doxyfile_* - Doxygen project files (required for rebuild). - | | +--html/ - Local HTML documentation (after rebuild). - | | +--reports/ - Test reports. - | | +--rsc/ - Documentation resource files (required for rebuild). - | | +--src/ - Documentation source files (required for rebuild). - | | +--Doxyfile_* - Doxygen project files (required for rebuild). - | | +--index.html - Local documentation access (after rebuild). - | +--rt/ - Builders for RT. - | | +--html/ - Local HTML documentation (after rebuild). - | | +--reports/ - Test reports. - | | +--rsc/ - Documentation resource files (required for rebuild). - | | +--src/ - Documentation source files (required for rebuild). - | | +--Doxyfile_* - Doxygen project files (required for rebuild). - | | +--index.html - Local documentation access (after rebuild). - +--ext/ - External libraries, not part of ChibiOS/RT. - +--os/ - ChibiOS components. - | +--hal/ - HAL component. - | | +--boards/ - HAL board support files. - | | +--dox/ - HAL documentation resources. - | | +--include/ - HAL high level headers. - | | +--lib/ - HAL libraries. - | | +--osal/ - HAL OSAL implementations. - | | +--src/ - HAL high level source. - | | +--ports/ - HAL ports. - | | +--templates/ - HAL driver template files. - | | +--osal/ - HAL OSAL templates. - | +--nil/ - NIL RTOS component. - | | +--dox/ - NIL documentation resources. - | | +--include/ - NIL high level headers. - | | +--src/ - NIL high level source. - | | +--ports/ - NIL ports. - | | +--templates/ - NIL port template files. - | +--rt/ - RT RTOS component. - | | +--dox/ - RT documentation resources. - | | +--include/ - RT high level headers. - | | +--src/ - RT high level source. - | | +--ports/ - RT ports. - | | +--templates/ - RT port template files. - | +--various/ - Various portable support files. - +--test/ - Kernel test suite source code. - | +--lib/ - Portable test engine. - | +--hal/ - HAL test suites. - | | +--testbuild/ - HAL build test and MISRA check. - | +--nil/ - NIL test suites. - | | +--testbuild/ - NIL build test and MISRA check. - | +--rt/ - RT test suites. - | | +--testbuild/ - RT build test and MISRA check. - | | +--coverage/ - RT code coverage project. - +--testhal/ - HAL integration test demos. - -***************************************************************************** -*** Releases and Change Log *** -***************************************************************************** - -*** 16.1.7 *** -- VAR: Fixed BYTE_ORDER redefined in lwip_bindings/arch/cc.h (bug #814). -- HAL: Fixed setting alternate mode in STM32 GPIOv3 and GPIOv3 drivers can fail - (bug #813). -- HAL: Fixed incorrect handling of shared ISRs in STM32 DMAv1 driver - (bug #812). -- HAL: Fixed protocol violation in usbDisableEndpointsI() API (bug #811). -- HAL: Fixed incorrect constants STM32_DAC1_CHx_DMA_CHN for STM32F7 (bug #810). -- HAL: Fixed redefined TIM in STM32F030 registry (bug #809). -- HAL: Fixed clock init in STM32F0x port which doesn't take in account - PLL_XTPRE and PREDIV_0 are hard-wired (bug #808). - -*** 16.1.6 *** -- HAL: Fixed wrong initialization in ADC lld v3 (bug #807). -- HAL: Fixed wrong clock init in STM32F0 port ad added more error checks - (bug #806). -- HAL: Fixed misplaced else in STM32F0 port (bug #805). -- HAL: Fixed flash waiting state misconfiguration in STM32L4 port (bug #804). -- HAL: Added CR field to DAC configuration in STM32 port (bug #803). -- HAL: Fixed wrong initialization for DACD4 in STM32 port (bug #802). -- HAL: Fixed tab instead of space in DAC driver (bug #801). -- HAL: Fixed missing GPT and DAC in STM32F07/?9x mcuconf (bug #800). -- HAL: Fixed STM32 RTCv2 driver does not handle the DST bit (bug #799). -- HAL: Fixed MAC driver broken on STM32F107 (bug #798). -- VAR: Fixed missing const qualifier in local shell commands array (bug #797). -- VAR: Fixed compilation error in cmsis_os.h (bug #796). -- HAL: Fixed double empty lines in HAL (bug #794). -- RT: Fixed double empty lines in RT (bug #793). -- HAL: Fixed wrong entries in STM32L4 registry (bug #792). -- HAL: Fixed missing ARPE bit in CR1 initialization on STM32 GPT driver - (bug #791). -- HAL: Fixed wrong DMA definition for STM32F303x8 ADC (bug #790). -- VAR: Fixed GCC garbage collector discards code in syscalls.c (bug #789). -- HAL: Fixed Makefile dependencies not generated for .S files (bug #787). -- HAL: Fixed OTGv1 driver not functional on STM32L4 (bug #786). -- HAL: Fixed wrong bit offset in STM32F37x ADC_CR2_EXTSEL_SRC() macro - (bug #785). -- RT: Fixed tick-less mode can fail in RT for very large delays (bug #784). -- HAL: Fixed STM32L0xx CCIPR initialization (bug #783). -- HAL: Fixed STM32F105 port not compiling (bug #782). -- HAL: Fixed wrong registry for STM32F205xx and STM32F215xx port - (bug #780). -- HAL: Fixed wrong HSE checks and PLL2 enable switch in STM32F105 and - STM32F107 port (bug #779). -- HAL: Fixed wrong SRAM2_BASE in STM32F7xx port (bug #778) - (backported to 16.1.6). -- HAL: Added DAC configs in RT-STM32F051-DISCOVERY\mcuconf.h (bug #777). -- HAL: Fixed DAC driver not compiling on STM32F051 and some bitmasks related - to DAC disabling (bug #776). -- HAL: Fixed addition semicolon in cpp wrapper (bug #774). -- HAL: Fixed function gpt_lld_polled_delay() is broken on STM32 (bug #775). -- HAL: Fixed invalid output initialization for STM32 DACx channels 2 - (bug #773). -- HAL: Fixed CAN inclusion path missing for STM32F107 (bug #772). -- HAL: Fixed extra brackets in STM32F0 registry (bug #771). -- HAL: Fixed STM32 CAN filters initialization problem (bug #770). -- HAL: Fixed wrong bit mask in STM32L0xx port (bug #769). -- HAL: Fixed potential wait states problem in STM32L4 initialization code - (bug #768). -- HAL: Fixed SDIO driver not compiling on STM32F446 devices (bug #767). -- HAL: Fixed error in STM32L4xx ST headers (bug #766). -- HAL: Fixed wrong check in win32 simulator serial driver (bug #765). -- HAL: Fixed dependency on RT in hal_usb.c (bug #764). -- HAL: Fixed wrong backup domain reset in STM32L4xx\hal_lld (bug #763). - -*** 16.1.5 *** -- NEW: Added support for more Nucleo and Discovery boards. -- HAL: Board files regenerated using the latest version of the generator - plugin. -- HAL: Fixed wrong PWR configurations in STM32L4xx\hal_lld (bug #761). -- HAL: Fixed wrong comment in STM32L4xx\hal_lld (bug #760). -- HAL: Fixed wrong MSIRANGE management for STM32L4xx in function - stm32_clock_init() (bug #759). -- HAL: Fixed problem in USB driver when changing configuration (bug #757). -- HAL: Fixed bug in function usbDisableEndpointsI() (bug #756). -- HAL: Fixed wrong info in readme of LWIP related demos (bug #755). -- HAL: Fixed misconfiguration in STM32L4 Discovery board files - (bug #754). -- HAL: Fixed errors in documentation related to OTG peripheral switches - (bug #753). -- HAL: Fixed CMSIS function osThreadGetPriority() does not return correct - priority (bug #752). -- HAL: Fixed wrong conditional branches in _adc_isr_error_code (bug #751). -- HAL: Fixed bug in STM32/ADCv3 (bug #750). -- HAL: Fixed OPT settings and added board folder in STM32F4xx-USB_CDC demo - (bug #749). -- HAL: Fixed wrong comments in STM32F4xx GPT demo (bug #748). -- HAL: Fixed wrong comments and indents in STM32F7xx-GPT-ADC and - STM32L4-GPT-ADC demos (bug #747). -- HAL: Fixed wrong comments and indent in STM32F4xx and STM32F7xx - hal_lld.h (bug #746). -- HAL: Removed wrong SAI masks in STM32F4xx hal_lld.h (bug #745). -- HAL: Fixed wrong mask placement in STM32F4xx hal_lld.h (bug #744). -- HAL: Fixed wrong indent in STM32F4xx hal_lld.h (bug #743). -- HAL: Removed unused macros in STM32F7xx and STM32F4xx hal_lld.h (bug #742). -- HAL: Fixed Doxygen related macros in STM32F7xx, STM32L0xx and STM32L4xx - lld files (bug #741). -- HAL: Fixed bug in VREF enable/disable functions in ADCv3 driver - (bug #740). -- HAL: Fixed DAC driver not enabled for STM32F4x7 and STM32F4x9 devices - (bug #739). -- HAL: Fixed bug in interrupt handlers in STM32F4xx EXT driver (bug #738). -- HAL: Fixed clock enabling in STM32 ADCv3 (bug #737). -- HAL: Fixed missing SDC initialization in RT-STM32F103-OLIMEX_STM32_P103 demo - (bug #735). -- HAL: Fixed STM32 dac bug when using only channel 2 in direct mode (bug #734). -- HAL: Fixed PAL lines support not working for STM32 GPIOv1 (bug #730). -- RT: Fixed bug in chSchPreemption() function (bug #728). -- HAL: Fixed prescaler not initialized in STM32 ADCv1 (bug #725). -- HAL: Fixed missing DAC section in STM32F072 mcuconf.h files (bug #724). - -*** 16.1.4 *** -- ALL: Startup files relicensed under Apache 2.0. -- RT: Added RT-STM32L476-DISCOVERY demo. -- HAL: Added more STM32L4xx testhal demos. -- HAL: Updated all STM32F476 mcuconf.h files. -- VAR: Fixed palSetMode glitching outputs (bug #723). -- VAR: Fixed error in STM32 PWM driver regarding channels 4 and 5 (bug #722). -- VAR: Fixed GCC 5.2 crashes while compiling ChibiOS (bug #718). -- HAL: Fixed wrong definition in STM32L4 ext_lld_isr.h (bug #717). -- HAL: Fixed wrong definitions in STM32F746 mcuconf.h files (bug #716) -- RT: Fixed wrong SysTick initialization in generic demos (bug #715). -- NIL: Fixed wrong SysTick initialization in generic demos (bug #715). -- HAL: Fixed usbStop does not resume threads suspended in synchronous calls - to usbTransmit (bug #714). -- VAR: Fixed state check in lwIP when SYS_LIGHTWEIGHT_PROT is disabled - (bug #713). -- RT: Fixed race condition in RT registry (bug #712). -- HAL: Fixed IAR warnings in ext_lld_isr.c (bug #711). -- HAL: Fixed build error caused by STM32 SPIv1 driver (bug #710). -- HAL: Fixed shift of signed constant causes warnings with IAR compiler - (bug #709). -- HAL: Fixed wrong RTCv2 settings for STM32L4 (bug #708). -- HAL: Fixed missing OTGv1 support for STM32L4 (bug #707). -- NIL: Fixed ARM errata 752419 (bug #706). -- RT: Fixed ARM errata 752419 (bug #706). - -*** 16.1.3 *** -- HAL: Fixed unused variable in STM32 SPIv2 driver (bug #705). -- HAL: Fixed chDbgAssert() still called from STM32 SPIv1 driver (bug #704). -- HAL: Fixed broken demo for STM32F429 (bug #703). -- HAL: Fixed wrong macro definition for palWriteLine (bug #702). -- HAL: Fixed error is buffer queues (bug #701). -- HAL: Fixed typos in STM32F0 RCC enable/disable macros (bug #698). -- RT: Fixed useless call to chTMStartMeasurementX() in _thread_init() - (bug #697). -- VAR: Fixed missing time conversion in lwIP arch module (bug #696, again). - -*** 16.1.2 *** -- VAR: Fixed missing time conversion in lwIP arch module (bug #696). -- HAL: Fixed incorrect handling of TIME_IMMEDIATE in the HAL buffer queues - (bug #695). - -*** 16.1.1 *** -- NIL: NIL_CFG_USE_EVENTS not properly checked in NIL (bug #694). -- RT: Fixed ISR statistics are not updated from a critical zone in RT - (bug #693). -- NIL: Fixed NIL test suite calls I and S functions outside critical zone - (bug #692). -- NIL: Fixed protocol violation in NIL OSAL (bug #691). -- HAL: Fixed error in HAL buffer queues (bug #689). -- RT: Fixed tm_stop - best case bug (bug #688). -- RT: Several minor documentation/formatting-related fixes. - -*** 16.1.0 *** -- RT: Added CodeWarrior compiler support to the e200 port. -- HAL: Added support for STM32F446. -- HAL: Introduced preliminary support for STM32F7xx devices. -- HAL: Introduced preliminary support for STM32L4xx devices. -- HAL: Introduced preliminary support for STM32L0xx devices. -- HAL: Increased performance of USBv1 and OTGv1 driver thanks to better - data copying code. -- HAL: Enhanced Serial-USB driver using the new buffers queues object. -- HAL: Simplified USB driver, queued API has been removed. -- HAL: Enhanced the CAN driver with I-class functions. Now it is possible - to exchange frames from ISRs. -- HAL: Added watchdog driver model (WDG) and STM32 implementation on IWDG. -- HAL: Added synchronous API and mutual exclusion to the UART driver. -- HAL: Added PAL driver for STM32L4xx GPIOv3 peripheral. -- HAL: Added I2S driver for STM32 SPIv2 peripheral. -- HAL: Added demos an- d board files for ST's Nucleo32 boards (F031, F042, F303). -- HAL: Added "lines" handling to PAL driver, lines are identifiers of both - ports and pins encoded in a single value. Added a set of macros - operating on lines. -- HAL: Merged the latest STM32F3xx CMSIS headers. -- HAL: Merged the latest STM32F2xx CMSIS headers and fixed the support - broken in 3.0.x. -- RT: Added new function chVTGetTimersStateI() returning the state of the - timers list. -- HAL: Now STM32 USARTv2 driver initializes the ISR vectors statically on - initialization. Disabling them was not necessary and added to - the code size. -- HAL: Added DMA channel selection on STM32F030xC devices. -- HAL: Added serial driver support for USART 3..6 on STM32F030xC devices. -- HAL: Merged the newest ST header files for STM32F1xx. -- HAL: Added support for differential mode to the STM32F3xx ADC driver. -- HAL: Experimental isochronous capability added to STM32 OTGv1 driver. -- HAL: Modified the serial-USB driver to reject write/read attempts if the - underlying USB is not in active state. In case of disconnection the - SDU driver broadcasts a CHN_DISCONNECTED event. -- HAL: Modified the USB driver to have a separate USB_SUSPENDED state, this - allows the application to detect if the USB is communicating or if - it is disconnected or powered down. -- HAL: Added wake-up and suspend events to the STM32 OTGv1 driver. -- HAL: STM32 USB/OTG buffers and queues do not more require to be aligned in - position and size. -- VAR: Improved GCC rules.ld, now it is possible to assign the heap to any - of the available RAM regions. -- HAL: STM32 GPT, ICU and PWM driver enhancements. Now it is possible to - suppress default ISRs by defining STM32_TIMx_SUPPRESS_ISR. - The application is now able to define custom handlers if required - or simply save space if the driver callbacks are not used. - Now the functions xxx_lld_serve_interrupts() have global scope, this - way custom ISRs can call them from outside the driver module. -- HAL: Added TIM units use cross-check in STM32 GPT, ICU, PWM and ST drivers, - now use collisions are explicitly reported. -- NIL: Added polled delays required to fix bug #629. -- HAL: Added support for I2C3 and I2C4 to the STM32 I2Cv2 I2C driver. -- HAL: Added support for SPI4...SPI6 to the STM32 SPIv2 SPI driver. -- HAL: Added support for UART4...UART8 to the STM32 UARTv2 UART driver. -- HAL: Added support for UART7 and UART8,LPUART1 to the STM32 UARTv2 serial - driver. -- HAL: STM32F3xx and STM32L4xx devices now share the same ADCv3 driver. -- HAL: STM32F2xx, STM32F4xx and STM32F7xx devices now share the same ADCv2 - and DMAv2 drivers. -- HAL: STM32F0xx and STM32L0xx devices now share the same ADCv1 driver. -- HAL: STM32F0xx, STM32F1xx, STM32F3xx, STM32F37x, STM32L0xx and STM32L1xx - devices now share the same DMAv1 driver. -- HAL: New STM32 shared DMAv2 driver supporting channel selection and - data cache invalidation (F2, F4, F7). -- HAL: New STM32 shared DMAv1 driver supporting channel selection and fixing - the behavior with shared IRQs (F0, L0). -- HAL: New STM32 ADCv3 driver supporting middle STM32 devices (F3, L4). -- HAL: New STM32 ADCv2 driver supporting large STM32 devices (F2, F4, F7). -- HAL: New STM32 ADCv1 driver supporting small STM32 devices (F0, L0). -- HAL: Introduced support for TIM21 and TIM22 in STM32 ST driver. -- HAL: Updated STM32F0xx headers to STM32CubeF0 version 1.3.0. Added support - for STM32F030xC, STM32F070x6, STM32F070xB, STM32F091xC, - STM32F098xx devices. -- RT: Fixed ARM port enforcing THUMB mode (bug #687)(backported to 3.0.5). -- HAL: Fixed HAL drivers still calling RT functions (bug #686)(backported - to 3.0.5). -- HAL: Fixed chprintf() still calling RT functions (bug #684)(backported - to 3.0.5). -- HAL: Fixed STM32 ICU driver uses chSysLock and chSysUnlock (bug #681) - (backported to 3.0.4). -- HAL: Fixed wrong DMA priority assigned to STM32F3 ADC3&4 (bug #680) - (backported to 3.0.4 and 2.6.10). -- HAL: Fixed invalid DMA settings in STM32 DACv1 driver in dual mode - (bug #677)(backported to 3.0.4). -- HAL: Fixed usbStop() hangs in STM32 OTGv1 driver (bug #674)(backported - to 3.0.4 and 2.6.10). -- HAL: Fixed STM32 I2Cv2 driver fails on transfers greater than 255 bytes - (bug #673)(backported to 3.0.4). -- HAL: Fixed STM32 I2Cv2 DMA conflict (bug #671)(backported to 3.0.4). -- HAL: Fixed I2S clock selection not working in STM32F4xx HAL (bug #667) - (backported to 3.0.4 and 2.6.10). -- HAL: Fixed differences in STM32F3 ADC macro definitions (bug #665) - (backported to 3.0.3). -- HAL: Fixed RTC module loses day of week when converting (bug #664) - (backported to 3.0.3). -- HAL: Fixed STM32 USBv1 broken isochronous endpoints (bug #662) - (backported to 3.0.4). -- HAL: Fixed STM32 USBv1 wrong multiplier when calculating descriptor address - in BTABLE (bug #661)(backported to 3.0.4 and 2.6.10). -- HAL: Fixed STM32 USBv1 does not make use of BTABLE_ADDR define (bug #660) - (backported to 3.0.4 and 2.6.10). -- HAL: Fixed invalid class type for sdPutWouldBlock() and sdGetWouldBlock() - functions (bug #659)(backported to 3.0.3 and 2.6.10). -- HAL: Fixed STM32F0xx HAL missing MCOPRE support (bug #658). -- HAL: Fixed STM32L1xx HAL errors in comments (bug #657)(backported - to 3.0.3 and 2.6.10). -- HAL: Fixed STM32 USBv1 wrong buffer alignment (bug #656)(backported - to 3.0.3 and 2.6.10). -- HAL: Fixed wrong vector name for STM32F3xx EXTI33 (bug #655)(backported - to 3.0.3 and 2.6.10). -- HAL: Fixed nvicEnableVector broken for Cortex-M0 (bug #654)(backported - to 3.0.3). -- HAL: Fixed no demo for nucleo STM32F072RB board (bug #652). -- HAL: Fixed missing RCC and ISR definitions for STM32F0xx timers (bug #651) - (backported to 3.0.3 and 2.6.10). -- HAL: Fixed incorrect compiler check in STM32 RTCv1 driver (bug #650) - (backported to 3.0.3). -- HAL: Fixed incorrect case in path (bug #649). -- HAL: Fixed STM32F3xx HAL checking for non-existing macros (bug #648) - (backported to 3.0.3 and 2.6.10). -- HAL: Fixed error in STM32F030 EXT driver (bug #647)(backported to 3.0.3). -- RT: Fixed problem with chVTIsTimeWithinX() (bug #646)(backported to - 3.0.3 and 2.6.10). -- VAR: Fixed _sbrk_r with incr == 0 should be valid (bug #645)(backported to - 3.0.3 and 2.6.10). -- RT: Fixed issues in CMSIS RTOS interface (bug #644)(backported to 3.0.3). -- HAL: Fixed RT dependency in STM32 SDCv1 driver (bug #643)(backported - to 3.0.2). -- VAR: Fixed incorrect working area size in LwIP creation in demos (bug #642) - (backported to 3.0.2 and 2.6.10). -- HAL: Fixed error in hal_lld_f100.h checks (bug #641)(backported to 3.0.2 - and 2.6.10). -- HAL: Fixed volatile variable issue in I/O queues, both RT and HAL (bug #640) - (backported to 3.0.2). -- HAL: Fixed wrong DMA assignment for I2C1 in STM32F302xC registry (bug #637) - (backported to 3.0.2). -- HAL: Fixed missing timers 5, 6, 7, 10 & 11 from STM32L1 HAL port (bug #636) - (backported to 3.0.2). -- VAR: Fixed CRT0_CALL_DESTRUCTORS not utilized in crt0_v7m.s (bug #635) - (backported to 3.0.2). -- HAL: Fixed wrong ld file in STM32F072xB USB CDC demo (bug #634)(backported - to 3.0.2). -- NIL: Fixed Wrong assertion in NIL chSemResetI() and NIL OSAL - osalThreadDequeueAllI() (bug #633)(backported to 3.0.2). -- RT: Fixed problem with RT mutexes involving priority inheritance (bug #632) - (backported to 3.0.2 and 2.6.10). -- HAL: Fixed HAL to RT dependency in STM32 DAC driver (bug #631)(backported - to 3.0.2). -- HAL: Fixed problem with STM32 I2S driver restart (bug #630)(backported - to 3.0.2). -- HAL: Fixed STM32F3xx ADC driver uses US2RTC directly (bug #629)(backported - to 3.0.2). -- HAL: Fixed CEC clock cannot be disabled on STM32F0xx (bug #628) - (backported to 3.0.1). -- VAR: Fixed lwIP arch code breaks with a 16-bit systick timer (bug #627) - (backported to 3.0.1). -- HAL: Fixed broken MAC driver for STM32F107 (bug #626)(backported to 3.0.1). -- NIL: Fixed missing configuration options from NIL PPC port (bug #625) - (backported to 3.0.1). -- HAL: Fixed wrong offset in STM32 DAC driver (bug #624)(backported to 3.0.1). -- HAL: Fixed crash on STM32F030x4/6 devices (bug #623)(backported to 3.0.1). -- HAL: Fixed duplicated doxygen tag in STM32F4xx hal_lld.h file (bug #621) - (backported to 3.0.1 and 2.6.9). -- HAL: Fixed STM32F042 registry error (bug #620)(backported to 3.0.1). -- HAL: Fixed wrong check in canReceive() (bug #619)(backported to 3.0.1 - and 2.6.9). -- HAL: Fixed wrong EXTI[18] vector number on STM32F373 (bug #618)(backported - to 3.0.1 and 2.6.9). -- HAL: Fixed wrong check on STM32_LSE_ENABLED definition in STM32L1xx HAL port - (bug #617)(backported to 3.0.1 and 2.6.9). -- HAL: Fixed rtcConvertDateTimeToFAT() incorrect conversion (bug #615) - (backported to 3.0.1). -- HAL: Fixed missing UART7 and UART8 support on STM32F4xx family (bug #612). -- HAL: Fixed outdated CMSIS headers for STM32F1xx devices (bug #609). -- HAL: Fixed CAN errors (bug #387). -- HAL: Fixed USB HS ULPI Support (except board files because patch originally - targeted version 2.6.x)(bug #377). - -*** 3.0.0 *** -- NEW: Added an initialization function to the lwIP bindings, now it is - sufficient to call lwipInit(NULL); in order to start the subsystem. - Demo updated. -- RT: Fixed compilation error in RT when registry is disabled (bug #614). -- NIL: Fixed OSAL_ST_MODE not defined in AVR port (bug #613). -- NIL: Fixed nilrtos redefinition of systime_t (bug #611). -- HAL: Fixed TIM2 wrongly classified as 32bits in STM32F1xx devices - (bug #610). - -*** 3.0.0p6 *** -- HAL: Removed call to localtime_r() function for non-GNU compilers in - STM32F1xx RTC driver. -- DEM: Fixed the FatFS demo timeout, now it is expressed in milliseconds. -- DEM: Added -Wundef to all the demos and test programs in order to find - common error cases. -- NIL: Added INTC priorities check to the e200z port. -- RT: Added INTC priorities check to the e200z port. -- HAL: Added support for CAN in STM32F042/72 devices. -- HAL: Added support for extra DMA channels in STM32F072 devices. -- HAL: Modified the STM32 CAN driver to support unified IRQs. -- RT: SPE-related issue in e200z ports (bug #607). -- NIL: SPE-related issue in e200z ports (bug #607). -- HAL: Fixed dependency between STM32 MAC driver and RT (bug #606). -- HAL: Fixed wrong macro names in STM32F0xx HAL driver (bug #605). -- HAL: Fixed wrong check on ADC3 in STM32F3xx ADC driver (bug #604). -- HAL: Fixed wrong macro names in STM32F3xx HAL driver (bug #603). -- HAL: Fixed errors in STM32 OTGv1 driver (bug #601). -- DEM: Fixed missing paths in e200z demos (bug #600). -- HAL: Fixed error in platform_f105_f107.mk file (bug #599). -- HAL: Fixed issue in DMA drivers when channels share ISRs (bug #597). - -*** 3.0.0p5 *** -- HAL: Added no-DMA mode to the STM32 I2Cv2 driver. -- HAL: Added DAC support to all STM32 sub-platforms, added another demo for - the STM32F3xx. -- HAL: Fixed STM32 USARTv1: incorrect txend2_cb callback behavior (bug #596). -- DEM: Fixed wrong comment in ARMCM4-STM32F401RE-NUCLEO demo (bug #595). -- HAL: Fixed STM32 SDC LLD driver initialization with Asserts disabled - (bug #594). - -*** 3.0.0p4 *** -- NEW: Added no-DMA mode to STM32 I2Cv2 driver. -- BLD: New "smart build" mode added to makefiles, now only used files are - compiled. -- HAL: Change to the Serial_USB driver, now the INT endpoint is no more - mandatory. -- HAL: New DAC driver implementation for STM32F4xx. -- HAL: Fixed SDC STM32 driver broken in 50MHz mode (bug #592). -- HAL: Fixed STM32 RTC SSR Register Counts Down (bug #591). -- HAL: Fixed STM32 RTC PRER Register not being set in init (bug #590). -- HAL: Fixed STM32F334 does not have an EXT18 interrupt (bug #588). -- HAL: Fixed STM32L1xx USB is missing disconnect/connect macros (bug #587). -- HAL: Fixed wrong vector number for STM32L1xx USB (bug #586). -- HAL: Fixed spurious TC interrupt in STM32 UART (v1 and v2) driver (bug #584). -- HAL: Fixed invalid checks on STM32L1xx LSI and LSE clocks (bug #583). -- HAL: Fixed RCC CAN2 macros missing in STM32F1xx platform (bug #582). -- HAL: Fixed STM32 I2Cv2 driver issue (bug 581). -- BLD: Fixed ules.mk: adding "PRE_MAKE_ALL_RULE_HOOK" (bug #580). -- BLD: Fixed rules.mk should not explicitly depend on $(BUILDDIR) (bug #579). - -*** 3.0.0p3 *** -- RT: Fixed tickless mode instability in RT (bug 577). - -*** 3.0.0p2 *** -- HAL: Fixed instances of RT API in HAL drivers (bug 574). -- RT: Fixed system time overflow issue in tickless mode (bug 573). -- RT: Improvements to the IRQ_STORM applications. - -*** 3.0.0p1 *** -- First 3.0.0 release, see release note 3.0.0. diff --git a/firmware/chibios/boards/OLIMEX_STM32_E407/board.c b/firmware/chibios/boards/OLIMEX_STM32_E407/board.c deleted file mode 100644 index faeaf64dbd..0000000000 --- a/firmware/chibios/boards/OLIMEX_STM32_E407/board.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_PAL || defined(__DOXYGEN__) -/** - * @brief PAL setup. - * @details Digital I/O ports static configuration as defined in @p board.h. - * This variable is used by the HAL when initializing the PAL driver. - */ -const PALConfig pal_default_config = -{ - {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, - VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, - {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, - VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, - {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, - VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, - {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, - VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, - {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, - VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, - {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, - VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, - {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, - VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, - {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, - VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, - {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, - VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH} -}; -#endif - -/** - * @brief Early initialization code. - * @details This initialization must be performed just after stack setup - * and before any other initialization. - */ -void __early_init(void) { - - stm32_clock_init(); -} - -#if HAL_USE_SDC || defined(__DOXYGEN__) -/** - * @brief SDC card detection. - */ -bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) { - static bool_t last_status = FALSE; - - if (blkIsTransferring(sdcp)) - return last_status; - return last_status = (bool_t)palReadPad(GPIOC, GPIOC_SD_D3); -} - -/** - * @brief SDC card write protection detection. - */ -bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) { - - (void)sdcp; - return FALSE; -} -#endif /* HAL_USE_SDC */ - -#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) -/** - * @brief MMC_SPI card detection. - */ -bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return TRUE; -} - -/** - * @brief MMC_SPI card write protection detection. - */ -bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return FALSE; -} -#endif - -/** - * @brief Board-specific initialization code. - * @todo Add your board-specific code, if any. - */ -void boardInit(void) { -} diff --git a/firmware/chibios/boards/OLIMEX_STM32_E407/board.h b/firmware/chibios/boards/OLIMEX_STM32_E407/board.h deleted file mode 100644 index 413904a33e..0000000000 --- a/firmware/chibios/boards/OLIMEX_STM32_E407/board.h +++ /dev/null @@ -1,1300 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -/* - * Setup for Olimex STM32-E407 board. - */ - -/* - * Board identifier. - */ -#define BOARD_OLIMEX_STM32_E407 -#define BOARD_NAME "Olimex STM32-E407" - -/* - * Ethernet PHY type. - */ -#define BOARD_PHY_ID MII_KS8721_ID -#define BOARD_PHY_RMII - -/* - * Board oscillators-related settings. - */ -#if !defined(STM32_LSECLK) -#define STM32_LSECLK 32768 -#endif - -#if !defined(STM32_HSECLK) -#define STM32_HSECLK 12000000 -#endif - -/* - * Board voltages. - * Required for performance limits calculation. - */ -#define STM32_VDD 330 - -/* - * MCU type as defined in the ST header. - */ -#define STM32F40_41xxx - -/* - * IO pins assignments. - */ -#define GPIOA_BUTTON_WKUP 0 -#define GPIOA_ETH_RMII_REF_CLK 1 -#define GPIOA_ETH_RMII_MDIO 2 -#define GPIOA_ETH_RMII_MDINT 3 -#define GPIOA_PIN4 4 -#define GPIOA_PIN5 5 -#define GPIOA_PIN6 6 -#define GPIOA_ETH_RMII_CRS_DV 7 -#define GPIOA_USB_HS_BUSON 8 -#define GPIOA_OTG_FS_VBUS 9 -#define GPIOA_OTG_FS_ID 10 -#define GPIOA_OTG_FS_DM 11 -#define GPIOA_OTG_FS_DP 12 -#define GPIOA_JTAG_TMS 13 -#define GPIOA_JTAG_TCK 14 -#define GPIOA_JTAG_TDI 15 - -#define GPIOB_USB_FS_BUSON 0 -#define GPIOB_USB_HS_FAULT 1 -#define GPIOB_BOOT1 2 -#define GPIOB_JTAG_TDO 3 -#define GPIOB_JTAG_TRST 4 -#define GPIOB_PIN5 5 -#define GPIOB_PIN6 6 -#define GPIOB_PIN7 7 -#define GPIOB_I2C1_SCL 8 -#define GPIOB_I2C1_SDA 9 -#define GPIOB_SPI2_SCK 10 -#define GPIOB_PIN11 11 -#define GPIOB_OTG_HS_ID 12 -#define GPIOB_OTG_HS_VBUS 13 -#define GPIOB_OTG_HS_DM 14 -#define GPIOB_OTG_HS_DP 15 - -#define GPIOC_PIN0 0 -#define GPIOC_ETH_RMII_MDC 1 -#define GPIOC_SPI2_MISO 2 -#define GPIOC_SPI2_MOSI 3 -#define GPIOC_ETH_RMII_RXD0 4 -#define GPIOC_ETH_RMII_RXD1 5 -#define GPIOC_USART6_TX 6 -#define GPIOC_USART6_RX 7 -#define GPIOC_SD_D0 8 -#define GPIOC_SD_D1 9 -#define GPIOC_SD_D2 10 -#define GPIOC_SD_D3 11 -#define GPIOC_SD_CLK 12 -#define GPIOC_LED 13 -#define GPIOC_OSC32_IN 14 -#define GPIOC_OSC32_OUT 15 - -#define GPIOD_PIN0 0 -#define GPIOD_PIN1 1 -#define GPIOD_SD_CMD 2 -#define GPIOD_PIN3 3 -#define GPIOD_PIN4 4 -#define GPIOD_PIN5 5 -#define GPIOD_PIN6 6 -#define GPIOD_PIN7 7 -#define GPIOD_PIN8 8 -#define GPIOD_PIN9 9 -#define GPIOD_PIN10 10 -#define GPIOD_PIN11 11 -#define GPIOD_PIN12 12 -#define GPIOD_PIN13 13 -#define GPIOD_PIN14 14 -#define GPIOD_PIN15 15 - -#define GPIOE_PIN0 0 -#define GPIOE_PIN1 1 -#define GPIOE_PIN2 2 -#define GPIOE_PIN3 3 -#define GPIOE_PIN4 4 -#define GPIOE_PIN5 5 -#define GPIOE_PIN6 6 -#define GPIOE_PIN7 7 -#define GPIOE_PIN8 8 -#define GPIOE_PIN9 9 -#define GPIOE_PIN10 10 -#define GPIOE_PIN11 11 -#define GPIOE_PIN12 12 -#define GPIOE_PIN13 13 -#define GPIOE_PIN14 14 -#define GPIOE_PIN15 15 - -#define GPIOF_PIN0 0 -#define GPIOF_PIN1 1 -#define GPIOF_PIN2 2 -#define GPIOF_PIN3 3 -#define GPIOF_PIN4 4 -#define GPIOF_PIN5 5 -#define GPIOF_PIN6 6 -#define GPIOF_PIN7 7 -#define GPIOF_PIN8 8 -#define GPIOF_PIN9 9 -#define GPIOF_PIN10 10 -#define GPIOF_USB_FS_FAULT 11 -#define GPIOF_PIN12 12 -#define GPIOF_PIN13 13 -#define GPIOF_PIN14 14 -#define GPIOF_PIN15 15 - -#define GPIOG_PIN0 0 -#define GPIOG_PIN1 1 -#define GPIOG_PIN2 2 -#define GPIOG_PIN3 3 -#define GPIOG_PIN4 4 -#define GPIOG_PIN5 5 -#define GPIOG_PIN6 6 -#define GPIOG_PIN7 7 -#define GPIOG_PIN8 8 -#define GPIOG_PIN9 9 -#define GPIOG_SPI2_CS 10 -#define GPIOG_ETH_RMII_TXEN 11 -#define GPIOG_PIN12 12 -#define GPIOG_ETH_RMII_TXD0 13 -#define GPIOG_ETH_RMII_TXD1 14 -#define GPIOG_PIN15 15 - -#define GPIOH_OSC_IN 0 -#define GPIOH_OSC_OUT 1 -#define GPIOH_PIN2 2 -#define GPIOH_PIN3 3 -#define GPIOH_PIN4 4 -#define GPIOH_PIN5 5 -#define GPIOH_PIN6 6 -#define GPIOH_PIN7 7 -#define GPIOH_PIN8 8 -#define GPIOH_PIN9 9 -#define GPIOH_PIN10 10 -#define GPIOH_PIN11 11 -#define GPIOH_PIN12 12 -#define GPIOH_PIN13 13 -#define GPIOH_PIN14 14 -#define GPIOH_PIN15 15 - -#define GPIOI_PIN0 0 -#define GPIOI_PIN1 1 -#define GPIOI_PIN2 2 -#define GPIOI_PIN3 3 -#define GPIOI_PIN4 4 -#define GPIOI_PIN5 5 -#define GPIOI_PIN6 6 -#define GPIOI_PIN7 7 -#define GPIOI_PIN8 8 -#define GPIOI_PIN9 9 -#define GPIOI_PIN10 10 -#define GPIOI_PIN11 11 -#define GPIOI_PIN12 12 -#define GPIOI_PIN13 13 -#define GPIOI_PIN14 14 -#define GPIOI_PIN15 15 - -/* - * I/O ports initial setup, this configuration is established soon after reset - * in the initialization code. - * Please refer to the STM32 Reference Manual for details. - */ -#define PIN_MODE_INPUT(n) (0U << ((n) * 2)) -#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2)) -#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2)) -#define PIN_MODE_ANALOG(n) (3U << ((n) * 2)) -#define PIN_ODR_LOW(n) (0U << (n)) -#define PIN_ODR_HIGH(n) (1U << (n)) -#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) -#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) -#define PIN_OSPEED_2M(n) (0U << ((n) * 2)) -#define PIN_OSPEED_25M(n) (1U << ((n) * 2)) -#define PIN_OSPEED_50M(n) (2U << ((n) * 2)) -#define PIN_OSPEED_100M(n) (3U << ((n) * 2)) -#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2)) -#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2)) -#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2)) -#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4)) - -/* - * GPIOA setup: - * - * PA0 - BUTTON_WKUP (input floating). - * PA1 - ETH_RMII_REF_CLK (alternate 11). - * PA2 - ETH_RMII_MDIO (alternate 11). - * PA3 - ETH_RMII_MDINT (input floating). - * PA4 - PIN4 (input pullup). - * PA5 - PIN5 (input pullup). - * PA6 - PIN6 (input pullup). - * PA7 - ETH_RMII_CRS_DV (alternate 11). - * PA8 - USB_HS_BUSON (output pushpull maximum). - * PA9 - OTG_FS_VBUS (input pulldown). - * PA10 - OTG_FS_ID (alternate 10). - * PA11 - OTG_FS_DM (alternate 10). - * PA12 - OTG_FS_DP (alternate 10). - * PA13 - JTAG_TMS (alternate 0). - * PA14 - JTAG_TCK (alternate 0). - * PA15 - JTAG_TDI (alternate 0). - */ -#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON_WKUP) | \ - PIN_MODE_ALTERNATE(GPIOA_ETH_RMII_REF_CLK) |\ - PIN_MODE_ALTERNATE(GPIOA_ETH_RMII_MDIO) |\ - PIN_MODE_INPUT(GPIOA_ETH_RMII_MDINT) | \ - PIN_MODE_INPUT(GPIOA_PIN4) | \ - PIN_MODE_INPUT(GPIOA_PIN5) | \ - PIN_MODE_INPUT(GPIOA_PIN6) | \ - PIN_MODE_ALTERNATE(GPIOA_ETH_RMII_CRS_DV) |\ - PIN_MODE_OUTPUT(GPIOA_USB_HS_BUSON) | \ - PIN_MODE_INPUT(GPIOA_OTG_FS_VBUS) | \ - PIN_MODE_ALTERNATE(GPIOA_OTG_FS_ID) | \ - PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \ - PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \ - PIN_MODE_ALTERNATE(GPIOA_JTAG_TMS) | \ - PIN_MODE_ALTERNATE(GPIOA_JTAG_TCK) | \ - PIN_MODE_ALTERNATE(GPIOA_JTAG_TDI)) -#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON_WKUP) |\ - PIN_OTYPE_PUSHPULL(GPIOA_ETH_RMII_REF_CLK) |\ - PIN_OTYPE_PUSHPULL(GPIOA_ETH_RMII_MDIO) |\ - PIN_OTYPE_PUSHPULL(GPIOA_ETH_RMII_MDINT) |\ - PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOA_ETH_RMII_CRS_DV) |\ - PIN_OTYPE_PUSHPULL(GPIOA_USB_HS_BUSON) |\ - PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_VBUS) |\ - PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_ID) | \ - PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \ - PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \ - PIN_OTYPE_PUSHPULL(GPIOA_JTAG_TMS) | \ - PIN_OTYPE_PUSHPULL(GPIOA_JTAG_TCK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_JTAG_TDI)) -#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_100M(GPIOA_BUTTON_WKUP) | \ - PIN_OSPEED_100M(GPIOA_ETH_RMII_REF_CLK) |\ - PIN_OSPEED_100M(GPIOA_ETH_RMII_MDIO) | \ - PIN_OSPEED_100M(GPIOA_ETH_RMII_MDINT) |\ - PIN_OSPEED_100M(GPIOA_PIN4) | \ - PIN_OSPEED_100M(GPIOA_PIN5) | \ - PIN_OSPEED_100M(GPIOA_PIN6) | \ - PIN_OSPEED_100M(GPIOA_ETH_RMII_CRS_DV) |\ - PIN_OSPEED_100M(GPIOA_USB_HS_BUSON) | \ - PIN_OSPEED_100M(GPIOA_OTG_FS_VBUS) | \ - PIN_OSPEED_100M(GPIOA_OTG_FS_ID) | \ - PIN_OSPEED_100M(GPIOA_OTG_FS_DM) | \ - PIN_OSPEED_100M(GPIOA_OTG_FS_DP) | \ - PIN_OSPEED_100M(GPIOA_JTAG_TMS) | \ - PIN_OSPEED_100M(GPIOA_JTAG_TCK) | \ - PIN_OSPEED_100M(GPIOA_JTAG_TDI)) -#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_BUTTON_WKUP) |\ - PIN_PUPDR_FLOATING(GPIOA_ETH_RMII_REF_CLK) |\ - PIN_PUPDR_FLOATING(GPIOA_ETH_RMII_MDIO) |\ - PIN_PUPDR_FLOATING(GPIOA_ETH_RMII_MDINT) |\ - PIN_PUPDR_PULLUP(GPIOA_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOA_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOA_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOA_ETH_RMII_CRS_DV) |\ - PIN_PUPDR_FLOATING(GPIOA_USB_HS_BUSON) |\ - PIN_PUPDR_PULLDOWN(GPIOA_OTG_FS_VBUS) |\ - PIN_PUPDR_FLOATING(GPIOA_OTG_FS_ID) | \ - PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \ - PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \ - PIN_PUPDR_FLOATING(GPIOA_JTAG_TMS) | \ - PIN_PUPDR_PULLDOWN(GPIOA_JTAG_TCK) | \ - PIN_PUPDR_FLOATING(GPIOA_JTAG_TDI)) -#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_BUTTON_WKUP) | \ - PIN_ODR_HIGH(GPIOA_ETH_RMII_REF_CLK) | \ - PIN_ODR_HIGH(GPIOA_ETH_RMII_MDIO) | \ - PIN_ODR_HIGH(GPIOA_ETH_RMII_MDINT) | \ - PIN_ODR_HIGH(GPIOA_PIN4) | \ - PIN_ODR_HIGH(GPIOA_PIN5) | \ - PIN_ODR_HIGH(GPIOA_PIN6) | \ - PIN_ODR_HIGH(GPIOA_ETH_RMII_CRS_DV) | \ - PIN_ODR_LOW(GPIOA_USB_HS_BUSON) | \ - PIN_ODR_HIGH(GPIOA_OTG_FS_VBUS) | \ - PIN_ODR_HIGH(GPIOA_OTG_FS_ID) | \ - PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \ - PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \ - PIN_ODR_HIGH(GPIOA_JTAG_TMS) | \ - PIN_ODR_HIGH(GPIOA_JTAG_TCK) | \ - PIN_ODR_HIGH(GPIOA_JTAG_TDI)) -#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON_WKUP, 0) | \ - PIN_AFIO_AF(GPIOA_ETH_RMII_REF_CLK, 11) |\ - PIN_AFIO_AF(GPIOA_ETH_RMII_MDIO, 11) | \ - PIN_AFIO_AF(GPIOA_ETH_RMII_MDINT, 0) | \ - PIN_AFIO_AF(GPIOA_PIN4, 0) | \ - PIN_AFIO_AF(GPIOA_PIN5, 0) | \ - PIN_AFIO_AF(GPIOA_PIN6, 0) | \ - PIN_AFIO_AF(GPIOA_ETH_RMII_CRS_DV, 11)) -#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_USB_HS_BUSON, 0) | \ - PIN_AFIO_AF(GPIOA_OTG_FS_VBUS, 0) | \ - PIN_AFIO_AF(GPIOA_OTG_FS_ID, 10) | \ - PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) | \ - PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) | \ - PIN_AFIO_AF(GPIOA_JTAG_TMS, 0) | \ - PIN_AFIO_AF(GPIOA_JTAG_TCK, 0) | \ - PIN_AFIO_AF(GPIOA_JTAG_TDI, 0)) - -/* - * GPIOB setup: - * - * PB0 - USB_FS_BUSON (output pushpull maximum). - * PB1 - USB_HS_FAULT (input floating). - * PB2 - BOOT1 (input floating). - * PB3 - JTAG_TDO (alternate 0). - * PB4 - JTAG_TRST (alternate 0). - * PB5 - PIN5 (input pullup). - * PB6 - PIN6 (input pullup). - * PB7 - PIN7 (input pullup). - * PB8 - I2C1_SCL (alternate 4). - * PB9 - I2C1_SDA (alternate 4). - * PB10 - SPI2_SCK (alternate 5). - * PB11 - PIN11 (input pullup). - * PB12 - OTG_HS_ID (alternate 12). - * PB13 - OTG_HS_VBUS (input pulldown). - * PB14 - OTG_HS_DM (alternate 12). - * PB15 - OTG_HS_DP (alternate 12). - */ -#define VAL_GPIOB_MODER (PIN_MODE_OUTPUT(GPIOB_USB_FS_BUSON) | \ - PIN_MODE_INPUT(GPIOB_USB_HS_FAULT) | \ - PIN_MODE_INPUT(GPIOB_BOOT1) | \ - PIN_MODE_ALTERNATE(GPIOB_JTAG_TDO) | \ - PIN_MODE_ALTERNATE(GPIOB_JTAG_TRST) | \ - PIN_MODE_INPUT(GPIOB_PIN5) | \ - PIN_MODE_INPUT(GPIOB_PIN6) | \ - PIN_MODE_INPUT(GPIOB_PIN7) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \ - PIN_MODE_ALTERNATE(GPIOB_SPI2_SCK) | \ - PIN_MODE_INPUT(GPIOB_PIN11) | \ - PIN_MODE_ALTERNATE(GPIOB_OTG_HS_ID) | \ - PIN_MODE_INPUT(GPIOB_OTG_HS_VBUS) | \ - PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DM) | \ - PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DP)) -#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_USB_FS_BUSON) |\ - PIN_OTYPE_PUSHPULL(GPIOB_USB_HS_FAULT) |\ - PIN_OTYPE_PUSHPULL(GPIOB_BOOT1) | \ - PIN_OTYPE_PUSHPULL(GPIOB_JTAG_TDO) | \ - PIN_OTYPE_PUSHPULL(GPIOB_JTAG_TRST) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) | \ - PIN_OTYPE_PUSHPULL(GPIOB_SPI2_SCK) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_ID) | \ - PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_VBUS) |\ - PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_DM) | \ - PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_DP)) -#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_100M(GPIOB_USB_FS_BUSON) | \ - PIN_OSPEED_100M(GPIOB_USB_HS_FAULT) | \ - PIN_OSPEED_100M(GPIOB_BOOT1) | \ - PIN_OSPEED_100M(GPIOB_JTAG_TDO) | \ - PIN_OSPEED_100M(GPIOB_JTAG_TRST) | \ - PIN_OSPEED_100M(GPIOB_PIN5) | \ - PIN_OSPEED_100M(GPIOB_PIN6) | \ - PIN_OSPEED_100M(GPIOB_PIN7) | \ - PIN_OSPEED_100M(GPIOB_I2C1_SCL) | \ - PIN_OSPEED_100M(GPIOB_I2C1_SDA) | \ - PIN_OSPEED_100M(GPIOB_SPI2_SCK) | \ - PIN_OSPEED_100M(GPIOB_PIN11) | \ - PIN_OSPEED_100M(GPIOB_OTG_HS_ID) | \ - PIN_OSPEED_100M(GPIOB_OTG_HS_VBUS) | \ - PIN_OSPEED_100M(GPIOB_OTG_HS_DM) | \ - PIN_OSPEED_100M(GPIOB_OTG_HS_DP)) -#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_USB_FS_BUSON) |\ - PIN_PUPDR_FLOATING(GPIOB_USB_HS_FAULT) |\ - PIN_PUPDR_FLOATING(GPIOB_BOOT1) | \ - PIN_PUPDR_FLOATING(GPIOB_JTAG_TDO) | \ - PIN_PUPDR_FLOATING(GPIOB_JTAG_TRST) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOB_I2C1_SCL) | \ - PIN_PUPDR_FLOATING(GPIOB_I2C1_SDA) | \ - PIN_PUPDR_FLOATING(GPIOB_SPI2_SCK) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOB_OTG_HS_ID) | \ - PIN_PUPDR_PULLDOWN(GPIOB_OTG_HS_VBUS) |\ - PIN_PUPDR_FLOATING(GPIOB_OTG_HS_DM) | \ - PIN_PUPDR_FLOATING(GPIOB_OTG_HS_DP)) -#define VAL_GPIOB_ODR (PIN_ODR_LOW(GPIOB_USB_FS_BUSON) | \ - PIN_ODR_HIGH(GPIOB_USB_HS_FAULT) | \ - PIN_ODR_HIGH(GPIOB_BOOT1) | \ - PIN_ODR_HIGH(GPIOB_JTAG_TDO) | \ - PIN_ODR_HIGH(GPIOB_JTAG_TRST) | \ - PIN_ODR_HIGH(GPIOB_PIN5) | \ - PIN_ODR_HIGH(GPIOB_PIN6) | \ - PIN_ODR_HIGH(GPIOB_PIN7) | \ - PIN_ODR_HIGH(GPIOB_I2C1_SCL) | \ - PIN_ODR_HIGH(GPIOB_I2C1_SDA) | \ - PIN_ODR_HIGH(GPIOB_SPI2_SCK) | \ - PIN_ODR_HIGH(GPIOB_PIN11) | \ - PIN_ODR_HIGH(GPIOB_OTG_HS_ID) | \ - PIN_ODR_HIGH(GPIOB_OTG_HS_VBUS) | \ - PIN_ODR_HIGH(GPIOB_OTG_HS_DM) | \ - PIN_ODR_HIGH(GPIOB_OTG_HS_DP)) -#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_USB_FS_BUSON, 0) | \ - PIN_AFIO_AF(GPIOB_USB_HS_FAULT, 0) | \ - PIN_AFIO_AF(GPIOB_BOOT1, 0) | \ - PIN_AFIO_AF(GPIOB_JTAG_TDO, 0) | \ - PIN_AFIO_AF(GPIOB_JTAG_TRST, 0) | \ - PIN_AFIO_AF(GPIOB_PIN5, 0) | \ - PIN_AFIO_AF(GPIOB_PIN6, 0) | \ - PIN_AFIO_AF(GPIOB_PIN7, 0)) -#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_I2C1_SCL, 4) | \ - PIN_AFIO_AF(GPIOB_I2C1_SDA, 4) | \ - PIN_AFIO_AF(GPIOB_SPI2_SCK, 5) | \ - PIN_AFIO_AF(GPIOB_PIN11, 0) | \ - PIN_AFIO_AF(GPIOB_OTG_HS_ID, 12) | \ - PIN_AFIO_AF(GPIOB_OTG_HS_VBUS, 0) | \ - PIN_AFIO_AF(GPIOB_OTG_HS_DM, 12) | \ - PIN_AFIO_AF(GPIOB_OTG_HS_DP, 12)) - -/* - * GPIOC setup: - * - * PC0 - PIN0 (input pullup). - * PC1 - ETH_RMII_MDC (alternate 11). - * PC2 - SPI2_MISO (alternate 5). - * PC3 - SPI2_MOSI (alternate 5). - * PC4 - ETH_RMII_RXD0 (alternate 11). - * PC5 - ETH_RMII_RXD1 (alternate 11). - * PC6 - USART6_TX (alternate 8). - * PC7 - USART6_RX (alternate 8). - * PC8 - SD_D0 (alternate 12). - * PC9 - SD_D1 (alternate 12). - * PC10 - SD_D2 (alternate 12). - * PC11 - SD_D3 (alternate 12). - * PC12 - SD_CLK (alternate 12). - * PC13 - LED (output pushpull maximum). - * PC14 - OSC32_IN (input floating). - * PC15 - OSC32_OUT (input floating). - */ -#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \ - PIN_MODE_ALTERNATE(GPIOC_ETH_RMII_MDC) |\ - PIN_MODE_ALTERNATE(GPIOC_SPI2_MISO) | \ - PIN_MODE_ALTERNATE(GPIOC_SPI2_MOSI) | \ - PIN_MODE_ALTERNATE(GPIOC_ETH_RMII_RXD0) |\ - PIN_MODE_ALTERNATE(GPIOC_ETH_RMII_RXD1) |\ - PIN_MODE_ALTERNATE(GPIOC_USART6_TX) | \ - PIN_MODE_ALTERNATE(GPIOC_USART6_RX) | \ - PIN_MODE_ALTERNATE(GPIOC_SD_D0) | \ - PIN_MODE_ALTERNATE(GPIOC_SD_D1) | \ - PIN_MODE_ALTERNATE(GPIOC_SD_D2) | \ - PIN_MODE_ALTERNATE(GPIOC_SD_D3) | \ - PIN_MODE_ALTERNATE(GPIOC_SD_CLK) | \ - PIN_MODE_OUTPUT(GPIOC_LED) | \ - PIN_MODE_INPUT(GPIOC_OSC32_IN) | \ - PIN_MODE_INPUT(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOC_ETH_RMII_MDC) |\ - PIN_OTYPE_PUSHPULL(GPIOC_SPI2_MISO) | \ - PIN_OTYPE_PUSHPULL(GPIOC_SPI2_MOSI) | \ - PIN_OTYPE_PUSHPULL(GPIOC_ETH_RMII_RXD0) |\ - PIN_OTYPE_PUSHPULL(GPIOC_ETH_RMII_RXD1) |\ - PIN_OTYPE_PUSHPULL(GPIOC_USART6_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOC_USART6_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOC_SD_D0) | \ - PIN_OTYPE_PUSHPULL(GPIOC_SD_D1) | \ - PIN_OTYPE_PUSHPULL(GPIOC_SD_D2) | \ - PIN_OTYPE_PUSHPULL(GPIOC_SD_D3) | \ - PIN_OTYPE_PUSHPULL(GPIOC_SD_CLK) | \ - PIN_OTYPE_PUSHPULL(GPIOC_LED) | \ - PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_100M(GPIOC_PIN0) | \ - PIN_OSPEED_100M(GPIOC_ETH_RMII_MDC) | \ - PIN_OSPEED_100M(GPIOC_SPI2_MISO) | \ - PIN_OSPEED_100M(GPIOC_SPI2_MOSI) | \ - PIN_OSPEED_100M(GPIOC_ETH_RMII_RXD0) | \ - PIN_OSPEED_100M(GPIOC_ETH_RMII_RXD1) | \ - PIN_OSPEED_100M(GPIOC_USART6_TX) | \ - PIN_OSPEED_100M(GPIOC_USART6_RX) | \ - PIN_OSPEED_100M(GPIOC_SD_D0) | \ - PIN_OSPEED_100M(GPIOC_SD_D1) | \ - PIN_OSPEED_100M(GPIOC_SD_D2) | \ - PIN_OSPEED_100M(GPIOC_SD_D3) | \ - PIN_OSPEED_100M(GPIOC_SD_CLK) | \ - PIN_OSPEED_100M(GPIOC_LED) | \ - PIN_OSPEED_100M(GPIOC_OSC32_IN) | \ - PIN_OSPEED_100M(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOC_ETH_RMII_MDC) |\ - PIN_PUPDR_FLOATING(GPIOC_SPI2_MISO) | \ - PIN_PUPDR_FLOATING(GPIOC_SPI2_MOSI) | \ - PIN_PUPDR_FLOATING(GPIOC_ETH_RMII_RXD0) |\ - PIN_PUPDR_FLOATING(GPIOC_ETH_RMII_RXD1) |\ - PIN_PUPDR_FLOATING(GPIOC_USART6_TX) | \ - PIN_PUPDR_FLOATING(GPIOC_USART6_RX) | \ - PIN_PUPDR_FLOATING(GPIOC_SD_D0) | \ - PIN_PUPDR_FLOATING(GPIOC_SD_D1) | \ - PIN_PUPDR_FLOATING(GPIOC_SD_D2) | \ - PIN_PUPDR_FLOATING(GPIOC_SD_D3) | \ - PIN_PUPDR_FLOATING(GPIOC_SD_CLK) | \ - PIN_PUPDR_FLOATING(GPIOC_LED) | \ - PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ - PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ - PIN_ODR_HIGH(GPIOC_ETH_RMII_MDC) | \ - PIN_ODR_HIGH(GPIOC_SPI2_MISO) | \ - PIN_ODR_HIGH(GPIOC_SPI2_MOSI) | \ - PIN_ODR_HIGH(GPIOC_ETH_RMII_RXD0) | \ - PIN_ODR_HIGH(GPIOC_ETH_RMII_RXD1) | \ - PIN_ODR_HIGH(GPIOC_USART6_TX) | \ - PIN_ODR_HIGH(GPIOC_USART6_RX) | \ - PIN_ODR_HIGH(GPIOC_SD_D0) | \ - PIN_ODR_HIGH(GPIOC_SD_D1) | \ - PIN_ODR_HIGH(GPIOC_SD_D2) | \ - PIN_ODR_HIGH(GPIOC_SD_D3) | \ - PIN_ODR_HIGH(GPIOC_SD_CLK) | \ - PIN_ODR_HIGH(GPIOC_LED) | \ - PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ - PIN_ODR_HIGH(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0) | \ - PIN_AFIO_AF(GPIOC_ETH_RMII_MDC, 11) | \ - PIN_AFIO_AF(GPIOC_SPI2_MISO, 5) | \ - PIN_AFIO_AF(GPIOC_SPI2_MOSI, 5) | \ - PIN_AFIO_AF(GPIOC_ETH_RMII_RXD0, 11) | \ - PIN_AFIO_AF(GPIOC_ETH_RMII_RXD1, 11) | \ - PIN_AFIO_AF(GPIOC_USART6_TX, 8) | \ - PIN_AFIO_AF(GPIOC_USART6_RX, 8)) -#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_SD_D0, 12) | \ - PIN_AFIO_AF(GPIOC_SD_D1, 12) | \ - PIN_AFIO_AF(GPIOC_SD_D2, 12) | \ - PIN_AFIO_AF(GPIOC_SD_D3, 12) | \ - PIN_AFIO_AF(GPIOC_SD_CLK, 12) | \ - PIN_AFIO_AF(GPIOC_LED, 0) | \ - PIN_AFIO_AF(GPIOC_OSC32_IN, 0) | \ - PIN_AFIO_AF(GPIOC_OSC32_OUT, 0)) - -/* - * GPIOD setup: - * - * PD0 - PIN0 (input pullup). - * PD1 - PIN1 (input pullup). - * PD2 - SD_CMD (alternate 12). - * PD3 - PIN3 (input pullup). - * PD4 - PIN4 (input pullup). - * PD5 - PIN5 (input pullup). - * PD6 - PIN6 (input pullup). - * PD7 - PIN7 (input pullup). - * PD8 - PIN8 (input pullup). - * PD9 - PIN9 (input pullup). - * PD10 - PIN10 (input pullup). - * PD11 - PIN11 (input pullup). - * PD12 - PIN12 (input pullup). - * PD13 - PIN13 (input pullup). - * PD14 - PIN14 (input pullup). - * PD15 - PIN15 (input pullup). - */ -#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \ - PIN_MODE_INPUT(GPIOD_PIN1) | \ - PIN_MODE_ALTERNATE(GPIOD_SD_CMD) | \ - PIN_MODE_INPUT(GPIOD_PIN3) | \ - PIN_MODE_INPUT(GPIOD_PIN4) | \ - PIN_MODE_INPUT(GPIOD_PIN5) | \ - PIN_MODE_INPUT(GPIOD_PIN6) | \ - PIN_MODE_INPUT(GPIOD_PIN7) | \ - PIN_MODE_INPUT(GPIOD_PIN8) | \ - PIN_MODE_INPUT(GPIOD_PIN9) | \ - PIN_MODE_INPUT(GPIOD_PIN10) | \ - PIN_MODE_INPUT(GPIOD_PIN11) | \ - PIN_MODE_INPUT(GPIOD_PIN12) | \ - PIN_MODE_INPUT(GPIOD_PIN13) | \ - PIN_MODE_INPUT(GPIOD_PIN14) | \ - PIN_MODE_INPUT(GPIOD_PIN15)) -#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOD_SD_CMD) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) -#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_100M(GPIOD_PIN0) | \ - PIN_OSPEED_100M(GPIOD_PIN1) | \ - PIN_OSPEED_100M(GPIOD_SD_CMD) | \ - PIN_OSPEED_100M(GPIOD_PIN3) | \ - PIN_OSPEED_100M(GPIOD_PIN4) | \ - PIN_OSPEED_100M(GPIOD_PIN5) | \ - PIN_OSPEED_100M(GPIOD_PIN6) | \ - PIN_OSPEED_100M(GPIOD_PIN7) | \ - PIN_OSPEED_100M(GPIOD_PIN8) | \ - PIN_OSPEED_100M(GPIOD_PIN9) | \ - PIN_OSPEED_100M(GPIOD_PIN10) | \ - PIN_OSPEED_100M(GPIOD_PIN11) | \ - PIN_OSPEED_100M(GPIOD_PIN12) | \ - PIN_OSPEED_100M(GPIOD_PIN13) | \ - PIN_OSPEED_100M(GPIOD_PIN14) | \ - PIN_OSPEED_100M(GPIOD_PIN15)) -#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOD_SD_CMD) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN15)) -#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ - PIN_ODR_HIGH(GPIOD_PIN1) | \ - PIN_ODR_HIGH(GPIOD_SD_CMD) | \ - PIN_ODR_HIGH(GPIOD_PIN3) | \ - PIN_ODR_HIGH(GPIOD_PIN4) | \ - PIN_ODR_HIGH(GPIOD_PIN5) | \ - PIN_ODR_HIGH(GPIOD_PIN6) | \ - PIN_ODR_HIGH(GPIOD_PIN7) | \ - PIN_ODR_HIGH(GPIOD_PIN8) | \ - PIN_ODR_HIGH(GPIOD_PIN9) | \ - PIN_ODR_HIGH(GPIOD_PIN10) | \ - PIN_ODR_HIGH(GPIOD_PIN11) | \ - PIN_ODR_HIGH(GPIOD_PIN12) | \ - PIN_ODR_HIGH(GPIOD_PIN13) | \ - PIN_ODR_HIGH(GPIOD_PIN14) | \ - PIN_ODR_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0) | \ - PIN_AFIO_AF(GPIOD_PIN1, 0) | \ - PIN_AFIO_AF(GPIOD_SD_CMD, 12) | \ - PIN_AFIO_AF(GPIOD_PIN3, 0) | \ - PIN_AFIO_AF(GPIOD_PIN4, 0) | \ - PIN_AFIO_AF(GPIOD_PIN5, 0) | \ - PIN_AFIO_AF(GPIOD_PIN6, 0) | \ - PIN_AFIO_AF(GPIOD_PIN7, 0)) -#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0) | \ - PIN_AFIO_AF(GPIOD_PIN9, 0) | \ - PIN_AFIO_AF(GPIOD_PIN10, 0) | \ - PIN_AFIO_AF(GPIOD_PIN11, 0) | \ - PIN_AFIO_AF(GPIOD_PIN12, 0) | \ - PIN_AFIO_AF(GPIOD_PIN13, 0) | \ - PIN_AFIO_AF(GPIOD_PIN14, 0) | \ - PIN_AFIO_AF(GPIOD_PIN15, 0)) - -/* - * GPIOE setup: - * - * PE0 - PIN0 (input pullup). - * PE1 - PIN1 (input pullup). - * PE2 - PIN2 (input pullup). - * PE3 - PIN3 (input pullup). - * PE4 - PIN4 (input pullup). - * PE5 - PIN5 (input pullup). - * PE6 - PIN6 (input pullup). - * PE7 - PIN7 (input pullup). - * PE8 - PIN8 (input pullup). - * PE9 - PIN9 (input pullup). - * PE10 - PIN10 (input pullup). - * PE11 - PIN11 (input pullup). - * PE12 - PIN12 (input pullup). - * PE13 - PIN13 (input pullup). - * PE14 - PIN14 (input pullup). - * PE15 - PIN15 (input pullup). - */ -#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \ - PIN_MODE_INPUT(GPIOE_PIN1) | \ - PIN_MODE_INPUT(GPIOE_PIN2) | \ - PIN_MODE_INPUT(GPIOE_PIN3) | \ - PIN_MODE_INPUT(GPIOE_PIN4) | \ - PIN_MODE_INPUT(GPIOE_PIN5) | \ - PIN_MODE_INPUT(GPIOE_PIN6) | \ - PIN_MODE_INPUT(GPIOE_PIN7) | \ - PIN_MODE_INPUT(GPIOE_PIN8) | \ - PIN_MODE_INPUT(GPIOE_PIN9) | \ - PIN_MODE_INPUT(GPIOE_PIN10) | \ - PIN_MODE_INPUT(GPIOE_PIN11) | \ - PIN_MODE_INPUT(GPIOE_PIN12) | \ - PIN_MODE_INPUT(GPIOE_PIN13) | \ - PIN_MODE_INPUT(GPIOE_PIN14) | \ - PIN_MODE_INPUT(GPIOE_PIN15)) -#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) -#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_100M(GPIOE_PIN0) | \ - PIN_OSPEED_100M(GPIOE_PIN1) | \ - PIN_OSPEED_100M(GPIOE_PIN2) | \ - PIN_OSPEED_100M(GPIOE_PIN3) | \ - PIN_OSPEED_100M(GPIOE_PIN4) | \ - PIN_OSPEED_100M(GPIOE_PIN5) | \ - PIN_OSPEED_100M(GPIOE_PIN6) | \ - PIN_OSPEED_100M(GPIOE_PIN7) | \ - PIN_OSPEED_100M(GPIOE_PIN8) | \ - PIN_OSPEED_100M(GPIOE_PIN9) | \ - PIN_OSPEED_100M(GPIOE_PIN10) | \ - PIN_OSPEED_100M(GPIOE_PIN11) | \ - PIN_OSPEED_100M(GPIOE_PIN12) | \ - PIN_OSPEED_100M(GPIOE_PIN13) | \ - PIN_OSPEED_100M(GPIOE_PIN14) | \ - PIN_OSPEED_100M(GPIOE_PIN15)) -#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN15)) -#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ - PIN_ODR_HIGH(GPIOE_PIN1) | \ - PIN_ODR_HIGH(GPIOE_PIN2) | \ - PIN_ODR_HIGH(GPIOE_PIN3) | \ - PIN_ODR_HIGH(GPIOE_PIN4) | \ - PIN_ODR_HIGH(GPIOE_PIN5) | \ - PIN_ODR_HIGH(GPIOE_PIN6) | \ - PIN_ODR_HIGH(GPIOE_PIN7) | \ - PIN_ODR_HIGH(GPIOE_PIN8) | \ - PIN_ODR_HIGH(GPIOE_PIN9) | \ - PIN_ODR_HIGH(GPIOE_PIN10) | \ - PIN_ODR_HIGH(GPIOE_PIN11) | \ - PIN_ODR_HIGH(GPIOE_PIN12) | \ - PIN_ODR_HIGH(GPIOE_PIN13) | \ - PIN_ODR_HIGH(GPIOE_PIN14) | \ - PIN_ODR_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0) | \ - PIN_AFIO_AF(GPIOE_PIN1, 0) | \ - PIN_AFIO_AF(GPIOE_PIN2, 0) | \ - PIN_AFIO_AF(GPIOE_PIN3, 0) | \ - PIN_AFIO_AF(GPIOE_PIN4, 0) | \ - PIN_AFIO_AF(GPIOE_PIN5, 0) | \ - PIN_AFIO_AF(GPIOE_PIN6, 0) | \ - PIN_AFIO_AF(GPIOE_PIN7, 0)) -#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0) | \ - PIN_AFIO_AF(GPIOE_PIN9, 0) | \ - PIN_AFIO_AF(GPIOE_PIN10, 0) | \ - PIN_AFIO_AF(GPIOE_PIN11, 0) | \ - PIN_AFIO_AF(GPIOE_PIN12, 0) | \ - PIN_AFIO_AF(GPIOE_PIN13, 0) | \ - PIN_AFIO_AF(GPIOE_PIN14, 0) | \ - PIN_AFIO_AF(GPIOE_PIN15, 0)) - -/* - * GPIOF setup: - * - * PF0 - PIN0 (input pullup). - * PF1 - PIN1 (input pullup). - * PF2 - PIN2 (input pullup). - * PF3 - PIN3 (input pullup). - * PF4 - PIN4 (input pullup). - * PF5 - PIN5 (input pullup). - * PF6 - PIN6 (input pullup). - * PF7 - PIN7 (input pullup). - * PF8 - PIN8 (input pullup). - * PF9 - PIN9 (input pullup). - * PF10 - PIN10 (input pullup). - * PF11 - USB_FS_FAULT (input floating). - * PF12 - PIN12 (input pullup). - * PF13 - PIN13 (input pullup). - * PF14 - PIN14 (input pullup). - * PF15 - PIN15 (input pullup). - */ -#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \ - PIN_MODE_INPUT(GPIOF_PIN1) | \ - PIN_MODE_INPUT(GPIOF_PIN2) | \ - PIN_MODE_INPUT(GPIOF_PIN3) | \ - PIN_MODE_INPUT(GPIOF_PIN4) | \ - PIN_MODE_INPUT(GPIOF_PIN5) | \ - PIN_MODE_INPUT(GPIOF_PIN6) | \ - PIN_MODE_INPUT(GPIOF_PIN7) | \ - PIN_MODE_INPUT(GPIOF_PIN8) | \ - PIN_MODE_INPUT(GPIOF_PIN9) | \ - PIN_MODE_INPUT(GPIOF_PIN10) | \ - PIN_MODE_INPUT(GPIOF_USB_FS_FAULT) | \ - PIN_MODE_INPUT(GPIOF_PIN12) | \ - PIN_MODE_INPUT(GPIOF_PIN13) | \ - PIN_MODE_INPUT(GPIOF_PIN14) | \ - PIN_MODE_INPUT(GPIOF_PIN15)) -#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOF_USB_FS_FAULT) |\ - PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) -#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_100M(GPIOF_PIN0) | \ - PIN_OSPEED_100M(GPIOF_PIN1) | \ - PIN_OSPEED_100M(GPIOF_PIN2) | \ - PIN_OSPEED_100M(GPIOF_PIN3) | \ - PIN_OSPEED_100M(GPIOF_PIN4) | \ - PIN_OSPEED_100M(GPIOF_PIN5) | \ - PIN_OSPEED_100M(GPIOF_PIN6) | \ - PIN_OSPEED_100M(GPIOF_PIN7) | \ - PIN_OSPEED_100M(GPIOF_PIN8) | \ - PIN_OSPEED_100M(GPIOF_PIN9) | \ - PIN_OSPEED_100M(GPIOF_PIN10) | \ - PIN_OSPEED_100M(GPIOF_USB_FS_FAULT) | \ - PIN_OSPEED_100M(GPIOF_PIN12) | \ - PIN_OSPEED_100M(GPIOF_PIN13) | \ - PIN_OSPEED_100M(GPIOF_PIN14) | \ - PIN_OSPEED_100M(GPIOF_PIN15)) -#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOF_USB_FS_FAULT) |\ - PIN_PUPDR_PULLUP(GPIOF_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN15)) -#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \ - PIN_ODR_HIGH(GPIOF_PIN1) | \ - PIN_ODR_HIGH(GPIOF_PIN2) | \ - PIN_ODR_HIGH(GPIOF_PIN3) | \ - PIN_ODR_HIGH(GPIOF_PIN4) | \ - PIN_ODR_HIGH(GPIOF_PIN5) | \ - PIN_ODR_HIGH(GPIOF_PIN6) | \ - PIN_ODR_HIGH(GPIOF_PIN7) | \ - PIN_ODR_HIGH(GPIOF_PIN8) | \ - PIN_ODR_HIGH(GPIOF_PIN9) | \ - PIN_ODR_HIGH(GPIOF_PIN10) | \ - PIN_ODR_HIGH(GPIOF_USB_FS_FAULT) | \ - PIN_ODR_HIGH(GPIOF_PIN12) | \ - PIN_ODR_HIGH(GPIOF_PIN13) | \ - PIN_ODR_HIGH(GPIOF_PIN14) | \ - PIN_ODR_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0) | \ - PIN_AFIO_AF(GPIOF_PIN1, 0) | \ - PIN_AFIO_AF(GPIOF_PIN2, 0) | \ - PIN_AFIO_AF(GPIOF_PIN3, 0) | \ - PIN_AFIO_AF(GPIOF_PIN4, 0) | \ - PIN_AFIO_AF(GPIOF_PIN5, 0) | \ - PIN_AFIO_AF(GPIOF_PIN6, 0) | \ - PIN_AFIO_AF(GPIOF_PIN7, 0)) -#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0) | \ - PIN_AFIO_AF(GPIOF_PIN9, 0) | \ - PIN_AFIO_AF(GPIOF_PIN10, 0) | \ - PIN_AFIO_AF(GPIOF_USB_FS_FAULT, 0) | \ - PIN_AFIO_AF(GPIOF_PIN12, 0) | \ - PIN_AFIO_AF(GPIOF_PIN13, 0) | \ - PIN_AFIO_AF(GPIOF_PIN14, 0) | \ - PIN_AFIO_AF(GPIOF_PIN15, 0)) - -/* - * GPIOG setup: - * - * PG0 - PIN0 (input pullup). - * PG1 - PIN1 (input pullup). - * PG2 - PIN2 (input pullup). - * PG3 - PIN3 (input pullup). - * PG4 - PIN4 (input pullup). - * PG5 - PIN5 (input pullup). - * PG6 - PIN6 (input pullup). - * PG7 - PIN7 (input pullup). - * PG8 - PIN8 (input pullup). - * PG9 - PIN9 (input pullup). - * PG10 - SPI2_CS (output pushpull maximum). - * PG11 - ETH_RMII_TXEN (alternate 11). - * PG12 - PIN12 (input pullup). - * PG13 - ETH_RMII_TXD0 (alternate 11). - * PG14 - ETH_RMII_TXD1 (alternate 11). - * PG15 - PIN15 (input pullup). - */ -#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | \ - PIN_MODE_INPUT(GPIOG_PIN1) | \ - PIN_MODE_INPUT(GPIOG_PIN2) | \ - PIN_MODE_INPUT(GPIOG_PIN3) | \ - PIN_MODE_INPUT(GPIOG_PIN4) | \ - PIN_MODE_INPUT(GPIOG_PIN5) | \ - PIN_MODE_INPUT(GPIOG_PIN6) | \ - PIN_MODE_INPUT(GPIOG_PIN7) | \ - PIN_MODE_INPUT(GPIOG_PIN8) | \ - PIN_MODE_INPUT(GPIOG_PIN9) | \ - PIN_MODE_OUTPUT(GPIOG_SPI2_CS) | \ - PIN_MODE_ALTERNATE(GPIOG_ETH_RMII_TXEN) |\ - PIN_MODE_INPUT(GPIOG_PIN12) | \ - PIN_MODE_ALTERNATE(GPIOG_ETH_RMII_TXD0) |\ - PIN_MODE_ALTERNATE(GPIOG_ETH_RMII_TXD1) |\ - PIN_MODE_INPUT(GPIOG_PIN15)) -#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOG_SPI2_CS) | \ - PIN_OTYPE_PUSHPULL(GPIOG_ETH_RMII_TXEN) |\ - PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOG_ETH_RMII_TXD0) |\ - PIN_OTYPE_PUSHPULL(GPIOG_ETH_RMII_TXD1) |\ - PIN_OTYPE_PUSHPULL(GPIOG_PIN15)) -#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_100M(GPIOG_PIN0) | \ - PIN_OSPEED_100M(GPIOG_PIN1) | \ - PIN_OSPEED_100M(GPIOG_PIN2) | \ - PIN_OSPEED_100M(GPIOG_PIN3) | \ - PIN_OSPEED_100M(GPIOG_PIN4) | \ - PIN_OSPEED_100M(GPIOG_PIN5) | \ - PIN_OSPEED_100M(GPIOG_PIN6) | \ - PIN_OSPEED_100M(GPIOG_PIN7) | \ - PIN_OSPEED_100M(GPIOG_PIN8) | \ - PIN_OSPEED_100M(GPIOG_PIN9) | \ - PIN_OSPEED_100M(GPIOG_SPI2_CS) | \ - PIN_OSPEED_100M(GPIOG_ETH_RMII_TXEN) | \ - PIN_OSPEED_100M(GPIOG_PIN12) | \ - PIN_OSPEED_100M(GPIOG_ETH_RMII_TXD0) | \ - PIN_OSPEED_100M(GPIOG_ETH_RMII_TXD1) | \ - PIN_OSPEED_100M(GPIOG_PIN15)) -#define VAL_GPIOG_PUPDR (PIN_PUPDR_PULLUP(GPIOG_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOG_SPI2_CS) | \ - PIN_PUPDR_FLOATING(GPIOG_ETH_RMII_TXEN) |\ - PIN_PUPDR_PULLUP(GPIOG_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOG_ETH_RMII_TXD0) |\ - PIN_PUPDR_FLOATING(GPIOG_ETH_RMII_TXD1) |\ - PIN_PUPDR_PULLUP(GPIOG_PIN15)) -#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \ - PIN_ODR_HIGH(GPIOG_PIN1) | \ - PIN_ODR_HIGH(GPIOG_PIN2) | \ - PIN_ODR_HIGH(GPIOG_PIN3) | \ - PIN_ODR_HIGH(GPIOG_PIN4) | \ - PIN_ODR_HIGH(GPIOG_PIN5) | \ - PIN_ODR_HIGH(GPIOG_PIN6) | \ - PIN_ODR_HIGH(GPIOG_PIN7) | \ - PIN_ODR_HIGH(GPIOG_PIN8) | \ - PIN_ODR_HIGH(GPIOG_PIN9) | \ - PIN_ODR_HIGH(GPIOG_SPI2_CS) | \ - PIN_ODR_HIGH(GPIOG_ETH_RMII_TXEN) | \ - PIN_ODR_HIGH(GPIOG_PIN12) | \ - PIN_ODR_HIGH(GPIOG_ETH_RMII_TXD0) | \ - PIN_ODR_HIGH(GPIOG_ETH_RMII_TXD1) | \ - PIN_ODR_HIGH(GPIOG_PIN15)) -#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0) | \ - PIN_AFIO_AF(GPIOG_PIN1, 0) | \ - PIN_AFIO_AF(GPIOG_PIN2, 0) | \ - PIN_AFIO_AF(GPIOG_PIN3, 0) | \ - PIN_AFIO_AF(GPIOG_PIN4, 0) | \ - PIN_AFIO_AF(GPIOG_PIN5, 0) | \ - PIN_AFIO_AF(GPIOG_PIN6, 0) | \ - PIN_AFIO_AF(GPIOG_PIN7, 0)) -#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0) | \ - PIN_AFIO_AF(GPIOG_PIN9, 0) | \ - PIN_AFIO_AF(GPIOG_SPI2_CS, 0) | \ - PIN_AFIO_AF(GPIOG_ETH_RMII_TXEN, 11) | \ - PIN_AFIO_AF(GPIOG_PIN12, 0) | \ - PIN_AFIO_AF(GPIOG_ETH_RMII_TXD0, 11) | \ - PIN_AFIO_AF(GPIOG_ETH_RMII_TXD1, 11) | \ - PIN_AFIO_AF(GPIOG_PIN15, 0)) - -/* - * GPIOH setup: - * - * PH0 - OSC_IN (input floating). - * PH1 - OSC_OUT (input floating). - * PH2 - PIN2 (input pullup). - * PH3 - PIN3 (input pullup). - * PH4 - PIN4 (input pullup). - * PH5 - PIN5 (input pullup). - * PH6 - PIN6 (input pullup). - * PH7 - PIN7 (input pullup). - * PH8 - PIN8 (input pullup). - * PH9 - PIN9 (input pullup). - * PH10 - PIN10 (input pullup). - * PH11 - PIN11 (input pullup). - * PH12 - PIN12 (input pullup). - * PH13 - PIN13 (input pullup). - * PH14 - PIN14 (input pullup). - * PH15 - PIN15 (input pullup). - */ -#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ - PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ - PIN_MODE_INPUT(GPIOH_PIN2) | \ - PIN_MODE_INPUT(GPIOH_PIN3) | \ - PIN_MODE_INPUT(GPIOH_PIN4) | \ - PIN_MODE_INPUT(GPIOH_PIN5) | \ - PIN_MODE_INPUT(GPIOH_PIN6) | \ - PIN_MODE_INPUT(GPIOH_PIN7) | \ - PIN_MODE_INPUT(GPIOH_PIN8) | \ - PIN_MODE_INPUT(GPIOH_PIN9) | \ - PIN_MODE_INPUT(GPIOH_PIN10) | \ - PIN_MODE_INPUT(GPIOH_PIN11) | \ - PIN_MODE_INPUT(GPIOH_PIN12) | \ - PIN_MODE_INPUT(GPIOH_PIN13) | \ - PIN_MODE_INPUT(GPIOH_PIN14) | \ - PIN_MODE_INPUT(GPIOH_PIN15)) -#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) -#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_100M(GPIOH_OSC_IN) | \ - PIN_OSPEED_100M(GPIOH_OSC_OUT) | \ - PIN_OSPEED_100M(GPIOH_PIN2) | \ - PIN_OSPEED_100M(GPIOH_PIN3) | \ - PIN_OSPEED_100M(GPIOH_PIN4) | \ - PIN_OSPEED_100M(GPIOH_PIN5) | \ - PIN_OSPEED_100M(GPIOH_PIN6) | \ - PIN_OSPEED_100M(GPIOH_PIN7) | \ - PIN_OSPEED_100M(GPIOH_PIN8) | \ - PIN_OSPEED_100M(GPIOH_PIN9) | \ - PIN_OSPEED_100M(GPIOH_PIN10) | \ - PIN_OSPEED_100M(GPIOH_PIN11) | \ - PIN_OSPEED_100M(GPIOH_PIN12) | \ - PIN_OSPEED_100M(GPIOH_PIN13) | \ - PIN_OSPEED_100M(GPIOH_PIN14) | \ - PIN_OSPEED_100M(GPIOH_PIN15)) -#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ - PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN15)) -#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ - PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ - PIN_ODR_HIGH(GPIOH_PIN2) | \ - PIN_ODR_HIGH(GPIOH_PIN3) | \ - PIN_ODR_HIGH(GPIOH_PIN4) | \ - PIN_ODR_HIGH(GPIOH_PIN5) | \ - PIN_ODR_HIGH(GPIOH_PIN6) | \ - PIN_ODR_HIGH(GPIOH_PIN7) | \ - PIN_ODR_HIGH(GPIOH_PIN8) | \ - PIN_ODR_HIGH(GPIOH_PIN9) | \ - PIN_ODR_HIGH(GPIOH_PIN10) | \ - PIN_ODR_HIGH(GPIOH_PIN11) | \ - PIN_ODR_HIGH(GPIOH_PIN12) | \ - PIN_ODR_HIGH(GPIOH_PIN13) | \ - PIN_ODR_HIGH(GPIOH_PIN14) | \ - PIN_ODR_HIGH(GPIOH_PIN15)) -#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0) | \ - PIN_AFIO_AF(GPIOH_OSC_OUT, 0) | \ - PIN_AFIO_AF(GPIOH_PIN2, 0) | \ - PIN_AFIO_AF(GPIOH_PIN3, 0) | \ - PIN_AFIO_AF(GPIOH_PIN4, 0) | \ - PIN_AFIO_AF(GPIOH_PIN5, 0) | \ - PIN_AFIO_AF(GPIOH_PIN6, 0) | \ - PIN_AFIO_AF(GPIOH_PIN7, 0)) -#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0) | \ - PIN_AFIO_AF(GPIOH_PIN9, 0) | \ - PIN_AFIO_AF(GPIOH_PIN10, 0) | \ - PIN_AFIO_AF(GPIOH_PIN11, 0) | \ - PIN_AFIO_AF(GPIOH_PIN12, 0) | \ - PIN_AFIO_AF(GPIOH_PIN13, 0) | \ - PIN_AFIO_AF(GPIOH_PIN14, 0) | \ - PIN_AFIO_AF(GPIOH_PIN15, 0)) - -/* - * GPIOI setup: - * - * PI0 - PIN0 (input pullup). - * PI1 - PIN1 (input pullup). - * PI2 - PIN2 (input pullup). - * PI3 - PIN3 (input pullup). - * PI4 - PIN4 (input pullup). - * PI5 - PIN5 (input pullup). - * PI6 - PIN6 (input pullup). - * PI7 - PIN7 (input pullup). - * PI8 - PIN8 (input pullup). - * PI9 - PIN9 (input pullup). - * PI10 - PIN10 (input pullup). - * PI11 - PIN11 (input pullup). - * PI12 - PIN12 (input pullup). - * PI13 - PIN13 (input pullup). - * PI14 - PIN14 (input pullup). - * PI15 - PIN15 (input pullup). - */ -#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \ - PIN_MODE_INPUT(GPIOI_PIN1) | \ - PIN_MODE_INPUT(GPIOI_PIN2) | \ - PIN_MODE_INPUT(GPIOI_PIN3) | \ - PIN_MODE_INPUT(GPIOI_PIN4) | \ - PIN_MODE_INPUT(GPIOI_PIN5) | \ - PIN_MODE_INPUT(GPIOI_PIN6) | \ - PIN_MODE_INPUT(GPIOI_PIN7) | \ - PIN_MODE_INPUT(GPIOI_PIN8) | \ - PIN_MODE_INPUT(GPIOI_PIN9) | \ - PIN_MODE_INPUT(GPIOI_PIN10) | \ - PIN_MODE_INPUT(GPIOI_PIN11) | \ - PIN_MODE_INPUT(GPIOI_PIN12) | \ - PIN_MODE_INPUT(GPIOI_PIN13) | \ - PIN_MODE_INPUT(GPIOI_PIN14) | \ - PIN_MODE_INPUT(GPIOI_PIN15)) -#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN15)) -#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_100M(GPIOI_PIN0) | \ - PIN_OSPEED_100M(GPIOI_PIN1) | \ - PIN_OSPEED_100M(GPIOI_PIN2) | \ - PIN_OSPEED_100M(GPIOI_PIN3) | \ - PIN_OSPEED_100M(GPIOI_PIN4) | \ - PIN_OSPEED_100M(GPIOI_PIN5) | \ - PIN_OSPEED_100M(GPIOI_PIN6) | \ - PIN_OSPEED_100M(GPIOI_PIN7) | \ - PIN_OSPEED_100M(GPIOI_PIN8) | \ - PIN_OSPEED_100M(GPIOI_PIN9) | \ - PIN_OSPEED_100M(GPIOI_PIN10) | \ - PIN_OSPEED_100M(GPIOI_PIN11) | \ - PIN_OSPEED_100M(GPIOI_PIN12) | \ - PIN_OSPEED_100M(GPIOI_PIN13) | \ - PIN_OSPEED_100M(GPIOI_PIN14) | \ - PIN_OSPEED_100M(GPIOI_PIN15)) -#define VAL_GPIOI_PUPDR (PIN_PUPDR_PULLUP(GPIOI_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN15)) -#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \ - PIN_ODR_HIGH(GPIOI_PIN1) | \ - PIN_ODR_HIGH(GPIOI_PIN2) | \ - PIN_ODR_HIGH(GPIOI_PIN3) | \ - PIN_ODR_HIGH(GPIOI_PIN4) | \ - PIN_ODR_HIGH(GPIOI_PIN5) | \ - PIN_ODR_HIGH(GPIOI_PIN6) | \ - PIN_ODR_HIGH(GPIOI_PIN7) | \ - PIN_ODR_HIGH(GPIOI_PIN8) | \ - PIN_ODR_HIGH(GPIOI_PIN9) | \ - PIN_ODR_HIGH(GPIOI_PIN10) | \ - PIN_ODR_HIGH(GPIOI_PIN11) | \ - PIN_ODR_HIGH(GPIOI_PIN12) | \ - PIN_ODR_HIGH(GPIOI_PIN13) | \ - PIN_ODR_HIGH(GPIOI_PIN14) | \ - PIN_ODR_HIGH(GPIOI_PIN15)) -#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0) | \ - PIN_AFIO_AF(GPIOI_PIN1, 0) | \ - PIN_AFIO_AF(GPIOI_PIN2, 0) | \ - PIN_AFIO_AF(GPIOI_PIN3, 0) | \ - PIN_AFIO_AF(GPIOI_PIN4, 0) | \ - PIN_AFIO_AF(GPIOI_PIN5, 0) | \ - PIN_AFIO_AF(GPIOI_PIN6, 0) | \ - PIN_AFIO_AF(GPIOI_PIN7, 0)) -#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0) | \ - PIN_AFIO_AF(GPIOI_PIN9, 0) | \ - PIN_AFIO_AF(GPIOI_PIN10, 0) | \ - PIN_AFIO_AF(GPIOI_PIN11, 0) | \ - PIN_AFIO_AF(GPIOI_PIN12, 0) | \ - PIN_AFIO_AF(GPIOI_PIN13, 0) | \ - PIN_AFIO_AF(GPIOI_PIN14, 0) | \ - PIN_AFIO_AF(GPIOI_PIN15, 0)) - - -#if !defined(_FROM_ASM_) -#ifdef __cplusplus -extern "C" { -#endif - void boardInit(void); -#ifdef __cplusplus -} -#endif -#endif /* _FROM_ASM_ */ - -#endif /* _BOARD_H_ */ diff --git a/firmware/chibios/boards/OLIMEX_STM32_E407/board.mk b/firmware/chibios/boards/OLIMEX_STM32_E407/board.mk deleted file mode 100644 index 4af25c29f1..0000000000 --- a/firmware/chibios/boards/OLIMEX_STM32_E407/board.mk +++ /dev/null @@ -1,5 +0,0 @@ -# List of all the board related files. -BOARDSRC = ${CHIBIOS}/boards/OLIMEX_STM32_E407/board.c - -# Required include directories -BOARDINC = ${CHIBIOS}/boards/OLIMEX_STM32_E407 diff --git a/firmware/chibios/boards/OLIMEX_STM32_E407/cfg/board.chcfg b/firmware/chibios/boards/OLIMEX_STM32_E407/cfg/board.chcfg deleted file mode 100644 index ba830a8df3..0000000000 --- a/firmware/chibios/boards/OLIMEX_STM32_E407/cfg/board.chcfg +++ /dev/null @@ -1,341 +0,0 @@ - - - - - resources/gencfg/processors/boards/stm32f4xx/templates - .. - - Olimex STM32-E407 - OLIMEX_STM32_E407 - - - - - - - MII_KS8721_ID - RMII - - STM32F40_41xxx - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/firmware/chibios/boards/ST_NUCLEO_F103RB/board.c b/firmware/chibios/boards/ST_NUCLEO_F103RB/board.c deleted file mode 100644 index b5aa8ff02d..0000000000 --- a/firmware/chibios/boards/ST_NUCLEO_F103RB/board.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include "ch.h" -#include "hal.h" - -/** - * @brief PAL setup. - * @details Digital I/O ports static configuration as defined in @p board.h. - * This variable is used by the HAL when initializing the PAL driver. - */ -#if HAL_USE_PAL || defined(__DOXYGEN__) -const PALConfig pal_default_config = -{ - {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH}, - {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH}, - {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH}, - {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH}, - {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH}, -}; -#endif - -/* - * Early initialization code. - * This initialization must be performed just after stack setup and before - * any other initialization. - */ -void __early_init(void) { - - stm32_clock_init(); -} - -/* - * Board-specific initialization code. - */ -void boardInit(void) { -} diff --git a/firmware/chibios/boards/ST_NUCLEO_F103RB/board.h b/firmware/chibios/boards/ST_NUCLEO_F103RB/board.h deleted file mode 100644 index f680249bd9..0000000000 --- a/firmware/chibios/boards/ST_NUCLEO_F103RB/board.h +++ /dev/null @@ -1,202 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -/* - * Setup for the ST INEMO-M1 Discovery board. - */ - -/* - * Board identifier. - */ -#define BOARD_ST_NUCLEO_F103RB -#define BOARD_NAME "STMicroelectronics NUCLEO-F103RB" - -/* - * Board frequencies. - */ -#define STM32_LSECLK 0 - -#if defined(NUCLEO_EXTERNAL_OSCILLATOR) -#define STM32_HSECLK 8000000 -#define STM32_HSE_BYPASS - -#elif defined(NUCLEO_HSE_CRYSTAL) -#define STM32_HSECLK 8000000 - -#else -#define STM32_HSECLK 0 -#endif - -/* - * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h. - */ -#define STM32F10X_MD - -/* - * IO pins assignments. - */ -#define GPIOA_PA0 0 -#define GPIOA_PA1 1 -#define GPIOA_USART_TX 2 -#define GPIOA_USART_RX 3 -#define GPIOA_PA4 4 -#define GPIOA_LED_GREEN 5 -#define GPIOA_PA6 6 -#define GPIOA_PA7 7 -#define GPIOA_PA8 8 -#define GPIOA_PA9 9 -#define GPIOA_PA10 10 -#define GPIOA_PA11 11 -#define GPIOA_PA12 12 -#define GPIOA_SWDIO 13 -#define GPIOA_SWCLK 14 -#define GPIOA_PA15 15 - -#define GPIOB_PB0 0 -#define GPIOB_PB1 1 -#define GPIOB_PB2 2 -#define GPIOB_SWO 3 -#define GPIOB_PB4 4 -#define GPIOB_PB5 5 -#define GPIOB_PB6 6 -#define GPIOB_PB7 7 -#define GPIOB_PB8 8 -#define GPIOB_PB9 9 -#define GPIOB_PB10 10 -#define GPIOB_PB11 11 -#define GPIOB_PB12 12 -#define GPIOB_PB13 13 -#define GPIOB_PB14 14 -#define GPIOB_PB15 15 - -#define GPIOC_PC0 0 -#define GPIOC_PC1 1 -#define GPIOC_PC2 2 -#define GPIOC_PC3 3 -#define GPIOC_PC4 4 -#define GPIOC_PC5 5 -#define GPIOC_PC6 6 -#define GPIOC_PC7 7 -#define GPIOC_PC8 8 -#define GPIOC_PC9 9 -#define GPIOC_PC10 10 -#define GPIOC_PC11 11 -#define GPIOC_PC12 12 -#define GPIOC_BUTTON 13 -#define GPIOC_PC14 14 -#define GPIOC_PC15 15 - -#define GPIOD_OSC_IN 0 -#define GPIOD_OSC_OUT 1 -#define GPIOD_PD2 2 - -/* - * I/O ports initial setup, this configuration is established soon after reset - * in the initialization code. - * - * The digits have the following meaning: - * 0 - Analog input. - * 1 - Push Pull output 10MHz. - * 2 - Push Pull output 2MHz. - * 3 - Push Pull output 50MHz. - * 4 - Digital input. - * 5 - Open Drain output 10MHz. - * 6 - Open Drain output 2MHz. - * 7 - Open Drain output 50MHz. - * 8 - Digital input with PullUp or PullDown resistor depending on ODR. - * 9 - Alternate Push Pull output 10MHz. - * A - Alternate Push Pull output 2MHz. - * B - Alternate Push Pull output 50MHz. - * C - Reserved. - * D - Alternate Open Drain output 10MHz. - * E - Alternate Open Drain output 2MHz. - * F - Alternate Open Drain output 50MHz. - * Please refer to the STM32 Reference Manual for details. - */ - -/* - * Port A setup. - * Everything input with pull-up except: - * PA2 - Alternate output (GPIOA_USART_TX). - * PA3 - Normal input (GPIOA_USART_RX). - * PA5 - Push Pull output (GPIOA_LED_GREEN). - * PA13 - Pull-up input (GPIOA_SWDIO). - * PA14 - Pull-down input (GPIOA_SWCLK). - */ -#define VAL_GPIOACRL 0x88384B88 /* PA7...PA0 */ -#define VAL_GPIOACRH 0x88888888 /* PA15...PA8 */ -#define VAL_GPIOAODR 0xFFFFBFDF - -/* - * Port B setup. - * Everything input with pull-up except: - * PB3 - Pull-up input (GPIOA_SWO). - */ -#define VAL_GPIOBCRL 0x88888888 /* PB7...PB0 */ -#define VAL_GPIOBCRH 0x88888888 /* PB15...PB8 */ -#define VAL_GPIOBODR 0xFFFFFFFF - -/* - * Port C setup. - * Everything input with pull-up except: - * PC13 - Normal input (GPIOC_BUTTON). - */ -#define VAL_GPIOCCRL 0x88888888 /* PC7...PC0 */ -#define VAL_GPIOCCRH 0x88488888 /* PC15...PC8 */ -#define VAL_GPIOCODR 0xFFFFFFFF - -/* - * Port D setup. - * Everything input with pull-up except: - * PD0 - Normal input (GPIOD_OSC_IN). - * PD1 - Normal input (GPIOD_OSC_OUT). - */ -#define VAL_GPIODCRL 0x88888844 /* PD7...PD0 */ -#define VAL_GPIODCRH 0x88888888 /* PD15...PD8 */ -#define VAL_GPIODODR 0xFFFFFFFF - -/* - * Port E setup. - * Everything input with pull-up except: - */ -#define VAL_GPIOECRL 0x88888888 /* PE7...PE0 */ -#define VAL_GPIOECRH 0x88888888 /* PE15...PE8 */ -#define VAL_GPIOEODR 0xFFFFFFFF - -/* - * USB bus activation macro, required by the USB driver. - */ -#define usb_lld_connect_bus(usbp) - -/* - * USB bus de-activation macro, required by the USB driver. - */ -#define usb_lld_disconnect_bus(usbp) - -#if !defined(_FROM_ASM_) -#ifdef __cplusplus -extern "C" { -#endif - void boardInit(void); -#ifdef __cplusplus -} -#endif -#endif /* _FROM_ASM_ */ - -#endif /* _BOARD_H_ */ diff --git a/firmware/chibios/boards/ST_NUCLEO_F103RB/board.mk b/firmware/chibios/boards/ST_NUCLEO_F103RB/board.mk deleted file mode 100644 index 9d4e46e9bb..0000000000 --- a/firmware/chibios/boards/ST_NUCLEO_F103RB/board.mk +++ /dev/null @@ -1,5 +0,0 @@ -# List of all the board related files. -BOARDSRC = ${CHIBIOS}/boards/ST_NUCLEO_F103RB/board.c - -# Required include directories -BOARDINC = ${CHIBIOS}/boards/ST_NUCLEO_F103RB diff --git a/firmware/chibios/boards/ST_STM32F0_DISCOVERY/board.c b/firmware/chibios/boards/ST_STM32F0_DISCOVERY/board.c deleted file mode 100644 index 60f4961b8e..0000000000 --- a/firmware/chibios/boards/ST_STM32F0_DISCOVERY/board.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include "hal.h" - -#if HAL_USE_PAL || defined(__DOXYGEN__) -/** - * @brief PAL setup. - * @details Digital I/O ports static configuration as defined in @p board.h. - * This variable is used by the HAL when initializing the PAL driver. - */ -const PALConfig pal_default_config = -{ - {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, - VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, - {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, - VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, - {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, - VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, - {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, - VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, - {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, - VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH} -}; -#endif - -/** - * @brief Early initialization code. - * @details This initialization must be performed just after stack setup - * and before any other initialization. - */ -void __early_init(void) { - - stm32_clock_init(); -} - -#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) -/** - * @brief MMC_SPI card detection. - */ -bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return TRUE; -} - -/** - * @brief MMC_SPI card write protection detection. - */ -bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return FALSE; -} -#endif - -/** - * @brief Board-specific initialization code. - * @todo Add your board-specific code, if any. - */ -void boardInit(void) { -} diff --git a/firmware/chibios/boards/ST_STM32F0_DISCOVERY/board.h b/firmware/chibios/boards/ST_STM32F0_DISCOVERY/board.h deleted file mode 100644 index 03f73419da..0000000000 --- a/firmware/chibios/boards/ST_STM32F0_DISCOVERY/board.h +++ /dev/null @@ -1,757 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -/* - * Setup for ST STM32F0-Discovery board. - */ - -/* - * Board identifier. - */ -#define BOARD_ST_STM32F0_DISCOVERY -#define BOARD_NAME "ST STM32F0-Discovery" - -/* - * Board oscillators-related settings. - * NOTE: LSE not fitted. - * NOTE: HSE not fitted. - */ -#if !defined(STM32_LSECLK) -#define STM32_LSECLK 0 -#endif - -#define STM32_LSEDRV (3 << 3) - -#if !defined(STM32_HSECLK) -#define STM32_HSECLK 0 -#endif - -#define STM32_HSE_BYPASS - -/* - * MCU type as defined in the ST header. - */ -#define STM32F0XX_MD - -/* - * IO pins assignments. - */ -#define GPIOA_BUTTON 0 -#define GPIOA_PIN1 1 -#define GPIOA_PIN2 2 -#define GPIOA_PIN3 3 -#define GPIOA_PIN4 4 -#define GPIOA_PIN5 5 -#define GPIOA_PIN6 6 -#define GPIOA_PIN7 7 -#define GPIOA_PIN8 8 -#define GPIOA_PIN9 9 -#define GPIOA_PIN10 10 -#define GPIOA_PIN11 11 -#define GPIOA_PIN12 12 -#define GPIOA_SWDAT 13 -#define GPIOA_SWCLK 14 -#define GPIOA_PIN15 15 - -#define GPIOB_PIN0 0 -#define GPIOB_PIN1 1 -#define GPIOB_PIN2 2 -#define GPIOB_PIN3 3 -#define GPIOB_PIN4 4 -#define GPIOB_PIN5 5 -#define GPIOB_PIN6 6 -#define GPIOB_PIN7 7 -#define GPIOB_PIN8 8 -#define GPIOB_PIN9 9 -#define GPIOB_PIN10 10 -#define GPIOB_PIN11 11 -#define GPIOB_PIN12 12 -#define GPIOB_PIN13 13 -#define GPIOB_PIN14 14 -#define GPIOB_PIN15 15 - -#define GPIOC_PIN0 0 -#define GPIOC_PIN1 1 -#define GPIOC_PIN2 2 -#define GPIOC_PIN3 3 -#define GPIOC_PIN4 4 -#define GPIOC_PIN5 5 -#define GPIOC_PIN6 6 -#define GPIOC_PIN7 7 -#define GPIOC_LED4 8 -#define GPIOC_LED3 9 -#define GPIOC_PIN10 10 -#define GPIOC_PIN11 11 -#define GPIOC_PIN12 12 -#define GPIOC_PIN13 13 -#define GPIOC_OSC32_IN 14 -#define GPIOC_OSC32_OUT 15 - -#define GPIOD_PIN0 0 -#define GPIOD_PIN1 1 -#define GPIOD_PIN2 2 -#define GPIOD_PIN3 3 -#define GPIOD_PIN4 4 -#define GPIOD_PIN5 5 -#define GPIOD_PIN6 6 -#define GPIOD_PIN7 7 -#define GPIOD_PIN8 8 -#define GPIOD_PIN9 9 -#define GPIOD_PIN10 10 -#define GPIOD_PIN11 11 -#define GPIOD_PIN12 12 -#define GPIOD_PIN13 13 -#define GPIOD_PIN14 14 -#define GPIOD_PIN15 15 - -#define GPIOF_OSC_IN 0 -#define GPIOF_OSC_OUT 1 -#define GPIOF_PIN2 2 -#define GPIOF_PIN3 3 -#define GPIOF_PIN4 4 -#define GPIOF_PIN5 5 -#define GPIOF_PIN6 6 -#define GPIOF_PIN7 7 -#define GPIOF_PIN8 8 -#define GPIOF_PIN9 9 -#define GPIOF_PIN10 10 -#define GPIOF_PIN11 11 -#define GPIOF_PIN12 12 -#define GPIOF_PIN13 13 -#define GPIOF_PIN14 14 -#define GPIOF_PIN15 15 - -/* - * I/O ports initial setup, this configuration is established soon after reset - * in the initialization code. - * Please refer to the STM32 Reference Manual for details. - */ -#define PIN_MODE_INPUT(n) (0U << ((n) * 2)) -#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2)) -#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2)) -#define PIN_MODE_ANALOG(n) (3U << ((n) * 2)) -#define PIN_ODR_LOW(n) (0U << (n)) -#define PIN_ODR_HIGH(n) (1U << (n)) -#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) -#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) -#define PIN_OSPEED_2M(n) (0U << ((n) * 2)) -#define PIN_OSPEED_10M(n) (1U << ((n) * 2)) -#define PIN_OSPEED_40M(n) (3U << ((n) * 2)) -#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2)) -#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2)) -#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2)) -#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4)) - -/* - * GPIOA setup: - * - * PA0 - BUTTON (input floating). - * PA1 - PIN1 (input pullup). - * PA2 - PIN2 (input pullup). - * PA3 - PIN3 (input pullup). - * PA4 - PIN4 (input pullup). - * PA5 - PIN5 (input pullup). - * PA6 - PIN6 (input pullup). - * PA7 - PIN7 (input pullup). - * PA8 - PIN8 (input pullup). - * PA9 - PIN9 (input pullup). - * PA10 - PIN10 (input pullup). - * PA11 - PIN11 (input pullup). - * PA12 - PIN12 (input pullup). - * PA13 - SWDAT (alternate 0). - * PA14 - SWCLK (alternate 0). - * PA15 - PIN15 (input pullup). - */ -#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON) | \ - PIN_MODE_INPUT(GPIOA_PIN1) | \ - PIN_MODE_INPUT(GPIOA_PIN2) | \ - PIN_MODE_INPUT(GPIOA_PIN3) | \ - PIN_MODE_INPUT(GPIOA_PIN4) | \ - PIN_MODE_INPUT(GPIOA_PIN5) | \ - PIN_MODE_INPUT(GPIOA_PIN6) | \ - PIN_MODE_INPUT(GPIOA_PIN7) | \ - PIN_MODE_INPUT(GPIOA_PIN8) | \ - PIN_MODE_INPUT(GPIOA_PIN9) | \ - PIN_MODE_INPUT(GPIOA_PIN10) | \ - PIN_MODE_INPUT(GPIOA_PIN11) | \ - PIN_MODE_INPUT(GPIOA_PIN12) | \ - PIN_MODE_ALTERNATE(GPIOA_SWDAT) | \ - PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ - PIN_MODE_INPUT(GPIOA_PIN15)) -#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWDAT) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) -#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_2M(GPIOA_BUTTON) | \ - PIN_OSPEED_2M(GPIOA_PIN1) | \ - PIN_OSPEED_2M(GPIOA_PIN2) | \ - PIN_OSPEED_2M(GPIOA_PIN3) | \ - PIN_OSPEED_2M(GPIOA_PIN4) | \ - PIN_OSPEED_2M(GPIOA_PIN5) | \ - PIN_OSPEED_2M(GPIOA_PIN6) | \ - PIN_OSPEED_2M(GPIOA_PIN7) | \ - PIN_OSPEED_2M(GPIOA_PIN8) | \ - PIN_OSPEED_2M(GPIOA_PIN9) | \ - PIN_OSPEED_2M(GPIOA_PIN10) | \ - PIN_OSPEED_2M(GPIOA_PIN11) | \ - PIN_OSPEED_2M(GPIOA_PIN12) | \ - PIN_OSPEED_40M(GPIOA_SWDAT) | \ - PIN_OSPEED_40M(GPIOA_SWCLK) | \ - PIN_OSPEED_40M(GPIOA_PIN15)) -#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_BUTTON) | \ - PIN_PUPDR_PULLUP(GPIOA_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOA_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOA_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOA_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOA_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOA_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOA_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOA_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOA_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOA_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOA_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOA_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOA_SWDAT) | \ - PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \ - PIN_PUPDR_PULLUP(GPIOA_PIN15)) -#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_BUTTON) | \ - PIN_ODR_HIGH(GPIOA_PIN1) | \ - PIN_ODR_HIGH(GPIOA_PIN2) | \ - PIN_ODR_HIGH(GPIOA_PIN3) | \ - PIN_ODR_HIGH(GPIOA_PIN4) | \ - PIN_ODR_HIGH(GPIOA_PIN5) | \ - PIN_ODR_HIGH(GPIOA_PIN6) | \ - PIN_ODR_HIGH(GPIOA_PIN7) | \ - PIN_ODR_HIGH(GPIOA_PIN8) | \ - PIN_ODR_HIGH(GPIOA_PIN9) | \ - PIN_ODR_HIGH(GPIOA_PIN10) | \ - PIN_ODR_HIGH(GPIOA_PIN11) | \ - PIN_ODR_HIGH(GPIOA_PIN12) | \ - PIN_ODR_HIGH(GPIOA_SWDAT) | \ - PIN_ODR_HIGH(GPIOA_SWCLK) | \ - PIN_ODR_HIGH(GPIOA_PIN15)) -#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON, 0) | \ - PIN_AFIO_AF(GPIOA_PIN1, 0) | \ - PIN_AFIO_AF(GPIOA_PIN2, 0) | \ - PIN_AFIO_AF(GPIOA_PIN3, 0) | \ - PIN_AFIO_AF(GPIOA_PIN4, 0) | \ - PIN_AFIO_AF(GPIOA_PIN5, 0) | \ - PIN_AFIO_AF(GPIOA_PIN6, 0) | \ - PIN_AFIO_AF(GPIOA_PIN7, 0)) -#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0) | \ - PIN_AFIO_AF(GPIOA_PIN9, 0) | \ - PIN_AFIO_AF(GPIOA_PIN10, 0) | \ - PIN_AFIO_AF(GPIOA_PIN11, 0) | \ - PIN_AFIO_AF(GPIOA_PIN12, 0) | \ - PIN_AFIO_AF(GPIOA_SWDAT, 0) | \ - PIN_AFIO_AF(GPIOA_SWCLK, 0) | \ - PIN_AFIO_AF(GPIOA_PIN15, 0)) - -/* - * GPIOB setup: - * - * PB0 - PIN0 (input pullup). - * PB1 - PIN1 (input pullup). - * PB2 - PIN2 (input pullup). - * PB3 - PIN3 (input pullup). - * PB4 - PIN4 (input pullup). - * PB5 - PIN5 (input pullup). - * PB6 - PIN6 (input pullup). - * PB7 - PIN7 (input pullup). - * PB8 - PIN8 (input pullup). - * PB9 - PIN9 (input pullup). - * PB10 - PIN10 (input pullup). - * PB11 - PIN11 (input pullup). - * PB12 - PIN12 (input pullup). - * PB13 - PIN13 (input pullup). - * PB14 - PIN14 (input pullup). - * PB15 - PIN15 (input pullup). - */ -#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \ - PIN_MODE_INPUT(GPIOB_PIN1) | \ - PIN_MODE_INPUT(GPIOB_PIN2) | \ - PIN_MODE_INPUT(GPIOB_PIN3) | \ - PIN_MODE_INPUT(GPIOB_PIN4) | \ - PIN_MODE_INPUT(GPIOB_PIN5) | \ - PIN_MODE_INPUT(GPIOB_PIN6) | \ - PIN_MODE_INPUT(GPIOB_PIN7) | \ - PIN_MODE_INPUT(GPIOB_PIN8) | \ - PIN_MODE_INPUT(GPIOB_PIN9) | \ - PIN_MODE_INPUT(GPIOB_PIN10) | \ - PIN_MODE_INPUT(GPIOB_PIN11) | \ - PIN_MODE_INPUT(GPIOB_PIN12) | \ - PIN_MODE_INPUT(GPIOB_PIN13) | \ - PIN_MODE_INPUT(GPIOB_PIN14) | \ - PIN_MODE_INPUT(GPIOB_PIN15)) -#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) -#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_2M(GPIOB_PIN0) | \ - PIN_OSPEED_2M(GPIOB_PIN1) | \ - PIN_OSPEED_40M(GPIOB_PIN2) | \ - PIN_OSPEED_40M(GPIOB_PIN3) | \ - PIN_OSPEED_40M(GPIOB_PIN4) | \ - PIN_OSPEED_2M(GPIOB_PIN5) | \ - PIN_OSPEED_2M(GPIOB_PIN6) | \ - PIN_OSPEED_2M(GPIOB_PIN7) | \ - PIN_OSPEED_2M(GPIOB_PIN8) | \ - PIN_OSPEED_2M(GPIOB_PIN9) | \ - PIN_OSPEED_2M(GPIOB_PIN10) | \ - PIN_OSPEED_2M(GPIOB_PIN11) | \ - PIN_OSPEED_2M(GPIOB_PIN12) | \ - PIN_OSPEED_2M(GPIOB_PIN13) | \ - PIN_OSPEED_2M(GPIOB_PIN14) | \ - PIN_OSPEED_2M(GPIOB_PIN15)) -#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN15)) -#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \ - PIN_ODR_HIGH(GPIOB_PIN1) | \ - PIN_ODR_HIGH(GPIOB_PIN2) | \ - PIN_ODR_HIGH(GPIOB_PIN3) | \ - PIN_ODR_HIGH(GPIOB_PIN4) | \ - PIN_ODR_HIGH(GPIOB_PIN5) | \ - PIN_ODR_HIGH(GPIOB_PIN6) | \ - PIN_ODR_HIGH(GPIOB_PIN7) | \ - PIN_ODR_HIGH(GPIOB_PIN8) | \ - PIN_ODR_HIGH(GPIOB_PIN9) | \ - PIN_ODR_HIGH(GPIOB_PIN10) | \ - PIN_ODR_HIGH(GPIOB_PIN11) | \ - PIN_ODR_HIGH(GPIOB_PIN12) | \ - PIN_ODR_HIGH(GPIOB_PIN13) | \ - PIN_ODR_HIGH(GPIOB_PIN14) | \ - PIN_ODR_HIGH(GPIOB_PIN15)) -#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0) | \ - PIN_AFIO_AF(GPIOB_PIN1, 0) | \ - PIN_AFIO_AF(GPIOB_PIN2, 0) | \ - PIN_AFIO_AF(GPIOB_PIN3, 0) | \ - PIN_AFIO_AF(GPIOB_PIN4, 0) | \ - PIN_AFIO_AF(GPIOB_PIN5, 0) | \ - PIN_AFIO_AF(GPIOB_PIN6, 0) | \ - PIN_AFIO_AF(GPIOB_PIN7, 0)) -#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0) | \ - PIN_AFIO_AF(GPIOB_PIN9, 0) | \ - PIN_AFIO_AF(GPIOB_PIN10, 0) | \ - PIN_AFIO_AF(GPIOB_PIN11, 0) | \ - PIN_AFIO_AF(GPIOB_PIN12, 0) | \ - PIN_AFIO_AF(GPIOB_PIN13, 0) | \ - PIN_AFIO_AF(GPIOB_PIN14, 0) | \ - PIN_AFIO_AF(GPIOB_PIN15, 0)) - -/* - * GPIOC setup: - * - * PC0 - PIN0 (input pullup). - * PC1 - PIN1 (input pullup). - * PC2 - PIN2 (input pullup). - * PC3 - PIN3 (input pullup). - * PC4 - PIN4 (input pullup). - * PC5 - PIN5 (input pullup). - * PC6 - PIN6 (input pullup). - * PC7 - PIN7 (input pullup). - * PC8 - LED4 (output pushpull maximum). - * PC9 - LED3 (output pushpull maximum). - * PC10 - PIN10 (input pullup). - * PC11 - PIN11 (input pullup). - * PC12 - PIN12 (input pullup). - * PC13 - PIN13 (input pullup). - * PC14 - OSC32_IN (input floating). - * PC15 - OSC32_OUT (input floating). - */ -#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \ - PIN_MODE_INPUT(GPIOC_PIN1) | \ - PIN_MODE_INPUT(GPIOC_PIN2) | \ - PIN_MODE_INPUT(GPIOC_PIN3) | \ - PIN_MODE_INPUT(GPIOC_PIN4) | \ - PIN_MODE_INPUT(GPIOC_PIN5) | \ - PIN_MODE_INPUT(GPIOC_PIN6) | \ - PIN_MODE_INPUT(GPIOC_PIN7) | \ - PIN_MODE_OUTPUT(GPIOC_LED4) | \ - PIN_MODE_OUTPUT(GPIOC_LED3) | \ - PIN_MODE_INPUT(GPIOC_PIN10) | \ - PIN_MODE_INPUT(GPIOC_PIN11) | \ - PIN_MODE_INPUT(GPIOC_PIN12) | \ - PIN_MODE_INPUT(GPIOC_PIN13) | \ - PIN_MODE_INPUT(GPIOC_OSC32_IN) | \ - PIN_MODE_INPUT(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOC_LED4) | \ - PIN_OTYPE_PUSHPULL(GPIOC_LED3) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_2M(GPIOC_PIN0) | \ - PIN_OSPEED_2M(GPIOC_PIN1) | \ - PIN_OSPEED_2M(GPIOC_PIN2) | \ - PIN_OSPEED_2M(GPIOC_PIN3) | \ - PIN_OSPEED_2M(GPIOC_PIN4) | \ - PIN_OSPEED_2M(GPIOC_PIN5) | \ - PIN_OSPEED_2M(GPIOC_PIN6) | \ - PIN_OSPEED_2M(GPIOC_PIN7) | \ - PIN_OSPEED_40M(GPIOC_LED4) | \ - PIN_OSPEED_40M(GPIOC_LED3) | \ - PIN_OSPEED_2M(GPIOC_PIN10) | \ - PIN_OSPEED_2M(GPIOC_PIN11) | \ - PIN_OSPEED_2M(GPIOC_PIN12) | \ - PIN_OSPEED_2M(GPIOC_PIN13) | \ - PIN_OSPEED_40M(GPIOC_OSC32_IN) | \ - PIN_OSPEED_40M(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOC_LED4) | \ - PIN_PUPDR_FLOATING(GPIOC_LED3) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ - PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ - PIN_ODR_HIGH(GPIOC_PIN1) | \ - PIN_ODR_HIGH(GPIOC_PIN2) | \ - PIN_ODR_HIGH(GPIOC_PIN3) | \ - PIN_ODR_HIGH(GPIOC_PIN4) | \ - PIN_ODR_HIGH(GPIOC_PIN5) | \ - PIN_ODR_HIGH(GPIOC_PIN6) | \ - PIN_ODR_HIGH(GPIOC_PIN7) | \ - PIN_ODR_LOW(GPIOC_LED4) | \ - PIN_ODR_LOW(GPIOC_LED3) | \ - PIN_ODR_HIGH(GPIOC_PIN10) | \ - PIN_ODR_HIGH(GPIOC_PIN11) | \ - PIN_ODR_HIGH(GPIOC_PIN12) | \ - PIN_ODR_HIGH(GPIOC_PIN13) | \ - PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ - PIN_ODR_HIGH(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0) | \ - PIN_AFIO_AF(GPIOC_PIN1, 0) | \ - PIN_AFIO_AF(GPIOC_PIN2, 0) | \ - PIN_AFIO_AF(GPIOC_PIN3, 0) | \ - PIN_AFIO_AF(GPIOC_PIN4, 0) | \ - PIN_AFIO_AF(GPIOC_PIN5, 0) | \ - PIN_AFIO_AF(GPIOC_PIN6, 0) | \ - PIN_AFIO_AF(GPIOC_PIN7, 0)) -#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_LED4, 0) | \ - PIN_AFIO_AF(GPIOC_LED3, 0) | \ - PIN_AFIO_AF(GPIOC_PIN10, 0) | \ - PIN_AFIO_AF(GPIOC_PIN11, 0) | \ - PIN_AFIO_AF(GPIOC_PIN12, 0) | \ - PIN_AFIO_AF(GPIOC_PIN13, 0) | \ - PIN_AFIO_AF(GPIOC_OSC32_IN, 0) | \ - PIN_AFIO_AF(GPIOC_OSC32_OUT, 0)) - -/* - * GPIOD setup: - * - * PD0 - PIN0 (input pullup). - * PD1 - PIN1 (input pullup). - * PD2 - PIN2 (input pullup). - * PD3 - PIN3 (input pullup). - * PD4 - PIN4 (input pullup). - * PD5 - PIN5 (input pullup). - * PD6 - PIN6 (input pullup). - * PD7 - PIN7 (input pullup). - * PD8 - PIN8 (input pullup). - * PD9 - PIN9 (input pullup). - * PD10 - PIN10 (input pullup). - * PD11 - PIN11 (input pullup). - * PD12 - PIN12 (input pullup). - * PD13 - PIN13 (input pullup). - * PD14 - PIN14 (input pullup). - * PD15 - PIN15 (input pullup). - */ -#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \ - PIN_MODE_INPUT(GPIOD_PIN1) | \ - PIN_MODE_INPUT(GPIOD_PIN2) | \ - PIN_MODE_INPUT(GPIOD_PIN3) | \ - PIN_MODE_INPUT(GPIOD_PIN4) | \ - PIN_MODE_INPUT(GPIOD_PIN5) | \ - PIN_MODE_INPUT(GPIOD_PIN6) | \ - PIN_MODE_INPUT(GPIOD_PIN7) | \ - PIN_MODE_INPUT(GPIOD_PIN8) | \ - PIN_MODE_INPUT(GPIOD_PIN9) | \ - PIN_MODE_INPUT(GPIOD_PIN10) | \ - PIN_MODE_INPUT(GPIOD_PIN11) | \ - PIN_MODE_INPUT(GPIOD_PIN12) | \ - PIN_MODE_INPUT(GPIOD_PIN13) | \ - PIN_MODE_INPUT(GPIOD_PIN14) | \ - PIN_MODE_INPUT(GPIOD_PIN15)) -#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) -#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_2M(GPIOD_PIN0) | \ - PIN_OSPEED_2M(GPIOD_PIN1) | \ - PIN_OSPEED_2M(GPIOD_PIN2) | \ - PIN_OSPEED_2M(GPIOD_PIN3) | \ - PIN_OSPEED_2M(GPIOD_PIN4) | \ - PIN_OSPEED_2M(GPIOD_PIN5) | \ - PIN_OSPEED_2M(GPIOD_PIN6) | \ - PIN_OSPEED_2M(GPIOD_PIN7) | \ - PIN_OSPEED_2M(GPIOD_PIN8) | \ - PIN_OSPEED_2M(GPIOD_PIN9) | \ - PIN_OSPEED_2M(GPIOD_PIN10) | \ - PIN_OSPEED_2M(GPIOD_PIN11) | \ - PIN_OSPEED_2M(GPIOD_PIN12) | \ - PIN_OSPEED_2M(GPIOD_PIN13) | \ - PIN_OSPEED_2M(GPIOD_PIN14) | \ - PIN_OSPEED_2M(GPIOD_PIN15)) -#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN15)) -#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ - PIN_ODR_HIGH(GPIOD_PIN1) | \ - PIN_ODR_HIGH(GPIOD_PIN2) | \ - PIN_ODR_HIGH(GPIOD_PIN3) | \ - PIN_ODR_HIGH(GPIOD_PIN4) | \ - PIN_ODR_HIGH(GPIOD_PIN5) | \ - PIN_ODR_HIGH(GPIOD_PIN6) | \ - PIN_ODR_HIGH(GPIOD_PIN7) | \ - PIN_ODR_HIGH(GPIOD_PIN8) | \ - PIN_ODR_HIGH(GPIOD_PIN9) | \ - PIN_ODR_HIGH(GPIOD_PIN10) | \ - PIN_ODR_HIGH(GPIOD_PIN11) | \ - PIN_ODR_HIGH(GPIOD_PIN12) | \ - PIN_ODR_HIGH(GPIOD_PIN13) | \ - PIN_ODR_HIGH(GPIOD_PIN14) | \ - PIN_ODR_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0) | \ - PIN_AFIO_AF(GPIOD_PIN1, 0) | \ - PIN_AFIO_AF(GPIOD_PIN2, 0) | \ - PIN_AFIO_AF(GPIOD_PIN3, 0) | \ - PIN_AFIO_AF(GPIOD_PIN4, 0) | \ - PIN_AFIO_AF(GPIOD_PIN5, 0) | \ - PIN_AFIO_AF(GPIOD_PIN6, 0) | \ - PIN_AFIO_AF(GPIOD_PIN7, 0)) -#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0) | \ - PIN_AFIO_AF(GPIOD_PIN9, 0) | \ - PIN_AFIO_AF(GPIOD_PIN10, 0) | \ - PIN_AFIO_AF(GPIOD_PIN11, 0) | \ - PIN_AFIO_AF(GPIOD_PIN12, 0) | \ - PIN_AFIO_AF(GPIOD_PIN13, 0) | \ - PIN_AFIO_AF(GPIOD_PIN14, 0) | \ - PIN_AFIO_AF(GPIOD_PIN15, 0)) - -/* - * GPIOF setup: - * - * PF0 - OSC_IN (input floating). - * PF1 - OSC_OUT (input floating). - * PF2 - PIN2 (input pullup). - * PF3 - PIN3 (input pullup). - * PF4 - PIN4 (input pullup). - * PF5 - PIN5 (input pullup). - * PF6 - PIN6 (input pullup). - * PF7 - PIN7 (input pullup). - * PF8 - PIN8 (input pullup). - * PF9 - PIN9 (input pullup). - * PF10 - PIN10 (input pullup). - * PF11 - PIN11 (input pullup). - * PF12 - PIN12 (input pullup). - * PF13 - PIN13 (input pullup). - * PF14 - PIN14 (input pullup). - * PF15 - PIN15 (input pullup). - */ -#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_OSC_IN) | \ - PIN_MODE_INPUT(GPIOF_OSC_OUT) | \ - PIN_MODE_INPUT(GPIOF_PIN2) | \ - PIN_MODE_INPUT(GPIOF_PIN3) | \ - PIN_MODE_INPUT(GPIOF_PIN4) | \ - PIN_MODE_INPUT(GPIOF_PIN5) | \ - PIN_MODE_INPUT(GPIOF_PIN6) | \ - PIN_MODE_INPUT(GPIOF_PIN7) | \ - PIN_MODE_INPUT(GPIOF_PIN8) | \ - PIN_MODE_INPUT(GPIOF_PIN9) | \ - PIN_MODE_INPUT(GPIOF_PIN10) | \ - PIN_MODE_INPUT(GPIOF_PIN11) | \ - PIN_MODE_INPUT(GPIOF_PIN12) | \ - PIN_MODE_INPUT(GPIOF_PIN13) | \ - PIN_MODE_INPUT(GPIOF_PIN14) | \ - PIN_MODE_INPUT(GPIOF_PIN15)) -#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_OSC_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOF_OSC_OUT) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) -#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_2M(GPIOF_OSC_IN) | \ - PIN_OSPEED_2M(GPIOF_OSC_OUT) | \ - PIN_OSPEED_2M(GPIOF_PIN2) | \ - PIN_OSPEED_2M(GPIOF_PIN3) | \ - PIN_OSPEED_2M(GPIOF_PIN4) | \ - PIN_OSPEED_2M(GPIOF_PIN5) | \ - PIN_OSPEED_2M(GPIOF_PIN6) | \ - PIN_OSPEED_2M(GPIOF_PIN7) | \ - PIN_OSPEED_2M(GPIOF_PIN8) | \ - PIN_OSPEED_2M(GPIOF_PIN9) | \ - PIN_OSPEED_2M(GPIOF_PIN10) | \ - PIN_OSPEED_2M(GPIOF_PIN11) | \ - PIN_OSPEED_2M(GPIOF_PIN12) | \ - PIN_OSPEED_2M(GPIOF_PIN13) | \ - PIN_OSPEED_2M(GPIOF_PIN14) | \ - PIN_OSPEED_2M(GPIOF_PIN15)) -#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_OSC_IN) | \ - PIN_PUPDR_FLOATING(GPIOF_OSC_OUT) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN15)) -#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_OSC_IN) | \ - PIN_ODR_HIGH(GPIOF_OSC_OUT) | \ - PIN_ODR_HIGH(GPIOF_PIN2) | \ - PIN_ODR_HIGH(GPIOF_PIN3) | \ - PIN_ODR_HIGH(GPIOF_PIN4) | \ - PIN_ODR_HIGH(GPIOF_PIN5) | \ - PIN_ODR_HIGH(GPIOF_PIN6) | \ - PIN_ODR_HIGH(GPIOF_PIN7) | \ - PIN_ODR_HIGH(GPIOF_PIN8) | \ - PIN_ODR_HIGH(GPIOF_PIN9) | \ - PIN_ODR_HIGH(GPIOF_PIN10) | \ - PIN_ODR_HIGH(GPIOF_PIN11) | \ - PIN_ODR_HIGH(GPIOF_PIN12) | \ - PIN_ODR_HIGH(GPIOF_PIN13) | \ - PIN_ODR_HIGH(GPIOF_PIN14) | \ - PIN_ODR_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_OSC_IN, 0) | \ - PIN_AFIO_AF(GPIOF_OSC_OUT, 0) | \ - PIN_AFIO_AF(GPIOF_PIN2, 0) | \ - PIN_AFIO_AF(GPIOF_PIN3, 0) | \ - PIN_AFIO_AF(GPIOF_PIN4, 0) | \ - PIN_AFIO_AF(GPIOF_PIN5, 0) | \ - PIN_AFIO_AF(GPIOF_PIN6, 0) | \ - PIN_AFIO_AF(GPIOF_PIN7, 0)) -#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0) | \ - PIN_AFIO_AF(GPIOF_PIN9, 0) | \ - PIN_AFIO_AF(GPIOF_PIN10, 0) | \ - PIN_AFIO_AF(GPIOF_PIN11, 0) | \ - PIN_AFIO_AF(GPIOF_PIN12, 0) | \ - PIN_AFIO_AF(GPIOF_PIN13, 0) | \ - PIN_AFIO_AF(GPIOF_PIN14, 0) | \ - PIN_AFIO_AF(GPIOF_PIN15, 0)) - - -#if !defined(_FROM_ASM_) -#ifdef __cplusplus -extern "C" { -#endif - void boardInit(void); -#ifdef __cplusplus -} -#endif -#endif /* _FROM_ASM_ */ - -#endif /* _BOARD_H_ */ diff --git a/firmware/chibios/boards/ST_STM32F0_DISCOVERY/board.mk b/firmware/chibios/boards/ST_STM32F0_DISCOVERY/board.mk deleted file mode 100644 index a8505e9c5c..0000000000 --- a/firmware/chibios/boards/ST_STM32F0_DISCOVERY/board.mk +++ /dev/null @@ -1,5 +0,0 @@ -# List of all the board related files. -BOARDSRC = ${CHIBIOS}/boards/ST_STM32F0_DISCOVERY/board.c - -# Required include directories -BOARDINC = ${CHIBIOS}/boards/ST_STM32F0_DISCOVERY diff --git a/firmware/chibios/boards/ST_STM32F0_DISCOVERY/cfg/board.chcfg b/firmware/chibios/boards/ST_STM32F0_DISCOVERY/cfg/board.chcfg deleted file mode 100644 index ec85130c77..0000000000 --- a/firmware/chibios/boards/ST_STM32F0_DISCOVERY/cfg/board.chcfg +++ /dev/null @@ -1,668 +0,0 @@ - - - - - resources/gencfg/processors/boards/stm32f0xx/templates - .. - - ST STM32F0-Discovery - ST_STM32F0_DISCOVERY - - STM32F0XX_MD - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/firmware/chibios/boards/ST_STM32F4_DISCOVERY/board.mk b/firmware/chibios/boards/ST_STM32F4_DISCOVERY/board.mk deleted file mode 100644 index 1eb1137289..0000000000 --- a/firmware/chibios/boards/ST_STM32F4_DISCOVERY/board.mk +++ /dev/null @@ -1,5 +0,0 @@ -# List of all the board related files. -BOARDSRC = ${CHIBIOS}/boards/ST_STM32F4_DISCOVERY/board.c - -# Required include directories -BOARDINC = ${CHIBIOS}/boards/ST_STM32F4_DISCOVERY diff --git a/firmware/chibios/boards/ST_STM32F4_DISCOVERY/cfg/board.chcfg b/firmware/chibios/boards/ST_STM32F4_DISCOVERY/cfg/board.chcfg deleted file mode 100644 index fbc9086bf9..0000000000 --- a/firmware/chibios/boards/ST_STM32F4_DISCOVERY/cfg/board.chcfg +++ /dev/null @@ -1,1192 +0,0 @@ - - - - - resources/gencfg/processors/boards/stm32f4xx/templates - .. - - STMicroelectronics STM32F4-Discovery - ST_STM32F4_DISCOVERY - - STM32F40_41xxx - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/firmware/chibios/boards/simulator/board.c b/firmware/chibios/boards/simulator/board.c deleted file mode 100644 index 8c1d175038..0000000000 --- a/firmware/chibios/boards/simulator/board.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include "ch.h" -#include "hal.h" - -/** - * @brief PAL setup. - * @details Digital I/O ports static configuration as defined in @p board.h. - */ -#if HAL_USE_PAL || defined(__DOXYGEN__) -const PALConfig pal_default_config = { - {0, 0, 0}, - {0, 0, 0} -}; -#endif - -/* - * Board-specific initialization code. - */ -void boardInit(void) { -} diff --git a/firmware/chibios/boards/simulator/board.h b/firmware/chibios/boards/simulator/board.h deleted file mode 100644 index 0e4e493aa8..0000000000 --- a/firmware/chibios/boards/simulator/board.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -#if !defined(_FROM_ASM_) -#ifdef __cplusplus -extern "C" { -#endif - void boardInit(void); -#ifdef __cplusplus -} -#endif -#endif /* _FROM_ASM_ */ - -#endif /* _BOARD_H_ */ diff --git a/firmware/chibios/boards/simulator/board.mk b/firmware/chibios/boards/simulator/board.mk deleted file mode 100644 index 7c51e1f107..0000000000 --- a/firmware/chibios/boards/simulator/board.mk +++ /dev/null @@ -1,5 +0,0 @@ -# List of all the simulator board related files. -BOARDSRC = ${CHIBIOS}/boards/simulator/board.c - -# Required include directories -BOARDINC = ${CHIBIOS}/boards/simulator diff --git a/firmware/chibios/create_patch.sh b/firmware/chibios/create_patch.sh deleted file mode 100644 index d2ab60d171..0000000000 --- a/firmware/chibios/create_patch.sh +++ /dev/null @@ -1,16 +0,0 @@ -echo Cleaning destination folder... -rm -rf os_untouched -mkdir os_untouched - - -# first we need to create the directory structure -echo Creating folders... -find boards -type d -exec mkdir -p os_untouched\\'{}' \; -find os -type d -exec mkdir -p os_untouched\\'{}' \; -find ext -type d -exec mkdir -p os_untouched\\'{}' \; - -echo Copying files... -# now copy all the files we use from the full ChibiOS bundle into our folder where we only keep the needed files -find boards -type f -exec cp ../../../ChibiOS_2.6.3/'{}' os_untouched/'{}' \; -find os -type f -exec cp ../../../ChibiOS_2.6.3/'{}' os_untouched/'{}' \; -find ext -type f -exec cp ../../../ChibiOS_2.6.3/'{}' os_untouched/'{}' \; diff --git a/firmware/chibios/ext/fatfs/src/ff.c b/firmware/chibios/ext/fatfs/src/ff.c deleted file mode 100644 index bc79e2fffa..0000000000 --- a/firmware/chibios/ext/fatfs/src/ff.c +++ /dev/null @@ -1,4077 +0,0 @@ -/*----------------------------------------------------------------------------/ -/ FatFs - FAT file system module R0.09 (C)ChaN, 2011 -/-----------------------------------------------------------------------------/ -/ FatFs module is a generic FAT file system module for small embedded systems. -/ This is a free software that opened for education, research and commercial -/ developments under license policy of following terms. -/ -/ Copyright (C) 2011, ChaN, all right reserved. -/ -/ * The FatFs module is a free software and there is NO WARRANTY. -/ * No restriction on use. You can use, modify and redistribute it for -/ personal, non-profit or commercial products UNDER YOUR RESPONSIBILITY. -/ * Redistributions of source code must retain the above copyright notice. -/ -/-----------------------------------------------------------------------------/ -/ Feb 26,'06 R0.00 Prototype. -/ -/ Apr 29,'06 R0.01 First stable version. -/ -/ Jun 01,'06 R0.02 Added FAT12 support. -/ Removed unbuffered mode. -/ Fixed a problem on small (<32M) partition. -/ Jun 10,'06 R0.02a Added a configuration option (_FS_MINIMUM). -/ -/ Sep 22,'06 R0.03 Added f_rename(). -/ Changed option _FS_MINIMUM to _FS_MINIMIZE. -/ Dec 11,'06 R0.03a Improved cluster scan algorithm to write files fast. -/ Fixed f_mkdir() creates incorrect directory on FAT32. -/ -/ Feb 04,'07 R0.04 Supported multiple drive system. -/ Changed some interfaces for multiple drive system. -/ Changed f_mountdrv() to f_mount(). -/ Added f_mkfs(). -/ Apr 01,'07 R0.04a Supported multiple partitions on a physical drive. -/ Added a capability of extending file size to f_lseek(). -/ Added minimization level 3. -/ Fixed an endian sensitive code in f_mkfs(). -/ May 05,'07 R0.04b Added a configuration option _USE_NTFLAG. -/ Added FSInfo support. -/ Fixed DBCS name can result FR_INVALID_NAME. -/ Fixed short seek (<= csize) collapses the file object. -/ -/ Aug 25,'07 R0.05 Changed arguments of f_read(), f_write() and f_mkfs(). -/ Fixed f_mkfs() on FAT32 creates incorrect FSInfo. -/ Fixed f_mkdir() on FAT32 creates incorrect directory. -/ Feb 03,'08 R0.05a Added f_truncate() and f_utime(). -/ Fixed off by one error at FAT sub-type determination. -/ Fixed btr in f_read() can be mistruncated. -/ Fixed cached sector is not flushed when create and close without write. -/ -/ Apr 01,'08 R0.06 Added fputc(), fputs(), fprintf() and fgets(). -/ Improved performance of f_lseek() on moving to the same or following cluster. -/ -/ Apr 01,'09 R0.07 Merged Tiny-FatFs as a configuration option. (_FS_TINY) -/ Added long file name feature. -/ Added multiple code page feature. -/ Added re-entrancy for multitask operation. -/ Added auto cluster size selection to f_mkfs(). -/ Added rewind option to f_readdir(). -/ Changed result code of critical errors. -/ Renamed string functions to avoid name collision. -/ Apr 14,'09 R0.07a Separated out OS dependent code on reentrant cfg. -/ Added multiple sector size feature. -/ Jun 21,'09 R0.07c Fixed f_unlink() can return FR_OK on error. -/ Fixed wrong cache control in f_lseek(). -/ Added relative path feature. -/ Added f_chdir() and f_chdrive(). -/ Added proper case conversion to extended char. -/ Nov 03,'09 R0.07e Separated out configuration options from ff.h to ffconf.h. -/ Fixed f_unlink() fails to remove a sub-dir on _FS_RPATH. -/ Fixed name matching error on the 13 char boundary. -/ Added a configuration option, _LFN_UNICODE. -/ Changed f_readdir() to return the SFN with always upper case on non-LFN cfg. -/ -/ May 15,'10 R0.08 Added a memory configuration option. (_USE_LFN = 3) -/ Added file lock feature. (_FS_SHARE) -/ Added fast seek feature. (_USE_FASTSEEK) -/ Changed some types on the API, XCHAR->TCHAR. -/ Changed fname member in the FILINFO structure on Unicode cfg. -/ String functions support UTF-8 encoding files on Unicode cfg. -/ Aug 16,'10 R0.08a Added f_getcwd(). (_FS_RPATH = 2) -/ Added sector erase feature. (_USE_ERASE) -/ Moved file lock semaphore table from fs object to the bss. -/ Fixed a wrong directory entry is created on non-LFN cfg when the given name contains ';'. -/ Fixed f_mkfs() creates wrong FAT32 volume. -/ Jan 15,'11 R0.08b Fast seek feature is also applied to f_read() and f_write(). -/ f_lseek() reports required table size on creating CLMP. -/ Extended format syntax of f_printf function. -/ Ignores duplicated directory separators in given path names. -/ -/ Sep 06,'11 R0.09 f_mkfs() supports multiple partition to finish the multiple partition feature. -/ Added f_fdisk(). (_MULTI_PARTITION = 2) -/---------------------------------------------------------------------------*/ - -#include "ff.h" /* FatFs configurations and declarations */ -#include "diskio.h" /* Declarations of low level disk I/O functions */ - - -/*-------------------------------------------------------------------------- - - Module Private Definitions - ----------------------------------------------------------------------------*/ - -#if _FATFS != 6502 /* Revision ID */ -#error Wrong include file (ff.h). -#endif - - -/* Definitions on sector size */ -#if _MAX_SS != 512 && _MAX_SS != 1024 && _MAX_SS != 2048 && _MAX_SS != 4096 -#error Wrong sector size. -#endif -#if _MAX_SS != 512 -#define SS(fs) ((fs)->ssize) /* Variable sector size */ -#else -#define SS(fs) 512U /* Fixed sector size */ -#endif - - -/* Reentrancy related */ -#if _FS_REENTRANT -#if _USE_LFN == 1 -#error Static LFN work area must not be used in re-entrant configuration. -#endif -#define ENTER_FF(fs) { if (!lock_fs(fs)) return FR_TIMEOUT; } -#define LEAVE_FF(fs, res) { unlock_fs(fs, res); return res; } -#else -#define ENTER_FF(fs) -#define LEAVE_FF(fs, res) return res -#endif - -#define ABORT(fs, res) { fp->flag |= FA__ERROR; LEAVE_FF(fs, res); } - - -/* File shareing feature */ -#if _FS_SHARE -#if _FS_READONLY -#error _FS_SHARE must be 0 on read-only cfg. -#endif -typedef struct { - FATFS *fs; /* File ID 1, volume (NULL:blank entry) */ - DWORD clu; /* File ID 2, directory */ - WORD idx; /* File ID 3, directory index */ - WORD ctr; /* File open counter, 0:none, 0x01..0xFF:read open count, 0x100:write mode */ -} FILESEM; -#endif - - -/* Misc definitions */ -#define LD_CLUST(dir) (((DWORD)LD_WORD(dir+DIR_FstClusHI)<<16) | LD_WORD(dir+DIR_FstClusLO)) -#define ST_CLUST(dir,cl) {ST_WORD(dir+DIR_FstClusLO, cl); ST_WORD(dir+DIR_FstClusHI, (DWORD)cl>>16);} - - -/* DBCS code ranges and SBCS extend char conversion table */ - -#if _CODE_PAGE == 932 /* Japanese Shift-JIS */ -#define _DF1S 0x81 /* DBC 1st byte range 1 start */ -#define _DF1E 0x9F /* DBC 1st byte range 1 end */ -#define _DF2S 0xE0 /* DBC 1st byte range 2 start */ -#define _DF2E 0xFC /* DBC 1st byte range 2 end */ -#define _DS1S 0x40 /* DBC 2nd byte range 1 start */ -#define _DS1E 0x7E /* DBC 2nd byte range 1 end */ -#define _DS2S 0x80 /* DBC 2nd byte range 2 start */ -#define _DS2E 0xFC /* DBC 2nd byte range 2 end */ - -#elif _CODE_PAGE == 936 /* Simplified Chinese GBK */ -#define _DF1S 0x81 -#define _DF1E 0xFE -#define _DS1S 0x40 -#define _DS1E 0x7E -#define _DS2S 0x80 -#define _DS2E 0xFE - -#elif _CODE_PAGE == 949 /* Korean */ -#define _DF1S 0x81 -#define _DF1E 0xFE -#define _DS1S 0x41 -#define _DS1E 0x5A -#define _DS2S 0x61 -#define _DS2E 0x7A -#define _DS3S 0x81 -#define _DS3E 0xFE - -#elif _CODE_PAGE == 950 /* Traditional Chinese Big5 */ -#define _DF1S 0x81 -#define _DF1E 0xFE -#define _DS1S 0x40 -#define _DS1E 0x7E -#define _DS2S 0xA1 -#define _DS2E 0xFE - -#elif _CODE_PAGE == 437 /* U.S. (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F,0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 720 /* Arabic (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x45,0x41,0x84,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x49,0x49,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 737 /* Greek (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \ - 0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xE7,0xE8,0xF1,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 775 /* Baltic (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ - 0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 850 /* Multilingual Latin 1 (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ - 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 852 /* Latin 2 (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F,0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0x9F, \ - 0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF} - -#elif _CODE_PAGE == 855 /* Cyrillic (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F,0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \ - 0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \ - 0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 857 /* Turkish (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x98,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \ - 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0x59,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 858 /* Multilingual Latin 1 + Euro (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ - 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 862 /* Hebrew (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 866 /* Russian (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0x90,0x91,0x92,0x93,0x9d,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F,0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 874 /* Thai (OEM, Windows) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 1250 /* Central Europe (Windows) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \ - 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xA3,0xB4,0xB5,0xB6,0xB7,0xB8,0xA5,0xAA,0xBB,0xBC,0xBD,0xBC,0xAF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF} - -#elif _CODE_PAGE == 1251 /* Cyrillic (Windows) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x82,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x80,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \ - 0xA0,0xA2,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB2,0xA5,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xA3,0xBD,0xBD,0xAF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF} - -#elif _CODE_PAGE == 1252 /* Latin 1 (Windows) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0xAd,0x9B,0x8C,0x9D,0xAE,0x9F, \ - 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F} - -#elif _CODE_PAGE == 1253 /* Greek (Windows) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xA2,0xB8,0xB9,0xBA, \ - 0xE0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xFB,0xBC,0xFD,0xBF,0xFF} - -#elif _CODE_PAGE == 1254 /* Turkish (Windows) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x9D,0x9E,0x9F, \ - 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F} - -#elif _CODE_PAGE == 1255 /* Hebrew (Windows) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 1256 /* Arabic (Windows) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x8C,0x9D,0x9E,0x9F, \ - 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0x41,0xE1,0x41,0xE3,0xE4,0xE5,0xE6,0x43,0x45,0x45,0x45,0x45,0xEC,0xED,0x49,0x49,0xF0,0xF1,0xF2,0xF3,0x4F,0xF5,0xF6,0xF7,0xF8,0x55,0xFA,0x55,0x55,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 1257 /* Baltic (Windows) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xBC,0xBD,0xBE,0xAF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF} - -#elif _CODE_PAGE == 1258 /* Vietnam (OEM, Windows) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0xAC,0x9D,0x9E,0x9F, \ - 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xEC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xFE,0x9F} - -#elif _CODE_PAGE == 1 /* ASCII (for only non-LFN cfg) */ -#if _USE_LFN -#error Cannot use LFN feature without valid code page. -#endif -#define _DF1S 0 - -#else -#error Unknown code page - -#endif - - -/* Character code support macros */ -#define IsUpper(c) (((c)>='A')&&((c)<='Z')) -#define IsLower(c) (((c)>='a')&&((c)<='z')) -#define IsDigit(c) (((c)>='0')&&((c)<='9')) - -#if _DF1S /* Code page is DBCS */ - -#ifdef _DF2S /* Two 1st byte areas */ -#define IsDBCS1(c) (((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) || ((BYTE)(c) >= _DF2S && (BYTE)(c) <= _DF2E)) -#else /* One 1st byte area */ -#define IsDBCS1(c) ((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) -#endif - -#ifdef _DS3S /* Three 2nd byte areas */ -#define IsDBCS2(c) (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E) || ((BYTE)(c) >= _DS3S && (BYTE)(c) <= _DS3E)) -#else /* Two 2nd byte areas */ -#define IsDBCS2(c) (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E)) -#endif - -#else /* Code page is SBCS */ - -#define IsDBCS1(c) 0 -#define IsDBCS2(c) 0 - -#endif /* _DF1S */ - - -/* Name status flags */ -#define NS 11 /* Index of name status byte in fn[] */ -#define NS_LOSS 0x01 /* Out of 8.3 format */ -#define NS_LFN 0x02 /* Force to create LFN entry */ -#define NS_LAST 0x04 /* Last segment */ -#define NS_BODY 0x08 /* Lower case flag (body) */ -#define NS_EXT 0x10 /* Lower case flag (ext) */ -#define NS_DOT 0x20 /* Dot entry */ - - -/* FAT sub-type boundaries */ -/* Note that the FAT spec by Microsoft says 4085 but Windows works with 4087! */ -#define MIN_FAT16 4086 /* Minimum number of clusters for FAT16 */ -#define MIN_FAT32 65526 /* Minimum number of clusters for FAT32 */ - - -/* FatFs refers the members in the FAT structures as byte array instead of -/ structure member because the structure is not binary compatible between -/ different platforms */ - -#define BS_jmpBoot 0 /* Jump instruction (3) */ -#define BS_OEMName 3 /* OEM name (8) */ -#define BPB_BytsPerSec 11 /* Sector size [byte] (2) */ -#define BPB_SecPerClus 13 /* Cluster size [sector] (1) */ -#define BPB_RsvdSecCnt 14 /* Size of reserved area [sector] (2) */ -#define BPB_NumFATs 16 /* Number of FAT copies (1) */ -#define BPB_RootEntCnt 17 /* Number of root dir entries for FAT12/16 (2) */ -#define BPB_TotSec16 19 /* Volume size [sector] (2) */ -#define BPB_Media 21 /* Media descriptor (1) */ -#define BPB_FATSz16 22 /* FAT size [sector] (2) */ -#define BPB_SecPerTrk 24 /* Track size [sector] (2) */ -#define BPB_NumHeads 26 /* Number of heads (2) */ -#define BPB_HiddSec 28 /* Number of special hidden sectors (4) */ -#define BPB_TotSec32 32 /* Volume size [sector] (4) */ -#define BS_DrvNum 36 /* Physical drive number (2) */ -#define BS_BootSig 38 /* Extended boot signature (1) */ -#define BS_VolID 39 /* Volume serial number (4) */ -#define BS_VolLab 43 /* Volume label (8) */ -#define BS_FilSysType 54 /* File system type (1) */ -#define BPB_FATSz32 36 /* FAT size [sector] (4) */ -#define BPB_ExtFlags 40 /* Extended flags (2) */ -#define BPB_FSVer 42 /* File system version (2) */ -#define BPB_RootClus 44 /* Root dir first cluster (4) */ -#define BPB_FSInfo 48 /* Offset of FSInfo sector (2) */ -#define BPB_BkBootSec 50 /* Offset of backup boot sectot (2) */ -#define BS_DrvNum32 64 /* Physical drive number (2) */ -#define BS_BootSig32 66 /* Extended boot signature (1) */ -#define BS_VolID32 67 /* Volume serial number (4) */ -#define BS_VolLab32 71 /* Volume label (8) */ -#define BS_FilSysType32 82 /* File system type (1) */ -#define FSI_LeadSig 0 /* FSI: Leading signature (4) */ -#define FSI_StrucSig 484 /* FSI: Structure signature (4) */ -#define FSI_Free_Count 488 /* FSI: Number of free clusters (4) */ -#define FSI_Nxt_Free 492 /* FSI: Last allocated cluster (4) */ -#define MBR_Table 446 /* MBR: Partition table offset (2) */ -#define SZ_PTE 16 /* MBR: Size of a partition table entry */ -#define BS_55AA 510 /* Boot sector signature (2) */ - -#define DIR_Name 0 /* Short file name (11) */ -#define DIR_Attr 11 /* Attribute (1) */ -#define DIR_NTres 12 /* NT flag (1) */ -#define DIR_CrtTime 14 /* Created time (2) */ -#define DIR_CrtDate 16 /* Created date (2) */ -#define DIR_FstClusHI 20 /* Higher 16-bit of first cluster (2) */ -#define DIR_WrtTime 22 /* Modified time (2) */ -#define DIR_WrtDate 24 /* Modified date (2) */ -#define DIR_FstClusLO 26 /* Lower 16-bit of first cluster (2) */ -#define DIR_FileSize 28 /* File size (4) */ -#define LDIR_Ord 0 /* LFN entry order and LLE flag (1) */ -#define LDIR_Attr 11 /* LFN attribute (1) */ -#define LDIR_Type 12 /* LFN type (1) */ -#define LDIR_Chksum 13 /* Sum of corresponding SFN entry */ -#define LDIR_FstClusLO 26 /* Filled by zero (0) */ -#define SZ_DIR 32 /* Size of a directory entry */ -#define LLE 0x40 /* Last long entry flag in LDIR_Ord */ -#define DDE 0xE5 /* Deleted directory enrty mark in DIR_Name[0] */ -#define NDDE 0x05 /* Replacement of a character collides with DDE */ - - -/*------------------------------------------------------------*/ -/* Module private work area */ -/*------------------------------------------------------------*/ -/* Note that uninitialized variables with static duration are -/ zeroed/nulled at start-up. If not, the compiler or start-up -/ routine is out of ANSI-C standard. -*/ - -#if _VOLUMES -static -FATFS *FatFs[_VOLUMES]; /* Pointer to the file system objects (logical drives) */ -#else -#error Number of volumes must not be 0. -#endif - -static -WORD Fsid; /* File system mount ID */ - -#if _FS_RPATH -static -BYTE CurrVol; /* Current drive */ -#endif - -#if _FS_SHARE -static -FILESEM Files[_FS_SHARE]; /* File lock semaphores */ -#endif - -#if _USE_LFN == 0 /* No LFN feature */ -#define DEF_NAMEBUF BYTE sfn[12] -#define INIT_BUF(dobj) (dobj).fn = sfn -#define FREE_BUF() - -#elif _USE_LFN == 1 /* LFN feature with static working buffer */ -static WCHAR LfnBuf[_MAX_LFN+1]; -#define DEF_NAMEBUF BYTE sfn[12] -#define INIT_BUF(dobj) { (dobj).fn = sfn; (dobj).lfn = LfnBuf; } -#define FREE_BUF() - -#elif _USE_LFN == 2 /* LFN feature with dynamic working buffer on the stack */ -#define DEF_NAMEBUF BYTE sfn[12]; WCHAR lbuf[_MAX_LFN+1] -#define INIT_BUF(dobj) { (dobj).fn = sfn; (dobj).lfn = lbuf; } -#define FREE_BUF() - -#elif _USE_LFN == 3 /* LFN feature with dynamic working buffer on the heap */ -#define DEF_NAMEBUF BYTE sfn[12]; WCHAR *lfn -#define INIT_BUF(dobj) { lfn = ff_memalloc((_MAX_LFN + 1) * 2); \ - if (!lfn) LEAVE_FF((dobj).fs, FR_NOT_ENOUGH_CORE); \ - (dobj).lfn = lfn; (dobj).fn = sfn; } -#define FREE_BUF() ff_memfree(lfn) - -#else -#error Wrong LFN configuration. -#endif - - - - -/*-------------------------------------------------------------------------- - - Module Private Functions - ----------------------------------------------------------------------------*/ - - -/*-----------------------------------------------------------------------*/ -/* String functions */ -/*-----------------------------------------------------------------------*/ - -/* Copy memory to memory */ -static -void mem_cpy (void* dst, const void* src, UINT cnt) { - BYTE *d = (BYTE*)dst; - const BYTE *s = (const BYTE*)src; - -#if _WORD_ACCESS == 1 - while (cnt >= sizeof(int)) { - *(int*)d = *(int*)s; - d += sizeof(int); s += sizeof(int); - cnt -= sizeof(int); - } -#endif - while (cnt--) - *d++ = *s++; -} - -/* Fill memory */ -static -void mem_set (void* dst, int val, UINT cnt) { - BYTE *d = (BYTE*)dst; - - while (cnt--) - *d++ = (BYTE)val; -} - -/* Compare memory to memory */ -static -int mem_cmp (const void* dst, const void* src, UINT cnt) { - const BYTE *d = (const BYTE *)dst, *s = (const BYTE *)src; - int r = 0; - - while (cnt-- && (r = *d++ - *s++) == 0) ; - return r; -} - -/* Check if chr is contained in the string */ -static -int chk_chr (const char* str, int chr) { - while (*str && *str != chr) str++; - return *str; -} - - - -/*-----------------------------------------------------------------------*/ -/* Request/Release grant to access the volume */ -/*-----------------------------------------------------------------------*/ -#if _FS_REENTRANT - -static -int lock_fs ( - FATFS *fs /* File system object */ -) -{ - return ff_req_grant(fs->sobj); -} - - -static -void unlock_fs ( - FATFS *fs, /* File system object */ - FRESULT res /* Result code to be returned */ -) -{ - if (res != FR_NOT_ENABLED && - res != FR_INVALID_DRIVE && - res != FR_INVALID_OBJECT && - res != FR_TIMEOUT) { - ff_rel_grant(fs->sobj); - } -} -#endif - - - -/*-----------------------------------------------------------------------*/ -/* File shareing control functions */ -/*-----------------------------------------------------------------------*/ -#if _FS_SHARE - -static -FRESULT chk_lock ( /* Check if the file can be accessed */ - DIR* dj, /* Directory object pointing the file to be checked */ - int acc /* Desired access (0:Read, 1:Write, 2:Delete/Rename) */ -) -{ - UINT i, be; - - /* Search file semaphore table */ - for (i = be = 0; i < _FS_SHARE; i++) { - if (Files[i].fs) { /* Existing entry */ - if (Files[i].fs == dj->fs && /* Check if the file matched with an open file */ - Files[i].clu == dj->sclust && - Files[i].idx == dj->index) break; - } else { /* Blank entry */ - be++; - } - } - if (i == _FS_SHARE) /* The file is not opened */ - return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES; /* Is there a blank entry for new file? */ - - /* The file has been opened. Reject any open against writing file and all write mode open */ - return (acc || Files[i].ctr == 0x100) ? FR_LOCKED : FR_OK; -} - - -static -int enq_lock (void) /* Check if an entry is available for a new file */ -{ - UINT i; - - for (i = 0; i < _FS_SHARE && Files[i].fs; i++) ; - return (i == _FS_SHARE) ? 0 : 1; -} - - -static -UINT inc_lock ( /* Increment file open counter and returns its index (0:int error) */ - DIR* dj, /* Directory object pointing the file to register or increment */ - int acc /* Desired access mode (0:Read, !0:Write) */ -) -{ - UINT i; - - - for (i = 0; i < _FS_SHARE; i++) { /* Find the file */ - if (Files[i].fs == dj->fs && - Files[i].clu == dj->sclust && - Files[i].idx == dj->index) break; - } - - if (i == _FS_SHARE) { /* Not opened. Register it as new. */ - for (i = 0; i < _FS_SHARE && Files[i].fs; i++) ; - if (i == _FS_SHARE) return 0; /* No space to register (int err) */ - Files[i].fs = dj->fs; - Files[i].clu = dj->sclust; - Files[i].idx = dj->index; - Files[i].ctr = 0; - } - - if (acc && Files[i].ctr) return 0; /* Access violation (int err) */ - - Files[i].ctr = acc ? 0x100 : Files[i].ctr + 1; /* Set semaphore value */ - - return i + 1; -} - - -static -FRESULT dec_lock ( /* Decrement file open counter */ - UINT i /* Semaphore index */ -) -{ - WORD n; - FRESULT res; - - - if (--i < _FS_SHARE) { - n = Files[i].ctr; - if (n == 0x100) n = 0; - if (n) n--; - Files[i].ctr = n; - if (!n) Files[i].fs = 0; - res = FR_OK; - } else { - res = FR_INT_ERR; - } - return res; -} - - -static -void clear_lock ( /* Clear lock entries of the volume */ - FATFS *fs -) -{ - UINT i; - - for (i = 0; i < _FS_SHARE; i++) { - if (Files[i].fs == fs) Files[i].fs = 0; - } -} -#endif - - - -/*-----------------------------------------------------------------------*/ -/* Change window offset */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT move_window ( - FATFS *fs, /* File system object */ - DWORD sector /* Sector number to make appearance in the fs->win[] */ -) /* Move to zero only writes back dirty window */ -{ - DWORD wsect; - - - wsect = fs->winsect; - if (wsect != sector) { /* Changed current window */ -#if !_FS_READONLY - if (fs->wflag) { /* Write back dirty window if needed */ - if (disk_write(fs->drv, fs->win, wsect, 1) != RES_OK) - return FR_DISK_ERR; - fs->wflag = 0; - if (wsect < (fs->fatbase + fs->fsize)) { /* In FAT area */ - BYTE nf; - for (nf = fs->n_fats; nf > 1; nf--) { /* Reflect the change to all FAT copies */ - wsect += fs->fsize; - disk_write(fs->drv, fs->win, wsect, 1); - } - } - } -#endif - if (sector) { - if (disk_read(fs->drv, fs->win, sector, 1) != RES_OK) - return FR_DISK_ERR; - fs->winsect = sector; - } - } - - return FR_OK; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Clean-up cached data */ -/*-----------------------------------------------------------------------*/ -#if !_FS_READONLY -static -FRESULT sync ( /* FR_OK: successful, FR_DISK_ERR: failed */ - FATFS *fs /* File system object */ -) -{ - FRESULT res; - - - res = move_window(fs, 0); - if (res == FR_OK) { - /* Update FSInfo sector if needed */ - if (fs->fs_type == FS_FAT32 && fs->fsi_flag) { - fs->winsect = 0; - /* Create FSInfo structure */ - mem_set(fs->win, 0, 512); - ST_WORD(fs->win+BS_55AA, 0xAA55); - ST_DWORD(fs->win+FSI_LeadSig, 0x41615252); - ST_DWORD(fs->win+FSI_StrucSig, 0x61417272); - ST_DWORD(fs->win+FSI_Free_Count, fs->free_clust); - ST_DWORD(fs->win+FSI_Nxt_Free, fs->last_clust); - /* Write it into the FSInfo sector */ - disk_write(fs->drv, fs->win, fs->fsi_sector, 1); - fs->fsi_flag = 0; - } - /* Make sure that no pending write process in the physical drive */ - if (disk_ioctl(fs->drv, CTRL_SYNC, 0) != RES_OK) - res = FR_DISK_ERR; - } - - return res; -} -#endif - - - - -/*-----------------------------------------------------------------------*/ -/* Get sector# from cluster# */ -/*-----------------------------------------------------------------------*/ - - -DWORD clust2sect ( /* !=0: Sector number, 0: Failed - invalid cluster# */ - FATFS *fs, /* File system object */ - DWORD clst /* Cluster# to be converted */ -) -{ - clst -= 2; - if (clst >= (fs->n_fatent - 2)) return 0; /* Invalid cluster# */ - return clst * fs->csize + fs->database; -} - - - - -/*-----------------------------------------------------------------------*/ -/* FAT access - Read value of a FAT entry */ -/*-----------------------------------------------------------------------*/ - - -DWORD get_fat ( /* 0xFFFFFFFF:Disk error, 1:Internal error, Else:Cluster status */ - FATFS *fs, /* File system object */ - DWORD clst /* Cluster# to get the link information */ -) -{ - UINT wc, bc; - BYTE *p; - - - if (clst < 2 || clst >= fs->n_fatent) /* Chack range */ - return 1; - - switch (fs->fs_type) { - case FS_FAT12 : - bc = (UINT)clst; bc += bc / 2; - if (move_window(fs, fs->fatbase + (bc / SS(fs)))) break; - wc = fs->win[bc % SS(fs)]; bc++; - if (move_window(fs, fs->fatbase + (bc / SS(fs)))) break; - wc |= fs->win[bc % SS(fs)] << 8; - return (clst & 1) ? (wc >> 4) : (wc & 0xFFF); - - case FS_FAT16 : - if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 2)))) break; - p = &fs->win[clst * 2 % SS(fs)]; - return LD_WORD(p); - - case FS_FAT32 : - if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4)))) break; - p = &fs->win[clst * 4 % SS(fs)]; - return LD_DWORD(p) & 0x0FFFFFFF; - } - - return 0xFFFFFFFF; /* An error occurred at the disk I/O layer */ -} - - - - -/*-----------------------------------------------------------------------*/ -/* FAT access - Change value of a FAT entry */ -/*-----------------------------------------------------------------------*/ -#if !_FS_READONLY - -FRESULT put_fat ( - FATFS *fs, /* File system object */ - DWORD clst, /* Cluster# to be changed in range of 2 to fs->n_fatent - 1 */ - DWORD val /* New value to mark the cluster */ -) -{ - UINT bc; - BYTE *p; - FRESULT res; - - - if (clst < 2 || clst >= fs->n_fatent) { /* Check range */ - res = FR_INT_ERR; - - } else { - switch (fs->fs_type) { - case FS_FAT12 : - bc = clst; bc += bc / 2; - res = move_window(fs, fs->fatbase + (bc / SS(fs))); - if (res != FR_OK) break; - p = &fs->win[bc % SS(fs)]; - *p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val; - bc++; - fs->wflag = 1; - res = move_window(fs, fs->fatbase + (bc / SS(fs))); - if (res != FR_OK) break; - p = &fs->win[bc % SS(fs)]; - *p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F)); - break; - - case FS_FAT16 : - res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))); - if (res != FR_OK) break; - p = &fs->win[clst * 2 % SS(fs)]; - ST_WORD(p, (WORD)val); - break; - - case FS_FAT32 : - res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))); - if (res != FR_OK) break; - p = &fs->win[clst * 4 % SS(fs)]; - val |= LD_DWORD(p) & 0xF0000000; - ST_DWORD(p, val); - break; - - default : - res = FR_INT_ERR; - } - fs->wflag = 1; - } - - return res; -} -#endif /* !_FS_READONLY */ - - - - -/*-----------------------------------------------------------------------*/ -/* FAT handling - Remove a cluster chain */ -/*-----------------------------------------------------------------------*/ -#if !_FS_READONLY -static -FRESULT remove_chain ( - FATFS *fs, /* File system object */ - DWORD clst /* Cluster# to remove a chain from */ -) -{ - FRESULT res; - DWORD nxt; -#if _USE_ERASE - DWORD scl = clst, ecl = clst, resion[2]; -#endif - - if (clst < 2 || clst >= fs->n_fatent) { /* Check range */ - res = FR_INT_ERR; - - } else { - res = FR_OK; - while (clst < fs->n_fatent) { /* Not a last link? */ - nxt = get_fat(fs, clst); /* Get cluster status */ - if (nxt == 0) break; /* Empty cluster? */ - if (nxt == 1) { res = FR_INT_ERR; break; } /* Internal error? */ - if (nxt == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } /* Disk error? */ - res = put_fat(fs, clst, 0); /* Mark the cluster "empty" */ - if (res != FR_OK) break; - if (fs->free_clust != 0xFFFFFFFF) { /* Update FSInfo */ - fs->free_clust++; - fs->fsi_flag = 1; - } -#if _USE_ERASE - if (ecl + 1 == nxt) { /* Next cluster is contiguous */ - ecl = nxt; - } else { /* End of contiguous clusters */ - resion[0] = clust2sect(fs, scl); /* Start sector */ - resion[1] = clust2sect(fs, ecl) + fs->csize - 1; /* End sector */ - disk_ioctl(fs->drv, CTRL_ERASE_SECTOR, resion); /* Erase the block */ - scl = ecl = nxt; - } -#endif - clst = nxt; /* Next cluster */ - } - } - - return res; -} -#endif - - - - -/*-----------------------------------------------------------------------*/ -/* FAT handling - Stretch or Create a cluster chain */ -/*-----------------------------------------------------------------------*/ -#if !_FS_READONLY -static -DWORD create_chain ( /* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:Disk error, >=2:New cluster# */ - FATFS *fs, /* File system object */ - DWORD clst /* Cluster# to stretch. 0 means create a new chain. */ -) -{ - DWORD cs, ncl, scl; - FRESULT res; - - - if (clst == 0) { /* Create a new chain */ - scl = fs->last_clust; /* Get suggested start point */ - if (!scl || scl >= fs->n_fatent) scl = 1; - } - else { /* Stretch the current chain */ - cs = get_fat(fs, clst); /* Check the cluster status */ - if (cs < 2) return 1; /* It is an invalid cluster */ - if (cs < fs->n_fatent) return cs; /* It is already followed by next cluster */ - scl = clst; - } - - ncl = scl; /* Start cluster */ - for (;;) { - ncl++; /* Next cluster */ - if (ncl >= fs->n_fatent) { /* Wrap around */ - ncl = 2; - if (ncl > scl) return 0; /* No free cluster */ - } - cs = get_fat(fs, ncl); /* Get the cluster status */ - if (cs == 0) break; /* Found a free cluster */ - if (cs == 0xFFFFFFFF || cs == 1)/* An error occurred */ - return cs; - if (ncl == scl) return 0; /* No free cluster */ - } - - res = put_fat(fs, ncl, 0x0FFFFFFF); /* Mark the new cluster "last link" */ - if (res == FR_OK && clst != 0) { - res = put_fat(fs, clst, ncl); /* Link it to the previous one if needed */ - } - if (res == FR_OK) { - fs->last_clust = ncl; /* Update FSINFO */ - if (fs->free_clust != 0xFFFFFFFF) { - fs->free_clust--; - fs->fsi_flag = 1; - } - } else { - ncl = (res == FR_DISK_ERR) ? 0xFFFFFFFF : 1; - } - - return ncl; /* Return new cluster number or error code */ -} -#endif /* !_FS_READONLY */ - - - -/*-----------------------------------------------------------------------*/ -/* FAT handling - Convert offset into cluster with link map table */ -/*-----------------------------------------------------------------------*/ - -#if _USE_FASTSEEK -static -DWORD clmt_clust ( /* <2:Error, >=2:Cluster number */ - FIL* fp, /* Pointer to the file object */ - DWORD ofs /* File offset to be converted to cluster# */ -) -{ - DWORD cl, ncl, *tbl; - - - tbl = fp->cltbl + 1; /* Top of CLMT */ - cl = ofs / SS(fp->fs) / fp->fs->csize; /* Cluster order from top of the file */ - for (;;) { - ncl = *tbl++; /* Number of cluters in the fragment */ - if (!ncl) return 0; /* End of table? (error) */ - if (cl < ncl) break; /* In this fragment? */ - cl -= ncl; tbl++; /* Next fragment */ - } - return cl + *tbl; /* Return the cluster number */ -} -#endif /* _USE_FASTSEEK */ - - - -/*-----------------------------------------------------------------------*/ -/* Directory handling - Set directory index */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT dir_sdi ( - DIR *dj, /* Pointer to directory object */ - WORD idx /* Directory index number */ -) -{ - DWORD clst; - WORD ic; - - - dj->index = idx; - clst = dj->sclust; - if (clst == 1 || clst >= dj->fs->n_fatent) /* Check start cluster range */ - return FR_INT_ERR; - if (!clst && dj->fs->fs_type == FS_FAT32) /* Replace cluster# 0 with root cluster# if in FAT32 */ - clst = dj->fs->dirbase; - - if (clst == 0) { /* Static table (root-dir in FAT12/16) */ - dj->clust = clst; - if (idx >= dj->fs->n_rootdir) /* Index is out of range */ - return FR_INT_ERR; - dj->sect = dj->fs->dirbase + idx / (SS(dj->fs) / SZ_DIR); /* Sector# */ - } - else { /* Dynamic table (sub-dirs or root-dir in FAT32) */ - ic = SS(dj->fs) / SZ_DIR * dj->fs->csize; /* Entries per cluster */ - while (idx >= ic) { /* Follow cluster chain */ - clst = get_fat(dj->fs, clst); /* Get next cluster */ - if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ - if (clst < 2 || clst >= dj->fs->n_fatent) /* Reached to end of table or int error */ - return FR_INT_ERR; - idx -= ic; - } - dj->clust = clst; - dj->sect = clust2sect(dj->fs, clst) + idx / (SS(dj->fs) / SZ_DIR); /* Sector# */ - } - - dj->dir = dj->fs->win + (idx % (SS(dj->fs) / SZ_DIR)) * SZ_DIR; /* Ptr to the entry in the sector */ - - return FR_OK; /* Seek succeeded */ -} - - - - -/*-----------------------------------------------------------------------*/ -/* Directory handling - Move directory index next */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT dir_next ( /* FR_OK:Succeeded, FR_NO_FILE:End of table, FR_DENIED:EOT and could not stretch */ - DIR *dj, /* Pointer to directory object */ - int stretch /* 0: Do not stretch table, 1: Stretch table if needed */ -) -{ - DWORD clst; - WORD i; - - - stretch = stretch; /* To suppress warning on read-only cfg. */ - i = dj->index + 1; - if (!i || !dj->sect) /* Report EOT when index has reached 65535 */ - return FR_NO_FILE; - - if (!(i % (SS(dj->fs) / SZ_DIR))) { /* Sector changed? */ - dj->sect++; /* Next sector */ - - if (dj->clust == 0) { /* Static table */ - if (i >= dj->fs->n_rootdir) /* Report EOT when end of table */ - return FR_NO_FILE; - } - else { /* Dynamic table */ - if (((i / (SS(dj->fs) / SZ_DIR)) & (dj->fs->csize - 1)) == 0) { /* Cluster changed? */ - clst = get_fat(dj->fs, dj->clust); /* Get next cluster */ - if (clst <= 1) return FR_INT_ERR; - if (clst == 0xFFFFFFFF) return FR_DISK_ERR; - if (clst >= dj->fs->n_fatent) { /* When it reached end of dynamic table */ -#if !_FS_READONLY - BYTE c; - if (!stretch) return FR_NO_FILE; /* When do not stretch, report EOT */ - clst = create_chain(dj->fs, dj->clust); /* Stretch cluster chain */ - if (clst == 0) return FR_DENIED; /* No free cluster */ - if (clst == 1) return FR_INT_ERR; - if (clst == 0xFFFFFFFF) return FR_DISK_ERR; - /* Clean-up stretched table */ - if (move_window(dj->fs, 0)) return FR_DISK_ERR; /* Flush active window */ - mem_set(dj->fs->win, 0, SS(dj->fs)); /* Clear window buffer */ - dj->fs->winsect = clust2sect(dj->fs, clst); /* Cluster start sector */ - for (c = 0; c < dj->fs->csize; c++) { /* Fill the new cluster with 0 */ - dj->fs->wflag = 1; - if (move_window(dj->fs, 0)) return FR_DISK_ERR; - dj->fs->winsect++; - } - dj->fs->winsect -= c; /* Rewind window address */ -#else - return FR_NO_FILE; /* Report EOT */ -#endif - } - dj->clust = clst; /* Initialize data for new cluster */ - dj->sect = clust2sect(dj->fs, clst); - } - } - } - - dj->index = i; - dj->dir = dj->fs->win + (i % (SS(dj->fs) / SZ_DIR)) * SZ_DIR; - - return FR_OK; -} - - - - -/*-----------------------------------------------------------------------*/ -/* LFN handling - Test/Pick/Fit an LFN segment from/to directory entry */ -/*-----------------------------------------------------------------------*/ -#if _USE_LFN -static -const BYTE LfnOfs[] = {1,3,5,7,9,14,16,18,20,22,24,28,30}; /* Offset of LFN chars in the directory entry */ - - -static -int cmp_lfn ( /* 1:Matched, 0:Not matched */ - WCHAR *lfnbuf, /* Pointer to the LFN to be compared */ - BYTE *dir /* Pointer to the directory entry containing a part of LFN */ -) -{ - UINT i, s; - WCHAR wc, uc; - - - i = ((dir[LDIR_Ord] & ~LLE) - 1) * 13; /* Get offset in the LFN buffer */ - s = 0; wc = 1; - do { - uc = LD_WORD(dir+LfnOfs[s]); /* Pick an LFN character from the entry */ - if (wc) { /* Last char has not been processed */ - wc = ff_wtoupper(uc); /* Convert it to upper case */ - if (i >= _MAX_LFN || wc != ff_wtoupper(lfnbuf[i++])) /* Compare it */ - return 0; /* Not matched */ - } else { - if (uc != 0xFFFF) return 0; /* Check filler */ - } - } while (++s < 13); /* Repeat until all chars in the entry are checked */ - - if ((dir[LDIR_Ord] & LLE) && wc && lfnbuf[i]) /* Last segment matched but different length */ - return 0; - - return 1; /* The part of LFN matched */ -} - - - -static -int pick_lfn ( /* 1:Succeeded, 0:Buffer overflow */ - WCHAR *lfnbuf, /* Pointer to the Unicode-LFN buffer */ - BYTE *dir /* Pointer to the directory entry */ -) -{ - UINT i, s; - WCHAR wc, uc; - - - i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13; /* Offset in the LFN buffer */ - - s = 0; wc = 1; - do { - uc = LD_WORD(dir+LfnOfs[s]); /* Pick an LFN character from the entry */ - if (wc) { /* Last char has not been processed */ - if (i >= _MAX_LFN) return 0; /* Buffer overflow? */ - lfnbuf[i++] = wc = uc; /* Store it */ - } else { - if (uc != 0xFFFF) return 0; /* Check filler */ - } - } while (++s < 13); /* Read all character in the entry */ - - if (dir[LDIR_Ord] & LLE) { /* Put terminator if it is the last LFN part */ - if (i >= _MAX_LFN) return 0; /* Buffer overflow? */ - lfnbuf[i] = 0; - } - - return 1; -} - - -#if !_FS_READONLY -static -void fit_lfn ( - const WCHAR *lfnbuf, /* Pointer to the LFN buffer */ - BYTE *dir, /* Pointer to the directory entry */ - BYTE ord, /* LFN order (1-20) */ - BYTE sum /* SFN sum */ -) -{ - UINT i, s; - WCHAR wc; - - - dir[LDIR_Chksum] = sum; /* Set check sum */ - dir[LDIR_Attr] = AM_LFN; /* Set attribute. LFN entry */ - dir[LDIR_Type] = 0; - ST_WORD(dir+LDIR_FstClusLO, 0); - - i = (ord - 1) * 13; /* Get offset in the LFN buffer */ - s = wc = 0; - do { - if (wc != 0xFFFF) wc = lfnbuf[i++]; /* Get an effective char */ - ST_WORD(dir+LfnOfs[s], wc); /* Put it */ - if (!wc) wc = 0xFFFF; /* Padding chars following last char */ - } while (++s < 13); - if (wc == 0xFFFF || !lfnbuf[i]) ord |= LLE; /* Bottom LFN part is the start of LFN sequence */ - dir[LDIR_Ord] = ord; /* Set the LFN order */ -} - -#endif -#endif - - - -/*-----------------------------------------------------------------------*/ -/* Create numbered name */ -/*-----------------------------------------------------------------------*/ -#if _USE_LFN -void gen_numname ( - BYTE *dst, /* Pointer to generated SFN */ - const BYTE *src, /* Pointer to source SFN to be modified */ - const WCHAR *lfn, /* Pointer to LFN */ - WORD seq /* Sequence number */ -) -{ - BYTE ns[8], c; - UINT i, j; - - - mem_cpy(dst, src, 11); - - if (seq > 5) { /* On many collisions, generate a hash number instead of sequential number */ - do seq = (seq >> 1) + (seq << 15) + (WORD)*lfn++; while (*lfn); - } - - /* itoa (hexdecimal) */ - i = 7; - do { - c = (seq % 16) + '0'; - if (c > '9') c += 7; - ns[i--] = c; - seq /= 16; - } while (seq); - ns[i] = '~'; - - /* Append the number */ - for (j = 0; j < i && dst[j] != ' '; j++) { - if (IsDBCS1(dst[j])) { - if (j == i - 1) break; - j++; - } - } - do { - dst[j++] = (i < 8) ? ns[i++] : ' '; - } while (j < 8); -} -#endif - - - - -/*-----------------------------------------------------------------------*/ -/* Calculate sum of an SFN */ -/*-----------------------------------------------------------------------*/ -#if _USE_LFN -static -BYTE sum_sfn ( - const BYTE *dir /* Ptr to directory entry */ -) -{ - BYTE sum = 0; - UINT n = 11; - - do sum = (sum >> 1) + (sum << 7) + *dir++; while (--n); - return sum; -} -#endif - - - - -/*-----------------------------------------------------------------------*/ -/* Directory handling - Find an object in the directory */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT dir_find ( - DIR *dj /* Pointer to the directory object linked to the file name */ -) -{ - FRESULT res; - BYTE c, *dir; -#if _USE_LFN - BYTE a, ord, sum; -#endif - - res = dir_sdi(dj, 0); /* Rewind directory object */ - if (res != FR_OK) return res; - -#if _USE_LFN - ord = sum = 0xFF; -#endif - do { - res = move_window(dj->fs, dj->sect); - if (res != FR_OK) break; - dir = dj->dir; /* Ptr to the directory entry of current index */ - c = dir[DIR_Name]; - if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */ -#if _USE_LFN /* LFN configuration */ - a = dir[DIR_Attr] & AM_MASK; - if (c == DDE || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */ - ord = 0xFF; - } else { - if (a == AM_LFN) { /* An LFN entry is found */ - if (dj->lfn) { - if (c & LLE) { /* Is it start of LFN sequence? */ - sum = dir[LDIR_Chksum]; - c &= ~LLE; ord = c; /* LFN start order */ - dj->lfn_idx = dj->index; - } - /* Check validity of the LFN entry and compare it with given name */ - ord = (c == ord && sum == dir[LDIR_Chksum] && cmp_lfn(dj->lfn, dir)) ? ord - 1 : 0xFF; - } - } else { /* An SFN entry is found */ - if (!ord && sum == sum_sfn(dir)) break; /* LFN matched? */ - ord = 0xFF; dj->lfn_idx = 0xFFFF; /* Reset LFN sequence */ - if (!(dj->fn[NS] & NS_LOSS) && !mem_cmp(dir, dj->fn, 11)) break; /* SFN matched? */ - } - } -#else /* Non LFN configuration */ - if (!(dir[DIR_Attr] & AM_VOL) && !mem_cmp(dir, dj->fn, 11)) /* Is it a valid entry? */ - break; -#endif - res = dir_next(dj, 0); /* Next entry */ - } while (res == FR_OK); - - return res; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Read an object from the directory */ -/*-----------------------------------------------------------------------*/ -#if _FS_MINIMIZE <= 1 -static -FRESULT dir_read ( - DIR *dj /* Pointer to the directory object that pointing the entry to be read */ -) -{ - FRESULT res; - BYTE c, *dir; -#if _USE_LFN - BYTE a, ord = 0xFF, sum = 0xFF; -#endif - - res = FR_NO_FILE; - while (dj->sect) { - res = move_window(dj->fs, dj->sect); - if (res != FR_OK) break; - dir = dj->dir; /* Ptr to the directory entry of current index */ - c = dir[DIR_Name]; - if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */ -#if _USE_LFN /* LFN configuration */ - a = dir[DIR_Attr] & AM_MASK; - if (c == DDE || (!_FS_RPATH && c == '.') || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */ - ord = 0xFF; - } else { - if (a == AM_LFN) { /* An LFN entry is found */ - if (c & LLE) { /* Is it start of LFN sequence? */ - sum = dir[LDIR_Chksum]; - c &= ~LLE; ord = c; - dj->lfn_idx = dj->index; - } - /* Check LFN validity and capture it */ - ord = (c == ord && sum == dir[LDIR_Chksum] && pick_lfn(dj->lfn, dir)) ? ord - 1 : 0xFF; - } else { /* An SFN entry is found */ - if (ord || sum != sum_sfn(dir)) /* Is there a valid LFN? */ - dj->lfn_idx = 0xFFFF; /* It has no LFN. */ - break; - } - } -#else /* Non LFN configuration */ - if (c != DDE && (_FS_RPATH || c != '.') && !(dir[DIR_Attr] & AM_VOL)) /* Is it a valid entry? */ - break; -#endif - res = dir_next(dj, 0); /* Next entry */ - if (res != FR_OK) break; - } - - if (res != FR_OK) dj->sect = 0; - - return res; -} -#endif - - - -/*-----------------------------------------------------------------------*/ -/* Register an object to the directory */ -/*-----------------------------------------------------------------------*/ -#if !_FS_READONLY -static -FRESULT dir_register ( /* FR_OK:Successful, FR_DENIED:No free entry or too many SFN collision, FR_DISK_ERR:Disk error */ - DIR *dj /* Target directory with object name to be created */ -) -{ - FRESULT res; - BYTE c, *dir; -#if _USE_LFN /* LFN configuration */ - WORD n, ne, is; - BYTE sn[12], *fn, sum; - WCHAR *lfn; - - - fn = dj->fn; lfn = dj->lfn; - mem_cpy(sn, fn, 12); - - if (_FS_RPATH && (sn[NS] & NS_DOT)) /* Cannot create dot entry */ - return FR_INVALID_NAME; - - if (sn[NS] & NS_LOSS) { /* When LFN is out of 8.3 format, generate a numbered name */ - fn[NS] = 0; dj->lfn = 0; /* Find only SFN */ - for (n = 1; n < 100; n++) { - gen_numname(fn, sn, lfn, n); /* Generate a numbered name */ - res = dir_find(dj); /* Check if the name collides with existing SFN */ - if (res != FR_OK) break; - } - if (n == 100) return FR_DENIED; /* Abort if too many collisions */ - if (res != FR_NO_FILE) return res; /* Abort if the result is other than 'not collided' */ - fn[NS] = sn[NS]; dj->lfn = lfn; - } - - if (sn[NS] & NS_LFN) { /* When LFN is to be created, reserve an SFN + LFN entries. */ - for (ne = 0; lfn[ne]; ne++) ; - ne = (ne + 25) / 13; - } else { /* Otherwise reserve only an SFN entry. */ - ne = 1; - } - - /* Reserve contiguous entries */ - res = dir_sdi(dj, 0); - if (res != FR_OK) return res; - n = is = 0; - do { - res = move_window(dj->fs, dj->sect); - if (res != FR_OK) break; - c = *dj->dir; /* Check the entry status */ - if (c == DDE || c == 0) { /* Is it a blank entry? */ - if (n == 0) is = dj->index; /* First index of the contiguous entry */ - if (++n == ne) break; /* A contiguous entry that required count is found */ - } else { - n = 0; /* Not a blank entry. Restart to search */ - } - res = dir_next(dj, 1); /* Next entry with table stretch */ - } while (res == FR_OK); - - if (res == FR_OK && ne > 1) { /* Initialize LFN entry if needed */ - res = dir_sdi(dj, is); - if (res == FR_OK) { - sum = sum_sfn(dj->fn); /* Sum of the SFN tied to the LFN */ - ne--; - do { /* Store LFN entries in bottom first */ - res = move_window(dj->fs, dj->sect); - if (res != FR_OK) break; - fit_lfn(dj->lfn, dj->dir, (BYTE)ne, sum); - dj->fs->wflag = 1; - res = dir_next(dj, 0); /* Next entry */ - } while (res == FR_OK && --ne); - } - } - -#else /* Non LFN configuration */ - res = dir_sdi(dj, 0); - if (res == FR_OK) { - do { /* Find a blank entry for the SFN */ - res = move_window(dj->fs, dj->sect); - if (res != FR_OK) break; - c = *dj->dir; - if (c == DDE || c == 0) break; /* Is it a blank entry? */ - res = dir_next(dj, 1); /* Next entry with table stretch */ - } while (res == FR_OK); - } -#endif - - if (res == FR_OK) { /* Initialize the SFN entry */ - res = move_window(dj->fs, dj->sect); - if (res == FR_OK) { - dir = dj->dir; - mem_set(dir, 0, SZ_DIR); /* Clean the entry */ - mem_cpy(dir, dj->fn, 11); /* Put SFN */ -#if _USE_LFN - dir[DIR_NTres] = *(dj->fn+NS) & (NS_BODY | NS_EXT); /* Put NT flag */ -#endif - dj->fs->wflag = 1; - } - } - - return res; -} -#endif /* !_FS_READONLY */ - - - - -/*-----------------------------------------------------------------------*/ -/* Remove an object from the directory */ -/*-----------------------------------------------------------------------*/ -#if !_FS_READONLY && !_FS_MINIMIZE -static -FRESULT dir_remove ( /* FR_OK: Successful, FR_DISK_ERR: A disk error */ - DIR *dj /* Directory object pointing the entry to be removed */ -) -{ - FRESULT res; -#if _USE_LFN /* LFN configuration */ - WORD i; - - i = dj->index; /* SFN index */ - res = dir_sdi(dj, (WORD)((dj->lfn_idx == 0xFFFF) ? i : dj->lfn_idx)); /* Goto the SFN or top of the LFN entries */ - if (res == FR_OK) { - do { - res = move_window(dj->fs, dj->sect); - if (res != FR_OK) break; - *dj->dir = DDE; /* Mark the entry "deleted" */ - dj->fs->wflag = 1; - if (dj->index >= i) break; /* When reached SFN, all entries of the object has been deleted. */ - res = dir_next(dj, 0); /* Next entry */ - } while (res == FR_OK); - if (res == FR_NO_FILE) res = FR_INT_ERR; - } - -#else /* Non LFN configuration */ - res = dir_sdi(dj, dj->index); - if (res == FR_OK) { - res = move_window(dj->fs, dj->sect); - if (res == FR_OK) { - *dj->dir = DDE; /* Mark the entry "deleted" */ - dj->fs->wflag = 1; - } - } -#endif - - return res; -} -#endif /* !_FS_READONLY */ - - - - -/*-----------------------------------------------------------------------*/ -/* Pick a segment and create the object name in directory form */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT create_name ( - DIR *dj, /* Pointer to the directory object */ - const TCHAR **path /* Pointer to pointer to the segment in the path string */ -) -{ -#ifdef _EXCVT - static const BYTE excvt[] = _EXCVT; /* Upper conversion table for extended chars */ -#endif - -#if _USE_LFN /* LFN configuration */ - BYTE b, cf; - WCHAR w, *lfn; - UINT i, ni, si, di; - const TCHAR *p; - - /* Create LFN in Unicode */ - for (p = *path; *p == '/' || *p == '\\'; p++) ; /* Strip duplicated separator */ - lfn = dj->lfn; - si = di = 0; - for (;;) { - w = p[si++]; /* Get a character */ - if (w < ' ' || w == '/' || w == '\\') break; /* Break on end of segment */ - if (di >= _MAX_LFN) /* Reject too long name */ - return FR_INVALID_NAME; -#if !_LFN_UNICODE - w &= 0xFF; - if (IsDBCS1(w)) { /* Check if it is a DBC 1st byte (always false on SBCS cfg) */ - b = (BYTE)p[si++]; /* Get 2nd byte */ - if (!IsDBCS2(b)) - return FR_INVALID_NAME; /* Reject invalid sequence */ - w = (w << 8) + b; /* Create a DBC */ - } - w = ff_convert(w, 1); /* Convert ANSI/OEM to Unicode */ - if (!w) return FR_INVALID_NAME; /* Reject invalid code */ -#endif - if (w < 0x80 && chk_chr("\"*:<>\?|\x7F", w)) /* Reject illegal chars for LFN */ - return FR_INVALID_NAME; - lfn[di++] = w; /* Store the Unicode char */ - } - *path = &p[si]; /* Return pointer to the next segment */ - cf = (w < ' ') ? NS_LAST : 0; /* Set last segment flag if end of path */ -#if _FS_RPATH - if ((di == 1 && lfn[di-1] == '.') || /* Is this a dot entry? */ - (di == 2 && lfn[di-1] == '.' && lfn[di-2] == '.')) { - lfn[di] = 0; - for (i = 0; i < 11; i++) - dj->fn[i] = (i < di) ? '.' : ' '; - dj->fn[i] = cf | NS_DOT; /* This is a dot entry */ - return FR_OK; - } -#endif - while (di) { /* Strip trailing spaces and dots */ - w = lfn[di-1]; - if (w != ' ' && w != '.') break; - di--; - } - if (!di) return FR_INVALID_NAME; /* Reject nul string */ - - lfn[di] = 0; /* LFN is created */ - - /* Create SFN in directory form */ - mem_set(dj->fn, ' ', 11); - for (si = 0; lfn[si] == ' ' || lfn[si] == '.'; si++) ; /* Strip leading spaces and dots */ - if (si) cf |= NS_LOSS | NS_LFN; - while (di && lfn[di - 1] != '.') di--; /* Find extension (di<=si: no extension) */ - - b = i = 0; ni = 8; - for (;;) { - w = lfn[si++]; /* Get an LFN char */ - if (!w) break; /* Break on end of the LFN */ - if (w == ' ' || (w == '.' && si != di)) { /* Remove spaces and dots */ - cf |= NS_LOSS | NS_LFN; continue; - } - - if (i >= ni || si == di) { /* Extension or end of SFN */ - if (ni == 11) { /* Long extension */ - cf |= NS_LOSS | NS_LFN; break; - } - if (si != di) cf |= NS_LOSS | NS_LFN; /* Out of 8.3 format */ - if (si > di) break; /* No extension */ - si = di; i = 8; ni = 11; /* Enter extension section */ - b <<= 2; continue; - } - - if (w >= 0x80) { /* Non ASCII char */ -#ifdef _EXCVT - w = ff_convert(w, 0); /* Unicode -> OEM code */ - if (w) w = excvt[w - 0x80]; /* Convert extended char to upper (SBCS) */ -#else - w = ff_convert(ff_wtoupper(w), 0); /* Upper converted Unicode -> OEM code */ -#endif - cf |= NS_LFN; /* Force create LFN entry */ - } - - if (_DF1S && w >= 0x100) { /* Double byte char (always false on SBCS cfg) */ - if (i >= ni - 1) { - cf |= NS_LOSS | NS_LFN; i = ni; continue; - } - dj->fn[i++] = (BYTE)(w >> 8); - } else { /* Single byte char */ - if (!w || chk_chr("+,;=[]", w)) { /* Replace illegal chars for SFN */ - w = '_'; cf |= NS_LOSS | NS_LFN;/* Lossy conversion */ - } else { - if (IsUpper(w)) { /* ASCII large capital */ - b |= 2; - } else { - if (IsLower(w)) { /* ASCII small capital */ - b |= 1; w -= 0x20; - } - } - } - } - dj->fn[i++] = (BYTE)w; - } - - if (dj->fn[0] == DDE) dj->fn[0] = NDDE; /* If the first char collides with deleted mark, replace it with 0x05 */ - - if (ni == 8) b <<= 2; - if ((b & 0x0C) == 0x0C || (b & 0x03) == 0x03) /* Create LFN entry when there are composite capitals */ - cf |= NS_LFN; - if (!(cf & NS_LFN)) { /* When LFN is in 8.3 format without extended char, NT flags are created */ - if ((b & 0x03) == 0x01) cf |= NS_EXT; /* NT flag (Extension has only small capital) */ - if ((b & 0x0C) == 0x04) cf |= NS_BODY; /* NT flag (Filename has only small capital) */ - } - - dj->fn[NS] = cf; /* SFN is created */ - - return FR_OK; - - -#else /* Non-LFN configuration */ - BYTE b, c, d, *sfn; - UINT ni, si, i; - const char *p; - - /* Create file name in directory form */ - for (p = *path; *p == '/' || *p == '\\'; p++) ; /* Strip duplicated separator */ - sfn = dj->fn; - mem_set(sfn, ' ', 11); - si = i = b = 0; ni = 8; -#if _FS_RPATH - if (p[si] == '.') { /* Is this a dot entry? */ - for (;;) { - c = (BYTE)p[si++]; - if (c != '.' || si >= 3) break; - sfn[i++] = c; - } - if (c != '/' && c != '\\' && c > ' ') return FR_INVALID_NAME; - *path = &p[si]; /* Return pointer to the next segment */ - sfn[NS] = (c <= ' ') ? NS_LAST | NS_DOT : NS_DOT; /* Set last segment flag if end of path */ - return FR_OK; - } -#endif - for (;;) { - c = (BYTE)p[si++]; - if (c <= ' ' || c == '/' || c == '\\') break; /* Break on end of segment */ - if (c == '.' || i >= ni) { - if (ni != 8 || c != '.') return FR_INVALID_NAME; - i = 8; ni = 11; - b <<= 2; continue; - } - if (c >= 0x80) { /* Extended char? */ - b |= 3; /* Eliminate NT flag */ -#ifdef _EXCVT - c = excvt[c-0x80]; /* Upper conversion (SBCS) */ -#else -#if !_DF1S /* ASCII only cfg */ - return FR_INVALID_NAME; -#endif -#endif - } - if (IsDBCS1(c)) { /* Check if it is a DBC 1st byte (always false on SBCS cfg) */ - d = (BYTE)p[si++]; /* Get 2nd byte */ - if (!IsDBCS2(d) || i >= ni - 1) /* Reject invalid DBC */ - return FR_INVALID_NAME; - sfn[i++] = c; - sfn[i++] = d; - } else { /* Single byte code */ - if (chk_chr("\"*+,:;<=>\?[]|\x7F", c)) /* Reject illegal chrs for SFN */ - return FR_INVALID_NAME; - if (IsUpper(c)) { /* ASCII large capital? */ - b |= 2; - } else { - if (IsLower(c)) { /* ASCII small capital? */ - b |= 1; c -= 0x20; - } - } - sfn[i++] = c; - } - } - *path = &p[si]; /* Return pointer to the next segment */ - c = (c <= ' ') ? NS_LAST : 0; /* Set last segment flag if end of path */ - - if (!i) return FR_INVALID_NAME; /* Reject nul string */ - if (sfn[0] == DDE) sfn[0] = NDDE; /* When first char collides with DDE, replace it with 0x05 */ - - if (ni == 8) b <<= 2; - if ((b & 0x03) == 0x01) c |= NS_EXT; /* NT flag (Name extension has only small capital) */ - if ((b & 0x0C) == 0x04) c |= NS_BODY; /* NT flag (Name body has only small capital) */ - - sfn[NS] = c; /* Store NT flag, File name is created */ - - return FR_OK; -#endif -} - - - - -/*-----------------------------------------------------------------------*/ -/* Get file information from directory entry */ -/*-----------------------------------------------------------------------*/ -#if _FS_MINIMIZE <= 1 -static -void get_fileinfo ( /* No return code */ - DIR *dj, /* Pointer to the directory object */ - FILINFO *fno /* Pointer to the file information to be filled */ -) -{ - UINT i; - BYTE nt, *dir; - TCHAR *p, c; - - - p = fno->fname; - if (dj->sect) { - dir = dj->dir; - nt = dir[DIR_NTres]; /* NT flag */ - for (i = 0; i < 8; i++) { /* Copy name body */ - c = dir[i]; - if (c == ' ') break; - if (c == NDDE) c = (TCHAR)DDE; - if (_USE_LFN && (nt & NS_BODY) && IsUpper(c)) c += 0x20; -#if _LFN_UNICODE - if (IsDBCS1(c) && i < 7 && IsDBCS2(dir[i+1])) - c = (c << 8) | dir[++i]; - c = ff_convert(c, 1); - if (!c) c = '?'; -#endif - *p++ = c; - } - if (dir[8] != ' ') { /* Copy name extension */ - *p++ = '.'; - for (i = 8; i < 11; i++) { - c = dir[i]; - if (c == ' ') break; - if (_USE_LFN && (nt & NS_EXT) && IsUpper(c)) c += 0x20; -#if _LFN_UNICODE - if (IsDBCS1(c) && i < 10 && IsDBCS2(dir[i+1])) - c = (c << 8) | dir[++i]; - c = ff_convert(c, 1); - if (!c) c = '?'; -#endif - *p++ = c; - } - } - fno->fattrib = dir[DIR_Attr]; /* Attribute */ - fno->fsize = LD_DWORD(dir+DIR_FileSize); /* Size */ - fno->fdate = LD_WORD(dir+DIR_WrtDate); /* Date */ - fno->ftime = LD_WORD(dir+DIR_WrtTime); /* Time */ - } - *p = 0; /* Terminate SFN str by a \0 */ - -#if _USE_LFN - if (fno->lfname && fno->lfsize) { - TCHAR *tp = fno->lfname; - WCHAR w, *lfn; - - i = 0; - if (dj->sect && dj->lfn_idx != 0xFFFF) {/* Get LFN if available */ - lfn = dj->lfn; - while ((w = *lfn++) != 0) { /* Get an LFN char */ -#if !_LFN_UNICODE - w = ff_convert(w, 0); /* Unicode -> OEM conversion */ - if (!w) { i = 0; break; } /* Could not convert, no LFN */ - if (_DF1S && w >= 0x100) /* Put 1st byte if it is a DBC (always false on SBCS cfg) */ - tp[i++] = (TCHAR)(w >> 8); -#endif - if (i >= fno->lfsize - 1) { i = 0; break; } /* Buffer overflow, no LFN */ - tp[i++] = (TCHAR)w; - } - } - tp[i] = 0; /* Terminate the LFN str by a \0 */ - } -#endif -} -#endif /* _FS_MINIMIZE <= 1 */ - - - - -/*-----------------------------------------------------------------------*/ -/* Follow a file path */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT follow_path ( /* FR_OK(0): successful, !=0: error code */ - DIR *dj, /* Directory object to return last directory and found object */ - const TCHAR *path /* Full-path string to find a file or directory */ -) -{ - FRESULT res; - BYTE *dir, ns; - - -#if _FS_RPATH - if (*path == '/' || *path == '\\') { /* There is a heading separator */ - path++; dj->sclust = 0; /* Strip it and start from the root dir */ - } else { /* No heading separator */ - dj->sclust = dj->fs->cdir; /* Start from the current dir */ - } -#else - if (*path == '/' || *path == '\\') /* Strip heading separator if exist */ - path++; - dj->sclust = 0; /* Start from the root dir */ -#endif - - if ((UINT)*path < ' ') { /* Nul path means the start directory itself */ - res = dir_sdi(dj, 0); - dj->dir = 0; - - } else { /* Follow path */ - for (;;) { - res = create_name(dj, &path); /* Get a segment */ - if (res != FR_OK) break; - res = dir_find(dj); /* Find it */ - ns = *(dj->fn+NS); - if (res != FR_OK) { /* Failed to find the object */ - if (res != FR_NO_FILE) break; /* Abort if any hard error occured */ - /* Object not found */ - if (_FS_RPATH && (ns & NS_DOT)) { /* If dot entry is not exit */ - dj->sclust = 0; dj->dir = 0; /* It is the root dir */ - res = FR_OK; - if (!(ns & NS_LAST)) continue; - } else { /* Could not find the object */ - if (!(ns & NS_LAST)) res = FR_NO_PATH; - } - break; - } - if (ns & NS_LAST) break; /* Last segment match. Function completed. */ - dir = dj->dir; /* There is next segment. Follow the sub directory */ - if (!(dir[DIR_Attr] & AM_DIR)) { /* Cannot follow because it is a file */ - res = FR_NO_PATH; break; - } - dj->sclust = LD_CLUST(dir); - } - } - - return res; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Load a sector and check if it is an FAT Volume Boot Record */ -/*-----------------------------------------------------------------------*/ - -static -BYTE check_fs ( /* 0:FAT-VBR, 1:Valid BR but not FAT, 2:Not a BR, 3:Disk error */ - FATFS *fs, /* File system object */ - DWORD sect /* Sector# (lba) to check if it is an FAT boot record or not */ -) -{ - if (disk_read(fs->drv, fs->win, sect, 1) != RES_OK) /* Load boot record */ - return 3; - if (LD_WORD(&fs->win[BS_55AA]) != 0xAA55) /* Check record signature (always placed at offset 510 even if the sector size is >512) */ - return 2; - - if ((LD_DWORD(&fs->win[BS_FilSysType]) & 0xFFFFFF) == 0x544146) /* Check "FAT" string */ - return 0; - if ((LD_DWORD(&fs->win[BS_FilSysType32]) & 0xFFFFFF) == 0x544146) - return 0; - - return 1; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Check if the file system object is valid or not */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT chk_mounted ( /* FR_OK(0): successful, !=0: any error occurred */ - const TCHAR **path, /* Pointer to pointer to the path name (drive number) */ - FATFS **rfs, /* Pointer to pointer to the found file system object */ - BYTE chk_wp /* !=0: Check media write protection for write access */ -) -{ - BYTE fmt, b, pi, *tbl; - UINT vol; - DSTATUS stat; - DWORD bsect, fasize, tsect, sysect, nclst, szbfat; - WORD nrsv; - const TCHAR *p = *path; - FATFS *fs; - - /* Get logical drive number from the path name */ - vol = p[0] - '0'; /* Is there a drive number? */ - if (vol <= 9 && p[1] == ':') { /* Found a drive number, get and strip it */ - p += 2; *path = p; /* Return pointer to the path name */ - } else { /* No drive number is given */ -#if _FS_RPATH - vol = CurrVol; /* Use current drive */ -#else - vol = 0; /* Use drive 0 */ -#endif - } - - /* Check if the file system object is valid or not */ - if (vol >= _VOLUMES) /* Is the drive number valid? */ - return FR_INVALID_DRIVE; - *rfs = fs = FatFs[vol]; /* Return pointer to the corresponding file system object */ - if (!fs) return FR_NOT_ENABLED; /* Is the file system object available? */ - - ENTER_FF(fs); /* Lock file system */ - - if (fs->fs_type) { /* If the logical drive has been mounted */ - stat = disk_status(fs->drv); - if (!(stat & STA_NOINIT)) { /* and the physical drive is kept initialized (has not been changed), */ - if (!_FS_READONLY && chk_wp && (stat & STA_PROTECT)) /* Check write protection if needed */ - return FR_WRITE_PROTECTED; - return FR_OK; /* The file system object is valid */ - } - } - - /* The file system object is not valid. */ - /* Following code attempts to mount the volume. (analyze BPB and initialize the fs object) */ - - fs->fs_type = 0; /* Clear the file system object */ - fs->drv = LD2PD(vol); /* Bind the logical drive and a physical drive */ - stat = disk_initialize(fs->drv); /* Initialize low level disk I/O layer */ - if (stat & STA_NOINIT) /* Check if the initialization succeeded */ - return FR_NOT_READY; /* Failed to initialize due to no media or hard error */ - if (!_FS_READONLY && chk_wp && (stat & STA_PROTECT)) /* Check disk write protection if needed */ - return FR_WRITE_PROTECTED; -#if _MAX_SS != 512 /* Get disk sector size (variable sector size cfg only) */ - if (disk_ioctl(fs->drv, GET_SECTOR_SIZE, &fs->ssize) != RES_OK) - return FR_DISK_ERR; -#endif - /* Search FAT partition on the drive. Supports only generic partitionings, FDISK and SFD. */ - fmt = check_fs(fs, bsect = 0); /* Load sector 0 and check if it is an FAT-VBR (in SFD) */ - if (LD2PT(vol) && !fmt) fmt = 1; /* Force non-SFD if the volume is forced partition */ - if (fmt == 1) { /* Not an FAT-VBR, the physical drive can be partitioned */ - /* Check the partition listed in the partition table */ - pi = LD2PT(vol); - if (pi) pi--; - tbl = &fs->win[MBR_Table + pi * SZ_PTE];/* Partition table */ - if (tbl[4]) { /* Is the partition existing? */ - bsect = LD_DWORD(&tbl[8]); /* Partition offset in LBA */ - fmt = check_fs(fs, bsect); /* Check the partition */ - } - } - if (fmt == 3) return FR_DISK_ERR; - if (fmt) return FR_NO_FILESYSTEM; /* No FAT volume is found */ - - /* An FAT volume is found. Following code initializes the file system object */ - - if (LD_WORD(fs->win+BPB_BytsPerSec) != SS(fs)) /* (BPB_BytsPerSec must be equal to the physical sector size) */ - return FR_NO_FILESYSTEM; - - fasize = LD_WORD(fs->win+BPB_FATSz16); /* Number of sectors per FAT */ - if (!fasize) fasize = LD_DWORD(fs->win+BPB_FATSz32); - fs->fsize = fasize; - - fs->n_fats = b = fs->win[BPB_NumFATs]; /* Number of FAT copies */ - if (b != 1 && b != 2) return FR_NO_FILESYSTEM; /* (Must be 1 or 2) */ - fasize *= b; /* Number of sectors for FAT area */ - - fs->csize = b = fs->win[BPB_SecPerClus]; /* Number of sectors per cluster */ - if (!b || (b & (b - 1))) return FR_NO_FILESYSTEM; /* (Must be power of 2) */ - - fs->n_rootdir = LD_WORD(fs->win+BPB_RootEntCnt); /* Number of root directory entries */ - if (fs->n_rootdir % (SS(fs) / SZ_DIR)) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be sector aligned) */ - - tsect = LD_WORD(fs->win+BPB_TotSec16); /* Number of sectors on the volume */ - if (!tsect) tsect = LD_DWORD(fs->win+BPB_TotSec32); - - nrsv = LD_WORD(fs->win+BPB_RsvdSecCnt); /* Number of reserved sectors */ - if (!nrsv) return FR_NO_FILESYSTEM; /* (BPB_RsvdSecCnt must not be 0) */ - - /* Determine the FAT sub type */ - sysect = nrsv + fasize + fs->n_rootdir / (SS(fs) / SZ_DIR); /* RSV+FAT+DIR */ - if (tsect < sysect) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ - nclst = (tsect - sysect) / fs->csize; /* Number of clusters */ - if (!nclst) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ - fmt = FS_FAT12; - if (nclst >= MIN_FAT16) fmt = FS_FAT16; - if (nclst >= MIN_FAT32) fmt = FS_FAT32; - - /* Boundaries and Limits */ - fs->n_fatent = nclst + 2; /* Number of FAT entries */ - fs->database = bsect + sysect; /* Data start sector */ - fs->fatbase = bsect + nrsv; /* FAT start sector */ - if (fmt == FS_FAT32) { - if (fs->n_rootdir) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be 0) */ - fs->dirbase = LD_DWORD(fs->win+BPB_RootClus); /* Root directory start cluster */ - szbfat = fs->n_fatent * 4; /* (Required FAT size) */ - } else { - if (!fs->n_rootdir) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must not be 0) */ - fs->dirbase = fs->fatbase + fasize; /* Root directory start sector */ - szbfat = (fmt == FS_FAT16) ? /* (Required FAT size) */ - fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1); - } - if (fs->fsize < (szbfat + (SS(fs) - 1)) / SS(fs)) /* (BPB_FATSz must not be less than required) */ - return FR_NO_FILESYSTEM; - -#if !_FS_READONLY - /* Initialize cluster allocation information */ - fs->free_clust = 0xFFFFFFFF; - fs->last_clust = 0; - - /* Get fsinfo if available */ - if (fmt == FS_FAT32) { - fs->fsi_flag = 0; - fs->fsi_sector = bsect + LD_WORD(fs->win+BPB_FSInfo); - if (disk_read(fs->drv, fs->win, fs->fsi_sector, 1) == RES_OK && - LD_WORD(fs->win+BS_55AA) == 0xAA55 && - LD_DWORD(fs->win+FSI_LeadSig) == 0x41615252 && - LD_DWORD(fs->win+FSI_StrucSig) == 0x61417272) { - fs->last_clust = LD_DWORD(fs->win+FSI_Nxt_Free); - fs->free_clust = LD_DWORD(fs->win+FSI_Free_Count); - } - } -#endif - fs->fs_type = fmt; /* FAT sub-type */ - fs->id = ++Fsid; /* File system mount ID */ - fs->winsect = 0; /* Invalidate sector cache */ - fs->wflag = 0; -#if _FS_RPATH - fs->cdir = 0; /* Current directory (root dir) */ -#endif -#if _FS_SHARE /* Clear file lock semaphores */ - clear_lock(fs); -#endif - - return FR_OK; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Check if the file/dir object is valid or not */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT validate ( /* FR_OK(0): The object is valid, !=0: Invalid */ - FATFS *fs, /* Pointer to the file system object */ - WORD id /* Member id of the target object to be checked */ -) -{ - if (!fs || !fs->fs_type || fs->id != id) - return FR_INVALID_OBJECT; - - ENTER_FF(fs); /* Lock file system */ - - if (disk_status(fs->drv) & STA_NOINIT) - return FR_NOT_READY; - - return FR_OK; -} - - - - -/*-------------------------------------------------------------------------- - - Public Functions - ---------------------------------------------------------------------------*/ - - - -/*-----------------------------------------------------------------------*/ -/* Mount/Unmount a Logical Drive */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_mount ( - BYTE vol, /* Logical drive number to be mounted/unmounted */ - FATFS *fs /* Pointer to new file system object (NULL for unmount)*/ -) -{ - FATFS *rfs; - - - if (vol >= _VOLUMES) /* Check if the drive number is valid */ - return FR_INVALID_DRIVE; - rfs = FatFs[vol]; /* Get current fs object */ - - if (rfs) { -#if _FS_SHARE - clear_lock(rfs); -#endif -#if _FS_REENTRANT /* Discard sync object of the current volume */ - if (!ff_del_syncobj(rfs->sobj)) return FR_INT_ERR; -#endif - rfs->fs_type = 0; /* Clear old fs object */ - } - - if (fs) { - fs->fs_type = 0; /* Clear new fs object */ -#if _FS_REENTRANT /* Create sync object for the new volume */ - if (!ff_cre_syncobj(vol, &fs->sobj)) return FR_INT_ERR; -#endif - } - FatFs[vol] = fs; /* Register new fs object */ - - return FR_OK; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Open or Create a File */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_open ( - FIL *fp, /* Pointer to the blank file object */ - const TCHAR *path, /* Pointer to the file name */ - BYTE mode /* Access mode and file open mode flags */ -) -{ - FRESULT res; - DIR dj; - BYTE *dir; - DEF_NAMEBUF; - - - fp->fs = 0; /* Clear file object */ - -#if !_FS_READONLY - mode &= FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW; - res = chk_mounted(&path, &dj.fs, (BYTE)(mode & ~FA_READ)); -#else - mode &= FA_READ; - res = chk_mounted(&path, &dj.fs, 0); -#endif - INIT_BUF(dj); - if (res == FR_OK) - res = follow_path(&dj, path); /* Follow the file path */ - dir = dj.dir; - -#if !_FS_READONLY /* R/W configuration */ - if (res == FR_OK) { - if (!dir) /* Current dir itself */ - res = FR_INVALID_NAME; -#if _FS_SHARE - else - res = chk_lock(&dj, (mode & ~FA_READ) ? 1 : 0); -#endif - } - /* Create or Open a file */ - if (mode & (FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW)) { - DWORD dw, cl; - - if (res != FR_OK) { /* No file, create new */ - if (res == FR_NO_FILE) /* There is no file to open, create a new entry */ -#if _FS_SHARE - res = enq_lock() ? dir_register(&dj) : FR_TOO_MANY_OPEN_FILES; -#else - res = dir_register(&dj); -#endif - mode |= FA_CREATE_ALWAYS; /* File is created */ - dir = dj.dir; /* New entry */ - } - else { /* Any object is already existing */ - if (dir[DIR_Attr] & (AM_RDO | AM_DIR)) { /* Cannot overwrite it (R/O or DIR) */ - res = FR_DENIED; - } else { - if (mode & FA_CREATE_NEW) /* Cannot create as new file */ - res = FR_EXIST; - } - } - if (res == FR_OK && (mode & FA_CREATE_ALWAYS)) { /* Truncate it if overwrite mode */ - dw = get_fattime(); /* Created time */ - ST_DWORD(dir+DIR_CrtTime, dw); - dir[DIR_Attr] = 0; /* Reset attribute */ - ST_DWORD(dir+DIR_FileSize, 0); /* size = 0 */ - cl = LD_CLUST(dir); /* Get start cluster */ - ST_CLUST(dir, 0); /* cluster = 0 */ - dj.fs->wflag = 1; - if (cl) { /* Remove the cluster chain if exist */ - dw = dj.fs->winsect; - res = remove_chain(dj.fs, cl); - if (res == FR_OK) { - dj.fs->last_clust = cl - 1; /* Reuse the cluster hole */ - res = move_window(dj.fs, dw); - } - } - } - } - else { /* Open an existing file */ - if (res == FR_OK) { /* Follow succeeded */ - if (dir[DIR_Attr] & AM_DIR) { /* It is a directory */ - res = FR_NO_FILE; - } else { - if ((mode & FA_WRITE) && (dir[DIR_Attr] & AM_RDO)) /* R/O violation */ - res = FR_DENIED; - } - } - } - if (res == FR_OK) { - if (mode & FA_CREATE_ALWAYS) /* Set file change flag if created or overwritten */ - mode |= FA__WRITTEN; - fp->dir_sect = dj.fs->winsect; /* Pointer to the directory entry */ - fp->dir_ptr = dir; -#if _FS_SHARE - fp->lockid = inc_lock(&dj, (mode & ~FA_READ) ? 1 : 0); - if (!fp->lockid) res = FR_INT_ERR; -#endif - } - -#else /* R/O configuration */ - if (res == FR_OK) { /* Follow succeeded */ - if (!dir) { /* Current dir itself */ - res = FR_INVALID_NAME; - } else { - if (dir[DIR_Attr] & AM_DIR) /* It is a directory */ - res = FR_NO_FILE; - } - } -#endif - FREE_BUF(); - - if (res == FR_OK) { - fp->flag = mode; /* File access mode */ - fp->sclust = LD_CLUST(dir); /* File start cluster */ - fp->fsize = LD_DWORD(dir+DIR_FileSize); /* File size */ - fp->fptr = 0; /* File pointer */ - fp->dsect = 0; -#if _USE_FASTSEEK - fp->cltbl = 0; /* Normal seek mode */ -#endif - fp->fs = dj.fs; fp->id = dj.fs->id; /* Validate file object */ - } - - LEAVE_FF(dj.fs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Read File */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_read ( - FIL *fp, /* Pointer to the file object */ - void *buff, /* Pointer to data buffer */ - UINT btr, /* Number of bytes to read */ - UINT *br /* Pointer to number of bytes read */ -) -{ - FRESULT res; - DWORD clst, sect, remain; - UINT rcnt, cc; - BYTE csect, *rbuff = buff; - - - *br = 0; /* Initialize byte counter */ - - res = validate(fp->fs, fp->id); /* Check validity */ - if (res != FR_OK) LEAVE_FF(fp->fs, res); - if (fp->flag & FA__ERROR) /* Aborted file? */ - LEAVE_FF(fp->fs, FR_INT_ERR); - if (!(fp->flag & FA_READ)) /* Check access mode */ - LEAVE_FF(fp->fs, FR_DENIED); - remain = fp->fsize - fp->fptr; - if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */ - - for ( ; btr; /* Repeat until all data read */ - rbuff += rcnt, fp->fptr += rcnt, *br += rcnt, btr -= rcnt) { - if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ - csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */ - if (!csect) { /* On the cluster boundary? */ - if (fp->fptr == 0) { /* On the top of the file? */ - clst = fp->sclust; /* Follow from the origin */ - } else { /* Middle or end of the file */ -#if _USE_FASTSEEK - if (fp->cltbl) - clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */ - else -#endif - clst = get_fat(fp->fs, fp->clust); /* Follow cluster chain on the FAT */ - } - if (clst < 2) ABORT(fp->fs, FR_INT_ERR); - if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); - fp->clust = clst; /* Update current cluster */ - } - sect = clust2sect(fp->fs, fp->clust); /* Get current sector */ - if (!sect) ABORT(fp->fs, FR_INT_ERR); - sect += csect; - cc = btr / SS(fp->fs); /* When remaining bytes >= sector size, */ - if (cc) { /* Read maximum contiguous sectors directly */ - if (csect + cc > fp->fs->csize) /* Clip at cluster boundary */ - cc = fp->fs->csize - csect; - if (disk_read(fp->fs->drv, rbuff, sect, (BYTE)cc) != RES_OK) - ABORT(fp->fs, FR_DISK_ERR); -#if !_FS_READONLY && _FS_MINIMIZE <= 2 /* Replace one of the read sectors with cached data if it contains a dirty sector */ -#if _FS_TINY - if (fp->fs->wflag && fp->fs->winsect - sect < cc) - mem_cpy(rbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), fp->fs->win, SS(fp->fs)); -#else - if ((fp->flag & FA__DIRTY) && fp->dsect - sect < cc) - mem_cpy(rbuff + ((fp->dsect - sect) * SS(fp->fs)), fp->buf, SS(fp->fs)); -#endif -#endif - rcnt = SS(fp->fs) * cc; /* Number of bytes transferred */ - continue; - } -#if !_FS_TINY - if (fp->dsect != sect) { /* Load data sector if not in cache */ -#if !_FS_READONLY - if (fp->flag & FA__DIRTY) { /* Write-back dirty sector cache */ - if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK) - ABORT(fp->fs, FR_DISK_ERR); - fp->flag &= ~FA__DIRTY; - } -#endif - if (disk_read(fp->fs->drv, fp->buf, sect, 1) != RES_OK) /* Fill sector cache */ - ABORT(fp->fs, FR_DISK_ERR); - } -#endif - fp->dsect = sect; - } - rcnt = SS(fp->fs) - (fp->fptr % SS(fp->fs)); /* Get partial sector data from sector buffer */ - if (rcnt > btr) rcnt = btr; -#if _FS_TINY - if (move_window(fp->fs, fp->dsect)) /* Move sector window */ - ABORT(fp->fs, FR_DISK_ERR); - mem_cpy(rbuff, &fp->fs->win[fp->fptr % SS(fp->fs)], rcnt); /* Pick partial sector */ -#else - mem_cpy(rbuff, &fp->buf[fp->fptr % SS(fp->fs)], rcnt); /* Pick partial sector */ -#endif - } - - LEAVE_FF(fp->fs, FR_OK); -} - - - - -#if !_FS_READONLY -/*-----------------------------------------------------------------------*/ -/* Write File */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_write ( - FIL *fp, /* Pointer to the file object */ - const void *buff, /* Pointer to the data to be written */ - UINT btw, /* Number of bytes to write */ - UINT *bw /* Pointer to number of bytes written */ -) -{ - FRESULT res; - DWORD clst, sect; - UINT wcnt, cc; - const BYTE *wbuff = buff; - BYTE csect; - - - *bw = 0; /* Initialize byte counter */ - - res = validate(fp->fs, fp->id); /* Check validity */ - if (res != FR_OK) LEAVE_FF(fp->fs, res); - if (fp->flag & FA__ERROR) /* Aborted file? */ - LEAVE_FF(fp->fs, FR_INT_ERR); - if (!(fp->flag & FA_WRITE)) /* Check access mode */ - LEAVE_FF(fp->fs, FR_DENIED); - if ((DWORD)(fp->fsize + btw) < fp->fsize) btw = 0; /* File size cannot reach 4GB */ - - for ( ; btw; /* Repeat until all data written */ - wbuff += wcnt, fp->fptr += wcnt, *bw += wcnt, btw -= wcnt) { - if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ - csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */ - if (!csect) { /* On the cluster boundary? */ - if (fp->fptr == 0) { /* On the top of the file? */ - clst = fp->sclust; /* Follow from the origin */ - if (clst == 0) /* When no cluster is allocated, */ - fp->sclust = clst = create_chain(fp->fs, 0); /* Create a new cluster chain */ - } else { /* Middle or end of the file */ -#if _USE_FASTSEEK - if (fp->cltbl) - clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */ - else -#endif - clst = create_chain(fp->fs, fp->clust); /* Follow or stretch cluster chain on the FAT */ - } - if (clst == 0) break; /* Could not allocate a new cluster (disk full) */ - if (clst == 1) ABORT(fp->fs, FR_INT_ERR); - if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); - fp->clust = clst; /* Update current cluster */ - } -#if _FS_TINY - if (fp->fs->winsect == fp->dsect && move_window(fp->fs, 0)) /* Write-back sector cache */ - ABORT(fp->fs, FR_DISK_ERR); -#else - if (fp->flag & FA__DIRTY) { /* Write-back sector cache */ - if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK) - ABORT(fp->fs, FR_DISK_ERR); - fp->flag &= ~FA__DIRTY; - } -#endif - sect = clust2sect(fp->fs, fp->clust); /* Get current sector */ - if (!sect) ABORT(fp->fs, FR_INT_ERR); - sect += csect; - cc = btw / SS(fp->fs); /* When remaining bytes >= sector size, */ - if (cc) { /* Write maximum contiguous sectors directly */ - if (csect + cc > fp->fs->csize) /* Clip at cluster boundary */ - cc = fp->fs->csize - csect; - if (disk_write(fp->fs->drv, wbuff, sect, (BYTE)cc) != RES_OK) - ABORT(fp->fs, FR_DISK_ERR); -#if _FS_TINY - if (fp->fs->winsect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */ - mem_cpy(fp->fs->win, wbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), SS(fp->fs)); - fp->fs->wflag = 0; - } -#else - if (fp->dsect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */ - mem_cpy(fp->buf, wbuff + ((fp->dsect - sect) * SS(fp->fs)), SS(fp->fs)); - fp->flag &= ~FA__DIRTY; - } -#endif - wcnt = SS(fp->fs) * cc; /* Number of bytes transferred */ - continue; - } -#if _FS_TINY - if (fp->fptr >= fp->fsize) { /* Avoid silly cache filling at growing edge */ - if (move_window(fp->fs, 0)) ABORT(fp->fs, FR_DISK_ERR); - fp->fs->winsect = sect; - } -#else - if (fp->dsect != sect) { /* Fill sector cache with file data */ - if (fp->fptr < fp->fsize && - disk_read(fp->fs->drv, fp->buf, sect, 1) != RES_OK) - ABORT(fp->fs, FR_DISK_ERR); - } -#endif - fp->dsect = sect; - } - wcnt = SS(fp->fs) - (fp->fptr % SS(fp->fs));/* Put partial sector into file I/O buffer */ - if (wcnt > btw) wcnt = btw; -#if _FS_TINY - if (move_window(fp->fs, fp->dsect)) /* Move sector window */ - ABORT(fp->fs, FR_DISK_ERR); - mem_cpy(&fp->fs->win[fp->fptr % SS(fp->fs)], wbuff, wcnt); /* Fit partial sector */ - fp->fs->wflag = 1; -#else - mem_cpy(&fp->buf[fp->fptr % SS(fp->fs)], wbuff, wcnt); /* Fit partial sector */ - fp->flag |= FA__DIRTY; -#endif - } - - if (fp->fptr > fp->fsize) fp->fsize = fp->fptr; /* Update file size if needed */ - fp->flag |= FA__WRITTEN; /* Set file change flag */ - - LEAVE_FF(fp->fs, FR_OK); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Synchronize the File Object */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_sync ( - FIL *fp /* Pointer to the file object */ -) -{ - FRESULT res; - DWORD tim; - BYTE *dir; - - - res = validate(fp->fs, fp->id); /* Check validity of the object */ - if (res == FR_OK) { - if (fp->flag & FA__WRITTEN) { /* Has the file been written? */ -#if !_FS_TINY /* Write-back dirty buffer */ - if (fp->flag & FA__DIRTY) { - if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK) - LEAVE_FF(fp->fs, FR_DISK_ERR); - fp->flag &= ~FA__DIRTY; - } -#endif - /* Update the directory entry */ - res = move_window(fp->fs, fp->dir_sect); - if (res == FR_OK) { - dir = fp->dir_ptr; - dir[DIR_Attr] |= AM_ARC; /* Set archive bit */ - ST_DWORD(dir+DIR_FileSize, fp->fsize); /* Update file size */ - ST_CLUST(dir, fp->sclust); /* Update start cluster */ - tim = get_fattime(); /* Update updated time */ - ST_DWORD(dir+DIR_WrtTime, tim); - fp->flag &= ~FA__WRITTEN; - fp->fs->wflag = 1; - res = sync(fp->fs); - } - } - } - - LEAVE_FF(fp->fs, res); -} - -#endif /* !_FS_READONLY */ - - - - -/*-----------------------------------------------------------------------*/ -/* Close File */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_close ( - FIL *fp /* Pointer to the file object to be closed */ -) -{ - FRESULT res; - -#if _FS_READONLY - FATFS *fs = fp->fs; - res = validate(fs, fp->id); - if (res == FR_OK) fp->fs = 0; /* Discard file object */ - LEAVE_FF(fs, res); - -#else - res = f_sync(fp); /* Flush cached data */ -#if _FS_SHARE - if (res == FR_OK) { /* Decrement open counter */ -#if _FS_REENTRANT - res = validate(fp->fs, fp->id); - if (res == FR_OK) { - res = dec_lock(fp->lockid); - unlock_fs(fp->fs, FR_OK); - } -#else - res = dec_lock(fp->lockid); -#endif - } -#endif - if (res == FR_OK) fp->fs = 0; /* Discard file object */ - return res; -#endif -} - - - - -/*-----------------------------------------------------------------------*/ -/* Current Drive/Directory Handlings */ -/*-----------------------------------------------------------------------*/ - -#if _FS_RPATH >= 1 - -FRESULT f_chdrive ( - BYTE drv /* Drive number */ -) -{ - if (drv >= _VOLUMES) return FR_INVALID_DRIVE; - - CurrVol = drv; - - return FR_OK; -} - - - -FRESULT f_chdir ( - const TCHAR *path /* Pointer to the directory path */ -) -{ - FRESULT res; - DIR dj; - DEF_NAMEBUF; - - - res = chk_mounted(&path, &dj.fs, 0); - if (res == FR_OK) { - INIT_BUF(dj); - res = follow_path(&dj, path); /* Follow the path */ - FREE_BUF(); - if (res == FR_OK) { /* Follow completed */ - if (!dj.dir) { - dj.fs->cdir = dj.sclust; /* Start directory itself */ - } else { - if (dj.dir[DIR_Attr] & AM_DIR) /* Reached to the directory */ - dj.fs->cdir = LD_CLUST(dj.dir); - else - res = FR_NO_PATH; /* Reached but a file */ - } - } - if (res == FR_NO_FILE) res = FR_NO_PATH; - } - - LEAVE_FF(dj.fs, res); -} - - -#if _FS_RPATH >= 2 -FRESULT f_getcwd ( - TCHAR *path, /* Pointer to the directory path */ - UINT sz_path /* Size of path */ -) -{ - FRESULT res; - DIR dj; - UINT i, n; - DWORD ccl; - TCHAR *tp; - FILINFO fno; - DEF_NAMEBUF; - - - *path = 0; - res = chk_mounted((const TCHAR**)&path, &dj.fs, 0); /* Get current volume */ - if (res == FR_OK) { - INIT_BUF(dj); - i = sz_path; /* Bottom of buffer (dir stack base) */ - dj.sclust = dj.fs->cdir; /* Start to follow upper dir from current dir */ - while ((ccl = dj.sclust) != 0) { /* Repeat while current dir is a sub-dir */ - res = dir_sdi(&dj, 1); /* Get parent dir */ - if (res != FR_OK) break; - res = dir_read(&dj); - if (res != FR_OK) break; - dj.sclust = LD_CLUST(dj.dir); /* Goto parent dir */ - res = dir_sdi(&dj, 0); - if (res != FR_OK) break; - do { /* Find the entry links to the child dir */ - res = dir_read(&dj); - if (res != FR_OK) break; - if (ccl == LD_CLUST(dj.dir)) break; /* Found the entry */ - res = dir_next(&dj, 0); - } while (res == FR_OK); - if (res == FR_NO_FILE) res = FR_INT_ERR;/* It cannot be 'not found'. */ - if (res != FR_OK) break; -#if _USE_LFN - fno.lfname = path; - fno.lfsize = i; -#endif - get_fileinfo(&dj, &fno); /* Get the dir name and push it to the buffer */ - tp = fno.fname; - if (_USE_LFN && *path) tp = path; - for (n = 0; tp[n]; n++) ; - if (i < n + 3) { - res = FR_NOT_ENOUGH_CORE; break; - } - while (n) path[--i] = tp[--n]; - path[--i] = '/'; - } - tp = path; - if (res == FR_OK) { - *tp++ = '0' + CurrVol; /* Put drive number */ - *tp++ = ':'; - if (i == sz_path) { /* Root-dir */ - *tp++ = '/'; - } else { /* Sub-dir */ - do /* Add stacked path str */ - *tp++ = path[i++]; - while (i < sz_path); - } - } - *tp = 0; - FREE_BUF(); - } - - LEAVE_FF(dj.fs, res); -} -#endif /* _FS_RPATH >= 2 */ -#endif /* _FS_RPATH >= 1 */ - - - -#if _FS_MINIMIZE <= 2 -/*-----------------------------------------------------------------------*/ -/* Seek File R/W Pointer */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_lseek ( - FIL *fp, /* Pointer to the file object */ - DWORD ofs /* File pointer from top of file */ -) -{ - FRESULT res; - - - res = validate(fp->fs, fp->id); /* Check validity of the object */ - if (res != FR_OK) LEAVE_FF(fp->fs, res); - if (fp->flag & FA__ERROR) /* Check abort flag */ - LEAVE_FF(fp->fs, FR_INT_ERR); - -#if _USE_FASTSEEK - if (fp->cltbl) { /* Fast seek */ - DWORD cl, pcl, ncl, tcl, dsc, tlen, ulen, *tbl; - - if (ofs == CREATE_LINKMAP) { /* Create CLMT */ - tbl = fp->cltbl; - tlen = *tbl++; ulen = 2; /* Given table size and required table size */ - cl = fp->sclust; /* Top of the chain */ - if (cl) { - do { - /* Get a fragment */ - tcl = cl; ncl = 0; ulen += 2; /* Top, length and used items */ - do { - pcl = cl; ncl++; - cl = get_fat(fp->fs, cl); - if (cl <= 1) ABORT(fp->fs, FR_INT_ERR); - if (cl == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); - } while (cl == pcl + 1); - if (ulen <= tlen) { /* Store the length and top of the fragment */ - *tbl++ = ncl; *tbl++ = tcl; - } - } while (cl < fp->fs->n_fatent); /* Repeat until end of chain */ - } - *fp->cltbl = ulen; /* Number of items used */ - if (ulen <= tlen) - *tbl = 0; /* Terminate table */ - else - res = FR_NOT_ENOUGH_CORE; /* Given table size is smaller than required */ - - } else { /* Fast seek */ - if (ofs > fp->fsize) /* Clip offset at the file size */ - ofs = fp->fsize; - fp->fptr = ofs; /* Set file pointer */ - if (ofs) { - fp->clust = clmt_clust(fp, ofs - 1); - dsc = clust2sect(fp->fs, fp->clust); - if (!dsc) ABORT(fp->fs, FR_INT_ERR); - dsc += (ofs - 1) / SS(fp->fs) & (fp->fs->csize - 1); - if (fp->fptr % SS(fp->fs) && dsc != fp->dsect) { /* Refill sector cache if needed */ -#if !_FS_TINY -#if !_FS_READONLY - if (fp->flag & FA__DIRTY) { /* Write-back dirty sector cache */ - if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK) - ABORT(fp->fs, FR_DISK_ERR); - fp->flag &= ~FA__DIRTY; - } -#endif - if (disk_read(fp->fs->drv, fp->buf, dsc, 1) != RES_OK) /* Load current sector */ - ABORT(fp->fs, FR_DISK_ERR); -#endif - fp->dsect = dsc; - } - } - } - } else -#endif - - /* Normal Seek */ - { - DWORD clst, bcs, nsect, ifptr; - - if (ofs > fp->fsize /* In read-only mode, clip offset with the file size */ -#if !_FS_READONLY - && !(fp->flag & FA_WRITE) -#endif - ) ofs = fp->fsize; - - ifptr = fp->fptr; - fp->fptr = nsect = 0; - if (ofs) { - bcs = (DWORD)fp->fs->csize * SS(fp->fs); /* Cluster size (byte) */ - if (ifptr > 0 && - (ofs - 1) / bcs >= (ifptr - 1) / bcs) { /* When seek to same or following cluster, */ - fp->fptr = (ifptr - 1) & ~(bcs - 1); /* start from the current cluster */ - ofs -= fp->fptr; - clst = fp->clust; - } else { /* When seek to back cluster, */ - clst = fp->sclust; /* start from the first cluster */ -#if !_FS_READONLY - if (clst == 0) { /* If no cluster chain, create a new chain */ - clst = create_chain(fp->fs, 0); - if (clst == 1) ABORT(fp->fs, FR_INT_ERR); - if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); - fp->sclust = clst; - } -#endif - fp->clust = clst; - } - if (clst != 0) { - while (ofs > bcs) { /* Cluster following loop */ -#if !_FS_READONLY - if (fp->flag & FA_WRITE) { /* Check if in write mode or not */ - clst = create_chain(fp->fs, clst); /* Force stretch if in write mode */ - if (clst == 0) { /* When disk gets full, clip file size */ - ofs = bcs; break; - } - } else -#endif - clst = get_fat(fp->fs, clst); /* Follow cluster chain if not in write mode */ - if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); - if (clst <= 1 || clst >= fp->fs->n_fatent) ABORT(fp->fs, FR_INT_ERR); - fp->clust = clst; - fp->fptr += bcs; - ofs -= bcs; - } - fp->fptr += ofs; - if (ofs % SS(fp->fs)) { - nsect = clust2sect(fp->fs, clst); /* Current sector */ - if (!nsect) ABORT(fp->fs, FR_INT_ERR); - nsect += ofs / SS(fp->fs); - } - } - } - if (fp->fptr % SS(fp->fs) && nsect != fp->dsect) { /* Fill sector cache if needed */ -#if !_FS_TINY -#if !_FS_READONLY - if (fp->flag & FA__DIRTY) { /* Write-back dirty sector cache */ - if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK) - ABORT(fp->fs, FR_DISK_ERR); - fp->flag &= ~FA__DIRTY; - } -#endif - if (disk_read(fp->fs->drv, fp->buf, nsect, 1) != RES_OK) /* Fill sector cache */ - ABORT(fp->fs, FR_DISK_ERR); -#endif - fp->dsect = nsect; - } -#if !_FS_READONLY - if (fp->fptr > fp->fsize) { /* Set file change flag if the file size is extended */ - fp->fsize = fp->fptr; - fp->flag |= FA__WRITTEN; - } -#endif - } - - LEAVE_FF(fp->fs, res); -} - - - -#if _FS_MINIMIZE <= 1 -/*-----------------------------------------------------------------------*/ -/* Create a Directroy Object */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_opendir ( - DIR *dj, /* Pointer to directory object to create */ - const TCHAR *path /* Pointer to the directory path */ -) -{ - FRESULT res; - DEF_NAMEBUF; - - - res = chk_mounted(&path, &dj->fs, 0); - if (res == FR_OK) { - INIT_BUF(*dj); - res = follow_path(dj, path); /* Follow the path to the directory */ - FREE_BUF(); - if (res == FR_OK) { /* Follow completed */ - if (dj->dir) { /* It is not the root dir */ - if (dj->dir[DIR_Attr] & AM_DIR) { /* The object is a directory */ - dj->sclust = LD_CLUST(dj->dir); - } else { /* The object is not a directory */ - res = FR_NO_PATH; - } - } - if (res == FR_OK) { - dj->id = dj->fs->id; - res = dir_sdi(dj, 0); /* Rewind dir */ - } - } - if (res == FR_NO_FILE) res = FR_NO_PATH; - } - - LEAVE_FF(dj->fs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Read Directory Entry in Sequense */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_readdir ( - DIR *dj, /* Pointer to the open directory object */ - FILINFO *fno /* Pointer to file information to return */ -) -{ - FRESULT res; - DEF_NAMEBUF; - - - res = validate(dj->fs, dj->id); /* Check validity of the object */ - if (res == FR_OK) { - if (!fno) { - res = dir_sdi(dj, 0); /* Rewind the directory object */ - } else { - INIT_BUF(*dj); - res = dir_read(dj); /* Read an directory item */ - if (res == FR_NO_FILE) { /* Reached end of dir */ - dj->sect = 0; - res = FR_OK; - } - if (res == FR_OK) { /* A valid entry is found */ - get_fileinfo(dj, fno); /* Get the object information */ - res = dir_next(dj, 0); /* Increment index for next */ - if (res == FR_NO_FILE) { - dj->sect = 0; - res = FR_OK; - } - } - FREE_BUF(); - } - } - - LEAVE_FF(dj->fs, res); -} - - - -#if _FS_MINIMIZE == 0 -/*-----------------------------------------------------------------------*/ -/* Get File Status */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_stat ( - const TCHAR *path, /* Pointer to the file path */ - FILINFO *fno /* Pointer to file information to return */ -) -{ - FRESULT res; - DIR dj; - DEF_NAMEBUF; - - - res = chk_mounted(&path, &dj.fs, 0); - if (res == FR_OK) { - INIT_BUF(dj); - res = follow_path(&dj, path); /* Follow the file path */ - if (res == FR_OK) { /* Follow completed */ - if (dj.dir) /* Found an object */ - get_fileinfo(&dj, fno); - else /* It is root dir */ - res = FR_INVALID_NAME; - } - FREE_BUF(); - } - - LEAVE_FF(dj.fs, res); -} - - - -#if !_FS_READONLY -/*-----------------------------------------------------------------------*/ -/* Get Number of Free Clusters */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_getfree ( - const TCHAR *path, /* Pointer to the logical drive number (root dir) */ - DWORD *nclst, /* Pointer to the variable to return number of free clusters */ - FATFS **fatfs /* Pointer to pointer to corresponding file system object to return */ -) -{ - FRESULT res; - DWORD n, clst, sect, stat; - UINT i; - BYTE fat, *p; - - - /* Get drive number */ - res = chk_mounted(&path, fatfs, 0); - if (res == FR_OK) { - /* If free_clust is valid, return it without full cluster scan */ - if ((*fatfs)->free_clust <= (*fatfs)->n_fatent - 2) { - *nclst = (*fatfs)->free_clust; - } else { - /* Get number of free clusters */ - fat = (*fatfs)->fs_type; - n = 0; - if (fat == FS_FAT12) { - clst = 2; - do { - stat = get_fat(*fatfs, clst); - if (stat == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } - if (stat == 1) { res = FR_INT_ERR; break; } - if (stat == 0) n++; - } while (++clst < (*fatfs)->n_fatent); - } else { - clst = (*fatfs)->n_fatent; - sect = (*fatfs)->fatbase; - i = 0; p = 0; - do { - if (!i) { - res = move_window(*fatfs, sect++); - if (res != FR_OK) break; - p = (*fatfs)->win; - i = SS(*fatfs); - } - if (fat == FS_FAT16) { - if (LD_WORD(p) == 0) n++; - p += 2; i -= 2; - } else { - if ((LD_DWORD(p) & 0x0FFFFFFF) == 0) n++; - p += 4; i -= 4; - } - } while (--clst); - } - (*fatfs)->free_clust = n; - if (fat == FS_FAT32) (*fatfs)->fsi_flag = 1; - *nclst = n; - } - } - LEAVE_FF(*fatfs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Truncate File */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_truncate ( - FIL *fp /* Pointer to the file object */ -) -{ - FRESULT res; - DWORD ncl; - - - res = validate(fp->fs, fp->id); /* Check validity of the object */ - if (res == FR_OK) { - if (fp->flag & FA__ERROR) { /* Check abort flag */ - res = FR_INT_ERR; - } else { - if (!(fp->flag & FA_WRITE)) /* Check access mode */ - res = FR_DENIED; - } - } - if (res == FR_OK) { - if (fp->fsize > fp->fptr) { - fp->fsize = fp->fptr; /* Set file size to current R/W point */ - fp->flag |= FA__WRITTEN; - if (fp->fptr == 0) { /* When set file size to zero, remove entire cluster chain */ - res = remove_chain(fp->fs, fp->sclust); - fp->sclust = 0; - } else { /* When truncate a part of the file, remove remaining clusters */ - ncl = get_fat(fp->fs, fp->clust); - res = FR_OK; - if (ncl == 0xFFFFFFFF) res = FR_DISK_ERR; - if (ncl == 1) res = FR_INT_ERR; - if (res == FR_OK && ncl < fp->fs->n_fatent) { - res = put_fat(fp->fs, fp->clust, 0x0FFFFFFF); - if (res == FR_OK) res = remove_chain(fp->fs, ncl); - } - } - } - if (res != FR_OK) fp->flag |= FA__ERROR; - } - - LEAVE_FF(fp->fs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Delete a File or Directory */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_unlink ( - const TCHAR *path /* Pointer to the file or directory path */ -) -{ - FRESULT res; - DIR dj, sdj; - BYTE *dir; - DWORD dclst; - DEF_NAMEBUF; - - - res = chk_mounted(&path, &dj.fs, 1); - if (res == FR_OK) { - INIT_BUF(dj); - res = follow_path(&dj, path); /* Follow the file path */ - if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT)) - res = FR_INVALID_NAME; /* Cannot remove dot entry */ -#if _FS_SHARE - if (res == FR_OK) res = chk_lock(&dj, 2); /* Cannot remove open file */ -#endif - if (res == FR_OK) { /* The object is accessible */ - dir = dj.dir; - if (!dir) { - res = FR_INVALID_NAME; /* Cannot remove the start directory */ - } else { - if (dir[DIR_Attr] & AM_RDO) - res = FR_DENIED; /* Cannot remove R/O object */ - } - dclst = LD_CLUST(dir); - if (res == FR_OK && (dir[DIR_Attr] & AM_DIR)) { /* Is it a sub-dir? */ - if (dclst < 2) { - res = FR_INT_ERR; - } else { - mem_cpy(&sdj, &dj, sizeof(DIR)); /* Check if the sub-dir is empty or not */ - sdj.sclust = dclst; - res = dir_sdi(&sdj, 2); /* Exclude dot entries */ - if (res == FR_OK) { - res = dir_read(&sdj); - if (res == FR_OK /* Not empty dir */ -#if _FS_RPATH - || dclst == sdj.fs->cdir /* Current dir */ -#endif - ) res = FR_DENIED; - if (res == FR_NO_FILE) res = FR_OK; /* Empty */ - } - } - } - if (res == FR_OK) { - res = dir_remove(&dj); /* Remove the directory entry */ - if (res == FR_OK) { - if (dclst) /* Remove the cluster chain if exist */ - res = remove_chain(dj.fs, dclst); - if (res == FR_OK) res = sync(dj.fs); - } - } - } - FREE_BUF(); - } - LEAVE_FF(dj.fs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Create a Directory */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_mkdir ( - const TCHAR *path /* Pointer to the directory path */ -) -{ - FRESULT res; - DIR dj; - BYTE *dir, n; - DWORD dsc, dcl, pcl, tim = get_fattime(); - DEF_NAMEBUF; - - - res = chk_mounted(&path, &dj.fs, 1); - if (res == FR_OK) { - INIT_BUF(dj); - res = follow_path(&dj, path); /* Follow the file path */ - if (res == FR_OK) res = FR_EXIST; /* Any object with same name is already existing */ - if (_FS_RPATH && res == FR_NO_FILE && (dj.fn[NS] & NS_DOT)) - res = FR_INVALID_NAME; - if (res == FR_NO_FILE) { /* Can create a new directory */ - dcl = create_chain(dj.fs, 0); /* Allocate a cluster for the new directory table */ - res = FR_OK; - if (dcl == 0) res = FR_DENIED; /* No space to allocate a new cluster */ - if (dcl == 1) res = FR_INT_ERR; - if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR; - if (res == FR_OK) /* Flush FAT */ - res = move_window(dj.fs, 0); - if (res == FR_OK) { /* Initialize the new directory table */ - dsc = clust2sect(dj.fs, dcl); - dir = dj.fs->win; - mem_set(dir, 0, SS(dj.fs)); - mem_set(dir+DIR_Name, ' ', 8+3); /* Create "." entry */ - dir[DIR_Name] = '.'; - dir[DIR_Attr] = AM_DIR; - ST_DWORD(dir+DIR_WrtTime, tim); - ST_CLUST(dir, dcl); - mem_cpy(dir+SZ_DIR, dir, SZ_DIR); /* Create ".." entry */ - dir[33] = '.'; pcl = dj.sclust; - if (dj.fs->fs_type == FS_FAT32 && pcl == dj.fs->dirbase) - pcl = 0; - ST_CLUST(dir+SZ_DIR, pcl); - for (n = dj.fs->csize; n; n--) { /* Write dot entries and clear following sectors */ - dj.fs->winsect = dsc++; - dj.fs->wflag = 1; - res = move_window(dj.fs, 0); - if (res != FR_OK) break; - mem_set(dir, 0, SS(dj.fs)); - } - } - if (res == FR_OK) res = dir_register(&dj); /* Register the object to the directoy */ - if (res != FR_OK) { - remove_chain(dj.fs, dcl); /* Could not register, remove cluster chain */ - } else { - dir = dj.dir; - dir[DIR_Attr] = AM_DIR; /* Attribute */ - ST_DWORD(dir+DIR_WrtTime, tim); /* Created time */ - ST_CLUST(dir, dcl); /* Table start cluster */ - dj.fs->wflag = 1; - res = sync(dj.fs); - } - } - FREE_BUF(); - } - - LEAVE_FF(dj.fs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Change Attribute */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_chmod ( - const TCHAR *path, /* Pointer to the file path */ - BYTE value, /* Attribute bits */ - BYTE mask /* Attribute mask to change */ -) -{ - FRESULT res; - DIR dj; - BYTE *dir; - DEF_NAMEBUF; - - - res = chk_mounted(&path, &dj.fs, 1); - if (res == FR_OK) { - INIT_BUF(dj); - res = follow_path(&dj, path); /* Follow the file path */ - FREE_BUF(); - if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT)) - res = FR_INVALID_NAME; - if (res == FR_OK) { - dir = dj.dir; - if (!dir) { /* Is it a root directory? */ - res = FR_INVALID_NAME; - } else { /* File or sub directory */ - mask &= AM_RDO|AM_HID|AM_SYS|AM_ARC; /* Valid attribute mask */ - dir[DIR_Attr] = (value & mask) | (dir[DIR_Attr] & (BYTE)~mask); /* Apply attribute change */ - dj.fs->wflag = 1; - res = sync(dj.fs); - } - } - } - - LEAVE_FF(dj.fs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Change Timestamp */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_utime ( - const TCHAR *path, /* Pointer to the file/directory name */ - const FILINFO *fno /* Pointer to the time stamp to be set */ -) -{ - FRESULT res; - DIR dj; - BYTE *dir; - DEF_NAMEBUF; - - - res = chk_mounted(&path, &dj.fs, 1); - if (res == FR_OK) { - INIT_BUF(dj); - res = follow_path(&dj, path); /* Follow the file path */ - FREE_BUF(); - if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT)) - res = FR_INVALID_NAME; - if (res == FR_OK) { - dir = dj.dir; - if (!dir) { /* Root directory */ - res = FR_INVALID_NAME; - } else { /* File or sub-directory */ - ST_WORD(dir+DIR_WrtTime, fno->ftime); - ST_WORD(dir+DIR_WrtDate, fno->fdate); - dj.fs->wflag = 1; - res = sync(dj.fs); - } - } - } - - LEAVE_FF(dj.fs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Rename File/Directory */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_rename ( - const TCHAR *path_old, /* Pointer to the old name */ - const TCHAR *path_new /* Pointer to the new name */ -) -{ - FRESULT res; - DIR djo, djn; - BYTE buf[21], *dir; - DWORD dw; - DEF_NAMEBUF; - - - res = chk_mounted(&path_old, &djo.fs, 1); - if (res == FR_OK) { - djn.fs = djo.fs; - INIT_BUF(djo); - res = follow_path(&djo, path_old); /* Check old object */ - if (_FS_RPATH && res == FR_OK && (djo.fn[NS] & NS_DOT)) - res = FR_INVALID_NAME; -#if _FS_SHARE - if (res == FR_OK) res = chk_lock(&djo, 2); -#endif - if (res == FR_OK) { /* Old object is found */ - if (!djo.dir) { /* Is root dir? */ - res = FR_NO_FILE; - } else { - mem_cpy(buf, djo.dir+DIR_Attr, 21); /* Save the object information except for name */ - mem_cpy(&djn, &djo, sizeof(DIR)); /* Check new object */ - res = follow_path(&djn, path_new); - if (res == FR_OK) res = FR_EXIST; /* The new object name is already existing */ - if (res == FR_NO_FILE) { /* Is it a valid path and no name collision? */ -/* Start critical section that any interruption or error can cause cross-link */ - res = dir_register(&djn); /* Register the new entry */ - if (res == FR_OK) { - dir = djn.dir; /* Copy object information except for name */ - mem_cpy(dir+13, buf+2, 19); - dir[DIR_Attr] = buf[0] | AM_ARC; - djo.fs->wflag = 1; - if (djo.sclust != djn.sclust && (dir[DIR_Attr] & AM_DIR)) { /* Update .. entry in the directory if needed */ - dw = clust2sect(djn.fs, LD_CLUST(dir)); - if (!dw) { - res = FR_INT_ERR; - } else { - res = move_window(djn.fs, dw); - dir = djn.fs->win+SZ_DIR; /* .. entry */ - if (res == FR_OK && dir[1] == '.') { - dw = (djn.fs->fs_type == FS_FAT32 && djn.sclust == djn.fs->dirbase) ? 0 : djn.sclust; - ST_CLUST(dir, dw); - djn.fs->wflag = 1; - } - } - } - if (res == FR_OK) { - res = dir_remove(&djo); /* Remove old entry */ - if (res == FR_OK) - res = sync(djo.fs); - } - } -/* End critical section */ - } - } - } - FREE_BUF(); - } - LEAVE_FF(djo.fs, res); -} - -#endif /* !_FS_READONLY */ -#endif /* _FS_MINIMIZE == 0 */ -#endif /* _FS_MINIMIZE <= 1 */ -#endif /* _FS_MINIMIZE <= 2 */ - - - -/*-----------------------------------------------------------------------*/ -/* Forward data to the stream directly (available on only tiny cfg) */ -/*-----------------------------------------------------------------------*/ -#if _USE_FORWARD && _FS_TINY - -FRESULT f_forward ( - FIL *fp, /* Pointer to the file object */ - UINT (*func)(const BYTE*,UINT), /* Pointer to the streaming function */ - UINT btr, /* Number of bytes to forward */ - UINT *bf /* Pointer to number of bytes forwarded */ -) -{ - FRESULT res; - DWORD remain, clst, sect; - UINT rcnt; - BYTE csect; - - - *bf = 0; /* Initialize byte counter */ - - res = validate(fp->fs, fp->id); /* Check validity of the object */ - if (res != FR_OK) LEAVE_FF(fp->fs, res); - if (fp->flag & FA__ERROR) /* Check error flag */ - LEAVE_FF(fp->fs, FR_INT_ERR); - if (!(fp->flag & FA_READ)) /* Check access mode */ - LEAVE_FF(fp->fs, FR_DENIED); - - remain = fp->fsize - fp->fptr; - if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */ - - for ( ; btr && (*func)(0, 0); /* Repeat until all data transferred or stream becomes busy */ - fp->fptr += rcnt, *bf += rcnt, btr -= rcnt) { - csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */ - if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ - if (!csect) { /* On the cluster boundary? */ - clst = (fp->fptr == 0) ? /* On the top of the file? */ - fp->sclust : get_fat(fp->fs, fp->clust); - if (clst <= 1) ABORT(fp->fs, FR_INT_ERR); - if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); - fp->clust = clst; /* Update current cluster */ - } - } - sect = clust2sect(fp->fs, fp->clust); /* Get current data sector */ - if (!sect) ABORT(fp->fs, FR_INT_ERR); - sect += csect; - if (move_window(fp->fs, sect)) /* Move sector window */ - ABORT(fp->fs, FR_DISK_ERR); - fp->dsect = sect; - rcnt = SS(fp->fs) - (WORD)(fp->fptr % SS(fp->fs)); /* Forward data from sector window */ - if (rcnt > btr) rcnt = btr; - rcnt = (*func)(&fp->fs->win[(WORD)fp->fptr % SS(fp->fs)], rcnt); - if (!rcnt) ABORT(fp->fs, FR_INT_ERR); - } - - LEAVE_FF(fp->fs, FR_OK); -} -#endif /* _USE_FORWARD */ - - - -#if _USE_MKFS && !_FS_READONLY -/*-----------------------------------------------------------------------*/ -/* Create File System on the Drive */ -/*-----------------------------------------------------------------------*/ -#define N_ROOTDIR 512 /* Number of root dir entries for FAT12/16 */ -#define N_FATS 1 /* Number of FAT copies (1 or 2) */ - - -FRESULT f_mkfs ( - BYTE drv, /* Logical drive number */ - BYTE sfd, /* Partitioning rule 0:FDISK, 1:SFD */ - UINT au /* Allocation unit size [bytes] */ -) -{ - static const WORD vst[] = { 1024, 512, 256, 128, 64, 32, 16, 8, 4, 2, 0}; - static const WORD cst[] = {32768, 16384, 8192, 4096, 2048, 16384, 8192, 4096, 2048, 1024, 512}; - BYTE fmt, md, sys, *tbl, pdrv, part; - DWORD n_clst, vs, n, wsect; - UINT i; - DWORD b_vol, b_fat, b_dir, b_data; /* LBA */ - DWORD n_vol, n_rsv, n_fat, n_dir; /* Size */ - FATFS *fs; - DSTATUS stat; - - - /* Check mounted drive and clear work area */ - if (drv >= _VOLUMES) return FR_INVALID_DRIVE; - if (sfd > 1) return FR_INVALID_PARAMETER; - if (au & (au - 1)) return FR_INVALID_PARAMETER; - fs = FatFs[drv]; - if (!fs) return FR_NOT_ENABLED; - fs->fs_type = 0; - pdrv = LD2PD(drv); /* Physical drive */ - part = LD2PT(drv); /* Partition (0:auto detect, 1-4:get from partition table)*/ - - /* Get disk statics */ - stat = disk_initialize(pdrv); - if (stat & STA_NOINIT) return FR_NOT_READY; - if (stat & STA_PROTECT) return FR_WRITE_PROTECTED; -#if _MAX_SS != 512 /* Get disk sector size */ - if (disk_ioctl(pdrv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK || SS(fs) > _MAX_SS) - return FR_DISK_ERR; -#endif - if (_MULTI_PARTITION && part) { - /* Get partition information from partition table in the MBR */ - if (disk_read(pdrv, fs->win, 0, 1) != RES_OK) return FR_DISK_ERR; - if (LD_WORD(fs->win+BS_55AA) != 0xAA55) return FR_MKFS_ABORTED; - tbl = &fs->win[MBR_Table + (part - 1) * SZ_PTE]; - if (!tbl[4]) return FR_MKFS_ABORTED; /* No partition? */ - b_vol = LD_DWORD(tbl+8); /* Volume start sector */ - n_vol = LD_DWORD(tbl+12); /* Volume size */ - } else { - /* Create a partition in this function */ - if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &n_vol) != RES_OK || n_vol < 128) - return FR_DISK_ERR; - b_vol = (sfd) ? 0 : 63; /* Volume start sector */ - n_vol -= b_vol; /* Volume size */ - } - - if (!au) { /* AU auto selection */ - vs = n_vol / (2000 / (SS(fs) / 512)); - for (i = 0; vs < vst[i]; i++) ; - au = cst[i]; - } - au /= SS(fs); /* Number of sectors per cluster */ - if (au == 0) au = 1; - if (au > 128) au = 128; - - /* Pre-compute number of clusters and FAT syb-type */ - n_clst = n_vol / au; - fmt = FS_FAT12; - if (n_clst >= MIN_FAT16) fmt = FS_FAT16; - if (n_clst >= MIN_FAT32) fmt = FS_FAT32; - - /* Determine offset and size of FAT structure */ - if (fmt == FS_FAT32) { - n_fat = ((n_clst * 4) + 8 + SS(fs) - 1) / SS(fs); - n_rsv = 32; - n_dir = 0; - } else { - n_fat = (fmt == FS_FAT12) ? (n_clst * 3 + 1) / 2 + 3 : (n_clst * 2) + 4; - n_fat = (n_fat + SS(fs) - 1) / SS(fs); - n_rsv = 1; - n_dir = (DWORD)N_ROOTDIR * SZ_DIR / SS(fs); - } - b_fat = b_vol + n_rsv; /* FAT area start sector */ - b_dir = b_fat + n_fat * N_FATS; /* Directory area start sector */ - b_data = b_dir + n_dir; /* Data area start sector */ - if (n_vol < b_data + au - b_vol) return FR_MKFS_ABORTED; /* Too small volume */ - - /* Align data start sector to erase block boundary (for flash memory media) */ - if (disk_ioctl(pdrv, GET_BLOCK_SIZE, &n) != RES_OK || !n || n > 32768) n = 1; - n = (b_data + n - 1) & ~(n - 1); /* Next nearest erase block from current data start */ - n = (n - b_data) / N_FATS; - if (fmt == FS_FAT32) { /* FAT32: Move FAT offset */ - n_rsv += n; - b_fat += n; - } else { /* FAT12/16: Expand FAT size */ - n_fat += n; - } - - /* Determine number of clusters and final check of validity of the FAT sub-type */ - n_clst = (n_vol - n_rsv - n_fat * N_FATS - n_dir) / au; - if ( (fmt == FS_FAT16 && n_clst < MIN_FAT16) - || (fmt == FS_FAT32 && n_clst < MIN_FAT32)) - return FR_MKFS_ABORTED; - - switch (fmt) { /* Determine system ID for partition table */ - case FS_FAT12: sys = 0x01; break; - case FS_FAT16: sys = (n_vol < 0x10000) ? 0x04 : 0x06; break; - default: sys = 0x0C; - } - - if (_MULTI_PARTITION && part) { - /* Update system ID in the partition table */ - tbl = &fs->win[MBR_Table + (part - 1) * SZ_PTE]; - tbl[4] = sys; - if (disk_write(pdrv, fs->win, 0, 1) != RES_OK) return FR_DISK_ERR; - md = 0xF8; - } else { - if (sfd) { /* No patition table (SFD) */ - md = 0xF0; - } else { /* Create partition table (FDISK) */ - mem_set(fs->win, 0, SS(fs)); - tbl = fs->win+MBR_Table; /* Create partiton table for single partition in the drive */ - tbl[1] = 1; /* Partition start head */ - tbl[2] = 1; /* Partition start sector */ - tbl[3] = 0; /* Partition start cylinder */ - tbl[4] = sys; /* System type */ - tbl[5] = 254; /* Partition end head */ - n = (b_vol + n_vol) / 63 / 255; - tbl[6] = (BYTE)((n >> 2) | 63); /* Partiiton end sector */ - tbl[7] = (BYTE)n; /* End cylinder */ - ST_DWORD(tbl+8, 63); /* Partition start in LBA */ - ST_DWORD(tbl+12, n_vol); /* Partition size in LBA */ - ST_WORD(fs->win+BS_55AA, 0xAA55); /* MBR signature */ - if (disk_write(pdrv, fs->win, 0, 1) != RES_OK) /* Write it to the MBR sector */ - return FR_DISK_ERR; - md = 0xF8; - } - } - - /* Create BPB in the VBR */ - tbl = fs->win; /* Clear sector */ - mem_set(tbl, 0, SS(fs)); - mem_cpy(tbl, "\xEB\xFE\x90" "MSDOS5.0", 11);/* Boot jump code, OEM name */ - i = SS(fs); /* Sector size */ - ST_WORD(tbl+BPB_BytsPerSec, i); - tbl[BPB_SecPerClus] = (BYTE)au; /* Sectors per cluster */ - ST_WORD(tbl+BPB_RsvdSecCnt, n_rsv); /* Reserved sectors */ - tbl[BPB_NumFATs] = N_FATS; /* Number of FATs */ - i = (fmt == FS_FAT32) ? 0 : N_ROOTDIR; /* Number of rootdir entries */ - ST_WORD(tbl+BPB_RootEntCnt, i); - if (n_vol < 0x10000) { /* Number of total sectors */ - ST_WORD(tbl+BPB_TotSec16, n_vol); - } else { - ST_DWORD(tbl+BPB_TotSec32, n_vol); - } - tbl[BPB_Media] = md; /* Media descriptor */ - ST_WORD(tbl+BPB_SecPerTrk, 63); /* Number of sectors per track */ - ST_WORD(tbl+BPB_NumHeads, 255); /* Number of heads */ - ST_DWORD(tbl+BPB_HiddSec, b_vol); /* Hidden sectors */ - n = get_fattime(); /* Use current time as VSN */ - if (fmt == FS_FAT32) { - ST_DWORD(tbl+BS_VolID32, n); /* VSN */ - ST_DWORD(tbl+BPB_FATSz32, n_fat); /* Number of sectors per FAT */ - ST_DWORD(tbl+BPB_RootClus, 2); /* Root directory start cluster (2) */ - ST_WORD(tbl+BPB_FSInfo, 1); /* FSInfo record offset (VBR+1) */ - ST_WORD(tbl+BPB_BkBootSec, 6); /* Backup boot record offset (VBR+6) */ - tbl[BS_DrvNum32] = 0x80; /* Drive number */ - tbl[BS_BootSig32] = 0x29; /* Extended boot signature */ - mem_cpy(tbl+BS_VolLab32, "NO NAME " "FAT32 ", 19); /* Volume label, FAT signature */ - } else { - ST_DWORD(tbl+BS_VolID, n); /* VSN */ - ST_WORD(tbl+BPB_FATSz16, n_fat); /* Number of sectors per FAT */ - tbl[BS_DrvNum] = 0x80; /* Drive number */ - tbl[BS_BootSig] = 0x29; /* Extended boot signature */ - mem_cpy(tbl+BS_VolLab, "NO NAME " "FAT ", 19); /* Volume label, FAT signature */ - } - ST_WORD(tbl+BS_55AA, 0xAA55); /* Signature (Offset is fixed here regardless of sector size) */ - if (disk_write(pdrv, tbl, b_vol, 1) != RES_OK) /* Write it to the VBR sector */ - return FR_DISK_ERR; - if (fmt == FS_FAT32) /* Write backup VBR if needed (VBR+6) */ - disk_write(pdrv, tbl, b_vol + 6, 1); - - /* Initialize FAT area */ - wsect = b_fat; - for (i = 0; i < N_FATS; i++) { /* Initialize each FAT copy */ - mem_set(tbl, 0, SS(fs)); /* 1st sector of the FAT */ - n = md; /* Media descriptor byte */ - if (fmt != FS_FAT32) { - n |= (fmt == FS_FAT12) ? 0x00FFFF00 : 0xFFFFFF00; - ST_DWORD(tbl+0, n); /* Reserve cluster #0-1 (FAT12/16) */ - } else { - n |= 0xFFFFFF00; - ST_DWORD(tbl+0, n); /* Reserve cluster #0-1 (FAT32) */ - ST_DWORD(tbl+4, 0xFFFFFFFF); - ST_DWORD(tbl+8, 0x0FFFFFFF); /* Reserve cluster #2 for root dir */ - } - if (disk_write(pdrv, tbl, wsect++, 1) != RES_OK) - return FR_DISK_ERR; - mem_set(tbl, 0, SS(fs)); /* Fill following FAT entries with zero */ - for (n = 1; n < n_fat; n++) { /* This loop may take a time on FAT32 volume due to many single sector writes */ - if (disk_write(pdrv, tbl, wsect++, 1) != RES_OK) - return FR_DISK_ERR; - } - } - - /* Initialize root directory */ - i = (fmt == FS_FAT32) ? au : n_dir; - do { - if (disk_write(pdrv, tbl, wsect++, 1) != RES_OK) - return FR_DISK_ERR; - } while (--i); - -#if _USE_ERASE /* Erase data area if needed */ - { - DWORD eb[2]; - - eb[0] = wsect; eb[1] = wsect + (n_clst - ((fmt == FS_FAT32) ? 1 : 0)) * au - 1; - disk_ioctl(pdrv, CTRL_ERASE_SECTOR, eb); - } -#endif - - /* Create FSInfo if needed */ - if (fmt == FS_FAT32) { - ST_DWORD(tbl+FSI_LeadSig, 0x41615252); - ST_DWORD(tbl+FSI_StrucSig, 0x61417272); - ST_DWORD(tbl+FSI_Free_Count, n_clst - 1); /* Number of free clusters */ - ST_DWORD(tbl+FSI_Nxt_Free, 2); /* Last allocated cluster# */ - ST_WORD(tbl+BS_55AA, 0xAA55); - disk_write(pdrv, tbl, b_vol + 1, 1); /* Write original (VBR+1) */ - disk_write(pdrv, tbl, b_vol + 7, 1); /* Write backup (VBR+7) */ - } - - return (disk_ioctl(pdrv, CTRL_SYNC, 0) == RES_OK) ? FR_OK : FR_DISK_ERR; -} - - -#if _MULTI_PARTITION == 2 -/*-----------------------------------------------------------------------*/ -/* Divide Physical Drive */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_fdisk ( - BYTE pdrv, /* Physical drive number */ - const DWORD szt[], /* Pointer to the size table for each partitions */ - void* work /* Pointer to the working buffer */ -) -{ - UINT i, n, sz_cyl, tot_cyl, b_cyl, e_cyl, p_cyl; - BYTE s_hd, e_hd, *p, *buf = (BYTE*)work; - DSTATUS stat; - DWORD sz_disk, sz_part, s_part; - - - stat = disk_initialize(pdrv); - if (stat & STA_NOINIT) return FR_NOT_READY; - if (stat & STA_PROTECT) return FR_WRITE_PROTECTED; - if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_disk)) return FR_DISK_ERR; - - /* Determine CHS in the table regardless of the drive geometry */ - for (n = 16; n < 256 && sz_disk / n / 63 > 1024; n *= 2) ; - if (n == 256) n--; - e_hd = n - 1; - sz_cyl = 63 * n; - tot_cyl = sz_disk / sz_cyl; - - /* Create partition table */ - mem_set(buf, 0, _MAX_SS); - p = buf + MBR_Table; b_cyl = 0; - for (i = 0; i < 4; i++, p += SZ_PTE) { - p_cyl = (szt[i] <= 100) ? (DWORD)tot_cyl * szt[i] / 100 : szt[i] / sz_cyl; - if (!p_cyl) continue; - s_part = (DWORD)sz_cyl * b_cyl; - sz_part = (DWORD)sz_cyl * p_cyl; - if (i == 0) { /* Exclude first track of cylinder 0 */ - s_hd = 1; - s_part += 63; sz_part -= 63; - } else { - s_hd = 0; - } - e_cyl = b_cyl + p_cyl - 1; - if (e_cyl >= tot_cyl) return FR_INVALID_PARAMETER; - - /* Set partition table */ - p[1] = s_hd; /* Start head */ - p[2] = (BYTE)((b_cyl >> 2) + 1); /* Start sector */ - p[3] = (BYTE)b_cyl; /* Start cylinder */ - p[4] = 0x06; /* System type (temporary setting) */ - p[5] = e_hd; /* End head */ - p[6] = (BYTE)((e_cyl >> 2) + 63); /* End sector */ - p[7] = (BYTE)e_cyl; /* End cylinder */ - ST_DWORD(p + 8, s_part); /* Start sector in LBA */ - ST_DWORD(p + 12, sz_part); /* Partition size */ - - /* Next partition */ - b_cyl += p_cyl; - } - ST_WORD(p, 0xAA55); - - /* Write it to the MBR */ - return (disk_write(pdrv, buf, 0, 1) || disk_ioctl(pdrv, CTRL_SYNC, 0)) ? FR_DISK_ERR : FR_OK; -} - - -#endif /* _MULTI_PARTITION == 2 */ -#endif /* _USE_MKFS && !_FS_READONLY */ - - - - -#if _USE_STRFUNC -/*-----------------------------------------------------------------------*/ -/* Get a string from the file */ -/*-----------------------------------------------------------------------*/ -TCHAR* f_gets ( - TCHAR* buff, /* Pointer to the string buffer to read */ - int len, /* Size of string buffer (characters) */ - FIL* fil /* Pointer to the file object */ -) -{ - int n = 0; - TCHAR c, *p = buff; - BYTE s[2]; - UINT rc; - - - while (n < len - 1) { /* Read bytes until buffer gets filled */ - f_read(fil, s, 1, &rc); - if (rc != 1) break; /* Break on EOF or error */ - c = s[0]; -#if _LFN_UNICODE /* Read a character in UTF-8 encoding */ - if (c >= 0x80) { - if (c < 0xC0) continue; /* Skip stray trailer */ - if (c < 0xE0) { /* Two-byte sequense */ - f_read(fil, s, 1, &rc); - if (rc != 1) break; - c = ((c & 0x1F) << 6) | (s[0] & 0x3F); - if (c < 0x80) c = '?'; - } else { - if (c < 0xF0) { /* Three-byte sequense */ - f_read(fil, s, 2, &rc); - if (rc != 2) break; - c = (c << 12) | ((s[0] & 0x3F) << 6) | (s[1] & 0x3F); - if (c < 0x800) c = '?'; - } else { /* Reject four-byte sequense */ - c = '?'; - } - } - } -#endif -#if _USE_STRFUNC >= 2 - if (c == '\r') continue; /* Strip '\r' */ -#endif - *p++ = c; - n++; - if (c == '\n') break; /* Break on EOL */ - } - *p = 0; - return n ? buff : 0; /* When no data read (eof or error), return with error. */ -} - - - -#if !_FS_READONLY -#include -/*-----------------------------------------------------------------------*/ -/* Put a character to the file */ -/*-----------------------------------------------------------------------*/ -int f_putc ( - TCHAR c, /* A character to be output */ - FIL* fil /* Pointer to the file object */ -) -{ - UINT bw, btw; - BYTE s[3]; - - -#if _USE_STRFUNC >= 2 - if (c == '\n') f_putc ('\r', fil); /* LF -> CRLF conversion */ -#endif - -#if _LFN_UNICODE /* Write the character in UTF-8 encoding */ - if (c < 0x80) { /* 7-bit */ - s[0] = (BYTE)c; - btw = 1; - } else { - if (c < 0x800) { /* 11-bit */ - s[0] = (BYTE)(0xC0 | (c >> 6)); - s[1] = (BYTE)(0x80 | (c & 0x3F)); - btw = 2; - } else { /* 16-bit */ - s[0] = (BYTE)(0xE0 | (c >> 12)); - s[1] = (BYTE)(0x80 | ((c >> 6) & 0x3F)); - s[2] = (BYTE)(0x80 | (c & 0x3F)); - btw = 3; - } - } -#else /* Write the character without conversion */ - s[0] = (BYTE)c; - btw = 1; -#endif - f_write(fil, s, btw, &bw); /* Write the char to the file */ - return (bw == btw) ? 1 : EOF; /* Return the result */ -} - - - - -/*-----------------------------------------------------------------------*/ -/* Put a string to the file */ -/*-----------------------------------------------------------------------*/ -int f_puts ( - const TCHAR* str, /* Pointer to the string to be output */ - FIL* fil /* Pointer to the file object */ -) -{ - int n; - - - for (n = 0; *str; str++, n++) { - if (f_putc(*str, fil) == EOF) return EOF; - } - return n; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Put a formatted string to the file */ -/*-----------------------------------------------------------------------*/ -int f_printf ( - FIL* fil, /* Pointer to the file object */ - const TCHAR* str, /* Pointer to the format string */ - ... /* Optional arguments... */ -) -{ - va_list arp; - BYTE f, r; - UINT i, j, w; - ULONG v; - TCHAR c, d, s[16], *p; - int res, chc, cc; - - - va_start(arp, str); - - for (cc = res = 0; cc != EOF; res += cc) { - c = *str++; - if (c == 0) break; /* End of string */ - if (c != '%') { /* Non escape character */ - cc = f_putc(c, fil); - if (cc != EOF) cc = 1; - continue; - } - w = f = 0; - c = *str++; - if (c == '0') { /* Flag: '0' padding */ - f = 1; c = *str++; - } else { - if (c == '-') { /* Flag: left justified */ - f = 2; c = *str++; - } - } - while (IsDigit(c)) { /* Precision */ - w = w * 10 + c - '0'; - c = *str++; - } - if (c == 'l' || c == 'L') { /* Prefix: Size is long int */ - f |= 4; c = *str++; - } - if (!c) break; - d = c; - if (IsLower(d)) d -= 0x20; - switch (d) { /* Type is... */ - case 'S' : /* String */ - p = va_arg(arp, TCHAR*); - for (j = 0; p[j]; j++) ; - chc = 0; - if (!(f & 2)) { - while (j++ < w) chc += (cc = f_putc(' ', fil)); - } - chc += (cc = f_puts(p, fil)); - while (j++ < w) chc += (cc = f_putc(' ', fil)); - if (cc != EOF) cc = chc; - continue; - case 'C' : /* Character */ - cc = f_putc((TCHAR)va_arg(arp, int), fil); continue; - case 'B' : /* Binary */ - r = 2; break; - case 'O' : /* Octal */ - r = 8; break; - case 'D' : /* Signed decimal */ - case 'U' : /* Unsigned decimal */ - r = 10; break; - case 'X' : /* Hexdecimal */ - r = 16; break; - default: /* Unknown type (passthrough) */ - cc = f_putc(c, fil); continue; - } - - /* Get an argument and put it in numeral */ - v = (f & 4) ? (ULONG)va_arg(arp, long) : ((d == 'D') ? (ULONG)(long)va_arg(arp, int) : (ULONG)va_arg(arp, unsigned int)); - if (d == 'D' && (v & 0x80000000)) { - v = 0 - v; - f |= 8; - } - i = 0; - do { - d = (TCHAR)(v % r); v /= r; - if (d > 9) d += (c == 'x') ? 0x27 : 0x07; - s[i++] = d + '0'; - } while (v && i < sizeof(s) / sizeof(s[0])); - if (f & 8) s[i++] = '-'; - j = i; d = (f & 1) ? '0' : ' '; - res = 0; - while (!(f & 2) && j++ < w) res += (cc = f_putc(d, fil)); - do res += (cc = f_putc(s[--i], fil)); while(i); - while (j++ < w) res += (cc = f_putc(' ', fil)); - if (cc != EOF) cc = res; - } - - va_end(arp); - return (cc == EOF) ? cc : res; -} - -#endif /* !_FS_READONLY */ -#endif /* _USE_STRFUNC */ diff --git a/firmware/chibios/ext/fatfs/src/option/ccsbcs.c b/firmware/chibios/ext/fatfs/src/option/ccsbcs.c deleted file mode 100644 index b540484a03..0000000000 --- a/firmware/chibios/ext/fatfs/src/option/ccsbcs.c +++ /dev/null @@ -1,540 +0,0 @@ -/*------------------------------------------------------------------------*/ -/* Unicode - Local code bidirectional converter (C)ChaN, 2009 */ -/* (SBCS code pages) */ -/*------------------------------------------------------------------------*/ -/* 437 U.S. (OEM) -/ 720 Arabic (OEM) -/ 1256 Arabic (Windows) -/ 737 Greek (OEM) -/ 1253 Greek (Windows) -/ 1250 Central Europe (Windows) -/ 775 Baltic (OEM) -/ 1257 Baltic (Windows) -/ 850 Multilingual Latin 1 (OEM) -/ 852 Latin 2 (OEM) -/ 1252 Latin 1 (Windows) -/ 855 Cyrillic (OEM) -/ 1251 Cyrillic (Windows) -/ 866 Russian (OEM) -/ 857 Turkish (OEM) -/ 1254 Turkish (Windows) -/ 858 Multilingual Latin 1 + Euro (OEM) -/ 862 Hebrew (OEM) -/ 1255 Hebrew (Windows) -/ 874 Thai (OEM, Windows) -/ 1258 Vietnam (OEM, Windows) -*/ - -#include "ff.h" - - -#if _CODE_PAGE == 437 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP437(0x80-0xFF) to Unicode conversion table */ - 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, - 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, - 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, - 0x00FF, 0x00D6, 0x00DC, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192, - 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, - 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, - 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, - 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, - 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, - 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, - 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, - 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, - 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 720 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP720(0x80-0xFF) to Unicode conversion table */ - 0x0000, 0x0000, 0x00E9, 0x00E2, 0x0000, 0x00E0, 0x0000, 0x00E7, - 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0651, 0x0652, 0x00F4, 0x00A4, 0x0640, 0x00FB, 0x00F9, - 0x0621, 0x0622, 0x0623, 0x0624, 0x00A3, 0x0625, 0x0626, 0x0627, - 0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F, - 0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, - 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, - 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, - 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, - 0x0636, 0x0637, 0x0638, 0x0639, 0x063A, 0x0641, 0x00B5, 0x0642, - 0x0643, 0x0644, 0x0645, 0x0646, 0x0647, 0x0648, 0x0649, 0x064A, - 0x2261, 0x064B, 0x064C, 0x064D, 0x064E, 0x064F, 0xO650, 0x2248, - 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 737 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP737(0x80-0xFF) to Unicode conversion table */ - 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x0398, - 0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F, 0x03A0, - 0x03A1, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7, 0x03A8, 0x03A9, - 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7, 0x03B8, - 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, 0x03C0, - 0x03C1, 0x03C3, 0x03C2, 0x03C4, 0x03C5, 0x03C6, 0x03C7, 0x03C8, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, - 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, - 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, - 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, - 0x03C9, 0x03AC, 0x03AD, 0x03AE, 0x03CA, 0x03AF, 0x03CC, 0x03CD, - 0x03CB, 0x03CE, 0x0386, 0x0388, 0x0389, 0x038A, 0x038C, 0x038E, - 0x038F, 0x00B1, 0x2265, 0x2264, 0x03AA, 0x03AB, 0x00F7, 0x2248, - 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 775 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP775(0x80-0xFF) to Unicode conversion table */ - 0x0106, 0x00FC, 0x00E9, 0x0101, 0x00E4, 0x0123, 0x00E5, 0x0107, - 0x0142, 0x0113, 0x0156, 0x0157, 0x012B, 0x0179, 0x00C4, 0x00C5, - 0x00C9, 0x00E6, 0x00C6, 0x014D, 0x00F6, 0x0122, 0x00A2, 0x015A, - 0x015B, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x00A4, - 0x0100, 0x012A, 0x00F3, 0x017B, 0x017C, 0x017A, 0x201D, 0x00A6, - 0x00A9, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x0141, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0104, 0x010C, 0x0118, - 0x0116, 0x2563, 0x2551, 0x2557, 0x255D, 0x012E, 0x0160, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0172, 0x016A, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x017D, - 0x0105, 0x010D, 0x0119, 0x0117, 0x012F, 0x0161, 0x0173, 0x016B, - 0x017E, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, - 0x00D3, 0x00DF, 0x014C, 0x0143, 0x00F5, 0x00D5, 0x00B5, 0x0144, - 0x0136, 0x0137, 0x013B, 0x013C, 0x0146, 0x0112, 0x0145, 0x2019, - 0x00AD, 0x00B1, 0x201C, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x201E, - 0x00B0, 0x2219, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 850 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP850(0x80-0xFF) to Unicode conversion table */ - 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, - 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, - 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, - 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192, - 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, - 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, - 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, - 0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x0131, 0x00CD, 0x00CE, - 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580, - 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE, - 0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4, - 0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, - 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 852 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP852(0x80-0xFF) to Unicode conversion table */ - 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x016F, 0x0107, 0x00E7, - 0x0142, 0x00EB, 0x0150, 0x0151, 0x00EE, 0x0179, 0x00C4, 0x0106, - 0x00C9, 0x0139, 0x013A, 0x00F4, 0x00F6, 0x013D, 0x013E, 0x015A, - 0x015B, 0x00D6, 0x00DC, 0x0164, 0x0165, 0x0141, 0x00D7, 0x010D, - 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x0104, 0x0105, 0x017D, 0x017E, - 0x0118, 0x0119, 0x00AC, 0x017A, 0x010C, 0x015F, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x011A, - 0x015E, 0x2563, 0x2551, 0x2557, 0x255D, 0x017B, 0x017C, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0102, 0x0103, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, - 0x0111, 0x0110, 0x010E, 0x00CB, 0x010F, 0x0147, 0x00CD, 0x00CE, - 0x011B, 0x2518, 0x250C, 0x2588, 0x2584, 0x0162, 0x016E, 0x2580, - 0x00D3, 0x00DF, 0x00D4, 0x0143, 0x0144, 0x0148, 0x0160, 0x0161, - 0x0154, 0x00DA, 0x0155, 0x0170, 0x00FD, 0x00DD, 0x0163, 0x00B4, - 0x00AD, 0x02DD, 0x02DB, 0x02C7, 0x02D8, 0x00A7, 0x00F7, 0x00B8, - 0x00B0, 0x00A8, 0x02D9, 0x0171, 0x0158, 0x0159, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 855 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP855(0x80-0xFF) to Unicode conversion table */ - 0x0452, 0x0402, 0x0453, 0x0403, 0x0451, 0x0401, 0x0454, 0x0404, - 0x0455, 0x0405, 0x0456, 0x0406, 0x0457, 0x0407, 0x0458, 0x0408, - 0x0459, 0x0409, 0x045A, 0x040A, 0x045B, 0x040B, 0x045C, 0x040C, - 0x045E, 0x040E, 0x045F, 0x040F, 0x044E, 0x042E, 0x044A, 0x042A, - 0x0430, 0x0410, 0x0431, 0x0411, 0x0446, 0x0426, 0x0434, 0x0414, - 0x0435, 0x0415, 0x0444, 0x0424, 0x0433, 0x0413, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0445, 0x0425, 0x0438, - 0x0418, 0x2563, 0x2551, 0x2557, 0x255D, 0x0439, 0x0419, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x043A, 0x041A, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, - 0x043B, 0x041B, 0x043C, 0x041C, 0x043D, 0x041D, 0x043E, 0x041E, - 0x043F, 0x2518, 0x250C, 0x2588, 0x2584, 0x041F, 0x044F, 0x2580, - 0x042F, 0x0440, 0x0420, 0x0441, 0x0421, 0x0442, 0x0422, 0x0443, - 0x0423, 0x0436, 0x0416, 0x0432, 0x0412, 0x044C, 0x042C, 0x2116, - 0x00AD, 0x044B, 0x042B, 0x0437, 0x0417, 0x0448, 0x0428, 0x044D, - 0x042D, 0x0449, 0x0429, 0x0447, 0x0427, 0x00A7, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 857 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP857(0x80-0xFF) to Unicode conversion table */ - 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, - 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0131, 0x00C4, 0x00C5, - 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, - 0x0130, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x015E, 0x015F, - 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x011E, 0x011F, - 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, - 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, - 0x00BA, 0x00AA, 0x00CA, 0x00CB, 0x00C8, 0x0000, 0x00CD, 0x00CE, - 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580, - 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x0000, - 0x00D7, 0x00DA, 0x00DB, 0x00D9, 0x00EC, 0x00FF, 0x00AF, 0x00B4, - 0x00AD, 0x00B1, 0x0000, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, - 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 858 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP858(0x80-0xFF) to Unicode conversion table */ - 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, - 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, - 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, - 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192, - 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, - 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, - 0x00A9, 0x2563, 0x2551, 0x2557, 0x2550, 0x00A2, 0x00A5, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, - 0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x20AC, 0x00CD, 0x00CE, - 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00C6, 0x00CC, 0x2580, - 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE, - 0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4, - 0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, - 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 862 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP862(0x80-0xFF) to Unicode conversion table */ - 0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7, - 0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF, - 0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7, - 0x05E8, 0x05E9, 0x05EA, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192, - 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, - 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, - 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, - 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, - 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, - 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, - 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, - 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, - 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 866 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP866(0x80-0xFF) to Unicode conversion table */ - 0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, - 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F, - 0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, - 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F, - 0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, - 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, - 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, - 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, - 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, - 0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, - 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F, - 0x0401, 0x0451, 0x0404, 0x0454, 0x0407, 0x0457, 0x040E, 0x045E, - 0x00B0, 0x2219, 0x00B7, 0x221A, 0x2116, 0x00A4, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 874 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP874(0x80-0xFF) to Unicode conversion table */ - 0x20AC, 0x0000, 0x0000, 0x0000, 0x0000, 0x2026, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x00A0, 0x0E01, 0x0E02, 0x0E03, 0x0E04, 0x0E05, 0x0E06, 0x0E07, - 0x0E08, 0x0E09, 0x0E0A, 0x0E0B, 0x0E0C, 0x0E0D, 0x0E0E, 0x0E0F, - 0x0E10, 0x0E11, 0x0E12, 0x0E13, 0x0E14, 0x0E15, 0x0E16, 0x0E17, - 0x0E18, 0x0E19, 0x0E1A, 0x0E1B, 0x0E1C, 0x0E1D, 0x0E1E, 0x0E1F, - 0x0E20, 0x0E21, 0x0E22, 0x0E23, 0x0E24, 0x0E25, 0x0E26, 0x0E27, - 0x0E28, 0x0E29, 0x0E2A, 0x0E2B, 0x0E2C, 0x0E2D, 0x0E2E, 0x0E2F, - 0x0E30, 0x0E31, 0x0E32, 0x0E33, 0x0E34, 0x0E35, 0x0E36, 0x0E37, - 0x0E38, 0x0E39, 0x0E3A, 0x0000, 0x0000, 0x0000, 0x0000, 0x0E3F, - 0x0E40, 0x0E41, 0x0E42, 0x0E43, 0x0E44, 0x0E45, 0x0E46, 0x0E47, - 0x0E48, 0x0E49, 0x0E4A, 0x0E4B, 0x0E4C, 0x0E4D, 0x0E4E, 0x0E4F, - 0x0E50, 0x0E51, 0x0E52, 0x0E53, 0x0E54, 0x0E55, 0x0E56, 0x0E57, - 0x0E58, 0x0E59, 0x0E5A, 0x0E5B, 0x0000, 0x0000, 0x0000, 0x0000 -}; - -#elif _CODE_PAGE == 1250 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP1250(0x80-0xFF) to Unicode conversion table */ - 0x20AC, 0x0000, 0x201A, 0x0000, 0x201E, 0x2026, 0x2020, 0x2021, - 0x0000, 0x2030, 0x0160, 0x2039, 0x015A, 0x0164, 0x017D, 0x0179, - 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, - 0x0000, 0x2122, 0x0161, 0x203A, 0x015B, 0x0165, 0x017E, 0x017A, - 0x00A0, 0x02C7, 0x02D8, 0x0141, 0x00A4, 0x0104, 0x00A6, 0x00A7, - 0x00A8, 0x00A9, 0x015E, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x017B, - 0x00B0, 0x00B1, 0x02DB, 0x0142, 0x00B4, 0x00B5, 0x00B6, 0x00B7, - 0x00B8, 0x0105, 0x015F, 0x00BB, 0x013D, 0x02DD, 0x013E, 0x017C, - 0x0154, 0x00C1, 0x00C2, 0x0102, 0x00C4, 0x0139, 0x0106, 0x00C7, - 0x010C, 0x00C9, 0x0118, 0x00CB, 0x011A, 0x00CD, 0x00CE, 0x010E, - 0x0110, 0x0143, 0x0147, 0x00D3, 0x00D4, 0x0150, 0x00D6, 0x00D7, - 0x0158, 0x016E, 0x00DA, 0x0170, 0x00DC, 0x00DD, 0x0162, 0x00DF, - 0x0155, 0x00E1, 0x00E2, 0x0103, 0x00E4, 0x013A, 0x0107, 0x00E7, - 0x010D, 0x00E9, 0x0119, 0x00EB, 0x011B, 0x00ED, 0x00EE, 0x010F, - 0x0111, 0x0144, 0x0148, 0x00F3, 0x00F4, 0x0151, 0x00F6, 0x00F7, - 0x0159, 0x016F, 0x00FA, 0x0171, 0x00FC, 0x00FD, 0x0163, 0x02D9 -}; - -#elif _CODE_PAGE == 1251 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP1251(0x80-0xFF) to Unicode conversion table */ - 0x0402, 0x0403, 0x201A, 0x0453, 0x201E, 0x2026, 0x2020, 0x2021, - 0x20AC, 0x2030, 0x0409, 0x2039, 0x040A, 0x040C, 0x040B, 0x040F, - 0x0452, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, - 0x0000, 0x2111, 0x0459, 0x203A, 0x045A, 0x045C, 0x045B, 0x045F, - 0x00A0, 0x040E, 0x045E, 0x0408, 0x00A4, 0x0490, 0x00A6, 0x00A7, - 0x0401, 0x00A9, 0x0404, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x0407, - 0x00B0, 0x00B1, 0x0406, 0x0456, 0x0491, 0x00B5, 0x00B6, 0x00B7, - 0x0451, 0x2116, 0x0454, 0x00BB, 0x0458, 0x0405, 0x0455, 0x0457, - 0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, - 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F, - 0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, - 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F, - 0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, - 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F, - 0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, - 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F -}; - -#elif _CODE_PAGE == 1252 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP1252(0x80-0xFF) to Unicode conversion table */ - 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, - 0x02C6, 0x2030, 0x0160, 0x2039, 0x0152, 0x0000, 0x017D, 0x0000, - 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, - 0x02DC, 0x2122, 0x0161, 0x203A, 0x0153, 0x0000, 0x017E, 0x0178, - 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, - 0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, - 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, - 0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, - 0x00C0, 0x00C1, 0x00C2, 0x00C3, 0x00C4, 0x00C5, 0x00C6, 0x00C7, - 0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x00CC, 0x00CD, 0x00CE, 0x00CF, - 0x00D0, 0x00D1, 0x00D2, 0x00D3, 0x00D4, 0x00D5, 0x00D6, 0x00D7, - 0x00D8, 0x00D9, 0x00DA, 0x00DB, 0x00DC, 0x00DD, 0x00DE, 0x00DF, - 0x00E0, 0x00E1, 0x00E2, 0x00E3, 0x00E4, 0x00E5, 0x00E6, 0x00E7, - 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x00EC, 0x00ED, 0x00EE, 0x00EF, - 0x00F0, 0x00F1, 0x00F2, 0x00F3, 0x00F4, 0x00F5, 0x00F6, 0x00F7, - 0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x00FD, 0x00FE, 0x00FF -}; - -#elif _CODE_PAGE == 1253 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP1253(0x80-0xFF) to Unicode conversion table */ - 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, - 0x0000, 0x2030, 0x0000, 0x2039, 0x000C, 0x0000, 0x0000, 0x0000, - 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, - 0x0000, 0x2122, 0x0000, 0x203A, 0x0000, 0x0000, 0x0000, 0x0000, - 0x00A0, 0x0385, 0x0386, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, - 0x00A8, 0x00A9, 0x0000, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x2015, - 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x0384, 0x00B5, 0x00B6, 0x00B7, - 0x0388, 0x0389, 0x038A, 0x00BB, 0x038C, 0x00BD, 0x038E, 0x038F, - 0x0390, 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, - 0x0398, 0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F, - 0x03A0, 0x03A1, 0x0000, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7, - 0x03A8, 0x03A9, 0x03AA, 0x03AD, 0x03AC, 0x03AD, 0x03AE, 0x03AF, - 0x03B0, 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7, - 0x03B8, 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, - 0x03C0, 0x03C1, 0x03C2, 0x03C3, 0x03C4, 0x03C5, 0x03C6, 0x03C7, - 0x03C8, 0x03C9, 0x03CA, 0x03CB, 0x03CC, 0x03CD, 0x03CE, 0x0000 -}; - -#elif _CODE_PAGE == 1254 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP1254(0x80-0xFF) to Unicode conversion table */ - 0x20AC, 0x0000, 0x210A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, - 0x02C6, 0x2030, 0x0160, 0x2039, 0x0152, 0x0000, 0x0000, 0x0000, - 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, - 0x02DC, 0x2122, 0x0161, 0x203A, 0x0153, 0x0000, 0x0000, 0x0178, - 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, - 0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, - 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, - 0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, - 0x00C0, 0x00C1, 0x00C2, 0x00C3, 0x00C4, 0x00C5, 0x00C6, 0x00C7, - 0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x00CC, 0x00CD, 0x00CE, 0x00CF, - 0x011E, 0x00D1, 0x00D2, 0x00D3, 0x00D4, 0x00D5, 0x00D6, 0x00D7, - 0x00D8, 0x00D9, 0x00DA, 0x00BD, 0x00DC, 0x0130, 0x015E, 0x00DF, - 0x00E0, 0x00E1, 0x00E2, 0x00E3, 0x00E4, 0x00E5, 0x00E6, 0x00E7, - 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x00EC, 0x00ED, 0x00EE, 0x00EF, - 0x011F, 0x00F1, 0x00F2, 0x00F3, 0x00F4, 0x00F5, 0x00F6, 0x00F7, - 0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x0131, 0x015F, 0x00FF -}; - -#elif _CODE_PAGE == 1255 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP1255(0x80-0xFF) to Unicode conversion table */ - 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, - 0x02C6, 0x2030, 0x0000, 0x2039, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, - 0x02DC, 0x2122, 0x0000, 0x203A, 0x0000, 0x0000, 0x0000, 0x0000, - 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, - 0x00A8, 0x00A9, 0x00D7, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, - 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, - 0x00B8, 0x00B9, 0x00F7, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, - 0x05B0, 0x05B1, 0x05B2, 0x05B3, 0x05B4, 0x05B5, 0x05B6, 0x05B7, - 0x05B8, 0x05B9, 0x0000, 0x05BB, 0x05BC, 0x05BD, 0x05BE, 0x05BF, - 0x05C0, 0x05C1, 0x05C2, 0x05C3, 0x05F0, 0x05F1, 0x05F2, 0x05F3, - 0x05F4, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7, - 0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF, - 0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7, - 0x05E8, 0x05E9, 0x05EA, 0x0000, 0x0000, 0x200E, 0x200F, 0x0000 -}; - -#elif _CODE_PAGE == 1256 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP1256(0x80-0xFF) to Unicode conversion table */ - 0x20AC, 0x067E, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, - 0x02C6, 0x2030, 0x0679, 0x2039, 0x0152, 0x0686, 0x0698, 0x0688, - 0x06AF, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, - 0x06A9, 0x2122, 0x0691, 0x203A, 0x0153, 0x200C, 0x200D, 0x06BA, - 0x00A0, 0x060C, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, - 0x00A8, 0x00A9, 0x06BE, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, - 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, - 0x00B8, 0x00B9, 0x061B, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x061F, - 0x06C1, 0x0621, 0x0622, 0x0623, 0x0624, 0x0625, 0x0626, 0x0627, - 0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F, - 0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x0636, 0x00D7, - 0x0637, 0x0638, 0x0639, 0x063A, 0x0640, 0x0640, 0x0642, 0x0643, - 0x00E0, 0x0644, 0x00E2, 0x0645, 0x0646, 0x0647, 0x0648, 0x00E7, - 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x0649, 0x064A, 0x00EE, 0x00EF, - 0x064B, 0x064C, 0x064D, 0x064E, 0x00F4, 0x064F, 0x0650, 0x00F7, - 0x0651, 0x00F9, 0x0652, 0x00FB, 0x00FC, 0x200E, 0x200F, 0x06D2 -} - -#elif _CODE_PAGE == 1257 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP1257(0x80-0xFF) to Unicode conversion table */ - 0x20AC, 0x0000, 0x201A, 0x0000, 0x201E, 0x2026, 0x2020, 0x2021, - 0x0000, 0x2030, 0x0000, 0x2039, 0x0000, 0x00A8, 0x02C7, 0x00B8, - 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, - 0x0000, 0x2122, 0x0000, 0x203A, 0x0000, 0x00AF, 0x02DB, 0x0000, - 0x00A0, 0x0000, 0x00A2, 0x00A3, 0x00A4, 0x0000, 0x00A6, 0x00A7, - 0x00D8, 0x00A9, 0x0156, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, - 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, - 0x00B8, 0x00B9, 0x0157, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00E6, - 0x0104, 0x012E, 0x0100, 0x0106, 0x00C4, 0x00C5, 0x0118, 0x0112, - 0x010C, 0x00C9, 0x0179, 0x0116, 0x0122, 0x0136, 0x012A, 0x013B, - 0x0160, 0x0143, 0x0145, 0x00D3, 0x014C, 0x00D5, 0x00D6, 0x00D7, - 0x0172, 0x0141, 0x015A, 0x016A, 0x00DC, 0x017B, 0x017D, 0x00DF, - 0x0105, 0x012F, 0x0101, 0x0107, 0x00E4, 0x00E5, 0x0119, 0x0113, - 0x010D, 0x00E9, 0x017A, 0x0117, 0x0123, 0x0137, 0x012B, 0x013C, - 0x0161, 0x0144, 0x0146, 0x00F3, 0x014D, 0x00F5, 0x00F6, 0x00F7, - 0x0173, 0x014E, 0x015B, 0x016B, 0x00FC, 0x017C, 0x017E, 0x02D9 -}; - -#elif _CODE_PAGE == 1258 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP1258(0x80-0xFF) to Unicode conversion table */ - 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, - 0x02C6, 0x2030, 0x0000, 0x2039, 0x0152, 0x0000, 0x0000, 0x0000, - 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, - 0x02DC, 0x2122, 0x0000, 0x203A, 0x0153, 0x0000, 0x0000, 0x0178, - 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, - 0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, - 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, - 0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, - 0x00C0, 0x00C1, 0x00C2, 0x0102, 0x00C4, 0x00C5, 0x00C6, 0x00C7, - 0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x0300, 0x00CD, 0x00CE, 0x00CF, - 0x0110, 0x00D1, 0x0309, 0x00D3, 0x00D4, 0x01A0, 0x00D6, 0x00D7, - 0x00D8, 0x00D9, 0x00DA, 0x00DB, 0x00DC, 0x01AF, 0x0303, 0x00DF, - 0x00E0, 0x00E1, 0x00E2, 0x0103, 0x00E4, 0x00E5, 0x00E6, 0x00E7, - 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x0301, 0x00ED, 0x00EE, 0x00EF, - 0x0111, 0x00F1, 0x0323, 0x00F3, 0x00F4, 0x01A1, 0x00F6, 0x00F7, - 0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x01B0, 0x20AB, 0x00FF -}; - -#endif - - -#if !_TBLDEF || !_USE_LFN -#error This file is not needed in current configuration. Remove from the project. -#endif - - -WCHAR ff_convert ( /* Converted character, Returns zero on error */ - WCHAR src, /* Character code to be converted */ - UINT dir /* 0: Unicode to OEMCP, 1: OEMCP to Unicode */ -) -{ - WCHAR c; - - - if (src < 0x80) { /* ASCII */ - c = src; - - } else { - if (dir) { /* OEMCP to Unicode */ - c = (src >= 0x100) ? 0 : Tbl[src - 0x80]; - - } else { /* Unicode to OEMCP */ - for (c = 0; c < 0x80; c++) { - if (src == Tbl[c]) break; - } - c = (c + 0x80) & 0xFF; - } - } - - return c; -} - - -WCHAR ff_wtoupper ( /* Upper converted character */ - WCHAR chr /* Input character */ -) -{ - static const WCHAR tbl_lower[] = { 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0xA1, 0x00A2, 0x00A3, 0x00A5, 0x00AC, 0x00AF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0x0FF, 0x101, 0x103, 0x105, 0x107, 0x109, 0x10B, 0x10D, 0x10F, 0x111, 0x113, 0x115, 0x117, 0x119, 0x11B, 0x11D, 0x11F, 0x121, 0x123, 0x125, 0x127, 0x129, 0x12B, 0x12D, 0x12F, 0x131, 0x133, 0x135, 0x137, 0x13A, 0x13C, 0x13E, 0x140, 0x142, 0x144, 0x146, 0x148, 0x14B, 0x14D, 0x14F, 0x151, 0x153, 0x155, 0x157, 0x159, 0x15B, 0x15D, 0x15F, 0x161, 0x163, 0x165, 0x167, 0x169, 0x16B, 0x16D, 0x16F, 0x171, 0x173, 0x175, 0x177, 0x17A, 0x17C, 0x17E, 0x192, 0x3B1, 0x3B2, 0x3B3, 0x3B4, 0x3B5, 0x3B6, 0x3B7, 0x3B8, 0x3B9, 0x3BA, 0x3BB, 0x3BC, 0x3BD, 0x3BE, 0x3BF, 0x3C0, 0x3C1, 0x3C3, 0x3C4, 0x3C5, 0x3C6, 0x3C7, 0x3C8, 0x3C9, 0x3CA, 0x430, 0x431, 0x432, 0x433, 0x434, 0x435, 0x436, 0x437, 0x438, 0x439, 0x43A, 0x43B, 0x43C, 0x43D, 0x43E, 0x43F, 0x440, 0x441, 0x442, 0x443, 0x444, 0x445, 0x446, 0x447, 0x448, 0x449, 0x44A, 0x44B, 0x44C, 0x44D, 0x44E, 0x44F, 0x451, 0x452, 0x453, 0x454, 0x455, 0x456, 0x457, 0x458, 0x459, 0x45A, 0x45B, 0x45C, 0x45E, 0x45F, 0x2170, 0x2171, 0x2172, 0x2173, 0x2174, 0x2175, 0x2176, 0x2177, 0x2178, 0x2179, 0x217A, 0x217B, 0x217C, 0x217D, 0x217E, 0x217F, 0xFF41, 0xFF42, 0xFF43, 0xFF44, 0xFF45, 0xFF46, 0xFF47, 0xFF48, 0xFF49, 0xFF4A, 0xFF4B, 0xFF4C, 0xFF4D, 0xFF4E, 0xFF4F, 0xFF50, 0xFF51, 0xFF52, 0xFF53, 0xFF54, 0xFF55, 0xFF56, 0xFF57, 0xFF58, 0xFF59, 0xFF5A, 0 }; - static const WCHAR tbl_upper[] = { 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x21, 0xFFE0, 0xFFE1, 0xFFE5, 0xFFE2, 0xFFE3, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0x178, 0x100, 0x102, 0x104, 0x106, 0x108, 0x10A, 0x10C, 0x10E, 0x110, 0x112, 0x114, 0x116, 0x118, 0x11A, 0x11C, 0x11E, 0x120, 0x122, 0x124, 0x126, 0x128, 0x12A, 0x12C, 0x12E, 0x130, 0x132, 0x134, 0x136, 0x139, 0x13B, 0x13D, 0x13F, 0x141, 0x143, 0x145, 0x147, 0x14A, 0x14C, 0x14E, 0x150, 0x152, 0x154, 0x156, 0x158, 0x15A, 0x15C, 0x15E, 0x160, 0x162, 0x164, 0x166, 0x168, 0x16A, 0x16C, 0x16E, 0x170, 0x172, 0x174, 0x176, 0x179, 0x17B, 0x17D, 0x191, 0x391, 0x392, 0x393, 0x394, 0x395, 0x396, 0x397, 0x398, 0x399, 0x39A, 0x39B, 0x39C, 0x39D, 0x39E, 0x39F, 0x3A0, 0x3A1, 0x3A3, 0x3A4, 0x3A5, 0x3A6, 0x3A7, 0x3A8, 0x3A9, 0x3AA, 0x410, 0x411, 0x412, 0x413, 0x414, 0x415, 0x416, 0x417, 0x418, 0x419, 0x41A, 0x41B, 0x41C, 0x41D, 0x41E, 0x41F, 0x420, 0x421, 0x422, 0x423, 0x424, 0x425, 0x426, 0x427, 0x428, 0x429, 0x42A, 0x42B, 0x42C, 0x42D, 0x42E, 0x42F, 0x401, 0x402, 0x403, 0x404, 0x405, 0x406, 0x407, 0x408, 0x409, 0x40A, 0x40B, 0x40C, 0x40E, 0x40F, 0x2160, 0x2161, 0x2162, 0x2163, 0x2164, 0x2165, 0x2166, 0x2167, 0x2168, 0x2169, 0x216A, 0x216B, 0x216C, 0x216D, 0x216E, 0x216F, 0xFF21, 0xFF22, 0xFF23, 0xFF24, 0xFF25, 0xFF26, 0xFF27, 0xFF28, 0xFF29, 0xFF2A, 0xFF2B, 0xFF2C, 0xFF2D, 0xFF2E, 0xFF2F, 0xFF30, 0xFF31, 0xFF32, 0xFF33, 0xFF34, 0xFF35, 0xFF36, 0xFF37, 0xFF38, 0xFF39, 0xFF3A, 0 }; - int i; - - - for (i = 0; tbl_lower[i] && chr != tbl_lower[i]; i++) ; - - return tbl_lower[i] ? tbl_upper[i] : chr; -} diff --git a/firmware/chibios/file.lst b/firmware/chibios/file.lst deleted file mode 100644 index f3d84bd725..0000000000 --- a/firmware/chibios/file.lst +++ /dev/null @@ -1,172 +0,0 @@ -os/hal/hal.mk -os/hal/include/adc.h -os/hal/include/can.h -os/hal/include/ext.h -os/hal/include/gpt.h -os/hal/include/hal.h -os/hal/include/i2c.h -os/hal/include/icu.h -os/hal/include/io_block.h -os/hal/include/io_channel.h -os/hal/include/mac.h -os/hal/include/mii.h -os/hal/include/mmcsd.h -os/hal/include/mmc_spi.h -os/hal/include/pal.h -os/hal/include/pwm.h -os/hal/include/rtc.h -os/hal/include/sdc.h -os/hal/include/serial.h -os/hal/include/serial_usb.h -os/hal/include/spi.h -os/hal/include/tm.h -os/hal/include/uart.h -os/hal/include/usb.h -os/hal/platforms/STM32/can_lld.c -os/hal/platforms/STM32/can_lld.h -os/hal/platforms/STM32/ext_lld.c -os/hal/platforms/STM32/ext_lld.h -os/hal/platforms/STM32/GPIOv2/pal_lld.c -os/hal/platforms/STM32/GPIOv2/pal_lld.h -os/hal/platforms/STM32/i2s_lld.c -os/hal/platforms/STM32/i2s_lld.h -os/hal/platforms/STM32/mac_lld.c -os/hal/platforms/STM32/mac_lld.h -os/hal/platforms/STM32/OTGv1/stm32_otg.h -os/hal/platforms/STM32/OTGv1/usb_lld.c -os/hal/platforms/STM32/OTGv1/usb_lld.h -os/hal/platforms/STM32/RTCv2/rtc_lld.c -os/hal/platforms/STM32/RTCv2/rtc_lld.h -os/hal/platforms/STM32/sdc_lld.c -os/hal/platforms/STM32/sdc_lld.h -os/hal/platforms/STM32/SPIv1/spi_lld.c -os/hal/platforms/STM32/SPIv1/spi_lld.h -os/hal/platforms/STM32/stm32.h -os/hal/platforms/STM32/TIMv1/gpt_lld.c -os/hal/platforms/STM32/TIMv1/gpt_lld.h -os/hal/platforms/STM32/TIMv1/icu_lld.c -os/hal/platforms/STM32/TIMv1/icu_lld.h -os/hal/platforms/STM32/TIMv1/pwm_lld.c -os/hal/platforms/STM32/TIMv1/pwm_lld.h -os/hal/platforms/STM32/TIMv1/stm32_tim.h -os/hal/platforms/STM32/USARTv1/serial_lld.c -os/hal/platforms/STM32/USARTv1/serial_lld.h -os/hal/platforms/STM32/USARTv1/uart_lld.c -os/hal/platforms/STM32/USARTv1/uart_lld.h -os/hal/platforms/STM32F4xx/adc_lld.c -os/hal/platforms/STM32F4xx/adc_lld.h -os/hal/platforms/STM32F4xx/ext_lld_isr.c -os/hal/platforms/STM32F4xx/ext_lld_isr.h -os/hal/platforms/STM32F4xx/hal_lld.c -os/hal/platforms/STM32F4xx/hal_lld.h -os/hal/platforms/STM32F4xx/platform.dox -os/hal/platforms/STM32F4xx/platform.mk -os/hal/platforms/STM32F4xx/stm32f2xx.h -os/hal/platforms/STM32F4xx/stm32f4xx.h -os/hal/platforms/STM32F4xx/stm32_dma.c -os/hal/platforms/STM32F4xx/stm32_dma.h -os/hal/platforms/STM32F4xx/stm32_isr.h -os/hal/platforms/STM32F4xx/stm32_rcc.h -os/hal/src/adc.c -os/hal/src/can.c -os/hal/src/ext.c -os/hal/src/gpt.c -os/hal/src/hal.c -os/hal/src/i2c.c -os/hal/src/icu.c -os/hal/src/mac.c -os/hal/src/mmcsd.c -os/hal/src/mmc_spi.c -os/hal/src/pal.c -os/hal/src/pwm.c -os/hal/src/rtc.c -os/hal/src/sdc.c -os/hal/src/serial.c -os/hal/src/serial_usb.c -os/hal/src/spi.c -os/hal/src/tm.c -os/hal/src/uart.c -os/hal/src/usb.c -os/kernel/include/ch.h -os/kernel/include/chbsem.h -os/kernel/include/chcond.h -os/kernel/include/chdebug.h -os/kernel/include/chdynamic.h -os/kernel/include/chevents.h -os/kernel/include/chfiles.h -os/kernel/include/chheap.h -os/kernel/include/chinline.h -os/kernel/include/chlists.h -os/kernel/include/chmboxes.h -os/kernel/include/chmemcore.h -os/kernel/include/chmempools.h -os/kernel/include/chmsg.h -os/kernel/include/chmtx.h -os/kernel/include/chqueues.h -os/kernel/include/chregistry.h -os/kernel/include/chschd.h -os/kernel/include/chsem.h -os/kernel/include/chstreams.h -os/kernel/include/chsys.h -os/kernel/include/chthreads.h -os/kernel/include/chvt.h -os/kernel/kernel.mk -os/kernel/src/chcond.c -os/kernel/src/chdebug.c -os/kernel/src/chdynamic.c -os/kernel/src/chevents.c -os/kernel/src/chheap.c -os/kernel/src/chlists.c -os/kernel/src/chmboxes.c -os/kernel/src/chmemcore.c -os/kernel/src/chmempools.c -os/kernel/src/chmsg.c -os/kernel/src/chmtx.c -os/kernel/src/chqueues.c -os/kernel/src/chregistry.c -os/kernel/src/chschd.c -os/kernel/src/chsem.c -os/kernel/src/chsys.c -os/kernel/src/chthreads.c -os/kernel/src/chvt.c -os/ports/common/ARMCMx/CMSIS/include/arm_common_tables.h -os/ports/common/ARMCMx/CMSIS/include/arm_math.h -os/ports/common/ARMCMx/CMSIS/include/core_cm0.h -os/ports/common/ARMCMx/CMSIS/include/core_cm0plus.h -os/ports/common/ARMCMx/CMSIS/include/core_cm3.h -os/ports/common/ARMCMx/CMSIS/include/core_cm4.h -os/ports/common/ARMCMx/CMSIS/include/core_cm4_simd.h -os/ports/common/ARMCMx/CMSIS/include/core_cmFunc.h -os/ports/common/ARMCMx/CMSIS/include/core_cmInstr.h -os/ports/common/ARMCMx/CMSIS/readme.txt -os/ports/common/ARMCMx/nvic.c -os/ports/common/ARMCMx/nvic.h -os/ports/GCC/ARMCMx/chcore.c -os/ports/GCC/ARMCMx/chcore.h -os/ports/GCC/ARMCMx/chcore_v7m.c -os/ports/GCC/ARMCMx/chcore_v7m.h -os/ports/GCC/ARMCMx/chtypes.h -os/ports/GCC/ARMCMx/crt0.c -os/ports/GCC/ARMCMx/rules.mk -os/ports/GCC/ARMCMx/STM32F4xx/cmparams.h -os/ports/GCC/ARMCMx/STM32F4xx/port.mk -os/ports/GCC/ARMCMx/STM32F4xx/vectors.c -os/ports/IAR/ARMCMx/chcore.c -os/ports/IAR/ARMCMx/chcore.h -os/ports/IAR/ARMCMx/chcoreasm_v6m.s -os/ports/IAR/ARMCMx/chcoreasm_v7m.s -os/ports/IAR/ARMCMx/chcore_v6m.c -os/ports/IAR/ARMCMx/chcore_v6m.h -os/ports/IAR/ARMCMx/chcore_v7m.c -os/ports/IAR/ARMCMx/chcore_v7m.h -os/ports/IAR/ARMCMx/chtypes.h -os/ports/IAR/ARMCMx/cstartup.s -os/ports/IAR/ARMCMx/STM32F4xx/cmparams.h -os/ports/IAR/ARMCMx/STM32F4xx/vectors.s -os/various/chprintf.c -os/various/chprintf.h -os/various/fatfs_diskio.c -os/various/fatfs_syscall.c -os/various/memstreams.c -os/various/memstreams.h -os/various/various.mk diff --git a/firmware/chibios/os/hal/hal.mk b/firmware/chibios/os/hal/hal.mk deleted file mode 100644 index f3fa3f758f..0000000000 --- a/firmware/chibios/os/hal/hal.mk +++ /dev/null @@ -1,25 +0,0 @@ -# List of all the ChibiOS/RT HAL files, there is no need to remove the files -# from this list, you can disable parts of the HAL by editing halconf.h. -HALSRC = ${CHIBIOS}/os/hal/src/hal.c \ - ${CHIBIOS}/os/hal/src/adc.c \ - ${CHIBIOS}/os/hal/src/can.c \ - ${CHIBIOS}/os/hal/src/ext.c \ - ${CHIBIOS}/os/hal/src/gpt.c \ - ${CHIBIOS}/os/hal/src/i2c.c \ - ${CHIBIOS}/os/hal/src/icu.c \ - ${CHIBIOS}/os/hal/src/mac.c \ - ${CHIBIOS}/os/hal/src/mmc_spi.c \ - ${CHIBIOS}/os/hal/src/mmcsd.c \ - ${CHIBIOS}/os/hal/src/pal.c \ - ${CHIBIOS}/os/hal/src/pwm.c \ - ${CHIBIOS}/os/hal/src/rtc.c \ - ${CHIBIOS}/os/hal/src/sdc.c \ - ${CHIBIOS}/os/hal/src/serial.c \ - ${CHIBIOS}/os/hal/src/serial_usb.c \ - ${CHIBIOS}/os/hal/src/spi.c \ - ${CHIBIOS}/os/hal/src/tm.c \ - ${CHIBIOS}/os/hal/src/uart.c \ - ${CHIBIOS}/os/hal/src/usb.c - -# Required include directories -HALINC = ${CHIBIOS}/os/hal/include diff --git a/firmware/chibios/os/hal/include/adc.h b/firmware/chibios/os/hal/include/adc.h deleted file mode 100644 index 120f631280..0000000000 --- a/firmware/chibios/os/hal/include/adc.h +++ /dev/null @@ -1,316 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file adc.h - * @brief ADC Driver macros and structures. - * - * @addtogroup ADC - * @{ - */ - -#ifndef _ADC_H_ -#define _ADC_H_ - -#if HAL_USE_ADC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name ADC configuration options - * @{ - */ -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) -#define ADC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define ADC_USE_MUTUAL_EXCLUSION TRUE -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if ADC_USE_MUTUAL_EXCLUSION && !CH_USE_MUTEXES && !CH_USE_SEMAPHORES -#error "ADC_USE_MUTUAL_EXCLUSION requires CH_USE_MUTEXES and/or CH_USE_SEMAPHORES" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - ADC_UNINIT = 0, /**< Not initialized. */ - ADC_STOP = 1, /**< Stopped. */ - ADC_READY = 2, /**< Ready. */ - ADC_ACTIVE = 3, /**< Converting. */ - ADC_COMPLETE = 4, /**< Conversion complete. */ - ADC_ERROR = 5 /**< Conversion complete. */ -} adcstate_t; - -#include "adc_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Low Level driver helper macros - * @{ - */ -#if ADC_USE_WAIT || defined(__DOXYGEN__) -/** - * @brief Resumes a thread waiting for a conversion completion. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -#define _adc_reset_i(adcp) { \ - if ((adcp)->thread != NULL) { \ - Thread *tp = (adcp)->thread; \ - (adcp)->thread = NULL; \ - tp->p_u.rdymsg = RDY_RESET; \ - chSchReadyI(tp); \ - } \ -} - -/** - * @brief Resumes a thread waiting for a conversion completion. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -#define _adc_reset_s(adcp) { \ - if ((adcp)->thread != NULL) { \ - Thread *tp = (adcp)->thread; \ - (adcp)->thread = NULL; \ - chSchWakeupS(tp, RDY_RESET); \ - } \ -} - -/** - * @brief Wakes up the waiting thread. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -#define _adc_wakeup_isr(adcp) { \ - chSysLockFromIsr(); \ - if ((adcp)->thread != NULL) { \ - Thread *tp; \ - tp = (adcp)->thread; \ - (adcp)->thread = NULL; \ - tp->p_u.rdymsg = RDY_OK; \ - chSchReadyI(tp); \ - } \ - chSysUnlockFromIsr(); \ -} - -/** - * @brief Wakes up the waiting thread with a timeout message. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -#define _adc_timeout_isr(adcp) { \ - chSysLockFromIsr(); \ - if ((adcp)->thread != NULL) { \ - Thread *tp; \ - tp = (adcp)->thread; \ - (adcp)->thread = NULL; \ - tp->p_u.rdymsg = RDY_TIMEOUT; \ - chSchReadyI(tp); \ - } \ - chSysUnlockFromIsr(); \ -} - -#else /* !ADC_USE_WAIT */ -#define _adc_reset_i(adcp) -#define _adc_reset_s(adcp) -#define _adc_wakeup_isr(adcp) -#define _adc_timeout_isr(adcp) -#endif /* !ADC_USE_WAIT */ - -/** - * @brief Common ISR code, half buffer event. - * @details This code handles the portable part of the ISR code: - * - Callback invocation. - * . - * @note This macro is meant to be used in the low level drivers - * implementation only. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -#define _adc_isr_half_code(adcp) { \ - if ((adcp)->grpp->end_cb != NULL) { \ - (adcp)->grpp->end_cb(adcp, (adcp)->samples, (adcp)->depth / 2); \ - } \ -} - -/** - * @brief Common ISR code, full buffer event. - * @details This code handles the portable part of the ISR code: - * - Callback invocation. - * - Waiting thread wakeup, if any. - * - Driver state transitions. - * . - * @note This macro is meant to be used in the low level drivers - * implementation only. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -#define _adc_isr_full_code(adcp) { \ - if ((adcp)->grpp->circular) { \ - /* Callback handling.*/ \ - if ((adcp)->grpp->end_cb != NULL) { \ - if ((adcp)->depth > 1) { \ - /* Invokes the callback passing the 2nd half of the buffer.*/ \ - size_t half = (adcp)->depth / 2; \ - size_t half_index = half * (adcp)->grpp->num_channels; \ - (adcp)->grpp->end_cb(adcp, (adcp)->samples + half_index, half); \ - } \ - else { \ - /* Invokes the callback passing the whole buffer.*/ \ - (adcp)->grpp->end_cb(adcp, (adcp)->samples, (adcp)->depth); \ - } \ - } \ - } \ - else { \ - /* End conversion.*/ \ - adc_lld_stop_conversion(adcp); \ - if ((adcp)->grpp->end_cb != NULL) { \ - (adcp)->state = ADC_COMPLETE; \ - /* Invoke the callback passing the whole buffer.*/ \ - (adcp)->grpp->end_cb(adcp, (adcp)->samples, (adcp)->depth); \ - if ((adcp)->state == ADC_COMPLETE) { \ - (adcp)->state = ADC_READY; \ - (adcp)->grpp = NULL; \ - } \ - } \ - else { \ - (adcp)->state = ADC_READY; \ - (adcp)->grpp = NULL; \ - } \ - _adc_wakeup_isr(adcp); \ - } \ -} - -/** - * @brief Common ISR code, error event. - * @details This code handles the portable part of the ISR code: - * - Callback invocation. - * - Waiting thread timeout signaling, if any. - * - Driver state transitions. - * . - * @note This macro is meant to be used in the low level drivers - * implementation only. - * - * @param[in] adcp pointer to the @p ADCDriver object - * @param[in] err platform dependent error code - * - * @notapi - */ -#define _adc_isr_error_code(adcp, err) { \ - adc_lld_stop_conversion(adcp); \ - if ((adcp)->grpp->error_cb != NULL) { \ - (adcp)->state = ADC_ERROR; \ - (adcp)->grpp->error_cb(adcp, err); \ - if ((adcp)->state == ADC_ERROR) \ - (adcp)->state = ADC_READY; \ - } \ - (adcp)->grpp = NULL; \ - _adc_timeout_isr(adcp); \ -} -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void adcInit(void); - void adcObjectInit(ADCDriver *adcp); - void adcStart(ADCDriver *adcp, const ADCConfig *config); - void adcStop(ADCDriver *adcp); - void adcStartConversion(ADCDriver *adcp, - const ADCConversionGroup *grpp, - adcsample_t *samples, - size_t depth); - void adcStartConversionI(ADCDriver *adcp, - const ADCConversionGroup *grpp, - adcsample_t *samples, - size_t depth); - void adcStopConversion(ADCDriver *adcp); - void adcStopConversionI(ADCDriver *adcp); -#if ADC_USE_WAIT - msg_t adcConvert(ADCDriver *adcp, - const ADCConversionGroup *grpp, - adcsample_t *samples, - size_t depth); -#endif -#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) - void adcAcquireBus(ADCDriver *adcp); - void adcReleaseBus(ADCDriver *adcp); -#endif /* ADC_USE_MUTUAL_EXCLUSION */ -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_ADC */ - -#endif /* _ADC_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/include/can.h b/firmware/chibios/os/hal/include/can.h deleted file mode 100644 index 99d2604c10..0000000000 --- a/firmware/chibios/os/hal/include/can.h +++ /dev/null @@ -1,165 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file can.h - * @brief CAN Driver macros and structures. - * - * @addtogroup CAN - * @{ - */ - -#ifndef _CAN_H_ -#define _CAN_H_ - -#if HAL_USE_CAN || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name CAN status flags - * @{ - */ -/** - * @brief Errors rate warning. - */ -#define CAN_LIMIT_WARNING 1 -/** - * @brief Errors rate error. - */ -#define CAN_LIMIT_ERROR 2 -/** - * @brief Bus off condition reached. - */ -#define CAN_BUS_OFF_ERROR 4 -/** - * @brief Framing error of some kind on the CAN bus. - */ -#define CAN_FRAMING_ERROR 8 -/** - * @brief Overflow in receive queue. - */ -#define CAN_OVERFLOW_ERROR 16 -/** @} */ - -/** - * @brief Special mailbox identifier. - */ -#define CAN_ANY_MAILBOX 0 - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name CAN configuration options - * @{ - */ -/** - * @brief Sleep mode related APIs inclusion switch. - * @details This option can only be enabled if the CAN implementation supports - * the sleep mode, see the macro @p CAN_SUPPORTS_SLEEP exported by - * the underlying implementation. - */ -#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) -#define CAN_USE_SLEEP_MODE TRUE -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !CH_USE_SEMAPHORES || !CH_USE_EVENTS -#error "CAN driver requires CH_USE_SEMAPHORES and CH_USE_EVENTS" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - CAN_UNINIT = 0, /**< Not initialized. */ - CAN_STOP = 1, /**< Stopped. */ - CAN_STARTING = 2, /**< Starting. */ - CAN_READY = 3, /**< Ready. */ - CAN_SLEEP = 4 /**< Sleep state. */ -} canstate_t; - -#include "can_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Converts a mailbox index to a bit mask. - */ -#define CAN_MAILBOX_TO_MASK(mbx) (1 << ((mbx) - 1)) -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void canInit(void); - void canObjectInit(CANDriver *canp); - void canStart(CANDriver *canp, const CANConfig *config); - void canStop(CANDriver *canp); - msg_t canTransmit(CANDriver *canp, - canmbx_t mailbox, - const CANTxFrame *ctfp, - systime_t timeout); - msg_t canReceive(CANDriver *canp, - canmbx_t mailbox, - CANRxFrame *crfp, - systime_t timeout); -#if CAN_USE_SLEEP_MODE - void canSleep(CANDriver *canp); - void canWakeup(CANDriver *canp); -#endif /* CAN_USE_SLEEP_MODE */ -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_CAN */ - -#endif /* _CAN_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/include/ext.h b/firmware/chibios/os/hal/include/ext.h deleted file mode 100644 index 8665a5f5d1..0000000000 --- a/firmware/chibios/os/hal/include/ext.h +++ /dev/null @@ -1,161 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file ext.h - * @brief EXT Driver macros and structures. - * - * @addtogroup EXT - * @{ - */ - -#ifndef _EXT_H_ -#define _EXT_H_ - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name EXT channel modes - * @{ - */ -#define EXT_CH_MODE_EDGES_MASK 3 /**< @brief Mask of edges field. */ -#define EXT_CH_MODE_DISABLED 0 /**< @brief Channel disabled. */ -#define EXT_CH_MODE_RISING_EDGE 1 /**< @brief Rising edge callback. */ -#define EXT_CH_MODE_FALLING_EDGE 2 /**< @brief Falling edge callback. */ -#define EXT_CH_MODE_BOTH_EDGES 3 /**< @brief Both edges callback. */ - -#define EXT_CH_MODE_AUTOSTART 4 /**< @brief Channel started - automatically on driver start. */ -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - EXT_UNINIT = 0, /**< Not initialized. */ - EXT_STOP = 1, /**< Stopped. */ - EXT_ACTIVE = 2, /**< Active. */ -} extstate_t; - -/** - * @brief Type of a structure representing a EXT driver. - */ -typedef struct EXTDriver EXTDriver; - -#include "ext_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Enables an EXT channel. - * - * @param[in] extp pointer to the @p EXTDriver object - * @param[in] channel channel to be enabled - * - * @iclass - */ -#define extChannelEnableI(extp, channel) ext_lld_channel_enable(extp, channel) - -/** - * @brief Disables an EXT channel. - * - * @param[in] extp pointer to the @p EXTDriver object - * @param[in] channel channel to be disabled - * - * @iclass - */ -#define extChannelDisableI(extp, channel) ext_lld_channel_disable(extp, channel) - -/** - * @brief Changes the operation mode of a channel. - * @note This function attempts to write over the current configuration - * structure that must have been not declared constant. This - * violates the @p const qualifier in @p extStart() but it is - * intentional. This function cannot be used if the configuration - * structure is declared @p const. - * - * @param[in] extp pointer to the @p EXTDriver object - * @param[in] channel channel to be changed - * @param[in] extcp new configuration for the channel - * - * @api - */ -#define extSetChannelMode(extp, channel, extcp) { \ - chSysLock(); \ - extSetChannelModeI(extp, channel, extcp); \ - chSysUnlock(); \ -} - -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void extInit(void); - void extObjectInit(EXTDriver *extp); - void extStart(EXTDriver *extp, const EXTConfig *config); - void extStop(EXTDriver *extp); - void extChannelEnable(EXTDriver *extp, expchannel_t channel); - void extChannelDisable(EXTDriver *extp, expchannel_t channel); - void extSetChannelModeI(EXTDriver *extp, - expchannel_t channel, - const EXTChannelConfig *extcp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_EXT */ - -#endif /* _EXT_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/include/gpt.h b/firmware/chibios/os/hal/include/gpt.h deleted file mode 100644 index e9ac3a5c2f..0000000000 --- a/firmware/chibios/os/hal/include/gpt.h +++ /dev/null @@ -1,130 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file gpt.h - * @brief GPT Driver macros and structures. - * - * @addtogroup GPT - * @{ - */ - -#ifndef _GPT_H_ -#define _GPT_H_ - -#if HAL_USE_GPT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - GPT_UNINIT = 0, /**< Not initialized. */ - GPT_STOP = 1, /**< Stopped. */ - GPT_READY = 2, /**< Ready. */ - GPT_CONTINUOUS = 3, /**< Active in continuous mode. */ - GPT_ONESHOT = 4 /**< Active in one shot mode. */ -} gptstate_t; - -/** - * @brief Type of a structure representing a GPT driver. - */ -typedef struct GPTDriver GPTDriver; - -/** - * @brief GPT notification callback type. - * - * @param[in] gptp pointer to a @p GPTDriver object - */ -typedef void (*gptcallback_t)(GPTDriver *gptp); - -#include "gpt_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Changes the interval of GPT peripheral. - * @details This function changes the interval of a running GPT unit. - * @pre The GPT unit must have been activated using @p gptStart(). - * @pre The GPT unit must have been running in continuous mode using - * @p gptStartContinuous(). - * @post The GPT unit interval is changed to the new value. - * - * @param[in] gptp pointer to a @p GPTDriver object - * @param[in] interval new cycle time in timer ticks - * - * @iclass - */ -#define gptChangeIntervalI(gptp, interval) { \ - gpt_lld_change_interval(gptp, interval); \ -} - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void gptInit(void); - void gptObjectInit(GPTDriver *gptp); - void gptStart(GPTDriver *gptp, const GPTConfig *config); - void gptStop(GPTDriver *gptp); - void gptStartContinuous(GPTDriver *gptp, gptcnt_t interval); - void gptStartContinuousI(GPTDriver *gptp, gptcnt_t interval); - void gptChangeInterval(GPTDriver *gptp, gptcnt_t interval); - void gptStartOneShot(GPTDriver *gptp, gptcnt_t interval); - void gptStartOneShotI(GPTDriver *gptp, gptcnt_t interval); - void gptStopTimer(GPTDriver *gptp); - void gptStopTimerI(GPTDriver *gptp); - void gptPolledDelay(GPTDriver *gptp, gptcnt_t interval); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_GPT */ - -#endif /* _GPT_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/include/hal.h b/firmware/chibios/os/hal/include/hal.h deleted file mode 100644 index 74d87b4825..0000000000 --- a/firmware/chibios/os/hal/include/hal.h +++ /dev/null @@ -1,219 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file hal.h - * @brief HAL subsystem header. - * - * @addtogroup HAL - * @{ - */ - -#ifndef _HAL_H_ -#define _HAL_H_ - -#include "ch.h" -#include "board.h" -#include "halconf.h" - -#include "hal_lld.h" - -/* Abstract interfaces.*/ -#include "io_channel.h" -#include "io_block.h" - -/* Shared headers.*/ -#include "mmcsd.h" - -/* Layered drivers.*/ -#include "tm.h" -#include "pal.h" -#include "adc.h" -#include "can.h" -#include "ext.h" -#include "gpt.h" -#include "i2c.h" -#include "icu.h" -#include "mac.h" -#include "pwm.h" -#include "rtc.h" -#include "serial.h" -#include "sdc.h" -#include "spi.h" -#include "uart.h" -#include "usb.h" - -/* Complex drivers.*/ -#include "mmc_spi.h" -#include "serial_usb.h" - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -#if HAL_IMPLEMENTS_COUNTERS || defined(__DOXYGEN__) -/** - * @name Time conversion utilities for the realtime counter - * @{ - */ -/** - * @brief Seconds to realtime ticks. - * @details Converts from seconds to realtime ticks number. - * @note The result is rounded upward to the next tick boundary. - * - * @param[in] sec number of seconds - * @return The number of ticks. - * - * @api - */ -#define S2RTT(sec) (halGetCounterFrequency() * (sec)) - -/** - * @brief Milliseconds to realtime ticks. - * @details Converts from milliseconds to realtime ticks number. - * @note The result is rounded upward to the next tick boundary. - * - * @param[in] msec number of milliseconds - * @return The number of ticks. - * - * @api - */ -#define MS2RTT(msec) (((halGetCounterFrequency() + 999UL) / 1000UL) * (msec)) - -/** - * @brief Microseconds to realtime ticks. - * @details Converts from microseconds to realtime ticks number. - * @note The result is rounded upward to the next tick boundary. - * - * @param[in] usec number of microseconds - * @return The number of ticks. - * - * @api - */ -#define US2RTT(usec) (((halGetCounterFrequency() + 999999UL) / 1000000UL) * \ - (usec)) - -/** - * @brief Realtime ticks to seconds to. - * @details Converts from realtime ticks number to seconds. - * - * @param[in] ticks number of ticks - * @return The number of seconds. - * - * @api - */ -#define RTT2S(ticks) ((ticks) / halGetCounterFrequency()) - -/** - * @brief Realtime ticks to milliseconds. - * @details Converts from realtime ticks number to milliseconds. - * - * @param[in] ticks number of ticks - * @return The number of milliseconds. - * - * @api - */ -#define RTT2MS(ticks) ((ticks) / (halGetCounterFrequency() / 1000UL)) - -/** - * @brief Realtime ticks to microseconds. - * @details Converts from realtime ticks number to microseconds. - * - * @param[in] ticks number of ticks - * @return The number of microseconds. - * - * @api - */ -#define RTT2US(ticks) ((ticks) / (halGetCounterFrequency() / 1000000UL)) -/** @} */ - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Returns the current value of the system free running counter. - * @note This is an optional service that could not be implemented in - * all HAL implementations. - * @note This function can be called from any context. - * - * @return The value of the system free running counter of - * type halrtcnt_t. - * - * @special - */ -#define halGetCounterValue() hal_lld_get_counter_value() - -/** - * @brief Realtime counter frequency. - * @note This is an optional service that could not be implemented in - * all HAL implementations. - * @note This function can be called from any context. - * - * @return The realtime counter frequency of type halclock_t. - * - * @special - */ -#define halGetCounterFrequency() hal_lld_get_counter_frequency() -/** @} */ -#endif /* HAL_IMPLEMENTS_COUNTERS */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void halInit(void); -#if HAL_IMPLEMENTS_COUNTERS - bool_t halIsCounterWithin(halrtcnt_t start, halrtcnt_t end); - void halPolledDelay(halrtcnt_t ticks); -#endif /* HAL_IMPLEMENTS_COUNTERS */ -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/include/i2c.h b/firmware/chibios/os/hal/include/i2c.h deleted file mode 100644 index 048b57ef71..0000000000 --- a/firmware/chibios/os/hal/include/i2c.h +++ /dev/null @@ -1,154 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ -/* - Concepts and parts of this file have been contributed by Uladzimir Pylinsky - aka barthess. - */ - -/** - * @file i2c.h - * @brief I2C Driver macros and structures. - * - * @addtogroup I2C - * @{ - */ - -#ifndef _I2C_H_ -#define _I2C_H_ - -#if HAL_USE_I2C || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name I2C bus error conditions - * @{ - */ -#define I2CD_NO_ERROR 0x00 /**< @brief No error. */ -#define I2CD_BUS_ERROR 0x01 /**< @brief Bus Error. */ -#define I2CD_ARBITRATION_LOST 0x02 /**< @brief Arbitration Lost. */ -#define I2CD_ACK_FAILURE 0x04 /**< @brief Acknowledge Failure. */ -#define I2CD_OVERRUN 0x08 /**< @brief Overrun/Underrun. */ -#define I2CD_PEC_ERROR 0x10 /**< @brief PEC Error in - reception. */ -#define I2CD_TIMEOUT 0x20 /**< @brief Hardware timeout. */ -#define I2CD_SMB_ALERT 0x40 /**< @brief SMBus Alert. */ -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the mutual exclusion APIs on the I2C bus. - */ -#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define I2C_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if I2C_USE_MUTUAL_EXCLUSION && !CH_USE_MUTEXES && !CH_USE_SEMAPHORES -#error "I2C_USE_MUTUAL_EXCLUSION requires CH_USE_MUTEXES and/or CH_USE_SEMAPHORES" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - I2C_UNINIT = 0, /**< Not initialized. */ - I2C_STOP = 1, /**< Stopped. */ - I2C_READY = 2, /**< Ready. */ - I2C_ACTIVE_TX = 3, /**< Transmitting. */ - I2C_ACTIVE_RX = 4, /**< Receiving. */ - I2C_LOCKED = 5 /**> Bus or driver locked. */ -} i2cstate_t; - -#include "i2c_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Wrap i2cMasterTransmitTimeout function with TIME_INFINITE timeout. - * @api - */ -#define i2cMasterTransmit(i2cp, addr, txbuf, txbytes, rxbuf, rxbytes) \ - (i2cMasterTransmitTimeout(i2cp, addr, txbuf, txbytes, rxbuf, rxbytes, \ - TIME_INFINITE)) - -/** - * @brief Wrap i2cMasterReceiveTimeout function with TIME_INFINITE timeout. - * @api - */ -#define i2cMasterReceive(i2cp, addr, rxbuf, rxbytes) \ - (i2cMasterReceiveTimeout(i2cp, addr, rxbuf, rxbytes, TIME_INFINITE)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void i2cInit(void); - void i2cObjectInit(I2CDriver *i2cp); - void i2cStart(I2CDriver *i2cp, const I2CConfig *config); - void i2cStop(I2CDriver *i2cp); - i2cflags_t i2cGetErrors(I2CDriver *i2cp); - msg_t i2cMasterTransmitTimeout(I2CDriver *i2cp, - i2caddr_t addr, - const uint8_t *txbuf, size_t txbytes, - uint8_t *rxbuf, size_t rxbytes, - systime_t timeout); - msg_t i2cMasterReceiveTimeout(I2CDriver *i2cp, - i2caddr_t addr, - uint8_t *rxbuf, size_t rxbytes, - systime_t timeout); -#if I2C_USE_MUTUAL_EXCLUSION - void i2cAcquireBus(I2CDriver *i2cp); - void i2cReleaseBus(I2CDriver *i2cp); -#endif /* I2C_USE_MUTUAL_EXCLUSION */ - -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_I2C */ - -#endif /* _I2C_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/include/icu.h b/firmware/chibios/os/hal/include/icu.h deleted file mode 100644 index f759648cdd..0000000000 --- a/firmware/chibios/os/hal/include/icu.h +++ /dev/null @@ -1,203 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file icu.h - * @brief ICU Driver macros and structures. - * - * @addtogroup ICU - * @{ - */ - -#ifndef _ICU_H_ -#define _ICU_H_ - -#if HAL_USE_ICU || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - ICU_UNINIT = 0, /**< Not initialized. */ - ICU_STOP = 1, /**< Stopped. */ - ICU_READY = 2, /**< Ready. */ - ICU_WAITING = 3, /**< Waiting first edge. */ - ICU_ACTIVE = 4, /**< Active cycle phase. */ - ICU_IDLE = 5, /**< Idle cycle phase. */ -} icustate_t; - -/** - * @brief Type of a structure representing an ICU driver. - */ -typedef struct ICUDriver ICUDriver; - -/** - * @brief ICU notification callback type. - * - * @param[in] icup pointer to a @p ICUDriver object - */ -typedef void (*icucallback_t)(ICUDriver *icup); - -#include "icu_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Enables the input capture. - * - * @param[in] icup pointer to the @p ICUDriver object - * - * @iclass - */ -#define icuEnableI(icup) icu_lld_enable(icup) - -/** - * @brief Disables the input capture. - * - * @param[in] icup pointer to the @p ICUDriver object - * - * @iclass - */ -#define icuDisableI(icup) icu_lld_disable(icup) - -/** - * @brief Returns the width of the latest pulse. - * @details The pulse width is defined as number of ticks between the start - * edge and the stop edge. - * @note This function is meant to be invoked from the width capture - * callback only. - * - * @param[in] icup pointer to the @p ICUDriver object - * @return The number of ticks. - * - * @special - */ -#define icuGetWidth(icup) icu_lld_get_width(icup) - -/** - * @brief Returns the width of the latest cycle. - * @details The cycle width is defined as number of ticks between a start - * edge and the next start edge. - * @note This function is meant to be invoked from the width capture - * callback only. - * - * @param[in] icup pointer to the @p ICUDriver object - * @return The number of ticks. - * - * @special - */ -#define icuGetPeriod(icup) icu_lld_get_period(icup) -/** @} */ - -/** - * @name Low Level driver helper macros - * @{ - */ -/** - * @brief Common ISR code, ICU width event. - * - * @param[in] icup pointer to the @p ICUDriver object - * - * @notapi - */ -#define _icu_isr_invoke_width_cb(icup) { \ - if ((icup)->state != ICU_WAITING) { \ - (icup)->state = ICU_IDLE; \ - (icup)->config->width_cb(icup); \ - } \ -} - -/** - * @brief Common ISR code, ICU period event. - * - * @param[in] icup pointer to the @p ICUDriver object - * - * @notapi - */ -#define _icu_isr_invoke_period_cb(icup) { \ - icustate_t previous_state = (icup)->state; \ - (icup)->state = ICU_ACTIVE; \ - if (previous_state != ICU_WAITING) \ - (icup)->config->period_cb(icup); \ -} - -/** - * @brief Common ISR code, ICU timer overflow event. - * - * @param[in] icup pointer to the @p ICUDriver object - * - * @notapi - */ -#define _icu_isr_invoke_overflow_cb(icup) { \ - (icup)->config->overflow_cb(icup); \ -} -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void icuInit(void); - void icuObjectInit(ICUDriver *icup); - void icuStart(ICUDriver *icup, const ICUConfig *config); - void icuStop(ICUDriver *icup); - void icuEnable(ICUDriver *icup); - void icuDisable(ICUDriver *icup); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_ICU */ - -#endif /* _ICU_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/include/io_block.h b/firmware/chibios/os/hal/include/io_block.h deleted file mode 100644 index 70da543b41..0000000000 --- a/firmware/chibios/os/hal/include/io_block.h +++ /dev/null @@ -1,276 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file io_block.h - * @brief I/O block devices access. - * @details This header defines an abstract interface useful to access generic - * I/O block devices in a standardized way. - * - * @addtogroup IO_BLOCK - * @details This module defines an abstract interface for accessing generic - * block devices.
- * Note that no code is present, just abstract interfaces-like - * structures, you should look at the system as to a set of - * abstract C++ classes (even if written in C). This system - * has then advantage to make the access to block devices - * independent from the implementation logic. - * @{ - */ - -#ifndef _IO_BLOCK_H_ -#define _IO_BLOCK_H_ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - BLK_UNINIT = 0, /**< Not initialized. */ - BLK_STOP = 1, /**< Stopped. */ - BLK_ACTIVE = 2, /**< Interface active. */ - BLK_CONNECTING = 3, /**< Connection in progress. */ - BLK_DISCONNECTING = 4, /**< Disconnection in progress. */ - BLK_READY = 5, /**< Device ready. */ - BLK_READING = 6, /**< Read operation in progress. */ - BLK_WRITING = 7, /**< Write operation in progress. */ - BLK_SYNCING = 8 /**< Sync. operation in progress. */ -} blkstate_t; - -/** - * @brief Block device info. - */ -typedef struct { - uint32_t blk_size; /**< @brief Block size in bytes. */ - uint32_t blk_num; /**< @brief Total number of blocks. */ -} BlockDeviceInfo; - -/** - * @brief @p BaseBlockDevice specific methods. - */ -#define _base_block_device_methods \ - /* Removable media detection.*/ \ - bool_t (*is_inserted)(void *instance); \ - /* Removable write protection detection.*/ \ - bool_t (*is_protected)(void *instance); \ - /* Connection to the block device.*/ \ - bool_t (*connect)(void *instance); \ - /* Disconnection from the block device.*/ \ - bool_t (*disconnect)(void *instance); \ - /* Reads one or more blocks.*/ \ - bool_t (*read)(void *instance, uint32_t startblk, \ - uint8_t *buffer, uint32_t n); \ - /* Writes one or more blocks.*/ \ - bool_t (*write)(void *instance, uint32_t startblk, \ - const uint8_t *buffer, uint32_t n); \ - /* Write operations synchronization.*/ \ - bool_t (*sync)(void *instance); \ - /* Obtains info about the media.*/ \ - bool_t (*get_info)(void *instance, BlockDeviceInfo *bdip); - -/** - * @brief @p BaseBlockDevice specific data. - */ -#define _base_block_device_data \ - /* Driver state.*/ \ - blkstate_t state; - -/** - * @brief @p BaseBlockDevice virtual methods table. - */ -struct BaseBlockDeviceVMT { - _base_block_device_methods -}; - -/** - * @brief Base block device class. - * @details This class represents a generic, block-accessible, device. - */ -typedef struct { - /** @brief Virtual Methods Table.*/ - const struct BaseBlockDeviceVMT *vmt; - _base_block_device_data -} BaseBlockDevice; - -/** - * @name Macro Functions (BaseBlockDevice) - * @{ - */ -/** - * @brief Returns the driver state. - * @note Can be called in ISR context. - * - * @param[in] ip pointer to a @p BaseBlockDevice or derived class - * - * @return The driver state. - * - * @special - */ -#define blkGetDriverState(ip) ((ip)->state) - -/** - * @brief Determines if the device is transferring data. - * @note Can be called in ISR context. - * - * @param[in] ip pointer to a @p BaseBlockDevice or derived class - * - * @return The driver state. - * @retval FALSE the device is not transferring data. - * @retval TRUE the device not transferring data. - * - * @special - */ -#define blkIsTransferring(ip) ((((ip)->state) == BLK_CONNECTING) || \ - (((ip)->state) == BLK_DISCONNECTING) || \ - (((ip)->state) == BLK_READING) || \ - (((ip)->state) == BLK_WRITING)) - -/** - * @brief Returns the media insertion status. - * @note On some implementations this function can only be called if the - * device is not transferring data. - * The function @p blkIsTransferring() should be used before calling - * this function. - * - * @param[in] ip pointer to a @p BaseBlockDevice or derived class - * - * @return The media state. - * @retval FALSE media not inserted. - * @retval TRUE media inserted. - * - * @api - */ -#define blkIsInserted(ip) ((ip)->vmt->is_inserted(ip)) - -/** - * @brief Returns the media write protection status. - * - * @param[in] ip pointer to a @p BaseBlockDevice or derived class - * - * @return The media state. - * @retval FALSE writable media. - * @retval TRUE non writable media. - * - * @api - */ -#define blkIsWriteProtected(ip) ((ip)->vmt->is_protected(ip)) - -/** - * @brief Performs the initialization procedure on the block device. - * @details This function should be performed before I/O operations can be - * attempted on the block device and after insertion has been - * confirmed using @p blkIsInserted(). - * - * @param[in] ip pointer to a @p BaseBlockDevice or derived class - * - * @return The operation status. - * @retval CH_SUCCESS operation succeeded. - * @retval CH_FAILED operation failed. - * - * @api - */ -#define blkConnect(ip) ((ip)->vmt->connect(ip)) - -/** - * @brief Terminates operations on the block device. - * @details This operation safely terminates operations on the block device. - * - * @param[in] ip pointer to a @p BaseBlockDevice or derived class - * - * @return The operation status. - * @retval CH_SUCCESS operation succeeded. - * @retval CH_FAILED operation failed. - * - * @api - */ -#define blkDisconnect(ip) ((ip)->vmt->disconnect(ip)) - -/** - * @brief Reads one or more blocks. - * - * @param[in] ip pointer to a @p BaseBlockDevice or derived class - * @param[in] startblk first block to read - * @param[out] buf pointer to the read buffer - * @param[in] n number of blocks to read - * - * @return The operation status. - * @retval CH_SUCCESS operation succeeded. - * @retval CH_FAILED operation failed. - * - * @api - */ -#define blkRead(ip, startblk, buf, n) \ - ((ip)->vmt->read(ip, startblk, buf, n)) - -/** - * @brief Writes one or more blocks. - * - * @param[in] ip pointer to a @p BaseBlockDevice or derived class - * @param[in] startblk first block to write - * @param[out] buf pointer to the write buffer - * @param[in] n number of blocks to write - * - * @return The operation status. - * @retval CH_SUCCESS operation succeeded. - * @retval CH_FAILED operation failed. - * - * @api - */ -#define blkWrite(ip, startblk, buf, n) \ - ((ip)->vmt->write(ip, startblk, buf, n)) - -/** - * @brief Ensures write synchronization. - * - * @param[in] ip pointer to a @p BaseBlockDevice or derived class - * - * @return The operation status. - * @retval CH_SUCCESS operation succeeded. - * @retval CH_FAILED operation failed. - * - * @api - */ -#define blkSync(ip) ((ip)->vmt->sync(ip)) - -/** - * @brief Returns a media information structure. - * - * @param[in] ip pointer to a @p BaseBlockDevice or derived class - * @param[out] bdip pointer to a @p BlockDeviceInfo structure - * - * @return The operation status. - * @retval CH_SUCCESS operation succeeded. - * @retval CH_FAILED operation failed. - * - * @api - */ -#define blkGetInfo(ip, bdip) ((ip)->vmt->get_info(ip, bdip)) - -/** @} */ - -#endif /* _IO_BLOCK_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/include/io_channel.h b/firmware/chibios/os/hal/include/io_channel.h deleted file mode 100644 index 7de6ea6c21..0000000000 --- a/firmware/chibios/os/hal/include/io_channel.h +++ /dev/null @@ -1,301 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file io_channel.h - * @brief I/O channels access. - * @details This header defines an abstract interface useful to access generic - * I/O serial devices in a standardized way. - * - * @addtogroup IO_CHANNEL - * @details This module defines an abstract interface for I/O channels by - * extending the @p BaseSequentialStream interface.
- * Note that no code is present, I/O channels are just abstract - * interface like structures, you should look at the systems as - * to a set of abstract C++ classes (even if written in C). - * Specific device drivers can use/extend the interface and - * implement them.
- * This system has the advantage to make the access to channels - * independent from the implementation logic. - * @{ - */ - -#ifndef _IO_CHANNEL_H_ -#define _IO_CHANNEL_H_ - -/** - * @brief @p BaseChannel specific methods. - */ -#define _base_channel_methods \ - _base_sequential_stream_methods \ - /* Channel put method with timeout specification.*/ \ - msg_t (*putt)(void *instance, uint8_t b, systime_t time); \ - /* Channel get method with timeout specification.*/ \ - msg_t (*gett)(void *instance, systime_t time); \ - /* Channel write method with timeout specification.*/ \ - size_t (*writet)(void *instance, const uint8_t *bp, \ - size_t n, systime_t time); \ - /* Channel read method with timeout specification.*/ \ - size_t (*readt)(void *instance, uint8_t *bp, size_t n, systime_t time); - -/** - * @brief @p BaseChannel specific data. - * @note It is empty because @p BaseChannel is only an interface without - * implementation. - */ -#define _base_channel_data \ - _base_sequential_stream_data - -/** - * @extends BaseSequentialStreamVMT - * - * @brief @p BaseChannel virtual methods table. - */ -struct BaseChannelVMT { - _base_channel_methods -}; - -/** - * @extends BaseSequentialStream - * - * @brief Base channel class. - * @details This class represents a generic, byte-wide, I/O channel. This class - * introduces generic I/O primitives with timeout specification. - */ -typedef struct { - /** @brief Virtual Methods Table.*/ - const struct BaseChannelVMT *vmt; - _base_channel_data -} BaseChannel; - -/** - * @name Macro Functions (BaseChannel) - * @{ - */ -/** - * @brief Channel blocking byte write with timeout. - * @details This function writes a byte value to a channel. If the channel - * is not ready to accept data then the calling thread is suspended. - * - * @param[in] ip pointer to a @p BaseChannel or derived class - * @param[in] b the byte value to be written to the channel - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval Q_OK if the operation succeeded. - * @retval Q_TIMEOUT if the specified time expired. - * @retval Q_RESET if the channel associated queue (if any) was reset. - * - * @api - */ -#define chnPutTimeout(ip, b, time) ((ip)->vmt->putt(ip, b, time)) - -/** - * @brief Channel blocking byte read with timeout. - * @details This function reads a byte value from a channel. If the data - * is not available then the calling thread is suspended. - * - * @param[in] ip pointer to a @p BaseChannel or derived class - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return A byte value from the queue. - * @retval Q_TIMEOUT if the specified time expired. - * @retval Q_RESET if the channel associated queue (if any) has been - * reset. - * - * @api - */ -#define chnGetTimeout(ip, time) ((ip)->vmt->gett(ip, time)) - -/** - * @brief Channel blocking write. - * @details The function writes data from a buffer to a channel. If the channel - * is not ready to accept data then the calling thread is suspended. - * - * @param[in] ip pointer to a @p BaseChannel or derived class - * @param[out] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred - * - * @return The number of bytes transferred. - * - * @api - */ -#define chnWrite(ip, bp, n) chSequentialStreamWrite(ip, bp, n) - -/** - * @brief Channel blocking write with timeout. - * @details The function writes data from a buffer to a channel. If the channel - * is not ready to accept data then the calling thread is suspended. - * - * @param[in] ip pointer to a @p BaseChannel or derived class - * @param[out] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The number of bytes transferred. - * - * @api - */ -#define chnWriteTimeout(ip, bp, n, time) ((ip)->vmt->writet(ip, bp, n, time)) - -/** - * @brief Channel blocking read. - * @details The function reads data from a channel into a buffer. If the data - * is not available then the calling thread is suspended. - * - * @param[in] ip pointer to a @p BaseChannel or derived class - * @param[in] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred - * - * @return The number of bytes transferred. - * - * @api - */ -#define chnRead(ip, bp, n) chSequentialStreamRead(ip, bp, n) - -/** - * @brief Channel blocking read with timeout. - * @details The function reads data from a channel into a buffer. If the data - * is not available then the calling thread is suspended. - * - * @param[in] ip pointer to a @p BaseChannel or derived class - * @param[in] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The number of bytes transferred. - * - * @api - */ -#define chnReadTimeout(ip, bp, n, time) ((ip)->vmt->readt(ip, bp, n, time)) -/** @} */ - -#if CH_USE_EVENTS || defined(__DOXYGEN__) -/** - * @name I/O status flags added to the event listener - * @{ - */ -/** @brief No pending conditions.*/ -#define CHN_NO_ERROR 0 -/** @brief Connection happened.*/ -#define CHN_CONNECTED 1 -/** @brief Disconnection happened.*/ -#define CHN_DISCONNECTED 2 -/** @brief Data available in the input queue.*/ -#define CHN_INPUT_AVAILABLE 4 -/** @brief Output queue empty.*/ -#define CHN_OUTPUT_EMPTY 8 -/** @brief Transmission end.*/ -#define CHN_TRANSMISSION_END 16 -/** @} */ - -/** - * @brief @p BaseAsynchronousChannel specific methods. - */ -#define _base_asynchronous_channel_methods \ - _base_channel_methods \ - -/** - * @brief @p BaseAsynchronousChannel specific data. - */ -#define _base_asynchronous_channel_data \ - _base_channel_data \ - /* I/O condition event source.*/ \ - EventSource event; - -/** - * @extends BaseChannelVMT - * - * @brief @p BaseAsynchronousChannel virtual methods table. - */ -struct BaseAsynchronousChannelVMT { - _base_asynchronous_channel_methods -}; - -/** - * @extends BaseChannel - * - * @brief Base asynchronous channel class. - * @details This class extends @p BaseChannel by adding event sources fields - * for asynchronous I/O for use in an event-driven environment. - */ -typedef struct { - /** @brief Virtual Methods Table.*/ - const struct BaseAsynchronousChannelVMT *vmt; - _base_asynchronous_channel_data -} BaseAsynchronousChannel; - -/** - * @name Macro Functions (BaseAsynchronousChannel) - * @{ - */ -/** - * @brief Returns the I/O condition event source. - * @details The event source is broadcasted when an I/O condition happens. - * - * @param[in] ip pointer to a @p BaseAsynchronousChannel or derived - * class - * @return A pointer to an @p EventSource object. - * - * @api - */ -#define chnGetEventSource(ip) (&((ip)->event)) - -/** - * @brief Adds status flags to the listeners's flags mask. - * @details This function is usually called from the I/O ISRs in order to - * notify I/O conditions such as data events, errors, signal - * changes etc. - * - * @param[in] ip pointer to a @p BaseAsynchronousChannel or derived - * class - * @param[in] flags condition flags to be added to the listener flags mask - * - * @iclass - */ -#define chnAddFlagsI(ip, flags) { \ - chEvtBroadcastFlagsI(&(ip)->event, flags); \ -} -/** @} */ - -#endif /* CH_USE_EVENTS */ - -#endif /* _IO_CHANNEL_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/include/mac.h b/firmware/chibios/os/hal/include/mac.h deleted file mode 100644 index 590e880d61..0000000000 --- a/firmware/chibios/os/hal/include/mac.h +++ /dev/null @@ -1,221 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file mac.h - * @brief MAC Driver macros and structures. - * @addtogroup MAC - * @{ - */ - -#ifndef _MAC_H_ -#define _MAC_H_ - -#if HAL_USE_MAC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name MAC configuration options - * @{ - */ -/** - * @brief Enables an event sources for incoming packets. - */ -#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) -#define MAC_USE_ZERO_COPY FALSE -#endif - -/** - * @brief Enables an event sources for incoming packets. - */ -#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) -#define MAC_USE_EVENTS TRUE -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !CH_USE_SEMAPHORES || !CH_USE_EVENTS -#error "the MAC driver requires CH_USE_SEMAPHORES" -#endif - -#if MAC_USE_EVENTS && !CH_USE_EVENTS -#error "the MAC driver requires CH_USE_EVENTS" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - MAC_UNINIT = 0, /**< Not initialized. */ - MAC_STOP = 1, /**< Stopped. */ - MAC_ACTIVE = 2 /**< Active. */ -} macstate_t; - -/** - * @brief Type of a structure representing a MAC driver. - */ -typedef struct MACDriver MACDriver; - -#include "mac_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Returns the received frames event source. - * - * @param[in] macp pointer to the @p MACDriver object - * @return The pointer to the @p EventSource structure. - * - * @api - */ -#if MAC_USE_EVENTS || defined(__DOXYGEN__) -#define macGetReceiveEventSource(macp) (&(macp)->rdevent) -#endif - -/** - * @brief Writes to a transmit descriptor's stream. - * - * @param[in] tdp pointer to a @p MACTransmitDescriptor structure - * @param[in] buf pointer to the buffer containing the data to be written - * @param[in] size number of bytes to be written - * @return The number of bytes written into the descriptor's - * stream, this value can be less than the amount - * specified in the parameter @p size if the maximum frame - * size is reached. - * - * @api - */ -#define macWriteTransmitDescriptor(tdp, buf, size) \ - mac_lld_write_transmit_descriptor(tdp, buf, size) - -/** - * @brief Reads from a receive descriptor's stream. - * - * @param[in] rdp pointer to a @p MACReceiveDescriptor structure - * @param[in] buf pointer to the buffer that will receive the read data - * @param[in] size number of bytes to be read - * @return The number of bytes read from the descriptor's stream, - * this value can be less than the amount specified in the - * parameter @p size if there are no more bytes to read. - * - * @api - */ -#define macReadReceiveDescriptor(rdp, buf, size) \ - mac_lld_read_receive_descriptor(rdp, buf, size) - -#if MAC_USE_ZERO_COPY || defined(__DOXYGEN__) -/** - * @brief Returns a pointer to the next transmit buffer in the descriptor - * chain. - * @note The API guarantees that enough buffers can be requested to fill - * a whole frame. - * - * @param[in] tdp pointer to a @p MACTransmitDescriptor structure - * @param[in] size size of the requested buffer. Specify the frame size - * on the first call then scale the value down subtracting - * the amount of data already copied into the previous - * buffers. - * @param[out] sizep pointer to variable receiving the real buffer size. - * The returned value can be less than the amount - * requested, this means that more buffers must be - * requested in order to fill the frame data entirely. - * @return Pointer to the returned buffer. - * - * @api - */ -#define macGetNextTransmitBuffer(tdp, size, sizep) \ - mac_lld_get_next_transmit_buffer(tdp, size, sizep) - -/** - * @brief Returns a pointer to the next receive buffer in the descriptor - * chain. - * @note The API guarantees that the descriptor chain contains a whole - * frame. - * - * @param[in] rdp pointer to a @p MACReceiveDescriptor structure - * @param[out] sizep pointer to variable receiving the buffer size, it is - * zero when the last buffer has already been returned. - * @return Pointer to the returned buffer. - * @retval NULL if the buffer chain has been entirely scanned. - * - * @api - */ -#define macGetNextReceiveBuffer(rdp, sizep) \ - mac_lld_get_next_receive_buffer(rdp, sizep) -#endif /* MAC_USE_ZERO_COPY */ -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void macInit(void); - void macObjectInit(MACDriver *macp); - void macStart(MACDriver *macp, const MACConfig *config); - void macStop(MACDriver *macp); - void macSetAddress(MACDriver *macp, const uint8_t *p); - msg_t macWaitTransmitDescriptor(MACDriver *macp, - MACTransmitDescriptor *tdp, - systime_t time); - void macReleaseTransmitDescriptor(MACTransmitDescriptor *tdp); - msg_t macWaitReceiveDescriptor(MACDriver *macp, - MACReceiveDescriptor *rdp, - systime_t time); - void macReleaseReceiveDescriptor(MACReceiveDescriptor *rdp); - bool_t macPollLinkStatus(MACDriver *macp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_MAC */ - -#endif /* _MAC_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/include/mii.h b/firmware/chibios/os/hal/include/mii.h deleted file mode 100644 index 7eb26c0e10..0000000000 --- a/firmware/chibios/os/hal/include/mii.h +++ /dev/null @@ -1,169 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/*-* - * @file mii.h - * @brief MII Driver macros and structures. - * - * @addtogroup MII - * @{ - */ - -#ifndef _MII_H_ -#define _MII_H_ - -/* - * Generic MII registers. Note, not all registers are present on all PHY - * devices and some extra registers may be present. - */ -#define MII_BMCR 0x00 /**< Basic mode control register. */ -#define MII_BMSR 0x01 /**< Basic mode status register. */ -#define MII_PHYSID1 0x02 /**< PHYS ID 1. */ -#define MII_PHYSID2 0x03 /**< PHYS ID 2. */ -#define MII_ADVERTISE 0x04 /**< Advertisement control reg. */ -#define MII_LPA 0x05 /**< Link partner ability reg. */ -#define MII_EXPANSION 0x06 /**< Expansion register. */ -#define MII_ANNPTR 0x07 /**< 1000BASE-T control. */ -#define MII_CTRL1000 0x09 /**< 1000BASE-T control. */ -#define MII_STAT1000 0x0a /**< 1000BASE-T status. */ -#define MII_ESTATUS 0x0f /**< Extended Status. */ -#define MII_PHYSTS 0x10 /**< PHY Status register. */ -#define MII_MICR 0x11 /**< MII Interrupt ctrl register. */ -#define MII_DCOUNTER 0x12 /**< Disconnect counter. */ -#define MII_FCSCOUNTER 0x13 /**< False carrier counter. */ -#define MII_NWAYTEST 0x14 /**< N-way auto-neg test reg. */ -#define MII_RERRCOUNTER 0x15 /**< Receive error counter. */ -#define MII_SREVISION 0x16 /**< Silicon revision. */ -#define MII_RESV1 0x17 /**< Reserved. */ -#define MII_LBRERROR 0x18 /**< Lpback, rx, bypass error. */ -#define MII_PHYADDR 0x19 /**< PHY address. */ -#define MII_RESV2 0x1a /**< Reserved. */ -#define MII_TPISTATUS 0x1b /**< TPI status for 10Mbps. */ -#define MII_NCONFIG 0x1c /**< Network interface config. */ - -/* - * Basic mode control register. - */ -#define BMCR_RESV 0x007f /**< Unused. */ -#define BMCR_CTST 0x0080 /**< Collision test. */ -#define BMCR_FULLDPLX 0x0100 /**< Full duplex. */ -#define BMCR_ANRESTART 0x0200 /**< Auto negotiation restart. */ -#define BMCR_ISOLATE 0x0400 /**< Disconnect DP83840 from MII. */ -#define BMCR_PDOWN 0x0800 /**< Powerdown. */ -#define BMCR_ANENABLE 0x1000 /**< Enable auto negotiation. */ -#define BMCR_SPEED100 0x2000 /**< Select 100Mbps. */ -#define BMCR_LOOPBACK 0x4000 /**< TXD loopback bit. */ -#define BMCR_RESET 0x8000 /**< Reset. */ - -/* - * Basic mode status register. - */ -#define BMSR_ERCAP 0x0001 /**< Ext-reg capability. */ -#define BMSR_JCD 0x0002 /**< Jabber detected. */ -#define BMSR_LSTATUS 0x0004 /**< Link status. */ -#define BMSR_ANEGCAPABLE 0x0008 /**< Able to do auto-negotiation. */ -#define BMSR_RFAULT 0x0010 /**< Remote fault detected. */ -#define BMSR_ANEGCOMPLETE 0x0020 /**< Auto-negotiation complete. */ -#define BMSR_MFPRESUPPCAP 0x0040 /**< Able to suppress preamble. */ -#define BMSR_RESV 0x0780 /**< Unused. */ -#define BMSR_10HALF 0x0800 /**< Can do 10mbps, half-duplex. */ -#define BMSR_10FULL 0x1000 /**< Can do 10mbps, full-duplex. */ -#define BMSR_100HALF 0x2000 /**< Can do 100mbps, half-duplex. */ -#define BMSR_100FULL 0x4000 /**< Can do 100mbps, full-duplex. */ -#define BMSR_100BASE4 0x8000 /**< Can do 100mbps, 4k packets. */ - -/* - * Advertisement control register. - */ -#define ADVERTISE_SLCT 0x001f /**< Selector bits. */ -#define ADVERTISE_CSMA 0x0001 /**< Only selector supported. */ -#define ADVERTISE_10HALF 0x0020 /**< Try for 10mbps half-duplex. */ -#define ADVERTISE_10FULL 0x0040 /**< Try for 10mbps full-duplex. */ -#define ADVERTISE_100HALF 0x0080 /**< Try for 100mbps half-duplex. */ -#define ADVERTISE_100FULL 0x0100 /**< Try for 100mbps full-duplex. */ -#define ADVERTISE_100BASE4 0x0200 /**< Try for 100mbps 4k packets. */ -#define ADVERTISE_PAUSE_CAP 0x0400 /**< Try for pause. */ -#define ADVERTISE_PAUSE_ASYM 0x0800 /**< Try for asymetric pause. */ -#define ADVERTISE_RESV 0x1000 /**< Unused. */ -#define ADVERTISE_RFAULT 0x2000 /**< Say we can detect faults. */ -#define ADVERTISE_LPACK 0x4000 /**< Ack link partners response. */ -#define ADVERTISE_NPAGE 0x8000 /**< Next page bit. */ - -#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ - ADVERTISE_CSMA) -#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ - ADVERTISE_100HALF | ADVERTISE_100FULL) - -/* - * Link partner ability register. - */ -#define LPA_SLCT 0x001f /**< Same as advertise selector. */ -#define LPA_10HALF 0x0020 /**< Can do 10mbps half-duplex. */ -#define LPA_10FULL 0x0040 /**< Can do 10mbps full-duplex. */ -#define LPA_100HALF 0x0080 /**< Can do 100mbps half-duplex. */ -#define LPA_100FULL 0x0100 /**< Can do 100mbps full-duplex. */ -#define LPA_100BASE4 0x0200 /**< Can do 100mbps 4k packets. */ -#define LPA_PAUSE_CAP 0x0400 /**< Can pause. */ -#define LPA_PAUSE_ASYM 0x0800 /**< Can pause asymetrically. */ -#define LPA_RESV 0x1000 /**< Unused. */ -#define LPA_RFAULT 0x2000 /**< Link partner faulted. */ -#define LPA_LPACK 0x4000 /**< Link partner acked us. */ -#define LPA_NPAGE 0x8000 /**< Next page bit. */ - -#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) -#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) - -/* - * Expansion register for auto-negotiation. - */ -#define EXPANSION_NWAY 0x0001 /**< Can do N-way auto-nego. */ -#define EXPANSION_LCWP 0x0002 /**< Got new RX page code word. */ -#define EXPANSION_ENABLENPAGE 0x0004 /**< This enables npage words. */ -#define EXPANSION_NPCAPABLE 0x0008 /**< Link partner supports npage. */ -#define EXPANSION_MFAULTS 0x0010 /**< Multiple faults detected. */ -#define EXPANSION_RESV 0xffe0 /**< Unused. */ - -/* - * N-way test register. - */ -#define NWAYTEST_RESV1 0x00ff /**< Unused. */ -#define NWAYTEST_LOOPBACK 0x0100 /**< Enable loopback for N-way. */ -#define NWAYTEST_RESV2 0xfe00 /**< Unused. */ - -/* - * PHY identifiers. - */ -#define MII_DM9161_ID 0x0181b8a0 -#define MII_AM79C875_ID 0x00225540 -#define MII_KS8721_ID 0x00221610 -#define MII_STE101P_ID 0x00061C50 -#define MII_DP83848I_ID 0x20005C90 -#define MII_LAN8710A_ID 0x0007C0F1 - -#endif /* _MII_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/include/mmc_spi.h b/firmware/chibios/os/hal/include/mmc_spi.h deleted file mode 100644 index 9c976a87ad..0000000000 --- a/firmware/chibios/os/hal/include/mmc_spi.h +++ /dev/null @@ -1,206 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file mmc_spi.h - * @brief MMC over SPI driver header. - * - * @addtogroup MMC_SPI - * @{ - */ - -#ifndef _MMC_SPI_H_ -#define _MMC_SPI_H_ - -#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#define MMC_CMD0_RETRY 10 -#define MMC_CMD1_RETRY 100 -#define MMC_ACMD41_RETRY 100 -#define MMC_WAIT_DATA 10000 - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name MMC_SPI configuration options - * @{ - */ -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - * This option is recommended also if the SPI driver does not - * use a DMA channel and heavily loads the CPU. - */ -#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) -#define MMC_NICE_WAITING TRUE -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !HAL_USE_SPI || !SPI_USE_WAIT -#error "MMC_SPI driver requires HAL_USE_SPI and SPI_USE_WAIT" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief MMC/SD over SPI driver configuration structure. - */ -typedef struct { - /** - * @brief SPI driver associated to this MMC driver. - */ - SPIDriver *spip; - /** - * @brief SPI low speed configuration used during initialization. - */ - const SPIConfig *lscfg; - /** - * @brief SPI high speed configuration used during transfers. - */ - const SPIConfig *hscfg; -} MMCConfig; - -/** - * @brief @p MMCDriver specific methods. - */ -#define _mmc_driver_methods \ - _mmcsd_block_device_methods - -/** - * @extends MMCSDBlockDeviceVMT - * - * @brief @p MMCDriver virtual methods table. - */ -struct MMCDriverVMT { - _mmc_driver_methods -}; - -/** - * @extends MMCSDBlockDevice - * - * @brief Structure representing a MMC/SD over SPI driver. - */ -typedef struct { - /** - * @brief Virtual Methods Table. - */ - const struct MMCDriverVMT *vmt; - _mmcsd_block_device_data - /** - * @brief Current configuration data. - */ - const MMCConfig *config; - /*** - * @brief Addresses use blocks instead of bytes. - */ - bool_t block_addresses; -} MMCDriver; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Returns the card insertion status. - * @note This macro wraps a low level function named - * @p sdc_lld_is_card_inserted(), this function must be - * provided by the application because it is not part of the - * SDC driver. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @return The card state. - * @retval FALSE card not inserted. - * @retval TRUE card inserted. - * - * @api - */ -#define mmcIsCardInserted(mmcp) mmc_lld_is_card_inserted(mmcp) - -/** - * @brief Returns the write protect status. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @return The card state. - * @retval FALSE card not inserted. - * @retval TRUE card inserted. - * - * @api - */ -#define mmcIsWriteProtected(mmcp) mmc_lld_is_write_protected(mmcp) -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void mmcInit(void); - void mmcObjectInit(MMCDriver *mmcp); - void mmcStart(MMCDriver *mmcp, const MMCConfig *config); - void mmcStop(MMCDriver *mmcp); - bool_t mmcConnect(MMCDriver *mmcp); - bool_t mmcDisconnect(MMCDriver *mmcp); - bool_t mmcStartSequentialRead(MMCDriver *mmcp, uint32_t startblk); - bool_t mmcSequentialRead(MMCDriver *mmcp, uint8_t *buffer); - bool_t mmcStopSequentialRead(MMCDriver *mmcp); - bool_t mmcStartSequentialWrite(MMCDriver *mmcp, uint32_t startblk); - bool_t mmcSequentialWrite(MMCDriver *mmcp, const uint8_t *buffer); - bool_t mmcStopSequentialWrite(MMCDriver *mmcp); - bool_t mmcSync(MMCDriver *mmcp); - bool_t mmcGetInfo(MMCDriver *mmcp, BlockDeviceInfo *bdip); - bool_t mmcErase(MMCDriver *mmcp, uint32_t startblk, uint32_t endblk); - bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp); - bool_t mmc_lld_is_write_protected(MMCDriver *mmcp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_MMC_SPI */ - -#endif /* _MMC_SPI_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/include/mmcsd.h b/firmware/chibios/os/hal/include/mmcsd.h deleted file mode 100644 index 866267babb..0000000000 --- a/firmware/chibios/os/hal/include/mmcsd.h +++ /dev/null @@ -1,286 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file mmcsd.h - * @brief MMC/SD cards common header. - * @details This header defines an abstract interface useful to access MMC/SD - * I/O block devices in a standardized way. - * - * @addtogroup MMCSD - * @{ - */ - -#ifndef _MMCSD_H_ -#define _MMCSD_H_ - -#if HAL_USE_MMC_SPI || HAL_USE_SDC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Fixed block size for MMC/SD block devices. - */ -#define MMCSD_BLOCK_SIZE 512 - -/** - * @brief Mask of error bits in R1 responses. - */ -#define MMCSD_R1_ERROR_MASK 0xFDFFE008 - -/** - * @brief Fixed pattern for CMD8. - */ -#define MMCSD_CMD8_PATTERN 0x000001AA - -/** - * @name SD/MMC status conditions - * @{ - */ -#define MMCSD_STS_IDLE 0 -#define MMCSD_STS_READY 1 -#define MMCSD_STS_IDENT 2 -#define MMCSD_STS_STBY 3 -#define MMCSD_STS_TRAN 4 -#define MMCSD_STS_DATA 5 -#define MMCSD_STS_RCV 6 -#define MMCSD_STS_PRG 7 -#define MMCSD_STS_DIS 8 -/** @} */ - -/** - * @name SD/MMC commands - * @{ - */ -#define MMCSD_CMD_GO_IDLE_STATE 0 -#define MMCSD_CMD_INIT 1 -#define MMCSD_CMD_ALL_SEND_CID 2 -#define MMCSD_CMD_SEND_RELATIVE_ADDR 3 -#define MMCSD_CMD_SET_BUS_WIDTH 6 -#define MMCSD_CMD_SEL_DESEL_CARD 7 -#define MMCSD_CMD_SEND_IF_COND 8 -#define MMCSD_CMD_SEND_CSD 9 -#define MMCSD_CMD_SEND_CID 10 -#define MMCSD_CMD_STOP_TRANSMISSION 12 -#define MMCSD_CMD_SEND_STATUS 13 -#define MMCSD_CMD_SET_BLOCKLEN 16 -#define MMCSD_CMD_READ_SINGLE_BLOCK 17 -#define MMCSD_CMD_READ_MULTIPLE_BLOCK 18 -#define MMCSD_CMD_SET_BLOCK_COUNT 23 -#define MMCSD_CMD_WRITE_BLOCK 24 -#define MMCSD_CMD_WRITE_MULTIPLE_BLOCK 25 -#define MMCSD_CMD_ERASE_RW_BLK_START 32 -#define MMCSD_CMD_ERASE_RW_BLK_END 33 -#define MMCSD_CMD_ERASE 38 -#define MMCSD_CMD_APP_OP_COND 41 -#define MMCSD_CMD_LOCK_UNLOCK 42 -#define MMCSD_CMD_APP_CMD 55 -#define MMCSD_CMD_READ_OCR 58 -/** @} */ - -/** - * @name CSD record offsets - */ -/** - * @brief Slice position of values in CSD register. - */ -/* CSD version 2.0 */ -#define MMCSD_CSD_20_CRC_SLICE 7,1 -#define MMCSD_CSD_20_FILE_FORMAT_SLICE 11,10 -#define MMCSD_CSD_20_TMP_WRITE_PROTECT_SLICE 12,12 -#define MMCSD_CSD_20_PERM_WRITE_PROTECT_SLICE 13,13 -#define MMCSD_CSD_20_COPY_SLICE 14,14 -#define MMCSD_CSD_20_FILE_FORMAT_GRP_SLICE 15,15 -#define MMCSD_CSD_20_WRITE_BL_PARTIAL_SLICE 21,21 -#define MMCSD_CSD_20_WRITE_BL_LEN_SLICE 25,12 -#define MMCSD_CSD_20_R2W_FACTOR_SLICE 28,26 -#define MMCSD_CSD_20_WP_GRP_ENABLE_SLICE 31,31 -#define MMCSD_CSD_20_WP_GRP_SIZE_SLICE 38,32 -#define MMCSD_CSD_20_ERASE_SECTOR_SIZE_SLICE 45,39 -#define MMCSD_CSD_20_ERASE_BLK_EN_SLICE 46,46 -#define MMCSD_CSD_20_C_SIZE_SLICE 69,48 -#define MMCSD_CSD_20_DSR_IMP_SLICE 76,76 -#define MMCSD_CSD_20_READ_BLK_MISALIGN_SLICE 77,77 -#define MMCSD_CSD_20_WRITE_BLK_MISALIGN_SLICE 78,78 -#define MMCSD_CSD_20_READ_BL_PARTIAL_SLICE 79,79 -#define MMCSD_CSD_20_READ_BL_LEN_SLICE 83,80 -#define MMCSD_CSD_20_CCC_SLICE 95,84 -#define MMCSD_CSD_20_TRANS_SPEED_SLICE 103,96 -#define MMCSD_CSD_20_NSAC_SLICE 111,104 -#define MMCSD_CSD_20_TAAC_SLICE 119,112 -#define MMCSD_CSD_20_STRUCTURE_SLICE 127,126 - -/* CSD version 1.0 */ -#define MMCSD_CSD_10_CRC_SLICE MMCSD_CSD_20_CRC_SLICE -#define MMCSD_CSD_10_FILE_FORMAT_SLICE MMCSD_CSD_20_FILE_FORMAT_SLICE -#define MMCSD_CSD_10_TMP_WRITE_PROTECT_SLICE MMCSD_CSD_20_TMP_WRITE_PROTECT_SLICE -#define MMCSD_CSD_10_PERM_WRITE_PROTECT_SLICE MMCSD_CSD_20_PERM_WRITE_PROTECT_SLICE -#define MMCSD_CSD_10_COPY_SLICE MMCSD_CSD_20_COPY_SLICE -#define MMCSD_CSD_10_FILE_FORMAT_GRP_SLICE MMCSD_CSD_20_FILE_FORMAT_GRP_SLICE -#define MMCSD_CSD_10_WRITE_BL_PARTIAL_SLICE MMCSD_CSD_20_WRITE_BL_PARTIAL_SLICE -#define MMCSD_CSD_10_WRITE_BL_LEN_SLICE MMCSD_CSD_20_WRITE_BL_LEN_SLICE -#define MMCSD_CSD_10_R2W_FACTOR_SLICE MMCSD_CSD_20_R2W_FACTOR_SLICE -#define MMCSD_CSD_10_WP_GRP_ENABLE_SLICE MMCSD_CSD_20_WP_GRP_ENABLE_SLICE -#define MMCSD_CSD_10_WP_GRP_SIZE_SLICE MMCSD_CSD_20_WP_GRP_SIZE_SLICE -#define MMCSD_CSD_10_ERASE_SECTOR_SIZE_SLICE MMCSD_CSD_20_ERASE_SECTOR_SIZE_SLICE -#define MMCSD_CSD_10_ERASE_BLK_EN_SLICE MMCSD_CSD_20_ERASE_BLK_EN_SLICE -#define MMCSD_CSD_10_C_SIZE_MULT_SLICE 49,47 -#define MMCSD_CSD_10_VDD_W_CURR_MAX_SLICE 52,50 -#define MMCSD_CSD_10_VDD_W_CURR_MIN_SLICE 55,53 -#define MMCSD_CSD_10_VDD_R_CURR_MAX_SLICE 58,56 -#define MMCSD_CSD_10_VDD_R_CURR_MIX_SLICE 61,59 -#define MMCSD_CSD_10_C_SIZE_SLICE 73,62 -#define MMCSD_CSD_10_DSR_IMP_SLICE MMCSD_CSD_20_DSR_IMP_SLICE -#define MMCSD_CSD_10_READ_BLK_MISALIGN_SLICE MMCSD_CSD_20_READ_BLK_MISALIGN_SLICE -#define MMCSD_CSD_10_WRITE_BLK_MISALIGN_SLICE MMCSD_CSD_20_WRITE_BLK_MISALIGN_SLICE -#define MMCSD_CSD_10_READ_BL_PARTIAL_SLICE MMCSD_CSD_20_READ_BL_PARTIAL_SLICE -#define MMCSD_CSD_10_READ_BL_LEN_SLICE 83, 80 -#define MMCSD_CSD_10_CCC_SLICE MMCSD_CSD_20_CCC_SLICE -#define MMCSD_CSD_10_TRANS_SPEED_SLICE MMCSD_CSD_20_TRANS_SPEED_SLICE -#define MMCSD_CSD_10_NSAC_SLICE MMCSD_CSD_20_NSAC_SLICE -#define MMCSD_CSD_10_TAAC_SLICE MMCSD_CSD_20_TAAC_SLICE -#define MMCSD_CSD_10_STRUCTURE_SLICE MMCSD_CSD_20_STRUCTURE_SLICE -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief @p MMCSDBlockDevice specific methods. - */ -#define _mmcsd_block_device_methods \ - _base_block_device_methods - -/** - * @brief @p MMCSDBlockDevice specific data. - * @note It is empty because @p MMCSDBlockDevice is only an interface - * without implementation. - */ -#define _mmcsd_block_device_data \ - _base_block_device_data \ - /* Card CID.*/ \ - uint32_t cid[4]; \ - /* Card CSD.*/ \ - uint32_t csd[4]; \ - /* Total number of blocks in card.*/ \ - uint32_t capacity; - -/** - * @extends BaseBlockDeviceVMT - * - * @brief @p MMCSDBlockDevice virtual methods table. - */ -struct MMCSDBlockDeviceVMT { - _base_block_device_methods -}; - -/** - * @extends BaseBlockDevice - * - * @brief MCC/SD block device class. - * @details This class represents a, block-accessible, MMC/SD device. - */ -typedef struct { - /** @brief Virtual Methods Table.*/ - const struct MMCSDBlockDeviceVMT *vmt; - _mmcsd_block_device_data -} MMCSDBlockDevice; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name R1 response utilities - * @{ - */ -/** - * @brief Evaluates to @p TRUE if the R1 response contains error flags. - * - * @param[in] r1 the r1 response - */ -#define MMCSD_R1_ERROR(r1) (((r1) & MMCSD_R1_ERROR_MASK) != 0) - -/** - * @brief Returns the status field of an R1 response. - * - * @param[in] r1 the r1 response - */ -#define MMCSD_R1_STS(r1) (((r1) >> 9) & 15) - -/** - * @brief Evaluates to @p TRUE if the R1 response indicates a locked card. - * - * @param[in] r1 the r1 response - */ -#define MMCSD_R1_IS_CARD_LOCKED(r1) (((r1) >> 21) & 1) -/** @} */ - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Returns the card capacity in blocks. - * - * @param[in] ip pointer to a @p MMCSDBlockDevice or derived class - * - * @return The card capacity. - * - * @api - */ -#define mmcsdGetCardCapacity(ip) ((ip)->capacity) -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - uint32_t mmcsdGetCapacity(uint32_t csd[4]); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_MMC_SPI || HAL_USE_MMC_SDC*/ - -#endif /* _MMCSD_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/include/pal.h b/firmware/chibios/os/hal/include/pal.h deleted file mode 100644 index db76efc369..0000000000 --- a/firmware/chibios/os/hal/include/pal.h +++ /dev/null @@ -1,562 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file pal.h - * @brief I/O Ports Abstraction Layer macros, types and structures. - * - * @addtogroup PAL - * @{ - */ - -#ifndef _PAL_H_ -#define _PAL_H_ - -#if HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name Pads mode constants - * @{ - */ -/** - * @brief After reset state. - * @details The state itself is not specified and is architecture dependent, - * it is guaranteed to be equal to the after-reset state. It is - * usually an input state. - */ -#define PAL_MODE_RESET 0 - -/** - * @brief Safe state for unconnected pads. - * @details The state itself is not specified and is architecture dependent, - * it may be mapped on @p PAL_MODE_INPUT_PULLUP, - * @p PAL_MODE_INPUT_PULLDOWN or @p PAL_MODE_OUTPUT_PUSHPULL for - * example. - */ -#define PAL_MODE_UNCONNECTED 1 - -/** - * @brief Regular input high-Z pad. - */ -#define PAL_MODE_INPUT 2 - -/** - * @brief Input pad with weak pull up resistor. - */ -#define PAL_MODE_INPUT_PULLUP 3 - -/** - * @brief Input pad with weak pull down resistor. - */ -#define PAL_MODE_INPUT_PULLDOWN 4 - -/** - * @brief Analog input mode. - */ -#define PAL_MODE_INPUT_ANALOG 5 - -/** - * @brief Push-pull output pad. - */ -#define PAL_MODE_OUTPUT_PUSHPULL 6 - -/** - * @brief Open-drain output pad. - */ -#define PAL_MODE_OUTPUT_OPENDRAIN 7 -/** @} */ - -/** - * @name Logic level constants - * @{ - */ -/** - * @brief Logical low state. - */ -#define PAL_LOW 0 - -/** - * @brief Logical high state. - */ -#define PAL_HIGH 1 -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -#include "pal_lld.h" - -/** - * @brief I/O bus descriptor. - * @details This structure describes a group of contiguous digital I/O lines - * that have to be handled as bus. - * @note I/O operations on a bus do not affect I/O lines on the same port but - * not belonging to the bus. - */ -typedef struct { - /** - * @brief Port identifier. - */ - ioportid_t portid; - /** - * @brief Bus mask aligned to port bit 0. - * @note The bus mask implicitly define the bus width. A logical AND is - * performed on the bus data. - */ - ioportmask_t mask; - /** - * @brief Offset, within the port, of the least significant bit of the bus. - */ - uint_fast8_t offset; -} IOBus; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Port bit helper macro. - * @details This macro calculates the mask of a bit within a port. - * - * @param[in] n bit position within the port - * @return The bit mask. - */ -#if !defined(PAL_PORT_BIT) || defined(__DOXYGEN__) -#define PAL_PORT_BIT(n) ((ioportmask_t)(1 << (n))) -#endif - -/** - * @brief Bits group mask helper. - * @details This macro calculates the mask of a bits group. - * - * @param[in] width group width - * @return The group mask. - */ -#if !defined(PAL_GROUP_MASK) || defined(__DOXYGEN__) -#define PAL_GROUP_MASK(width) ((ioportmask_t)(1 << (width)) - 1) -#endif - -/** - * @brief Data part of a static I/O bus initializer. - * @details This macro should be used when statically initializing an I/O bus - * that is part of a bigger structure. - * - * @param[in] name name of the IOBus variable - * @param[in] port I/O port descriptor - * @param[in] width bus width in bits - * @param[in] offset bus bit offset within the port - */ -#define _IOBUS_DATA(name, port, width, offset) \ - {port, PAL_GROUP_MASK(width), offset} - -/** - * @brief Static I/O bus initializer. - * - * @param[in] name name of the IOBus variable - * @param[in] port I/O port descriptor - * @param[in] width bus width in bits - * @param[in] offset bus bit offset within the port - */ -#define IOBUS_DECL(name, port, width, offset) \ - IOBus name = _IOBUS_DATA(name, port, width, offset) - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief PAL subsystem initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @param[in] config pointer to an architecture specific configuration - * structure. This structure is defined in the low level driver - * header. - * - * @init - */ -#define palInit(config) pal_lld_init(config) - -/** - * @brief Reads the physical I/O port states. - * @note The default implementation always return zero and computes the - * parameter eventual side effects. - * @note The function can be called from any context. - * - * @param[in] port port identifier - * @return The port logical states. - * - * @special - */ -#if !defined(pal_lld_readport) || defined(__DOXYGEN__) -#define palReadPort(port) ((void)(port), 0) -#else -#define palReadPort(port) pal_lld_readport(port) -#endif - -/** - * @brief Reads the output latch. - * @details The purpose of this function is to read back the latched output - * value. - * @note The default implementation always return zero and computes the - * parameter eventual side effects. - * @note The function can be called from any context. - * - * @param[in] port port identifier - * @return The latched logical states. - * - * @special - */ -#if !defined(pal_lld_readlatch) || defined(__DOXYGEN__) -#define palReadLatch(port) ((void)(port), 0) -#else -#define palReadLatch(port) pal_lld_readlatch(port) -#endif - -/** - * @brief Writes a bits mask on a I/O port. - * @note The default implementation does nothing except computing the - * parameters eventual side effects. - * @note The function can be called from any context. - * - * @param[in] port port identifier - * @param[in] bits bits to be written on the specified port - * - * @special - */ -#if !defined(pal_lld_writeport) || defined(__DOXYGEN__) -#define palWritePort(port, bits) ((void)(port), (void)(bits)) -#else -#define palWritePort(port, bits) pal_lld_writeport(port, bits) -#endif - -/** - * @brief Sets a bits mask on a I/O port. - * @note The operation is not guaranteed to be atomic on all the - * architectures, for atomicity and/or portability reasons you may - * need to enclose port I/O operations between @p chSysLock() and - * @p chSysUnlock(). - * @note The default implementation is non atomic and not necessarily - * optimal. Low level drivers may optimize the function by using - * specific hardware or coding. - * @note The function can be called from any context. - * - * @param[in] port port identifier - * @param[in] bits bits to be ORed on the specified port - * - * @special - */ -#if !defined(pal_lld_setport) || defined(__DOXYGEN__) -#define palSetPort(port, bits) \ - palWritePort(port, palReadLatch(port) | (bits)) -#else -#define palSetPort(port, bits) pal_lld_setport(port, bits) -#endif - -/** - * @brief Clears a bits mask on a I/O port. - * @note The operation is not guaranteed to be atomic on all the - * architectures, for atomicity and/or portability reasons you may - * need to enclose port I/O operations between @p chSysLock() and - * @p chSysUnlock(). - * @note The default implementation is non atomic and not necessarily - * optimal. Low level drivers may optimize the function by using - * specific hardware or coding. - * @note The function can be called from any context. - * - * @param[in] port port identifier - * @param[in] bits bits to be cleared on the specified port - * - * @special - */ -#if !defined(pal_lld_clearport) || defined(__DOXYGEN__) -#define palClearPort(port, bits) \ - palWritePort(port, palReadLatch(port) & ~(bits)) -#else -#define palClearPort(port, bits) pal_lld_clearport(port, bits) -#endif - -/** - * @brief Toggles a bits mask on a I/O port. - * @note The operation is not guaranteed to be atomic on all the - * architectures, for atomicity and/or portability reasons you may - * need to enclose port I/O operations between @p chSysLock() and - * @p chSysUnlock(). - * @note The default implementation is non atomic and not necessarily - * optimal. Low level drivers may optimize the function by using - * specific hardware or coding. - * @note The function can be called from any context. - * - * @param[in] port port identifier - * @param[in] bits bits to be XORed on the specified port - * - * @special - */ -#if !defined(pal_lld_toggleport) || defined(__DOXYGEN__) -#define palTogglePort(port, bits) \ - palWritePort(port, palReadLatch(port) ^ (bits)) -#else -#define palTogglePort(port, bits) pal_lld_toggleport(port, bits) -#endif - -/** - * @brief Reads a group of bits. - * @note The function can be called from any context. - * - * @param[in] port port identifier - * @param[in] mask group mask, a logical AND is performed on the input - * data - * @param[in] offset group bit offset within the port - * @return The group logical states. - * - * @special - */ -#if !defined(pal_lld_readgroup) || defined(__DOXYGEN__) -#define palReadGroup(port, mask, offset) \ - ((palReadPort(port) >> (offset)) & (mask)) -#else -#define palReadGroup(port, mask, offset) pal_lld_readgroup(port, mask, offset) -#endif - -/** - * @brief Writes a group of bits. - * @note The function can be called from any context. - * - * @param[in] port port identifier - * @param[in] mask group mask, a logical AND is performed on the - * output data - * @param[in] offset group bit offset within the port - * @param[in] bits bits to be written. Values exceeding the group - * width are masked. - * - * @special - */ -#if !defined(pal_lld_writegroup) || defined(__DOXYGEN__) -#define palWriteGroup(port, mask, offset, bits) \ - palWritePort(port, (palReadLatch(port) & ~((mask) << (offset))) | \ - (((bits) & (mask)) << (offset))) -#else -#define palWriteGroup(port, mask, offset, bits) \ - pal_lld_writegroup(port, mask, offset, bits) -#endif - - -/** - * @brief Pads group mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * @note Programming an unknown or unsupported mode is silently ignored. - * @note The function can be called from any context. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] offset group bit offset within the port - * @param[in] mode group mode - * - * @special - */ -#if !defined(pal_lld_setgroupmode) || defined(__DOXYGEN__) -#define palSetGroupMode(port, mask, offset, mode) -#else -#define palSetGroupMode(port, mask, offset, mode) \ - pal_lld_setgroupmode(port, mask, offset, mode) -#endif - -/** - * @brief Reads an input pad logical state. - * @note The default implementation not necessarily optimal. Low level - * drivers may optimize the function by using specific hardware - * or coding. - * @note The default implementation internally uses the @p palReadPort(). - * @note The function can be called from any context. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * @return The logical state. - * @retval PAL_LOW low logical state. - * @retval PAL_HIGH high logical state. - * - * @special - */ -#if !defined(pal_lld_readpad) || defined(__DOXYGEN__) -#define palReadPad(port, pad) ((palReadPort(port) >> (pad)) & 1) -#else -#define palReadPad(port, pad) pal_lld_readpad(port, pad) -#endif - -/** - * @brief Writes a logical state on an output pad. - * @note The operation is not guaranteed to be atomic on all the - * architectures, for atomicity and/or portability reasons you may - * need to enclose port I/O operations between @p chSysLock() and - * @p chSysUnlock(). - * @note The default implementation is non atomic and not necessarily - * optimal. Low level drivers may optimize the function by using - * specific hardware or coding. - * @note The default implementation internally uses the @p palReadLatch() - * and @p palWritePort(). - * @note The function can be called from any context. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * @param[in] bit logical value, the value must be @p PAL_LOW or - * @p PAL_HIGH - * - * @special - */ -#if !defined(pal_lld_writepad) || defined(__DOXYGEN__) -#define palWritePad(port, pad, bit) \ - palWritePort(port, (palReadLatch(port) & ~PAL_PORT_BIT(pad)) | \ - (((bit) & 1) << pad)) -#else -#define palWritePad(port, pad, bit) pal_lld_writepad(port, pad, bit) -#endif - -/** - * @brief Sets a pad logical state to @p PAL_HIGH. - * @note The operation is not guaranteed to be atomic on all the - * architectures, for atomicity and/or portability reasons you may - * need to enclose port I/O operations between @p chSysLock() and - * @p chSysUnlock(). - * @note The default implementation is non atomic and not necessarily - * optimal. Low level drivers may optimize the function by using - * specific hardware or coding. - * @note The default implementation internally uses the @p palSetPort(). - * @note The function can be called from any context. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * - * @special - */ -#if !defined(pal_lld_setpad) || defined(__DOXYGEN__) -#define palSetPad(port, pad) palSetPort(port, PAL_PORT_BIT(pad)) -#else -#define palSetPad(port, pad) pal_lld_setpad(port, pad) -#endif - -/** - * @brief Clears a pad logical state to @p PAL_LOW. - * @note The operation is not guaranteed to be atomic on all the - * architectures, for atomicity and/or portability reasons you may - * need to enclose port I/O operations between @p chSysLock() and - * @p chSysUnlock(). - * @note The default implementation is non atomic and not necessarily - * optimal. Low level drivers may optimize the function by using - * specific hardware or coding. - * @note The default implementation internally uses the @p palClearPort(). - * @note The function can be called from any context. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * - * @special - */ -#if !defined(pal_lld_clearpad) || defined(__DOXYGEN__) -#define palClearPad(port, pad) palClearPort(port, PAL_PORT_BIT(pad)) -#else -#define palClearPad(port, pad) pal_lld_clearpad(port, pad) -#endif - -/** - * @brief Toggles a pad logical state. - * @note The operation is not guaranteed to be atomic on all the - * architectures, for atomicity and/or portability reasons you may - * need to enclose port I/O operations between @p chSysLock() and - * @p chSysUnlock(). - * @note The default implementation is non atomic and not necessarily - * optimal. Low level drivers may optimize the function by using - * specific hardware or coding. - * @note The default implementation internally uses the @p palTogglePort(). - * @note The function can be called from any context. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * - * @special - */ -#if !defined(pal_lld_togglepad) || defined(__DOXYGEN__) -#define palTogglePad(port, pad) palTogglePort(port, PAL_PORT_BIT(pad)) -#else -#define palTogglePad(port, pad) pal_lld_togglepad(port, pad) -#endif - -/** - * @brief Pad mode setup. - * @details This function programs a pad with the specified mode. - * @note The default implementation not necessarily optimal. Low level - * drivers may optimize the function by using specific hardware - * or coding. - * @note Programming an unknown or unsupported mode is silently ignored. - * @note The function can be called from any context. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * @param[in] mode pad mode - * - * @special - */ -#if !defined(pal_lld_setpadmode) || defined(__DOXYGEN__) -#define palSetPadMode(port, pad, mode) \ - palSetGroupMode(port, PAL_PORT_BIT(pad), 0, mode) -#else -#define palSetPadMode(port, pad, mode) pal_lld_setpadmode(port, pad, mode) -#endif -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - ioportmask_t palReadBus(IOBus *bus); - void palWriteBus(IOBus *bus, ioportmask_t bits); - void palSetBusMode(IOBus *bus, iomode_t mode); -#ifdef __cplusplus -} -#endif - -#endif /* _PAL_H_ */ - -#endif /* HAL_USE_PAL */ - -/** @} */ diff --git a/firmware/chibios/os/hal/include/pwm.h b/firmware/chibios/os/hal/include/pwm.h deleted file mode 100644 index 9149944e7c..0000000000 --- a/firmware/chibios/os/hal/include/pwm.h +++ /dev/null @@ -1,259 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file pwm.h - * @brief PWM Driver macros and structures. - * - * @addtogroup PWM - * @{ - */ - -#ifndef _PWM_H_ -#define _PWM_H_ - -#if HAL_USE_PWM || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name PWM output mode macros - * @{ - */ -/** - * @brief Standard output modes mask. - */ -#define PWM_OUTPUT_MASK 0x0F - -/** - * @brief Output not driven, callback only. - */ -#define PWM_OUTPUT_DISABLED 0x00 - -/** - * @brief Positive PWM logic, active is logic level one. - */ -#define PWM_OUTPUT_ACTIVE_HIGH 0x01 - -/** - * @brief Inverse PWM logic, active is logic level zero. - */ -#define PWM_OUTPUT_ACTIVE_LOW 0x02 -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - PWM_UNINIT = 0, /**< Not initialized. */ - PWM_STOP = 1, /**< Stopped. */ - PWM_READY = 2, /**< Ready. */ -} pwmstate_t; - -/** - * @brief Type of a structure representing a PWM driver. - */ -typedef struct PWMDriver PWMDriver; - -/** - * @brief PWM notification callback type. - * - * @param[in] pwmp pointer to a @p PWMDriver object - */ -typedef void (*pwmcallback_t)(PWMDriver *pwmp); - -#include "pwm_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name PWM duty cycle conversion - * @{ - */ -/** - * @brief Converts from fraction to pulse width. - * @note Be careful with rounding errors, this is integer math not magic. - * You can specify tenths of thousandth but make sure you have the - * proper hardware resolution by carefully choosing the clock source - * and prescaler settings, see @p PWM_COMPUTE_PSC. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] denominator denominator of the fraction - * @param[in] numerator numerator of the fraction - * @return The pulse width to be passed to @p pwmEnableChannel(). - * - * @api - */ -#define PWM_FRACTION_TO_WIDTH(pwmp, denominator, numerator) \ - ((pwmcnt_t)((((pwmcnt_t)(pwmp)->period) * \ - (pwmcnt_t)(numerator)) / (pwmcnt_t)(denominator))) - -/** - * @brief Converts from degrees to pulse width. - * @note Be careful with rounding errors, this is integer math not magic. - * You can specify hundredths of degrees but make sure you have the - * proper hardware resolution by carefully choosing the clock source - * and prescaler settings, see @p PWM_COMPUTE_PSC. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] degrees degrees as an integer between 0 and 36000 - * @return The pulse width to be passed to @p pwmEnableChannel(). - * - * @api - */ -#define PWM_DEGREES_TO_WIDTH(pwmp, degrees) \ - PWM_FRACTION_TO_WIDTH(pwmp, 36000, degrees) - -/** - * @brief Converts from percentage to pulse width. - * @note Be careful with rounding errors, this is integer math not magic. - * You can specify tenths of thousandth but make sure you have the - * proper hardware resolution by carefully choosing the clock source - * and prescaler settings, see @p PWM_COMPUTE_PSC. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] percentage percentage as an integer between 0 and 10000 - * @return The pulse width to be passed to @p pwmEnableChannel(). - * - * @api - */ -#define PWM_PERCENTAGE_TO_WIDTH(pwmp, percentage) \ - PWM_FRACTION_TO_WIDTH(pwmp, 10000, percentage) -/** @} */ - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Changes the period the PWM peripheral. - * @details This function changes the period of a PWM unit that has already - * been activated using @p pwmStart(). - * @pre The PWM unit must have been activated using @p pwmStart(). - * @post The PWM unit period is changed to the new value. - * @note If a period is specified that is shorter than the pulse width - * programmed in one of the channels then the behavior is not - * guaranteed. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] value new cycle time in ticks - * - * @iclass - */ -#define pwmChangePeriodI(pwmp, value) { \ - (pwmp)->period = (value); \ - pwm_lld_change_period(pwmp, value); \ -} - -/** - * @brief Enables a PWM channel. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @post The channel is active using the specified configuration. - * @note Depending on the hardware implementation this function has - * effect starting on the next cycle (recommended implementation) - * or immediately (fallback implementation). - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) - * @param[in] width PWM pulse width as clock pulses number - * - * @iclass - */ -#define pwmEnableChannelI(pwmp, channel, width) \ - pwm_lld_enable_channel(pwmp, channel, width) - -/** - * @brief Disables a PWM channel. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @post The channel is disabled and its output line returned to the - * idle state. - * @note Depending on the hardware implementation this function has - * effect starting on the next cycle (recommended implementation) - * or immediately (fallback implementation). - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) - * - * @iclass - */ -#define pwmDisableChannelI(pwmp, channel) \ - pwm_lld_disable_channel(pwmp, channel) - -/** - * @brief Returns a PWM channel status. - * @pre The PWM unit must have been activated using @p pwmStart(). - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) - * - * @iclass - */ -#define pwmIsChannelEnabledI(pwmp, channel) \ - pwm_lld_is_channel_enabled(pwmp, channel) -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void pwmInit(void); - void pwmObjectInit(PWMDriver *pwmp); - void pwmStart(PWMDriver *pwmp, const PWMConfig *config); - void pwmStop(PWMDriver *pwmp); - void pwmChangePeriod(PWMDriver *pwmp, pwmcnt_t period); - void pwmEnableChannel(PWMDriver *pwmp, - pwmchannel_t channel, - pwmcnt_t width); - void pwmDisableChannel(PWMDriver *pwmp, pwmchannel_t channel); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_PWM */ - -#endif /* _PWM_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/include/rtc.h b/firmware/chibios/os/hal/include/rtc.h deleted file mode 100644 index 7fb53fd581..0000000000 --- a/firmware/chibios/os/hal/include/rtc.h +++ /dev/null @@ -1,178 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ -/* - Concepts and parts of this file have been contributed by Uladzimir Pylinsky - aka barthess. - */ - -/** - * @file rtc.h - * @brief RTC Driver macros and structures. - * - * @addtogroup RTC - * @{ - */ - -#ifndef _RTC_H_ -#define _RTC_H_ - -#if HAL_USE_RTC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name Date/Time bit masks - * @{ - */ -#define RTC_TIME_SECONDS_MASK 0x0000001F /* @brief Seconds mask. */ -#define RTC_TIME_MINUTES_MASK 0x000007E0 /* @brief Minutes mask. */ -#define RTC_TIME_HOURS_MASK 0x0000F800 /* @brief Hours mask. */ -#define RTC_DATE_DAYS_MASK 0x001F0000 /* @brief Days mask. */ -#define RTC_DATE_MONTHS_MASK 0x01E00000 /* @brief Months mask. */ -#define RTC_DATE_YEARS_MASK 0xFE000000 /* @brief Years mask. */ -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a structure representing an RTC driver. - */ -typedef struct RTCDriver RTCDriver; - -/** - * @brief Type of a structure representing an RTC time stamp. - */ -typedef struct RTCTime RTCTime; - -#include "rtc_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Set current time. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[in] timespec pointer to a @p RTCTime structure - * - * @iclass - */ -#define rtcSetTimeI(rtcp, timespec) rtc_lld_set_time(rtcp, timespec) - -/** - * @brief Get current time. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[out] timespec pointer to a @p RTCTime structure - * - * @iclass - */ -#define rtcGetTimeI(rtcp, timespec) rtc_lld_get_time(rtcp, timespec) - -#if (RTC_ALARMS > 0) || defined(__DOXYGEN__) -/** - * @brief Set alarm time. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[in] alarm alarm identifier - * @param[in] alarmspec pointer to a @p RTCAlarm structure or @p NULL - * - * @iclass - */ -#define rtcSetAlarmI(rtcp, alarm, alarmspec) \ - rtc_lld_set_alarm(rtcp, alarm, alarmspec) - -/** - * @brief Get current alarm. - * @note If an alarm has not been set then the returned alarm specification - * is not meaningful. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[in] alarm alarm identifier - * @param[out] alarmspec pointer to a @p RTCAlarm structure - * - * @iclass - */ -#define rtcGetAlarmI(rtcp, alarm, alarmspec) \ - rtc_lld_get_alarm(rtcp, alarm, alarmspec) -#endif /* RTC_ALARMS > 0 */ - -#if RTC_SUPPORTS_CALLBACKS || defined(__DOXYGEN__) -/** - * @brief Enables or disables RTC callbacks. - * @details This function enables or disables the callback, use a @p NULL - * pointer in order to disable it. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[in] callback callback function pointer or @p NULL - * - * @iclass - */ -#define rtcSetCallbackI(rtcp, callback) rtc_lld_set_callback(rtcp, callback) -#endif /* RTC_SUPPORTS_CALLBACKS */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void rtcInit(void); - void rtcSetTime(RTCDriver *rtcp, const RTCTime *timespec); - void rtcGetTime(RTCDriver *rtcp, RTCTime *timespec); -#if RTC_ALARMS > 0 - void rtcSetAlarm(RTCDriver *rtcp, - rtcalarm_t alarm, - const RTCAlarm *alarmspec); - void rtcGetAlarm(RTCDriver *rtcp, rtcalarm_t alarm, RTCAlarm *alarmspec); -#endif - uint32_t rtcGetTimeFat(RTCDriver *rtcp); -#if RTC_SUPPORTS_CALLBACKS - void rtcSetCallback(RTCDriver *rtcp, rtccb_t callback); -#endif -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_RTC */ -#endif /* _RTC_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/include/sdc.h b/firmware/chibios/os/hal/include/sdc.h deleted file mode 100644 index 1b74769a89..0000000000 --- a/firmware/chibios/os/hal/include/sdc.h +++ /dev/null @@ -1,189 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file sdc.h - * @brief SDC Driver macros and structures. - * - * @addtogroup SDC - * @{ - */ - -#ifndef _SDC_H_ -#define _SDC_H_ - -#if HAL_USE_SDC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name SD cart types - * @{ - */ -#define SDC_MODE_CARDTYPE_MASK 0xF /**< @brief Card type mask. */ -#define SDC_MODE_CARDTYPE_SDV11 0 /**< @brief Card is SD V1.1.*/ -#define SDC_MODE_CARDTYPE_SDV20 1 /**< @brief Card is SD V2.0.*/ -#define SDC_MODE_CARDTYPE_MMC 2 /**< @brief Card is MMC. */ -#define SDC_MODE_HIGH_CAPACITY 0x10 /**< @brief High cap.card. */ -/** @} */ - -/** - * @name SDC bus error conditions - * @{ - */ -#define SDC_NO_ERROR 0 /**< @brief No error. */ -#define SDC_CMD_CRC_ERROR 1 /**< @brief Command CRC error. */ -#define SDC_DATA_CRC_ERROR 2 /**< @brief Data CRC error. */ -#define SDC_DATA_TIMEOUT 4 /**< @brief HW write timeout. */ -#define SDC_COMMAND_TIMEOUT 8 /**< @brief HW read timeout. */ -#define SDC_TX_UNDERRUN 16 /**< @brief TX buffer underrun. */ -#define SDC_RX_OVERRUN 32 /**< @brief RX buffer overrun. */ -#define SDC_STARTBIT_ERROR 64 /**< @brief Start bit missing. */ -#define SDC_OVERFLOW_ERROR 128 /**< @brief Card overflow error. */ -#define SDC_UNHANDLED_ERROR 0xFFFFFFFF -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name SDC configuration options - * @{ - */ -/** - * @brief Number of initialization attempts before rejecting the card. - * @note Attempts are performed at 10mS intervals. - */ -#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) -#define SDC_INIT_RETRY 100 -#endif - -/** - * @brief Include support for MMC cards. - * @note MMC support is not yet implemented so this option must be kept - * at @p FALSE. - */ -#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) -#define SDC_MMC_SUPPORT FALSE -#endif - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - */ -#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) -#define SDC_NICE_WAITING TRUE -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -#include "sdc_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Returns the card insertion status. - * @note This macro wraps a low level function named - * @p sdc_lld_is_card_inserted(), this function must be - * provided by the application because it is not part of the - * SDC driver. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @return The card state. - * @retval FALSE card not inserted. - * @retval TRUE card inserted. - * - * @api - */ -#define sdcIsCardInserted(sdcp) (sdc_lld_is_card_inserted(sdcp)) - -/** - * @brief Returns the write protect status. - * @note This macro wraps a low level function named - * @p sdc_lld_is_write_protected(), this function must be - * provided by the application because it is not part of the - * SDC driver. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @return The card state. - * @retval FALSE not write protected. - * @retval TRUE write protected. - * - * @api - */ -#define sdcIsWriteProtected(sdcp) (sdc_lld_is_write_protected(sdcp)) -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void sdcInit(void); - void sdcObjectInit(SDCDriver *sdcp); - void sdcStart(SDCDriver *sdcp, const SDCConfig *config); - void sdcStop(SDCDriver *sdcp); - bool_t sdcConnect(SDCDriver *sdcp); - bool_t sdcDisconnect(SDCDriver *sdcp); - bool_t sdcRead(SDCDriver *sdcp, uint32_t startblk, - uint8_t *buffer, uint32_t n); - bool_t sdcWrite(SDCDriver *sdcp, uint32_t startblk, - const uint8_t *buffer, uint32_t n); - sdcflags_t sdcGetAndClearErrors(SDCDriver *sdcp); - bool_t sdcSync(SDCDriver *sdcp); - bool_t sdcGetInfo(SDCDriver *sdcp, BlockDeviceInfo *bdip); - bool_t sdcErase(SDCDriver *mmcp, uint32_t startblk, uint32_t endblk); - bool_t _sdc_wait_for_transfer_state(SDCDriver *sdcp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_SDC */ - -#endif /* _SDC_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/include/serial.h b/firmware/chibios/os/hal/include/serial.h deleted file mode 100644 index 396be5b3c5..0000000000 --- a/firmware/chibios/os/hal/include/serial.h +++ /dev/null @@ -1,323 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file serial.h - * @brief Serial Driver macros and structures. - * - * @addtogroup SERIAL - * @{ - */ - -#ifndef _SERIAL_H_ -#define _SERIAL_H_ - -#if HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name Serial status flags - * @{ - */ -#define SD_PARITY_ERROR 32 /**< @brief Parity error happened. */ -#define SD_FRAMING_ERROR 64 /**< @brief Framing error happened. */ -#define SD_OVERRUN_ERROR 128 /**< @brief Overflow happened. */ -#define SD_NOISE_ERROR 256 /**< @brief Noise on the line. */ -#define SD_BREAK_DETECTED 512 /**< @brief Break detected. */ -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Serial configuration options - * @{ - */ -/** - * @brief Default bit rate. - * @details Configuration parameter, this is the baud rate selected for the - * default configuration. - */ -#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SERIAL_DEFAULT_BITRATE 38400 -#endif - -/** - * @brief Serial buffers size. - * @details Configuration parameter, you can change the depth of the queue - * buffers depending on the requirements of your application. - * @note The default is 16 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_BUFFERS_SIZE 16 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !CH_USE_QUEUES && !CH_USE_EVENTS -#error "Serial Driver requires CH_USE_QUEUES and CH_USE_EVENTS" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - SD_UNINIT = 0, /**< Not initialized. */ - SD_STOP = 1, /**< Stopped. */ - SD_READY = 2 /**< Ready. */ -} sdstate_t; - -/** - * @brief Structure representing a serial driver. - */ -typedef struct SerialDriver SerialDriver; - -#include "serial_lld.h" - -/** - * @brief @p SerialDriver specific methods. - */ -#define _serial_driver_methods \ - _base_asynchronous_channel_methods - -/** - * @extends BaseAsynchronousChannelVMT - * - * @brief @p SerialDriver virtual methods table. - */ -struct SerialDriverVMT { - _serial_driver_methods -}; - -/** - * @extends BaseAsynchronousChannel - * - * @brief Full duplex serial driver class. - * @details This class extends @p BaseAsynchronousChannel by adding physical - * I/O queues. - */ -struct SerialDriver { - /** @brief Virtual Methods Table.*/ - const struct SerialDriverVMT *vmt; - _serial_driver_data -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Direct output check on a @p SerialDriver. - * @note This function bypasses the indirect access to the channel and - * checks directly the output queue. This is faster but cannot - * be used to check different channels implementations. - * - * @deprecated - * - * @api - */ -#define sdPutWouldBlock(sdp) chOQIsFullI(&(sdp)->oqueue) - -/** - * @brief Direct input check on a @p SerialDriver. - * @note This function bypasses the indirect access to the channel and - * checks directly the input queue. This is faster but cannot - * be used to check different channels implementations. - * - * @deprecated - * - * @api - */ -#define sdGetWouldBlock(sdp) chIQIsEmptyI(&(sdp)->iqueue) - -/** - * @brief Direct write to a @p SerialDriver. - * @note This function bypasses the indirect access to the channel and - * writes directly on the output queue. This is faster but cannot - * be used to write to different channels implementations. - * - * @see chnPutTimeout() - * - * @api - */ -#define sdPut(sdp, b) chOQPut(&(sdp)->oqueue, b) - -/** - * @brief Direct write to a @p SerialDriver with timeout specification. - * @note This function bypasses the indirect access to the channel and - * writes directly on the output queue. This is faster but cannot - * be used to write to different channels implementations. - * - * @see chnPutTimeout() - * - * @api - */ -#define sdPutTimeout(sdp, b, t) chOQPutTimeout(&(sdp)->oqueue, b, t) - -/** - * @brief Direct read from a @p SerialDriver. - * @note This function bypasses the indirect access to the channel and - * reads directly from the input queue. This is faster but cannot - * be used to read from different channels implementations. - * - * @see chnGetTimeout() - * - * @api - */ -#define sdGet(sdp) chIQGet(&(sdp)->iqueue) - -/** - * @brief Direct read from a @p SerialDriver with timeout specification. - * @note This function bypasses the indirect access to the channel and - * reads directly from the input queue. This is faster but cannot - * be used to read from different channels implementations. - * - * @see chnGetTimeout() - * - * @api - */ -#define sdGetTimeout(sdp, t) chIQGetTimeout(&(sdp)->iqueue, t) - -/** - * @brief Direct blocking write to a @p SerialDriver. - * @note This function bypasses the indirect access to the channel and - * writes directly to the output queue. This is faster but cannot - * be used to write from different channels implementations. - * - * @see chnWrite() - * - * @api - */ -#define sdWrite(sdp, b, n) \ - chOQWriteTimeout(&(sdp)->oqueue, b, n, TIME_INFINITE) - -/** - * @brief Direct blocking write to a @p SerialDriver with timeout - * specification. - * @note This function bypasses the indirect access to the channel and - * writes directly to the output queue. This is faster but cannot - * be used to write to different channels implementations. - * - * @see chnWriteTimeout() - * - * @api - */ -#define sdWriteTimeout(sdp, b, n, t) \ - chOQWriteTimeout(&(sdp)->oqueue, b, n, t) - -/** - * @brief Direct non-blocking write to a @p SerialDriver. - * @note This function bypasses the indirect access to the channel and - * writes directly to the output queue. This is faster but cannot - * be used to write to different channels implementations. - * - * @see chnWriteTimeout() - * - * @api - */ -#define sdAsynchronousWrite(sdp, b, n) \ - chOQWriteTimeout(&(sdp)->oqueue, b, n, TIME_IMMEDIATE) - -/** - * @brief Direct blocking read from a @p SerialDriver. - * @note This function bypasses the indirect access to the channel and - * reads directly from the input queue. This is faster but cannot - * be used to read from different channels implementations. - * - * @see chnRead() - * - * @api - */ -#define sdRead(sdp, b, n) \ - chIQReadTimeout(&(sdp)->iqueue, b, n, TIME_INFINITE) - -/** - * @brief Direct blocking read from a @p SerialDriver with timeout - * specification. - * @note This function bypasses the indirect access to the channel and - * reads directly from the input queue. This is faster but cannot - * be used to read from different channels implementations. - * - * @see chnReadTimeout() - * - * @api - */ -#define sdReadTimeout(sdp, b, n, t) \ - chIQReadTimeout(&(sdp)->iqueue, b, n, t) - -/** - * @brief Direct non-blocking read from a @p SerialDriver. - * @note This function bypasses the indirect access to the channel and - * reads directly from the input queue. This is faster but cannot - * be used to read from different channels implementations. - * - * @see chnReadTimeout() - * - * @api - */ -#define sdAsynchronousRead(sdp, b, n) \ - chIQReadTimeout(&(sdp)->iqueue, b, n, TIME_IMMEDIATE) -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void sdInit(void); - void sdObjectInit(SerialDriver *sdp, qnotify_t inotify, qnotify_t onotify); - void sdStart(SerialDriver *sdp, const SerialConfig *config); - void sdStop(SerialDriver *sdp); - void sdIncomingDataI(SerialDriver *sdp, uint8_t b); - msg_t sdRequestDataI(SerialDriver *sdp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_SERIAL */ - -#endif /* _SERIAL_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/include/serial_usb.h b/firmware/chibios/os/hal/include/serial_usb.h deleted file mode 100644 index c031a9d9b1..0000000000 --- a/firmware/chibios/os/hal/include/serial_usb.h +++ /dev/null @@ -1,241 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file serial_usb.h - * @brief Serial over USB Driver macros and structures. - * - * @addtogroup SERIAL_USB - * @{ - */ - -#ifndef _SERIAL_USB_H_ -#define _SERIAL_USB_H_ - -#if HAL_USE_SERIAL_USB || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name CDC specific messages. - * @{ - */ -#define CDC_SEND_ENCAPSULATED_COMMAND 0x00 -#define CDC_GET_ENCAPSULATED_RESPONSE 0x01 -#define CDC_SET_COMM_FEATURE 0x02 -#define CDC_GET_COMM_FEATURE 0x03 -#define CDC_CLEAR_COMM_FEATURE 0x04 -#define CDC_SET_AUX_LINE_STATE 0x10 -#define CDC_SET_HOOK_STATE 0x11 -#define CDC_PULSE_SETUP 0x12 -#define CDC_SEND_PULSE 0x13 -#define CDC_SET_PULSE_TIME 0x14 -#define CDC_RING_AUX_JACK 0x15 -#define CDC_SET_LINE_CODING 0x20 -#define CDC_GET_LINE_CODING 0x21 -#define CDC_SET_CONTROL_LINE_STATE 0x22 -#define CDC_SEND_BREAK 0x23 -#define CDC_SET_RINGER_PARMS 0x30 -#define CDC_GET_RINGER_PARMS 0x31 -#define CDC_SET_OPERATION_PARMS 0x32 -#define CDC_GET_OPERATION_PARMS 0x33 -/** @} */ - -/** - * @name Line Control bit definitions. - * @{ - */ -#define LC_STOP_1 0 -#define LC_STOP_1P5 1 -#define LC_STOP_2 2 - -#define LC_PARITY_NONE 0 -#define LC_PARITY_ODD 1 -#define LC_PARITY_EVEN 2 -#define LC_PARITY_MARK 3 -#define LC_PARITY_SPACE 4 -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name SERIAL_USB configuration options - * @{ - */ -/** - * @brief Serial over USB buffers size. - * @details Configuration parameter, the buffer size must be a multiple of - * the USB data endpoint maximum packet size. - * @note The default is 256 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_SIZE 256 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !HAL_USE_USB || !CH_USE_QUEUES || !CH_USE_EVENTS -#error "Serial over USB Driver requires HAL_USE_USB, CH_USE_QUEUES, " - "CH_USE_EVENTS" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of Line Coding structure. - */ -typedef struct { - uint8_t dwDTERate[4]; - uint8_t bCharFormat; - uint8_t bParityType; - uint8_t bDataBits; -} cdc_linecoding_t; - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - SDU_UNINIT = 0, /**< Not initialized. */ - SDU_STOP = 1, /**< Stopped. */ - SDU_READY = 2 /**< Ready. */ -} sdustate_t; - -/** - * @brief Structure representing a serial over USB driver. - */ -typedef struct SerialUSBDriver SerialUSBDriver; - -/** - * @brief Serial over USB Driver configuration structure. - * @details An instance of this structure must be passed to @p sduStart() - * in order to configure and start the driver operations. - */ -typedef struct { - /** - * @brief USB driver to use. - */ - USBDriver *usbp; - /** - * @brief Bulk IN endpoint used for outgoing data transfer. - */ - usbep_t bulk_in; - /** - * @brief Bulk OUT endpoint used for incoming data transfer. - */ - usbep_t bulk_out; - /** - * @brief Interrupt IN endpoint used for notifications. - */ - usbep_t int_in; -} SerialUSBConfig; - -/** - * @brief @p SerialDriver specific data. - */ -#define _serial_usb_driver_data \ - _base_asynchronous_channel_data \ - /* Driver state.*/ \ - sdustate_t state; \ - /* Input queue.*/ \ - InputQueue iqueue; \ - /* Output queue.*/ \ - OutputQueue oqueue; \ - /* Input buffer.*/ \ - uint8_t ib[SERIAL_USB_BUFFERS_SIZE]; \ - /* Output buffer.*/ \ - uint8_t ob[SERIAL_USB_BUFFERS_SIZE]; \ - /* End of the mandatory fields.*/ \ - /* Current configuration data.*/ \ - const SerialUSBConfig *config; - -/** - * @brief @p SerialUSBDriver specific methods. - */ -#define _serial_usb_driver_methods \ - _base_asynchronous_channel_methods - -/** - * @extends BaseAsynchronousChannelVMT - * - * @brief @p SerialDriver virtual methods table. - */ -struct SerialUSBDriverVMT { - _serial_usb_driver_methods -}; - -/** - * @extends BaseAsynchronousChannel - * - * @brief Full duplex serial driver class. - * @details This class extends @p BaseAsynchronousChannel by adding physical - * I/O queues. - */ -struct SerialUSBDriver { - /** @brief Virtual Methods Table.*/ - const struct SerialUSBDriverVMT *vmt; - _serial_usb_driver_data -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void sduInit(void); - void sduObjectInit(SerialUSBDriver *sdp); - void sduStart(SerialUSBDriver *sdup, const SerialUSBConfig *config); - void sduStop(SerialUSBDriver *sdup); - void sduConfigureHookI(SerialUSBDriver *sdup); - bool_t sduRequestsHook(USBDriver *usbp); - void sduDataTransmitted(USBDriver *usbp, usbep_t ep); - void sduDataReceived(USBDriver *usbp, usbep_t ep); - void sduInterruptTransmitted(USBDriver *usbp, usbep_t ep); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_SERIAL_USB */ - -#endif /* _SERIAL_USB_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/include/spi.h b/firmware/chibios/os/hal/include/spi.h deleted file mode 100644 index 9b60b2b7a3..0000000000 --- a/firmware/chibios/os/hal/include/spi.h +++ /dev/null @@ -1,331 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file spi.h - * @brief SPI Driver macros and structures. - * - * @addtogroup SPI - * @{ - */ - -#ifndef _SPI_H_ -#define _SPI_H_ - -#if HAL_USE_SPI || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name SPI configuration options - * @{ - */ -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) -#define SPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define SPI_USE_MUTUAL_EXCLUSION TRUE -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if SPI_USE_MUTUAL_EXCLUSION && !CH_USE_MUTEXES && !CH_USE_SEMAPHORES -#error "SPI_USE_MUTUAL_EXCLUSION requires CH_USE_MUTEXES and/or CH_USE_SEMAPHORES" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - SPI_UNINIT = 0, /**< Not initialized. */ - SPI_STOP = 1, /**< Stopped. */ - SPI_READY = 2, /**< Ready. */ - SPI_ACTIVE = 3, /**< Exchanging data. */ - SPI_COMPLETE = 4 /**< Asynchronous operation complete. */ -} spistate_t; - -#include "spi_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Asserts the slave select signal and prepares for transfers. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @iclass - */ -#define spiSelectI(spip) { \ - spi_lld_select(spip); \ -} - -/** - * @brief Deasserts the slave select signal. - * @details The previously selected peripheral is unselected. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @iclass - */ -#define spiUnselectI(spip) { \ - spi_lld_unselect(spip); \ -} - -/** - * @brief Ignores data on the SPI bus. - * @details This asynchronous function starts the transmission of a series of - * idle words on the SPI bus and ignores the received data. - * @pre A slave must have been selected using @p spiSelect() or - * @p spiSelectI(). - * @post At the end of the operation the configured callback is invoked. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be ignored - * - * @iclass - */ -#define spiStartIgnoreI(spip, n) { \ - (spip)->state = SPI_ACTIVE; \ - spi_lld_ignore(spip, n); \ -} - -/** - * @brief Exchanges data on the SPI bus. - * @details This asynchronous function starts a simultaneous transmit/receive - * operation. - * @pre A slave must have been selected using @p spiSelect() or - * @p spiSelectI(). - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be exchanged - * @param[in] txbuf the pointer to the transmit buffer - * @param[out] rxbuf the pointer to the receive buffer - * - * @iclass - */ -#define spiStartExchangeI(spip, n, txbuf, rxbuf) { \ - (spip)->state = SPI_ACTIVE; \ - spi_lld_exchange(spip, n, txbuf, rxbuf); \ -} - -/** - * @brief Sends data over the SPI bus. - * @details This asynchronous function starts a transmit operation. - * @pre A slave must have been selected using @p spiSelect() or - * @p spiSelectI(). - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to send - * @param[in] txbuf the pointer to the transmit buffer - * - * @iclass - */ -#define spiStartSendI(spip, n, txbuf) { \ - (spip)->state = SPI_ACTIVE; \ - spi_lld_send(spip, n, txbuf); \ -} - -/** - * @brief Receives data from the SPI bus. - * @details This asynchronous function starts a receive operation. - * @pre A slave must have been selected using @p spiSelect() or - * @p spiSelectI(). - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to receive - * @param[out] rxbuf the pointer to the receive buffer - * - * @iclass - */ -#define spiStartReceiveI(spip, n, rxbuf) { \ - (spip)->state = SPI_ACTIVE; \ - spi_lld_receive(spip, n, rxbuf); \ -} - -/** - * @brief Exchanges one frame using a polled wait. - * @details This synchronous function exchanges one frame using a polled - * synchronization method. This function is useful when exchanging - * small amount of data on high speed channels, usually in this - * situation is much more efficient just wait for completion using - * polling than suspending the thread waiting for an interrupt. - * @note This API is implemented as a macro in order to minimize latency. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] frame the data frame to send over the SPI bus - * @return The received data frame from the SPI bus. - */ -#define spiPolledExchange(spip, frame) spi_lld_polled_exchange(spip, frame) -/** @} */ - -/** - * @name Low Level driver helper macros - * @{ - */ -#if SPI_USE_WAIT || defined(__DOXYGEN__) -/** - * @brief Waits for operation completion. - * @details This function waits for the driver to complete the current - * operation. - * @pre An operation must be running while the function is invoked. - * @note No more than one thread can wait on a SPI driver using - * this function. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -#define _spi_wait_s(spip) { \ - chDbgAssert((spip)->thread == NULL, \ - "_spi_wait(), #1", "already waiting"); \ - (spip)->thread = chThdSelf(); \ - chSchGoSleepS(THD_STATE_SUSPENDED); \ -} - -/** - * @brief Wakes up the waiting thread. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -#define _spi_wakeup_isr(spip) { \ - chSysLockFromIsr(); \ - if ((spip)->thread != NULL) { \ - Thread *tp = (spip)->thread; \ - (spip)->thread = NULL; \ - tp->p_u.rdymsg = RDY_OK; \ - chSchReadyI(tp); \ - } \ - chSysUnlockFromIsr(); \ -} -#else /* !SPI_USE_WAIT */ -#define _spi_wait_s(spip) -#define _spi_wakeup_isr(spip) -#endif /* !SPI_USE_WAIT */ - -/** - * @brief Common ISR code. - * @details This code handles the portable part of the ISR code: - * - Callback invocation. - * - Waiting thread wakeup, if any. - * - Driver state transitions. - * . - * @note This macro is meant to be used in the low level drivers - * implementation only. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -#define _spi_isr_code(spip) { \ - if ((spip)->config->end_cb) { \ - (spip)->state = SPI_COMPLETE; \ - (spip)->config->end_cb(spip); \ - if ((spip)->state == SPI_COMPLETE) \ - (spip)->state = SPI_READY; \ - } \ - else \ - (spip)->state = SPI_READY; \ - _spi_wakeup_isr(spip); \ -} -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void spiInit(void); - void spiObjectInit(SPIDriver *spip); - void spiStart(SPIDriver *spip, const SPIConfig *config); - void spiStop(SPIDriver *spip); - void spiSelect(SPIDriver *spip); - void spiUnselect(SPIDriver *spip); - void spiStartIgnore(SPIDriver *spip, size_t n); - void spiStartExchange(SPIDriver *spip, size_t n, - const void *txbuf, void *rxbuf); - void spiStartSend(SPIDriver *spip, size_t n, const void *txbuf); - void spiStartReceive(SPIDriver *spip, size_t n, void *rxbuf); -#if SPI_USE_WAIT - void spiIgnore(SPIDriver *spip, size_t n); - void spiExchange(SPIDriver *spip, size_t n, const void *txbuf, void *rxbuf); - void spiSend(SPIDriver *spip, size_t n, const void *txbuf); - void spiReceive(SPIDriver *spip, size_t n, void *rxbuf); -#endif /* SPI_USE_WAIT */ -#if SPI_USE_MUTUAL_EXCLUSION - void spiAcquireBus(SPIDriver *spip); - void spiReleaseBus(SPIDriver *spip); -#endif /* SPI_USE_MUTUAL_EXCLUSION */ -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_SPI */ - -#endif /* _SPI_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/include/tm.h b/firmware/chibios/os/hal/include/tm.h deleted file mode 100644 index 2b9c2d8eb1..0000000000 --- a/firmware/chibios/os/hal/include/tm.h +++ /dev/null @@ -1,125 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file tm.h - * @brief Time Measurement driver header. - * - * @addtogroup TM - * @{ - */ - -#ifndef _TM_H_ -#define _TM_H_ - -#if HAL_USE_TM || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a Time Measurement object. - * @note Start/stop of measurements is performed through the function - * pointers in order to avoid inlining of those functions which - * could compromise measurement accuracy. - * @note The maximum measurable time period depends on the implementation - * of the realtime counter in the HAL driver. - * @note The measurement is not 100% cycle-accurate, it can be in excess - * of few cycles depending on the compiler and target architecture. - * @note Interrupts can affect measurement if the measurement is performed - * with interrupts enabled. - */ -typedef struct TimeMeasurement TimeMeasurement; - -/** - * @brief Time Measurement structure. - */ -struct TimeMeasurement { - void (*start)(TimeMeasurement *tmp); /**< @brief Starts a measurement. */ - void (*stop)(TimeMeasurement *tmp); /**< @brief Stops a measurement. */ - halrtcnt_t last; /**< @brief Last measurement. */ - halrtcnt_t worst; /**< @brief Worst measurement. */ - halrtcnt_t best; /**< @brief Best measurement. */ -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Starts a measurement. - * @pre The @p TimeMeasurement must be initialized. - * @note This function can be invoked in any context. - * - * @param[in,out] tmp pointer to a @p TimeMeasurement structure - * - * @special - */ -#define tmStartMeasurement(tmp) (tmp)->start(tmp) - -/** - * @brief Stops a measurement. - * @pre The @p TimeMeasurement must be initialized. - * @note This function can be invoked in any context. - * - * @param[in,out] tmp pointer to a @p TimeMeasurement structure - * - * @special - */ -#define tmStopMeasurement(tmp) (tmp)->stop(tmp) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void tmInit(void); - void tmObjectInit(TimeMeasurement *tmp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_TM */ - -#endif /* _TM_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/include/uart.h b/firmware/chibios/os/hal/include/uart.h deleted file mode 100644 index 4f4c2c158a..0000000000 --- a/firmware/chibios/os/hal/include/uart.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file uart.h - * @brief UART Driver macros and structures. - * - * @addtogroup UART - * @{ - */ - -#ifndef _UART_H_ -#define _UART_H_ - -#if HAL_USE_UART || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name UART status flags - * @{ - */ -#define UART_NO_ERROR 0 /**< @brief No pending conditions. */ -#define UART_PARITY_ERROR 4 /**< @brief Parity error happened. */ -#define UART_FRAMING_ERROR 8 /**< @brief Framing error happened. */ -#define UART_OVERRUN_ERROR 16 /**< @brief Overflow happened. */ -#define UART_NOISE_ERROR 32 /**< @brief Noise on the line. */ -#define UART_BREAK_DETECTED 64 /**< @brief Break detected. */ -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - UART_UNINIT = 0, /**< Not initialized. */ - UART_STOP = 1, /**< Stopped. */ - UART_READY = 2 /**< Ready. */ -} uartstate_t; - -/** - * @brief Transmitter state machine states. - */ -typedef enum { - UART_TX_IDLE = 0, /**< Not transmitting. */ - UART_TX_ACTIVE = 1, /**< Transmitting. */ - UART_TX_COMPLETE = 2 /**< Buffer complete. */ -} uarttxstate_t; - -/** - * @brief Receiver state machine states. - */ -typedef enum { - UART_RX_IDLE = 0, /**< Not receiving. */ - UART_RX_ACTIVE = 1, /**< Receiving. */ - UART_RX_COMPLETE = 2 /**< Buffer complete. */ -} uartrxstate_t; - -#include "uart_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void uartInit(void); - void uartObjectInit(UARTDriver *uartp); - void uartStart(UARTDriver *uartp, const UARTConfig *config); - void uartStop(UARTDriver *uartp); - void uartStartSend(UARTDriver *uartp, size_t n, const void *txbuf); - void uartStartSendI(UARTDriver *uartp, size_t n, const void *txbuf); - size_t uartStopSend(UARTDriver *uartp); - size_t uartStopSendI(UARTDriver *uartp); - void uartStartReceive(UARTDriver *uartp, size_t n, void *rxbuf); - void uartStartReceiveI(UARTDriver *uartp, size_t n, void *rxbuf); - size_t uartStopReceive(UARTDriver *uartp); - size_t uartStopReceiveI(UARTDriver *uartp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_UART */ - -#endif /* _UART_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/include/usb.h b/firmware/chibios/os/hal/include/usb.h deleted file mode 100644 index 9ccb199723..0000000000 --- a/firmware/chibios/os/hal/include/usb.h +++ /dev/null @@ -1,585 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file usb.h - * @brief USB Driver macros and structures. - * - * @addtogroup USB - * @{ - */ - -#ifndef _USB_H_ -#define _USB_H_ - -#if HAL_USE_USB || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#define USB_RTYPE_DIR_MASK 0x80 -#define USB_RTYPE_DIR_HOST2DEV 0x00 -#define USB_RTYPE_DIR_DEV2HOST 0x80 -#define USB_RTYPE_TYPE_MASK 0x60 -#define USB_RTYPE_TYPE_STD 0x00 -#define USB_RTYPE_TYPE_CLASS 0x20 -#define USB_RTYPE_TYPE_VENDOR 0x40 -#define USB_RTYPE_TYPE_RESERVED 0x60 -#define USB_RTYPE_RECIPIENT_MASK 0x1F -#define USB_RTYPE_RECIPIENT_DEVICE 0x00 -#define USB_RTYPE_RECIPIENT_INTERFACE 0x01 -#define USB_RTYPE_RECIPIENT_ENDPOINT 0x02 -#define USB_RTYPE_RECIPIENT_OTHER 0x03 - -#define USB_REQ_GET_STATUS 0 -#define USB_REQ_CLEAR_FEATURE 1 -#define USB_REQ_SET_FEATURE 3 -#define USB_REQ_SET_ADDRESS 5 -#define USB_REQ_GET_DESCRIPTOR 6 -#define USB_REQ_SET_DESCRIPTOR 7 -#define USB_REQ_GET_CONFIGURATION 8 -#define USB_REQ_SET_CONFIGURATION 9 -#define USB_REQ_GET_INTERFACE 10 -#define USB_REQ_SET_INTERFACE 11 -#define USB_REQ_SYNCH_FRAME 12 - -#define USB_DESCRIPTOR_DEVICE 1 -#define USB_DESCRIPTOR_CONFIGURATION 2 -#define USB_DESCRIPTOR_STRING 3 -#define USB_DESCRIPTOR_INTERFACE 4 -#define USB_DESCRIPTOR_ENDPOINT 5 -#define USB_DESCRIPTOR_DEVICE_QUALIFIER 6 -#define USB_DESCRIPTOR_OTHER_SPEED_CFG 7 -#define USB_DESCRIPTOR_INTERFACE_POWER 8 -#define USB_DESCRIPTOR_INTERFACE_ASSOCIATION 11 - -#define USB_FEATURE_ENDPOINT_HALT 0 -#define USB_FEATURE_DEVICE_REMOTE_WAKEUP 1 -#define USB_FEATURE_TEST_MODE 2 - -#define USB_EARLY_SET_ADDRESS 0 -#define USB_LATE_SET_ADDRESS 1 - -#define USB_EP0_STATUS_STAGE_SW 0 -#define USB_EP0_STATUS_STAGE_HW 1 - -#define USB_SET_ADDRESS_ACK_SW 0 -#define USB_SET_ADDRESS_ACK_HW 1 - -/** - * @name Helper macros for USB descriptors - * @{ - */ -/** - * @brief Helper macro for index values into descriptor strings. - */ -#define USB_DESC_INDEX(i) ((uint8_t)(i)) - -/** - * @brief Helper macro for byte values into descriptor strings. - */ -#define USB_DESC_BYTE(b) ((uint8_t)(b)) - -/** - * @brief Helper macro for word values into descriptor strings. - */ -#define USB_DESC_WORD(w) \ - (uint8_t)((w) & 255), \ - (uint8_t)(((w) >> 8) & 255) - -/** - * @brief Helper macro for BCD values into descriptor strings. - */ -#define USB_DESC_BCD(bcd) \ - (uint8_t)((bcd) & 255), \ - (uint8_t)(((bcd) >> 8) & 255) - -/** - * @brief Device Descriptor helper macro. - */ -#define USB_DESC_DEVICE(bcdUSB, bDeviceClass, bDeviceSubClass, \ - bDeviceProtocol, bMaxPacketSize, idVendor, \ - idProduct, bcdDevice, iManufacturer, \ - iProduct, iSerialNumber, bNumConfigurations) \ - USB_DESC_BYTE(18), \ - USB_DESC_BYTE(USB_DESCRIPTOR_DEVICE), \ - USB_DESC_BCD(bcdUSB), \ - USB_DESC_BYTE(bDeviceClass), \ - USB_DESC_BYTE(bDeviceSubClass), \ - USB_DESC_BYTE(bDeviceProtocol), \ - USB_DESC_BYTE(bMaxPacketSize), \ - USB_DESC_WORD(idVendor), \ - USB_DESC_WORD(idProduct), \ - USB_DESC_BCD(bcdDevice), \ - USB_DESC_INDEX(iManufacturer), \ - USB_DESC_INDEX(iProduct), \ - USB_DESC_INDEX(iSerialNumber), \ - USB_DESC_BYTE(bNumConfigurations) - -/** - * @brief Configuration Descriptor helper macro. - */ -#define USB_DESC_CONFIGURATION(wTotalLength, bNumInterfaces, \ - bConfigurationValue, iConfiguration, \ - bmAttributes, bMaxPower) \ - USB_DESC_BYTE(9), \ - USB_DESC_BYTE(USB_DESCRIPTOR_CONFIGURATION), \ - USB_DESC_WORD(wTotalLength), \ - USB_DESC_BYTE(bNumInterfaces), \ - USB_DESC_BYTE(bConfigurationValue), \ - USB_DESC_INDEX(iConfiguration), \ - USB_DESC_BYTE(bmAttributes), \ - USB_DESC_BYTE(bMaxPower) - -/** - * @brief Interface Descriptor helper macro. - */ -#define USB_DESC_INTERFACE(bInterfaceNumber, bAlternateSetting, \ - bNumEndpoints, bInterfaceClass, \ - bInterfaceSubClass, bInterfaceProtocol, \ - iInterface) \ - USB_DESC_BYTE(9), \ - USB_DESC_BYTE(USB_DESCRIPTOR_INTERFACE), \ - USB_DESC_BYTE(bInterfaceNumber), \ - USB_DESC_BYTE(bAlternateSetting), \ - USB_DESC_BYTE(bNumEndpoints), \ - USB_DESC_BYTE(bInterfaceClass), \ - USB_DESC_BYTE(bInterfaceSubClass), \ - USB_DESC_BYTE(bInterfaceProtocol), \ - USB_DESC_INDEX(iInterface) - -/** - * @brief Interface Association Descriptor helper macro. - */ -#define USB_DESC_INTERFACE_ASSOCIATION(bFirstInterface, \ - bInterfaceCount, bFunctionClass, \ - bFunctionSubClass, bFunctionProcotol, \ - iInterface) \ - USB_DESC_BYTE(8), \ - USB_DESC_BYTE(USB_DESCRIPTOR_INTERFACE_ASSOCIATION), \ - USB_DESC_BYTE(bFirstInterface), \ - USB_DESC_BYTE(bInterfaceCount), \ - USB_DESC_BYTE(bFunctionClass), \ - USB_DESC_BYTE(bFunctionSubClass), \ - USB_DESC_BYTE(bFunctionProcotol), \ - USB_DESC_INDEX(iInterface) - -/** - * @brief Endpoint Descriptor helper macro. - */ -#define USB_DESC_ENDPOINT(bEndpointAddress, bmAttributes, wMaxPacketSize, \ - bInterval) \ - USB_DESC_BYTE(7), \ - USB_DESC_BYTE(USB_DESCRIPTOR_ENDPOINT), \ - USB_DESC_BYTE(bEndpointAddress), \ - USB_DESC_BYTE(bmAttributes), \ - USB_DESC_WORD(wMaxPacketSize), \ - USB_DESC_BYTE(bInterval) -/** @} */ - -/** - * @name Endpoint types and settings - * @{ - */ -#define USB_EP_MODE_TYPE 0x0003 /**< Endpoint type mask. */ -#define USB_EP_MODE_TYPE_CTRL 0x0000 /**< Control endpoint. */ -#define USB_EP_MODE_TYPE_ISOC 0x0001 /**< Isochronous endpoint. */ -#define USB_EP_MODE_TYPE_BULK 0x0002 /**< Bulk endpoint. */ -#define USB_EP_MODE_TYPE_INTR 0x0003 /**< Interrupt endpoint. */ -#define USB_EP_MODE_LINEAR_BUFFER 0x0000 /**< Linear buffer mode. */ -#define USB_EP_MODE_QUEUE_BUFFER 0x0010 /**< Queue buffer mode. */ -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a structure representing an USB driver. - */ -typedef struct USBDriver USBDriver; - -/** - * @brief Type of an endpoint identifier. - */ -typedef uint8_t usbep_t; - -/** - * @brief Type of a driver state machine possible states. - */ -typedef enum { - USB_UNINIT = 0, /**< Not initialized. */ - USB_STOP = 1, /**< Stopped. */ - USB_READY = 2, /**< Ready, after bus reset. */ - USB_SELECTED = 3, /**< Address assigned. */ - USB_ACTIVE = 4 /**< Active, configuration selected.*/ -} usbstate_t; - -/** - * @brief Type of an endpoint status. - */ -typedef enum { - EP_STATUS_DISABLED = 0, /**< Endpoint not active. */ - EP_STATUS_STALLED = 1, /**< Endpoint opened but stalled. */ - EP_STATUS_ACTIVE = 2 /**< Active endpoint. */ -} usbepstatus_t; - -/** - * @brief Type of an endpoint zero state machine states. - */ -typedef enum { - USB_EP0_WAITING_SETUP, /**< Waiting for SETUP data. */ - USB_EP0_TX, /**< Transmitting. */ - USB_EP0_WAITING_TX0, /**< Waiting transmit 0. */ - USB_EP0_WAITING_STS, /**< Waiting status. */ - USB_EP0_RX, /**< Receiving. */ - USB_EP0_SENDING_STS, /**< Sending status. */ - USB_EP0_ERROR /**< Error, EP0 stalled. */ -} usbep0state_t; - -/** - * @brief Type of an enumeration of the possible USB events. - */ -typedef enum { - USB_EVENT_RESET = 0, /**< Driver has been reset by host. */ - USB_EVENT_ADDRESS = 1, /**< Address assigned. */ - USB_EVENT_CONFIGURED = 2, /**< Configuration selected. */ - USB_EVENT_SUSPEND = 3, /**< Entering suspend mode. */ - USB_EVENT_WAKEUP = 4, /**< Leaving suspend mode. */ - USB_EVENT_STALLED = 5 /**< Endpoint 0 error, stalled. */ -} usbevent_t; - -/** - * @brief Type of an USB descriptor. - */ -typedef struct { - /** - * @brief Descriptor size in unicode characters. - */ - size_t ud_size; - /** - * @brief Pointer to the descriptor. - */ - const uint8_t *ud_string; -} USBDescriptor; - -/** - * @brief Type of an USB generic notification callback. - * - * @param[in] usbp pointer to the @p USBDriver object triggering the - * callback - */ -typedef void (*usbcallback_t)(USBDriver *usbp); - -/** - * @brief Type of an USB endpoint callback. - * - * @param[in] usbp pointer to the @p USBDriver object triggering the - * callback - * @param[in] ep endpoint number - */ -typedef void (*usbepcallback_t)(USBDriver *usbp, usbep_t ep); - -/** - * @brief Type of an USB event notification callback. - * - * @param[in] usbp pointer to the @p USBDriver object triggering the - * callback - * @param[in] event event type - */ -typedef void (*usbeventcb_t)(USBDriver *usbp, usbevent_t event); - -/** - * @brief Type of a requests handler callback. - * @details The request is encoded in the @p usb_setup buffer. - * - * @param[in] usbp pointer to the @p USBDriver object triggering the - * callback - * @return The request handling exit code. - * @retval FALSE Request not recognized by the handler. - * @retval TRUE Request handled. - */ -typedef bool_t (*usbreqhandler_t)(USBDriver *usbp); - -/** - * @brief Type of an USB descriptor-retrieving callback. - */ -typedef const USBDescriptor * (*usbgetdescriptor_t)(USBDriver *usbp, - uint8_t dtype, - uint8_t dindex, - uint16_t lang); - -#include "usb_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Returns the driver state. - * - * @param[in] usbp pointer to the @p USBDriver object - * @return The driver state. - * - * @iclass - */ -#define usbGetDriverStateI(usbp) ((usbp)->state) - -/** - * @brief Fetches a 16 bits word value from an USB message. - * - * @param[in] p pointer to the 16 bits word - * - * @notapi - */ -#define usbFetchWord(p) ((uint16_t)*(p) | ((uint16_t)*((p) + 1) << 8)) - -/** - * @brief Connects the USB device. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @api - */ -#define usbConnectBus(usbp) usb_lld_connect_bus(usbp) - -/** - * @brief Disconnect the USB device. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @api - */ -#define usbDisconnectBus(usbp) usb_lld_disconnect_bus(usbp) - -/** - * @brief Returns the current frame number. - * - * @param[in] usbp pointer to the @p USBDriver object - * @return The current frame number. - * - * @api - */ -#define usbGetFrameNumber(usbp) usb_lld_get_frame_number(usbp) - -/** - * @brief Returns the status of an IN endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @return The operation status. - * @retval FALSE Endpoint ready. - * @retval TRUE Endpoint transmitting. - * - * @iclass - */ -#define usbGetTransmitStatusI(usbp, ep) ((usbp)->transmitting & (1 << (ep))) - -/** - * @brief Returns the status of an OUT endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @return The operation status. - * @retval FALSE Endpoint ready. - * @retval TRUE Endpoint receiving. - * - * @iclass - */ -#define usbGetReceiveStatusI(usbp, ep) ((usbp)->receiving & (1 << (ep))) - -/** - * @brief Returns the exact size of a receive transaction. - * @details The received size can be different from the size specified in - * @p usbStartReceiveI() because the last packet could have a size - * different from the expected one. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @return Received data size. - * - * @iclass - */ -#define usbGetReceiveTransactionSizeI(usbp, ep) \ - usb_lld_get_transaction_size(usbp, ep) - -/** - * @brief Request transfer setup. - * @details This macro is used by the request handling callbacks in order to - * prepare a transaction over the endpoint zero. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] buf pointer to a buffer for the transaction data - * @param[in] n number of bytes to be transferred - * @param[in] endcb callback to be invoked after the transfer or @p NULL - * - * @api - */ -#define usbSetupTransfer(usbp, buf, n, endcb) { \ - (usbp)->ep0next = (buf); \ - (usbp)->ep0n = (n); \ - (usbp)->ep0endcb = (endcb); \ -} - -/** - * @brief Reads a setup packet from the dedicated packet buffer. - * @details This function must be invoked in the context of the @p setup_cb - * callback in order to read the received setup packet. - * @pre In order to use this function the endpoint must have been - * initialized as a control endpoint. - * @note This function can be invoked both in thread and IRQ context. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @param[out] buf buffer where to copy the packet data - * - * @special - */ -#define usbReadSetup(usbp, ep, buf) usb_lld_read_setup(usbp, ep, buf) -/** @} */ - -/** - * @name Low Level driver helper macros - * @{ - */ -/** - * @brief Common ISR code, usb event callback. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] evt USB event code - * - * @notapi - */ -#define _usb_isr_invoke_event_cb(usbp, evt) { \ - if (((usbp)->config->event_cb) != NULL) \ - (usbp)->config->event_cb(usbp, evt); \ -} - -/** - * @brief Common ISR code, SOF callback. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -#define _usb_isr_invoke_sof_cb(usbp) { \ - if (((usbp)->config->sof_cb) != NULL) \ - (usbp)->config->sof_cb(usbp); \ -} - -/** - * @brief Common ISR code, setup packet callback. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -#define _usb_isr_invoke_setup_cb(usbp, ep) { \ - (usbp)->epc[ep]->setup_cb(usbp, ep); \ -} - -/** - * @brief Common ISR code, IN endpoint callback. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -#define _usb_isr_invoke_in_cb(usbp, ep) { \ - (usbp)->transmitting &= ~(1 << (ep)); \ - (usbp)->epc[ep]->in_cb(usbp, ep); \ -} - -/** - * @brief Common ISR code, OUT endpoint event. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -#define _usb_isr_invoke_out_cb(usbp, ep) { \ - (usbp)->receiving &= ~(1 << (ep)); \ - (usbp)->epc[ep]->out_cb(usbp, ep); \ -} -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void usbInit(void); - void usbObjectInit(USBDriver *usbp); - void usbStart(USBDriver *usbp, const USBConfig *config); - void usbStop(USBDriver *usbp); - void usbInitEndpointI(USBDriver *usbp, usbep_t ep, - const USBEndpointConfig *epcp); - void usbDisableEndpointsI(USBDriver *usbp); - void usbReadSetupI(USBDriver *usbp, usbep_t ep, uint8_t *buf); - void usbPrepareReceive(USBDriver *usbp, usbep_t ep, - uint8_t *buf, size_t n); - void usbPrepareTransmit(USBDriver *usbp, usbep_t ep, - const uint8_t *buf, size_t n); - void usbPrepareQueuedReceive(USBDriver *usbp, usbep_t ep, - InputQueue *iqp, size_t n); - void usbPrepareQueuedTransmit(USBDriver *usbp, usbep_t ep, - OutputQueue *oqp, size_t n); - bool_t usbStartReceiveI(USBDriver *usbp, usbep_t ep); - bool_t usbStartTransmitI(USBDriver *usbp, usbep_t ep); - bool_t usbStallReceiveI(USBDriver *usbp, usbep_t ep); - bool_t usbStallTransmitI(USBDriver *usbp, usbep_t ep); - void _usb_reset(USBDriver *usbp); - void _usb_ep0setup(USBDriver *usbp, usbep_t ep); - void _usb_ep0in(USBDriver *usbp, usbep_t ep); - void _usb_ep0out(USBDriver *usbp, usbep_t ep); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_USB */ - -#endif /* _USB_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/Posix/console.c b/firmware/chibios/os/hal/platforms/Posix/console.c deleted file mode 100644 index 53c2593e66..0000000000 --- a/firmware/chibios/os/hal/platforms/Posix/console.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file console.c - * @brief Simulator console driver code. - * @{ - */ - -#include - -#include "ch.h" -#include "hal.h" -#include "console.h" - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief Console driver 1. - */ -BaseChannel CD1; - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static size_t write(void *ip, const uint8_t *bp, size_t n) { - size_t ret; - - (void)ip; - ret = fwrite(bp, 1, n, stdout); - fflush(stdout); - return ret; -} - -static size_t read(void *ip, uint8_t *bp, size_t n) { - - (void)ip; - return fread(bp, 1, n, stdin); -} - -static msg_t put(void *ip, uint8_t b) { - - (void)ip; - - fputc(b, stdout); - fflush(stdout); - return RDY_OK; -} - -static msg_t get(void *ip) { - - (void)ip; - - return fgetc(stdin); -} - -static msg_t putt(void *ip, uint8_t b, systime_t timeout) { - - (void)ip; - (void)timeout; - fputc(b, stdout); - fflush(stdout); - return RDY_OK; -} - -static msg_t gett(void *ip, systime_t timeout) { - - (void)ip; - (void)timeout; - return fgetc(stdin); -} - -static size_t writet(void *ip, const uint8_t *bp, size_t n, systime_t timeout) { - size_t ret; - - (void)ip; - (void)timeout; - ret = fwrite(bp, 1, n, stdout); - fflush(stdout); - return ret; -} - -static size_t readt(void *ip, uint8_t *bp, size_t n, systime_t timeout) { - - (void)ip; - (void)timeout; - return fread(bp, 1, n, stdin); -} - -static const struct BaseChannelVMT vmt = { - write, read, put, get, - putt, gett, writet, readt -}; - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -void conInit(void) { - - CD1.vmt = &vmt; -} - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/Posix/console.h b/firmware/chibios/os/hal/platforms/Posix/console.h deleted file mode 100644 index 58f0f08ec9..0000000000 --- a/firmware/chibios/os/hal/platforms/Posix/console.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file console.h - * @brief Simulator console driver header. - * @{ - */ - -#ifndef _CONSOLE_H_ -#define _CONSOLE_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -extern BaseChannel CD1; - -#ifdef __cplusplus -extern "C" { -#endif - void conInit(void); -#ifdef __cplusplus -} -#endif - -#endif /* _CONSOLE_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/Posix/hal_lld.c b/firmware/chibios/os/hal/platforms/Posix/hal_lld.c deleted file mode 100644 index 39e8003e10..0000000000 --- a/firmware/chibios/os/hal/platforms/Posix/hal_lld.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file Posix/hal_lld.c - * @brief Posix HAL subsystem low level driver code. - * - * @addtogroup POSIX_HAL - * @{ - */ - -#include -#include -#include - -#include "ch.h" -#include "hal.h" - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -static struct timeval nextcnt; -static struct timeval tick = {0, 1000000 / CH_FREQUENCY}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level HAL driver initialization. - */ -void hal_lld_init(void) { - -#if defined(__APPLE__) - puts("ChibiOS/RT simulator (OS X)\n"); -#else - puts("ChibiOS/RT simulator (Linux)\n"); -#endif - gettimeofday(&nextcnt, NULL); - timeradd(&nextcnt, &tick, &nextcnt); -} - -/** - * @brief Interrupt simulation. - */ -void ChkIntSources(void) { - struct timeval tv; - -#if HAL_USE_SERIAL - if (sd_lld_interrupt_pending()) { - dbg_check_lock(); - if (chSchIsPreemptionRequired()) - chSchDoReschedule(); - dbg_check_unlock(); - return; - } -#endif - - gettimeofday(&tv, NULL); - if (timercmp(&tv, &nextcnt, >=)) { - timeradd(&nextcnt, &tick, &nextcnt); - - CH_IRQ_PROLOGUE(); - - chSysLockFromIsr(); - chSysTimerHandlerI(); - chSysUnlockFromIsr(); - - CH_IRQ_EPILOGUE(); - - dbg_check_lock(); - if (chSchIsPreemptionRequired()) - chSchDoReschedule(); - dbg_check_unlock(); - } -} - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/Posix/hal_lld.h b/firmware/chibios/os/hal/platforms/Posix/hal_lld.h deleted file mode 100644 index d038c542a4..0000000000 --- a/firmware/chibios/os/hal/platforms/Posix/hal_lld.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file Posix/hal_lld.h - * @brief Posix simulator HAL subsystem low level driver header. - * - * @addtogroup POSIX_HAL - * @{ - */ - -#ifndef _HAL_LLD_H_ -#define _HAL_LLD_H_ - -#include -#include -#include - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Defines the support for realtime counters in the HAL. - */ -#define HAL_IMPLEMENTS_COUNTERS FALSE - -/** - * @brief Platform name. - */ -#define PLATFORM_NAME "Linux" - -#define SOCKET int -#define INVALID_SOCKET -1 - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void hal_lld_init(void); - void ChkIntSources(void); -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_LLD_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/Posix/pal_lld.c b/firmware/chibios/os/hal/platforms/Posix/pal_lld.c deleted file mode 100644 index 6a6261b558..0000000000 --- a/firmware/chibios/os/hal/platforms/Posix/pal_lld.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file Posix/pal_lld.c - * @brief Posix low level simulated PAL driver code. - * - * @addtogroup POSIX_PAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief VIO1 simulated port. - */ -sim_vio_port_t vio_port_1; - -/** - * @brief VIO2 simulated port. - */ -sim_vio_port_t vio_port_2; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Pads mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * - * @param[in] port the port identifier - * @param[in] mask the group mask - * @param[in] mode the mode - * - * @note This function is not meant to be invoked directly by the application - * code. - * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output with high - * state. - * @note This function does not alter the @p PINSELx registers. Alternate - * functions setup must be handled by device-specific code. - */ -void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - iomode_t mode) { - - switch (mode) { - case PAL_MODE_RESET: - case PAL_MODE_INPUT: - port->dir &= ~mask; - break; - case PAL_MODE_UNCONNECTED: - port->latch |= mask; - case PAL_MODE_OUTPUT_PUSHPULL: - port->dir |= mask; - break; - } -} - -#endif /* HAL_USE_PAL */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/Posix/pal_lld.h b/firmware/chibios/os/hal/platforms/Posix/pal_lld.h deleted file mode 100644 index d2d5942b87..0000000000 --- a/firmware/chibios/os/hal/platforms/Posix/pal_lld.h +++ /dev/null @@ -1,206 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file Posix/pal_lld.h - * @brief Posix low level simulated PAL driver header. - * - * @addtogroup POSIX_PAL - * @{ - */ - -#ifndef _PAL_LLD_H_ -#define _PAL_LLD_H_ - -#if HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Unsupported modes and specific modes */ -/*===========================================================================*/ - -#undef PAL_MODE_INPUT_PULLUP -#undef PAL_MODE_INPUT_PULLDOWN -#undef PAL_MODE_OUTPUT_OPENDRAIN -#undef PAL_MODE_INPUT_ANALOG - -/*===========================================================================*/ -/* I/O Ports Types and constants. */ -/*===========================================================================*/ - -/** - * @brief VIO port structure. - */ -typedef struct { - /** - * @brief VIO_LATCH register. - * @details This register represents the output latch of the VIO port. - */ - uint32_t latch; - /** - * @brief VIO_PIN register. - * @details This register represents the logical level at the VIO port - * pin level. - */ - uint32_t pin; - /** - * @brief VIO_DIR register. - * @details Direction of the VIO port bits, 0=input, 1=output. - */ - uint32_t dir; -} sim_vio_port_t; - -/** - * @brief Virtual I/O ports static initializer. - * @details An instance of this structure must be passed to @p palInit() at - * system startup time in order to initialized the digital I/O - * subsystem. This represents only the initial setup, specific pads - * or whole ports can be reprogrammed at later time. - */ -typedef struct { - /** - * @brief Virtual port 1 setup data. - */ - sim_vio_port_t VP1Data; - /** - * @brief Virtual port 2 setup data. - */ - sim_vio_port_t VP2Data; -} PALConfig; - -/** - * @brief Width, in bits, of an I/O port. - */ -#define PAL_IOPORTS_WIDTH 32 - -/** - * @brief Whole port mask. - * @brief This macro specifies all the valid bits into a port. - */ -#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFF) - -/** - * @brief Digital I/O port sized unsigned type. - */ -typedef uint32_t ioportmask_t; - -/** - * @brief Digital I/O modes. - */ -typedef uint32_t iomode_t; - -/** - * @brief Port Identifier. - */ -typedef sim_vio_port_t *ioportid_t; - -/*===========================================================================*/ -/* I/O Ports Identifiers. */ -/*===========================================================================*/ - -/** - * @brief VIO port 1 identifier. - */ -#define IOPORT1 (&vio_port_1) - -/** - * @brief VIO port 2 identifier. - */ -#define IOPORT2 (&vio_port_2) - -/*===========================================================================*/ -/* Implementation, some of the following macros could be implemented as */ -/* functions, if so please put them in pal_lld.c. */ -/*===========================================================================*/ - -/** - * @brief Low level PAL subsystem initialization. - * - * @param[in] config architecture-dependent ports configuration - * - * @notapi - */ -#define pal_lld_init(config) \ - (vio_port_1 = (config)->VP1Data, \ - vio_port_2 = (config)->VP2Data) - -/** - * @brief Reads the physical I/O port states. - * - * @param[in] port port identifier - * @return The port bits. - * - * @notapi - */ -#define pal_lld_readport(port) ((port)->pin) - -/** - * @brief Reads the output latch. - * @details The purpose of this function is to read back the latched output - * value. - * - * @param[in] port port identifier - * @return The latched logical states. - * - * @notapi - */ -#define pal_lld_readlatch(port) ((port)->latch) - -/** - * @brief Writes a bits mask on a I/O port. - * - * @param[in] port port identifier - * @param[in] bits bits to be written on the specified port - * - * @notapi - */ -#define pal_lld_writeport(port, bits) ((port)->latch = (bits)) - -/** - * @brief Pads group mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] offset group bit offset within the port - * @param[in] mode group mode - * - * @notapi - */ -#define pal_lld_setgroupmode(port, mask, offset, mode) \ - _pal_lld_setgroupmode(port, mask << offset, mode) - -#if !defined(__DOXYGEN__) -extern sim_vio_port_t vio_port_1; -extern sim_vio_port_t vio_port_2; -extern const PALConfig pal_default_config; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - iomode_t mode); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_PAL */ - -#endif /* _PAL_LLD_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/Posix/platform.mk b/firmware/chibios/os/hal/platforms/Posix/platform.mk deleted file mode 100644 index ea0c2e4ba0..0000000000 --- a/firmware/chibios/os/hal/platforms/Posix/platform.mk +++ /dev/null @@ -1,7 +0,0 @@ -# List of all the Posix platform files. -PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/Posix/hal_lld.c \ - ${CHIBIOS}/os/hal/platforms/Posix/pal_lld.c \ - ${CHIBIOS}/os/hal/platforms/Posix/serial_lld.c - -# Required include directories -PLATFORMINC = ${CHIBIOS}/os/hal/platforms/Posix diff --git a/firmware/chibios/os/hal/platforms/Posix/serial_lld.c b/firmware/chibios/os/hal/platforms/Posix/serial_lld.c deleted file mode 100644 index 5c8ea5f68c..0000000000 --- a/firmware/chibios/os/hal/platforms/Posix/serial_lld.c +++ /dev/null @@ -1,287 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file Posix/serial_lld.c - * @brief Posix low level simulated serial driver code. - * - * @addtogroup POSIX_SERIAL - * @{ - */ - -#include -#include -#include -#include -#include -#include - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief Serial driver 1 identifier.*/ -#if USE_SIM_SERIAL1 || defined(__DOXYGEN__) -SerialDriver SD1; -#endif -/** @brief Serial driver 2 identifier.*/ -#if USE_SIM_SERIAL2 || defined(__DOXYGEN__) -SerialDriver SD2; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** @brief Driver default configuration.*/ -static const SerialConfig default_config = { -}; - -static u_long nb = 1; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void init(SerialDriver *sdp, uint16_t port) { - struct sockaddr_in sad; - struct protoent *prtp; - int sockval = 1; - socklen_t socklen = sizeof(sockval); - - - if ((prtp = getprotobyname("tcp")) == NULL) { - printf("%s: Error mapping protocol name to protocol number\n", sdp->com_name); - goto abort; - } - - sdp->com_listen = socket(PF_INET, SOCK_STREAM, prtp->p_proto); - if (sdp->com_listen == INVALID_SOCKET) { - printf("%s: Error creating simulator socket\n", sdp->com_name); - goto abort; - } - - - setsockopt(sdp->com_listen, SOL_SOCKET, SO_REUSEADDR, &sockval, socklen); - - if (ioctl(sdp->com_listen, FIONBIO, &nb) != 0) { - printf("%s: Unable to setup non blocking mode on socket\n", sdp->com_name); - goto abort; - } - - memset(&sad, 0, sizeof(sad)); - sad.sin_family = AF_INET; - sad.sin_addr.s_addr = INADDR_ANY; - sad.sin_port = htons(port); - if (bind(sdp->com_listen, (struct sockaddr *)&sad, sizeof(sad))) { - printf("%s: Error binding socket\n", sdp->com_name); - goto abort; - } - - if (listen(sdp->com_listen, 1) != 0) { - printf("%s: Error listening socket\n", sdp->com_name); - goto abort; - } - printf("Full Duplex Channel %s listening on port %d\n", sdp->com_name, port); - return; - -abort: - if (sdp->com_listen != INVALID_SOCKET) - close(sdp->com_listen); - exit(1); -} - -static bool_t connint(SerialDriver *sdp) { - - if (sdp->com_data == INVALID_SOCKET) { - struct sockaddr addr; - socklen_t addrlen = sizeof(addr); - - if ((sdp->com_data = accept(sdp->com_listen, &addr, &addrlen)) == INVALID_SOCKET) - return FALSE; - - if (ioctl(sdp->com_data, FIONBIO, &nb) != 0) { - printf("%s: Unable to setup non blocking mode on data socket\n", sdp->com_name); - goto abort; - } - chSysLockFromIsr(); - chnAddFlagsI(sdp, CHN_CONNECTED); - chSysUnlockFromIsr(); - return TRUE; - } - return FALSE; -abort: - if (sdp->com_listen != INVALID_SOCKET) - close(sdp->com_listen); - if (sdp->com_data != INVALID_SOCKET) - close(sdp->com_data); - exit(1); -} - -static bool_t inint(SerialDriver *sdp) { - - if (sdp->com_data != INVALID_SOCKET) { - int i; - uint8_t data[32]; - - /* - * Input. - */ - int n = recv(sdp->com_data, data, sizeof(data), 0); - switch (n) { - case 0: - close(sdp->com_data); - sdp->com_data = INVALID_SOCKET; - chSysLockFromIsr(); - chnAddFlagsI(sdp, CHN_DISCONNECTED); - chSysUnlockFromIsr(); - return FALSE; - case INVALID_SOCKET: - if (errno == EWOULDBLOCK) - return FALSE; - close(sdp->com_data); - sdp->com_data = INVALID_SOCKET; - return FALSE; - } - for (i = 0; i < n; i++) { - chSysLockFromIsr(); - sdIncomingDataI(sdp, data[i]); - chSysUnlockFromIsr(); - } - return TRUE; - } - return FALSE; -} - -static bool_t outint(SerialDriver *sdp) { - - if (sdp->com_data != INVALID_SOCKET) { - int n; - uint8_t data[1]; - - /* - * Input. - */ - chSysLockFromIsr(); - n = sdRequestDataI(sdp); - chSysUnlockFromIsr(); - if (n < 0) - return FALSE; - data[0] = (uint8_t)n; - n = send(sdp->com_data, data, sizeof(data), 0); - switch (n) { - case 0: - close(sdp->com_data); - sdp->com_data = INVALID_SOCKET; - chSysLockFromIsr(); - chnAddFlagsI(sdp, CHN_DISCONNECTED); - chSysUnlockFromIsr(); - return FALSE; - case INVALID_SOCKET: - if (errno == EWOULDBLOCK) - return FALSE; - close(sdp->com_data); - sdp->com_data = INVALID_SOCKET; - return FALSE; - } - return TRUE; - } - return FALSE; -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level serial driver initialization. - */ -void sd_lld_init(void) { - -#if USE_SIM_SERIAL1 - sdObjectInit(&SD1, NULL, NULL); - SD1.com_listen = INVALID_SOCKET; - SD1.com_data = INVALID_SOCKET; - SD1.com_name = "SD1"; -#endif - -#if USE_SIM_SERIAL2 - sdObjectInit(&SD2, NULL, NULL); - SD2.com_listen = INVALID_SOCKET; - SD2.com_data = INVALID_SOCKET; - SD2.com_name = "SD2"; -#endif -} - -/** - * @brief Low level serial driver configuration and (re)start. - * - * @param[in] sdp pointer to a @p SerialDriver object - */ -void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { - - if (config == NULL) - config = &default_config; - -#if USE_SIM_SERIAL1 - if (sdp == &SD1) - init(&SD1, SIM_SD1_PORT); -#endif - -#if USE_SIM_SERIAL2 - if (sdp == &SD2) - init(&SD2, SIM_SD2_PORT); -#endif -} - -/** - * @brief Low level serial driver stop. - * @details De-initializes the USART, stops the associated clock, resets the - * interrupt vector. - * - * @param[in] sdp pointer to a @p SerialDriver object - */ -void sd_lld_stop(SerialDriver *sdp) { - - (void)sdp; -} - -bool_t sd_lld_interrupt_pending(void) { - bool_t b; - - CH_IRQ_PROLOGUE(); - - b = connint(&SD1) || connint(&SD2) || - inint(&SD1) || inint(&SD2) || - outint(&SD1) || outint(&SD2); - - CH_IRQ_EPILOGUE(); - - return b; -} - -#endif /* HAL_USE_SERIAL */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/Posix/serial_lld.h b/firmware/chibios/os/hal/platforms/Posix/serial_lld.h deleted file mode 100644 index 7c86d3cda3..0000000000 --- a/firmware/chibios/os/hal/platforms/Posix/serial_lld.h +++ /dev/null @@ -1,151 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file Posix/serial_lld.h - * @brief Posix low level simulated serial driver header. - * - * @addtogroup POSIX_SERIAL - * @{ - */ - -#ifndef _SERIAL_LLD_H_ -#define _SERIAL_LLD_H_ - -#if HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Serial buffers size. - * @details Configuration parameter, you can change the depth of the queue - * buffers depending on the requirements of your application. - */ -#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_BUFFERS_SIZE 1024 -#endif - -/** - * @brief SD1 driver enable switch. - * @details If set to @p TRUE the support for SD1 is included. - * @note The default is @p TRUE. - */ -#if !defined(USE_SIM_SERIAL1) || defined(__DOXYGEN__) -#define USE_SIM_SERIAL1 TRUE -#endif - -/** - * @brief SD2 driver enable switch. - * @details If set to @p TRUE the support for SD2 is included. - * @note The default is @p TRUE. - */ -#if !defined(USE_SIM_SERIAL2) || defined(__DOXYGEN__) -#define USE_SIM_SERIAL2 TRUE -#endif - -/** - * @brief Listen port for SD1. - */ -#if !defined(SD1_PORT) || defined(__DOXYGEN__) -#define SIM_SD1_PORT 29001 -#endif - -/** - * @brief Listen port for SD2. - */ -#if !defined(SD2_PORT) || defined(__DOXYGEN__) -#define SIM_SD2_PORT 29002 -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Generic Serial Driver configuration structure. - * @details An instance of this structure must be passed to @p sdStart() - * in order to configure and start a serial driver operations. - * @note This structure content is architecture dependent, each driver - * implementation defines its own version and the custom static - * initializers. - */ -typedef struct { -} SerialConfig; - -/** - * @brief @p SerialDriver specific data. - */ -#define _serial_driver_data \ - _base_asynchronous_channel_data \ - /* Driver state.*/ \ - sdstate_t state; \ - /* Input queue.*/ \ - InputQueue iqueue; \ - /* Output queue.*/ \ - OutputQueue oqueue; \ - /* Input circular buffer.*/ \ - uint8_t ib[SERIAL_BUFFERS_SIZE]; \ - /* Output circular buffer.*/ \ - uint8_t ob[SERIAL_BUFFERS_SIZE]; \ - /* End of the mandatory fields.*/ \ - /* Listen socket for simulated serial port.*/ \ - SOCKET com_listen; \ - /* Data socket for simulated serial port.*/ \ - SOCKET com_data; \ - /* Port readable name.*/ \ - const char *com_name; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if USE_SIM_SERIAL1 && !defined(__DOXYGEN__) -extern SerialDriver SD1; -#endif -#if USE_SIM_SERIAL2 && !defined(__DOXYGEN__) -extern SerialDriver SD2; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void sd_lld_init(void); - void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); - void sd_lld_stop(SerialDriver *sdp); - bool_t sd_lld_interrupt_pending(void); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_SERIAL */ - -#endif /* _SERIAL_LLD_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/GPIOv1/pal_lld.c b/firmware/chibios/os/hal/platforms/STM32/GPIOv1/pal_lld.c deleted file mode 100644 index f442dee7f7..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/GPIOv1/pal_lld.c +++ /dev/null @@ -1,184 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/GPIOv1/pal_lld.c - * @brief STM32F1xx GPIO low level driver code. - * - * @addtogroup PAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#if STM32_HAS_GPIOG -#define APB2_EN_MASK (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | \ - RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | \ - RCC_APB2ENR_IOPEEN | RCC_APB2ENR_IOPFEN | \ - RCC_APB2ENR_IOPGEN | RCC_APB2ENR_AFIOEN) -#elif STM32_HAS_GPIOE -#define APB2_EN_MASK (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | \ - RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | \ - RCC_APB2ENR_IOPEEN | RCC_APB2ENR_AFIOEN) -#else -#define APB2_EN_MASK (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | \ - RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | \ - RCC_APB2ENR_AFIOEN) -#endif - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief STM32 I/O ports configuration. - * @details Ports A-D(E, F, G) clocks enabled, AFIO clock enabled. - * - * @param[in] config the STM32 ports configuration - * - * @notapi - */ -void _pal_lld_init(const PALConfig *config) { - - /* - * Enables the GPIO related clocks. - */ - rccEnableAPB2(APB2_EN_MASK, FALSE); - - /* - * Initial GPIO setup. - */ - GPIOA->ODR = config->PAData.odr; - GPIOA->CRH = config->PAData.crh; - GPIOA->CRL = config->PAData.crl; - GPIOB->ODR = config->PBData.odr; - GPIOB->CRH = config->PBData.crh; - GPIOB->CRL = config->PBData.crl; - GPIOC->ODR = config->PCData.odr; - GPIOC->CRH = config->PCData.crh; - GPIOC->CRL = config->PCData.crl; - GPIOD->ODR = config->PDData.odr; - GPIOD->CRH = config->PDData.crh; - GPIOD->CRL = config->PDData.crl; -#if STM32_HAS_GPIOE || defined(__DOXYGEN__) - GPIOE->ODR = config->PEData.odr; - GPIOE->CRH = config->PEData.crh; - GPIOE->CRL = config->PEData.crl; -#if STM32_HAS_GPIOF || defined(__DOXYGEN__) - GPIOF->ODR = config->PFData.odr; - GPIOF->CRH = config->PFData.crh; - GPIOF->CRL = config->PFData.crl; -#if STM32_HAS_GPIOG || defined(__DOXYGEN__) - GPIOG->ODR = config->PGData.odr; - GPIOG->CRH = config->PGData.crh; - GPIOG->CRL = config->PGData.crl; -#endif -#endif -#endif -} - -/** - * @brief Pads mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output at 2MHz. - * @note Writing on pads programmed as pull-up or pull-down has the side - * effect to modify the resistor setting because the output latched - * data is used for the resistor selection. - * - * @param[in] port the port identifier - * @param[in] mask the group mask - * @param[in] mode the mode - * - * @notapi - */ -void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - iomode_t mode) { - static const uint8_t cfgtab[] = { - 4, /* PAL_MODE_RESET, implemented as input.*/ - 2, /* PAL_MODE_UNCONNECTED, implemented as push pull output 2MHz.*/ - 4, /* PAL_MODE_INPUT */ - 8, /* PAL_MODE_INPUT_PULLUP */ - 8, /* PAL_MODE_INPUT_PULLDOWN */ - 0, /* PAL_MODE_INPUT_ANALOG */ - 3, /* PAL_MODE_OUTPUT_PUSHPULL, 50MHz.*/ - 7, /* PAL_MODE_OUTPUT_OPENDRAIN, 50MHz.*/ - 8, /* Reserved.*/ - 8, /* Reserved.*/ - 8, /* Reserved.*/ - 8, /* Reserved.*/ - 8, /* Reserved.*/ - 8, /* Reserved.*/ - 8, /* Reserved.*/ - 8, /* Reserved.*/ - 0xB, /* PAL_MODE_STM32_ALTERNATE_PUSHPULL, 50MHz.*/ - 0xF, /* PAL_MODE_STM32_ALTERNATE_OPENDRAIN, 50MHz.*/ - }; - uint32_t mh, ml, crh, crl, cfg; - unsigned i; - - if (mode == PAL_MODE_INPUT_PULLUP) - port->BSRR = mask; - else if (mode == PAL_MODE_INPUT_PULLDOWN) - port->BRR = mask; - cfg = cfgtab[mode]; - mh = ml = crh = crl = 0; - for (i = 0; i < 8; i++) { - ml <<= 4; - mh <<= 4; - crl <<= 4; - crh <<= 4; - if ((mask & 0x0080) == 0) - ml |= 0xf; - else - crl |= cfg; - if ((mask & 0x8000) == 0) - mh |= 0xf; - else - crh |= cfg; - mask <<= 1; - } - port->CRH = (port->CRH & mh) | crh; - port->CRL = (port->CRL & ml) | crl; -} - -#endif /* HAL_USE_PAL */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/GPIOv1/pal_lld.h b/firmware/chibios/os/hal/platforms/STM32/GPIOv1/pal_lld.h deleted file mode 100644 index 3beae53499..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/GPIOv1/pal_lld.h +++ /dev/null @@ -1,334 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/GPIOv1/pal_lld.h - * @brief STM32F1xx GPIO low level driver header. - * - * @addtogroup PAL - * @{ - */ - -#ifndef _PAL_LLD_H_ -#define _PAL_LLD_H_ - -#if HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Unsupported modes and specific modes */ -/*===========================================================================*/ - -/** - * @name STM32-specific I/O mode flags - * @{ - */ -/** - * @brief STM32 specific alternate push-pull output mode. - */ -#define PAL_MODE_STM32_ALTERNATE_PUSHPULL 16 - -/** - * @brief STM32 specific alternate open-drain output mode. - */ -#define PAL_MODE_STM32_ALTERNATE_OPENDRAIN 17 -/** @} */ - -/*===========================================================================*/ -/* I/O Ports Types and constants. */ -/*===========================================================================*/ - -/** - * @brief GPIO port setup info. - */ -typedef struct { - /** Initial value for ODR register.*/ - uint32_t odr; - /** Initial value for CRL register.*/ - uint32_t crl; - /** Initial value for CRH register.*/ - uint32_t crh; -} stm32_gpio_setup_t; - -/** - * @brief STM32 GPIO static initializer. - * @details An instance of this structure must be passed to @p palInit() at - * system startup time in order to initialize the digital I/O - * subsystem. This represents only the initial setup, specific pads - * or whole ports can be reprogrammed at later time. - */ -typedef struct { - /** @brief Port A setup data.*/ - stm32_gpio_setup_t PAData; - /** @brief Port B setup data.*/ - stm32_gpio_setup_t PBData; - /** @brief Port C setup data.*/ - stm32_gpio_setup_t PCData; - /** @brief Port D setup data.*/ - stm32_gpio_setup_t PDData; -#if STM32_HAS_GPIOE || defined(__DOXYGEN__) - /** @brief Port E setup data.*/ - stm32_gpio_setup_t PEData; -#if STM32_HAS_GPIOF || defined(__DOXYGEN__) - /** @brief Port F setup data.*/ - stm32_gpio_setup_t PFData; -#if STM32_HAS_GPIOG || defined(__DOXYGEN__) - /** @brief Port G setup data.*/ - stm32_gpio_setup_t PGData; -#endif -#endif -#endif -} PALConfig; - -/** - * @brief Width, in bits, of an I/O port. - */ -#define PAL_IOPORTS_WIDTH 16 - -/** - * @brief Whole port mask. - * @details This macro specifies all the valid bits into a port. - */ -#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF) - -/** - * @brief Digital I/O port sized unsigned type. - */ -typedef uint32_t ioportmask_t; - -/** - * @brief Digital I/O modes. - */ -typedef uint32_t iomode_t; - -/** - * @brief Port Identifier. - * @details This type can be a scalar or some kind of pointer, do not make - * any assumption about it, use the provided macros when populating - * variables of this type. - */ -typedef GPIO_TypeDef * ioportid_t; - -/*===========================================================================*/ -/* I/O Ports Identifiers. */ -/* The low level driver wraps the definitions already present in the STM32 */ -/* firmware library. */ -/*===========================================================================*/ - -/** - * @brief GPIO port A identifier. - */ -#if STM32_HAS_GPIOA || defined(__DOXYGEN__) -#define IOPORT1 GPIOA -#endif - -/** - * @brief GPIO port B identifier. - */ -#if STM32_HAS_GPIOB || defined(__DOXYGEN__) -#define IOPORT2 GPIOB -#endif - -/** - * @brief GPIO port C identifier. - */ -#if STM32_HAS_GPIOC || defined(__DOXYGEN__) -#define IOPORT3 GPIOC -#endif - -/** - * @brief GPIO port D identifier. - */ -#if STM32_HAS_GPIOD || defined(__DOXYGEN__) -#define IOPORT4 GPIOD -#endif - -/** - * @brief GPIO port E identifier. - */ -#if STM32_HAS_GPIOE || defined(__DOXYGEN__) -#define IOPORT5 GPIOE -#endif - -/** - * @brief GPIO port F identifier. - */ -#if STM32_HAS_GPIOF || defined(__DOXYGEN__) -#define IOPORT6 GPIOF -#endif - -/** - * @brief GPIO port G identifier. - */ -#if STM32_HAS_GPIOG || defined(__DOXYGEN__) -#define IOPORT7 GPIOG -#endif - -/*===========================================================================*/ -/* Implementation, some of the following macros could be implemented as */ -/* functions, if so please put them in pal_lld.c. */ -/*===========================================================================*/ - -/** - * @brief GPIO ports subsystem initialization. - * - * @notapi - */ -#define pal_lld_init(config) _pal_lld_init(config) - -/** - * @brief Reads an I/O port. - * @details This function is implemented by reading the GPIO IDR register, the - * implementation has no side effects. - * @note This function is not meant to be invoked directly by the application - * code. - * - * @param[in] port port identifier - * @return The port bits. - * - * @notapi - */ -#define pal_lld_readport(port) ((port)->IDR) - -/** - * @brief Reads the output latch. - * @details This function is implemented by reading the GPIO ODR register, the - * implementation has no side effects. - * @note This function is not meant to be invoked directly by the application - * code. - * - * @param[in] port port identifier - * @return The latched logical states. - * - * @notapi - */ -#define pal_lld_readlatch(port) ((port)->ODR) - -/** - * @brief Writes on a I/O port. - * @details This function is implemented by writing the GPIO ODR register, the - * implementation has no side effects. - * @note Writing on pads programmed as pull-up or pull-down has the side - * effect to modify the resistor setting because the output latched - * data is used for the resistor selection. - * - * @param[in] port port identifier - * @param[in] bits bits to be written on the specified port - * - * @notapi - */ -#define pal_lld_writeport(port, bits) ((port)->ODR = (bits)) - -/** - * @brief Sets a bits mask on a I/O port. - * @details This function is implemented by writing the GPIO BSRR register, the - * implementation has no side effects. - * @note Writing on pads programmed as pull-up or pull-down has the side - * effect to modify the resistor setting because the output latched - * data is used for the resistor selection. - * - * @param[in] port port identifier - * @param[in] bits bits to be ORed on the specified port - * - * @notapi - */ -#define pal_lld_setport(port, bits) ((port)->BSRR = (bits)) - -/** - * @brief Clears a bits mask on a I/O port. - * @details This function is implemented by writing the GPIO BRR register, the - * implementation has no side effects. - * @note Writing on pads programmed as pull-up or pull-down has the side - * effect to modify the resistor setting because the output latched - * data is used for the resistor selection. - * - * @param[in] port port identifier - * @param[in] bits bits to be cleared on the specified port - * - * @notapi - */ -#define pal_lld_clearport(port, bits) ((port)->BRR = (bits)) - -/** - * @brief Writes a group of bits. - * @details This function is implemented by writing the GPIO BSRR register, the - * implementation has no side effects. - * @note Writing on pads programmed as pull-up or pull-down has the side - * effect to modify the resistor setting because the output latched - * data is used for the resistor selection. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] offset the group bit offset within the port - * @param[in] bits bits to be written. Values exceeding the group - * width are masked. - * - * @notapi - */ -#define pal_lld_writegroup(port, mask, offset, bits) \ - ((port)->BSRR = ((~(bits) & (mask)) << (16 + (offset))) | \ - (((bits) & (mask)) << (offset))) - -/** - * @brief Pads group mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * @note Writing on pads programmed as pull-up or pull-down has the side - * effect to modify the resistor setting because the output latched - * data is used for the resistor selection. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] offset group bit offset within the port - * @param[in] mode group mode - * - * @notapi - */ -#define pal_lld_setgroupmode(port, mask, offset, mode) \ - _pal_lld_setgroupmode(port, mask << offset, mode) - -/** - * @brief Writes a logical state on an output pad. - * @note Writing on pads programmed as pull-up or pull-down has the side - * effect to modify the resistor setting because the output latched - * data is used for the resistor selection. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * @param[in] bit logical value, the value must be @p PAL_LOW or - * @p PAL_HIGH - * - * @notapi - */ -#define pal_lld_writepad(port, pad, bit) pal_lld_writegroup(port, 1, pad, bit) - -extern const PALConfig pal_default_config; - -#ifdef __cplusplus -extern "C" { -#endif - void _pal_lld_init(const PALConfig *config); - void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - iomode_t mode); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_PAL */ - -#endif /* _PAL_LLD_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/GPIOv2/pal_lld.c b/firmware/chibios/os/hal/platforms/STM32/GPIOv2/pal_lld.c deleted file mode 100644 index 2405c3cd84..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/GPIOv2/pal_lld.c +++ /dev/null @@ -1,261 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/GPIOv2/pal_lld.c - * @brief STM32L1xx/STM32F2xx/STM32F4xx GPIO low level driver code. - * - * @addtogroup PAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#if defined(STM32L1XX) -#define AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | \ - RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | \ - RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIOHEN) -#define AHB_LPEN_MASK AHB_EN_MASK - -#elif defined(STM32F030) || defined(STM32F0XX_MD) -#define AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | \ - RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | \ - RCC_AHBENR_GPIOFEN) - -#elif defined(STM32F0XX_LD) -#define AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | \ - RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIOFEN) - -#elif defined(STM32F2XX) -#define AHB1_EN_MASK (RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | \ - RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | \ - RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | \ - RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | \ - RCC_AHB1ENR_GPIOIEN) -#define AHB1_LPEN_MASK AHB1_EN_MASK - -#elif defined(STM32F30X) || defined(STM32F37X) -#define AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | \ - RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | \ - RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIOFEN) - -#elif defined(STM32F4XX) -#if STM32_HAS_GPIOF && STM32_HAS_GPIOG && STM32_HAS_GPIOI -#define AHB1_EN_MASK (RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | \ - RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | \ - RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | \ - RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | \ - RCC_AHB1ENR_GPIOIEN) -#else -#define AHB1_EN_MASK (RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | \ - RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | \ - RCC_AHB1ENR_GPIOEEN) -#endif /* STM32_HAS_GPIOF && STM32_HAS_GPIOG && STM32_HAS_GPIOI */ -#define AHB1_LPEN_MASK AHB1_EN_MASK - -#else -#error "missing or unsupported platform for GPIOv2 PAL driver" -#endif - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void initgpio(GPIO_TypeDef *gpiop, const stm32_gpio_setup_t *config) { - - gpiop->OTYPER = config->otyper; - gpiop->OSPEEDR = config->ospeedr; - gpiop->PUPDR = config->pupdr; - gpiop->ODR = config->odr; - gpiop->AFRL = config->afrl; - gpiop->AFRH = config->afrh; - gpiop->MODER = config->moder; -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief STM32 I/O ports configuration. - * @details Ports A-D(E, F, G, H) clocks enabled. - * - * @param[in] config the STM32 ports configuration - * - * @notapi - */ -void _pal_lld_init(const PALConfig *config) { - - /* - * Enables the GPIO related clocks. - */ -#if defined(STM32L1XX) - rccEnableAHB(AHB_EN_MASK, TRUE); - RCC->AHBLPENR |= AHB_LPEN_MASK; -#elif defined(STM32F0XX) - rccEnableAHB(AHB_EN_MASK, TRUE); -#elif defined(STM32F30X) || defined(STM32F37X) - rccEnableAHB(AHB_EN_MASK, TRUE); -#elif defined(STM32F2XX) || defined(STM32F4XX) - RCC->AHB1ENR |= AHB1_EN_MASK; - RCC->AHB1LPENR |= AHB1_LPEN_MASK; -#endif - - /* - * Initial GPIO setup. - */ -#if STM32_HAS_GPIOA - initgpio(GPIOA, &config->PAData); -#endif -#if STM32_HAS_GPIOB - initgpio(GPIOB, &config->PBData); -#endif -#if STM32_HAS_GPIOC - initgpio(GPIOC, &config->PCData); -#endif -#if STM32_HAS_GPIOD - initgpio(GPIOD, &config->PDData); -#endif -#if STM32_HAS_GPIOE - initgpio(GPIOE, &config->PEData); -#endif -#if STM32_HAS_GPIOF - initgpio(GPIOF, &config->PFData); -#endif -#if STM32_HAS_GPIOG - initgpio(GPIOG, &config->PGData); -#endif -#if STM32_HAS_GPIOH - initgpio(GPIOH, &config->PHData); -#endif -#if STM32_HAS_GPIOI - initgpio(GPIOI, &config->PIData); -#endif -} - -/** - * @brief Pads mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * @note @p PAL_MODE_UNCONNECTED is implemented as push pull at minimum - * speed. - * - * @param[in] port the port identifier - * @param[in] mask the group mask - * @param[in] mode the mode - * - * @notapi - */ -#if 1 -void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - iomode_t mode) { - - uint32_t moder = (mode & PAL_STM32_MODE_MASK) >> 0; - uint32_t otyper = (mode & PAL_STM32_OTYPE_MASK) >> 2; - uint32_t ospeedr = (mode & PAL_STM32_OSPEED_MASK) >> 3; - uint32_t pupdr = (mode & PAL_STM32_PUDR_MASK) >> 5; - uint32_t altr = (mode & PAL_STM32_ALTERNATE_MASK) >> 7; - uint32_t bit = 0; - while (TRUE) { - if ((mask & 1) != 0) { - uint32_t altrmask, m1, m2, m4; - - altrmask = altr << ((bit & 7) * 4); - m4 = 15 << ((bit & 7) * 4); - if (bit < 8) - port->AFRL = (port->AFRL & ~m4) | altrmask; - else - port->AFRH = (port->AFRH & ~m4) | altrmask; - m1 = 1 << bit; - port->OTYPER = (port->OTYPER & ~m1) | otyper; - m2 = 3 << (bit * 2); - port->OSPEEDR = (port->OSPEEDR & ~m2) | ospeedr; - port->PUPDR = (port->PUPDR & ~m2) | pupdr; - port->MODER = (port->MODER & ~m2) | moder; - } - mask >>= 1; - if (!mask) - return; - otyper <<= 1; - ospeedr <<= 2; - pupdr <<= 2; - moder <<= 2; - bit++; - } -} -#else -void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - iomode_t mode) { - uint32_t afrm, moderm, pupdrm, otyperm, ospeedrm; - uint32_t m1 = (uint32_t)mask; - uint32_t m2 = 0; - uint32_t m4l = 0; - uint32_t m4h = 0; - uint32_t bit = 0; - do { - if ((mask & 1) != 0) { - m2 |= 3 << bit; - if (bit < 16) - m4l |= 15 << ((bit & 14) * 2); - else - m4h |= 15 << ((bit & 14) * 2); - } - bit += 2; - mask >>= 1; - } while (mask); - - afrm = ((mode & PAL_STM32_ALTERNATE_MASK) >> 7) * 0x1111; - port->AFRL = (port->AFRL & ~m4l) | (afrm & m4l); - port->AFRH = (port->AFRH & ~m4h) | (afrm & m4h); - - ospeedrm = ((mode & PAL_STM32_OSPEED_MASK) >> 3) * 0x5555; - port->OSPEEDR = (port->OSPEEDR & ~m2) | (ospeedrm & m2); - - otyperm = ((mode & PAL_STM32_OTYPE_MASK) >> 2) * 0xffff; - port->OTYPER = (port->OTYPER & ~m1) | (otyperm & m1); - - pupdrm = ((mode & PAL_STM32_PUDR_MASK) >> 5) * 0x5555; - port->PUPDR = (port->PUPDR & ~m2) | (pupdrm & m2); - - moderm = ((mode & PAL_STM32_MODE_MASK) >> 0) * 0x5555; - port->MODER = (port->MODER & ~m2) | (moderm & m2); -} -#endif - -#endif /* HAL_USE_PAL */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/GPIOv2/pal_lld.h b/firmware/chibios/os/hal/platforms/STM32/GPIOv2/pal_lld.h deleted file mode 100644 index acc6874af8..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/GPIOv2/pal_lld.h +++ /dev/null @@ -1,461 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/GPIOv2/pal_lld.h - * @brief STM32L1xx/STM32F2xx/STM32F4xx GPIO low level driver header. - * - * @addtogroup PAL - * @{ - */ - -#ifndef _PAL_LLD_H_ -#define _PAL_LLD_H_ - -#if HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Unsupported modes and specific modes */ -/*===========================================================================*/ - -#undef PAL_MODE_RESET -#undef PAL_MODE_UNCONNECTED -#undef PAL_MODE_INPUT -#undef PAL_MODE_INPUT_PULLUP -#undef PAL_MODE_INPUT_PULLDOWN -#undef PAL_MODE_INPUT_ANALOG -#undef PAL_MODE_OUTPUT_PUSHPULL -#undef PAL_MODE_OUTPUT_OPENDRAIN - -/** - * @name STM32-specific I/O mode flags - * @{ - */ -#define PAL_STM32_MODE_MASK (3 << 0) -#define PAL_STM32_MODE_INPUT (0 << 0) -#define PAL_STM32_MODE_OUTPUT (1 << 0) -#define PAL_STM32_MODE_ALTERNATE (2 << 0) -#define PAL_STM32_MODE_ANALOG (3 << 0) - -#define PAL_STM32_OTYPE_MASK (1 << 2) -#define PAL_STM32_OTYPE_PUSHPULL (0 << 2) -#define PAL_STM32_OTYPE_OPENDRAIN (1 << 2) - -#define PAL_STM32_OSPEED_MASK (3 << 3) -#define PAL_STM32_OSPEED_LOWEST (0 << 3) -#if defined(STM32F0XX) || defined(STM32F30X) || defined(STM32F37X) -#define PAL_STM32_OSPEED_MID (1 << 3) -#else -#define PAL_STM32_OSPEED_MID1 (1 << 3) -#define PAL_STM32_OSPEED_MID2 (2 << 3) -#endif -#define PAL_STM32_OSPEED_HIGHEST (3 << 3) - -#define PAL_STM32_PUDR_MASK (3 << 5) -#define PAL_STM32_PUDR_FLOATING (0 << 5) -#define PAL_STM32_PUDR_PULLUP (1 << 5) -#define PAL_STM32_PUDR_PULLDOWN (2 << 5) - -#define PAL_STM32_ALTERNATE_MASK (15 << 7) -#define PAL_STM32_ALTERNATE(n) ((n) << 7) - -/** - * @brief Alternate function. - * - * @param[in] n alternate function selector - */ -#define PAL_MODE_ALTERNATE(n) (PAL_STM32_MODE_ALTERNATE | \ - PAL_STM32_ALTERNATE(n)) -/** @} */ - -/** - * @name Standard I/O mode flags - * @{ - */ -/** - * @brief This mode is implemented as input. - */ -#define PAL_MODE_RESET PAL_STM32_MODE_INPUT - -/** - * @brief This mode is implemented as input with pull-up. - */ -#define PAL_MODE_UNCONNECTED PAL_MODE_INPUT_PULLUP - -/** - * @brief Regular input high-Z pad. - */ -#define PAL_MODE_INPUT PAL_STM32_MODE_INPUT - -/** - * @brief Input pad with weak pull up resistor. - */ -#define PAL_MODE_INPUT_PULLUP (PAL_STM32_MODE_INPUT | \ - PAL_STM32_PUDR_PULLUP) - -/** - * @brief Input pad with weak pull down resistor. - */ -#define PAL_MODE_INPUT_PULLDOWN (PAL_STM32_MODE_INPUT | \ - PAL_STM32_PUDR_PULLDOWN) - -/** - * @brief Analog input mode. - */ -#define PAL_MODE_INPUT_ANALOG PAL_STM32_MODE_ANALOG - -/** - * @brief Push-pull output pad. - */ -#define PAL_MODE_OUTPUT_PUSHPULL (PAL_STM32_MODE_OUTPUT | \ - PAL_STM32_OTYPE_PUSHPULL) - -/** - * @brief Open-drain output pad. - */ -#define PAL_MODE_OUTPUT_OPENDRAIN (PAL_STM32_MODE_OUTPUT | \ - PAL_STM32_OTYPE_OPENDRAIN) -/** @} */ - -/*===========================================================================*/ -/* I/O Ports Types and constants. */ -/*===========================================================================*/ - -/** - * @brief STM32 GPIO registers block. - */ -typedef struct { - - volatile uint32_t MODER; - volatile uint32_t OTYPER; - volatile uint32_t OSPEEDR; - volatile uint32_t PUPDR; - volatile uint32_t IDR; - volatile uint32_t ODR; - volatile union { - uint32_t W; - struct { - uint16_t set; - uint16_t clear; - } H; - } BSRR; - volatile uint32_t LCKR; - volatile uint32_t AFRL; - volatile uint32_t AFRH; -} GPIO_TypeDef; - -/** - * @brief GPIO port setup info. - */ -typedef struct { - /** Initial value for MODER register.*/ - uint32_t moder; - /** Initial value for OTYPER register.*/ - uint32_t otyper; - /** Initial value for OSPEEDR register.*/ - uint32_t ospeedr; - /** Initial value for PUPDR register.*/ - uint32_t pupdr; - /** Initial value for ODR register.*/ - uint32_t odr; - /** Initial value for AFRL register.*/ - uint32_t afrl; - /** Initial value for AFRH register.*/ - uint32_t afrh; -} stm32_gpio_setup_t; - -/** - * @brief STM32 GPIO static initializer. - * @details An instance of this structure must be passed to @p palInit() at - * system startup time in order to initialize the digital I/O - * subsystem. This represents only the initial setup, specific pads - * or whole ports can be reprogrammed at later time. - */ -typedef struct { -#if STM32_HAS_GPIOA || defined(__DOXYGEN__) - /** @brief Port A setup data.*/ - stm32_gpio_setup_t PAData; -#endif -#if STM32_HAS_GPIOB || defined(__DOXYGEN__) - /** @brief Port B setup data.*/ - stm32_gpio_setup_t PBData; -#endif -#if STM32_HAS_GPIOC || defined(__DOXYGEN__) - /** @brief Port C setup data.*/ - stm32_gpio_setup_t PCData; -#endif -#if STM32_HAS_GPIOD || defined(__DOXYGEN__) - /** @brief Port D setup data.*/ - stm32_gpio_setup_t PDData; -#endif -#if STM32_HAS_GPIOE || defined(__DOXYGEN__) - /** @brief Port E setup data.*/ - stm32_gpio_setup_t PEData; -#endif -#if STM32_HAS_GPIOF || defined(__DOXYGEN__) - /** @brief Port F setup data.*/ - stm32_gpio_setup_t PFData; -#endif -#if STM32_HAS_GPIOG || defined(__DOXYGEN__) - /** @brief Port G setup data.*/ - stm32_gpio_setup_t PGData; -#endif -#if STM32_HAS_GPIOH || defined(__DOXYGEN__) - /** @brief Port H setup data.*/ - stm32_gpio_setup_t PHData; -#endif -#if STM32_HAS_GPIOI || defined(__DOXYGEN__) - /** @brief Port I setup data.*/ - stm32_gpio_setup_t PIData; -#endif -} PALConfig; - -/** - * @brief Width, in bits, of an I/O port. - */ -#define PAL_IOPORTS_WIDTH 16 - -/** - * @brief Whole port mask. - * @details This macro specifies all the valid bits into a port. - */ -#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF) - -/** - * @brief Digital I/O port sized unsigned type. - */ -typedef uint32_t ioportmask_t; - -/** - * @brief Digital I/O modes. - */ -typedef uint32_t iomode_t; - -/** - * @brief Port Identifier. - * @details This type can be a scalar or some kind of pointer, do not make - * any assumption about it, use the provided macros when populating - * variables of this type. - */ -typedef GPIO_TypeDef * ioportid_t; - -/*===========================================================================*/ -/* I/O Ports Identifiers. */ -/* The low level driver wraps the definitions already present in the STM32 */ -/* firmware library. */ -/*===========================================================================*/ - -/** - * @brief GPIO port A identifier. - */ -#if STM32_HAS_GPIOA || defined(__DOXYGEN__) -#define IOPORT1 GPIOA -#endif - -/** - * @brief GPIO port B identifier. - */ -#if STM32_HAS_GPIOB || defined(__DOXYGEN__) -#define IOPORT2 GPIOB -#endif - -/** - * @brief GPIO port C identifier. - */ -#if STM32_HAS_GPIOC || defined(__DOXYGEN__) -#define IOPORT3 GPIOC -#endif - -/** - * @brief GPIO port D identifier. - */ -#if STM32_HAS_GPIOD || defined(__DOXYGEN__) -#define IOPORT4 GPIOD -#endif - -/** - * @brief GPIO port E identifier. - */ -#if STM32_HAS_GPIOE || defined(__DOXYGEN__) -#define IOPORT5 GPIOE -#endif - -/** - * @brief GPIO port F identifier. - */ -#if STM32_HAS_GPIOF || defined(__DOXYGEN__) -#define IOPORT6 GPIOF -#endif - -/** - * @brief GPIO port G identifier. - */ -#if STM32_HAS_GPIOG || defined(__DOXYGEN__) -#define IOPORT7 GPIOG -#endif - -/** - * @brief GPIO port H identifier. - */ -#if STM32_HAS_GPIOH || defined(__DOXYGEN__) -#define IOPORT8 GPIOH -#endif - -/** - * @brief GPIO port I identifier. - */ -#if STM32_HAS_GPIOI || defined(__DOXYGEN__) -#define IOPORT9 GPIOI -#endif - -/*===========================================================================*/ -/* Implementation, some of the following macros could be implemented as */ -/* functions, if so please put them in pal_lld.c. */ -/*===========================================================================*/ - -/** - * @brief GPIO ports subsystem initialization. - * - * @notapi - */ -#define pal_lld_init(config) _pal_lld_init(config) - -/** - * @brief Reads an I/O port. - * @details This function is implemented by reading the GPIO IDR register, the - * implementation has no side effects. - * @note This function is not meant to be invoked directly by the application - * code. - * - * @param[in] port port identifier - * @return The port bits. - * - * @notapi - */ -#define pal_lld_readport(port) ((port)->IDR) - -/** - * @brief Reads the output latch. - * @details This function is implemented by reading the GPIO ODR register, the - * implementation has no side effects. - * @note This function is not meant to be invoked directly by the application - * code. - * - * @param[in] port port identifier - * @return The latched logical states. - * - * @notapi - */ -#define pal_lld_readlatch(port) ((port)->ODR) - -/** - * @brief Writes on a I/O port. - * @details This function is implemented by writing the GPIO ODR register, the - * implementation has no side effects. - * - * @param[in] port port identifier - * @param[in] bits bits to be written on the specified port - * - * @notapi - */ -#define pal_lld_writeport(port, bits) ((port)->ODR = (bits)) - -/** - * @brief Sets a bits mask on a I/O port. - * @details This function is implemented by writing the GPIO BSRR register, the - * implementation has no side effects. - * - * @param[in] port port identifier - * @param[in] bits bits to be ORed on the specified port - * - * @notapi - */ -#define pal_lld_setport(port, bits) ((port)->BSRR.H.set = (uint16_t)(bits)) - -/** - * @brief Clears a bits mask on a I/O port. - * @details This function is implemented by writing the GPIO BSRR register, the - * implementation has no side effects. - * - * @param[in] port port identifier - * @param[in] bits bits to be cleared on the specified port - * - * @notapi - */ -#define pal_lld_clearport(port, bits) ((port)->BSRR.H.clear = (uint16_t)(bits)) - -/** - * @brief Writes a group of bits. - * @details This function is implemented by writing the GPIO BSRR register, the - * implementation has no side effects. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] offset the group bit offset within the port - * @param[in] bits bits to be written. Values exceeding the group - * width are masked. - * - * @notapi - */ -#define pal_lld_writegroup(port, mask, offset, bits) \ - ((port)->BSRR.W = ((~(bits) & (mask)) << (16 + (offset))) | \ - (((bits) & (mask)) << (offset))) - -/** - * @brief Pads group mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] offset group bit offset within the port - * @param[in] mode group mode - * - * @notapi - */ -#define pal_lld_setgroupmode(port, mask, offset, mode) \ - _pal_lld_setgroupmode(port, mask << offset, mode) - -/** - * @brief Writes a logical state on an output pad. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * @param[in] bit logical value, the value must be @p PAL_LOW or - * @p PAL_HIGH - * - * @notapi - */ -#define pal_lld_writepad(port, pad, bit) pal_lld_writegroup(port, 1, pad, bit) - -extern const PALConfig pal_default_config; - -#ifdef __cplusplus -extern "C" { -#endif - void _pal_lld_init(const PALConfig *config); - void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - iomode_t mode); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_PAL */ - -#endif /* _PAL_LLD_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/I2Cv1/i2c_lld.c b/firmware/chibios/os/hal/platforms/STM32/I2Cv1/i2c_lld.c deleted file mode 100644 index 1ecfaa1154..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/I2Cv1/i2c_lld.c +++ /dev/null @@ -1,914 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Concepts and parts of this file have been contributed by Uladzimir Pylinsky - aka barthess. - */ - -/** - * @file STM32/I2Cv1/i2c_lld.c - * @brief STM32 I2C subsystem low level driver source. - * - * @addtogroup I2C - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_I2C || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define I2C1_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_RX_DMA_STREAM, \ - STM32_I2C1_RX_DMA_CHN) - -#define I2C1_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_TX_DMA_STREAM, \ - STM32_I2C1_TX_DMA_CHN) - -#define I2C2_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_I2C_I2C2_RX_DMA_STREAM, \ - STM32_I2C2_RX_DMA_CHN) - -#define I2C2_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_I2C_I2C2_TX_DMA_STREAM, \ - STM32_I2C2_TX_DMA_CHN) - -#define I2C3_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_I2C_I2C3_RX_DMA_STREAM, \ - STM32_I2C3_RX_DMA_CHN) - -#define I2C3_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_I2C_I2C3_TX_DMA_STREAM, \ - STM32_I2C3_TX_DMA_CHN) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#define I2C_EV5_MASTER_MODE_SELECT \ - ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY) << 16) | I2C_SR1_SB)) - -#define I2C_EV6_MASTER_TRA_MODE_SELECTED \ - ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY | I2C_SR2_TRA) << 16) | \ - I2C_SR1_ADDR | I2C_SR1_TXE)) - -#define I2C_EV6_MASTER_REC_MODE_SELECTED \ - ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY)<< 16) | I2C_SR1_ADDR)) - -#define I2C_EV8_2_MASTER_BYTE_TRANSMITTED \ - ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY | I2C_SR2_TRA) << 16) | \ - I2C_SR1_BTF | I2C_SR1_TXE)) - -#define I2C_EV9_MASTER_ADD10 \ - ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY) << 16) | I2C_SR1_ADD10)) - -#define I2C_EV_MASK 0x00FFFFFF - -#define I2C_ERROR_MASK \ - ((uint16_t)(I2C_SR1_BERR | I2C_SR1_ARLO | I2C_SR1_AF | I2C_SR1_OVR | \ - I2C_SR1_PECERR | I2C_SR1_TIMEOUT | I2C_SR1_SMBALERT)) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief I2C1 driver identifier.*/ -#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__) -I2CDriver I2CD1; -#endif - -/** @brief I2C2 driver identifier.*/ -#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__) -I2CDriver I2CD2; -#endif - -/** @brief I2C3 driver identifier.*/ -#if STM32_I2C_USE_I2C3 || defined(__DOXYGEN__) -I2CDriver I2CD3; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Wakes up the waiting thread. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] msg wakeup message - * - * @notapi - */ -#define wakeup_isr(i2cp, msg) { \ - chSysLockFromIsr(); \ - if ((i2cp)->thread != NULL) { \ - Thread *tp = (i2cp)->thread; \ - (i2cp)->thread = NULL; \ - tp->p_u.rdymsg = (msg); \ - chSchReadyI(tp); \ - } \ - chSysUnlockFromIsr(); \ -} - -/** - * @brief Aborts an I2C transaction. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -static void i2c_lld_abort_operation(I2CDriver *i2cp) { - I2C_TypeDef *dp = i2cp->i2c; - - /* Stops the I2C peripheral.*/ - dp->CR1 = I2C_CR1_SWRST; - dp->CR1 = 0; - dp->CR2 = 0; - dp->SR1 = 0; - - /* Stops the associated DMA streams.*/ - dmaStreamDisable(i2cp->dmatx); - dmaStreamDisable(i2cp->dmarx); -} - -/** - * @brief Handling of stalled I2C transactions. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -static void i2c_lld_safety_timeout(void *p) { - I2CDriver *i2cp = (I2CDriver *)p; - - chSysLockFromIsr(); - if (i2cp->thread) { - Thread *tp = i2cp->thread; - i2c_lld_abort_operation(i2cp); - i2cp->thread = NULL; - tp->p_u.rdymsg = RDY_TIMEOUT; - chSchReadyI(tp); - } - chSysUnlockFromIsr(); -} - -/** - * @brief Set clock speed. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -static void i2c_lld_set_clock(I2CDriver *i2cp) { - I2C_TypeDef *dp = i2cp->i2c; - uint16_t regCCR, clock_div; - int32_t clock_speed = i2cp->config->clock_speed; - i2cdutycycle_t duty = i2cp->config->duty_cycle; - - chDbgCheck((i2cp != NULL) && (clock_speed > 0) && (clock_speed <= 4000000), - "i2c_lld_set_clock"); - - /* CR2 Configuration.*/ - dp->CR2 &= (uint16_t)~I2C_CR2_FREQ; - dp->CR2 |= (uint16_t)I2C_CLK_FREQ; - - /* CCR Configuration.*/ - regCCR = 0; - clock_div = I2C_CCR_CCR; - - if (clock_speed <= 100000) { - /* Configure clock_div in standard mode.*/ - chDbgAssert(duty == STD_DUTY_CYCLE, - "i2c_lld_set_clock(), #1", - "Invalid standard mode duty cycle"); - - /* Standard mode clock_div calculate: Tlow/Thigh = 1/1.*/ - chDbgAssert((STM32_PCLK1 % (clock_speed * 2)) == 0, - "i2c_lld_set_clock(), #2", - "PCLK1 must be divided without remainder"); - clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 2)); - - chDbgAssert(clock_div >= 0x04, - "i2c_lld_set_clock(), #3", - "Clock divider less then 0x04 not allowed"); - regCCR |= (clock_div & I2C_CCR_CCR); - - /* Sets the Maximum Rise Time for standard mode.*/ - dp->TRISE = I2C_CLK_FREQ + 1; - } - else if (clock_speed <= 400000) { - /* Configure clock_div in fast mode.*/ - chDbgAssert((duty == FAST_DUTY_CYCLE_2) || (duty == FAST_DUTY_CYCLE_16_9), - "i2c_lld_set_clock(), #4", - "Invalid fast mode duty cycle"); - - if (duty == FAST_DUTY_CYCLE_2) { - /* Fast mode clock_div calculate: Tlow/Thigh = 2/1.*/ - chDbgAssert((STM32_PCLK1 % (clock_speed * 3)) == 0, - "i2c_lld_set_clock(), #5", - "PCLK1 must be divided without remainder"); - clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 3)); - } - else if (duty == FAST_DUTY_CYCLE_16_9) { - /* Fast mode clock_div calculate: Tlow/Thigh = 16/9.*/ - chDbgAssert((STM32_PCLK1 % (clock_speed * 25)) == 0, - "i2c_lld_set_clock(), #6", - "PCLK1 must be divided without remainder"); - clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 25)); - regCCR |= I2C_CCR_DUTY; - } - - chDbgAssert(clock_div >= 0x01, - "i2c_lld_set_clock(), #7", - "Clock divider less then 0x04 not allowed"); - regCCR |= (I2C_CCR_FS | (clock_div & I2C_CCR_CCR)); - - /* Sets the Maximum Rise Time for fast mode.*/ - dp->TRISE = (I2C_CLK_FREQ * 300 / 1000) + 1; - } - - chDbgAssert((clock_div <= I2C_CCR_CCR), - "i2c_lld_set_clock(), #8", "the selected clock is too low"); - - dp->CCR = regCCR; -} - -/** - * @brief Set operation mode of I2C hardware. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -static void i2c_lld_set_opmode(I2CDriver *i2cp) { - I2C_TypeDef *dp = i2cp->i2c; - i2copmode_t opmode = i2cp->config->op_mode; - uint16_t regCR1; - - regCR1 = dp->CR1; - switch (opmode) { - case OPMODE_I2C: - regCR1 &= (uint16_t)~(I2C_CR1_SMBUS|I2C_CR1_SMBTYPE); - break; - case OPMODE_SMBUS_DEVICE: - regCR1 |= I2C_CR1_SMBUS; - regCR1 &= (uint16_t)~(I2C_CR1_SMBTYPE); - break; - case OPMODE_SMBUS_HOST: - regCR1 |= (I2C_CR1_SMBUS|I2C_CR1_SMBTYPE); - break; - } - dp->CR1 = regCR1; -} - -/** - * @brief I2C shared ISR code. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp) { - I2C_TypeDef *dp = i2cp->i2c; - uint32_t regSR2 = dp->SR2; - uint32_t event = dp->SR1; - - /* Interrupts are disabled just before dmaStreamEnable() because there - is no need of interrupts until next transaction begin. All the work is - done by the DMA.*/ - switch (I2C_EV_MASK & (event | (regSR2 << 16))) { - case I2C_EV5_MASTER_MODE_SELECT: - if ((i2cp->addr >> 8) > 0) { - /* 10-bit address: 1 1 1 1 0 X X R/W */ - dp->DR = 0xF0 | (0x6 & (i2cp->addr >> 8)) | (0x1 & i2cp->addr); - } else { - dp->DR = i2cp->addr; - } - break; - case I2C_EV9_MASTER_ADD10: - /* Set second addr byte (10-bit addressing)*/ - dp->DR = (0xFF & (i2cp->addr >> 1)); - break; - case I2C_EV6_MASTER_REC_MODE_SELECTED: - dp->CR2 &= ~I2C_CR2_ITEVTEN; - dmaStreamEnable(i2cp->dmarx); - dp->CR2 |= I2C_CR2_LAST; /* Needed in receiver mode. */ - if (dmaStreamGetTransactionSize(i2cp->dmarx) < 2) - dp->CR1 &= ~I2C_CR1_ACK; - break; - case I2C_EV6_MASTER_TRA_MODE_SELECTED: - dp->CR2 &= ~I2C_CR2_ITEVTEN; - dmaStreamEnable(i2cp->dmatx); - break; - case I2C_EV8_2_MASTER_BYTE_TRANSMITTED: - /* Catches BTF event after the end of transmission.*/ - if (dmaStreamGetTransactionSize(i2cp->dmarx) > 0) { - /* Starts "read after write" operation, LSB = 1 -> receive.*/ - i2cp->addr |= 0x01; - dp->CR1 |= I2C_CR1_START | I2C_CR1_ACK; - return; - } - dp->CR2 &= ~I2C_CR2_ITEVTEN; - dp->CR1 |= I2C_CR1_STOP; - wakeup_isr(i2cp, RDY_OK); - break; - default: - break; - } - /* Clear ADDR flag. */ - if (event & (I2C_SR1_ADDR | I2C_SR1_ADD10)) - (void)dp->SR2; -} - -/** - * @brief DMA RX end IRQ handler. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] flags pre-shifted content of the ISR register - * - * @notapi - */ -static void i2c_lld_serve_rx_end_irq(I2CDriver *i2cp, uint32_t flags) { - I2C_TypeDef *dp = i2cp->i2c; - - /* DMA errors handling.*/ -#if defined(STM32_I2C_DMA_ERROR_HOOK) - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - STM32_I2C_DMA_ERROR_HOOK(i2cp); - } -#else - (void)flags; -#endif - - dmaStreamDisable(i2cp->dmarx); - - dp->CR2 &= ~I2C_CR2_LAST; - dp->CR1 &= ~I2C_CR1_ACK; - dp->CR1 |= I2C_CR1_STOP; - wakeup_isr(i2cp, RDY_OK); -} - -/** - * @brief DMA TX end IRQ handler. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -static void i2c_lld_serve_tx_end_irq(I2CDriver *i2cp, uint32_t flags) { - I2C_TypeDef *dp = i2cp->i2c; - - /* DMA errors handling.*/ -#if defined(STM32_I2C_DMA_ERROR_HOOK) - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - STM32_I2C_DMA_ERROR_HOOK(i2cp); - } -#else - (void)flags; -#endif - - dmaStreamDisable(i2cp->dmatx); - /* Enables interrupts to catch BTF event meaning transmission part complete. - Interrupt handler will decide to generate STOP or to begin receiving part - of R/W transaction itself.*/ - dp->CR2 |= I2C_CR2_ITEVTEN; -} - -/** - * @brief I2C error handler. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] sr content of the SR1 register to be decoded - * - * @notapi - */ -static void i2c_lld_serve_error_interrupt(I2CDriver *i2cp, uint16_t sr) { - - /* Clears interrupt flags just to be safe.*/ - dmaStreamDisable(i2cp->dmatx); - dmaStreamDisable(i2cp->dmarx); - - i2cp->errors = I2CD_NO_ERROR; - - if (sr & I2C_SR1_BERR) /* Bus error. */ - i2cp->errors |= I2CD_BUS_ERROR; - - if (sr & I2C_SR1_ARLO) /* Arbitration lost. */ - i2cp->errors |= I2CD_ARBITRATION_LOST; - - if (sr & I2C_SR1_AF) { /* Acknowledge fail. */ - i2cp->i2c->CR2 &= ~I2C_CR2_ITEVTEN; - i2cp->i2c->CR1 |= I2C_CR1_STOP; /* Setting stop bit. */ - i2cp->errors |= I2CD_ACK_FAILURE; - } - - if (sr & I2C_SR1_OVR) /* Overrun. */ - i2cp->errors |= I2CD_OVERRUN; - - if (sr & I2C_SR1_TIMEOUT) /* SMBus Timeout. */ - i2cp->errors |= I2CD_TIMEOUT; - - if (sr & I2C_SR1_PECERR) /* PEC error. */ - i2cp->errors |= I2CD_PEC_ERROR; - - if (sr & I2C_SR1_SMBALERT) /* SMBus alert. */ - i2cp->errors |= I2CD_SMB_ALERT; - - /* If some error has been identified then sends wakes the waiting thread.*/ - if (i2cp->errors != I2CD_NO_ERROR) - wakeup_isr(i2cp, RDY_RESET); -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__) -/** - * @brief I2C1 event interrupt handler. - * - * @notapi - */ -CH_IRQ_HANDLER(I2C1_EV_IRQHandler) { - - CH_IRQ_PROLOGUE(); - - i2c_lld_serve_event_interrupt(&I2CD1); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief I2C1 error interrupt handler. - */ -CH_IRQ_HANDLER(I2C1_ER_IRQHandler) { - uint16_t sr = I2CD1.i2c->SR1; - - CH_IRQ_PROLOGUE(); - - I2CD1.i2c->SR1 = ~(sr & I2C_ERROR_MASK); - i2c_lld_serve_error_interrupt(&I2CD1, sr); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_I2C_USE_I2C1 */ - -#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__) -/** - * @brief I2C2 event interrupt handler. - * - * @notapi - */ -CH_IRQ_HANDLER(I2C2_EV_IRQHandler) { - - CH_IRQ_PROLOGUE(); - - i2c_lld_serve_event_interrupt(&I2CD2); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief I2C2 error interrupt handler. - * - * @notapi - */ -CH_IRQ_HANDLER(I2C2_ER_IRQHandler) { - uint16_t sr = I2CD2.i2c->SR1; - - CH_IRQ_PROLOGUE(); - - I2CD2.i2c->SR1 = ~(sr & I2C_ERROR_MASK); - i2c_lld_serve_error_interrupt(&I2CD2, sr); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_I2C_USE_I2C2 */ - -#if STM32_I2C_USE_I2C3 || defined(__DOXYGEN__) -/** - * @brief I2C3 event interrupt handler. - * - * @notapi - */ -CH_IRQ_HANDLER(I2C3_EV_IRQHandler) { - - CH_IRQ_PROLOGUE(); - - i2c_lld_serve_event_interrupt(&I2CD3); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief I2C3 error interrupt handler. - * - * @notapi - */ -CH_IRQ_HANDLER(I2C3_ER_IRQHandler) { - uint16_t sr = I2CD3.i2c->SR1; - - CH_IRQ_PROLOGUE(); - - I2CD3.i2c->SR1 = ~(sr & I2C_ERROR_MASK); - i2c_lld_serve_error_interrupt(&I2CD3, sr); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_I2C_USE_I2C3 */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level I2C driver initialization. - * - * @notapi - */ -void i2c_lld_init(void) { - -#if STM32_I2C_USE_I2C1 - i2cObjectInit(&I2CD1); - I2CD1.thread = NULL; - I2CD1.i2c = I2C1; - I2CD1.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C1_RX_DMA_STREAM); - I2CD1.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C1_TX_DMA_STREAM); -#endif /* STM32_I2C_USE_I2C1 */ - -#if STM32_I2C_USE_I2C2 - i2cObjectInit(&I2CD2); - I2CD2.thread = NULL; - I2CD2.i2c = I2C2; - I2CD2.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C2_RX_DMA_STREAM); - I2CD2.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C2_TX_DMA_STREAM); -#endif /* STM32_I2C_USE_I2C2 */ - -#if STM32_I2C_USE_I2C3 - i2cObjectInit(&I2CD3); - I2CD3.thread = NULL; - I2CD3.i2c = I2C3; - I2CD3.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C3_RX_DMA_STREAM); - I2CD3.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C3_TX_DMA_STREAM); -#endif /* STM32_I2C_USE_I2C3 */ -} - -/** - * @brief Configures and activates the I2C peripheral. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -void i2c_lld_start(I2CDriver *i2cp) { - I2C_TypeDef *dp = i2cp->i2c; - - i2cp->txdmamode = STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE | - STM32_DMA_CR_MINC | STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE | STM32_DMA_CR_TCIE | - STM32_DMA_CR_DIR_M2P; - i2cp->rxdmamode = STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE | - STM32_DMA_CR_MINC | STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE | STM32_DMA_CR_TCIE | - STM32_DMA_CR_DIR_P2M; - - /* If in stopped state then enables the I2C and DMA clocks.*/ - if (i2cp->state == I2C_STOP) { - -#if STM32_I2C_USE_I2C1 - if (&I2CD1 == i2cp) { - bool_t b; - - rccResetI2C1(); - b = dmaStreamAllocate(i2cp->dmarx, - STM32_I2C_I2C1_IRQ_PRIORITY, - (stm32_dmaisr_t)i2c_lld_serve_rx_end_irq, - (void *)i2cp); - chDbgAssert(!b, "i2c_lld_start(), #1", "stream already allocated"); - b = dmaStreamAllocate(i2cp->dmatx, - STM32_I2C_I2C1_IRQ_PRIORITY, - (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq, - (void *)i2cp); - chDbgAssert(!b, "i2c_lld_start(), #2", "stream already allocated"); - rccEnableI2C1(FALSE); - nvicEnableVector(I2C1_EV_IRQn, - CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); - nvicEnableVector(I2C1_ER_IRQn, - CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); - - i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C1_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY); - i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C1_TX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY); - } -#endif /* STM32_I2C_USE_I2C1 */ - -#if STM32_I2C_USE_I2C2 - if (&I2CD2 == i2cp) { - bool_t b; - - rccResetI2C2(); - b = dmaStreamAllocate(i2cp->dmarx, - STM32_I2C_I2C2_IRQ_PRIORITY, - (stm32_dmaisr_t)i2c_lld_serve_rx_end_irq, - (void *)i2cp); - chDbgAssert(!b, "i2c_lld_start(), #3", "stream already allocated"); - b = dmaStreamAllocate(i2cp->dmatx, - STM32_I2C_I2C2_IRQ_PRIORITY, - (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq, - (void *)i2cp); - chDbgAssert(!b, "i2c_lld_start(), #4", "stream already allocated"); - rccEnableI2C2(FALSE); - nvicEnableVector(I2C2_EV_IRQn, - CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY)); - nvicEnableVector(I2C2_ER_IRQn, - CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY)); - - i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C2_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY); - i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C2_TX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY); - } -#endif /* STM32_I2C_USE_I2C2 */ - -#if STM32_I2C_USE_I2C3 - if (&I2CD3 == i2cp) { - bool_t b; - - rccResetI2C3(); - b = dmaStreamAllocate(i2cp->dmarx, - STM32_I2C_I2C3_IRQ_PRIORITY, - (stm32_dmaisr_t)i2c_lld_serve_rx_end_irq, - (void *)i2cp); - chDbgAssert(!b, "i2c_lld_start(), #5", "stream already allocated"); - b = dmaStreamAllocate(i2cp->dmatx, - STM32_I2C_I2C3_IRQ_PRIORITY, - (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq, - (void *)i2cp); - chDbgAssert(!b, "i2c_lld_start(), #6", "stream already allocated"); - rccEnableI2C3(FALSE); - nvicEnableVector(I2C3_EV_IRQn, - CORTEX_PRIORITY_MASK(STM32_I2C_I2C3_IRQ_PRIORITY)); - nvicEnableVector(I2C3_ER_IRQn, - CORTEX_PRIORITY_MASK(STM32_I2C_I2C3_IRQ_PRIORITY)); - - i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C3_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_I2C_I2C3_DMA_PRIORITY); - i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C3_TX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_I2C_I2C3_DMA_PRIORITY); - } -#endif /* STM32_I2C_USE_I2C3 */ - } - - /* I2C registers pointed by the DMA.*/ - dmaStreamSetPeripheral(i2cp->dmarx, &dp->DR); - dmaStreamSetPeripheral(i2cp->dmatx, &dp->DR); - - /* Reset i2c peripheral.*/ - dp->CR1 = I2C_CR1_SWRST; - dp->CR1 = 0; - dp->CR2 = I2C_CR2_ITERREN | I2C_CR2_DMAEN; - - /* Setup I2C parameters.*/ - i2c_lld_set_clock(i2cp); - i2c_lld_set_opmode(i2cp); - - /* Ready to go.*/ - dp->CR1 |= I2C_CR1_PE; -} - -/** - * @brief Deactivates the I2C peripheral. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -void i2c_lld_stop(I2CDriver *i2cp) { - - /* If not in stopped state then disables the I2C clock.*/ - if (i2cp->state != I2C_STOP) { - - /* I2C disable.*/ - i2c_lld_abort_operation(i2cp); - dmaStreamRelease(i2cp->dmatx); - dmaStreamRelease(i2cp->dmarx); - -#if STM32_I2C_USE_I2C1 - if (&I2CD1 == i2cp) { - nvicDisableVector(I2C1_EV_IRQn); - nvicDisableVector(I2C1_ER_IRQn); - rccDisableI2C1(FALSE); - } -#endif - -#if STM32_I2C_USE_I2C2 - if (&I2CD2 == i2cp) { - nvicDisableVector(I2C2_EV_IRQn); - nvicDisableVector(I2C2_ER_IRQn); - rccDisableI2C2(FALSE); - } -#endif - -#if STM32_I2C_USE_I2C3 - if (&I2CD3 == i2cp) { - nvicDisableVector(I2C3_EV_IRQn); - nvicDisableVector(I2C3_ER_IRQn); - rccDisableI2C3(FALSE); - } -#endif - } -} - -/** - * @brief Receives data via the I2C bus as master. - * @details Number of receiving bytes must be more than 1 on STM32F1x. This is - * hardware restriction. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] addr slave device address - * @param[out] rxbuf pointer to the receive buffer - * @param[in] rxbytes number of bytes to be received - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval RDY_OK if the function succeeded. - * @retval RDY_RESET if one or more I2C errors occurred, the errors can - * be retrieved using @p i2cGetErrors(). - * @retval RDY_TIMEOUT if a timeout occurred before operation end. After a - * timeout the driver must be stopped and restarted - * because the bus is in an uncertain state. - * - * @notapi - */ -msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, - uint8_t *rxbuf, size_t rxbytes, - systime_t timeout) { - I2C_TypeDef *dp = i2cp->i2c; - VirtualTimer vt; - -#if defined(STM32F1XX_I2C) - chDbgCheck((rxbytes > 1), "i2c_lld_master_receive_timeout"); -#endif - - /* Global timeout for the whole operation.*/ - if (timeout != TIME_INFINITE) - chVTSetI(&vt, timeout, i2c_lld_safety_timeout, (void *)i2cp); - - /* Releases the lock from high level driver.*/ - chSysUnlock(); - - /* Initializes driver fields, LSB = 1 -> receive.*/ - i2cp->addr = (addr << 1) | 0x01; - i2cp->errors = 0; - - /* RX DMA setup.*/ - dmaStreamSetMode(i2cp->dmarx, i2cp->rxdmamode); - dmaStreamSetMemory0(i2cp->dmarx, rxbuf); - dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes); - - /* Waits until BUSY flag is reset and the STOP from the previous operation - is completed, alternatively for a timeout condition.*/ - while ((dp->SR2 & I2C_SR2_BUSY) || (dp->CR1 & I2C_CR1_STOP)) { - chSysLock(); - if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt)) - return RDY_TIMEOUT; - chSysUnlock(); - } - - /* This lock will be released in high level driver.*/ - chSysLock(); - - /* Atomic check on the timer in order to make sure that a timeout didn't - happen outside the critical zone.*/ - if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt)) - return RDY_TIMEOUT; - - /* Starts the operation.*/ - dp->CR2 |= I2C_CR2_ITEVTEN; - dp->CR1 |= I2C_CR1_START | I2C_CR1_ACK; - - /* Waits for the operation completion or a timeout.*/ - i2cp->thread = chThdSelf(); - chSchGoSleepS(THD_STATE_SUSPENDED); - if ((timeout != TIME_INFINITE) && chVTIsArmedI(&vt)) - chVTResetI(&vt); - - return chThdSelf()->p_u.rdymsg; -} - -/** - * @brief Transmits data via the I2C bus as master. - * @details Number of receiving bytes must be 0 or more than 1 on STM32F1x. - * This is hardware restriction. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] addr slave device address - * @param[in] txbuf pointer to the transmit buffer - * @param[in] txbytes number of bytes to be transmitted - * @param[out] rxbuf pointer to the receive buffer - * @param[in] rxbytes number of bytes to be received - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval RDY_OK if the function succeeded. - * @retval RDY_RESET if one or more I2C errors occurred, the errors can - * be retrieved using @p i2cGetErrors(). - * @retval RDY_TIMEOUT if a timeout occurred before operation end. After a - * timeout the driver must be stopped and restarted - * because the bus is in an uncertain state. - * - * @notapi - */ -msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, - const uint8_t *txbuf, size_t txbytes, - uint8_t *rxbuf, size_t rxbytes, - systime_t timeout) { - I2C_TypeDef *dp = i2cp->i2c; - VirtualTimer vt; - -#if defined(STM32F1XX_I2C) - chDbgCheck(((rxbytes == 0) || ((rxbytes > 1) && (rxbuf != NULL))), - "i2c_lld_master_transmit_timeout"); -#endif - - /* Global timeout for the whole operation.*/ - if (timeout != TIME_INFINITE) - chVTSetI(&vt, timeout, i2c_lld_safety_timeout, (void *)i2cp); - - /* Releases the lock from high level driver.*/ - chSysUnlock(); - - /* Initializes driver fields, LSB = 0 -> write.*/ - i2cp->addr = addr << 1; - i2cp->errors = 0; - - /* TX DMA setup.*/ - dmaStreamSetMode(i2cp->dmatx, i2cp->txdmamode); - dmaStreamSetMemory0(i2cp->dmatx, txbuf); - dmaStreamSetTransactionSize(i2cp->dmatx, txbytes); - - /* RX DMA setup.*/ - dmaStreamSetMode(i2cp->dmarx, i2cp->rxdmamode); - dmaStreamSetMemory0(i2cp->dmarx, rxbuf); - dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes); - - /* Waits until BUSY flag is reset and the STOP from the previous operation - is completed, alternatively for a timeout condition.*/ - while ((dp->SR2 & I2C_SR2_BUSY) || (dp->CR1 & I2C_CR1_STOP)) { - chSysLock(); - if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt)) - return RDY_TIMEOUT; - chSysUnlock(); - } - - /* This lock will be released in high level driver.*/ - chSysLock(); - - /* Atomic check on the timer in order to make sure that a timeout didn't - happen outside the critical zone.*/ - if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt)) - return RDY_TIMEOUT; - - /* Starts the operation.*/ - dp->CR2 |= I2C_CR2_ITEVTEN; - dp->CR1 |= I2C_CR1_START; - - /* Waits for the operation completion or a timeout.*/ - i2cp->thread = chThdSelf(); - chSchGoSleepS(THD_STATE_SUSPENDED); - if ((timeout != TIME_INFINITE) && chVTIsArmedI(&vt)) - chVTResetI(&vt); - - return chThdSelf()->p_u.rdymsg; -} - -#endif /* HAL_USE_I2C */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/I2Cv1/i2c_lld.h b/firmware/chibios/os/hal/platforms/STM32/I2Cv1/i2c_lld.h deleted file mode 100644 index 5844841fae..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/I2Cv1/i2c_lld.h +++ /dev/null @@ -1,463 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Concepts and parts of this file have been contributed by Uladzimir Pylinsky - aka barthess. - */ - -/** - * @file STM32/I2Cv1/i2c_lld.h - * @brief STM32 I2C subsystem low level driver header. - * - * @addtogroup I2C - * @{ - */ - -#ifndef _I2C_LLD_H_ -#define _I2C_LLD_H_ - -#if HAL_USE_I2C || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Peripheral clock frequency. - */ -#define I2C_CLK_FREQ ((STM32_PCLK1) / 1000000) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief I2C1 driver enable switch. - * @details If set to @p TRUE the support for I2C1 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_I2C_USE_I2C1) || defined(__DOXYGEN__) -#define STM32_I2C_USE_I2C1 FALSE -#endif - -/** - * @brief I2C2 driver enable switch. - * @details If set to @p TRUE the support for I2C2 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_I2C_USE_I2C2) || defined(__DOXYGEN__) -#define STM32_I2C_USE_I2C2 FALSE -#endif - -/** - * @brief I2C3 driver enable switch. - * @details If set to @p TRUE the support for I2C3 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_I2C_USE_I2C3) || defined(__DOXYGEN__) -#define STM32_I2C_USE_I2C3 FALSE -#endif - -/** - * @brief I2C1 interrupt priority level setting. - */ -#if !defined(STM32_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2C_I2C1_IRQ_PRIORITY 10 -#endif - -/** - * @brief I2C2 interrupt priority level setting. - */ -#if !defined(STM32_I2C_I2C2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2C_I2C2_IRQ_PRIORITY 10 -#endif - -/** - * @brief I2C3 interrupt priority level setting. - */ -#if !defined(STM32_I2C_I2C3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2C_I2C3_IRQ_PRIORITY 10 -#endif - -/** -* @brief I2C1 DMA priority (0..3|lowest..highest). -* @note The priority level is used for both the TX and RX DMA streams but -* because of the streams ordering the RX stream has always priority -* over the TX stream. -*/ -#if !defined(STM32_I2C_I2C1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2C_I2C1_DMA_PRIORITY 1 -#endif - -/** -* @brief I2C2 DMA priority (0..3|lowest..highest). -* @note The priority level is used for both the TX and RX DMA streams but -* because of the streams ordering the RX stream has always priority -* over the TX stream. -*/ -#if !defined(STM32_I2C_I2C2_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2C_I2C2_DMA_PRIORITY 1 -#endif - -/** -* @brief I2C3 DMA priority (0..3|lowest..highest). -* @note The priority level is used for both the TX and RX DMA streams but -* because of the streams ordering the RX stream has always priority -* over the TX stream. -*/ -#if !defined(STM32_I2C_I2C3_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2C_I2C3_DMA_PRIORITY 1 -#endif - -/** - * @brief I2C DMA error hook. - * @note The default action for DMA errors is a system halt because DMA - * error can only happen because programming errors. - */ -#if !defined(STM32_I2C_DMA_ERROR_HOOK) || defined(__DOXYGEN__) -#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt() -#endif - -#if STM32_ADVANCED_DMA || defined(__DOXYGEN__) - -/** - * @brief DMA stream used for I2C1 RX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_I2C_I2C1_RX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#endif - -/** - * @brief DMA stream used for I2C1 TX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_I2C_I2C1_TX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#endif - -/** - * @brief DMA stream used for I2C2 RX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_I2C_I2C2_RX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#endif - -/** - * @brief DMA stream used for I2C2 TX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_I2C_I2C2_TX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#endif - -/** - * @brief DMA stream used for I2C3 RX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_I2C_I2C3_RX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#endif - -/** - * @brief DMA stream used for I2C3 TX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_I2C_I2C3_TX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#endif - -#else /* !STM32_ADVANCED_DMA */ - -/* Fixed streams for platforms using the old DMA peripheral, the values are - valid for both STM32F1xx and STM32L1xx.*/ -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) - -#endif /* !STM32_ADVANCED_DMA*/ - -/* Flag for the whole STM32F1XX family. */ -#if defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \ - defined(STM32F10X_LD) || defined(STM32F10X_MD) || \ - defined(STM32F10X_HD) || defined(STM32F10X_XL) || \ - defined(STM32F10X_CL) -#define STM32F1XX_I2C -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/** @brief error checks */ -#if STM32_I2C_USE_I2C1 && !STM32_HAS_I2C1 -#error "I2C1 not present in the selected device" -#endif - -#if STM32_I2C_USE_I2C2 && !STM32_HAS_I2C2 -#error "I2C2 not present in the selected device" -#endif - -#if STM32_I2C_USE_I2C3 && !STM32_HAS_I2C3 -#error "I2C3 not present in the selected device" -#endif - -#if !STM32_I2C_USE_I2C1 && !STM32_I2C_USE_I2C2 && \ - !STM32_I2C_USE_I2C3 -#error "I2C driver activated but no I2C peripheral assigned" -#endif - -#if STM32_I2C_USE_I2C1 && \ - !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_RX_DMA_STREAM, \ - STM32_I2C1_RX_DMA_MSK) -#error "invalid DMA stream associated to I2C1 RX" -#endif - -#if STM32_I2C_USE_I2C1 && \ - !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_TX_DMA_STREAM, \ - STM32_I2C1_TX_DMA_MSK) -#error "invalid DMA stream associated to I2C1 TX" -#endif - -#if STM32_I2C_USE_I2C2 && \ - !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C2_RX_DMA_STREAM, \ - STM32_I2C2_RX_DMA_MSK) -#error "invalid DMA stream associated to I2C2 RX" -#endif - -#if STM32_I2C_USE_I2C2 && \ - !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C2_TX_DMA_STREAM, \ - STM32_I2C2_TX_DMA_MSK) -#error "invalid DMA stream associated to I2C2 TX" -#endif - -#if STM32_I2C_USE_I2C3 && \ - !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C3_RX_DMA_STREAM, \ - STM32_I2C3_RX_DMA_MSK) -#error "invalid DMA stream associated to I2C3 RX" -#endif - -#if STM32_I2C_USE_I2C3 && \ - !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C3_TX_DMA_STREAM, \ - STM32_I2C3_TX_DMA_MSK) -#error "invalid DMA stream associated to I2C3 TX" -#endif - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif - -/* Check clock range. */ -#if defined(STM32F4XX) -#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 42) -#error "I2C peripheral clock frequency out of range." -#endif - -#elif defined(STM32L1XX) -#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 32) -#error "I2C peripheral clock frequency out of range." -#endif - -#elif defined(STM32F2XX) -#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 30) -#error "I2C peripheral clock frequency out of range." -#endif - -#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \ - defined(STM32F10X_HD_VL) -#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 24) -#error "I2C peripheral clock frequency out of range." -#endif - -#elif defined(STM32F10X_LD) || defined(STM32F10X_MD) || \ - defined(STM32F10X_HD) || defined(STM32F10X_XL) || \ - defined(STM32F10X_CL) -#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 36) -#error "I2C peripheral clock frequency out of range." -#endif -#else -#error "unspecified, unsupported or invalid STM32 platform" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type representing I2C address. - */ -typedef uint16_t i2caddr_t; - -/** - * @brief I2C Driver condition flags type. - */ -typedef uint32_t i2cflags_t; - -/** - * @brief Supported modes for the I2C bus. - */ -typedef enum { - OPMODE_I2C = 1, - OPMODE_SMBUS_DEVICE = 2, - OPMODE_SMBUS_HOST = 3, -} i2copmode_t; - -/** - * @brief Supported duty cycle modes for the I2C bus. - */ -typedef enum { - STD_DUTY_CYCLE = 1, - FAST_DUTY_CYCLE_2 = 2, - FAST_DUTY_CYCLE_16_9 = 3, -} i2cdutycycle_t; - -/** - * @brief Driver configuration structure. - */ -typedef struct { - i2copmode_t op_mode; /**< @brief Specifies the I2C mode. */ - uint32_t clock_speed; /**< @brief Specifies the clock frequency. - @note Must be set to a value lower - than 400kHz. */ - i2cdutycycle_t duty_cycle; /**< @brief Specifies the I2C fast mode - duty cycle. */ -} I2CConfig; - -/** - * @brief Type of a structure representing an I2C driver. - */ -typedef struct I2CDriver I2CDriver; - -/** - * @brief Structure representing an I2C driver. - */ -struct I2CDriver { - /** - * @brief Driver state. - */ - i2cstate_t state; - /** - * @brief Current configuration data. - */ - const I2CConfig *config; - /** - * @brief Error flags. - */ - i2cflags_t errors; -#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) -#if CH_USE_MUTEXES || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the bus. - */ - Mutex mutex; -#elif CH_USE_SEMAPHORES - Semaphore semaphore; -#endif -#endif /* I2C_USE_MUTUAL_EXCLUSION */ -#if defined(I2C_DRIVER_EXT_FIELDS) - I2C_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Thread waiting for I/O completion. - */ - Thread *thread; - /** - * @brief Current slave address without R/W bit. - */ - i2caddr_t addr; - /** - * @brief RX DMA mode bit mask. - */ - uint32_t rxdmamode; - /** - * @brief TX DMA mode bit mask. - */ - uint32_t txdmamode; - /** - * @brief Receive DMA channel. - */ - const stm32_dma_stream_t *dmarx; - /** - * @brief Transmit DMA channel. - */ - const stm32_dma_stream_t *dmatx; - /** - * @brief Pointer to the I2Cx registers block. - */ - I2C_TypeDef *i2c; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Get errors from I2C driver. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -#define i2c_lld_get_errors(i2cp) ((i2cp)->errors) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -#if STM32_I2C_USE_I2C1 -extern I2CDriver I2CD1; -#endif - -#if STM32_I2C_USE_I2C2 -extern I2CDriver I2CD2; -#endif - -#if STM32_I2C_USE_I2C3 -extern I2CDriver I2CD3; -#endif -#endif /* !defined(__DOXYGEN__) */ - -#ifdef __cplusplus -extern "C" { -#endif - void i2c_lld_init(void); - void i2c_lld_start(I2CDriver *i2cp); - void i2c_lld_stop(I2CDriver *i2cp); - msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, - const uint8_t *txbuf, size_t txbytes, - uint8_t *rxbuf, size_t rxbytes, - systime_t timeout); - msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, - uint8_t *rxbuf, size_t rxbytes, - systime_t timeout); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_I2C */ - -#endif /* _I2C_LLD_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/I2Cv2/i2c_lld.c b/firmware/chibios/os/hal/platforms/STM32/I2Cv2/i2c_lld.c deleted file mode 100644 index d02ba2319e..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/I2Cv2/i2c_lld.c +++ /dev/null @@ -1,789 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Concepts and parts of this file have been contributed by Uladzimir Pylinsky - aka barthess. - */ - -/** - * @file STM32/I2Cv2/i2c_lld.c - * @brief STM32 I2C subsystem low level driver source. - * - * @addtogroup I2C - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_I2C || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define DMAMODE_COMMON \ - (STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE | \ - STM32_DMA_CR_MINC | STM32_DMA_CR_DMEIE | \ - STM32_DMA_CR_TEIE | STM32_DMA_CR_TCIE) - -#define I2C1_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_RX_DMA_STREAM, \ - STM32_I2C1_RX_DMA_CHN) - -#define I2C1_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_TX_DMA_STREAM, \ - STM32_I2C1_TX_DMA_CHN) - -#define I2C2_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_I2C_I2C2_RX_DMA_STREAM, \ - STM32_I2C2_RX_DMA_CHN) - -#define I2C2_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_I2C_I2C2_TX_DMA_STREAM, \ - STM32_I2C2_TX_DMA_CHN) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#define I2C_MASTER_TC \ - ((uint32_t)(I2C_ISR_BUSY | I2C_ISR_TC)) - -#define I2C_ERROR_MASK \ - ((uint32_t)(I2C_ISR_BERR | I2C_ISR_ARLO | I2C_ISR_OVR | I2C_ISR_PECERR | \ - I2C_ISR_TIMEOUT | I2C_ISR_ALERT)) - -#define I2C_INT_MASK \ - ((uint32_t)(I2C_ISR_TCR | I2C_ISR_TC | I2C_ISR_STOPF | I2C_ISR_NACKF | \ - I2C_ISR_ADDR | I2C_ISR_RXNE | I2C_ISR_TXIS)) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief I2C1 driver identifier.*/ -#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__) -I2CDriver I2CD1; -#endif - -/** @brief I2C2 driver identifier.*/ -#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__) -I2CDriver I2CD2; -#endif - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Wakes up the waiting thread. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] msg wakeup message - * - * @notapi - */ -#define wakeup_isr(i2cp, msg) { \ - chSysLockFromIsr(); \ - if ((i2cp)->thread != NULL) { \ - Thread *tp = (i2cp)->thread; \ - (i2cp)->thread = NULL; \ - tp->p_u.rdymsg = (msg); \ - chSchReadyI(tp); \ - } \ - chSysUnlockFromIsr(); \ -} - -/** - * @brief Aborts an I2C transaction. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -static void i2c_lld_abort_operation(I2CDriver *i2cp) { - I2C_TypeDef *dp = i2cp->i2c; - - if (dp->CR1 & I2C_CR1_PE) { - /* Stops the I2C peripheral.*/ - dp->CR1 &= ~I2C_CR1_PE; - while (dp->CR1 & I2C_CR1_PE) - dp->CR1 &= ~I2C_CR1_PE; - dp->CR1 |= I2C_CR1_PE; - } - - /* Stops the associated DMA streams.*/ - dmaStreamDisable(i2cp->dmatx); - dmaStreamDisable(i2cp->dmarx); -} - -/** - * @brief Handling of stalled I2C transactions. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -static void i2c_lld_safety_timeout(void *p) { - I2CDriver *i2cp = (I2CDriver *)p; - - chSysLockFromIsr(); - if (i2cp->thread) { - Thread *tp = i2cp->thread; - i2c_lld_abort_operation(i2cp); - i2cp->thread = NULL; - tp->p_u.rdymsg = RDY_TIMEOUT; - chSchReadyI(tp); - } - chSysUnlockFromIsr(); -} - -/** - * @brief I2C shared ISR code. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] isr content of the ISR register to be decoded - * - * @notapi - */ -static void i2c_lld_serve_interrupt(I2CDriver *i2cp, uint32_t isr) { - I2C_TypeDef *dp = i2cp->i2c; - - if ((isr & I2C_ISR_TC) && (i2cp->state == I2C_ACTIVE_TX)) { - size_t rxbytes; - - /* Make sure no more 'Transfer complete' interrupts.*/ - dp->CR1 &= ~I2C_CR1_TCIE; - - rxbytes = dmaStreamGetTransactionSize(i2cp->dmarx); - if (rxbytes > 0) { - i2cp->state = I2C_ACTIVE_RX; - - /* Enable RX DMA */ - dmaStreamEnable(i2cp->dmarx); - - dp->CR2 &= ~I2C_CR2_NBYTES; - dp->CR2 |= rxbytes << 16; - - /* Starts the read operation.*/ - dp->CR2 |= I2C_CR2_RD_WRN; - dp->CR2 |= I2C_CR2_START; - } - else { - /* Nothing to receive - send STOP immediately.*/ - dp->CR2 |= I2C_CR2_STOP; - } - } - if (isr & I2C_ISR_NACKF) { - /* Starts a STOP sequence immediately on error.*/ - dp->CR2 |= I2C_CR2_STOP; - - i2cp->errors |= I2CD_ACK_FAILURE; - } - if (isr & I2C_ISR_STOPF) { - /* Stops the associated DMA streams.*/ - dmaStreamDisable(i2cp->dmatx); - dmaStreamDisable(i2cp->dmarx); - - if (i2cp->errors) { - wakeup_isr(i2cp, RDY_RESET); - } - else { - wakeup_isr(i2cp, RDY_OK); - } - } -} - -/** - * @brief DMA RX end IRQ handler. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] flags pre-shifted content of the ISR register - * - * @notapi - */ -static void i2c_lld_serve_rx_end_irq(I2CDriver *i2cp, uint32_t flags) { - I2C_TypeDef *dp = i2cp->i2c; - - /* DMA errors handling.*/ -#if defined(STM32_I2C_DMA_ERROR_HOOK) - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - STM32_I2C_DMA_ERROR_HOOK(i2cp); - } -#else - (void)flags; -#endif - - dmaStreamDisable(i2cp->dmarx); - dp->CR2 |= I2C_CR2_STOP; - wakeup_isr(i2cp, RDY_OK); -} - -/** - * @brief DMA TX end IRQ handler. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -static void i2c_lld_serve_tx_end_irq(I2CDriver *i2cp, uint32_t flags) { - - /* DMA errors handling.*/ -#if defined(STM32_I2C_DMA_ERROR_HOOK) - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - STM32_I2C_DMA_ERROR_HOOK(i2cp); - } -#else - (void)flags; -#endif - - dmaStreamDisable(i2cp->dmatx); -} - -/** - * @brief I2C error handler. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] isr content of the ISR register to be decoded - * - * @notapi - */ -static void i2c_lld_serve_error_interrupt(I2CDriver *i2cp, uint32_t isr) { - - /* Clears interrupt flags just to be safe.*/ - dmaStreamDisable(i2cp->dmatx); - dmaStreamDisable(i2cp->dmarx); - - if (isr & I2C_ISR_BERR) - i2cp->errors |= I2CD_BUS_ERROR; - - if (isr & I2C_ISR_ARLO) - i2cp->errors |= I2CD_ARBITRATION_LOST; - - if (isr & I2C_ISR_OVR) - i2cp->errors |= I2CD_OVERRUN; - - if (isr & I2C_ISR_TIMEOUT) - i2cp->errors |= I2CD_TIMEOUT; - - /* If some error has been identified then sends wakes the waiting thread.*/ - if (i2cp->errors != I2CD_NO_ERROR) - wakeup_isr(i2cp, RDY_RESET); -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__) -#if defined(STM32_I2C1_GLOBAL_HANDLER) || defined(__DOXYGEN__) -/** - * @brief I2C1 event interrupt handler. - * - * @notapi - */ -CH_IRQ_HANDLER(STM32_I2C1_GLOBAL_HANDLER) { - uint32_t isr = I2CD1.i2c->ISR; - - CH_IRQ_PROLOGUE(); - - /* Clearing IRQ bits.*/ - I2CD1.i2c->ICR = isr; - - if (isr & I2C_ERROR_MASK) - i2c_lld_serve_error_interrupt(&I2CD1, isr); - else if (isr & I2C_INT_MASK) - i2c_lld_serve_interrupt(&I2CD1, isr); - - CH_IRQ_EPILOGUE(); -} - -#elif defined(STM32_I2C1_EVENT_HANDLER) && defined(STM32_I2C1_ERROR_HANDLER) -CH_IRQ_HANDLER(STM32_I2C1_EVENT_HANDLER) { - uint32_t isr = I2CD1.i2c->ISR; - - CH_IRQ_PROLOGUE(); - - /* Clearing IRQ bits.*/ - I2CD1.i2c->ICR = isr & I2C_INT_MASK; - - i2c_lld_serve_interrupt(&I2CD1, isr); - - CH_IRQ_EPILOGUE(); -} - -CH_IRQ_HANDLER(STM32_I2C1_ERROR_HANDLER) { - uint32_t isr = I2CD1.i2c->ISR; - - CH_IRQ_PROLOGUE(); - - /* Clearing IRQ bits.*/ - I2CD1.i2c->ICR = isr & I2C_ERROR_MASK; - - i2c_lld_serve_error_interrupt(&I2CD1, isr); - - CH_IRQ_EPILOGUE(); -} - -#else -#error "I2C1 interrupt handlers not defined" -#endif -#endif /* STM32_I2C_USE_I2C1 */ - -#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__) -#if defined(STM32_I2C2_GLOBAL_HANDLER) || defined(__DOXYGEN__) -/** - * @brief I2C2 event interrupt handler. - * - * @notapi - */ -CH_IRQ_HANDLER(STM32_I2C2_GLOBAL_HANDLER) { - uint32_t isr = I2CD2.i2c->ISR; - - CH_IRQ_PROLOGUE(); - - /* Clearing IRQ bits.*/ - I2CD2.i2c->ICR = isr; - - if (isr & I2C_ERROR_MASK) - i2c_lld_serve_error_interrupt(&I2CD2, isr); - else if (isr & I2C_INT_MASK) - i2c_lld_serve_interrupt(&I2CD2, isr); - - CH_IRQ_EPILOGUE(); -} - -#elif defined(STM32_I2C2_EVENT_HANDLER) && defined(STM32_I2C2_ERROR_HANDLER) -CH_IRQ_HANDLER(STM32_I2C2_EVENT_HANDLER) { - uint32_t isr = I2CD2.i2c->ISR; - - CH_IRQ_PROLOGUE(); - - /* Clearing IRQ bits.*/ - I2CD2.i2c->ICR = isr & I2C_INT_MASK; - - i2c_lld_serve_interrupt(&I2CD2, isr); - - CH_IRQ_EPILOGUE(); -} - -CH_IRQ_HANDLER(STM32_I2C2_ERROR_HANDLER) { - uint32_t isr = I2CD2.i2c->ISR; - - CH_IRQ_PROLOGUE(); - - /* Clearing IRQ bits.*/ - I2CD2.i2c->ICR = isr & I2C_ERROR_MASK; - - i2c_lld_serve_error_interrupt(&I2CD2, isr); - - CH_IRQ_EPILOGUE(); -} - -#else -#error "I2C2 interrupt handlers not defined" -#endif -#endif /* STM32_I2C_USE_I2C2 */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level I2C driver initialization. - * - * @notapi - */ -void i2c_lld_init(void) { - -#if STM32_I2C_USE_I2C1 - i2cObjectInit(&I2CD1); - I2CD1.thread = NULL; - I2CD1.i2c = I2C1; - I2CD1.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C1_RX_DMA_STREAM); - I2CD1.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C1_TX_DMA_STREAM); -#endif /* STM32_I2C_USE_I2C1 */ - -#if STM32_I2C_USE_I2C2 - i2cObjectInit(&I2CD2); - I2CD2.thread = NULL; - I2CD2.i2c = I2C2; - I2CD2.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C2_RX_DMA_STREAM); - I2CD2.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C2_TX_DMA_STREAM); -#endif /* STM32_I2C_USE_I2C2 */ -} - -/** - * @brief Configures and activates the I2C peripheral. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -void i2c_lld_start(I2CDriver *i2cp) { - I2C_TypeDef *dp = i2cp->i2c; - - i2cp->txdmamode = DMAMODE_COMMON | STM32_DMA_CR_DIR_M2P; - i2cp->rxdmamode = DMAMODE_COMMON | STM32_DMA_CR_DIR_P2M; - - /* Make sure I2C peripheral is disabled */ - dp->CR1 &= ~I2C_CR1_PE; - - /* If in stopped state then enables the I2C and DMA clocks.*/ - if (i2cp->state == I2C_STOP) { - -#if STM32_I2C_USE_I2C1 - if (&I2CD1 == i2cp) { - bool_t b; - - rccResetI2C1(); - b = dmaStreamAllocate(i2cp->dmarx, - STM32_I2C_I2C1_IRQ_PRIORITY, - (stm32_dmaisr_t)i2c_lld_serve_rx_end_irq, - (void *)i2cp); - chDbgAssert(!b, "i2c_lld_start(), #1", "stream already allocated"); - b = dmaStreamAllocate(i2cp->dmatx, - STM32_I2C_I2C1_IRQ_PRIORITY, - (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq, - (void *)i2cp); - chDbgAssert(!b, "i2c_lld_start(), #2", "stream already allocated"); - rccEnableI2C1(FALSE); - -#if defined(STM32_I2C1_GLOBAL_NUMBER) || defined(__DOXYGEN__) - nvicEnableVector(STM32_I2C1_GLOBAL_NUMBER, - CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); -#elif defined(STM32_I2C1_EVENT_NUMBER) && defined(STM32_I2C1_ERROR_NUMBER) - nvicEnableVector(STM32_I2C1_EVENT_NUMBER, - CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); - nvicEnableVector(STM32_I2C1_ERROR_NUMBER, - CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); -#else -#error "I2C1 interrupt numbers not defined" -#endif - - i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C1_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY); - i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C1_TX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY); - } -#endif /* STM32_I2C_USE_I2C1 */ - -#if STM32_I2C_USE_I2C2 - if (&I2CD2 == i2cp) { - bool_t b; - - rccResetI2C2(); - b = dmaStreamAllocate(i2cp->dmarx, - STM32_I2C_I2C2_IRQ_PRIORITY, - (stm32_dmaisr_t)i2c_lld_serve_rx_end_irq, - (void *)i2cp); - chDbgAssert(!b, "i2c_lld_start(), #3", "stream already allocated"); - b = dmaStreamAllocate(i2cp->dmatx, - STM32_I2C_I2C2_IRQ_PRIORITY, - (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq, - (void *)i2cp); - chDbgAssert(!b, "i2c_lld_start(), #4", "stream already allocated"); - rccEnableI2C2(FALSE); - -#if defined(STM32_I2C2_GLOBAL_NUMBER) || defined(__DOXYGEN__) - nvicEnableVector(STM32_I2C2_GLOBAL_NUMBER, - CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY)); -#elif defined(STM32_I2C2_EVENT_NUMBER) && defined(STM32_I2C2_ERROR_NUMBER) - nvicEnableVector(STM32_I2C2_EVENT_NUMBER, - CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY)); - nvicEnableVector(STM32_I2C2_ERROR_NUMBER, - CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY)); -#else -#error "I2C2 interrupt numbers not defined" -#endif - - i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C2_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY); - i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C2_TX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY); - } -#endif /* STM32_I2C_USE_I2C2 */ - } - - /* I2C registers pointed by the DMA.*/ - dmaStreamSetPeripheral(i2cp->dmarx, &dp->RXDR); - dmaStreamSetPeripheral(i2cp->dmatx, &dp->TXDR); - - /* Reset i2c peripheral, the TCIE bit will be handled separately.*/ - dp->CR1 = i2cp->config->cr1 | I2C_CR1_ERRIE | I2C_CR1_STOPIE | - I2C_CR1_NACKIE | I2C_CR1_TXDMAEN | I2C_CR1_RXDMAEN; - - /* Set slave address field (master mode) */ - dp->CR2 = (i2cp->config->cr2 & ~I2C_CR2_SADD); - - /* Setup I2C parameters.*/ - dp->TIMINGR = i2cp->config->timingr; - - /* Ready to go.*/ - dp->CR1 |= I2C_CR1_PE; -} - -/** - * @brief Deactivates the I2C peripheral. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -void i2c_lld_stop(I2CDriver *i2cp) { - - /* If not in stopped state then disables the I2C clock.*/ - if (i2cp->state != I2C_STOP) { - - /* I2C disable.*/ - i2c_lld_abort_operation(i2cp); - dmaStreamRelease(i2cp->dmatx); - dmaStreamRelease(i2cp->dmarx); - -#if STM32_I2C_USE_I2C1 - if (&I2CD1 == i2cp) { -#if defined(STM32_I2C1_GLOBAL_NUMBER) || defined(__DOXYGEN__) - nvicDisableVector(STM32_I2C1_GLOBAL_NUMBER); -#elif defined(STM32_I2C1_EVENT_NUMBER) && defined(STM32_I2C1_ERROR_NUMBER) - nvicDisableVector(STM32_I2C1_EVENT_NUMBER); - nvicDisableVector(STM32_I2C1_ERROR_NUMBER); -#else -#error "I2C1 interrupt numbers not defined" -#endif - - rccDisableI2C1(FALSE); - } -#endif - -#if STM32_I2C_USE_I2C2 - if (&I2CD2 == i2cp) { -#if defined(STM32_I2C2_GLOBAL_NUMBER) || defined(__DOXYGEN__) - nvicDisableVector(STM32_I2C2_GLOBAL_NUMBER); -#elif defined(STM32_I2C2_EVENT_NUMBER) && defined(STM32_I2C2_ERROR_NUMBER) - nvicDisableVector(STM32_I2C2_EVENT_NUMBER); - nvicDisableVector(STM32_I2C2_ERROR_NUMBER); -#else -#error "I2C2 interrupt numbers not defined" -#endif - - rccDisableI2C2(FALSE); - } -#endif - } -} - -/** - * @brief Receives data via the I2C bus as master. - * @details Number of receiving bytes must be more than 1 on STM32F1x. This is - * hardware restriction. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] addr slave device address - * @param[out] rxbuf pointer to the receive buffer - * @param[in] rxbytes number of bytes to be received - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval RDY_OK if the function succeeded. - * @retval RDY_RESET if one or more I2C errors occurred, the errors can - * be retrieved using @p i2cGetErrors(). - * @retval RDY_TIMEOUT if a timeout occurred before operation end. After a - * timeout the driver must be stopped and restarted - * because the bus is in an uncertain state. - * - * @notapi - */ -msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, - uint8_t *rxbuf, size_t rxbytes, - systime_t timeout) { - I2C_TypeDef *dp = i2cp->i2c; - VirtualTimer vt; - uint32_t addr_cr2 = addr & I2C_CR2_SADD; - - chDbgCheck((rxbytes > 0), "i2c_lld_master_receive_timeout"); - - /* Resetting error flags for this transfer.*/ - i2cp->errors = I2CD_NO_ERROR; - - /* Global timeout for the whole operation.*/ - if (timeout != TIME_INFINITE) - chVTSetI(&vt, timeout, i2c_lld_safety_timeout, (void *)i2cp); - - /* Releases the lock from high level driver.*/ - chSysUnlock(); - - /* Waits until BUSY flag is reset and the STOP from the previous operation - is completed, alternatively for a timeout condition.*/ - while (dp->ISR & I2C_ISR_BUSY) { - chSysLock(); - if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt)) - return RDY_TIMEOUT; - chSysUnlock(); - } - - /* This lock will be released in high level driver.*/ - chSysLock(); - - /* Adjust slave address (master mode) for 7-bit address mode */ - if ((i2cp->config->cr2 & I2C_CR2_ADD10) == 0) - addr_cr2 = (addr_cr2 & 0x7f) << 1; - - /* Set slave address field (master mode) */ - dp->CR2 &= ~(I2C_CR2_SADD | I2C_CR2_NBYTES); - dp->CR2 |= (rxbytes << 16) | addr_cr2; - - /* Initializes driver fields */ - i2cp->errors = 0; - - /* RX DMA setup.*/ - dmaStreamSetMode(i2cp->dmarx, i2cp->rxdmamode); - dmaStreamSetMemory0(i2cp->dmarx, rxbuf); - dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes); - - /* Enable RX DMA */ - dmaStreamEnable(i2cp->dmarx); - - /* Atomic check on the timer in order to make sure that a timeout didn't - happen outside the critical zone.*/ - if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt)) - return RDY_TIMEOUT; - - /* Starts the operation.*/ - dp->CR2 |= I2C_CR2_RD_WRN; - dp->CR2 |= I2C_CR2_START; - - /* Waits for the operation completion or a timeout.*/ - i2cp->thread = chThdSelf(); - chSchGoSleepS(THD_STATE_SUSPENDED); - if ((timeout != TIME_INFINITE) && chVTIsArmedI(&vt)) - chVTResetI(&vt); - - return chThdSelf()->p_u.rdymsg; -} - -/** - * @brief Transmits data via the I2C bus as master. - * @details Number of receiving bytes must be 0 or more than 1 on STM32F1x. - * This is hardware restriction. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] addr slave device address - * @param[in] txbuf pointer to the transmit buffer - * @param[in] txbytes number of bytes to be transmitted - * @param[out] rxbuf pointer to the receive buffer - * @param[in] rxbytes number of bytes to be received - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval RDY_OK if the function succeeded. - * @retval RDY_RESET if one or more I2C errors occurred, the errors can - * be retrieved using @p i2cGetErrors(). - * @retval RDY_TIMEOUT if a timeout occurred before operation end. After a - * timeout the driver must be stopped and restarted - * because the bus is in an uncertain state. - * - * @notapi - */ -msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, - const uint8_t *txbuf, size_t txbytes, - uint8_t *rxbuf, size_t rxbytes, - systime_t timeout) { - I2C_TypeDef *dp = i2cp->i2c; - VirtualTimer vt; - uint32_t addr_cr2 = addr & I2C_CR2_SADD; - - chDbgCheck(((rxbytes == 0) || ((rxbytes > 0) && (rxbuf != NULL))), - "i2c_lld_master_transmit_timeout"); - - /* Resetting error flags for this transfer.*/ - i2cp->errors = I2CD_NO_ERROR; - - /* Global timeout for the whole operation.*/ - if (timeout != TIME_INFINITE) - chVTSetI(&vt, timeout, i2c_lld_safety_timeout, (void *)i2cp); - - /* Releases the lock from high level driver.*/ - chSysUnlock(); - - /* Waits until BUSY flag is reset and the STOP from the previous operation - is completed, alternatively for a timeout condition.*/ - while (dp->ISR & I2C_ISR_BUSY) { - chSysLock(); - if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt)) - return RDY_TIMEOUT; - chSysUnlock(); - } - - /* This lock will be released in high level driver.*/ - chSysLock(); - - /* Adjust slave address (master mode) for 7-bit address mode */ - if ((i2cp->config->cr2 & I2C_CR2_ADD10) == 0) - addr_cr2 = (addr_cr2 & 0x7f) << 1; - - /* Set slave address field (master mode) */ - dp->CR2 &= ~(I2C_CR2_SADD | I2C_CR2_NBYTES); - dp->CR2 |= (txbytes << 16) | addr_cr2; - - /* Initializes driver fields */ - i2cp->errors = 0; - - /* TX DMA setup.*/ - dmaStreamSetMode(i2cp->dmatx, i2cp->txdmamode); - dmaStreamSetMemory0(i2cp->dmatx, txbuf); - dmaStreamSetTransactionSize(i2cp->dmatx, txbytes); - - /* RX DMA setup.*/ - dmaStreamSetMode(i2cp->dmarx, i2cp->rxdmamode); - dmaStreamSetMemory0(i2cp->dmarx, rxbuf); - dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes); - - /* Enable TX DMA */ - dmaStreamEnable(i2cp->dmatx); - - /* Atomic check on the timer in order to make sure that a timeout didn't - happen outside the critical zone.*/ - if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt)) - return RDY_TIMEOUT; - - /* Transmission complete interrupt enabled.*/ - dp->CR1 |= I2C_CR1_TCIE; - - /* Starts the operation as the very last thing.*/ - dp->CR2 &= ~I2C_CR2_RD_WRN; - dp->CR2 |= I2C_CR2_START; - - /* Waits for the operation completion or a timeout.*/ - i2cp->thread = chThdSelf(); - chSchGoSleepS(THD_STATE_SUSPENDED); - if ((timeout != TIME_INFINITE) && chVTIsArmedI(&vt)) - chVTResetI(&vt); - - return chThdSelf()->p_u.rdymsg; -} - -#endif /* HAL_USE_I2C */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/I2Cv2/i2c_lld.h b/firmware/chibios/os/hal/platforms/STM32/I2Cv2/i2c_lld.h deleted file mode 100644 index 1450b7ab07..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/I2Cv2/i2c_lld.h +++ /dev/null @@ -1,338 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Concepts and parts of this file have been contributed by Uladzimir Pylinsky - aka barthess. - */ - -/** - * @file STM32/I2Cv2/i2c_lld.h - * @brief STM32 I2C subsystem low level driver header. - * - * @addtogroup I2C - * @{ - */ - -#ifndef _I2C_LLD_H_ -#define _I2C_LLD_H_ - -#if HAL_USE_I2C || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name TIMINGR register definitions - * @{ - */ -#define STM32_TIMINGR_PRESC_MASK (15U << 28) -#define STM32_TIMINGR_PRESC(n) ((n) << 28) -#define STM32_TIMINGR_SCLDEL_MASK (15U << 20) -#define STM32_TIMINGR_SCLDEL(n) ((n) << 20) -#define STM32_TIMINGR_SDADEL_MASK (15U << 16) -#define STM32_TIMINGR_SDADEL(n) ((n) << 16) -#define STM32_TIMINGR_SCLH_MASK (255U << 8) -#define STM32_TIMINGR_SCLH(n) ((n) << 8) -#define STM32_TIMINGR_SCLL_MASK (255U << 0) -#define STM32_TIMINGR_SCLL(n) ((n) << 0) -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief I2C1 driver enable switch. - * @details If set to @p TRUE the support for I2C1 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_I2C_USE_I2C1) || defined(__DOXYGEN__) -#define STM32_I2C_USE_I2C1 FALSE -#endif - -/** - * @brief I2C2 driver enable switch. - * @details If set to @p TRUE the support for I2C2 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_I2C_USE_I2C2) || defined(__DOXYGEN__) -#define STM32_I2C_USE_I2C2 FALSE -#endif - -/** - * @brief I2C1 interrupt priority level setting. - */ -#if !defined(STM32_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2C_I2C1_IRQ_PRIORITY 10 -#endif - -/** - * @brief I2C2 interrupt priority level setting. - */ -#if !defined(STM32_I2C_I2C2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2C_I2C2_IRQ_PRIORITY 10 -#endif - -/** - * @brief I2C1 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA streams but - * because of the streams ordering the RX stream has always priority - * over the TX stream. - */ -#if !defined(STM32_I2C_I2C1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2C_I2C1_DMA_PRIORITY 1 -#endif - -/** - * @brief I2C2 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA streams but - * because of the streams ordering the RX stream has always priority - * over the TX stream. - */ -#if !defined(STM32_I2C_I2C2_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2C_I2C2_DMA_PRIORITY 1 -#endif - -/** - * @brief I2C DMA error hook. - * @note The default action for DMA errors is a system halt because DMA - * error can only happen because programming errors. - */ -#if !defined(STM32_I2C_DMA_ERROR_HOOK) || defined(__DOXYGEN__) -#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt() -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/* Streams for the DMA peripheral.*/ -#if defined(STM32F0XX) -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) - -#elif defined(STM32F30X) || defined(STM32F37X) -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) - -#else -#error "device unsupported by I2Cv2 driver" -#endif - -/** @brief error checks */ -#if STM32_I2C_USE_I2C1 && !STM32_HAS_I2C1 -#error "I2C1 not present in the selected device" -#endif - -#if STM32_I2C_USE_I2C2 && !STM32_HAS_I2C2 -#error "I2C2 not present in the selected device" -#endif - -#if !STM32_I2C_USE_I2C1 && !STM32_I2C_USE_I2C2 -#error "I2C driver activated but no I2C peripheral assigned" -#endif - -#if STM32_I2C_USE_I2C1 && \ - !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_RX_DMA_STREAM, \ - STM32_I2C1_RX_DMA_MSK) -#error "invalid DMA stream associated to I2C1 RX" -#endif - -#if STM32_I2C_USE_I2C1 && \ - !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_TX_DMA_STREAM, \ - STM32_I2C1_TX_DMA_MSK) -#error "invalid DMA stream associated to I2C1 TX" -#endif - -#if STM32_I2C_USE_I2C2 && \ - !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C2_RX_DMA_STREAM, \ - STM32_I2C2_RX_DMA_MSK) -#error "invalid DMA stream associated to I2C2 RX" -#endif - -#if STM32_I2C_USE_I2C2 && \ - !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C2_TX_DMA_STREAM, \ - STM32_I2C2_TX_DMA_MSK) -#error "invalid DMA stream associated to I2C2 TX" -#endif - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif - -/* Check clock range. */ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type representing I2C address. - */ -typedef uint16_t i2caddr_t; - -/** - * @brief I2C Driver condition flags type. - */ -typedef uint32_t i2cflags_t; - -/** - * @brief Driver configuration structure. - */ -typedef struct { - /** - * @brief TIMINGR register initialization. - * @note Refer to the STM32 reference manual, the values are affected - * by the system clock settings in mcuconf.h. - */ - uint32_t timingr; - /** - * @brief CR1 register initialization. - * @note Leave to zero unless you know what you are doing. - */ - uint32_t cr1; - /** - * @brief CR2 register initialization. - * @note Only the ADD10 bit can eventually be specified here. - */ - uint32_t cr2; -} I2CConfig; - -/** - * @brief Type of a structure representing an I2C driver. - */ -typedef struct I2CDriver I2CDriver; - -/** - * @brief Structure representing an I2C driver. - */ -struct I2CDriver{ - /** - * @brief Driver state. - */ - i2cstate_t state; - /** - * @brief Current configuration data. - */ - const I2CConfig *config; - /** - * @brief Error flags. - */ - i2cflags_t errors; -#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) -#if CH_USE_MUTEXES || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the bus. - */ - Mutex mutex; -#elif CH_USE_SEMAPHORES - Semaphore semaphore; -#endif -#endif /* I2C_USE_MUTUAL_EXCLUSION */ -#if defined(I2C_DRIVER_EXT_FIELDS) - I2C_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Thread waiting for I/O completion. - */ - Thread *thread; - /** - * @brief Current slave address without R/W bit. - */ - i2caddr_t addr; - /** - * @brief RX DMA mode bit mask. - */ - uint32_t rxdmamode; - /** - * @brief TX DMA mode bit mask. - */ - uint32_t txdmamode; - /** - * @brief Receive DMA channel. - */ - const stm32_dma_stream_t *dmarx; - /** - * @brief Transmit DMA channel. - */ - const stm32_dma_stream_t *dmatx; - /** - * @brief Pointer to the I2Cx registers block. - */ - I2C_TypeDef *i2c; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Get errors from I2C driver. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -#define i2c_lld_get_errors(i2cp) ((i2cp)->errors) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -#if STM32_I2C_USE_I2C1 -extern I2CDriver I2CD1; -#endif - -#if STM32_I2C_USE_I2C2 -extern I2CDriver I2CD2; -#endif - -#endif /* !defined(__DOXYGEN__) */ - -#ifdef __cplusplus -extern "C" { -#endif - void i2c_lld_init(void); - void i2c_lld_start(I2CDriver *i2cp); - void i2c_lld_stop(I2CDriver *i2cp); - msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, - const uint8_t *txbuf, size_t txbytes, - uint8_t *rxbuf, size_t rxbytes, - systime_t timeout); - msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, - uint8_t *rxbuf, size_t rxbytes, - systime_t timeout); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_I2C */ - -#endif /* _I2C_LLD_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/OTGv1/stm32_otg.h b/firmware/chibios/os/hal/platforms/STM32/OTGv1/stm32_otg.h deleted file mode 100644 index 7b1c183ff9..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/OTGv1/stm32_otg.h +++ /dev/null @@ -1,916 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file stm32_otg.h - * @brief STM32 OTG registers layout header. - * - * @addtogroup USB - * @{ - */ - -#ifndef _STM32_OTG_H_ -#define _STM32_OTG_H_ - -/** - * @brief Number of the implemented endpoints in OTG_FS. - * @details This value does not include the endpoint 0 that is always present. - */ -#define STM32_OTG1_ENDOPOINTS_NUMBER 3 - -/** - * @brief Number of the implemented endpoints in OTG_HS. - * @details This value does not include the endpoint 0 that is always present. - */ -#define STM32_OTG2_ENDOPOINTS_NUMBER 5 - -/** - * @brief OTG_FS FIFO memory size in words. - */ -#define STM32_OTG1_FIFO_MEM_SIZE 320 - -/** - * @brief OTG_HS FIFO memory size in words. - */ -#define STM32_OTG2_FIFO_MEM_SIZE 1024 - -/** - * @brief Host channel registers group. - */ -typedef struct { - volatile uint32_t HCCHAR; /**< @brief Host channel characteristics - register. */ - volatile uint32_t resvd8; - volatile uint32_t HCINT; /**< @brief Host channel interrupt register.*/ - volatile uint32_t HCINTMSK; /**< @brief Host channel interrupt mask - register. */ - volatile uint32_t HCTSIZ; /**< @brief Host channel transfer size - register. */ - volatile uint32_t resvd14; - volatile uint32_t resvd18; - volatile uint32_t resvd1c; -} stm32_otg_host_chn_t; - -/** - * @brief Device input endpoint registers group. - */ -typedef struct { - volatile uint32_t DIEPCTL; /**< @brief Device control IN endpoint - control register. */ - volatile uint32_t resvd4; - volatile uint32_t DIEPINT; /**< @brief Device IN endpoint interrupt - register. */ - volatile uint32_t resvdC; - volatile uint32_t DIEPTSIZ; /**< @brief Device IN endpoint transfer size - register. */ - volatile uint32_t resvd14; - volatile uint32_t DTXFSTS; /**< @brief Device IN endpoint transmit FIFO - status register. */ - volatile uint32_t resvd1C; -} stm32_otg_in_ep_t; - -/** - * @brief Device output endpoint registers group. - */ -typedef struct { - volatile uint32_t DOEPCTL; /**< @brief Device control OUT endpoint - control register. */ - volatile uint32_t resvd4; - volatile uint32_t DOEPINT; /**< @brief Device OUT endpoint interrupt - register. */ - volatile uint32_t resvdC; - volatile uint32_t DOEPTSIZ; /**< @brief Device OUT endpoint transfer - size register. */ - volatile uint32_t resvd14; - volatile uint32_t resvd18; - volatile uint32_t resvd1C; -} stm32_otg_out_ep_t; - -/** - * @brief USB registers memory map. - */ -typedef struct { - volatile uint32_t GOTGCTL; /**< @brief OTG control and status register.*/ - volatile uint32_t GOTGINT; /**< @brief OTG interrupt register. */ - volatile uint32_t GAHBCFG; /**< @brief AHB configuration register. */ - volatile uint32_t GUSBCFG; /**< @brief USB configuration register. */ - volatile uint32_t GRSTCTL; /**< @brief Reset register size. */ - volatile uint32_t GINTSTS; /**< @brief Interrupt register. */ - volatile uint32_t GINTMSK; /**< @brief Interrupt mask register. */ - volatile uint32_t GRXSTSR; /**< @brief Receive status debug read - register. */ - volatile uint32_t GRXSTSP; /**< @brief Receive status read/pop - register. */ - volatile uint32_t GRXFSIZ; /**< @brief Receive FIFO size register. */ - volatile uint32_t DIEPTXF0; /**< @brief Endpoint 0 transmit FIFO size - register. */ - volatile uint32_t HNPTXSTS; /**< @brief Non-periodic transmit FIFO/queue - status register. */ - volatile uint32_t resvd30; - volatile uint32_t resvd34; - volatile uint32_t GCCFG; /**< @brief General core configuration. */ - volatile uint32_t CID; /**< @brief Core ID register. */ - volatile uint32_t resvd58[48]; - volatile uint32_t HPTXFSIZ; /**< @brief Host periodic transmit FIFO size - register. */ - volatile uint32_t DIEPTXF[15];/**< @brief Device IN endpoint transmit FIFO - size registers. */ - volatile uint32_t resvd140[176]; - volatile uint32_t HCFG; /**< @brief Host configuration register. */ - volatile uint32_t HFIR; /**< @brief Host frame interval register. */ - volatile uint32_t HFNUM; /**< @brief Host frame number/frame time - Remaining register. */ - volatile uint32_t resvd40C; - volatile uint32_t HPTXSTS; /**< @brief Host periodic transmit FIFO/queue - status register. */ - volatile uint32_t HAINT; /**< @brief Host all channels interrupt - register. */ - volatile uint32_t HAINTMSK; /**< @brief Host all channels interrupt mask - register. */ - volatile uint32_t resvd41C[9]; - volatile uint32_t HPRT; /**< @brief Host port control and status - register. */ - volatile uint32_t resvd444[47]; - stm32_otg_host_chn_t hc[16]; /**< @brief Host channels array. */ - volatile uint32_t resvd700[64]; - volatile uint32_t DCFG; /**< @brief Device configuration register. */ - volatile uint32_t DCTL; /**< @brief Device control register. */ - volatile uint32_t DSTS; /**< @brief Device status register. */ - volatile uint32_t resvd80C; - volatile uint32_t DIEPMSK; /**< @brief Device IN endpoint common - interrupt mask register. */ - volatile uint32_t DOEPMSK; /**< @brief Device OUT endpoint common - interrupt mask register. */ - volatile uint32_t DAINT; /**< @brief Device all endpoints interrupt - register. */ - volatile uint32_t DAINTMSK; /**< @brief Device all endpoints interrupt - mask register. */ - volatile uint32_t resvd820; - volatile uint32_t resvd824; - volatile uint32_t DVBUSDIS; /**< @brief Device VBUS discharge time - register. */ - volatile uint32_t DVBUSPULSE; /**< @brief Device VBUS pulsing time - register. */ - volatile uint32_t resvd830; - volatile uint32_t DIEPEMPMSK; /**< @brief Device IN endpoint FIFO empty - interrupt mask register. */ - volatile uint32_t resvd838; - volatile uint32_t resvd83C; - volatile uint32_t resvd840[16]; - volatile uint32_t resvd880[16]; - volatile uint32_t resvd8C0[16]; - stm32_otg_in_ep_t ie[16]; /**< @brief Input endpoints. */ - stm32_otg_out_ep_t oe[16]; /**< @brief Output endpoints. */ - volatile uint32_t resvdD00[64]; - volatile uint32_t PCGCCTL; /**< @brief Power and clock gating control - register. */ - volatile uint32_t resvdE04[127]; - volatile uint32_t FIFO[16][1024]; -} stm32_otg_t; - -/** - * @name GOTGCTL register bit definitions - * @{ - */ -#define GOTGCTL_BSVLD (1U<<19) /**< B-Session Valid. */ -#define GOTGCTL_ASVLD (1U<<18) /**< A-Session Valid. */ -#define GOTGCTL_DBCT (1U<<17) /**< Long/Short debounce time. */ -#define GOTGCTL_CIDSTS (1U<<16) /**< Connector ID status. */ -#define GOTGCTL_DHNPEN (1U<<11) /**< Device HNP enabled. */ -#define GOTGCTL_HSHNPEN (1U<<10) /**< Host Set HNP enable. */ -#define GOTGCTL_HNPRQ (1U<<9) /**< HNP request. */ -#define GOTGCTL_HNGSCS (1U<<8) /**< Host negotiation success. */ -#define GOTGCTL_SRQ (1U<<1) /**< Session request. */ -#define GOTGCTL_SRQSCS (1U<<0) /**< Session request success. */ -/** @} */ - -/** - * @name GOTGINT register bit definitions - * @{ - */ -#define GOTGINT_DBCDNE (1U<<19) /**< Debounce done. */ -#define GOTGINT_ADTOCHG (1U<<18) /**< A-Device timeout change. */ -#define GOTGINT_HNGDET (1U<<17) /**< Host negotiation detected. */ -#define GOTGINT_HNSSCHG (1U<<9) /**< Host negotiation success - status change. */ -#define GOTGINT_SRSSCHG (1U<<8) /**< Session request success - status change. */ -#define GOTGINT_SEDET (1U<<2) /**< Session end detected. */ -/** @} */ - -/** - * @name GAHBCFG register bit definitions - * @{ - */ -#define GAHBCFG_PTXFELVL (1U<<8) /**< Periodic TxFIFO empty - level. */ -#define GAHBCFG_TXFELVL (1U<<7) /**< Non-periodic TxFIFO empty - level. */ -#define GAHBCFG_DMAEN (1U<<5) /**< DMA enable (HS only). */ -#define GAHBCFG_HBSTLEN_MASK (15U<<1) /**< Burst length/type mask (HS - only). */ -#define GAHBCFG_HBSTLEN(n) ((n)<<1) /**< Burst length/type (HS - only). */ -#define GAHBCFG_GINTMSK (1U<<0) /**< Global interrupt mask. */ -/** @} */ - -/** - * @name GUSBCFG register bit definitions - * @{ - */ -#define GUSBCFG_CTXPKT (1U<<31) /**< Corrupt Tx packet. */ -#define GUSBCFG_FDMOD (1U<<30) /**< Force Device Mode. */ -#define GUSBCFG_FHMOD (1U<<29) /**< Force Host Mode. */ -#define GUSBCFG_TRDT_MASK (15U<<10) /**< USB Turnaround time field - mask. */ -#define GUSBCFG_TRDT(n) ((n)<<10) /**< USB Turnaround time field - value. */ -#define GUSBCFG_HNPCAP (1U<<9) /**< HNP-Capable. */ -#define GUSBCFG_SRPCAP (1U<<8) /**< SRP-Capable. */ -#define GUSBCFG_PHYSEL (1U<<6) /**< USB 2.0 High-Speed PHY or - USB 1.1 Full-Speed serial - transceiver Select. */ -#define GUSBCFG_TOCAL_MASK (7U<<0) /**< HS/FS timeout calibration - field mask. */ -#define GUSBCFG_TOCAL(n) ((n)<<0) /**< HS/FS timeout calibration - field value. */ -/** @} */ - -/** - * @name GRSTCTL register bit definitions - * @{ - */ -#define GRSTCTL_AHBIDL (1U<<31) /**< AHB Master Idle. */ -#define GRSTCTL_TXFNUM_MASK (31U<<6) /**< TxFIFO number field mask. */ -#define GRSTCTL_TXFNUM(n) ((n)<<6) /**< TxFIFO number field value. */ -#define GRSTCTL_TXFFLSH (1U<<5) /**< TxFIFO flush. */ -#define GRSTCTL_RXFFLSH (1U<<4) /**< RxFIFO flush. */ -#define GRSTCTL_FCRST (1U<<2) /**< Host frame counter reset. */ -#define GRSTCTL_HSRST (1U<<1) /**< HClk soft reset. */ -#define GRSTCTL_CSRST (1U<<0) /**< Core soft reset. */ -/** @} */ - -/** - * @name GINTSTS register bit definitions - * @{ - */ -#define GINTSTS_WKUPINT (1U<<31) /**< Resume/Remote wakeup - detected interrupt. */ -#define GINTSTS_SRQINT (1U<<30) /**< Session request/New session - detected interrupt. */ -#define GINTSTS_DISCINT (1U<<29) /**< Disconnect detected - interrupt. */ -#define GINTSTS_CIDSCHG (1U<<28) /**< Connector ID status change.*/ -#define GINTSTS_PTXFE (1U<<26) /**< Periodic TxFIFO empty. */ -#define GINTSTS_HCINT (1U<<25) /**< Host channels interrupt. */ -#define GINTSTS_HPRTINT (1U<<24) /**< Host port interrupt. */ -#define GINTSTS_IPXFR (1U<<21) /**< Incomplete periodic - transfer. */ -#define GINTSTS_IISOOXFR (1U<<21) /**< Incomplete isochronous OUT - transfer. */ -#define GINTSTS_IISOIXFR (1U<<20) /**< Incomplete isochronous IN - transfer. */ -#define GINTSTS_OEPINT (1U<<19) /**< OUT endpoints interrupt. */ -#define GINTSTS_IEPINT (1U<<18) /**< IN endpoints interrupt. */ -#define GINTSTS_EOPF (1U<<15) /**< End of periodic frame - interrupt. */ -#define GINTSTS_ISOODRP (1U<<14) /**< Isochronous OUT packet - dropped interrupt. */ -#define GINTSTS_ENUMDNE (1U<<13) /**< Enumeration done. */ -#define GINTSTS_USBRST (1U<<12) /**< USB reset. */ -#define GINTSTS_USBSUSP (1U<<11) /**< USB suspend. */ -#define GINTSTS_ESUSP (1U<<10) /**< Early suspend. */ -#define GINTSTS_GONAKEFF (1U<<7) /**< Global OUT NAK effective. */ -#define GINTSTS_GINAKEFF (1U<<6) /**< Global IN non-periodic NAK - effective. */ -#define GINTSTS_NPTXFE (1U<<5) /**< Non-periodic TxFIFO empty. */ -#define GINTSTS_RXFLVL (1U<<4) /**< RxFIFO non-empty. */ -#define GINTSTS_SOF (1U<<3) /**< Start of frame. */ -#define GINTSTS_OTGINT (1U<<2) /**< OTG interrupt. */ -#define GINTSTS_MMIS (1U<<1) /**< Mode Mismatch interrupt. */ -#define GINTSTS_CMOD (1U<<0) /**< Current mode of operation. */ -/** @} */ - -/** - * @name GINTMSK register bit definitions - * @{ - */ -#define GINTMSK_WKUM (1U<<31) /**< Resume/remote wakeup - detected interrupt mask. */ -#define GINTMSK_SRQM (1U<<30) /**< Session request/New session - detected interrupt mask. */ -#define GINTMSK_DISCM (1U<<29) /**< Disconnect detected - interrupt mask. */ -#define GINTMSK_CIDSCHGM (1U<<28) /**< Connector ID status change - mask. */ -#define GINTMSK_PTXFEM (1U<<26) /**< Periodic TxFIFO empty mask.*/ -#define GINTMSK_HCM (1U<<25) /**< Host channels interrupt - mask. */ -#define GINTMSK_HPRTM (1U<<24) /**< Host port interrupt mask. */ -#define GINTMSK_IPXFRM (1U<<21) /**< Incomplete periodic - transfer mask. */ -#define GINTMSK_IISOOXFRM (1U<<21) /**< Incomplete isochronous OUT - transfer mask. */ -#define GINTMSK_IISOIXFRM (1U<<20) /**< Incomplete isochronous IN - transfer mask. */ -#define GINTMSK_OEPM (1U<<19) /**< OUT endpoints interrupt - mask. */ -#define GINTMSK_IEPM (1U<<18) /**< IN endpoints interrupt - mask. */ -#define GINTMSK_EOPFM (1U<<15) /**< End of periodic frame - interrupt mask. */ -#define GINTMSK_ISOODRPM (1U<<14) /**< Isochronous OUT packet - dropped interrupt mask. */ -#define GINTMSK_ENUMDNEM (1U<<13) /**< Enumeration done mask. */ -#define GINTMSK_USBRSTM (1U<<12) /**< USB reset mask. */ -#define GINTMSK_USBSUSPM (1U<<11) /**< USB suspend mask. */ -#define GINTMSK_ESUSPM (1U<<10) /**< Early suspend mask. */ -#define GINTMSK_GONAKEFFM (1U<<7) /**< Global OUT NAK effective - mask. */ -#define GINTMSK_GINAKEFFM (1U<<6) /**< Global non-periodic IN NAK - effective mask. */ -#define GINTMSK_NPTXFEM (1U<<5) /**< Non-periodic TxFIFO empty - mask. */ -#define GINTMSK_RXFLVLM (1U<<4) /**< Receive FIFO non-empty - mask. */ -#define GINTMSK_SOFM (1U<<3) /**< Start of (micro)frame mask.*/ -#define GINTMSK_OTGM (1U<<2) /**< OTG interrupt mask. */ -#define GINTMSK_MMISM (1U<<1) /**< Mode Mismatch interrupt - mask. */ -/** @} */ - -/** - * @name GRXSTSR register bit definitions - * @{ - */ -#define GRXSTSR_PKTSTS_MASK (15U<<17) /**< Packet status mask. */ -#define GRXSTSR_PKTSTS(n) ((n)<<17) /**< Packet status value. */ -#define GRXSTSR_OUT_GLOBAL_NAK GRXSTSR_PKTSTS(1) -#define GRXSTSR_OUT_DATA GRXSTSR_PKTSTS(2) -#define GRXSTSR_OUT_COMP GRXSTSR_PKTSTS(3) -#define GRXSTSR_SETUP_COMP GRXSTSR_PKTSTS(4) -#define GRXSTSR_SETUP_DATA GRXSTSR_PKTSTS(6) -#define GRXSTSR_DPID_MASK (3U<<15) /**< Data PID mask. */ -#define GRXSTSR_DPID(n) ((n)<<15) /**< Data PID value. */ -#define GRXSTSR_BCNT_MASK (0x7FF<<4) /**< Byte count mask. */ -#define GRXSTSR_BCNT(n) ((n)<<4) /**< Byte count value. */ -#define GRXSTSR_CHNUM_MASK (15U<<0) /**< Channel number mask. */ -#define GRXSTSR_CHNUM(n) ((n)<<0) /**< Channel number value. */ -#define GRXSTSR_EPNUM_MASK (15U<<0) /**< Endpoint number mask. */ -#define GRXSTSR_EPNUM(n) ((n)<<0) /**< Endpoint number value. */ -/** @} */ - -/** - * @name GRXSTSP register bit definitions - * @{ - */ -#define GRXSTSP_PKTSTS_MASK (15<<17) /**< Packet status mask. */ -#define GRXSTSP_PKTSTS(n) ((n)<<17) /**< Packet status value. */ -#define GRXSTSP_OUT_GLOBAL_NAK GRXSTSP_PKTSTS(1) -#define GRXSTSP_OUT_DATA GRXSTSP_PKTSTS(2) -#define GRXSTSP_OUT_COMP GRXSTSP_PKTSTS(3) -#define GRXSTSP_SETUP_COMP GRXSTSP_PKTSTS(4) -#define GRXSTSP_SETUP_DATA GRXSTSP_PKTSTS(6) -#define GRXSTSP_DPID_MASK (3U<<15) /**< Data PID mask. */ -#define GRXSTSP_DPID(n) ((n)<<15) /**< Data PID value. */ -#define GRXSTSP_BCNT_MASK (0x7FF<<4) /**< Byte count mask. */ -#define GRXSTSP_BCNT_OFF 4 /**< Byte count offset. */ -#define GRXSTSP_BCNT(n) ((n)<<4) /**< Byte count value. */ -#define GRXSTSP_CHNUM_MASK (15U<<0) /**< Channel number mask. */ -#define GRXSTSP_CHNUM(n) ((n)<<0) /**< Channel number value. */ -#define GRXSTSP_EPNUM_MASK (15U<<0) /**< Endpoint number mask. */ -#define GRXSTSP_EPNUM_OFF 0 /**< Endpoint number offset. */ -#define GRXSTSP_EPNUM(n) ((n)<<0) /**< Endpoint number value. */ -/** @} */ - -/** - * @name GRXFSIZ register bit definitions - * @{ - */ -#define GRXFSIZ_RXFD_MASK (0xFFFF<<0) /**< RxFIFO depth mask. */ -#define GRXFSIZ_RXFD(n) ((n)<<0) /**< RxFIFO depth value. */ -/** @} */ - -/** - * @name DIEPTXFx register bit definitions - * @{ - */ -#define DIEPTXF_INEPTXFD_MASK (0xFFFFU<<16)/**< IN endpoint TxFIFO depth - mask. */ -#define DIEPTXF_INEPTXFD(n) ((n)<<16) /**< IN endpoint TxFIFO depth - value. */ -#define DIEPTXF_INEPTXSA_MASK (0xFFFF<<0) /**< IN endpoint FIFOx transmit - RAM start address mask. */ -#define DIEPTXF_INEPTXSA(n) ((n)<<0) /**< IN endpoint FIFOx transmit - RAM start address value. */ -/** @} */ - -/** - * @name GCCFG register bit definitions - * @{ - */ -#define GCCFG_NOVBUSSENS (1U<<21) /**< VBUS sensing disable. */ -#define GCCFG_SOFOUTEN (1U<<20) /**< SOF output enable. */ -#define GCCFG_VBUSBSEN (1U<<19) /**< Enable the VBUS sensing "B" - device. */ -#define GCCFG_VBUSASEN (1U<<18) /**< Enable the VBUS sensing "A" - device. */ -#define GCCFG_PWRDWN (1U<<16) /**< Power down. */ -/** @} */ - -/** - * @name HPTXFSIZ register bit definitions - * @{ - */ -#define HPTXFSIZ_PTXFD_MASK (0xFFFFU<<16)/**< Host periodic TxFIFO - depth mask. */ -#define HPTXFSIZ_PTXFD(n) ((n)<<16) /**< Host periodic TxFIFO - depth value. */ -#define HPTXFSIZ_PTXSA_MASK (0xFFFFU<<0)/**< Host periodic TxFIFO - Start address mask. */ -#define HPTXFSIZ_PTXSA(n) ((n)<<0) /**< Host periodic TxFIFO - start address value. */ -/** @} */ - -/** - * @name HCFG register bit definitions - * @{ - */ -#define HCFG_FSLSS (1U<<2) /**< FS- and LS-only support. */ -#define HCFG_FSLSPCS_MASK (3U<<0) /**< FS/LS PHY clock select - mask. */ -#define HCFG_FSLSPCS_48 (1U<<0) /**< PHY clock is running at - 48 MHz. */ -#define HCFG_FSLSPCS_6 (2U<<0) /**< PHY clock is running at - 6 MHz. */ -/** @} */ - -/** - * @name HFIR register bit definitions - * @{ - */ -#define HFIR_FRIVL_MASK (0xFFFFU<<0)/**< Frame interval mask. */ -#define HFIR_FRIVL(n) ((n)<<0) /**< Frame interval value. */ -/** @} */ - -/** - * @name HFNUM register bit definitions - * @{ - */ -#define HFNUM_FTREM_MASK (0xFFFFU<<16)/**< Frame time Remaining mask.*/ -#define HFNUM_FTREM(n) ((n)<<16) /**< Frame time Remaining value.*/ -#define HFNUM_FRNUM_MASK (0xFFFFU<<0)/**< Frame number mask. */ -#define HFNUM_FRNUM(n) ((n)<<0) /**< Frame number value. */ -/** @} */ - -/** - * @name HPTXSTS register bit definitions - * @{ - */ -#define HPTXSTS_PTXQTOP_MASK (0xFFU<<24) /**< Top of the periodic - transmit request queue - mask. */ -#define HPTXSTS_PTXQTOP(n) ((n)<<24) /**< Top of the periodic - transmit request queue - value. */ -#define HPTXSTS_PTXQSAV_MASK (0xFF<<16) /**< Periodic transmit request - queue Space Available - mask. */ -#define HPTXSTS_PTXQSAV(n) ((n)<<16) /**< Periodic transmit request - queue Space Available - value. */ -#define HPTXSTS_PTXFSAVL_MASK (0xFFFF<<0) /**< Periodic transmit Data - FIFO Space Available - mask. */ -#define HPTXSTS_PTXFSAVL(n) ((n)<<0) /**< Periodic transmit Data - FIFO Space Available - value. */ -/** @} */ - -/** - * @name HAINT register bit definitions - * @{ - */ -#define HAINT_HAINT_MASK (0xFFFFU<<0)/**< Channel interrupts mask. */ -#define HAINT_HAINT(n) ((n)<<0) /**< Channel interrupts value. */ -/** @} */ - -/** - * @name HAINTMSK register bit definitions - * @{ - */ -#define HAINTMSK_HAINTM_MASK (0xFFFFU<<0)/**< Channel interrupt mask - mask. */ -#define HAINTMSK_HAINTM(n) ((n)<<0) /**< Channel interrupt mask - value. */ -/** @} */ - -/** - * @name HPRT register bit definitions - * @{ - */ -#define HPRT_PSPD_MASK (3U<<17) /**< Port speed mask. */ -#define HPRT_PSPD_FS (1U<<17) /**< Full speed value. */ -#define HPRT_PSPD_LS (2U<<17) /**< Low speed value. */ -#define HPRT_PTCTL_MASK (15<<13) /**< Port Test control mask. */ -#define HPRT_PTCTL(n) ((n)<<13) /**< Port Test control value. */ -#define HPRT_PPWR (1U<<12) /**< Port power. */ -#define HPRT_PLSTS_MASK (3U<<11) /**< Port Line status mask. */ -#define HPRT_PLSTS_DM (1U<<11) /**< Logic level of D-. */ -#define HPRT_PLSTS_DP (1U<<10) /**< Logic level of D+. */ -#define HPRT_PRST (1U<<8) /**< Port reset. */ -#define HPRT_PSUSP (1U<<7) /**< Port suspend. */ -#define HPRT_PRES (1U<<6) /**< Port Resume. */ -#define HPRT_POCCHNG (1U<<5) /**< Port overcurrent change. */ -#define HPRT_POCA (1U<<4) /**< Port overcurrent active. */ -#define HPRT_PENCHNG (1U<<3) /**< Port enable/disable change.*/ -#define HPRT_PENA (1U<<2) /**< Port enable. */ -#define HPRT_PCDET (1U<<1) /**< Port Connect detected. */ -#define HPRT_PCSTS (1U<<0) /**< Port connect status. */ -/** @} */ - -/** - * @name HCCHAR register bit definitions - * @{ - */ -#define HCCHAR_CHENA (1U<<31) /**< Channel enable. */ -#define HCCHAR_CHDIS (1U<<30) /**< Channel Disable. */ -#define HCCHAR_ODDFRM (1U<<29) /**< Odd frame. */ -#define HCCHAR_DAD_MASK (0x7FU<<22) /**< Device Address mask. */ -#define HCCHAR_DAD(n) ((n)<<22) /**< Device Address value. */ -#define HCCHAR_MCNT_MASK (3U<<20) /**< Multicount mask. */ -#define HCCHAR_MCNT(n) ((n)<<20) /**< Multicount value. */ -#define HCCHAR_EPTYP_MASK (3U<<18) /**< Endpoint type mask. */ -#define HCCHAR_EPTYP(n) ((n)<<18) /**< Endpoint type value. */ -#define HCCHAR_EPTYP_CTL (0U<<18) /**< Control endpoint value. */ -#define HCCHAR_EPTYP_ISO (1U<<18) /**< Isochronous endpoint value.*/ -#define HCCHAR_EPTYP_BULK (2U<<18) /**< Bulk endpoint value. */ -#define HCCHAR_EPTYP_INTR (3U<<18) /**< Interrupt endpoint value. */ -#define HCCHAR_LSDEV (1U<<17) /**< Low-Speed device. */ -#define HCCHAR_EPDIR (1U<<15) /**< Endpoint direction. */ -#define HCCHAR_EPNUM_MASK (15U<<11) /**< Endpoint number mask. */ -#define HCCHAR_EPNUM(n) ((n)<<11) /**< Endpoint number value. */ -#define HCCHAR_MPS_MASK (11U<<0) /**< Maximum packet size mask. */ -#define HCCHAR_MPS(n) (11U<<0) /**< Maximum packet size value. */ -/** @} */ - -/** - * @name HCINT register bit definitions - * @{ - */ -#define HCINT_DTERR (1U<<10) /**< Data toggle error. */ -#define HCINT_FRMOR (1U<<9) /**< Frame overrun. */ -#define HCINT_BBERR (1U<<8) /**< Babble error. */ -#define HCINT_TRERR (1U<<7) /**< Transaction Error. */ -#define HCINT_ACK (1U<<5) /**< ACK response - received/transmitted - interrupt. */ -#define HCINT_NAK (1U<<4) /**< NAK response received - interrupt. */ -#define HCINT_STALL (1U<<3) /**< STALL response received - interrupt. */ -#define HCINT_CHH (1U<<1) /**< Channel halted. */ -#define HCINT_XFRC (1U<<0) /**< Transfer completed. */ -/** @} */ - -/** - * @name HCINTMSK register bit definitions - * @{ - */ -#define HCINTMSK_DTERRM (1U<<10) /**< Data toggle error mask. */ -#define HCINTMSK_FRMORM (1U<<9) /**< Frame overrun mask. */ -#define HCINTMSK_BBERRM (1U<<8) /**< Babble error mask. */ -#define HCINTMSK_TRERRM (1U<<7) /**< Transaction error mask. */ -#define HCINTMSK_NYET (1U<<6) /**< NYET response received - interrupt mask. */ -#define HCINTMSK_ACKM (1U<<5) /**< ACK Response - received/transmitted - interrupt mask. */ -#define HCINTMSK_NAKM (1U<<4) /**< NAK response received - interrupt mask. */ -#define HCINTMSK_STALLM (1U<<3) /**< STALL response received - interrupt mask. */ -#define HCINTMSK_CHHM (1U<<1) /**< Channel halted mask. */ -#define HCINTMSK_XFRCM (1U<<0) /**< Transfer completed mask. */ -/** @} */ - -/** - * @name HCTSIZ register bit definitions - * @{ - */ -#define HCTSIZ_DPID_MASK (3U<<29) /**< PID mask. */ -#define HCTSIZ_DPID_DATA0 (0U<<29) /**< DATA0. */ -#define HCTSIZ_DPID_DATA2 (1U<<29) /**< DATA2. */ -#define HCTSIZ_DPID_DATA1 (2U<<29) /**< DATA1. */ -#define HCTSIZ_DPID_MDATA (3U<<29) /**< MDATA. */ -#define HCTSIZ_PKTCNT_MASK (0x3FFU<<19)/**< Packet count mask. */ -#define HCTSIZ_PKTCNT(n) ((n)<<19) /**< Packet count value. */ -#define HCTSIZ_XFRSIZ_MASK (0x7FFFF<<0)/**< Transfer size mask. */ -#define HCTSIZ_XFRSIZ(n) ((n)<<0) /**< Transfer size value. */ -/** @} */ - -/** - * @name DCFG register bit definitions - * @{ - */ -#define DCFG_PFIVL_MASK (3U<<11) /**< Periodic frame interval - mask. */ -#define DCFG_PFIVL(n) ((n)<<11) /**< Periodic frame interval - value. */ -#define DCFG_DAD_MASK (0x7FU<<4) /**< Device address mask. */ -#define DCFG_DAD(n) ((n)<<4) /**< Device address value. */ -#define DCFG_NZLSOHSK (1U<<2) /**< Non-Zero-Length status - OUT handshake. */ -#define DCFG_DSPD_MASK (3U<<0) /**< Device speed mask. */ -#define DCFG_DSPD_HS (0U<<0) /**< High speed (USB 2.0). */ -#define DCFG_DSPD_HS_FS (1U<<0) /**< High speed (USB 2.0) in FS - mode. */ -#define DCFG_DSPD_FS11 (3U<<0) /**< Full speed (USB 1.1 - transceiver clock is 48 - MHz). */ -/** @} */ - -/** - * @name DCTL register bit definitions - * @{ - */ -#define DCTL_POPRGDNE (1U<<11) /**< Power-on programming done. */ -#define DCTL_CGONAK (1U<<10) /**< Clear global OUT NAK. */ -#define DCTL_SGONAK (1U<<9) /**< Set global OUT NAK. */ -#define DCTL_CGINAK (1U<<8) /**< Clear global non-periodic - IN NAK. */ -#define DCTL_SGINAK (1U<<7) /**< Set global non-periodic - IN NAK. */ -#define DCTL_TCTL_MASK (7U<<4) /**< Test control mask. */ -#define DCTL_TCTL(n) ((n)<<4 /**< Test control value. */ -#define DCTL_GONSTS (1U<<3) /**< Global OUT NAK status. */ -#define DCTL_GINSTS (1U<<2) /**< Global non-periodic IN - NAK status. */ -#define DCTL_SDIS (1U<<1) /**< Soft disconnect. */ -#define DCTL_RWUSIG (1U<<0) /**< Remote wakeup signaling. */ -/** @} */ - -/** - * @name DSTS register bit definitions - * @{ - */ -#define DSTS_FNSOF_MASK (0x3FFU<<8) /**< Frame number of the received - SOF mask. */ -#define DSTS_FNSOF(n) ((n)<<8) /**< Frame number of the received - SOF value. */ -#define DSTS_EERR (1U<<3) /**< Erratic error. */ -#define DSTS_ENUMSPD_MASK (3U<<1) /**< Enumerated speed mask. */ -#define DSTS_ENUMSPD_FS_48 (3U<<1) /**< Full speed (PHY clock is - running at 48 MHz). */ -#define DSTS_SUSPSTS (1U<<0) /**< Suspend status. */ -/** @} */ - -/** - * @name DIEPMSK register bit definitions - * @{ - */ -#define DIEPMSK_TXFEM (1U<<6) /**< Transmit FIFO empty mask. */ -#define DIEPMSK_INEPNEM (1U<<6) /**< IN endpoint NAK effective - mask. */ -#define DIEPMSK_ITTXFEMSK (1U<<4) /**< IN token received when - TxFIFO empty mask. */ -#define DIEPMSK_TOCM (1U<<3) /**< Timeout condition mask. */ -#define DIEPMSK_EPDM (1U<<1) /**< Endpoint disabled - interrupt mask. */ -#define DIEPMSK_XFRCM (1U<<0) /**< Transfer completed - interrupt mask. */ -/** @} */ - -/** - * @name DOEPMSK register bit definitions - * @{ - */ -#define DOEPMSK_OTEPDM (1U<<4) /**< OUT token received when - endpoint disabled mask. */ -#define DOEPMSK_STUPM (1U<<3) /**< SETUP phase done mask. */ -#define DOEPMSK_EPDM (1U<<1) /**< Endpoint disabled - interrupt mask. */ -#define DOEPMSK_XFRCM (1U<<0) /**< Transfer completed - interrupt mask. */ -/** @} */ - -/** - * @name DAINT register bit definitions - * @{ - */ -#define DAINT_OEPINT_MASK (0xFFFFU<<16)/**< OUT endpoint interrupt - bits mask. */ -#define DAINT_OEPINT(n) ((n)<<16) /**< OUT endpoint interrupt - bits value. */ -#define DAINT_IEPINT_MASK (0xFFFFU<<0)/**< IN endpoint interrupt - bits mask. */ -#define DAINT_IEPINT(n) ((n)<<0) /**< IN endpoint interrupt - bits value. */ -/** @} */ - -/** - * @name DAINTMSK register bit definitions - * @{ - */ -#define DAINTMSK_OEPM_MASK (0xFFFFU<<16)/**< OUT EP interrupt mask - bits mask. */ -#define DAINTMSK_OEPM(n) (1U<<(16+(n)))/**< OUT EP interrupt mask - bits value. */ -#define DAINTMSK_IEPM_MASK (0xFFFFU<<0)/**< IN EP interrupt mask - bits mask. */ -#define DAINTMSK_IEPM(n) (1U<<(n)) /**< IN EP interrupt mask - bits value. */ -/** @} */ - -/** - * @name DVBUSDIS register bit definitions - * @{ - */ -#define DVBUSDIS_VBUSDT_MASK (0xFFFFU<<0)/**< Device VBUS discharge - time mask. */ -#define DVBUSDIS_VBUSDT(n) ((n)<<0) /**< Device VBUS discharge - time value. */ -/** @} */ - -/** - * @name DVBUSPULSE register bit definitions - * @{ - */ -#define DVBUSPULSE_DVBUSP_MASK (0xFFFU<<0) /**< Device VBUSpulsing time - mask. */ -#define DVBUSPULSE_DVBUSP(n) ((n)<<0) /**< Device VBUS pulsing time - value. */ -/** @} */ - -/** - * @name DIEPEMPMSK register bit definitions - * @{ - */ -#define DIEPEMPMSK_INEPTXFEM(n) (1U<<(n)) /**< IN EP Tx FIFO empty - interrupt mask bit. */ -/** @} */ - -/** - * @name DIEPCTL register bit definitions - * @{ - */ -#define DIEPCTL_EPENA (1U<<31) /**< Endpoint enable. */ -#define DIEPCTL_EPDIS (1U<<30) /**< Endpoint disable. */ -#define DIEPCTL_SD1PID (1U<<29) /**< Set DATA1 PID. */ -#define DIEPCTL_SODDFRM (1U<<29) /**< Set odd frame. */ -#define DIEPCTL_SD0PID (1U<<28) /**< Set DATA0 PID. */ -#define DIEPCTL_SEVNFRM (1U<<28) /**< Set even frame. */ -#define DIEPCTL_SNAK (1U<<27) /**< Set NAK. */ -#define DIEPCTL_CNAK (1U<<26) /**< Clear NAK. */ -#define DIEPCTL_TXFNUM_MASK (15U<<22) /**< TxFIFO number mask. */ -#define DIEPCTL_TXFNUM(n) ((n)<<22) /**< TxFIFO number value. */ -#define DIEPCTL_STALL (1U<<21) /**< STALL handshake. */ -#define DIEPCTL_SNPM (1U<<20) /**< Snoop mode. */ -#define DIEPCTL_EPTYP_MASK (3<<18) /**< Endpoint type mask. */ -#define DIEPCTL_EPTYP_CTRL (0U<<18) /**< Control. */ -#define DIEPCTL_EPTYP_ISO (1U<<18) /**< Isochronous. */ -#define DIEPCTL_EPTYP_BULK (2U<<18) /**< Bulk. */ -#define DIEPCTL_EPTYP_INTR (3U<<18) /**< Interrupt. */ -#define DIEPCTL_NAKSTS (1U<<17) /**< NAK status. */ -#define DIEPCTL_EONUM (1U<<16) /**< Even/odd frame. */ -#define DIEPCTL_DPID (1U<<16) /**< Endpoint data PID. */ -#define DIEPCTL_USBAEP (1U<<15) /**< USB active endpoint. */ -#define DIEPCTL_MPSIZ_MASK (0x3FFU<<0) /**< Maximum Packet size mask. */ -#define DIEPCTL_MPSIZ(n) ((n)<<0) /**< Maximum Packet size value. */ -/** @} */ - -/** - * @name DIEPINT register bit definitions - * @{ - */ -#define DIEPINT_TXFE (1U<<7) /**< Transmit FIFO empty. */ -#define DIEPINT_INEPNE (1U<<6) /**< IN endpoint NAK effective. */ -#define DIEPINT_ITTXFE (1U<<4) /**< IN Token received when - TxFIFO is empty. */ -#define DIEPINT_TOC (1U<<3) /**< Timeout condition. */ -#define DIEPINT_EPDISD (1U<<1) /**< Endpoint disabled - interrupt. */ -#define DIEPINT_XFRC (1U<<0) /**< Transfer completed. */ -/** @} */ - -/** - * @name DIEPTSIZ register bit definitions - * @{ - */ -#define DIEPTSIZ_MCNT_MASK (3U<<29) /**< Multi count mask. */ -#define DIEPTSIZ_MCNT(n) ((n)<<29) /**< Multi count value. */ -#define DIEPTSIZ_PKTCNT_MASK (0x3FF<<19) /**< Packet count mask. */ -#define DIEPTSIZ_PKTCNT(n) ((n)<<19) /**< Packet count value. */ -#define DIEPTSIZ_XFRSIZ_MASK (0x7FFFFU<<0)/**< Transfer size mask. */ -#define DIEPTSIZ_XFRSIZ(n) ((n)<<0) /**< Transfer size value. */ -/** @} */ - -/** - * @name DTXFSTS register bit definitions. - * @{ - */ -#define DTXFSTS_INEPTFSAV_MASK (0xFFFF<<0) /**< IN endpoint TxFIFO space - available. */ -/** @} */ - -/** - * @name DOEPCTL register bit definitions. - * @{ - */ -#define DOEPCTL_EPENA (1U<<31) /**< Endpoint enable. */ -#define DOEPCTL_EPDIS (1U<<30) /**< Endpoint disable. */ -#define DOEPCTL_SD1PID (1U<<29) /**< Set DATA1 PID. */ -#define DOEPCTL_SODDFRM (1U<<29) /**< Set odd frame. */ -#define DOEPCTL_SD0PID (1U<<28) /**< Set DATA0 PID. */ -#define DOEPCTL_SEVNFRM (1U<<28) /**< Set even frame. */ -#define DOEPCTL_SNAK (1U<<27) /**< Set NAK. */ -#define DOEPCTL_CNAK (1U<<26) /**< Clear NAK. */ -#define DOEPCTL_STALL (1U<<21) /**< STALL handshake. */ -#define DOEPCTL_SNPM (1U<<20) /**< Snoop mode. */ -#define DOEPCTL_EPTYP_MASK (3U<<18) /**< Endpoint type mask. */ -#define DOEPCTL_EPTYP_CTRL (0U<<18) /**< Control. */ -#define DOEPCTL_EPTYP_ISO (1U<<18) /**< Isochronous. */ -#define DOEPCTL_EPTYP_BULK (2U<<18) /**< Bulk. */ -#define DOEPCTL_EPTYP_INTR (3U<<18) /**< Interrupt. */ -#define DOEPCTL_NAKSTS (1U<<17) /**< NAK status. */ -#define DOEPCTL_EONUM (1U<<16) /**< Even/odd frame. */ -#define DOEPCTL_DPID (1U<<16) /**< Endpoint data PID. */ -#define DOEPCTL_USBAEP (1U<<15) /**< USB active endpoint. */ -#define DOEPCTL_MPSIZ_MASK (0x3FFU<<0) /**< Maximum Packet size mask. */ -#define DOEPCTL_MPSIZ(n) ((n)<<0) /**< Maximum Packet size value. */ -/** @} */ - -/** - * @name DOEPINT register bit definitions - * @{ - */ -#define DOEPINT_B2BSTUP (1U<<6) /**< Back-to-back SETUP packets - received. */ -#define DOEPINT_OTEPDIS (1U<<4) /**< OUT token received when - endpoint disabled. */ -#define DOEPINT_STUP (1U<<3) /**< SETUP phase done. */ -#define DOEPINT_EPDISD (1U<<1) /**< Endpoint disabled - interrupt. */ -#define DOEPINT_XFRC (1U<<0) /**< Transfer completed - interrupt. */ -/** @} */ - -/** - * @name DOEPTSIZ register bit definitions - * @{ - */ -#define DOEPTSIZ_RXDPID_MASK (3U<<29) /**< Received data PID mask. */ -#define DOEPTSIZ_RXDPID(n) ((n)<<29) /**< Received data PID value. */ -#define DOEPTSIZ_STUPCNT_MASK (3U<<29) /**< SETUP packet count mask. */ -#define DOEPTSIZ_STUPCNT(n) ((n)<<29) /**< SETUP packet count value. */ -#define DOEPTSIZ_PKTCNT_MASK (0x3FFU<<19)/**< Packet count mask. */ -#define DOEPTSIZ_PKTCNT(n) ((n)<<19) /**< Packet count value. */ -#define DOEPTSIZ_XFRSIZ_MASK (0x7FFFFU<<0)/**< Transfer size mask. */ -#define DOEPTSIZ_XFRSIZ(n) ((n)<<0) /**< Transfer size value. */ -/** @} */ - -/** - * @name PCGCCTL register bit definitions - * @{ - */ -#define PCGCCTL_PHYSUSP (1U<<4) /**< PHY Suspended. */ -#define PCGCCTL_GATEHCLK (1U<<1) /**< Gate HCLK. */ -#define PCGCCTL_STPPCLK (1U<<0) /**< Stop PCLK. */ -/** @} */ - -/** - * @brief OTG_FS registers block memory address. - */ -#define OTG_FS_ADDR 0x50000000 - -/** - * @brief OTG_HS registers block memory address. - */ -#define OTG_HS_ADDR 0x40040000 - -/** - * @brief Accesses to the OTG_FS registers block. - */ -#define OTG_FS ((stm32_otg_t *)OTG_FS_ADDR) - -/** - * @brief Accesses to the OTG_HS registers block. - */ -#define OTG_HS ((stm32_otg_t *)OTG_HS_ADDR) - -#endif /* _STM32_OTG_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/OTGv1/usb_lld.c b/firmware/chibios/os/hal/platforms/STM32/OTGv1/usb_lld.c deleted file mode 100644 index 99ab0762d8..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/OTGv1/usb_lld.c +++ /dev/null @@ -1,1356 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/OTGv1/usb_lld.c - * @brief STM32 USB subsystem low level driver source. - * - * @addtogroup USB - * @{ - */ - -#include - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_USB || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define TRDT_VALUE 5 - -#define EP0_MAX_INSIZE 64 -#define EP0_MAX_OUTSIZE 64 - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief OTG_FS driver identifier.*/ -#if STM32_USB_USE_OTG1 || defined(__DOXYGEN__) -USBDriver USBD1; -#endif - -/** @brief OTG_HS driver identifier.*/ -#if STM32_USB_USE_OTG2 || defined(__DOXYGEN__) -USBDriver USBD2; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief EP0 state. - * @note It is an union because IN and OUT endpoints are never used at the - * same time for EP0. - */ -static union { - /** - * @brief IN EP0 state. - */ - USBInEndpointState in; - /** - * @brief OUT EP0 state. - */ - USBOutEndpointState out; -} ep0_state; - -/** - * @brief Buffer for the EP0 setup packets. - */ -static uint8_t ep0setup_buffer[8]; - -/** - * @brief EP0 initialization structure. - */ -static const USBEndpointConfig ep0config = { - USB_EP_MODE_TYPE_CTRL, - _usb_ep0setup, - _usb_ep0in, - _usb_ep0out, - 0x40, - 0x40, - &ep0_state.in, - &ep0_state.out, - 1, - ep0setup_buffer -}; - -#if STM32_USB_USE_OTG1 -static const stm32_otg_params_t fsparams = { - STM32_USB_OTG1_RX_FIFO_SIZE / 4, - STM32_OTG1_FIFO_MEM_SIZE, - STM32_OTG1_ENDOPOINTS_NUMBER -}; -#endif - -#if STM32_USB_USE_OTG2 -static const stm32_otg_params_t hsparams = { - STM32_USB_OTG2_RX_FIFO_SIZE / 4, - STM32_OTG2_FIFO_MEM_SIZE, - STM32_OTG2_ENDOPOINTS_NUMBER -}; -#endif - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Wakes up the pump thread. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -static void usb_lld_wakeup_pump(USBDriver *usbp) { - - if (usbp->thd_wait != NULL) { - chThdResumeI(usbp->thd_wait); - usbp->thd_wait = NULL; - } -} - -static void otg_core_reset(USBDriver *usbp) { - stm32_otg_t *otgp = usbp->otg; - - halPolledDelay(32); - - /* Core reset and delay of at least 3 PHY cycles.*/ - otgp->GRSTCTL = GRSTCTL_CSRST; - while ((otgp->GRSTCTL & GRSTCTL_CSRST) != 0) - ; - - halPolledDelay(12); - - /* Wait AHB idle condition.*/ - while ((otgp->GRSTCTL & GRSTCTL_AHBIDL) == 0) - ; -} - -static void otg_disable_ep(USBDriver *usbp) { - stm32_otg_t *otgp = usbp->otg; - unsigned i; - - for (i = 0; i <= usbp->otgparams->num_endpoints; i++) { - /* Disable only if enabled because this sentence in the manual: - "The application must set this bit only if Endpoint Enable is - already set for this endpoint".*/ - if ((otgp->ie[i].DIEPCTL & DIEPCTL_EPENA) != 0) { - otgp->ie[i].DIEPCTL = DIEPCTL_EPDIS; - /* Wait for endpoint disable.*/ - while (!(otgp->ie[i].DIEPINT & DIEPINT_EPDISD)) - ; - } - else - otgp->ie[i].DIEPCTL = 0; - otgp->ie[i].DIEPTSIZ = 0; - otgp->ie[i].DIEPINT = 0xFFFFFFFF; - /* Disable only if enabled because this sentence in the manual: - "The application must set this bit only if Endpoint Enable is - already set for this endpoint". - Note that the attempt to disable the OUT EP0 is ignored by the - hardware but the code is simpler this way.*/ - if ((otgp->oe[i].DOEPCTL & DOEPCTL_EPENA) != 0) { - otgp->oe[i].DOEPCTL = DOEPCTL_EPDIS; - /* Wait for endpoint disable.*/ - while (!(otgp->oe[i].DOEPINT & DOEPINT_OTEPDIS)) - ; - } - else - otgp->oe[i].DOEPCTL = 0; - otgp->oe[i].DOEPTSIZ = 0; - otgp->oe[i].DOEPINT = 0xFFFFFFFF; - } - otgp->DAINTMSK = DAINTMSK_OEPM(0) | DAINTMSK_IEPM(0); -} - -static void otg_rxfifo_flush(USBDriver *usbp) { - stm32_otg_t *otgp = usbp->otg; - - otgp->GRSTCTL = GRSTCTL_RXFFLSH; - while ((otgp->GRSTCTL & GRSTCTL_RXFFLSH) != 0) - ; - /* Wait for 3 PHY Clocks.*/ - halPolledDelay(12); -} - -static void otg_txfifo_flush(USBDriver *usbp, uint32_t fifo) { - stm32_otg_t *otgp = usbp->otg; - - otgp->GRSTCTL = GRSTCTL_TXFNUM(fifo) | GRSTCTL_TXFFLSH; - while ((otgp->GRSTCTL & GRSTCTL_TXFFLSH) != 0) - ; - /* Wait for 3 PHY Clocks.*/ - halPolledDelay(12); -} - -/** - * @brief Resets the FIFO RAM memory allocator. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -static void otg_ram_reset(USBDriver *usbp) { - - usbp->pmnext = usbp->otgparams->rx_fifo_size; -} - -/** - * @brief Allocates a block from the FIFO RAM memory. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] size size of the packet buffer to allocate in words - * - * @notapi - */ -static uint32_t otg_ram_alloc(USBDriver *usbp, size_t size) { - uint32_t next; - - next = usbp->pmnext; - usbp->pmnext += size; - chDbgAssert(usbp->pmnext <= usbp->otgparams->otg_ram_size, - "otg_fifo_alloc(), #1", "OTG FIFO memory overflow"); - return next; -} - -/** - * @brief Pushes a series of words into a FIFO. - * - * @param[in] fifop pointer to the FIFO register - * @param[in] buf pointer to the words buffer, not necessarily word - * aligned - * @param[in] n number of words to push - * - * @return A pointer after the last word pushed. - * - * @notapi - */ -static uint8_t *otg_do_push(volatile uint32_t *fifop, uint8_t *buf, size_t n) { - - while (n > 0) { - /* Note, this line relies on the Cortex-M3/M4 ability to perform - unaligned word accesses and on the LSB-first memory organization.*/ - *fifop = *((PACKED_VAR uint32_t *)buf); - buf += 4; - n--; - } - return buf; -} - -/** - * @brief Writes to a TX FIFO. - * - * @param[in] fifop pointer to the FIFO register - * @param[in] buf buffer where to copy the endpoint data - * @param[in] n maximum number of bytes to copy - * - * @notapi - */ -static void otg_fifo_write_from_buffer(volatile uint32_t *fifop, - const uint8_t *buf, - size_t n) { - - otg_do_push(fifop, (uint8_t *)buf, (n + 3) / 4); -} - -/** - * @brief Writes to a TX FIFO fetching data from a queue. - * - * @param[in] fifop pointer to the FIFO register - * @param[in] oqp pointer to an @p OutputQueue object - * @param[in] n maximum number of bytes to copy - * - * @notapi - */ -static void otg_fifo_write_from_queue(volatile uint32_t *fifop, - OutputQueue *oqp, - size_t n) { - size_t ntogo; - - ntogo = n; - while (ntogo > 0) { - uint32_t w, i; - size_t nw = ntogo / 4; - - if (nw > 0) { - size_t streak; - uint32_t nw2end = (oqp->q_top - oqp->q_rdptr) / 4; - - ntogo -= (streak = nw <= nw2end ? nw : nw2end) * 4; - oqp->q_rdptr = otg_do_push(fifop, oqp->q_rdptr, streak); - if (oqp->q_rdptr >= oqp->q_top) { - oqp->q_rdptr = oqp->q_buffer; - continue; - } - } - - /* If this condition is not satisfied then there is a word lying across - queue circular buffer boundary or there are some remaining bytes.*/ - if (ntogo <= 0) - break; - - /* One byte at time.*/ - w = 0; - i = 0; - while ((ntogo > 0) && (i < 4)) { - w |= (uint32_t)*oqp->q_rdptr++ << (i * 8); - if (oqp->q_rdptr >= oqp->q_top) - oqp->q_rdptr = oqp->q_buffer; - ntogo--; - i++; - } - *fifop = w; - } - - /* Updating queue.*/ - chSysLock(); - oqp->q_counter += n; - while (notempty(&oqp->q_waiting)) - chSchReadyI(fifo_remove(&oqp->q_waiting))->p_u.rdymsg = Q_OK; - chSchRescheduleS(); - chSysUnlock(); -} - -/** - * @brief Pops a series of words from a FIFO. - * - * @param[in] fifop pointer to the FIFO register - * @param[in] buf pointer to the words buffer, not necessarily word - * aligned - * @param[in] n number of words to push - * - * @return A pointer after the last word pushed. - * - * @notapi - */ -static uint8_t *otg_do_pop(volatile uint32_t *fifop, uint8_t *buf, size_t n) { - - while (n > 0) { - uint32_t w = *fifop; - /* Note, this line relies on the Cortex-M3/M4 ability to perform - unaligned word accesses and on the LSB-first memory organization.*/ - *((PACKED_VAR uint32_t *)buf) = w; - buf += 4; - n--; - } - return buf; -} - -/** - * @brief Reads a packet from the RXFIFO. - * - * @param[in] fifop pointer to the FIFO register - * @param[out] buf buffer where to copy the endpoint data - * @param[in] n number of bytes to pull from the FIFO - * @param[in] max number of bytes to copy into the buffer - * - * @notapi - */ -static void otg_fifo_read_to_buffer(volatile uint32_t *fifop, - uint8_t *buf, - size_t n, - size_t max) { - - n = (n + 3) / 4; - max = (max + 3) / 4; - while (n) { - uint32_t w = *fifop; - if (max) { - /* Note, this line relies on the Cortex-M3/M4 ability to perform - unaligned word accesses and on the LSB-first memory organization.*/ - *((PACKED_VAR uint32_t *)buf) = w; - buf += 4; - max--; - } - n--; - } -} - -/** - * @brief Reads a packet from the RXFIFO. - * - * @param[in] fifop pointer to the FIFO register - * @param[in] iqp pointer to an @p InputQueue object - * @param[in] n number of bytes to pull from the FIFO - * - * @notapi - */ -static void otg_fifo_read_to_queue(volatile uint32_t *fifop, - InputQueue *iqp, - size_t n) { - size_t ntogo; - - ntogo = n; - while (ntogo > 0) { - uint32_t w, i; - size_t nw = ntogo / 4; - - if (nw > 0) { - size_t streak; - uint32_t nw2end = (iqp->q_wrptr - iqp->q_wrptr) / 4; - - ntogo -= (streak = nw <= nw2end ? nw : nw2end) * 4; - iqp->q_wrptr = otg_do_pop(fifop, iqp->q_wrptr, streak); - if (iqp->q_wrptr >= iqp->q_top) { - iqp->q_wrptr = iqp->q_buffer; - continue; - } - } - - /* If this condition is not satisfied then there is a word lying across - queue circular buffer boundary or there are some remaining bytes.*/ - if (ntogo <= 0) - break; - - /* One byte at time.*/ - w = *fifop; - i = 0; - while ((ntogo > 0) && (i < 4)) { - *iqp->q_wrptr++ = (uint8_t)(w >> (i * 8)); - if (iqp->q_wrptr >= iqp->q_top) - iqp->q_wrptr = iqp->q_buffer; - ntogo--; - i++; - } - } - - /* Updating queue.*/ - chSysLock(); - iqp->q_counter += n; - while (notempty(&iqp->q_waiting)) - chSchReadyI(fifo_remove(&iqp->q_waiting))->p_u.rdymsg = Q_OK; - chSchRescheduleS(); - chSysUnlock(); -} - -/** - * @brief Incoming packets handler. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -static void otg_rxfifo_handler(USBDriver *usbp) { - uint32_t sts, cnt, ep; - - sts = usbp->otg->GRXSTSP; - switch (sts & GRXSTSP_PKTSTS_MASK) { - case GRXSTSP_SETUP_COMP: - break; - case GRXSTSP_SETUP_DATA: - cnt = (sts & GRXSTSP_BCNT_MASK) >> GRXSTSP_BCNT_OFF; - ep = (sts & GRXSTSP_EPNUM_MASK) >> GRXSTSP_EPNUM_OFF; - otg_fifo_read_to_buffer(usbp->otg->FIFO[0], usbp->epc[ep]->setup_buf, - cnt, 8); - break; - case GRXSTSP_OUT_DATA: - cnt = (sts & GRXSTSP_BCNT_MASK) >> GRXSTSP_BCNT_OFF; - ep = (sts & GRXSTSP_EPNUM_MASK) >> GRXSTSP_EPNUM_OFF; - if (usbp->epc[ep]->out_state->rxqueued) { - /* Queue associated.*/ - otg_fifo_read_to_queue(usbp->otg->FIFO[0], - usbp->epc[ep]->out_state->mode.queue.rxqueue, - cnt); - } - else { - otg_fifo_read_to_buffer(usbp->otg->FIFO[0], - usbp->epc[ep]->out_state->mode.linear.rxbuf, - cnt, - usbp->epc[ep]->out_state->rxsize - - usbp->epc[ep]->out_state->rxcnt); - usbp->epc[ep]->out_state->mode.linear.rxbuf += cnt; - } - usbp->epc[ep]->out_state->rxcnt += cnt; - break; - case GRXSTSP_OUT_GLOBAL_NAK: - case GRXSTSP_OUT_COMP: - default: - ; - } -} - -/** - * @brief Outgoing packets handler. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -static bool_t otg_txfifo_handler(USBDriver *usbp, usbep_t ep) { - - /* The TXFIFO is filled until there is space and data to be transmitted.*/ - while (TRUE) { - uint32_t n; - - /* Transaction end condition.*/ - if (usbp->epc[ep]->in_state->txcnt >= usbp->epc[ep]->in_state->txsize) - return TRUE; - - /* Number of bytes remaining in current transaction.*/ - n = usbp->epc[ep]->in_state->txsize - usbp->epc[ep]->in_state->txcnt; - if (n > usbp->epc[ep]->in_maxsize) - n = usbp->epc[ep]->in_maxsize; - - /* Checks if in the TXFIFO there is enough space to accommodate the - next packet.*/ - if (((usbp->otg->ie[ep].DTXFSTS & DTXFSTS_INEPTFSAV_MASK) * 4) < n) - return FALSE; - -#if STM32_USB_OTGFIFO_FILL_BASEPRI - __set_BASEPRI(CORTEX_PRIORITY_MASK(STM32_USB_OTGFIFO_FILL_BASEPRI)); -#endif - /* Handles the two cases: linear buffer or queue.*/ - if (usbp->epc[ep]->in_state->txqueued) { - /* Queue associated.*/ - otg_fifo_write_from_queue(usbp->otg->FIFO[ep], - usbp->epc[ep]->in_state->mode.queue.txqueue, - n); - } - else { - /* Linear buffer associated.*/ - otg_fifo_write_from_buffer(usbp->otg->FIFO[ep], - usbp->epc[ep]->in_state->mode.linear.txbuf, - n); - usbp->epc[ep]->in_state->mode.linear.txbuf += n; - } -#if STM32_USB_OTGFIFO_FILL_BASEPRI - __set_BASEPRI(0); -#endif - usbp->epc[ep]->in_state->txcnt += n; - } -} - -/** - * @brief Generic endpoint IN handler. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -static void otg_epin_handler(USBDriver *usbp, usbep_t ep) { - stm32_otg_t *otgp = usbp->otg; - uint32_t epint = otgp->ie[ep].DIEPINT; - - otgp->ie[ep].DIEPINT = epint; - - if (epint & DIEPINT_TOC) { - /* Timeouts not handled yet, not sure how to handle.*/ - } - if ((epint & DIEPINT_XFRC) && (otgp->DIEPMSK & DIEPMSK_XFRCM)) { - /* Transmit transfer complete.*/ - USBInEndpointState *isp = usbp->epc[ep]->in_state; - - if (isp->txsize < isp->totsize) { - /* In case the transaction covered only part of the total transfer - then another transaction is immediately started in order to - cover the remaining.*/ - isp->txsize = isp->totsize - isp->txsize; - isp->txcnt = 0; - usb_lld_prepare_transmit(usbp, ep); - chSysLockFromIsr(); - usb_lld_start_in(usbp, ep); - chSysUnlockFromIsr(); - } - else { - /* End on IN transfer.*/ - _usb_isr_invoke_in_cb(usbp, ep); - } - } - if ((epint & DIEPINT_TXFE) && - (otgp->DIEPEMPMSK & DIEPEMPMSK_INEPTXFEM(ep))) { - /* The thread is made ready, it will be scheduled on ISR exit.*/ - chSysLockFromIsr(); - usbp->txpending |= (1 << ep); - otgp->DIEPEMPMSK &= ~(1 << ep); - usb_lld_wakeup_pump(usbp); - chSysUnlockFromIsr(); - } -} - -/** - * @brief Generic endpoint OUT handler. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -static void otg_epout_handler(USBDriver *usbp, usbep_t ep) { - stm32_otg_t *otgp = usbp->otg; - uint32_t epint = otgp->oe[ep].DOEPINT; - - /* Resets all EP IRQ sources.*/ - otgp->oe[ep].DOEPINT = epint; - - if ((epint & DOEPINT_STUP) && (otgp->DOEPMSK & DOEPMSK_STUPM)) { - /* Setup packets handling, setup packets are handled using a - specific callback.*/ - _usb_isr_invoke_setup_cb(usbp, ep); - - } - if ((epint & DOEPINT_XFRC) && (otgp->DOEPMSK & DOEPMSK_XFRCM)) { - /* Receive transfer complete.*/ - USBOutEndpointState *osp = usbp->epc[ep]->out_state; - - if (osp->rxsize < osp->totsize) { - /* In case the transaction covered only part of the total transfer - then another transaction is immediately started in order to - cover the remaining.*/ - osp->rxsize = osp->totsize - osp->rxsize; - osp->rxcnt = 0; - usb_lld_prepare_receive(usbp, ep); - chSysLockFromIsr(); - usb_lld_start_out(usbp, ep); - chSysUnlockFromIsr(); - } - else { - /* End on OUT transfer.*/ - _usb_isr_invoke_out_cb(usbp, ep); - } - } -} - -/** - * @brief OTG shared ISR. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -static void usb_lld_serve_interrupt(USBDriver *usbp) { - stm32_otg_t *otgp = usbp->otg; - uint32_t sts, src; - - sts = otgp->GINTSTS; - sts &= otgp->GINTMSK; - otgp->GINTSTS = sts; - - /* Reset interrupt handling.*/ - if (sts & GINTSTS_USBRST) { - _usb_reset(usbp); - _usb_isr_invoke_event_cb(usbp, USB_EVENT_RESET); - } - - /* Enumeration done.*/ - if (sts & GINTSTS_ENUMDNE) { - (void)otgp->DSTS; - } - - /* SOF interrupt handling.*/ - if (sts & GINTSTS_SOF) { - _usb_isr_invoke_sof_cb(usbp); - } - - /* RX FIFO not empty handling.*/ - if (sts & GINTSTS_RXFLVL) { - /* The interrupt is masked while the thread has control or it would - be triggered again.*/ - chSysLockFromIsr(); - otgp->GINTMSK &= ~GINTMSK_RXFLVLM; - usb_lld_wakeup_pump(usbp); - chSysUnlockFromIsr(); - } - - /* IN/OUT endpoints event handling.*/ - src = otgp->DAINT; - if (sts & GINTSTS_IEPINT) { - if (src & (1 << 0)) - otg_epin_handler(usbp, 0); - if (src & (1 << 1)) - otg_epin_handler(usbp, 1); - if (src & (1 << 2)) - otg_epin_handler(usbp, 2); - if (src & (1 << 3)) - otg_epin_handler(usbp, 3); -#if STM32_USB_USE_OTG2 - if (src & (1 << 4)) - otg_epin_handler(usbp, 4); - if (src & (1 << 5)) - otg_epin_handler(usbp, 5); -#endif - } - if (sts & GINTSTS_OEPINT) { - if (src & (1 << 16)) - otg_epout_handler(usbp, 0); - if (src & (1 << 17)) - otg_epout_handler(usbp, 1); - if (src & (1 << 18)) - otg_epout_handler(usbp, 2); - if (src & (1 << 19)) - otg_epout_handler(usbp, 3); -#if STM32_USB_USE_OTG2 - if (src & (1 << 20)) - otg_epout_handler(usbp, 4); - if (src & (1 << 21)) - otg_epout_handler(usbp, 5); -#endif - } -} - -/*===========================================================================*/ -/* Driver interrupt handlers and threads. */ -/*===========================================================================*/ - -static msg_t usb_lld_pump(void *p) { - USBDriver *usbp = (USBDriver *)p; - stm32_otg_t *otgp = usbp->otg; - - chRegSetThreadName("usb_lld_pump"); - chSysLock(); - while (TRUE) { - usbep_t ep; - uint32_t epmask; - - /* Nothing to do, going to sleep.*/ - if ((usbp->state == USB_STOP) || - ((usbp->txpending == 0) && !(otgp->GINTSTS & GINTSTS_RXFLVL))) { - otgp->GINTMSK |= GINTMSK_RXFLVLM; - usbp->thd_wait = chThdSelf(); - chSchGoSleepS(THD_STATE_SUSPENDED); - } - chSysUnlock(); - - /* Checks if there are TXFIFOs to be filled.*/ - for (ep = 0; ep <= usbp->otgparams->num_endpoints; ep++) { - - /* Empties the RX FIFO.*/ - while (otgp->GINTSTS & GINTSTS_RXFLVL) { - otg_rxfifo_handler(usbp); - } - - epmask = (1 << ep); - if (usbp->txpending & epmask) { - bool_t done; - - chSysLock(); - /* USB interrupts are globally *suspended* because the peripheral - does not allow any interference during the TX FIFO filling - operation. - Synopsys document: DesignWare Cores USB 2.0 Hi-Speed On-The-Go (OTG) - "The application has to finish writing one complete packet before - switching to a different channel/endpoint FIFO. Violating this - rule results in an error.".*/ - otgp->GAHBCFG &= ~GAHBCFG_GINTMSK; - usbp->txpending &= ~epmask; - chSysUnlock(); - - done = otg_txfifo_handler(usbp, ep); - - chSysLock(); - otgp->GAHBCFG |= GAHBCFG_GINTMSK; - if (!done) - otgp->DIEPEMPMSK |= epmask; - chSysUnlock(); - } - } - chSysLock(); - } - // we are never here but GCC cannot figure this out - return 0; -} - -#if STM32_USB_USE_OTG1 || defined(__DOXYGEN__) -#if !defined(STM32_OTG1_HANDLER) -#error "STM32_OTG1_HANDLER not defined" -#endif -/** - * @brief OTG1 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_OTG1_HANDLER) { - - CH_IRQ_PROLOGUE(); - - usb_lld_serve_interrupt(&USBD1); - - CH_IRQ_EPILOGUE(); -} -#endif - -#if STM32_USB_USE_OTG2 || defined(__DOXYGEN__) -#if !defined(STM32_OTG2_HANDLER) -#error "STM32_OTG2_HANDLER not defined" -#endif -/** - * @brief OTG2 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_OTG2_HANDLER) { - - CH_IRQ_PROLOGUE(); - - usb_lld_serve_interrupt(&USBD2); - - CH_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level USB driver initialization. - * - * @notapi - */ -void usb_lld_init(void) { - - /* Driver initialization.*/ -#if STM32_USB_USE_OTG1 - usbObjectInit(&USBD1); - USBD1.thd_ptr = NULL; - USBD1.thd_wait = NULL; - USBD1.otg = OTG_FS; - USBD1.otgparams = &fsparams; - - /* Filling the thread working area here because the function - @p chThdCreateI() does not do it.*/ -#if CH_DBG_FILL_THREADS - { - void *wsp = USBD1.wa_pump; - _thread_memfill((uint8_t *)wsp, - (uint8_t *)wsp + sizeof(Thread), - CH_THREAD_FILL_VALUE); - _thread_memfill((uint8_t *)wsp + sizeof(Thread), - (uint8_t *)wsp + sizeof(USBD1.wa_pump), - CH_STACK_FILL_VALUE); - } -#endif -#endif - -#if STM32_USB_USE_OTG2 - usbObjectInit(&USBD2); - USBD2.thd_ptr = NULL; - USBD2.thd_wait = NULL; - USBD2.otg = OTG_HS; - USBD2.otgparams = &hsparams; - - /* Filling the thread working area here because the function - @p chThdCreateI() does not do it.*/ -#if CH_DBG_FILL_THREADS - { - void *wsp = USBD2.wa_pump; - _thread_memfill((uint8_t *)wsp, - (uint8_t *)wsp + sizeof(Thread), - CH_THREAD_FILL_VALUE); - _thread_memfill((uint8_t *)wsp + sizeof(Thread), - (uint8_t *)wsp + sizeof(USBD2.wa_pump), - CH_STACK_FILL_VALUE); - } -#endif -#endif -} - -/** - * @brief Configures and activates the USB peripheral. - * @note Starting the OTG cell can be a slow operation carried out with - * interrupts disabled, perform it before starting time-critical - * operations. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -void usb_lld_start(USBDriver *usbp) { - stm32_otg_t *otgp = usbp->otg; - - if (usbp->state == USB_STOP) { - /* Clock activation.*/ -#if STM32_USB_USE_OTG1 - if (&USBD1 == usbp) { - /* OTG FS clock enable and reset.*/ - rccEnableOTG_FS(FALSE); - rccResetOTG_FS(); - - /* Enables IRQ vector.*/ - nvicEnableVector(STM32_OTG1_NUMBER, - CORTEX_PRIORITY_MASK(STM32_USB_OTG1_IRQ_PRIORITY)); - } -#endif -#if STM32_USB_USE_OTG2 - if (&USBD2 == usbp) { - /* OTG HS clock enable and reset.*/ - rccEnableOTG_HS(FALSE); - rccResetOTG_HS(); - - /* Workaround for the problem described here: - http://forum.chibios.org/phpbb/viewtopic.php?f=16&t=1798 */ - rccDisableOTG_HSULPI(TRUE); - - /* Enables IRQ vector.*/ - nvicEnableVector(STM32_OTG2_NUMBER, - CORTEX_PRIORITY_MASK(STM32_USB_OTG2_IRQ_PRIORITY)); - } -#endif - - /* Creates the data pump threads in a suspended state. Note, it is - created only once, the first time @p usbStart() is invoked.*/ - usbp->txpending = 0; - if (usbp->thd_ptr == NULL) - usbp->thd_ptr = usbp->thd_wait = chThdCreateI(usbp->wa_pump, - sizeof usbp->wa_pump, - STM32_USB_OTG_THREAD_PRIO, - usb_lld_pump, - usbp); - - /* - Forced device mode. - - USB turn-around time = TRDT_VALUE. - - Full Speed 1.1 PHY.*/ - otgp->GUSBCFG = GUSBCFG_FDMOD | GUSBCFG_TRDT(TRDT_VALUE) | GUSBCFG_PHYSEL; - - /* 48MHz 1.1 PHY.*/ - otgp->DCFG = 0x02200000 | DCFG_DSPD_FS11; - - /* PHY enabled.*/ - otgp->PCGCCTL = 0; - - /* Internal FS PHY activation.*/ -#if defined(BOARD_OTG_NOVBUSSENS) - otgp->GCCFG = GCCFG_NOVBUSSENS | GCCFG_VBUSASEN | GCCFG_VBUSBSEN | - GCCFG_PWRDWN; -#else - otgp->GCCFG = GCCFG_VBUSASEN | GCCFG_VBUSBSEN | GCCFG_PWRDWN; -#endif - - /* Soft core reset.*/ - otg_core_reset(usbp); - - /* Interrupts on TXFIFOs half empty.*/ - otgp->GAHBCFG = 0; - - /* Endpoints re-initialization.*/ - otg_disable_ep(usbp); - - /* Clear all pending Device Interrupts, only the USB Reset interrupt - is required initially.*/ - otgp->DIEPMSK = 0; - otgp->DOEPMSK = 0; - otgp->DAINTMSK = 0; - if (usbp->config->sof_cb == NULL) - otgp->GINTMSK = GINTMSK_ENUMDNEM | GINTMSK_USBRSTM /*| GINTMSK_USBSUSPM | - GINTMSK_ESUSPM |*/; - else - otgp->GINTMSK = GINTMSK_ENUMDNEM | GINTMSK_USBRSTM /*| GINTMSK_USBSUSPM | - GINTMSK_ESUSPM */ | GINTMSK_SOFM; - otgp->GINTSTS = 0xFFFFFFFF; /* Clears all pending IRQs, if any. */ - - /* Global interrupts enable.*/ - otgp->GAHBCFG |= GAHBCFG_GINTMSK; - } -} - -/** - * @brief Deactivates the USB peripheral. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -void usb_lld_stop(USBDriver *usbp) { - stm32_otg_t *otgp = usbp->otg; - - /* If in ready state then disables the USB clock.*/ - if (usbp->state != USB_STOP) { - - /* Disabling all endpoints in case the driver has been stopped while - active.*/ - otg_disable_ep(usbp); - - usbp->txpending = 0; - - otgp->DAINTMSK = 0; - otgp->GAHBCFG = 0; - otgp->GCCFG = 0; - -#if STM32_USB_USE_USB1 - if (&USBD1 == usbp) { - nvicDisableVector(STM32_OTG1_NUMBER); - rccDisableOTG1(FALSE); - } -#endif - -#if STM32_USB_USE_USB2 - if (&USBD2 == usbp) { - nvicDisableVector(STM32_OTG2_NUMBER); - rccDisableOTG2(FALSE); - } -#endif - } -} - -/** - * @brief USB low level reset routine. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -void usb_lld_reset(USBDriver *usbp) { - unsigned i; - stm32_otg_t *otgp = usbp->otg; - - /* Flush the Tx FIFO.*/ - otg_txfifo_flush(usbp, 0); - - /* All endpoints in NAK mode, interrupts cleared.*/ - for (i = 0; i <= usbp->otgparams->num_endpoints; i++) { - otgp->ie[i].DIEPCTL = DIEPCTL_SNAK; - otgp->oe[i].DOEPCTL = DOEPCTL_SNAK; - otgp->ie[i].DIEPINT = 0xFF; - otgp->oe[i].DOEPINT = 0xFF; - } - - /* Endpoint interrupts all disabled and cleared.*/ - otgp->DAINT = 0xFFFFFFFF; - otgp->DAINTMSK = DAINTMSK_OEPM(0) | DAINTMSK_IEPM(0); - - /* Resets the FIFO memory allocator.*/ - otg_ram_reset(usbp); - - /* Receive FIFO size initialization, the address is always zero.*/ - otgp->GRXFSIZ = usbp->otgparams->rx_fifo_size; - otg_rxfifo_flush(usbp); - - /* Resets the device address to zero.*/ - otgp->DCFG = (otgp->DCFG & ~DCFG_DAD_MASK) | DCFG_DAD(0); - - /* Enables also EP-related interrupt sources.*/ - otgp->GINTMSK |= GINTMSK_RXFLVLM | GINTMSK_OEPM | GINTMSK_IEPM; - otgp->DIEPMSK = DIEPMSK_TOCM | DIEPMSK_XFRCM; - otgp->DOEPMSK = DOEPMSK_STUPM | DOEPMSK_XFRCM; - - /* EP0 initialization, it is a special case.*/ - usbp->epc[0] = &ep0config; - otgp->oe[0].DOEPTSIZ = 0; - otgp->oe[0].DOEPCTL = DOEPCTL_SD0PID | DOEPCTL_USBAEP | DOEPCTL_EPTYP_CTRL | - DOEPCTL_MPSIZ(ep0config.out_maxsize); - otgp->ie[0].DIEPTSIZ = 0; - otgp->ie[0].DIEPCTL = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_CTRL | - DIEPCTL_TXFNUM(0) | DIEPCTL_MPSIZ(ep0config.in_maxsize); - otgp->DIEPTXF0 = DIEPTXF_INEPTXFD(ep0config.in_maxsize / 4) | - DIEPTXF_INEPTXSA(otg_ram_alloc(usbp, - ep0config.in_maxsize / 4)); -} - -/** - * @brief Sets the USB address. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -void usb_lld_set_address(USBDriver *usbp) { - stm32_otg_t *otgp = usbp->otg; - - otgp->DCFG = (otgp->DCFG & ~DCFG_DAD_MASK) | DCFG_DAD(usbp->address); -} - -/** - * @brief Enables an endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) { - uint32_t ctl, fsize; - stm32_otg_t *otgp = usbp->otg; - - /* IN and OUT common parameters.*/ - switch (usbp->epc[ep]->ep_mode & USB_EP_MODE_TYPE) { - case USB_EP_MODE_TYPE_CTRL: - ctl = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_CTRL; - break; - case USB_EP_MODE_TYPE_ISOC: - ctl = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_ISO; - break; - case USB_EP_MODE_TYPE_BULK: - ctl = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_BULK; - break; - case USB_EP_MODE_TYPE_INTR: - ctl = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_INTR; - break; - default: - return; - } - - /* OUT endpoint activation or deactivation.*/ - otgp->oe[ep].DOEPTSIZ = 0; - if (usbp->epc[ep]->out_cb != NULL) { - otgp->oe[ep].DOEPCTL = ctl | DOEPCTL_MPSIZ(usbp->epc[ep]->out_maxsize); - otgp->DAINTMSK |= DAINTMSK_OEPM(ep); - } - else { - otgp->oe[ep].DOEPCTL &= ~DOEPCTL_USBAEP; - otgp->DAINTMSK &= ~DAINTMSK_OEPM(ep); - } - - /* IN endpoint activation or deactivation.*/ - otgp->ie[ep].DIEPTSIZ = 0; - if (usbp->epc[ep]->in_cb != NULL) { - /* FIFO allocation for the IN endpoint.*/ - fsize = usbp->epc[ep]->in_maxsize / 4; - if (usbp->epc[ep]->in_multiplier > 1) - fsize *= usbp->epc[ep]->in_multiplier; - otgp->DIEPTXF[ep - 1] = DIEPTXF_INEPTXFD(fsize) | - DIEPTXF_INEPTXSA(otg_ram_alloc(usbp, fsize)); - otg_txfifo_flush(usbp, ep); - - otgp->ie[ep].DIEPCTL = ctl | - DIEPCTL_TXFNUM(ep) | - DIEPCTL_MPSIZ(usbp->epc[ep]->in_maxsize); - otgp->DAINTMSK |= DAINTMSK_IEPM(ep); - } - else { - otgp->DIEPTXF[ep - 1] = 0x02000400; /* Reset value.*/ - otg_txfifo_flush(usbp, ep); - otgp->ie[ep].DIEPCTL &= ~DIEPCTL_USBAEP; - otgp->DAINTMSK &= ~DAINTMSK_IEPM(ep); - } -} - -/** - * @brief Disables all the active endpoints except the endpoint zero. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -void usb_lld_disable_endpoints(USBDriver *usbp) { - - /* Resets the FIFO memory allocator.*/ - otg_ram_reset(usbp); - - /* Disabling all endpoints.*/ - otg_disable_ep(usbp); -} - -/** - * @brief Returns the status of an OUT endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @return The endpoint status. - * @retval EP_STATUS_DISABLED The endpoint is not active. - * @retval EP_STATUS_STALLED The endpoint is stalled. - * @retval EP_STATUS_ACTIVE The endpoint is active. - * - * @notapi - */ -usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep) { - uint32_t ctl; - - (void)usbp; - - ctl = usbp->otg->oe[ep].DOEPCTL; - if (!(ctl & DOEPCTL_USBAEP)) - return EP_STATUS_DISABLED; - if (ctl & DOEPCTL_STALL) - return EP_STATUS_STALLED; - return EP_STATUS_ACTIVE; -} - -/** - * @brief Returns the status of an IN endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @return The endpoint status. - * @retval EP_STATUS_DISABLED The endpoint is not active. - * @retval EP_STATUS_STALLED The endpoint is stalled. - * @retval EP_STATUS_ACTIVE The endpoint is active. - * - * @notapi - */ -usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep) { - uint32_t ctl; - - (void)usbp; - - ctl = usbp->otg->ie[ep].DIEPCTL; - if (!(ctl & DIEPCTL_USBAEP)) - return EP_STATUS_DISABLED; - if (ctl & DIEPCTL_STALL) - return EP_STATUS_STALLED; - return EP_STATUS_ACTIVE; -} - -/** - * @brief Reads a setup packet from the dedicated packet buffer. - * @details This function must be invoked in the context of the @p setup_cb - * callback in order to read the received setup packet. - * @pre In order to use this function the endpoint must have been - * initialized as a control endpoint. - * @post The endpoint is ready to accept another packet. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @param[out] buf buffer where to copy the packet data - * - * @notapi - */ -void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) { - - memcpy(buf, usbp->epc[ep]->setup_buf, 8); -} - -/** - * @brief Prepares for a receive operation. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep) { - uint32_t pcnt; - USBOutEndpointState *osp = usbp->epc[ep]->out_state; - - /* Transfer initialization.*/ - osp->totsize = osp->rxsize; - if ((ep == 0) && (osp->rxsize > EP0_MAX_OUTSIZE)) - osp->rxsize = EP0_MAX_OUTSIZE; - - pcnt = (osp->rxsize + usbp->epc[ep]->out_maxsize - 1) / - usbp->epc[ep]->out_maxsize; - usbp->otg->oe[ep].DOEPTSIZ = DOEPTSIZ_STUPCNT(3) | DOEPTSIZ_PKTCNT(pcnt) | - DOEPTSIZ_XFRSIZ(osp->rxsize); - -} - -/** - * @brief Prepares for a transmit operation. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep) { - USBInEndpointState *isp = usbp->epc[ep]->in_state; - - /* Transfer initialization.*/ - isp->totsize = isp->txsize; - if (isp->txsize == 0) { - /* Special case, sending zero size packet.*/ - usbp->otg->ie[ep].DIEPTSIZ = DIEPTSIZ_PKTCNT(1) | DIEPTSIZ_XFRSIZ(0); - } - else { - if ((ep == 0) && (isp->txsize > EP0_MAX_INSIZE)) - isp->txsize = EP0_MAX_INSIZE; - - /* Normal case.*/ - uint32_t pcnt = (isp->txsize + usbp->epc[ep]->in_maxsize - 1) / - usbp->epc[ep]->in_maxsize; - usbp->otg->ie[ep].DIEPTSIZ = DIEPTSIZ_PKTCNT(pcnt) | - DIEPTSIZ_XFRSIZ(isp->txsize); - } -} - -/** - * @brief Starts a receive operation on an OUT endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_start_out(USBDriver *usbp, usbep_t ep) { - - usbp->otg->oe[ep].DOEPCTL |= DOEPCTL_CNAK; -} - -/** - * @brief Starts a transmit operation on an IN endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_start_in(USBDriver *usbp, usbep_t ep) { - - usbp->otg->ie[ep].DIEPCTL |= DIEPCTL_EPENA | DIEPCTL_CNAK; - usbp->otg->DIEPEMPMSK |= DIEPEMPMSK_INEPTXFEM(ep); -} - -/** - * @brief Brings an OUT endpoint in the stalled state. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_stall_out(USBDriver *usbp, usbep_t ep) { - - usbp->otg->oe[ep].DOEPCTL |= DOEPCTL_STALL; -} - -/** - * @brief Brings an IN endpoint in the stalled state. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_stall_in(USBDriver *usbp, usbep_t ep) { - - usbp->otg->ie[ep].DIEPCTL |= DIEPCTL_STALL; -} - -/** - * @brief Brings an OUT endpoint in the active state. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_clear_out(USBDriver *usbp, usbep_t ep) { - - usbp->otg->oe[ep].DOEPCTL &= ~DOEPCTL_STALL; -} - -/** - * @brief Brings an IN endpoint in the active state. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_clear_in(USBDriver *usbp, usbep_t ep) { - - usbp->otg->ie[ep].DIEPCTL &= ~DIEPCTL_STALL; -} - -#endif /* HAL_USE_USB */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/OTGv1/usb_lld.h b/firmware/chibios/os/hal/platforms/STM32/OTGv1/usb_lld.h deleted file mode 100644 index 802f13a222..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/OTGv1/usb_lld.h +++ /dev/null @@ -1,552 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/OTGv1/usb_lld.h - * @brief STM32 USB subsystem low level driver header. - * - * @addtogroup USB - * @{ - */ - -#ifndef _USB_LLD_H_ -#define _USB_LLD_H_ - -#if HAL_USE_USB || defined(__DOXYGEN__) - -#include "stm32_otg.h" - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Maximum endpoint address. - */ -#if !STM32_USB_USE_OTG2 || defined(__DOXYGEN__) -#define USB_MAX_ENDPOINTS 3 -#else -#define USB_MAX_ENDPOINTS 5 -#endif - -/** - * @brief Status stage handling method. - */ -#define USB_EP0_STATUS_STAGE USB_EP0_STATUS_STAGE_SW - -/** - * @brief The address can be changed immediately upon packet reception. - */ -#define USB_SET_ADDRESS_MODE USB_EARLY_SET_ADDRESS - -/** - * @brief Method for set address acknowledge. - */ -#define USB_SET_ADDRESS_ACK_HANDLING USB_SET_ADDRESS_ACK_SW - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief OTG1 driver enable switch. - * @details If set to @p TRUE the support for OTG_FS is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_USB_USE_OTG1) || defined(__DOXYGEN__) -#define STM32_USB_USE_OTG1 FALSE -#endif - -/** - * @brief OTG2 driver enable switch. - * @details If set to @p TRUE the support for OTG_HS is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_USB_USE_OTG2) || defined(__DOXYGEN__) -#define STM32_USB_USE_OTG2 FALSE -#endif - -/** - * @brief OTG1 interrupt priority level setting. - */ -#if !defined(STM32_USB_OTG1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_USB_OTG1_IRQ_PRIORITY 14 -#endif - -/** - * @brief OTG2 interrupt priority level setting. - */ -#if !defined(STM32_USB_OTG2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_USB_OTG2_IRQ_PRIORITY 14 -#endif - -/** - * @brief OTG1 RX shared FIFO size. - * @note Must be a multiple of 4. - */ -#if !defined(STM32_USB_OTG1_RX_FIFO_SIZE) || defined(__DOXYGEN__) -#define STM32_USB_OTG1_RX_FIFO_SIZE 512 -#endif - -/** - * @brief OTG2 RX shared FIFO size. - * @note Must be a multiple of 4. - */ -#if !defined(STM32_USB_OTG2_RX_FIFO_SIZE) || defined(__DOXYGEN__) -#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 -#endif - -/** - * @brief Dedicated data pump threads priority. - */ -#if !defined(STM32_USB_OTG_THREAD_PRIO) || defined(__DOXYGEN__) -#define STM32_USB_OTG_THREAD_PRIO LOWPRIO -#endif - -/** - * @brief Dedicated data pump threads stack size. - */ -#if !defined(STM32_USB_OTG_THREAD_STACK_SIZE) || defined(__DOXYGEN__) -#define STM32_USB_OTG_THREAD_STACK_SIZE 128 -#endif - -/** - * @brief Exception priority level during TXFIFOs operations. - * @note Because an undocumented silicon behavior the operation of - * copying a packet into a TXFIFO must not be interrupted by - * any other operation on the OTG peripheral. - * This parameter represents the priority mask during copy - * operations. The default value only allows to call USB - * functions from callbacks invoked from USB ISR handlers. - * If you need to invoke USB functions from other handlers - * then raise this priority mast to the same level of the - * handler you need to use. - * @note The value zero means disabled, when disabled calling USB - * functions is only safe from thread level or from USB - * callbacks. - */ -#if !defined(STM32_USB_OTGFIFO_FILL_BASEPRI) || defined(__DOXYGEN__) -#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_USB_USE_OTG1 && !STM32_HAS_OTG1 -#error "OTG1 not present in the selected device" -#endif - -#if STM32_USB_USE_OTG2 && !STM32_HAS_OTG2 -#error "OTG2 not present in the selected device" -#endif - -#if !STM32_USB_USE_OTG1 && !STM32_USB_USE_OTG2 -#error "USB driver activated but no USB peripheral assigned" -#endif - -#if STM32_USB_USE_OTG1 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_USB_OTG1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to OTG1" -#endif - -#if STM32_USB_USE_OTG2 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_USB_OTG2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to OTG2" -#endif - -#if (STM32_USB_OTG1_RX_FIFO_SIZE & 3) != 0 -#error "OTG1 RX FIFO size must be a multiple of 4" -#endif - -#if (STM32_USB_OTG2_RX_FIFO_SIZE & 3) != 0 -#error "OTG2 RX FIFO size must be a multiple of 4" -#endif - -#if defined(STM32F4XX) || defined(STM32F2XX) -#define STM32_USBCLK STM32_PLL48CLK -#elif defined(STM32F10X_CL) -#define STM32_USBCLK STM32_OTGFSCLK -#else -#error "unsupported STM32 platform for OTG functionality" -#endif - -#if STM32_USBCLK != 48000000 -#error "the USB OTG driver requires a 48MHz clock" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Peripheral-specific parameters block. - */ -typedef struct { - uint32_t rx_fifo_size; - uint32_t otg_ram_size; - uint32_t num_endpoints; -} stm32_otg_params_t; - -/** - * @brief Type of an IN endpoint state structure. - */ -typedef struct { - /** - * @brief Buffer mode, queue or linear. - */ - bool_t txqueued; - /** - * @brief Requested transmit transfer size. - */ - size_t txsize; - /** - * @brief Transmitted bytes so far. - */ - size_t txcnt; - union { - struct { - /** - * @brief Pointer to the transmission linear buffer. - */ - const uint8_t *txbuf; - } linear; - struct { - /** - * @brief Pointer to the output queue. - */ - OutputQueue *txqueue; - } queue; - } mode; - /** - * @brief Total transmit transfer size. - */ - size_t totsize; -} USBInEndpointState; - -/** - * @brief Type of an OUT endpoint state structure. - */ -typedef struct { - /** - * @brief Buffer mode, queue or linear. - */ - bool_t rxqueued; - /** - * @brief Requested receive transfer size. - */ - size_t rxsize; - /** - * @brief Received bytes so far. - */ - size_t rxcnt; - union { - struct { - /** - * @brief Pointer to the receive linear buffer. - */ - uint8_t *rxbuf; - } linear; - struct { - /** - * @brief Pointer to the input queue. - */ - InputQueue *rxqueue; - } queue; - } mode; - /** - * @brief Total transmit transfer size. - */ - size_t totsize; -} USBOutEndpointState; - -/** - * @brief Type of an USB endpoint configuration structure. - * @note Platform specific restrictions may apply to endpoints. - */ -typedef struct { - /** - * @brief Type and mode of the endpoint. - */ - uint32_t ep_mode; - /** - * @brief Setup packet notification callback. - * @details This callback is invoked when a setup packet has been - * received. - * @post The application must immediately call @p usbReadPacket() in - * order to access the received packet. - * @note This field is only valid for @p USB_EP_MODE_TYPE_CTRL - * endpoints, it should be set to @p NULL for other endpoint - * types. - */ - usbepcallback_t setup_cb; - /** - * @brief IN endpoint notification callback. - * @details This field must be set to @p NULL if the IN endpoint is not - * used. - */ - usbepcallback_t in_cb; - /** - * @brief OUT endpoint notification callback. - * @details This field must be set to @p NULL if the OUT endpoint is not - * used. - */ - usbepcallback_t out_cb; - /** - * @brief IN endpoint maximum packet size. - * @details This field must be set to zero if the IN endpoint is not - * used. - */ - uint16_t in_maxsize; - /** - * @brief OUT endpoint maximum packet size. - * @details This field must be set to zero if the OUT endpoint is not - * used. - */ - uint16_t out_maxsize; - /** - * @brief @p USBEndpointState associated to the IN endpoint. - * @details This structure maintains the state of the IN endpoint. - */ - USBInEndpointState *in_state; - /** - * @brief @p USBEndpointState associated to the OUT endpoint. - * @details This structure maintains the state of the OUT endpoint. - */ - USBOutEndpointState *out_state; - /* End of the mandatory fields.*/ - /** - * @brief Determines the space allocated for the TXFIFO as multiples of - * the packet size (@p in_maxsize). Note that zero is interpreted - * as one for simplicity and robustness. - */ - uint16_t in_multiplier; - /** - * @brief Pointer to a buffer for setup packets. - * @details Setup packets require a dedicated 8-bytes buffer, set this - * field to @p NULL for non-control endpoints. - */ - uint8_t *setup_buf; -} USBEndpointConfig; - -/** - * @brief Type of an USB driver configuration structure. - */ -typedef struct { - /** - * @brief USB events callback. - * @details This callback is invoked when an USB driver event is registered. - */ - usbeventcb_t event_cb; - /** - * @brief Device GET_DESCRIPTOR request callback. - * @note This callback is mandatory and cannot be set to @p NULL. - */ - usbgetdescriptor_t get_descriptor_cb; - /** - * @brief Requests hook callback. - * @details This hook allows to be notified of standard requests or to - * handle non standard requests. - */ - usbreqhandler_t requests_hook_cb; - /** - * @brief Start Of Frame callback. - */ - usbcallback_t sof_cb; - /* End of the mandatory fields.*/ -} USBConfig; - -/** - * @brief Structure representing an USB driver. - */ -struct USBDriver { - /** - * @brief Driver state. - */ - usbstate_t state; - /** - * @brief Current configuration data. - */ - const USBConfig *config; - /** - * @brief Bit map of the transmitting IN endpoints. - */ - uint16_t transmitting; - /** - * @brief Bit map of the receiving OUT endpoints. - */ - uint16_t receiving; - /** - * @brief Active endpoints configurations. - */ - const USBEndpointConfig *epc[USB_MAX_ENDPOINTS + 1]; - /** - * @brief Fields available to user, it can be used to associate an - * application-defined handler to an IN endpoint. - * @note The base index is one, the endpoint zero does not have a - * reserved element in this array. - */ - void *in_params[USB_MAX_ENDPOINTS]; - /** - * @brief Fields available to user, it can be used to associate an - * application-defined handler to an OUT endpoint. - * @note The base index is one, the endpoint zero does not have a - * reserved element in this array. - */ - void *out_params[USB_MAX_ENDPOINTS]; - /** - * @brief Endpoint 0 state. - */ - usbep0state_t ep0state; - /** - * @brief Next position in the buffer to be transferred through endpoint 0. - */ - uint8_t *ep0next; - /** - * @brief Number of bytes yet to be transferred through endpoint 0. - */ - size_t ep0n; - /** - * @brief Endpoint 0 end transaction callback. - */ - usbcallback_t ep0endcb; - /** - * @brief Setup packet buffer. - */ - uint8_t setup[8]; - /** - * @brief Current USB device status. - */ - uint16_t status; - /** - * @brief Assigned USB address. - */ - uint8_t address; - /** - * @brief Current USB device configuration. - */ - uint8_t configuration; -#if defined(USB_DRIVER_EXT_FIELDS) - USB_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the OTG peripheral associated to this driver. - */ - stm32_otg_t *otg; - /** - * @brief Peripheral-specific parameters. - */ - const stm32_otg_params_t *otgparams; - /** - * @brief Pointer to the next address in the packet memory. - */ - uint32_t pmnext; - /** - * @brief Mask of TXFIFOs to be filled by the pump thread. - */ - uint32_t txpending; - /** - * @brief Pointer to the thread. - */ - Thread *thd_ptr; - /** - * @brief Pointer to the thread when it is sleeping or @p NULL. - */ - Thread *thd_wait; - /** - * @brief Working area for the dedicated data pump thread; - */ - WORKING_AREA(wa_pump, STM32_USB_OTG_THREAD_STACK_SIZE); -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Returns the exact size of a receive transaction. - * @details The received size can be different from the size specified in - * @p usbStartReceiveI() because the last packet could have a size - * different from the expected one. - * @pre The OUT endpoint must have been configured in transaction mode - * in order to use this function. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @return Received data size. - * - * @notapi - */ -#define usb_lld_get_transaction_size(usbp, ep) \ - ((usbp)->epc[ep]->out_state->rxcnt) - -/** - * @brief Connects the USB device. - * - * @api - */ -#define usb_lld_connect_bus(usbp) ((usbp)->otg->GCCFG |= GCCFG_VBUSBSEN) - -/** - * @brief Disconnect the USB device. - * - * @api - */ -#define usb_lld_disconnect_bus(usbp) ((usbp)->otg->GCCFG &= ~GCCFG_VBUSBSEN) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_USB_USE_OTG1 && !defined(__DOXYGEN__) -extern USBDriver USBD1; -#endif - -#if STM32_USB_USE_OTG2 && !defined(__DOXYGEN__) -extern USBDriver USBD2; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void usb_lld_init(void); - void usb_lld_start(USBDriver *usbp); - void usb_lld_stop(USBDriver *usbp); - void usb_lld_reset(USBDriver *usbp); - void usb_lld_set_address(USBDriver *usbp); - void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep); - void usb_lld_disable_endpoints(USBDriver *usbp); - usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep); - usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep); - void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf); - void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep); - void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep); - void usb_lld_start_out(USBDriver *usbp, usbep_t ep); - void usb_lld_start_in(USBDriver *usbp, usbep_t ep); - void usb_lld_stall_out(USBDriver *usbp, usbep_t ep); - void usb_lld_stall_in(USBDriver *usbp, usbep_t ep); - void usb_lld_clear_out(USBDriver *usbp, usbep_t ep); - void usb_lld_clear_in(USBDriver *usbp, usbep_t ep); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_USB */ - -#endif /* _USB_LLD_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/RTCv1/rtc_lld.c b/firmware/chibios/os/hal/platforms/STM32/RTCv1/rtc_lld.c deleted file mode 100644 index 6980dbd6b2..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/RTCv1/rtc_lld.c +++ /dev/null @@ -1,329 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Concepts and parts of this file have been contributed by Uladzimir Pylinsky - aka barthess. - */ - -/** - * @file STM32/RTCv1/rtc_lld.c - * @brief STM32 RTC subsystem low level driver header. - * - * @addtogroup RTC - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_RTC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief RTC driver identifier. - */ -RTCDriver RTCD1; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Wait for synchronization of RTC registers with APB1 bus. - * @details This function must be invoked before trying to read RTC registers - * in the backup domain: DIV, CNT, ALR. CR registers can always - * be read. - * - * @notapi - */ -#define rtc_lld_apb1_sync() {while ((RTC->CRL & RTC_CRL_RSF) == 0);} - -/** - * @brief Wait for for previous write operation complete. - * @details This function must be invoked before writing to any RTC registers - * - * @notapi - */ -#define rtc_lld_wait_write() {while ((RTC->CRL & RTC_CRL_RTOFF) == 0);} - -/** - * @brief Acquires write access to RTC registers. - * @details Before writing to the backup domain RTC registers the previous - * write operation must be completed. Use this function before - * writing to PRL, CNT, ALR registers. - * - * @notapi - */ -#define rtc_lld_acquire() {rtc_lld_wait_write(); RTC->CRL |= RTC_CRL_CNF;} - -/** - * @brief Releases write access to RTC registers. - * - * @notapi - */ -#define rtc_lld_release() {RTC->CRL &= ~RTC_CRL_CNF;} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief RTC interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(RTC_IRQHandler) { - uint16_t flags; - - CH_IRQ_PROLOGUE(); - - /* This wait works only when AHB1 bus was previously powered off by any - reason (standby, reset, etc). In other cases it does nothing.*/ - rtc_lld_apb1_sync(); - - /* Mask of all enabled and pending sources.*/ - flags = RTC->CRH & RTC->CRL; - RTC->CRL &= ~(RTC_CRL_SECF | RTC_CRL_ALRF | RTC_CRL_OWF); - - if (flags & RTC_CRL_SECF) - RTCD1.callback(&RTCD1, RTC_EVENT_SECOND); - - if (flags & RTC_CRL_ALRF) - RTCD1.callback(&RTCD1, RTC_EVENT_ALARM); - - if (flags & RTC_CRL_OWF) - RTCD1.callback(&RTCD1, RTC_EVENT_OVERFLOW); - - CH_IRQ_EPILOGUE(); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Load value of RTCCLK to prescaler registers. - * @note The pre-scaler must not be set on every reset as RTC clock - * counts are lost when it is set. - * @note This function designed to be called from - * hal_lld_backup_domain_init(). Because there is only place - * where possible to detect BKP domain reset event reliably. - * - * @notapi - */ -void rtc_lld_set_prescaler(void){ - rtc_lld_acquire(); - RTC->PRLH = (uint16_t)((STM32_RTCCLK - 1) >> 16) & 0x000F; - RTC->PRLL = (uint16_t)(((STM32_RTCCLK - 1)) & 0xFFFF); - rtc_lld_release(); -} - -/** - * @brief Initialize RTC. - * - * @notapi - */ -void rtc_lld_init(void){ - - /* RSF bit must be cleared by software after an APB1 reset or an APB1 clock - stop. Otherwise its value will not be actual. */ - RTC->CRL &= ~RTC_CRL_RSF; - - /* Required because access to PRL.*/ - rtc_lld_apb1_sync(); - - /* All interrupts initially disabled.*/ - rtc_lld_wait_write(); - RTC->CRH = 0; - - /* Callback initially disabled.*/ - RTCD1.callback = NULL; - - /* IRQ vector permanently assigned to this driver.*/ - nvicEnableVector(RTC_IRQn, CORTEX_PRIORITY_MASK(STM32_RTC_IRQ_PRIORITY)); -} - -/** - * @brief Set current time. - * @note Fractional part will be silently ignored. There is no possibility - * to change it on STM32F1xx platform. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[in] timespec pointer to a @p RTCTime structure - * - * @notapi - */ -void rtc_lld_set_time(RTCDriver *rtcp, const RTCTime *timespec) { - - (void)rtcp; - - rtc_lld_acquire(); - RTC->CNTH = (uint16_t)(timespec->tv_sec >> 16); - RTC->CNTL = (uint16_t)(timespec->tv_sec & 0xFFFF); - rtc_lld_release(); -} - -/** - * @brief Get current time. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[in] timespec pointer to a @p RTCTime structure - * - * @notapi - */ -void rtc_lld_get_time(RTCDriver *rtcp, RTCTime *timespec) { - (void)rtcp; - - uint32_t time_frac; - - /* Required because access to CNT and DIV.*/ - rtc_lld_apb1_sync(); - - /* Loops until two consecutive read returning the same value.*/ - do { - timespec->tv_sec = ((uint32_t)(RTC->CNTH) << 16) + RTC->CNTL; - time_frac = (((uint32_t)RTC->DIVH) << 16) + (uint32_t)RTC->DIVL; - } while ((timespec->tv_sec) != (((uint32_t)(RTC->CNTH) << 16) + RTC->CNTL)); - - timespec->tv_msec = (uint16_t)(((STM32_RTCCLK - 1 - time_frac) * 1000) / - STM32_RTCCLK); -} - -/** - * @brief Set alarm time. - * - * @note Default value after BKP domain reset is 0xFFFFFFFF - * - * @param[in] rtcp pointer to RTC driver structure - * @param[in] alarm alarm identifier - * @param[in] alarmspec pointer to a @p RTCAlarm structure - * - * @notapi - */ -void rtc_lld_set_alarm(RTCDriver *rtcp, - rtcalarm_t alarm, - const RTCAlarm *alarmspec) { - - (void)rtcp; - (void)alarm; - - rtc_lld_acquire(); - if (alarmspec != NULL) { - RTC->ALRH = (uint16_t)(alarmspec->tv_sec >> 16); - RTC->ALRL = (uint16_t)(alarmspec->tv_sec & 0xFFFF); - } - else { - RTC->ALRH = 0; - RTC->ALRL = 0; - } - rtc_lld_release(); -} - -/** - * @brief Get current alarm. - * @note If an alarm has not been set then the returned alarm specification - * is not meaningful. - * - * @note Default value after BKP domain reset is 0xFFFFFFFF. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[in] alarm alarm identifier - * @param[out] alarmspec pointer to a @p RTCAlarm structure - * - * @notapi - */ -void rtc_lld_get_alarm(RTCDriver *rtcp, - rtcalarm_t alarm, - RTCAlarm *alarmspec) { - - (void)rtcp; - (void)alarm; - - /* Required because access to ALR.*/ - rtc_lld_apb1_sync(); - - alarmspec->tv_sec = ((RTC->ALRH << 16) + RTC->ALRL); -} - -/** - * @brief Enables or disables RTC callbacks. - * @details This function enables or disables callbacks, use a @p NULL pointer - * in order to disable a callback. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[in] callback callback function pointer or @p NULL - * - * @notapi - */ -void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback) { - - if (callback != NULL) { - - /* IRQ sources enabled only after setting up the callback.*/ - rtcp->callback = callback; - - rtc_lld_wait_write(); - RTC->CRL &= ~(RTC_CRL_OWF | RTC_CRL_ALRF | RTC_CRL_SECF); - RTC->CRH = RTC_CRH_OWIE | RTC_CRH_ALRIE | RTC_CRH_SECIE; - } - else { - rtc_lld_wait_write(); - RTC->CRH = 0; - - /* Callback set to NULL only after disabling the IRQ sources.*/ - rtcp->callback = NULL; - } -} - -#include "chrtclib.h" - -/** - * @brief Get current time in format suitable for usage in FatFS. - * - * @param[in] rtcp pointer to RTC driver structure - * @return FAT time value. - * - * @api - */ -uint32_t rtc_lld_get_time_fat(RTCDriver *rtcp) { - uint32_t fattime; - struct tm timp; - - rtcGetTimeTm(rtcp, &timp); - - fattime = (timp.tm_sec) >> 1; - fattime |= (timp.tm_min) << 5; - fattime |= (timp.tm_hour) << 11; - fattime |= (timp.tm_mday) << 16; - fattime |= (timp.tm_mon + 1) << 21; - fattime |= (timp.tm_year - 80) << 25; - - return fattime; -} -#endif /* HAL_USE_RTC */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/RTCv1/rtc_lld.h b/firmware/chibios/os/hal/platforms/STM32/RTCv1/rtc_lld.h deleted file mode 100644 index 69508d60a4..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/RTCv1/rtc_lld.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Concepts and parts of this file have been contributed by Uladzimir Pylinsky - aka barthess. - */ - -/** - * @file STM32/RTCv1/rtc_lld.h - * @brief STM32F1xx RTC subsystem low level driver header. - * - * @addtogroup RTC - * @{ - */ - -#ifndef _RTC_LLD_H_ -#define _RTC_LLD_H_ - -#if HAL_USE_RTC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief This RTC implementation supports callbacks. - */ -#define RTC_SUPPORTS_CALLBACKS TRUE - -/** - * @brief One alarm comparator available. - */ -#define RTC_ALARMS 1 - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/* - * RTC driver system settings. - */ -#define STM32_RTC_IRQ_PRIORITY 15 -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if HAL_USE_RTC && !STM32_HAS_RTC -#error "RTC not present in the selected device" -#endif - -#if STM32_RTCCLK == 0 -#error "RTC clock not enabled" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a structure representing an RTC alarm time stamp. - */ -typedef struct RTCAlarm RTCAlarm; - -/** - * @brief Type of a structure representing an RTC callbacks config. - */ -typedef struct RTCCallbackConfig RTCCallbackConfig; - -/** - * @brief Type of an RTC alarm. - * @details Meaningful on platforms with more than 1 alarm comparator. - */ -typedef uint32_t rtcalarm_t; - -/** - * @brief Type of an RTC event. - */ -typedef enum { - RTC_EVENT_SECOND = 0, /** Triggered every second. */ - RTC_EVENT_ALARM = 1, /** Triggered on alarm. */ - RTC_EVENT_OVERFLOW = 2 /** Triggered on counter overflow. */ -} rtcevent_t; - -/** - * @brief Type of a generic RTC callback. - */ -typedef void (*rtccb_t)(RTCDriver *rtcp, rtcevent_t event); - -/** - * @brief Structure representing an RTC callbacks config. - */ -struct RTCCallbackConfig{ - /** - * @brief Generic RTC callback pointer. - */ - rtccb_t callback; -}; - -/** - * @brief Structure representing an RTC time stamp. - */ -struct RTCTime { - /** - * @brief Seconds since UNIX epoch. - */ - uint32_t tv_sec; - /** - * @brief Fractional part. - */ - uint32_t tv_msec; -}; - -/** - * @brief Structure representing an RTC alarm time stamp. - */ -struct RTCAlarm { - /** - * @brief Seconds since UNIX epoch. - */ - uint32_t tv_sec; -}; - -/** - * @brief Structure representing an RTC driver. - */ -struct RTCDriver{ - /** - * @brief Callback pointer. - */ - rtccb_t callback; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -extern RTCDriver RTCD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void rtc_lld_set_prescaler(void); - void rtc_lld_init(void); - void rtc_lld_set_time(RTCDriver *rtcp, const RTCTime *timespec); - void rtc_lld_get_time(RTCDriver *rtcp, RTCTime *timespec); - void rtc_lld_set_alarm(RTCDriver *rtcp, - rtcalarm_t alarm, - const RTCAlarm *alarmspec); - void rtc_lld_get_alarm(RTCDriver *rtcp, - rtcalarm_t alarm, - RTCAlarm *alarmspec); - void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback); - uint32_t rtc_lld_get_time_fat(RTCDriver *rtcp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_RTC */ - -#endif /* _RTC_LLD_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/RTCv2/rtc_lld.c b/firmware/chibios/os/hal/platforms/STM32/RTCv2/rtc_lld.c deleted file mode 100644 index 48dee3a058..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/RTCv2/rtc_lld.c +++ /dev/null @@ -1,352 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Concepts and parts of this file have been contributed by Uladzimir Pylinsky - aka barthess. - */ - -/** - * @file STM32/RTCv2/rtc_lld.c - * @brief RTC low level driver. - * - * @addtogroup RTC - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_RTC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief RTC driver identifier. - */ -RTCDriver RTCD1; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -extern bool rtcWorks; - -/** - * @brief Wait for synchronization of RTC registers with APB1 bus. - * @details This function must be invoked before trying to read RTC registers. - * - * @notapi - */ -#define rtc_lld_apb1_sync() { \ - int counter = 0; \ - while ((RTCD1.id_rtc->ISR & RTC_ISR_RSF) == 0 && ++counter ISR |= RTC_ISR_INIT; \ - int counter = 0; \ - while ((RTCD1.id_rtc->ISR & RTC_ISR_INITF) == 0 && ++counter ISR &= ~RTC_ISR_INIT;} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Enable access to registers. - * - * @api - */ -void rtc_lld_init(void){ - RTCD1.id_rtc = RTC; - - /* Asynchronous part of preloader. Set it to maximum value. */ - uint32_t prediv_a = 0x7F; - - /* Disable write protection. */ - RTCD1.id_rtc->WPR = 0xCA; - RTCD1.id_rtc->WPR = 0x53; - - /* If calendar not init yet. */ - if (!(RTC->ISR & RTC_ISR_INITS)){ - rtc_lld_enter_init(); - - /* Prescaler register must be written in two SEPARATE writes. */ - prediv_a = (prediv_a << 16) | - (((STM32_RTCCLK / (prediv_a + 1)) - 1) & 0x7FFF); - RTCD1.id_rtc->PRER = prediv_a; - RTCD1.id_rtc->PRER = prediv_a; - rtc_lld_exit_init(); - } -} - -/** - * @brief Set current time. - * @note Fractional part will be silently ignored. There is no possibility - * to set it on STM32 platform. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[in] timespec pointer to a @p RTCTime structure - * - * @api - */ -void rtc_lld_set_time(RTCDriver *rtcp, const RTCTime *timespec) { - (void)rtcp; - - if (!rtcWorks) - return; - - rtc_lld_enter_init(); - if (timespec->h12) - RTCD1.id_rtc->CR |= RTC_CR_FMT; - else - RTCD1.id_rtc->CR &= ~RTC_CR_FMT; - RTCD1.id_rtc->TR = timespec->tv_time; - RTCD1.id_rtc->DR = timespec->tv_date; - rtc_lld_exit_init(); -} - -/** - * @brief Get current time. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[out] timespec pointer to a @p RTCTime structure - * - * @api - */ -void rtc_lld_get_time(RTCDriver *rtcp, RTCTime *timespec) { - (void)rtcp; - - chDbgAssert(RTCD1.id_rtc == RTC, "RTC", "RTC"); - - rtc_lld_apb1_sync(); - -#if STM32_RTC_HAS_SUBSECONDS - { - uint32_t prer = RTCD1.id_rtc->PRER & 0x7FFF; - uint32_t ssr = RTCD1.id_rtc->SSR; - timespec->tv_msec = (1000 * (prer - ssr)) / (prer + 1); - } -#endif /* STM32_RTC_HAS_SUBSECONDS */ - timespec->tv_time = RTCD1.id_rtc->TR; - timespec->tv_date = RTCD1.id_rtc->DR; -} - -/** - * @brief Set alarm time. - * - * @note Default value after BKP domain reset for both comparators is 0. - * @note Function does not performs any checks of alarm time validity. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[in] alarm alarm identifier starting from zero - * @param[in] alarmspec pointer to a @p RTCAlarm structure - * - * @api - */ -void rtc_lld_set_alarm(RTCDriver *rtcp, - rtcalarm_t alarm, - const RTCAlarm *alarmspec) { - - if (alarm == 0) { - if (alarmspec != NULL){ - rtcp->id_rtc->CR &= ~RTC_CR_ALRAE; - while(!(rtcp->id_rtc->ISR & RTC_ISR_ALRAWF)) - ; - rtcp->id_rtc->ALRMAR = alarmspec->tv_datetime; - rtcp->id_rtc->CR |= RTC_CR_ALRAE; - rtcp->id_rtc->CR |= RTC_CR_ALRAIE; - } - else { - rtcp->id_rtc->CR &= ~RTC_CR_ALRAIE; - rtcp->id_rtc->CR &= ~RTC_CR_ALRAE; - } - } -#if RTC_ALARMS == 2 - else{ - if (alarmspec != NULL){ - rtcp->id_rtc->CR &= ~RTC_CR_ALRBE; - while(!(rtcp->id_rtc->ISR & RTC_ISR_ALRBWF)) - ; - rtcp->id_rtc->ALRMBR = alarmspec->tv_datetime; - rtcp->id_rtc->CR |= RTC_CR_ALRBE; - rtcp->id_rtc->CR |= RTC_CR_ALRBIE; - } - else { - rtcp->id_rtc->CR &= ~RTC_CR_ALRBIE; - rtcp->id_rtc->CR &= ~RTC_CR_ALRBE; - } - } -#endif /* RTC_ALARMS == 2 */ -} - -/** - * @brief Get alarm time. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[in] alarm alarm identifier starting from zero - * @param[out] alarmspec pointer to a @p RTCAlarm structure - * - * @api - */ -void rtc_lld_get_alarm(RTCDriver *rtcp, - rtcalarm_t alarm, - RTCAlarm *alarmspec) { - - if (alarm == 0) - alarmspec->tv_datetime = rtcp->id_rtc->ALRMAR; -#if RTC_ALARMS == 2 - else - alarmspec->tv_datetime = rtcp->id_rtc->ALRMBR; -#endif -} - -/** - * @brief Sets time of periodic wakeup. - * - * @note Default value after BKP domain reset is 0x0000FFFF - * - * @param[in] rtcp pointer to RTC driver structure - * @param[in] wakeupspec pointer to a @p RTCWakeup structure - * - * @api - */ -#if RTC_HAS_PERIODIC_WAKEUPS -void rtcSetPeriodicWakeup_v2(RTCDriver *rtcp, const RTCWakeup *wakeupspec) { - - if (wakeupspec != NULL){ - chDbgCheck((wakeupspec->wakeup != 0x30000), - "rtc_lld_set_periodic_wakeup, forbidden combination"); - - rtcp->id_rtc->CR &= ~RTC_CR_WUTE; - while(!(rtcp->id_rtc->ISR & RTC_ISR_WUTWF)) - ; - rtcp->id_rtc->WUTR = wakeupspec->wakeup & 0xFFFF; - rtcp->id_rtc->CR = (wakeupspec->wakeup >> 16) & 0x7; - rtcp->id_rtc->CR |= RTC_CR_WUTIE; - rtcp->id_rtc->CR |= RTC_CR_WUTE; - } - else { - rtcp->id_rtc->CR &= ~RTC_CR_WUTIE; - rtcp->id_rtc->CR &= ~RTC_CR_WUTE; - } -} -#endif /* RTC_HAS_PERIODIC_WAKEUPS */ - -/** - * @brief Gets time of periodic wakeup. - * - * @note Default value after BKP domain reset is 0x0000FFFF - * - * @param[in] rtcp pointer to RTC driver structure - * @param[out] wakeupspec pointer to a @p RTCWakeup structure - * - * @api - */ -#if RTC_HAS_PERIODIC_WAKEUPS -void rtcGetPeriodicWakeup_v2(RTCDriver *rtcp, RTCWakeup *wakeupspec) { - - wakeupspec->wakeup = 0; - wakeupspec->wakeup |= rtcp->id_rtc->WUTR; - wakeupspec->wakeup |= (((uint32_t)rtcp->id_rtc->CR) & 0x7) << 16; -} -#endif /* RTC_HAS_PERIODIC_WAKEUPS */ - -/** - * @brief Get current time in format suitable for usage in FatFS. - * - * @param[in] rtcp pointer to RTC driver structure - * @return FAT time value. - * - * @api - */ -uint32_t rtc_lld_get_time_fat(RTCDriver *rtcp) { - uint32_t fattime; - RTCTime timespec; - uint32_t tv_time; - uint32_t tv_date; - uint32_t v; - - chSysLock(); - if (rtcWorks) - rtcGetTimeI(rtcp, ×pec); - chSysUnlock(); - - tv_time = timespec.tv_time; - tv_date = timespec.tv_date; - - v = (tv_time & RTC_TR_SU) >> RTC_TR_SU_OFFSET; - v += ((tv_time & RTC_TR_ST) >> RTC_TR_ST_OFFSET) * 10; - fattime = v >> 1; - - v = (tv_time & RTC_TR_MNU) >> RTC_TR_MNU_OFFSET; - v += ((tv_time & RTC_TR_MNT) >> RTC_TR_MNT_OFFSET) * 10; - fattime |= v << 5; - - v = (tv_time & RTC_TR_HU) >> RTC_TR_HU_OFFSET; - v += ((tv_time & RTC_TR_HT) >> RTC_TR_HT_OFFSET) * 10; - v += 12 * ((tv_time & RTC_TR_PM) >> RTC_TR_PM_OFFSET); - fattime |= v << 11; - - v = (tv_date & RTC_DR_DU) >> RTC_DR_DU_OFFSET; - v += ((tv_date & RTC_DR_DT) >> RTC_DR_DT_OFFSET) * 10; - fattime |= v << 16; - - v = (tv_date & RTC_DR_MU) >> RTC_DR_MU_OFFSET; - v += ((tv_date & RTC_DR_MT) >> RTC_DR_MT_OFFSET) * 10; - fattime |= v << 21; - - v = (tv_date & RTC_DR_YU) >> RTC_DR_YU_OFFSET; - v += ((tv_date & RTC_DR_YT) >> RTC_DR_YT_OFFSET) * 10; - v += 2000 - 1900 - 80; - fattime |= v << 25; - - return fattime; -} - -#endif /* HAL_USE_RTC */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/RTCv2/rtc_lld.h b/firmware/chibios/os/hal/platforms/STM32/RTCv2/rtc_lld.h deleted file mode 100644 index a5a50b40de..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/RTCv2/rtc_lld.h +++ /dev/null @@ -1,230 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Concepts and parts of this file have been contributed by Uladzimir Pylinsky - aka barthess. - */ - -/** - * @file STM32/RTCv2/rtc_lld.h - * @brief RTC low level driver header. - * - * @addtogroup RTC - * @{ - */ - -#ifndef _RTC_LLD_H_ -#define _RTC_LLD_H_ - -#if HAL_USE_RTC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * this rusEfi hack is about surviving lack of LSE (32kHz osc) part of RTC - */ -#define LSE_TIMEOUT 1000000 - -/** - * @brief Two alarm comparators available on STM32F4x and STM32F2x. - */ -#if !defined(STM32F0XX) -#define RTC_ALARMS 2 -#else -#define RTC_ALARMS 1 -#endif - -/** - * @brief STM32F0x has no periodic wakeups. - */ -#if !defined(STM32F0XX) -#define RTC_HAS_PERIODIC_WAKEUPS TRUE -#else -#define RTC_HAS_PERIODIC_WAKEUPS FALSE -#endif - -/** - * @brief Data offsets in RTC date and time registers. - */ -#define RTC_TR_PM_OFFSET 22 -#define RTC_TR_HT_OFFSET 20 -#define RTC_TR_HU_OFFSET 16 -#define RTC_TR_MNT_OFFSET 12 -#define RTC_TR_MNU_OFFSET 8 -#define RTC_TR_ST_OFFSET 4 -#define RTC_TR_SU_OFFSET 0 - -#define RTC_DR_YT_OFFSET 20 -#define RTC_DR_YU_OFFSET 16 -#define RTC_DR_WDU_OFFSET 13 -#define RTC_DR_MT_OFFSET 12 -#define RTC_DR_MU_OFFSET 8 -#define RTC_DR_DT_OFFSET 4 -#define RTC_DR_DU_OFFSET 0 - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if HAL_USE_RTC && !STM32_HAS_RTC -#error "RTC not present in the selected device" -#endif - -#if !(STM32_RTCSEL == STM32_RTCSEL_LSE) && \ - !(STM32_RTCSEL == STM32_RTCSEL_LSI) && \ - !(STM32_RTCSEL == STM32_RTCSEL_HSEDIV) -#error "invalid source selected for RTC clock" -#endif - -#if !defined(RTC_USE_INTERRUPTS) || defined(__DOXYGEN__) -#define RTC_USE_INTERRUPTS FALSE -#endif - -#if defined(STM32_PCLK1) /* For devices without STM32_PCLK1 (STM32F0xx) */ -#if STM32_PCLK1 < (STM32_RTCCLK * 7) -#error "STM32_PCLK1 frequency is too low to handle RTC without ugly workaround" -#endif -#endif /* defined(STM32_PCLK1) */ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a structure representing an RTC alarm time stamp. - */ -typedef struct RTCAlarm RTCAlarm; - -/** - * @brief Type of a structure representing an RTC wakeup period. - */ -typedef struct RTCWakeup RTCWakeup; - -/** - * @brief Type of a structure representing an RTC callbacks config. - */ -typedef struct RTCCallbackConfig RTCCallbackConfig; - -/** - * @brief Type of an RTC alarm. - * @details Meaningful on platforms with more than 1 alarm comparator. - */ -typedef uint32_t rtcalarm_t; - -/** - * @brief Structure representing an RTC time stamp. - */ -struct RTCTime { - /** - * @brief RTC date register in STM32 BCD format. - */ - uint32_t tv_date; - /** - * @brief RTC time register in STM32 BCD format. - */ - uint32_t tv_time; - /** - * @brief Set this to TRUE to use 12 hour notation. - */ - bool_t h12; - /** - * @brief Fractional part of time. - */ -#if STM32_RTC_HAS_SUBSECONDS - uint32_t tv_msec; -#endif -}; - -/** - * @brief Structure representing an RTC alarm time stamp. - */ -struct RTCAlarm { - /** - * @brief Date and time of alarm in STM32 BCD. - */ - uint32_t tv_datetime; -}; - -#if RTC_HAS_PERIODIC_WAKEUPS -/** - * @brief Structure representing an RTC periodic wakeup period. - */ -struct RTCWakeup { - /** - * @brief RTC WUTR register. - * @details Bits [15:0] contain value of WUTR register - * Bits [18:16] contain value of WUCKSEL bits in CR register - * - * @note ((WUTR == 0) || (WUCKSEL == 3)) is forbidden combination. - */ - uint32_t wakeup; -}; -#endif /* RTC_HAS_PERIODIC_WAKEUPS */ - -/** - * @brief Structure representing an RTC driver. - */ -struct RTCDriver{ - /** - * @brief Pointer to the RTC registers block. - */ - RTC_TypeDef *id_rtc; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -extern RTCDriver RTCD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void rtc_lld_init(void); - void rtc_lld_set_time(RTCDriver *rtcp, const RTCTime *timespec); - void rtc_lld_get_time(RTCDriver *rtcp, RTCTime *timespec); - void rtc_lld_set_alarm(RTCDriver *rtcp, - rtcalarm_t alarm, - const RTCAlarm *alarmspec); - void rtc_lld_get_alarm(RTCDriver *rtcp, - rtcalarm_t alarm, - RTCAlarm *alarmspec); -#if RTC_HAS_PERIODIC_WAKEUPS - void rtcSetPeriodicWakeup_v2(RTCDriver *rtcp, const RTCWakeup *wakeupspec); - void rtcGetPeriodicWakeup_v2(RTCDriver *rtcp, RTCWakeup *wakeupspec); -#endif /* RTC_HAS_PERIODIC_WAKEUPS */ - uint32_t rtc_lld_get_time_fat(RTCDriver *rtcp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_RTC */ - -#endif /* _RTC_LLD_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/SPIv1/spi_lld.c b/firmware/chibios/os/hal/platforms/STM32/SPIv1/spi_lld.c deleted file mode 100644 index 7c0a5e58a6..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/SPIv1/spi_lld.c +++ /dev/null @@ -1,636 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/SPIv1/spi_lld.c - * @brief STM32 SPI subsystem low level driver source. - * - * @addtogroup SPI - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_SPI || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define SPI1_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI1_RX_DMA_STREAM, \ - STM32_SPI1_RX_DMA_CHN) - -#define SPI1_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI1_TX_DMA_STREAM, \ - STM32_SPI1_TX_DMA_CHN) - -#define SPI2_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI2_RX_DMA_STREAM, \ - STM32_SPI2_RX_DMA_CHN) - -#define SPI2_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI2_TX_DMA_STREAM, \ - STM32_SPI2_TX_DMA_CHN) - -#define SPI3_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI3_RX_DMA_STREAM, \ - STM32_SPI3_RX_DMA_CHN) - -#define SPI3_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI3_TX_DMA_STREAM, \ - STM32_SPI3_TX_DMA_CHN) - -#define SPI4_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI4_RX_DMA_STREAM, \ - STM32_SPI4_RX_DMA_CHN) - -#define SPI4_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI4_TX_DMA_STREAM, \ - STM32_SPI4_TX_DMA_CHN) - -#define SPI5_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI5_RX_DMA_STREAM, \ - STM32_SPI5_RX_DMA_CHN) - -#define SPI5_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI5_TX_DMA_STREAM, \ - STM32_SPI5_TX_DMA_CHN) - -#define SPI6_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI6_RX_DMA_STREAM, \ - STM32_SPI6_RX_DMA_CHN) - -#define SPI6_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI6_TX_DMA_STREAM, \ - STM32_SPI6_TX_DMA_CHN) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief SPI1 driver identifier.*/ -#if STM32_SPI_USE_SPI1 || defined(__DOXYGEN__) -SPIDriver SPID1; -#endif - -/** @brief SPI2 driver identifier.*/ -#if STM32_SPI_USE_SPI2 || defined(__DOXYGEN__) -SPIDriver SPID2; -#endif - -/** @brief SPI3 driver identifier.*/ -#if STM32_SPI_USE_SPI3 || defined(__DOXYGEN__) -SPIDriver SPID3; -#endif - -/** @brief SPI4 driver identifier.*/ -#if STM32_SPI_USE_SPI4 || defined(__DOXYGEN__) -SPIDriver SPID4; -#endif - -/** @brief SPI5 driver identifier.*/ -#if STM32_SPI_USE_SPI5 || defined(__DOXYGEN__) -SPIDriver SPID5; -#endif - -/** @brief SPI6 driver identifier.*/ -#if STM32_SPI_USE_SPI6 || defined(__DOXYGEN__) -SPIDriver SPID6; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -static uint16_t dummytx; -static uint16_t dummyrx; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Shared end-of-rx service routine. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] flags pre-shifted content of the ISR register - */ -static void spi_lld_serve_rx_interrupt(SPIDriver *spip, uint32_t flags) { - - /* DMA errors handling.*/ -#if defined(STM32_SPI_DMA_ERROR_HOOK) - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - STM32_SPI_DMA_ERROR_HOOK(spip); - } -#else - (void)flags; -#endif - - /* Stop everything.*/ - dmaStreamDisable(spip->dmatx); - dmaStreamDisable(spip->dmarx); - - /* Portable SPI ISR code defined in the high level driver, note, it is - a macro.*/ - _spi_isr_code(spip); -} - -/** - * @brief Shared end-of-tx service routine. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] flags pre-shifted content of the ISR register - */ -static void spi_lld_serve_tx_interrupt(SPIDriver *spip, uint32_t flags) { - - /* DMA errors handling.*/ -#if defined(STM32_SPI_DMA_ERROR_HOOK) - (void)spip; - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - STM32_SPI_DMA_ERROR_HOOK(spip); - } -#else - (void)spip; - (void)flags; -#endif -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level SPI driver initialization. - * - * @notapi - */ -void spi_lld_init(void) { - - dummytx = 0xFFFF; - -#if STM32_SPI_USE_SPI1 - spiObjectInit(&SPID1); - SPID1.spi = SPI1; - SPID1.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI1_RX_DMA_STREAM); - SPID1.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI1_TX_DMA_STREAM); - SPID1.rxdmamode = STM32_DMA_CR_CHSEL(SPI1_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; - SPID1.txdmamode = STM32_DMA_CR_CHSEL(SPI1_TX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) | - STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; -#endif - -#if STM32_SPI_USE_SPI2 - spiObjectInit(&SPID2); - SPID2.spi = SPI2; - SPID2.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI2_RX_DMA_STREAM); - SPID2.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI2_TX_DMA_STREAM); - SPID2.rxdmamode = STM32_DMA_CR_CHSEL(SPI2_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; - SPID2.txdmamode = STM32_DMA_CR_CHSEL(SPI2_TX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) | - STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; -#endif - -#if STM32_SPI_USE_SPI3 - spiObjectInit(&SPID3); - SPID3.spi = SPI3; - SPID3.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI3_RX_DMA_STREAM); - SPID3.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI3_TX_DMA_STREAM); - SPID3.rxdmamode = STM32_DMA_CR_CHSEL(SPI3_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; - SPID3.txdmamode = STM32_DMA_CR_CHSEL(SPI3_TX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) | - STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; -#endif - -#if STM32_SPI_USE_SPI4 - spiObjectInit(&SPID4); - SPID4.spi = SPI4; - SPID4.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI4_RX_DMA_STREAM); - SPID4.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI4_TX_DMA_STREAM); - SPID4.rxdmamode = STM32_DMA_CR_CHSEL(SPI4_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI4_DMA_PRIORITY) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; - SPID4.txdmamode = STM32_DMA_CR_CHSEL(SPI4_TX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI4_DMA_PRIORITY) | - STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; -#endif - -#if STM32_SPI_USE_SPI5 - spiObjectInit(&SPID5); - SPID5.spi = SPI5; - SPID5.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI5_RX_DMA_STREAM); - SPID5.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI5_TX_DMA_STREAM); - SPID5.rxdmamode = STM32_DMA_CR_CHSEL(SPI5_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI5_DMA_PRIORITY) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; - SPID5.txdmamode = STM32_DMA_CR_CHSEL(SPI5_TX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI5_DMA_PRIORITY) | - STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; -#endif - -#if STM32_SPI_USE_SPI6 - spiObjectInit(&SPID6); - SPID6.spi = SPI6; - SPID6.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI6_RX_DMA_STREAM); - SPID6.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI6_TX_DMA_STREAM); - SPID6.rxdmamode = STM32_DMA_CR_CHSEL(SPI6_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI6_DMA_PRIORITY) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; - SPID6.txdmamode = STM32_DMA_CR_CHSEL(SPI6_TX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI6_DMA_PRIORITY) | - STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; -#endif -} - -/** - * @brief Configures and activates the SPI peripheral. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_start(SPIDriver *spip) { - - /* If in stopped state then enables the SPI and DMA clocks.*/ - if (spip->state == SPI_STOP) { -#if STM32_SPI_USE_SPI1 - if (&SPID1 == spip) { - bool_t b; - b = dmaStreamAllocate(spip->dmarx, - STM32_SPI_SPI1_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, - (void *)spip); - chDbgAssert(!b, "spi_lld_start(), #1", "stream already allocated"); - b = dmaStreamAllocate(spip->dmatx, - STM32_SPI_SPI1_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, - (void *)spip); - chDbgAssert(!b, "spi_lld_start(), #2", "stream already allocated"); - rccEnableSPI1(FALSE); - } -#endif -#if STM32_SPI_USE_SPI2 - if (&SPID2 == spip) { - bool_t b; - b = dmaStreamAllocate(spip->dmarx, - STM32_SPI_SPI2_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, - (void *)spip); - chDbgAssert(!b, "spi_lld_start(), #3", "stream already allocated"); - b = dmaStreamAllocate(spip->dmatx, - STM32_SPI_SPI2_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, - (void *)spip); - chDbgAssert(!b, "spi_lld_start(), #4", "stream already allocated"); - rccEnableSPI2(FALSE); - } -#endif -#if STM32_SPI_USE_SPI3 - if (&SPID3 == spip) { - bool_t b; - b = dmaStreamAllocate(spip->dmarx, - STM32_SPI_SPI3_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, - (void *)spip); - chDbgAssert(!b, "spi_lld_start(), #5", "stream already allocated"); - b = dmaStreamAllocate(spip->dmatx, - STM32_SPI_SPI3_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, - (void *)spip); - chDbgAssert(!b, "spi_lld_start(), #6", "stream already allocated"); - rccEnableSPI3(FALSE); - } -#endif -#if STM32_SPI_USE_SPI4 - if (&SPID4 == spip) { - bool_t b; - b = dmaStreamAllocate(spip->dmarx, - STM32_SPI_SPI4_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, - (void *)spip); - chDbgAssert(!b, "spi_lld_start(), #7", "stream already allocated"); - b = dmaStreamAllocate(spip->dmatx, - STM32_SPI_SPI4_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, - (void *)spip); - chDbgAssert(!b, "spi_lld_start(), #8", "stream already allocated"); - rccEnableSPI4(FALSE); - } -#endif -#if STM32_SPI_USE_SPI5 - if (&SPID5 == spip) { - bool_t b; - b = dmaStreamAllocate(spip->dmarx, - STM32_SPI_SPI5_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, - (void *)spip); - chDbgAssert(!b, "spi_lld_start(), #9", "stream already allocated"); - b = dmaStreamAllocate(spip->dmatx, - STM32_SPI_SPI5_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, - (void *)spip); - chDbgAssert(!b, "spi_lld_start(), #10", "stream already allocated"); - rccEnableSPI5(FALSE); - } -#endif -#if STM32_SPI_USE_SPI6 - if (&SPID6 == spip) { - bool_t b; - b = dmaStreamAllocate(spip->dmarx, - STM32_SPI_SPI6_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, - (void *)spip); - chDbgAssert(!b, "spi_lld_start(), #11", "stream already allocated"); - b = dmaStreamAllocate(spip->dmatx, - STM32_SPI_SPI6_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, - (void *)spip); - chDbgAssert(!b, "spi_lld_start(), #12", "stream already allocated"); - rccEnableSPI6(FALSE); - } -#endif - - /* DMA setup.*/ - dmaStreamSetPeripheral(spip->dmarx, &spip->spi->DR); - dmaStreamSetPeripheral(spip->dmatx, &spip->spi->DR); - } - - /* Configuration-specific DMA setup.*/ - if ((spip->config->cr1 & SPI_CR1_DFF) == 0) { - /* Frame width is 8 bits or smaller.*/ - spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) | - STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE; - spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) | - STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE; - } - else { - /* Frame width is larger than 8 bits.*/ - spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) | - STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; - spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) | - STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; - } - /* SPI setup and enable.*/ - spip->spi->CR1 = 0; - spip->spi->CR1 = spip->config->cr1 | SPI_CR1_MSTR | SPI_CR1_SSM | - SPI_CR1_SSI; - spip->spi->CR2 = SPI_CR2_SSOE | SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN; - spip->spi->CR1 |= SPI_CR1_SPE; -} - -/** - * @brief Deactivates the SPI peripheral. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_stop(SPIDriver *spip) { - - /* If in ready state then disables the SPI clock.*/ - if (spip->state == SPI_READY) { - - /* SPI disable.*/ - spip->spi->CR1 = 0; - spip->spi->CR2 = 0; - dmaStreamRelease(spip->dmarx); - dmaStreamRelease(spip->dmatx); - -#if STM32_SPI_USE_SPI1 - if (&SPID1 == spip) - rccDisableSPI1(FALSE); -#endif -#if STM32_SPI_USE_SPI2 - if (&SPID2 == spip) - rccDisableSPI2(FALSE); -#endif -#if STM32_SPI_USE_SPI3 - if (&SPID3 == spip) - rccDisableSPI3(FALSE); -#endif -#if STM32_SPI_USE_SPI4 - if (&SPID4 == spip) - rccDisableSPI4(FALSE); -#endif -#if STM32_SPI_USE_SPI5 - if (&SPID5 == spip) - rccDisableSPI5(FALSE); -#endif -#if STM32_SPI_USE_SPI6 - if (&SPID6 == spip) - rccDisableSPI6(FALSE); -#endif - } -} - -/** - * @brief Asserts the slave select signal and prepares for transfers. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_select(SPIDriver *spip) { - - palClearPad(spip->config->ssport, spip->config->sspad); -} - -/** - * @brief Deasserts the slave select signal. - * @details The previously selected peripheral is unselected. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_unselect(SPIDriver *spip) { - - palSetPad(spip->config->ssport, spip->config->sspad); -} - -/** - * @brief Ignores data on the SPI bus. - * @details This asynchronous function starts the transmission of a series of - * idle words on the SPI bus and ignores the received data. - * @post At the end of the operation the configured callback is invoked. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be ignored - * - * @notapi - */ -void spi_lld_ignore(SPIDriver *spip, size_t n) { - - dmaStreamSetMemory0(spip->dmarx, &dummyrx); - dmaStreamSetTransactionSize(spip->dmarx, n); - dmaStreamSetMode(spip->dmarx, spip->rxdmamode); - - dmaStreamSetMemory0(spip->dmatx, &dummytx); - dmaStreamSetTransactionSize(spip->dmatx, n); - dmaStreamSetMode(spip->dmatx, spip->txdmamode); - - dmaStreamEnable(spip->dmarx); - dmaStreamEnable(spip->dmatx); -} - -/** - * @brief Exchanges data on the SPI bus. - * @details This asynchronous function starts a simultaneous transmit/receive - * operation. - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be exchanged - * @param[in] txbuf the pointer to the transmit buffer - * @param[out] rxbuf the pointer to the receive buffer - * - * @notapi - */ -void spi_lld_exchange(SPIDriver *spip, size_t n, - const void *txbuf, void *rxbuf) { - - dmaStreamSetMemory0(spip->dmarx, rxbuf); - dmaStreamSetTransactionSize(spip->dmarx, n); - dmaStreamSetMode(spip->dmarx, spip->rxdmamode| STM32_DMA_CR_MINC); - - dmaStreamSetMemory0(spip->dmatx, txbuf); - dmaStreamSetTransactionSize(spip->dmatx, n); - dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC); - - dmaStreamEnable(spip->dmarx); - dmaStreamEnable(spip->dmatx); -} - -/** - * @brief Sends data over the SPI bus. - * @details This asynchronous function starts a transmit operation. - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to send - * @param[in] txbuf the pointer to the transmit buffer - * - * @notapi - */ -void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { - - dmaStreamSetMemory0(spip->dmarx, &dummyrx); - dmaStreamSetTransactionSize(spip->dmarx, n); - dmaStreamSetMode(spip->dmarx, spip->rxdmamode); - - dmaStreamSetMemory0(spip->dmatx, txbuf); - dmaStreamSetTransactionSize(spip->dmatx, n); - dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC); - - dmaStreamEnable(spip->dmarx); - dmaStreamEnable(spip->dmatx); -} - -/** - * @brief Receives data from the SPI bus. - * @details This asynchronous function starts a receive operation. - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to receive - * @param[out] rxbuf the pointer to the receive buffer - * - * @notapi - */ -void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { - - dmaStreamSetMemory0(spip->dmarx, rxbuf); - dmaStreamSetTransactionSize(spip->dmarx, n); - dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_MINC); - - dmaStreamSetMemory0(spip->dmatx, &dummytx); - dmaStreamSetTransactionSize(spip->dmatx, n); - dmaStreamSetMode(spip->dmatx, spip->txdmamode); - - dmaStreamEnable(spip->dmarx); - dmaStreamEnable(spip->dmatx); -} - -/** - * @brief Exchanges one frame using a polled wait. - * @details This synchronous function exchanges one frame using a polled - * synchronization method. This function is useful when exchanging - * small amount of data on high speed channels, usually in this - * situation is much more efficient just wait for completion using - * polling than suspending the thread waiting for an interrupt. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] frame the data frame to send over the SPI bus - * @return The received data frame from the SPI bus. - */ -uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) { - - spip->spi->DR = frame; - while ((spip->spi->SR & SPI_SR_RXNE) == 0) - ; - return spip->spi->DR; -} - -#endif /* HAL_USE_SPI */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/SPIv1/spi_lld.h b/firmware/chibios/os/hal/platforms/STM32/SPIv1/spi_lld.h deleted file mode 100644 index c7a417907c..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/SPIv1/spi_lld.h +++ /dev/null @@ -1,628 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/SPIv1/spi_lld.h - * @brief STM32 SPI subsystem low level driver header. - * - * @addtogroup SPI - * @{ - */ - -#ifndef _SPI_LLD_H_ -#define _SPI_LLD_H_ - -#if HAL_USE_SPI || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief SPI1 driver enable switch. - * @details If set to @p TRUE the support for SPI1 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SPI_USE_SPI1) || defined(__DOXYGEN__) -#define STM32_SPI_USE_SPI1 FALSE -#endif - -/** - * @brief SPI2 driver enable switch. - * @details If set to @p TRUE the support for SPI2 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SPI_USE_SPI2) || defined(__DOXYGEN__) -#define STM32_SPI_USE_SPI2 FALSE -#endif - -/** - * @brief SPI3 driver enable switch. - * @details If set to @p TRUE the support for SPI3 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SPI_USE_SPI3) || defined(__DOXYGEN__) -#define STM32_SPI_USE_SPI3 FALSE -#endif - -/** - * @brief SPI4 driver enable switch. - * @details If set to @p TRUE the support for SPI4 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SPI_USE_SPI4) || defined(__DOXYGEN__) -#define STM32_SPI_USE_SPI4 FALSE -#endif - -/** - * @brief SPI5 driver enable switch. - * @details If set to @p TRUE the support for SPI5 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SPI_USE_SPI5) || defined(__DOXYGEN__) -#define STM32_SPI_USE_SPI5 FALSE -#endif - -/** - * @brief SPI6 driver enable switch. - * @details If set to @p TRUE the support for SPI6 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SPI_USE_SPI6) || defined(__DOXYGEN__) -#define STM32_SPI_USE_SPI6 FALSE -#endif - -/** - * @brief SPI1 interrupt priority level setting. - */ -#if !defined(STM32_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI1_IRQ_PRIORITY 10 -#endif - -/** - * @brief SPI2 interrupt priority level setting. - */ -#if !defined(STM32_SPI_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI2_IRQ_PRIORITY 10 -#endif - -/** - * @brief SPI3 interrupt priority level setting. - */ -#if !defined(STM32_SPI_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI3_IRQ_PRIORITY 10 -#endif - -/** - * @brief SPI4 interrupt priority level setting. - */ -#if !defined(STM32_SPI_SPI4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI4_IRQ_PRIORITY 10 -#endif - -/** - * @brief SPI5 interrupt priority level setting. - */ -#if !defined(STM32_SPI_SPI5_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI5_IRQ_PRIORITY 10 -#endif - -/** - * @brief SPI6 interrupt priority level setting. - */ -#if !defined(STM32_SPI_SPI6_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI6_IRQ_PRIORITY 10 -#endif - -/** - * @brief SPI1 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA streams but - * because of the streams ordering the RX stream has always priority - * over the TX stream. - */ -#if !defined(STM32_SPI_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#endif - -/** - * @brief SPI2 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA streams but - * because of the streams ordering the RX stream has always priority - * over the TX stream. - */ -#if !defined(STM32_SPI_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI2_DMA_PRIORITY 1 -#endif - -/** - * @brief SPI3 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA streams but - * because of the streams ordering the RX stream has always priority - * over the TX stream. - */ -#if !defined(STM32_SPI_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI3_DMA_PRIORITY 1 -#endif - -/** - * @brief SPI4 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA streams but - * because of the streams ordering the RX stream has always priority - * over the TX stream. - */ -#if !defined(STM32_SPI_SPI4_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI4_DMA_PRIORITY 1 -#endif - -/** - * @brief SPI5 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA streams but - * because of the streams ordering the RX stream has always priority - * over the TX stream. - */ -#if !defined(STM32_SPI_SPI5_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI5_DMA_PRIORITY 1 -#endif - -/** - * @brief SPI6 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA streams but - * because of the streams ordering the RX stream has always priority - * over the TX stream. - */ -#if !defined(STM32_SPI_SPI6_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI6_DMA_PRIORITY 1 -#endif - -/** - * @brief SPI DMA error hook. - */ -#if !defined(STM32_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__) -#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() -#endif - -#if STM32_ADVANCED_DMA || defined(__DOXYGEN__) - -/** - * @brief DMA stream used for SPI1 RX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_SPI_SPI1_RX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#endif - -/** - * @brief DMA stream used for SPI1 TX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_SPI_SPI1_TX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) -#endif - -/** - * @brief DMA stream used for SPI2 RX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_SPI_SPI2_RX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#endif - -/** - * @brief DMA stream used for SPI2 TX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_SPI_SPI2_TX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#endif - -/** - * @brief DMA stream used for SPI3 RX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_SPI_SPI3_RX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#endif - -/** - * @brief DMA stream used for SPI3 TX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_SPI_SPI3_TX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#endif - -/** - * @brief DMA stream used for SPI4 RX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_SPI_SPI4_RX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#endif - -/** - * @brief DMA stream used for SPI4 TX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_SPI_SPI4_TX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#endif - -/** - * @brief DMA stream used for SPI5 RX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_SPI_SPI5_RX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) -#endif - -/** - * @brief DMA stream used for SPI5 TX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_SPI_SPI5_TX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) -#endif - -/** - * @brief DMA stream used for SPI6 RX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_SPI_SPI6_RX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) -#endif - -/** - * @brief DMA stream used for SPI6 TX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_SPI_SPI6_TX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) -#endif - -#else /* !STM32_ADVANCED_DMA */ - -/* Fixed streams for platforms using the old DMA peripheral, the values are - valid for both STM32F1xx and STM32L1xx.*/ -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) -#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) -#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) -#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) - -#endif /* !STM32_ADVANCED_DMA*/ -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_SPI_USE_SPI1 && !STM32_HAS_SPI1 -#error "SPI1 not present in the selected device" -#endif - -#if STM32_SPI_USE_SPI2 && !STM32_HAS_SPI2 -#error "SPI2 not present in the selected device" -#endif - -#if STM32_SPI_USE_SPI3 && !STM32_HAS_SPI3 -#error "SPI3 not present in the selected device" -#endif - -#if STM32_SPI_USE_SPI4 && !STM32_HAS_SPI4 -#error "SPI4 not present in the selected device" -#endif - -#if STM32_SPI_USE_SPI5 && !STM32_HAS_SPI5 -#error "SPI5 not present in the selected device" -#endif - -#if STM32_SPI_USE_SPI6 && !STM32_HAS_SPI6 -#error "SPI6 not present in the selected device" -#endif - -#if !STM32_SPI_USE_SPI1 && !STM32_SPI_USE_SPI2 && !STM32_SPI_USE_SPI3 && \ - !STM32_SPI_USE_SPI4 && !STM32_SPI_USE_SPI5 && !STM32_SPI_USE_SPI6 -#error "SPI driver activated but no SPI peripheral assigned" -#endif - -#if STM32_SPI_USE_SPI1 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SPI1" -#endif - -#if STM32_SPI_USE_SPI2 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SPI2" -#endif - -#if STM32_SPI_USE_SPI3 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SPI3" -#endif - -#if STM32_SPI_USE_SPI4 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI4_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SPI4" -#endif - -#if STM32_SPI_USE_SPI5 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI5_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SPI5" -#endif - -#if STM32_SPI_USE_SPI6 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI6_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SPI6" -#endif - -#if STM32_SPI_USE_SPI1 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI1_DMA_PRIORITY) -#error "Invalid DMA priority assigned to SPI1" -#endif - -#if STM32_SPI_USE_SPI2 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI2_DMA_PRIORITY) -#error "Invalid DMA priority assigned to SPI2" -#endif - -#if STM32_SPI_USE_SPI3 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI3_DMA_PRIORITY) -#error "Invalid DMA priority assigned to SPI3" -#endif - -#if STM32_SPI_USE_SPI4 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI4_DMA_PRIORITY) -#error "Invalid DMA priority assigned to SPI4" -#endif - -#if STM32_SPI_USE_SPI5 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI5_DMA_PRIORITY) -#error "Invalid DMA priority assigned to SPI5" -#endif - -#if STM32_SPI_USE_SPI6 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI6_DMA_PRIORITY) -#error "Invalid DMA priority assigned to SPI6" -#endif - -#if STM32_SPI_USE_SPI1 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_RX_DMA_STREAM, STM32_SPI1_RX_DMA_MSK) -#error "invalid DMA stream associated to SPI1 RX" -#endif - -#if STM32_SPI_USE_SPI1 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_TX_DMA_STREAM, STM32_SPI1_TX_DMA_MSK) -#error "invalid DMA stream associated to SPI1 TX" -#endif - -#if STM32_SPI_USE_SPI2 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI2_RX_DMA_STREAM, STM32_SPI2_RX_DMA_MSK) -#error "invalid DMA stream associated to SPI2 RX" -#endif - -#if STM32_SPI_USE_SPI2 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI2_TX_DMA_STREAM, STM32_SPI2_TX_DMA_MSK) -#error "invalid DMA stream associated to SPI2 TX" -#endif - -#if STM32_SPI_USE_SPI3 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI3_RX_DMA_STREAM, STM32_SPI3_RX_DMA_MSK) -#error "invalid DMA stream associated to SPI3 RX" -#endif - -#if STM32_SPI_USE_SPI3 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI3_TX_DMA_STREAM, STM32_SPI3_TX_DMA_MSK) -#error "invalid DMA stream associated to SPI3 TX" -#endif - -#if STM32_SPI_USE_SPI4 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI4_RX_DMA_STREAM, STM32_SPI4_RX_DMA_MSK) -#error "invalid DMA stream associated to SPI4 RX" -#endif - -#if STM32_SPI_USE_SPI4 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI4_TX_DMA_STREAM, STM32_SPI4_TX_DMA_MSK) -#error "invalid DMA stream associated to SPI4 TX" -#endif - -#if STM32_SPI_USE_SPI5 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI5_RX_DMA_STREAM, STM32_SPI5_RX_DMA_MSK) -#error "invalid DMA stream associated to SPI5 RX" -#endif - -#if STM32_SPI_USE_SPI5 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI5_TX_DMA_STREAM, STM32_SPI5_TX_DMA_MSK) -#error "invalid DMA stream associated to SPI5 TX" -#endif - -#if STM32_SPI_USE_SPI6 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI6_RX_DMA_STREAM, STM32_SPI6_RX_DMA_MSK) -#error "invalid DMA stream associated to SPI6 RX" -#endif - -#if STM32_SPI_USE_SPI6 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI6_TX_DMA_STREAM, STM32_SPI6_TX_DMA_MSK) -#error "invalid DMA stream associated to SPI6 TX" -#endif - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a structure representing an SPI driver. - */ -typedef struct SPIDriver SPIDriver; - -/** - * @brief SPI notification callback type. - * - * @param[in] spip pointer to the @p SPIDriver object triggering the - * callback - */ -typedef void (*spicallback_t)(SPIDriver *spip); - -/** - * @brief Driver configuration structure. - */ -typedef struct { - /** - * @brief Operation complete callback or @p NULL. - */ - spicallback_t end_cb; - /* End of the mandatory fields.*/ - /** - * @brief The chip select line port. - */ - ioportid_t ssport; - /** - * @brief The chip select line pad number. - */ - uint16_t sspad; - /** - * @brief SPI initialization data. - */ - uint16_t cr1; -} SPIConfig; - -/** - * @brief Structure representing a SPI driver. - */ -struct SPIDriver { - /** - * @brief Driver state. - */ - spistate_t state; - /** - * @brief Current configuration data. - */ - const SPIConfig *config; -#if SPI_USE_WAIT || defined(__DOXYGEN__) - /** - * @brief Waiting thread. - */ - Thread *thread; -#endif /* SPI_USE_WAIT */ -#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) -#if CH_USE_MUTEXES || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the bus. - */ - Mutex mutex; -#elif CH_USE_SEMAPHORES - Semaphore semaphore; -#endif -#endif /* SPI_USE_MUTUAL_EXCLUSION */ -#if defined(SPI_DRIVER_EXT_FIELDS) - SPI_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the SPIx registers block. - */ - SPI_TypeDef *spi; - /** - * @brief Receive DMA stream. - */ - const stm32_dma_stream_t *dmarx; - /** - * @brief Transmit DMA stream. - */ - const stm32_dma_stream_t *dmatx; - /** - * @brief RX DMA mode bit mask. - */ - uint32_t rxdmamode; - /** - * @brief TX DMA mode bit mask. - */ - uint32_t txdmamode; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_SPI_USE_SPI1 && !defined(__DOXYGEN__) -extern SPIDriver SPID1; -#endif - -#if STM32_SPI_USE_SPI2 && !defined(__DOXYGEN__) -extern SPIDriver SPID2; -#endif - -#if STM32_SPI_USE_SPI3 && !defined(__DOXYGEN__) -extern SPIDriver SPID3; -#endif - -#if STM32_SPI_USE_SPI4 && !defined(__DOXYGEN__) -extern SPIDriver SPID4; -#endif - -#if STM32_SPI_USE_SPI5 && !defined(__DOXYGEN__) -extern SPIDriver SPID5; -#endif - -#if STM32_SPI_USE_SPI6 && !defined(__DOXYGEN__) -extern SPIDriver SPID6; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void spi_lld_init(void); - void spi_lld_start(SPIDriver *spip); - void spi_lld_stop(SPIDriver *spip); - void spi_lld_select(SPIDriver *spip); - void spi_lld_unselect(SPIDriver *spip); - void spi_lld_ignore(SPIDriver *spip, size_t n); - void spi_lld_exchange(SPIDriver *spip, size_t n, - const void *txbuf, void *rxbuf); - void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); - void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); - uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_SPI */ - -#endif /* _SPI_LLD_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/SPIv2/spi_lld.c b/firmware/chibios/os/hal/platforms/STM32/SPIv2/spi_lld.c deleted file mode 100644 index 300ea68ce6..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/SPIv2/spi_lld.c +++ /dev/null @@ -1,502 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/SPIv2/spi_lld.c - * @brief STM32 SPI subsystem low level driver source. - * - * @addtogroup SPI - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_SPI || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define SPI1_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI1_RX_DMA_STREAM, \ - STM32_SPI1_RX_DMA_CHN) - -#define SPI1_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI1_TX_DMA_STREAM, \ - STM32_SPI1_TX_DMA_CHN) - -#define SPI2_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI2_RX_DMA_STREAM, \ - STM32_SPI2_RX_DMA_CHN) - -#define SPI2_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI2_TX_DMA_STREAM, \ - STM32_SPI2_TX_DMA_CHN) - -#define SPI3_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI3_RX_DMA_STREAM, \ - STM32_SPI3_RX_DMA_CHN) - -#define SPI3_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SPI_SPI3_TX_DMA_STREAM, \ - STM32_SPI3_TX_DMA_CHN) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief SPI1 driver identifier.*/ -#if STM32_SPI_USE_SPI1 || defined(__DOXYGEN__) -SPIDriver SPID1; -#endif - -/** @brief SPI2 driver identifier.*/ -#if STM32_SPI_USE_SPI2 || defined(__DOXYGEN__) -SPIDriver SPID2; -#endif - -/** @brief SPI3 driver identifier.*/ -#if STM32_SPI_USE_SPI3 || defined(__DOXYGEN__) -SPIDriver SPID3; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -static uint16_t dummytx; -static uint16_t dummyrx; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Shared end-of-rx service routine. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] flags pre-shifted content of the ISR register - */ -static void spi_lld_serve_rx_interrupt(SPIDriver *spip, uint32_t flags) { - - /* DMA errors handling.*/ -#if defined(STM32_SPI_DMA_ERROR_HOOK) - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - STM32_SPI_DMA_ERROR_HOOK(spip); - } -#else - (void)flags; -#endif - - /* Stop everything.*/ - dmaStreamDisable(spip->dmatx); - dmaStreamDisable(spip->dmarx); - - /* Portable SPI ISR code defined in the high level driver, note, it is - a macro.*/ - _spi_isr_code(spip); -} - -/** - * @brief Shared end-of-tx service routine. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] flags pre-shifted content of the ISR register - */ -static void spi_lld_serve_tx_interrupt(SPIDriver *spip, uint32_t flags) { - - /* DMA errors handling.*/ -#if defined(STM32_SPI_DMA_ERROR_HOOK) - (void)spip; - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - STM32_SPI_DMA_ERROR_HOOK(spip); - } -#else - (void)spip; - (void)flags; -#endif -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level SPI driver initialization. - * - * @notapi - */ -void spi_lld_init(void) { - - dummytx = 0xFFFF; - -#if STM32_SPI_USE_SPI1 - spiObjectInit(&SPID1); - SPID1.spi = SPI1; - SPID1.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI1_RX_DMA_STREAM); - SPID1.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI1_TX_DMA_STREAM); - SPID1.rxdmamode = STM32_DMA_CR_CHSEL(SPI1_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; - SPID1.txdmamode = STM32_DMA_CR_CHSEL(SPI1_TX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) | - STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; -#endif - -#if STM32_SPI_USE_SPI2 - spiObjectInit(&SPID2); - SPID2.spi = SPI2; - SPID2.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI2_RX_DMA_STREAM); - SPID2.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI2_TX_DMA_STREAM); - SPID2.rxdmamode = STM32_DMA_CR_CHSEL(SPI2_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; - SPID2.txdmamode = STM32_DMA_CR_CHSEL(SPI2_TX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) | - STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; -#endif - -#if STM32_SPI_USE_SPI3 - spiObjectInit(&SPID3); - SPID3.spi = SPI3; - SPID3.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI3_RX_DMA_STREAM); - SPID3.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI3_TX_DMA_STREAM); - SPID3.rxdmamode = STM32_DMA_CR_CHSEL(SPI3_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; - SPID3.txdmamode = STM32_DMA_CR_CHSEL(SPI3_TX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) | - STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE; -#endif -} - -/** - * @brief Configures and activates the SPI peripheral. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_start(SPIDriver *spip) { - uint32_t ds; - - /* If in stopped state then enables the SPI and DMA clocks.*/ - if (spip->state == SPI_STOP) { -#if STM32_SPI_USE_SPI1 - if (&SPID1 == spip) { - bool_t b; - b = dmaStreamAllocate(spip->dmarx, - STM32_SPI_SPI1_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, - (void *)spip); - chDbgAssert(!b, "spi_lld_start(), #1", "stream already allocated"); - b = dmaStreamAllocate(spip->dmatx, - STM32_SPI_SPI1_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, - (void *)spip); - chDbgAssert(!b, "spi_lld_start(), #2", "stream already allocated"); - rccEnableSPI1(FALSE); - } -#endif -#if STM32_SPI_USE_SPI2 - if (&SPID2 == spip) { - bool_t b; - b = dmaStreamAllocate(spip->dmarx, - STM32_SPI_SPI2_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, - (void *)spip); - chDbgAssert(!b, "spi_lld_start(), #3", "stream already allocated"); - b = dmaStreamAllocate(spip->dmatx, - STM32_SPI_SPI2_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, - (void *)spip); - chDbgAssert(!b, "spi_lld_start(), #4", "stream already allocated"); - rccEnableSPI2(FALSE); - } -#endif -#if STM32_SPI_USE_SPI3 - if (&SPID3 == spip) { - bool_t b; - b = dmaStreamAllocate(spip->dmarx, - STM32_SPI_SPI3_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, - (void *)spip); - chDbgAssert(!b, "spi_lld_start(), #5", "stream already allocated"); - b = dmaStreamAllocate(spip->dmatx, - STM32_SPI_SPI3_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, - (void *)spip); - chDbgAssert(!b, "spi_lld_start(), #6", "stream already allocated"); - rccEnableSPI3(FALSE); - } -#endif - - /* DMA setup.*/ - dmaStreamSetPeripheral(spip->dmarx, &spip->spi->DR); - dmaStreamSetPeripheral(spip->dmatx, &spip->spi->DR); - } - - /* Configuration-specific DMA setup.*/ - ds = spip->config->cr2 & SPI_CR2_DS; - if (!ds || (ds <= (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0))) { - /* Frame width is 8 bits or smaller.*/ - spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) | - STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE; - spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) | - STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE; - } - else { - /* Frame width is larger than 8 bits.*/ - spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) | - STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; - spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) | - STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; - } - /* SPI setup and enable.*/ - spip->spi->CR1 = 0; - spip->spi->CR1 = spip->config->cr1 | SPI_CR1_MSTR | SPI_CR1_SSM | - SPI_CR1_SSI; - spip->spi->CR2 = spip->config->cr2 | SPI_CR2_FRXTH | SPI_CR2_SSOE | - SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN; - spip->spi->CR1 |= SPI_CR1_SPE; -} - -/** - * @brief Deactivates the SPI peripheral. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_stop(SPIDriver *spip) { - - /* If in ready state then disables the SPI clock.*/ - if (spip->state == SPI_READY) { - - /* SPI disable.*/ - spip->spi->CR1 = 0; - spip->spi->CR2 = 0; - dmaStreamRelease(spip->dmarx); - dmaStreamRelease(spip->dmatx); - -#if STM32_SPI_USE_SPI1 - if (&SPID1 == spip) - rccDisableSPI1(FALSE); -#endif -#if STM32_SPI_USE_SPI2 - if (&SPID2 == spip) - rccDisableSPI2(FALSE); -#endif -#if STM32_SPI_USE_SPI3 - if (&SPID3 == spip) - rccDisableSPI3(FALSE); -#endif - } -} - -/** - * @brief Asserts the slave select signal and prepares for transfers. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_select(SPIDriver *spip) { - - palClearPad(spip->config->ssport, spip->config->sspad); -} - -/** - * @brief Deasserts the slave select signal. - * @details The previously selected peripheral is unselected. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_unselect(SPIDriver *spip) { - - palSetPad(spip->config->ssport, spip->config->sspad); -} - -/** - * @brief Ignores data on the SPI bus. - * @details This asynchronous function starts the transmission of a series of - * idle words on the SPI bus and ignores the received data. - * @post At the end of the operation the configured callback is invoked. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be ignored - * - * @notapi - */ -void spi_lld_ignore(SPIDriver *spip, size_t n) { - - dmaStreamSetMemory0(spip->dmarx, &dummyrx); - dmaStreamSetTransactionSize(spip->dmarx, n); - dmaStreamSetMode(spip->dmarx, spip->rxdmamode); - - dmaStreamSetMemory0(spip->dmatx, &dummytx); - dmaStreamSetTransactionSize(spip->dmatx, n); - dmaStreamSetMode(spip->dmatx, spip->txdmamode); - - dmaStreamEnable(spip->dmarx); - dmaStreamEnable(spip->dmatx); -} - -/** - * @brief Exchanges data on the SPI bus. - * @details This asynchronous function starts a simultaneous transmit/receive - * operation. - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be exchanged - * @param[in] txbuf the pointer to the transmit buffer - * @param[out] rxbuf the pointer to the receive buffer - * - * @notapi - */ -void spi_lld_exchange(SPIDriver *spip, size_t n, - const void *txbuf, void *rxbuf) { - - dmaStreamSetMemory0(spip->dmarx, rxbuf); - dmaStreamSetTransactionSize(spip->dmarx, n); - dmaStreamSetMode(spip->dmarx, spip->rxdmamode| STM32_DMA_CR_MINC); - - dmaStreamSetMemory0(spip->dmatx, txbuf); - dmaStreamSetTransactionSize(spip->dmatx, n); - dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC); - - dmaStreamEnable(spip->dmarx); - dmaStreamEnable(spip->dmatx); -} - -/** - * @brief Sends data over the SPI bus. - * @details This asynchronous function starts a transmit operation. - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to send - * @param[in] txbuf the pointer to the transmit buffer - * - * @notapi - */ -void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { - - dmaStreamSetMemory0(spip->dmarx, &dummyrx); - dmaStreamSetTransactionSize(spip->dmarx, n); - dmaStreamSetMode(spip->dmarx, spip->rxdmamode); - - dmaStreamSetMemory0(spip->dmatx, txbuf); - dmaStreamSetTransactionSize(spip->dmatx, n); - dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC); - - dmaStreamEnable(spip->dmarx); - dmaStreamEnable(spip->dmatx); -} - -/** - * @brief Receives data from the SPI bus. - * @details This asynchronous function starts a receive operation. - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to receive - * @param[out] rxbuf the pointer to the receive buffer - * - * @notapi - */ -void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { - - dmaStreamSetMemory0(spip->dmarx, rxbuf); - dmaStreamSetTransactionSize(spip->dmarx, n); - dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_MINC); - - dmaStreamSetMemory0(spip->dmatx, &dummytx); - dmaStreamSetTransactionSize(spip->dmatx, n); - dmaStreamSetMode(spip->dmatx, spip->txdmamode); - - dmaStreamEnable(spip->dmarx); - dmaStreamEnable(spip->dmatx); -} - -/** - * @brief Exchanges one frame using a polled wait. - * @details This synchronous function exchanges one frame using a polled - * synchronization method. This function is useful when exchanging - * small amount of data on high speed channels, usually in this - * situation is much more efficient just wait for completion using - * polling than suspending the thread waiting for an interrupt. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] frame the data frame to send over the SPI bus - * @return The received data frame from the SPI bus. - */ -uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) { - - /* - * Data register must be accessed with the appropriate data size. - * Byte size access (uint8_t *) for transactions that are <= 8-bit. - * Halfword size access (uint16_t) for transactions that are <= 8-bit. - */ - if ((spip->config->cr2 & SPI_CR2_DS) <= (SPI_CR2_DS_2 | - SPI_CR2_DS_1 | - SPI_CR2_DS_0)) { - volatile uint8_t *spidr = (volatile uint8_t *)&spip->spi->DR; - *spidr = (uint8_t)frame; - while ((spip->spi->SR & SPI_SR_RXNE) == 0) - ; - return (uint16_t)*spidr; - } - else { - spip->spi->DR = frame; - while ((spip->spi->SR & SPI_SR_RXNE) == 0) - ; - return spip->spi->DR; - } -} - -#endif /* HAL_USE_SPI */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/SPIv2/spi_lld.h b/firmware/chibios/os/hal/platforms/STM32/SPIv2/spi_lld.h deleted file mode 100644 index 9dfe2f2424..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/SPIv2/spi_lld.h +++ /dev/null @@ -1,424 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/SPIv2/spi_lld.h - * @brief STM32 SPI subsystem low level driver header. - * - * @addtogroup SPI - * @{ - */ - -#ifndef _SPI_LLD_H_ -#define _SPI_LLD_H_ - -#if HAL_USE_SPI || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief SPI1 driver enable switch. - * @details If set to @p TRUE the support for SPI1 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SPI_USE_SPI1) || defined(__DOXYGEN__) -#define STM32_SPI_USE_SPI1 FALSE -#endif - -/** - * @brief SPI2 driver enable switch. - * @details If set to @p TRUE the support for SPI2 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SPI_USE_SPI2) || defined(__DOXYGEN__) -#define STM32_SPI_USE_SPI2 FALSE -#endif - -/** - * @brief SPI3 driver enable switch. - * @details If set to @p TRUE the support for SPI3 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SPI_USE_SPI3) || defined(__DOXYGEN__) -#define STM32_SPI_USE_SPI3 FALSE -#endif - -/** - * @brief SPI1 interrupt priority level setting. - */ -#if !defined(STM32_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI1_IRQ_PRIORITY 10 -#endif - -/** - * @brief SPI2 interrupt priority level setting. - */ -#if !defined(STM32_SPI_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI2_IRQ_PRIORITY 10 -#endif - -/** - * @brief SPI3 interrupt priority level setting. - */ -#if !defined(STM32_SPI_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI3_IRQ_PRIORITY 10 -#endif - -/** - * @brief SPI1 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA streams but - * because of the streams ordering the RX stream has always priority - * over the TX stream. - */ -#if !defined(STM32_SPI_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#endif - -/** - * @brief SPI2 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA streams but - * because of the streams ordering the RX stream has always priority - * over the TX stream. - */ -#if !defined(STM32_SPI_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI2_DMA_PRIORITY 1 -#endif - -/** - * @brief SPI3 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA streams but - * because of the streams ordering the RX stream has always priority - * over the TX stream. - */ -#if !defined(STM32_SPI_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI3_DMA_PRIORITY 1 -#endif - -/** - * @brief SPI DMA error hook. - */ -#if !defined(STM32_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__) -#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() -#endif - -#if STM32_ADVANCED_DMA || defined(__DOXYGEN__) - -/** - * @brief DMA stream used for SPI1 RX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_SPI_SPI1_RX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#endif - -/** - * @brief DMA stream used for SPI1 TX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_SPI_SPI1_TX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) -#endif - -/** - * @brief DMA stream used for SPI2 RX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_SPI_SPI2_RX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#endif - -/** - * @brief DMA stream used for SPI2 TX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_SPI_SPI2_TX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#endif - -/** - * @brief DMA stream used for SPI3 RX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_SPI_SPI3_RX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#endif - -/** - * @brief DMA stream used for SPI3 TX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_SPI_SPI3_TX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#endif - -#else /* !STM32_ADVANCED_DMA */ - -#if defined(STM32F0XX) -/* Fixed values for STM32F0xx devices.*/ -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#endif /* defined(STM32F0XX) */ - -#if defined(STM32F30X) || defined(STM32F37X) -/* Fixed values for STM32F3xx devices.*/ -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#endif /* defined(STM32F30X) */ - -#endif /* !STM32_ADVANCED_DMA*/ -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_SPI_USE_SPI1 && !STM32_HAS_SPI1 -#error "SPI1 not present in the selected device" -#endif - -#if STM32_SPI_USE_SPI2 && !STM32_HAS_SPI2 -#error "SPI2 not present in the selected device" -#endif - -#if STM32_SPI_USE_SPI3 && !STM32_HAS_SPI3 -#error "SPI3 not present in the selected device" -#endif - -#if !STM32_SPI_USE_SPI1 && !STM32_SPI_USE_SPI2 && !STM32_SPI_USE_SPI3 -#error "SPI driver activated but no SPI peripheral assigned" -#endif - -#if STM32_SPI_USE_SPI1 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SPI1" -#endif - -#if STM32_SPI_USE_SPI2 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SPI2" -#endif - -#if STM32_SPI_USE_SPI3 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SPI3" -#endif - -#if STM32_SPI_USE_SPI1 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI1_DMA_PRIORITY) -#error "Invalid DMA priority assigned to SPI1" -#endif - -#if STM32_SPI_USE_SPI2 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI2_DMA_PRIORITY) -#error "Invalid DMA priority assigned to SPI2" -#endif - -#if STM32_SPI_USE_SPI3 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI3_DMA_PRIORITY) -#error "Invalid DMA priority assigned to SPI3" -#endif - -#if STM32_SPI_USE_SPI1 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_RX_DMA_STREAM, STM32_SPI1_RX_DMA_MSK) -#error "invalid DMA stream associated to SPI1 RX" -#endif - -#if STM32_SPI_USE_SPI1 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_TX_DMA_STREAM, STM32_SPI1_TX_DMA_MSK) -#error "invalid DMA stream associated to SPI1 TX" -#endif - -#if STM32_SPI_USE_SPI2 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI2_RX_DMA_STREAM, STM32_SPI2_RX_DMA_MSK) -#error "invalid DMA stream associated to SPI2 RX" -#endif - -#if STM32_SPI_USE_SPI2 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI2_TX_DMA_STREAM, STM32_SPI2_TX_DMA_MSK) -#error "invalid DMA stream associated to SPI2 TX" -#endif - -#if STM32_SPI_USE_SPI3 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI3_RX_DMA_STREAM, STM32_SPI3_RX_DMA_MSK) -#error "invalid DMA stream associated to SPI3 RX" -#endif - -#if STM32_SPI_USE_SPI3 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI3_TX_DMA_STREAM, STM32_SPI3_TX_DMA_MSK) -#error "invalid DMA stream associated to SPI3 TX" -#endif - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a structure representing an SPI driver. - */ -typedef struct SPIDriver SPIDriver; - -/** - * @brief SPI notification callback type. - * - * @param[in] spip pointer to the @p SPIDriver object triggering the - * callback - */ -typedef void (*spicallback_t)(SPIDriver *spip); - -/** - * @brief Driver configuration structure. - */ -typedef struct { - /** - * @brief Operation complete callback or @p NULL. - */ - spicallback_t end_cb; - /* End of the mandatory fields.*/ - /** - * @brief The chip select line port. - */ - ioportid_t ssport; - /** - * @brief The chip select line pad number. - */ - uint16_t sspad; - /** - * @brief SPI CR1 register initialization data. - */ - uint16_t cr1; - /** - * @brief SPI CR2 register initialization data. - */ - uint16_t cr2; -} SPIConfig; - -/** - * @brief Structure representing a SPI driver. - */ -struct SPIDriver { - /** - * @brief Driver state. - */ - spistate_t state; - /** - * @brief Current configuration data. - */ - const SPIConfig *config; -#if SPI_USE_WAIT || defined(__DOXYGEN__) - /** - * @brief Waiting thread. - */ - Thread *thread; -#endif /* SPI_USE_WAIT */ -#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) -#if CH_USE_MUTEXES || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the bus. - */ - Mutex mutex; -#elif CH_USE_SEMAPHORES - Semaphore semaphore; -#endif -#endif /* SPI_USE_MUTUAL_EXCLUSION */ -#if defined(SPI_DRIVER_EXT_FIELDS) - SPI_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the SPIx registers block. - */ - SPI_TypeDef *spi; - /** - * @brief Receive DMA stream. - */ - const stm32_dma_stream_t *dmarx; - /** - * @brief Transmit DMA stream. - */ - const stm32_dma_stream_t *dmatx; - /** - * @brief RX DMA mode bit mask. - */ - uint32_t rxdmamode; - /** - * @brief TX DMA mode bit mask. - */ - uint32_t txdmamode; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_SPI_USE_SPI1 && !defined(__DOXYGEN__) -extern SPIDriver SPID1; -#endif - -#if STM32_SPI_USE_SPI2 && !defined(__DOXYGEN__) -extern SPIDriver SPID2; -#endif - -#if STM32_SPI_USE_SPI3 && !defined(__DOXYGEN__) -extern SPIDriver SPID3; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void spi_lld_init(void); - void spi_lld_start(SPIDriver *spip); - void spi_lld_stop(SPIDriver *spip); - void spi_lld_select(SPIDriver *spip); - void spi_lld_unselect(SPIDriver *spip); - void spi_lld_ignore(SPIDriver *spip, size_t n); - void spi_lld_exchange(SPIDriver *spip, size_t n, - const void *txbuf, void *rxbuf); - void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); - void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); - uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_SPI */ - -#endif /* _SPI_LLD_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/TIMv1/gpt_lld.c b/firmware/chibios/os/hal/platforms/STM32/TIMv1/gpt_lld.c deleted file mode 100644 index 60ad0299b8..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/TIMv1/gpt_lld.c +++ /dev/null @@ -1,775 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/gpt_lld.c - * @brief STM32 GPT subsystem low level driver source. - * - * @addtogroup GPT - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_GPT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief GPTD1 driver identifier. - * @note The driver GPTD1 allocates the complex timer TIM1 when enabled. - */ -#if STM32_GPT_USE_TIM1 || defined(__DOXYGEN__) -GPTDriver GPTD1; -#endif - -/** - * @brief GPTD2 driver identifier. - * @note The driver GPTD2 allocates the timer TIM2 when enabled. - */ -#if STM32_GPT_USE_TIM2 || defined(__DOXYGEN__) -GPTDriver GPTD2; -#endif - -/** - * @brief GPTD3 driver identifier. - * @note The driver GPTD3 allocates the timer TIM3 when enabled. - */ -#if STM32_GPT_USE_TIM3 || defined(__DOXYGEN__) -GPTDriver GPTD3; -#endif - -/** - * @brief GPTD4 driver identifier. - * @note The driver GPTD4 allocates the timer TIM4 when enabled. - */ -#if STM32_GPT_USE_TIM4 || defined(__DOXYGEN__) -GPTDriver GPTD4; -#endif - -/** - * @brief GPTD5 driver identifier. - * @note The driver GPTD5 allocates the timer TIM5 when enabled. - */ -#if STM32_GPT_USE_TIM5 || defined(__DOXYGEN__) -GPTDriver GPTD5; -#endif - -/** - * @brief GPTD6 driver identifier. - * @note The driver GPTD6 allocates the timer TIM6 when enabled. - */ -#if STM32_GPT_USE_TIM6 || defined(__DOXYGEN__) -GPTDriver GPTD6; -#endif - -/** - * @brief GPTD7 driver identifier. - * @note The driver GPTD7 allocates the timer TIM7 when enabled. - */ -#if STM32_GPT_USE_TIM7 || defined(__DOXYGEN__) -GPTDriver GPTD7; -#endif - -/** - * @brief GPTD8 driver identifier. - * @note The driver GPTD8 allocates the timer TIM8 when enabled. - */ -#if STM32_GPT_USE_TIM8 || defined(__DOXYGEN__) -GPTDriver GPTD8; -#endif - -/** - * @brief GPTD9 driver identifier. - * @note The driver GPTD9 allocates the timer TIM9 when enabled. - */ -#if STM32_GPT_USE_TIM9 || defined(__DOXYGEN__) -GPTDriver GPTD9; -#endif - -/** - * @brief GPTD11 driver identifier. - * @note The driver GPTD11 allocates the timer TIM11 when enabled. - */ -#if STM32_GPT_USE_TIM11 || defined(__DOXYGEN__) -GPTDriver GPTD11; -#endif - -/** - * @brief GPTD12 driver identifier. - * @note The driver GPTD12 allocates the timer TIM12 when enabled. - */ -#if STM32_GPT_USE_TIM12 || defined(__DOXYGEN__) -GPTDriver GPTD12; -#endif - -/** - * @brief GPTD14 driver identifier. - * @note The driver GPTD14 allocates the timer TIM14 when enabled. - */ -#if STM32_GPT_USE_TIM14 || defined(__DOXYGEN__) -GPTDriver GPTD14; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Shared IRQ handler. - * - * @param[in] gptp pointer to a @p GPTDriver object - */ -static void gpt_lld_serve_interrupt(GPTDriver *gptp) { - - gptp->tim->SR = 0; - if (gptp->state == GPT_ONESHOT) { - gptp->state = GPT_READY; /* Back in GPT_READY state. */ - gpt_lld_stop_timer(gptp); /* Timer automatically stopped. */ - } - gptp->config->callback(gptp); -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if STM32_GPT_USE_TIM1 -#if !defined(STM32_TIM1_UP_HANDLER) -#error "STM32_TIM1_UP_HANDLER not defined" -#endif -/** - * @brief TIM2 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) { - - CH_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD1); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_GPT_USE_TIM1 */ - -#if STM32_GPT_USE_TIM2 -#if !defined(STM32_TIM2_HANDLER) -#error "STM32_TIM2_HANDLER not defined" -#endif -/** - * @brief TIM2 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM2_HANDLER) { - - CH_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD2); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_GPT_USE_TIM2 */ - -#if STM32_GPT_USE_TIM3 -#if !defined(STM32_TIM3_HANDLER) -#error "STM32_TIM3_HANDLER not defined" -#endif -/** - * @brief TIM3 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM3_HANDLER) { - - CH_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD3); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_GPT_USE_TIM3 */ - -#if STM32_GPT_USE_TIM4 -#if !defined(STM32_TIM4_HANDLER) -#error "STM32_TIM4_HANDLER not defined" -#endif -/** - * @brief TIM4 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM4_HANDLER) { - - CH_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD4); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_GPT_USE_TIM4 */ - -#if STM32_GPT_USE_TIM5 -#if !defined(STM32_TIM5_HANDLER) -#error "STM32_TIM5_HANDLER not defined" -#endif -/** - * @brief TIM5 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM5_HANDLER) { - - CH_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD5); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_GPT_USE_TIM5 */ - -#if STM32_GPT_USE_TIM6 -#if !defined(STM32_TIM6_HANDLER) -#error "STM32_TIM6_HANDLER not defined" -#endif -/** - * @brief TIM6 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM6_HANDLER) { - - CH_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD6); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_GPT_USE_TIM6 */ - -#if STM32_GPT_USE_TIM7 -#if !defined(STM32_TIM7_HANDLER) -#error "STM32_TIM7_HANDLER not defined" -#endif -/** - * @brief TIM7 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM7_HANDLER) { - - CH_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD7); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_GPT_USE_TIM7 */ - -#if STM32_GPT_USE_TIM8 -#if !defined(STM32_TIM8_UP_HANDLER) -#error "STM32_TIM8_UP_HANDLER not defined" -#endif -/** - * @brief TIM8 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) { - - CH_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD8); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_GPT_USE_TIM8 */ - -#if STM32_GPT_USE_TIM9 -#if !defined(STM32_TIM9_HANDLER) -#error "STM32_TIM9_HANDLER not defined" -#endif -/** - * @brief TIM9 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM9_HANDLER) { - - CH_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD9); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_GPT_USE_TIM9 */ - -#if STM32_GPT_USE_TIM11 -#if !defined(STM32_TIM11_HANDLER) -#error "STM32_TIM11_HANDLER not defined" -#endif -/** - * @brief TIM11 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM11_HANDLER) { - - CH_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD11); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_GPT_USE_TIM11 */ - -#if STM32_GPT_USE_TIM12 -#if !defined(STM32_TIM12_HANDLER) -#error "STM32_TIM12_HANDLER not defined" -#endif -/** - * @brief TIM12 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM12_HANDLER) { - - CH_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD12); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_GPT_USE_TIM12 */ - -#if STM32_GPT_USE_TIM14 -#if !defined(STM32_TIM14_HANDLER) -#error "STM32_TIM14_HANDLER not defined" -#endif -/** - * @brief TIM14 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM14_HANDLER) { - - CH_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD14); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_GPT_USE_TIM14 */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level GPT driver initialization. - * - * @notapi - */ -void gpt_lld_init(void) { - -#if STM32_GPT_USE_TIM1 - /* Driver initialization.*/ - GPTD1.tim = STM32_TIM1; - gptObjectInit(&GPTD1); -#endif - -#if STM32_GPT_USE_TIM2 - /* Driver initialization.*/ - GPTD2.tim = STM32_TIM2; - gptObjectInit(&GPTD2); -#endif - -#if STM32_GPT_USE_TIM3 - /* Driver initialization.*/ - GPTD3.tim = STM32_TIM3; - gptObjectInit(&GPTD3); -#endif - -#if STM32_GPT_USE_TIM4 - /* Driver initialization.*/ - GPTD4.tim = STM32_TIM4; - gptObjectInit(&GPTD4); -#endif - -#if STM32_GPT_USE_TIM5 - /* Driver initialization.*/ - GPTD5.tim = STM32_TIM5; - gptObjectInit(&GPTD5); -#endif - -#if STM32_GPT_USE_TIM6 - /* Driver initialization.*/ - GPTD6.tim = STM32_TIM6; - gptObjectInit(&GPTD6); -#endif - -#if STM32_GPT_USE_TIM7 - /* Driver initialization.*/ - GPTD7.tim = STM32_TIM7; - gptObjectInit(&GPTD7); -#endif - -#if STM32_GPT_USE_TIM8 - /* Driver initialization.*/ - GPTD8.tim = STM32_TIM8; - gptObjectInit(&GPTD8); -#endif - -#if STM32_GPT_USE_TIM9 - /* Driver initialization.*/ - GPTD9.tim = STM32_TIM9; - gptObjectInit(&GPTD9); -#endif - -#if STM32_GPT_USE_TIM11 - /* Driver initialization.*/ - GPTD11.tim = STM32_TIM11; - gptObjectInit(&GPTD11); -#endif - -#if STM32_GPT_USE_TIM12 - /* Driver initialization.*/ - GPTD12.tim = STM32_TIM12; - gptObjectInit(&GPTD12); -#endif - -#if STM32_GPT_USE_TIM14 - /* Driver initialization.*/ - GPTD14.tim = STM32_TIM14; - gptObjectInit(&GPTD14); -#endif -} - -/** - * @brief Configures and activates the GPT peripheral. - * - * @param[in] gptp pointer to the @p GPTDriver object - * - * @notapi - */ -void gpt_lld_start(GPTDriver *gptp) { - uint16_t psc; - - if (gptp->state == GPT_STOP) { - /* Clock activation.*/ -#if STM32_GPT_USE_TIM1 - if (&GPTD1 == gptp) { - rccEnableTIM1(FALSE); - rccResetTIM1(); - nvicEnableVector(STM32_TIM1_UP_NUMBER, - CORTEX_PRIORITY_MASK(STM32_GPT_TIM1_IRQ_PRIORITY)); -#if defined(STM32_TIM1CLK) - gptp->clock = STM32_TIM1CLK; -#else - gptp->clock = STM32_TIMCLK2; -#endif - } -#endif -#if STM32_GPT_USE_TIM2 - if (&GPTD2 == gptp) { - rccEnableTIM2(FALSE); - rccResetTIM2(); - nvicEnableVector(STM32_TIM2_NUMBER, - CORTEX_PRIORITY_MASK(STM32_GPT_TIM2_IRQ_PRIORITY)); - gptp->clock = STM32_TIMCLK1; - } -#endif -#if STM32_GPT_USE_TIM3 - if (&GPTD3 == gptp) { - rccEnableTIM3(FALSE); - rccResetTIM3(); - nvicEnableVector(STM32_TIM3_NUMBER, - CORTEX_PRIORITY_MASK(STM32_GPT_TIM3_IRQ_PRIORITY)); - gptp->clock = STM32_TIMCLK1; - } -#endif -#if STM32_GPT_USE_TIM4 - if (&GPTD4 == gptp) { - rccEnableTIM4(FALSE); - rccResetTIM4(); - nvicEnableVector(STM32_TIM4_NUMBER, - CORTEX_PRIORITY_MASK(STM32_GPT_TIM4_IRQ_PRIORITY)); - gptp->clock = STM32_TIMCLK1; - } -#endif - -#if STM32_GPT_USE_TIM5 - if (&GPTD5 == gptp) { - rccEnableTIM5(FALSE); - rccResetTIM5(); - nvicEnableVector(STM32_TIM5_NUMBER, - CORTEX_PRIORITY_MASK(STM32_GPT_TIM5_IRQ_PRIORITY)); - gptp->clock = STM32_TIMCLK1; - } -#endif - -#if STM32_GPT_USE_TIM6 - if (&GPTD6 == gptp) { - rccEnableTIM6(FALSE); - rccResetTIM6(); - nvicEnableVector(STM32_TIM6_NUMBER, - CORTEX_PRIORITY_MASK(STM32_GPT_TIM6_IRQ_PRIORITY)); - gptp->clock = STM32_TIMCLK1; - } -#endif - -#if STM32_GPT_USE_TIM7 - if (&GPTD7 == gptp) { - rccEnableTIM7(FALSE); - rccResetTIM7(); - nvicEnableVector(STM32_TIM7_NUMBER, - CORTEX_PRIORITY_MASK(STM32_GPT_TIM7_IRQ_PRIORITY)); - gptp->clock = STM32_TIMCLK1; - } -#endif - -#if STM32_GPT_USE_TIM8 - if (&GPTD8 == gptp) { - rccEnableTIM8(FALSE); - rccResetTIM8(); - nvicEnableVector(STM32_TIM8_UP_NUMBER, - CORTEX_PRIORITY_MASK(STM32_GPT_TIM8_IRQ_PRIORITY)); -#if defined(STM32_TIM8CLK) - gptp->clock = STM32_TIM8CLK; -#else - gptp->clock = STM32_TIMCLK2; -#endif - } -#endif - -#if STM32_GPT_USE_TIM9 - if (&GPTD9 == gptp) { - rccEnableTIM9(FALSE); - rccResetTIM9(); - nvicEnableVector(STM32_TIM9_NUMBER, - CORTEX_PRIORITY_MASK(STM32_GPT_TIM9_IRQ_PRIORITY)); - gptp->clock = STM32_TIMCLK2; - } -#endif - -#if STM32_GPT_USE_TIM11 - if (&GPTD11 == gptp) { - rccEnableTIM11(FALSE); - rccResetTIM11(); - nvicEnableVector(STM32_TIM11_NUMBER, - CORTEX_PRIORITY_MASK(STM32_GPT_TIM11_IRQ_PRIORITY)); - gptp->clock = STM32_TIMCLK2; - } -#endif - -#if STM32_GPT_USE_TIM12 - if (&GPTD12 == gptp) { - rccEnableTIM12(FALSE); - rccResetTIM12(); - nvicEnableVector(STM32_TIM12_NUMBER, - CORTEX_PRIORITY_MASK(STM32_GPT_TIM12_IRQ_PRIORITY)); - gptp->clock = STM32_TIMCLK1; - } -#endif - -#if STM32_GPT_USE_TIM14 - if (&GPTD14 == gptp) { - rccEnableTIM14(FALSE); - rccResetTIM14(); - nvicEnableVector(STM32_TIM14_NUMBER, - CORTEX_PRIORITY_MASK(STM32_GPT_TIM14_IRQ_PRIORITY)); - gptp->clock = STM32_TIMCLK1; - } -#endif - } - - /* Prescaler value calculation.*/ - psc = (uint16_t)((gptp->clock / gptp->config->frequency) - 1); - chDbgAssert(((uint32_t)(psc + 1) * gptp->config->frequency) == gptp->clock, - "gpt_lld_start(), #1", "invalid frequency"); - - /* Timer configuration.*/ - gptp->tim->CR1 = 0; /* Initially stopped. */ - gptp->tim->CR2 = STM32_TIM_CR2_CCDS; /* DMA on UE (if any). */ - gptp->tim->PSC = psc; /* Prescaler value. */ - gptp->tim->DIER = gptp->config->dier & /* DMA-related DIER bits. */ - STM32_TIM_DIER_IRQ_MASK; - gptp->tim->SR = 0; /* Clear pending IRQs. */ -} - -/** - * @brief Deactivates the GPT peripheral. - * - * @param[in] gptp pointer to the @p GPTDriver object - * - * @notapi - */ -void gpt_lld_stop(GPTDriver *gptp) { - - if (gptp->state == GPT_READY) { - gptp->tim->CR1 = 0; /* Timer disabled. */ - gptp->tim->DIER = 0; /* All IRQs disabled. */ - gptp->tim->SR = 0; /* Clear pending IRQs. */ - -#if STM32_GPT_USE_TIM1 - if (&GPTD1 == gptp) { - nvicDisableVector(STM32_TIM1_UP_NUMBER); - rccDisableTIM1(FALSE); - } -#endif -#if STM32_GPT_USE_TIM2 - if (&GPTD2 == gptp) { - nvicDisableVector(STM32_TIM2_NUMBER); - rccDisableTIM2(FALSE); - } -#endif -#if STM32_GPT_USE_TIM3 - if (&GPTD3 == gptp) { - nvicDisableVector(STM32_TIM3_NUMBER); - rccDisableTIM3(FALSE); - } -#endif -#if STM32_GPT_USE_TIM4 - if (&GPTD4 == gptp) { - nvicDisableVector(STM32_TIM4_NUMBER); - rccDisableTIM4(FALSE); - } -#endif -#if STM32_GPT_USE_TIM5 - if (&GPTD5 == gptp) { - nvicDisableVector(STM32_TIM5_NUMBER); - rccDisableTIM5(FALSE); - } -#endif -#if STM32_GPT_USE_TIM6 - if (&GPTD6 == gptp) { - nvicDisableVector(STM32_TIM6_NUMBER); - rccDisableTIM6(FALSE); - } -#endif -#if STM32_GPT_USE_TIM7 - if (&GPTD7 == gptp) { - nvicDisableVector(STM32_TIM7_NUMBER); - rccDisableTIM7(FALSE); - } -#endif -#if STM32_GPT_USE_TIM8 - if (&GPTD8 == gptp) { - nvicDisableVector(STM32_TIM8_UP_NUMBER); - rccDisableTIM8(FALSE); - } -#endif -#if STM32_GPT_USE_TIM9 - if (&GPTD9 == gptp) { - nvicDisableVector(STM32_TIM9_NUMBER); - rccDisableTIM9(FALSE); - } -#endif -#if STM32_GPT_USE_TIM11 - if (&GPTD11 == gptp) { - nvicDisableVector(STM32_TIM11_NUMBER); - rccDisableTIM11(FALSE); - } -#endif -#if STM32_GPT_USE_TIM12 - if (&GPTD12 == gptp) { - nvicDisableVector(STM32_TIM12_NUMBER); - rccDisableTIM12(FALSE); - } -#endif -#if STM32_GPT_USE_TIM14 - if (&GPTD14 == gptp) { - nvicDisableVector(STM32_TIM14_NUMBER); - rccDisableTIM14(FALSE); - } -#endif - } -} - -/** - * @brief Starts the timer in continuous mode. - * - * @param[in] gptp pointer to the @p GPTDriver object - * @param[in] interval period in ticks - * - * @notapi - */ -void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) { - - gptp->tim->ARR = (uint32_t)(interval - 1); /* Time constant. */ - gptp->tim->EGR = STM32_TIM_EGR_UG; /* Update event. */ - gptp->tim->CNT = 0; /* Reset counter. */ - - /* NOTE: After generating the UG event it takes several clock cycles before - SR bit 0 goes to 1. This is because the clearing of CNT has been inserted - before the clearing of SR, to give it some time.*/ - gptp->tim->SR = 0; /* Clear pending IRQs. */ - gptp->tim->DIER |= STM32_TIM_DIER_UIE; /* Update Event IRQ enabled.*/ - gptp->tim->CR1 = STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN; -} - -/** - * @brief Stops the timer. - * - * @param[in] gptp pointer to the @p GPTDriver object - * - * @notapi - */ -void gpt_lld_stop_timer(GPTDriver *gptp) { - - gptp->tim->CR1 = 0; /* Initially stopped. */ - gptp->tim->SR = 0; /* Clear pending IRQs. */ - - /* All interrupts disabled.*/ - gptp->tim->DIER &= ~STM32_TIM_DIER_IRQ_MASK; -} - -/** - * @brief Starts the timer in one shot mode and waits for completion. - * @details This function specifically polls the timer waiting for completion - * in order to not have extra delays caused by interrupt servicing, - * this function is only recommended for short delays. - * - * @param[in] gptp pointer to the @p GPTDriver object - * @param[in] interval time interval in ticks - * - * @notapi - */ -void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) { - - gptp->tim->ARR = (uint32_t)(interval - 1); /* Time constant. */ - gptp->tim->EGR = STM32_TIM_EGR_UG; /* Update event. */ - gptp->tim->SR = 0; /* Clear pending IRQs. */ - gptp->tim->CR1 = STM32_TIM_CR1_OPM | STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN; - while (!(gptp->tim->SR & STM32_TIM_SR_UIF)) - ; -} - -#endif /* HAL_USE_GPT */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/TIMv1/gpt_lld.h b/firmware/chibios/os/hal/platforms/STM32/TIMv1/gpt_lld.h deleted file mode 100644 index f303a1bd18..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/TIMv1/gpt_lld.h +++ /dev/null @@ -1,512 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/gpt_lld.h - * @brief STM32 GPT subsystem low level driver header. - * - * @addtogroup GPT - * @{ - */ - -#ifndef _GPT_LLD_H_ -#define _GPT_LLD_H_ - -#include "stm32_tim.h" - -#if HAL_USE_GPT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief GPTD1 driver enable switch. - * @details If set to @p TRUE the support for GPTD1 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_GPT_USE_TIM1) || defined(__DOXYGEN__) -#define STM32_GPT_USE_TIM1 FALSE -#endif - -/** - * @brief GPTD2 driver enable switch. - * @details If set to @p TRUE the support for GPTD2 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_GPT_USE_TIM2) || defined(__DOXYGEN__) -#define STM32_GPT_USE_TIM2 FALSE -#endif - -/** - * @brief GPTD3 driver enable switch. - * @details If set to @p TRUE the support for GPTD3 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_GPT_USE_TIM3) || defined(__DOXYGEN__) -#define STM32_GPT_USE_TIM3 FALSE -#endif - -/** - * @brief GPTD4 driver enable switch. - * @details If set to @p TRUE the support for GPTD4 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_GPT_USE_TIM4) || defined(__DOXYGEN__) -#define STM32_GPT_USE_TIM4 FALSE -#endif - -/** - * @brief GPTD5 driver enable switch. - * @details If set to @p TRUE the support for GPTD5 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_GPT_USE_TIM5) || defined(__DOXYGEN__) -#define STM32_GPT_USE_TIM5 FALSE -#endif - -/** - * @brief GPTD6 driver enable switch. - * @details If set to @p TRUE the support for GPTD6 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_GPT_USE_TIM6) || defined(__DOXYGEN__) -#define STM32_GPT_USE_TIM6 FALSE -#endif - -/** - * @brief GPTD7 driver enable switch. - * @details If set to @p TRUE the support for GPTD7 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_GPT_USE_TIM7) || defined(__DOXYGEN__) -#define STM32_GPT_USE_TIM7 FALSE -#endif - -/** - * @brief GPTD8 driver enable switch. - * @details If set to @p TRUE the support for GPTD8 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_GPT_USE_TIM8) || defined(__DOXYGEN__) -#define STM32_GPT_USE_TIM8 FALSE -#endif - -/** - * @brief GPTD9 driver enable switch. - * @details If set to @p TRUE the support for GPTD9 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_GPT_USE_TIM9) || defined(__DOXYGEN__) -#define STM32_GPT_USE_TIM9 FALSE -#endif - -/** - * @brief GPTD11 driver enable switch. - * @details If set to @p TRUE the support for GPTD11 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_GPT_USE_TIM11) || defined(__DOXYGEN__) -#define STM32_GPT_USE_TIM11 FALSE -#endif - -/** - * @brief GPTD12 driver enable switch. - * @details If set to @p TRUE the support for GPTD12 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_GPT_USE_TIM12) || defined(__DOXYGEN__) -#define STM32_GPT_USE_TIM12 FALSE -#endif - -/** - * @brief GPTD14 driver enable switch. - * @details If set to @p TRUE the support for GPTD14 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_GPT_USE_TIM14) || defined(__DOXYGEN__) -#define STM32_GPT_USE_TIM14 FALSE -#endif - -/** - * @brief GPTD1 interrupt priority level setting. - */ -#if !defined(STM32_GPT_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_GPT_TIM1_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD2 interrupt priority level setting. - */ -#if !defined(STM32_GPT_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_GPT_TIM2_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD3 interrupt priority level setting. - */ -#if !defined(STM32_GPT_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_GPT_TIM3_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD4 interrupt priority level setting. - */ -#if !defined(STM32_GPT_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_GPT_TIM4_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD5 interrupt priority level setting. - */ -#if !defined(STM32_GPT_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_GPT_TIM5_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD6 interrupt priority level setting. - */ -#if !defined(STM32_GPT_TIM6_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_GPT_TIM6_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD7 interrupt priority level setting. - */ -#if !defined(STM32_GPT_TIM7_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_GPT_TIM7_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD8 interrupt priority level setting. - */ -#if !defined(STM32_GPT_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_GPT_TIM8_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD9 interrupt priority level setting. - */ -#if !defined(STM32_GPT_TIM9_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_GPT_TIM9_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD11 interrupt priority level setting. - */ -#if !defined(STM32_GPT_TIM11_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_GPT_TIM11_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD12 interrupt priority level setting. - */ -#if !defined(STM32_GPT_TIM12_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_GPT_TIM12_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD14 interrupt priority level setting. - */ -#if !defined(STM32_GPT_TIM14_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_GPT_TIM14_IRQ_PRIORITY 7 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_GPT_USE_TIM1 && !STM32_HAS_TIM1 -#error "TIM1 not present in the selected device" -#endif - -#if STM32_GPT_USE_TIM2 && !STM32_HAS_TIM2 -#error "TIM2 not present in the selected device" -#endif - -#if STM32_GPT_USE_TIM3 && !STM32_HAS_TIM3 -#error "TIM3 not present in the selected device" -#endif - -#if STM32_GPT_USE_TIM4 && !STM32_HAS_TIM4 -#error "TIM4 not present in the selected device" -#endif - -#if STM32_GPT_USE_TIM5 && !STM32_HAS_TIM5 -#error "TIM5 not present in the selected device" -#endif - -#if STM32_GPT_USE_TIM6 && !STM32_HAS_TIM6 -#error "TIM6 not present in the selected device" -#endif - -#if STM32_GPT_USE_TIM7 && !STM32_HAS_TIM7 -#error "TIM7 not present in the selected device" -#endif - -#if STM32_GPT_USE_TIM8 && !STM32_HAS_TIM8 -#error "TIM8 not present in the selected device" -#endif - -#if STM32_GPT_USE_TIM9 && !STM32_HAS_TIM9 -#error "TIM9 not present in the selected device" -#endif - -#if STM32_GPT_USE_TIM11 && !STM32_HAS_TIM11 -#error "TIM11 not present in the selected device" -#endif - -#if STM32_GPT_USE_TIM12 && !STM32_HAS_TIM12 -#error "TIM12 not present in the selected device" -#endif - -#if STM32_GPT_USE_TIM14 && !STM32_HAS_TIM14 -#error "TIM14 not present in the selected device" -#endif - -#if !STM32_GPT_USE_TIM1 && !STM32_GPT_USE_TIM2 && \ - !STM32_GPT_USE_TIM3 && !STM32_GPT_USE_TIM4 && \ - !STM32_GPT_USE_TIM5 && !STM32_GPT_USE_TIM6 && \ - !STM32_GPT_USE_TIM7 && !STM32_GPT_USE_TIM8 && \ - !STM32_GPT_USE_TIM9 && !STM32_GPT_USE_TIM11 && \ - !STM32_GPT_USE_TIM12 && !STM32_GPT_USE_TIM14 -#error "GPT driver activated but no TIM peripheral assigned" -#endif - -#if STM32_GPT_USE_TIM1 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM1" -#endif - -#if STM32_GPT_USE_TIM2 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM2" -#endif - -#if STM32_GPT_USE_TIM3 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM3" -#endif - -#if STM32_GPT_USE_TIM4 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM4_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM4" -#endif - -#if STM32_GPT_USE_TIM5 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM5_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM5" -#endif - -#if STM32_GPT_USE_TIM6 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM6_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM6" -#endif - -#if STM32_GPT_USE_TIM7 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM7_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM7" -#endif - -#if STM32_GPT_USE_TIM8 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM8_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM8" -#endif - -#if STM32_GPT_USE_TIM9 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM9_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM9" -#endif - -#if STM32_GPT_USE_TIM11 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM11_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM11" -#endif - -#if STM32_GPT_USE_TIM12 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM12_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM12" -#endif - -#if STM32_GPT_USE_TIM14 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM14_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM14" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief GPT frequency type. - */ -typedef uint32_t gptfreq_t; - -/** - * @brief GPT counter type. - */ -typedef uint32_t gptcnt_t; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief Timer clock in Hz. - * @note The low level can use assertions in order to catch invalid - * frequency specifications. - */ - gptfreq_t frequency; - /** - * @brief Timer callback pointer. - * @note This callback is invoked on GPT counter events. - */ - gptcallback_t callback; - /* End of the mandatory fields.*/ - /** - * @brief TIM DIER register initialization data. - * @note The value of this field should normally be equal to zero. - * @note Only the DMA-related bits can be specified in this field. - */ - uint32_t dier; -} GPTConfig; - -/** - * @brief Structure representing a GPT driver. - */ -struct GPTDriver { - /** - * @brief Driver state. - */ - gptstate_t state; - /** - * @brief Current configuration data. - */ - const GPTConfig *config; -#if defined(GPT_DRIVER_EXT_FIELDS) - GPT_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Timer base clock. - */ - uint32_t clock; - /** - * @brief Pointer to the TIMx registers block. - */ - stm32_tim_t *tim; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Changes the interval of GPT peripheral. - * @details This function changes the interval of a running GPT unit. - * @pre The GPT unit must have been activated using @p gptStart(). - * @pre The GPT unit must have been running in continuous mode using - * @p gptStartContinuous(). - * @post The GPT unit interval is changed to the new value. - * @note The function has effect at the next cycle start. - * - * @param[in] gptp pointer to a @p GPTDriver object - * @param[in] interval new cycle time in timer ticks - * @notapi - */ -#define gpt_lld_change_interval(gptp, interval) \ - ((gptp)->tim->ARR = (uint32_t)((interval) - 1)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_GPT_USE_TIM1 && !defined(__DOXYGEN__) -extern GPTDriver GPTD1; -#endif - -#if STM32_GPT_USE_TIM2 && !defined(__DOXYGEN__) -extern GPTDriver GPTD2; -#endif - -#if STM32_GPT_USE_TIM3 && !defined(__DOXYGEN__) -extern GPTDriver GPTD3; -#endif - -#if STM32_GPT_USE_TIM4 && !defined(__DOXYGEN__) -extern GPTDriver GPTD4; -#endif - -#if STM32_GPT_USE_TIM5 && !defined(__DOXYGEN__) -extern GPTDriver GPTD5; -#endif - -#if STM32_GPT_USE_TIM6 && !defined(__DOXYGEN__) -extern GPTDriver GPTD6; -#endif - -#if STM32_GPT_USE_TIM7 && !defined(__DOXYGEN__) -extern GPTDriver GPTD7; -#endif - -#if STM32_GPT_USE_TIM8 && !defined(__DOXYGEN__) -extern GPTDriver GPTD8; -#endif - -#if STM32_GPT_USE_TIM9 && !defined(__DOXYGEN__) -extern GPTDriver GPTD9; -#endif - -#if STM32_GPT_USE_TIM11 && !defined(__DOXYGEN__) -extern GPTDriver GPTD11; -#endif - -#if STM32_GPT_USE_TIM12 && !defined(__DOXYGEN__) -extern GPTDriver GPTD12; -#endif - -#if STM32_GPT_USE_TIM14 && !defined(__DOXYGEN__) -extern GPTDriver GPTD14; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void gpt_lld_init(void); - void gpt_lld_start(GPTDriver *gptp); - void gpt_lld_stop(GPTDriver *gptp); - void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period); - void gpt_lld_stop_timer(GPTDriver *gptp); - void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_GPT */ - -#endif /* _GPT_LLD_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/TIMv1/icu_lld.c b/firmware/chibios/os/hal/platforms/STM32/TIMv1/icu_lld.c deleted file mode 100644 index 2ceeaca363..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/TIMv1/icu_lld.c +++ /dev/null @@ -1,653 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Concepts and parts of this file have been contributed by Fabio Utzig and - Xo Wang. - */ - -/** - * @file STM32/icu_lld.c - * @brief STM32 ICU subsystem low level driver header. - * - * @addtogroup ICU - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_ICU || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief ICUD1 driver identifier. - * @note The driver ICUD1 allocates the complex timer TIM1 when enabled. - */ -#if STM32_ICU_USE_TIM1 || defined(__DOXYGEN__) -ICUDriver ICUD1; -#endif - -/** - * @brief ICUD2 driver identifier. - * @note The driver ICUD1 allocates the timer TIM2 when enabled. - */ -#if STM32_ICU_USE_TIM2 || defined(__DOXYGEN__) -ICUDriver ICUD2; -#endif - -/** - * @brief ICUD3 driver identifier. - * @note The driver ICUD1 allocates the timer TIM3 when enabled. - */ -#if STM32_ICU_USE_TIM3 || defined(__DOXYGEN__) -ICUDriver ICUD3; -#endif - -/** - * @brief ICUD4 driver identifier. - * @note The driver ICUD4 allocates the timer TIM4 when enabled. - */ -#if STM32_ICU_USE_TIM4 || defined(__DOXYGEN__) -ICUDriver ICUD4; -#endif - -/** - * @brief ICUD5 driver identifier. - * @note The driver ICUD5 allocates the timer TIM5 when enabled. - */ -#if STM32_ICU_USE_TIM5 || defined(__DOXYGEN__) -ICUDriver ICUD5; -#endif - -/** - * @brief ICUD8 driver identifier. - * @note The driver ICUD8 allocates the timer TIM8 when enabled. - */ -#if STM32_ICU_USE_TIM8 || defined(__DOXYGEN__) -ICUDriver ICUD8; -#endif - -/** - * @brief ICUD9 driver identifier. - * @note The driver ICUD9 allocates the timer TIM9 when enabled. - */ -#if STM32_ICU_USE_TIM9 || defined(__DOXYGEN__) -ICUDriver ICUD9; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Shared IRQ handler. - * - * @param[in] icup pointer to the @p ICUDriver object - */ -static void icu_lld_serve_interrupt(ICUDriver *icup) { - uint16_t sr; - - sr = icup->tim->SR; - sr &= icup->tim->DIER & STM32_TIM_DIER_IRQ_MASK; - icup->tim->SR = ~sr; - if (icup->config->channel == ICU_CHANNEL_1) { - if ((sr & STM32_TIM_SR_CC1IF) != 0) - _icu_isr_invoke_period_cb(icup); - if ((sr & STM32_TIM_SR_CC2IF) != 0) - _icu_isr_invoke_width_cb(icup); - } else { - if ((sr & STM32_TIM_SR_CC1IF) != 0) - _icu_isr_invoke_width_cb(icup); - if ((sr & STM32_TIM_SR_CC2IF) != 0) - _icu_isr_invoke_period_cb(icup); - } - if ((sr & STM32_TIM_SR_UIF) != 0) - _icu_isr_invoke_overflow_cb(icup); -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if STM32_ICU_USE_TIM1 -#if !defined(STM32_TIM1_UP_HANDLER) -#error "STM32_TIM1_UP_HANDLER not defined" -#endif -/** - * @brief TIM1 compare interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) { - - CH_IRQ_PROLOGUE(); - - icu_lld_serve_interrupt(&ICUD1); - - CH_IRQ_EPILOGUE(); -} - -#if !defined(STM32_TIM1_CC_HANDLER) -#error "STM32_TIM1_CC_HANDLER not defined" -#endif -/** - * @brief TIM1 compare interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM1_CC_HANDLER) { - - CH_IRQ_PROLOGUE(); - - icu_lld_serve_interrupt(&ICUD1); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_ICU_USE_TIM1 */ - -#if STM32_ICU_USE_TIM2 -#if !defined(STM32_TIM2_HANDLER) -#error "STM32_TIM2_HANDLER not defined" -#endif -/** - * @brief TIM2 interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM2_HANDLER) { - - CH_IRQ_PROLOGUE(); - - icu_lld_serve_interrupt(&ICUD2); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_ICU_USE_TIM2 */ - -#if STM32_ICU_USE_TIM3 -#if !defined(STM32_TIM3_HANDLER) -#error "STM32_TIM3_HANDLER not defined" -#endif -/** - * @brief TIM3 interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM3_HANDLER) { - - CH_IRQ_PROLOGUE(); - - icu_lld_serve_interrupt(&ICUD3); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_ICU_USE_TIM3 */ - -#if STM32_ICU_USE_TIM4 -#if !defined(STM32_TIM4_HANDLER) -#error "STM32_TIM4_HANDLER not defined" -#endif -/** - * @brief TIM4 interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM4_HANDLER) { - - CH_IRQ_PROLOGUE(); - - icu_lld_serve_interrupt(&ICUD4); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_ICU_USE_TIM4 */ - -#if STM32_ICU_USE_TIM5 -#if !defined(STM32_TIM5_HANDLER) -#error "STM32_TIM5_HANDLER not defined" -#endif -/** - * @brief TIM5 interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM5_HANDLER) { - - CH_IRQ_PROLOGUE(); - - icu_lld_serve_interrupt(&ICUD5); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_ICU_USE_TIM5 */ - -#if STM32_ICU_USE_TIM8 -#if !defined(STM32_TIM8_UP_HANDLER) -#error "STM32_TIM8_UP_HANDLER not defined" -#endif -/** - * @brief TIM8 compare interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) { - - CH_IRQ_PROLOGUE(); - - icu_lld_serve_interrupt(&ICUD8); - - CH_IRQ_EPILOGUE(); -} - -#if !defined(STM32_TIM8_CC_HANDLER) -#error "STM32_TIM8_CC_HANDLER not defined" -#endif -/** - * @brief TIM8 compare interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM8_CC_HANDLER) { - - CH_IRQ_PROLOGUE(); - - icu_lld_serve_interrupt(&ICUD8); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_ICU_USE_TIM8 */ - -#if STM32_ICU_USE_TIM9 -#if !defined(STM32_TIM9_HANDLER) -#error "STM32_TIM9_HANDLER not defined" -#endif -/** - * @brief TIM9 interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM9_HANDLER) { - - CH_IRQ_PROLOGUE(); - - icu_lld_serve_interrupt(&ICUD9); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_ICU_USE_TIM9 */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level ICU driver initialization. - * - * @notapi - */ -void icu_lld_init(void) { - -#if STM32_ICU_USE_TIM1 - /* Driver initialization.*/ - icuObjectInit(&ICUD1); - ICUD1.tim = STM32_TIM1; -#endif - -#if STM32_ICU_USE_TIM2 - /* Driver initialization.*/ - icuObjectInit(&ICUD2); - ICUD2.tim = STM32_TIM2; -#endif - -#if STM32_ICU_USE_TIM3 - /* Driver initialization.*/ - icuObjectInit(&ICUD3); - ICUD3.tim = STM32_TIM3; -#endif - -#if STM32_ICU_USE_TIM4 - /* Driver initialization.*/ - icuObjectInit(&ICUD4); - ICUD4.tim = STM32_TIM4; -#endif - -#if STM32_ICU_USE_TIM5 - /* Driver initialization.*/ - icuObjectInit(&ICUD5); - ICUD5.tim = STM32_TIM5; -#endif - -#if STM32_ICU_USE_TIM8 - /* Driver initialization.*/ - icuObjectInit(&ICUD8); - ICUD8.tim = STM32_TIM8; -#endif - -#if STM32_ICU_USE_TIM9 - /* Driver initialization.*/ - icuObjectInit(&ICUD9); - ICUD9.tim = STM32_TIM9; -#endif -} - -/** - * @brief Configures and activates the ICU peripheral. - * - * @param[in] icup pointer to the @p ICUDriver object - * - * @notapi - */ -void icu_lld_start(ICUDriver *icup) { - uint32_t psc; - - chDbgAssert((icup->config->channel == ICU_CHANNEL_1) || - (icup->config->channel == ICU_CHANNEL_2), - "icu_lld_start(), #1", "invalid input"); - - if (icup->state == ICU_STOP) { - /* Clock activation and timer reset.*/ -#if STM32_ICU_USE_TIM1 - if (&ICUD1 == icup) { - rccEnableTIM1(FALSE); - rccResetTIM1(); - nvicEnableVector(STM32_TIM1_UP_NUMBER, - CORTEX_PRIORITY_MASK(STM32_ICU_TIM1_IRQ_PRIORITY)); - nvicEnableVector(STM32_TIM1_CC_NUMBER, - CORTEX_PRIORITY_MASK(STM32_ICU_TIM1_IRQ_PRIORITY)); -#if defined(STM32_TIM1CLK) - icup->clock = STM32_TIM1CLK; -#else - icup->clock = STM32_TIMCLK2; -#endif - } -#endif -#if STM32_ICU_USE_TIM2 - if (&ICUD2 == icup) { - rccEnableTIM2(FALSE); - rccResetTIM2(); - nvicEnableVector(STM32_TIM2_NUMBER, - CORTEX_PRIORITY_MASK(STM32_ICU_TIM2_IRQ_PRIORITY)); - icup->clock = STM32_TIMCLK1; - } -#endif -#if STM32_ICU_USE_TIM3 - if (&ICUD3 == icup) { - rccEnableTIM3(FALSE); - rccResetTIM3(); - nvicEnableVector(STM32_TIM3_NUMBER, - CORTEX_PRIORITY_MASK(STM32_ICU_TIM3_IRQ_PRIORITY)); - icup->clock = STM32_TIMCLK1; - } -#endif -#if STM32_ICU_USE_TIM4 - if (&ICUD4 == icup) { - rccEnableTIM4(FALSE); - rccResetTIM4(); - nvicEnableVector(STM32_TIM4_NUMBER, - CORTEX_PRIORITY_MASK(STM32_ICU_TIM4_IRQ_PRIORITY)); - icup->clock = STM32_TIMCLK1; - } -#endif -#if STM32_ICU_USE_TIM5 - if (&ICUD5 == icup) { - rccEnableTIM5(FALSE); - rccResetTIM5(); - nvicEnableVector(STM32_TIM5_NUMBER, - CORTEX_PRIORITY_MASK(STM32_ICU_TIM5_IRQ_PRIORITY)); - icup->clock = STM32_TIMCLK1; - } -#endif -#if STM32_ICU_USE_TIM8 - if (&ICUD8 == icup) { - rccEnableTIM8(FALSE); - rccResetTIM8(); - nvicEnableVector(STM32_TIM8_UP_NUMBER, - CORTEX_PRIORITY_MASK(STM32_ICU_TIM8_IRQ_PRIORITY)); - nvicEnableVector(STM32_TIM8_CC_NUMBER, - CORTEX_PRIORITY_MASK(STM32_ICU_TIM8_IRQ_PRIORITY)); -#if defined(STM32_TIM8CLK) - icup->clock = STM32_TIM8CLK; -#else - icup->clock = STM32_TIMCLK2; -#endif - } -#endif -#if STM32_ICU_USE_TIM9 - if (&ICUD9 == icup) { - rccEnableTIM9(FALSE); - rccResetTIM9(); - nvicEnableVector(STM32_TIM9_NUMBER, - CORTEX_PRIORITY_MASK(STM32_ICU_TIM9_IRQ_PRIORITY)); - icup->clock = STM32_TIMCLK2; - } -#endif - } - else { - /* Driver re-configuration scenario, it must be stopped first.*/ - icup->tim->CR1 = 0; /* Timer disabled. */ - icup->tim->CCR[0] = 0; /* Comparator 1 disabled. */ - icup->tim->CCR[1] = 0; /* Comparator 2 disabled. */ - icup->tim->CNT = 0; /* Counter reset to zero. */ - } - - /* Timer configuration.*/ - icup->tim->SR = 0; /* Clear eventual pending IRQs. */ - icup->tim->DIER = icup->config->dier & /* DMA-related DIER settings. */ - ~STM32_TIM_DIER_IRQ_MASK; - psc = (icup->clock / icup->config->frequency) - 1; - chDbgAssert((psc <= 0xFFFF) && - ((psc + 1) * icup->config->frequency) == icup->clock, - "icu_lld_start(), #1", "invalid frequency"); - icup->tim->PSC = (uint16_t)psc; - icup->tim->ARR = 0xFFFF; - - if (icup->config->channel == ICU_CHANNEL_1) { - /* Selected input 1. - CCMR1_CC1S = 01 = CH1 Input on TI1. - CCMR1_CC2S = 10 = CH2 Input on TI1.*/ - icup->tim->CCMR1 = STM32_TIM_CCMR1_CC1S(1) | STM32_TIM_CCMR1_CC2S(2); - - /* SMCR_TS = 101, input is TI1FP1. - SMCR_SMS = 100, reset on rising edge.*/ - icup->tim->SMCR = STM32_TIM_SMCR_TS(5) | STM32_TIM_SMCR_SMS(4); - - /* The CCER settings depend on the selected trigger mode. - ICU_INPUT_ACTIVE_HIGH: Active on rising edge, idle on falling edge. - ICU_INPUT_ACTIVE_LOW: Active on falling edge, idle on rising edge.*/ - if (icup->config->mode == ICU_INPUT_ACTIVE_HIGH) - icup->tim->CCER = STM32_TIM_CCER_CC1E | - STM32_TIM_CCER_CC2E | STM32_TIM_CCER_CC2P; - else - icup->tim->CCER = STM32_TIM_CCER_CC1E | STM32_TIM_CCER_CC1P | - STM32_TIM_CCER_CC2E; - - /* Direct pointers to the capture registers in order to make reading - data faster from within callbacks.*/ - icup->wccrp = &icup->tim->CCR[1]; - icup->pccrp = &icup->tim->CCR[0]; - } else { - /* Selected input 2. - CCMR1_CC1S = 10 = CH1 Input on TI2. - CCMR1_CC2S = 01 = CH2 Input on TI2.*/ - icup->tim->CCMR1 = STM32_TIM_CCMR1_CC1S(2) | STM32_TIM_CCMR1_CC2S(1); - - /* SMCR_TS = 110, input is TI2FP2. - SMCR_SMS = 100, reset on rising edge.*/ - icup->tim->SMCR = STM32_TIM_SMCR_TS(6) | STM32_TIM_SMCR_SMS(4); - - /* The CCER settings depend on the selected trigger mode. - ICU_INPUT_ACTIVE_HIGH: Active on rising edge, idle on falling edge. - ICU_INPUT_ACTIVE_LOW: Active on falling edge, idle on rising edge.*/ - if (icup->config->mode == ICU_INPUT_ACTIVE_HIGH) - icup->tim->CCER = STM32_TIM_CCER_CC1E | STM32_TIM_CCER_CC1P | - STM32_TIM_CCER_CC2E; - else - icup->tim->CCER = STM32_TIM_CCER_CC1E | - STM32_TIM_CCER_CC2E | STM32_TIM_CCER_CC2P; - - /* Direct pointers to the capture registers in order to make reading - data faster from within callbacks.*/ - icup->wccrp = &icup->tim->CCR[0]; - icup->pccrp = &icup->tim->CCR[1]; - } -} - -/** - * @brief Deactivates the ICU peripheral. - * - * @param[in] icup pointer to the @p ICUDriver object - * - * @notapi - */ -void icu_lld_stop(ICUDriver *icup) { - - if (icup->state == ICU_READY) { - /* Clock deactivation.*/ - icup->tim->CR1 = 0; /* Timer disabled. */ - icup->tim->DIER = 0; /* All IRQs disabled. */ - icup->tim->SR = 0; /* Clear eventual pending IRQs. */ - -#if STM32_ICU_USE_TIM1 - if (&ICUD1 == icup) { - nvicDisableVector(STM32_TIM1_UP_NUMBER); - nvicDisableVector(STM32_TIM1_CC_NUMBER); - rccDisableTIM1(FALSE); - } -#endif -#if STM32_ICU_USE_TIM2 - if (&ICUD2 == icup) { - nvicDisableVector(STM32_TIM2_NUMBER); - rccDisableTIM2(FALSE); - } -#endif -#if STM32_ICU_USE_TIM3 - if (&ICUD3 == icup) { - nvicDisableVector(STM32_TIM3_NUMBER); - rccDisableTIM3(FALSE); - } -#endif -#if STM32_ICU_USE_TIM4 - if (&ICUD4 == icup) { - nvicDisableVector(STM32_TIM4_NUMBER); - rccDisableTIM4(FALSE); - } -#endif -#if STM32_ICU_USE_TIM5 - if (&ICUD5 == icup) { - nvicDisableVector(STM32_TIM5_NUMBER); - rccDisableTIM5(FALSE); - } -#endif -#if STM32_ICU_USE_TIM8 - if (&ICUD8 == icup) { - nvicDisableVector(STM32_TIM8_UP_NUMBER); - nvicDisableVector(STM32_TIM8_CC_NUMBER); - rccDisableTIM8(FALSE); - } -#endif -#if STM32_ICU_USE_TIM9 - if (&ICUD9 == icup) { - nvicDisableVector(STM32_TIM9_NUMBER); - rccDisableTIM9(FALSE); - } -#endif - } -} - -/** - * @brief Enables the input capture. - * - * @param[in] icup pointer to the @p ICUDriver object - * - * @notapi - */ -void icu_lld_enable(ICUDriver *icup) { - - icup->tim->EGR |= STM32_TIM_EGR_UG; - icup->tim->SR = 0; /* Clear pending IRQs (if any). */ - if (icup->config->channel == ICU_CHANNEL_1) { - if (icup->config->period_cb != NULL) - icup->tim->DIER |= STM32_TIM_DIER_CC1IE; - if (icup->config->width_cb != NULL) - icup->tim->DIER |= STM32_TIM_DIER_CC2IE; - } else { - if (icup->config->width_cb != NULL) - icup->tim->DIER |= STM32_TIM_DIER_CC1IE; - if (icup->config->period_cb != NULL) - icup->tim->DIER |= STM32_TIM_DIER_CC2IE; - } - if (icup->config->overflow_cb != NULL) - icup->tim->DIER |= STM32_TIM_DIER_UIE; - icup->tim->CR1 = STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN; -} - -/** - * @brief Disables the input capture. - * - * @param[in] icup pointer to the @p ICUDriver object - * - * @notapi - */ -void icu_lld_disable(ICUDriver *icup) { - - icup->tim->CR1 = 0; /* Initially stopped. */ - icup->tim->SR = 0; /* Clear pending IRQs (if any). */ - - /* All interrupts disabled.*/ - icup->tim->DIER &= ~STM32_TIM_DIER_IRQ_MASK; -} - -#endif /* HAL_USE_ICU */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/TIMv1/icu_lld.h b/firmware/chibios/os/hal/platforms/STM32/TIMv1/icu_lld.h deleted file mode 100644 index 6c48831541..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/TIMv1/icu_lld.h +++ /dev/null @@ -1,412 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/icu_lld.h - * @brief STM32 ICU subsystem low level driver header. - * - * @addtogroup ICU - * @{ - */ - -#ifndef _ICU_LLD_H_ -#define _ICU_LLD_H_ - -#include "stm32_tim.h" - -#if HAL_USE_ICU || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief ICUD1 driver enable switch. - * @details If set to @p TRUE the support for ICUD1 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_ICU_USE_TIM1) || defined(__DOXYGEN__) -#define STM32_ICU_USE_TIM1 FALSE -#endif - -/** - * @brief ICUD2 driver enable switch. - * @details If set to @p TRUE the support for ICUD2 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_ICU_USE_TIM2) || defined(__DOXYGEN__) -#define STM32_ICU_USE_TIM2 FALSE -#endif - -/** - * @brief ICUD3 driver enable switch. - * @details If set to @p TRUE the support for ICUD3 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_ICU_USE_TIM3) || defined(__DOXYGEN__) -#define STM32_ICU_USE_TIM3 FALSE -#endif - -/** - * @brief ICUD4 driver enable switch. - * @details If set to @p TRUE the support for ICUD4 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_ICU_USE_TIM4) || defined(__DOXYGEN__) -#define STM32_ICU_USE_TIM4 FALSE -#endif - -/** - * @brief ICUD5 driver enable switch. - * @details If set to @p TRUE the support for ICUD5 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_ICU_USE_TIM5) || defined(__DOXYGEN__) -#define STM32_ICU_USE_TIM5 FALSE -#endif - -/** - * @brief ICUD8 driver enable switch. - * @details If set to @p TRUE the support for ICUD8 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_ICU_USE_TIM8) || defined(__DOXYGEN__) -#define STM32_ICU_USE_TIM8 FALSE -#endif - -/** - * @brief ICUD9 driver enable switch. - * @details If set to @p TRUE the support for ICUD9 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_ICU_USE_TIM9) || defined(__DOXYGEN__) -#define STM32_ICU_USE_TIM9 FALSE -#endif - -/** - * @brief ICUD1 interrupt priority level setting. - */ -#if !defined(STM32_ICU_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ICU_TIM1_IRQ_PRIORITY 7 -#endif - -/** - * @brief ICUD2 interrupt priority level setting. - */ -#if !defined(STM32_ICU_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ICU_TIM2_IRQ_PRIORITY 7 -#endif - -/** - * @brief ICUD3 interrupt priority level setting. - */ -#if !defined(STM32_ICU_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ICU_TIM3_IRQ_PRIORITY 7 -#endif - -/** - * @brief ICUD4 interrupt priority level setting. - */ -#if !defined(STM32_ICU_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ICU_TIM4_IRQ_PRIORITY 7 -#endif - -/** - * @brief ICUD5 interrupt priority level setting. - */ -#if !defined(STM32_ICU_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ICU_TIM5_IRQ_PRIORITY 7 -#endif - -/** - * @brief ICUD8 interrupt priority level setting. - */ -#if !defined(STM32_ICU_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ICU_TIM8_IRQ_PRIORITY 7 -#endif - -/** - * @brief ICUD9 interrupt priority level setting. - */ -#if !defined(STM32_ICU_TIM9_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ICU_TIM9_IRQ_PRIORITY 7 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_ICU_USE_TIM1 && !STM32_HAS_TIM1 -#error "TIM1 not present in the selected device" -#endif - -#if STM32_ICU_USE_TIM2 && !STM32_HAS_TIM2 -#error "TIM2 not present in the selected device" -#endif - -#if STM32_ICU_USE_TIM3 && !STM32_HAS_TIM3 -#error "TIM3 not present in the selected device" -#endif - -#if STM32_ICU_USE_TIM4 && !STM32_HAS_TIM4 -#error "TIM4 not present in the selected device" -#endif - -#if STM32_ICU_USE_TIM5 && !STM32_HAS_TIM5 -#error "TIM5 not present in the selected device" -#endif - -#if STM32_ICU_USE_TIM8 && !STM32_HAS_TIM8 -#error "TIM8 not present in the selected device" -#endif - -#if STM32_ICU_USE_TIM9 && !STM32_HAS_TIM9 -#error "TIM9 not present in the selected device" -#endif - -#if !STM32_ICU_USE_TIM1 && !STM32_ICU_USE_TIM2 && \ - !STM32_ICU_USE_TIM3 && !STM32_ICU_USE_TIM4 && \ - !STM32_ICU_USE_TIM5 && !STM32_ICU_USE_TIM8 && \ - !STM32_ICU_USE_TIM9 -#error "ICU driver activated but no TIM peripheral assigned" -#endif - -#if STM32_ICU_USE_TIM1 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM1" -#endif - -#if STM32_ICU_USE_TIM2 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM2" -#endif - -#if STM32_ICU_USE_TIM3 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM3" -#endif - -#if STM32_ICU_USE_TIM4 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM4_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM4" -#endif - -#if STM32_ICU_USE_TIM5 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM5_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM5" -#endif - -#if STM32_ICU_USE_TIM8 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM8_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM8" -#endif - -#if STM32_ICU_USE_TIM9 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM9_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM9" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief ICU driver mode. - */ -typedef enum { - ICU_INPUT_ACTIVE_HIGH = 0, /**< Trigger on rising edge. */ - ICU_INPUT_ACTIVE_LOW = 1, /**< Trigger on falling edge. */ -} icumode_t; - -/** - * @brief ICU frequency type. - */ -typedef uint32_t icufreq_t; - -/** - * @brief ICU channel type. - */ -typedef enum { - ICU_CHANNEL_1 = 0, /**< Use TIMxCH1. */ - ICU_CHANNEL_2 = 1, /**< Use TIMxCH2. */ -} icuchannel_t; - -/** - * @brief ICU counter type. - */ -typedef uint16_t icucnt_t; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief Driver mode. - */ - icumode_t mode; - /** - * @brief Timer clock in Hz. - * @note The low level can use assertions in order to catch invalid - * frequency specifications. - */ - icufreq_t frequency; - /** - * @brief Callback for pulse width measurement. - */ - icucallback_t width_cb; - /** - * @brief Callback for cycle period measurement. - */ - icucallback_t period_cb; - /** - * @brief Callback for timer overflow. - */ - icucallback_t overflow_cb; - /* End of the mandatory fields.*/ - /** - * @brief Timer input channel to be used. - * @note Only inputs TIMx 1 and 2 are supported. - */ - icuchannel_t channel; - /** - * @brief TIM DIER register initialization data. - * @note The value of this field should normally be equal to zero. - * @note Only the DMA-related bits can be specified in this field. - */ - uint32_t dier; -} ICUConfig; - -/** - * @brief Structure representing an ICU driver. - */ -struct ICUDriver { - /** - * @brief Driver state. - */ - icustate_t state; - /** - * @brief Current configuration data. - */ - const ICUConfig *config; -#if defined(ICU_DRIVER_EXT_FIELDS) - ICU_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Timer base clock. - */ - uint32_t clock; - /** - * @brief Pointer to the TIMx registers block. - */ - stm32_tim_t *tim; - /** - * @brief CCR register used for width capture. - */ - volatile uint32_t *wccrp; - /** - * @brief CCR register used for period capture. - */ - volatile uint32_t *pccrp; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Returns the width of the latest pulse. - * @details The pulse width is defined as number of ticks between the start - * edge and the stop edge. - * - * @param[in] icup pointer to the @p ICUDriver object - * @return The number of ticks. - * - * @notapi - */ -#define icu_lld_get_width(icup) (*((icup)->wccrp) + 1) - -/** - * @brief Returns the width of the latest cycle. - * @details The cycle width is defined as number of ticks between a start - * edge and the next start edge. - * - * @param[in] icup pointer to the @p ICUDriver object - * @return The number of ticks. - * - * @notapi - */ -#define icu_lld_get_period(icup) (*((icup)->pccrp) + 1) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_ICU_USE_TIM1 && !defined(__DOXYGEN__) -extern ICUDriver ICUD1; -#endif - -#if STM32_ICU_USE_TIM2 && !defined(__DOXYGEN__) -extern ICUDriver ICUD2; -#endif - -#if STM32_ICU_USE_TIM3 && !defined(__DOXYGEN__) -extern ICUDriver ICUD3; -#endif - -#if STM32_ICU_USE_TIM4 && !defined(__DOXYGEN__) -extern ICUDriver ICUD4; -#endif - -#if STM32_ICU_USE_TIM5 && !defined(__DOXYGEN__) -extern ICUDriver ICUD5; -#endif - -#if STM32_ICU_USE_TIM8 && !defined(__DOXYGEN__) -extern ICUDriver ICUD8; -#endif - -#if STM32_ICU_USE_TIM9 && !defined(__DOXYGEN__) -extern ICUDriver ICUD9; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void icu_lld_init(void); - void icu_lld_start(ICUDriver *icup); - void icu_lld_stop(ICUDriver *icup); - void icu_lld_enable(ICUDriver *icup); - void icu_lld_disable(ICUDriver *icup); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_ICU */ - -#endif /* _ICU_LLD_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/TIMv1/pwm_lld.c b/firmware/chibios/os/hal/platforms/STM32/TIMv1/pwm_lld.c deleted file mode 100644 index 31faafe918..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/TIMv1/pwm_lld.c +++ /dev/null @@ -1,711 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/pwm_lld.c - * @brief STM32 PWM subsystem low level driver header. - * - * @addtogroup PWM - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_PWM || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief PWMD1 driver identifier. - * @note The driver PWMD1 allocates the complex timer TIM1 when enabled. - */ -#if STM32_PWM_USE_TIM1 || defined(__DOXYGEN__) -PWMDriver PWMD1; -#endif - -/** - * @brief PWMD2 driver identifier. - * @note The driver PWMD2 allocates the timer TIM2 when enabled. - */ -#if STM32_PWM_USE_TIM2 || defined(__DOXYGEN__) -PWMDriver PWMD2; -#endif - -/** - * @brief PWMD3 driver identifier. - * @note The driver PWMD3 allocates the timer TIM3 when enabled. - */ -#if STM32_PWM_USE_TIM3 || defined(__DOXYGEN__) -PWMDriver PWMD3; -#endif - -/** - * @brief PWMD4 driver identifier. - * @note The driver PWMD4 allocates the timer TIM4 when enabled. - */ -#if STM32_PWM_USE_TIM4 || defined(__DOXYGEN__) -PWMDriver PWMD4; -#endif - -/** - * @brief PWMD5 driver identifier. - * @note The driver PWMD5 allocates the timer TIM5 when enabled. - */ -#if STM32_PWM_USE_TIM5 || defined(__DOXYGEN__) -PWMDriver PWMD5; -#endif - -/** - * @brief PWMD8 driver identifier. - * @note The driver PWMD8 allocates the timer TIM8 when enabled. - */ -#if STM32_PWM_USE_TIM8 || defined(__DOXYGEN__) -PWMDriver PWMD8; -#endif - -/** - * @brief PWMD9 driver identifier. - * @note The driver PWMD9 allocates the timer TIM9 when enabled. - */ -#if STM32_PWM_USE_TIM9 || defined(__DOXYGEN__) -PWMDriver PWMD9; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -#if STM32_PWM_USE_TIM2 || STM32_PWM_USE_TIM3 || STM32_PWM_USE_TIM4 || \ - STM32_PWM_USE_TIM5 || STM32_PWM_USE_TIM9 || defined(__DOXYGEN__) -/** - * @brief Common TIM2...TIM5,TIM9 IRQ handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @param[in] pwmp pointer to a @p PWMDriver object - */ -static void pwm_lld_serve_interrupt(PWMDriver *pwmp) { - uint16_t sr; - - sr = pwmp->tim->SR; - sr &= pwmp->tim->DIER & STM32_TIM_DIER_IRQ_MASK; - pwmp->tim->SR = ~sr; - if ((sr & STM32_TIM_SR_CC1IF) != 0) - pwmp->config->channels[0].callback(pwmp); - if ((sr & STM32_TIM_SR_CC2IF) != 0) - pwmp->config->channels[1].callback(pwmp); - if ((sr & STM32_TIM_SR_CC3IF) != 0) - pwmp->config->channels[2].callback(pwmp); - if ((sr & STM32_TIM_SR_CC4IF) != 0) - pwmp->config->channels[3].callback(pwmp); - if ((sr & STM32_TIM_SR_UIF) != 0) - pwmp->config->callback(pwmp); -} -#endif /* STM32_PWM_USE_TIM2 || ... || STM32_PWM_USE_TIM5 */ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if STM32_PWM_USE_TIM1 -#if !defined(STM32_TIM1_UP_HANDLER) -#error "STM32_TIM1_UP_HANDLER not defined" -#endif -/** - * @brief TIM1 update interrupt handler. - * @note It is assumed that this interrupt is only activated if the callback - * pointer is not equal to @p NULL in order to not perform an extra - * check in a potentially critical interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) { - - CH_IRQ_PROLOGUE(); - - STM32_TIM1->SR = ~STM32_TIM_SR_UIF; - PWMD1.config->callback(&PWMD1); - - CH_IRQ_EPILOGUE(); -} - -#if !defined(STM32_TIM1_CC_HANDLER) -#error "STM32_TIM1_CC_HANDLER not defined" -#endif -/** - * @brief TIM1 compare interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM1_CC_HANDLER) { - uint16_t sr; - - CH_IRQ_PROLOGUE(); - - sr = STM32_TIM1->SR & STM32_TIM1->DIER & STM32_TIM_DIER_IRQ_MASK; - STM32_TIM1->SR = ~sr; - if ((sr & STM32_TIM_SR_CC1IF) != 0) - PWMD1.config->channels[0].callback(&PWMD1); - if ((sr & STM32_TIM_SR_CC2IF) != 0) - PWMD1.config->channels[1].callback(&PWMD1); - if ((sr & STM32_TIM_SR_CC3IF) != 0) - PWMD1.config->channels[2].callback(&PWMD1); - if ((sr & STM32_TIM_SR_CC4IF) != 0) - PWMD1.config->channels[3].callback(&PWMD1); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_PWM_USE_TIM1 */ - -#if STM32_PWM_USE_TIM2 -#if !defined(STM32_TIM2_HANDLER) -#error "STM32_TIM2_HANDLER not defined" -#endif -/** - * @brief TIM2 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM2_HANDLER) { - - CH_IRQ_PROLOGUE(); - - pwm_lld_serve_interrupt(&PWMD2); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_PWM_USE_TIM2 */ - -#if STM32_PWM_USE_TIM3 -#if !defined(STM32_TIM3_HANDLER) -#error "STM32_TIM3_HANDLER not defined" -#endif -/** - * @brief TIM3 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM3_HANDLER) { - - CH_IRQ_PROLOGUE(); - - pwm_lld_serve_interrupt(&PWMD3); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_PWM_USE_TIM3 */ - -#if STM32_PWM_USE_TIM4 -#if !defined(STM32_TIM4_HANDLER) -#error "STM32_TIM4_HANDLER not defined" -#endif -/** - * @brief TIM4 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM4_HANDLER) { - - CH_IRQ_PROLOGUE(); - - pwm_lld_serve_interrupt(&PWMD4); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_PWM_USE_TIM4 */ - -#if STM32_PWM_USE_TIM5 -#if !defined(STM32_TIM5_HANDLER) -#error "STM32_TIM5_HANDLER not defined" -#endif -/** - * @brief TIM5 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM5_HANDLER) { - - CH_IRQ_PROLOGUE(); - - pwm_lld_serve_interrupt(&PWMD5); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_PWM_USE_TIM5 */ - -#if STM32_PWM_USE_TIM8 -#if !defined(STM32_TIM8_UP_HANDLER) -#error "STM32_TIM8_UP_HANDLER not defined" -#endif -/** - * @brief TIM8 update interrupt handler. - * @note It is assumed that this interrupt is only activated if the callback - * pointer is not equal to @p NULL in order to not perform an extra - * check in a potentially critical interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) { - - CH_IRQ_PROLOGUE(); - - STM32_TIM8->SR = ~TIM_SR_UIF; - PWMD8.config->callback(&PWMD8); - - CH_IRQ_EPILOGUE(); -} - -#if !defined(STM32_TIM8_CC_HANDLER) -#error "STM32_TIM8_CC_HANDLER not defined" -#endif -/** - * @brief TIM8 compare interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM8_CC_HANDLER) { - uint16_t sr; - - CH_IRQ_PROLOGUE(); - - sr = STM32_TIM8->SR & STM32_TIM8->DIER & STM32_TIM_DIER_IRQ_MASK; - STM32_TIM8->SR = ~sr; - if ((sr & STM32_TIM_SR_CC1IF) != 0) - PWMD8.config->channels[0].callback(&PWMD8); - if ((sr & STM32_TIM_SR_CC2IF) != 0) - PWMD8.config->channels[1].callback(&PWMD8); - if ((sr & STM32_TIM_SR_CC3IF) != 0) - PWMD8.config->channels[2].callback(&PWMD8); - if ((sr & STM32_TIM_SR_CC4IF) != 0) - PWMD8.config->channels[3].callback(&PWMD8); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_PWM_USE_TIM8 */ - -#if STM32_PWM_USE_TIM9 -#if !defined(STM32_TIM9_HANDLER) -#error "STM32_TIM9_HANDLER not defined" -#endif -/** - * @brief TIM9 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM9_HANDLER) { - - CH_IRQ_PROLOGUE(); - - pwm_lld_serve_interrupt(&PWMD9); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_PWM_USE_TIM9 */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level PWM driver initialization. - * - * @notapi - */ -void pwm_lld_init(void) { - -#if STM32_PWM_USE_TIM1 - /* Driver initialization.*/ - pwmObjectInit(&PWMD1); - PWMD1.tim = STM32_TIM1; -#endif - -#if STM32_PWM_USE_TIM2 - /* Driver initialization.*/ - pwmObjectInit(&PWMD2); - PWMD2.tim = STM32_TIM2; -#endif - -#if STM32_PWM_USE_TIM3 - /* Driver initialization.*/ - pwmObjectInit(&PWMD3); - PWMD3.tim = STM32_TIM3; -#endif - -#if STM32_PWM_USE_TIM4 - /* Driver initialization.*/ - pwmObjectInit(&PWMD4); - PWMD4.tim = STM32_TIM4; -#endif - -#if STM32_PWM_USE_TIM5 - /* Driver initialization.*/ - pwmObjectInit(&PWMD5); - PWMD5.tim = STM32_TIM5; -#endif - -#if STM32_PWM_USE_TIM8 - /* Driver initialization.*/ - pwmObjectInit(&PWMD8); - PWMD8.tim = STM32_TIM8; -#endif - -#if STM32_PWM_USE_TIM9 - /* Driver initialization.*/ - pwmObjectInit(&PWMD9); - PWMD9.tim = STM32_TIM9; -#endif -} - -/** - * @brief Configures and activates the PWM peripheral. - * @note Starting a driver that is already in the @p PWM_READY state - * disables all the active channels. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * - * @notapi - */ -void pwm_lld_start(PWMDriver *pwmp) { - uint32_t psc; - uint32_t ccer; - - if (pwmp->state == PWM_STOP) { - /* Clock activation and timer reset.*/ -#if STM32_PWM_USE_TIM1 - if (&PWMD1 == pwmp) { - rccEnableTIM1(FALSE); - rccResetTIM1(); - nvicEnableVector(STM32_TIM1_UP_NUMBER, - CORTEX_PRIORITY_MASK(STM32_PWM_TIM1_IRQ_PRIORITY)); - nvicEnableVector(STM32_TIM1_CC_NUMBER, - CORTEX_PRIORITY_MASK(STM32_PWM_TIM1_IRQ_PRIORITY)); -#if defined(STM32_TIM1CLK) - pwmp->clock = STM32_TIM1CLK; -#else - pwmp->clock = STM32_TIMCLK2; -#endif - } -#endif -#if STM32_PWM_USE_TIM2 - if (&PWMD2 == pwmp) { - rccEnableTIM2(FALSE); - rccResetTIM2(); - nvicEnableVector(STM32_TIM2_NUMBER, - CORTEX_PRIORITY_MASK(STM32_PWM_TIM2_IRQ_PRIORITY)); - pwmp->clock = STM32_TIMCLK1; - } -#endif -#if STM32_PWM_USE_TIM3 - if (&PWMD3 == pwmp) { - rccEnableTIM3(FALSE); - rccResetTIM3(); - nvicEnableVector(STM32_TIM3_NUMBER, - CORTEX_PRIORITY_MASK(STM32_PWM_TIM3_IRQ_PRIORITY)); - pwmp->clock = STM32_TIMCLK1; - } -#endif -#if STM32_PWM_USE_TIM4 - if (&PWMD4 == pwmp) { - rccEnableTIM4(FALSE); - rccResetTIM4(); - nvicEnableVector(STM32_TIM4_NUMBER, - CORTEX_PRIORITY_MASK(STM32_PWM_TIM4_IRQ_PRIORITY)); - pwmp->clock = STM32_TIMCLK1; - } -#endif - -#if STM32_PWM_USE_TIM5 - if (&PWMD5 == pwmp) { - rccEnableTIM5(FALSE); - rccResetTIM5(); - nvicEnableVector(STM32_TIM5_NUMBER, - CORTEX_PRIORITY_MASK(STM32_PWM_TIM5_IRQ_PRIORITY)); - pwmp->clock = STM32_TIMCLK1; - } -#endif -#if STM32_PWM_USE_TIM8 - if (&PWMD8 == pwmp) { - rccEnableTIM8(FALSE); - rccResetTIM8(); - nvicEnableVector(STM32_TIM8_UP_NUMBER, - CORTEX_PRIORITY_MASK(STM32_PWM_TIM8_IRQ_PRIORITY)); - nvicEnableVector(STM32_TIM8_CC_NUMBER, - CORTEX_PRIORITY_MASK(STM32_PWM_TIM8_IRQ_PRIORITY)); -#if defined(STM32_TIM8CLK) - pwmp->clock = STM32_TIM8CLK; -#else - pwmp->clock = STM32_TIMCLK2; -#endif - } -#endif -#if STM32_PWM_USE_TIM9 - if (&PWMD9 == pwmp) { - rccEnableTIM9(FALSE); - rccResetTIM9(); - nvicEnableVector(STM32_TIM9_NUMBER, - CORTEX_PRIORITY_MASK(STM32_PWM_TIM9_IRQ_PRIORITY)); - pwmp->clock = STM32_TIMCLK2; - } -#endif - - /* All channels configured in PWM1 mode with preload enabled and will - stay that way until the driver is stopped.*/ - pwmp->tim->CCMR1 = STM32_TIM_CCMR1_OC1M(6) | STM32_TIM_CCMR1_OC1PE | - STM32_TIM_CCMR1_OC2M(6) | STM32_TIM_CCMR1_OC2PE; - pwmp->tim->CCMR2 = STM32_TIM_CCMR2_OC3M(6) | STM32_TIM_CCMR2_OC3PE | - STM32_TIM_CCMR2_OC4M(6) | STM32_TIM_CCMR2_OC4PE; - } - else { - /* Driver re-configuration scenario, it must be stopped first.*/ - pwmp->tim->CR1 = 0; /* Timer disabled. */ - pwmp->tim->CCR[0] = 0; /* Comparator 1 disabled. */ - pwmp->tim->CCR[1] = 0; /* Comparator 2 disabled. */ - pwmp->tim->CCR[2] = 0; /* Comparator 3 disabled. */ - pwmp->tim->CCR[3] = 0; /* Comparator 4 disabled. */ - pwmp->tim->CNT = 0; /* Counter reset to zero. */ - } - - /* Timer configuration.*/ - psc = (pwmp->clock / pwmp->config->frequency) - 1; - chDbgAssert((psc <= 0xFFFF) && - ((psc + 1) * pwmp->config->frequency) == pwmp->clock, - "pwm_lld_start(), #1", "invalid frequency"); - pwmp->tim->PSC = (uint16_t)psc; - pwmp->tim->ARR = (uint16_t)(pwmp->period - 1); - pwmp->tim->CR2 = pwmp->config->cr2; - - /* Output enables and polarities setup.*/ - ccer = 0; - switch (pwmp->config->channels[0].mode & PWM_OUTPUT_MASK) { - case PWM_OUTPUT_ACTIVE_LOW: - ccer |= STM32_TIM_CCER_CC1P; - case PWM_OUTPUT_ACTIVE_HIGH: - ccer |= STM32_TIM_CCER_CC1E; - default: - ; - } - switch (pwmp->config->channels[1].mode & PWM_OUTPUT_MASK) { - case PWM_OUTPUT_ACTIVE_LOW: - ccer |= STM32_TIM_CCER_CC2P; - case PWM_OUTPUT_ACTIVE_HIGH: - ccer |= STM32_TIM_CCER_CC2E; - default: - ; - } - switch (pwmp->config->channels[2].mode & PWM_OUTPUT_MASK) { - case PWM_OUTPUT_ACTIVE_LOW: - ccer |= STM32_TIM_CCER_CC3P; - case PWM_OUTPUT_ACTIVE_HIGH: - ccer |= STM32_TIM_CCER_CC3E; - default: - ; - } - switch (pwmp->config->channels[3].mode & PWM_OUTPUT_MASK) { - case PWM_OUTPUT_ACTIVE_LOW: - ccer |= STM32_TIM_CCER_CC4P; - case PWM_OUTPUT_ACTIVE_HIGH: - ccer |= STM32_TIM_CCER_CC4E; - default: - ; - } -#if STM32_PWM_USE_ADVANCED -#if STM32_PWM_USE_TIM1 && !STM32_PWM_USE_TIM8 - if (&PWMD1 == pwmp) { -#endif -#if !STM32_PWM_USE_TIM1 && STM32_PWM_USE_TIM8 - if (&PWMD8 == pwmp) { -#endif -#if STM32_PWM_USE_TIM1 && STM32_PWM_USE_TIM8 - if ((&PWMD1 == pwmp) || (&PWMD8 == pwmp)) { -#endif - switch (pwmp->config->channels[0].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) { - case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW: - ccer |= STM32_TIM_CCER_CC1NP; - case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH: - ccer |= STM32_TIM_CCER_CC1NE; - default: - ; - } - switch (pwmp->config->channels[1].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) { - case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW: - ccer |= STM32_TIM_CCER_CC2NP; - case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH: - ccer |= STM32_TIM_CCER_CC2NE; - default: - ; - } - switch (pwmp->config->channels[2].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) { - case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW: - ccer |= STM32_TIM_CCER_CC3NP; - case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH: - ccer |= STM32_TIM_CCER_CC3NE; - default: - ; - } - } -#endif /* STM32_PWM_USE_ADVANCED*/ - - pwmp->tim->CCER = ccer; - pwmp->tim->EGR = STM32_TIM_EGR_UG; /* Update event. */ - pwmp->tim->SR = 0; /* Clear pending IRQs. */ - pwmp->tim->DIER = (pwmp->config->callback == NULL ? 0 : STM32_TIM_DIER_UIE) | - (pwmp->config->dier & ~STM32_TIM_DIER_IRQ_MASK); -#if STM32_PWM_USE_TIM1 || STM32_PWM_USE_TIM8 -#if STM32_PWM_USE_ADVANCED - pwmp->tim->BDTR = pwmp->config->bdtr | STM32_TIM_BDTR_MOE; -#else - pwmp->tim->BDTR = STM32_TIM_BDTR_MOE; -#endif -#endif - /* Timer configured and started.*/ - pwmp->tim->CR1 = STM32_TIM_CR1_ARPE | STM32_TIM_CR1_URS | - STM32_TIM_CR1_CEN; -} - -/** - * @brief Deactivates the PWM peripheral. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * - * @notapi - */ -void pwm_lld_stop(PWMDriver *pwmp) { - - /* If in ready state then disables the PWM clock.*/ - if (pwmp->state == PWM_READY) { - pwmp->tim->CR1 = 0; /* Timer disabled. */ - pwmp->tim->DIER = 0; /* All IRQs disabled. */ - pwmp->tim->SR = 0; /* Clear eventual pending IRQs. */ -#if STM32_PWM_USE_TIM1 || STM32_PWM_USE_TIM8 - pwmp->tim->BDTR = 0; -#endif - -#if STM32_PWM_USE_TIM1 - if (&PWMD1 == pwmp) { - nvicDisableVector(STM32_TIM1_UP_NUMBER); - nvicDisableVector(STM32_TIM1_CC_NUMBER); - rccDisableTIM1(FALSE); - } -#endif -#if STM32_PWM_USE_TIM2 - if (&PWMD2 == pwmp) { - nvicDisableVector(STM32_TIM2_NUMBER); - rccDisableTIM2(FALSE); - } -#endif -#if STM32_PWM_USE_TIM3 - if (&PWMD3 == pwmp) { - nvicDisableVector(STM32_TIM3_NUMBER); - rccDisableTIM3(FALSE); - } -#endif -#if STM32_PWM_USE_TIM4 - if (&PWMD4 == pwmp) { - nvicDisableVector(STM32_TIM4_NUMBER); - rccDisableTIM4(FALSE); - } -#endif -#if STM32_PWM_USE_TIM5 - if (&PWMD5 == pwmp) { - nvicDisableVector(STM32_TIM5_NUMBER); - rccDisableTIM5(FALSE); - } -#endif -#if STM32_PWM_USE_TIM8 - if (&PWMD8 == pwmp) { - nvicDisableVector(STM32_TIM8_UP_NUMBER); - nvicDisableVector(STM32_TIM8_CC_NUMBER); - rccDisableTIM8(FALSE); - } -#endif -#if STM32_PWM_USE_TIM9 - if (&PWMD9 == pwmp) { - nvicDisableVector(STM32_TIM9_NUMBER); - rccDisableTIM9(FALSE); - } -#endif - } -} - -/** - * @brief Enables a PWM channel. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @post The channel is active using the specified configuration. - * @note The function has effect at the next cycle start. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) - * @param[in] width PWM pulse width as clock pulses number - * - * @notapi - */ -void pwm_lld_enable_channel(PWMDriver *pwmp, - pwmchannel_t channel, - pwmcnt_t width) { - - pwmp->tim->CCR[channel] = width; /* New duty cycle. */ - /* If there is a callback defined for the channel then the associated - interrupt must be enabled.*/ - if (pwmp->config->channels[channel].callback != NULL) { - uint32_t dier = pwmp->tim->DIER; - /* If the IRQ is not already enabled care must be taken to clear it, - it is probably already pending because the timer is running.*/ - if ((dier & (2 << channel)) == 0) { - pwmp->tim->DIER = dier | (2 << channel); - pwmp->tim->SR = ~(2 << channel); - } - } -} - -/** - * @brief Disables a PWM channel. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @post The channel is disabled and its output line returned to the - * idle state. - * @note The function has effect at the next cycle start. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) - * - * @notapi - */ -void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) { - - pwmp->tim->CCR[channel] = 0; - pwmp->tim->DIER &= ~(2 << channel); -} - -#endif /* HAL_USE_PWM */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/TIMv1/pwm_lld.h b/firmware/chibios/os/hal/platforms/STM32/TIMv1/pwm_lld.h deleted file mode 100644 index 4f3b459517..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/TIMv1/pwm_lld.h +++ /dev/null @@ -1,480 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/pwm_lld.h - * @brief STM32 PWM subsystem low level driver header. - * - * @addtogroup PWM - * @{ - */ - -#ifndef _PWM_LLD_H_ -#define _PWM_LLD_H_ - -#include "stm32_tim.h" - -#if HAL_USE_PWM || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Number of PWM channels per PWM driver. - */ -#define PWM_CHANNELS 4 - -/** - * @brief Complementary output modes mask. - * @note This is an STM32-specific setting. - */ -#define PWM_COMPLEMENTARY_OUTPUT_MASK 0xF0 - -/** - * @brief Complementary output not driven. - * @note This is an STM32-specific setting. - */ -#define PWM_COMPLEMENTARY_OUTPUT_DISABLED 0x00 - -/** - * @brief Complementary output, active is logic level one. - * @note This is an STM32-specific setting. - * @note This setting is only available if the configuration option - * @p STM32_PWM_USE_ADVANCED is set to TRUE and only for advanced - * timers TIM1 and TIM8. - */ -#define PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH 0x10 - -/** - * @brief Complementary output, active is logic level zero. - * @note This is an STM32-specific setting. - * @note This setting is only available if the configuration option - * @p STM32_PWM_USE_ADVANCED is set to TRUE and only for advanced - * timers TIM1 and TIM8. - */ -#define PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW 0x20 - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief If advanced timer features switch. - * @details If set to @p TRUE the advanced features for TIM1 and TIM8 are - * enabled. - * @note The default is @p TRUE. - */ -#if !defined(STM32_PWM_USE_ADVANCED) || defined(__DOXYGEN__) -#define STM32_PWM_USE_ADVANCED FALSE -#endif - -/** - * @brief PWMD1 driver enable switch. - * @details If set to @p TRUE the support for PWMD1 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_PWM_USE_TIM1) || defined(__DOXYGEN__) -#define STM32_PWM_USE_TIM1 FALSE -#endif - -/** - * @brief PWMD2 driver enable switch. - * @details If set to @p TRUE the support for PWMD2 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_PWM_USE_TIM2) || defined(__DOXYGEN__) -#define STM32_PWM_USE_TIM2 FALSE -#endif - -/** - * @brief PWMD3 driver enable switch. - * @details If set to @p TRUE the support for PWMD3 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_PWM_USE_TIM3) || defined(__DOXYGEN__) -#define STM32_PWM_USE_TIM3 FALSE -#endif - -/** - * @brief PWMD4 driver enable switch. - * @details If set to @p TRUE the support for PWMD4 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_PWM_USE_TIM4) || defined(__DOXYGEN__) -#define STM32_PWM_USE_TIM4 FALSE -#endif - -/** - * @brief PWMD5 driver enable switch. - * @details If set to @p TRUE the support for PWMD5 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_PWM_USE_TIM5) || defined(__DOXYGEN__) -#define STM32_PWM_USE_TIM5 FALSE -#endif - -/** - * @brief PWMD8 driver enable switch. - * @details If set to @p TRUE the support for PWMD8 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_PWM_USE_TIM8) || defined(__DOXYGEN__) -#define STM32_PWM_USE_TIM8 FALSE -#endif - -/** - * @brief PWMD9 driver enable switch. - * @details If set to @p TRUE the support for PWMD9 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_PWM_USE_TIM9) || defined(__DOXYGEN__) -#define STM32_PWM_USE_TIM9 FALSE -#endif - -/** - * @brief PWMD1 interrupt priority level setting. - */ -#if !defined(STM32_PWM_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_PWM_TIM1_IRQ_PRIORITY 7 -#endif - -/** - * @brief PWMD2 interrupt priority level setting. - */ -#if !defined(STM32_PWM_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_PWM_TIM2_IRQ_PRIORITY 7 -#endif - -/** - * @brief PWMD3 interrupt priority level setting. - */ -#if !defined(STM32_PWM_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_PWM_TIM3_IRQ_PRIORITY 7 -#endif - -/** - * @brief PWMD4 interrupt priority level setting. - */ -#if !defined(STM32_PWM_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_PWM_TIM4_IRQ_PRIORITY 7 -#endif - -/** - * @brief PWMD5 interrupt priority level setting. - */ -#if !defined(STM32_PWM_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_PWM_TIM5_IRQ_PRIORITY 7 -#endif - -/** - * @brief PWMD8 interrupt priority level setting. - */ -#if !defined(STM32_PWM_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_PWM_TIM8_IRQ_PRIORITY 7 -#endif -/** @} */ - -/** - * @brief PWMD9 interrupt priority level setting. - */ -#if !defined(STM32_PWM_TIM9_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_PWM_TIM9_IRQ_PRIORITY 7 -#endif -/** @} */ - -/*===========================================================================*/ -/* Configuration checks. */ -/*===========================================================================*/ - -#if STM32_PWM_USE_TIM1 && !STM32_HAS_TIM1 -#error "TIM1 not present in the selected device" -#endif - -#if STM32_PWM_USE_TIM2 && !STM32_HAS_TIM2 -#error "TIM2 not present in the selected device" -#endif - -#if STM32_PWM_USE_TIM3 && !STM32_HAS_TIM3 -#error "TIM3 not present in the selected device" -#endif - -#if STM32_PWM_USE_TIM4 && !STM32_HAS_TIM4 -#error "TIM4 not present in the selected device" -#endif - -#if STM32_PWM_USE_TIM5 && !STM32_HAS_TIM5 -#error "TIM5 not present in the selected device" -#endif - -#if STM32_PWM_USE_TIM8 && !STM32_HAS_TIM8 -#error "TIM8 not present in the selected device" -#endif - -#if STM32_PWM_USE_TIM9 && !STM32_HAS_TIM9 -#error "TIM9 not present in the selected device" -#endif - -#if !STM32_PWM_USE_TIM1 && !STM32_PWM_USE_TIM2 && \ - !STM32_PWM_USE_TIM3 && !STM32_PWM_USE_TIM4 && \ - !STM32_PWM_USE_TIM5 && !STM32_PWM_USE_TIM8 && \ - !STM32_PWM_USE_TIM9 -#error "PWM driver activated but no TIM peripheral assigned" -#endif - -#if STM32_PWM_USE_ADVANCED && !STM32_PWM_USE_TIM1 && !STM32_PWM_USE_TIM8 -#error "advanced mode selected but no advanced timer assigned" -#endif - -#if STM32_PWM_USE_TIM1 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_PWM_TIM1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM1" -#endif - -#if STM32_PWM_USE_TIM2 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_PWM_TIM2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM2" -#endif - -#if STM32_PWM_USE_TIM3 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_PWM_TIM3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM3" -#endif - -#if STM32_PWM_USE_TIM4 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_PWM_TIM4_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM4" -#endif - -#if STM32_PWM_USE_TIM5 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_PWM_TIM5_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM5" -#endif - -#if STM32_PWM_USE_TIM8 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_PWM_TIM8_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM8" -#endif - -#if STM32_PWM_USE_TIM9 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_PWM_TIM9_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM9" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief PWM mode type. - */ -typedef uint32_t pwmmode_t; - -/** - * @brief PWM channel type. - */ -typedef uint8_t pwmchannel_t; - -/** - * @brief PWM counter type. - */ -typedef uint16_t pwmcnt_t; - -/** - * @brief PWM driver channel configuration structure. - */ -typedef struct { - /** - * @brief Channel active logic level. - */ - pwmmode_t mode; - /** - * @brief Channel callback pointer. - * @note This callback is invoked on the channel compare event. If set to - * @p NULL then the callback is disabled. - */ - pwmcallback_t callback; - /* End of the mandatory fields.*/ -} PWMChannelConfig; - -/** - * @brief PWM driver configuration structure. - */ -typedef struct { - /** - * @brief Timer clock in Hz. - * @note The low level can use assertions in order to catch invalid - * frequency specifications. - */ - uint32_t frequency; - /** - * @brief PWM period in ticks. - * @note The low level can use assertions in order to catch invalid - * period specifications. - */ - pwmcnt_t period; - /** - * @brief Periodic callback pointer. - * @note This callback is invoked on PWM counter reset. If set to - * @p NULL then the callback is disabled. - */ - pwmcallback_t callback; - /** - * @brief Channels configurations. - */ - PWMChannelConfig channels[PWM_CHANNELS]; - /* End of the mandatory fields.*/ - /** - * @brief TIM CR2 register initialization data. - * @note The value of this field should normally be equal to zero. - */ - uint32_t cr2; -#if STM32_PWM_USE_ADVANCED || defined(__DOXYGEN__) - /** - * @brief TIM BDTR (break & dead-time) register initialization data. - * @note The value of this field should normally be equal to zero. - */ \ - uint32_t bdtr; -#endif - /** - * @brief TIM DIER register initialization data. - * @note The value of this field should normally be equal to zero. - * @note Only the DMA-related bits can be specified in this field. - */ - uint32_t dier; -} PWMConfig; - -/** - * @brief Structure representing a PWM driver. - */ -struct PWMDriver { - /** - * @brief Driver state. - */ - pwmstate_t state; - /** - * @brief Current driver configuration data. - */ - const PWMConfig *config; - /** - * @brief Current PWM period in ticks. - */ - pwmcnt_t period; -#if defined(PWM_DRIVER_EXT_FIELDS) - PWM_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Timer base clock. - */ - uint32_t clock; - /** - * @brief Pointer to the TIMx registers block. - */ - stm32_tim_t *tim; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Changes the period the PWM peripheral. - * @details This function changes the period of a PWM unit that has already - * been activated using @p pwmStart(). - * @pre The PWM unit must have been activated using @p pwmStart(). - * @post The PWM unit period is changed to the new value. - * @note The function has effect at the next cycle start. - * @note If a period is specified that is shorter than the pulse width - * programmed in one of the channels then the behavior is not - * guaranteed. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] period new cycle time in ticks - * - * @notapi - */ -#define pwm_lld_change_period(pwmp, period) \ - ((pwmp)->tim->ARR = (uint16_t)((period) - 1)) - -/** - * @brief Returns a PWM channel status. - * @pre The PWM unit must have been activated using @p pwmStart(). - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) - * - * @notapi - */ -#define pwm_lld_is_channel_enabled(pwmp, channel) \ - (((pwmp)->tim->CCR[channel] != 0) || \ - (((pwmp)->tim->DIER & (2 << channel)) != 0)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_PWM_USE_TIM1 && !defined(__DOXYGEN__) -extern PWMDriver PWMD1; -#endif - -#if STM32_PWM_USE_TIM2 && !defined(__DOXYGEN__) -extern PWMDriver PWMD2; -#endif - -#if STM32_PWM_USE_TIM3 && !defined(__DOXYGEN__) -extern PWMDriver PWMD3; -#endif - -#if STM32_PWM_USE_TIM4 && !defined(__DOXYGEN__) -extern PWMDriver PWMD4; -#endif - -#if STM32_PWM_USE_TIM5 && !defined(__DOXYGEN__) -extern PWMDriver PWMD5; -#endif - -#if STM32_PWM_USE_TIM8 && !defined(__DOXYGEN__) -extern PWMDriver PWMD8; -#endif - -#if STM32_PWM_USE_TIM9 && !defined(__DOXYGEN__) -extern PWMDriver PWMD9; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void pwm_lld_init(void); - void pwm_lld_start(PWMDriver *pwmp); - void pwm_lld_stop(PWMDriver *pwmp); - void pwm_lld_enable_channel(PWMDriver *pwmp, - pwmchannel_t channel, - pwmcnt_t width); - void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_PWM */ - -#endif /* _PWM_LLD_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/TIMv1/stm32_tim.h b/firmware/chibios/os/hal/platforms/STM32/TIMv1/stm32_tim.h deleted file mode 100644 index 5d48170f58..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/TIMv1/stm32_tim.h +++ /dev/null @@ -1,448 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file stm32_tim.h - * @brief STM32 TIM registers layout header. - * @note This file requires definitions from the ST STM32 header file. - * - * @addtogroup STM32_TIMv1 - * @{ - */ - -#ifndef _STM32_TIM_H_ -#define _STM32_TIM_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name TIM_CR1 register - * @{ - */ -#define STM32_TIM_CR1_CEN (1U << 0) -#define STM32_TIM_CR1_UDIS (1U << 1) -#define STM32_TIM_CR1_URS (1U << 2) -#define STM32_TIM_CR1_OPM (1U << 3) -#define STM32_TIM_CR1_DIR (1U << 4) - -#define STM32_TIM_CR1_CMS_MASK (3U << 5) -#define STM32_TIM_CR1_CMS(n) ((n) << 5) - -#define STM32_TIM_CR1_ARPE (1U << 7) - -#define STM32_TIM_CR1_CKD_MASK (3U << 8) -#define STM32_TIM_CR1_CKD(n) ((n) << 8) - -#define STM32_TIM_CR1_UIFREMAP (1U << 11) -/** @} */ - -/** - * @name TIM_CR2 register - * @{ - */ -#define STM32_TIM_CR2_CCPC (1U << 0) -#define STM32_TIM_CR2_CCUS (1U << 2) -#define STM32_TIM_CR2_CCDS (1U << 3) - -#define STM32_TIM_CR2_MMS_MASK (7U << 4) -#define STM32_TIM_CR2_MMS(n) ((n) << 4) - -#define STM32_TIM_CR2_TI1S (1U << 7) -#define STM32_TIM_CR2_OIS1 (1U << 8) -#define STM32_TIM_CR2_OIS1N (1U << 9) -#define STM32_TIM_CR2_OIS2 (1U << 10) -#define STM32_TIM_CR2_OIS2N (1U << 11) -#define STM32_TIM_CR2_OIS3 (1U << 12) -#define STM32_TIM_CR2_OIS3N (1U << 13) -#define STM32_TIM_CR2_OIS4 (1U << 14) -#define STM32_TIM_CR2_OIS5 (1U << 16) -#define STM32_TIM_CR2_OIS6 (1U << 18) - -#define STM32_TIM_CR2_MMS2_MASK (15U << 20) -#define STM32_TIM_CR2_MMS2(n) ((n) << 20) -/** @} */ - -/** - * @name TIM_SMCR register - * @{ - */ -#define STM32_TIM_SMCR_SMS_MASK ((7U << 0) | (1U << 16)) -#define STM32_TIM_SMCR_SMS(n) ((((n) & 7) << 0) | \ - (((n) >> 3) << 16)) - -#define STM32_TIM_SMCR_OCCS (1U << 3) - -#define STM32_TIM_SMCR_TS_MASK (7U << 4) -#define STM32_TIM_SMCR_TS(n) ((n) << 4) - -#define STM32_TIM_SMCR_MSM (1U << 7) - -#define STM32_TIM_SMCR_ETF_MASK (15U << 8) -#define STM32_TIM_SMCR_ETF(n) ((n) << 8) - -#define STM32_TIM_SMCR_ETPS_MASK (3U << 12) -#define STM32_TIM_SMCR_ETPS(n) ((n) << 12) - -#define STM32_TIM_SMCR_ECE (1U << 14) -#define STM32_TIM_SMCR_ETP (1U << 15) -/** @} */ - -/** - * @name TIM_DIER register - * @{ - */ -#define STM32_TIM_DIER_UIE (1U << 0) -#define STM32_TIM_DIER_CC1IE (1U << 1) -#define STM32_TIM_DIER_CC2IE (1U << 2) -#define STM32_TIM_DIER_CC3IE (1U << 3) -#define STM32_TIM_DIER_CC4IE (1U << 4) -#define STM32_TIM_DIER_COMIE (1U << 5) -#define STM32_TIM_DIER_TIE (1U << 6) -#define STM32_TIM_DIER_BIE (1U << 7) -#define STM32_TIM_DIER_UDE (1U << 8) -#define STM32_TIM_DIER_CC1DE (1U << 9) -#define STM32_TIM_DIER_CC2DE (1U << 10) -#define STM32_TIM_DIER_CC3DE (1U << 11) -#define STM32_TIM_DIER_CC4DE (1U << 12) -#define STM32_TIM_DIER_COMDE (1U << 13) -#define STM32_TIM_DIER_TDE (1U << 14) - -#define STM32_TIM_DIER_IRQ_MASK (STM32_TIM_DIER_UIE | \ - STM32_TIM_DIER_CC1IE | \ - STM32_TIM_DIER_CC2IE | \ - STM32_TIM_DIER_CC3IE | \ - STM32_TIM_DIER_CC4IE | \ - STM32_TIM_DIER_COMIE | \ - STM32_TIM_DIER_TIE | \ - STM32_TIM_DIER_BIE) - -/** @} */ - -/** - * @name TIM_SR register - * @{ - */ -#define STM32_TIM_SR_UIF (1U << 0) -#define STM32_TIM_SR_CC1IF (1U << 1) -#define STM32_TIM_SR_CC2IF (1U << 2) -#define STM32_TIM_SR_CC3IF (1U << 3) -#define STM32_TIM_SR_CC4IF (1U << 4) -#define STM32_TIM_SR_COMIF (1U << 5) -#define STM32_TIM_SR_TIF (1U << 6) -#define STM32_TIM_SR_BIF (1U << 7) -#define STM32_TIM_SR_B2IF (1U << 8) -#define STM32_TIM_SR_CC1OF (1U << 9) -#define STM32_TIM_SR_CC2OF (1U << 10) -#define STM32_TIM_SR_CC3OF (1U << 11) -#define STM32_TIM_SR_CC4OF (1U << 12) -#define STM32_TIM_SR_CC5IF (1U << 16) -#define STM32_TIM_SR_CC6IF (1U << 17) -/** @} */ - -/** - * @name TIM_EGR register - * @{ - */ -#define STM32_TIM_EGR_UG (1U << 0) -#define STM32_TIM_EGR_CC1G (1U << 1) -#define STM32_TIM_EGR_CC2G (1U << 2) -#define STM32_TIM_EGR_CC3G (1U << 3) -#define STM32_TIM_EGR_CC4G (1U << 4) -#define STM32_TIM_EGR_COMG (1U << 5) -#define STM32_TIM_EGR_TG (1U << 6) -#define STM32_TIM_EGR_BG (1U << 7) -#define STM32_TIM_EGR_B2G (1U << 8) -/** @} */ - -/** - * @name TIM_CCMR1 register (output) - * @{ - */ -#define STM32_TIM_CCMR1_CC1S_MASK (3U << 0) -#define STM32_TIM_CCMR1_CC1S(n) ((n) << 0) - -#define STM32_TIM_CCMR1_OC1FE (1U << 2) -#define STM32_TIM_CCMR1_OC1PE (1U << 3) - -#define STM32_TIM_CCMR1_OC1M_MASK ((7U << 4) | (1U << 16)) -#define STM32_TIM_CCMR1_OC1M(n) ((((n) & 7) << 4) | \ - (((n) >> 3) << 16)) - -#define STM32_TIM_CCMR1_OC1CE (1U << 7) - -#define STM32_TIM_CCMR1_CC2S_MASK (3U << 8) -#define STM32_TIM_CCMR1_CC2S(n) ((n) << 8) - -#define STM32_TIM_CCMR1_OC2FE (1U << 10) -#define STM32_TIM_CCMR1_OC2PE (1U << 11) - -#define STM32_TIM_CCMR1_OC2M_MASK ((7U << 12) | (1U << 24)) -#define STM32_TIM_CCMR1_OC2M(n) ((((n) & 7) << 12) | \ - (((n) >> 3) << 24)) - -#define STM32_TIM_CCMR1_OC2CE (1U << 15) -/** @} */ - -/** - * @name CCMR1 register (input) - * @{ - */ -#define STM32_TIM_CCMR1_IC1PSC_MASK (3U << 2) -#define STM32_TIM_CCMR1_IC1PSC(n) ((n) << 2) - -#define STM32_TIM_CCMR1_IC1F_MASK (15U << 4) -#define STM32_TIM_CCMR1_IC1F(n) ((n) << 4) - -#define STM32_TIM_CCMR1_IC2PSC_MASK (3U << 10) -#define STM32_TIM_CCMR1_IC2PSC(n) ((n) << 10) - -#define STM32_TIM_CCMR1_IC2F_MASK (15U << 12) -#define STM32_TIM_CCMR1_IC2F(n) ((n) << 12) -/** @} */ - -/** - * @name TIM_CCMR2 register (output) - * @{ - */ -#define STM32_TIM_CCMR2_CC3S_MASK (3U << 0) -#define STM32_TIM_CCMR2_CC3S(n) ((n) << 0) - -#define STM32_TIM_CCMR2_OC3FE (1U << 2) -#define STM32_TIM_CCMR2_OC3PE (1U << 3) - -#define STM32_TIM_CCMR2_OC3M_MASK ((7U << 4) | (1U << 16)) -#define STM32_TIM_CCMR2_OC3M(n) ((((n) & 7) << 4) | \ - (((n) >> 3) << 16)) - -#define STM32_TIM_CCMR2_OC3CE (1U << 7) - -#define STM32_TIM_CCMR2_CC4S_MASK (3U << 8) -#define STM32_TIM_CCMR2_CC4S(n) ((n) << 8) - -#define STM32_TIM_CCMR2_OC4FE (1U << 10) -#define STM32_TIM_CCMR2_OC4PE (1U << 11) - -#define STM32_TIM_CCMR2_OC4M_MASK ((7U << 12) | (1U << 24)) -#define STM32_TIM_CCMR2_OC4M(n) ((((n) & 7) << 12) | \ - (((n) >> 3) << 24)) - -#define STM32_TIM_CCMR2_OC4CE (1U << 15) -/** @} */ - -/** - * @name TIM_CCMR2 register (input) - * @{ - */ -#define STM32_TIM_CCMR2_IC3PSC_MASK (3U << 2) -#define STM32_TIM_CCMR2_IC3PSC(n) ((n) << 2) - -#define STM32_TIM_CCMR2_IC3F_MASK (15U << 4) -#define STM32_TIM_CCMR2_IC3F(n) ((n) << 4) - -#define STM32_TIM_CCMR2_IC4PSC_MASK (3U << 10) -#define STM32_TIM_CCMR2_IC4PSC(n) ((n) << 10) - -#define STM32_TIM_CCMR2_IC4F_MASK (15U << 12) -#define STM32_TIM_CCMR2_IC4F(n) ((n) << 12) -/** @} */ - -/** - * @name TIM_CCER register - * @{ - */ -#define STM32_TIM_CCER_CC1E (1U << 0) -#define STM32_TIM_CCER_CC1P (1U << 1) -#define STM32_TIM_CCER_CC1NE (1U << 2) -#define STM32_TIM_CCER_CC1NP (1U << 3) -#define STM32_TIM_CCER_CC2E (1U << 4) -#define STM32_TIM_CCER_CC2P (1U << 5) -#define STM32_TIM_CCER_CC2NE (1U << 6) -#define STM32_TIM_CCER_CC2NP (1U << 7) -#define STM32_TIM_CCER_CC3E (1U << 8) -#define STM32_TIM_CCER_CC3P (1U << 9) -#define STM32_TIM_CCER_CC3NE (1U << 10) -#define STM32_TIM_CCER_CC3NP (1U << 11) -#define STM32_TIM_CCER_CC4E (1U << 12) -#define STM32_TIM_CCER_CC4P (1U << 13) -#define STM32_TIM_CCER_CC4NP (1U << 15) -#define STM32_TIM_CCER_CC5E (1U << 16) -#define STM32_TIM_CCER_CC5P (1U << 17) -#define STM32_TIM_CCER_CC6E (1U << 20) -#define STM32_TIM_CCER_CC6P (1U << 21) -/** @} */ - -/** - * @name TIM_CNT register - * @{ - */ -#define STM32_TIM_CNT_UIFCPY (1U << 31) -/** @} */ - -/** - * @name TIM_BDTR register - * @{ - */ -#define STM32_TIM_BDTR_DTG_MASK (255U << 0) -#define STM32_TIM_BDTR_DTG(n) ((n) << 0) - -#define STM32_TIM_BDTR_LOCK_MASK (3U << 8) -#define STM32_TIM_BDTR_LOCK(n) ((n) << 8) - -#define STM32_TIM_BDTR_OSSI (1U << 10) -#define STM32_TIM_BDTR_OSSR (1U << 11) -#define STM32_TIM_BDTR_BKE (1U << 12) -#define STM32_TIM_BDTR_BKP (1U << 13) -#define STM32_TIM_BDTR_AOE (1U << 14) -#define STM32_TIM_BDTR_MOE (1U << 15) - -#define STM32_TIM_BDTR_BKF_MASK (15U << 16) -#define STM32_TIM_BDTR_BKF(n) ((n) << 16) -#define STM32_TIM_BDTR_BK2F_MASK (15U << 20) -#define STM32_TIM_BDTR_BK2F(n) ((n) << 20) - -#define STM32_TIM_BDTR_BK2E (1U << 24) -#define STM32_TIM_BDTR_BK2P (1U << 25) -/** @} */ - -/** - * @name TIM_DCR register - * @{ - */ -#define STM32_TIM_DCR_DBA_MASK (31U << 0) -#define STM32_TIM_DCR_DBA(n) ((n) << 0) - -#define STM32_TIM_DCR_DBL_MASK (31U << 8) -#define STM32_TIM_DCR_DBL(b) ((n) << 8) -/** @} */ - -/** - * @name TIM16_OR register - * @{ - */ -#define STM32_TIM16_OR_TI1_RMP_MASK (3U << 6) -#define STM32_TIM16_OR_TI1_RMP(n) ((n) << 6) -/** @} */ - -/** - * @name TIM_OR register - * @{ - */ -#define STM32_TIM_OR_ETR_RMP_MASK (15U << 0) -#define STM32_TIM_OR_ETR_RMP(n) ((n) << 0) -/** @} */ - -/** - * @name TIM_CCMR3 register - * @{ - */ -#define STM32_TIM_CCMR3_OC5FE (1U << 2) -#define STM32_TIM_CCMR3_OC5PE (1U << 3) - -#define STM32_TIM_CCMR3_OC5M_MASK ((7U << 4) | (1U << 16)) -#define STM32_TIM_CCMR3_OC5M(n) ((((n) & 7) << 4) | \ - (((n) >> 2) << 16)) - -#define STM32_TIM_CCMR3_OC5CE (1U << 7) - -#define STM32_TIM_CCMR3_OC6FE (1U << 10) -#define STM32_TIM_CCMR3_OC6PE (1U << 11) - -#define STM32_TIM_CCMR3_OC6M_MASK ((7U << 12) | (1U << 24)) -#define STM32_TIM_CCMR3_OC6M(n) ((((n) & 7) << 12) | \ - (((n) >> 2) << 24)) - -#define STM32_TIM_CCMR3_OC6CE (1U << 15) -/** @} */ - -/** - * @name TIM units references - * @{ - */ -#define STM32_TIM1 ((stm32_tim_t *)TIM1_BASE) -#define STM32_TIM2 ((stm32_tim_t *)TIM2_BASE) -#define STM32_TIM3 ((stm32_tim_t *)TIM3_BASE) -#define STM32_TIM4 ((stm32_tim_t *)TIM4_BASE) -#define STM32_TIM5 ((stm32_tim_t *)TIM5_BASE) -#define STM32_TIM6 ((stm32_tim_t *)TIM6_BASE) -#define STM32_TIM7 ((stm32_tim_t *)TIM7_BASE) -#define STM32_TIM8 ((stm32_tim_t *)TIM8_BASE) -#define STM32_TIM9 ((stm32_tim_t *)TIM9_BASE) -#define STM32_TIM10 ((stm32_tim_t *)TIM10_BASE) -#define STM32_TIM11 ((stm32_tim_t *)TIM11_BASE) -#define STM32_TIM12 ((stm32_tim_t *)TIM12_BASE) -#define STM32_TIM13 ((stm32_tim_t *)TIM13_BASE) -#define STM32_TIM14 ((stm32_tim_t *)TIM14_BASE) -#define STM32_TIM15 ((stm32_tim_t *)TIM15_BASE) -#define STM32_TIM16 ((stm32_tim_t *)TIM16_BASE) -#define STM32_TIM17 ((stm32_tim_t *)TIM17_BASE) -#define STM32_TIM18 ((stm32_tim_t *)TIM18_BASE) -#define STM32_TIM19 ((stm32_tim_t *)TIM19_BASE) -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief STM32 TIM registers block. - * @note This is the most general known form, not all timers have - * necessarily all registers and bits. - */ -typedef struct { - volatile uint32_t CR1; - volatile uint32_t CR2; - volatile uint32_t SMCR; - volatile uint32_t DIER; - volatile uint32_t SR; - volatile uint32_t EGR; - volatile uint32_t CCMR1; - volatile uint32_t CCMR2; - volatile uint32_t CCER; - volatile uint32_t CNT; - volatile uint32_t PSC; - volatile uint32_t ARR; - volatile uint32_t RCR; - volatile uint32_t CCR[4]; - volatile uint32_t BDTR; - volatile uint32_t DCR; - volatile uint32_t DMAR; - volatile uint32_t OR; - volatile uint32_t CCMR3; - volatile uint32_t CCR5; - volatile uint32_t CCR6; -} stm32_tim_t; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#endif /* _STM32_TIM_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/USARTv1/serial_lld.c b/firmware/chibios/os/hal/platforms/STM32/USARTv1/serial_lld.c deleted file mode 100644 index 01942bba00..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/USARTv1/serial_lld.c +++ /dev/null @@ -1,538 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/USARTv1/serial_lld.c - * @brief STM32 low level serial driver code. - * - * @addtogroup SERIAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief USART1 serial driver identifier.*/ -#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__) -SerialDriver SD1; -#endif - -/** @brief USART2 serial driver identifier.*/ -#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__) -SerialDriver SD2; -#endif - -/** @brief USART3 serial driver identifier.*/ -#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__) -SerialDriver SD3; -#endif - -/** @brief UART4 serial driver identifier.*/ -#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__) -SerialDriver SD4; -#endif - -/** @brief UART5 serial driver identifier.*/ -#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__) -SerialDriver SD5; -#endif - -/** @brief USART6 serial driver identifier.*/ -#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__) -SerialDriver SD6; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** @brief Driver default configuration.*/ -static const SerialConfig default_config = -{ - SERIAL_DEFAULT_BITRATE, - 0, - USART_CR2_STOP1_BITS | USART_CR2_LINEN, - 0 -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief USART initialization. - * @details This function must be invoked with interrupts disabled. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] config the architecture-dependent serial driver configuration - */ -static void usart_init(SerialDriver *sdp, const SerialConfig *config) { - USART_TypeDef *u = sdp->usart; - - /* Baud rate setting.*/ -#if STM32_HAS_USART6 - if ((sdp->usart == USART1) || (sdp->usart == USART6)) -#else - if (sdp->usart == USART1) -#endif - u->BRR = STM32_PCLK2 / config->speed; - else - u->BRR = STM32_PCLK1 / config->speed; - - /* Note that some bits are enforced.*/ - u->CR2 = config->cr2 | USART_CR2_LBDIE; - u->CR3 = config->cr3 | USART_CR3_EIE; - u->CR1 = config->cr1 | USART_CR1_UE | USART_CR1_PEIE | - USART_CR1_RXNEIE | USART_CR1_TE | - USART_CR1_RE; - u->SR = 0; - (void)u->SR; /* SR reset step 1.*/ - (void)u->DR; /* SR reset step 2.*/ -} - -/** - * @brief USART de-initialization. - * @details This function must be invoked with interrupts disabled. - * - * @param[in] u pointer to an USART I/O block - */ -static void usart_deinit(USART_TypeDef *u) { - - u->CR1 = 0; - u->CR2 = 0; - u->CR3 = 0; -} - -/** - * @brief Error handling routine. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] sr USART SR register value - */ -static void set_error(SerialDriver *sdp, uint16_t sr) { - flagsmask_t sts = 0; - - if (sr & USART_SR_ORE) - sts |= SD_OVERRUN_ERROR; - if (sr & USART_SR_PE) - sts |= SD_PARITY_ERROR; - if (sr & USART_SR_FE) - sts |= SD_FRAMING_ERROR; - if (sr & USART_SR_NE) - sts |= SD_NOISE_ERROR; - chnAddFlagsI(sdp, sts); -} - -/** - * @brief Common IRQ handler. - * - * @param[in] sdp communication channel associated to the USART - */ -static void serve_interrupt(SerialDriver *sdp) { - USART_TypeDef *u = sdp->usart; - uint16_t cr1 = u->CR1; - uint16_t sr = u->SR; - - /* Special case, LIN break detection.*/ - if (sr & USART_SR_LBD) { - chSysLockFromIsr(); - chnAddFlagsI(sdp, SD_BREAK_DETECTED); - chSysUnlockFromIsr(); - u->SR = ~USART_SR_LBD; - } - - /* Data available.*/ - chSysLockFromIsr(); - while (sr & (USART_SR_RXNE | USART_SR_ORE | USART_SR_NE | USART_SR_FE | - USART_SR_PE)) { - uint8_t b; - - /* Error condition detection.*/ - if (sr & (USART_SR_ORE | USART_SR_NE | USART_SR_FE | USART_SR_PE)) - set_error(sdp, sr); - b = u->DR; - if (sr & USART_SR_RXNE) - sdIncomingDataI(sdp, b); - sr = u->SR; - } - chSysUnlockFromIsr(); - - /* Transmission buffer empty.*/ - if ((cr1 & USART_CR1_TXEIE) && (sr & USART_SR_TXE)) { - msg_t b; - chSysLockFromIsr(); - b = chOQGetI(&sdp->oqueue); - if (b < Q_OK) { - chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); - u->CR1 = (cr1 & ~USART_CR1_TXEIE) | USART_CR1_TCIE; - } - else - u->DR = b; - chSysUnlockFromIsr(); - } - - /* Physical transmission end.*/ - if (sr & USART_SR_TC) { - chSysLockFromIsr(); - if (chOQIsEmptyI(&sdp->oqueue)) - chnAddFlagsI(sdp, CHN_TRANSMISSION_END); - u->CR1 = cr1 & ~USART_CR1_TCIE; - u->SR = ~USART_SR_TC; - chSysUnlockFromIsr(); - } -} - -#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__) -static void notify1(GenericQueue *qp) { - - (void)qp; - USART1->CR1 |= USART_CR1_TXEIE; -} -#endif - -#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__) -static void notify2(GenericQueue *qp) { - - (void)qp; - USART2->CR1 |= USART_CR1_TXEIE; -} -#endif - -#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__) -static void notify3(GenericQueue *qp) { - - (void)qp; - USART3->CR1 |= USART_CR1_TXEIE; -} -#endif - -#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__) -static void notify4(GenericQueue *qp) { - - (void)qp; - UART4->CR1 |= USART_CR1_TXEIE; -} -#endif - -#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__) -static void notify5(GenericQueue *qp) { - - (void)qp; - UART5->CR1 |= USART_CR1_TXEIE; -} -#endif - -#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__) -static void notify6(GenericQueue *qp) { - - (void)qp; - USART6->CR1 |= USART_CR1_TXEIE; -} -#endif - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__) -#if !defined(STM32_USART1_HANDLER) -#error "STM32_USART1_HANDLER not defined" -#endif -/** - * @brief USART1 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_USART1_HANDLER) { - - CH_IRQ_PROLOGUE(); - - serve_interrupt(&SD1); - - CH_IRQ_EPILOGUE(); -} -#endif - -#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__) -#if !defined(STM32_USART2_HANDLER) -#error "STM32_USART2_HANDLER not defined" -#endif -/** - * @brief USART2 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_USART2_HANDLER) { - - CH_IRQ_PROLOGUE(); - - serve_interrupt(&SD2); - - CH_IRQ_EPILOGUE(); -} -#endif - -#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__) -#if !defined(STM32_USART3_HANDLER) -#error "STM32_USART3_HANDLER not defined" -#endif -/** - * @brief USART3 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_USART3_HANDLER) { - - CH_IRQ_PROLOGUE(); - - serve_interrupt(&SD3); - - CH_IRQ_EPILOGUE(); -} -#endif - -#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__) -#if !defined(STM32_UART4_HANDLER) -#error "STM32_UART4_HANDLER not defined" -#endif -/** - * @brief UART4 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_UART4_HANDLER) { - - CH_IRQ_PROLOGUE(); - - serve_interrupt(&SD4); - - CH_IRQ_EPILOGUE(); -} -#endif - -#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__) -#if !defined(STM32_UART5_HANDLER) -#error "STM32_UART5_HANDLER not defined" -#endif -/** - * @brief UART5 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_UART5_HANDLER) { - - CH_IRQ_PROLOGUE(); - - serve_interrupt(&SD5); - - CH_IRQ_EPILOGUE(); -} -#endif - -#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__) -#if !defined(STM32_USART6_HANDLER) -#error "STM32_USART6_HANDLER not defined" -#endif -/** - * @brief USART1 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_USART6_HANDLER) { - - CH_IRQ_PROLOGUE(); - - serve_interrupt(&SD6); - - CH_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level serial driver initialization. - * - * @notapi - */ -void sd_lld_init(void) { - -#if STM32_SERIAL_USE_USART1 - sdObjectInit(&SD1, NULL, notify1); - SD1.usart = USART1; -#endif - -#if STM32_SERIAL_USE_USART2 - sdObjectInit(&SD2, NULL, notify2); - SD2.usart = USART2; -#endif - -#if STM32_SERIAL_USE_USART3 - sdObjectInit(&SD3, NULL, notify3); - SD3.usart = USART3; -#endif - -#if STM32_SERIAL_USE_UART4 - sdObjectInit(&SD4, NULL, notify4); - SD4.usart = UART4; -#endif - -#if STM32_SERIAL_USE_UART5 - sdObjectInit(&SD5, NULL, notify5); - SD5.usart = UART5; -#endif - -#if STM32_SERIAL_USE_USART6 - sdObjectInit(&SD6, NULL, notify6); - SD6.usart = USART6; -#endif -} - -/** - * @brief Low level serial driver configuration and (re)start. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] config the architecture-dependent serial driver configuration. - * If this parameter is set to @p NULL then a default - * configuration is used. - * - * @notapi - */ -void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { - - if (config == NULL) - config = &default_config; - - if (sdp->state == SD_STOP) { -#if STM32_SERIAL_USE_USART1 - if (&SD1 == sdp) { - rccEnableUSART1(FALSE); - nvicEnableVector(STM32_USART1_NUMBER, - CORTEX_PRIORITY_MASK(STM32_SERIAL_USART1_PRIORITY)); - } -#endif -#if STM32_SERIAL_USE_USART2 - if (&SD2 == sdp) { - rccEnableUSART2(FALSE); - nvicEnableVector(STM32_USART2_NUMBER, - CORTEX_PRIORITY_MASK(STM32_SERIAL_USART2_PRIORITY)); - } -#endif -#if STM32_SERIAL_USE_USART3 - if (&SD3 == sdp) { - rccEnableUSART3(FALSE); - nvicEnableVector(STM32_USART3_NUMBER, - CORTEX_PRIORITY_MASK(STM32_SERIAL_USART3_PRIORITY)); - } -#endif -#if STM32_SERIAL_USE_UART4 - if (&SD4 == sdp) { - rccEnableUART4(FALSE); - nvicEnableVector(STM32_UART4_NUMBER, - CORTEX_PRIORITY_MASK(STM32_SERIAL_UART4_PRIORITY)); - } -#endif -#if STM32_SERIAL_USE_UART5 - if (&SD5 == sdp) { - rccEnableUART5(FALSE); - nvicEnableVector(STM32_UART5_NUMBER, - CORTEX_PRIORITY_MASK(STM32_SERIAL_UART5_PRIORITY)); - } -#endif -#if STM32_SERIAL_USE_USART6 - if (&SD6 == sdp) { - rccEnableUSART6(FALSE); - nvicEnableVector(STM32_USART6_NUMBER, - CORTEX_PRIORITY_MASK(STM32_SERIAL_USART6_PRIORITY)); - } -#endif - } - usart_init(sdp, config); -} - -/** - * @brief Low level serial driver stop. - * @details De-initializes the USART, stops the associated clock, resets the - * interrupt vector. - * - * @param[in] sdp pointer to a @p SerialDriver object - * - * @notapi - */ -void sd_lld_stop(SerialDriver *sdp) { - - if (sdp->state == SD_READY) { - usart_deinit(sdp->usart); -#if STM32_SERIAL_USE_USART1 - if (&SD1 == sdp) { - rccDisableUSART1(FALSE); - nvicDisableVector(STM32_USART1_NUMBER); - return; - } -#endif -#if STM32_SERIAL_USE_USART2 - if (&SD2 == sdp) { - rccDisableUSART2(FALSE); - nvicDisableVector(STM32_USART2_NUMBER); - return; - } -#endif -#if STM32_SERIAL_USE_USART3 - if (&SD3 == sdp) { - rccDisableUSART3(FALSE); - nvicDisableVector(STM32_USART3_NUMBER); - return; - } -#endif -#if STM32_SERIAL_USE_UART4 - if (&SD4 == sdp) { - rccDisableUART4(FALSE); - nvicDisableVector(STM32_UART4_NUMBER); - return; - } -#endif -#if STM32_SERIAL_USE_UART5 - if (&SD5 == sdp) { - rccDisableUART5(FALSE); - nvicDisableVector(STM32_UART5_NUMBER); - return; - } -#endif -#if STM32_SERIAL_USE_USART6 - if (&SD6 == sdp) { - rccDisableUSART6(FALSE); - nvicDisableVector(STM32_USART6_NUMBER); - return; - } -#endif - } -} - -#endif /* HAL_USE_SERIAL */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/USARTv1/serial_lld.h b/firmware/chibios/os/hal/platforms/STM32/USARTv1/serial_lld.h deleted file mode 100644 index c1a9e2f9b5..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/USARTv1/serial_lld.h +++ /dev/null @@ -1,303 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/USARTv1/serial_lld.h - * @brief STM32 low level serial driver header. - * - * @addtogroup SERIAL - * @{ - */ - -#ifndef _SERIAL_LLD_H_ -#define _SERIAL_LLD_H_ - -#if HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief USART1 driver enable switch. - * @details If set to @p TRUE the support for USART1 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_SERIAL_USE_USART1) || defined(__DOXYGEN__) -#define STM32_SERIAL_USE_USART1 FALSE -#endif - -/** - * @brief USART2 driver enable switch. - * @details If set to @p TRUE the support for USART2 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_SERIAL_USE_USART2) || defined(__DOXYGEN__) -#define STM32_SERIAL_USE_USART2 FALSE -#endif - -/** - * @brief USART3 driver enable switch. - * @details If set to @p TRUE the support for USART3 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_SERIAL_USE_USART3) || defined(__DOXYGEN__) -#define STM32_SERIAL_USE_USART3 FALSE -#endif - -/** - * @brief UART4 driver enable switch. - * @details If set to @p TRUE the support for UART4 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_SERIAL_USE_UART4) || defined(__DOXYGEN__) -#define STM32_SERIAL_USE_UART4 FALSE -#endif - -/** - * @brief UART5 driver enable switch. - * @details If set to @p TRUE the support for UART5 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_SERIAL_USE_UART5) || defined(__DOXYGEN__) -#define STM32_SERIAL_USE_UART5 FALSE -#endif - -/** - * @brief USART6 driver enable switch. - * @details If set to @p TRUE the support for USART6 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_SERIAL_USE_USART6) || defined(__DOXYGEN__) -#define STM32_SERIAL_USE_USART6 FALSE -#endif - -/** - * @brief USART1 interrupt priority level setting. - */ -#if !defined(STM32_SERIAL_USART1_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SERIAL_USART1_PRIORITY 12 -#endif - -/** - * @brief USART2 interrupt priority level setting. - */ -#if !defined(STM32_SERIAL_USART2_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SERIAL_USART2_PRIORITY 12 -#endif - -/** - * @brief USART3 interrupt priority level setting. - */ -#if !defined(STM32_SERIAL_USART3_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SERIAL_USART3_PRIORITY 12 -#endif - -/** - * @brief UART4 interrupt priority level setting. - */ -#if !defined(STM32_SERIAL_UART4_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SERIAL_UART4_PRIORITY 12 -#endif - -/** - * @brief UART5 interrupt priority level setting. - */ -#if !defined(STM32_SERIAL_UART5_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SERIAL_UART5_PRIORITY 12 -#endif - -/** - * @brief USART6 interrupt priority level setting. - */ -#if !defined(STM32_SERIAL_USART6_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SERIAL_USART6_PRIORITY 12 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_SERIAL_USE_USART1 && !STM32_HAS_USART1 -#error "USART1 not present in the selected device" -#endif - -#if STM32_SERIAL_USE_USART2 && !STM32_HAS_USART2 -#error "USART2 not present in the selected device" -#endif - -#if STM32_SERIAL_USE_USART3 && !STM32_HAS_USART3 -#error "USART3 not present in the selected device" -#endif - -#if STM32_SERIAL_USE_UART4 && !STM32_HAS_UART4 -#error "UART4 not present in the selected device" -#endif - -#if STM32_SERIAL_USE_UART5 && !STM32_HAS_UART5 -#error "UART5 not present in the selected device" -#endif - -#if STM32_SERIAL_USE_USART6 && !STM32_HAS_USART6 -#error "USART6 not present in the selected device" -#endif - -#if !STM32_SERIAL_USE_USART1 && !STM32_SERIAL_USE_USART2 && \ - !STM32_SERIAL_USE_USART3 && !STM32_SERIAL_USE_UART4 && \ - !STM32_SERIAL_USE_UART5 && !STM32_SERIAL_USE_USART6 -#error "SERIAL driver activated but no USART/UART peripheral assigned" -#endif - -#if STM32_SERIAL_USE_USART1 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART1_PRIORITY) -#error "Invalid IRQ priority assigned to USART1" -#endif - -#if STM32_SERIAL_USE_USART2 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART2_PRIORITY) -#error "Invalid IRQ priority assigned to USART2" -#endif - -#if STM32_SERIAL_USE_USART3 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART3_PRIORITY) -#error "Invalid IRQ priority assigned to USART3" -#endif - -#if STM32_SERIAL_USE_UART4 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_UART4_PRIORITY) -#error "Invalid IRQ priority assigned to UART4" -#endif - -#if STM32_SERIAL_USE_UART5 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_UART5_PRIORITY) -#error "Invalid IRQ priority assigned to UART5" -#endif - -#if STM32_SERIAL_USE_USART6 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART6_PRIORITY) -#error "Invalid IRQ priority assigned to USART6" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief STM32 Serial Driver configuration structure. - * @details An instance of this structure must be passed to @p sdStart() - * in order to configure and start a serial driver operations. - * @note This structure content is architecture dependent, each driver - * implementation defines its own version and the custom static - * initializers. - */ -typedef struct { - /** - * @brief Bit rate. - */ - uint32_t speed; - /* End of the mandatory fields.*/ - /** - * @brief Initialization value for the CR1 register. - */ - uint16_t cr1; - /** - * @brief Initialization value for the CR2 register. - */ - uint16_t cr2; - /** - * @brief Initialization value for the CR3 register. - */ - uint16_t cr3; -} SerialConfig; - -/** - * @brief @p SerialDriver specific data. - */ -#define _serial_driver_data \ - _base_asynchronous_channel_data \ - /* Driver state.*/ \ - sdstate_t state; \ - /* Input queue.*/ \ - InputQueue iqueue; \ - /* Output queue.*/ \ - OutputQueue oqueue; \ - /* Input circular buffer.*/ \ - uint8_t ib[SERIAL_BUFFERS_SIZE]; \ - /* Output circular buffer.*/ \ - uint8_t ob[SERIAL_BUFFERS_SIZE]; \ - /* End of the mandatory fields.*/ \ - /* Pointer to the USART registers block.*/ \ - USART_TypeDef *usart; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/* - * Extra USARTs definitions here (missing from the ST header file). - */ -#define USART_CR2_STOP1_BITS (0 << 12) /**< @brief CR2 1 stop bit value.*/ -#define USART_CR2_STOP0P5_BITS (1 << 12) /**< @brief CR2 0.5 stop bit value.*/ -#define USART_CR2_STOP2_BITS (2 << 12) /**< @brief CR2 2 stop bit value.*/ -#define USART_CR2_STOP1P5_BITS (3 << 12) /**< @brief CR2 1.5 stop bit value.*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_SERIAL_USE_USART1 && !defined(__DOXYGEN__) -extern SerialDriver SD1; -#endif -#if STM32_SERIAL_USE_USART2 && !defined(__DOXYGEN__) -extern SerialDriver SD2; -#endif -#if STM32_SERIAL_USE_USART3 && !defined(__DOXYGEN__) -extern SerialDriver SD3; -#endif -#if STM32_SERIAL_USE_UART4 && !defined(__DOXYGEN__) -extern SerialDriver SD4; -#endif -#if STM32_SERIAL_USE_UART5 && !defined(__DOXYGEN__) -extern SerialDriver SD5; -#endif -#if STM32_SERIAL_USE_USART6 && !defined(__DOXYGEN__) -extern SerialDriver SD6; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void sd_lld_init(void); - void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); - void sd_lld_stop(SerialDriver *sdp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_SERIAL */ - -#endif /* _SERIAL_LLD_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/USARTv1/uart_lld.c b/firmware/chibios/os/hal/platforms/STM32/USARTv1/uart_lld.c deleted file mode 100644 index 2e40309359..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/USARTv1/uart_lld.c +++ /dev/null @@ -1,834 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/USARTv1/uart_lld.c - * @brief STM32 low level UART driver code. - * - * @addtogroup UART - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_UART || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define USART1_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_USART1_RX_DMA_STREAM, \ - STM32_USART1_RX_DMA_CHN) - -#define USART1_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_USART1_TX_DMA_STREAM, \ - STM32_USART1_TX_DMA_CHN) - -#define USART2_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_USART2_RX_DMA_STREAM, \ - STM32_USART2_RX_DMA_CHN) - -#define USART2_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_USART2_TX_DMA_STREAM, \ - STM32_USART2_TX_DMA_CHN) - -#define USART3_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_USART3_RX_DMA_STREAM, \ - STM32_USART3_RX_DMA_CHN) - -#define USART3_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_USART3_TX_DMA_STREAM, \ - STM32_USART3_TX_DMA_CHN) - -#define UART4_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_UART4_RX_DMA_STREAM, \ - STM32_UART4_RX_DMA_CHN) - -#define UART4_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_UART4_TX_DMA_STREAM, \ - STM32_UART4_TX_DMA_CHN) - -#define UART5_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_UART5_RX_DMA_STREAM, \ - STM32_UART5_RX_DMA_CHN) - -#define UART5_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_UART5_TX_DMA_STREAM, \ - STM32_UART5_TX_DMA_CHN) - -#define USART6_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_USART6_RX_DMA_STREAM, \ - STM32_USART6_RX_DMA_CHN) - -#define USART6_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_USART6_TX_DMA_STREAM, \ - STM32_USART6_TX_DMA_CHN) - -#define STM32_UART45_CR2_CHECK_MASK \ - (USART_CR2_STOP_0 | USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | \ - USART_CR2_LBCL) - -#define STM32_UART45_CR3_CHECK_MASK \ - (USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | USART_CR3_SCEN | \ - USART_CR3_NACK) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief USART1 UART driver identifier.*/ -#if STM32_UART_USE_USART1 || defined(__DOXYGEN__) -UARTDriver UARTD1; -#endif - -/** @brief USART2 UART driver identifier.*/ -#if STM32_UART_USE_USART2 || defined(__DOXYGEN__) -UARTDriver UARTD2; -#endif - -/** @brief USART3 UART driver identifier.*/ -#if STM32_UART_USE_USART3 || defined(__DOXYGEN__) -UARTDriver UARTD3; -#endif - -/** @brief UART4 UART driver identifier.*/ -#if STM32_UART_USE_UART4 || defined(__DOXYGEN__) -UARTDriver UARTD4; -#endif - -/** @brief UART5 UART driver identifier.*/ -#if STM32_UART_USE_UART5 || defined(__DOXYGEN__) -UARTDriver UARTD5; -#endif - -/** @brief USART6 UART driver identifier.*/ -#if STM32_UART_USE_USART6 || defined(__DOXYGEN__) -UARTDriver UARTD6; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Status bits translation. - * - * @param[in] sr USART SR register value - * - * @return The error flags. - */ -static uartflags_t translate_errors(uint16_t sr) { - uartflags_t sts = 0; - - if (sr & USART_SR_ORE) - sts |= UART_OVERRUN_ERROR; - if (sr & USART_SR_PE) - sts |= UART_PARITY_ERROR; - if (sr & USART_SR_FE) - sts |= UART_FRAMING_ERROR; - if (sr & USART_SR_NE) - sts |= UART_NOISE_ERROR; - if (sr & USART_SR_LBD) - sts |= UART_BREAK_DETECTED; - return sts; -} - -/** - * @brief Puts the receiver in the UART_RX_IDLE state. - * - * @param[in] uartp pointer to the @p UARTDriver object - */ -static void set_rx_idle_loop(UARTDriver *uartp) { - uint32_t mode; - - /* RX DMA channel preparation, if the char callback is defined then the - TCIE interrupt is enabled too.*/ - if (uartp->config->rxchar_cb == NULL) - mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC; - else - mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC | STM32_DMA_CR_TCIE; - dmaStreamSetMemory0(uartp->dmarx, &uartp->rxbuf); - dmaStreamSetTransactionSize(uartp->dmarx, 1); - dmaStreamSetMode(uartp->dmarx, uartp->dmamode | mode); - dmaStreamEnable(uartp->dmarx); -} - -/** - * @brief USART de-initialization. - * @details This function must be invoked with interrupts disabled. - * - * @param[in] uartp pointer to the @p UARTDriver object - */ -static void usart_stop(UARTDriver *uartp) { - - /* Stops RX and TX DMA channels.*/ - dmaStreamDisable(uartp->dmarx); - dmaStreamDisable(uartp->dmatx); - - /* Stops USART operations.*/ - uartp->usart->CR1 = 0; - uartp->usart->CR2 = 0; - uartp->usart->CR3 = 0; -} - -/** - * @brief USART initialization. - * @details This function must be invoked with interrupts disabled. - * - * @param[in] uartp pointer to the @p UARTDriver object - */ -static void usart_start(UARTDriver *uartp) { - uint16_t cr1; - USART_TypeDef *u = uartp->usart; - - /* Defensive programming, starting from a clean state.*/ - usart_stop(uartp); - - /* Baud rate setting.*/ -#if STM32_HAS_USART6 - if ((uartp->usart == USART1) || (uartp->usart == USART6)) -#else - if (uartp->usart == USART1) -#endif - u->BRR = STM32_PCLK2 / uartp->config->speed; - else - u->BRR = STM32_PCLK1 / uartp->config->speed; - - /* Resetting eventual pending status flags.*/ - (void)u->SR; /* SR reset step 1.*/ - (void)u->DR; /* SR reset step 2.*/ - u->SR = 0; - - /* Note that some bits are enforced because required for correct driver - operations.*/ - u->CR2 = uartp->config->cr2 | USART_CR2_LBDIE; - u->CR3 = uartp->config->cr3 | USART_CR3_DMAT | USART_CR3_DMAR | - USART_CR3_EIE; - - /* Mustn't ever set TCIE here - if done, it causes an immediate - interrupt.*/ - cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE; - u->CR1 = uartp->config->cr1 | cr1; - - /* Starting the receiver idle loop.*/ - set_rx_idle_loop(uartp); -} - -/** - * @brief RX DMA common service routine. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] flags pre-shifted content of the ISR register - */ -static void uart_lld_serve_rx_end_irq(UARTDriver *uartp, uint32_t flags) { - - /* DMA errors handling.*/ -#if defined(STM32_UART_DMA_ERROR_HOOK) - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - STM32_UART_DMA_ERROR_HOOK(uartp); - } -#else - (void)flags; -#endif - - if (uartp->rxstate == UART_RX_IDLE) { - /* Receiver in idle state, a callback is generated, if enabled, for each - received character and then the driver stays in the same state.*/ - if (uartp->config->rxchar_cb != NULL) - uartp->config->rxchar_cb(uartp, uartp->rxbuf); - } - else { - /* Receiver in active state, a callback is generated, if enabled, after - a completed transfer.*/ - dmaStreamDisable(uartp->dmarx); - uartp->rxstate = UART_RX_COMPLETE; - if (uartp->config->rxend_cb != NULL) - uartp->config->rxend_cb(uartp); - - /* If the callback didn't explicitly change state then the receiver - automatically returns to the idle state.*/ - if (uartp->rxstate == UART_RX_COMPLETE) { - uartp->rxstate = UART_RX_IDLE; - set_rx_idle_loop(uartp); - } - } -} - -/** - * @brief TX DMA common service routine. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] flags pre-shifted content of the ISR register - */ -static void uart_lld_serve_tx_end_irq(UARTDriver *uartp, uint32_t flags) { - - /* DMA errors handling.*/ -#if defined(STM32_UART_DMA_ERROR_HOOK) - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - STM32_UART_DMA_ERROR_HOOK(uartp); - } -#else - (void)flags; -#endif - - dmaStreamDisable(uartp->dmatx); - - /* Only enable TC interrupt if there's a callback attached to it. - We have to do it here, rather than earlier, because TC flag is set - until transmission starts.*/ - if (uartp->config->txend2_cb != NULL) - uartp->usart->CR1 |= USART_CR1_TCIE; - - /* A callback is generated, if enabled, after a completed transfer.*/ - uartp->txstate = UART_TX_COMPLETE; - if (uartp->config->txend1_cb != NULL) - uartp->config->txend1_cb(uartp); - - /* If the callback didn't explicitly change state then the transmitter - automatically returns to the idle state.*/ - if (uartp->txstate == UART_TX_COMPLETE) - uartp->txstate = UART_TX_IDLE; -} - -/** - * @brief USART common service routine. - * - * @param[in] uartp pointer to the @p UARTDriver object - */ -static void serve_usart_irq(UARTDriver *uartp) { - uint16_t sr; - USART_TypeDef *u = uartp->usart; - uint32_t cr1 = u->CR1; - - sr = u->SR; /* SR reset step 1.*/ - (void)u->DR; /* SR reset step 2.*/ - - if (sr & (USART_SR_LBD | USART_SR_ORE | USART_SR_NE | - USART_SR_FE | USART_SR_PE)) { - u->SR = ~USART_SR_LBD; - if (uartp->config->rxerr_cb != NULL) - uartp->config->rxerr_cb(uartp, translate_errors(sr)); - } - - if ((sr & USART_SR_TC) && (cr1 & USART_CR1_TCIE)) { - /* TC interrupt cleared and disabled.*/ - u->SR = ~USART_SR_TC; - u->CR1 = cr1 & ~USART_CR1_TCIE; - - /* End of transmission, a callback is generated.*/ - if (uartp->config->txend2_cb != NULL) - uartp->config->txend2_cb(uartp); - } -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if STM32_UART_USE_USART1 || defined(__DOXYGEN__) -#if !defined(STM32_USART1_HANDLER) -#error "STM32_USART1_HANDLER not defined" -#endif -/** - * @brief USART1 IRQ handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_USART1_HANDLER) { - - CH_IRQ_PROLOGUE(); - - serve_usart_irq(&UARTD1); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_UART_USE_USART1 */ - -#if STM32_UART_USE_USART2 || defined(__DOXYGEN__) -#if !defined(STM32_USART2_HANDLER) -#error "STM32_USART2_HANDLER not defined" -#endif -/** - * @brief USART2 IRQ handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_USART2_HANDLER) { - - CH_IRQ_PROLOGUE(); - - serve_usart_irq(&UARTD2); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_UART_USE_USART2 */ - -#if STM32_UART_USE_USART3 || defined(__DOXYGEN__) -#if !defined(STM32_USART3_HANDLER) -#error "STM32_USART3_HANDLER not defined" -#endif -/** - * @brief USART3 IRQ handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_USART3_HANDLER) { - - CH_IRQ_PROLOGUE(); - - serve_usart_irq(&UARTD3); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_UART_USE_USART3 */ - -#if STM32_UART_USE_UART4 || defined(__DOXYGEN__) -#if !defined(STM32_UART4_HANDLER) -#error "STM32_UART4_HANDLER not defined" -#endif -/** - * @brief UART4 IRQ handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_UART4_HANDLER) { - - CH_IRQ_PROLOGUE(); - - serve_usart_irq(&UARTD4); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_UART_USE_UART4 */ - -#if STM32_UART_USE_UART5 || defined(__DOXYGEN__) -#if !defined(STM32_UART5_HANDLER) -#error "STM32_UART5_HANDLER not defined" -#endif -/** - * @brief UART5 IRQ handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_UART5_HANDLER) { - - CH_IRQ_PROLOGUE(); - - serve_usart_irq(&UARTD5); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_UART_USE_UART5 */ - -#if STM32_UART_USE_USART6 || defined(__DOXYGEN__) -#if !defined(STM32_USART6_HANDLER) -#error "STM32_USART6_HANDLER not defined" -#endif -/** - * @brief USART6 IRQ handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_USART6_HANDLER) { - - CH_IRQ_PROLOGUE(); - - serve_usart_irq(&UARTD6); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_UART_USE_USART6 */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level UART driver initialization. - * - * @notapi - */ -void uart_lld_init(void) { - -#if STM32_UART_USE_USART1 - uartObjectInit(&UARTD1); - UARTD1.usart = USART1; - UARTD1.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; - UARTD1.dmarx = STM32_DMA_STREAM(STM32_UART_USART1_RX_DMA_STREAM); - UARTD1.dmatx = STM32_DMA_STREAM(STM32_UART_USART1_TX_DMA_STREAM); -#endif - -#if STM32_UART_USE_USART2 - uartObjectInit(&UARTD2); - UARTD2.usart = USART2; - UARTD2.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; - UARTD2.dmarx = STM32_DMA_STREAM(STM32_UART_USART2_RX_DMA_STREAM); - UARTD2.dmatx = STM32_DMA_STREAM(STM32_UART_USART2_TX_DMA_STREAM); -#endif - -#if STM32_UART_USE_USART3 - uartObjectInit(&UARTD3); - UARTD3.usart = USART3; - UARTD3.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; - UARTD3.dmarx = STM32_DMA_STREAM(STM32_UART_USART3_RX_DMA_STREAM); - UARTD3.dmatx = STM32_DMA_STREAM(STM32_UART_USART3_TX_DMA_STREAM); -#endif - -#if STM32_UART_USE_UART4 - uartObjectInit(&UARTD4); - UARTD4.usart = UART4; - UARTD4.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; - UARTD4.dmarx = STM32_DMA_STREAM(STM32_UART_UART4_RX_DMA_STREAM); - UARTD4.dmatx = STM32_DMA_STREAM(STM32_UART_UART4_TX_DMA_STREAM); -#endif - -#if STM32_UART_USE_UART5 - uartObjectInit(&UARTD5); - UARTD5.usart = UART5; - UARTD5.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; - UARTD5.dmarx = STM32_DMA_STREAM(STM32_UART_UART5_RX_DMA_STREAM); - UARTD5.dmatx = STM32_DMA_STREAM(STM32_UART_UART5_TX_DMA_STREAM); -#endif - -#if STM32_UART_USE_USART6 - uartObjectInit(&UARTD6); - UARTD6.usart = USART6; - UARTD6.dmarx = STM32_DMA_STREAM(STM32_UART_USART6_RX_DMA_STREAM); - UARTD6.dmatx = STM32_DMA_STREAM(STM32_UART_USART6_TX_DMA_STREAM); -#endif -} - -/** - * @brief Configures and activates the UART peripheral. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @notapi - */ -void uart_lld_start(UARTDriver *uartp) { - - if (uartp->state == UART_STOP) { -#if STM32_UART_USE_USART1 - if (&UARTD1 == uartp) { - bool_t b; - b = dmaStreamAllocate(uartp->dmarx, - STM32_UART_USART1_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, - (void *)uartp); - chDbgAssert(!b, "uart_lld_start(), #1", "stream already allocated"); - b = dmaStreamAllocate(uartp->dmatx, - STM32_UART_USART1_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, - (void *)uartp); - chDbgAssert(!b, "uart_lld_start(), #2", "stream already allocated"); - rccEnableUSART1(FALSE); - nvicEnableVector(STM32_USART1_NUMBER, - CORTEX_PRIORITY_MASK(STM32_UART_USART1_IRQ_PRIORITY)); - uartp->dmamode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY); - } -#endif - -#if STM32_UART_USE_USART2 - if (&UARTD2 == uartp) { - bool_t b; - b = dmaStreamAllocate(uartp->dmarx, - STM32_UART_USART2_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, - (void *)uartp); - chDbgAssert(!b, "uart_lld_start(), #3", "stream already allocated"); - b = dmaStreamAllocate(uartp->dmatx, - STM32_UART_USART2_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, - (void *)uartp); - chDbgAssert(!b, "uart_lld_start(), #4", "stream already allocated"); - rccEnableUSART2(FALSE); - nvicEnableVector(STM32_USART2_NUMBER, - CORTEX_PRIORITY_MASK(STM32_UART_USART2_IRQ_PRIORITY)); - uartp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY); - } -#endif - -#if STM32_UART_USE_USART3 - if (&UARTD3 == uartp) { - bool_t b; - b = dmaStreamAllocate(uartp->dmarx, - STM32_UART_USART3_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, - (void *)uartp); - chDbgAssert(!b, "uart_lld_start(), #5", "stream already allocated"); - b = dmaStreamAllocate(uartp->dmatx, - STM32_UART_USART3_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, - (void *)uartp); - chDbgAssert(!b, "uart_lld_start(), #6", "stream already allocated"); - rccEnableUSART3(FALSE); - nvicEnableVector(STM32_USART3_NUMBER, - CORTEX_PRIORITY_MASK(STM32_UART_USART3_IRQ_PRIORITY)); - uartp->dmamode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY); - } -#endif - -#if STM32_UART_USE_UART4 - if (&UARTD4 == uartp) { - bool_t b; - - chDbgAssert((uartp->config->cr2 & STM32_UART45_CR2_CHECK_MASK) == 0, - "uart_lld_start(), #7", - "specified invalid bits in UART4 CR2 register settings"); - chDbgAssert((uartp->config->cr3 & STM32_UART45_CR3_CHECK_MASK) == 0, - "uart_lld_start(), #8", - "specified invalid bits in UART4 CR3 register settings"); - - b = dmaStreamAllocate(uartp->dmarx, - STM32_UART_UART4_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, - (void *)uartp); - chDbgAssert(!b, "uart_lld_start(), #9", "stream already allocated"); - b = dmaStreamAllocate(uartp->dmatx, - STM32_UART_UART4_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, - (void *)uartp); - chDbgAssert(!b, "uart_lld_start(), #10", "stream already allocated"); - rccEnableUART4(FALSE); - nvicEnableVector(STM32_UART4_NUMBER, - CORTEX_PRIORITY_MASK(STM32_UART_UART4_IRQ_PRIORITY)); - uartp->dmamode |= STM32_DMA_CR_CHSEL(UART4_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_UART_UART4_DMA_PRIORITY); - } -#endif - -#if STM32_UART_USE_UART5 - if (&UARTD5 == uartp) { - bool_t b; - - chDbgAssert((uartp->config->cr2 & STM32_UART45_CR2_CHECK_MASK) == 0, - "uart_lld_start(), #11", - "specified invalid bits in UART5 CR2 register settings"); - chDbgAssert((uartp->config->cr3 & STM32_UART45_CR3_CHECK_MASK) == 0, - "uart_lld_start(), #12", - "specified invalid bits in UART5 CR3 register settings"); - - b = dmaStreamAllocate(uartp->dmarx, - STM32_UART_UART5_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, - (void *)uartp); - chDbgAssert(!b, "uart_lld_start(), #13", "stream already allocated"); - b = dmaStreamAllocate(uartp->dmatx, - STM32_UART_UART5_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, - (void *)uartp); - chDbgAssert(!b, "uart_lld_start(), #14", "stream already allocated"); - rccEnableUART5(FALSE); - nvicEnableVector(STM32_UART5_NUMBER, - CORTEX_PRIORITY_MASK(STM32_UART_UART5_IRQ_PRIORITY)); - uartp->dmamode |= STM32_DMA_CR_CHSEL(UART5_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_UART_UART5_DMA_PRIORITY); - } -#endif - -#if STM32_UART_USE_USART6 - if (&UARTD6 == uartp) { - bool_t b; - b = dmaStreamAllocate(uartp->dmarx, - STM32_UART_USART6_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, - (void *)uartp); - chDbgAssert(!b, "uart_lld_start(), #15", "stream already allocated"); - b = dmaStreamAllocate(uartp->dmatx, - STM32_UART_USART6_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, - (void *)uartp); - chDbgAssert(!b, "uart_lld_start(), #16", "stream already allocated"); - rccEnableUSART6(FALSE); - nvicEnableVector(STM32_USART6_NUMBER, - CORTEX_PRIORITY_MASK(STM32_UART_USART6_IRQ_PRIORITY)); - uartp->dmamode |= STM32_DMA_CR_CHSEL(USART6_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_UART_USART6_DMA_PRIORITY); - } -#endif - - /* Static DMA setup, the transfer size depends on the USART settings, - it is 16 bits if M=1 and PCE=0 else it is 8 bits.*/ - if ((uartp->config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M) - uartp->dmamode |= STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; - dmaStreamSetPeripheral(uartp->dmarx, &uartp->usart->DR); - dmaStreamSetPeripheral(uartp->dmatx, &uartp->usart->DR); - uartp->rxbuf = 0; - } - - uartp->rxstate = UART_RX_IDLE; - uartp->txstate = UART_TX_IDLE; - usart_start(uartp); -} - -/** - * @brief Deactivates the UART peripheral. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @notapi - */ -void uart_lld_stop(UARTDriver *uartp) { - - if (uartp->state == UART_READY) { - usart_stop(uartp); - dmaStreamRelease(uartp->dmarx); - dmaStreamRelease(uartp->dmatx); - -#if STM32_UART_USE_USART1 - if (&UARTD1 == uartp) { - nvicDisableVector(STM32_USART1_NUMBER); - rccDisableUSART1(FALSE); - return; - } -#endif - -#if STM32_UART_USE_USART2 - if (&UARTD2 == uartp) { - nvicDisableVector(STM32_USART2_NUMBER); - rccDisableUSART2(FALSE); - return; - } -#endif - -#if STM32_UART_USE_USART3 - if (&UARTD3 == uartp) { - nvicDisableVector(STM32_USART3_NUMBER); - rccDisableUSART3(FALSE); - return; - } -#endif - -#if STM32_UART_USE_UART4 - if (&UARTD4 == uartp) { - nvicDisableVector(STM32_UART4_NUMBER); - rccDisableUART4(FALSE); - return; - } -#endif - -#if STM32_UART_USE_UART5 - if (&UARTD5 == uartp) { - nvicDisableVector(STM32_UART5_NUMBER); - rccDisableUART5(FALSE); - return; - } -#endif - -#if STM32_UART_USE_USART6 - if (&UARTD6 == uartp) { - nvicDisableVector(STM32_USART6_NUMBER); - rccDisableUSART6(FALSE); - return; - } -#endif - } -} - -/** - * @brief Starts a transmission on the UART peripheral. - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] n number of data frames to send - * @param[in] txbuf the pointer to the transmit buffer - * - * @notapi - */ -void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) { - - /* TX DMA channel preparation and start.*/ - dmaStreamSetMemory0(uartp->dmatx, txbuf); - dmaStreamSetTransactionSize(uartp->dmatx, n); - dmaStreamSetMode(uartp->dmatx, uartp->dmamode | STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE); - dmaStreamEnable(uartp->dmatx); -} - -/** - * @brief Stops any ongoing transmission. - * @note Stopping a transmission also suppresses the transmission callbacks. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @return The number of data frames not transmitted by the - * stopped transmit operation. - * - * @notapi - */ -size_t uart_lld_stop_send(UARTDriver *uartp) { - - dmaStreamDisable(uartp->dmatx); - return dmaStreamGetTransactionSize(uartp->dmatx); -} - -/** - * @brief Starts a receive operation on the UART peripheral. - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] n number of data frames to send - * @param[out] rxbuf the pointer to the receive buffer - * - * @notapi - */ -void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) { - - /* Stopping previous activity (idle state).*/ - dmaStreamDisable(uartp->dmarx); - - /* RX DMA channel preparation and start.*/ - dmaStreamSetMemory0(uartp->dmarx, rxbuf); - dmaStreamSetTransactionSize(uartp->dmarx, n); - dmaStreamSetMode(uartp->dmarx, uartp->dmamode | STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE); - dmaStreamEnable(uartp->dmarx); -} - -/** - * @brief Stops any ongoing receive operation. - * @note Stopping a receive operation also suppresses the receive callbacks. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @return The number of data frames not received by the - * stopped receive operation. - * - * @notapi - */ -size_t uart_lld_stop_receive(UARTDriver *uartp) { - size_t n; - - dmaStreamDisable(uartp->dmarx); - n = dmaStreamGetTransactionSize(uartp->dmarx); - set_rx_idle_loop(uartp); - return n; -} - -#endif /* HAL_USE_UART */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/USARTv1/uart_lld.h b/firmware/chibios/os/hal/platforms/STM32/USARTv1/uart_lld.h deleted file mode 100644 index e70acd6dc0..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/USARTv1/uart_lld.h +++ /dev/null @@ -1,680 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/USARTv1/uart_lld.h - * @brief STM32 low level UART driver header. - * - * @addtogroup UART - * @{ - */ - -#ifndef _UART_LLD_H_ -#define _UART_LLD_H_ - -#if HAL_USE_UART || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief UART driver on USART1 enable switch. - * @details If set to @p TRUE the support for USART1 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_UART_USE_USART1) || defined(__DOXYGEN__) -#define STM32_UART_USE_USART1 FALSE -#endif - -/** - * @brief UART driver on USART2 enable switch. - * @details If set to @p TRUE the support for USART2 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_UART_USE_USART2) || defined(__DOXYGEN__) -#define STM32_UART_USE_USART2 FALSE -#endif - -/** - * @brief UART driver on USART3 enable switch. - * @details If set to @p TRUE the support for USART3 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_UART_USE_USART3) || defined(__DOXYGEN__) -#define STM32_UART_USE_USART3 FALSE -#endif - -/** - * @brief UART driver on UART4 enable switch. - * @details If set to @p TRUE the support for UART4 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_UART_USE_UART4) || defined(__DOXYGEN__) -#define STM32_UART_USE_UART4 FALSE -#endif - -/** - * @brief UART driver on UART5 enable switch. - * @details If set to @p TRUE the support for UART5 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_UART_USE_UART5) || defined(__DOXYGEN__) -#define STM32_UART_USE_UART5 FALSE -#endif - -/** - * @brief UART driver on USART6 enable switch. - * @details If set to @p TRUE the support for USART6 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_UART_USE_USART6) || defined(__DOXYGEN__) -#define STM32_UART_USE_USART6 FALSE -#endif - -/** - * @brief USART1 interrupt priority level setting. - */ -#if !defined(STM32_UART_USART1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART1_IRQ_PRIORITY 12 -#endif - -/** - * @brief USART2 interrupt priority level setting. - */ -#if !defined(STM32_UART_USART2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART2_IRQ_PRIORITY 12 -#endif - -/** - * @brief USART3 interrupt priority level setting. - */ -#if !defined(STM32_UART_USART3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART3_IRQ_PRIORITY 12 -#endif - -/** - * @brief UART4 interrupt priority level setting. - */ -#if !defined(STM32_UART_UART4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_UART4_IRQ_PRIORITY 12 -#endif - -/** - * @brief UART5 interrupt priority level setting. - */ -#if !defined(STM32_UART_UART5_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_UART5_IRQ_PRIORITY 12 -#endif - -/** - * @brief USART6 interrupt priority level setting. - */ -#if !defined(STM32_UART_USART6_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART6_IRQ_PRIORITY 12 -#endif - -/** - * @brief USART1 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA channels but - * because of the channels ordering the RX channel has always priority - * over the TX channel. - */ -#if !defined(STM32_UART_USART1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART1_DMA_PRIORITY 0 -#endif - -/** - * @brief USART2 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA channels but - * because of the channels ordering the RX channel has always priority - * over the TX channel. - */ -#if !defined(STM32_UART_USART2_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART2_DMA_PRIORITY 0 -#endif - -/** - * @brief USART3 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA channels but - * because of the channels ordering the RX channel has always priority - * over the TX channel. - */ -#if !defined(STM32_UART_USART3_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART3_DMA_PRIORITY 0 -#endif - -/** - * @brief UART4 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA channels but - * because of the channels ordering the RX channel has always priority - * over the TX channel. - */ -#if !defined(STM32_UART_UART4_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_UART4_DMA_PRIORITY 0 -#endif - -/** - * @brief UART5 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA channels but - * because of the channels ordering the RX channel has always priority - * over the TX channel. - */ -#if !defined(STM32_UART_UART5_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_UART5_DMA_PRIORITY 0 -#endif - -/** - * @brief USART6 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA channels but - * because of the channels ordering the RX channel has always priority - * over the TX channel. - */ -#if !defined(STM32_UART_USART6_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART6_DMA_PRIORITY 0 -#endif - -/** - * @brief USART DMA error hook. - * @note The default action for DMA errors is a system halt because DMA - * error can only happen because programming errors. - */ -#if !defined(STM32_UART_DMA_ERROR_HOOK) || defined(__DOXYGEN__) -#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() -#endif - -#if STM32_ADVANCED_DMA || defined(__DOXYGEN__) - -/** - * @brief DMA stream used for USART1 RX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_UART_USART1_RX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) -#endif - -/** - * @brief DMA stream used for USART1 TX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_UART_USART1_TX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#endif - -/** - * @brief DMA stream used for USART2 RX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_UART_USART2_RX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#endif - -/** - * @brief DMA stream used for USART2 TX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_UART_USART2_TX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#endif - -/** - * @brief DMA stream used for USART3 RX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_UART_USART3_RX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) -#endif - -/** - * @brief DMA stream used for USART3 TX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_UART_USART3_TX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#endif - -/** - * @brief DMA stream used for UART4 RX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_UART_UART4_RX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#endif - -/** - * @brief DMA stream used for UART4 TX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_UART_UART4_TX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#endif - -/** - * @brief DMA stream used for UART5 RX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_UART_UART5_RX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#endif - -/** - * @brief DMA stream used for UART5 TX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_UART_UART5_TX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#endif - -/** - * @brief DMA stream used for USART6 RX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_UART_USART6_RX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#endif - -/** - * @brief DMA stream used for USART6 TX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_UART_USART6_TX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#endif - -#else /* !STM32_ADVANCED_DMA */ - -/* Fixed streams for platforms using the old DMA peripheral, the values are - valid for both STM32F1xx and STM32L1xx.*/ -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) -#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) - -#endif /* !STM32_ADVANCED_DMA*/ -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_UART_USE_USART1 && !STM32_HAS_USART1 -#error "USART1 not present in the selected device" -#endif - -#if STM32_UART_USE_USART2 && !STM32_HAS_USART2 -#error "USART2 not present in the selected device" -#endif - -#if STM32_UART_USE_USART3 && !STM32_HAS_USART3 -#error "USART3 not present in the selected device" -#endif - -#if STM32_UART_USE_UART4 -#if !STM32_HAS_UART4 -#error "UART4 not present in the selected device" -#endif - -#if !defined(STM32F2XX) && !defined(STM32F4XX) -#error "UART4 DMA access not supported in this platform" -#endif -#endif /* STM32_UART_USE_UART4 */ - -#if STM32_UART_USE_UART5 -#if !STM32_HAS_UART5 -#error "UART5 not present in the selected device" -#endif - -#if !defined(STM32F2XX) && !defined(STM32F4XX) -#error "UART5 DMA access not supported in this platform" -#endif -#endif /* STM32_UART_USE_UART5 */ - -#if STM32_UART_USE_USART6 && !STM32_HAS_USART6 -#error "USART6 not present in the selected device" -#endif - -#if !STM32_UART_USE_USART1 && !STM32_UART_USE_USART2 && \ - !STM32_UART_USE_USART3 && !STM32_UART_USE_UART4 && \ - !STM32_UART_USE_UART5 && !STM32_UART_USE_USART6 -#error "UART driver activated but no USART/UART peripheral assigned" -#endif - -#if STM32_UART_USE_USART1 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_USART1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to USART1" -#endif - -#if STM32_UART_USE_USART2 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_USART2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to USART2" -#endif - -#if STM32_UART_USE_USART3 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_USART3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to USART3" -#endif - -#if STM32_UART_USE_UART4 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_UART4_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to UART4" -#endif - -#if STM32_UART_USE_UART5 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_UART5_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to UART5" -#endif - -#if STM32_UART_USE_USART6 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_USART6_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to USART6" -#endif - -#if STM32_UART_USE_USART1 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART1_DMA_PRIORITY) -#error "Invalid DMA priority assigned to USART1" -#endif - -#if STM32_UART_USE_USART2 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART2_DMA_PRIORITY) -#error "Invalid DMA priority assigned to USART2" -#endif - -#if STM32_UART_USE_USART3 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART3_DMA_PRIORITY) -#error "Invalid DMA priority assigned to USART3" -#endif - -#if STM32_UART_USE_UART4 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_UART4_DMA_PRIORITY) -#error "Invalid DMA priority assigned to UART4" -#endif - -#if STM32_UART_USE_UART5 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_UART5_DMA_PRIORITY) -#error "Invalid DMA priority assigned to UART5" -#endif - -#if STM32_UART_USE_USART6 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART6_DMA_PRIORITY) -#error "Invalid DMA priority assigned to USART6" -#endif - -#if STM32_UART_USE_USART1 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_USART1_RX_DMA_STREAM, \ - STM32_USART1_RX_DMA_MSK) -#error "invalid DMA stream associated to USART1 RX" -#endif - -#if STM32_UART_USE_USART1 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_USART1_TX_DMA_STREAM, \ - STM32_USART1_TX_DMA_MSK) -#error "invalid DMA stream associated to USART1 TX" -#endif - -#if STM32_UART_USE_USART2 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_USART2_RX_DMA_STREAM, \ - STM32_USART2_RX_DMA_MSK) -#error "invalid DMA stream associated to USART2 RX" -#endif - -#if STM32_UART_USE_USART2 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_USART2_TX_DMA_STREAM, \ - STM32_USART2_TX_DMA_MSK) -#error "invalid DMA stream associated to USART2 TX" -#endif - -#if STM32_UART_USE_USART3 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_USART3_RX_DMA_STREAM, \ - STM32_USART3_RX_DMA_MSK) -#error "invalid DMA stream associated to USART3 RX" -#endif - -#if STM32_UART_USE_USART3 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_USART3_TX_DMA_STREAM, \ - STM32_USART3_TX_DMA_MSK) -#error "invalid DMA stream associated to USART3 TX" -#endif - -#if STM32_UART_USE_UART4 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_UART4_RX_DMA_STREAM, \ - STM32_UART4_RX_DMA_MSK) -#error "invalid DMA stream associated to UART4 RX" -#endif - -#if STM32_UART_USE_UART4 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_UART4_TX_DMA_STREAM, \ - STM32_UART4_TX_DMA_MSK) -#error "invalid DMA stream associated to UART4 TX" -#endif - -#if STM32_UART_USE_UART5 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_UART5_RX_DMA_STREAM, \ - STM32_UART5_RX_DMA_MSK) -#error "invalid DMA stream associated to UART5 RX" -#endif - -#if STM32_UART_USE_UART5 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_UART5_TX_DMA_STREAM, \ - STM32_UART5_TX_DMA_MSK) -#error "invalid DMA stream associated to UART5 TX" -#endif - -#if STM32_UART_USE_USART6 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_USART6_RX_DMA_STREAM, \ - STM32_USART6_RX_DMA_MSK) -#error "invalid DMA stream associated to USART6 RX" -#endif - -#if STM32_UART_USE_USART6 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_USART6_TX_DMA_STREAM, \ - STM32_USART6_TX_DMA_MSK) -#error "invalid DMA stream associated to USART6 TX" -#endif - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief UART driver condition flags type. - */ -typedef uint32_t uartflags_t; - -/** - * @brief Structure representing an UART driver. - */ -typedef struct UARTDriver UARTDriver; - -/** - * @brief Generic UART notification callback type. - * - * @param[in] uartp pointer to the @p UARTDriver object - */ -typedef void (*uartcb_t)(UARTDriver *uartp); - -/** - * @brief Character received UART notification callback type. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] c received character - */ -typedef void (*uartccb_t)(UARTDriver *uartp, uint16_t c); - -/** - * @brief Receive error UART notification callback type. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] e receive error mask - */ -typedef void (*uartecb_t)(UARTDriver *uartp, uartflags_t e); - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief End of transmission buffer callback. - */ - uartcb_t txend1_cb; - /** - * @brief Physical end of transmission callback. - */ - uartcb_t txend2_cb; - /** - * @brief Receive buffer filled callback. - */ - uartcb_t rxend_cb; - /** - * @brief Character received while out if the @p UART_RECEIVE state. - */ - uartccb_t rxchar_cb; - /** - * @brief Receive error callback. - */ - uartecb_t rxerr_cb; - /* End of the mandatory fields.*/ - /** - * @brief Bit rate. - */ - uint32_t speed; - /** - * @brief Initialization value for the CR1 register. - */ - uint16_t cr1; - /** - * @brief Initialization value for the CR2 register. - */ - uint16_t cr2; - /** - * @brief Initialization value for the CR3 register. - */ - uint16_t cr3; -} UARTConfig; - -/** - * @brief Structure representing an UART driver. - */ -struct UARTDriver { - /** - * @brief Driver state. - */ - uartstate_t state; - /** - * @brief Transmitter state. - */ - uarttxstate_t txstate; - /** - * @brief Receiver state. - */ - uartrxstate_t rxstate; - /** - * @brief Current configuration data. - */ - const UARTConfig *config; -#if defined(UART_DRIVER_EXT_FIELDS) - UART_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the USART registers block. - */ - USART_TypeDef *usart; - /** - * @brief DMA mode bit mask. - */ - uint32_t dmamode; - /** - * @brief Receive DMA channel. - */ - const stm32_dma_stream_t *dmarx; - /** - * @brief Transmit DMA channel. - */ - const stm32_dma_stream_t *dmatx; - /** - * @brief Default receive buffer while into @p UART_RX_IDLE state. - */ - volatile uint16_t rxbuf; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_UART_USE_USART1 && !defined(__DOXYGEN__) -extern UARTDriver UARTD1; -#endif - -#if STM32_UART_USE_USART2 && !defined(__DOXYGEN__) -extern UARTDriver UARTD2; -#endif - -#if STM32_UART_USE_USART3 && !defined(__DOXYGEN__) -extern UARTDriver UARTD3; -#endif - -#if STM32_UART_USE_UART4 && !defined(__DOXYGEN__) -extern UARTDriver UARTD4; -#endif - -#if STM32_UART_USE_UART5 && !defined(__DOXYGEN__) -extern UARTDriver UARTD5; -#endif - -#if STM32_UART_USE_USART6 && !defined(__DOXYGEN__) -extern UARTDriver UARTD6; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void uart_lld_init(void); - void uart_lld_start(UARTDriver *uartp); - void uart_lld_stop(UARTDriver *uartp); - void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf); - size_t uart_lld_stop_send(UARTDriver *uartp); - void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf); - size_t uart_lld_stop_receive(UARTDriver *uartp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_UART */ - -#endif /* _UART_LLD_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/USARTv2/serial_lld.c b/firmware/chibios/os/hal/platforms/STM32/USARTv2/serial_lld.c deleted file mode 100644 index c19ac260e1..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/USARTv2/serial_lld.c +++ /dev/null @@ -1,534 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/USARTv2/serial_lld.c - * @brief STM32 low level serial driver code. - * - * @addtogroup SERIAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief USART1 serial driver identifier.*/ -#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__) -SerialDriver SD1; -#endif - -/** @brief USART2 serial driver identifier.*/ -#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__) -SerialDriver SD2; -#endif - -/** @brief USART3 serial driver identifier.*/ -#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__) -SerialDriver SD3; -#endif - -/** @brief UART4 serial driver identifier.*/ -#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__) -SerialDriver SD4; -#endif - -/** @brief UART5 serial driver identifier.*/ -#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__) -SerialDriver SD5; -#endif - -/** @brief USART6 serial driver identifier.*/ -#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__) -SerialDriver SD6; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** @brief Driver default configuration.*/ -static const SerialConfig default_config = -{ - SERIAL_DEFAULT_BITRATE, - 0, - USART_CR2_STOP1_BITS | USART_CR2_LINEN, - 0 -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief USART initialization. - * @details This function must be invoked with interrupts disabled. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] config the architecture-dependent serial driver configuration - */ -static void usart_init(SerialDriver *sdp, const SerialConfig *config) { - USART_TypeDef *u = sdp->usart; - - /* Baud rate setting.*/ - u->BRR = (uint16_t)(sdp->clock / config->speed); - - /* Note that some bits are enforced.*/ - u->CR2 = config->cr2 | USART_CR2_LBDIE; - u->CR3 = config->cr3 | USART_CR3_EIE; - u->CR1 = config->cr1 | USART_CR1_UE | USART_CR1_PEIE | - USART_CR1_RXNEIE | USART_CR1_TE | - USART_CR1_RE; - u->ICR = 0xFFFFFFFF; -} - -/** - * @brief USART de-initialization. - * @details This function must be invoked with interrupts disabled. - * - * @param[in] u pointer to an USART I/O block - */ -static void usart_deinit(USART_TypeDef *u) { - - u->CR1 = 0; - u->CR2 = 0; - u->CR3 = 0; -} - -/** - * @brief Error handling routine. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] isr USART ISR register value - */ -static void set_error(SerialDriver *sdp, uint32_t isr) { - flagsmask_t sts = 0; - - if (isr & USART_ISR_ORE) - sts |= SD_OVERRUN_ERROR; - if (isr & USART_ISR_PE) - sts |= SD_PARITY_ERROR; - if (isr & USART_ISR_FE) - sts |= SD_FRAMING_ERROR; - if (isr & USART_ISR_NE) - sts |= SD_NOISE_ERROR; - chSysLockFromIsr(); - chnAddFlagsI(sdp, sts); - chSysUnlockFromIsr(); -} - -/** - * @brief Common IRQ handler. - * - * @param[in] sdp communication channel associated to the USART - */ -static void serve_interrupt(SerialDriver *sdp) { - USART_TypeDef *u = sdp->usart; - uint32_t cr1 = u->CR1; - uint32_t isr; - - /* Reading and clearing status.*/ - isr = u->ISR; - u->ICR = isr; - - /* Error condition detection.*/ - if (isr & (USART_ISR_ORE | USART_ISR_NE | USART_ISR_FE | USART_ISR_PE)) - set_error(sdp, isr); - - /* Special case, LIN break detection.*/ - if (isr & USART_ISR_LBD) { - chSysLockFromIsr(); - chnAddFlagsI(sdp, SD_BREAK_DETECTED); - chSysUnlockFromIsr(); - } - - /* Data available.*/ - if (isr & USART_ISR_RXNE) { - chSysLockFromIsr(); - sdIncomingDataI(sdp, (uint8_t)u->RDR); - chSysUnlockFromIsr(); - } - - /* Transmission buffer empty.*/ - if ((cr1 & USART_CR1_TXEIE) && (isr & USART_ISR_TXE)) { - msg_t b; - chSysLockFromIsr(); - b = chOQGetI(&sdp->oqueue); - if (b < Q_OK) { - chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); - u->CR1 = (cr1 & ~USART_CR1_TXEIE) | USART_CR1_TCIE; - } - else - u->TDR = b; - chSysUnlockFromIsr(); - } - - /* Physical transmission end.*/ - if (isr & USART_ISR_TC) { - chSysLockFromIsr(); - if (chOQIsEmptyI(&sdp->oqueue)) - chnAddFlagsI(sdp, CHN_TRANSMISSION_END); - u->CR1 = cr1 & ~USART_CR1_TCIE; - chSysUnlockFromIsr(); - } -} - -#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__) -static void notify1(GenericQueue *qp) { - - (void)qp; - USART1->CR1 |= USART_CR1_TXEIE; -} -#endif - -#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__) -static void notify2(GenericQueue *qp) { - - (void)qp; - USART2->CR1 |= USART_CR1_TXEIE; -} -#endif - -#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__) -static void notify3(GenericQueue *qp) { - - (void)qp; - USART3->CR1 |= USART_CR1_TXEIE; -} -#endif - -#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__) -static void notify4(GenericQueue *qp) { - - (void)qp; - UART4->CR1 |= USART_CR1_TXEIE; -} -#endif - -#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__) -static void notify5(GenericQueue *qp) { - - (void)qp; - UART5->CR1 |= USART_CR1_TXEIE; -} -#endif - -#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__) -static void notify6(GenericQueue *qp) { - - (void)qp; - USART6->CR1 |= USART_CR1_TXEIE; -} -#endif - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__) -#if !defined(STM32_USART1_HANDLER) -#error "STM32_USART1_HANDLER not defined" -#endif -/** - * @brief USART1 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_USART1_HANDLER) { - - CH_IRQ_PROLOGUE(); - - serve_interrupt(&SD1); - - CH_IRQ_EPILOGUE(); -} -#endif - -#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__) -#if !defined(STM32_USART2_HANDLER) -#error "STM32_USART2_HANDLER not defined" -#endif -/** - * @brief USART2 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_USART2_HANDLER) { - - CH_IRQ_PROLOGUE(); - - serve_interrupt(&SD2); - - CH_IRQ_EPILOGUE(); -} -#endif - -#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__) -#if !defined(STM32_USART3_HANDLER) -#error "STM32_USART3_HANDLER not defined" -#endif -/** - * @brief USART3 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_USART3_HANDLER) { - - CH_IRQ_PROLOGUE(); - - serve_interrupt(&SD3); - - CH_IRQ_EPILOGUE(); -} -#endif - -#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__) -#if !defined(STM32_UART4_HANDLER) -#error "STM32_UART4_HANDLER not defined" -#endif -/** - * @brief UART4 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_UART4_HANDLER) { - - CH_IRQ_PROLOGUE(); - - serve_interrupt(&SD4); - - CH_IRQ_EPILOGUE(); -} -#endif - -#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__) -#if !defined(STM32_UART5_HANDLER) -#error "STM32_UART5_HANDLER not defined" -#endif -/** - * @brief UART5 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_UART5_HANDLER) { - - CH_IRQ_PROLOGUE(); - - serve_interrupt(&SD5); - - CH_IRQ_EPILOGUE(); -} -#endif - -#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__) -#if !defined(STM32_USART6_HANDLER) -#error "STM32_USART6_HANDLER not defined" -#endif -/** - * @brief USART1 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_USART6_HANDLER) { - - CH_IRQ_PROLOGUE(); - - serve_interrupt(&SD6); - - CH_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level serial driver initialization. - * - * @notapi - */ -void sd_lld_init(void) { - -#if STM32_SERIAL_USE_USART1 - sdObjectInit(&SD1, NULL, notify1); - SD1.usart = USART1; - SD1.clock = STM32_USART1CLK; -#endif - -#if STM32_SERIAL_USE_USART2 - sdObjectInit(&SD2, NULL, notify2); - SD2.usart = USART2; - SD2.clock = STM32_USART2CLK; -#endif - -#if STM32_SERIAL_USE_USART3 - sdObjectInit(&SD3, NULL, notify3); - SD3.usart = USART3; - SD3.clock = STM32_USART3CLK; -#endif - -#if STM32_SERIAL_USE_UART4 - sdObjectInit(&SD4, NULL, notify4); - SD4.usart = UART4; - SD4.clock = STM32_UART4CLK; -#endif - -#if STM32_SERIAL_USE_UART5 - sdObjectInit(&SD5, NULL, notify5); - SD5.usart = UART5; - SD5.clock = STM32_UART5CLK; -#endif - -#if STM32_SERIAL_USE_USART6 - sdObjectInit(&SD6, NULL, notify6); - SD6.usart = USART6; - SD6.clock = STM32_USART6CLK; -#endif -} - -/** - * @brief Low level serial driver configuration and (re)start. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] config the architecture-dependent serial driver configuration. - * If this parameter is set to @p NULL then a default - * configuration is used. - * - * @notapi - */ -void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { - - if (config == NULL) - config = &default_config; - - if (sdp->state == SD_STOP) { -#if STM32_SERIAL_USE_USART1 - if (&SD1 == sdp) { - rccEnableUSART1(FALSE); - nvicEnableVector(STM32_USART1_NUMBER, - CORTEX_PRIORITY_MASK(STM32_SERIAL_USART1_PRIORITY)); - } -#endif -#if STM32_SERIAL_USE_USART2 - if (&SD2 == sdp) { - rccEnableUSART2(FALSE); - nvicEnableVector(STM32_USART2_NUMBER, - CORTEX_PRIORITY_MASK(STM32_SERIAL_USART2_PRIORITY)); - } -#endif -#if STM32_SERIAL_USE_USART3 - if (&SD3 == sdp) { - rccEnableUSART3(FALSE); - nvicEnableVector(STM32_USART3_NUMBER, - CORTEX_PRIORITY_MASK(STM32_SERIAL_USART3_PRIORITY)); - } -#endif -#if STM32_SERIAL_USE_UART4 - if (&SD4 == sdp) { - rccEnableUART4(FALSE); - nvicEnableVector(STM32_UART4_NUMBER, - CORTEX_PRIORITY_MASK(STM32_SERIAL_UART4_PRIORITY)); - } -#endif -#if STM32_SERIAL_USE_UART5 - if (&SD5 == sdp) { - rccEnableUART5(FALSE); - nvicEnableVector(STM32_UART5_NUMBER, - CORTEX_PRIORITY_MASK(STM32_SERIAL_UART5_PRIORITY)); - } -#endif -#if STM32_SERIAL_USE_USART6 - if (&SD6 == sdp) { - rccEnableUSART6(FALSE); - nvicEnableVector(STM32_USART6_NUMBER, - CORTEX_PRIORITY_MASK(STM32_SERIAL_USART6_PRIORITY)); - } -#endif - } - usart_init(sdp, config); -} - -/** - * @brief Low level serial driver stop. - * @details De-initializes the USART, stops the associated clock, resets the - * interrupt vector. - * - * @param[in] sdp pointer to a @p SerialDriver object - * - * @notapi - */ -void sd_lld_stop(SerialDriver *sdp) { - - if (sdp->state == SD_READY) { - usart_deinit(sdp->usart); -#if STM32_SERIAL_USE_USART1 - if (&SD1 == sdp) { - rccDisableUSART1(FALSE); - nvicDisableVector(STM32_USART1_NUMBER); - return; - } -#endif -#if STM32_SERIAL_USE_USART2 - if (&SD2 == sdp) { - rccDisableUSART2(FALSE); - nvicDisableVector(STM32_USART2_NUMBER); - return; - } -#endif -#if STM32_SERIAL_USE_USART3 - if (&SD3 == sdp) { - rccDisableUSART3(FALSE); - nvicDisableVector(STM32_USART3_NUMBER); - return; - } -#endif -#if STM32_SERIAL_USE_UART4 - if (&SD4 == sdp) { - rccDisableUART4(FALSE); - nvicDisableVector(STM32_UART4_NUMBER); - return; - } -#endif -#if STM32_SERIAL_USE_UART5 - if (&SD5 == sdp) { - rccDisableUART5(FALSE); - nvicDisableVector(STM32_UART5_NUMBER); - return; - } -#endif -#if STM32_SERIAL_USE_USART6 - if (&SD6 == sdp) { - rccDisableUSART6(FALSE); - nvicDisableVector(STM32_USART6_NUMBER); - return; - } -#endif - } -} - -#endif /* HAL_USE_SERIAL */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/USARTv2/serial_lld.h b/firmware/chibios/os/hal/platforms/STM32/USARTv2/serial_lld.h deleted file mode 100644 index 003e200b61..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/USARTv2/serial_lld.h +++ /dev/null @@ -1,305 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/USARTv2/serial_lld.h - * @brief STM32 low level serial driver header. - * - * @addtogroup SERIAL - * @{ - */ - -#ifndef _SERIAL_LLD_H_ -#define _SERIAL_LLD_H_ - -#if HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief USART1 driver enable switch. - * @details If set to @p TRUE the support for USART1 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_SERIAL_USE_USART1) || defined(__DOXYGEN__) -#define STM32_SERIAL_USE_USART1 FALSE -#endif - -/** - * @brief USART2 driver enable switch. - * @details If set to @p TRUE the support for USART2 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_SERIAL_USE_USART2) || defined(__DOXYGEN__) -#define STM32_SERIAL_USE_USART2 FALSE -#endif - -/** - * @brief USART3 driver enable switch. - * @details If set to @p TRUE the support for USART3 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_SERIAL_USE_USART3) || defined(__DOXYGEN__) -#define STM32_SERIAL_USE_USART3 FALSE -#endif - -/** - * @brief UART4 driver enable switch. - * @details If set to @p TRUE the support for UART4 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_SERIAL_USE_UART4) || defined(__DOXYGEN__) -#define STM32_SERIAL_USE_UART4 FALSE -#endif - -/** - * @brief UART5 driver enable switch. - * @details If set to @p TRUE the support for UART5 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_SERIAL_USE_UART5) || defined(__DOXYGEN__) -#define STM32_SERIAL_USE_UART5 FALSE -#endif - -/** - * @brief USART6 driver enable switch. - * @details If set to @p TRUE the support for USART6 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_SERIAL_USE_USART6) || defined(__DOXYGEN__) -#define STM32_SERIAL_USE_USART6 FALSE -#endif - -/** - * @brief USART1 interrupt priority level setting. - */ -#if !defined(STM32_SERIAL_USART1_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SERIAL_USART1_PRIORITY 12 -#endif - -/** - * @brief USART2 interrupt priority level setting. - */ -#if !defined(STM32_SERIAL_USART2_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SERIAL_USART2_PRIORITY 12 -#endif - -/** - * @brief USART3 interrupt priority level setting. - */ -#if !defined(STM32_SERIAL_USART3_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SERIAL_USART3_PRIORITY 12 -#endif - -/** - * @brief UART4 interrupt priority level setting. - */ -#if !defined(STM32_SERIAL_UART4_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SERIAL_UART4_PRIORITY 12 -#endif - -/** - * @brief UART5 interrupt priority level setting. - */ -#if !defined(STM32_SERIAL_UART5_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SERIAL_UART5_PRIORITY 12 -#endif - -/** - * @brief USART6 interrupt priority level setting. - */ -#if !defined(STM32_SERIAL_USART6_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SERIAL_USART6_PRIORITY 12 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_SERIAL_USE_USART1 && !STM32_HAS_USART1 -#error "USART1 not present in the selected device" -#endif - -#if STM32_SERIAL_USE_USART2 && !STM32_HAS_USART2 -#error "USART2 not present in the selected device" -#endif - -#if STM32_SERIAL_USE_USART3 && !STM32_HAS_USART3 -#error "USART3 not present in the selected device" -#endif - -#if STM32_SERIAL_USE_UART4 && !STM32_HAS_UART4 -#error "UART4 not present in the selected device" -#endif - -#if STM32_SERIAL_USE_UART5 && !STM32_HAS_UART5 -#error "UART5 not present in the selected device" -#endif - -#if STM32_SERIAL_USE_USART6 && !STM32_HAS_USART6 -#error "USART6 not present in the selected device" -#endif - -#if !STM32_SERIAL_USE_USART1 && !STM32_SERIAL_USE_USART2 && \ - !STM32_SERIAL_USE_USART3 && !STM32_SERIAL_USE_UART4 && \ - !STM32_SERIAL_USE_UART5 && !STM32_SERIAL_USE_USART6 -#error "SERIAL driver activated but no USART/UART peripheral assigned" -#endif - -#if STM32_SERIAL_USE_USART1 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART1_PRIORITY) -#error "Invalid IRQ priority assigned to USART1" -#endif - -#if STM32_SERIAL_USE_USART2 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART2_PRIORITY) -#error "Invalid IRQ priority assigned to USART2" -#endif - -#if STM32_SERIAL_USE_USART3 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART3_PRIORITY) -#error "Invalid IRQ priority assigned to USART3" -#endif - -#if STM32_SERIAL_USE_UART4 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_UART4_PRIORITY) -#error "Invalid IRQ priority assigned to UART4" -#endif - -#if STM32_SERIAL_USE_UART5 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_UART5_PRIORITY) -#error "Invalid IRQ priority assigned to UART5" -#endif - -#if STM32_SERIAL_USE_USART6 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART6_PRIORITY) -#error "Invalid IRQ priority assigned to USART6" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief STM32 Serial Driver configuration structure. - * @details An instance of this structure must be passed to @p sdStart() - * in order to configure and start a serial driver operations. - * @note This structure content is architecture dependent, each driver - * implementation defines its own version and the custom static - * initializers. - */ -typedef struct { - /** - * @brief Bit rate. - */ - uint32_t speed; - /* End of the mandatory fields.*/ - /** - * @brief Initialization value for the CR1 register. - */ - uint32_t cr1; - /** - * @brief Initialization value for the CR2 register. - */ - uint32_t cr2; - /** - * @brief Initialization value for the CR3 register. - */ - uint32_t cr3; -} SerialConfig; - -/** - * @brief @p SerialDriver specific data. - */ -#define _serial_driver_data \ - _base_asynchronous_channel_data \ - /* Driver state.*/ \ - sdstate_t state; \ - /* Input queue.*/ \ - InputQueue iqueue; \ - /* Output queue.*/ \ - OutputQueue oqueue; \ - /* Input circular buffer.*/ \ - uint8_t ib[SERIAL_BUFFERS_SIZE]; \ - /* Output circular buffer.*/ \ - uint8_t ob[SERIAL_BUFFERS_SIZE]; \ - /* End of the mandatory fields.*/ \ - /* Pointer to the USART registers block.*/ \ - USART_TypeDef *usart; \ - /* Clock frequency for the associated USART/UART.*/ \ - uint32_t clock; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/* - * Extra USARTs definitions here (missing from the ST header file). - */ -#define USART_CR2_STOP1_BITS (0 << 12) /**< @brief CR2 1 stop bit value.*/ -#define USART_CR2_STOP0P5_BITS (1 << 12) /**< @brief CR2 0.5 stop bit value.*/ -#define USART_CR2_STOP2_BITS (2 << 12) /**< @brief CR2 2 stop bit value.*/ -#define USART_CR2_STOP1P5_BITS (3 << 12) /**< @brief CR2 1.5 stop bit value.*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_SERIAL_USE_USART1 && !defined(__DOXYGEN__) -extern SerialDriver SD1; -#endif -#if STM32_SERIAL_USE_USART2 && !defined(__DOXYGEN__) -extern SerialDriver SD2; -#endif -#if STM32_SERIAL_USE_USART3 && !defined(__DOXYGEN__) -extern SerialDriver SD3; -#endif -#if STM32_SERIAL_USE_UART4 && !defined(__DOXYGEN__) -extern SerialDriver SD4; -#endif -#if STM32_SERIAL_USE_UART5 && !defined(__DOXYGEN__) -extern SerialDriver SD5; -#endif -#if STM32_SERIAL_USE_USART6 && !defined(__DOXYGEN__) -extern SerialDriver SD6; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void sd_lld_init(void); - void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); - void sd_lld_stop(SerialDriver *sdp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_SERIAL */ - -#endif /* _SERIAL_LLD_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/USARTv2/uart_lld.c b/firmware/chibios/os/hal/platforms/STM32/USARTv2/uart_lld.c deleted file mode 100644 index 72a0857e18..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/USARTv2/uart_lld.c +++ /dev/null @@ -1,604 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/USARTv2/uart_lld.c - * @brief STM32 low level UART driver code. - * - * @addtogroup UART - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_UART || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define USART1_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_USART1_RX_DMA_STREAM, \ - STM32_USART1_RX_DMA_CHN) - -#define USART1_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_USART1_TX_DMA_STREAM, \ - STM32_USART1_TX_DMA_CHN) - -#define USART2_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_USART2_RX_DMA_STREAM, \ - STM32_USART2_RX_DMA_CHN) - -#define USART2_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_USART2_TX_DMA_STREAM, \ - STM32_USART2_TX_DMA_CHN) - -#define USART3_RX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_USART3_RX_DMA_STREAM, \ - STM32_USART3_RX_DMA_CHN) - -#define USART3_TX_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_UART_USART3_TX_DMA_STREAM, \ - STM32_USART3_TX_DMA_CHN) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief USART1 UART driver identifier.*/ -#if STM32_UART_USE_USART1 || defined(__DOXYGEN__) -UARTDriver UARTD1; -#endif - -/** @brief USART2 UART driver identifier.*/ -#if STM32_UART_USE_USART2 || defined(__DOXYGEN__) -UARTDriver UARTD2; -#endif - -/** @brief USART3 UART driver identifier.*/ -#if STM32_UART_USE_USART3 || defined(__DOXYGEN__) -UARTDriver UARTD3; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Status bits translation. - * - * @param[in] sr USART SR register value - * - * @return The error flags. - */ -static uartflags_t translate_errors(uint32_t isr) { - uartflags_t sts = 0; - - if (isr & USART_ISR_ORE) - sts |= UART_OVERRUN_ERROR; - if (isr & USART_ISR_PE) - sts |= UART_PARITY_ERROR; - if (isr & USART_ISR_FE) - sts |= UART_FRAMING_ERROR; - if (isr & USART_ISR_NE) - sts |= UART_NOISE_ERROR; - if (isr & USART_ISR_LBD) - sts |= UART_BREAK_DETECTED; - return sts; -} - -/** - * @brief Puts the receiver in the UART_RX_IDLE state. - * - * @param[in] uartp pointer to the @p UARTDriver object - */ -static void set_rx_idle_loop(UARTDriver *uartp) { - uint32_t mode; - - /* RX DMA channel preparation, if the char callback is defined then the - TCIE interrupt is enabled too.*/ - if (uartp->config->rxchar_cb == NULL) - mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC; - else - mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC | STM32_DMA_CR_TCIE; - dmaStreamSetMemory0(uartp->dmarx, &uartp->rxbuf); - dmaStreamSetTransactionSize(uartp->dmarx, 1); - dmaStreamSetMode(uartp->dmarx, uartp->dmamode | mode); - dmaStreamEnable(uartp->dmarx); -} - -/** - * @brief USART de-initialization. - * @details This function must be invoked with interrupts disabled. - * - * @param[in] uartp pointer to the @p UARTDriver object - */ -static void usart_stop(UARTDriver *uartp) { - - /* Stops RX and TX DMA channels.*/ - dmaStreamDisable(uartp->dmarx); - dmaStreamDisable(uartp->dmatx); - - /* Stops USART operations.*/ - uartp->usart->CR1 = 0; - uartp->usart->CR2 = 0; - uartp->usart->CR3 = 0; -} - -/** - * @brief USART initialization. - * @details This function must be invoked with interrupts disabled. - * - * @param[in] uartp pointer to the @p UARTDriver object - */ -static void usart_start(UARTDriver *uartp) { - uint32_t cr1; - USART_TypeDef *u = uartp->usart; - - /* Defensive programming, starting from a clean state.*/ - usart_stop(uartp); - - /* Baud rate setting.*/ -#if defined(STM32F0XX) - if (uartp->usart == USART1) - u->BRR = STM32_USART1CLK / uartp->config->speed; - else - u->BRR = STM32_PCLK / uartp->config->speed; -#else /* !defined(STM32F0XX) */ - if (uartp->usart == USART1) - u->BRR = STM32_PCLK2 / uartp->config->speed; - else - u->BRR = STM32_PCLK1 / uartp->config->speed; -#endif /* !defined(STM32F0XX) */ - - /* Resetting eventual pending status flags.*/ - u->ICR = 0xFFFFFFFF; - - /* Note that some bits are enforced because required for correct driver - operations.*/ - u->CR2 = uartp->config->cr2 | USART_CR2_LBDIE; - u->CR3 = uartp->config->cr3 | USART_CR3_DMAT | USART_CR3_DMAR | - USART_CR3_EIE; - - /* Mustn't ever set TCIE here - if done, it causes an immediate - interrupt.*/ - cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE; - u->CR1 = uartp->config->cr1 | cr1; - - /* Starting the receiver idle loop.*/ - set_rx_idle_loop(uartp); -} - -/** - * @brief RX DMA common service routine. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] flags pre-shifted content of the ISR register - */ -static void uart_lld_serve_rx_end_irq(UARTDriver *uartp, uint32_t flags) { - - /* DMA errors handling.*/ -#if defined(STM32_UART_DMA_ERROR_HOOK) - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - STM32_UART_DMA_ERROR_HOOK(uartp); - } -#else - (void)flags; -#endif - - if (uartp->rxstate == UART_RX_IDLE) { - /* Receiver in idle state, a callback is generated, if enabled, for each - received character and then the driver stays in the same state.*/ - if (uartp->config->rxchar_cb != NULL) - uartp->config->rxchar_cb(uartp, uartp->rxbuf); - } - else { - /* Receiver in active state, a callback is generated, if enabled, after - a completed transfer.*/ - dmaStreamDisable(uartp->dmarx); - uartp->rxstate = UART_RX_COMPLETE; - if (uartp->config->rxend_cb != NULL) - uartp->config->rxend_cb(uartp); - - /* If the callback didn't explicitly change state then the receiver - automatically returns to the idle state.*/ - if (uartp->rxstate == UART_RX_COMPLETE) { - uartp->rxstate = UART_RX_IDLE; - set_rx_idle_loop(uartp); - } - } -} - -/** - * @brief TX DMA common service routine. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] flags pre-shifted content of the ISR register - */ -static void uart_lld_serve_tx_end_irq(UARTDriver *uartp, uint32_t flags) { - - /* DMA errors handling.*/ -#if defined(STM32_UART_DMA_ERROR_HOOK) - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - STM32_UART_DMA_ERROR_HOOK(uartp); - } -#else - (void)flags; -#endif - - dmaStreamDisable(uartp->dmatx); - - /* Only enable TC interrupt if there's a callback attached to it. - We have to do it here, rather than earlier, because TC flag is set - until transmission starts.*/ - if (uartp->config->txend2_cb != NULL) - uartp->usart->CR1 |= USART_CR1_TCIE; - - /* A callback is generated, if enabled, after a completed transfer.*/ - uartp->txstate = UART_TX_COMPLETE; - if (uartp->config->txend1_cb != NULL) - uartp->config->txend1_cb(uartp); - - /* If the callback didn't explicitly change state then the transmitter - automatically returns to the idle state.*/ - if (uartp->txstate == UART_TX_COMPLETE) - uartp->txstate = UART_TX_IDLE; -} - -/** - * @brief USART common service routine. - * - * @param[in] uartp pointer to the @p UARTDriver object - */ -static void serve_usart_irq(UARTDriver *uartp) { - uint32_t isr; - USART_TypeDef *u = uartp->usart; - uint32_t cr1 = u->CR1; - - /* Reading and clearing status.*/ - isr = u->ISR; - u->ICR = isr; - - if (isr & (USART_ISR_LBD | USART_ISR_ORE | USART_ISR_NE | - USART_ISR_FE | USART_ISR_PE)) { - if (uartp->config->rxerr_cb != NULL) - uartp->config->rxerr_cb(uartp, translate_errors(isr)); - } - - if ((isr & USART_ISR_TC) && (cr1 & USART_CR1_TCIE)) { - /* TC interrupt disabled.*/ - u->CR1 = cr1 & ~USART_CR1_TCIE; - - /* End of transmission, a callback is generated.*/ - if (uartp->config->txend2_cb != NULL) - uartp->config->txend2_cb(uartp); - } -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if STM32_UART_USE_USART1 || defined(__DOXYGEN__) -#if !defined(STM32_USART1_HANDLER) -#error "STM32_USART1_HANDLER not defined" -#endif -/** - * @brief USART1 IRQ handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_USART1_HANDLER) { - - CH_IRQ_PROLOGUE(); - - serve_usart_irq(&UARTD1); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_UART_USE_USART1 */ - -#if STM32_UART_USE_USART2 || defined(__DOXYGEN__) -#if !defined(STM32_USART2_HANDLER) -#error "STM32_USART2_HANDLER not defined" -#endif -/** - * @brief USART2 IRQ handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_USART2_HANDLER) { - - CH_IRQ_PROLOGUE(); - - serve_usart_irq(&UARTD2); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_UART_USE_USART2 */ - -#if STM32_UART_USE_USART3 || defined(__DOXYGEN__) -#if !defined(STM32_USART3_HANDLER) -#error "STM32_USART3_HANDLER not defined" -#endif -/** - * @brief USART3 IRQ handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_USART3_HANDLER) { - - CH_IRQ_PROLOGUE(); - - serve_usart_irq(&UARTD3); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_UART_USE_USART3 */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level UART driver initialization. - * - * @notapi - */ -void uart_lld_init(void) { - -#if STM32_UART_USE_USART1 - uartObjectInit(&UARTD1); - UARTD1.usart = USART1; - UARTD1.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; - UARTD1.dmarx = STM32_DMA_STREAM(STM32_UART_USART1_RX_DMA_STREAM); - UARTD1.dmatx = STM32_DMA_STREAM(STM32_UART_USART1_TX_DMA_STREAM); -#endif - -#if STM32_UART_USE_USART2 - uartObjectInit(&UARTD2); - UARTD2.usart = USART2; - UARTD2.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; - UARTD2.dmarx = STM32_DMA_STREAM(STM32_UART_USART2_RX_DMA_STREAM); - UARTD2.dmatx = STM32_DMA_STREAM(STM32_UART_USART2_TX_DMA_STREAM); -#endif - -#if STM32_UART_USE_USART3 - uartObjectInit(&UARTD3); - UARTD3.usart = USART3; - UARTD3.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; - UARTD3.dmarx = STM32_DMA_STREAM(STM32_UART_USART3_RX_DMA_STREAM); - UARTD3.dmatx = STM32_DMA_STREAM(STM32_UART_USART3_TX_DMA_STREAM); -#endif -} - -/** - * @brief Configures and activates the UART peripheral. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @notapi - */ -void uart_lld_start(UARTDriver *uartp) { - - if (uartp->state == UART_STOP) { -#if STM32_UART_USE_USART1 - if (&UARTD1 == uartp) { - bool_t b; - b = dmaStreamAllocate(uartp->dmarx, - STM32_UART_USART1_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, - (void *)uartp); - chDbgAssert(!b, "uart_lld_start(), #1", "stream already allocated"); - b = dmaStreamAllocate(uartp->dmatx, - STM32_UART_USART1_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, - (void *)uartp); - chDbgAssert(!b, "uart_lld_start(), #2", "stream already allocated"); - rccEnableUSART1(FALSE); - nvicEnableVector(STM32_USART1_NUMBER, - CORTEX_PRIORITY_MASK(STM32_UART_USART1_IRQ_PRIORITY)); - uartp->dmamode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY); - } -#endif - -#if STM32_UART_USE_USART2 - if (&UARTD2 == uartp) { - bool_t b; - b = dmaStreamAllocate(uartp->dmarx, - STM32_UART_USART2_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, - (void *)uartp); - chDbgAssert(!b, "uart_lld_start(), #3", "stream already allocated"); - b = dmaStreamAllocate(uartp->dmatx, - STM32_UART_USART2_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, - (void *)uartp); - chDbgAssert(!b, "uart_lld_start(), #4", "stream already allocated"); - rccEnableUSART2(FALSE); - nvicEnableVector(STM32_USART2_NUMBER, - CORTEX_PRIORITY_MASK(STM32_UART_USART2_IRQ_PRIORITY)); - uartp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY); - } -#endif - -#if STM32_UART_USE_USART3 - if (&UARTD3 == uartp) { - bool_t b; - b = dmaStreamAllocate(uartp->dmarx, - STM32_UART_USART3_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, - (void *)uartp); - chDbgAssert(!b, "uart_lld_start(), #5", "stream already allocated"); - b = dmaStreamAllocate(uartp->dmatx, - STM32_UART_USART3_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, - (void *)uartp); - chDbgAssert(!b, "uart_lld_start(), #6", "stream already allocated"); - rccEnableUSART3(FALSE); - nvicEnableVector(STM32_USART3_NUMBER, - CORTEX_PRIORITY_MASK(STM32_UART_USART3_IRQ_PRIORITY)); - uartp->dmamode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY); - } -#endif - - /* Static DMA setup, the transfer size depends on the USART settings, - it is 16 bits if M=1 and PCE=0 else it is 8 bits.*/ - if ((uartp->config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M) - uartp->dmamode |= STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; - dmaStreamSetPeripheral(uartp->dmarx, &uartp->usart->RDR); - dmaStreamSetPeripheral(uartp->dmatx, &uartp->usart->TDR); - uartp->rxbuf = 0; - } - - uartp->rxstate = UART_RX_IDLE; - uartp->txstate = UART_TX_IDLE; - usart_start(uartp); -} - -/** - * @brief Deactivates the UART peripheral. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @notapi - */ -void uart_lld_stop(UARTDriver *uartp) { - - if (uartp->state == UART_READY) { - usart_stop(uartp); - dmaStreamRelease(uartp->dmarx); - dmaStreamRelease(uartp->dmatx); - -#if STM32_UART_USE_USART1 - if (&UARTD1 == uartp) { - nvicDisableVector(STM32_USART1_NUMBER); - rccDisableUSART1(FALSE); - return; - } -#endif - -#if STM32_UART_USE_USART2 - if (&UARTD2 == uartp) { - nvicDisableVector(STM32_USART2_NUMBER); - rccDisableUSART2(FALSE); - return; - } -#endif - -#if STM32_UART_USE_USART3 - if (&UARTD3 == uartp) { - nvicDisableVector(STM32_USART3_NUMBER); - rccDisableUSART3(FALSE); - return; - } -#endif - } -} - -/** - * @brief Starts a transmission on the UART peripheral. - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] n number of data frames to send - * @param[in] txbuf the pointer to the transmit buffer - * - * @notapi - */ -void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) { - - /* TX DMA channel preparation and start.*/ - dmaStreamSetMemory0(uartp->dmatx, txbuf); - dmaStreamSetTransactionSize(uartp->dmatx, n); - dmaStreamSetMode(uartp->dmatx, uartp->dmamode | STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE); - dmaStreamEnable(uartp->dmatx); -} - -/** - * @brief Stops any ongoing transmission. - * @note Stopping a transmission also suppresses the transmission callbacks. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @return The number of data frames not transmitted by the - * stopped transmit operation. - * - * @notapi - */ -size_t uart_lld_stop_send(UARTDriver *uartp) { - - dmaStreamDisable(uartp->dmatx); - return dmaStreamGetTransactionSize(uartp->dmatx); -} - -/** - * @brief Starts a receive operation on the UART peripheral. - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] n number of data frames to send - * @param[out] rxbuf the pointer to the receive buffer - * - * @notapi - */ -void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) { - - /* Stopping previous activity (idle state).*/ - dmaStreamDisable(uartp->dmarx); - - /* RX DMA channel preparation and start.*/ - dmaStreamSetMemory0(uartp->dmarx, rxbuf); - dmaStreamSetTransactionSize(uartp->dmarx, n); - dmaStreamSetMode(uartp->dmarx, uartp->dmamode | STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE); - dmaStreamEnable(uartp->dmarx); -} - -/** - * @brief Stops any ongoing receive operation. - * @note Stopping a receive operation also suppresses the receive callbacks. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @return The number of data frames not received by the - * stopped receive operation. - * - * @notapi - */ -size_t uart_lld_stop_receive(UARTDriver *uartp) { - size_t n; - - dmaStreamDisable(uartp->dmarx); - n = dmaStreamGetTransactionSize(uartp->dmarx); - set_rx_idle_loop(uartp); - return n; -} - -#endif /* HAL_USE_UART */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/USARTv2/uart_lld.h b/firmware/chibios/os/hal/platforms/STM32/USARTv2/uart_lld.h deleted file mode 100644 index 8d8392f2a6..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/USARTv2/uart_lld.h +++ /dev/null @@ -1,458 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/USARTv2/uart_lld.h - * @brief STM32 low level UART driver header. - * - * @addtogroup UART - * @{ - */ - -#ifndef _UART_LLD_H_ -#define _UART_LLD_H_ - -#if HAL_USE_UART || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief UART driver on USART1 enable switch. - * @details If set to @p TRUE the support for USART1 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_UART_USE_USART1) || defined(__DOXYGEN__) -#define STM32_UART_USE_USART1 FALSE -#endif - -/** - * @brief UART driver on USART2 enable switch. - * @details If set to @p TRUE the support for USART2 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_UART_USE_USART2) || defined(__DOXYGEN__) -#define STM32_UART_USE_USART2 FALSE -#endif - -/** - * @brief UART driver on USART3 enable switch. - * @details If set to @p TRUE the support for USART3 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_UART_USE_USART3) || defined(__DOXYGEN__) -#define STM32_UART_USE_USART3 FALSE -#endif - -/** - * @brief USART1 interrupt priority level setting. - */ -#if !defined(STM32_UART_USART1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART1_IRQ_PRIORITY 12 -#endif - -/** - * @brief USART2 interrupt priority level setting. - */ -#if !defined(STM32_UART_USART2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART2_IRQ_PRIORITY 12 -#endif - -/** - * @brief USART3 interrupt priority level setting. - */ -#if !defined(STM32_UART_USART3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART3_IRQ_PRIORITY 12 -#endif - -/** - * @brief USART1 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA channels but - * because of the channels ordering the RX channel has always priority - * over the TX channel. - */ -#if !defined(STM32_UART_USART1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART1_DMA_PRIORITY 0 -#endif - -/** - * @brief USART2 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA channels but - * because of the channels ordering the RX channel has always priority - * over the TX channel. - */ -#if !defined(STM32_UART_USART2_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART2_DMA_PRIORITY 0 -#endif - -/** - * @brief USART3 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA channels but - * because of the channels ordering the RX channel has always priority - * over the TX channel. - */ -#if !defined(STM32_UART_USART3_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART3_DMA_PRIORITY 0 -#endif - -/** - * @brief USART1 DMA error hook. - * @note The default action for DMA errors is a system halt because DMA - * error can only happen because programming errors. - */ -#if !defined(STM32_UART_DMA_ERROR_HOOK) || defined(__DOXYGEN__) -#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() -#endif - -#if STM32_ADVANCED_DMA || defined(__DOXYGEN__) - -/** - * @brief DMA stream used for USART1 RX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_UART_USART1_RX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) -#endif - -/** - * @brief DMA stream used for USART1 TX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_UART_USART1_TX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#endif - -/** - * @brief DMA stream used for USART2 RX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_UART_USART2_RX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#endif - -/** - * @brief DMA stream used for USART2 TX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_UART_USART2_TX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#endif - -/** - * @brief DMA stream used for USART3 RX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_UART_USART3_RX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) -#endif - -/** - * @brief DMA stream used for USART3 TX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_UART_USART3_TX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#endif - -#else /* !STM32_ADVANCED_DMA*/ - -#if defined(STM32F0XX) -/* Fixed values for STM32F0xx devices.*/ -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#endif /* defined(STM32F0XX) */ - -#if defined(STM32F30X)|| defined(STM32F37X) -/* Fixed values for STM32F3xx devices.*/ -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#endif /* defined(STM32F30X) */ - -#endif /* !STM32_ADVANCED_DMA*/ -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_UART_USE_USART1 && !STM32_HAS_USART1 -#error "USART1 not present in the selected device" -#endif - -#if STM32_UART_USE_USART2 && !STM32_HAS_USART2 -#error "USART2 not present in the selected device" -#endif - -#if STM32_UART_USE_USART3 && !STM32_HAS_USART3 -#error "USART3 not present in the selected device" -#endif - -#if !STM32_UART_USE_USART1 && !STM32_UART_USE_USART2 && \ - !STM32_UART_USE_USART3 -#error "UART driver activated but no USART/UART peripheral assigned" -#endif - -#if STM32_UART_USE_USART1 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_USART1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to USART1" -#endif - -#if STM32_UART_USE_USART2 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_USART2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to USART2" -#endif - -#if STM32_UART_USE_USART3 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_USART3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to USART3" -#endif - -#if STM32_UART_USE_USART1 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART1_DMA_PRIORITY) -#error "Invalid DMA priority assigned to USART1" -#endif - -#if STM32_UART_USE_USART2 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART2_DMA_PRIORITY) -#error "Invalid DMA priority assigned to USART2" -#endif - -#if STM32_UART_USE_USART3 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART3_DMA_PRIORITY) -#error "Invalid DMA priority assigned to USART3" -#endif - -#if STM32_UART_USE_USART1 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_USART1_RX_DMA_STREAM, \ - STM32_USART1_RX_DMA_MSK) -#error "invalid DMA stream associated to USART1 RX" -#endif - -#if STM32_UART_USE_USART1 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_USART1_TX_DMA_STREAM, \ - STM32_USART1_TX_DMA_MSK) -#error "invalid DMA stream associated to USART1 TX" -#endif - -#if STM32_UART_USE_USART2 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_USART2_RX_DMA_STREAM, \ - STM32_USART2_RX_DMA_MSK) -#error "invalid DMA stream associated to USART2 RX" -#endif - -#if STM32_UART_USE_USART2 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_USART2_TX_DMA_STREAM, \ - STM32_USART2_TX_DMA_MSK) -#error "invalid DMA stream associated to USART2 TX" -#endif - -#if STM32_UART_USE_USART3 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_USART3_RX_DMA_STREAM, \ - STM32_USART3_RX_DMA_MSK) -#error "invalid DMA stream associated to USART3 RX" -#endif - -#if STM32_UART_USE_USART3 && \ - !STM32_DMA_IS_VALID_ID(STM32_UART_USART3_TX_DMA_STREAM, \ - STM32_USART3_TX_DMA_MSK) -#error "invalid DMA stream associated to USART3 TX" -#endif - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief UART driver condition flags type. - */ -typedef uint32_t uartflags_t; - -/** - * @brief Structure representing an UART driver. - */ -typedef struct UARTDriver UARTDriver; - -/** - * @brief Generic UART notification callback type. - * - * @param[in] uartp pointer to the @p UARTDriver object - */ -typedef void (*uartcb_t)(UARTDriver *uartp); - -/** - * @brief Character received UART notification callback type. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] c received character - */ -typedef void (*uartccb_t)(UARTDriver *uartp, uint16_t c); - -/** - * @brief Receive error UART notification callback type. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] e receive error mask - */ -typedef void (*uartecb_t)(UARTDriver *uartp, uartflags_t e); - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief End of transmission buffer callback. - */ - uartcb_t txend1_cb; - /** - * @brief Physical end of transmission callback. - */ - uartcb_t txend2_cb; - /** - * @brief Receive buffer filled callback. - */ - uartcb_t rxend_cb; - /** - * @brief Character received while out if the @p UART_RECEIVE state. - */ - uartccb_t rxchar_cb; - /** - * @brief Receive error callback. - */ - uartecb_t rxerr_cb; - /* End of the mandatory fields.*/ - /** - * @brief Bit rate. - */ - uint32_t speed; - /** - * @brief Initialization value for the CR1 register. - */ - uint32_t cr1; - /** - * @brief Initialization value for the CR2 register. - */ - uint32_t cr2; - /** - * @brief Initialization value for the CR3 register. - */ - uint32_t cr3; -} UARTConfig; - -/** - * @brief Structure representing an UART driver. - */ -struct UARTDriver { - /** - * @brief Driver state. - */ - uartstate_t state; - /** - * @brief Transmitter state. - */ - uarttxstate_t txstate; - /** - * @brief Receiver state. - */ - uartrxstate_t rxstate; - /** - * @brief Current configuration data. - */ - const UARTConfig *config; -#if defined(UART_DRIVER_EXT_FIELDS) - UART_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the USART registers block. - */ - USART_TypeDef *usart; - /** - * @brief DMA mode bit mask. - */ - uint32_t dmamode; - /** - * @brief Receive DMA channel. - */ - const stm32_dma_stream_t *dmarx; - /** - * @brief Transmit DMA channel. - */ - const stm32_dma_stream_t *dmatx; - /** - * @brief Default receive buffer while into @p UART_RX_IDLE state. - */ - volatile uint16_t rxbuf; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_UART_USE_USART1 && !defined(__DOXYGEN__) -extern UARTDriver UARTD1; -#endif - -#if STM32_UART_USE_USART2 && !defined(__DOXYGEN__) -extern UARTDriver UARTD2; -#endif - -#if STM32_UART_USE_USART3 && !defined(__DOXYGEN__) -extern UARTDriver UARTD3; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void uart_lld_init(void); - void uart_lld_start(UARTDriver *uartp); - void uart_lld_stop(UARTDriver *uartp); - void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf); - size_t uart_lld_stop_send(UARTDriver *uartp); - void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf); - size_t uart_lld_stop_receive(UARTDriver *uartp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_UART */ - -#endif /* _UART_LLD_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/USBv1/stm32_usb.h b/firmware/chibios/os/hal/platforms/STM32/USBv1/stm32_usb.h deleted file mode 100644 index 6f18c57710..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/USBv1/stm32_usb.h +++ /dev/null @@ -1,248 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file stm32_usb.h - * @brief STM32 USB registers layout header. - * @note This file requires definitions from the ST STM32 header files - * stm32f10x.h or stm32l1xx.h. - * - * @addtogroup USB - * @{ - */ - -#ifndef _STM32_USB_H_ -#define _STM32_USB_H_ - -/** - * @brief Number of the available endpoints. - * @details This value does not include the endpoint 0 which is always present. - */ -#define USB_ENDOPOINTS_NUMBER 7 - -/** - * @brief USB registers block. - */ -typedef struct { - /** - * @brief Endpoint registers. - */ - volatile uint32_t EPR[USB_ENDOPOINTS_NUMBER + 1]; - /* - * @brief Reserved space. - */ - volatile uint32_t _r20[8]; - /* - * @brief Control Register. - */ - volatile uint32_t CNTR; - /* - * @brief Interrupt Status Register. - */ - volatile uint32_t ISTR; - /* - * @brief Frame Number Register. - */ - volatile uint32_t FNR; - /* - * @brief Device Address Register. - */ - volatile uint32_t DADDR; - /* - * @brief Buffer Table Address. - */ - volatile uint32_t BTABLE; -} stm32_usb_t; - -/** - * @brief USB descriptor registers block. - */ -typedef struct { - /** - * @brief TX buffer offset register. - */ - volatile uint32_t TXADDR0; - /** - * @brief TX counter register 0. - */ - volatile uint16_t TXCOUNT0; - /** - * @brief TX counter register 1. - */ - volatile uint16_t TXCOUNT1; - /** - * @brief RX buffer offset register. - */ - volatile uint32_t RXADDR0; - /** - * @brief RX counter register 0. - */ - volatile uint16_t RXCOUNT0; - /** - * @brief RX counter register 1. - */ - volatile uint16_t RXCOUNT1; -} stm32_usb_descriptor_t; - -/** - * @name Register aliases - * @{ - */ -#define RXADDR1 TXADDR0 -#define TXADDR1 RXADDR0 -/** @} */ - -/** - * @brief USB registers block numeric address. - */ -#define STM32_USB_BASE (APB1PERIPH_BASE + 0x5C00) - -/** - * @brief USB RAM numeric address. - */ -#define STM32_USBRAM_BASE (APB1PERIPH_BASE + 0x6000) - -/** - * @brief Pointer to the USB registers block. - */ -#define STM32_USB ((stm32_usb_t *)STM32_USB_BASE) - -/** - * @brief Pointer to the USB RAM. - */ -#define STM32_USBRAM ((uint32_t *)STM32_USBRAM_BASE) - -/** - * @brief Size of the dedicated packet memory. - */ -#define USB_PMA_SIZE 512 - -/** - * @brief Mask of all the toggling bits in the EPR register. - */ -#define EPR_TOGGLE_MASK (EPR_STAT_TX_MASK | EPR_DTOG_TX | \ - EPR_STAT_RX_MASK | EPR_DTOG_RX | \ - EPR_SETUP) - -#define EPR_EA_MASK 0x000F -#define EPR_STAT_TX_MASK 0x0030 -#define EPR_STAT_TX_DIS 0x0000 -#define EPR_STAT_TX_STALL 0x0010 -#define EPR_STAT_TX_NAK 0x0020 -#define EPR_STAT_TX_VALID 0x0030 -#define EPR_DTOG_TX 0x0040 -#define EPR_SWBUF_RX EPR_DTOG_TX -#define EPR_CTR_TX 0x0080 -#define EPR_EP_KIND 0x0100 -#define EPR_EP_DBL_BUF EPR_EP_KIND -#define EPR_EP_STATUS_OUT EPR_EP_KIND -#define EPR_EP_TYPE_MASK 0x0600 -#define EPR_EP_TYPE_BULK 0x0000 -#define EPR_EP_TYPE_CONTROL 0x0200 -#define EPR_EP_TYPE_ISO 0x0400 -#define EPR_EP_TYPE_INTERRUPT 0x0600 -#define EPR_SETUP 0x0800 -#define EPR_STAT_RX_MASK 0x3000 -#define EPR_STAT_RX_DIS 0x0000 -#define EPR_STAT_RX_STALL 0x1000 -#define EPR_STAT_RX_NAK 0x2000 -#define EPR_STAT_RX_VALID 0x3000 -#define EPR_DTOG_RX 0x4000 -#define EPR_SWBUF_TX EPR_DTOG_RX -#define EPR_CTR_RX 0x8000 - -#define CNTR_FRES 0x0001 -#define CNTR_PDWN 0x0002 -#define CNTR_LP_MODE 0x0004 -#define CNTR_FSUSP 0x0008 -#define CNTR_RESUME 0x0010 -#define CNTR_ESOFM 0x0100 -#define CNTR_SOFM 0x0200 -#define CNTR_RESETM 0x0400 -#define CNTR_SUSPM 0x0800 -#define CNTR_WKUPM 0x1000 -#define CNTR_ERRM 0x2000 -#define CNTR_PMAOVRM 0x4000 -#define CNTR_CTRM 0x8000 - -#define ISTR_EP_ID_MASK 0x000F -#define ISTR_DIR 0x0010 -#define ISTR_ESOF 0x0100 -#define ISTR_SOF 0x0200 -#define ISTR_RESET 0x0400 -#define ISTR_SUSP 0x0800 -#define ISTR_WKUP 0x1000 -#define ISTR_ERR 0x2000 -#define ISTR_PMAOVR 0x4000 -#define ISTR_CTR 0x8000 - -#define FNR_FN_MASK 0x07FF -#define FNR_LSOF 0x1800 -#define FNR_LCK 0x2000 -#define FNR_RXDM 0x4000 -#define FNR_RXDP 0x8000 - -#define DADDR_ADD_MASK 0x007F -#define DADDR_EF 0x0080 - -#define RXCOUNT_COUNT_MASK 0x03FF -#define TXCOUNT_COUNT_MASK 0x03FF - -#define EPR_CTR_MASK (EPR_CTR_TX | EPR_CTR_RX) - -#define EPR_SET(ep, epr) \ - STM32_USB->EPR[ep] = ((epr) & ~EPR_TOGGLE_MASK) | EPR_CTR_MASK - -#define EPR_TOGGLE(ep, epr) \ - STM32_USB->EPR[ep] = (STM32_USB->EPR[ep] ^ ((epr) & EPR_TOGGLE_MASK)) \ - | EPR_CTR_MASK - -#define EPR_SET_STAT_RX(ep, epr) \ - STM32_USB->EPR[ep] = ((STM32_USB->EPR[ep] & \ - ~(EPR_TOGGLE_MASK & ~EPR_STAT_RX_MASK)) ^ \ - (epr)) | EPR_CTR_MASK - -#define EPR_SET_STAT_TX(ep, epr) \ - STM32_USB->EPR[ep] = ((STM32_USB->EPR[ep] & \ - ~(EPR_TOGGLE_MASK & ~EPR_STAT_TX_MASK)) ^ \ - (epr)) | EPR_CTR_MASK - -#define EPR_CLEAR_CTR_RX(ep) \ - STM32_USB->EPR[ep] = (STM32_USB->EPR[ep] & ~EPR_CTR_RX & ~EPR_TOGGLE_MASK)\ - | EPR_CTR_TX - -#define EPR_CLEAR_CTR_TX(ep) \ - STM32_USB->EPR[ep] = (STM32_USB->EPR[ep] & ~EPR_CTR_TX & ~EPR_TOGGLE_MASK)\ - | EPR_CTR_RX - -/** - * @brief Returns an endpoint descriptor pointer. - */ -#define USB_GET_DESCRIPTOR(ep) \ - ((stm32_usb_descriptor_t *)((uint32_t)STM32_USBRAM_BASE + \ - (uint32_t)STM32_USB->BTABLE * 2 + \ - (uint32_t)(ep) * \ - sizeof(stm32_usb_descriptor_t))) - -/** - * @brief Converts from a PMA address to a physical address. - */ -#define USB_ADDR2PTR(addr) \ - ((uint32_t *)((addr) * 2 + STM32_USBRAM_BASE)) - -#endif /* _STM32_USB_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/USBv1/usb_lld.c b/firmware/chibios/os/hal/platforms/STM32/USBv1/usb_lld.c deleted file mode 100644 index a3b4ea73f8..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/USBv1/usb_lld.c +++ /dev/null @@ -1,830 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/USBv1/usb_lld.c - * @brief STM32 USB subsystem low level driver source. - * - * @addtogroup USB - * @{ - */ - -#include - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_USB || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define BTABLE_ADDR 0x0000 - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief USB1 driver identifier.*/ -#if STM32_USB_USE_USB1 || defined(__DOXYGEN__) -USBDriver USBD1; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief EP0 state. - * @note It is an union because IN and OUT endpoints are never used at the - * same time for EP0. - */ -static union { - /** - * @brief IN EP0 state. - */ - USBInEndpointState in; - /** - * @brief OUT EP0 state. - */ - USBOutEndpointState out; -} ep0_state; - -/** - * @brief Buffer for the EP0 setup packets. - */ -static uint8_t ep0setup_buffer[8]; - -/** - * @brief EP0 initialization structure. - */ -static const USBEndpointConfig ep0config = { - USB_EP_MODE_TYPE_CTRL, - _usb_ep0setup, - _usb_ep0in, - _usb_ep0out, - 0x40, - 0x40, - &ep0_state.in, - &ep0_state.out, - 1, - ep0setup_buffer -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Resets the packet memory allocator. - * - * @param[in] usbp pointer to the @p USBDriver object - */ -static void usb_pm_reset(USBDriver *usbp) { - - /* The first 64 bytes are reserved for the descriptors table. The effective - available RAM for endpoint buffers is just 448 bytes.*/ - usbp->pmnext = 64; -} - -/** - * @brief Resets the packet memory allocator. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] size size of the packet buffer to allocate - */ -static uint32_t usb_pm_alloc(USBDriver *usbp, size_t size) { - uint32_t next; - - next = usbp->pmnext; - usbp->pmnext += size; - chDbgAssert(usbp->pmnext <= USB_PMA_SIZE, "usb_pm_alloc(), #1", "PMA overflow"); - return next; -} - -/** - * @brief Reads from a dedicated packet buffer. - * - * @param[in] udp pointer to a @p stm32_usb_descriptor_t - * @param[out] buf buffer where to copy the packet data - * @param[in] n maximum number of bytes to copy. This value must - * not exceed the maximum packet size for this endpoint. - * - * @notapi - */ -static void usb_packet_read_to_buffer(stm32_usb_descriptor_t *udp, - uint8_t *buf, size_t n) { - uint32_t *pmap= USB_ADDR2PTR(udp->RXADDR0); - - n = (n + 1) / 2; - while (n > 0) { - /* Note, this line relies on the Cortex-M3/M4 ability to perform - unaligned word accesses.*/ - *(uint16_t *)buf = (uint16_t)*pmap++; - buf += 2; - n--; - } -} - -/** - * @brief Reads from a dedicated packet buffer. - * - * @param[in] udp pointer to a @p stm32_usb_descriptor_t - * @param[in] iqp pointer to an @p InputQueue object - * @param[in] n maximum number of bytes to copy. This value must - * not exceed the maximum packet size for this endpoint. - * - * @notapi - */ -static void usb_packet_read_to_queue(stm32_usb_descriptor_t *udp, - InputQueue *iqp, size_t n) { - size_t nhw; - uint32_t *pmap= USB_ADDR2PTR(udp->RXADDR0); - - nhw = n / 2; - while (nhw > 0) { - uint32_t w; - - w = *pmap++; - *iqp->q_wrptr++ = (uint8_t)w; - if (iqp->q_wrptr >= iqp->q_top) - iqp->q_wrptr = iqp->q_buffer; - *iqp->q_wrptr++ = (uint8_t)(w >> 8); - if (iqp->q_wrptr >= iqp->q_top) - iqp->q_wrptr = iqp->q_buffer; - nhw--; - } - /* Last byte for odd numbers.*/ - if ((n & 1) != 0) { - *iqp->q_wrptr++ = (uint8_t)*pmap; - if (iqp->q_wrptr >= iqp->q_top) - iqp->q_wrptr = iqp->q_buffer; - } - - /* Updating queue.*/ - chSysLockFromIsr(); - iqp->q_counter += n; - while (notempty(&iqp->q_waiting)) - chSchReadyI(fifo_remove(&iqp->q_waiting))->p_u.rdymsg = Q_OK; - chSysUnlockFromIsr(); -} - -/** - * @brief Writes to a dedicated packet buffer. - * - * @param[in] udp pointer to a @p stm32_usb_descriptor_t - * @param[in] buf buffer where to fetch the packet data - * @param[in] n maximum number of bytes to copy. This value must - * not exceed the maximum packet size for this endpoint. - * - * @notapi - */ -static void usb_packet_write_from_buffer(stm32_usb_descriptor_t *udp, - const uint8_t *buf, - size_t n) { - uint32_t *pmap = USB_ADDR2PTR(udp->TXADDR0); - - udp->TXCOUNT0 = (uint16_t)n; - n = (n + 1) / 2; - while (n > 0) { - /* Note, this line relies on the Cortex-M3/M4 ability to perform - unaligned word accesses.*/ - *pmap++ = *(uint16_t *)buf; - buf += 2; - n--; - } -} - -/** - * @brief Writes to a dedicated packet buffer. - * - * @param[in] udp pointer to a @p stm32_usb_descriptor_t - * @param[in] buf buffer where to fetch the packet data - * @param[in] n maximum number of bytes to copy. This value must - * not exceed the maximum packet size for this endpoint. - * - * @notapi - */ -static void usb_packet_write_from_queue(stm32_usb_descriptor_t *udp, - OutputQueue *oqp, size_t n) { - size_t nhw; - uint32_t *pmap = USB_ADDR2PTR(udp->TXADDR0); - - udp->TXCOUNT0 = (uint16_t)n; - nhw = n / 2; - while (nhw > 0) { - uint32_t w; - - w = (uint32_t)*oqp->q_rdptr++; - if (oqp->q_rdptr >= oqp->q_top) - oqp->q_rdptr = oqp->q_buffer; - w |= (uint32_t)*oqp->q_rdptr++ << 8; - if (oqp->q_rdptr >= oqp->q_top) - oqp->q_rdptr = oqp->q_buffer; - *pmap++ = w; - nhw--; - } - - /* Last byte for odd numbers.*/ - if ((n & 1) != 0) { - *pmap = (uint32_t)*oqp->q_rdptr++; - if (oqp->q_rdptr >= oqp->q_top) - oqp->q_rdptr = oqp->q_buffer; - } - - /* Updating queue. Note, the lock is done in this unusual way because this - function can be called from both ISR and thread context so the kind - of lock function to be invoked cannot be decided beforehand.*/ - port_lock(); - dbg_enter_lock(); - - oqp->q_counter += n; - while (notempty(&oqp->q_waiting)) - chSchReadyI(fifo_remove(&oqp->q_waiting))->p_u.rdymsg = Q_OK; - - dbg_leave_lock(); - port_unlock(); -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if STM32_USB_USE_USB1 || defined(__DOXYGEN__) -#if !defined(STM32_USB1_HP_HANDLER) -#error "STM32_USB1_HP_HANDLER not defined" -#endif -/** - * @brief USB high priority interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_USB1_HP_HANDLER) { - - CH_IRQ_PROLOGUE(); - - CH_IRQ_EPILOGUE(); -} - -#if !defined(STM32_USB1_LP_HANDLER) -#error "STM32_USB1_LP_HANDLER not defined" -#endif -/** - * @brief USB low priority interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_USB1_LP_HANDLER) { - uint32_t istr; - USBDriver *usbp = &USBD1; - - CH_IRQ_PROLOGUE(); - - istr = STM32_USB->ISTR; - - /* USB bus reset condition handling.*/ - if (istr & ISTR_RESET) { - _usb_reset(usbp); - _usb_isr_invoke_event_cb(usbp, USB_EVENT_RESET); - STM32_USB->ISTR = ~ISTR_RESET; - } - - /* USB bus SUSPEND condition handling.*/ - if (istr & ISTR_SUSP) { - STM32_USB->CNTR |= CNTR_FSUSP; - _usb_isr_invoke_event_cb(usbp, USB_EVENT_SUSPEND); -#if STM32_USB_LOW_POWER_ON_SUSPEND - STM32_USB->CNTR |= CNTR_LP_MODE; -#endif - STM32_USB->ISTR = ~ISTR_SUSP; - } - - /* USB bus WAKEUP condition handling.*/ - if (istr & ISTR_WKUP) { - uint32_t fnr = STM32_USB->FNR; - if (!(fnr & FNR_RXDP)) { - STM32_USB->CNTR &= ~CNTR_FSUSP; - _usb_isr_invoke_event_cb(usbp, USB_EVENT_WAKEUP); - } -#if STM32_USB_LOW_POWER_ON_SUSPEND - else { - /* Just noise, going back in SUSPEND mode, reference manual 22.4.5, - table 169.*/ - STM32_USB->CNTR |= CNTR_LP_MODE; - } -#endif - STM32_USB->ISTR = ~ISTR_WKUP; - } - - /* SOF handling.*/ - if (istr & ISTR_SOF) { - _usb_isr_invoke_sof_cb(usbp); - STM32_USB->ISTR = ~ISTR_SOF; - } - - /* Endpoint events handling.*/ - while (istr & ISTR_CTR) { - size_t n; - uint32_t ep; - uint32_t epr = STM32_USB->EPR[ep = istr & ISTR_EP_ID_MASK]; - const USBEndpointConfig *epcp = usbp->epc[ep]; - - if (epr & EPR_CTR_TX) { - size_t transmitted; - /* IN endpoint, transmission.*/ - EPR_CLEAR_CTR_TX(ep); - - transmitted = (size_t)USB_GET_DESCRIPTOR(ep)->TXCOUNT0; - epcp->in_state->txcnt += transmitted; - n = epcp->in_state->txsize - epcp->in_state->txcnt; - if (n > 0) { - /* Transfer not completed, there are more packets to send.*/ - if (n > epcp->in_maxsize) - n = epcp->in_maxsize; - - if (epcp->in_state->txqueued) - usb_packet_write_from_queue(USB_GET_DESCRIPTOR(ep), - epcp->in_state->mode.queue.txqueue, - n); - else { - epcp->in_state->mode.linear.txbuf += transmitted; - usb_packet_write_from_buffer(USB_GET_DESCRIPTOR(ep), - epcp->in_state->mode.linear.txbuf, - n); - } - chSysLockFromIsr(); - usb_lld_start_in(usbp, ep); - chSysUnlockFromIsr(); - } - else { - /* Transfer completed, invokes the callback.*/ - _usb_isr_invoke_in_cb(usbp, ep); - } - } - if (epr & EPR_CTR_RX) { - EPR_CLEAR_CTR_RX(ep); - /* OUT endpoint, receive.*/ - if (epr & EPR_SETUP) { - /* Setup packets handling, setup packets are handled using a - specific callback.*/ - _usb_isr_invoke_setup_cb(usbp, ep); - } - else { - stm32_usb_descriptor_t *udp = USB_GET_DESCRIPTOR(ep); - n = (size_t)udp->RXCOUNT0 & RXCOUNT_COUNT_MASK; - - /* Reads the packet into the defined buffer.*/ - if (epcp->out_state->rxqueued) - usb_packet_read_to_queue(udp, - epcp->out_state->mode.queue.rxqueue, - n); - else { - usb_packet_read_to_buffer(udp, - epcp->out_state->mode.linear.rxbuf, - n); - epcp->out_state->mode.linear.rxbuf += n; - } - /* Transaction data updated.*/ - epcp->out_state->rxcnt += n; - epcp->out_state->rxsize -= n; - epcp->out_state->rxpkts -= 1; - - /* The transaction is completed if the specified number of packets - has been received or the current packet is a short packet.*/ - if ((n < epcp->out_maxsize) || (epcp->out_state->rxpkts == 0)) { - /* Transfer complete, invokes the callback.*/ - _usb_isr_invoke_out_cb(usbp, ep); - } - else { - /* Transfer not complete, there are more packets to receive.*/ - EPR_SET_STAT_RX(ep, EPR_STAT_RX_VALID); - } - } - } - istr = STM32_USB->ISTR; - } - - CH_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level USB driver initialization. - * - * @notapi - */ -void usb_lld_init(void) { - - /* Driver initialization.*/ - usbObjectInit(&USBD1); -} - -/** - * @brief Configures and activates the USB peripheral. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -void usb_lld_start(USBDriver *usbp) { - - if (usbp->state == USB_STOP) { - /* Clock activation.*/ -#if STM32_USB_USE_USB1 - if (&USBD1 == usbp) { - /* USB clock enabled.*/ - rccEnableUSB(FALSE); - /* Powers up the transceiver while holding the USB in reset state.*/ - STM32_USB->CNTR = CNTR_FRES; - /* Enabling the USB IRQ vectors, this also gives enough time to allow - the transceiver power up (1uS).*/ - nvicEnableVector(STM32_USB1_HP_NUMBER, - CORTEX_PRIORITY_MASK(STM32_USB_USB1_HP_IRQ_PRIORITY)); - nvicEnableVector(STM32_USB1_LP_NUMBER, - CORTEX_PRIORITY_MASK(STM32_USB_USB1_LP_IRQ_PRIORITY)); - /* Releases the USB reset.*/ - STM32_USB->CNTR = 0; - } -#endif - /* Reset procedure enforced on driver start.*/ - _usb_reset(usbp); - } - /* Configuration.*/ -} - -/** - * @brief Deactivates the USB peripheral. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -void usb_lld_stop(USBDriver *usbp) { - - /* If in ready state then disables the USB clock.*/ - if (usbp->state == USB_STOP) { -#if STM32_USB_USE_USB1 - if (&USBD1 == usbp) { - nvicDisableVector(STM32_USB1_HP_NUMBER); - nvicDisableVector(STM32_USB1_LP_NUMBER); - STM32_USB->CNTR = CNTR_PDWN | CNTR_FRES; - rccDisableUSB(FALSE); - } -#endif - } -} - -/** - * @brief USB low level reset routine. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -void usb_lld_reset(USBDriver *usbp) { - uint32_t cntr; - - /* Post reset initialization.*/ - STM32_USB->BTABLE = 0; - STM32_USB->ISTR = 0; - STM32_USB->DADDR = DADDR_EF; - cntr = /*CNTR_ESOFM | */ CNTR_RESETM | CNTR_SUSPM | - CNTR_WKUPM | /*CNTR_ERRM | CNTR_PMAOVRM |*/ CNTR_CTRM; - /* The SOF interrupt is only enabled if a callback is defined for - this service because it is an high rate source.*/ - if (usbp->config->sof_cb != NULL) - cntr |= CNTR_SOFM; - STM32_USB->CNTR = cntr; - - /* Resets the packet memory allocator.*/ - usb_pm_reset(usbp); - - /* EP0 initialization.*/ - usbp->epc[0] = &ep0config; - usb_lld_init_endpoint(usbp, 0); -} - -/** - * @brief Sets the USB address. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -void usb_lld_set_address(USBDriver *usbp) { - - STM32_USB->DADDR = (uint32_t)(usbp->address) | DADDR_EF; -} - -/** - * @brief Enables an endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) { - uint16_t nblocks, epr; - stm32_usb_descriptor_t *dp; - const USBEndpointConfig *epcp = usbp->epc[ep]; - - /* Setting the endpoint type.*/ - switch (epcp->ep_mode & USB_EP_MODE_TYPE) { - case USB_EP_MODE_TYPE_ISOC: - epr = EPR_EP_TYPE_ISO; - break; - case USB_EP_MODE_TYPE_BULK: - epr = EPR_EP_TYPE_BULK; - break; - case USB_EP_MODE_TYPE_INTR: - epr = EPR_EP_TYPE_INTERRUPT; - break; - default: - epr = EPR_EP_TYPE_CONTROL; - } - - /* IN endpoint initially in NAK mode.*/ - if (epcp->in_cb != NULL) - epr |= EPR_STAT_TX_NAK; - - /* OUT endpoint initially in NAK mode.*/ - if (epcp->out_cb != NULL) - epr |= EPR_STAT_RX_NAK; - - /* EPxR register setup.*/ - EPR_SET(ep, epr | ep); - EPR_TOGGLE(ep, epr); - - /* Endpoint size and address initialization.*/ - if (epcp->out_maxsize > 62) - nblocks = (((((epcp->out_maxsize - 1) | 0x1f) + 1) / 32) << 10) | - 0x8000; - else - nblocks = ((((epcp->out_maxsize - 1) | 1) + 1) / 2) << 10; - dp = USB_GET_DESCRIPTOR(ep); - dp->TXCOUNT0 = 0; - dp->RXCOUNT0 = nblocks; - dp->TXADDR0 = usb_pm_alloc(usbp, epcp->in_maxsize); - dp->RXADDR0 = usb_pm_alloc(usbp, epcp->out_maxsize); -} - -/** - * @brief Disables all the active endpoints except the endpoint zero. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -void usb_lld_disable_endpoints(USBDriver *usbp) { - unsigned i; - - /* Resets the packet memory allocator.*/ - usb_pm_reset(usbp); - - /* Disabling all endpoints.*/ - for (i = 1; i <= USB_ENDOPOINTS_NUMBER; i++) { - EPR_TOGGLE(i, 0); - EPR_SET(i, 0); - } -} - -/** - * @brief Returns the status of an OUT endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @return The endpoint status. - * @retval EP_STATUS_DISABLED The endpoint is not active. - * @retval EP_STATUS_STALLED The endpoint is stalled. - * @retval EP_STATUS_ACTIVE The endpoint is active. - * - * @notapi - */ -usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep) { - - (void)usbp; - switch (STM32_USB->EPR[ep] & EPR_STAT_RX_MASK) { - case EPR_STAT_RX_DIS: - return EP_STATUS_DISABLED; - case EPR_STAT_RX_STALL: - return EP_STATUS_STALLED; - default: - return EP_STATUS_ACTIVE; - } -} - -/** - * @brief Returns the status of an IN endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @return The endpoint status. - * @retval EP_STATUS_DISABLED The endpoint is not active. - * @retval EP_STATUS_STALLED The endpoint is stalled. - * @retval EP_STATUS_ACTIVE The endpoint is active. - * - * @notapi - */ -usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep) { - - (void)usbp; - switch (STM32_USB->EPR[ep] & EPR_STAT_TX_MASK) { - case EPR_STAT_TX_DIS: - return EP_STATUS_DISABLED; - case EPR_STAT_TX_STALL: - return EP_STATUS_STALLED; - default: - return EP_STATUS_ACTIVE; - } -} - -/** - * @brief Reads a setup packet from the dedicated packet buffer. - * @details This function must be invoked in the context of the @p setup_cb - * callback in order to read the received setup packet. - * @pre In order to use this function the endpoint must have been - * initialized as a control endpoint. - * @post The endpoint is ready to accept another packet. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @param[out] buf buffer where to copy the packet data - * - * @notapi - */ -void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) { - uint32_t *pmap; - stm32_usb_descriptor_t *udp; - uint32_t n; - - (void)usbp; - udp = USB_GET_DESCRIPTOR(ep); - pmap = USB_ADDR2PTR(udp->RXADDR0); - for (n = 0; n < 4; n++) { - *(uint16_t *)buf = (uint16_t)*pmap++; - buf += 2; - } -} - -/** - * @brief Prepares for a receive operation. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep) { - USBOutEndpointState *osp = usbp->epc[ep]->out_state; - - /* Transfer initialization.*/ - if (osp->rxsize == 0) /* Special case for zero sized packets.*/ - osp->rxpkts = 1; - else - osp->rxpkts = (uint16_t)((osp->rxsize + usbp->epc[ep]->out_maxsize - 1) / - usbp->epc[ep]->out_maxsize); -} - -/** - * @brief Prepares for a transmit operation. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep) { - size_t n; - USBInEndpointState *isp = usbp->epc[ep]->in_state; - - /* Transfer initialization.*/ - n = isp->txsize; - if (n > (size_t)usbp->epc[ep]->in_maxsize) - n = (size_t)usbp->epc[ep]->in_maxsize; - - if (isp->txqueued) - usb_packet_write_from_queue(USB_GET_DESCRIPTOR(ep), - isp->mode.queue.txqueue, n); - else - usb_packet_write_from_buffer(USB_GET_DESCRIPTOR(ep), - isp->mode.linear.txbuf, n); -} - -/** - * @brief Starts a receive operation on an OUT endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_start_out(USBDriver *usbp, usbep_t ep) { - - (void)usbp; - - EPR_SET_STAT_RX(ep, EPR_STAT_RX_VALID); -} - -/** - * @brief Starts a transmit operation on an IN endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_start_in(USBDriver *usbp, usbep_t ep) { - - (void)usbp; - - EPR_SET_STAT_TX(ep, EPR_STAT_TX_VALID); -} - -/** - * @brief Brings an OUT endpoint in the stalled state. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_stall_out(USBDriver *usbp, usbep_t ep) { - - (void)usbp; - - EPR_SET_STAT_RX(ep, EPR_STAT_RX_STALL); -} - -/** - * @brief Brings an IN endpoint in the stalled state. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_stall_in(USBDriver *usbp, usbep_t ep) { - - (void)usbp; - - EPR_SET_STAT_TX(ep, EPR_STAT_TX_STALL); -} - -/** - * @brief Brings an OUT endpoint in the active state. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_clear_out(USBDriver *usbp, usbep_t ep) { - - (void)usbp; - - /* Makes sure to not put to NAK an endpoint that is already - transferring.*/ - if ((STM32_USB->EPR[ep] & EPR_STAT_RX_MASK) != EPR_STAT_RX_VALID) - EPR_SET_STAT_TX(ep, EPR_STAT_RX_NAK); -} - -/** - * @brief Brings an IN endpoint in the active state. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @notapi - */ -void usb_lld_clear_in(USBDriver *usbp, usbep_t ep) { - - (void)usbp; - - /* Makes sure to not put to NAK an endpoint that is already - transferring.*/ - if ((STM32_USB->EPR[ep] & EPR_STAT_TX_MASK) != EPR_STAT_TX_VALID) - EPR_SET_STAT_TX(ep, EPR_STAT_TX_NAK); -} - -#endif /* HAL_USE_USB */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/USBv1/usb_lld.h b/firmware/chibios/os/hal/platforms/STM32/USBv1/usb_lld.h deleted file mode 100644 index 405b0c8e4f..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/USBv1/usb_lld.h +++ /dev/null @@ -1,447 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/USBv1/usb_lld.h - * @brief STM32 USB subsystem low level driver header. - * - * @addtogroup USB - * @{ - */ - -#ifndef _USB_LLD_H_ -#define _USB_LLD_H_ - -#if HAL_USE_USB || defined(__DOXYGEN__) - -#include "stm32_usb.h" - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Maximum endpoint address. - */ -#define USB_MAX_ENDPOINTS USB_ENDOPOINTS_NUMBER - -/** - * @brief Status stage handling method. - */ -#define USB_EP0_STATUS_STAGE USB_EP0_STATUS_STAGE_SW - -/** - * @brief This device requires the address change after the status packet. - */ -#define USB_SET_ADDRESS_MODE USB_LATE_SET_ADDRESS - -/** - * @brief Method for set address acknowledge. - */ -#define USB_SET_ADDRESS_ACK_HANDLING USB_SET_ADDRESS_ACK_SW - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief USB1 driver enable switch. - * @details If set to @p TRUE the support for USB1 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_USB_USE_USB1) || defined(__DOXYGEN__) -#define STM32_USB_USE_USB1 FALSE -#endif - -/** - * @brief Enables the USB device low power mode on suspend. - */ -#if !defined(STM32_USB_LOW_POWER_ON_SUSPEND) || defined(__DOXYGEN__) -#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE -#endif - -/** - * @brief USB1 interrupt priority level setting. - */ -#if !defined(STM32_USB_USB1_HP_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 -#endif - -/** - * @brief USB1 interrupt priority level setting. - */ -#if !defined(STM32_USB_USB1_LP_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_USB_USE_USB1 && !STM32_HAS_USB -#error "USB not present in the selected device" -#endif - -#if !STM32_USB_USE_USB1 -#error "USB driver activated but no USB peripheral assigned" -#endif - -#if STM32_USB_USE_USB1 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_USB_USB1_HP_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to USB HP" -#endif - -#if STM32_USB_USE_USB1 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_USB_USB1_LP_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to USB LP" -#endif - -#if STM32_USBCLK != 48000000 -#error "the USB driver requires a 48MHz clock" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of an IN endpoint state structure. - */ -typedef struct { - /** - * @brief Buffer mode, queue or linear. - */ - bool_t txqueued; - /** - * @brief Requested transmit transfer size. - */ - size_t txsize; - /** - * @brief Transmitted bytes so far. - */ - size_t txcnt; - union { - struct { - /** - * @brief Pointer to the transmission linear buffer. - */ - const uint8_t *txbuf; - } linear; - struct { - /** - * @brief Pointer to the output queue. - */ - OutputQueue *txqueue; - } queue; - /* End of the mandatory fields.*/ - } mode; -} USBInEndpointState; - -/** - * @brief Type of an OUT endpoint state structure. - */ -typedef struct { - /** - * @brief Buffer mode, queue or linear. - */ - bool_t rxqueued; - /** - * @brief Requested receive transfer size. - */ - size_t rxsize; - /** - * @brief Received bytes so far. - */ - size_t rxcnt; - union { - struct { - /** - * @brief Pointer to the receive linear buffer. - */ - uint8_t *rxbuf; - } linear; - struct { - /** - * @brief Pointer to the input queue. - */ - InputQueue *rxqueue; - } queue; - } mode; - /* End of the mandatory fields.*/ - /** - * @brief Number of packets to receive. - */ - uint16_t rxpkts; -} USBOutEndpointState; - -/** - * @brief Type of an USB endpoint configuration structure. - * @note Platform specific restrictions may apply to endpoints. - */ -typedef struct { - /** - * @brief Type and mode of the endpoint. - */ - uint32_t ep_mode; - /** - * @brief Setup packet notification callback. - * @details This callback is invoked when a setup packet has been - * received. - * @post The application must immediately call @p usbReadPacket() in - * order to access the received packet. - * @note This field is only valid for @p USB_EP_MODE_TYPE_CTRL - * endpoints, it should be set to @p NULL for other endpoint - * types. - */ - usbepcallback_t setup_cb; - /** - * @brief IN endpoint notification callback. - * @details This field must be set to @p NULL if the IN endpoint is not - * used. - */ - usbepcallback_t in_cb; - /** - * @brief OUT endpoint notification callback. - * @details This field must be set to @p NULL if the OUT endpoint is not - * used. - */ - usbepcallback_t out_cb; - /** - * @brief IN endpoint maximum packet size. - * @details This field must be set to zero if the IN endpoint is not - * used. - */ - uint16_t in_maxsize; - /** - * @brief OUT endpoint maximum packet size. - * @details This field must be set to zero if the OUT endpoint is not - * used. - */ - uint16_t out_maxsize; - /** - * @brief @p USBEndpointState associated to the IN endpoint. - * @details This structure maintains the state of the IN endpoint. - */ - USBInEndpointState *in_state; - /** - * @brief @p USBEndpointState associated to the OUT endpoint. - * @details This structure maintains the state of the OUT endpoint. - */ - USBOutEndpointState *out_state; - /* End of the mandatory fields.*/ - /** - * @brief Reserved field, not currently used. - * @note Initialize this field to 1 in order to be forward compatible. - */ - uint16_t ep_buffers; - /** - * @brief Pointer to a buffer for setup packets. - * @details Setup packets require a dedicated 8-bytes buffer, set this - * field to @p NULL for non-control endpoints. - */ - uint8_t *setup_buf; -} USBEndpointConfig; - -/** - * @brief Type of an USB driver configuration structure. - */ -typedef struct { - /** - * @brief USB events callback. - * @details This callback is invoked when an USB driver event is registered. - */ - usbeventcb_t event_cb; - /** - * @brief Device GET_DESCRIPTOR request callback. - * @note This callback is mandatory and cannot be set to @p NULL. - */ - usbgetdescriptor_t get_descriptor_cb; - /** - * @brief Requests hook callback. - * @details This hook allows to be notified of standard requests or to - * handle non standard requests. - */ - usbreqhandler_t requests_hook_cb; - /** - * @brief Start Of Frame callback. - */ - usbcallback_t sof_cb; - /* End of the mandatory fields.*/ -} USBConfig; - -/** - * @brief Structure representing an USB driver. - */ -struct USBDriver { - /** - * @brief Driver state. - */ - usbstate_t state; - /** - * @brief Current configuration data. - */ - const USBConfig *config; - /** - * @brief Bit map of the transmitting IN endpoints. - */ - uint16_t transmitting; - /** - * @brief Bit map of the receiving OUT endpoints. - */ - uint16_t receiving; - /** - * @brief Active endpoints configurations. - */ - const USBEndpointConfig *epc[USB_MAX_ENDPOINTS + 1]; - /** - * @brief Fields available to user, it can be used to associate an - * application-defined handler to an IN endpoint. - * @note The base index is one, the endpoint zero does not have a - * reserved element in this array. - */ - void *in_params[USB_MAX_ENDPOINTS]; - /** - * @brief Fields available to user, it can be used to associate an - * application-defined handler to an OUT endpoint. - * @note The base index is one, the endpoint zero does not have a - * reserved element in this array. - */ - void *out_params[USB_MAX_ENDPOINTS]; - /** - * @brief Endpoint 0 state. - */ - usbep0state_t ep0state; - /** - * @brief Next position in the buffer to be transferred through endpoint 0. - */ - uint8_t *ep0next; - /** - * @brief Number of bytes yet to be transferred through endpoint 0. - */ - size_t ep0n; - /** - * @brief Endpoint 0 end transaction callback. - */ - usbcallback_t ep0endcb; - /** - * @brief Setup packet buffer. - */ - uint8_t setup[8]; - /** - * @brief Current USB device status. - */ - uint16_t status; - /** - * @brief Assigned USB address. - */ - uint8_t address; - /** - * @brief Current USB device configuration. - */ - uint8_t configuration; -#if defined(USB_DRIVER_EXT_FIELDS) - USB_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the next address in the packet memory. - */ - uint32_t pmnext; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Returns the current frame number. - * - * @param[in] usbp pointer to the @p USBDriver object - * @return The current frame number. - * - * @notapi - */ -#define usb_lld_get_frame_number(usbp) (STM32_USB->FNR & FNR_FN_MASK) - -/** - * @brief Returns the exact size of a receive transaction. - * @details The received size can be different from the size specified in - * @p usbStartReceiveI() because the last packet could have a size - * different from the expected one. - * @pre The OUT endpoint must have been configured in transaction mode - * in order to use this function. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @return Received data size. - * - * @notapi - */ -#define usb_lld_get_transaction_size(usbp, ep) \ - ((usbp)->epc[ep]->out_state->rxcnt) - -/** - * @brief Returns the exact size of a received packet. - * @pre The OUT endpoint must have been configured in packet mode - * in order to use this function. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @return Received data size. - * - * @notapi - */ -#define usb_lld_get_packet_size(usbp, ep) \ - ((size_t)USB_GET_DESCRIPTOR(ep)->RXCOUNT & RXCOUNT_COUNT_MASK) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_USB_USE_USB1 && !defined(__DOXYGEN__) -extern USBDriver USBD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void usb_lld_init(void); - void usb_lld_start(USBDriver *usbp); - void usb_lld_stop(USBDriver *usbp); - void usb_lld_reset(USBDriver *usbp); - void usb_lld_set_address(USBDriver *usbp); - void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep); - void usb_lld_disable_endpoints(USBDriver *usbp); - usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep); - usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep); - void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf); - void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep); - void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep); - void usb_lld_start_out(USBDriver *usbp, usbep_t ep); - void usb_lld_start_in(USBDriver *usbp, usbep_t ep); - void usb_lld_stall_out(USBDriver *usbp, usbep_t ep); - void usb_lld_stall_in(USBDriver *usbp, usbep_t ep); - void usb_lld_clear_out(USBDriver *usbp, usbep_t ep); - void usb_lld_clear_in(USBDriver *usbp, usbep_t ep); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_USB */ - -#endif /* _USB_LLD_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/can_lld.c b/firmware/chibios/os/hal/platforms/STM32/can_lld.c deleted file mode 100644 index 4c02c006bc..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/can_lld.c +++ /dev/null @@ -1,725 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/can_lld.c - * @brief STM32 CAN subsystem low level driver source. - * - * @addtogroup CAN - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_CAN || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief CAN1 driver identifier.*/ -#if STM32_CAN_USE_CAN1 || defined(__DOXYGEN__) -CANDriver CAND1; -#endif - -/** @brief CAN2 driver identifier.*/ -#if STM32_CAN_USE_CAN2 || defined(__DOXYGEN__) -CANDriver CAND2; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Programs the filters. - * - * @param[in] can2sb number of the first filter assigned to CAN2 - * @param[in] num number of entries in the filters array, if zero then - * a default filter is programmed - * @param[in] cfp pointer to the filters array, can be @p NULL if - * (num == 0) - * - * @notapi - */ -static void can_lld_set_filters(uint32_t can2sb, - uint32_t num, - const CANFilter *cfp) { - - /* Temporarily enabling CAN1 clock.*/ - rccEnableCAN1(FALSE); - - /* Filters initialization.*/ - CAN1->FMR = (CAN1->FMR & 0xFFFF0000) | (can2sb << 8) | CAN_FMR_FINIT; - if (num > 0) { - uint32_t i, fmask; - - /* All filters cleared.*/ - CAN1->FA1R = 0; - CAN1->FM1R = 0; - CAN1->FS1R = 0; - CAN1->FFA1R = 0; - for (i = 0; i < STM32_CAN_MAX_FILTERS; i++) { - CAN1->sFilterRegister[i].FR1 = 0; - CAN1->sFilterRegister[i].FR2 = 0; - } - - /* Scanning the filters array.*/ - for (i = 0; i < num; i++) { - fmask = 1 << cfp->filter; - if (cfp->mode) - CAN1->FM1R |= fmask; - if (cfp->scale) - CAN1->FS1R |= fmask; - if (cfp->assignment) - CAN1->FFA1R |= fmask; - CAN1->sFilterRegister[cfp->filter].FR1 = cfp->register1; - CAN1->sFilterRegister[cfp->filter].FR2 = cfp->register2; - CAN1->FA1R |= fmask; - cfp++; - } - } - else { - /* Setting up a single default filter that enables everything for both - CANs.*/ - CAN1->sFilterRegister[0].FR1 = 0; - CAN1->sFilterRegister[0].FR2 = 0; -#if STM32_HAS_CAN2 - CAN1->sFilterRegister[can2sb].FR1 = 0; - CAN1->sFilterRegister[can2sb].FR2 = 0; -#endif - CAN1->FM1R = 0; - CAN1->FFA1R = 0; -#if STM32_HAS_CAN2 - CAN1->FS1R = 1 | (1 << can2sb); - CAN1->FA1R = 1 | (1 << can2sb); -#else - CAN1->FS1R = 1; - CAN1->FA1R = 1; -#endif - } - CAN1->FMR &= ~CAN_FMR_FINIT; - - /* Clock disabled, it will be enabled again in can_lld_start().*/ - rccDisableCAN1(FALSE); -} - -/** - * @brief Common TX ISR handler. - * - * @param[in] canp pointer to the @p CANDriver object - * - * @notapi - */ -static void can_lld_tx_handler(CANDriver *canp) { - - /* No more events until a message is transmitted.*/ - canp->can->TSR = CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2; - chSysLockFromIsr(); - while (chSemGetCounterI(&canp->txsem) < 0) - chSemSignalI(&canp->txsem); - chEvtBroadcastFlagsI(&canp->txempty_event, CAN_MAILBOX_TO_MASK(1)); - chSysUnlockFromIsr(); -} - -/** - * @brief Common RX0 ISR handler. - * - * @param[in] canp pointer to the @p CANDriver object - * - * @notapi - */ -static void can_lld_rx0_handler(CANDriver *canp) { - uint32_t rf0r; - - rf0r = canp->can->RF0R; - if ((rf0r & CAN_RF0R_FMP0) > 0) { - /* No more receive events until the queue 0 has been emptied.*/ - canp->can->IER &= ~CAN_IER_FMPIE0; - chSysLockFromIsr(); - while (chSemGetCounterI(&canp->rxsem) < 0) - chSemSignalI(&canp->rxsem); - chEvtBroadcastFlagsI(&canp->rxfull_event, CAN_MAILBOX_TO_MASK(1)); - chSysUnlockFromIsr(); - } - if ((rf0r & CAN_RF0R_FOVR0) > 0) { - /* Overflow events handling.*/ - canp->can->RF0R = CAN_RF0R_FOVR0; - chSysLockFromIsr(); - chEvtBroadcastFlagsI(&canp->error_event, CAN_OVERFLOW_ERROR); - chSysUnlockFromIsr(); - } -} - -/** - * @brief Common RX1 ISR handler. - * - * @param[in] canp pointer to the @p CANDriver object - * - * @notapi - */ -static void can_lld_rx1_handler(CANDriver *canp) { - uint32_t rf1r; - - rf1r = canp->can->RF1R; - if ((rf1r & CAN_RF1R_FMP1) > 0) { - /* No more receive events until the queue 0 has been emptied.*/ - canp->can->IER &= ~CAN_IER_FMPIE1; - chSysLockFromIsr(); - while (chSemGetCounterI(&canp->rxsem) < 0) - chSemSignalI(&canp->rxsem); - chEvtBroadcastFlagsI(&canp->rxfull_event, CAN_MAILBOX_TO_MASK(2)); - chSysUnlockFromIsr(); - } - if ((rf1r & CAN_RF1R_FOVR1) > 0) { - /* Overflow events handling.*/ - canp->can->RF1R = CAN_RF1R_FOVR1; - chSysLockFromIsr(); - chEvtBroadcastFlagsI(&canp->error_event, CAN_OVERFLOW_ERROR); - chSysUnlockFromIsr(); - } -} - -/** - * @brief Common SCE ISR handler. - * - * @param[in] canp pointer to the @p CANDriver object - * - * @notapi - */ -static void can_lld_sce_handler(CANDriver *canp) { - uint32_t msr; - - msr = canp->can->MSR; - canp->can->MSR = CAN_MSR_ERRI | CAN_MSR_WKUI | CAN_MSR_SLAKI; - /* Wakeup event.*/ -#if CAN_USE_SLEEP_MODE - if (msr & CAN_MSR_WKUI) { - canp->state = CAN_READY; - canp->can->MCR &= ~CAN_MCR_SLEEP; - chSysLockFromIsr(); - chEvtBroadcastI(&canp->wakeup_event); - chSysUnlockFromIsr(); - } -#endif /* CAN_USE_SLEEP_MODE */ - /* Error event.*/ - if (msr & CAN_MSR_ERRI) { - flagsmask_t flags; - uint32_t esr = canp->can->ESR; - - canp->can->ESR &= ~CAN_ESR_LEC; - flags = (flagsmask_t)(esr & 7); - if ((esr & CAN_ESR_LEC) > 0) - flags |= CAN_FRAMING_ERROR; - - chSysLockFromIsr(); - /* The content of the ESR register is copied unchanged in the upper - half word of the listener flags mask.*/ - chEvtBroadcastFlagsI(&canp->error_event, flags | (flagsmask_t)(esr << 16)); - chSysUnlockFromIsr(); - } -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if STM32_CAN_USE_CAN1 || defined(__DOXYGEN__) -/** - * @brief CAN1 TX interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_CAN1_TX_HANDLER) { - - CH_IRQ_PROLOGUE(); - - can_lld_tx_handler(&CAND1); - - CH_IRQ_EPILOGUE(); -} - -/* - * @brief CAN1 RX0 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_CAN1_RX0_HANDLER) { - - CH_IRQ_PROLOGUE(); - - can_lld_rx0_handler(&CAND1); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief CAN1 RX1 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_CAN1_RX1_HANDLER) { - - CH_IRQ_PROLOGUE(); - - can_lld_rx1_handler(&CAND1); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief CAN1 SCE interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_CAN1_SCE_HANDLER) { - - CH_IRQ_PROLOGUE(); - - can_lld_sce_handler(&CAND1); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_CAN_USE_CAN1 */ - -#if STM32_CAN_USE_CAN2 || defined(__DOXYGEN__) -/** - * @brief CAN2 TX interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_CAN2_TX_HANDLER) { - - CH_IRQ_PROLOGUE(); - - can_lld_tx_handler(&CAND2); - - CH_IRQ_EPILOGUE(); -} - -/* - * @brief CAN2 RX0 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_CAN2_RX0_HANDLER) { - - CH_IRQ_PROLOGUE(); - - can_lld_rx0_handler(&CAND2); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief CAN2 RX1 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_CAN2_RX1_HANDLER) { - - CH_IRQ_PROLOGUE(); - - can_lld_rx1_handler(&CAND2); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief CAN2 SCE interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_CAN2_SCE_HANDLER) { - - CH_IRQ_PROLOGUE(); - - can_lld_sce_handler(&CAND2); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_CAN_USE_CAN2 */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level CAN driver initialization. - * - * @notapi - */ -void can_lld_init(void) { - -#if STM32_CAN_USE_CAN1 - /* Driver initialization.*/ - canObjectInit(&CAND1); - CAND1.can = CAN1; -#endif -#if STM32_CAN_USE_CAN2 - /* Driver initialization.*/ - canObjectInit(&CAND2); - CAND2.can = CAN2; -#endif - - /* Filters initialization.*/ -#if STM32_HAS_CAN2 - can_lld_set_filters(STM32_CAN_MAX_FILTERS / 2, 0, NULL); -#else - can_lld_set_filters(STM32_CAN_MAX_FILTERS, 0, NULL); -#endif -} - -/** - * @brief Configures and activates the CAN peripheral. - * - * @param[in] canp pointer to the @p CANDriver object - * - * @notapi - */ -void can_lld_start(CANDriver *canp) { - - /* Clock activation.*/ -#if STM32_CAN_USE_CAN1 - if (&CAND1 == canp) { - nvicEnableVector(STM32_CAN1_TX_NUMBER, - CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY)); - nvicEnableVector(STM32_CAN1_RX0_NUMBER, - CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY)); - nvicEnableVector(STM32_CAN1_RX1_NUMBER, - CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY)); - nvicEnableVector(STM32_CAN1_SCE_NUMBER, - CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY)); - rccEnableCAN1(FALSE); - } -#endif -#if STM32_CAN_USE_CAN2 - if (&CAND2 == canp) { - - chDbgAssert(CAND1.state != CAN_STOP, - "can_lld_start(), #1", "CAN1 must be started"); - - nvicEnableVector(STM32_CAN2_TX_NUMBER, - CORTEX_PRIORITY_MASK(STM32_CAN_CAN2_IRQ_PRIORITY)); - nvicEnableVector(STM32_CAN2_RX0_NUMBER, - CORTEX_PRIORITY_MASK(STM32_CAN_CAN2_IRQ_PRIORITY)); - nvicEnableVector(STM32_CAN2_RX1_NUMBER, - CORTEX_PRIORITY_MASK(STM32_CAN_CAN2_IRQ_PRIORITY)); - nvicEnableVector(STM32_CAN2_SCE_NUMBER, - CORTEX_PRIORITY_MASK(STM32_CAN_CAN2_IRQ_PRIORITY)); - rccEnableCAN2(FALSE); - } -#endif - - /* Entering initialization mode. */ - canp->state = CAN_STARTING; - canp->can->MCR = CAN_MCR_INRQ; - while ((canp->can->MSR & CAN_MSR_INAK) == 0) - chThdSleepS(1); - /* BTR initialization.*/ - canp->can->BTR = canp->config->btr; - /* MCR initialization.*/ - canp->can->MCR = canp->config->mcr; - - /* Interrupt sources initialization.*/ - canp->can->IER = CAN_IER_TMEIE | CAN_IER_FMPIE0 | CAN_IER_FMPIE1 | - CAN_IER_WKUIE | CAN_IER_ERRIE | CAN_IER_LECIE | - CAN_IER_BOFIE | CAN_IER_EPVIE | CAN_IER_EWGIE | - CAN_IER_FOVIE0 | CAN_IER_FOVIE1; -} - -/** - * @brief Deactivates the CAN peripheral. - * - * @param[in] canp pointer to the @p CANDriver object - * - * @notapi - */ -void can_lld_stop(CANDriver *canp) { - - /* If in ready state then disables the CAN peripheral.*/ - if (canp->state == CAN_READY) { -#if STM32_CAN_USE_CAN1 - if (&CAND1 == canp) { - -#if STM32_CAN_USE_CAN2 - chDbgAssert(CAND2.state == CAN_STOP, - "can_lld_stop(), #1", "CAN2 must be stopped"); -#endif - - CAN1->MCR = 0x00010002; /* Register reset value. */ - CAN1->IER = 0x00000000; /* All sources disabled. */ - nvicDisableVector(STM32_CAN1_TX_NUMBER); - nvicDisableVector(STM32_CAN1_RX0_NUMBER); - nvicDisableVector(STM32_CAN1_RX1_NUMBER); - nvicDisableVector(STM32_CAN1_SCE_NUMBER); - rccDisableCAN1(FALSE); - } -#endif -#if STM32_CAN_USE_CAN2 - if (&CAND2 == canp) { - CAN2->MCR = 0x00010002; /* Register reset value. */ - CAN2->IER = 0x00000000; /* All sources disabled. */ - nvicDisableVector(STM32_CAN2_TX_NUMBER); - nvicDisableVector(STM32_CAN2_RX0_NUMBER); - nvicDisableVector(STM32_CAN2_RX1_NUMBER); - nvicDisableVector(STM32_CAN2_SCE_NUMBER); - rccDisableCAN2(FALSE); - } -#endif - } -} - -/** - * @brief Determines whether a frame can be transmitted. - * - * @param[in] canp pointer to the @p CANDriver object - * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox - * - * @return The queue space availability. - * @retval FALSE no space in the transmit queue. - * @retval TRUE transmit slot available. - * - * @notapi - */ -bool_t can_lld_is_tx_empty(CANDriver *canp, canmbx_t mailbox) { - - switch (mailbox) { - case CAN_ANY_MAILBOX: - return (canp->can->TSR & CAN_TSR_TME) != 0; - case 1: - return (canp->can->TSR & CAN_TSR_TME0) != 0; - case 2: - return (canp->can->TSR & CAN_TSR_TME1) != 0; - case 3: - return (canp->can->TSR & CAN_TSR_TME2) != 0; - default: - return FALSE; - } -} - -/** - * @brief Inserts a frame into the transmit queue. - * - * @param[in] canp pointer to the @p CANDriver object - * @param[in] ctfp pointer to the CAN frame to be transmitted - * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox - * - * @notapi - */ -void can_lld_transmit(CANDriver *canp, - canmbx_t mailbox, - const CANTxFrame *ctfp) { - uint32_t tir; - CAN_TxMailBox_TypeDef *tmbp; - - /* Pointer to a free transmission mailbox.*/ - switch (mailbox) { - case CAN_ANY_MAILBOX: - tmbp = &canp->can->sTxMailBox[(canp->can->TSR & CAN_TSR_CODE) >> 24]; - break; - case 1: - tmbp = &canp->can->sTxMailBox[0]; - break; - case 2: - tmbp = &canp->can->sTxMailBox[1]; - break; - case 3: - tmbp = &canp->can->sTxMailBox[2]; - break; - default: - return; - } - - /* Preparing the message.*/ - if (ctfp->IDE) - tir = ((uint32_t)ctfp->EID << 3) | ((uint32_t)ctfp->RTR << 1) | - CAN_TI0R_IDE; - else - tir = ((uint32_t)ctfp->SID << 21) | ((uint32_t)ctfp->RTR << 1); - tmbp->TDTR = ctfp->DLC; - tmbp->TDLR = ctfp->data32[0]; - tmbp->TDHR = ctfp->data32[1]; - tmbp->TIR = tir | CAN_TI0R_TXRQ; -} - -/** - * @brief Determines whether a frame has been received. - * - * @param[in] canp pointer to the @p CANDriver object - * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox - * - * @return The queue space availability. - * @retval FALSE no space in the transmit queue. - * @retval TRUE transmit slot available. - * - * @notapi - */ -bool_t can_lld_is_rx_nonempty(CANDriver *canp, canmbx_t mailbox) { - - switch (mailbox) { - case CAN_ANY_MAILBOX: - return ((canp->can->RF0R & CAN_RF0R_FMP0) != 0 || - (canp->can->RF1R & CAN_RF1R_FMP1) != 0); - case 1: - return (canp->can->RF0R & CAN_RF0R_FMP0) != 0; - case 2: - return (canp->can->RF1R & CAN_RF1R_FMP1) != 0; - default: - return FALSE; - } -} - -/** - * @brief Receives a frame from the input queue. - * - * @param[in] canp pointer to the @p CANDriver object - * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox - * @param[out] crfp pointer to the buffer where the CAN frame is copied - * - * @notapi - */ -void can_lld_receive(CANDriver *canp, - canmbx_t mailbox, - CANRxFrame *crfp) { - uint32_t rir, rdtr; - - if (mailbox == CAN_ANY_MAILBOX) { - if ((canp->can->RF0R & CAN_RF0R_FMP0) != 0) - mailbox = 1; - else if ((canp->can->RF1R & CAN_RF1R_FMP1) != 0) - mailbox = 2; - else { - /* Should not happen, do nothing.*/ - return; - } - } - switch (mailbox) { - case 1: - /* Fetches the message.*/ - rir = canp->can->sFIFOMailBox[0].RIR; - rdtr = canp->can->sFIFOMailBox[0].RDTR; - crfp->data32[0] = canp->can->sFIFOMailBox[0].RDLR; - crfp->data32[1] = canp->can->sFIFOMailBox[0].RDHR; - - /* Releases the mailbox.*/ - canp->can->RF0R = CAN_RF0R_RFOM0; - - /* If the queue is empty re-enables the interrupt in order to generate - events again.*/ - if ((canp->can->RF0R & CAN_RF0R_FMP0) == 0) - canp->can->IER |= CAN_IER_FMPIE0; - break; - case 2: - /* Fetches the message.*/ - rir = canp->can->sFIFOMailBox[1].RIR; - rdtr = canp->can->sFIFOMailBox[1].RDTR; - crfp->data32[0] = canp->can->sFIFOMailBox[1].RDLR; - crfp->data32[1] = canp->can->sFIFOMailBox[1].RDHR; - - /* Releases the mailbox.*/ - canp->can->RF1R = CAN_RF1R_RFOM1; - - /* If the queue is empty re-enables the interrupt in order to generate - events again.*/ - if ((canp->can->RF1R & CAN_RF1R_FMP1) == 0) - canp->can->IER |= CAN_IER_FMPIE1; - break; - default: - /* Should not happen, do nothing.*/ - return; - } - - /* Decodes the various fields in the RX frame.*/ - crfp->RTR = (rir & CAN_RI0R_RTR) >> 1; - crfp->IDE = (rir & CAN_RI0R_IDE) >> 2; - if (crfp->IDE) - crfp->EID = rir >> 3; - else - crfp->SID = rir >> 21; - crfp->DLC = rdtr & CAN_RDT0R_DLC; - crfp->FMI = (uint8_t)(rdtr >> 8); - crfp->TIME = (uint16_t)(rdtr >> 16); -} - -#if CAN_USE_SLEEP_MODE || defined(__DOXYGEN__) -/** - * @brief Enters the sleep mode. - * - * @param[in] canp pointer to the @p CANDriver object - * - * @notapi - */ -void can_lld_sleep(CANDriver *canp) { - - canp->can->MCR |= CAN_MCR_SLEEP; -} - -/** - * @brief Enforces leaving the sleep mode. - * - * @param[in] canp pointer to the @p CANDriver object - * - * @notapi - */ -void can_lld_wakeup(CANDriver *canp) { - - canp->can->MCR &= ~CAN_MCR_SLEEP; -} -#endif /* CAN_USE_SLEEP_MODE */ - -/** - * @brief Programs the filters. - * @note This is an STM32-specific API. - * - * @param[in] can2sb number of the first filter assigned to CAN2 - * @param[in] num number of entries in the filters array, if zero then - * a default filter is programmed - * @param[in] cfp pointer to the filters array, can be @p NULL if - * (num == 0) - * - * @api - */ -void canSTM32SetFilters(uint32_t can2sb, uint32_t num, const CANFilter *cfp) { - - chDbgCheck((can2sb >= 1) && (can2sb < STM32_CAN_MAX_FILTERS) && - (num <= STM32_CAN_MAX_FILTERS), - "canSTM32SetFilters"); - -#if STM32_CAN_USE_CAN1 - chDbgAssert(CAND1.state == CAN_STOP, - "canSTM32SetFilters(), #1", "invalid state"); -#endif -#if STM32_CAN_USE_CAN2 - chDbgAssert(CAND2.state == CAN_STOP, - "canSTM32SetFilters(), #2", "invalid state"); -#endif - - can_lld_set_filters(can2sb, num, cfp); -} - -#endif /* HAL_USE_CAN */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/can_lld.h b/firmware/chibios/os/hal/platforms/STM32/can_lld.h deleted file mode 100644 index 7a037c4a35..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/can_lld.h +++ /dev/null @@ -1,367 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/can_lld.h - * @brief STM32 CAN subsystem low level driver header. - * - * @addtogroup CAN - * @{ - */ - -#ifndef _CAN_LLD_H_ -#define _CAN_LLD_H_ - -#if HAL_USE_CAN || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/* - * The following macros from the ST header file are replaced with better - * equivalents. - */ -#undef CAN_BTR_BRP -#undef CAN_BTR_TS1 -#undef CAN_BTR_TS2 -#undef CAN_BTR_SJW - -/** - * @brief This switch defines whether the driver implementation supports - * a low power switch mode with automatic an wakeup feature. - */ -#define CAN_SUPPORTS_SLEEP TRUE - -/** - * @brief This implementation supports three transmit mailboxes. - */ -#define CAN_TX_MAILBOXES 3 - -/** - * @brief This implementation supports two receive mailboxes. - */ -#define CAN_RX_MAILBOXES 2 - -/** - * @name CAN registers helper macros - * @{ - */ -#define CAN_BTR_BRP(n) (n) /**< @brief BRP field macro.*/ -#define CAN_BTR_TS1(n) ((n) << 16) /**< @brief TS1 field macro.*/ -#define CAN_BTR_TS2(n) ((n) << 20) /**< @brief TS2 field macro.*/ -#define CAN_BTR_SJW(n) ((n) << 24) /**< @brief SJW field macro.*/ - -#define CAN_IDE_STD 0 /**< @brief Standard id. */ -#define CAN_IDE_EXT 1 /**< @brief Extended id. */ - -#define CAN_RTR_DATA 0 /**< @brief Data frame. */ -#define CAN_RTR_REMOTE 1 /**< @brief Remote frame. */ -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief CAN1 driver enable switch. - * @details If set to @p TRUE the support for CAN1 is included. - */ -#if !defined(STM32_CAN_USE_CAN1) || defined(__DOXYGEN__) -#define STM32_CAN_USE_CAN1 FALSE -#endif - -/** - * @brief CAN2 driver enable switch. - * @details If set to @p TRUE the support for CAN2 is included. - */ -#if !defined(STM32_CAN_USE_CAN2) || defined(__DOXYGEN__) -#define STM32_CAN_USE_CAN2 FALSE -#endif - -/** - * @brief CAN1 interrupt priority level setting. - */ -#if !defined(STM32_CAN_CAN1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_CAN_CAN1_IRQ_PRIORITY 11 -#endif -/** @} */ - -/** - * @brief CAN2 interrupt priority level setting. - */ -#if !defined(STM32_CAN_CAN2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_CAN_CAN2_IRQ_PRIORITY 11 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_CAN_USE_CAN1 && !STM32_HAS_CAN1 -#error "CAN1 not present in the selected device" -#endif - -#if STM32_CAN_USE_CAN2 && !STM32_HAS_CAN2 -#error "CAN2 not present in the selected device" -#endif - -#if !STM32_CAN_USE_CAN1 && !STM32_CAN_USE_CAN2 -#error "CAN driver activated but no CAN peripheral assigned" -#endif - -#if !STM32_CAN_USE_CAN1 && STM32_CAN_USE_CAN2 -#error "CAN2 requires CAN1, it cannot operate independently" -#endif - -#if CAN_USE_SLEEP_MODE && !CAN_SUPPORTS_SLEEP -#error "CAN sleep mode not supported in this architecture" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a transmission mailbox index. - */ -typedef uint32_t canmbx_t; - -/** - * @brief CAN transmission frame. - * @note Accessing the frame data as word16 or word32 is not portable because - * machine data endianness, it can be still useful for a quick filling. - */ -typedef struct { - struct { - uint8_t DLC:4; /**< @brief Data length. */ - uint8_t RTR:1; /**< @brief Frame type. */ - uint8_t IDE:1; /**< @brief Identifier type. */ - }; - union { - struct { - uint32_t SID:11; /**< @brief Standard identifier.*/ - }; - struct { - uint32_t EID:29; /**< @brief Extended identifier.*/ - }; - }; - union { - uint8_t data8[8]; /**< @brief Frame data. */ - uint16_t data16[4]; /**< @brief Frame data. */ - uint32_t data32[2]; /**< @brief Frame data. */ - }; -} CANTxFrame; - -/** - * @brief CAN received frame. - * @note Accessing the frame data as word16 or word32 is not portable because - * machine data endianness, it can be still useful for a quick filling. - */ -typedef struct { - struct { - uint8_t FMI; /**< @brief Filter id. */ - uint16_t TIME; /**< @brief Time stamp. */ - }; - struct { - uint8_t DLC:4; /**< @brief Data length. */ - uint8_t RTR:1; /**< @brief Frame type. */ - uint8_t IDE:1; /**< @brief Identifier type. */ - }; - union { - struct { - uint32_t SID:11; /**< @brief Standard identifier.*/ - }; - struct { - uint32_t EID:29; /**< @brief Extended identifier.*/ - }; - }; - union { - uint8_t data8[8]; /**< @brief Frame data. */ - uint16_t data16[4]; /**< @brief Frame data. */ - uint32_t data32[2]; /**< @brief Frame data. */ - }; -} CANRxFrame; - -/** - * @brief CAN filter. - * @note Refer to the STM32 reference manual for info about filters. - */ -typedef struct { - /** - * @brief Number of the filter to be programmed. - */ - uint32_t filter; - /** - * @brief Filter mode. - * @note This bit represent the CAN_FM1R register bit associated to this - * filter (0=mask mode, 1=list mode). - */ - uint32_t mode:1; - /** - * @brief Filter scale. - * @note This bit represent the CAN_FS1R register bit associated to this - * filter (0=16 bits mode, 1=32 bits mode). - */ - uint32_t scale:1; - /** - * @brief Filter mode. - * @note This bit represent the CAN_FFA1R register bit associated to this - * filter, must be set to zero in this version of the driver. - */ - uint32_t assignment:1; - /** - * @brief Filter register 1 (identifier). - */ - uint32_t register1; - /** - * @brief Filter register 2 (mask/identifier depending on mode=0/1). - */ - uint32_t register2; -} CANFilter; - -/** - * @brief Driver configuration structure. - */ -typedef struct { - /** - * @brief CAN MCR register initialization data. - * @note Some bits in this register are enforced by the driver regardless - * their status in this field. - */ - uint32_t mcr; - /** - * @brief CAN BTR register initialization data. - * @note Some bits in this register are enforced by the driver regardless - * their status in this field. - */ - uint32_t btr; -} CANConfig; - -/** - * @brief Structure representing an CAN driver. - */ -typedef struct { - /** - * @brief Driver state. - */ - canstate_t state; - /** - * @brief Current configuration data. - */ - const CANConfig *config; - /** - * @brief Transmission queue semaphore. - */ - Semaphore txsem; - /** - * @brief Receive queue semaphore. - */ - Semaphore rxsem; - /** - * @brief One or more frames become available. - * @note After broadcasting this event it will not be broadcasted again - * until the received frames queue has been completely emptied. It - * is not broadcasted for each received frame. It is - * responsibility of the application to empty the queue by - * repeatedly invoking @p chReceive() when listening to this event. - * This behavior minimizes the interrupt served by the system - * because CAN traffic. - * @note The flags associated to the listeners will indicate which - * receive mailboxes become non-empty. - */ - EventSource rxfull_event; - /** - * @brief One or more transmission mailbox become available. - * @note The flags associated to the listeners will indicate which - * transmit mailboxes become empty. - * - */ - EventSource txempty_event; - /** - * @brief A CAN bus error happened. - * @note The flags associated to the listeners will indicate the - * error(s) that have occurred. - */ - EventSource error_event; -#if CAN_USE_SLEEP_MODE || defined (__DOXYGEN__) - /** - * @brief Entering sleep state event. - */ - EventSource sleep_event; - /** - * @brief Exiting sleep state event. - */ - EventSource wakeup_event; -#endif /* CAN_USE_SLEEP_MODE */ - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the CAN registers. - */ - CAN_TypeDef *can; -} CANDriver; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_CAN_USE_CAN1 && !defined(__DOXYGEN__) -extern CANDriver CAND1; -#endif - -#if STM32_CAN_USE_CAN2 && !defined(__DOXYGEN__) -extern CANDriver CAND2; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void can_lld_init(void); - void can_lld_start(CANDriver *canp); - void can_lld_stop(CANDriver *canp); - bool_t can_lld_is_tx_empty(CANDriver *canp, - canmbx_t mailbox); - void can_lld_transmit(CANDriver *canp, - canmbx_t mailbox, - const CANTxFrame *crfp); - bool_t can_lld_is_rx_nonempty(CANDriver *canp, - canmbx_t mailbox); - void can_lld_receive(CANDriver *canp, - canmbx_t mailbox, - CANRxFrame *ctfp); -#if CAN_USE_SLEEP_MODE - void can_lld_sleep(CANDriver *canp); - void can_lld_wakeup(CANDriver *canp); -#endif /* CAN_USE_SLEEP_MODE */ - void canSTM32SetFilters(uint32_t can2sb, uint32_t num, const CANFilter *cfp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_CAN */ - -#endif /* _CAN_LLD_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/ext_lld.c b/firmware/chibios/os/hal/platforms/STM32/ext_lld.c deleted file mode 100644 index 6dee976196..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/ext_lld.c +++ /dev/null @@ -1,223 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/ext_lld.c - * @brief STM32 EXT subsystem low level driver source. - * - * @addtogroup EXT - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -#include "ext_lld_isr.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief EXTD1 driver identifier. - */ -EXTDriver EXTD1; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level EXT driver initialization. - * - * @notapi - */ -void ext_lld_init(void) { - - /* Driver initialization.*/ - extObjectInit(&EXTD1); -} - -/** - * @brief Configures and activates the EXT peripheral. - * - * @param[in] extp pointer to the @p EXTDriver object - * - * @notapi - */ -void ext_lld_start(EXTDriver *extp) { - unsigned i; - - if (extp->state == EXT_STOP) - ext_lld_exti_irq_enable(); - - /* Configuration of automatic channels.*/ - for (i = 0; i < EXT_MAX_CHANNELS; i++) - if (extp->config->channels[i].mode & EXT_CH_MODE_AUTOSTART) - ext_lld_channel_enable(extp, i); - else - ext_lld_channel_disable(extp, i); -} - -/** - * @brief Deactivates the EXT peripheral. - * - * @param[in] extp pointer to the @p EXTDriver object - * - * @notapi - */ -void ext_lld_stop(EXTDriver *extp) { - - if (extp->state == EXT_ACTIVE) - ext_lld_exti_irq_disable(); - - EXTI->EMR = 0; - EXTI->IMR = 0; - EXTI->PR = 0xFFFFFFFF; -#if STM32_EXTI_NUM_CHANNELS > 32 - EXTI->PR2 = 0xFFFFFFFF; -#endif -} - -/** - * @brief Enables an EXT channel. - * - * @param[in] extp pointer to the @p EXTDriver object - * @param[in] channel channel to be enabled - * - * @notapi - */ -void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) { - - /* Setting the associated GPIO for external channels.*/ - if (channel < 16) { - uint32_t n = channel >> 2; - uint32_t mask = ~(0xF << ((channel & 3) * 4)); - uint32_t port = ((extp->config->channels[channel].mode & - EXT_MODE_GPIO_MASK) >> - EXT_MODE_GPIO_OFF) << ((channel & 3) * 4); - -#if defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \ - defined(STM32F10X_HD_VL) || defined(STM32F10X_LD) || \ - defined(STM32F10X_MD) || defined(STM32F10X_HD) || \ - defined(STM32F10X_XL) || defined(STM32F10X_CL) - AFIO->EXTICR[n] = (AFIO->EXTICR[n] & mask) | port; -#else /* !defined(STM32F1XX) */ - SYSCFG->EXTICR[n] = (SYSCFG->EXTICR[n] & mask) | port; -#endif /* !defined(STM32F1XX) */ - } - -#if STM32_EXTI_NUM_CHANNELS > 32 - if (channel < 32) { -#endif - /* Programming edge registers.*/ - if (extp->config->channels[channel].mode & EXT_CH_MODE_RISING_EDGE) - EXTI->RTSR |= (1 << channel); - else - EXTI->RTSR &= ~(1 << channel); - if (extp->config->channels[channel].mode & EXT_CH_MODE_FALLING_EDGE) - EXTI->FTSR |= (1 << channel); - else - EXTI->FTSR &= ~(1 << channel); - - /* Programming interrupt and event registers.*/ - if (extp->config->channels[channel].cb != NULL) { - EXTI->IMR |= (1 << channel); - EXTI->EMR &= ~(1 << channel); - } - else { - EXTI->EMR |= (1 << channel); - EXTI->IMR &= ~(1 << channel); - } -#if STM32_EXTI_NUM_CHANNELS > 32 - } - else { - /* Programming edge registers.*/ - if (extp->config->channels[channel].mode & EXT_CH_MODE_RISING_EDGE) - EXTI->RTSR2 |= (1 << (32 - channel)); - else - EXTI->RTSR2 &= ~(1 << (32 - channel)); - if (extp->config->channels[channel].mode & EXT_CH_MODE_FALLING_EDGE) - EXTI->FTSR2 |= (1 << (32 - channel)); - else - EXTI->FTSR2 &= ~(1 << (32 - channel)); - - /* Programming interrupt and event registers.*/ - if (extp->config->channels[channel].cb != NULL) { - EXTI->IMR2 |= (1 << (32 - channel)); - EXTI->EMR2 &= ~(1 << (32 - channel)); - } - else { - EXTI->EMR2 |= (1 << (32 - channel)); - EXTI->IMR2 &= ~(1 << (32 - channel)); - } - } -#endif -} - -/** - * @brief Disables an EXT channel. - * - * @param[in] extp pointer to the @p EXTDriver object - * @param[in] channel channel to be disabled - * - * @notapi - */ -void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) { - - (void)extp; - -#if STM32_EXTI_NUM_CHANNELS > 32 - if (channel < 32) { -#endif - EXTI->IMR &= ~(1 << channel); - EXTI->EMR &= ~(1 << channel); - EXTI->RTSR &= ~(1 << channel); - EXTI->FTSR &= ~(1 << channel); - EXTI->PR = (1 << channel); -#if STM32_EXTI_NUM_CHANNELS > 32 - } - else { - EXTI->IMR2 &= ~(1 << (32 - channel)); - EXTI->EMR2 &= ~(1 << (32 - channel)); - EXTI->RTSR2 &= ~(1 << (32 - channel)); - EXTI->FTSR2 &= ~(1 << (32 - channel)); - EXTI->PR2 = (1 << (32 - channel)); - } -#endif -} - -#endif /* HAL_USE_EXT */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/ext_lld.h b/firmware/chibios/os/hal/platforms/STM32/ext_lld.h deleted file mode 100644 index 9736b9796c..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/ext_lld.h +++ /dev/null @@ -1,153 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/ext_lld.h - * @brief STM32 EXT subsystem low level driver header. - * - * @addtogroup EXT - * @{ - */ - -#ifndef _EXT_LLD_H_ -#define _EXT_LLD_H_ - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Available number of EXT channels. - */ -#define EXT_MAX_CHANNELS STM32_EXTI_NUM_CHANNELS - -/** - * @name STM32-specific EXT channel modes - * @{ - */ -#define EXT_MODE_GPIO_MASK 0xF0 /**< @brief Port field mask. */ -#define EXT_MODE_GPIO_OFF 4 /**< @brief Port field offset. */ -#define EXT_MODE_GPIOA 0x00 /**< @brief GPIOA identifier. */ -#define EXT_MODE_GPIOB 0x10 /**< @brief GPIOB identifier. */ -#define EXT_MODE_GPIOC 0x20 /**< @brief GPIOC identifier. */ -#define EXT_MODE_GPIOD 0x30 /**< @brief GPIOD identifier. */ -#define EXT_MODE_GPIOE 0x40 /**< @brief GPIOE identifier. */ -#define EXT_MODE_GPIOF 0x50 /**< @brief GPIOF identifier. */ -#define EXT_MODE_GPIOG 0x60 /**< @brief GPIOG identifier. */ -#define EXT_MODE_GPIOH 0x70 /**< @brief GPIOH identifier. */ -#define EXT_MODE_GPIOI 0x80 /**< @brief GPIOI identifier. */ -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief EXT channel identifier. - */ -typedef uint32_t expchannel_t; - -/** - * @brief Type of an EXT generic notification callback. - * - * @param[in] extp pointer to the @p EXPDriver object triggering the - * callback - */ -typedef void (*extcallback_t)(EXTDriver *extp, expchannel_t channel); - -/** - * @brief Channel configuration structure. - */ -typedef struct { - /** - * @brief Channel mode. - */ - uint32_t mode; - /** - * @brief Channel callback. - * @details In the STM32 implementation a @p NULL callback pointer is - * valid and configures the channel as an event sources instead - * of an interrupt source. - */ - extcallback_t cb; -} EXTChannelConfig; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief Channel configurations. - */ - EXTChannelConfig channels[EXT_MAX_CHANNELS]; - /* End of the mandatory fields.*/ -} EXTConfig; - -/** - * @brief Structure representing an EXT driver. - */ -struct EXTDriver { - /** - * @brief Driver state. - */ - extstate_t state; - /** - * @brief Current configuration data. - */ - const EXTConfig *config; - /* End of the mandatory fields.*/ -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -extern EXTDriver EXTD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void ext_lld_init(void); - void ext_lld_start(EXTDriver *extp); - void ext_lld_stop(EXTDriver *extp); - void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel); - void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_EXT */ - -#endif /* _EXT_LLD_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/i2s_lld.c b/firmware/chibios/os/hal/platforms/STM32/i2s_lld.c deleted file mode 100644 index b92ca0a865..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/i2s_lld.c +++ /dev/null @@ -1,161 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/i2s_lld.c - * @brief I2S Driver subsystem low level driver source template. - * - * @addtogroup I2S - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_I2S || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level I2S driver initialization. - * - * @notapi - */ -void i2s_lld_init(void) { - -#if STM32_I2S_USE_I2S2 - spiObjectInit(&I2SD2); - I2SD2.spi = SPI2; -#endif - -#if STM32_I2S_USE_I2S3 - spiObjectInit(&I2SD3); - I2SD3.spi = SPI3; -#endif -} - -/** - * @brief Configures and activates the I2S peripheral. - * - * @param[in] i2sp pointer to the @p I2SDriver object - * - * @notapi - */ -void i2s_lld_start(I2SDriver *i2sp) { - - /* If in stopped state then enables the SPI and DMA clocks.*/ - if (i2sp->state == I2S_STOP) { -#if STM32_SPI_USE_SPI2 - if (&SPID2 == spip) { - bool_t b; - b = dmaStreamAllocate(spip->dma, - STM32_I2S_I2S2_IRQ_PRIORITY, - (stm32_dmaisr_t)i2s_lld_serve_rx_interrupt, - (void *)spip); - chDbgAssert(!b, "spi_lld_start(), #1", "stream already allocated"); - rccEnableSPI2(FALSE); - } -#endif -#if STM32_SPI_USE_SPI3 - if (&SPID3 == spip) { - bool_t b; - b = dmaStreamAllocate(spip->dma, - STM32_I2S_I2S3_IRQ_PRIORITY, - (stm32_dmaisr_t)i2s_lld_serve_rx_interrupt, - (void *)spip); - chDbgAssert(!b, "spi_lld_start(), #2", "stream already allocated"); - rccEnableSPI3(FALSE); - } -#endif - } - /* Configuration.*/ -} - -/** - * @brief Deactivates the I2S peripheral. - * - * @param[in] i2sp pointer to the @p I2SDriver object - * - * @notapi - */ -void i2s_lld_stop(I2SDriver *i2sp) { - - if (i2sp->state == I2S_READY) { - /* Clock deactivation.*/ - - } -} - -/** - * @brief Starts a I2S data exchange. - * - * @param[in] i2sp pointer to the @p I2SDriver object - * - * @notapi - */ -void i2s_lld_start_exchange(I2SDriver *i2sp) { - -} - -/** - * @brief Starts a I2S data exchange in continuous mode. - * - * @param[in] i2sp pointer to the @p I2SDriver object - * - * @notapi - */ -void i2s_lld_start_exchange_continuous(I2SDriver *i2sp) { - -} - -/** - * @brief Stops the ongoing data exchange. - * @details The ongoing data exchange, if any, is stopped, if the driver - * was not active the function does nothing. - * - * @param[in] i2sp pointer to the @p I2SDriver object - * - * @notapi - */ -void i2s_lld_stop_exchange(I2SDriver *i2sp) { - -} - -#endif /* HAL_USE_I2S */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/i2s_lld.h b/firmware/chibios/os/hal/platforms/STM32/i2s_lld.h deleted file mode 100644 index ce73129fa4..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/i2s_lld.h +++ /dev/null @@ -1,317 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/i2s_lld.h - * @brief I2S Driver subsystem low level driver header template. - * - * @addtogroup I2S - * @{ - */ - -#ifndef _I2S_LLD_H_ -#define _I2S_LLD_H_ - -#if HAL_USE_I2S || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief I2S2 driver enable switch. - * @details If set to @p TRUE the support for I2S2 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_I2S_USE_I2S2) || defined(__DOXYGEN__) -#define STM32_I2S_USE_I2S2 FALSE -#endif - -/** - * @brief I2S3 driver enable switch. - * @details If set to @p TRUE the support for I2S3 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_I2S_USE_I2S3) || defined(__DOXYGEN__) -#define STM32_I2S_USE_I2S3 FALSE -#endif - -/** - * @brief I2S2 interrupt priority level setting. - */ -#if !defined(STM32_I2S_I2S2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2S_I2S2_IRQ_PRIORITY 10 -#endif - -/** - * @brief I2S3 interrupt priority level setting. - */ -#if !defined(STM32_I2S_I2S3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2S_I2S3_IRQ_PRIORITY 10 -#endif - -/** - * @brief I2S2 DMA priority (0..3|lowest..highest). - */ -#if !defined(STM32_I2S_I2S2_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2S_I2S2_DMA_PRIORITY 1 -#endif - -/** - * @brief I2S3 DMA priority (0..3|lowest..highest). - */ -#if !defined(STM32_I2S_I2S2_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2S_I2S2_DMA_PRIORITY 1 -#endif - -/** - * @brief I2S DMA error hook. - */ -#if !defined(STM32_I2S_DMA_ERROR_HOOK) || defined(__DOXYGEN__) -#define STM32_I2S_DMA_ERROR_HOOK(i2sp) chSysHalt() -#endif - -#if STM32_ADVANCED_DMA || defined(__DOXYGEN__) - -/** - * @brief DMA stream used for I2S2 RX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_I2S_I2S2_RX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_I2S_I2S2_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#endif - -/** - * @brief DMA stream used for I2S2 TX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_I2S_I2S2_TX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_I2S_I2S2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#endif - -/** - * @brief DMA stream used for I2S3 RX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_I2S_I2S3_RX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_I2S_I2S3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#endif - -/** - * @brief DMA stream used for I2S3 TX operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_I2S_I2S3_TX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_I2S_I2S3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#endif - -#else /* !STM32_ADVANCED_DMA */ - -/* Fixed streams for platforms using the old DMA peripheral, the values are - valid for both STM32F1xx and STM32L1xx.*/ -#define STM32_I2S_I2S2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2S_I2S2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_I2S_I2S3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_I2S_I2S3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) - -#endif /* !STM32_ADVANCED_DMA */ -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_I2S_USE_I2S2 && !STM32_HAS_SPI2 -#error "SPI2 not present in the selected device" -#endif - -#if STM32_I2S_USE_I2S3 && !STM32_HAS_SPI3 -#error "SPI3 not present in the selected device" -#endif - -#if !STM32_I2S_USE_I2S2 && !STM32_I2S_USE_I2S3 -#error "I2S driver activated but no I2S peripheral assigned" -#endif - -#if STM32_I2S_USE_I2S2 && \ - !STM32_DMA_IS_VALID_ID(STM32_I2S_I2S2_RX_DMA_STREAM, STM32_SPI2_RX_DMA_MSK) -#error "invalid DMA stream associated to I2S2 RX" -#endif - -#if STM32_I2S_USE_I2S2 && \ - !STM32_DMA_IS_VALID_ID(STM32_I2S_I2S2_TX_DMA_STREAM, STM32_SPI2_TX_DMA_MSK) -#error "invalid DMA stream associated to I2S2 TX" -#endif - -#if STM32_I2S_USE_I2S3 && \ - !STM32_DMA_IS_VALID_ID(STM32_I2S_I2S3_RX_DMA_STREAM, STM32_SPI3_RX_DMA_MSK) -#error "invalid DMA stream associated to I2S3 RX" -#endif - -#if STM32_I2S_USE_I2S3 && \ - !STM32_DMA_IS_VALID_ID(STM32_I2S_I2S3_TX_DMA_STREAM, STM32_SPI3_TX_DMA_MSK) -#error "invalid DMA stream associated to I2S3 TX" -#endif - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief I2S mode type. - */ -typedef uint32_t i2smode_t; - -/** - * @brief Type of a structure representing an I2S driver. - */ -typedef struct I2SDriver I2SDriver; - -/** - * @brief I2S notification callback type. - * - * @param[in] i2sp pointer to the @p I2SDriver object - * @param[in] buffer pointer to the buffer - * @param[in] n number of sample positions starting from @p buffer - */ -typedef void (*i2scallback_t)(I2SDriver *i2sp, void *buffer, size_t n); - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief I2S mode selection. - */ - i2smode_t mode; - /** - * @brief Transmission buffer pointer. - */ - const void *tx_buffer; - /** - * @brief Transmission buffer size in number of samples. - */ - size_t tx_size; - /** - * @brief Callback function associated to the transmission or @p NULL. - */ - i2scallback_t tx_cb; - /** - * @brief Receive buffer pointer. - */ - void *rx_buffer; - /** - * @brief Receive buffer size in number of samples. - */ - size_t rx_size; - /** - * @brief Callback function associated to the reception or @p NULL. - */ - i2scallback_t rx_cb;; - /* End of the mandatory fields.*/ - /** - * @brief Configuration of the I2SCFGR register. - * @details See the STM32 reference manual, this register is used for - * the I2S configuration, the following bits must not be - * specified because handled directly by the driver: - * - I2SMOD - * - I2SE - * - I2SCFG - * . - */ - int16_t i2scfgr; - /** - * @brief Configuration of the I2SPR register. - * @details See the STM32 reference manual, this register is used for - * the I2S clock setup. - */ - int16_t i2spr; -} I2SConfig; - -/** - * @brief Structure representing an I2S driver. - */ -struct I2SDriver { - /** - * @brief Driver state. - */ - i2sstate_t state; - /** - * @brief Current configuration data. - */ - const I2SConfig *config; - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the SPIx registers block. - */ - SPI_TypeDef *spi; - /** - * @brief DMA stream. - */ - const stm32_dma_stream_t *dma; - /** - * @brief DMA mode bit mask. - */ - uint32_t dmamode; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_I2S_USE_I2S2 && !defined(__DOXYGEN__) -extern I2SDriver I2SD2; -#endif - -#if STM32_I2S_USE_I2S3 && !defined(__DOXYGEN__) -extern I2SDriver I2SD3; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void i2s_lld_init(void); - void i2s_lld_start(I2SDriver *i2sp); - void i2s_lld_stop(I2SDriver *i2sp); - void i2s_lld_start_exchange(I2SDriver *i2sp); - void i2s_lld_start_exchange_continuous(I2SDriver *i2sp); - void i2s_lld_stop_exchange(I2SDriver *i2sp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_I2S */ - -#endif /* _I2S_LLD_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/mac_lld.c b/firmware/chibios/os/hal/platforms/STM32/mac_lld.c deleted file mode 100644 index a237ca3f0c..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/mac_lld.c +++ /dev/null @@ -1,745 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/mac_lld.c - * @brief STM32 low level MAC driver code. - * - * @addtogroup MAC - * @{ - */ - -#include - -#include "ch.h" -#include "hal.h" -#include "mii.h" - -#if HAL_USE_MAC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define BUFFER_SIZE ((((STM32_MAC_BUFFERS_SIZE - 1) | 3) + 1) / 4) - -/* MII divider optimal value.*/ -#if (STM32_HCLK >= 150000000) -#define MACMIIDR_CR ETH_MACMIIAR_CR_Div102 -#elif (STM32_HCLK >= 100000000) -#define MACMIIDR_CR ETH_MACMIIAR_CR_Div62 -#elif (STM32_HCLK >= 60000000) -#define MACMIIDR_CR ETH_MACMIIAR_CR_Div42 -#elif (STM32_HCLK >= 35000000) -#define MACMIIDR_CR ETH_MACMIIAR_CR_Div26 -#elif (STM32_HCLK >= 20000000) -#define MACMIIDR_CR ETH_MACMIIAR_CR_Div16 -#else -#error "STM32_HCLK below minimum frequency for ETH operations (20MHz)" -#endif - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief Ethernet driver 1. - */ -MACDriver ETHD1; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -static const uint8_t default_mac_address[] = {0xAA, 0x55, 0x13, - 0x37, 0x01, 0x10}; - -static stm32_eth_rx_descriptor_t rd[STM32_MAC_RECEIVE_BUFFERS]; -static stm32_eth_tx_descriptor_t td[STM32_MAC_TRANSMIT_BUFFERS]; - -static uint32_t rb[STM32_MAC_RECEIVE_BUFFERS][BUFFER_SIZE]; -static uint32_t tb[STM32_MAC_TRANSMIT_BUFFERS][BUFFER_SIZE]; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Writes a PHY register. - * - * @param[in] macp pointer to the @p MACDriver object - * @param[in] reg register number - * @param[in] value new register value - * - * @notapi - */ -void mii_write(MACDriver *macp, uint32_t reg, uint32_t value) { - - ETH->MACMIIDR = value; - ETH->MACMIIAR = macp->phyaddr | (reg << 6) | MACMIIDR_CR | - ETH_MACMIIAR_MW | ETH_MACMIIAR_MB; - while ((ETH->MACMIIAR & ETH_MACMIIAR_MB) != 0) - ; -} - -/** - * @brief Reads a PHY register. - * - * @param[in] macp pointer to the @p MACDriver object - * @param[in] reg register number - * - * @return The PHY register content. - * - * @notapi - */ -uint32_t mii_read(MACDriver *macp, uint32_t reg) { - - ETH->MACMIIAR = macp->phyaddr | (reg << 6) | MACMIIDR_CR | ETH_MACMIIAR_MB; - while ((ETH->MACMIIAR & ETH_MACMIIAR_MB) != 0) - ; - return ETH->MACMIIDR; -} - -#if !defined(BOARD_PHY_ADDRESS) -/** - * @brief PHY address detection. - * - * @param[in] macp pointer to the @p MACDriver object - */ -static void mii_find_phy(MACDriver *macp) { - uint32_t i; - -#if STM32_MAC_PHY_TIMEOUT > 0 - halrtcnt_t start = halGetCounterValue(); - halrtcnt_t timeout = start + MS2RTT(STM32_MAC_PHY_TIMEOUT); - while (halIsCounterWithin(start, timeout)) { -#endif - for (i = 0; i < 31; i++) { - macp->phyaddr = i << 11; - ETH->MACMIIDR = (i << 6) | MACMIIDR_CR; - if ((mii_read(macp, MII_PHYSID1) == (BOARD_PHY_ID >> 16)) && - ((mii_read(macp, MII_PHYSID2) & 0xFFF0) == (BOARD_PHY_ID & 0xFFF0))) { - return; - } - } -#if STM32_MAC_PHY_TIMEOUT > 0 - } -#endif - /* Wrong or defective board.*/ - chSysHalt(); -} -#endif - -/** - * @brief MAC address setup. - * - * @param[in] p pointer to a six bytes buffer containing the MAC - * address - */ -static void mac_lld_set_address(const uint8_t *p) { - - /* MAC address configuration, only a single address comparator is used, - hash table not used.*/ - ETH->MACA0HR = ((uint32_t)p[5] << 8) | - ((uint32_t)p[4] << 0); - ETH->MACA0LR = ((uint32_t)p[3] << 24) | - ((uint32_t)p[2] << 16) | - ((uint32_t)p[1] << 8) | - ((uint32_t)p[0] << 0); - ETH->MACA1HR = 0x0000FFFF; - ETH->MACA1LR = 0xFFFFFFFF; - ETH->MACA2HR = 0x0000FFFF; - ETH->MACA2LR = 0xFFFFFFFF; - ETH->MACA3HR = 0x0000FFFF; - ETH->MACA3LR = 0xFFFFFFFF; - ETH->MACHTHR = 0; - ETH->MACHTLR = 0; -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -CH_IRQ_HANDLER(ETH_IRQHandler) { - uint32_t dmasr; - - CH_IRQ_PROLOGUE(); - - dmasr = ETH->DMASR; - ETH->DMASR = dmasr; /* Clear status bits.*/ - - if (dmasr & ETH_DMASR_RS) { - /* Data Received.*/ - chSysLockFromIsr(); - chSemResetI(ÐD1.rdsem, 0); -#if MAC_USE_EVENTS - chEvtBroadcastI(ÐD1.rdevent); -#endif - chSysUnlockFromIsr(); - } - - if (dmasr & ETH_DMASR_TS) { - /* Data Transmitted.*/ - chSysLockFromIsr(); - chSemResetI(ÐD1.tdsem, 0); - chSysUnlockFromIsr(); - } - - CH_IRQ_EPILOGUE(); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level MAC initialization. - * - * @notapi - */ -void mac_lld_init(void) { - unsigned i; - - macObjectInit(ÐD1); - ETHD1.link_up = FALSE; - - /* Descriptor tables are initialized in chained mode, note that the first - word is not initialized here but in mac_lld_start().*/ - for (i = 0; i < STM32_MAC_RECEIVE_BUFFERS; i++) { - rd[i].rdes1 = STM32_RDES1_RCH | STM32_MAC_BUFFERS_SIZE; - rd[i].rdes2 = (uint32_t)rb[i]; - rd[i].rdes3 = (uint32_t)&rd[(i + 1) % STM32_MAC_RECEIVE_BUFFERS]; - } - for (i = 0; i < STM32_MAC_TRANSMIT_BUFFERS; i++) { - td[i].tdes1 = 0; - td[i].tdes2 = (uint32_t)tb[i]; - td[i].tdes3 = (uint32_t)&td[(i + 1) % STM32_MAC_TRANSMIT_BUFFERS]; - } - - /* Selection of the RMII or MII mode based on info exported by board.h.*/ -#if defined(STM32F10X_CL) -#if defined(BOARD_PHY_RMII) - AFIO->MAPR |= AFIO_MAPR_MII_RMII_SEL; -#else - AFIO->MAPR &= ~AFIO_MAPR_MII_RMII_SEL; -#endif -#elif defined(STM32F2XX) || defined(STM32F4XX) -#if defined(BOARD_PHY_RMII) - SYSCFG->PMC |= SYSCFG_PMC_MII_RMII_SEL; -#else - SYSCFG->PMC &= ~SYSCFG_PMC_MII_RMII_SEL; -#endif -#else -#error "unsupported STM32 platform for MAC driver" -#endif - - /* Reset of the MAC core.*/ - rccResetETH(); - - /* MAC clocks temporary activation.*/ - rccEnableETH(FALSE); - - /* PHY address setup.*/ -#if defined(BOARD_PHY_ADDRESS) - ETHD1.phyaddr = BOARD_PHY_ADDRESS << 11; -#else - mii_find_phy(ÐD1); -#endif - -#if defined(BOARD_PHY_RESET) - /* PHY board-specific reset procedure.*/ - BOARD_PHY_RESET(); -#else - /* PHY soft reset procedure.*/ - mii_write(ÐD1, MII_BMCR, BMCR_RESET); -#if defined(BOARD_PHY_RESET_DELAY) - halPolledDelay(BOARD_PHY_RESET_DELAY); -#endif - while (mii_read(ÐD1, MII_BMCR) & BMCR_RESET) - ; -#endif - -#if STM32_MAC_ETH1_CHANGE_PHY_STATE - /* PHY in power down mode until the driver will be started.*/ - mii_write(ÐD1, MII_BMCR, mii_read(ÐD1, MII_BMCR) | BMCR_PDOWN); -#endif - - /* MAC clocks stopped again.*/ - rccDisableETH(FALSE); -} - -/** - * @brief Configures and activates the MAC peripheral. - * - * @param[in] macp pointer to the @p MACDriver object - * - * @notapi - */ -void mac_lld_start(MACDriver *macp) { - unsigned i; - - /* Resets the state of all descriptors.*/ - for (i = 0; i < STM32_MAC_RECEIVE_BUFFERS; i++) - rd[i].rdes0 = STM32_RDES0_OWN; - macp->rxptr = (stm32_eth_rx_descriptor_t *)rd; - for (i = 0; i < STM32_MAC_TRANSMIT_BUFFERS; i++) - td[i].tdes0 = STM32_TDES0_TCH; - macp->txptr = (stm32_eth_tx_descriptor_t *)td; - - /* MAC clocks activation and commanded reset procedure.*/ - rccEnableETH(FALSE); -#if defined(STM32_MAC_DMABMR_SR) - ETH->DMABMR |= ETH_DMABMR_SR; - while(ETH->DMABMR & ETH_DMABMR_SR) - ; -#endif - - /* ISR vector enabled.*/ - nvicEnableVector(ETH_IRQn, - CORTEX_PRIORITY_MASK(STM32_MAC_ETH1_IRQ_PRIORITY)); - -#if STM32_MAC_ETH1_CHANGE_PHY_STATE - /* PHY in power up mode.*/ - mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) & ~BMCR_PDOWN); -#endif - - /* MAC configuration.*/ - ETH->MACFFR = 0; - ETH->MACFCR = 0; - ETH->MACVLANTR = 0; - - /* MAC address setup.*/ - if (macp->config->mac_address == NULL) - mac_lld_set_address(default_mac_address); - else - mac_lld_set_address(macp->config->mac_address); - - /* Transmitter and receiver enabled. - Note that the complete setup of the MAC is performed when the link - status is detected.*/ -#if STM32_MAC_IP_CHECKSUM_OFFLOAD - ETH->MACCR = ETH_MACCR_IPCO | ETH_MACCR_RE | ETH_MACCR_TE; -#else - ETH->MACCR = ETH_MACCR_RE | ETH_MACCR_TE; -#endif - - /* DMA configuration: - Descriptor chains pointers.*/ - ETH->DMARDLAR = (uint32_t)rd; - ETH->DMATDLAR = (uint32_t)td; - - /* Enabling required interrupt sources.*/ - ETH->DMASR = ETH->DMASR; - ETH->DMAIER = ETH_DMAIER_NISE | ETH_DMAIER_RIE | ETH_DMAIER_TIE; - - /* DMA general settings.*/ - ETH->DMABMR = ETH_DMABMR_AAB | ETH_DMABMR_RDP_1Beat | ETH_DMABMR_PBL_1Beat; - - /* Transmit FIFO flush.*/ - ETH->DMAOMR = ETH_DMAOMR_FTF; - while (ETH->DMAOMR & ETH_DMAOMR_FTF) - ; - - /* DMA final configuration and start.*/ - ETH->DMAOMR = ETH_DMAOMR_DTCEFD | ETH_DMAOMR_RSF | ETH_DMAOMR_TSF | - ETH_DMAOMR_ST | ETH_DMAOMR_SR; -} - -/** - * @brief Deactivates the MAC peripheral. - * - * @param[in] macp pointer to the @p MACDriver object - * - * @notapi - */ -void mac_lld_stop(MACDriver *macp) { - - if (macp->state != MAC_STOP) { -#if STM32_MAC_ETH1_CHANGE_PHY_STATE - /* PHY in power down mode until the driver will be restarted.*/ - mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) | BMCR_PDOWN); -#endif - - /* MAC and DMA stopped.*/ - ETH->MACCR = 0; - ETH->DMAOMR = 0; - ETH->DMAIER = 0; - ETH->DMASR = ETH->DMASR; - - /* MAC clocks stopped.*/ - rccDisableETH(FALSE); - - /* ISR vector disabled.*/ - nvicDisableVector(ETH_IRQn); - } -} - -/** - * @brief Returns a transmission descriptor. - * @details One of the available transmission descriptors is locked and - * returned. - * - * @param[in] macp pointer to the @p MACDriver object - * @param[out] tdp pointer to a @p MACTransmitDescriptor structure - * @return The operation status. - * @retval RDY_OK the descriptor has been obtained. - * @retval RDY_TIMEOUT descriptor not available. - * - * @notapi - */ -msg_t mac_lld_get_transmit_descriptor(MACDriver *macp, - MACTransmitDescriptor *tdp) { - stm32_eth_tx_descriptor_t *tdes; - - if (!macp->link_up) - return RDY_TIMEOUT; - - chSysLock(); - - /* Get Current TX descriptor.*/ - tdes = macp->txptr; - - /* Ensure that descriptor isn't owned by the Ethernet DMA or locked by - another thread.*/ - if (tdes->tdes0 & (STM32_TDES0_OWN | STM32_TDES0_LOCKED)) { - chSysUnlock(); - return RDY_TIMEOUT; - } - - /* Marks the current descriptor as locked using a reserved bit.*/ - tdes->tdes0 |= STM32_TDES0_LOCKED; - - /* Next TX descriptor to use.*/ - macp->txptr = (stm32_eth_tx_descriptor_t *)tdes->tdes3; - - chSysUnlock(); - - /* Set the buffer size and configuration.*/ - tdp->offset = 0; - tdp->size = STM32_MAC_BUFFERS_SIZE; - tdp->physdesc = tdes; - - return RDY_OK; -} - -/** - * @brief Releases a transmit descriptor and starts the transmission of the - * enqueued data as a single frame. - * - * @param[in] tdp the pointer to the @p MACTransmitDescriptor structure - * - * @notapi - */ -void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) { - - chDbgAssert(!(tdp->physdesc->tdes0 & STM32_TDES0_OWN), - "mac_lld_release_transmit_descriptor(), #1", - "attempt to release descriptor already owned by DMA"); - - chSysLock(); - - /* Unlocks the descriptor and returns it to the DMA engine.*/ - tdp->physdesc->tdes1 = tdp->offset; - tdp->physdesc->tdes0 = STM32_TDES0_CIC(STM32_MAC_IP_CHECKSUM_OFFLOAD) | - STM32_TDES0_IC | STM32_TDES0_LS | STM32_TDES0_FS | - STM32_TDES0_TCH | STM32_TDES0_OWN; - - /* If the DMA engine is stalled then a restart request is issued.*/ - if ((ETH->DMASR & ETH_DMASR_TPS) == ETH_DMASR_TPS_Suspended) { - ETH->DMASR = ETH_DMASR_TBUS; - ETH->DMATPDR = ETH_DMASR_TBUS; /* Any value is OK.*/ - } - - chSysUnlock(); -} - -/** - * @brief Returns a receive descriptor. - * - * @param[in] macp pointer to the @p MACDriver object - * @param[out] rdp pointer to a @p MACReceiveDescriptor structure - * @return The operation status. - * @retval RDY_OK the descriptor has been obtained. - * @retval RDY_TIMEOUT descriptor not available. - * - * @notapi - */ -msg_t mac_lld_get_receive_descriptor(MACDriver *macp, - MACReceiveDescriptor *rdp) { - stm32_eth_rx_descriptor_t *rdes; - - chSysLock(); - - /* Get Current RX descriptor.*/ - rdes = macp->rxptr; - - /* Iterates through received frames until a valid one is found, invalid - frames are discarded.*/ - while (!(rdes->rdes0 & STM32_RDES0_OWN)) { - if (!(rdes->rdes0 & (STM32_RDES0_AFM | STM32_RDES0_ES)) -#if STM32_MAC_IP_CHECKSUM_OFFLOAD - && (rdes->rdes0 & STM32_RDES0_FT) - && !(rdes->rdes0 & (STM32_RDES0_IPHCE | STM32_RDES0_PCE)) -#endif - && (rdes->rdes0 & STM32_RDES0_FS) && (rdes->rdes0 & STM32_RDES0_LS)) { - /* Found a valid one.*/ - rdp->offset = 0; - rdp->size = ((rdes->rdes0 & STM32_RDES0_FL_MASK) >> 16) - 4; - rdp->physdesc = rdes; - macp->rxptr = (stm32_eth_rx_descriptor_t *)rdes->rdes3; - - chSysUnlock(); - return RDY_OK; - } - /* Invalid frame found, purging.*/ - rdes->rdes0 = STM32_RDES0_OWN; - rdes = (stm32_eth_rx_descriptor_t *)rdes->rdes3; - } - - /* Next descriptor to check.*/ - macp->rxptr = rdes; - - chSysUnlock(); - return RDY_TIMEOUT; -} - -/** - * @brief Releases a receive descriptor. - * @details The descriptor and its buffer are made available for more incoming - * frames. - * - * @param[in] rdp the pointer to the @p MACReceiveDescriptor structure - * - * @notapi - */ -void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp) { - - chDbgAssert(!(rdp->physdesc->rdes0 & STM32_RDES0_OWN), - "mac_lld_release_receive_descriptor(), #1", - "attempt to release descriptor already owned by DMA"); - - chSysLock(); - - /* Give buffer back to the Ethernet DMA.*/ - rdp->physdesc->rdes0 = STM32_RDES0_OWN; - - /* If the DMA engine is stalled then a restart request is issued.*/ - if ((ETH->DMASR & ETH_DMASR_RPS) == ETH_DMASR_RPS_Suspended) { - ETH->DMASR = ETH_DMASR_RBUS; - ETH->DMARPDR = ETH_DMASR_RBUS; /* Any value is OK.*/ - } - - chSysUnlock(); -} - -/** - * @brief Updates and returns the link status. - * - * @param[in] macp pointer to the @p MACDriver object - * @return The link status. - * @retval TRUE if the link is active. - * @retval FALSE if the link is down. - * - * @notapi - */ -bool_t mac_lld_poll_link_status(MACDriver *macp) { - uint32_t maccr, bmsr, bmcr; - - maccr = ETH->MACCR; - - /* PHY CR and SR registers read.*/ - (void)mii_read(macp, MII_BMSR); - bmsr = mii_read(macp, MII_BMSR); - bmcr = mii_read(macp, MII_BMCR); - - /* Check on auto-negotiation mode.*/ - if (bmcr & BMCR_ANENABLE) { - uint32_t lpa; - - /* Auto-negotiation must be finished without faults and link established.*/ - if ((bmsr & (BMSR_LSTATUS | BMSR_RFAULT | BMSR_ANEGCOMPLETE)) != - (BMSR_LSTATUS | BMSR_ANEGCOMPLETE)) - return macp->link_up = FALSE; - - /* Auto-negotiation enabled, checks the LPA register.*/ - lpa = mii_read(macp, MII_LPA); - - /* Check on link speed.*/ - if (lpa & (LPA_100HALF | LPA_100FULL | LPA_100BASE4)) - maccr |= ETH_MACCR_FES; - else - maccr &= ~ETH_MACCR_FES; - - /* Check on link mode.*/ - if (lpa & (LPA_10FULL | LPA_100FULL)) - maccr |= ETH_MACCR_DM; - else - maccr &= ~ETH_MACCR_DM; - } - else { - /* Link must be established.*/ - if (!(bmsr & BMSR_LSTATUS)) - return macp->link_up = FALSE; - - /* Check on link speed.*/ - if (bmcr & BMCR_SPEED100) - maccr |= ETH_MACCR_FES; - else - maccr &= ~ETH_MACCR_FES; - - /* Check on link mode.*/ - if (bmcr & BMCR_FULLDPLX) - maccr |= ETH_MACCR_DM; - else - maccr &= ~ETH_MACCR_DM; - } - - /* Changes the mode in the MAC.*/ - ETH->MACCR = maccr; - - /* Returns the link status.*/ - return macp->link_up = TRUE; -} - -/** - * @brief Writes to a transmit descriptor's stream. - * - * @param[in] tdp pointer to a @p MACTransmitDescriptor structure - * @param[in] buf pointer to the buffer containing the data to be - * written - * @param[in] size number of bytes to be written - * @return The number of bytes written into the descriptor's - * stream, this value can be less than the amount - * specified in the parameter @p size if the maximum - * frame size is reached. - * - * @notapi - */ -size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp, - uint8_t *buf, - size_t size) { - - chDbgAssert(!(tdp->physdesc->tdes0 & STM32_TDES0_OWN), - "mac_lld_write_transmit_descriptor(), #1", - "attempt to write descriptor already owned by DMA"); - - if (size > tdp->size - tdp->offset) - size = tdp->size - tdp->offset; - - if (size > 0) { - memcpy((uint8_t *)(tdp->physdesc->tdes2) + tdp->offset, buf, size); - tdp->offset += size; - } - return size; -} - -/** - * @brief Reads from a receive descriptor's stream. - * - * @param[in] rdp pointer to a @p MACReceiveDescriptor structure - * @param[in] buf pointer to the buffer that will receive the read data - * @param[in] size number of bytes to be read - * @return The number of bytes read from the descriptor's - * stream, this value can be less than the amount - * specified in the parameter @p size if there are - * no more bytes to read. - * - * @notapi - */ -size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp, - uint8_t *buf, - size_t size) { - - chDbgAssert(!(rdp->physdesc->rdes0 & STM32_RDES0_OWN), - "mac_lld_read_receive_descriptor(), #1", - "attempt to read descriptor already owned by DMA"); - - if (size > rdp->size - rdp->offset) - size = rdp->size - rdp->offset; - - if (size > 0) { - memcpy(buf, (uint8_t *)(rdp->physdesc->rdes2) + rdp->offset, size); - rdp->offset += size; - } - return size; -} - -#if MAC_USE_ZERO_COPY || defined(__DOXYGEN__) -/** - * @brief Returns a pointer to the next transmit buffer in the descriptor - * chain. - * @note The API guarantees that enough buffers can be requested to fill - * a whole frame. - * - * @param[in] tdp pointer to a @p MACTransmitDescriptor structure - * @param[in] size size of the requested buffer. Specify the frame size - * on the first call then scale the value down subtracting - * the amount of data already copied into the previous - * buffers. - * @param[out] sizep pointer to variable receiving the buffer size, it is - * zero when the last buffer has already been returned. - * Note that a returned size lower than the amount - * requested means that more buffers must be requested - * in order to fill the frame data entirely. - * @return Pointer to the returned buffer. - * @retval NULL if the buffer chain has been entirely scanned. - * - * @notapi - */ -uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp, - size_t size, - size_t *sizep) { - - if (tdp->offset == 0) { - *sizep = tdp->size; - tdp->offset = size; - return (uint8_t *)tdp->physdesc->tdes2; - } - *sizep = 0; - return NULL; -} - -/** - * @brief Returns a pointer to the next receive buffer in the descriptor - * chain. - * @note The API guarantees that the descriptor chain contains a whole - * frame. - * - * @param[in] rdp pointer to a @p MACReceiveDescriptor structure - * @param[out] sizep pointer to variable receiving the buffer size, it is - * zero when the last buffer has already been returned. - * @return Pointer to the returned buffer. - * @retval NULL if the buffer chain has been entirely scanned. - * - * @notapi - */ -const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp, - size_t *sizep) { - - if (rdp->size > 0) { - *sizep = rdp->size; - rdp->offset = rdp->size; - rdp->size = 0; - return (uint8_t *)rdp->physdesc->rdes2; - } - *sizep = 0; - return NULL; -} -#endif /* MAC_USE_ZERO_COPY */ - -#endif /* HAL_USE_MAC */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/mac_lld.h b/firmware/chibios/os/hal/platforms/STM32/mac_lld.h deleted file mode 100644 index 1d2c50b00c..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/mac_lld.h +++ /dev/null @@ -1,364 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/mac_lld.h - * @brief STM32 low level MAC driver header. - * - * @addtogroup MAC - * @{ - */ - -#ifndef _MAC_LLD_H_ -#define _MAC_LLD_H_ - -#if HAL_USE_MAC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief This implementation supports the zero-copy mode API. - */ -#define MAC_SUPPORTS_ZERO_COPY TRUE - -/** - * @name RDES0 constants - * @{ - */ -#define STM32_RDES0_OWN 0x80000000 -#define STM32_RDES0_AFM 0x40000000 -#define STM32_RDES0_FL_MASK 0x3FFF0000 -#define STM32_RDES0_ES 0x00008000 -#define STM32_RDES0_DESERR 0x00004000 -#define STM32_RDES0_SAF 0x00002000 -#define STM32_RDES0_LE 0x00001000 -#define STM32_RDES0_OE 0x00000800 -#define STM32_RDES0_VLAN 0x00000400 -#define STM32_RDES0_FS 0x00000200 -#define STM32_RDES0_LS 0x00000100 -#define STM32_RDES0_IPHCE 0x00000080 -#define STM32_RDES0_LCO 0x00000040 -#define STM32_RDES0_FT 0x00000020 -#define STM32_RDES0_RWT 0x00000010 -#define STM32_RDES0_RE 0x00000008 -#define STM32_RDES0_DE 0x00000004 -#define STM32_RDES0_CE 0x00000002 -#define STM32_RDES0_PCE 0x00000001 -/** @} */ - -/** - * @name RDES1 constants - * @{ - */ -#define STM32_RDES1_DIC 0x80000000 -#define STM32_RDES1_RBS2_MASK 0x1FFF0000 -#define STM32_RDES1_RER 0x00008000 -#define STM32_RDES1_RCH 0x00004000 -#define STM32_RDES1_RBS1_MASK 0x00001FFF -/** @} */ - -/** - * @name TDES0 constants - * @{ - */ -#define STM32_TDES0_OWN 0x80000000 -#define STM32_TDES0_IC 0x40000000 -#define STM32_TDES0_LS 0x20000000 -#define STM32_TDES0_FS 0x10000000 -#define STM32_TDES0_DC 0x08000000 -#define STM32_TDES0_DP 0x04000000 -#define STM32_TDES0_TTSE 0x02000000 -#define STM32_TDES0_LOCKED 0x01000000 /* NOTE: Pseudo flag. */ -#define STM32_TDES0_CIC_MASK 0x00C00000 -#define STM32_TDES0_CIC(n) ((n) << 22) -#define STM32_TDES0_TER 0x00200000 -#define STM32_TDES0_TCH 0x00100000 -#define STM32_TDES0_TTSS 0x00020000 -#define STM32_TDES0_IHE 0x00010000 -#define STM32_TDES0_ES 0x00008000 -#define STM32_TDES0_JT 0x00004000 -#define STM32_TDES0_FF 0x00002000 -#define STM32_TDES0_IPE 0x00001000 -#define STM32_TDES0_LCA 0x00000800 -#define STM32_TDES0_NC 0x00000400 -#define STM32_TDES0_LCO 0x00000200 -#define STM32_TDES0_EC 0x00000100 -#define STM32_TDES0_VF 0x00000080 -#define STM32_TDES0_CC_MASK 0x00000078 -#define STM32_TDES0_ED 0x00000004 -#define STM32_TDES0_UF 0x00000002 -#define STM32_TDES0_DB 0x00000001 -/** @} */ - -/** - * @name TDES1 constants - * @{ - */ -#define STM32_TDES1_TBS2_MASK 0x1FFF0000 -#define STM32_TDES1_TBS1_MASK 0x00001FFF -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief Number of available transmit buffers. - */ -#if !defined(STM32_MAC_TRANSMIT_BUFFERS) || defined(__DOXYGEN__) -#define STM32_MAC_TRANSMIT_BUFFERS 2 -#endif - -/** - * @brief Number of available receive buffers. - */ -#if !defined(STM32_MAC_RECEIVE_BUFFERS) || defined(__DOXYGEN__) -#define STM32_MAC_RECEIVE_BUFFERS 4 -#endif - -/** - * @brief Maximum supported frame size. - */ -#if !defined(STM32_MAC_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define STM32_MAC_BUFFERS_SIZE 1522 -#endif - -/** - * @brief PHY detection timeout. - * @details Timeout, in milliseconds, for PHY address detection, if a PHY - * is not detected within the timeout then the driver halts during - * initialization. This setting applies only if the PHY address is - * not explicitly set in the board header file using - * @p BOARD_PHY_ADDRESS. A zero value disables the timeout and a - * single search path is performed. - */ -#if !defined(STM32_MAC_PHY_TIMEOUT) || defined(__DOXYGEN__) -#define STM32_MAC_PHY_TIMEOUT 100 -#endif - -/** - * @brief Change the PHY power state inside the driver. - */ -#if !defined(STM32_MAC_ETH1_CHANGE_PHY_STATE) || defined(__DOXYGEN__) -#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE -#endif - -/** - * @brief ETHD1 interrupt priority level setting. - */ -#if !defined(STM32_MAC_ETH1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_MAC_ETH1_IRQ_PRIORITY 13 -#endif - -/** - * @brief IP checksum offload. - * @details The following modes are available: - * - 0 Function disabled. - * - 1 Only IP header checksum calculation and insertion are enabled. - * - 2 IP header checksum and payload checksum calculation and - * insertion are enabled, but pseudo-header checksum is not - * calculated in hardware. - * - 3 IP Header checksum and payload checksum calculation and - * insertion are enabled, and pseudo-header checksum is - * calculated in hardware. - * . - */ -#if !defined(STM32_MAC_IP_CHECKSUM_OFFLOAD) || defined(__DOXYGEN__) -#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if (STM32_MAC_PHY_TIMEOUT > 0) && !HAL_IMPLEMENTS_COUNTERS -#error "STM32_MAC_PHY_TIMEOUT requires the realtime counter service" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of an STM32 Ethernet receive descriptor. - */ -typedef struct { - volatile uint32_t rdes0; - volatile uint32_t rdes1; - volatile uint32_t rdes2; - volatile uint32_t rdes3; -} stm32_eth_rx_descriptor_t; - -/** - * @brief Type of an STM32 Ethernet transmit descriptor. - */ -typedef struct { - volatile uint32_t tdes0; - volatile uint32_t tdes1; - volatile uint32_t tdes2; - volatile uint32_t tdes3; -} stm32_eth_tx_descriptor_t; - -/** - * @brief Driver configuration structure. - */ -typedef struct { - /** - * @brief MAC address. - */ - uint8_t *mac_address; - /* End of the mandatory fields.*/ -} MACConfig; - -/** - * @brief Structure representing a MAC driver. - */ -struct MACDriver { - /** - * @brief Driver state. - */ - macstate_t state; - /** - * @brief Current configuration data. - */ - const MACConfig *config; - /** - * @brief Transmit semaphore. - */ - Semaphore tdsem; - /** - * @brief Receive semaphore. - */ - Semaphore rdsem; -#if MAC_USE_EVENTS || defined(__DOXYGEN__) - /** - * @brief Receive event. - */ - EventSource rdevent; -#endif - /* End of the mandatory fields.*/ - /** - * @brief Link status flag. - */ - bool_t link_up; - /** - * @brief PHY address (pre shifted). - */ - uint32_t phyaddr; - /** - * @brief Receive next frame pointer. - */ - stm32_eth_rx_descriptor_t *rxptr; - /** - * @brief Transmit next frame pointer. - */ - stm32_eth_tx_descriptor_t *txptr; -}; - -/** - * @brief Structure representing a transmit descriptor. - */ -typedef struct { - /** - * @brief Current write offset. - */ - size_t offset; - /** - * @brief Available space size. - */ - size_t size; - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the physical descriptor. - */ - stm32_eth_tx_descriptor_t *physdesc; -} MACTransmitDescriptor; - -/** - * @brief Structure representing a receive descriptor. - */ -typedef struct { - /** - * @brief Current read offset. - */ - size_t offset; - /** - * @brief Available data size. - */ - size_t size; - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the physical descriptor. - */ - stm32_eth_rx_descriptor_t *physdesc; -} MACReceiveDescriptor; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -extern MACDriver ETHD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void mii_write(MACDriver *macp, uint32_t reg, uint32_t value); - uint32_t mii_read(MACDriver *macp, uint32_t reg); - void mac_lld_init(void); - void mac_lld_start(MACDriver *macp); - void mac_lld_stop(MACDriver *macp); - msg_t mac_lld_get_transmit_descriptor(MACDriver *macp, - MACTransmitDescriptor *tdp); - void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp); - msg_t mac_lld_get_receive_descriptor(MACDriver *macp, - MACReceiveDescriptor *rdp); - void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp); - bool_t mac_lld_poll_link_status(MACDriver *macp); - size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp, - uint8_t *buf, - size_t size); - size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp, - uint8_t *buf, - size_t size); -#if MAC_USE_ZERO_COPY - uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp, - size_t size, - size_t *sizep); - const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp, - size_t *sizep); -#endif /* MAC_USE_ZERO_COPY */ -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_MAC */ - -#endif /* _MAC_LLD_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/sdc_lld.c b/firmware/chibios/os/hal/platforms/STM32/sdc_lld.c deleted file mode 100644 index 483d277ff6..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/sdc_lld.c +++ /dev/null @@ -1,791 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/sdc_lld.c - * @brief STM32 SDC subsystem low level driver source. - * - * @addtogroup SDC - * @{ - */ - -/* - TODO: Try preerase blocks before writing (ACMD23). - */ - -#include - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_SDC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_SDC_SDIO_DMA_STREAM, \ - STM32_SDC_SDIO_DMA_CHN) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief SDCD1 driver identifier.*/ -SDCDriver SDCD1; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -#if STM32_SDC_SDIO_UNALIGNED_SUPPORT -/** - * @brief Buffer for temporary storage during unaligned transfers. - */ -static union { - uint32_t alignment; - uint8_t buf[MMCSD_BLOCK_SIZE]; -} u; -#endif /* STM32_SDC_SDIO_UNALIGNED_SUPPORT */ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Prepares card to handle read transaction. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] startblk first block to read - * @param[in] n number of blocks to read - * @param[in] resp pointer to the response buffer - * - * @return The operation status. - * @retval CH_SUCCESS operation succeeded. - * @retval CH_FAILED operation failed. - * - * @notapi - */ -static bool_t sdc_lld_prepare_read(SDCDriver *sdcp, uint32_t startblk, - uint32_t n, uint32_t *resp) { - - /* Driver handles data in 512 bytes blocks (just like HC cards). But if we - have not HC card than we must convert address from blocks to bytes.*/ - if (!(sdcp->cardmode & SDC_MODE_HIGH_CAPACITY)) - startblk *= MMCSD_BLOCK_SIZE; - - if (n > 1) { - /* Send read multiple blocks command to card.*/ - if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_READ_MULTIPLE_BLOCK, - startblk, resp) || MMCSD_R1_ERROR(resp[0])) - return CH_FAILED; - } - else{ - /* Send read single block command.*/ - if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_READ_SINGLE_BLOCK, - startblk, resp) || MMCSD_R1_ERROR(resp[0])) - return CH_FAILED; - } - - return CH_SUCCESS; -} - -/** - * @brief Prepares card to handle write transaction. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] startblk first block to read - * @param[in] n number of blocks to write - * @param[in] resp pointer to the response buffer - * - * @return The operation status. - * @retval CH_SUCCESS operation succeeded. - * @retval CH_FAILED operation failed. - * - * @notapi - */ -static bool_t sdc_lld_prepare_write(SDCDriver *sdcp, uint32_t startblk, - uint32_t n, uint32_t *resp) { - - /* Driver handles data in 512 bytes blocks (just like HC cards). But if we - have not HC card than we must convert address from blocks to bytes.*/ - if (!(sdcp->cardmode & SDC_MODE_HIGH_CAPACITY)) - startblk *= MMCSD_BLOCK_SIZE; - - if (n > 1) { - /* Write multiple blocks command.*/ - if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_WRITE_MULTIPLE_BLOCK, - startblk, resp) || MMCSD_R1_ERROR(resp[0])) - return CH_FAILED; - } - else{ - /* Write single block command.*/ - if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_WRITE_BLOCK, - startblk, resp) || MMCSD_R1_ERROR(resp[0])) - return CH_FAILED; - } - - return CH_SUCCESS; -} - -/** - * @brief Wait end of data transaction and performs finalizations. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] n number of blocks in transaction - * @param[in] resp pointer to the response buffer - * - * @return The operation status. - * @retval CH_SUCCESS operation succeeded. - * @retval CH_FAILED operation failed. - */ -static bool_t sdc_lld_wait_transaction_end(SDCDriver *sdcp, uint32_t n, - uint32_t *resp) { - - /* Note the mask is checked before going to sleep because the interrupt - may have occurred before reaching the critical zone.*/ - chSysLock(); - if (SDIO->MASK != 0) { - chDbgAssert(sdcp->thread == NULL, - "sdc_lld_start_data_transaction(), #1", "not NULL"); - sdcp->thread = chThdSelf(); - chSchGoSleepS(THD_STATE_SUSPENDED); - chDbgAssert(sdcp->thread == NULL, - "sdc_lld_start_data_transaction(), #2", "not NULL"); - } - if ((SDIO->STA & SDIO_STA_DATAEND) == 0) { - chSysUnlock(); - return CH_FAILED; - } - -#if (defined(STM32F4XX) || defined(STM32F2XX)) - /* Wait until DMA channel enabled to be sure that all data transferred.*/ - while (sdcp->dma->stream->CR & STM32_DMA_CR_EN) - ; - - /* DMA event flags must be manually cleared.*/ - dmaStreamClearInterrupt(sdcp->dma); - - SDIO->ICR = STM32_SDIO_ICR_ALL_FLAGS; - SDIO->DCTRL = 0; - chSysUnlock(); - - /* Wait until interrupt flags to be cleared.*/ - /*while (((DMA2->LISR) >> (sdcp->dma->ishift)) & STM32_DMA_ISR_TCIF) - dmaStreamClearInterrupt(sdcp->dma);*/ -#else - /* Waits for transfer completion at DMA level, the the stream is - disabled and cleared.*/ - dmaWaitCompletion(sdcp->dma); - - SDIO->ICR = STM32_SDIO_ICR_ALL_FLAGS; - SDIO->DCTRL = 0; - chSysUnlock(); -#endif - - /* Finalize transaction.*/ - if (n > 1) - return sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_STOP_TRANSMISSION, 0, resp); - - return CH_SUCCESS; -} - -/** - * @brief Gets SDC errors. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] sta value of the STA register - * - * @notapi - */ -static void sdc_lld_collect_errors(SDCDriver *sdcp, uint32_t sta) { - uint32_t errors = SDC_NO_ERROR; - - if (sta & SDIO_STA_CCRCFAIL) - errors |= SDC_CMD_CRC_ERROR; - if (sta & SDIO_STA_DCRCFAIL) - errors |= SDC_DATA_CRC_ERROR; - if (sta & SDIO_STA_CTIMEOUT) - errors |= SDC_COMMAND_TIMEOUT; - if (sta & SDIO_STA_DTIMEOUT) - errors |= SDC_DATA_TIMEOUT; - if (sta & SDIO_STA_TXUNDERR) - errors |= SDC_TX_UNDERRUN; - if (sta & SDIO_STA_RXOVERR) - errors |= SDC_RX_OVERRUN; - if (sta & SDIO_STA_STBITERR) - errors |= SDC_STARTBIT_ERROR; - - sdcp->errors |= errors; -} - -/** - * @brief Performs clean transaction stopping in case of errors. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] n number of blocks in transaction - * @param[in] resp pointer to the response buffer - * - * @notapi - */ -static void sdc_lld_error_cleanup(SDCDriver *sdcp, - uint32_t n, - uint32_t *resp) { - uint32_t sta = SDIO->STA; - - dmaStreamClearInterrupt(sdcp->dma); - dmaStreamDisable(sdcp->dma); - SDIO->ICR = STM32_SDIO_ICR_ALL_FLAGS; - SDIO->MASK = 0; - SDIO->DCTRL = 0; - sdc_lld_collect_errors(sdcp, sta); - if (n > 1) - sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_STOP_TRANSMISSION, 0, resp); -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if !defined(STM32_SDIO_HANDLER) -#error "STM32_SDIO_HANDLER not defined" -#endif -/** - * @brief SDIO IRQ handler. - * @details It just wakes transaction thread. All error handling performs in - * that thread. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_SDIO_HANDLER) { - - CH_IRQ_PROLOGUE(); - - chSysLockFromIsr() - - /* Disables the source but the status flags are not reset because the - read/write functions needs to check them.*/ - SDIO->MASK = 0; - - if (SDCD1.thread != NULL) { - chSchReadyI(SDCD1.thread); - SDCD1.thread = NULL; - } - - chSysUnlockFromIsr(); - - CH_IRQ_EPILOGUE(); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level SDC driver initialization. - * - * @notapi - */ -void sdc_lld_init(void) { - - sdcObjectInit(&SDCD1); - SDCD1.thread = NULL; - SDCD1.dma = STM32_DMA_STREAM(STM32_SDC_SDIO_DMA_STREAM); -#if CH_DBG_ENABLE_ASSERTS - SDCD1.sdio = SDIO; -#endif -} - -/** - * @brief Configures and activates the SDC peripheral. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @notapi - */ -void sdc_lld_start(SDCDriver *sdcp) { - - sdcp->dmamode = STM32_DMA_CR_CHSEL(DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_SDC_SDIO_DMA_PRIORITY) | - STM32_DMA_CR_PSIZE_WORD | - STM32_DMA_CR_MSIZE_WORD | - STM32_DMA_CR_MINC; - -#if (defined(STM32F4XX) || defined(STM32F2XX)) - sdcp->dmamode |= STM32_DMA_CR_PFCTRL | - STM32_DMA_CR_PBURST_INCR4 | - STM32_DMA_CR_MBURST_INCR4; -#endif - - if (sdcp->state == BLK_STOP) { - /* Note, the DMA must be enabled before the IRQs.*/ - bool_t b; - b = dmaStreamAllocate(sdcp->dma, STM32_SDC_SDIO_IRQ_PRIORITY, NULL, NULL); - chDbgAssert(!b, "sdc_lld_start(), #1", "stream already allocated"); - dmaStreamSetPeripheral(sdcp->dma, &SDIO->FIFO); -#if (defined(STM32F4XX) || defined(STM32F2XX)) - dmaStreamSetFIFO(sdcp->dma, STM32_DMA_FCR_DMDIS | STM32_DMA_FCR_FTH_FULL); -#endif - nvicEnableVector(STM32_SDIO_NUMBER, - CORTEX_PRIORITY_MASK(STM32_SDC_SDIO_IRQ_PRIORITY)); - rccEnableSDIO(FALSE); - } - - /* Configuration, card clock is initially stopped.*/ - SDIO->POWER = 0; - SDIO->CLKCR = 0; - SDIO->DCTRL = 0; - SDIO->DTIMER = 0; -} - -/** - * @brief Deactivates the SDC peripheral. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @notapi - */ -void sdc_lld_stop(SDCDriver *sdcp) { - - if (sdcp->state != BLK_STOP) { - - /* SDIO deactivation.*/ - SDIO->POWER = 0; - SDIO->CLKCR = 0; - SDIO->DCTRL = 0; - SDIO->DTIMER = 0; - - /* Clock deactivation.*/ - nvicDisableVector(STM32_SDIO_NUMBER); - dmaStreamRelease(sdcp->dma); - rccDisableSDIO(FALSE); - } -} - -/** - * @brief Starts the SDIO clock and sets it to init mode (400kHz or less). - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @notapi - */ -void sdc_lld_start_clk(SDCDriver *sdcp) { - - (void)sdcp; - - /* Initial clock setting: 400kHz, 1bit mode.*/ - SDIO->CLKCR = STM32_SDIO_DIV_LS; - SDIO->POWER |= SDIO_POWER_PWRCTRL_0 | SDIO_POWER_PWRCTRL_1; - SDIO->CLKCR |= SDIO_CLKCR_CLKEN; - - /* Clock activation delay.*/ - chThdSleepMilliseconds(STM32_SDC_CLOCK_ACTIVATION_DELAY); -} - -/** - * @brief Sets the SDIO clock to data mode (25MHz or less). - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @notapi - */ -void sdc_lld_set_data_clk(SDCDriver *sdcp) { - - (void)sdcp; - - SDIO->CLKCR = (SDIO->CLKCR & 0xFFFFFF00) | STM32_SDIO_DIV_HS; -} - -/** - * @brief Stops the SDIO clock. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @notapi - */ -void sdc_lld_stop_clk(SDCDriver *sdcp) { - - (void)sdcp; - - SDIO->CLKCR = 0; - SDIO->POWER = 0; -} - -/** - * @brief Switches the bus to 4 bits mode. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] mode bus mode - * - * @notapi - */ -void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode) { - uint32_t clk = SDIO->CLKCR & ~SDIO_CLKCR_WIDBUS; - - (void)sdcp; - - switch (mode) { - case SDC_MODE_1BIT: - SDIO->CLKCR = clk; - break; - case SDC_MODE_4BIT: - SDIO->CLKCR = clk | SDIO_CLKCR_WIDBUS_0; - break; - case SDC_MODE_8BIT: - SDIO->CLKCR = clk | SDIO_CLKCR_WIDBUS_1; - break; - } -} - -/** - * @brief Sends an SDIO command with no response expected. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] cmd card command - * @param[in] arg command argument - * - * @notapi - */ -void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg) { - - (void)sdcp; - - SDIO->ARG = arg; - SDIO->CMD = (uint32_t)cmd | SDIO_CMD_CPSMEN; - while ((SDIO->STA & SDIO_STA_CMDSENT) == 0) - ; - SDIO->ICR = SDIO_ICR_CMDSENTC; -} - -/** - * @brief Sends an SDIO command with a short response expected. - * @note The CRC is not verified. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] cmd card command - * @param[in] arg command argument - * @param[out] resp pointer to the response buffer (one word) - * - * @return The operation status. - * @retval CH_SUCCESS operation succeeded. - * @retval CH_FAILED operation failed. - * - * @notapi - */ -bool_t sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, - uint32_t *resp) { - uint32_t sta; - - (void)sdcp; - - SDIO->ARG = arg; - SDIO->CMD = (uint32_t)cmd | SDIO_CMD_WAITRESP_0 | SDIO_CMD_CPSMEN; - while (((sta = SDIO->STA) & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT | - SDIO_STA_CCRCFAIL)) == 0) - ; - SDIO->ICR = sta & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT | SDIO_STA_CCRCFAIL); - if ((sta & (SDIO_STA_CTIMEOUT)) != 0) { - sdc_lld_collect_errors(sdcp, sta); - return CH_FAILED; - } - *resp = SDIO->RESP1; - return CH_SUCCESS; -} - -/** - * @brief Sends an SDIO command with a short response expected and CRC. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] cmd card command - * @param[in] arg command argument - * @param[out] resp pointer to the response buffer (one word) - * - * @return The operation status. - * @retval CH_SUCCESS operation succeeded. - * @retval CH_FAILED operation failed. - * - * @notapi - */ -bool_t sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, - uint32_t *resp) { - uint32_t sta; - - (void)sdcp; - - SDIO->ARG = arg; - SDIO->CMD = (uint32_t)cmd | SDIO_CMD_WAITRESP_0 | SDIO_CMD_CPSMEN; - while (((sta = SDIO->STA) & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT | - SDIO_STA_CCRCFAIL)) == 0) - ; - SDIO->ICR = sta & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT | SDIO_STA_CCRCFAIL); - if ((sta & (SDIO_STA_CTIMEOUT | SDIO_STA_CCRCFAIL)) != 0) { - sdc_lld_collect_errors(sdcp, sta); - return CH_FAILED; - } - *resp = SDIO->RESP1; - return CH_SUCCESS; -} - -/** - * @brief Sends an SDIO command with a long response expected and CRC. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] cmd card command - * @param[in] arg command argument - * @param[out] resp pointer to the response buffer (four words) - * - * @return The operation status. - * @retval CH_SUCCESS operation succeeded. - * @retval CH_FAILED operation failed. - * - * @notapi - */ -bool_t sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, - uint32_t *resp) { - uint32_t sta; - - (void)sdcp; - - SDIO->ARG = arg; - SDIO->CMD = (uint32_t)cmd | SDIO_CMD_WAITRESP_0 | SDIO_CMD_WAITRESP_1 | - SDIO_CMD_CPSMEN; - while (((sta = SDIO->STA) & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT | - SDIO_STA_CCRCFAIL)) == 0) - ; - SDIO->ICR = sta & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT | SDIO_STA_CCRCFAIL); - if ((sta & (STM32_SDIO_STA_ERROR_MASK)) != 0) { - sdc_lld_collect_errors(sdcp, sta); - return CH_FAILED; - } - /* Save bytes in reverse order because MSB in response comes first.*/ - *resp++ = SDIO->RESP4; - *resp++ = SDIO->RESP3; - *resp++ = SDIO->RESP2; - *resp = SDIO->RESP1; - return CH_SUCCESS; -} - -/** - * @brief Reads one or more blocks. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] startblk first block to read - * @param[out] buf pointer to the read buffer - * @param[in] n number of blocks to read - * - * @return The operation status. - * @retval CH_SUCCESS operation succeeded. - * @retval CH_FAILED operation failed. - * - * @notapi - */ -bool_t sdc_lld_read_aligned(SDCDriver *sdcp, uint32_t startblk, - uint8_t *buf, uint32_t n) { - uint32_t resp[1]; - - chDbgCheck((n < (0x1000000 / MMCSD_BLOCK_SIZE)), "max transaction size"); - - SDIO->DTIMER = STM32_SDC_READ_TIMEOUT; - - /* Checks for errors and waits for the card to be ready for reading.*/ - if (_sdc_wait_for_transfer_state(sdcp)) - return CH_FAILED; - - /* Prepares the DMA channel for writing.*/ - dmaStreamSetMemory0(sdcp->dma, buf); - dmaStreamSetTransactionSize(sdcp->dma, - (n * MMCSD_BLOCK_SIZE) / sizeof (uint32_t)); - dmaStreamSetMode(sdcp->dma, sdcp->dmamode | STM32_DMA_CR_DIR_P2M); - dmaStreamEnable(sdcp->dma); - - /* Setting up data transfer.*/ - SDIO->ICR = STM32_SDIO_ICR_ALL_FLAGS; - SDIO->MASK = SDIO_MASK_DCRCFAILIE | - SDIO_MASK_DTIMEOUTIE | - SDIO_MASK_STBITERRIE | - SDIO_MASK_RXOVERRIE | - SDIO_MASK_DATAENDIE; - SDIO->DLEN = n * MMCSD_BLOCK_SIZE; - - /* Transaction starts just after DTEN bit setting.*/ - SDIO->DCTRL = SDIO_DCTRL_DTDIR | - SDIO_DCTRL_DBLOCKSIZE_3 | - SDIO_DCTRL_DBLOCKSIZE_0 | - SDIO_DCTRL_DMAEN | - SDIO_DCTRL_DTEN; - - /* Talk to card what we want from it.*/ - if (sdc_lld_prepare_read(sdcp, startblk, n, resp) == TRUE) - goto error; - if (sdc_lld_wait_transaction_end(sdcp, n, resp) == TRUE) - goto error; - - return CH_SUCCESS; - -error: - sdc_lld_error_cleanup(sdcp, n, resp); - return CH_FAILED; -} - -/** - * @brief Writes one or more blocks. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] startblk first block to write - * @param[out] buf pointer to the write buffer - * @param[in] n number of blocks to write - * - * @return The operation status. - * @retval CH_SUCCESS operation succeeded. - * @retval CH_FAILED operation failed. - * - * @notapi - */ -bool_t sdc_lld_write_aligned(SDCDriver *sdcp, uint32_t startblk, - const uint8_t *buf, uint32_t n) { - uint32_t resp[1]; - - chDbgCheck((n < (0x1000000 / MMCSD_BLOCK_SIZE)), "max transaction size"); - - SDIO->DTIMER = STM32_SDC_WRITE_TIMEOUT; - - /* Checks for errors and waits for the card to be ready for writing.*/ - if (_sdc_wait_for_transfer_state(sdcp)) - return CH_FAILED; - - /* Prepares the DMA channel for writing.*/ - dmaStreamSetMemory0(sdcp->dma, buf); - dmaStreamSetTransactionSize(sdcp->dma, - (n * MMCSD_BLOCK_SIZE) / sizeof (uint32_t)); - dmaStreamSetMode(sdcp->dma, sdcp->dmamode | STM32_DMA_CR_DIR_M2P); - dmaStreamEnable(sdcp->dma); - - /* Setting up data transfer.*/ - SDIO->ICR = STM32_SDIO_ICR_ALL_FLAGS; - SDIO->MASK = SDIO_MASK_DCRCFAILIE | - SDIO_MASK_DTIMEOUTIE | - SDIO_MASK_STBITERRIE | - SDIO_MASK_TXUNDERRIE | - SDIO_MASK_DATAENDIE; - SDIO->DLEN = n * MMCSD_BLOCK_SIZE; - - /* Talk to card what we want from it.*/ - if (sdc_lld_prepare_write(sdcp, startblk, n, resp) == TRUE) - goto error; - - /* Transaction starts just after DTEN bit setting.*/ - SDIO->DCTRL = SDIO_DCTRL_DBLOCKSIZE_3 | - SDIO_DCTRL_DBLOCKSIZE_0 | - SDIO_DCTRL_DMAEN | - SDIO_DCTRL_DTEN; - if (sdc_lld_wait_transaction_end(sdcp, n, resp) == TRUE) - goto error; - - return CH_SUCCESS; - -error: - sdc_lld_error_cleanup(sdcp, n, resp); - return CH_FAILED; -} - -/** - * @brief Reads one or more blocks. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] startblk first block to read - * @param[out] buf pointer to the read buffer - * @param[in] n number of blocks to read - * - * @return The operation status. - * @retval CH_SUCCESS operation succeeded. - * @retval CH_FAILED operation failed. - * - * @notapi - */ -bool_t sdc_lld_read(SDCDriver *sdcp, uint32_t startblk, - uint8_t *buf, uint32_t n) { - -#if STM32_SDC_SDIO_UNALIGNED_SUPPORT - if (((unsigned)buf & 3) != 0) { - uint32_t i; - for (i = 0; i < n; i++) { - if (sdc_lld_read_aligned(sdcp, startblk, u.buf, 1)) - return CH_FAILED; - memcpy(buf, u.buf, MMCSD_BLOCK_SIZE); - buf += MMCSD_BLOCK_SIZE; - startblk++; - } - return CH_SUCCESS; - } -#endif /* STM32_SDC_SDIO_UNALIGNED_SUPPORT */ - return sdc_lld_read_aligned(sdcp, startblk, buf, n); -} - -/** - * @brief Writes one or more blocks. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] startblk first block to write - * @param[out] buf pointer to the write buffer - * @param[in] n number of blocks to write - * - * @return The operation status. - * @retval CH_SUCCESS operation succeeded. - * @retval CH_FAILED operation failed. - * - * @notapi - */ -bool_t sdc_lld_write(SDCDriver *sdcp, uint32_t startblk, - const uint8_t *buf, uint32_t n) { - -#if STM32_SDC_SDIO_UNALIGNED_SUPPORT - if (((unsigned)buf & 3) != 0) { - uint32_t i; - for (i = 0; i < n; i++) { - memcpy(u.buf, buf, MMCSD_BLOCK_SIZE); - buf += MMCSD_BLOCK_SIZE; - if (sdc_lld_write_aligned(sdcp, startblk, u.buf, 1)) - return CH_FAILED; - startblk++; - } - return CH_SUCCESS; - } -#endif /* STM32_SDC_SDIO_UNALIGNED_SUPPORT */ - return sdc_lld_write_aligned(sdcp, startblk, buf, n); -} - -/** - * @brief Waits for card idle condition. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @return The operation status. - * @retval CH_SUCCESS the operation succeeded. - * @retval CH_FAILED the operation failed. - * - * @api - */ -bool_t sdc_lld_sync(SDCDriver *sdcp) { - - /* TODO: Implement.*/ - (void)sdcp; - return CH_SUCCESS; -} - -#endif /* HAL_USE_SDC */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/sdc_lld.h b/firmware/chibios/os/hal/platforms/STM32/sdc_lld.h deleted file mode 100644 index 9af4804a33..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/sdc_lld.h +++ /dev/null @@ -1,317 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/sdc_lld.h - * @brief STM32 SDC subsystem low level driver header. - * - * @addtogroup SDC - * @{ - */ - -#ifndef _SDC_LLD_H_ -#define _SDC_LLD_H_ - -#if HAL_USE_SDC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Value to clear all interrupts flag at once. - */ -#define STM32_SDIO_ICR_ALL_FLAGS (SDIO_ICR_CCRCFAILC | SDIO_ICR_DCRCFAILC | \ - SDIO_ICR_CTIMEOUTC | SDIO_ICR_DTIMEOUTC | \ - SDIO_ICR_TXUNDERRC | SDIO_ICR_RXOVERRC | \ - SDIO_ICR_CMDRENDC | SDIO_ICR_CMDSENTC | \ - SDIO_ICR_DATAENDC | SDIO_ICR_STBITERRC | \ - SDIO_ICR_DBCKENDC | SDIO_ICR_SDIOITC | \ - SDIO_ICR_CEATAENDC) - -/** - * @brief Mask of error flags in STA register. - */ -#define STM32_SDIO_STA_ERROR_MASK (SDIO_STA_CCRCFAIL | SDIO_STA_DCRCFAIL | \ - SDIO_STA_CTIMEOUT | SDIO_STA_DTIMEOUT | \ - SDIO_STA_TXUNDERR | SDIO_STA_RXOVERR) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief SDIO DMA priority (0..3|lowest..highest). - */ -#if !defined(STM32_SDC_SDIO_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SDC_SDIO_DMA_PRIORITY 3 -#endif - -/** - * @brief SDIO interrupt priority level setting. - */ -#if !defined(STM32_SDC_SDIO_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SDC_SDIO_IRQ_PRIORITY 9 -#endif - -/** - * @brief Write timeout in milliseconds. - */ -#if !defined(SDC_WRITE_TIMEOUT_MS) || defined(__DOXYGEN__) -#define SDC_WRITE_TIMEOUT_MS 250 -#endif - -/** - * @brief Read timeout in milliseconds. - */ -#if !defined(SDC_READ_TIMEOUT_MS) || defined(__DOXYGEN__) -#define SDC_READ_TIMEOUT_MS 25 -#endif - -/** - * @brief Card clock activation delay in milliseconds. - */ -#if !defined(STM32_SDC_CLOCK_ACTIVATION_DELAY) || defined(__DOXYGEN__) -#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 -#endif - -/** - * @brief Support for unaligned transfers. - * @note Unaligned transfers are much slower. - */ -#if !defined(STM32_SDC_SDIO_UNALIGNED_SUPPORT) || defined(__DOXYGEN__) -#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE -#endif - -#if STM32_ADVANCED_DMA || defined(__DOXYGEN__) - -/** - * @brief DMA stream used for SDC operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_SDC_SDIO_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) -#endif - -#else /* !STM32_ADVANCED_DMA*/ -#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) - -#endif /* !STM32_ADVANCED_DMA*/ -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !STM32_HAS_SDIO -#error "SDIO not present in the selected device" -#endif - -#if !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SDC_SDIO_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SDIO" -#endif - -#if !STM32_DMA_IS_VALID_PRIORITY(STM32_SDC_SDIO_DMA_PRIORITY) -#error "Invalid DMA priority assigned to SDIO" -#endif - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif - -/* - * SDIO clock divider. - */ -#if (defined(STM32F4XX) || defined(STM32F2XX)) -#define STM32_SDIO_DIV_HS 0 -#define STM32_SDIO_DIV_LS 120 - -#elif STM32_HCLK > 48000000 -#define STM32_SDIO_DIV_HS 1 -#define STM32_SDIO_DIV_LS 178 -#else - -#define STM32_SDIO_DIV_HS 0 -#define STM32_SDIO_DIV_LS 118 -#endif - -/** - * @brief SDIO data timeouts in SDIO clock cycles. - */ -#if (defined(STM32F4XX) || defined(STM32F2XX)) -#if !STM32_CLOCK48_REQUIRED -#error "SDIO requires STM32_CLOCK48_REQUIRED to be enabled" -#endif - -#define STM32_SDC_WRITE_TIMEOUT \ - (((STM32_PLL48CLK / (STM32_SDIO_DIV_HS + 2)) / 1000) * SDC_WRITE_TIMEOUT_MS) -#define STM32_SDC_READ_TIMEOUT \ - (((STM32_PLL48CLK / (STM32_SDIO_DIV_HS + 2)) / 1000) * SDC_READ_TIMEOUT_MS) - -#else -#define STM32_SDC_WRITE_TIMEOUT \ - (((STM32_HCLK / (STM32_SDIO_DIV_HS + 2)) / 1000) * SDC_WRITE_TIMEOUT_MS) -#define STM32_SDC_READ_TIMEOUT \ - (((STM32_HCLK / (STM32_SDIO_DIV_HS + 2)) / 1000) * SDC_READ_TIMEOUT_MS) -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of SDIO bus mode. - */ -typedef enum { - SDC_MODE_1BIT = 0, - SDC_MODE_4BIT, - SDC_MODE_8BIT -} sdcbusmode_t; - -/** - * @brief Type of card flags. - */ -typedef uint32_t sdcmode_t; - -/** - * @brief SDC Driver condition flags type. - */ -typedef uint32_t sdcflags_t; - -/** - * @brief Type of a structure representing an SDC driver. - */ -typedef struct SDCDriver SDCDriver; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - uint32_t dummy; -} SDCConfig; - -/** - * @brief @p SDCDriver specific methods. - */ -#define _sdc_driver_methods \ - _mmcsd_block_device_methods - -/** - * @extends MMCSDBlockDeviceVMT - * - * @brief @p SDCDriver virtual methods table. - */ -struct SDCDriverVMT { - _sdc_driver_methods -}; - -/** - * @brief Structure representing an SDC driver. - */ -struct SDCDriver { - /** - * @brief Virtual Methods Table. - */ - const struct SDCDriverVMT *vmt; - _mmcsd_block_device_data - /** - * @brief Current configuration data. - */ - const SDCConfig *config; - /** - * @brief Various flags regarding the mounted card. - */ - sdcmode_t cardmode; - /** - * @brief Errors flags. - */ - sdcflags_t errors; - /** - * @brief Card RCA. - */ - uint32_t rca; - /* End of the mandatory fields.*/ - /** - * @brief Thread waiting for I/O completion IRQ. - */ - Thread *thread; - /** - * @brief DMA mode bit mask. - */ - uint32_t dmamode; - /** - * @brief Transmit DMA channel. - */ - const stm32_dma_stream_t *dma; - /** - * @brief Pointer to the SDIO registers block. - * @note Used only for dubugging purpose. - */ -#if CH_DBG_ENABLE_ASSERTS - SDIO_TypeDef *sdio; -#endif -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -extern SDCDriver SDCD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void sdc_lld_init(void); - void sdc_lld_start(SDCDriver *sdcp); - void sdc_lld_stop(SDCDriver *sdcp); - void sdc_lld_start_clk(SDCDriver *sdcp); - void sdc_lld_set_data_clk(SDCDriver *sdcp); - void sdc_lld_stop_clk(SDCDriver *sdcp); - void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode); - void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg); - bool_t sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, - uint32_t *resp); - bool_t sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, - uint32_t *resp); - bool_t sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, - uint32_t *resp); - bool_t sdc_lld_read(SDCDriver *sdcp, uint32_t startblk, - uint8_t *buf, uint32_t n); - bool_t sdc_lld_write(SDCDriver *sdcp, uint32_t startblk, - const uint8_t *buf, uint32_t n); - bool_t sdc_lld_sync(SDCDriver *sdcp); - bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp); - bool_t sdc_lld_is_write_protected(SDCDriver *sdcp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_SDC */ - -#endif /* _SDC_LLD_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32/stm32.h b/firmware/chibios/os/hal/platforms/STM32/stm32.h deleted file mode 100644 index 16e0a80ea9..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32/stm32.h +++ /dev/null @@ -1,105 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/stm32.h - * @brief STM32 common header. - * @pre One of the following macros must be defined before including - * this header, the macro selects the inclusion of the appropriate - * vendor header: - * - STM32F0XX for Entry Level devices. - * - STM32F10X_LD_VL for Value Line Low Density devices. - * - STM32F10X_MD_VL for Value Line Medium Density devices. - * - STM32F10X_LD for Performance Low Density devices. - * - STM32F10X_MD for Performance Medium Density devices. - * - STM32F10X_HD for Performance High Density devices. - * - STM32F10X_XL for Performance eXtra Density devices. - * - STM32F10X_CL for Connectivity Line devices. - * - STM32F2XX for High-performance STM32 F-2 devices. - * - STM32F30X for Analog & DSP devices. - * - STM32F37X for Analog & DSP devices. - * - STM32F4XX for High-performance STM32 F-4 devices. - * - STM32L1XX_MD for Ultra Low Power Medium-density devices. - * - STM32L1XX_MDP for Ultra Low Power Medium-density Plus devices. - * - STM32L1XX_HD for Ultra Low Power High-density devices. - * . - * - * @addtogroup HAL - * @{ - */ - -#ifndef _STM32_H_ -#define _STM32_H_ - -#if defined(STM32F030) || defined(STM32F0XX_LD) || \ - defined(STM32F0XX_MD) -#include "stm32f0xx.h" - -#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \ - defined(STM32F10X_HD_VL) || defined(STM32F10X_LD) || \ - defined(STM32F10X_MD) || defined(STM32F10X_HD) || \ - defined(STM32F10X_XL) || defined(STM32F10X_CL) || \ - defined(__DOXYGEN__) -#include "stm32f10x.h" - -#elif defined(STM32F2XX) -#include "stm32f2xx.h" - -#elif defined(STM32F30X) -#include "stm32f30x.h" - -#elif defined(STM32F37X) -#include "stm32f37x.h" - -#elif defined(STM32F401xx) || defined(STM32F40_41xxx) || \ - defined(STM32F427_437xx) || defined(STM32F429_439xx) -#include "stm32f4xx.h" - -#elif defined(STM32L1XX_MD) || defined(STM32L1XX_MDP) || \ - defined(STM32L1XX_HD) -#include "stm32l1xx.h" - -#else -#error "STM32 device not specified" -#endif - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#endif /* _STM32_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32F0xx/adc_lld.c b/firmware/chibios/os/hal/platforms/STM32F0xx/adc_lld.c deleted file mode 100644 index 625b26ceb0..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F0xx/adc_lld.c +++ /dev/null @@ -1,298 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F0xx/adc_lld.c - * @brief STM32F0xx ADC subsystem low level driver source. - * - * @addtogroup ADC - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_ADC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief ADC1 driver identifier.*/ -#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__) -ADCDriver ADCD1; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Stops an ongoing conversion, if any. - * - * @param[in] adc pointer to the ADC registers block - */ -static void adc_lld_stop_adc(ADC_TypeDef *adc) { - - if (adc->CR & ADC_CR_ADSTART) { - adc->CR |= ADC_CR_ADSTP; - while (adc->CR & ADC_CR_ADSTP) - ; - } -} - -/** - * @brief ADC DMA ISR service routine. - * - * @param[in] adcp pointer to the @p ADCDriver object - * @param[in] flags pre-shifted content of the ISR register - */ -static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) { - - /* DMA errors handling.*/ - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - /* DMA, this could help only if the DMA tries to access an unmapped - address space or violates alignment rules.*/ - _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE); - } - else { - /* It is possible that the conversion group has already be reset by the - ADC error handler, in this case this interrupt is spurious.*/ - if (adcp->grpp != NULL) { - if ((flags & STM32_DMA_ISR_TCIF) != 0) { - /* Transfer complete processing.*/ - _adc_isr_full_code(adcp); - } - else if ((flags & STM32_DMA_ISR_HTIF) != 0) { - /* Half transfer processing.*/ - _adc_isr_half_code(adcp); - } - } - } -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__) -/** - * @brief ADC interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(Vector70) { - uint32_t isr; - - CH_IRQ_PROLOGUE(); - - isr = ADC1->ISR; - ADC1->ISR = isr; - - /* It could be a spurious interrupt caused by overflows after DMA disabling, - just ignore it in this case.*/ - if (ADCD1.grpp != NULL) { - /* Note, an overflow may occur after the conversion ended before the driver - is able to stop the ADC, this is why the DMA channel is checked too.*/ - if ((isr & ADC_ISR_OVR) && - (dmaStreamGetTransactionSize(ADCD1.dmastp) > 0)) { - /* ADC overflow condition, this could happen only if the DMA is unable - to read data fast enough.*/ - _adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW); - } - if (isr & ADC_ISR_AWD) { - /* Analog watchdog error.*/ - _adc_isr_error_code(&ADCD1, ADC_ERR_AWD); - } - } - - CH_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level ADC driver initialization. - * - * @notapi - */ -void adc_lld_init(void) { - -#if STM32_ADC_USE_ADC1 - /* Driver initialization.*/ - adcObjectInit(&ADCD1); - ADCD1.adc = ADC1; - ADCD1.dmastp = STM32_DMA1_STREAM1; - ADCD1.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | - STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; -#endif - - /* The shared vector is initialized on driver initialization and never - disabled.*/ - nvicEnableVector(12, CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY)); - - /* Calibration procedure.*/ - rccEnableADC1(FALSE); - chDbgAssert(ADC1->CR == 0, "adc_lld_init(), #1", "invalid register state"); - ADC1->CR |= ADC_CR_ADCAL; - while (ADC1->CR & ADC_CR_ADCAL) - ; - rccDisableADC1(FALSE); -} - -/** - * @brief Configures and activates the ADC peripheral. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_start(ADCDriver *adcp) { - - /* If in stopped state then enables the ADC and DMA clocks.*/ - if (adcp->state == ADC_STOP) { -#if STM32_ADC_USE_ADC1 - if (&ADCD1 == adcp) { - bool_t b; - b = dmaStreamAllocate(adcp->dmastp, - STM32_ADC_ADC1_DMA_IRQ_PRIORITY, - (stm32_dmaisr_t)adc_lld_serve_rx_interrupt, - (void *)adcp); - chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated"); - dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR); - rccEnableADC1(FALSE); -#if STM32_ADCSW == STM32_ADCSW_HSI14 - /* Clock from HSI14, no need for jitter removal.*/ - ADC1->CFGR2 = 0; -#else -#if STM32_ADCPRE == STM32_ADCPRE_DIV2 - ADC1->CFGR2 = ADC_CFGR2_JITOFFDIV2; -#else - ADC1->CFGR2 = ADC_CFGR2_JITOFFDIV4; -#endif -#endif - } -#endif /* STM32_ADC_USE_ADC1 */ - - /* ADC initial setup, starting the analog part here in order to reduce - the latency when starting a conversion.*/ - adcp->adc->CR = ADC_CR_ADEN; - while (!(adcp->adc->ISR & ADC_ISR_ADRDY)) - ; - } -} - -/** - * @brief Deactivates the ADC peripheral. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_stop(ADCDriver *adcp) { - - /* If in ready state then disables the ADC clock and analog part.*/ - if (adcp->state == ADC_READY) { - - dmaStreamRelease(adcp->dmastp); - - /* Disabling ADC.*/ - if (adcp->adc->CR & ADC_CR_ADEN) { - adc_lld_stop_adc(adcp->adc); - adcp->adc->CR |= ADC_CR_ADDIS; - while (adcp->adc->CR & ADC_CR_ADDIS) - ; - } - -#if STM32_ADC_USE_ADC1 - if (&ADCD1 == adcp) - rccDisableADC1(FALSE); -#endif - } -} - -/** - * @brief Starts an ADC conversion. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_start_conversion(ADCDriver *adcp) { - uint32_t mode, cfgr1; - const ADCConversionGroup *grpp = adcp->grpp; - - /* DMA setup.*/ - mode = adcp->dmamode; - cfgr1 = grpp->cfgr1 | ADC_CFGR1_DMAEN; - if (grpp->circular) { - mode |= STM32_DMA_CR_CIRC; - cfgr1 |= ADC_CFGR1_DMACFG; - if (adcp->depth > 1) { - /* If circular buffer depth > 1, then the half transfer interrupt - is enabled in order to allow streaming processing.*/ - mode |= STM32_DMA_CR_HTIE; - } - } - dmaStreamSetMemory0(adcp->dmastp, adcp->samples); - dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels * - (uint32_t)adcp->depth); - dmaStreamSetMode(adcp->dmastp, mode); - dmaStreamEnable(adcp->dmastp); - - /* ADC setup, if it is defined a callback for the analog watch dog then it - is enabled.*/ - adcp->adc->ISR = adcp->adc->ISR; - adcp->adc->IER = ADC_IER_OVRIE | ADC_IER_AWDIE; - adcp->adc->TR = grpp->tr; - adcp->adc->SMPR = grpp->smpr; - adcp->adc->CHSELR = grpp->chselr; - - /* ADC configuration and start.*/ - adcp->adc->CFGR1 = cfgr1; - adcp->adc->CR |= ADC_CR_ADSTART; -} - -/** - * @brief Stops an ongoing conversion. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_stop_conversion(ADCDriver *adcp) { - - dmaStreamDisable(adcp->dmastp); - adc_lld_stop_adc(adcp->adc); -} - -#endif /* HAL_USE_ADC */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32F0xx/adc_lld.h b/firmware/chibios/os/hal/platforms/STM32F0xx/adc_lld.h deleted file mode 100644 index df9f06aad2..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F0xx/adc_lld.h +++ /dev/null @@ -1,348 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F0xx/adc_lld.h - * @brief STM32F0xx ADC subsystem low level driver header. - * - * @addtogroup ADC - * @{ - */ - -#ifndef _ADC_LLD_H_ -#define _ADC_LLD_H_ - -#if HAL_USE_ADC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name Sampling rates - * @{ - */ -#define ADC_SMPR_SMP_1P5 0 /**< @brief 14 cycles conversion time */ -#define ADC_SMPR_SMP_7P5 1 /**< @brief 21 cycles conversion time. */ -#define ADC_SMPR_SMP_13P5 2 /**< @brief 28 cycles conversion time. */ -#define ADC_SMPR_SMP_28P5 3 /**< @brief 41 cycles conversion time. */ -#define ADC_SMPR_SMP_41P5 4 /**< @brief 54 cycles conversion time. */ -#define ADC_SMPR_SMP_55P5 5 /**< @brief 68 cycles conversion time. */ -#define ADC_SMPR_SMP_71P5 6 /**< @brief 84 cycles conversion time. */ -#define ADC_SMPR_SMP_239P5 7 /**< @brief 252 cycles conversion time. */ -/** @} */ - -/** - * @name CFGR1 register configuration helpers - * @{ - */ -#define ADC_CFGR1_RES_12BIT (0 << 3) -#define ADC_CFGR1_RES_10BIT (1 << 3) -#define ADC_CFGR1_RES_8BIT (2 << 3) -#define ADC_CFGR1_RES_6BIT (3 << 3) - -#define ADC_CFGR1_EXTSEL_MASK (15 << 6) -#define ADC_CFGR1_EXTSEL_SRC(n) ((n) << 6) - -#define ADC_CFGR1_EXTEN_MASK (3 << 10) -#define ADC_CFGR1_EXTEN_DISABLED (0 << 10) -#define ADC_CFGR1_EXTEN_RISING (1 << 10) -#define ADC_CFGR1_EXTEN_FALLING (2 << 10) -#define ADC_CFGR1_EXTEN_BOTH (3 << 10) -/** @} */ - -/** - * @name Threashold register initializer - * @{ - */ -#define ADC_TR(low, high) (((uint32_t)(high) << 16) | \ - (uint32_t)(low)) -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief ADC1 driver enable switch. - * @details If set to @p TRUE the support for ADC1 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__) -#define STM32_ADC_USE_ADC1 FALSE -#endif - -/** - * @brief ADC1 DMA priority (0..3|lowest..highest). - */ -#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#endif - -/** - * @brief ADC interrupt priority level setting. - */ -#if !defined(STM32_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_IRQ_PRIORITY 2 -#endif - -/** - * @brief ADC1 DMA interrupt priority level setting. - */ -#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2 -#endif - -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1 -#error "ADC1 not present in the selected device" -#endif - -#if !STM32_ADC_USE_ADC1 -#error "ADC driver activated but no ADC peripheral assigned" -#endif - -#if STM32_ADC_USE_ADC1 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to ADC1" -#endif - -#if STM32_ADC_USE_ADC1 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to ADC1 DMA" -#endif - -#if STM32_ADC_USE_ADC1 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_PRIORITY) -#error "Invalid DMA priority assigned to ADC1" -#endif - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief ADC sample data type. - */ -typedef uint16_t adcsample_t; - -/** - * @brief Channels number in a conversion group. - */ -typedef uint16_t adc_channels_num_t; - -/** - * @brief Possible ADC failure causes. - * @note Error codes are architecture dependent and should not relied - * upon. - */ -typedef enum { - ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */ - ADC_ERR_OVERFLOW = 1, /**< ADC overflow condition. */ - ADC_ERR_AWD = 2 /**< Analog watchdog triggered. */ -} adcerror_t; - -/** - * @brief Type of a structure representing an ADC driver. - */ -typedef struct ADCDriver ADCDriver; - -/** - * @brief ADC notification callback type. - * - * @param[in] adcp pointer to the @p ADCDriver object triggering the - * callback - * @param[in] buffer pointer to the most recent samples data - * @param[in] n number of buffer rows available starting from @p buffer - */ -typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n); - -/** - * @brief ADC error callback type. - * - * @param[in] adcp pointer to the @p ADCDriver object triggering the - * callback - * @param[in] err ADC error code - */ -typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err); - -/** - * @brief Conversion group configuration structure. - * @details This implementation-dependent structure describes a conversion - * operation. - * @note The use of this configuration structure requires knowledge of - * STM32 ADC cell registers interface, please refer to the STM32 - * reference manual for details. - */ -typedef struct { - /** - * @brief Enables the circular buffer mode for the group. - */ - bool_t circular; - /** - * @brief Number of the analog channels belonging to the conversion group. - */ - adc_channels_num_t num_channels; - /** - * @brief Callback function associated to the group or @p NULL. - */ - adccallback_t end_cb; - /** - * @brief Error callback or @p NULL. - */ - adcerrorcallback_t error_cb; - /* End of the mandatory fields.*/ - /** - * @brief ADC CFGR1 register initialization data. - * @note The bits DMAEN and DMACFG are enforced internally - * to the driver, keep them to zero. - * @note The bits @p ADC_CFGR1_CONT or @p ADC_CFGR1_DISCEN must be - * specified in continuous more or if the buffer depth is - * greater than one. - */ - uint32_t cfgr1; - /** - * @brief ADC TR register initialization data. - */ - uint32_t tr; - /** - * @brief ADC SMPR register initialization data. - */ - uint32_t smpr; - /** - * @brief ADC CHSELR register initialization data. - * @details The number of bits at logic level one in this register must - * be equal to the number in the @p num_channels field. - */ - uint32_t chselr; -} ADCConversionGroup; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - uint32_t dummy; -} ADCConfig; - -/** - * @brief Structure representing an ADC driver. - */ -struct ADCDriver { - /** - * @brief Driver state. - */ - adcstate_t state; - /** - * @brief Current configuration data. - */ - const ADCConfig *config; - /** - * @brief Current samples buffer pointer or @p NULL. - */ - adcsample_t *samples; - /** - * @brief Current samples buffer depth or @p 0. - */ - size_t depth; - /** - * @brief Current conversion group pointer or @p NULL. - */ - const ADCConversionGroup *grpp; -#if ADC_USE_WAIT || defined(__DOXYGEN__) - /** - * @brief Waiting thread. - */ - Thread *thread; -#endif -#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) -#if CH_USE_MUTEXES || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the peripheral. - */ - Mutex mutex; -#elif CH_USE_SEMAPHORES - Semaphore semaphore; -#endif -#endif /* ADC_USE_MUTUAL_EXCLUSION */ -#if defined(ADC_DRIVER_EXT_FIELDS) - ADC_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the ADCx registers block. - */ - ADC_TypeDef *adc; - /** - * @brief Pointer to associated DMA channel. - */ - const stm32_dma_stream_t *dmastp; - /** - * @brief DMA mode bit mask. - */ - uint32_t dmamode; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Changes the value of the ADC CCR register. - * @details Use this function in order to enable or disable the internal - * analog sources. See the documentation in the STM32F0xx Reference - * Manual. - */ -#define adcSTM32SetCCR(ccr) (ADC->CCR = (ccr)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__) -extern ADCDriver ADCD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void adc_lld_init(void); - void adc_lld_start(ADCDriver *adcp); - void adc_lld_stop(ADCDriver *adcp); - void adc_lld_start_conversion(ADCDriver *adcp); - void adc_lld_stop_conversion(ADCDriver *adcp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_ADC */ - -#endif /* _ADC_LLD_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32F0xx/ext_lld_isr.c b/firmware/chibios/os/hal/platforms/STM32F0xx/ext_lld_isr.c deleted file mode 100644 index ab20534c0c..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F0xx/ext_lld_isr.c +++ /dev/null @@ -1,207 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F0xx/ext_lld_isr.c - * @brief STM32F0xx EXT subsystem low level driver ISR code. - * - * @addtogroup EXT - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -#include "ext_lld_isr.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief EXTI[0]...EXTI[1] interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(Vector54) { - uint32_t pr; - - CH_IRQ_PROLOGUE(); - - pr = EXTI->PR & ((1 << 0) | (1 << 1)); - EXTI->PR = pr; - if (pr & (1 << 0)) - EXTD1.config->channels[0].cb(&EXTD1, 0); - if (pr & (1 << 1)) - EXTD1.config->channels[1].cb(&EXTD1, 1); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[2]...EXTI[3] interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(Vector58) { - uint32_t pr; - - CH_IRQ_PROLOGUE(); - - pr = EXTI->PR & ((1 << 2) | (1 << 3)); - EXTI->PR = pr; - if (pr & (1 << 2)) - EXTD1.config->channels[2].cb(&EXTD1, 2); - if (pr & (1 << 3)) - EXTD1.config->channels[3].cb(&EXTD1, 3); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[4]...EXTI[15] interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(Vector5C) { - uint32_t pr; - - CH_IRQ_PROLOGUE(); - - pr = EXTI->PR & ((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | - (1 << 9) | (1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | - (1 << 14) | (1 << 15)); - EXTI->PR = pr; - if (pr & (1 << 4)) - EXTD1.config->channels[4].cb(&EXTD1, 4); - if (pr & (1 << 5)) - EXTD1.config->channels[5].cb(&EXTD1, 5); - if (pr & (1 << 6)) - EXTD1.config->channels[6].cb(&EXTD1, 6); - if (pr & (1 << 7)) - EXTD1.config->channels[7].cb(&EXTD1, 7); - if (pr & (1 << 8)) - EXTD1.config->channels[8].cb(&EXTD1, 8); - if (pr & (1 << 9)) - EXTD1.config->channels[9].cb(&EXTD1, 9); - if (pr & (1 << 10)) - EXTD1.config->channels[10].cb(&EXTD1, 10); - if (pr & (1 << 11)) - EXTD1.config->channels[11].cb(&EXTD1, 11); - if (pr & (1 << 12)) - EXTD1.config->channels[12].cb(&EXTD1, 12); - if (pr & (1 << 13)) - EXTD1.config->channels[13].cb(&EXTD1, 13); - if (pr & (1 << 14)) - EXTD1.config->channels[14].cb(&EXTD1, 14); - if (pr & (1 << 15)) - EXTD1.config->channels[15].cb(&EXTD1, 15); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[16] interrupt handler (PVD). - * - * @isr - */ -CH_IRQ_HANDLER(Vector44) { - - CH_IRQ_PROLOGUE(); - - EXTI->PR = (1 << 16); - EXTD1.config->channels[16].cb(&EXTD1, 16); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[17] interrupt handler (RTC). - * - * @isr - */ -CH_IRQ_HANDLER(Vector48) { - - CH_IRQ_PROLOGUE(); - - EXTI->PR = (1 << 17); - EXTD1.config->channels[17].cb(&EXTD1, 17); - - CH_IRQ_EPILOGUE(); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Enables EXTI IRQ sources. - * - * @notapi - */ -void ext_lld_exti_irq_enable(void) { - - nvicEnableVector(EXTI0_1_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI0_1_IRQ_PRIORITY)); - nvicEnableVector(EXTI2_3_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI2_3_IRQ_PRIORITY)); - nvicEnableVector(EXTI4_15_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_15_IRQ_PRIORITY)); -#if !defined(STM32F030) - nvicEnableVector(PVD_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY)); -#endif - nvicEnableVector(RTC_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY)); -} - -/** - * @brief Disables EXTI IRQ sources. - * - * @notapi - */ -void ext_lld_exti_irq_disable(void) { - - nvicDisableVector(EXTI0_1_IRQn); - nvicDisableVector(EXTI2_3_IRQn); - nvicDisableVector(EXTI4_15_IRQn); -#if !defined(STM32F030) - nvicDisableVector(PVD_IRQn); -#endif - nvicDisableVector(RTC_IRQn); -} - -#endif /* HAL_USE_EXT */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32F0xx/ext_lld_isr.h b/firmware/chibios/os/hal/platforms/STM32F0xx/ext_lld_isr.h deleted file mode 100644 index b37fd2fd11..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F0xx/ext_lld_isr.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F0xx/ext_lld_isr.h - * @brief STM32F0xx EXT subsystem low level driver ISR header. - * - * @addtogroup EXT - * @{ - */ - -#ifndef _EXT_LLD_ISR_H_ -#define _EXT_LLD_ISR_H_ - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief EXTI0..1 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI0_1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI0_1_IRQ_PRIORITY 3 -#endif - -/** - * @brief EXTI2..3 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI2_3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI2_3_IRQ_PRIORITY 3 -#endif - -/** - * @brief EXTI4..15 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI4_15_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI4_15_IRQ_PRIORITY 3 -#endif - -/** - * @brief EXTI16 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI16_IRQ_PRIORITY 3 -#endif - -/** - * @brief EXTI17 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI17_IRQ_PRIORITY 3 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void ext_lld_exti_irq_enable(void); - void ext_lld_exti_irq_disable(void); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_EXT */ - -#endif /* _EXT_LLD_ISR_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32F0xx/hal_lld.c b/firmware/chibios/os/hal/platforms/STM32F0xx/hal_lld.c deleted file mode 100644 index 46f02fca98..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F0xx/hal_lld.c +++ /dev/null @@ -1,216 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F0xx/hal_lld.c - * @brief STM32F0xx HAL subsystem low level driver source. - * - * @addtogroup HAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Initializes the backup domain. - * @note WARNING! Changing clock source impossible without resetting - * of the whole BKP domain. - */ -static void hal_lld_backup_domain_init(void) { - - /* Backup domain access enabled and left open.*/ - PWR->CR |= PWR_CR_DBP; - - /* Reset BKP domain if different clock source selected.*/ - if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL){ - /* Backup domain reset.*/ - RCC->BDCR = RCC_BDCR_BDRST; - RCC->BDCR = 0; - } - - /* If enabled then the LSE is started.*/ -#if STM32_LSE_ENABLED -#if defined(STM32_LSE_BYPASS) - /* LSE Bypass.*/ - RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP; -#else - /* No LSE Bypass.*/ - RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON; -#endif - while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) - ; /* Waits until LSE is stable. */ -#endif - -#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK - /* If the backup domain hasn't been initialized yet then proceed with - initialization.*/ - if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) { - /* Selects clock source.*/ - RCC->BDCR |= STM32_RTCSEL; - - /* RTC clock enabled.*/ - RCC->BDCR |= RCC_BDCR_RTCEN; - } -#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */ -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level HAL driver initialization. - * - * @notapi - */ -void hal_lld_init(void) { - - /* Reset of all peripherals.*/ - rccResetAHB(0xFFFFFFFF); - rccResetAPB1(0xFFFFFFFF); - rccResetAPB2(~RCC_APB2RSTR_DBGMCURST); - - /* SysTick initialization using the system clock.*/ - SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1; - SysTick->VAL = 0; - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk | - SysTick_CTRL_TICKINT_Msk; - - /* PWR clock enabled.*/ - rccEnablePWRInterface(FALSE); - - /* Initializes the backup domain.*/ - hal_lld_backup_domain_init(); - -#if defined(STM32_DMA_REQUIRED) - dmaInit(); -#endif - - /* Programmable voltage detector enable.*/ -#if STM32_PVD_ENABLE - PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK); -#endif /* STM32_PVD_ENABLE */ -} - -/** - * @brief STM32 clocks and PLL initialization. - * @note All the involved constants come from the file @p board.h. - * @note This function should be invoked just after the system reset. - * - * @special - */ -void stm32_clock_init(void) { - -#if !STM32_NO_INIT - /* HSI setup, it enforces the reset situation in order to handle possible - problems with JTAG probes and re-initializations.*/ - RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */ - while (!(RCC->CR & RCC_CR_HSIRDY)) - ; /* Wait until HSI is stable. */ - - /* HSI is selected as new source without touching the other fields in - CFGR. Clearing the register has to be postponed after HSI is the - new source.*/ - RCC->CFGR &= ~RCC_CFGR_SW; /* Reset SW */ - RCC->CFGR |= RCC_CFGR_SWS_HSI; /* Select HSI as internal*/ - while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) - ; /* Wait until HSI is selected. */ - - /* Registers finally cleared to reset values.*/ - RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */ - RCC->CFGR = 0; /* CFGR reset value. */ - -#if STM32_HSE_ENABLED - /* HSE activation.*/ -#if defined(STM32_HSE_BYPASS) - /* HSE Bypass.*/ - RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP; -#else - /* No HSE Bypass.*/ - RCC->CR |= RCC_CR_HSEON; -#endif - while (!(RCC->CR & RCC_CR_HSERDY)) - ; /* Waits until HSE is stable. */ -#endif - -#if STM32_HSE14_ENABLED - /* HSI14 activation.*/ - RCC->CR2 |= RCC_CR2_HSI14ON; - while (!(RCC->CR2 & RCC_CR2_HSI14RDY)) - ; /* Waits until HSI14 is stable. */ -#endif - -#if STM32_LSI_ENABLED - /* LSI activation.*/ - RCC->CSR |= RCC_CSR_LSION; - while ((RCC->CSR & RCC_CSR_LSIRDY) == 0) - ; /* Waits until LSI is stable. */ -#endif - - /* Clock settings.*/ - RCC->CFGR = STM32_MCOSEL | STM32_PLLMUL | STM32_PLLSRC | - STM32_ADCPRE | STM32_PPRE | STM32_HPRE; - RCC->CFGR2 = STM32_PREDIV; - RCC->CFGR3 = STM32_ADCSW | STM32_CECSW | STM32_I2C1SW | - STM32_USART1SW; - -#if STM32_ACTIVATE_PLL - /* PLL activation.*/ - RCC->CR |= RCC_CR_PLLON; - while (!(RCC->CR & RCC_CR_PLLRDY)) - ; /* Waits until PLL is stable. */ -#endif - - /* Flash setup and final clock selection. */ - FLASH->ACR = STM32_FLASHBITS; - - /* Switching to the configured clock source if it is different from HSI.*/ -#if (STM32_SW != STM32_SW_HSI) - /* Switches clock source.*/ - RCC->CFGR |= STM32_SW; - while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2)) - ; /* Waits selection complete. */ -#endif - - /* SYSCFG clock enabled here because it is a multi-functional unit shared - among multiple drivers.*/ - rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE); -#endif /* !STM32_NO_INIT */ -} - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32F0xx/hal_lld.h b/firmware/chibios/os/hal/platforms/STM32F0xx/hal_lld.h deleted file mode 100644 index 404e98a9c4..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F0xx/hal_lld.h +++ /dev/null @@ -1,796 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F0xx/hal_lld.h - * @brief STM32F0xx HAL subsystem low level driver header. - * @pre This module requires the following macros to be defined in the - * @p board.h file: - * - STM32_LSECLK. - * - STM32_LSEDRV. - * - STM32_LSE_BYPASS (optionally). - * - STM32_HSECLK. - * - STM32_HSE_BYPASS (optionally). - * . - * One of the following macros must also be defined: - * - STM32F030 for Value Line devices. - * - STM32F0XX_LD for Low Density devices. - * - STM32F0XX_MD for Medium Density devices. - * . - * - * @addtogroup HAL - * @{ - */ - -#ifndef _HAL_LLD_H_ -#define _HAL_LLD_H_ - -#include "stm32.h" -#include "stm32_registry.h" - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Defines the support for realtime counters in the HAL. - */ -#define HAL_IMPLEMENTS_COUNTERS FALSE - -/** - * @name Platform identification macros - * @{ - */ -#if defined(STM32F0XX_MD) || defined(__DOXYGEN__) -#define PLATFORM_NAME "STM32F051xx/F061xx Entry Level Medium Density devices" -#define STM32F0XX - -#elif defined(STM32F0XX_LD) -#define PLATFORM_NAME "STM32F050xx/F060xx Entry Level Low Density devices" -#define STM32F0XX - -#elif defined(STM32F030) -#define PLATFORM_NAME "STM32F030xx Entry Level Value Line devices" -#define STM32F0XX - -#else -#error "STM32F0xx device not specified" -#endif -/** @} */ - -/** - * @name Absolute Maximum Ratings - * @{ - */ -/** - * @brief Maximum system clock frequency. - */ -#define STM32_SYSCLK_MAX 48000000 - -/** - * @brief Maximum HSE clock frequency. - */ -#define STM32_HSECLK_MAX 32000000 - -/** - * @brief Minimum HSE clock frequency. - */ -#define STM32_HSECLK_MIN 1000000 - -/** - * @brief Maximum LSE clock frequency. - */ -#define STM32_LSECLK_MAX 1000000 - -/** - * @brief Minimum LSE clock frequency. - */ -#define STM32_LSECLK_MIN 32768 - -/** - * @brief Maximum PLLs input clock frequency. - */ -#define STM32_PLLIN_MAX 25000000 - -/** - * @brief Minimum PLLs input clock frequency. - */ -#define STM32_PLLIN_MIN 1000000 - -/** - * @brief Maximum PLL output clock frequency. - */ -#define STM32_PLLOUT_MAX 48000000 - -/** - * @brief Minimum PLL output clock frequency. - */ -#define STM32_PLLOUT_MIN 16000000 - -/** - * @brief Maximum APB clock frequency. - */ -#define STM32_PCLK_MAX 48000000 - -/** - * @brief Maximum ADC clock frequency. - */ -#define STM32_ADCCLK_MAX 14000000 -/** @} */ - -/** - * @name Internal clock sources - * @{ - */ -#define STM32_HSICLK 8000000 /**< High speed internal clock. */ -#define STM32_HSI14CLK 14000000 /**< 14MHz speed internal clock.*/ -#define STM32_LSICLK 40000 /**< Low speed internal clock. */ -/** @} */ - -/** - * @name PWR_CR register bits definitions - * @{ - */ -#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */ -#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */ -#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */ -#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 2. */ -#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 3. */ -#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 4. */ -#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 5. */ -#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 6. */ -#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 7. */ -/** @} */ - -/** - * @name RCC_CFGR register bits definitions - * @{ - */ -#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */ -#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */ -#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */ - -#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */ -#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */ -#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */ -#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */ -#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */ -#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */ -#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */ -#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */ -#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */ - -#define STM32_PPRE_DIV1 (0 << 8) /**< HCLK divided by 1. */ -#define STM32_PPRE_DIV2 (4 << 8) /**< HCLK divided by 2. */ -#define STM32_PPRE_DIV4 (5 << 8) /**< HCLK divided by 4. */ -#define STM32_PPRE_DIV8 (6 << 8) /**< HCLK divided by 8. */ -#define STM32_PPRE_DIV16 (7 << 8) /**< HCLK divided by 16. */ - -#define STM32_ADCPRE_DIV2 (0 << 14) /**< PCLK divided by 2. */ -#define STM32_ADCPRE_DIV4 (1 << 14) /**< PCLK divided by 4. */ - -#define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */ -#define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */ - -#define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */ -#define STM32_MCOSEL_HSI14 (3 << 24) /**< HSI14 clock on MCO pin. */ -#define STM32_MCOSEL_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */ -#define STM32_MCOSEL_HSI (5 << 24) /**< HSI clock on MCO pin. */ -#define STM32_MCOSEL_HSE (6 << 24) /**< HSE clock on MCO pin. */ -#define STM32_MCOSEL_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */ -/** @} */ - -/** - * @name RCC_BDCR register bits definitions - * @{ - */ -#define STM32_RTCSEL_MASK (3 << 8) /**< RTC clock source mask. */ -#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No clock. */ -#define STM32_RTCSEL_LSE (1 << 8) /**< LSE used as RTC clock. */ -#define STM32_RTCSEL_LSI (2 << 8) /**< LSI used as RTC clock. */ -#define STM32_RTCSEL_HSEDIV (3 << 8) /**< HSE divided by 32 used as - RTC clock. */ -/** @} */ - -/** - * @name RCC_CFGR3 register bits definitions - * @{ - */ -#define STM32_USART1SW_MASK (3 << 0) /**< USART1 clock source mask. */ -#define STM32_USART1SW_PCLK (0 << 0) /**< USART1 clock is PCLK. */ -#define STM32_USART1SW_SYSCLK (1 << 0) /**< USART1 clock is SYSCLK. */ -#define STM32_USART1SW_LSE (2 << 0) /**< USART1 clock is LSE. */ -#define STM32_USART1SW_HSI (3 << 0) /**< USART1 clock is HSI. */ -#define STM32_I2C1SW_MASK (1 << 4) /**< I2C clock source mask. */ -#define STM32_I2C1SW_HSI (0 << 4) /**< I2C clock is HSI. */ -#define STM32_I2C1SW_SYSCLK (1 << 4) /**< I2C clock is SYSCLK. */ -#define STM32_CECSW_MASK (1 << 6) /**< CEC clock source mask. */ -#define STM32_CECSW_HSI (0 << 6) /**< CEC clock is HSI/244. */ -#define STM32_CECSW_LSE (1 << 6) /**< CEC clock is LSE. */ -#define STM32_ADCSW_MASK (1 << 8) /**< ADC clock source mask. */ -#define STM32_ADCSW_HSI14 (0 << 8) /**< ADC clock is HSI14. */ -#define STM32_ADCSW_PCLK (1 << 8) /**< ADC clock is PCLK/2|4. */ -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief Disables the PWR/RCC initialization in the HAL. - */ -#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__) -#define STM32_NO_INIT FALSE -#endif - -/** - * @brief Enables or disables the programmable voltage detector. - */ -#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__) -#define STM32_PVD_ENABLE FALSE -#endif - -/** - * @brief Sets voltage level for programmable voltage detector. - */ -#if !defined(STM32_PLS) || defined(__DOXYGEN__) -#define STM32_PLS STM32_PLS_LEV0 -#endif - -/** - * @brief Enables or disables the HSI clock source. - */ -#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__) -#define STM32_HSI_ENABLED TRUE -#endif - -/** - * @brief Enables or disables the HSI14 clock source. - */ -#if !defined(STM32_HSI14_ENABLED) || defined(__DOXYGEN__) -#define STM32_HSI14_ENABLED TRUE -#endif - -/** - * @brief Enables or disables the LSI clock source. - */ -#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__) -#define STM32_LSI_ENABLED FALSE -#endif - -/** - * @brief Enables or disables the HSE clock source. - */ -#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__) -#define STM32_HSE_ENABLED TRUE -#endif - -/** - * @brief Enables or disables the LSE clock source. - */ -#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__) -#define STM32_LSE_ENABLED FALSE -#endif - -/** - * @brief Main clock source selection. - * @note If the selected clock source is not the PLL then the PLL is not - * initialized and started. - * @note The default value is calculated for a 48MHz system clock from - * a 8MHz crystal using the PLL. - */ -#if !defined(STM32_SW) || defined(__DOXYGEN__) -#define STM32_SW STM32_SW_PLL -#endif - -/** - * @brief Clock source for the PLL. - * @note This setting has only effect if the PLL is selected as the - * system clock source. - * @note The default value is calculated for a 48MHz system clock from - * a 8MHz crystal using the PLL. - */ -#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__) -#define STM32_PLLSRC STM32_PLLSRC_HSE -#endif - -/** - * @brief Crystal PLL pre-divider. - * @note This setting has only effect if the PLL is selected as the - * system clock source. - * @note The default value is calculated for a 72MHz system clock from - * a 8MHz crystal using the PLL. - */ -#if !defined(STM32_PREDIV_VALUE) || defined(__DOXYGEN__) -#define STM32_PREDIV_VALUE 1 -#endif - -/** - * @brief PLL multiplier value. - * @note The allowed range is 2...16. - * @note The default value is calculated for a 48MHz system clock from - * a 8MHz crystal using the PLL. - */ -#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLMUL_VALUE 6 -#endif - -/** - * @brief AHB prescaler value. - * @note The default value is calculated for a 48MHz system clock from - * a 8MHz crystal using the PLL. - */ -#if !defined(STM32_HPRE) || defined(__DOXYGEN__) -#define STM32_HPRE STM32_HPRE_DIV1 -#endif - -/** - * @brief APB1 prescaler value. - */ -#if !defined(STM32_PPRE) || defined(__DOXYGEN__) -#define STM32_PPRE STM32_PPRE_DIV1 -#endif - -/** - * @brief MCO pin setting. - */ -#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__) -#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK -#endif - -/** - * @brief ADC prescaler value. - */ -#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__) -#define STM32_ADCPRE STM32_ADCPRE_DIV4 -#endif - -/** - * @brief ADC clock source. - */ -#if !defined(STM32_ADCSW) || defined(__DOXYGEN__) -#define STM32_ADCSW STM32_ADCSW_HSI14 -#endif - -/** - * @brief CEC clock source. - */ -#if !defined(STM32_CECSW) || defined(__DOXYGEN__) -#define STM32_CECSW STM32_CECSW_HSI -#endif - -/** - * @brief I2C1 clock source. - */ -#if !defined(STM32_I2C1SW) || defined(__DOXYGEN__) -#define STM32_I2C1SW STM32_I2C1SW_HSI -#endif - -/** - * @brief USART1 clock source. - */ -#if !defined(STM32_USART1SW) || defined(__DOXYGEN__) -#define STM32_USART1SW STM32_USART1SW_PCLK -#endif - -/** - * @brief RTC clock source. - */ -#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__) -#define STM32_RTCSEL STM32_RTCSEL_LSI -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/* - * Configuration-related checks. - */ -#if !defined(STM32F0xx_MCUCONF) -#error "Using a wrong mcuconf.h file, STM32F0xx_MCUCONF not defined" -#endif - -/* - * HSI related checks. - */ -#if STM32_HSI_ENABLED -#else /* !STM32_HSI_ENABLED */ - -#if STM32_SW == STM32_SW_HSI -#error "HSI not enabled, required by STM32_SW" -#endif - -#if STM32_CECSW == STM32_CECSW_HSI -#error "HSI not enabled, required by STM32_CECSW" -#endif - -#if STM32_I2C1SW == STM32_I2C1SW_HSI -#error "HSI not enabled, required by STM32_I2C1SW" -#endif - -#if STM32_USART1SW == STM32_USART1SW_HSI -#error "HSI not enabled, required by STM32_USART1SW" -#endif - -#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI) -#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC" -#endif - -#if (STM32_MCOSEL == STM32_MCOSEL_HSI) || \ - ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \ - (STM32_PLLSRC == STM32_PLLSRC_HSI)) -#error "HSI not enabled, required by STM32_MCOSEL" -#endif - -#endif /* !STM32_HSI_ENABLED */ - -/* - * HSI14 related checks. - */ -#if STM32_HSI14_ENABLED -#else /* !STM32_HSI14_ENABLED */ - -#if STM32_MCOSEL == STM32_MCOSEL_HSI14 -#error "HSI14 not enabled, required by STM32_MCOSEL" -#endif - -#if STM32_ADCSW == STM32_ADCSW_HSI14 -#error "HSI14 not enabled, required by STM32_ADCSW" -#endif - -#endif /* !STM32_HSI14_ENABLED */ - -/* - * HSE related checks. - */ -#if STM32_HSE_ENABLED - -#if STM32_HSECLK == 0 -#error "HSE frequency not defined" -#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX) -#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)" -#endif - -#else /* !STM32_HSE_ENABLED */ - -#if STM32_SW == STM32_SW_HSE -#error "HSE not enabled, required by STM32_SW" -#endif - -#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE) -#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC" -#endif - -#if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \ - ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \ - (STM32_PLLSRC == STM32_PLLSRC_HSE)) -#error "HSE not enabled, required by STM32_MCOSEL" -#endif - -#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV -#error "HSE not enabled, required by STM32_RTCSEL" -#endif - -#endif /* !STM32_HSE_ENABLED */ - -/* - * LSI related checks. - */ -#if STM32_LSI_ENABLED -#else /* !STM32_LSI_ENABLED */ - -#if STM32_RTCSEL == STM32_RTCSEL_LSI -#error "LSI not enabled, required by STM32_RTCSEL" -#endif - -#endif /* !STM32_LSI_ENABLED */ - -/* - * LSE related checks. - */ -#if STM32_LSE_ENABLED - -#if (STM32_LSECLK == 0) -#error "LSE frequency not defined" -#endif - -#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX) -#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)" -#endif - -#if !defined(STM32_LSEDRV) -#error "STM32_LSEDRV not defined" -#endif - -#if (STM32_LSEDRV >> 3) > 3 -#error "STM32_LSEDRV outside acceptable range ((0<<3)...(3<<3))" -#endif - -#if STM32_CECSW == STM32_CECSW_LSE -#error "LSE not enabled, required by STM32_CECSW" -#endif - -#if STM32_USART1SW == STM32_USART1SW_LSE -#error "LSE not enabled, required by STM32_USART1SW" -#endif - -#else /* !STM32_LSE_ENABLED */ - -#if STM32_RTCSEL == STM32_RTCSEL_LSE -#error "LSE not enabled, required by STM32_RTCSEL" -#endif - -#endif /* !STM32_LSE_ENABLED */ - -/* PLL activation conditions.*/ -#if (STM32_SW == STM32_SW_PLL) || \ - (STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) || \ - defined(__DOXYGEN__) -/** - * @brief PLL activation flag. - */ -#define STM32_ACTIVATE_PLL TRUE -#else -#define STM32_ACTIVATE_PLL FALSE -#endif - -/* HSE prescaler setting check.*/ -#if ((STM32_PREDIV_VALUE >= 1) || (STM32_PREDIV_VALUE <= 16)) -#define STM32_PREDIV ((STM32_PREDIV_VALUE - 1) << 0) -#else -#error "invalid STM32_PREDIV value specified" -#endif - -/** - * @brief PLLMUL field. - */ -#if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) || \ - defined(__DOXYGEN__) -#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18) -#else -#error "invalid STM32_PLLMUL_VALUE value specified" -#endif - -/** - * @brief PLL input clock frequency. - */ -#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) -#define STM32_PLLCLKIN (STM32_HSECLK / STM32_PREDIV_VALUE) -#elif STM32_PLLSRC == STM32_PLLSRC_HSI -#define STM32_PLLCLKIN (STM32_HSICLK / 2) -#else -#error "invalid STM32_PLLSRC value specified" -#endif - -/* PLL input frequency range check.*/ -#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX) -#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)" -#endif - -/** - * @brief PLL output clock frequency. - */ -#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE) - -/* PLL output frequency range check.*/ -#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX) -#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)" -#endif - -/** - * @brief System clock source. - */ -#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__) -#define STM32_SYSCLK STM32_PLLCLKOUT -#elif (STM32_SW == STM32_SW_HSI) -#define STM32_SYSCLK STM32_HSICLK -#elif (STM32_SW == STM32_SW_HSE) -#define STM32_SYSCLK STM32_HSECLK -#else -#error "invalid STM32_SW value specified" -#endif - -/* Check on the system clock.*/ -#if STM32_SYSCLK > STM32_SYSCLK_MAX -#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)" -#endif - -/** - * @brief AHB frequency. - */ -#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__) -#define STM32_HCLK (STM32_SYSCLK / 1) -#elif STM32_HPRE == STM32_HPRE_DIV2 -#define STM32_HCLK (STM32_SYSCLK / 2) -#elif STM32_HPRE == STM32_HPRE_DIV4 -#define STM32_HCLK (STM32_SYSCLK / 4) -#elif STM32_HPRE == STM32_HPRE_DIV8 -#define STM32_HCLK (STM32_SYSCLK / 8) -#elif STM32_HPRE == STM32_HPRE_DIV16 -#define STM32_HCLK (STM32_SYSCLK / 16) -#elif STM32_HPRE == STM32_HPRE_DIV64 -#define STM32_HCLK (STM32_SYSCLK / 64) -#elif STM32_HPRE == STM32_HPRE_DIV128 -#define STM32_HCLK (STM32_SYSCLK / 128) -#elif STM32_HPRE == STM32_HPRE_DIV256 -#define STM32_HCLK (STM32_SYSCLK / 256) -#elif STM32_HPRE == STM32_HPRE_DIV512 -#define STM32_HCLK (STM32_SYSCLK / 512) -#else -#error "invalid STM32_HPRE value specified" -#endif - -/* AHB frequency check.*/ -#if STM32_HCLK > STM32_SYSCLK_MAX -#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)" -#endif - -/** - * @brief APB frequency. - */ -#if (STM32_PPRE == STM32_PPRE_DIV1) || defined(__DOXYGEN__) -#define STM32_PCLK (STM32_HCLK / 1) -#elif STM32_PPRE == STM32_PPRE_DIV2 -#define STM32_PCLK (STM32_HCLK / 2) -#elif STM32_PPRE == STM32_PPRE_DIV4 -#define STM32_PCLK (STM32_HCLK / 4) -#elif STM32_PPRE == STM32_PPRE_DIV8 -#define STM32_PCLK (STM32_HCLK / 8) -#elif STM32_PPRE == STM32_PPRE_DIV16 -#define STM32_PCLK (STM32_HCLK / 16) -#else -#error "invalid STM32_PPRE value specified" -#endif - -/* APB frequency check.*/ -#if STM32_PCLK > STM32_PCLK_MAX -#error "STM32_PCLK exceeding maximum frequency (STM32_PCLK_MAX)" -#endif - -/** - * @brief RTC clock. - */ -#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__) -#define STM32_RTCCLK STM32_LSECLK -#elif STM32_RTCSEL == STM32_RTCSEL_LSI -#define STM32_RTCCLK STM32_LSICLK -#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV -#define STM32_RTCCLK (STM32_HSECLK / 32) -#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK -#define STM32_RTCCLK 0 -#else -#error "invalid source selected for RTC clock" -#endif - -/** - * @brief ADC frequency. - */ -#if STM32_ADCSW == STM32_ADCSW_HSI14 -#define STM32_ADCCLK STM32_HSI14CLK -#elif STM32_ADCSW == STM32_ADCSW_PCLK -#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__) -#define STM32_ADCCLK (STM32_PCLK / 2) -#elif STM32_ADCPRE == STM32_ADCPRE_DIV4 -#define STM32_ADCCLK (STM32_PCLK / 4) -#else -#error "invalid STM32_ADCPRE value specified" -#endif -#else -#error "invalid source selected for ADC clock" -#endif - -/* ADC frequency check.*/ -#if STM32_ADCCLK > STM32_ADCCLK_MAX -#error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MAX)" -#endif - -/** - * @brief CEC frequency. - */ -#if STM32_CECSW == STM32_CECSW_HSI -#define STM32_CECCLK STM32_HSICLK -#elif STM32_CECSW == STM32_CECSW_LSE -#define STM32_CECCLK STM32_LSECLK -#else -#error "invalid source selected for CEC clock" -#endif - -/** - * @brief I2C1 frequency. - */ -#if STM32_I2C1SW == STM32_I2C1SW_HSI -#define STM32_I2C1CLK STM32_HSICLK -#elif STM32_I2C1SW == STM32_I2C1SW_SYSCLK -#define STM32_I2C1CLK STM32_SYSCLK -#else -#error "invalid source selected for I2C1 clock" -#endif - -/** - * @brief USART1 frequency. - */ -#if STM32_USART1SW == STM32_USART1SW_PCLK -#define STM32_USART1CLK STM32_PCLK -#elif STM32_USART1SW == STM32_USART1SW_SYSCLK -#define STM32_USART1CLK STM32_SYSCLK -#elif STM32_USART1SW == STM32_USART1SW_LSE -#define STM32_USART1CLK STM32_LSECLK -#elif STM32_USART1SW == STM32_USART1SW_HSI -#define STM32_USART1CLK STM32_HSICLK -#else -#error "invalid source selected for USART1 clock" -#endif - -/** - * @brief USART2 frequency. - */ -#define STM32_USART2CLK STM32_PCLK - -/** - * @brief Timers clock. - */ -#if (STM32_PPRE == STM32_PPRE_DIV1) || defined(__DOXYGEN__) -#define STM32_TIMCLK1 (STM32_PCLK * 1) -#define STM32_TIMCLK2 (STM32_PCLK * 1) -#else -#define STM32_TIMCLK1 (STM32_PCLK * 2) -#define STM32_TIMCLK2 (STM32_PCLK * 2) -#endif - -/** - * @brief Flash settings. - */ -#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__) -#define STM32_FLASHBITS 0x00000010 -#else -#define STM32_FLASHBITS 0x00000011 -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/* STM32 ISR, DMA and RCC helpers.*/ -#include "stm32_isr.h" -#include "stm32_dma.h" -#include "stm32_rcc.h" - -#ifdef __cplusplus -extern "C" { -#endif - void hal_lld_init(void); - void stm32_clock_init(void); -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_LLD_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32F0xx/platform.dox b/firmware/chibios/os/hal/platforms/STM32F0xx/platform.dox deleted file mode 100644 index 17c3acf2ad..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F0xx/platform.dox +++ /dev/null @@ -1,292 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @defgroup STM32F0xx_DRIVERS STM32F0xx Drivers - * @details This section describes all the supported drivers on the STM32F0xx - * platform and the implementation details of the single drivers. - * - * @ingroup platforms - */ - -/** - * @defgroup STM32F0xx_HAL STM32F0xx Initialization Support - * @details The STM32F0xx HAL support is responsible for system initialization. - * - * @section stm32f0xx_hal_1 Supported HW resources - * - PLL1. - * - RCC. - * - Flash. - * . - * @section stm32f0xx_hal_2 STM32F0xx HAL driver implementation features - * - PLL startup and stabilization. - * - Clock tree initialization. - * - Clock source selection. - * - Flash wait states initialization based on the selected clock options. - * - SYSTICK initialization based on current clock and kernel required rate. - * - DMA support initialization. - * . - * @ingroup STM32F0xx_DRIVERS - */ - -/** - * @defgroup STM32F0xx_ADC STM32F0xx ADC Support - * @details The STM32F0xx ADC driver supports the ADC peripherals using DMA - * channels for maximum performance. - * - * @section stm32f0xx_adc_1 Supported HW resources - * - ADC1. - * - DMA1. - * . - * @section stm32f0xx_adc_2 STM32F0xx ADC driver implementation features - * - Clock stop for reduced power usage when the driver is in stop state. - * - Streaming conversion using DMA for maximum performance. - * - Programmable ADC interrupt priority level. - * - Programmable DMA bus priority for each DMA channel. - * - Programmable DMA interrupt priority for each DMA channel. - * - DMA errors detection. - * . - * @ingroup STM32F0xx_DRIVERS - */ - -/** - * @defgroup STM32F0xx_EXT STM32F0xx EXT Support - * @details The STM32F0xx EXT driver uses the EXTI peripheral. - * - * @section stm32f0xx_ext_1 Supported HW resources - * - EXTI. - * . - * @section stm32f0xx_ext_2 STM32F0xx EXT driver implementation features - * - Each EXTI channel can be independently enabled and programmed. - * - Programmable EXTI interrupts priority level. - * - Capability to work as event sources (WFE) rather than interrupt sources. - * . - * @ingroup STM32F0xx_DRIVERS - */ - -/** - * @defgroup STM32F0xx_GPT STM32F0xx GPT Support - * @details The STM32F0xx GPT driver uses the TIMx peripherals. - * - * @section stm32f0xx_gpt_1 Supported HW resources - * - TIM1. - * - TIM2. - * - TIM3. - * . - * @section stm32f0xx_gpt_2 STM32F0xx GPT driver implementation features - * - Each timer can be independently enabled and programmed. Unused - * peripherals are left in low power mode. - * - Programmable TIMx interrupts priority level. - * . - * @ingroup STM32F0xx_DRIVERS - */ - -/** - * @defgroup STM32F0xx_ICU STM32F0xx ICU Support - * @details The STM32F0xx ICU driver uses the TIMx peripherals. - * - * @section stm32f0xx_icu_1 Supported HW resources - * - TIM1. - * - TIM2. - * - TIM3. - * . - * @section stm32f0xx_icu_2 STM32F0xx ICU driver implementation features - * - Each timer can be independently enabled and programmed. Unused - * peripherals are left in low power mode. - * - Programmable TIMx interrupts priority level. - * . - * @ingroup STM32F0xx_DRIVERS - */ - -/** - * @defgroup STM32F0xx_PAL STM32F0xx PAL Support - * @details The STM32F0xx PAL driver uses the GPIO peripherals. - * - * @section stm32f0xx_pal_1 Supported HW resources - * - GPIOA. - * - GPIOB. - * - GPIOC. - * - GPIOD. - * - GPIOF. - * . - * @section stm32f0xx_pal_2 STM32F0xx PAL driver implementation features - * The PAL driver implementation fully supports the following hardware - * capabilities: - * - 16 bits wide ports. - * - Atomic set/reset functions. - * - Atomic set+reset function (atomic bus operations). - * - Output latched regardless of the pad setting. - * - Direct read of input pads regardless of the pad setting. - * . - * @section stm32f0xx_pal_3 Supported PAL setup modes - * The STM32F0xx PAL driver supports the following I/O modes: - * - @p PAL_MODE_RESET. - * - @p PAL_MODE_UNCONNECTED. - * - @p PAL_MODE_INPUT. - * - @p PAL_MODE_INPUT_PULLUP. - * - @p PAL_MODE_INPUT_PULLDOWN. - * - @p PAL_MODE_INPUT_ANALOG. - * - @p PAL_MODE_OUTPUT_PUSHPULL. - * - @p PAL_MODE_OUTPUT_OPENDRAIN. - * - @p PAL_MODE_ALTERNATE (non standard). - * . - * Any attempt to setup an invalid mode is ignored. - * - * @section stm32f0xx_pal_4 Suboptimal behavior - * The STM32F0xx GPIO is less than optimal in several areas, the limitations - * should be taken in account while using the PAL driver: - * - Pad/port toggling operations are not atomic. - * - Pad/group mode setup is not atomic. - * . - * @ingroup STM32F0xx_DRIVERS - */ - -/** - * @defgroup STM32F0xx_PWM STM32F0xx PWM Support - * @details The STM32F0xx PWM driver uses the TIMx peripherals. - * - * @section stm32f0xx_pwm_1 Supported HW resources - * - TIM1. - * - TIM2. - * - TIM3. - * . - * @section stm32f0xx_pwm_2 STM32F0xx PWM driver implementation features - * - Each timer can be independently enabled and programmed. Unused - * peripherals are left in low power mode. - * - Four independent PWM channels per timer. - * - Programmable TIMx interrupts priority level. - * . - * @ingroup STM32F0xx_DRIVERS - */ - -/** - * @defgroup STM32F0xx_SERIAL STM32F0xx Serial Support - * @details The STM32F0xx Serial driver uses the USART/UART peripherals in a - * buffered, interrupt driven, implementation. - * - * @section stm32f0xx_serial_1 Supported HW resources - * The serial driver can support any of the following hardware resources: - * - USART1. - * - USART2. - * . - * @section stm32f0xx_serial_2 STM32F0xx Serial driver implementation features - * - Clock stop for reduced power usage when the driver is in stop state. - * - Each UART/USART can be independently enabled and programmed. Unused - * peripherals are left in low power mode. - * - Fully interrupt driven. - * - Programmable priority levels for each UART/USART. - * . - * @ingroup STM32F0xx_DRIVERS - */ - -/** - * @defgroup STM32F0xx_SPI STM32F0xx SPI Support - * @details The SPI driver supports the STM32F0xx SPI peripherals using DMA - * channels for maximum performance. - * - * @section stm32f0xx_spi_1 Supported HW resources - * - SPI1. - * - SPI2. - * - DMA1. - * . - * @section stm32f0xx_spi_2 STM32F0xx SPI driver implementation features - * - Clock stop for reduced power usage when the driver is in stop state. - * - Each SPI can be independently enabled and programmed. Unused - * peripherals are left in low power mode. - * - Programmable interrupt priority levels for each SPI. - * - DMA is used for receiving and transmitting. - * - Programmable DMA bus priority for each DMA channel. - * - Programmable DMA interrupt priority for each DMA channel. - * - Programmable DMA error hook. - * . - * @ingroup STM32F0xx_DRIVERS - */ - -/** - * @defgroup STM32F0xx_UART STM32F0xx UART Support - * @details The UART driver supports the STM32F0xx USART peripherals using DMA - * channels for maximum performance. - * - * @section stm32f0xx_uart_1 Supported HW resources - * The UART driver can support any of the following hardware resources: - * - USART1. - * - USART2. - * - DMA1. - * . - * @section stm32f0xx_uart_2 STM32F0xx UART driver implementation features - * - Clock stop for reduced power usage when the driver is in stop state. - * - Each UART/USART can be independently enabled and programmed. Unused - * peripherals are left in low power mode. - * - Programmable interrupt priority levels for each UART/USART. - * - DMA is used for receiving and transmitting. - * - Programmable DMA bus priority for each DMA channel. - * - Programmable DMA interrupt priority for each DMA channel. - * - Programmable DMA error hook. - * . - * @ingroup STM32F0xx_DRIVERS - */ - -/** - * @defgroup STM32F0xx_PLATFORM_DRIVERS STM32F0xx Platform Drivers - * @details Platform support drivers. Platform drivers do not implement HAL - * standard driver templates, their role is to support platform - * specific functionalities. - * - * @ingroup STM32F0xx_DRIVERS - */ - -/** - * @defgroup STM32F0xx_DMA STM32F0xx DMA Support - * @details This DMA helper driver is used by the other drivers in order to - * access the shared DMA resources in a consistent way. - * - * @section stm32f0xx_dma_1 Supported HW resources - * The DMA driver can support any of the following hardware resources: - * - DMA1. - * - DMA2 (where present). - * . - * @section stm32f0xx_dma_2 STM32F0xx DMA driver implementation features - * - Exports helper functions/macros to the other drivers that share the - * DMA resource. - * - Automatic DMA clock stop when not in use by any driver. - * - DMA streams and interrupt vectors sharing among multiple drivers. - * . - * @ingroup STM32F0xx_PLATFORM_DRIVERS - */ - -/** - * @defgroup STM32F0xx_ISR STM32F0xx ISR Support - * @details This ISR helper driver is used by the other drivers in order to - * map ISR names to physical vector names. - * - * @ingroup STM32F0xx_PLATFORM_DRIVERS - */ - -/** - * @defgroup STM32F0xx_RCC STM32F0xx RCC Support - * @details This RCC helper driver is used by the other drivers in order to - * access the shared RCC resources in a consistent way. - * - * @section stm32f0xx_rcc_1 Supported HW resources - * - RCC. - * . - * @section stm32f0xx_rcc_2 STM32F0xx RCC driver implementation features - * - Peripherals reset. - * - Peripherals clock enable. - * - Peripherals clock disable. - * . - * @ingroup STM32F0xx_PLATFORM_DRIVERS - */ diff --git a/firmware/chibios/os/hal/platforms/STM32F0xx/platform.mk b/firmware/chibios/os/hal/platforms/STM32F0xx/platform.mk deleted file mode 100644 index 42b2465fb2..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F0xx/platform.mk +++ /dev/null @@ -1,25 +0,0 @@ -# List of all the STM32F0xx platform files. -PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F0xx/stm32_dma.c \ - ${CHIBIOS}/os/hal/platforms/STM32F0xx/hal_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32F0xx/adc_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32F0xx/ext_lld_isr.c \ - ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/I2Cv2/i2c_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/RTCv2/rtc_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/SPIv2/spi_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/gpt_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/icu_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/pwm_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/USARTv2/serial_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/USARTv2/uart_lld.c - -# Required include directories -PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F0xx \ - ${CHIBIOS}/os/hal/platforms/STM32 \ - ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \ - ${CHIBIOS}/os/hal/platforms/STM32/RTCv2 \ - ${CHIBIOS}/os/hal/platforms/STM32/I2Cv2 \ - ${CHIBIOS}/os/hal/platforms/STM32/SPIv2 \ - ${CHIBIOS}/os/hal/platforms/STM32/TIMv1 \ - ${CHIBIOS}/os/hal/platforms/STM32/USARTv2 diff --git a/firmware/chibios/os/hal/platforms/STM32F0xx/stm32_dma.c b/firmware/chibios/os/hal/platforms/STM32F0xx/stm32_dma.c deleted file mode 100644 index 892cf9518c..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F0xx/stm32_dma.c +++ /dev/null @@ -1,315 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F0xx/stm32_dma.c - * @brief DMA helper driver code. - * - * @addtogroup STM32F0xx_DMA - * @details DMA sharing helper driver. In the STM32 the DMA streams are a - * shared resource, this driver allows to allocate and free DMA - * streams at runtime in order to allow all the other device - * drivers to coordinate the access to the resource. - * @note The DMA ISR handlers are all declared into this module because - * sharing, the various device drivers can associate a callback to - * ISRs when allocating streams. - * @{ - */ - -#include "ch.h" -#include "hal.h" - -/* The following macro is only defined if some driver requiring DMA services - has been enabled.*/ -#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/** - * @brief Mask of the DMA1 streams in @p dma_streams_mask. - */ -#define STM32_DMA1_STREAMS_MASK 0x0000007F - -/** - * @brief Mask of the DMA2 streams in @p dma_streams_mask. - */ -#define STM32_DMA2_STREAMS_MASK 0x00000F80 - -/** - * @brief Post-reset value of the stream CCR register. - */ -#define STM32_DMA_CCR_RESET_VALUE 0x00000000 - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief DMA streams descriptors. - * @details This table keeps the association between an unique stream - * identifier and the involved physical registers. - * @note Don't use this array directly, use the appropriate wrapper macros - * instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc. - */ -const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = { - {DMA1_Channel1, &DMA1->IFCR, 0x0001, 0, 0, DMA1_Channel1_IRQn}, - {DMA1_Channel2, &DMA1->IFCR, 0x0006, 4, 1, DMA1_Channel2_3_IRQn}, - {DMA1_Channel3, &DMA1->IFCR, 0x0006, 8, 2, DMA1_Channel2_3_IRQn}, - {DMA1_Channel4, &DMA1->IFCR, 0x0078, 12, 3, DMA1_Channel4_5_IRQn}, - {DMA1_Channel5, &DMA1->IFCR, 0x0078, 16, 4, DMA1_Channel4_5_IRQn}, -#if STM32_DMA_STREAMS > 5 - {DMA1_Channel6, &DMA1->IFCR, 0x0078, 20, 5, DMA1_Channel4_5_6_7_IRQn}, - {DMA1_Channel7, &DMA1->IFCR, 0x0078, 24, 6, DMA1_Channel4_5_6_7_IRQn} -#endif -}; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief DMA ISR redirector type. - */ -typedef struct { - stm32_dmaisr_t dma_func; /**< @brief DMA callback function. */ - void *dma_param; /**< @brief DMA callback parameter. */ -} dma_isr_redir_t; - -/** - * @brief Mask of the allocated streams. - */ -static uint32_t dma_streams_mask; - -/** - * @brief DMA IRQ redirectors. - */ -static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS]; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief DMA1 stream 1 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(Vector64) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK; - DMA1->IFCR = flags << 0; - if (dma_isr_redir[0].dma_func) - dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 streams 2 and 3 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(Vector68) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - /* Check on channel 2.*/ - flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK; - if (flags & STM32_DMA_ISR_MASK) { - DMA1->IFCR = flags << 4; - if (dma_isr_redir[1].dma_func) - dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags); - } - - /* Check on channel 3.*/ - flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK; - if (flags & STM32_DMA_ISR_MASK) { - DMA1->IFCR = flags << 8; - if (dma_isr_redir[2].dma_func) - dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags); - } - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 streams 4 and 5 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(Vector6C) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - /* Check on channel 4.*/ - flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK; - if (flags & STM32_DMA_ISR_MASK) { - DMA1->IFCR = flags << 12; - if (dma_isr_redir[3].dma_func) - dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags); - } - - /* Check on channel 5.*/ - flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK; - if (flags & STM32_DMA_ISR_MASK) { - DMA1->IFCR = flags << 16; - if (dma_isr_redir[4].dma_func) - dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags); - } - -#if STM32_DMA_STREAMS > 5 - /* Check on channel 6.*/ - flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK; - if (flags & STM32_DMA_ISR_MASK) { - DMA1->IFCR = flags << 20; - if (dma_isr_redir[5].dma_func) - dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags); - } - - /* Check on channel 7.*/ - flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK; - if (flags & STM32_DMA_ISR_MASK) { - DMA1->IFCR = flags << 24; - if (dma_isr_redir[6].dma_func) - dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags); - } -#endif - - CH_IRQ_EPILOGUE(); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief STM32 DMA helper initialization. - * - * @init - */ -void dmaInit(void) { - int i; - - dma_streams_mask = 0; - for (i = 0; i < STM32_DMA_STREAMS; i++) { - _stm32_dma_streams[i].channel->CCR = 0; - dma_isr_redir[i].dma_func = NULL; - } - DMA1->IFCR = 0xFFFFFFFF; -} - -/** - * @brief Allocates a DMA stream. - * @details The stream is allocated and, if required, the DMA clock enabled. - * The function also enables the IRQ vector associated to the stream - * and initializes its priority. - * @pre The stream must not be already in use or an error is returned. - * @post The stream is allocated and the default ISR handler redirected - * to the specified function. - * @post The stream ISR vector is enabled and its priority configured. - * @post The stream must be freed using @p dmaStreamRelease() before it can - * be reused with another peripheral. - * @post The stream is in its post-reset state. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] priority IRQ priority mask for the DMA stream - * @param[in] func handling function pointer, can be @p NULL - * @param[in] param a parameter to be passed to the handling function - * @return The operation status. - * @retval FALSE no error, stream taken. - * @retval TRUE error, stream already taken. - * - * @special - */ -bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, - uint32_t priority, - stm32_dmaisr_t func, - void *param) { - - chDbgCheck(dmastp != NULL, "dmaStreamAllocate"); - - /* Checks if the stream is already taken.*/ - if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0) - return TRUE; - - /* Marks the stream as allocated.*/ - dma_isr_redir[dmastp->selfindex].dma_func = func; - dma_isr_redir[dmastp->selfindex].dma_param = param; - dma_streams_mask |= (1 << dmastp->selfindex); - - /* Enabling DMA clocks required by the current streams set.*/ - if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0) - rccEnableDMA1(FALSE); - - /* Putting the stream in a safe state.*/ - dmaStreamDisable(dmastp); - dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE; - - /* Enables the associated IRQ vector.*/ - nvicEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority)); - - return FALSE; -} - -/** - * @brief Releases a DMA stream. - * @details The stream is freed and, if required, the DMA clock disabled. - * Trying to release a unallocated stream is an illegal operation - * and is trapped if assertions are enabled. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post The stream is again available. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * - * @special - */ -void dmaStreamRelease(const stm32_dma_stream_t *dmastp) { - - chDbgCheck(dmastp != NULL, "dmaStreamRelease"); - - /* Check if the streams is not taken.*/ - chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0, - "dmaStreamRelease(), #1", "not allocated"); - - /* Marks the stream as not allocated.*/ - dma_streams_mask &= ~(1 << dmastp->selfindex); - - /* Disables the associated IRQ vector if also the sharing channels are - also disabled.*/ - if ((dma_streams_mask & dmastp->sharedmask) == 0) - nvicDisableVector(dmastp->vector); - - /* Shutting down clocks that are no more required, if any.*/ - if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0) - rccDisableDMA1(FALSE); -} - -#endif /* STM32_DMA_REQUIRED */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32F0xx/stm32_dma.h b/firmware/chibios/os/hal/platforms/STM32F0xx/stm32_dma.h deleted file mode 100644 index 7de326a76a..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F0xx/stm32_dma.h +++ /dev/null @@ -1,406 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F0xx/stm32_dma.h - * @brief DMA helper driver header. - * @note This file requires definitions from the ST header file stm32f0xx.h. - * @note This driver uses the new naming convention used for the STM32F2xx - * so the "DMA channels" are referred as "DMA streams". - * - * @addtogroup STM32F0xx_DMA - * @{ - */ - -#ifndef _STM32_DMA_H_ -#define _STM32_DMA_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Mask of the ISR bits passed to the DMA callback functions. - */ -#define STM32_DMA_ISR_MASK 0x0F - -/** - * @brief Returns the channel associated to the specified stream. - * - * @param[in] n the stream number (0...STM32_DMA_STREAMS-1) - * @param[in] c a stream/channel association word, one channel per - * nibble, not associated channels must be set to 0xF - * @return Always zero, in this platform there is no dynamic - * association between streams and channels. - */ -#define STM32_DMA_GETCHANNEL(n, c) 0 - -/** - * @brief Checks if a DMA priority is within the valid range. - * @param[in] prio DMA priority - * - * @retval The check result. - * @retval FALSE invalid DMA priority. - * @retval TRUE correct DMA priority. - */ -#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3)) - -/** - * @brief Returns an unique numeric identifier for a DMA stream. - * - * @param[in] dma the DMA unit number - * @param[in] stream the stream number - * @return An unique numeric stream identifier. - */ -#define STM32_DMA_STREAM_ID(dma, stream) ((stream) - 1) - -/** - * @brief Returns a DMA stream identifier mask. - * - * - * @param[in] dma the DMA unit number - * @param[in] stream the stream number - * @return A DMA stream identifier mask. - */ -#define STM32_DMA_STREAM_ID_MSK(dma, stream) \ - (1 << STM32_DMA_STREAM_ID(dma, stream)) - -/** - * @brief Checks if a DMA stream unique identifier belongs to a mask. - * @param[in] id the stream numeric identifier - * @param[in] mask the stream numeric identifiers mask - * - * @retval The check result. - * @retval FALSE id does not belong to the mask. - * @retval TRUE id belongs to the mask. - */ -#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask))) - -/** - * @name DMA streams identifiers - * @{ - */ -/** - * @brief Returns a pointer to a stm32_dma_stream_t structure. - * - * @param[in] id the stream numeric identifier - * @return A pointer to the stm32_dma_stream_t constant structure - * associated to the DMA stream. - */ -#define STM32_DMA_STREAM(id) (&_stm32_dma_streams[id]) - -#define STM32_DMA1_STREAM1 STM32_DMA_STREAM(0) -#define STM32_DMA1_STREAM2 STM32_DMA_STREAM(1) -#define STM32_DMA1_STREAM3 STM32_DMA_STREAM(2) -#define STM32_DMA1_STREAM4 STM32_DMA_STREAM(3) -#define STM32_DMA1_STREAM5 STM32_DMA_STREAM(4) -#if (STM32_DMA_STREAMS > 5) || defined(__DOXYGEN__) -#define STM32_DMA1_STREAM6 STM32_DMA_STREAM(5) -#define STM32_DMA1_STREAM7 STM32_DMA_STREAM(6) -#endif -/** @} */ - -/** - * @name CR register constants common to all DMA types - * @{ - */ -#define STM32_DMA_CR_EN DMA_CCR_EN -#define STM32_DMA_CR_TEIE DMA_CCR_TEIE -#define STM32_DMA_CR_HTIE DMA_CCR_HTIE -#define STM32_DMA_CR_TCIE DMA_CCR_TCIE -#define STM32_DMA_CR_DIR_MASK (DMA_CCR_DIR | DMA_CCR_MEM2MEM) -#define STM32_DMA_CR_DIR_P2M 0 -#define STM32_DMA_CR_DIR_M2P DMA_CCR_DIR -#define STM32_DMA_CR_DIR_M2M DMA_CCR_MEM2MEM -#define STM32_DMA_CR_CIRC DMA_CCR_CIRC -#define STM32_DMA_CR_PINC DMA_CCR_PINC -#define STM32_DMA_CR_MINC DMA_CCR_MINC -#define STM32_DMA_CR_PSIZE_MASK DMA_CCR_PSIZE -#define STM32_DMA_CR_PSIZE_BYTE 0 -#define STM32_DMA_CR_PSIZE_HWORD DMA_CCR_PSIZE_0 -#define STM32_DMA_CR_PSIZE_WORD DMA_CCR_PSIZE_1 -#define STM32_DMA_CR_MSIZE_MASK DMA_CCR_MSIZE -#define STM32_DMA_CR_MSIZE_BYTE 0 -#define STM32_DMA_CR_MSIZE_HWORD DMA_CCR_MSIZE_0 -#define STM32_DMA_CR_MSIZE_WORD DMA_CCR_MSIZE_1 -#define STM32_DMA_CR_SIZE_MASK (STM32_DMA_CR_PSIZE_MASK | \ - STM32_DMA_CR_MSIZE_MASK) -#define STM32_DMA_CR_PL_MASK DMA_CCR_PL -#define STM32_DMA_CR_PL(n) ((n) << 12) -/** @} */ - -/** - * @name CR register constants only found in enhanced DMA - * @{ - */ -#define STM32_DMA_CR_DMEIE 0 /**< @brief Ignored by normal DMA. */ -#define STM32_DMA_CR_CHSEL_MASK 0 /**< @brief Ignored by normal DMA. */ -#define STM32_DMA_CR_CHSEL(n) 0 /**< @brief Ignored by normal DMA. */ -/** @} */ - -/** - * @name Status flags passed to the ISR callbacks - * @{ - */ -#define STM32_DMA_ISR_FEIF 0 -#define STM32_DMA_ISR_DMEIF 0 -#define STM32_DMA_ISR_TEIF DMA_ISR_TEIF1 -#define STM32_DMA_ISR_HTIF DMA_ISR_HTIF1 -#define STM32_DMA_ISR_TCIF DMA_ISR_TCIF1 -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !defined(STM32_ADVANCED_DMA) -#error "missing STM32_ADVANCED_DMA definition in registry" -#endif - -#if !defined(STM32_DMA_STREAMS) -#error "missing STM32_DMA_STREAMS definition in registry" -#endif - -#if STM32_ADVANCED_DMA == TRUE -#error "DMAv1 driver does not support STM32_ADVANCED_DMA" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief STM32 DMA stream descriptor structure. - */ -typedef struct { - DMA_Channel_TypeDef *channel; /**< @brief Associated DMA channel. */ - volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */ - uint32_t sharedmask; /**< @brief Mask of channels sharing - the same ISR. */ - uint8_t ishift; /**< @brief Bits offset in xIFCR - register. */ - uint8_t selfindex; /**< @brief Index to self in array. */ - uint8_t vector; /**< @brief Associated IRQ vector. */ -} stm32_dma_stream_t; - -/** - * @brief STM32 DMA ISR function type. - * - * @param[in] p parameter for the registered function - * @param[in] flags pre-shifted content of the ISR register, the bits - * are aligned to bit zero - */ -typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Associates a peripheral data register to a DMA stream. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] addr value to be written in the CPAR register - * - * @special - */ -#define dmaStreamSetPeripheral(dmastp, addr) { \ - (dmastp)->channel->CPAR = (uint32_t)(addr); \ -} - -/** - * @brief Associates a memory destination to a DMA stream. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] addr value to be written in the CMAR register - * - * @special - */ -#define dmaStreamSetMemory0(dmastp, addr) { \ - (dmastp)->channel->CMAR = (uint32_t)(addr); \ -} - -/** - * @brief Sets the number of transfers to be performed. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] size value to be written in the CNDTR register - * - * @special - */ -#define dmaStreamSetTransactionSize(dmastp, size) { \ - (dmastp)->channel->CNDTR = (uint32_t)(size); \ -} - -/** - * @brief Returns the number of transfers to be performed. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @return The number of transfers to be performed. - * - * @special - */ -#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR)) - -/** - * @brief Programs the stream mode settings. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] mode value to be written in the CCR register - * - * @special - */ -#define dmaStreamSetMode(dmastp, mode) { \ - (dmastp)->channel->CCR = (uint32_t)(mode); \ -} - -/** - * @brief DMA stream enable. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * - * @special - */ -#define dmaStreamEnable(dmastp) { \ - (dmastp)->channel->CCR |= STM32_DMA_CR_EN; \ -} - -/** - * @brief DMA stream disable. - * @details The function disables the specified stream and then clears any - * pending interrupt. - * @note This function can be invoked in both ISR or thread context. - * @note Interrupts enabling flags are set to zero after this call, see - * bug 3607518. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * - * @special - */ -#define dmaStreamDisable(dmastp) { \ - (dmastp)->channel->CCR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | \ - STM32_DMA_CR_TEIE | STM32_DMA_CR_EN); \ - dmaStreamClearInterrupt(dmastp); \ -} - -/** - * @brief DMA stream interrupt sources clear. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * - * @special - */ -#define dmaStreamClearInterrupt(dmastp) { \ - *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \ -} - -/** - * @brief Starts a memory to memory operation using the specified stream. - * @note The default transfer data mode is "byte to byte" but it can be - * changed by specifying extra options in the @p mode parameter. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] mode value to be written in the CCR register, this value - * is implicitly ORed with: - * - @p STM32_DMA_CR_MINC - * - @p STM32_DMA_CR_PINC - * - @p STM32_DMA_CR_DIR_M2M - * - @p STM32_DMA_CR_EN - * . - * @param[in] src source address - * @param[in] dst destination address - * @param[in] n number of data units to copy - */ -#define dmaStartMemCopy(dmastp, mode, src, dst, n) { \ - dmaStreamSetPeripheral(dmastp, src); \ - dmaStreamSetMemory0(dmastp, dst); \ - dmaStreamSetTransactionSize(dmastp, n); \ - dmaStreamSetMode(dmastp, (mode) | \ - STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \ - STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); \ -} - -/** - * @brief Polled wait for DMA transfer end. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - */ -#define dmaWaitCompletion(dmastp) { \ - while ((dmastp)->channel->CNDTR > 0) \ - ; \ - dmaStreamDisable(dmastp); \ -} -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS]; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void dmaInit(void); - bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, - uint32_t priority, - stm32_dmaisr_t func, - void *param); - void dmaStreamRelease(const stm32_dma_stream_t *dmastp); -#ifdef __cplusplus -} -#endif - -#endif /* _STM32_DMA_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32F0xx/stm32_isr.h b/firmware/chibios/os/hal/platforms/STM32F0xx/stm32_isr.h deleted file mode 100644 index 97d15c41c3..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F0xx/stm32_isr.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F0xx/stm32_isr.h - * @brief ISR remapper driver header. - * - * @addtogroup STM32F0xx_ISR - * @{ - */ - -#ifndef _STM32_ISR_H_ -#define _STM32_ISR_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name ISR names and numbers remapping - * @{ - */ - -/* - * I2C units. - */ -#define STM32_I2C1_GLOBAL_HANDLER Vector9C -#define STM32_I2C1_GLOBAL_NUMBER 23 - -#define STM32_I2C2_GLOBAL_HANDLER VectorA0 -#define STM32_I2C2_GLOBAL_NUMBER 24 - -/* - * TIM units. - */ -#define STM32_TIM1_UP_HANDLER Vector74 -#define STM32_TIM1_CC_HANDLER Vector78 -#define STM32_TIM2_HANDLER Vector7C -#define STM32_TIM3_HANDLER Vector80 - -#define STM32_TIM1_UP_NUMBER 13 -#define STM32_TIM1_CC_NUMBER 14 -#define STM32_TIM2_NUMBER 15 -#define STM32_TIM3_NUMBER 16 - -/* - * USART units. - */ -#define STM32_USART1_HANDLER VectorAC -#define STM32_USART2_HANDLER VectorB0 - -#define STM32_USART1_NUMBER 27 -#define STM32_USART2_NUMBER 28 -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#endif /* _STM32_ISR_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32F0xx/stm32_rcc.h b/firmware/chibios/os/hal/platforms/STM32F0xx/stm32_rcc.h deleted file mode 100644 index c943d31532..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F0xx/stm32_rcc.h +++ /dev/null @@ -1,596 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F0xx/stm32_rcc.h - * @brief RCC helper driver header. - * @note This file requires definitions from the ST header file - * @p stm32f0xx.h. - * - * @addtogroup STM32F0xx_RCC - * @{ - */ - -#ifndef _STM32_RCC_ -#define _STM32_RCC_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Generic RCC operations - * @{ - */ -/** - * @brief Enables the clock of one or more peripheral on the APB1 bus. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] mask APB1 peripherals mask - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableAPB1(mask, lp) { \ - RCC->APB1ENR |= (mask); \ -} - -/** - * @brief Disables the clock of one or more peripheral on the APB1 bus. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] mask APB1 peripherals mask - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableAPB1(mask, lp) { \ - RCC->APB1ENR &= ~(mask); \ -} - -/** - * @brief Resets one or more peripheral on the APB1 bus. - * - * @param[in] mask APB1 peripherals mask - * - * @api - */ -#define rccResetAPB1(mask) { \ - RCC->APB1RSTR |= (mask); \ - RCC->APB1RSTR = 0; \ -} - -/** - * @brief Enables the clock of one or more peripheral on the APB2 bus. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] mask APB2 peripherals mask - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableAPB2(mask, lp) { \ - RCC->APB2ENR |= (mask); \ -} - -/** - * @brief Disables the clock of one or more peripheral on the APB2 bus. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] mask APB2 peripherals mask - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableAPB2(mask, lp) { \ - RCC->APB2ENR &= ~(mask); \ -} - -/** - * @brief Resets one or more peripheral on the APB2 bus. - * - * @param[in] mask APB2 peripherals mask - * - * @api - */ -#define rccResetAPB2(mask) { \ - RCC->APB2RSTR |= (mask); \ - RCC->APB2RSTR = 0; \ -} - -/** - * @brief Enables the clock of one or more peripheral on the AHB bus. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] mask AHB peripherals mask - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableAHB(mask, lp) { \ - RCC->AHBENR |= (mask); \ -} - -/** - * @brief Disables the clock of one or more peripheral on the AHB bus. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] mask AHB peripherals mask - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableAHB(mask, lp) { \ - RCC->AHBENR &= ~(mask); \ -} - -/** - * @brief Resets one or more peripheral on the AHB bus. - * - * @param[in] mask AHB peripherals mask - * - * @api - */ -#define rccResetAHB(mask) { \ - RCC->AHBRSTR |= (mask); \ - RCC->AHBRSTR = 0; \ -} -/** @} */ - -/** - * @name ADC peripherals specific RCC operations - * @{ - */ -/** - * @brief Enables the ADC1 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp) - -/** - * @brief Disables the ADC1 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableADC1(lp) rccDisableAPB2(RCC_APB2ENR_ADC1EN, lp) - -/** - * @brief Resets the ADC1 peripheral. - * - * @api - */ -#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST) -/** @} */ - -/** - * @name PWR interface specific RCC operations - * @{ - */ -/** - * @brief Enables the PWR interface clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp) - -/** - * @brief Disables PWR interface clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp) - -/** - * @brief Resets the PWR interface. - * - * @api - */ -#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST) -/** @} */ - -/** - * @name DMA peripherals specific RCC operations - * @{ - */ -/** - * @brief Enables the DMA1 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableDMA1(lp) rccEnableAHB(RCC_AHBENR_DMA1EN, lp) - -/** - * @brief Disables the DMA1 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableDMA1(lp) rccDisableAHB(RCC_AHBENR_DMA1EN, lp) - -/** - * @brief Resets the DMA1 peripheral. - * @note Not supported in this family, does nothing. - * - * @api - */ -#define rccResetDMA1() -/** @} */ - -/** - * @name I2C peripherals specific RCC operations - * @{ - */ -/** - * @brief Enables the I2C1 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp) - -/** - * @brief Disables the I2C1 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableI2C1(lp) rccDisableAPB1(RCC_APB1ENR_I2C1EN, lp) - -/** - * @brief Resets the I2C1 peripheral. - * - * @api - */ -#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST) - -/** - * @brief Enables the I2C2 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp) - -/** - * @brief Disables the I2C2 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableI2C2(lp) rccDisableAPB1(RCC_APB1ENR_I2C2EN, lp) - -/** - * @brief Resets the I2C2 peripheral. - * - * @api - */ -#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST) -/** @} */ - -/** - * @name SPI peripherals specific RCC operations - * @{ - */ -/** - * @brief Enables the SPI1 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp) - -/** - * @brief Disables the SPI1 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp) - -/** - * @brief Resets the SPI1 peripheral. - * - * @api - */ -#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST) - -/** - * @brief Enables the SPI2 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp) - -/** - * @brief Disables the SPI2 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableSPI2(lp) rccDisableAPB1(RCC_APB1ENR_SPI2EN, lp) - -/** - * @brief Resets the SPI2 peripheral. - * - * @api - */ -#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST) -/** @} */ - -/** - * @name TIM peripherals specific RCC operations - * @{ - */ -/** - * @brief Enables the TIM1 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp) - -/** - * @brief Disables the TIM1 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM1(lp) rccDisableAPB2(RCC_APB2ENR_TIM1EN, lp) - -/** - * @brief Resets the TIM1 peripheral. - * - * @api - */ -#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST) - -/** - * @brief Enables the TIM2 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp) - -/** - * @brief Disables the TIM2 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp) - -/** - * @brief Resets the TIM2 peripheral. - * - * @api - */ -#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST) - -/** - * @brief Enables the TIM3 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp) - -/** - * @brief Disables the TIM3 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp) - -/** - * @brief Resets the TIM3 peripheral. - * - * @api - */ -#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST) -/** @} */ - -/** - * @name USART/UART peripherals specific RCC operations - * @{ - */ -/** - * @brief Enables the USART1 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp) - -/** - * @brief Disables the USART1 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp) - -/** - * @brief Resets the USART1 peripheral. - * - * @api - */ -#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST) - -/** - * @brief Enables the USART2 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp) - -/** - * @brief Disables the USART2 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableUSART2(lp) rccDisableAPB1(RCC_APB1ENR_USART2EN, lp) - -/** - * @brief Resets the USART2 peripheral. - * - * @api - */ -#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST) - -/** - * @brief Enables the CRC peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableCRC(lp) rccEnableAHB(RCC_AHBENR_CRCEN, lp) - -/** - * @brief Disables the CRC peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableCRC(lp) rccDisableAHB(RCC_AHBENR_CRCEN, lp) - -/** - * @brief Resets the CRC peripheral. - * - * @api - */ -#define rccResetCRC() rccResetAHB(RCC_AHBRSTR_CRCRST) - -/** - * @brief Enables the WWDG peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableWWDG(lp) rccEnableAPB1(RCC_APB1ENR_WWDGEN, lp) - -/** - * @brief Disables the WWDG peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableWWDG(lp) rccDisableAPB1(RCC_APB1ENR_WWDGEN, lp) - -/** - * @brief Resets the WWDG peripheral. - * - * @api - */ -#define rccResetWWDG() rccResetAPB1(RCC_APB1RSTR_WWDGRST) -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif -#ifdef __cplusplus -} -#endif - -#endif /* _STM32_RCC_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32F0xx/stm32_registry.h b/firmware/chibios/os/hal/platforms/STM32F0xx/stm32_registry.h deleted file mode 100644 index 22bee5bef7..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F0xx/stm32_registry.h +++ /dev/null @@ -1,417 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F0xx/stm32_registry.h - * @brief STM32F0xx capabilities registry. - * - * @addtogroup HAL - * @{ - */ - -#ifndef _STM32_REGISTRY_H_ -#define _STM32_REGISTRY_H_ - -/*===========================================================================*/ -/* Platform capabilities. */ -/*===========================================================================*/ - -/** - * @name STM32F0xx capabilities - * @{ - */ -#if defined(STM32F0XX_MD) || defined(__DOXYGEN__) - -/* ADC attributes.*/ -#define STM32_HAS_ADC1 TRUE -#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) | \ - STM32_DMA_STREAM_ID_MSK(1, 2)) -#define STM32_ADC1_DMA_CHN 0x00000000 - -#define STM32_HAS_ADC2 FALSE -#define STM32_HAS_ADC3 FALSE -#define STM32_HAS_ADC4 FALSE - -/* CAN attributes.*/ -#define STM32_HAS_CAN1 FALSE -#define STM32_HAS_CAN2 FALSE -#define STM32_CAN_MAX_FILTERS 0 - -/* DAC attributes.*/ -#define STM32_HAS_DAC TRUE - -/* DMA attributes.*/ -#define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 FALSE -#define STM32_DMA_STREAMS 5 - -/* ETH attributes.*/ -#define STM32_HAS_ETH FALSE - -/* EXTI attributes.*/ -#define STM32_EXTI_NUM_CHANNELS 28 - -/* GPIO attributes.*/ -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE FALSE -#define STM32_HAS_GPIOF TRUE -#define STM32_HAS_GPIOG FALSE -#define STM32_HAS_GPIOH FALSE -#define STM32_HAS_GPIOI FALSE - -/* I2C attributes.*/ -#define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) -#define STM32_I2C1_RX_DMA_CHN 0x00000000 -#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) -#define STM32_I2C1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_I2C2 TRUE -#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_I2C2_RX_DMA_CHN 0x00000000 -#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_I2C2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_I2C3 FALSE - -/* RTC attributes.*/ -#define STM32_HAS_RTC TRUE -#define STM32_RTC_HAS_SUBSECONDS FALSE -#define STM32_RTC_IS_CALENDAR TRUE - -/* SDIO attributes.*/ -#define STM32_HAS_SDIO FALSE - -/* SPI attributes.*/ -#define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) -#define STM32_SPI1_RX_DMA_CHN 0x00000000 -#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) -#define STM32_SPI1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI2 TRUE -#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) -#define STM32_SPI2_RX_DMA_CHN 0x00000000 -#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) -#define STM32_SPI2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI3 FALSE -#define STM32_HAS_SPI4 FALSE -#define STM32_HAS_SPI5 FALSE -#define STM32_HAS_SPI6 FALSE - -/* TIM attributes.*/ -#define STM32_HAS_TIM1 TRUE -#define STM32_HAS_TIM2 TRUE -#define STM32_HAS_TIM3 TRUE -#define STM32_HAS_TIM4 FALSE -#define STM32_HAS_TIM5 FALSE -#define STM32_HAS_TIM6 TRUE -#define STM32_HAS_TIM7 FALSE -#define STM32_HAS_TIM8 FALSE -#define STM32_HAS_TIM9 FALSE -#define STM32_HAS_TIM10 FALSE -#define STM32_HAS_TIM11 FALSE -#define STM32_HAS_TIM12 FALSE -#define STM32_HAS_TIM13 FALSE -#define STM32_HAS_TIM14 TRUE -#define STM32_HAS_TIM15 TRUE -#define STM32_HAS_TIM16 TRUE -#define STM32_HAS_TIM17 TRUE -#define STM32_HAS_TIM18 FALSE -#define STM32_HAS_TIM19 FALSE - -/* USART attributes.*/ -#define STM32_HAS_USART1 TRUE -#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) | \ - STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_USART1_RX_DMA_CHN 0x00000000 -#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) | \ - STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_USART1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART2 TRUE -#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_USART2_RX_DMA_CHN 0x00000000 -#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_USART2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART3 FALSE -#define STM32_HAS_UART4 FALSE -#define STM32_HAS_UART5 FALSE -#define STM32_HAS_USART6 FALSE - -/* USB attributes.*/ -#define STM32_HAS_USB TRUE -#define STM32_HAS_OTG1 FALSE -#define STM32_HAS_OTG2 FALSE - -#elif defined(STM32F0XX_LD) - -/* ADC attributes.*/ -#define STM32_HAS_ADC1 TRUE -#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) | \ - STM32_DMA_STREAM_ID_MSK(1, 2)) -#define STM32_ADC1_DMA_CHN 0x00000000 - -#define STM32_HAS_ADC2 FALSE -#define STM32_HAS_ADC3 FALSE -#define STM32_HAS_ADC4 FALSE - -/* CAN attributes.*/ -#define STM32_HAS_CAN1 FALSE -#define STM32_HAS_CAN2 FALSE -#define STM32_CAN_MAX_FILTERS 0 - -/* DAC attributes.*/ -#define STM32_HAS_DAC FALSE - -/* DMA attributes.*/ -#define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 FALSE -#define STM32_DMA_STREAMS 5 - -/* ETH attributes.*/ -#define STM32_HAS_ETH FALSE - -/* EXTI attributes.*/ -#define STM32_EXTI_NUM_CHANNELS 28 - -/* GPIO attributes.*/ -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD FALSE -#define STM32_HAS_GPIOE FALSE -#define STM32_HAS_GPIOF TRUE -#define STM32_HAS_GPIOG FALSE -#define STM32_HAS_GPIOH FALSE -#define STM32_HAS_GPIOI FALSE - -/* I2C attributes.*/ -#define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) -#define STM32_I2C1_RX_DMA_CHN 0x00000000 -#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) -#define STM32_I2C1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_I2C2 FALSE -#define STM32_HAS_I2C3 FALSE - -/* RTC attributes.*/ -#define STM32_HAS_RTC TRUE -#define STM32_RTC_HAS_SUBSECONDS FALSE -#define STM32_RTC_IS_CALENDAR TRUE - -/* SDIO attributes.*/ -#define STM32_HAS_SDIO FALSE - -/* SPI attributes.*/ -#define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) -#define STM32_SPI1_RX_DMA_CHN 0x00000000 -#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) -#define STM32_SPI1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI2 FALSE -#define STM32_HAS_SPI3 FALSE -#define STM32_HAS_SPI4 FALSE -#define STM32_HAS_SPI5 FALSE -#define STM32_HAS_SPI6 FALSE - -/* TIM attributes.*/ -#define STM32_HAS_TIM1 TRUE -#define STM32_HAS_TIM2 TRUE -#define STM32_HAS_TIM3 TRUE -#define STM32_HAS_TIM4 FALSE -#define STM32_HAS_TIM5 FALSE -#define STM32_HAS_TIM6 FALSE -#define STM32_HAS_TIM7 FALSE -#define STM32_HAS_TIM8 FALSE -#define STM32_HAS_TIM9 FALSE -#define STM32_HAS_TIM10 FALSE -#define STM32_HAS_TIM11 FALSE -#define STM32_HAS_TIM12 FALSE -#define STM32_HAS_TIM13 FALSE -#define STM32_HAS_TIM14 TRUE -#define STM32_HAS_TIM15 FALSE -#define STM32_HAS_TIM16 TRUE -#define STM32_HAS_TIM17 TRUE -#define STM32_HAS_TIM18 FALSE -#define STM32_HAS_TIM19 FALSE - -/* USART attributes.*/ -#define STM32_HAS_USART1 TRUE -#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) | \ - STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_USART1_RX_DMA_CHN 0x00000000 -#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) | \ - STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_USART1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART2 FALSE -#define STM32_HAS_USART3 FALSE -#define STM32_HAS_UART4 FALSE -#define STM32_HAS_UART5 FALSE -#define STM32_HAS_USART6 FALSE - -/* USB attributes.*/ -#define STM32_HAS_USB FALSE -#define STM32_HAS_OTG1 FALSE -#define STM32_HAS_OTG2 FALSE - -#else /* STM32F030 */ - -/* ADC attributes.*/ -#define STM32_HAS_ADC1 TRUE -#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) | \ - STM32_DMA_STREAM_ID_MSK(1, 2)) -#define STM32_ADC1_DMA_CHN 0x00000000 - -#define STM32_HAS_ADC2 FALSE -#define STM32_HAS_ADC3 FALSE -#define STM32_HAS_ADC4 FALSE - -/* CAN attributes.*/ -#define STM32_HAS_CAN1 FALSE -#define STM32_HAS_CAN2 FALSE -#define STM32_CAN_MAX_FILTERS 0 - -/* DAC attributes.*/ -#define STM32_HAS_DAC FALSE - -/* DMA attributes.*/ -#define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 FALSE -#define STM32_DMA_STREAMS 5 - -/* ETH attributes.*/ -#define STM32_HAS_ETH FALSE - -/* EXTI attributes.*/ -#define STM32_EXTI_NUM_CHANNELS 28 - -/* GPIO attributes.*/ -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE FALSE -#define STM32_HAS_GPIOF TRUE -#define STM32_HAS_GPIOG FALSE -#define STM32_HAS_GPIOH FALSE -#define STM32_HAS_GPIOI FALSE - -/* I2C attributes.*/ -#define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) -#define STM32_I2C1_RX_DMA_CHN 0x00000000 -#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) -#define STM32_I2C1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_I2C2 TRUE -#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_I2C2_RX_DMA_CHN 0x00000000 -#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_I2C2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_I2C3 FALSE - -/* RTC attributes.*/ -#define STM32_HAS_RTC TRUE -#define STM32_RTC_HAS_SUBSECONDS FALSE -#define STM32_RTC_IS_CALENDAR TRUE - -/* SDIO attributes.*/ -#define STM32_HAS_SDIO FALSE - -/* SPI attributes.*/ -#define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) -#define STM32_SPI1_RX_DMA_CHN 0x00000000 -#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) -#define STM32_SPI1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI2 TRUE -#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) -#define STM32_SPI2_RX_DMA_CHN 0x00000000 -#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) -#define STM32_SPI2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI3 FALSE -#define STM32_HAS_SPI4 FALSE -#define STM32_HAS_SPI5 FALSE -#define STM32_HAS_SPI6 FALSE - -/* TIM attributes.*/ -#define STM32_HAS_TIM1 TRUE -#define STM32_HAS_TIM2 FALSE -#define STM32_HAS_TIM3 TRUE -#define STM32_HAS_TIM4 FALSE -#define STM32_HAS_TIM5 FALSE -#define STM32_HAS_TIM6 TRUE -#define STM32_HAS_TIM7 FALSE -#define STM32_HAS_TIM8 FALSE -#define STM32_HAS_TIM9 FALSE -#define STM32_HAS_TIM10 FALSE -#define STM32_HAS_TIM11 FALSE -#define STM32_HAS_TIM12 FALSE -#define STM32_HAS_TIM13 FALSE -#define STM32_HAS_TIM14 TRUE -#define STM32_HAS_TIM15 TRUE -#define STM32_HAS_TIM16 TRUE -#define STM32_HAS_TIM17 TRUE -#define STM32_HAS_TIM18 FALSE -#define STM32_HAS_TIM19 FALSE - -/* USART attributes.*/ -#define STM32_HAS_USART1 TRUE -#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) | \ - STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_USART1_RX_DMA_CHN 0x00000000 -#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) | \ - STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_USART1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART2 TRUE -#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_USART2_RX_DMA_CHN 0x00000000 -#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_USART2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART3 FALSE -#define STM32_HAS_UART4 FALSE -#define STM32_HAS_UART5 FALSE -#define STM32_HAS_USART6 FALSE - -/* USB attributes.*/ -#define STM32_HAS_USB FALSE -#define STM32_HAS_OTG1 FALSE -#define STM32_HAS_OTG2 FALSE - -#endif /* STM32F030 */ - -/** @} */ - -#endif /* _STM32_REGISTRY_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32F0xx/stm32f0xx.h b/firmware/chibios/os/hal/platforms/STM32F0xx/stm32f0xx.h deleted file mode 100644 index 744cb319ca..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F0xx/stm32f0xx.h +++ /dev/null @@ -1,3295 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx.h - * @author MCD Application Team - * @version V1.2.1 - * @date 22-November-2013 - * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. - * This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for STM32F0xx devices. - * - * The file is the unique include file that the application programmer - * is using in the C source code, usually in main.c. This file contains: - * - Configuration section that allows to select: - * - The device used in the target application - * - To use or not the peripheral’s drivers in application code(i.e. - * code will be based on direct access to peripheral’s registers - * rather than drivers API), this option is controlled by - * "#define USE_STDPERIPH_DRIVER" - * - To change few application-specific parameters such as the HSE - * crystal frequency - * - Data structures and the address mapping for all peripherals - * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f0xx - * @{ - */ - -#ifndef __STM32F0XX_H -#define __STM32F0XX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup Library_configuration_section - * @{ - */ - -/* Uncomment the line below according to the target STM32F0 device used in your - application - */ - -#if !defined (STM32F0XX_LD) && !defined (STM32F0XX_MD) && !defined (STM32F030) - /* #define STM32F0XX_LD */ /*!< STM32F0xx Low-density devices are STM32F050xx and STM32F060xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes */ - /* #define STM32F0XX_MD */ /*!< STM32F0xx Medium-density devices are STM32F051xx and STM32F061xx microcontrollers where the Flash memory ranges between 16 and 64 Kbytes */ - #define STM32F030 /*!< STM32F030 devices are STM32F030xx value line microcontrollers */ -#endif -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - */ - -/* Old STM32F0XX definition, maintained for legacy purpose */ -#if defined(STM32F0XX) - #define STM32F0XX_MD -#endif /* STM32F0XX */ - -/* Old STM32F030X6/X8 definition, maintained for legacy purpose */ -#if defined (STM32F030X8) || defined (STM32F030X6) - #define STM32F030 -#endif /* STM32F030X8 or STM32F030X6 */ - -#if !defined (STM32F0XX_LD) && !defined (STM32F0XX_MD) && !defined (STM32F030) - #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)" -#endif - -#if !defined USE_STDPERIPH_DRIVER -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - /*#define USE_STDPERIPH_DRIVER*/ -#endif /* USE_STDPERIPH_DRIVER */ - -/** - * @brief In the following line adjust the value of External High Speed oscillator (HSE) - used in your application - - Tip: To avoid modifying this file each time you need to use different HSE, you - can define the HSE value in your toolchain compiler preprocessor. - */ -#if !defined (HSE_VALUE) -#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/ -#endif /* HSE_VALUE */ - -/** - * @brief In the following line adjust the External High Speed oscillator (HSE) Startup - Timeout value - */ -#if !defined (HSE_STARTUP_TIMEOUT) -#define HSE_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSE start up */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup - Timeout value - */ -#if !defined (HSI_STARTUP_TIMEOUT) -#define HSI_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSI start up */ -#endif /* HSI_STARTUP_TIMEOUT */ - -#if !defined (HSI_VALUE) -#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal High Speed oscillator in Hz. - The real value may vary depending on the variations - in voltage and temperature. */ -#endif /* HSI_VALUE */ - -#if !defined (HSI14_VALUE) -#define HSI14_VALUE ((uint32_t)14000000) /*!< Value of the Internal High Speed oscillator for ADC in Hz. - The real value may vary depending on the variations - in voltage and temperature. */ -#endif /* HSI14_VALUE */ - -#if !defined (LSI_VALUE) -#define LSI_VALUE ((uint32_t)40000) /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ -#endif /* LSI_VALUE */ - -#if !defined (LSE_VALUE) -#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -/** - * @brief STM32F0xx Standard Peripheral Library version number V1.2.1 - */ -#define __STM32F0XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32F0XX_STDPERIPH_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ -#define __STM32F0XX_STDPERIPH_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ -#define __STM32F0XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32F0XX_STDPERIPH_VERSION ((__STM32F0XX_STDPERIPH_VERSION_MAIN << 24)\ - |(__STM32F0XX_STDPERIPH_VERSION_SUB1 << 16)\ - |(__STM32F0XX_STDPERIPH_VERSION_SUB2 << 8)\ - |(__STM32F0XX_STDPERIPH_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ - -/** - * @brief STM32F0xx Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ -#define __CM0_REV 0 /*!< Core Revision r0p0 */ -#define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */ -#define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/*!< Interrupt Number Definition */ -typedef enum IRQn -{ -/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ -#if defined (STM32F0XX_MD) -/****** STM32F0XX_MD specific Interrupt Numbers ****************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ - RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ - FLASH_IRQn = 3, /*!< FLASH Interrupt */ - RCC_IRQn = 4, /*!< RCC Interrupt */ - EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ - EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ - EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ - TS_IRQn = 8, /*!< Touch sense controller Interrupt */ - DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ - DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ - DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */ - ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */ - TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ - TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 15, /*!< TIM2 Interrupt */ - TIM3_IRQn = 16, /*!< TIM3 Interrupt */ - TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */ - TIM14_IRQn = 19, /*!< TIM14 Interrupt */ - TIM15_IRQn = 20, /*!< TIM15 Interrupt */ - TIM16_IRQn = 21, /*!< TIM16 Interrupt */ - TIM17_IRQn = 22, /*!< TIM17 Interrupt */ - I2C1_IRQn = 23, /*!< I2C1 Interrupt */ - I2C2_IRQn = 24, /*!< I2C2 Interrupt */ - SPI1_IRQn = 25, /*!< SPI1 Interrupt */ - SPI2_IRQn = 26, /*!< SPI2 Interrupt */ - USART1_IRQn = 27, /*!< USART1 Interrupt */ - USART2_IRQn = 28, /*!< USART2 Interrupt */ - CEC_IRQn = 30 /*!< CEC Interrupt */ -#elif defined (STM32F0XX_LD) -/****** STM32F0XX_LD specific Interrupt Numbers *****************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ - RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ - FLASH_IRQn = 3, /*!< FLASH Interrupt */ - RCC_IRQn = 4, /*!< RCC Interrupt */ - EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ - EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ - EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ - DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ - DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ - DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */ - ADC1_IRQn = 12, /*!< ADC1 Interrupt */ - TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ - TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 15, /*!< TIM2 Interrupt */ - TIM3_IRQn = 16, /*!< TIM3 Interrupt */ - TIM14_IRQn = 19, /*!< TIM14 Interrupt */ - TIM16_IRQn = 21, /*!< TIM16 Interrupt */ - TIM17_IRQn = 22, /*!< TIM17 Interrupt */ - I2C1_IRQn = 23, /*!< I2C1 Interrupt */ - SPI1_IRQn = 25, /*!< SPI1 Interrupt */ - USART1_IRQn = 27 /*!< USART1 Interrupt */ -#elif defined (STM32F030) -/****** STM32F030 specific Interrupt Numbers ********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ - FLASH_IRQn = 3, /*!< FLASH Interrupt */ - RCC_IRQn = 4, /*!< RCC Interrupt */ - EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ - EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ - EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ - DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ - DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ - DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */ - ADC1_IRQn = 12, /*!< ADC1 Interrupt */ - TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ - TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ - TIM3_IRQn = 16, /*!< TIM3 Interrupt */ - TIM14_IRQn = 19, /*!< TIM14 Interrupt */ - TIM15_IRQn = 20, /*!< TIM15 Interrupt */ - TIM16_IRQn = 21, /*!< TIM16 Interrupt */ - TIM17_IRQn = 22, /*!< TIM17 Interrupt */ - I2C1_IRQn = 23, /*!< I2C1 Interrupt */ - I2C2_IRQn = 24, /*!< I2C2 Interrupt */ - SPI1_IRQn = 25, /*!< SPI1 Interrupt */ - SPI2_IRQn = 26, /*!< SPI2 Interrupt */ - USART1_IRQn = 27, /*!< USART1 Interrupt */ - USART2_IRQn = 28 /*!< USART2 Interrupt */ -#endif /* STM32F0XX_MD */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm0.h" -/* CHIBIOS FIX */ -/*#include "system_stm32f0xx.h"*/ -#include - -/** @addtogroup Exported_types - * @{ - */ - -typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; - -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ - __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ - __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ - __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */ - __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */ - __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */ - uint32_t RESERVED3; /*!< Reserved, 0x24 */ - __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ - uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ - __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CCR; -} ADC_Common_TypeDef; - -/** - * @brief HDMI-CEC - */ - -typedef struct -{ - __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ - __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ - __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ - __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ - __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ - __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ -}CEC_TypeDef; - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x1C */ -} COMP_TypeDef; - - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - uint8_t RESERVED0; /*!< Reserved, 0x05 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ - uint32_t RESERVED2; /*!< Reserved, 0x0C */ - __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ -} CRC_TypeDef; - - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - uint32_t RESERVED[6]; /*!< Reserved, 0x14 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - uint32_t RESERVED1; /*!< Reserved, 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -} DMA_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!CR1 = 0; - ADC1->CR2 = ADC_CR2_ADON; - - /* Reset calibration just to be safe.*/ - ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_RSTCAL; - while ((ADC1->CR2 & ADC_CR2_RSTCAL) != 0) - ; - - /* Calibration.*/ - ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_CAL; - while ((ADC1->CR2 & ADC_CR2_CAL) != 0) - ; - - /* Return the ADC in low power mode.*/ - ADC1->CR2 = 0; - rccDisableADC1(FALSE); -#endif -} - -/** - * @brief Configures and activates the ADC peripheral. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_start(ADCDriver *adcp) { - - /* If in stopped state then enables the ADC and DMA clocks.*/ - if (adcp->state == ADC_STOP) { -#if STM32_ADC_USE_ADC1 - if (&ADCD1 == adcp) { - bool_t b; - b = dmaStreamAllocate(adcp->dmastp, - STM32_ADC_ADC1_IRQ_PRIORITY, - (stm32_dmaisr_t)adc_lld_serve_rx_interrupt, - (void *)adcp); - chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated"); - dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR); - rccEnableADC1(FALSE); - } -#endif - - /* ADC setup, the calibration procedure has already been performed - during initialization.*/ - adcp->adc->CR1 = 0; - adcp->adc->CR2 = 0; - } -} - -/** - * @brief Deactivates the ADC peripheral. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_stop(ADCDriver *adcp) { - - /* If in ready state then disables the ADC clock.*/ - if (adcp->state == ADC_READY) { -#if STM32_ADC_USE_ADC1 - if (&ADCD1 == adcp) { - ADC1->CR1 = 0; - ADC1->CR2 = 0; - dmaStreamRelease(adcp->dmastp); - rccDisableADC1(FALSE); - } -#endif - } -} - -/** - * @brief Starts an ADC conversion. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_start_conversion(ADCDriver *adcp) { - uint32_t mode, cr2; - const ADCConversionGroup *grpp = adcp->grpp; - - /* DMA setup.*/ - mode = adcp->dmamode; - if (grpp->circular) { - mode |= STM32_DMA_CR_CIRC; - if (adcp->depth > 1) { - /* If circular buffer depth > 1, then the half transfer interrupt - is enabled in order to allow streaming processing.*/ - mode |= STM32_DMA_CR_HTIE; - } - } - dmaStreamSetMemory0(adcp->dmastp, adcp->samples); - dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels * - (uint32_t)adcp->depth); - dmaStreamSetMode(adcp->dmastp, mode); - dmaStreamEnable(adcp->dmastp); - - /* ADC setup.*/ - adcp->adc->CR1 = grpp->cr1 | ADC_CR1_SCAN; - cr2 = grpp->cr2 | ADC_CR2_DMA | ADC_CR2_ADON; - if ((cr2 & (ADC_CR2_EXTTRIG | ADC_CR2_JEXTTRIG)) == 0) - cr2 |= ADC_CR2_CONT; - adcp->adc->CR2 = grpp->cr2 | cr2; - adcp->adc->SMPR1 = grpp->smpr1; - adcp->adc->SMPR2 = grpp->smpr2; - adcp->adc->SQR1 = grpp->sqr1; - adcp->adc->SQR2 = grpp->sqr2; - adcp->adc->SQR3 = grpp->sqr3; - - /* ADC start by writing ADC_CR2_ADON a second time.*/ - adcp->adc->CR2 = cr2; -} - -/** - * @brief Stops an ongoing conversion. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_stop_conversion(ADCDriver *adcp) { - - dmaStreamDisable(adcp->dmastp); - adcp->adc->CR2 = 0; -} - -#endif /* HAL_USE_ADC */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32F1xx/adc_lld.h b/firmware/chibios/os/hal/platforms/STM32F1xx/adc_lld.h deleted file mode 100644 index 0c6b68919f..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F1xx/adc_lld.h +++ /dev/null @@ -1,393 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F1xx/adc_lld.h - * @brief STM32F1xx ADC subsystem low level driver header. - * - * @addtogroup ADC - * @{ - */ - -#ifndef _ADC_LLD_H_ -#define _ADC_LLD_H_ - -#if HAL_USE_ADC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name Triggers selection - * @{ - */ -#define ADC_CR2_EXTSEL_SRC(n) ((n) << 17) /**< @brief Trigger source. */ -#define ADC_CR2_EXTSEL_SWSTART (7 << 17) /**< @brief Software trigger. */ -/** @} */ - -/** - * @name Available analog channels - * @{ - */ -#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */ -#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */ -#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */ -#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */ -#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */ -#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */ -#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */ -#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */ -#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */ -#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */ -#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */ -#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */ -#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */ -#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */ -#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */ -#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */ -#define ADC_CHANNEL_SENSOR 16 /**< @brief Internal temperature sensor.*/ -#define ADC_CHANNEL_VREFINT 17 /**< @brief Internal reference. */ -/** @} */ - -/** - * @name Sampling rates - * @{ - */ -#define ADC_SAMPLE_1P5 0 /**< @brief 1.5 cycles sampling time. */ -#define ADC_SAMPLE_7P5 1 /**< @brief 7.5 cycles sampling time. */ -#define ADC_SAMPLE_13P5 2 /**< @brief 13.5 cycles sampling time. */ -#define ADC_SAMPLE_28P5 3 /**< @brief 28.5 cycles sampling time. */ -#define ADC_SAMPLE_41P5 4 /**< @brief 41.5 cycles sampling time. */ -#define ADC_SAMPLE_55P5 5 /**< @brief 55.5 cycles sampling time. */ -#define ADC_SAMPLE_71P5 6 /**< @brief 71.5 cycles sampling time. */ -#define ADC_SAMPLE_239P5 7 /**< @brief 239.5 cycles sampling time. */ -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief ADC1 driver enable switch. - * @details If set to @p TRUE the support for ADC1 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__) -#define STM32_ADC_USE_ADC1 FALSE -#endif - -/** - * @brief ADC1 DMA priority (0..3|lowest..highest). - */ -#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#endif - -/** - * @brief ADC1 interrupt priority level setting. - */ -#if !defined(STM32_ADC_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_ADC1_IRQ_PRIORITY 5 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1 -#error "ADC1 not present in the selected device" -#endif - -#if !STM32_ADC_USE_ADC1 -#error "ADC driver activated but no ADC peripheral assigned" -#endif - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief ADC sample data type. - */ -typedef uint16_t adcsample_t; - -/** - * @brief Channels number in a conversion group. - */ -typedef uint16_t adc_channels_num_t; - -/** - * @brief Possible ADC failure causes. - * @note Error codes are architecture dependent and should not relied - * upon. - */ -typedef enum { - ADC_ERR_DMAFAILURE = 0 /**< DMA operations failure. */ -} adcerror_t; - -/** - * @brief Type of a structure representing an ADC driver. - */ -typedef struct ADCDriver ADCDriver; - -/** - * @brief ADC notification callback type. - * - * @param[in] adcp pointer to the @p ADCDriver object triggering the - * callback - * @param[in] buffer pointer to the most recent samples data - * @param[in] n number of buffer rows available starting from @p buffer - */ -typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n); - -/** - * @brief ADC error callback type. - * - * @param[in] adcp pointer to the @p ADCDriver object triggering the - * callback - * @param[in] err ADC error code - */ -typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err); - -/** - * @brief Conversion group configuration structure. - * @details This implementation-dependent structure describes a conversion - * operation. - * @note The use of this configuration structure requires knowledge of - * STM32 ADC cell registers interface, please refer to the STM32 - * reference manual for details. - */ -typedef struct { - /** - * @brief Enables the circular buffer mode for the group. - */ - bool_t circular; - /** - * @brief Number of the analog channels belonging to the conversion group. - */ - adc_channels_num_t num_channels; - /** - * @brief Callback function associated to the group or @p NULL. - */ - adccallback_t end_cb; - /** - * @brief Error callback or @p NULL. - */ - adcerrorcallback_t error_cb; - /* End of the mandatory fields.*/ - /** - * @brief ADC CR1 register initialization data. - * @note All the required bits must be defined into this field except - * @p ADC_CR1_SCAN that is enforced inside the driver. - */ - uint32_t cr1; - /** - * @brief ADC CR2 register initialization data. - * @note All the required bits must be defined into this field except - * @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are - * enforced inside the driver. - */ - uint32_t cr2; - /** - * @brief ADC SMPR1 register initialization data. - * @details In this field must be specified the sample times for channels - * 10...17. - */ - uint32_t smpr1; - /** - * @brief ADC SMPR2 register initialization data. - * @details In this field must be specified the sample times for channels - * 0...9. - */ - uint32_t smpr2; - /** - * @brief ADC SQR1 register initialization data. - * @details Conversion group sequence 13...16 + sequence length. - */ - uint32_t sqr1; - /** - * @brief ADC SQR2 register initialization data. - * @details Conversion group sequence 7...12. - */ - uint32_t sqr2; - /** - * @brief ADC SQR3 register initialization data. - * @details Conversion group sequence 1...6. - */ - uint32_t sqr3; -} ADCConversionGroup; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - uint32_t dummy; -} ADCConfig; - -/** - * @brief Structure representing an ADC driver. - */ -struct ADCDriver { - /** - * @brief Driver state. - */ - adcstate_t state; - /** - * @brief Current configuration data. - */ - const ADCConfig *config; - /** - * @brief Current samples buffer pointer or @p NULL. - */ - adcsample_t *samples; - /** - * @brief Current samples buffer depth or @p 0. - */ - size_t depth; - /** - * @brief Current conversion group pointer or @p NULL. - */ - const ADCConversionGroup *grpp; -#if ADC_USE_WAIT || defined(__DOXYGEN__) - /** - * @brief Waiting thread. - */ - Thread *thread; -#endif -#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) -#if CH_USE_MUTEXES || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the peripheral. - */ - Mutex mutex; -#elif CH_USE_SEMAPHORES - Semaphore semaphore; -#endif -#endif /* ADC_USE_MUTUAL_EXCLUSION */ -#if defined(ADC_DRIVER_EXT_FIELDS) - ADC_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the ADCx registers block. - */ - ADC_TypeDef *adc; - /** - * @brief Pointer to associated DMA channel. - */ - const stm32_dma_stream_t *dmastp; - /** - * @brief DMA mode bit mask. - */ - uint32_t dmamode; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Sequences building helper macros - * @{ - */ -/** - * @brief Number of channels in a conversion sequence. - */ -#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 20) - -#define ADC_SQR3_SQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */ -#define ADC_SQR3_SQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */ -#define ADC_SQR3_SQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */ -#define ADC_SQR3_SQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */ -#define ADC_SQR3_SQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */ -#define ADC_SQR3_SQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */ - -#define ADC_SQR2_SQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */ -#define ADC_SQR2_SQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */ -#define ADC_SQR2_SQ9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */ -#define ADC_SQR2_SQ10_N(n) ((n) << 15) /**< @brief 10th channel in seq.*/ -#define ADC_SQR2_SQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/ -#define ADC_SQR2_SQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/ - -#define ADC_SQR1_SQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/ -#define ADC_SQR1_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/ -#define ADC_SQR1_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/ -#define ADC_SQR1_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/ -/** @} */ - -/** - * @name Sampling rate settings helper macros - * @{ - */ -#define ADC_SMPR2_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */ -#define ADC_SMPR2_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */ -#define ADC_SMPR2_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */ -#define ADC_SMPR2_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */ -#define ADC_SMPR2_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */ -#define ADC_SMPR2_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */ -#define ADC_SMPR2_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */ -#define ADC_SMPR2_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */ -#define ADC_SMPR2_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */ -#define ADC_SMPR2_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */ - -#define ADC_SMPR1_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */ -#define ADC_SMPR1_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */ -#define ADC_SMPR1_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */ -#define ADC_SMPR1_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */ -#define ADC_SMPR1_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */ -#define ADC_SMPR1_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */ -#define ADC_SMPR1_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor - sampling time. */ -#define ADC_SMPR1_SMP_VREF(n) ((n) << 21) /**< @brief Voltage Reference - sampling time. */ -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__) -extern ADCDriver ADCD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void adc_lld_init(void); - void adc_lld_start(ADCDriver *adcp); - void adc_lld_stop(ADCDriver *adcp); - void adc_lld_start_conversion(ADCDriver *adcp); - void adc_lld_stop_conversion(ADCDriver *adcp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_ADC */ - -#endif /* _ADC_LLD_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32F1xx/ext_lld_isr.c b/firmware/chibios/os/hal/platforms/STM32F1xx/ext_lld_isr.c deleted file mode 100644 index 8d9afb3cca..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F1xx/ext_lld_isr.c +++ /dev/null @@ -1,338 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F1xx/ext_lld_isr.c - * @brief STM32F1xx EXT subsystem low level driver ISR code. - * - * @addtogroup EXT - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -#include "ext_lld_isr.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief EXTI[0] interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(EXTI0_IRQHandler) { - - CH_IRQ_PROLOGUE(); - - EXTI->PR = (1 << 0); - EXTD1.config->channels[0].cb(&EXTD1, 0); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[1] interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(EXTI1_IRQHandler) { - - CH_IRQ_PROLOGUE(); - - EXTI->PR = (1 << 1); - EXTD1.config->channels[1].cb(&EXTD1, 1); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[2] interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(EXTI2_IRQHandler) { - - CH_IRQ_PROLOGUE(); - - EXTI->PR = (1 << 2); - EXTD1.config->channels[2].cb(&EXTD1, 2); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[3] interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(EXTI3_IRQHandler) { - - CH_IRQ_PROLOGUE(); - - EXTI->PR = (1 << 3); - EXTD1.config->channels[3].cb(&EXTD1, 3); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[4] interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(EXTI4_IRQHandler) { - - CH_IRQ_PROLOGUE(); - - EXTI->PR = (1 << 4); - EXTD1.config->channels[4].cb(&EXTD1, 4); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[5]...EXTI[9] interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(EXTI9_5_IRQHandler) { - uint32_t pr; - - CH_IRQ_PROLOGUE(); - - pr = EXTI->PR & ((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9)); - EXTI->PR = pr; - if (pr & (1 << 5)) - EXTD1.config->channels[5].cb(&EXTD1, 5); - if (pr & (1 << 6)) - EXTD1.config->channels[6].cb(&EXTD1, 6); - if (pr & (1 << 7)) - EXTD1.config->channels[7].cb(&EXTD1, 7); - if (pr & (1 << 8)) - EXTD1.config->channels[8].cb(&EXTD1, 8); - if (pr & (1 << 9)) - EXTD1.config->channels[9].cb(&EXTD1, 9); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[10]...EXTI[15] interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(EXTI15_10_IRQHandler) { - uint32_t pr; - - CH_IRQ_PROLOGUE(); - - pr = EXTI->PR & ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) | - (1 << 15)); - EXTI->PR = pr; - if (pr & (1 << 10)) - EXTD1.config->channels[10].cb(&EXTD1, 10); - if (pr & (1 << 11)) - EXTD1.config->channels[11].cb(&EXTD1, 11); - if (pr & (1 << 12)) - EXTD1.config->channels[12].cb(&EXTD1, 12); - if (pr & (1 << 13)) - EXTD1.config->channels[13].cb(&EXTD1, 13); - if (pr & (1 << 14)) - EXTD1.config->channels[14].cb(&EXTD1, 14); - if (pr & (1 << 15)) - EXTD1.config->channels[15].cb(&EXTD1, 15); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[16] interrupt handler (PVD). - * - * @isr - */ -CH_IRQ_HANDLER(PVD_IRQHandler) { - - CH_IRQ_PROLOGUE(); - - EXTI->PR = (1 << 16); - EXTD1.config->channels[16].cb(&EXTD1, 16); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[17] interrupt handler (RTC). - * - * @isr - */ -CH_IRQ_HANDLER(RTC_Alarm_IRQHandler) { - - CH_IRQ_PROLOGUE(); - - EXTI->PR = (1 << 17); - EXTD1.config->channels[17].cb(&EXTD1, 17); - - CH_IRQ_EPILOGUE(); -} - -#if defined(STM32F10X_CL) -/** - * @brief EXTI[18] interrupt handler (OTG_FS_WKUP). - * - * @isr - */ -CH_IRQ_HANDLER(OTG_FS_WKUP_IRQHandler) { - - CH_IRQ_PROLOGUE(); - - EXTI->PR = (1 << 18); - EXTD1.config->channels[18].cb(&EXTD1, 18); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[19] interrupt handler (ETH_WKUP). - * - * @isr - */ -CH_IRQ_HANDLER(ETH_WKUP_IRQHandler) { - - CH_IRQ_PROLOGUE(); - - EXTI->PR = (1 << 19); - EXTD1.config->channels[19].cb(&EXTD1, 19); - - CH_IRQ_EPILOGUE(); -} -#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \ - defined(STM32F10X_HD_VL) - -#else /* Other STM32F1xx devices.*/ -/** - * @brief EXTI[18] interrupt handler (USB_FS_WKUP). - * - * @isr - */ -CH_IRQ_HANDLER(USB_FS_WKUP_IRQHandler) { - - CH_IRQ_PROLOGUE(); - - EXTI->PR = (1 << 18); - EXTD1.config->channels[18].cb(&EXTD1, 18); - - CH_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Enables EXTI IRQ sources. - * - * @notapi - */ -void ext_lld_exti_irq_enable(void) { - - nvicEnableVector(EXTI0_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI0_IRQ_PRIORITY)); - nvicEnableVector(EXTI1_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI1_IRQ_PRIORITY)); - nvicEnableVector(EXTI2_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI2_IRQ_PRIORITY)); - nvicEnableVector(EXTI3_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI3_IRQ_PRIORITY)); - nvicEnableVector(EXTI4_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_IRQ_PRIORITY)); - nvicEnableVector(EXTI9_5_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI5_9_IRQ_PRIORITY)); - nvicEnableVector(EXTI15_10_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI10_15_IRQ_PRIORITY)); - nvicEnableVector(PVD_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY)); - nvicEnableVector(RTC_Alarm_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY)); -#if defined(STM32F10X_CL) - /* EXTI vectors specific to STM32F1xx Connectivity Line.*/ - nvicEnableVector(OTG_FS_WKUP_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY)); - nvicEnableVector(ETH_WKUP_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY)); -#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \ - defined(STM32F10X_HD_VL) - /* EXTI vectors specific to STM32F1xx Value Line.*/ -#else - /* EXTI vectors specific to STM32F1xx except Connectivity Line.*/ - nvicEnableVector(USB_FS_WKUP_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY)); -#endif -} - -/** - * @brief Disables EXTI IRQ sources. - * - * @notapi - */ -void ext_lld_exti_irq_disable(void) { - - nvicDisableVector(EXTI0_IRQn); - nvicDisableVector(EXTI1_IRQn); - nvicDisableVector(EXTI2_IRQn); - nvicDisableVector(EXTI3_IRQn); - nvicDisableVector(EXTI4_IRQn); - nvicDisableVector(EXTI9_5_IRQn); - nvicDisableVector(EXTI15_10_IRQn); - nvicDisableVector(PVD_IRQn); - nvicDisableVector(RTC_Alarm_IRQn); -#if defined(STM32F10X_CL) - /* EXTI vectors specific to STM32F1xx Connectivity Line.*/ - nvicDisableVector(OTG_FS_WKUP_IRQn); - nvicDisableVector(ETH_WKUP_IRQn); -#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \ - defined(STM32F10X_HD_VL) - /* EXTI vectors specific to STM32F1xx Value Line.*/ -#else - /* EXTI vectors specific to STM32F1xx except Connectivity Line.*/ - nvicDisableVector(USB_FS_WKUP_IRQn); -#endif -} - -#endif /* HAL_USE_EXT */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32F1xx/ext_lld_isr.h b/firmware/chibios/os/hal/platforms/STM32F1xx/ext_lld_isr.h deleted file mode 100644 index 9bc30d7c06..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F1xx/ext_lld_isr.h +++ /dev/null @@ -1,149 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F1xx/ext_lld_isr.h - * @brief STM32F1xx EXT subsystem low level driver ISR header. - * - * @addtogroup EXT - * @{ - */ - -#ifndef _EXT_LLD_ISR_H_ -#define _EXT_LLD_ISR_H_ - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief EXTI0 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI1 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI2 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI3 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI4 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI9..5 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI5_9_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI15..10 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI10_15_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI16 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI17 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI18 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI18_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI19 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI19_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void ext_lld_exti_irq_enable(void); - void ext_lld_exti_irq_disable(void); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_EXT */ - -#endif /* _EXT_LLD_ISR_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32F1xx/hal_lld.c b/firmware/chibios/os/hal/platforms/STM32F1xx/hal_lld.c deleted file mode 100644 index 414b282332..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F1xx/hal_lld.c +++ /dev/null @@ -1,310 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F1xx/hal_lld.c - * @brief STM32F1xx HAL subsystem low level driver source. - * - * @addtogroup HAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Initializes the backup domain. - * @note WARNING! Changing clock source impossible without resetting - * of the whole BKP domain. - */ -static void hal_lld_backup_domain_init(void) { - - /* Backup domain access enabled and left open.*/ - PWR->CR |= PWR_CR_DBP; - -#if HAL_USE_RTC - /* Reset BKP domain if different clock source selected.*/ - if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL){ - /* Backup domain reset.*/ - RCC->BDCR = RCC_BDCR_BDRST; - RCC->BDCR = 0; - } - - /* If enabled then the LSE is started.*/ -#if STM32_LSE_ENABLED - RCC->BDCR |= RCC_BDCR_LSEON; - while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) - ; /* Waits until LSE is stable. */ -#endif /* STM32_LSE_ENABLED */ - -#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK - /* If the backup domain hasn't been initialized yet then proceed with - initialization.*/ - if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) { - /* Selects clock source.*/ - RCC->BDCR |= STM32_RTCSEL; - - /* Prescaler value loaded in registers.*/ - rtc_lld_set_prescaler(); - - /* RTC clock enabled.*/ - RCC->BDCR |= RCC_BDCR_RTCEN; - } -#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */ -#endif /* HAL_USE_RTC */ -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level HAL driver initialization. - * - * @notapi - */ -void hal_lld_init(void) { - - /* Reset of all peripherals.*/ - rccResetAPB1(0xFFFFFFFF); - rccResetAPB2(0xFFFFFFFF); - - /* SysTick initialization using the system clock.*/ - SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1; - SysTick->VAL = 0; - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk | - SysTick_CTRL_TICKINT_Msk; - - /* DWT cycle counter enable.*/ - SCS_DEMCR |= SCS_DEMCR_TRCENA; - DWT_CTRL |= DWT_CTRL_CYCCNTENA; - - /* PWR and BD clocks enabled.*/ - rccEnablePWRInterface(FALSE); - rccEnableBKPInterface(FALSE); - - /* Initializes the backup domain.*/ - hal_lld_backup_domain_init(); - -#if defined(STM32_DMA_REQUIRED) - dmaInit(); -#endif - - /* Programmable voltage detector enable.*/ -#if STM32_PVD_ENABLE - PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK); -#endif /* STM32_PVD_ENABLE */ -} - -/** - * @brief STM32 clocks and PLL initialization. - * @note All the involved constants come from the file @p board.h. - * @note This function should be invoked just after the system reset. - * - * @special - */ -#if defined(STM32F10X_LD) || defined(STM32F10X_LD_VL) || \ - defined(STM32F10X_MD) || defined(STM32F10X_MD_VL) || \ - defined(STM32F10X_HD) || defined(STM32F10X_XL) || \ - defined(__DOXYGEN__) -/* - * Clocks initialization for all sub-families except CL. - */ -void stm32_clock_init(void) { - -#if !STM32_NO_INIT - /* HSI setup, it enforces the reset situation in order to handle possible - problems with JTAG probes and re-initializations.*/ - RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */ - while (!(RCC->CR & RCC_CR_HSIRDY)) - ; /* Wait until HSI is stable. */ - - /* HSI is selected as new source without touching the other fields in - CFGR. Clearing the register has to be postponed after HSI is the - new source.*/ - RCC->CFGR &= ~RCC_CFGR_SW; /* Reset SW */ - RCC->CFGR |= RCC_CFGR_SWS_HSI; /* Select HSI as internal*/ - while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) - ; /* Wait until HSI is selected. */ - - /* Registers finally cleared to reset values.*/ - RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */ - RCC->CFGR = 0; /* CFGR reset value. */ - -#if STM32_HSE_ENABLED -#if defined(STM32_HSE_BYPASS) - /* HSE Bypass.*/ - RCC->CR |= RCC_CR_HSEBYP; -#endif - /* HSE activation.*/ - RCC->CR |= RCC_CR_HSEON; - while (!(RCC->CR & RCC_CR_HSERDY)) - ; /* Waits until HSE is stable. */ -#endif - -#if STM32_LSI_ENABLED - /* LSI activation.*/ - RCC->CSR |= RCC_CSR_LSION; - while ((RCC->CSR & RCC_CSR_LSIRDY) == 0) - ; /* Waits until LSI is stable. */ -#endif - -#if STM32_ACTIVATE_PLL - /* PLL activation.*/ - RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC; - RCC->CR |= RCC_CR_PLLON; - while (!(RCC->CR & RCC_CR_PLLRDY)) - ; /* Waits until PLL is stable. */ -#endif - - /* Clock settings.*/ -#if STM32_HAS_USB - RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE | - STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | - STM32_HPRE; -#else - RCC->CFGR = STM32_MCOSEL | STM32_PLLMUL | STM32_PLLXTPRE | - STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | - STM32_HPRE; -#endif - - /* Flash setup and final clock selection. */ - FLASH->ACR = STM32_FLASHBITS; - - /* Switching to the configured clock source if it is different from HSI.*/ -#if (STM32_SW != STM32_SW_HSI) - /* Switches clock source.*/ - RCC->CFGR |= STM32_SW; - while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2)) - ; /* Waits selection complete. */ -#endif - -#if !STM32_HSI_ENABLED - RCC->CR &= ~RCC_CR_HSION; -#endif -#endif /* !STM32_NO_INIT */ -} - -#elif defined(STM32F10X_CL) -/* - * Clocks initialization for the CL sub-family. - */ -void stm32_clock_init(void) { - -#if !STM32_NO_INIT - /* HSI setup.*/ - RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */ - while (!(RCC->CR & RCC_CR_HSIRDY)) - ; /* Wait until HSI is stable. */ - RCC->CFGR = 0; - RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */ - while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) - ; /* Wait until HSI is the source.*/ - -#if STM32_HSE_ENABLED -#if defined(STM32_HSE_BYPASS) - /* HSE Bypass.*/ - RCC->CR |= RCC_CR_HSEBYP; -#endif - /* HSE activation.*/ - RCC->CR |= RCC_CR_HSEON; - while (!(RCC->CR & RCC_CR_HSERDY)) - ; /* Waits until HSE is stable. */ -#endif - -#if STM32_LSI_ENABLED - /* LSI activation.*/ - RCC->CSR |= RCC_CSR_LSION; - while ((RCC->CSR & RCC_CSR_LSIRDY) == 0) - ; /* Waits until LSI is stable. */ -#endif - - /* Settings of various dividers and multipliers in CFGR2.*/ - RCC->CFGR2 = STM32_PLL3MUL | STM32_PLL2MUL | STM32_PREDIV2 | - STM32_PREDIV1 | STM32_PREDIV1SRC; - - /* PLL2 setup, if activated.*/ -#if STM32_ACTIVATE_PLL2 - RCC->CR |= RCC_CR_PLL2ON; - while (!(RCC->CR & RCC_CR_PLL2RDY)) - ; /* Waits until PLL2 is stable. */ -#endif - - /* PLL3 setup, if activated.*/ -#if STM32_ACTIVATE_PLL3 - RCC->CR |= RCC_CR_PLL3ON; - while (!(RCC->CR & RCC_CR_PLL3RDY)) - ; /* Waits until PLL3 is stable. */ -#endif - - /* PLL1 setup, if activated.*/ -#if STM32_ACTIVATE_PLL1 - RCC->CFGR |= STM32_PLLMUL | STM32_PLLSRC; - RCC->CR |= RCC_CR_PLLON; - while (!(RCC->CR & RCC_CR_PLLRDY)) - ; /* Waits until PLL1 is stable. */ -#endif - - /* Clock settings.*/ -#if STM32_HAS_OTG1 - RCC->CFGR = STM32_MCOSEL | STM32_OTGFSPRE | STM32_PLLMUL | STM32_PLLSRC | - STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; -#else - RCC->CFGR = STM32_MCO | STM32_PLLMUL | STM32_PLLSRC | - STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; -#endif - - /* Flash setup and final clock selection. */ - FLASH->ACR = STM32_FLASHBITS; /* Flash wait states depending on clock. */ - - /* Switching to the configured clock source if it is different from HSI.*/ -#if (STM32_SW != STM32_SW_HSI) - RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */ - while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2)) - ; -#endif - -#if !STM32_HSI_ENABLED - RCC->CR &= ~RCC_CR_HSION; -#endif -#endif /* !STM32_NO_INIT */ -} -#else -void stm32_clock_init(void) {} -#endif - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32F1xx/hal_lld.h b/firmware/chibios/os/hal/platforms/STM32F1xx/hal_lld.h deleted file mode 100644 index 16b999a7ce..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F1xx/hal_lld.h +++ /dev/null @@ -1,255 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F1xx/hal_lld.h - * @brief STM32F1xx HAL subsystem low level driver header. - * @pre This module requires the following macros to be defined in the - * @p board.h file: - * - STM32_LSECLK. - * - STM32_HSECLK. - * - STM32_HSE_BYPASS (optionally). - * . - * One of the following macros must also be defined: - * - STM32F10X_LD_VL for Value Line Low Density devices. - * - STM32F10X_MD_VL for Value Line Medium Density devices. - * - STM32F10X_LD for Performance Low Density devices. - * - STM32F10X_MD for Performance Medium Density devices. - * - STM32F10X_HD for Performance High Density devices. - * - STM32F10X_XL for Performance eXtra Density devices. - * - STM32F10X_CL for Connectivity Line devices. - * . - * - * @addtogroup HAL - * @{ - */ - -#ifndef _HAL_LLD_H_ -#define _HAL_LLD_H_ - -#include "stm32.h" - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Defines the support for realtime counters in the HAL. - */ -#define HAL_IMPLEMENTS_COUNTERS TRUE - -/** - * @name Internal clock sources - * @{ - */ -#define STM32_HSICLK 8000000 /**< High speed internal clock. */ -#define STM32_LSICLK 40000 /**< Low speed internal clock. */ -/** @} */ - -/** - * @name PWR_CR register bits definitions - * @{ - */ -#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */ -#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */ -#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */ -#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 2. */ -#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 3. */ -#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 4. */ -#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 5. */ -#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 6. */ -#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 7. */ -/** @} */ - -/*===========================================================================*/ -/* Platform capabilities. */ -/*===========================================================================*/ - -/** - * @name STM32F1xx capabilities - * @{ - */ -/* RTC attributes.*/ -#define STM32_HAS_RTC TRUE -#define STM32_RTC_HAS_SUBSECONDS TRUE -#define STM32_RTC_IS_CALENDAR FALSE -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief Disables the PWR/RCC initialization in the HAL. - */ -#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__) -#define STM32_NO_INIT FALSE -#endif - -/** - * @brief Enables or disables the programmable voltage detector. - */ -#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__) -#define STM32_PVD_ENABLE FALSE -#endif - -/** - * @brief Sets voltage level for programmable voltage detector. - */ -#if !defined(STM32_PLS) || defined(__DOXYGEN__) -#define STM32_PLS STM32_PLS_LEV0 -#endif - -/** - * @brief Enables or disables the HSI clock source. - */ -#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__) -#define STM32_HSI_ENABLED TRUE -#endif - -/** - * @brief Enables or disables the LSI clock source. - */ -#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__) -#define STM32_LSI_ENABLED FALSE -#endif - -/** - * @brief Enables or disables the HSE clock source. - */ -#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__) -#define STM32_HSE_ENABLED TRUE -#endif - -/** - * @brief Enables or disables the LSE clock source. - */ -#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__) -#define STM32_LSE_ENABLED FALSE -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if defined(__DOXYGEN__) -/** - * @name Platform identification - * @{ - */ -#define PLATFORM_NAME "STM32" -/** @} */ - -#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \ - defined(STM32F10X_HD_VL) || defined(__DOXYGEN__) -#include "hal_lld_f100.h" - -#elif defined(STM32F10X_LD) || defined(STM32F10X_MD) || \ - defined(STM32F10X_HD) || defined(STM32F10X_XL) || \ - defined(__DOXYGEN__) -#include "hal_lld_f103.h" - -#elif defined(STM32F10X_CL) || defined(__DOXYGEN__) -#include "hal_lld_f105_f107.h" - -#else -#error "unspecified, unsupported or invalid STM32 platform" -#endif - -/* There are differences in vector names in the various sub-families, - normalizing.*/ -#if defined(STM32F10X_XL) -#define TIM1_BRK_IRQn TIM1_BRK_TIM9_IRQn -#define TIM1_UP_IRQn TIM1_UP_TIM10_IRQn -#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM11_IRQn -#define TIM8_BRK_IRQn TIM8_BRK_TIM12_IRQn -#define TIM8_UP_IRQn TIM8_UP_TIM13_IRQn -#define TIM8_TRG_COM_IRQn TIM8_TRG_COM_TIM14_IRQn - -#elif defined(STM32F10X_LD_VL)|| defined(STM32F10X_MD_VL) || \ - defined(STM32F10X_HD_VL) -#define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn -#define TIM1_UP_IRQn TIM1_UP_TIM16_IRQn -#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type representing a system clock frequency. - */ -typedef uint32_t halclock_t; - -/** - * @brief Type of the realtime free counter value. - */ -typedef uint32_t halrtcnt_t; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Returns the current value of the system free running counter. - * @note This service is implemented by returning the content of the - * DWT_CYCCNT register. - * - * @return The value of the system free running counter of - * type halrtcnt_t. - * - * @notapi - */ -#define hal_lld_get_counter_value() DWT_CYCCNT - -/** - * @brief Realtime counter frequency. - * @note The DWT_CYCCNT register is incremented directly by the system - * clock so this function returns STM32_HCLK. - * - * @return The realtime counter frequency of type halclock_t. - * - * @notapi - */ -#define hal_lld_get_counter_frequency() STM32_HCLK - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/* STM32 ISR, DMA and RCC helpers.*/ -#include "stm32_isr.h" -#include "stm32_dma.h" -#include "stm32_rcc.h" - -#ifdef __cplusplus -extern "C" { -#endif - void hal_lld_init(void); - void stm32_clock_init(void); -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_LLD_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32F1xx/hal_lld_f100.h b/firmware/chibios/os/hal/platforms/STM32F1xx/hal_lld_f100.h deleted file mode 100644 index 65be1dfd85..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F1xx/hal_lld_f100.h +++ /dev/null @@ -1,950 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @defgroup STM32F100_HAL STM32F100 HAL Support - * @details HAL support for STM32 Value Line LD, MD and HD sub-families. - * - * @ingroup HAL - */ - -/** - * @file STM32F1xx/hal_lld_f100.h - * @brief STM32F100 Value Line HAL subsystem low level driver header. - * - * @addtogroup STM32F100_HAL - * @{ - */ - -#ifndef _HAL_LLD_F100_H_ -#define _HAL_LLD_F100_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name Platform identification - * @{ - */ -#if defined(__DOXYGEN__) -#define PLATFORM_NAME "STM32F100 Value Line" - -#elif defined(STM32F10X_LD_VL) -#define PLATFORM_NAME "STM32F100 Value Line Low Density" - -#elif defined(STM32F10X_MD_VL) -#define PLATFORM_NAME "STM32F100 Value Line Medium Density" -#else -#error "unsupported STM32 Value Line member" -#endif -/** @} */ - -/** - * @name Absolute Maximum Ratings - * @{ - */ -/** - * @brief Maximum system clock frequency. - */ -#define STM32_SYSCLK_MAX 24000000 - -/** - * @brief Maximum HSE clock frequency. - */ -#define STM32_HSECLK_MAX 24000000 - -/** - * @brief Minimum HSE clock frequency. - */ -#define STM32_HSECLK_MIN 1000000 - -/** - * @brief Maximum LSE clock frequency. - */ -#define STM32_LSECLK_MAX 1000000 - -/** - * @brief Minimum LSE clock frequency. - */ -#define STM32_LSECLK_MIN 32768 - -/** - * @brief Maximum PLLs input clock frequency. - */ -#define STM32_PLLIN_MAX 24000000 - -/** - * @brief Maximum PLLs input clock frequency. - */ -#define STM32_PLLIN_MIN 1000000 - -/** - * @brief Maximum PLL output clock frequency. - */ -#define STM32_PLLOUT_MAX 24000000 - -/** - * @brief Maximum PLL output clock frequency. - */ -#define STM32_PLLOUT_MIN 16000000 - -/** - * @brief Maximum APB1 clock frequency. - */ -#define STM32_PCLK1_MAX 24000000 - -/** - * @brief Maximum APB2 clock frequency. - */ -#define STM32_PCLK2_MAX 24000000 - -/** - * @brief Maximum ADC clock frequency. - */ -#define STM32_ADCCLK_MAX 12000000 -/** @} */ - -/** - * @name RCC_CFGR register bits definitions - * @{ - */ -#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */ -#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */ -#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */ - -#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */ -#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */ -#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */ -#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */ -#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */ -#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */ -#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */ -#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */ -#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */ - -#define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */ -#define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */ -#define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */ -#define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */ -#define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */ - -#define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */ -#define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */ -#define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */ -#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */ -#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */ - -#define STM32_ADCPRE_DIV2 (0 << 14) /**< PPRE2 divided by 2. */ -#define STM32_ADCPRE_DIV4 (1 << 14) /**< PPRE2 divided by 4. */ -#define STM32_ADCPRE_DIV6 (2 << 14) /**< PPRE2 divided by 6. */ -#define STM32_ADCPRE_DIV8 (3 << 14) /**< PPRE2 divided by 8. */ - -#define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */ -#define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */ - -#define STM32_PLLXTPRE_DIV1 (0 << 17) /**< HSE divided by 1. */ -#define STM32_PLLXTPRE_DIV2 (1 << 17) /**< HSE divided by 2. */ - -#define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */ -#define STM32_MCOSEL_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */ -#define STM32_MCOSEL_HSI (5 << 24) /**< HSI clock on MCO pin. */ -#define STM32_MCOSEL_HSE (6 << 24) /**< HSE clock on MCO pin. */ -#define STM32_MCOSEL_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */ -/** @} */ - -/** - * @name RCC_BDCR register bits definitions - * @{ - */ -#define STM32_RTCSEL_MASK (3 << 8) /**< RTC clock source mask. */ -#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No clock. */ -#define STM32_RTCSEL_LSE (1 << 8) /**< LSE used as RTC clock. */ -#define STM32_RTCSEL_LSI (2 << 8) /**< LSI used as RTC clock. */ -#define STM32_RTCSEL_HSEDIV (3 << 8) /**< HSE divided by 128 used as - RTC clock. */ -/** @} */ - -/*===========================================================================*/ -/* Platform capabilities. */ -/*===========================================================================*/ - -#if defined(STM32F10X_LD_VL) || defined(__DOXYGEN__) -/** - * @name STM32F100 LD capabilities - * @{ - */ -/* ADC attributes.*/ -#define STM32_HAS_ADC1 TRUE -#define STM32_HAS_ADC2 FALSE -#define STM32_HAS_ADC3 FALSE - -/* CAN attributes.*/ -#define STM32_HAS_CAN1 FALSE -#define STM32_HAS_CAN2 FALSE -#define STM32_CAN_MAX_FILTERS 0 - -/* DAC attributes.*/ -#define STM32_HAS_DAC TRUE - -/* DMA attributes.*/ -#define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 FALSE - -/* ETH attributes.*/ -#define STM32_HAS_ETH FALSE - -/* EXTI attributes.*/ -#define STM32_EXTI_NUM_CHANNELS 18 - -/* GPIO attributes.*/ -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE FALSE -#define STM32_HAS_GPIOF FALSE -#define STM32_HAS_GPIOG FALSE -#define STM32_HAS_GPIOH FALSE -#define STM32_HAS_GPIOI FALSE - -/* I2C attributes.*/ -#define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_I2C1_RX_DMA_CHN 0x00000000 -#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_I2C1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_I2C2 FALSE -#define STM32_I2C2_RX_DMA_MSK 0 -#define STM32_I2C2_RX_DMA_CHN 0x00000000 -#define STM32_I2C2_TX_DMA_MSK 0 -#define STM32_I2C2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_I2C3 FALSE -#define STM32_SPI3_RX_DMA_MSK 0 -#define STM32_SPI3_RX_DMA_CHN 0x00000000 -#define STM32_SPI3_TX_DMA_MSK 0 -#define STM32_SPI3_TX_DMA_CHN 0x00000000 - -/* SDIO attributes.*/ -#define STM32_HAS_SDIO FALSE - -/* SPI attributes.*/ -#define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) -#define STM32_SPI1_RX_DMA_CHN 0x00000000 -#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) -#define STM32_SPI1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI2 FALSE -#define STM32_SPI2_RX_DMA_MSK 0 -#define STM32_SPI2_RX_DMA_CHN 0x00000000 -#define STM32_SPI2_TX_DMA_MSK 0 -#define STM32_SPI2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI3 FALSE -#define STM32_SPI3_RX_DMA_MSK 0 -#define STM32_SPI3_RX_DMA_CHN 0x00000000 -#define STM32_SPI3_TX_DMA_MSK 0 -#define STM32_SPI3_TX_DMA_CHN 0x00000000 - -/* TIM attributes.*/ -#define STM32_HAS_TIM1 TRUE -#define STM32_HAS_TIM2 TRUE -#define STM32_HAS_TIM3 TRUE -#define STM32_HAS_TIM4 FALSE -#define STM32_HAS_TIM5 FALSE -#define STM32_HAS_TIM6 TRUE -#define STM32_HAS_TIM7 TRUE -#define STM32_HAS_TIM8 FALSE -#define STM32_HAS_TIM9 FALSE -#define STM32_HAS_TIM10 FALSE -#define STM32_HAS_TIM11 FALSE -#define STM32_HAS_TIM12 FALSE -#define STM32_HAS_TIM13 FALSE -#define STM32_HAS_TIM14 FALSE -#define STM32_HAS_TIM15 TRUE -#define STM32_HAS_TIM16 TRUE -#define STM32_HAS_TIM17 TRUE -#define STM32_HAS_TIM18 FALSE -#define STM32_HAS_TIM19 FALSE - -/* USART attributes.*/ -#define STM32_HAS_USART1 TRUE -#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_USART1_RX_DMA_CHN 0x00000000 -#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_USART1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART2 TRUE -#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_USART2_RX_DMA_CHN 0x00000000 -#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_USART2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART3 FALSE -#define STM32_USART3_RX_DMA_MSK 0 -#define STM32_USART3_RX_DMA_CHN 0x00000000 -#define STM32_USART3_TX_DMA_MSK 0 -#define STM32_USART3_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_UART4 FALSE -#define STM32_UART4_RX_DMA_MSK 0 -#define STM32_UART4_RX_DMA_CHN 0x00000000 -#define STM32_UART4_TX_DMA_MSK 0 -#define STM32_UART4_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_UART5 FALSE -#define STM32_UART5_RX_DMA_MSK 0 -#define STM32_UART5_RX_DMA_CHN 0x00000000 -#define STM32_UART5_TX_DMA_MSK 0 -#define STM32_UART5_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART6 FALSE -#define STM32_USART6_RX_DMA_MSK 0 -#define STM32_USART6_RX_DMA_CHN 0x00000000 -#define STM32_USART6_TX_DMA_MSK 0 -#define STM32_USART6_TX_DMA_CHN 0x00000000 - -/* USB attributes.*/ -#define STM32_HAS_USB FALSE -#define STM32_HAS_OTG1 FALSE -#define STM32_HAS_OTG2 FALSE -/** @} */ -#endif /* defined(STM32F10X_LD_VL) */ - -#if defined(STM32F10X_MD_VL) || defined(__DOXYGEN__) -/** - * @name STM32F100 MD capabilities - * @{ - */ -/* ADC attributes.*/ -#define STM32_HAS_ADC1 TRUE -#define STM32_HAS_ADC2 FALSE -#define STM32_HAS_ADC3 FALSE -#define STM32_HAS_ADC4 FALSE - -/* CAN attributes.*/ -#define STM32_HAS_CAN1 FALSE -#define STM32_HAS_CAN2 FALSE -#define STM32_CAN_MAX_FILTERS 0 - -/* DAC attributes.*/ -#define STM32_HAS_DAC TRUE - -/* DMA attributes.*/ -#define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 FALSE - -/* ETH attributes.*/ -#define STM32_HAS_ETH FALSE - -/* EXTI attributes.*/ -#define STM32_EXTI_NUM_CHANNELS 19 - -/* GPIO attributes.*/ -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE TRUE -#define STM32_HAS_GPIOF FALSE -#define STM32_HAS_GPIOG FALSE -#define STM32_HAS_GPIOH FALSE -#define STM32_HAS_GPIOI FALSE - -/* I2C attributes.*/ -#define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_I2C1_RX_DMA_CHN 0x00000000 -#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_I2C1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_I2C2 TRUE -#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_I2C2_RX_DMA_CHN 0x00000000 -#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_I2C2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_I2C3 FALSE -#define STM32_I2C3_RX_DMA_MSK 0 -#define STM32_I2C3_RX_DMA_CHN 0x00000000 -#define STM32_I2C3_TX_DMA_MSK 0 -#define STM32_I2C3_TX_DMA_CHN 0x00000000 - -/* RTC attributes.*/ -#define STM32_HAS_RTC TRUE - -/* SDIO attributes.*/ -#define STM32_HAS_SDIO FALSE - -/* SPI attributes.*/ -#define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) -#define STM32_SPI1_RX_DMA_CHN 0x00000000 -#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) -#define STM32_SPI1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI2 TRUE -#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) -#define STM32_SPI2_RX_DMA_CHN 0x00000000 -#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) -#define STM32_SPI2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI3 FALSE -#define STM32_HAS_SPI4 FALSE -#define STM32_HAS_SPI5 FALSE -#define STM32_HAS_SPI6 FALSE - -/* TIM attributes.*/ -#define STM32_HAS_TIM1 TRUE -#define STM32_HAS_TIM2 TRUE -#define STM32_HAS_TIM3 TRUE -#define STM32_HAS_TIM4 TRUE -#define STM32_HAS_TIM5 FALSE -#define STM32_HAS_TIM6 TRUE -#define STM32_HAS_TIM7 TRUE -#define STM32_HAS_TIM8 FALSE -#define STM32_HAS_TIM9 FALSE -#define STM32_HAS_TIM10 FALSE -#define STM32_HAS_TIM11 FALSE -#define STM32_HAS_TIM12 FALSE -#define STM32_HAS_TIM13 FALSE -#define STM32_HAS_TIM14 FALSE -#define STM32_HAS_TIM15 TRUE -#define STM32_HAS_TIM16 TRUE -#define STM32_HAS_TIM17 TRUE - -/* USART attributes.*/ -#define STM32_HAS_USART1 TRUE -#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_USART1_RX_DMA_CHN 0x00000000 -#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_USART1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART2 TRUE -#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_USART2_RX_DMA_CHN 0x00000000 -#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_USART2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART3 TRUE -#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) -#define STM32_USART3_RX_DMA_CHN 0x00000000 -#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) -#define STM32_USART3_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_UART4 FALSE -#define STM32_UART4_RX_DMA_MSK 0 -#define STM32_UART4_RX_DMA_CHN 0x00000000 -#define STM32_UART4_TX_DMA_MSK 0 -#define STM32_UART4_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_UART5 FALSE -#define STM32_UART5_RX_DMA_MSK 0 -#define STM32_UART5_RX_DMA_CHN 0x00000000 -#define STM32_UART5_TX_DMA_MSK 0 -#define STM32_UART5_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART6 FALSE -#define STM32_USART6_RX_DMA_MSK 0 -#define STM32_USART6_RX_DMA_CHN 0x00000000 -#define STM32_USART6_TX_DMA_MSK 0 -#define STM32_USART6_TX_DMA_CHN 0x00000000 - -/* USB attributes.*/ -#define STM32_HAS_USB FALSE -#define STM32_HAS_OTG1 FALSE -#define STM32_HAS_OTG2 FALSE -/** @} */ -#endif /* defined(STM32F10X_MD_VL) */ - -/*===========================================================================*/ -/* Platform specific friendly IRQ names. */ -/*===========================================================================*/ - -/** - * @name IRQ VECTOR names - * @{ - */ -#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */ -#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line - detect. */ -#define TAMPER_IRQHandler Vector48 /**< Tamper. */ -#define RTC_IRQHandler Vector4C /**< RTC. */ -#define FLASH_IRQHandler Vector50 /**< Flash. */ -#define RCC_IRQHandler Vector54 /**< RCC. */ -#define EXTI0_IRQHandler Vector58 /**< EXTI Line 0. */ -#define EXTI1_IRQHandler Vector5C /**< EXTI Line 1. */ -#define EXTI2_IRQHandler Vector60 /**< EXTI Line 2. */ -#define EXTI3_IRQHandler Vector64 /**< EXTI Line 3. */ -#define EXTI4_IRQHandler Vector68 /**< EXTI Line 4. */ -#define DMA1_Ch1_IRQHandler Vector6C /**< DMA1 Channel 1. */ -#define DMA1_Ch2_IRQHandler Vector70 /**< DMA1 Channel 2. */ -#define DMA1_Ch3_IRQHandler Vector74 /**< DMA1 Channel 3. */ -#define DMA1_Ch4_IRQHandler Vector78 /**< DMA1 Channel 4. */ -#define DMA1_Ch5_IRQHandler Vector7C /**< DMA1 Channel 5. */ -#define DMA1_Ch6_IRQHandler Vector80 /**< DMA1 Channel 6. */ -#define DMA1_Ch7_IRQHandler Vector84 /**< DMA1 Channel 7. */ -#define ADC1_2_IRQHandler Vector88 /**< ADC1_2. */ -#define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */ -#define TIM1_BRK_IRQHandler VectorA0 /**< TIM1 Break. */ -#define TIM1_UP_IRQHandler VectorA4 /**< TIM1 Update. */ -#define TIM1_TRG_COM_IRQHandler VectorA8 /**< TIM1 Trigger and - Commutation. */ -#define TIM1_CC_IRQHandler VectorAC /**< TIM1 Capture Compare. */ -#define TIM2_IRQHandler VectorB0 /**< TIM2. */ -#define TIM3_IRQHandler VectorB4 /**< TIM3. */ -#if !defined(STM32F10X_LD_VL) || defined(__DOXYGEN__) -#define TIM4_IRQHandler VectorB8 /**< TIM4. */ -#endif -#define I2C1_EV_IRQHandler VectorBC /**< I2C1 Event. */ -#define I2C1_ER_IRQHandler VectorC0 /**< I2C1 Error. */ -#if !defined(STM32F10X_LD_VL) || defined(__DOXYGEN__) -#define I2C2_EV_IRQHandler VectorC4 /**< I2C2 Event. */ -#define I2C2_ER_IRQHandler VectorC8 /**< I2C2 Error. */ -#endif -#define SPI1_IRQHandler VectorCC /**< SPI1. */ -#if !defined(STM32F10X_LD_VL) || defined(__DOXYGEN__) -#define SPI2_IRQHandler VectorD0 /**< SPI2. */ -#endif -#define USART1_IRQHandler VectorD4 /**< USART1. */ -#define USART2_IRQHandler VectorD8 /**< USART2. */ -#if !defined(STM32F10X_LD_VL) || defined(__DOXYGEN__) -#define USART3_IRQHandler VectorDC /**< USART3. */ -#endif -#define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */ -#define RTC_Alarm_IRQHandler VectorE4 /**< RTC Alarm through EXTI. */ -#define CEC_IRQHandler VectorE8 /**< CEC. */ -#define TIM12_IRQHandler VectorEC /**< TIM12. */ -#define TIM13_IRQHandler VectorF0 /**< TIM13. */ -#define TIM14_IRQHandler VectorF4 /**< TIM14. */ -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief Main clock source selection. - * @note If the selected clock source is not the PLL then the PLL is not - * initialized and started. - * @note The default value is calculated for a 72MHz system clock from - * a 8MHz crystal using the PLL. - */ -#if !defined(STM32_SW) || defined(__DOXYGEN__) -#define STM32_SW STM32_SW_PLL -#endif - -/** - * @brief Clock source for the PLL. - * @note This setting has only effect if the PLL is selected as the - * system clock source. - * @note The default value is calculated for a 72MHz system clock from - * a 8MHz crystal using the PLL. - */ -#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__) -#define STM32_PLLSRC STM32_PLLSRC_HSE -#endif - -/** - * @brief Crystal PLL pre-divider. - * @note This setting has only effect if the PLL is selected as the - * system clock source. - * @note The default value is calculated for a 72MHz system clock from - * a 8MHz crystal using the PLL. - */ -#if !defined(STM32_PLLXTPRE) || defined(__DOXYGEN__) -#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 -#endif - -/** - * @brief PLL multiplier value. - * @note The allowed range is 2...16. - * @note The default value is calculated for a 24MHz system clock from - * a 8MHz crystal using the PLL. - */ -#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLMUL_VALUE 3 -#endif - -/** - * @brief AHB prescaler value. - * @note The default value is calculated for a 24MHz system clock from - * a 8MHz crystal using the PLL. - */ -#if !defined(STM32_HPRE) || defined(__DOXYGEN__) -#define STM32_HPRE STM32_HPRE_DIV1 -#endif - -/** - * @brief APB1 prescaler value. - */ -#if !defined(STM32_PPRE1) || defined(__DOXYGEN__) -#define STM32_PPRE1 STM32_PPRE1_DIV1 -#endif - -/** - * @brief APB2 prescaler value. - */ -#if !defined(STM32_PPRE2) || defined(__DOXYGEN__) -#define STM32_PPRE2 STM32_PPRE2_DIV1 -#endif - -/** - * @brief ADC prescaler value. - */ -#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__) -#define STM32_ADCPRE STM32_ADCPRE_DIV2 -#endif - -/** - * @brief MCO pin setting. - */ -#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__) -#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK -#endif - -/** - * @brief RTC clock source. - */ -#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__) -#define STM32_RTCSEL STM32_RTCSEL_LSI -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/* - * Configuration-related checks. - */ -#if !defined(STM32F100_MCUCONF) -#error "Using a wrong mcuconf.h file, STM32F100_MCUCONF not defined" -#endif - -/* - * HSI related checks. - */ -#if STM32_HSI_ENABLED -#else /* !STM32_HSI_ENABLED */ - -#if STM32_SW == STM32_SW_HSI -#error "HSI not enabled, required by STM32_SW" -#endif - -#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI) -#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC" -#endif - -#if (STM32_MCOSEL == STM32_MCOSEL_HSI) || \ - ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \ - (STM32_PLLSRC == STM32_PLLSRC_HSI)) -#error "HSI not enabled, required by STM32_MCOSEL" -#endif - -#endif /* !STM32_HSI_ENABLED */ - -/* - * HSE related checks. - */ -#if STM32_HSE_ENABLED - -#if STM32_HSECLK == 0 -#error "HSE frequency not defined" -#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX) -#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)" -#endif - -#else /* !STM32_HSE_ENABLED */ - -#if STM32_SW == STM32_SW_HSE -#error "HSE not enabled, required by STM32_SW" -#endif - -#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE) -#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC" -#endif - -#if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \ - ((STM32_MCOSEL == STM32_MCOSEL_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)) -#error "HSE not enabled, required by STM32_MCOSEL" -#endif - -#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV -#error "HSE not enabled, required by STM32_RTCSELSEL" -#endif - -#endif /* !STM32_HSE_ENABLED */ - -/* - * LSI related checks. - */ -#if STM32_LSI_ENABLED -#else /* !STM32_LSI_ENABLED */ - -#if STM32_RTCSEL == STM32_RTCSEL_LSI -#error "LSI not enabled, required by STM32_RTCSEL" -#endif - -#endif /* !STM32_LSI_ENABLED */ - -/* - * LSE related checks. - */ -#if STM32_LSE_ENABLED - -#if (STM32_LSECLK == 0) -#error "LSE frequency not defined" -#endif - -#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX) -#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)" -#endif - -#else /* !STM32_LSE_ENABLED */ - -#if STM32_RTCSEL == STM32_RTCSEL_LSE -#error "LSE not enabled, required by STM32_RTCSEL" -#endif - -#endif /* !STM32_LSE_ENABLED */ - -/* PLL activation conditions.*/ -#if (STM32_SW == STM32_SW_PLL) || \ - (STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) || \ - defined(__DOXYGEN__) -/** - * @brief PLL activation flag. - */ -#define STM32_ACTIVATE_PLL TRUE -#else -#define STM32_ACTIVATE_PLL FALSE -#endif - -/* HSE prescaler setting check.*/ -#if (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV1) && \ - (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV2) -#error "invalid STM32_PLLXTPRE value specified" -#endif - -/** - * @brief PLLMUL field. - */ -#if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) || \ - defined(__DOXYGEN__) -#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18) -#else -#error "invalid STM32_PLLMUL_VALUE value specified" -#endif - -/** - * @brief PLL input clock frequency. - */ -#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) -#if STM32_PLLXTPRE == STM32_PLLXTPRE_DIV1 -#define STM32_PLLCLKIN (STM32_HSECLK / 1) -#else -#define STM32_PLLCLKIN (STM32_HSECLK / 2) -#endif -#elif STM32_PLLSRC == STM32_PLLSRC_HSI -#define STM32_PLLCLKIN (STM32_HSICLK / 2) -#else -#error "invalid STM32_PLLSRC value specified" -#endif - -/* PLL input frequency range check.*/ -#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX) -#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)" -#endif - -/** - * @brief PLL output clock frequency. - */ -#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE) - -/* PLL output frequency range check.*/ -#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX) -#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)" -#endif - -/** - * @brief System clock source. - */ -#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__) -#define STM32_SYSCLK STM32_PLLCLKOUT -#elif (STM32_SW == STM32_SW_HSI) -#define STM32_SYSCLK STM32_HSICLK -#elif (STM32_SW == STM32_SW_HSE) -#define STM32_SYSCLK STM32_HSECLK -#else -#error "invalid STM32_SW value specified" -#endif - -/* Check on the system clock.*/ -#if STM32_SYSCLK > STM32_SYSCLK_MAX -#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)" -#endif - -/** - * @brief AHB frequency. - */ -#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__) -#define STM32_HCLK (STM32_SYSCLK / 1) -#elif STM32_HPRE == STM32_HPRE_DIV2 -#define STM32_HCLK (STM32_SYSCLK / 2) -#elif STM32_HPRE == STM32_HPRE_DIV4 -#define STM32_HCLK (STM32_SYSCLK / 4) -#elif STM32_HPRE == STM32_HPRE_DIV8 -#define STM32_HCLK (STM32_SYSCLK / 8) -#elif STM32_HPRE == STM32_HPRE_DIV16 -#define STM32_HCLK (STM32_SYSCLK / 16) -#elif STM32_HPRE == STM32_HPRE_DIV64 -#define STM32_HCLK (STM32_SYSCLK / 64) -#elif STM32_HPRE == STM32_HPRE_DIV128 -#define STM32_HCLK (STM32_SYSCLK / 128) -#elif STM32_HPRE == STM32_HPRE_DIV256 -#define STM32_HCLK (STM32_SYSCLK / 256) -#elif STM32_HPRE == STM32_HPRE_DIV512 -#define STM32_HCLK (STM32_SYSCLK / 512) -#else -#error "invalid STM32_HPRE value specified" -#endif - -/* AHB frequency check.*/ -#if STM32_HCLK > STM32_SYSCLK_MAX -#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)" -#endif - -/** - * @brief APB1 frequency. - */ -#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) -#define STM32_PCLK1 (STM32_HCLK / 1) -#elif STM32_PPRE1 == STM32_PPRE1_DIV2 -#define STM32_PCLK1 (STM32_HCLK / 2) -#elif STM32_PPRE1 == STM32_PPRE1_DIV4 -#define STM32_PCLK1 (STM32_HCLK / 4) -#elif STM32_PPRE1 == STM32_PPRE1_DIV8 -#define STM32_PCLK1 (STM32_HCLK / 8) -#elif STM32_PPRE1 == STM32_PPRE1_DIV16 -#define STM32_PCLK1 (STM32_HCLK / 16) -#else -#error "invalid STM32_PPRE1 value specified" -#endif - -/* APB1 frequency check.*/ -#if STM32_PCLK1 > STM32_PCLK1_MAX -#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)" -#endif - -/** - * @brief APB2 frequency. - */ -#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) -#define STM32_PCLK2 (STM32_HCLK / 1) -#elif STM32_PPRE2 == STM32_PPRE2_DIV2 -#define STM32_PCLK2 (STM32_HCLK / 2) -#elif STM32_PPRE2 == STM32_PPRE2_DIV4 -#define STM32_PCLK2 (STM32_HCLK / 4) -#elif STM32_PPRE2 == STM32_PPRE2_DIV8 -#define STM32_PCLK2 (STM32_HCLK / 8) -#elif STM32_PPRE2 == STM32_PPRE2_DIV16 -#define STM32_PCLK2 (STM32_HCLK / 16) -#else -#error "invalid STM32_PPRE2 value specified" -#endif - -/* APB2 frequency check.*/ -#if STM32_PCLK2 > STM32_PCLK2_MAX -#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)" -#endif - -/** - * @brief RTC clock. - */ -#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__) -#define STM32_RTCCLK STM32_LSECLK -#elif STM32_RTCSEL == STM32_RTCSEL_LSI -#define STM32_RTCCLK STM32_LSICLK -#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV -#define STM32_RTCCLK (STM32_HSECLK / 128) -#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK -#define STM32_RTCCLK 0 -#else -#error "invalid source selected for RTC clock" -#endif - -/** - * @brief ADC frequency. - */ -#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__) -#define STM32_ADCCLK (STM32_PCLK2 / 2) -#elif STM32_ADCPRE == STM32_ADCPRE_DIV4 -#define STM32_ADCCLK (STM32_PCLK2 / 4) -#elif STM32_ADCPRE == STM32_ADCPRE_DIV6 -#define STM32_ADCCLK (STM32_PCLK2 / 6) -#elif STM32_ADCPRE == STM32_ADCPRE_DIV8 -#define STM32_ADCCLK (STM32_PCLK2 / 8) -#else -#error "invalid STM32_ADCPRE value specified" -#endif - -/* ADC frequency check.*/ -#if STM32_ADCCLK > STM32_ADCCLK_MAX -#error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MAX)" -#endif - -/** - * @brief Timers 2, 3, 4, 5, 6, 7, 12, 13, 14 clock. - */ -#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) -#define STM32_TIMCLK1 (STM32_PCLK1 * 1) -#else -#define STM32_TIMCLK1 (STM32_PCLK1 * 2) -#endif - -/** - * @brief Timers 1, 8, 9, 10, 11 clock. - */ -#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) -#define STM32_TIMCLK2 (STM32_PCLK2 * 1) -#else -#define STM32_TIMCLK2 (STM32_PCLK2 * 2) -#endif - -/** - * @brief Flash settings. - */ -#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__) -#define STM32_FLASHBITS 0x00000010 -#elif STM32_HCLK <= 48000000 -#define STM32_FLASHBITS 0x00000011 -#else -#define STM32_FLASHBITS 0x00000012 -#endif - -#endif /* _HAL_LLD_F100_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32F1xx/hal_lld_f103.h b/firmware/chibios/os/hal/platforms/STM32F1xx/hal_lld_f103.h deleted file mode 100644 index 55c8e96818..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F1xx/hal_lld_f103.h +++ /dev/null @@ -1,1308 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @defgroup STM32F103_HAL STM32F103 HAL Support - * @details HAL support for STM32 Performance Line LD, MD and HD sub-families. - * - * @ingroup HAL - */ - -/** - * @file STM32F1xx/hal_lld_f103.h - * @brief STM32F103 Performance Line HAL subsystem low level driver header. - * - * @addtogroup STM32F103_HAL - * @{ - */ - -#ifndef _HAL_LLD_F103_H_ -#define _HAL_LLD_F103_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name Platform identification - * @{ - */ -#if defined(__DOXYGEN__) -#define PLATFORM_NAME "STM32F10x Performance Line" - -#elif defined(STM32F10X_LD) -#define PLATFORM_NAME "STM32F10x Performance Line Low Density" - -#elif defined(STM32F10X_MD) -#define PLATFORM_NAME "STM32F10x Performance Line Medium Density" - -#elif defined(STM32F10X_HD) -#define PLATFORM_NAME "STM32F10x Performance Line High Density" - -#elif defined(STM32F10X_XL) -#define PLATFORM_NAME "STM32F10x Performance Line eXtra Density" - -#else -#error "unsupported STM32 Performance Line member" -#endif -/** @} */ - -/** - * @name Absolute Maximum Ratings - * @{ - */ -/** - * @brief Maximum system clock frequency. - */ -#define STM32_SYSCLK_MAX 72000000 - -/** - * @brief Maximum HSE clock frequency. - */ -#define STM32_HSECLK_MAX 25000000 - -/** - * @brief Minimum HSE clock frequency. - */ -#define STM32_HSECLK_MIN 1000000 - -/** - * @brief Maximum LSE clock frequency. - */ -#define STM32_LSECLK_MAX 1000000 - -/** - * @brief Minimum LSE clock frequency. - */ -#define STM32_LSECLK_MIN 32768 - -/** - * @brief Maximum PLLs input clock frequency. - */ -#define STM32_PLLIN_MAX 25000000 - -/** - * @brief Maximum PLLs input clock frequency. - */ -#define STM32_PLLIN_MIN 1000000 - -/** - * @brief Maximum PLL output clock frequency. - */ -#define STM32_PLLOUT_MAX 72000000 - -/** - * @brief Maximum PLL output clock frequency. - */ -#define STM32_PLLOUT_MIN 16000000 - -/** - * @brief Maximum APB1 clock frequency. - */ -#define STM32_PCLK1_MAX 36000000 - -/** - * @brief Maximum APB2 clock frequency. - */ -#define STM32_PCLK2_MAX 72000000 - -/** - * @brief Maximum ADC clock frequency. - */ -#define STM32_ADCCLK_MAX 14000000 -/** @} */ - -/** - * @name RCC_CFGR register bits definitions - * @{ - */ -#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */ -#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */ -#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */ - -#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */ -#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */ -#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */ -#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */ -#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */ -#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */ -#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */ -#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */ -#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */ - -#define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */ -#define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */ -#define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */ -#define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */ -#define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */ - -#define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */ -#define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */ -#define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */ -#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */ -#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */ - -#define STM32_ADCPRE_DIV2 (0 << 14) /**< PPRE2 divided by 2. */ -#define STM32_ADCPRE_DIV4 (1 << 14) /**< PPRE2 divided by 4. */ -#define STM32_ADCPRE_DIV6 (2 << 14) /**< PPRE2 divided by 6. */ -#define STM32_ADCPRE_DIV8 (3 << 14) /**< PPRE2 divided by 8. */ - -#define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */ -#define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */ - -#define STM32_PLLXTPRE_DIV1 (0 << 17) /**< HSE divided by 1. */ -#define STM32_PLLXTPRE_DIV2 (1 << 17) /**< HSE divided by 2. */ - -#define STM32_USBPRE_DIV1P5 (0 << 22) /**< PLLOUT divided by 1.5. */ -#define STM32_USBPRE_DIV1 (1 << 22) /**< PLLOUT divided by 1. */ - -#define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */ -#define STM32_MCOSEL_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */ -#define STM32_MCOSEL_HSI (5 << 24) /**< HSI clock on MCO pin. */ -#define STM32_MCOSEL_HSE (6 << 24) /**< HSE clock on MCO pin. */ -#define STM32_MCOSEL_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */ -/** @} */ - -/** - * @name RCC_BDCR register bits definitions - * @{ - */ -#define STM32_RTCSEL_MASK (3 << 8) /**< RTC clock source mask. */ -#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No clock. */ -#define STM32_RTCSEL_LSE (1 << 8) /**< LSE used as RTC clock. */ -#define STM32_RTCSEL_LSI (2 << 8) /**< LSI used as RTC clock. */ -#define STM32_RTCSEL_HSEDIV (3 << 8) /**< HSE divided by 128 used as - RTC clock. */ -/** @} */ - -/*===========================================================================*/ -/* Platform capabilities. */ -/*===========================================================================*/ - -#if defined(STM32F10X_LD) || defined(__DOXYGEN__) -/** - * @name STM32F103 LD capabilities - * @{ - */ -/* ADC attributes.*/ -#define STM32_HAS_ADC1 TRUE -#define STM32_HAS_ADC2 TRUE -#define STM32_HAS_ADC3 FALSE -#define STM32_HAS_ADC4 FALSE - -/* CAN attributes.*/ -#define STM32_HAS_CAN1 TRUE -#define STM32_HAS_CAN2 FALSE -#define STM32_CAN_MAX_FILTERS 14 - -/* DAC attributes.*/ -#define STM32_HAS_DAC FALSE - -/* DMA attributes.*/ -#define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 FALSE - -/* ETH attributes.*/ -#define STM32_HAS_ETH FALSE - -/* EXTI attributes.*/ -#define STM32_EXTI_NUM_CHANNELS 19 - -/* GPIO attributes.*/ -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE FALSE -#define STM32_HAS_GPIOF FALSE -#define STM32_HAS_GPIOG FALSE -#define STM32_HAS_GPIOH FALSE -#define STM32_HAS_GPIOI FALSE - -/* I2C attributes.*/ -#define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_I2C1_RX_DMA_CHN 0x00000000 -#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_I2C1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_I2C2 FALSE -#define STM32_I2C2_RX_DMA_MSK 0 -#define STM32_I2C2_RX_DMA_CHN 0x00000000 -#define STM32_I2C2_TX_DMA_MSK 0 -#define STM32_I2C2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_I2C3 FALSE -#define STM32_SPI3_RX_DMA_MSK 0 -#define STM32_SPI3_RX_DMA_CHN 0x00000000 -#define STM32_SPI3_TX_DMA_MSK 0 -#define STM32_SPI3_TX_DMA_CHN 0x00000000 - -/* SDIO attributes.*/ -#define STM32_HAS_SDIO FALSE - -/* SPI attributes.*/ -#define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) -#define STM32_SPI1_RX_DMA_CHN 0x00000000 -#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) -#define STM32_SPI1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI2 FALSE -#define STM32_SPI2_RX_DMA_MSK 0 -#define STM32_SPI2_RX_DMA_CHN 0x00000000 -#define STM32_SPI2_TX_DMA_MSK 0 -#define STM32_SPI2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI3 FALSE -#define STM32_SPI3_RX_DMA_MSK 0 -#define STM32_SPI3_RX_DMA_CHN 0x00000000 -#define STM32_SPI3_TX_DMA_MSK 0 -#define STM32_SPI3_TX_DMA_CHN 0x00000000 - -/* TIM attributes.*/ -#define STM32_HAS_TIM1 TRUE -#define STM32_HAS_TIM2 TRUE -#define STM32_HAS_TIM3 TRUE -#define STM32_HAS_TIM4 FALSE -#define STM32_HAS_TIM5 FALSE -#define STM32_HAS_TIM6 FALSE -#define STM32_HAS_TIM7 FALSE -#define STM32_HAS_TIM8 FALSE -#define STM32_HAS_TIM9 FALSE -#define STM32_HAS_TIM10 FALSE -#define STM32_HAS_TIM11 FALSE -#define STM32_HAS_TIM12 FALSE -#define STM32_HAS_TIM13 FALSE -#define STM32_HAS_TIM14 FALSE -#define STM32_HAS_TIM15 FALSE -#define STM32_HAS_TIM16 FALSE -#define STM32_HAS_TIM17 FALSE -#define STM32_HAS_TIM18 FALSE -#define STM32_HAS_TIM19 FALSE - -/* USART attributes.*/ -#define STM32_HAS_USART1 TRUE -#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_USART1_RX_DMA_CHN 0x00000000 -#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_USART1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART2 TRUE -#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_USART2_RX_DMA_CHN 0x00000000 -#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_USART2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART3 FALSE -#define STM32_USART3_RX_DMA_MSK 0 -#define STM32_USART3_RX_DMA_CHN 0x00000000 -#define STM32_USART3_TX_DMA_MSK 0 -#define STM32_USART3_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_UART4 FALSE -#define STM32_UART4_RX_DMA_MSK 0 -#define STM32_UART4_RX_DMA_CHN 0x00000000 -#define STM32_UART4_TX_DMA_MSK 0 -#define STM32_UART4_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_UART5 FALSE -#define STM32_UART5_RX_DMA_MSK 0 -#define STM32_UART5_RX_DMA_CHN 0x00000000 -#define STM32_UART5_TX_DMA_MSK 0 -#define STM32_UART5_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART6 FALSE -#define STM32_USART6_RX_DMA_MSK 0 -#define STM32_USART6_RX_DMA_CHN 0x00000000 -#define STM32_USART6_TX_DMA_MSK 0 -#define STM32_USART6_TX_DMA_CHN 0x00000000 - -/* USB attributes.*/ -#define STM32_HAS_USB FALSE -#define STM32_HAS_OTG1 FALSE -#define STM32_HAS_OTG2 FALSE -/** @} */ -#endif /* defined(STM32F10X_LD) */ - -#if defined(STM32F10X_MD) || defined(__DOXYGEN__) -/** - * @name STM32F103 MD capabilities - * @{ - */ -/* ADC attributes.*/ -#define STM32_HAS_ADC1 TRUE -#define STM32_HAS_ADC2 TRUE -#define STM32_HAS_ADC3 FALSE - -/* CAN attributes.*/ -#define STM32_HAS_CAN1 TRUE -#define STM32_HAS_CAN2 FALSE -#define STM32_CAN_MAX_FILTERS 14 - -/* DAC attributes.*/ -#define STM32_HAS_DAC FALSE - -/* DMA attributes.*/ -#define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 FALSE - -/* ETH attributes.*/ -#define STM32_HAS_ETH FALSE - -/* EXTI attributes.*/ -#define STM32_EXTI_NUM_CHANNELS 19 - -/* GPIO attributes.*/ -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE TRUE -#define STM32_HAS_GPIOF FALSE -#define STM32_HAS_GPIOG FALSE -#define STM32_HAS_GPIOH FALSE -#define STM32_HAS_GPIOI FALSE - -/* I2C attributes.*/ -#define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_I2C1_RX_DMA_CHN 0x00000000 -#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_I2C1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_I2C2 TRUE -#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_I2C2_RX_DMA_CHN 0x00000000 -#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_I2C2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_I2C3 FALSE -#define STM32_I2C3_RX_DMA_MSK 0 -#define STM32_I2C3_RX_DMA_CHN 0x00000000 -#define STM32_I2C3_TX_DMA_MSK 0 -#define STM32_I2C3_TX_DMA_CHN 0x00000000 - -/* RTC attributes.*/ -#define STM32_HAS_RTC TRUE -#define STM32_RTCSEL_HAS_SUBSECONDS TRUE - -/* SDIO attributes.*/ -#define STM32_HAS_SDIO FALSE - -/* SPI attributes.*/ -#define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) -#define STM32_SPI1_RX_DMA_CHN 0x00000000 -#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) -#define STM32_SPI1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI2 TRUE -#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) -#define STM32_SPI2_RX_DMA_CHN 0x00000000 -#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) -#define STM32_SPI2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI3 FALSE -#define STM32_SPI3_RX_DMA_MSK 0 -#define STM32_SPI3_RX_DMA_CHN 0x00000000 -#define STM32_SPI3_TX_DMA_MSK 0 -#define STM32_SPI3_TX_DMA_CHN 0x00000000 - -/* TIM attributes.*/ -#define STM32_HAS_TIM1 TRUE -#define STM32_HAS_TIM2 TRUE -#define STM32_HAS_TIM3 TRUE -#define STM32_HAS_TIM4 TRUE -#define STM32_HAS_TIM5 FALSE -#define STM32_HAS_TIM6 FALSE -#define STM32_HAS_TIM7 FALSE -#define STM32_HAS_TIM8 FALSE -#define STM32_HAS_TIM9 FALSE -#define STM32_HAS_TIM10 FALSE -#define STM32_HAS_TIM11 FALSE -#define STM32_HAS_TIM12 FALSE -#define STM32_HAS_TIM13 FALSE -#define STM32_HAS_TIM14 FALSE -#define STM32_HAS_TIM15 FALSE -#define STM32_HAS_TIM16 FALSE -#define STM32_HAS_TIM17 FALSE -#define STM32_HAS_TIM18 FALSE -#define STM32_HAS_TIM19 FALSE - -/* USART attributes.*/ -#define STM32_HAS_USART1 TRUE -#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_USART1_RX_DMA_CHN 0x00000000 -#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_USART1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART2 TRUE -#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_USART2_RX_DMA_CHN 0x00000000 -#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_USART2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART3 TRUE -#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) -#define STM32_USART3_RX_DMA_CHN 0x00000000 -#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) -#define STM32_USART3_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_UART4 FALSE -#define STM32_UART4_RX_DMA_MSK 0 -#define STM32_UART4_RX_DMA_CHN 0x00000000 -#define STM32_UART4_TX_DMA_MSK 0 -#define STM32_UART4_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_UART5 FALSE -#define STM32_UART5_RX_DMA_MSK 0 -#define STM32_UART5_RX_DMA_CHN 0x00000000 -#define STM32_UART5_TX_DMA_MSK 0 -#define STM32_UART5_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART6 FALSE -#define STM32_USART6_RX_DMA_MSK 0 -#define STM32_USART6_RX_DMA_CHN 0x00000000 -#define STM32_USART6_TX_DMA_MSK 0 -#define STM32_USART6_TX_DMA_CHN 0x00000000 - -/* USB attributes.*/ -#define STM32_HAS_USB TRUE -#define STM32_HAS_OTG1 FALSE -#define STM32_HAS_OTG2 FALSE -/** @} */ -#endif /* defined(STM32F10X_MD) */ - -#if defined(STM32F10X_HD) || defined(__DOXYGEN__) -/** - * @name STM32F103 HD capabilities - * @{ - */ -/* ADC attributes.*/ -#define STM32_HAS_ADC1 TRUE -#define STM32_HAS_ADC2 TRUE -#define STM32_HAS_ADC3 TRUE - -/* CAN attributes.*/ -#define STM32_HAS_CAN1 TRUE -#define STM32_HAS_CAN2 FALSE -#define STM32_CAN_MAX_FILTERS 14 - -/* DAC attributes.*/ -#define STM32_HAS_DAC TRUE - -/* DMA attributes.*/ -#define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 TRUE - -/* ETH attributes.*/ -#define STM32_HAS_ETH FALSE - -/* EXTI attributes.*/ -#define STM32_EXTI_NUM_CHANNELS 19 - -/* GPIO attributes.*/ -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE TRUE -#define STM32_HAS_GPIOF TRUE -#define STM32_HAS_GPIOG TRUE -#define STM32_HAS_GPIOH FALSE -#define STM32_HAS_GPIOI FALSE - -/* I2C attributes.*/ -#define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_I2C1_RX_DMA_CHN 0x00000000 -#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_I2C1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_I2C2 TRUE -#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_I2C2_RX_DMA_CHN 0x00000000 -#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_I2C2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_I2C3 FALSE -#define STM32_I2C3_RX_DMA_MSK 0 -#define STM32_I2C3_RX_DMA_CHN 0x00000000 -#define STM32_I2C3_TX_DMA_MSK 0 -#define STM32_I2C3_TX_DMA_CHN 0x00000000 - -/* RTC attributes.*/ -#define STM32_HAS_RTC TRUE -#define STM32_RTCSEL_HAS_SUBSECONDS TRUE - -/* SDIO attributes.*/ -#define STM32_HAS_SDIO TRUE - -/* SPI attributes.*/ -#define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) -#define STM32_SPI1_RX_DMA_CHN 0x00000000 -#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) -#define STM32_SPI1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI2 TRUE -#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) -#define STM32_SPI2_RX_DMA_CHN 0x00000000 -#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) -#define STM32_SPI2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI3 TRUE -#define STM32_SPI3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 1) -#define STM32_SPI3_RX_DMA_CHN 0x00000000 -#define STM32_SPI3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 2) -#define STM32_SPI3_TX_DMA_CHN 0x00000000 - -/* TIM attributes.*/ -#define STM32_HAS_TIM1 TRUE -#define STM32_HAS_TIM2 TRUE -#define STM32_HAS_TIM3 TRUE -#define STM32_HAS_TIM4 TRUE -#define STM32_HAS_TIM5 TRUE -#define STM32_HAS_TIM6 TRUE -#define STM32_HAS_TIM7 TRUE -#define STM32_HAS_TIM8 TRUE -#define STM32_HAS_TIM9 TRUE -#define STM32_HAS_TIM10 TRUE -#define STM32_HAS_TIM11 TRUE -#define STM32_HAS_TIM12 TRUE -#define STM32_HAS_TIM13 TRUE -#define STM32_HAS_TIM14 TRUE -#define STM32_HAS_TIM15 FALSE -#define STM32_HAS_TIM16 FALSE -#define STM32_HAS_TIM17 FALSE -#define STM32_HAS_TIM18 FALSE -#define STM32_HAS_TIM19 FALSE - -/* USART attributes.*/ -#define STM32_HAS_USART1 TRUE -#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_USART1_RX_DMA_CHN 0x00000000 -#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_USART1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART2 TRUE -#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_USART2_RX_DMA_CHN 0x00000000 -#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_USART2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART3 TRUE -#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) -#define STM32_USART3_RX_DMA_CHN 0x00000000 -#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) -#define STM32_USART3_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_UART4 TRUE -#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3)) -#define STM32_UART4_RX_DMA_CHN 0x00000000 -#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5)) -#define STM32_UART4_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_UART5 TRUE -#define STM32_UART5_RX_DMA_MSK 0 -#define STM32_UART5_RX_DMA_CHN 0x00000000 -#define STM32_UART5_TX_DMA_MSK 0 -#define STM32_UART5_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART6 FALSE -#define STM32_USART6_RX_DMA_MSK 0 -#define STM32_USART6_RX_DMA_CHN 0x00000000 -#define STM32_USART6_TX_DMA_MSK 0 -#define STM32_USART6_TX_DMA_CHN 0x00000000 - -/* USB attributes.*/ -#define STM32_HAS_USB TRUE -#define STM32_HAS_OTG1 FALSE -#define STM32_HAS_OTG2 FALSE -/** @} */ -#endif /* defined(STM32F10X_HD) */ - -#if defined(STM32F10X_XL) || defined(__DOXYGEN__) -/** - * @name STM32F103 XL capabilities - * @{ - */ -/* ADC attributes.*/ -#define STM32_HAS_ADC1 TRUE -#define STM32_HAS_ADC2 TRUE -#define STM32_HAS_ADC3 TRUE - -/* CAN attributes.*/ -#define STM32_HAS_CAN1 TRUE -#define STM32_HAS_CAN2 FALSE -#define STM32_CAN_MAX_FILTERS 14 - -/* DAC attributes.*/ -#define STM32_HAS_DAC TRUE - -/* DMA attributes.*/ -#define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 TRUE - -/* ETH attributes.*/ -#define STM32_HAS_ETH FALSE - -/* EXTI attributes.*/ -#define STM32_EXTI_NUM_CHANNELS 19 - -/* GPIO attributes.*/ -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE TRUE -#define STM32_HAS_GPIOF TRUE -#define STM32_HAS_GPIOG TRUE -#define STM32_HAS_GPIOH FALSE -#define STM32_HAS_GPIOI FALSE - -/* I2C attributes.*/ -#define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_I2C1_RX_DMA_CHN 0x00000000 -#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_I2C1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_I2C2 TRUE -#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_I2C2_RX_DMA_CHN 0x00000000 -#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_I2C2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_I2C3 FALSE -#define STM32_I2C3_RX_DMA_MSK 0 -#define STM32_I2C3_RX_DMA_CHN 0x00000000 -#define STM32_I2C3_TX_DMA_MSK 0 -#define STM32_I2C3_TX_DMA_CHN 0x00000000 - -/* RTC attributes.*/ -#define STM32_HAS_RTC TRUE -#define STM32_RTCSEL_HAS_SUBSECONDS TRUE - -/* SDIO attributes.*/ -#define STM32_HAS_SDIO TRUE - -/* SPI attributes.*/ -#define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) -#define STM32_SPI1_RX_DMA_CHN 0x00000000 -#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) -#define STM32_SPI1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI2 TRUE -#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) -#define STM32_SPI2_RX_DMA_CHN 0x00000000 -#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) -#define STM32_SPI2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI3 TRUE -#define STM32_SPI3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 1) -#define STM32_SPI3_RX_DMA_CHN 0x00000000 -#define STM32_SPI3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 2) -#define STM32_SPI3_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI4 FALSE -#define STM32_HAS_SPI5 FALSE -#define STM32_HAS_SPI6 FALSE - -/* TIM attributes.*/ -#define STM32_HAS_TIM1 TRUE -#define STM32_HAS_TIM2 TRUE -#define STM32_HAS_TIM3 TRUE -#define STM32_HAS_TIM4 TRUE -#define STM32_HAS_TIM5 TRUE -#define STM32_HAS_TIM6 TRUE -#define STM32_HAS_TIM7 TRUE -#define STM32_HAS_TIM8 TRUE -#define STM32_HAS_TIM9 FALSE -#define STM32_HAS_TIM10 FALSE -#define STM32_HAS_TIM11 FALSE -#define STM32_HAS_TIM12 FALSE -#define STM32_HAS_TIM13 FALSE -#define STM32_HAS_TIM14 FALSE -#define STM32_HAS_TIM15 FALSE -#define STM32_HAS_TIM16 FALSE -#define STM32_HAS_TIM17 FALSE -#define STM32_HAS_TIM18 FALSE -#define STM32_HAS_TIM19 FALSE - -/* USART attributes.*/ -#define STM32_HAS_USART1 TRUE -#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_USART1_RX_DMA_CHN 0x00000000 -#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_USART1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART2 TRUE -#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_USART2_RX_DMA_CHN 0x00000000 -#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_USART2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART3 TRUE -#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) -#define STM32_USART3_RX_DMA_CHN 0x00000000 -#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) -#define STM32_USART3_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_UART4 TRUE -#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3)) -#define STM32_UART4_RX_DMA_CHN 0x00000000 -#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5)) -#define STM32_UART4_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_UART5 TRUE -#define STM32_UART5_RX_DMA_MSK 0 -#define STM32_UART5_RX_DMA_CHN 0x00000000 -#define STM32_UART5_TX_DMA_MSK 0 -#define STM32_UART5_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART6 FALSE -#define STM32_USART6_RX_DMA_MSK 0 -#define STM32_USART6_RX_DMA_CHN 0x00000000 -#define STM32_USART6_TX_DMA_MSK 0 -#define STM32_USART6_TX_DMA_CHN 0x00000000 - -/* USB attributes.*/ -#define STM32_HAS_USB TRUE -#define STM32_HAS_OTG1 FALSE -#define STM32_HAS_OTG2 FALSE -/** @} */ -#endif /* defined(STM32F10X_XL) */ - -/*===========================================================================*/ -/* Platform specific friendly IRQ names. */ -/*===========================================================================*/ - -/** - * @name IRQ VECTOR names - * @{ - */ -#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */ -#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line - detect. */ -#define TAMPER_IRQHandler Vector48 /**< Tamper. */ -#define RTC_IRQHandler Vector4C /**< RTC. */ -#define FLASH_IRQHandler Vector50 /**< Flash. */ -#define RCC_IRQHandler Vector54 /**< RCC. */ -#define EXTI0_IRQHandler Vector58 /**< EXTI Line 0. */ -#define EXTI1_IRQHandler Vector5C /**< EXTI Line 1. */ -#define EXTI2_IRQHandler Vector60 /**< EXTI Line 2. */ -#define EXTI3_IRQHandler Vector64 /**< EXTI Line 3. */ -#define EXTI4_IRQHandler Vector68 /**< EXTI Line 4. */ -#define DMA1_Ch1_IRQHandler Vector6C /**< DMA1 Channel 1. */ -#define DMA1_Ch2_IRQHandler Vector70 /**< DMA1 Channel 2. */ -#define DMA1_Ch3_IRQHandler Vector74 /**< DMA1 Channel 3. */ -#define DMA1_Ch4_IRQHandler Vector78 /**< DMA1 Channel 4. */ -#define DMA1_Ch5_IRQHandler Vector7C /**< DMA1 Channel 5. */ -#define DMA1_Ch6_IRQHandler Vector80 /**< DMA1 Channel 6. */ -#define DMA1_Ch7_IRQHandler Vector84 /**< DMA1 Channel 7. */ -#define ADC1_2_IRQHandler Vector88 /**< ADC1_2. */ -#define CAN1_TX_IRQHandler Vector8C /**< CAN1 TX. */ -#define USB_HP_IRQHandler Vector8C /**< USB High Priority, CAN1 TX.*/ -#define CAN1_RX0_IRQHandler Vector90 /**< CAN1 RX0. */ -#define USB_LP_IRQHandler Vector90 /**< USB Low Priority, CAN1 RX0.*/ -#define CAN1_RX1_IRQHandler Vector94 /**< CAN1 RX1. */ -#define CAN1_SCE_IRQHandler Vector98 /**< CAN1 SCE. */ -#define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */ -#define TIM1_BRK_IRQHandler VectorA0 /**< TIM1 Break. */ -#define TIM1_UP_IRQHandler VectorA4 /**< TIM1 Update. */ -#define TIM1_TRG_COM_IRQHandler VectorA8 /**< TIM1 Trigger and - Commutation. */ -#define TIM1_CC_IRQHandler VectorAC /**< TIM1 Capture Compare. */ -#define TIM2_IRQHandler VectorB0 /**< TIM2. */ -#define TIM3_IRQHandler VectorB4 /**< TIM3. */ -#define TIM4_IRQHandler VectorB8 /**< TIM4. */ -#define I2C1_EV_IRQHandler VectorBC /**< I2C1 Event. */ -#define I2C1_ER_IRQHandler VectorC0 /**< I2C1 Error. */ -#define I2C2_EV_IRQHandler VectorC4 /**< I2C2 Event. */ -#define I2C2_ER_IRQHandler VectorC8 /**< I2C2 Error. */ -#define SPI1_IRQHandler VectorCC /**< SPI1. */ -#define SPI2_IRQHandler VectorD0 /**< SPI2. */ -#define USART1_IRQHandler VectorD4 /**< USART1. */ -#define USART2_IRQHandler VectorD8 /**< USART2. */ -#define USART3_IRQHandler VectorDC /**< USART3. */ -#define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */ -#define RTC_Alarm_IRQHandler VectorE4 /**< RTC Alarm through EXTI. */ -#define USB_FS_WKUP_IRQHandler VectorE8 /**< USB Wakeup from suspend. */ -#define TIM8_BRK_IRQHandler VectorEC /**< TIM8 Break. */ -#define TIM8_UP_IRQHandler VectorF0 /**< TIM8 Update. */ -#define TIM8_TRG_COM_IRQHandler VectorF4 /**< TIM8 Trigger and - Commutation. */ -#define TIM8_CC_IRQHandler VectorF8 /**< TIM8 Capture Compare. */ -#define ADC3_IRQHandler VectorFC /**< ADC3. */ -#define FSMC_IRQHandler Vector100 /**< FSMC. */ -#define SDIO_IRQHandler Vector104 /**< SDIO. */ -#define TIM5_IRQHandler Vector108 /**< TIM5. */ -#define SPI3_IRQHandler Vector10C /**< SPI3. */ -#define UART4_IRQHandler Vector110 /**< UART4. */ -#define UART5_IRQHandler Vector114 /**< UART5. */ -#define TIM6_IRQHandler Vector118 /**< TIM6. */ -#define TIM7_IRQHandler Vector11C /**< TIM7. */ -#define DMA2_Ch1_IRQHandler Vector120 /**< DMA2 Channel1. */ -#define DMA2_Ch2_IRQHandler Vector124 /**< DMA2 Channel2. */ -#define DMA2_Ch3_IRQHandler Vector128 /**< DMA2 Channel3. */ -#define DMA2_Ch4_5_IRQHandler Vector12C /**< DMA2 Channel4 & Channel5. */ -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief Main clock source selection. - * @note If the selected clock source is not the PLL then the PLL is not - * initialized and started. - * @note The default value is calculated for a 72MHz system clock from - * a 8MHz crystal using the PLL. - */ -#if !defined(STM32_SW) || defined(__DOXYGEN__) -#define STM32_SW STM32_SW_PLL -#endif - -/** - * @brief Clock source for the PLL. - * @note This setting has only effect if the PLL is selected as the - * system clock source. - * @note The default value is calculated for a 72MHz system clock from - * a 8MHz crystal using the PLL. - */ -#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__) -#define STM32_PLLSRC STM32_PLLSRC_HSE -#endif - -/** - * @brief Crystal PLL pre-divider. - * @note This setting has only effect if the PLL is selected as the - * system clock source. - * @note The default value is calculated for a 72MHz system clock from - * a 8MHz crystal using the PLL. - */ -#if !defined(STM32_PLLXTPRE) || defined(__DOXYGEN__) -#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 -#endif - -/** - * @brief PLL multiplier value. - * @note The allowed range is 2...16. - * @note The default value is calculated for a 72MHz system clock from - * a 8MHz crystal using the PLL. - */ -#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLMUL_VALUE 9 -#endif - -/** - * @brief AHB prescaler value. - * @note The default value is calculated for a 72MHz system clock from - * a 8MHz crystal using the PLL. - */ -#if !defined(STM32_HPRE) || defined(__DOXYGEN__) -#define STM32_HPRE STM32_HPRE_DIV1 -#endif - -/** - * @brief APB1 prescaler value. - */ -#if !defined(STM32_PPRE1) || defined(__DOXYGEN__) -#define STM32_PPRE1 STM32_PPRE1_DIV2 -#endif - -/** - * @brief APB2 prescaler value. - */ -#if !defined(STM32_PPRE2) || defined(__DOXYGEN__) -#define STM32_PPRE2 STM32_PPRE2_DIV2 -#endif - -/** - * @brief ADC prescaler value. - */ -#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__) -#define STM32_ADCPRE STM32_ADCPRE_DIV4 -#endif - -/** - * @brief USB clock setting. - */ -#if !defined(STM32_USB_CLOCK_REQUIRED) || defined(__DOXYGEN__) -#define STM32_USB_CLOCK_REQUIRED TRUE -#endif - -/** - * @brief USB prescaler initialization. - */ -#if !defined(STM32_USBPRE) || defined(__DOXYGEN__) -#define STM32_USBPRE STM32_USBPRE_DIV1P5 -#endif - -/** - * @brief MCO pin setting. - */ -#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__) -#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK -#endif - -/** - * @brief RTC clock source. - */ -#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__) -#define STM32_RTCSEL STM32_RTCSEL_LSI -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/* - * Configuration-related checks. - */ -#if !defined(STM32F103_MCUCONF) -#error "Using a wrong mcuconf.h file, STM32F103_MCUCONF not defined" -#endif - -/* - * HSI related checks. - */ -#if STM32_HSI_ENABLED -#else /* !STM32_HSI_ENABLED */ - -#if STM32_SW == STM32_SW_HSI -#error "HSI not enabled, required by STM32_SW" -#endif - -#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI) -#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC" -#endif - -#if (STM32_MCOSEL == STM32_MCOSEL_HSI) || \ - ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \ - (STM32_PLLSRC == STM32_PLLSRC_HSI)) -#error "HSI not enabled, required by STM32_MCOSEL" -#endif - -#endif /* !STM32_HSI_ENABLED */ - -/* - * HSE related checks. - */ -#if STM32_HSE_ENABLED - -#if STM32_HSECLK == 0 -#error "HSE frequency not defined" -#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX) -#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)" -#endif - -#else /* !STM32_HSE_ENABLED */ - -#if STM32_SW == STM32_SW_HSE -#error "HSE not enabled, required by STM32_SW" -#endif - -#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE) -#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC" -#endif - -#if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \ - ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \ - (STM32_PLLSRC == STM32_PLLSRC_HSE)) -#error "HSE not enabled, required by STM32_MCOSEL" -#endif - -#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV -#error "HSE not enabled, required by STM32_RTCSEL" -#endif - -#endif /* !STM32_HSE_ENABLED */ - -/* - * LSI related checks. - */ -#if STM32_LSI_ENABLED -#else /* !STM32_LSI_ENABLED */ - -#if STM32_RTCSEL == STM32_RTCSEL_LSI -#error "LSI not enabled, required by STM32_RTCSEL" -#endif - -#endif /* !STM32_LSI_ENABLED */ - -/* - * LSE related checks. - */ -#if STM32_LSE_ENABLED - -#if (STM32_LSECLK == 0) -#error "LSE frequency not defined" -#endif - -#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX) -#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)" -#endif - -#else /* !STM32_LSE_ENABLED */ - -#if STM32_RTCSEL == STM32_RTCSEL_LSE -#error "LSE not enabled, required by STM32_RTCSEL" -#endif - -#endif /* !STM32_LSE_ENABLED */ - -/* PLL activation conditions.*/ -#if STM32_USB_CLOCK_REQUIRED || \ - (STM32_SW == STM32_SW_PLL) || \ - (STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) || \ - defined(__DOXYGEN__) -/** - * @brief PLL activation flag. - */ -#define STM32_ACTIVATE_PLL TRUE -#else -#define STM32_ACTIVATE_PLL FALSE -#endif - -/* HSE prescaler setting check.*/ -#if (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV1) && \ - (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV2) -#error "invalid STM32_PLLXTPRE value specified" -#endif - -/** - * @brief PLLMUL field. - */ -#if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) || \ - defined(__DOXYGEN__) -#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18) -#else -#error "invalid STM32_PLLMUL_VALUE value specified" -#endif - -/** - * @brief PLL input clock frequency. - */ -#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) -#if STM32_PLLXTPRE == STM32_PLLXTPRE_DIV1 -#define STM32_PLLCLKIN (STM32_HSECLK / 1) -#else -#define STM32_PLLCLKIN (STM32_HSECLK / 2) -#endif -#elif STM32_PLLSRC == STM32_PLLSRC_HSI -#define STM32_PLLCLKIN (STM32_HSICLK / 2) -#else -#error "invalid STM32_PLLSRC value specified" -#endif - -/* PLL input frequency range check.*/ -#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX) -#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)" -#endif - -/** - * @brief PLL output clock frequency. - */ -#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE) - -/* PLL output frequency range check.*/ -#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX) -#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)" -#endif - -/** - * @brief System clock source. - */ -#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__) -#define STM32_SYSCLK STM32_PLLCLKOUT -#elif (STM32_SW == STM32_SW_HSI) -#define STM32_SYSCLK STM32_HSICLK -#elif (STM32_SW == STM32_SW_HSE) -#define STM32_SYSCLK STM32_HSECLK -#else -#error "invalid STM32_SW value specified" -#endif - -/* Check on the system clock.*/ -#if STM32_SYSCLK > STM32_SYSCLK_MAX -#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)" -#endif - -/** - * @brief AHB frequency. - */ -#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__) -#define STM32_HCLK (STM32_SYSCLK / 1) -#elif STM32_HPRE == STM32_HPRE_DIV2 -#define STM32_HCLK (STM32_SYSCLK / 2) -#elif STM32_HPRE == STM32_HPRE_DIV4 -#define STM32_HCLK (STM32_SYSCLK / 4) -#elif STM32_HPRE == STM32_HPRE_DIV8 -#define STM32_HCLK (STM32_SYSCLK / 8) -#elif STM32_HPRE == STM32_HPRE_DIV16 -#define STM32_HCLK (STM32_SYSCLK / 16) -#elif STM32_HPRE == STM32_HPRE_DIV64 -#define STM32_HCLK (STM32_SYSCLK / 64) -#elif STM32_HPRE == STM32_HPRE_DIV128 -#define STM32_HCLK (STM32_SYSCLK / 128) -#elif STM32_HPRE == STM32_HPRE_DIV256 -#define STM32_HCLK (STM32_SYSCLK / 256) -#elif STM32_HPRE == STM32_HPRE_DIV512 -#define STM32_HCLK (STM32_SYSCLK / 512) -#else -#error "invalid STM32_HPRE value specified" -#endif - -/* AHB frequency check.*/ -#if STM32_HCLK > STM32_SYSCLK_MAX -#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)" -#endif - -/** - * @brief APB1 frequency. - */ -#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) -#define STM32_PCLK1 (STM32_HCLK / 1) -#elif STM32_PPRE1 == STM32_PPRE1_DIV2 -#define STM32_PCLK1 (STM32_HCLK / 2) -#elif STM32_PPRE1 == STM32_PPRE1_DIV4 -#define STM32_PCLK1 (STM32_HCLK / 4) -#elif STM32_PPRE1 == STM32_PPRE1_DIV8 -#define STM32_PCLK1 (STM32_HCLK / 8) -#elif STM32_PPRE1 == STM32_PPRE1_DIV16 -#define STM32_PCLK1 (STM32_HCLK / 16) -#else -#error "invalid STM32_PPRE1 value specified" -#endif - -/* APB1 frequency check.*/ -#if STM32_PCLK1 > STM32_PCLK1_MAX -#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)" -#endif - -/** - * @brief APB2 frequency. - */ -#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) -#define STM32_PCLK2 (STM32_HCLK / 1) -#elif STM32_PPRE2 == STM32_PPRE2_DIV2 -#define STM32_PCLK2 (STM32_HCLK / 2) -#elif STM32_PPRE2 == STM32_PPRE2_DIV4 -#define STM32_PCLK2 (STM32_HCLK / 4) -#elif STM32_PPRE2 == STM32_PPRE2_DIV8 -#define STM32_PCLK2 (STM32_HCLK / 8) -#elif STM32_PPRE2 == STM32_PPRE2_DIV16 -#define STM32_PCLK2 (STM32_HCLK / 16) -#else -#error "invalid STM32_PPRE2 value specified" -#endif - -/* APB2 frequency check.*/ -#if STM32_PCLK2 > STM32_PCLK2_MAX -#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)" -#endif - -/** - * @brief RTC clock. - */ -#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__) -#define STM32_RTCCLK STM32_LSECLK -#elif STM32_RTCSEL == STM32_RTCSEL_LSI -#define STM32_RTCCLK STM32_LSICLK -#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV -#define STM32_RTCCLK (STM32_HSECLK / 128) -#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK -#define STM32_RTCCLK 0 -#else -#error "invalid source selected for RTC clock" -#endif - -/** - * @brief ADC frequency. - */ -#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__) -#define STM32_ADCCLK (STM32_PCLK2 / 2) -#elif STM32_ADCPRE == STM32_ADCPRE_DIV4 -#define STM32_ADCCLK (STM32_PCLK2 / 4) -#elif STM32_ADCPRE == STM32_ADCPRE_DIV6 -#define STM32_ADCCLK (STM32_PCLK2 / 6) -#elif STM32_ADCPRE == STM32_ADCPRE_DIV8 -#define STM32_ADCCLK (STM32_PCLK2 / 8) -#else -#error "invalid STM32_ADCPRE value specified" -#endif - -/* ADC frequency check.*/ -#if STM32_ADCCLK > STM32_ADCCLK_MAX -#error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MAX)" -#endif - -/** - * @brief USB frequency. - */ -#if (STM32_USBPRE == STM32_USBPRE_DIV1P5) || defined(__DOXYGEN__) -#define STM32_USBCLK ((STM32_PLLCLKOUT * 2) / 3) -#elif (STM32_USBPRE == STM32_USBPRE_DIV1) -#define STM32_USBCLK STM32_PLLCLKOUT -#else -#error "invalid STM32_USBPRE value specified" -#endif - -/** - * @brief Timers 2, 3, 4, 5, 6, 7, 12, 13, 14 clock. - */ -#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) -#define STM32_TIMCLK1 (STM32_PCLK1 * 1) -#else -#define STM32_TIMCLK1 (STM32_PCLK1 * 2) -#endif - -/** - * @brief Timers 1, 8, 9, 10, 11 clock. - */ -#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) -#define STM32_TIMCLK2 (STM32_PCLK2 * 1) -#else -#define STM32_TIMCLK2 (STM32_PCLK2 * 2) -#endif - -/** - * @brief Flash settings. - */ -#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__) -#define STM32_FLASHBITS 0x00000010 -#elif STM32_HCLK <= 48000000 -#define STM32_FLASHBITS 0x00000011 -#else -#define STM32_FLASHBITS 0x00000012 -#endif - -#endif /* _HAL_LLD_F103_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h b/firmware/chibios/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h deleted file mode 100644 index 10913c0271..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h +++ /dev/null @@ -1,1050 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @defgroup STM32F10X_CL_HAL STM32F105/F107 HAL Support - * @details HAL support for STM32 Connectivity Line sub-family. - * - * @ingroup HAL - */ - -/** - * @file STM32F1xx/hal_lld_f105_f107.h - * @brief STM32F10x Connectivity Line HAL subsystem low level driver header. - * - * @addtogroup STM32F10X_CL_HAL - * @{ - */ - -#ifndef _HAL_LLD_F105_F107_H_ -#define _HAL_LLD_F105_F107_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name Platform identification - * @{ - */ -#define PLATFORM_NAME "STM32F10x Connectivity Line" -/** @} */ - -/** - * @name Absolute Maximum Ratings - * @{ - */ -/** - * @brief Maximum system clock frequency. - */ -#define STM32_SYSCLK_MAX 72000000 - -/** - * @brief Maximum HSE clock frequency. - */ -#define STM32_HSECLK_MAX 50000000 - -/** - * @brief Minimum HSE clock frequency. - */ -#define STM32_HSECLK_MIN 1000000 - -/** - * @brief Maximum LSE clock frequency. - */ -#define STM32_LSECLK_MAX 1000000 - -/** - * @brief Minimum LSE clock frequency. - */ -#define STM32_LSECLK_MIN 32768 - -/** - * @brief Maximum PLLs input clock frequency. - */ -#define STM32_PLL1IN_MAX 12000000 - -/** - * @brief Maximum PLL1 input clock frequency. - */ -#define STM32_PLL1IN_MIN 3000000 - -/** - * @brief Maximum PLL1 input clock frequency. - */ -#define STM32_PLL23IN_MAX 5000000 - -/** - * @brief Maximum PLL2 and PLL3 input clock frequency. - */ -#define STM32_PLL23IN_MIN 3000000 - -/** - * @brief Maximum PLL1 VCO clock frequency. - */ -#define STM32_PLL1VCO_MAX 144000000 - -/** - * @brief Maximum PLL1 VCO clock frequency. - */ -#define STM32_PLL1VCO_MIN 36000000 - -/** - * @brief Maximum PLL2 and PLL3 VCO clock frequency. - */ -#define STM32_PLL23VCO_MAX 148000000 - -/** - * @brief Maximum PLL2 and PLL3 VCO clock frequency. - */ -#define STM32_PLL23VCO_MIN 80000000 - -/** - * @brief Maximum APB1 clock frequency. - */ -#define STM32_PCLK1_MAX 36000000 - -/** - * @brief Maximum APB2 clock frequency. - */ -#define STM32_PCLK2_MAX 72000000 - -/** - * @brief Maximum ADC clock frequency. - */ -#define STM32_ADCCLK_MAX 14000000 - -/** - * @brief Maximum SPI/I2S clock frequency. - */ -#define STM32_SPII2S_MAX 18000000 -/** @} */ - -/** - * @name RCC_CFGR register bits definitions - * @{ - */ -#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */ -#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */ -#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */ - -#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */ -#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */ -#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */ -#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */ -#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */ -#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */ -#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */ -#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */ -#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */ - -#define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */ -#define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */ -#define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */ -#define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */ -#define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */ - -#define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */ -#define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */ -#define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */ -#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */ -#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */ - -#define STM32_ADCPRE_DIV2 (0 << 14) /**< PPRE2 divided by 2. */ -#define STM32_ADCPRE_DIV4 (1 << 14) /**< PPRE2 divided by 4. */ -#define STM32_ADCPRE_DIV6 (2 << 14) /**< PPRE2 divided by 6. */ -#define STM32_ADCPRE_DIV8 (3 << 14) /**< PPRE2 divided by 8. */ - -#define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */ -#define STM32_PLLSRC_PREDIV1 (1 << 16) /**< PLL clock source is - PREDIV1. */ - -#define STM32_OTGFSPRE_DIV2 (1 << 22) /**< HCLK*2 divided by 2. */ -#define STM32_OTGFSPRE_DIV3 (0 << 22) /**< HCLK*2 divided by 3. */ - -#define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */ -#define STM32_MCOSEL_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */ -#define STM32_MCOSEL_HSI (5 << 24) /**< HSI clock on MCO pin. */ -#define STM32_MCOSEL_HSE (6 << 24) /**< HSE clock on MCO pin. */ -#define STM32_MCOSEL_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */ -#define STM32_MCOSEL_PLL2 (8 << 24) /**< PLL2 clock on MCO pin. */ -#define STM32_MCOSEL_PLL3DIV2 (9 << 24) /**< PLL3/2 clock on MCO pin. */ -#define STM32_MCOSEL_XT1 (10 << 24) /**< XT1 clock on MCO pin. */ -#define STM32_MCOSEL_PLL3 (11 << 24) /**< PLL3 clock on MCO pin. */ -/** @} */ - -/** - * @name RCC_BDCR register bits definitions - * @{ - */ -#define STM32_RTCSEL_MASK (3 << 8) /**< RTC clock source mask. */ -#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No clock. */ -#define STM32_RTCSEL_LSE (1 << 8) /**< LSE used as RTC clock. */ -#define STM32_RTCSEL_LSI (2 << 8) /**< LSI used as RTC clock. */ -#define STM32_RTCSEL_HSEDIV (3 << 8) /**< HSE divided by 128 used as - RTC clock. */ -/** @} */ - -/** - * @name RCC_CFGR2 register bits definitions - * @{ - */ -#define STM32_PREDIV1SRC_HSE (0 << 16) /**< PREDIV1 source is HSE. */ -#define STM32_PREDIV1SRC_PLL2 (1 << 16) /**< PREDIV1 source is PLL2. */ -/** @} */ - -/*===========================================================================*/ -/* Platform capabilities. */ -/*===========================================================================*/ - -/** - * @name STM32F105/F107 CL capabilities - * @{ - */ -/* ADC attributes.*/ -#define STM32_HAS_ADC1 TRUE -#define STM32_HAS_ADC2 TRUE -#define STM32_HAS_ADC3 FALSE -#define STM32_HAS_ADC4 FALSE - -/* CAN attributes.*/ -#define STM32_HAS_CAN1 TRUE -#define STM32_HAS_CAN2 TRUE -#define STM32_CAN_MAX_FILTERS 28 - -/* DAC attributes.*/ -#define STM32_HAS_DAC TRUE - -/* DMA attributes.*/ -#define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 TRUE - -/* ETH attributes.*/ -#define STM32_HAS_ETH TRUE - -/* EXTI attributes.*/ -#define STM32_EXTI_NUM_CHANNELS 20 - -/* GPIO attributes.*/ -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE TRUE -#define STM32_HAS_GPIOF FALSE -#define STM32_HAS_GPIOG FALSE -#define STM32_HAS_GPIOH FALSE -#define STM32_HAS_GPIOI FALSE - -/* I2C attributes.*/ -#define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_I2C1_RX_DMA_CHN 0x00000000 -#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_I2C1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_I2C2 TRUE -#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_I2C2_RX_DMA_CHN 0x00000000 -#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_I2C2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_I2C3 FALSE -#define STM32_I2C3_RX_DMA_MSK 0 -#define STM32_I2C3_RX_DMA_CHN 0x00000000 -#define STM32_I2C3_TX_DMA_MSK 0 -#define STM32_I2C3_TX_DMA_CHN 0x00000000 - -/* SDIO attributes.*/ -#define STM32_HAS_SDIO FALSE - -/* SPI attributes.*/ -#define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) -#define STM32_SPI1_RX_DMA_CHN 0x00000000 -#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) -#define STM32_SPI1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI2 TRUE -#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) -#define STM32_SPI2_RX_DMA_CHN 0x00000000 -#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) -#define STM32_SPI2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI3 TRUE -#define STM32_SPI3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 1) -#define STM32_SPI3_RX_DMA_CHN 0x00000000 -#define STM32_SPI3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 2) -#define STM32_SPI3_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI4 FALSE -#define STM32_HAS_SPI5 FALSE -#define STM32_HAS_SPI6 FALSE - -/* TIM attributes.*/ -#define STM32_HAS_TIM1 TRUE -#define STM32_HAS_TIM2 TRUE -#define STM32_HAS_TIM3 TRUE -#define STM32_HAS_TIM4 TRUE -#define STM32_HAS_TIM5 TRUE -#define STM32_HAS_TIM6 TRUE -#define STM32_HAS_TIM7 TRUE -#define STM32_HAS_TIM8 FALSE -#define STM32_HAS_TIM9 FALSE -#define STM32_HAS_TIM10 FALSE -#define STM32_HAS_TIM11 FALSE -#define STM32_HAS_TIM12 FALSE -#define STM32_HAS_TIM13 FALSE -#define STM32_HAS_TIM14 FALSE -#define STM32_HAS_TIM15 FALSE -#define STM32_HAS_TIM16 FALSE -#define STM32_HAS_TIM17 FALSE -#define STM32_HAS_TIM18 FALSE -#define STM32_HAS_TIM19 FALSE - -/* USART attributes.*/ -#define STM32_HAS_USART1 TRUE -#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_USART1_RX_DMA_CHN 0x00000000 -#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_USART1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART2 TRUE -#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_USART2_RX_DMA_CHN 0x00000000 -#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_USART2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART3 TRUE -#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) -#define STM32_USART3_RX_DMA_CHN 0x00000000 -#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) -#define STM32_USART3_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_UART4 TRUE -#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3)) -#define STM32_UART4_RX_DMA_CHN 0x00000000 -#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5)) -#define STM32_UART4_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_UART5 TRUE -#define STM32_UART5_RX_DMA_MSK 0 -#define STM32_UART5_RX_DMA_CHN 0x00000000 -#define STM32_UART5_TX_DMA_MSK 0 -#define STM32_UART5_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART6 FALSE -#define STM32_USART6_RX_DMA_MSK 0 -#define STM32_USART6_RX_DMA_CHN 0x00000000 -#define STM32_USART6_TX_DMA_MSK 0 -#define STM32_USART6_TX_DMA_CHN 0x00000000 - -/* USB attributes.*/ -#define STM32_HAS_USB FALSE -#define STM32_HAS_OTG1 TRUE -#define STM32_HAS_OTG2 FALSE -/** @} */ - -/*===========================================================================*/ -/* Platform specific friendly IRQ names. */ -/*===========================================================================*/ - -/** - * @name IRQ VECTOR names - * @{ - */ -#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */ -#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line - detect. */ -#define TAMPER_IRQHandler Vector48 /**< Tamper. */ -#define RTC_IRQHandler Vector4C /**< RTC. */ -#define FLASH_IRQHandler Vector50 /**< Flash. */ -#define RCC_IRQHandler Vector54 /**< RCC. */ -#define EXTI0_IRQHandler Vector58 /**< EXTI Line 0. */ -#define EXTI1_IRQHandler Vector5C /**< EXTI Line 1. */ -#define EXTI2_IRQHandler Vector60 /**< EXTI Line 2. */ -#define EXTI3_IRQHandler Vector64 /**< EXTI Line 3. */ -#define EXTI4_IRQHandler Vector68 /**< EXTI Line 4. */ -#define DMA1_Ch1_IRQHandler Vector6C /**< DMA1 Channel 1. */ -#define DMA1_Ch2_IRQHandler Vector70 /**< DMA1 Channel 2. */ -#define DMA1_Ch3_IRQHandler Vector74 /**< DMA1 Channel 3. */ -#define DMA1_Ch4_IRQHandler Vector78 /**< DMA1 Channel 4. */ -#define DMA1_Ch5_IRQHandler Vector7C /**< DMA1 Channel 5. */ -#define DMA1_Ch6_IRQHandler Vector80 /**< DMA1 Channel 6. */ -#define DMA1_Ch7_IRQHandler Vector84 /**< DMA1 Channel 7. */ -#define ADC1_2_IRQHandler Vector88 /**< ADC1 and ADC2. */ -#define CAN1_TX_IRQHandler Vector8C /**< CAN1 TX. */ -#define CAN1_RX0_IRQHandler Vector90 /**< CAN1 RX0. */ -#define CAN1_RX1_IRQHandler Vector94 /**< CAN1 RX1. */ -#define CAN1_SCE_IRQHandler Vector98 /**< CAN1 SCE. */ -#define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */ -#define TIM1_BRK_IRQHandler VectorA0 /**< TIM1 Break. */ -#define TIM1_UP_IRQHandler VectorA4 /**< TIM1 Update. */ -#define TIM1_TRG_COM_IRQHandler VectorA8 /**< TIM1 Trigger and - Commutation. */ -#define TIM1_CC_IRQHandler VectorAC /**< TIM1 Capture Compare. */ -#define TIM2_IRQHandler VectorB0 /**< TIM2. */ -#define TIM3_IRQHandler VectorB4 /**< TIM3. */ -#define TIM4_IRQHandler VectorB8 /**< TIM4. */ -#define I2C1_EV_IRQHandler VectorBC /**< I2C1 Event. */ -#define I2C1_ER_IRQHandler VectorC0 /**< I2C1 Error. */ -#define I2C2_EV_IRQHandler VectorC4 /**< I2C2 Event. */ -#define I2C2_ER_IRQHandler VectorC8 /**< I2C1 Error. */ -#define SPI1_IRQHandler VectorCC /**< SPI1. */ -#define SPI2_IRQHandler VectorD0 /**< SPI2. */ -#define USART1_IRQHandler VectorD4 /**< USART1. */ -#define USART2_IRQHandler VectorD8 /**< USART2. */ -#define USART3_IRQHandler VectorDC /**< USART3. */ -#define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */ -#define RTC_Alarm_IRQHandler VectorE4 /**< RTC alarm through EXTI - line. */ -#define OTG_FS_WKUP_IRQHandler VectorE8 /**< USB OTG FS Wakeup through - EXTI line. */ -#define TIM5_IRQHandler Vector108 /**< TIM5. */ -#define SPI3_IRQHandler Vector10C /**< SPI3. */ -#define UART4_IRQHandler Vector110 /**< UART4. */ -#define UART5_IRQHandler Vector114 /**< UART5. */ -#define TIM6_IRQHandler Vector118 /**< TIM6. */ -#define TIM7_IRQHandler Vector11C /**< TIM7. */ -#define DMA2_Ch1_IRQHandler Vector120 /**< DMA2 Channel1. */ -#define DMA2_Ch2_IRQHandler Vector124 /**< DMA2 Channel2. */ -#define DMA2_Ch3_IRQHandler Vector128 /**< DMA2 Channel3. */ -#define DMA2_Ch4_IRQHandler Vector12C /**< DMA2 Channel4. */ -#define DMA2_Ch5_IRQHandler Vector130 /**< DMA2 Channel5. */ -#define ETH_IRQHandler Vector134 /**< Ethernet. */ -#define ETH_WKUP_IRQHandler Vector138 /**< Ethernet Wakeup through - EXTI line. */ -#define CAN2_TX_IRQHandler Vector13C /**< CAN2 TX. */ -#define CAN2_RX0_IRQHandler Vector140 /**< CAN2 RX0. */ -#define CAN2_RX1_IRQHandler Vector144 /**< CAN2 RX1. */ -#define CAN2_SCE_IRQHandler Vector148 /**< CAN2 SCE. */ -#define OTG_FS_IRQHandler Vector14C /**< USB OTG FS. */ -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief Main clock source selection. - * @note The default value is calculated for a 72MHz system clock from - * a 25MHz crystal using both PLL and PLL2. - */ -#if !defined(STM32_SW) || defined(__DOXYGEN__) -#define STM32_SW STM32_SW_PLL -#endif - -/** - * @brief Clock source for the PLL. - * @note The default value is calculated for a 72MHz system clock from - * a 25MHz crystal using both PLL and PLL2. - */ -#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__) -#define STM32_PLLSRC STM32_PLLSRC_PREDIV1 -#endif - -/** - * @brief PREDIV1 clock source. - * @note The default value is calculated for a 72MHz system clock from - * a 25MHz crystal using both PLL and PLL2. - */ -#if !defined(STM32_PREDIV1SRC) || defined(__DOXYGEN__) -#define STM32_PREDIV1SRC STM32_PREDIV1SRC_HSE -#endif - -/** - * @brief PREDIV1 division factor. - * @note The allowed range is 1...16. - * @note The default value is calculated for a 72MHz system clock from - * a 25MHz crystal using both PLL and PLL2. - */ -#if !defined(STM32_PREDIV1_VALUE) || defined(__DOXYGEN__) -#define STM32_PREDIV1_VALUE 5 -#endif - -/** - * @brief PLL multiplier value. - * @note The allowed range is 4...9. - * @note The default value is calculated for a 72MHz system clock from - * a 25MHz crystal using both PLL and PLL2. - */ -#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLMUL_VALUE 9 -#endif - -/** - * @brief PREDIV2 division factor. - * @note The allowed range is 1...16. - * @note The default value is calculated for a 72MHz system clock from - * a 25MHz crystal using both PLL and PLL2. - */ -#if !defined(STM32_PREDIV2_VALUE) || defined(__DOXYGEN__) -#define STM32_PREDIV2_VALUE 5 -#endif - -/** - * @brief PLL2 multiplier value. - * @note The default value is calculated for a 72MHz system clock from - * a 25MHz crystal using both PLL and PLL2. - */ -#if !defined(STM32_PLL2MUL_VALUE) || defined(__DOXYGEN__) -#define STM32_PLL2MUL_VALUE 8 -#endif - -/** - * @brief PLL3 multiplier value. - * @note The default value is calculated for a 50MHz clock from - * a 25MHz crystal. - */ -#if !defined(STM32_PLL3MUL_VALUE) || defined(__DOXYGEN__) -#define STM32_PLL3MUL_VALUE 10 -#endif - -/** - * @brief AHB prescaler value. - * @note The default value is calculated for a 72MHz system clock from - * a 25MHz crystal using both PLL and PLL2. - */ -#if !defined(STM32_HPRE) || defined(__DOXYGEN__) -#define STM32_HPRE STM32_HPRE_DIV1 -#endif - -/** - * @brief APB1 prescaler value. - */ -#if !defined(STM32_PPRE1) || defined(__DOXYGEN__) -#define STM32_PPRE1 STM32_PPRE1_DIV2 -#endif - -/** - * @brief APB2 prescaler value. - */ -#if !defined(STM32_PPRE2) || defined(__DOXYGEN__) -#define STM32_PPRE2 STM32_PPRE2_DIV2 -#endif - -/** - * @brief ADC prescaler value. - */ -#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__) -#define STM32_ADCPRE STM32_ADCPRE_DIV4 -#endif - -/** - * @brief USB clock setting. - */ -#if !defined(STM32_OTG_CLOCK_REQUIRED) || defined(__DOXYGEN__) -#define STM32_OTG_CLOCK_REQUIRED TRUE -#endif - -/** - * @brief OTG prescaler initialization. - */ -#if !defined(STM32_OTGFSPRE) || defined(__DOXYGEN__) -#define STM32_OTGFSPRE STM32_OTGFSPRE_DIV3 -#endif - -/** - * @brief Dedicated I2S clock setting. - */ -#if !defined(STM32_I2S_CLOCK_REQUIRED) || defined(__DOXYGEN__) -#define STM32_I2S_CLOCK_REQUIRED FALSE -#endif - -/** - * @brief MCO pin setting. - */ -#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__) -#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK -#endif - -/** - * @brief RTC clock source. - */ -#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__) -#define STM32_RTCSEL STM32_RTCSEL_HSEDIV -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/* - * Configuration-related checks. - */ -#if !defined(STM32F107_MCUCONF) -#error "Using a wrong mcuconf.h file, STM32F107_MCUCONF not defined" -#endif - -/* - * HSI related checks. - */ -#if STM32_HSI_ENABLED -#else /* !STM32_HSI_ENABLED */ - -#if STM32_SW == STM32_SW_HSI -#error "HSI not enabled, required by STM32_SW" -#endif - -#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI) -#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC" -#endif - -#if (STM32_MCOSEL == STM32_MCOSEL_HSI) || \ - ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \ - (STM32_PLLSRC == STM32_PLLSRC_HSI)) -#error "HSI not enabled, required by STM32_MCOSEL" -#endif - -#endif /* !STM32_HSI_ENABLED */ - -/* - * HSE related checks. - */ -#if STM32_HSE_ENABLED - -#if STM32_HSECLK == 0 -#error "HSE frequency not defined" -#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX) -#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)" -#endif - -#else /* !STM32_HSE_ENABLED */ - -#if STM32_SW == STM32_SW_HSE -#error "HSE not enabled, required by STM32_SW" -#endif - -#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_PREDIV1) -#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC" -#endif - -#if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \ - ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \ - (STM32_PLLSRC == STM32_PLLSRC_HSE)) || \ - (STM32_MCOSEL == STM32_MCOSEL_PLL2DIV2) || \ - (STM32_MCOSEL == STM32_MCOSEL_PLL3DIV2) || \ - (STM32_MCOSEL == STM32_MCOSEL_XT1) -#error "HSE not enabled, required by STM32_MCOSEL" -#endif - -#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV -#error "HSE not enabled, required by STM32_RTCSEL" -#endif - -#endif /* !STM32_HSE_ENABLED */ - -/* - * LSI related checks. - */ -#if STM32_LSI_ENABLED -#else /* !STM32_LSI_ENABLED */ - -#if STM32_RTCSEL == STM32_RTCSEL_LSI -#error "LSI not enabled, required by STM32_RTCSEL" -#endif - -#endif /* !STM32_LSI_ENABLED */ - -/* - * LSE related checks. - */ -#if STM32_LSE_ENABLED - -#if (STM32_LSECLK == 0) -#error "LSE frequency not defined" -#endif - -#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX) -#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)" -#endif - -#else /* !STM32_LSE_ENABLED */ - -#if STM32_RTCSEL == STM32_RTCSEL_LSE -#error "LSE not enabled, required by STM32_RTCSEL" -#endif - -#endif /* !STM32_LSE_ENABLED */ - -/* PLL1 activation conditions.*/ -#if STM32_OTG_CLOCK_REQUIRED || \ - (STM32_SW == STM32_SW_PLL) || \ - (STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) || \ - defined(__DOXYGEN__) -/** - * @brief PLL1 activation flag. - */ -#define STM32_ACTIVATE_PLL1 TRUE -#else -#define STM32_ACTIVATE_PLL1 FALSE -#endif - -/* PLL2 activation conditions.*/ -#if ((STM32_PREDIV1SRC == STM32_PREDIV1SRC_PLL2) && STM32_ACTIVATE_PLL1) || \ - (STM32_MCOSEL == STM32_MCOSEL_PLL2DIV2) || \ - defined(__DOXYGEN__) -/** - * @brief PLL2 activation flag. - */ -#define STM32_ACTIVATE_PLL2 TRUE -#else -#define STM32_ACTIVATE_PLL2 FALSE -#endif - -/* PLL3 activation conditions.*/ -#if STM32_I2S_CLOCK_REQUIRED || \ - (STM32_MCOSEL == STM32_MCOSEL_PLL3DIV2) || \ - (STM32_MCOSEL == STM32_MCOSEL_PLL3) || \ - defined(__DOXYGEN__) -/** - * @brief PLL3 activation flag. - */ -#define STM32_ACTIVATE_PLL3 TRUE -#else -#define STM32_ACTIVATE_PLL3 FALSE -#endif - -/** - * @brief PREDIV1 field. - */ -#if (STM32_PREDIV1_VALUE >= 1) && (STM32_PREDIV1_VALUE <= 16) || \ - defined(__DOXYGEN__) -#define STM32_PREDIV1 ((STM32_PREDIV1_VALUE - 1) << 0) -#else -#error "invalid STM32_PREDIV1_VALUE value specified" -#endif - -/** - * @brief PREDIV2 field. - */ -#if (STM32_PREDIV2_VALUE >= 1) && (STM32_PREDIV2_VALUE <= 16) || \ - defined(__DOXYGEN__) -#define STM32_PREDIV2 ((STM32_PREDIV2_VALUE - 1) << 4) -#else -#error "invalid STM32_PREDIV2_VALUE value specified" -#endif - -/** - * @brief PLLMUL field. - */ -#if ((STM32_PLLMUL_VALUE >= 4) && (STM32_PLLMUL_VALUE <= 9)) || \ - defined(__DOXYGEN__) -#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18) -#else -#error "invalid STM32_PLLMUL_VALUE value specified" -#endif - -/** - * @brief PLL2MUL field. - */ -#if ((STM32_PLL2MUL_VALUE >= 8) && (STM32_PLL2MUL_VALUE <= 14)) || \ - defined(__DOXYGEN__) -#define STM32_PLL2MUL ((STM32_PLL2MUL_VALUE - 2) << 8) -#elif (STM32_PLL2MUL_VALUE == 16) -#define STM32_PLL2MUL (14 << 8) -#elif (STM32_PLL2MUL_VALUE == 20) -#define STM32_PLL2MUL (15 << 8) -#else -#error "invalid STM32_PLL2MUL_VALUE value specified" -#endif - -/** - * @brief PLL3MUL field. - */ -#if ((STM32_PLL3MUL_VALUE >= 8) && (STM32_PLL3MUL_VALUE <= 14)) || \ - defined(__DOXYGEN__) -#define STM32_PLL3MUL ((STM32_PLL3MUL_VALUE - 2) << 12) -#elif (STM32_PLL3MUL_VALUE == 16) -#define STM32_PLL3MUL (14 << 12) -#elif (STM32_PLL3MUL_VALUE == 20) -#define STM32_PLL3MUL (15 << 12) -#else -#error "invalid STM32_PLL3MUL_VALUE value specified" -#endif - -/** - * @brief PLL2 input frequency. - */ -#define STM32_PLL2CLKIN (STM32_HSECLK / STM32_PREDIV2_VALUE) - -/* PLL2 input frequency range check.*/ -#if (STM32_PLL2CLKIN < STM32_PLL23IN_MIN) || \ - (STM32_PLL2CLKIN > STM32_PLL23IN_MAX) -#error "STM32_PLL2CLKIN outside acceptable range (STM32_PLL23IN_MIN...STM32_PLL23IN_MAX)" -#endif - -/** - * @brief PLL2 output clock frequency. - */ -#define STM32_PLL2CLKOUT (STM32_PLL2CLKIN * STM32_PLL2MUL_VALUE) - -/** - * @brief PLL2 VCO clock frequency. - */ -#define STM32_PLL2VCO (STM32_PLL2CLKOUT * 2) - -/* PLL2 output frequency range check.*/ -#if (STM32_PLL2VCO < STM32_PLL23VCO_MIN) || \ - (STM32_PLL2VCO > STM32_PLL23VCO_MAX) -#error "STM32_PLL2VCO outside acceptable range (STM32_PLL23VCO_MIN...STM32_PLL23VCO_MAX)" -#endif - -/** - * @brief PLL3 input frequency. - */ -#define STM32_PLL3CLKIN (STM32_HSECLK / STM32_PREDIV2_VALUE) - -/* PLL3 input frequency range check.*/ -#if (STM32_PLL3CLKIN < STM32_PLL23IN_MIN) || \ - (STM32_PLL3CLKIN > STM32_PLL23IN_MAX) -#error "STM32_PLL3CLKIN outside acceptable range (STM32_PLL23IN_MIN...STM32_PLL23IN_MAX)" -#endif - -/** - * @brief PLL3 output clock frequency. - */ -#define STM32_PLL3CLKOUT (STM32_PLL3CLKIN * STM32_PLL3MUL_VALUE) - -/** - * @brief PLL3 VCO clock frequency. - */ -#define STM32_PLL3VCO (STM32_PLL3CLKOUT * 2) - -/* PLL3 output frequency range check.*/ -#if (STM32_PLL3VCO < STM32_PLL23VCO_MIN) || \ - (STM32_PLL3VCO > STM32_PLL23VCO_MAX) -#error "STM32_PLL3CLKOUT outside acceptable range (STM32_PLL23VCO_MIN...STM32_PLL23VCO_MAX)" -#endif - -/** - * @brief PREDIV1 input frequency. - */ -#if (STM32_PREDIV1SRC == STM32_PREDIV1SRC_HSE) || defined(__DOXYGEN__) -#define STM32_PREDIV1CLK STM32_HSECLK -#elif STM32_PREDIV1SRC == STM32_PREDIV1SRC_PLL2 -#define STM32_PREDIV1CLK STM32_PLL2CLKOUT -#else -#error "invalid STM32_PREDIV1SRC value specified" -#endif - -/** - * @brief PLL input clock frequency. - */ -#if (STM32_PLLSRC == STM32_PLLSRC_PREDIV1) || defined(__DOXYGEN__) -#define STM32_PLLCLKIN (STM32_PREDIV1CLK / STM32_PREDIV1_VALUE) -#elif STM32_PLLSRC == STM32_PLLSRC_HSI -#define STM32_PLLCLKIN (STM32_HSICLK / 2) -#else -#error "invalid STM32_PLLSRC value specified" -#endif - -/* PLL input frequency range check.*/ -#if (STM32_PLLCLKIN < STM32_PLL1IN_MIN) || (STM32_PLLCLKIN > STM32_PLL1IN_MAX) -#error "STM32_PLLCLKIN outside acceptable range (STM32_PLL1IN_MIN...STM32_PLL1IN_MAX)" -#endif - -/** - * @brief PLL output clock frequency. - */ -#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE) - -/** - * @brief PLL VCO clock frequency. - */ -#define STM32_PLLVCO (STM32_PLLCLKOUT * 2) - -/* PLL output frequency range check.*/ -#if (STM32_PLLVCO < STM32_PLL1VCO_MIN) || (STM32_PLLVCO > STM32_PLL1VCO_MAX) -#error "STM32_PLLVCO outside acceptable range (STM32_PLL1VCO_MIN...STM32_PLL1VCO_MAX)" -#endif - -/** - * @brief System clock source. - */ -#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__) -#define STM32_SYSCLK STM32_PLLCLKOUT -#elif (STM32_SW == STM32_SW_HSI) -#define STM32_SYSCLK STM32_HSICLK -#elif (STM32_SW == STM32_SW_HSE) -#define STM32_SYSCLK STM32_HSECLK -#else -#error "invalid STM32_SW value specified" -#endif - -/* Check on the system clock.*/ -#if STM32_SYSCLK > STM32_SYSCLK_MAX -#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)" -#endif - -/** - * @brief AHB frequency. - */ -#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__) -#define STM32_HCLK (STM32_SYSCLK / 1) -#elif STM32_HPRE == STM32_HPRE_DIV2 -#define STM32_HCLK (STM32_SYSCLK / 2) -#elif STM32_HPRE == STM32_HPRE_DIV4 -#define STM32_HCLK (STM32_SYSCLK / 4) -#elif STM32_HPRE == STM32_HPRE_DIV8 -#define STM32_HCLK (STM32_SYSCLK / 8) -#elif STM32_HPRE == STM32_HPRE_DIV16 -#define STM32_HCLK (STM32_SYSCLK / 16) -#elif STM32_HPRE == STM32_HPRE_DIV64 -#define STM32_HCLK (STM32_SYSCLK / 64) -#elif STM32_HPRE == STM32_HPRE_DIV128 -#define STM32_HCLK (STM32_SYSCLK / 128) -#elif STM32_HPRE == STM32_HPRE_DIV256 -#define STM32_HCLK (STM32_SYSCLK / 256) -#elif STM32_HPRE == STM32_HPRE_DIV512 -#define STM32_HCLK (STM32_SYSCLK / 512) -#else -#error "invalid STM32_HPRE value specified" -#endif - -/* AHB frequency check.*/ -#if STM32_HCLK > STM32_SYSCLK_MAX -#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)" -#endif - -/** - * @brief APB1 frequency. - */ -#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) -#define STM32_PCLK1 (STM32_HCLK / 1) -#elif STM32_PPRE1 == STM32_PPRE1_DIV2 -#define STM32_PCLK1 (STM32_HCLK / 2) -#elif STM32_PPRE1 == STM32_PPRE1_DIV4 -#define STM32_PCLK1 (STM32_HCLK / 4) -#elif STM32_PPRE1 == STM32_PPRE1_DIV8 -#define STM32_PCLK1 (STM32_HCLK / 8) -#elif STM32_PPRE1 == STM32_PPRE1_DIV16 -#define STM32_PCLK1 (STM32_HCLK / 16) -#else -#error "invalid STM32_PPRE1 value specified" -#endif - -/* APB1 frequency check.*/ -#if STM32_PCLK1 > STM32_PCLK1_MAX -#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)" -#endif - -/** - * @brief APB2 frequency. - */ -#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) -#define STM32_PCLK2 (STM32_HCLK / 1) -#elif STM32_PPRE2 == STM32_PPRE2_DIV2 -#define STM32_PCLK2 (STM32_HCLK / 2) -#elif STM32_PPRE2 == STM32_PPRE2_DIV4 -#define STM32_PCLK2 (STM32_HCLK / 4) -#elif STM32_PPRE2 == STM32_PPRE2_DIV8 -#define STM32_PCLK2 (STM32_HCLK / 8) -#elif STM32_PPRE2 == STM32_PPRE2_DIV16 -#define STM32_PCLK2 (STM32_HCLK / 16) -#else -#error "invalid STM32_PPRE2 value specified" -#endif - -/* APB2 frequency check.*/ -#if STM32_PCLK2 > STM32_PCLK2_MAX -#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)" -#endif - -/** - * @brief RTC clock. - */ -#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__) -#define STM32_RTCCLK STM32_LSECLK -#elif STM32_RTCSEL == STM32_RTCSEL_LSI -#define STM32_RTCCLK STM32_LSICLK -#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV -#define STM32_RTCCLK (STM32_HSECLK / 128) -#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK -#define STM32_RTCCLK 0 -#else -#error "invalid source selected for RTC clock" -#endif - -/** - * @brief ADC frequency. - */ -#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__) -#define STM32_ADCCLK (STM32_PCLK2 / 2) -#elif STM32_ADCPRE == STM32_ADCPRE_DIV4 -#define STM32_ADCCLK (STM32_PCLK2 / 4) -#elif STM32_ADCPRE == STM32_ADCPRE_DIV6 -#define STM32_ADCCLK (STM32_PCLK2 / 6) -#elif STM32_ADCPRE == STM32_ADCPRE_DIV8 -#define STM32_ADCCLK (STM32_PCLK2 / 8) -#else -#error "invalid STM32_ADCPRE value specified" -#endif - -/* ADC frequency check.*/ -#if STM32_ADCCLK > STM32_ADCCLK_MAX -#error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MAX)" -#endif - -/** - * @brief OTG frequency. - */ -#if (STM32_OTGFSPRE == STM32_OTGFSPRE_DIV3) || defined(__DOXYGEN__) -#define STM32_OTGFSCLK (STM32_PLLVCO / 3) -#elif (STM32_OTGFSPRE == STM32_OTGFSPRE_DIV2) -#define STM32_OTGFSCLK (STM32_PLLVCO / 2) -#else -#error "invalid STM32_OTGFSPRE value specified" -#endif - -/** - * @brief Timers 2, 3, 4, 5, 6, 7 clock. - */ -#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) -#define STM32_TIMCLK1 (STM32_PCLK1 * 1) -#else -#define STM32_TIMCLK1 (STM32_PCLK1 * 2) -#endif - -/** - * @brief Timers 1, 8 clock. - */ -#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) -#define STM32_TIMCLK2 (STM32_PCLK2 * 1) -#else -#define STM32_TIMCLK2 (STM32_PCLK2 * 2) -#endif - -/** - * @brief Flash settings. - */ -#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__) -#define STM32_FLASHBITS 0x00000010 -#elif STM32_HCLK <= 48000000 -#define STM32_FLASHBITS 0x00000011 -#else -#define STM32_FLASHBITS 0x00000012 -#endif - -#endif /* _HAL_LLD_F105_F107_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32F1xx/platform.dox b/firmware/chibios/os/hal/platforms/STM32F1xx/platform.dox deleted file mode 100644 index f5fb63d8a9..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F1xx/platform.dox +++ /dev/null @@ -1,398 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @defgroup STM32F1xx_DRIVERS STM32F1xx Drivers - * @details This section describes all the supported drivers on the STM32F1xx - * platform and the implementation details of the single drivers. - * - * @ingroup platforms - */ - -/** - * @defgroup STM32F1xx_HAL STM32F1xx Initialization Support - * @details The STM32F1xx HAL support is responsible for system initialization. - * - * @section stm32f1xx_hal_1 Supported HW resources - * - PLL1. - * - PLL2 (where present). - * - RCC. - * - Flash. - * . - * @section stm32f1xx_hal_2 STM32F1xx HAL driver implementation features - * - PLLs startup and stabilization. - * - Clock tree initialization. - * - Clock source selection. - * - Flash wait states initialization based on the selected clock options. - * - SYSTICK initialization based on current clock and kernel required rate. - * - DMA support initialization. - * . - * @ingroup STM32F1xx_DRIVERS - */ - -/** - * @defgroup STM32F1xx_ADC STM32F1xx ADC Support - * @details The STM32F1xx ADC driver supports the ADC peripherals using DMA - * channels for maximum performance. - * - * @section stm32f1xx_adc_1 Supported HW resources - * - ADC1. - * - DMA1. - * . - * @section stm32f1xx_adc_2 STM32F1xx ADC driver implementation features - * - Clock stop for reduced power usage when the driver is in stop state. - * - Streaming conversion using DMA for maximum performance. - * - Programmable ADC interrupt priority level. - * - Programmable DMA bus priority for each DMA channel. - * - Programmable DMA interrupt priority for each DMA channel. - * - DMA errors detection. - * . - * @ingroup STM32F1xx_DRIVERS - */ - -/** - * @defgroup STM32F1xx_CAN STM32F1xx CAN Support - * @details The STM32F1xx CAN driver uses the CAN peripherals. - * - * @section stm32f1xx_can_1 Supported HW resources - * - bxCAN1. - * . - * @section stm32f1xx_can_2 STM32F1xx CAN driver implementation features - * - Clock stop for reduced power usage when the driver is in stop state. - * - Support for bxCAN sleep mode. - * - Programmable bxCAN interrupts priority level. - * . - * @ingroup STM32F1xx_DRIVERS - */ - -/** - * @defgroup STM32F1xx_EXT STM32F1xx EXT Support - * @details The STM32F1xx EXT driver uses the EXTI peripheral. - * - * @section stm32f1xx_ext_1 Supported HW resources - * - EXTI. - * . - * @section stm32f1xx_ext_2 STM32F1xx EXT driver implementation features - * - Each EXTI channel can be independently enabled and programmed. - * - Programmable EXTI interrupts priority level. - * - Capability to work as event sources (WFE) rather than interrupt sources. - * . - * @ingroup STM32F1xx_DRIVERS - */ - -/** - * @defgroup STM32F1xx_GPT STM32F1xx GPT Support - * @details The STM32F1xx GPT driver uses the TIMx peripherals. - * - * @section stm32f1xx_gpt_1 Supported HW resources - * - TIM1. - * - TIM2. - * - TIM3. - * - TIM4. - * - TIM5. - * . - * @section stm32f1xx_gpt_2 STM32F1xx GPT driver implementation features - * - Each timer can be independently enabled and programmed. Unused - * peripherals are left in low power mode. - * - Programmable TIMx interrupts priority level. - * . - * @ingroup STM32F1xx_DRIVERS - */ - -/** - * @defgroup STM32F1xx_I2C STM32F1xx I2C Support - * @details The STM32F1xx I2C driver uses the I2Cx peripherals. - * - * @section stm32f1xx_i2c_1 Supported HW resources - * - I2C1. - * - I2C2. - * . - * @section stm32f1xx_i2c_2 STM32F1xx I2C driver implementation features - * - Each I2C port can be independently enabled and programmed. Unused - * peripherals are left in low power mode. - * - Programmable I2Cx interrupts priority level. - * . - * @ingroup STM32F1xx_DRIVERS - */ - -/** - * @defgroup STM32F1xx_ICU STM32F1xx ICU Support - * @details The STM32F1xx ICU driver uses the TIMx peripherals. - * - * @section stm32f1xx_icu_1 Supported HW resources - * - TIM1. - * - TIM2. - * - TIM3. - * - TIM4. - * - TIM5. - * . - * @section stm32f1xx_icu_2 STM32F1xx ICU driver implementation features - * - Each timer can be independently enabled and programmed. Unused - * peripherals are left in low power mode. - * - Programmable TIMx interrupts priority level. - * . - * @ingroup STM32F1xx_DRIVERS - */ - -/** - * @defgroup STM32F1xx_MAC STM32F1xx MAC Support - * @details The STM32 MAC driver supports the ETH peripheral. - * - * @section at91sam7_mac_1 Supported HW resources - * - ETH. - * . - * @ingroup STM32F1xx_DRIVERS - */ - -/** - * @defgroup STM32F1xx_PAL STM32F1xx PAL Support - * @details The STM32F1xx PAL driver uses the GPIO peripherals. - * - * @section stm32f1xx_pal_1 Supported HW resources - * - AFIO. - * - GPIOA. - * - GPIOB. - * - GPIOC. - * - GPIOD. - * - GPIOE (where present). - * - GPIOF (where present). - * - GPIOG (where present). - * . - * @section stm32f1xx_pal_2 STM32F1xx PAL driver implementation features - * The PAL driver implementation fully supports the following hardware - * capabilities: - * - 16 bits wide ports. - * - Atomic set/reset functions. - * - Atomic set+reset function (atomic bus operations). - * - Output latched regardless of the pad setting. - * - Direct read of input pads regardless of the pad setting. - * . - * @section stm32f1xx_pal_3 Supported PAL setup modes - * The STM32F1xx PAL driver supports the following I/O modes: - * - @p PAL_MODE_RESET. - * - @p PAL_MODE_UNCONNECTED. - * - @p PAL_MODE_INPUT. - * - @p PAL_MODE_INPUT_PULLUP. - * - @p PAL_MODE_INPUT_PULLDOWN. - * - @p PAL_MODE_INPUT_ANALOG. - * - @p PAL_MODE_OUTPUT_PUSHPULL. - * - @p PAL_MODE_OUTPUT_OPENDRAIN. - * - @p PAL_MODE_STM32F1xx_ALTERNATE_PUSHPULL (non standard). - * - @p PAL_MODE_STM32F1xx_ALTERNATE_OPENDRAIN (non standard). - * . - * Any attempt to setup an invalid mode is ignored. - * - * @section stm32f1xx_pal_4 Suboptimal behavior - * The STM32F1xx GPIO is less than optimal in several areas, the limitations - * should be taken in account while using the PAL driver: - * - Pad/port toggling operations are not atomic. - * - Pad/group mode setup is not atomic. - * - Writing on pads/groups/ports programmed as input with pull-up/down - * resistor can change the resistor setting because the output latch is - * used for resistor selection. - * . - * @ingroup STM32F1xx_DRIVERS - */ - -/** - * @defgroup STM32F1xx_PWM STM32F1xx PWM Support - * @details The STM32F1xx PWM driver uses the TIMx peripherals. - * - * @section stm32f1xx_pwm_1 Supported HW resources - * - TIM1. - * - TIM2. - * - TIM3. - * - TIM4. - * - TIM5. - * . - * @section stm32f1xx_pwm_2 STM32F1xx PWM driver implementation features - * - Each timer can be independently enabled and programmed. Unused - * peripherals are left in low power mode. - * - Four independent PWM channels per timer. - * - Programmable TIMx interrupts priority level. - * . - * @ingroup STM32F1xx_DRIVERS - */ - -/** - * @defgroup STM32F1xx_RTC STM32F1xx RTC Support - * @details The STM32F1xx RTC driver uses the RTC peripheral. - * - * @section stm32f1xx_rtc_1 Supported HW resources - * - RTC. - * . - * @ingroup STM32F1xx_DRIVERS - */ - -/** - * @defgroup STM32F1xx_SDC STM32F1xx SDC Support - * @details The STM32F1xx SDC driver uses the SDIO peripheral. - * - * @section stm32f1xx_sdc_1 Supported HW resources - * - SDIO. - * - DMA2. - * . - * @section stm32f1xx_sdc_2 STM32F1xx SDC driver implementation features - * - Clock stop for reduced power usage when the driver is in stop state. - * - Programmable interrupt priority. - * - DMA is used for receiving and transmitting. - * - Programmable DMA bus priority for each DMA channel. - * . - * @ingroup STM32F1xx_DRIVERS - */ - -/** - * @defgroup STM32F1xx_SERIAL STM32F1xx Serial Support - * @details The STM32F1xx Serial driver uses the USART/UART peripherals in a - * buffered, interrupt driven, implementation. - * - * @section stm32f1xx_serial_1 Supported HW resources - * The serial driver can support any of the following hardware resources: - * - USART1. - * - USART2. - * - USART3 (where present). - * - UART4 (where present). - * - UART5 (where present). - * . - * @section stm32f1xx_serial_2 STM32F1xx Serial driver implementation features - * - Clock stop for reduced power usage when the driver is in stop state. - * - Each UART/USART can be independently enabled and programmed. Unused - * peripherals are left in low power mode. - * - Fully interrupt driven. - * - Programmable priority levels for each UART/USART. - * . - * @ingroup STM32F1xx_DRIVERS - */ - -/** - * @defgroup STM32F1xx_SPI STM32F1xx SPI Support - * @details The SPI driver supports the STM32F1xx SPI peripherals using DMA - * channels for maximum performance. - * - * @section stm32f1xx_spi_1 Supported HW resources - * - SPI1. - * - SPI2. - * - SPI3 (where present). - * - DMA1. - * - DMA2 (where present). - * . - * @section stm32f1xx_spi_2 STM32F1xx SPI driver implementation features - * - Clock stop for reduced power usage when the driver is in stop state. - * - Each SPI can be independently enabled and programmed. Unused - * peripherals are left in low power mode. - * - Programmable interrupt priority levels for each SPI. - * - DMA is used for receiving and transmitting. - * - Programmable DMA bus priority for each DMA channel. - * - Programmable DMA interrupt priority for each DMA channel. - * - Programmable DMA error hook. - * . - * @ingroup STM32F1xx_DRIVERS - */ - -/** - * @defgroup STM32F1xx_UART STM32F1xx UART Support - * @details The UART driver supports the STM32F1xx USART peripherals using DMA - * channels for maximum performance. - * - * @section stm32f1xx_uart_1 Supported HW resources - * The UART driver can support any of the following hardware resources: - * - USART1. - * - USART2. - * - USART3 (where present). - * - UART4 (where present). - * - DMA1. - * - DMA2 (where present). - * . - * @section stm32f1xx_uart_2 STM32F1xx UART driver implementation features - * - Clock stop for reduced power usage when the driver is in stop state. - * - Each UART/USART can be independently enabled and programmed. Unused - * peripherals are left in low power mode. - * - Programmable interrupt priority levels for each UART/USART. - * - DMA is used for receiving and transmitting. - * - Programmable DMA bus priority for each DMA channel. - * - Programmable DMA interrupt priority for each DMA channel. - * - Programmable DMA error hook. - * . - * @ingroup STM32F1xx_DRIVERS - */ - -/** - * @defgroup STM32F1xx_USB STM32F1xx USB Support - * @details The USB driver supports the STM32F1xx USB peripheral. - * - * @section stm32f1xx_usb_1 Supported HW resources - * The USB driver can support any of the following hardware resources: - * - USB. - * . - * @section stm32f1xx_usb_2 STM32F1xx USB driver implementation features - * - Clock stop for reduced power usage when the driver is in stop state. - * - Programmable interrupt priority levels. - * - Each endpoint programmable in Control, Bulk and Interrupt modes. - * . - * @ingroup STM32F1xx_DRIVERS - */ - -/** - * @defgroup STM32F1xx_PLATFORM_DRIVERS STM32F1xx Platform Drivers - * @details Platform support drivers. Platform drivers do not implement HAL - * standard driver templates, their role is to support platform - * specific functionalities. - * - * @ingroup STM32F1xx_DRIVERS - */ - -/** - * @defgroup STM32F1xx_DMA STM32F1xx DMA Support - * @details This DMA helper driver is used by the other drivers in order to - * access the shared DMA resources in a consistent way. - * - * @section stm32f1xx_dma_1 Supported HW resources - * The DMA driver can support any of the following hardware resources: - * - DMA1. - * - DMA2 (where present). - * . - * @section stm32f1xx_dma_2 STM32F1xx DMA driver implementation features - * - Exports helper functions/macros to the other drivers that share the - * DMA resource. - * - Automatic DMA clock stop when not in use by any driver. - * - DMA streams and interrupt vectors sharing among multiple drivers. - * . - * @ingroup STM32F1xx_PLATFORM_DRIVERS - */ - -/** - * @defgroup STM32F1xx_ISR STM32F1xx ISR Support - * @details This ISR helper driver is used by the other drivers in order to - * map ISR names to physical vector names. - * - * @ingroup STM32F1xx_PLATFORM_DRIVERS - */ - -/** - * @defgroup STM32F1xx_RCC STM32F1xx RCC Support - * @details This RCC helper driver is used by the other drivers in order to - * access the shared RCC resources in a consistent way. - * - * @section stm32f1xx_rcc_1 Supported HW resources - * - RCC. - * . - * @section stm32f1xx_rcc_2 STM32F1xx RCC driver implementation features - * - Peripherals reset. - * - Peripherals clock enable. - * - Peripherals clock disable. - * . - * @ingroup STM32F1xx_PLATFORM_DRIVERS - */ diff --git a/firmware/chibios/os/hal/platforms/STM32F1xx/platform.mk b/firmware/chibios/os/hal/platforms/STM32F1xx/platform.mk deleted file mode 100644 index 9111e49545..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F1xx/platform.mk +++ /dev/null @@ -1,31 +0,0 @@ -# List of all the STM32F1xx platform files. -PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F1xx/stm32_dma.c \ - ${CHIBIOS}/os/hal/platforms/STM32F1xx/hal_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32F1xx/adc_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32F1xx/ext_lld_isr.c \ - ${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/mac_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/sdc_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/GPIOv1/pal_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/I2Cv1/i2c_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/RTCv1/rtc_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/SPIv1/spi_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/gpt_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/icu_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/pwm_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/USARTv1/serial_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/USARTv1/uart_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/USBv1/usb_lld.c - -# Required include directories -PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F1xx \ - ${CHIBIOS}/os/hal/platforms/STM32 \ - ${CHIBIOS}/os/hal/platforms/STM32/GPIOv1 \ - ${CHIBIOS}/os/hal/platforms/STM32/I2Cv1 \ - ${CHIBIOS}/os/hal/platforms/STM32/RTCv1 \ - ${CHIBIOS}/os/hal/platforms/STM32/SPIv1 \ - ${CHIBIOS}/os/hal/platforms/STM32/TIMv1 \ - ${CHIBIOS}/os/hal/platforms/STM32/USARTv1 \ - ${CHIBIOS}/os/hal/platforms/STM32/USBv1 - diff --git a/firmware/chibios/os/hal/platforms/STM32F1xx/stm32_dma.c b/firmware/chibios/os/hal/platforms/STM32F1xx/stm32_dma.c deleted file mode 100644 index 9a50379021..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F1xx/stm32_dma.c +++ /dev/null @@ -1,503 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F1xx/stm32_dma.c - * @brief DMA helper driver code. - * - * @addtogroup STM32F1xx_DMA - * @details DMA sharing helper driver. In the STM32 the DMA streams are a - * shared resource, this driver allows to allocate and free DMA - * streams at runtime in order to allow all the other device - * drivers to coordinate the access to the resource. - * @note The DMA ISR handlers are all declared into this module because - * sharing, the various device drivers can associate a callback to - * ISRs when allocating streams. - * @{ - */ - -#include "ch.h" -#include "hal.h" - -/* The following macro is only defined if some driver requiring DMA services - has been enabled.*/ -#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/** - * @brief Mask of the DMA1 streams in @p dma_streams_mask. - */ -#define STM32_DMA1_STREAMS_MASK 0x0000007F - -/** - * @brief Mask of the DMA2 streams in @p dma_streams_mask. - */ -#define STM32_DMA2_STREAMS_MASK 0x00000F80 - -/** - * @brief Post-reset value of the stream CCR register. - */ -#define STM32_DMA_CCR_RESET_VALUE 0x00000000 - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief DMA streams descriptors. - * @details This table keeps the association between an unique stream - * identifier and the involved physical registers. - * @note Don't use this array directly, use the appropriate wrapper macros - * instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc. - */ -const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = { - {DMA1_Channel1, &DMA1->IFCR, 0, 0, DMA1_Channel1_IRQn}, - {DMA1_Channel2, &DMA1->IFCR, 4, 1, DMA1_Channel2_IRQn}, - {DMA1_Channel3, &DMA1->IFCR, 8, 2, DMA1_Channel3_IRQn}, - {DMA1_Channel4, &DMA1->IFCR, 12, 3, DMA1_Channel4_IRQn}, - {DMA1_Channel5, &DMA1->IFCR, 16, 4, DMA1_Channel5_IRQn}, - {DMA1_Channel6, &DMA1->IFCR, 20, 5, DMA1_Channel6_IRQn}, - {DMA1_Channel7, &DMA1->IFCR, 24, 6, DMA1_Channel7_IRQn}, -#if STM32_HAS_DMA2 || defined(__DOXYGEN__) - {DMA2_Channel1, &DMA2->IFCR, 0, 7, DMA2_Channel1_IRQn}, - {DMA2_Channel2, &DMA2->IFCR, 4, 8, DMA2_Channel2_IRQn}, - {DMA2_Channel3, &DMA2->IFCR, 8, 9, DMA2_Channel3_IRQn}, -#if defined(STM32F10X_CL) || defined(__DOXYGEN__) - {DMA2_Channel4, &DMA2->IFCR, 12, 10, DMA2_Channel4_IRQn}, - {DMA2_Channel5, &DMA2->IFCR, 16, 11, DMA2_Channel5_IRQn}, -#else /* !STM32F10X_CL */ - {DMA2_Channel4, &DMA2->IFCR, 12, 10, DMA2_Channel4_5_IRQn}, - {DMA2_Channel5, &DMA2->IFCR, 16, 11, DMA2_Channel4_5_IRQn}, -#endif /* !STM32F10X_CL */ -#endif /* STM32_HAS_DMA2 */ -}; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief DMA ISR redirector type. - */ -typedef struct { - stm32_dmaisr_t dma_func; /**< @brief DMA callback function. */ - void *dma_param; /**< @brief DMA callback parameter. */ -} dma_isr_redir_t; - -/** - * @brief Mask of the allocated streams. - */ -static uint32_t dma_streams_mask; - -/** - * @brief DMA IRQ redirectors. - */ -static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS]; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief DMA1 stream 1 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA1_Ch1_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK; - DMA1->IFCR = flags << 0; - if (dma_isr_redir[0].dma_func) - dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 2 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA1_Ch2_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK; - DMA1->IFCR = flags << 4; - if (dma_isr_redir[1].dma_func) - dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 3 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA1_Ch3_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK; - DMA1->IFCR = flags << 8; - if (dma_isr_redir[2].dma_func) - dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 4 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA1_Ch4_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK; - DMA1->IFCR = flags << 12; - if (dma_isr_redir[3].dma_func) - dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 5 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA1_Ch5_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK; - DMA1->IFCR = flags << 16; - if (dma_isr_redir[4].dma_func) - dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 6 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA1_Ch6_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK; - DMA1->IFCR = flags << 20; - if (dma_isr_redir[5].dma_func) - dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 7 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA1_Ch7_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK; - DMA1->IFCR = flags << 24; - if (dma_isr_redir[6].dma_func) - dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -#if STM32_HAS_DMA2 || defined(__DOXYGEN__) -/** - * @brief DMA2 stream 1 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA2_Ch1_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA2->ISR >> 0) & STM32_DMA_ISR_MASK; - DMA2->IFCR = flags << 0; - if (dma_isr_redir[7].dma_func) - dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 2 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA2_Ch2_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA2->ISR >> 4) & STM32_DMA_ISR_MASK; - DMA2->IFCR = flags << 4; - if (dma_isr_redir[8].dma_func) - dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 3 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA2_Ch3_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA2->ISR >> 8) & STM32_DMA_ISR_MASK; - DMA2->IFCR = flags << 8; - if (dma_isr_redir[9].dma_func) - dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -#if defined(STM32F10X_CL) || defined(__DOXYGEN__) -/** - * @brief DMA2 stream 4 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA2_Ch4_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK; - DMA2->IFCR = flags << 12; - if (dma_isr_redir[10].dma_func) - dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 5 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA2_Ch5_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK; - DMA2->IFCR = flags << 16; - if (dma_isr_redir[11].dma_func) - dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} -#else /* !STM32F10X_CL */ -/** - * @brief DMA2 streams 4 and 5 shared interrupt handler. - * @note This IRQ is shared between DMA2 channels 4 and 5 so it is a - * bit less efficient because an extra check. - * - * @isr - */ -CH_IRQ_HANDLER(DMA2_Ch4_5_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - /* Check on channel 4.*/ - flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK; - if (flags & STM32_DMA_ISR_MASK) { - DMA2->IFCR = flags << 12; - if (dma_isr_redir[10].dma_func) - dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags); - } - - /* Check on channel 5.*/ - flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK; - if (flags & STM32_DMA_ISR_MASK) { - DMA2->IFCR = flags << 16; - if (dma_isr_redir[11].dma_func) - dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags); - } - - CH_IRQ_EPILOGUE(); -} -#endif /* !STM32F10X_CL */ -#endif /* STM32_HAS_DMA2 */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief STM32 DMA helper initialization. - * - * @init - */ -void dmaInit(void) { - int i; - - dma_streams_mask = 0; - for (i = 0; i < STM32_DMA_STREAMS; i++) { - _stm32_dma_streams[i].channel->CCR = 0; - dma_isr_redir[i].dma_func = NULL; - } - DMA1->IFCR = 0xFFFFFFFF; -#if STM32_HAS_DMA2 - DMA2->IFCR = 0xFFFFFFFF; -#endif -} - -/** - * @brief Allocates a DMA stream. - * @details The stream is allocated and, if required, the DMA clock enabled. - * The function also enables the IRQ vector associated to the stream - * and initializes its priority. - * @pre The stream must not be already in use or an error is returned. - * @post The stream is allocated and the default ISR handler redirected - * to the specified function. - * @post The stream ISR vector is enabled and its priority configured. - * @post The stream must be freed using @p dmaStreamRelease() before it can - * be reused with another peripheral. - * @post The stream is in its post-reset state. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] priority IRQ priority mask for the DMA stream - * @param[in] func handling function pointer, can be @p NULL - * @param[in] param a parameter to be passed to the handling function - * @return The operation status. - * @retval FALSE no error, stream taken. - * @retval TRUE error, stream already taken. - * - * @special - */ -bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, - uint32_t priority, - stm32_dmaisr_t func, - void *param) { - - chDbgCheck(dmastp != NULL, "dmaStreamAllocate"); - - /* Checks if the stream is already taken.*/ - if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0) - return TRUE; - - /* Marks the stream as allocated.*/ - dma_isr_redir[dmastp->selfindex].dma_func = func; - dma_isr_redir[dmastp->selfindex].dma_param = param; - dma_streams_mask |= (1 << dmastp->selfindex); - - /* Enabling DMA clocks required by the current streams set.*/ - if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0) - rccEnableDMA1(FALSE); -#if STM32_HAS_DMA2 - if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0) - rccEnableDMA2(FALSE); -#endif - - /* Putting the stream in a safe state.*/ - dmaStreamDisable(dmastp); - dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE; - - /* Enables the associated IRQ vector if a callback is defined.*/ - if (func != NULL) - nvicEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority)); - - return FALSE; -} - -/** - * @brief Releases a DMA stream. - * @details The stream is freed and, if required, the DMA clock disabled. - * Trying to release a unallocated stream is an illegal operation - * and is trapped if assertions are enabled. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post The stream is again available. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * - * @special - */ -void dmaStreamRelease(const stm32_dma_stream_t *dmastp) { - - chDbgCheck(dmastp != NULL, "dmaStreamRelease"); - - /* Check if the streams is not taken.*/ - chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0, - "dmaStreamRelease(), #1", "not allocated"); - - /* Marks the stream as not allocated.*/ - dma_streams_mask &= ~(1 << dmastp->selfindex); - - /* Disables the associated IRQ vector.*/ -#if !(STM32_HAS_DMA2 && !defined(STM32F10X_CL)) - nvicDisableVector(dmastp->vector); -#else - /* Check unless it is 10 or 11 stream. If yes, make additional check before - disabling IRQ.*/ - if (dmastp->selfindex < 10) - nvicDisableVector(dmastp->vector); - else { - if ((dma_streams_mask & (3 << 10)) == 0) - nvicDisableVector(dmastp->vector); - } -#endif /* STM32_HAS_DMA2 && !STM32F10X_CL */ - - /* Shutting down clocks that are no more required, if any.*/ - if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0) - rccDisableDMA1(FALSE); -#if STM32_HAS_DMA2 - if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0) - rccDisableDMA2(FALSE); -#endif -} - -#endif /* STM32_DMA_REQUIRED */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32F1xx/stm32_dma.h b/firmware/chibios/os/hal/platforms/STM32F1xx/stm32_dma.h deleted file mode 100644 index 8bbd8b637e..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F1xx/stm32_dma.h +++ /dev/null @@ -1,406 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F1xx/stm32_dma.h - * @brief DMA helper driver header. - * @note This file requires definitions from the ST header file stm32f10x.h. - * @note This driver uses the new naming convention used for the STM32F2xx - * so the "DMA channels" are referred as "DMA streams". - * - * @addtogroup STM32F1xx_DMA - * @{ - */ - -#ifndef _STM32_DMA_H_ -#define _STM32_DMA_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Total number of DMA streams. - * @note This is the total number of streams among all the DMA units. - */ -#if STM32_HAS_DMA2 || defined(__DOXYGEN__) -#define STM32_DMA_STREAMS 12 -#else -#define STM32_DMA_STREAMS 7 -#endif - -/** - * @brief Mask of the ISR bits passed to the DMA callback functions. - */ -#define STM32_DMA_ISR_MASK 0x0F - -/** - * @brief Returns the channel associated to the specified stream. - * - * @param[in] n the stream number (0...STM32_DMA_STREAMS-1) - * @param[in] c a stream/channel association word, one channel per - * nibble, not associated channels must be set to 0xF - * @return Always zero, in this platform there is no dynamic - * association between streams and channels. - */ -#define STM32_DMA_GETCHANNEL(n, c) 0 - -/** - * @brief Checks if a DMA priority is within the valid range. - * @param[in] prio DMA priority - * - * @retval The check result. - * @retval FALSE invalid DMA priority. - * @retval TRUE correct DMA priority. - */ -#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3)) - -/** - * @brief Returns an unique numeric identifier for a DMA stream. - * - * @param[in] dma the DMA unit number - * @param[in] stream the stream number - * @return An unique numeric stream identifier. - */ -#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1) * 7) + ((stream) - 1)) - -/** - * @brief Returns a DMA stream identifier mask. - * - * - * @param[in] dma the DMA unit number - * @param[in] stream the stream number - * @return A DMA stream identifier mask. - */ -#define STM32_DMA_STREAM_ID_MSK(dma, stream) \ - (1 << STM32_DMA_STREAM_ID(dma, stream)) - -/** - * @brief Checks if a DMA stream unique identifier belongs to a mask. - * @param[in] id the stream numeric identifier - * @param[in] mask the stream numeric identifiers mask - * - * @retval The check result. - * @retval FALSE id does not belong to the mask. - * @retval TRUE id belongs to the mask. - */ -#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask))) - -/** - * @name DMA streams identifiers - * @{ - */ -/** - * @brief Returns a pointer to a stm32_dma_stream_t structure. - * - * @param[in] id the stream numeric identifier - * @return A pointer to the stm32_dma_stream_t constant structure - * associated to the DMA stream. - */ -#define STM32_DMA_STREAM(id) (&_stm32_dma_streams[id]) - -#define STM32_DMA1_STREAM1 STM32_DMA_STREAM(0) -#define STM32_DMA1_STREAM2 STM32_DMA_STREAM(1) -#define STM32_DMA1_STREAM3 STM32_DMA_STREAM(2) -#define STM32_DMA1_STREAM4 STM32_DMA_STREAM(3) -#define STM32_DMA1_STREAM5 STM32_DMA_STREAM(4) -#define STM32_DMA1_STREAM6 STM32_DMA_STREAM(5) -#define STM32_DMA1_STREAM7 STM32_DMA_STREAM(6) -#define STM32_DMA2_STREAM1 STM32_DMA_STREAM(7) -#define STM32_DMA2_STREAM2 STM32_DMA_STREAM(8) -#define STM32_DMA2_STREAM3 STM32_DMA_STREAM(9) -#define STM32_DMA2_STREAM4 STM32_DMA_STREAM(10) -#define STM32_DMA2_STREAM5 STM32_DMA_STREAM(11) -/** @} */ - -/** - * @name CR register constants common to all DMA types - * @{ - */ -#define STM32_DMA_CR_EN DMA_CCR1_EN -#define STM32_DMA_CR_TEIE DMA_CCR1_TEIE -#define STM32_DMA_CR_HTIE DMA_CCR1_HTIE -#define STM32_DMA_CR_TCIE DMA_CCR1_TCIE -#define STM32_DMA_CR_DIR_MASK (DMA_CCR1_DIR | DMA_CCR1_MEM2MEM) -#define STM32_DMA_CR_DIR_P2M 0 -#define STM32_DMA_CR_DIR_M2P DMA_CCR1_DIR -#define STM32_DMA_CR_DIR_M2M DMA_CCR1_MEM2MEM -#define STM32_DMA_CR_CIRC DMA_CCR1_CIRC -#define STM32_DMA_CR_PINC DMA_CCR1_PINC -#define STM32_DMA_CR_MINC DMA_CCR1_MINC -#define STM32_DMA_CR_PSIZE_MASK DMA_CCR1_PSIZE -#define STM32_DMA_CR_PSIZE_BYTE 0 -#define STM32_DMA_CR_PSIZE_HWORD DMA_CCR1_PSIZE_0 -#define STM32_DMA_CR_PSIZE_WORD DMA_CCR1_PSIZE_1 -#define STM32_DMA_CR_MSIZE_MASK DMA_CCR1_MSIZE -#define STM32_DMA_CR_MSIZE_BYTE 0 -#define STM32_DMA_CR_MSIZE_HWORD DMA_CCR1_MSIZE_0 -#define STM32_DMA_CR_MSIZE_WORD DMA_CCR1_MSIZE_1 -#define STM32_DMA_CR_SIZE_MASK (STM32_DMA_CR_PSIZE_MASK | \ - STM32_DMA_CR_MSIZE_MASK) -#define STM32_DMA_CR_PL_MASK DMA_CCR1_PL -#define STM32_DMA_CR_PL(n) ((n) << 12) -/** @} */ - -/** - * @name CR register constants only found in enhanced DMA - * @{ - */ -#define STM32_DMA_CR_DMEIE 0 /**< @brief Ignored by normal DMA. */ -#define STM32_DMA_CR_CHSEL_MASK 0 /**< @brief Ignored by normal DMA. */ -#define STM32_DMA_CR_CHSEL(n) 0 /**< @brief Ignored by normal DMA. */ -/** @} */ - -/** - * @name Status flags passed to the ISR callbacks - * @{ - */ -#define STM32_DMA_ISR_FEIF 0 -#define STM32_DMA_ISR_DMEIF 0 -#define STM32_DMA_ISR_TEIF DMA_ISR_TEIF1 -#define STM32_DMA_ISR_HTIF DMA_ISR_HTIF1 -#define STM32_DMA_ISR_TCIF DMA_ISR_TCIF1 -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief STM32 DMA stream descriptor structure. - */ -typedef struct { - DMA_Channel_TypeDef *channel; /**< @brief Associated DMA channel. */ - volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */ - uint8_t ishift; /**< @brief Bits offset in xIFCR - register. */ - uint8_t selfindex; /**< @brief Index to self in array. */ - uint8_t vector; /**< @brief Associated IRQ vector. */ -} stm32_dma_stream_t; - -/** - * @brief STM32 DMA ISR function type. - * - * @param[in] p parameter for the registered function - * @param[in] flags pre-shifted content of the ISR register, the bits - * are aligned to bit zero - */ -typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Associates a peripheral data register to a DMA stream. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] addr value to be written in the CPAR register - * - * @special - */ -#define dmaStreamSetPeripheral(dmastp, addr) { \ - (dmastp)->channel->CPAR = (uint32_t)(addr); \ -} - -/** - * @brief Associates a memory destination to a DMA stream. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] addr value to be written in the CMAR register - * - * @special - */ -#define dmaStreamSetMemory0(dmastp, addr) { \ - (dmastp)->channel->CMAR = (uint32_t)(addr); \ -} - -/** - * @brief Sets the number of transfers to be performed. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] size value to be written in the CNDTR register - * - * @special - */ -#define dmaStreamSetTransactionSize(dmastp, size) { \ - (dmastp)->channel->CNDTR = (uint32_t)(size); \ -} - -/** - * @brief Returns the number of transfers to be performed. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @return The number of transfers to be performed. - * - * @special - */ -#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR)) - -/** - * @brief Programs the stream mode settings. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] mode value to be written in the CCR register - * - * @special - */ -#define dmaStreamSetMode(dmastp, mode) { \ - (dmastp)->channel->CCR = (uint32_t)(mode); \ -} - -/** - * @brief DMA stream enable. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * - * @special - */ -#define dmaStreamEnable(dmastp) { \ - (dmastp)->channel->CCR |= STM32_DMA_CR_EN; \ -} - -/** - * @brief DMA stream disable. - * @details The function disables the specified stream and then clears any - * pending interrupt. - * @note This function can be invoked in both ISR or thread context. - * @note Interrupts enabling flags are set to zero after this call, see - * bug 3607518. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * - * @special - */ -#define dmaStreamDisable(dmastp) { \ - (dmastp)->channel->CCR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | \ - STM32_DMA_CR_TEIE | STM32_DMA_CR_EN); \ - dmaStreamClearInterrupt(dmastp); \ -} - -/** - * @brief DMA stream interrupt sources clear. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * - * @special - */ -#define dmaStreamClearInterrupt(dmastp) { \ - *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \ -} - -/** - * @brief Starts a memory to memory operation using the specified stream. - * @note The default transfer data mode is "byte to byte" but it can be - * changed by specifying extra options in the @p mode parameter. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] mode value to be written in the CCR register, this value - * is implicitly ORed with: - * - @p STM32_DMA_CR_MINC - * - @p STM32_DMA_CR_PINC - * - @p STM32_DMA_CR_DIR_M2M - * - @p STM32_DMA_CR_EN - * . - * @param[in] src source address - * @param[in] dst destination address - * @param[in] n number of data units to copy - */ -#define dmaStartMemCopy(dmastp, mode, src, dst, n) { \ - dmaStreamSetPeripheral(dmastp, src); \ - dmaStreamSetMemory0(dmastp, dst); \ - dmaStreamSetTransactionSize(dmastp, n); \ - dmaStreamSetMode(dmastp, (mode) | \ - STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \ - STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); \ -} - -/** - * @brief Polled wait for DMA transfer end. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - */ -#define dmaWaitCompletion(dmastp) { \ - while ((dmastp)->channel->CNDTR > 0) \ - ; \ - dmaStreamDisable(dmastp); \ -} - -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS]; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void dmaInit(void); - bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, - uint32_t priority, - stm32_dmaisr_t func, - void *param); - void dmaStreamRelease(const stm32_dma_stream_t *dmastp); -#ifdef __cplusplus -} -#endif - -#endif /* _STM32_DMA_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32F1xx/stm32_isr.h b/firmware/chibios/os/hal/platforms/STM32F1xx/stm32_isr.h deleted file mode 100644 index c13c20c273..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F1xx/stm32_isr.h +++ /dev/null @@ -1,156 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F1xx/stm32_isr.h - * @brief ISR remapper driver header. - * - * @addtogroup STM32F1xx_ISR - * @{ - */ - -#ifndef _STM32_ISR_H_ -#define _STM32_ISR_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name ISR names and numbers remapping - * @{ - */ -/* - * CAN units. - */ -#define STM32_CAN1_TX_HANDLER Vector8C -#define STM32_CAN1_RX0_HANDLER Vector90 -#define STM32_CAN1_RX1_HANDLER Vector94 -#define STM32_CAN1_SCE_HANDLER Vector98 -#define STM32_CAN2_TX_HANDLER Vector13C -#define STM32_CAN2_RX0_HANDLER Vector140 -#define STM32_CAN2_RX1_HANDLER Vector144 -#define STM32_CAN2_SCE_HANDLER Vector148 - -#define STM32_CAN1_TX_NUMBER 19 -#define STM32_CAN1_RX0_NUMBER 20 -#define STM32_CAN1_RX1_NUMBER 21 -#define STM32_CAN1_SCE_NUMBER 22 -#define STM32_CAN2_TX_NUMBER 63 -#define STM32_CAN2_RX0_NUMBER 64 -#define STM32_CAN2_RX1_NUMBER 65 -#define STM32_CAN2_SCE_NUMBER 66 - -/* - * I2C units. - */ -#define STM32_I2C1_EVENT_HANDLER VectorBC -#define STM32_I2C1_ERROR_HANDLER VectorC0 -#define STM32_I2C1_EVENT_NUMBER 31 -#define STM32_I2C1_ERROR_NUMBER 32 - -#define STM32_I2C2_EVENT_HANDLER VectorC4 -#define STM32_I2C2_ERROR_HANDLER VectorC8 -#define STM32_I2C2_EVENT_NUMBER 33 -#define STM32_I2C2_ERROR_NUMBER 34 - -/* - * OTG units. - */ -#define STM32_OTG1_HANDLER Vector14C - -#define STM32_OTG1_NUMBER 67 - -/* - * SDIO unit. - */ -#define STM32_SDIO_HANDLER Vector104 - -#define STM32_SDIO_NUMBER 49 - -/* - * TIM units. - */ -#define STM32_TIM1_UP_HANDLER VectorA4 -#define STM32_TIM1_CC_HANDLER VectorAC -#define STM32_TIM2_HANDLER VectorB0 -#define STM32_TIM3_HANDLER VectorB4 -#define STM32_TIM4_HANDLER VectorB8 -#define STM32_TIM5_HANDLER Vector108 -#define STM32_TIM6_HANDLER Vector118 -#define STM32_TIM7_HANDLER Vector11C -#define STM32_TIM8_UP_HANDLER VectorF0 -#define STM32_TIM8_CC_HANDLER VectorF8 - -#define STM32_TIM1_UP_NUMBER 25 -#define STM32_TIM1_CC_NUMBER 27 -#define STM32_TIM2_NUMBER 28 -#define STM32_TIM3_NUMBER 29 -#define STM32_TIM4_NUMBER 30 -#define STM32_TIM5_NUMBER 50 -#define STM32_TIM6_NUMBER 54 -#define STM32_TIM7_NUMBER 55 -#define STM32_TIM8_UP_NUMBER 44 -#define STM32_TIM8_CC_NUMBER 46 - -/* - * USART units. - */ -#define STM32_USART1_HANDLER VectorD4 -#define STM32_USART2_HANDLER VectorD8 -#define STM32_USART3_HANDLER VectorDC -#define STM32_UART4_HANDLER Vector110 -#define STM32_UART5_HANDLER Vector114 - -#define STM32_USART1_NUMBER 37 -#define STM32_USART2_NUMBER 38 -#define STM32_USART3_NUMBER 39 -#define STM32_UART4_NUMBER 52 -#define STM32_UART5_NUMBER 53 - -/* - * USB units. - */ -#define STM32_USB1_HP_HANDLER Vector8C -#define STM32_USB1_LP_HANDLER Vector90 - -#define STM32_USB1_HP_NUMBER 19 -#define STM32_USB1_LP_NUMBER 20 -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#endif /* _STM32_ISR_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32F1xx/stm32_rcc.h b/firmware/chibios/os/hal/platforms/STM32F1xx/stm32_rcc.h deleted file mode 100644 index 4cb73e3755..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F1xx/stm32_rcc.h +++ /dev/null @@ -1,1036 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F1xx/stm32_rcc.h - * @brief RCC helper driver header. - * @note This file requires definitions from the ST header file - * @p stm32f10x.h. - * - * @addtogroup STM32F1xx_RCC - * @{ - */ - -#ifndef _STM32_RCC_ -#define _STM32_RCC_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Generic RCC operations - * @{ - */ -/** - * @brief Enables the clock of one or more peripheral on the APB1 bus. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] mask APB1 peripherals mask - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableAPB1(mask, lp) { \ - RCC->APB1ENR |= (mask); \ -} - -/** - * @brief Disables the clock of one or more peripheral on the APB1 bus. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] mask APB1 peripherals mask - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableAPB1(mask, lp) { \ - RCC->APB1ENR &= ~(mask); \ -} - -/** - * @brief Resets one or more peripheral on the APB1 bus. - * - * @param[in] mask APB1 peripherals mask - * - * @api - */ -#define rccResetAPB1(mask) { \ - RCC->APB1RSTR |= (mask); \ - RCC->APB1RSTR = 0; \ -} - -/** - * @brief Enables the clock of one or more peripheral on the APB2 bus. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] mask APB2 peripherals mask - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableAPB2(mask, lp) { \ - RCC->APB2ENR |= (mask); \ -} - -/** - * @brief Disables the clock of one or more peripheral on the APB2 bus. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] mask APB2 peripherals mask - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableAPB2(mask, lp) { \ - RCC->APB2ENR &= ~(mask); \ -} - -/** - * @brief Resets one or more peripheral on the APB2 bus. - * - * @param[in] mask APB2 peripherals mask - * - * @api - */ -#define rccResetAPB2(mask) { \ - RCC->APB2RSTR |= (mask); \ - RCC->APB2RSTR = 0; \ -} - -/** - * @brief Enables the clock of one or more peripheral on the AHB bus. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] mask AHB peripherals mask - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableAHB(mask, lp) { \ - RCC->AHBENR |= (mask); \ -} - -/** - * @brief Disables the clock of one or more peripheral on the AHB bus. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] mask AHB peripherals mask - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableAHB(mask, lp) { \ - RCC->AHBENR &= ~(mask); \ -} - -/** - * @brief Resets one or more peripheral on the AHB bus. - * - * @param[in] mask AHB peripherals mask - * - * @api - */ -#define rccResetAHB(mask) { \ - RCC->AHBRSTR |= (mask); \ - RCC->AHBRSTR = 0; \ -} -/** @} */ - -/** - * @name ADC peripherals specific RCC operations - * @{ - */ -/** - * @brief Enables the ADC1 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp) - -/** - * @brief Disables the ADC1 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableADC1(lp) rccDisableAPB2(RCC_APB2ENR_ADC1EN, lp) - -/** - * @brief Resets the ADC1 peripheral. - * - * @api - */ -#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST) -/** @} */ - -/** - * @name Backup domain interface specific RCC operations - * @{ - */ -/** - * @brief Enables the BKP interface clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableBKPInterface(lp) rccEnableAPB1((RCC_APB1ENR_BKPEN), lp) - -/** - * @brief Disables BKP interface clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableBKPInterface(lp) rccDisableAPB1((RCC_APB1ENR_BKPEN), lp) - -/** - * @brief Resets the Backup Domain interface. - * - * @api - */ -#define rccResetBKPInterface() rccResetAPB1(RCC_APB1ENR_BKPRST) - -/** - * @brief Resets the entire Backup Domain. - * - * @api - */ -#define rccResetBKP() (RCC->BDCR |= RCC_BDCR_BDRST) -/** @} */ - -/** - * @name PWR interface specific RCC operations - * @{ - */ -/** - * @brief Enables the PWR interface clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp) - -/** - * @brief Disables PWR interface clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp) - -/** - * @brief Resets the PWR interface. - * - * @api - */ -#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST) -/** @} */ - -/** - * @name CAN peripherals specific RCC operations - * @{ - */ -/** - * @brief Enables the CAN1 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableCAN1(lp) rccEnableAPB1(RCC_APB1ENR_CAN1EN, lp) - -/** - * @brief Disables the CAN1 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableCAN1(lp) rccDisableAPB1(RCC_APB1ENR_CAN1EN, lp) - -/** - * @brief Resets the CAN1 peripheral. - * - * @api - */ -#define rccResetCAN1() rccResetAPB1(RCC_APB1RSTR_CAN1RST) - -/** - * @brief Enables the CAN2 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableCAN2(lp) rccEnableAPB1(RCC_APB1ENR_CAN2EN, lp) - -/** - * @brief Disables the CAN2 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableCAN2(lp) rccDisableAPB1(RCC_APB1ENR_CAN2EN, lp) - -/** - * @brief Resets the CAN2 peripheral. - * - * @api - */ -#define rccResetCAN2() rccResetAPB1(RCC_APB1RSTR_CAN2RST) -/** @} */ - -/** - * @name DMA peripherals specific RCC operations - * @{ - */ -/** - * @brief Enables the DMA1 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableDMA1(lp) rccEnableAHB(RCC_AHBENR_DMA1EN, lp) - -/** - * @brief Disables the DMA1 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableDMA1(lp) rccDisableAHB(RCC_AHBENR_DMA1EN, lp) - -/** - * @brief Resets the DMA1 peripheral. - * @note Not supported in this family, does nothing. - * - * @api - */ -#define rccResetDMA1() - -/** - * @brief Enables the DMA2 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableDMA2(lp) rccEnableAHB(RCC_AHBENR_DMA2EN, lp) - -/** - * @brief Disables the DMA2 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableDMA2(lp) rccDisableAHB(RCC_AHBENR_DMA2EN, lp) - -/** - * @brief Resets the DMA1 peripheral. - * @note Not supported in this family, does nothing. - * - * @api - */ -#define rccResetDMA2() -/** @} */ - -/** - * @name ETH peripheral specific RCC operations - * @{ - */ -/** - * @brief Enables the ETH peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableETH(lp) rccEnableAHB(RCC_AHBENR_ETHMACEN | \ - RCC_AHBENR_ETHMACTXEN | \ - RCC_AHBENR_ETHMACRXEN, lp) - -/** - * @brief Disables the ETH peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableETH(lp) rccDisableAHB(RCC_AHBENR_ETHMACEN | \ - RCC_AHBENR_ETHMACTXEN | \ - RCC_AHBENR_ETHMACRXEN, lp) - -/** - * @brief Resets the ETH peripheral. - * - * @api - */ -#define rccResetETH() rccResetAHB(RCC_AHBRSTR_ETHMACRST) -/** @} */ - -/** - * @name I2C peripherals specific RCC operations - * @{ - */ -/** - * @brief Enables the I2C1 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp) - -/** - * @brief Disables the I2C1 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableI2C1(lp) rccDisableAPB1(RCC_APB1ENR_I2C1EN, lp) - -/** - * @brief Resets the I2C1 peripheral. - * - * @api - */ -#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST) - -/** - * @brief Enables the I2C2 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp) - -/** - * @brief Disables the I2C2 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableI2C2(lp) rccDisableAPB1(RCC_APB1ENR_I2C2EN, lp) - -/** - * @brief Resets the I2C2 peripheral. - * - * @api - */ -#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST) -/** @} */ - -/** - * @name OTG peripherals specific RCC operations - * @{ - */ -/** - * @brief Enables the OTG_FS peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableOTG_FS(lp) rccEnableAHB(RCC_AHBENR_OTGFSEN, lp) - -/** - * @brief Disables the OTG_FS peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableOTG_FS(lp) rccDisableAHB(RCC_AHBENR_OTGFSEN, lp) - -/** - * @brief Resets the OTG_FS peripheral. - * - * @api - */ -#define rccResetOTG_FS() rccResetAHB(RCC_AHBRSTR_OTGFSRST) -/** @} */ - -/** - * @name SDIO peripheral specific RCC operations - * @{ - */ -/** - * @brief Enables the SDIO peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableSDIO(lp) rccEnableAHB(RCC_AHBENR_SDIOEN, lp) - -/** - * @brief Disables the SDIO peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableSDIO(lp) rccDisableAHB(RCC_AHBENR_SDIOEN, lp) - -/** - * @brief Resets the SDIO peripheral. - * @note Not supported in this family, does nothing. - * - * @api - */ -#define rccResetSDIO() -/** @} */ - -/** - * @name SPI peripherals specific RCC operations - * @{ - */ -/** - * @brief Enables the SPI1 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp) - -/** - * @brief Disables the SPI1 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp) - -/** - * @brief Resets the SPI1 peripheral. - * - * @api - */ -#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST) - -/** - * @brief Enables the SPI2 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp) - -/** - * @brief Disables the SPI2 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableSPI2(lp) rccDisableAPB1(RCC_APB1ENR_SPI2EN, lp) - -/** - * @brief Resets the SPI2 peripheral. - * - * @api - */ -#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST) - -/** - * @brief Enables the SPI3 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableSPI3(lp) rccEnableAPB1(RCC_APB1ENR_SPI3EN, lp) - -/** - * @brief Disables the SPI3 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableSPI3(lp) rccDisableAPB1(RCC_APB1ENR_SPI3EN, lp) - -/** - * @brief Resets the SPI3 peripheral. - * - * @api - */ -#define rccResetSPI3() rccResetAPB1(RCC_APB1RSTR_SPI3RST) -/** @} */ - -/** - * @name TIM peripherals specific RCC operations - * @{ - */ -/** - * @brief Enables the TIM1 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp) - -/** - * @brief Disables the TIM1 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM1(lp) rccDisableAPB2(RCC_APB2ENR_TIM1EN, lp) - -/** - * @brief Resets the TIM1 peripheral. - * - * @api - */ -#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST) - -/** - * @brief Enables the TIM2 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp) - -/** - * @brief Disables the TIM2 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp) - -/** - * @brief Resets the TIM2 peripheral. - * - * @api - */ -#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST) - -/** - * @brief Enables the TIM3 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp) - -/** - * @brief Disables the TIM3 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp) - -/** - * @brief Resets the TIM3 peripheral. - * - * @api - */ -#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST) - -/** - * @brief Enables the TIM4 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM4(lp) rccEnableAPB1(RCC_APB1ENR_TIM4EN, lp) - -/** - * @brief Disables the TIM4 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM4(lp) rccDisableAPB1(RCC_APB1ENR_TIM4EN, lp) - -/** - * @brief Resets the TIM4 peripheral. - * - * @api - */ -#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST) - -/** - * @brief Enables the TIM5 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM5(lp) rccEnableAPB1(RCC_APB1ENR_TIM5EN, lp) - -/** - * @brief Disables the TIM5 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM5(lp) rccDisableAPB1(RCC_APB1ENR_TIM5EN, lp) - -/** - * @brief Resets the TIM5 peripheral. - * - * @api - */ -#define rccResetTIM5() rccResetAPB1(RCC_APB1RSTR_TIM5RST) - -/** - * @brief Enables the TIM6 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM6(lp) rccEnableAPB1(RCC_APB1ENR_TIM6EN, lp) - -/** - * @brief Disables the TIM6 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM6(lp) rccDisableAPB1(RCC_APB1ENR_TIM6EN, lp) - -/** - * @brief Resets the TIM6 peripheral. - * - * @api - */ -#define rccResetTIM6() rccResetAPB1(RCC_APB1RSTR_TIM6RST) - -/** - * @brief Enables the TIM7 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM7(lp) rccEnableAPB1(RCC_APB1ENR_TIM7EN, lp) - -/** - * @brief Disables the TIM7 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM7(lp) rccDisableAPB1(RCC_APB1ENR_TIM7EN, lp) - -/** - * @brief Resets the TIM7 peripheral. - * - * @api - */ -#define rccResetTIM7() rccResetAPB1(RCC_APB1RSTR_TIM7RST) - -/** - * @brief Enables the TIM8 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM8(lp) rccEnableAPB2(RCC_APB2ENR_TIM8EN, lp) - -/** - * @brief Disables the TIM8 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM8(lp) rccDisableAPB2(RCC_APB2ENR_TIM8EN, lp) - -/** - * @brief Resets the TIM8 peripheral. - * - * @api - */ -#define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST) -/** @} */ - -/** - * @name USART/UART peripherals specific RCC operations - * @{ - */ -/** - * @brief Enables the USART1 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp) - -/** - * @brief Disables the USART1 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp) - -/** - * @brief Resets the USART1 peripheral. - * - * @api - */ -#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST) - -/** - * @brief Enables the USART2 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp) - -/** - * @brief Disables the USART2 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableUSART2(lp) rccDisableAPB1(RCC_APB1ENR_USART2EN, lp) - -/** - * @brief Resets the USART2 peripheral. - * - * @api - */ -#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST) - -/** - * @brief Enables the USART3 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp) - -/** - * @brief Disables the USART3 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableUSART3(lp) rccDisableAPB1(RCC_APB1ENR_USART3EN, lp) - -/** - * @brief Resets the USART3 peripheral. - * - * @api - */ -#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST) - -/** - * @brief Enables the UART4 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableUART4(lp) rccEnableAPB1(RCC_APB1ENR_UART4EN, lp) - -/** - * @brief Disables the UART4 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableUART4(lp) rccDisableAPB1(RCC_APB1ENR_UART4EN, lp) - -/** - * @brief Resets the UART4 peripheral. - * - * @api - */ -#define rccResetUART4() rccResetAPB1(RCC_APB1RSTR_UART4RST) - -/** - * @brief Enables the UART5 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableUART5(lp) rccEnableAPB1(RCC_APB1ENR_UART5EN, lp) - -/** - * @brief Disables the UART5 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableUART5(lp) rccDisableAPB1(RCC_APB1ENR_UART5EN, lp) - -/** - * @brief Resets the UART5 peripheral. - * - * @api - */ -#define rccResetUART5() rccResetAPB1(RCC_APB1RSTR_UART5RST) -/** @} */ - -/** - * @name USB peripheral specific RCC operations - * @{ - */ -/** - * @brief Enables the USB peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableUSB(lp) rccEnableAPB1(RCC_APB1ENR_USBEN, lp) - -/** - * @brief Disables the USB peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableUSB(lp) rccDisableAPB1(RCC_APB1ENR_USBEN, lp) - -/** - * @brief Resets the USB peripheral. - * - * @api - */ -#define rccResetUSB() rccResetAPB1(RCC_APB1RSTR_USBRST) -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif -#ifdef __cplusplus -} -#endif - -#endif /* _STM32_RCC_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32F1xx/stm32f10x.h b/firmware/chibios/os/hal/platforms/STM32F1xx/stm32f10x.h deleted file mode 100644 index 2c085669e9..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F1xx/stm32f10x.h +++ /dev/null @@ -1,8360 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. - * This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for STM32F10x Connectivity line, - * High density, High density value line, Medium density, - * Medium density Value line, Low density, Low density Value line - * and XL-density devices. - * - * The file is the unique include file that the application programmer - * is using in the C source code, usually in main.c. This file contains: - * - Configuration section that allows to select: - * - The device used in the target application - * - To use or not the peripheral’s drivers in application code(i.e. - * code will be based on direct access to peripheral’s registers - * rather than drivers API), this option is controlled by - * "#define USE_STDPERIPH_DRIVER" - * - To change few application-specific parameters such as the HSE - * crystal frequency - * - Data structures and the address mapping for all peripherals - * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f10x - * @{ - */ - -#ifndef __STM32F10x_H -#define __STM32F10x_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup Library_configuration_section - * @{ - */ - -/* Uncomment the line below according to the target STM32 device used in your - application - */ - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) - /* CHIBIOS FIX */ -#include "board.h" - /* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */ - /* #define STM32F10X_LD_VL */ /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */ - /* #define STM32F10X_MD */ /*!< STM32F10X_MD: STM32 Medium density devices */ - /* #define STM32F10X_MD_VL */ /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */ - /* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */ - /* #define STM32F10X_HD_VL */ /*!< STM32F10X_HD_VL: STM32 High density value line devices */ - /* #define STM32F10X_XL */ /*!< STM32F10X_XL: STM32 XL-density devices */ - /* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */ -#endif -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - - - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers - where the Flash memory density ranges between 16 and 32 Kbytes. - - Low-density value line devices are STM32F100xx microcontrollers where the Flash - memory density ranges between 16 and 32 Kbytes. - - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers - where the Flash memory density ranges between 64 and 128 Kbytes. - - Medium-density value line devices are STM32F100xx microcontrollers where the - Flash memory density ranges between 64 and 128 Kbytes. - - High-density devices are STM32F101xx and STM32F103xx microcontrollers where - the Flash memory density ranges between 256 and 512 Kbytes. - - High-density value line devices are STM32F100xx microcontrollers where the - Flash memory density ranges between 256 and 512 Kbytes. - - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where - the Flash memory density ranges between 512 and 1024 Kbytes. - - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. - */ - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) - #error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)" -#endif - -#if !defined USE_STDPERIPH_DRIVER -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - /*#define USE_STDPERIPH_DRIVER*/ -#endif - -/** - * @brief In the following line adjust the value of External High Speed oscillator (HSE) - used in your application - - Tip: To avoid modifying this file each time you need to use different HSE, you - can define the HSE value in your toolchain compiler preprocessor. - */ -#if !defined HSE_VALUE - #ifdef STM32F10X_CL - #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ - #else - #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ - #endif /* STM32F10X_CL */ -#endif /* HSE_VALUE */ - - -/** - * @brief In the following line adjust the External High Speed oscillator (HSE) Startup - Timeout value - */ -#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ - -#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ - -/** - * @brief STM32F10x Standard Peripheral Library version number - */ -#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */ -#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */ -#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __STM32F10X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32F10X_STDPERIPH_VERSION ( (__STM32F10X_STDPERIPH_VERSION_MAIN << 24)\ - |(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16)\ - |(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8)\ - |(__STM32F10X_STDPERIPH_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ - -/** - * @brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ -/* CHIBIOS FIX */ -#define __CM3_REV 0x0201 /*!< Core revision r2p1, not sure it is right */ -/* END CHIBIOS FIX */ -#ifdef STM32F10X_XL - #define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */ -#else - #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */ -#endif /* STM32F10X_XL */ -#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * @brief STM32F10x Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - -/****** STM32 specific Interrupt Numbers *********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMPER_IRQn = 2, /*!< Tamper Interrupt */ - RTC_IRQn = 3, /*!< RTC global Interrupt */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ - DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ - DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ - DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ - DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ - DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ - DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ - -#ifdef STM32F10X_LD - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ - TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ - USB_FS_WKUP_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ -#endif /* STM32F10X_LD */ - -#ifdef STM32F10X_LD_VL - ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ - TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ - TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ - TIM7_IRQn = 55 /*!< TIM7 Interrupt */ -#endif /* STM32F10X_LD_VL */ - -#ifdef STM32F10X_MD - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ - TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ - USB_FS_WKUP_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ -#endif /* STM32F10X_MD */ - -#ifdef STM32F10X_MD_VL - ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ - TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ - TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ - TIM7_IRQn = 55 /*!< TIM7 Interrupt */ -#endif /* STM32F10X_MD_VL */ - -#ifdef STM32F10X_HD - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ - TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ - USB_FS_WKUP_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ - TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ - TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ - TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ - FSMC_IRQn = 48, /*!< FSMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ - TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ - DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ -#endif /* STM32F10X_HD */ - -#ifdef STM32F10X_HD_VL - ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ - TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ - TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ - TIM12_IRQn = 43, /*!< TIM12 global Interrupt */ - TIM13_IRQn = 44, /*!< TIM13 global Interrupt */ - TIM14_IRQn = 45, /*!< TIM14 global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ - TIM7_IRQn = 55, /*!< TIM7 Interrupt */ - DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ - DMA2_Channel5_IRQn = 60 /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is - mapped at position 60 only if the MISC_REMAP bit in - the AFIO_MAPR2 register is set) */ -#endif /* STM32F10X_HD_VL */ - -#ifdef STM32F10X_XL - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break Interrupt and TIM9 global Interrupt */ - TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global Interrupt */ - TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ - USB_FS_WKUP_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ - TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global Interrupt */ - TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global Interrupt */ - TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ - FSMC_IRQn = 48, /*!< FSMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ - TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ - DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ -#endif /* STM32F10X_XL */ - -#ifdef STM32F10X_CL - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ - TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ - TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ - DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ - DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ - ETH_IRQn = 61, /*!< Ethernet global Interrupt */ - ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ - CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ - CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ - CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ - CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ - OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */ -#endif /* STM32F10X_CL */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm3.h" -/* CHIBIOS FIX */ -/*#include "system_stm32f10x.h"*/ -#include - -/** @addtogroup Exported_types - * @{ - */ - -/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ -typedef int32_t s32; -typedef int16_t s16; -typedef int8_t s8; - -typedef const int32_t sc32; /*!< Read Only */ -typedef const int16_t sc16; /*!< Read Only */ -typedef const int8_t sc8; /*!< Read Only */ - -typedef __IO int32_t vs32; -typedef __IO int16_t vs16; -typedef __IO int8_t vs8; - -typedef __I int32_t vsc32; /*!< Read Only */ -typedef __I int16_t vsc16; /*!< Read Only */ -typedef __I int8_t vsc8; /*!< Read Only */ - -typedef uint32_t u32; -typedef uint16_t u16; -typedef uint8_t u8; - -typedef const uint32_t uc32; /*!< Read Only */ -typedef const uint16_t uc16; /*!< Read Only */ -typedef const uint8_t uc8; /*!< Read Only */ - -typedef __IO uint32_t vu32; -typedef __IO uint16_t vu16; -typedef __IO uint8_t vu8; - -typedef __I uint32_t vuc32; /*!< Read Only */ -typedef __I uint16_t vuc16; /*!< Read Only */ -typedef __I uint8_t vuc8; /*!< Read Only */ - -typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; - -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; - -/*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */ -#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT -#define HSE_Value HSE_VALUE -#define HSI_Value HSI_VALUE -/** - * @} - */ - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t SR; - __IO uint32_t CR1; - __IO uint32_t CR2; - __IO uint32_t SMPR1; - __IO uint32_t SMPR2; - __IO uint32_t JOFR1; - __IO uint32_t JOFR2; - __IO uint32_t JOFR3; - __IO uint32_t JOFR4; - __IO uint32_t HTR; - __IO uint32_t LTR; - __IO uint32_t SQR1; - __IO uint32_t SQR2; - __IO uint32_t SQR3; - __IO uint32_t JSQR; - __IO uint32_t JDR1; - __IO uint32_t JDR2; - __IO uint32_t JDR3; - __IO uint32_t JDR4; - __IO uint32_t DR; -} ADC_TypeDef; - -/** - * @brief Backup Registers - */ - -typedef struct -{ - uint32_t RESERVED0; - __IO uint16_t DR1; - uint16_t RESERVED1; - __IO uint16_t DR2; - uint16_t RESERVED2; - __IO uint16_t DR3; - uint16_t RESERVED3; - __IO uint16_t DR4; - uint16_t RESERVED4; - __IO uint16_t DR5; - uint16_t RESERVED5; - __IO uint16_t DR6; - uint16_t RESERVED6; - __IO uint16_t DR7; - uint16_t RESERVED7; - __IO uint16_t DR8; - uint16_t RESERVED8; - __IO uint16_t DR9; - uint16_t RESERVED9; - __IO uint16_t DR10; - uint16_t RESERVED10; - __IO uint16_t RTCCR; - uint16_t RESERVED11; - __IO uint16_t CR; - uint16_t RESERVED12; - __IO uint16_t CSR; - uint16_t RESERVED13[5]; - __IO uint16_t DR11; - uint16_t RESERVED14; - __IO uint16_t DR12; - uint16_t RESERVED15; - __IO uint16_t DR13; - uint16_t RESERVED16; - __IO uint16_t DR14; - uint16_t RESERVED17; - __IO uint16_t DR15; - uint16_t RESERVED18; - __IO uint16_t DR16; - uint16_t RESERVED19; - __IO uint16_t DR17; - uint16_t RESERVED20; - __IO uint16_t DR18; - uint16_t RESERVED21; - __IO uint16_t DR19; - uint16_t RESERVED22; - __IO uint16_t DR20; - uint16_t RESERVED23; - __IO uint16_t DR21; - uint16_t RESERVED24; - __IO uint16_t DR22; - uint16_t RESERVED25; - __IO uint16_t DR23; - uint16_t RESERVED26; - __IO uint16_t DR24; - uint16_t RESERVED27; - __IO uint16_t DR25; - uint16_t RESERVED28; - __IO uint16_t DR26; - uint16_t RESERVED29; - __IO uint16_t DR27; - uint16_t RESERVED30; - __IO uint16_t DR28; - uint16_t RESERVED31; - __IO uint16_t DR29; - uint16_t RESERVED32; - __IO uint16_t DR30; - uint16_t RESERVED33; - __IO uint16_t DR31; - uint16_t RESERVED34; - __IO uint16_t DR32; - uint16_t RESERVED35; - __IO uint16_t DR33; - uint16_t RESERVED36; - __IO uint16_t DR34; - uint16_t RESERVED37; - __IO uint16_t DR35; - uint16_t RESERVED38; - __IO uint16_t DR36; - uint16_t RESERVED39; - __IO uint16_t DR37; - uint16_t RESERVED40; - __IO uint16_t DR38; - uint16_t RESERVED41; - __IO uint16_t DR39; - uint16_t RESERVED42; - __IO uint16_t DR40; - uint16_t RESERVED43; - __IO uint16_t DR41; - uint16_t RESERVED44; - __IO uint16_t DR42; - uint16_t RESERVED45; -} BKP_TypeDef; - -/** - * @brief Controller Area Network TxMailBox - */ - -typedef struct -{ - __IO uint32_t TIR; - __IO uint32_t TDTR; - __IO uint32_t TDLR; - __IO uint32_t TDHR; -} CAN_TxMailBox_TypeDef; - -/** - * @brief Controller Area Network FIFOMailBox - */ - -typedef struct -{ - __IO uint32_t RIR; - __IO uint32_t RDTR; - __IO uint32_t RDLR; - __IO uint32_t RDHR; -} CAN_FIFOMailBox_TypeDef; - -/** - * @brief Controller Area Network FilterRegister - */ - -typedef struct -{ - __IO uint32_t FR1; - __IO uint32_t FR2; -} CAN_FilterRegister_TypeDef; - -/** - * @brief Controller Area Network - */ - -typedef struct -{ - __IO uint32_t MCR; - __IO uint32_t MSR; - __IO uint32_t TSR; - __IO uint32_t RF0R; - __IO uint32_t RF1R; - __IO uint32_t IER; - __IO uint32_t ESR; - __IO uint32_t BTR; - uint32_t RESERVED0[88]; - CAN_TxMailBox_TypeDef sTxMailBox[3]; - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; - uint32_t RESERVED1[12]; - __IO uint32_t FMR; - __IO uint32_t FM1R; - uint32_t RESERVED2; - __IO uint32_t FS1R; - uint32_t RESERVED3; - __IO uint32_t FFA1R; - uint32_t RESERVED4; - __IO uint32_t FA1R; - uint32_t RESERVED5[8]; -#ifndef STM32F10X_CL - CAN_FilterRegister_TypeDef sFilterRegister[14]; -#else - CAN_FilterRegister_TypeDef sFilterRegister[28]; -#endif /* STM32F10X_CL */ -} CAN_TypeDef; - -/** - * @brief Consumer Electronics Control (CEC) - */ -typedef struct -{ - __IO uint32_t CFGR; - __IO uint32_t OAR; - __IO uint32_t PRES; - __IO uint32_t ESR; - __IO uint32_t CSR; - __IO uint32_t TXD; - __IO uint32_t RXD; -} CEC_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; - __IO uint8_t IDR; - uint8_t RESERVED0; - uint16_t RESERVED1; - __IO uint32_t CR; -} CRC_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t SWTRIGR; - __IO uint32_t DHR12R1; - __IO uint32_t DHR12L1; - __IO uint32_t DHR8R1; - __IO uint32_t DHR12R2; - __IO uint32_t DHR12L2; - __IO uint32_t DHR8R2; - __IO uint32_t DHR12RD; - __IO uint32_t DHR12LD; - __IO uint32_t DHR8RD; - __IO uint32_t DOR1; - __IO uint32_t DOR2; -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - __IO uint32_t SR; -#endif -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; - __IO uint32_t CR; -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; - __IO uint32_t CNDTR; - __IO uint32_t CPAR; - __IO uint32_t CMAR; -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; - __IO uint32_t IFCR; -} DMA_TypeDef; - -/** - * @brief Ethernet MAC - */ - -typedef struct -{ - __IO uint32_t MACCR; - __IO uint32_t MACFFR; - __IO uint32_t MACHTHR; - __IO uint32_t MACHTLR; - __IO uint32_t MACMIIAR; - __IO uint32_t MACMIIDR; - __IO uint32_t MACFCR; - __IO uint32_t MACVLANTR; /* 8 */ - uint32_t RESERVED0[2]; - __IO uint32_t MACRWUFFR; /* 11 */ - __IO uint32_t MACPMTCSR; - uint32_t RESERVED1[2]; - __IO uint32_t MACSR; /* 15 */ - __IO uint32_t MACIMR; - __IO uint32_t MACA0HR; - __IO uint32_t MACA0LR; - __IO uint32_t MACA1HR; - __IO uint32_t MACA1LR; - __IO uint32_t MACA2HR; - __IO uint32_t MACA2LR; - __IO uint32_t MACA3HR; - __IO uint32_t MACA3LR; /* 24 */ - uint32_t RESERVED2[40]; - __IO uint32_t MMCCR; /* 65 */ - __IO uint32_t MMCRIR; - __IO uint32_t MMCTIR; - __IO uint32_t MMCRIMR; - __IO uint32_t MMCTIMR; /* 69 */ - uint32_t RESERVED3[14]; - __IO uint32_t MMCTGFSCCR; /* 84 */ - __IO uint32_t MMCTGFMSCCR; - uint32_t RESERVED4[5]; - __IO uint32_t MMCTGFCR; - uint32_t RESERVED5[10]; - __IO uint32_t MMCRFCECR; - __IO uint32_t MMCRFAECR; - uint32_t RESERVED6[10]; - __IO uint32_t MMCRGUFCR; - uint32_t RESERVED7[334]; - __IO uint32_t PTPTSCR; - __IO uint32_t PTPSSIR; - __IO uint32_t PTPTSHR; - __IO uint32_t PTPTSLR; - __IO uint32_t PTPTSHUR; - __IO uint32_t PTPTSLUR; - __IO uint32_t PTPTSAR; - __IO uint32_t PTPTTHR; - __IO uint32_t PTPTTLR; - uint32_t RESERVED8[567]; - __IO uint32_t DMABMR; - __IO uint32_t DMATPDR; - __IO uint32_t DMARPDR; - __IO uint32_t DMARDLAR; - __IO uint32_t DMATDLAR; - __IO uint32_t DMASR; - __IO uint32_t DMAOMR; - __IO uint32_t DMAIER; - __IO uint32_t DMAMFBOCR; - uint32_t RESERVED9[9]; - __IO uint32_t DMACHTDR; - __IO uint32_t DMACHRDR; - __IO uint32_t DMACHTBAR; - __IO uint32_t DMACHRBAR; -} ETH_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; - __IO uint32_t EMR; - __IO uint32_t RTSR; - __IO uint32_t FTSR; - __IO uint32_t SWIER; - __IO uint32_t PR; -} EXTI_TypeDef; - -/** - * @brief FLASH Registers - */ - -typedef struct -{ - __IO uint32_t ACR; - __IO uint32_t KEYR; - __IO uint32_t OPTKEYR; - __IO uint32_t SR; - __IO uint32_t CR; - __IO uint32_t AR; - __IO uint32_t RESERVED; - __IO uint32_t OBR; - __IO uint32_t WRPR; -#ifdef STM32F10X_XL - uint32_t RESERVED1[8]; - __IO uint32_t KEYR2; - uint32_t RESERVED2; - __IO uint32_t SR2; - __IO uint32_t CR2; - __IO uint32_t AR2; -#endif /* STM32F10X_XL */ -} FLASH_TypeDef; - -/** - * @brief Option Bytes Registers - */ - -typedef struct -{ - __IO uint16_t RDP; - __IO uint16_t USER; - __IO uint16_t Data0; - __IO uint16_t Data1; - __IO uint16_t WRP0; - __IO uint16_t WRP1; - __IO uint16_t WRP2; - __IO uint16_t WRP3; -} OB_TypeDef; - -/** - * @brief Flexible Static Memory Controller - */ - -typedef struct -{ - __IO uint32_t BTCR[8]; -} FSMC_Bank1_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank1E - */ - -typedef struct -{ - __IO uint32_t BWTR[7]; -} FSMC_Bank1E_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank2 - */ - -typedef struct -{ - __IO uint32_t PCR2; - __IO uint32_t SR2; - __IO uint32_t PMEM2; - __IO uint32_t PATT2; - uint32_t RESERVED0; - __IO uint32_t ECCR2; -} FSMC_Bank2_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank3 - */ - -typedef struct -{ - __IO uint32_t PCR3; - __IO uint32_t SR3; - __IO uint32_t PMEM3; - __IO uint32_t PATT3; - uint32_t RESERVED0; - __IO uint32_t ECCR3; -} FSMC_Bank3_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank4 - */ - -typedef struct -{ - __IO uint32_t PCR4; - __IO uint32_t SR4; - __IO uint32_t PMEM4; - __IO uint32_t PATT4; - __IO uint32_t PIO4; -} FSMC_Bank4_TypeDef; - -/** - * @brief General Purpose I/O - */ - -typedef struct -{ - __IO uint32_t CRL; - __IO uint32_t CRH; - __IO uint32_t IDR; - __IO uint32_t ODR; - __IO uint32_t BSRR; - __IO uint32_t BRR; - __IO uint32_t LCKR; -} GPIO_TypeDef; - -/** - * @brief Alternate Function I/O - */ - -typedef struct -{ - __IO uint32_t EVCR; - __IO uint32_t MAPR; - __IO uint32_t EXTICR[4]; - uint32_t RESERVED0; - __IO uint32_t MAPR2; -} AFIO_TypeDef; -/** - * @brief Inter Integrated Circuit Interface - */ - -typedef struct -{ - __IO uint16_t CR1; - uint16_t RESERVED0; - __IO uint16_t CR2; - uint16_t RESERVED1; - __IO uint16_t OAR1; - uint16_t RESERVED2; - __IO uint16_t OAR2; - uint16_t RESERVED3; - __IO uint16_t DR; - uint16_t RESERVED4; - __IO uint16_t SR1; - uint16_t RESERVED5; - __IO uint16_t SR2; - uint16_t RESERVED6; - __IO uint16_t CCR; - uint16_t RESERVED7; - __IO uint16_t TRISE; - uint16_t RESERVED8; -} I2C_TypeDef; - -/** - * @brief Independent WATCHDOG - */ - -typedef struct -{ - __IO uint32_t KR; - __IO uint32_t PR; - __IO uint32_t RLR; - __IO uint32_t SR; -} IWDG_TypeDef; - -/** - * @brief Power Control - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t CSR; -} PWR_TypeDef; - -/** - * @brief Reset and Clock Control - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t CFGR; - __IO uint32_t CIR; - __IO uint32_t APB2RSTR; - __IO uint32_t APB1RSTR; - __IO uint32_t AHBENR; - __IO uint32_t APB2ENR; - __IO uint32_t APB1ENR; - __IO uint32_t BDCR; - __IO uint32_t CSR; - -#ifdef STM32F10X_CL - __IO uint32_t AHBRSTR; - __IO uint32_t CFGR2; -#endif /* STM32F10X_CL */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - uint32_t RESERVED0; - __IO uint32_t CFGR2; -#endif /* STM32F10X_LD_VL || STM32F10X_MD_VL || STM32F10X_HD_VL */ -} RCC_TypeDef; - -/** - * @brief Real-Time Clock - */ - -typedef struct -{ - __IO uint16_t CRH; - uint16_t RESERVED0; - __IO uint16_t CRL; - uint16_t RESERVED1; - __IO uint16_t PRLH; - uint16_t RESERVED2; - __IO uint16_t PRLL; - uint16_t RESERVED3; - __IO uint16_t DIVH; - uint16_t RESERVED4; - __IO uint16_t DIVL; - uint16_t RESERVED5; - __IO uint16_t CNTH; - uint16_t RESERVED6; - __IO uint16_t CNTL; - uint16_t RESERVED7; - __IO uint16_t ALRH; - uint16_t RESERVED8; - __IO uint16_t ALRL; - uint16_t RESERVED9; -} RTC_TypeDef; - -/** - * @brief SD host Interface - */ - -typedef struct -{ - __IO uint32_t POWER; - __IO uint32_t CLKCR; - __IO uint32_t ARG; - __IO uint32_t CMD; - __I uint32_t RESPCMD; - __I uint32_t RESP1; - __I uint32_t RESP2; - __I uint32_t RESP3; - __I uint32_t RESP4; - __IO uint32_t DTIMER; - __IO uint32_t DLEN; - __IO uint32_t DCTRL; - __I uint32_t DCOUNT; - __I uint32_t STA; - __IO uint32_t ICR; - __IO uint32_t MASK; - uint32_t RESERVED0[2]; - __I uint32_t FIFOCNT; - uint32_t RESERVED1[13]; - __IO uint32_t FIFO; -} SDIO_TypeDef; - -/** - * @brief Serial Peripheral Interface - */ - -typedef struct -{ - __IO uint16_t CR1; - uint16_t RESERVED0; - __IO uint16_t CR2; - uint16_t RESERVED1; - __IO uint16_t SR; - uint16_t RESERVED2; - __IO uint16_t DR; - uint16_t RESERVED3; - __IO uint16_t CRCPR; - uint16_t RESERVED4; - __IO uint16_t RXCRCR; - uint16_t RESERVED5; - __IO uint16_t TXCRCR; - uint16_t RESERVED6; - __IO uint16_t I2SCFGR; - uint16_t RESERVED7; - __IO uint16_t I2SPR; - uint16_t RESERVED8; -} SPI_TypeDef; - -/** - * @brief TIM - */ - -typedef struct -{ - __IO uint16_t CR1; - uint16_t RESERVED0; - __IO uint16_t CR2; - uint16_t RESERVED1; - __IO uint16_t SMCR; - uint16_t RESERVED2; - __IO uint16_t DIER; - uint16_t RESERVED3; - __IO uint16_t SR; - uint16_t RESERVED4; - __IO uint16_t EGR; - uint16_t RESERVED5; - __IO uint16_t CCMR1; - uint16_t RESERVED6; - __IO uint16_t CCMR2; - uint16_t RESERVED7; - __IO uint16_t CCER; - uint16_t RESERVED8; - __IO uint16_t CNT; - uint16_t RESERVED9; - __IO uint16_t PSC; - uint16_t RESERVED10; - __IO uint16_t ARR; - uint16_t RESERVED11; - __IO uint16_t RCR; - uint16_t RESERVED12; - __IO uint16_t CCR1; - uint16_t RESERVED13; - __IO uint16_t CCR2; - uint16_t RESERVED14; - __IO uint16_t CCR3; - uint16_t RESERVED15; - __IO uint16_t CCR4; - uint16_t RESERVED16; - __IO uint16_t BDTR; - uint16_t RESERVED17; - __IO uint16_t DCR; - uint16_t RESERVED18; - __IO uint16_t DMAR; - uint16_t RESERVED19; -} TIM_TypeDef; - -/** - * @brief Universal Synchronous Asynchronous Receiver Transmitter - */ - -typedef struct -{ - __IO uint16_t SR; - uint16_t RESERVED0; - __IO uint16_t DR; - uint16_t RESERVED1; - __IO uint16_t BRR; - uint16_t RESERVED2; - __IO uint16_t CR1; - uint16_t RESERVED3; - __IO uint16_t CR2; - uint16_t RESERVED4; - __IO uint16_t CR3; - uint16_t RESERVED5; - __IO uint16_t GTPR; - uint16_t RESERVED6; -} USART_TypeDef; - -/** - * @brief Window WATCHDOG - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t CFR; - __IO uint32_t SR; -} WWDG_TypeDef; - -/** - * @} - */ - -/** @addtogroup Peripheral_memory_map - * @{ - */ - - -#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ -#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ - -#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ - -#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ - -/*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) - -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) -#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) -#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) -#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) -#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800) -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) -#define UART5_BASE (APB1PERIPH_BASE + 0x5000) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) -#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) -#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400) -#define CEC_BASE (APB1PERIPH_BASE + 0x7800) - -#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) -#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) -#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) -#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) -#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) -#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) -#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) -#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) -#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) -#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) -#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) -#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) -#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) -#define USART1_BASE (APB2PERIPH_BASE + 0x3800) -#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) -#define TIM15_BASE (APB2PERIPH_BASE + 0x4000) -#define TIM16_BASE (APB2PERIPH_BASE + 0x4400) -#define TIM17_BASE (APB2PERIPH_BASE + 0x4800) -#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00) -#define TIM10_BASE (APB2PERIPH_BASE + 0x5000) -#define TIM11_BASE (APB2PERIPH_BASE + 0x5400) - -#define SDIO_BASE (PERIPH_BASE + 0x18000) - -#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) -#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) -#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) -#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) -#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) -#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) -#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) -#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) -#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) -#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) -#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) -#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) -#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) -#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) -#define RCC_BASE (AHBPERIPH_BASE + 0x1000) -#define CRC_BASE (AHBPERIPH_BASE + 0x3000) - -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */ -#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ - -#define ETH_BASE (AHBPERIPH_BASE + 0x8000) -#define ETH_MAC_BASE (ETH_BASE) -#define ETH_MMC_BASE (ETH_BASE + 0x0100) -#define ETH_PTP_BASE (ETH_BASE + 0x0700) -#define ETH_DMA_BASE (ETH_BASE + 0x1000) - -#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */ -#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */ -#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */ -#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */ -#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */ - -#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ - -/** - * @} - */ - -/** @addtogroup Peripheral_declaration - * @{ - */ - -#define TIM2 ((TIM_TypeDef *) TIM2_BASE) -#define TIM3 ((TIM_TypeDef *) TIM3_BASE) -#define TIM4 ((TIM_TypeDef *) TIM4_BASE) -#define TIM5 ((TIM_TypeDef *) TIM5_BASE) -#define TIM6 ((TIM_TypeDef *) TIM6_BASE) -#define TIM7 ((TIM_TypeDef *) TIM7_BASE) -#define TIM12 ((TIM_TypeDef *) TIM12_BASE) -#define TIM13 ((TIM_TypeDef *) TIM13_BASE) -#define TIM14 ((TIM_TypeDef *) TIM14_BASE) -#define RTC ((RTC_TypeDef *) RTC_BASE) -#define WWDG ((WWDG_TypeDef *) WWDG_BASE) -#define IWDG ((IWDG_TypeDef *) IWDG_BASE) -#define SPI2 ((SPI_TypeDef *) SPI2_BASE) -#define SPI3 ((SPI_TypeDef *) SPI3_BASE) -#define USART2 ((USART_TypeDef *) USART2_BASE) -#define USART3 ((USART_TypeDef *) USART3_BASE) -#define UART4 ((USART_TypeDef *) UART4_BASE) -#define UART5 ((USART_TypeDef *) UART5_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define CAN1 ((CAN_TypeDef *) CAN1_BASE) -#define CAN2 ((CAN_TypeDef *) CAN2_BASE) -#define BKP ((BKP_TypeDef *) BKP_BASE) -#define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) -#define CEC ((CEC_TypeDef *) CEC_BASE) -#define AFIO ((AFIO_TypeDef *) AFIO_BASE) -#define EXTI ((EXTI_TypeDef *) EXTI_BASE) -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) -#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) -#define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC2 ((ADC_TypeDef *) ADC2_BASE) -#define TIM1 ((TIM_TypeDef *) TIM1_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#define TIM8 ((TIM_TypeDef *) TIM8_BASE) -#define USART1 ((USART_TypeDef *) USART1_BASE) -#define ADC3 ((ADC_TypeDef *) ADC3_BASE) -#define TIM15 ((TIM_TypeDef *) TIM15_BASE) -#define TIM16 ((TIM_TypeDef *) TIM16_BASE) -#define TIM17 ((TIM_TypeDef *) TIM17_BASE) -#define TIM9 ((TIM_TypeDef *) TIM9_BASE) -#define TIM10 ((TIM_TypeDef *) TIM10_BASE) -#define TIM11 ((TIM_TypeDef *) TIM11_BASE) -#define SDIO ((SDIO_TypeDef *) SDIO_BASE) -#define DMA1 ((DMA_TypeDef *) DMA1_BASE) -#define DMA2 ((DMA_TypeDef *) DMA2_BASE) -#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) -#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) -#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) -#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) -#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) -#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) -#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) -#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) -#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) -#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) -#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) -#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) -#define RCC ((RCC_TypeDef *) RCC_BASE) -#define CRC ((CRC_TypeDef *) CRC_BASE) -#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) -#define OB ((OB_TypeDef *) OB_BASE) -#define ETH ((ETH_TypeDef *) ETH_BASE) -#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) -#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) -#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) -#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) -#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) -#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) - -/** - * @} - */ - -/** @addtogroup Exported_constants - * @{ - */ - - /** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ - -/******************************************************************************/ -/* Peripheral Registers_Bits_Definition */ -/******************************************************************************/ - -/******************************************************************************/ -/* */ -/* CRC calculation unit */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ - - -/******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ - - -/******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */ - -/******************************************************************************/ -/* */ -/* Power Control */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for PWR_CR register ********************/ -#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */ -#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */ -#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */ -#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */ -#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */ - -#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */ -#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */ -#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */ -#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */ - -/*!< PVD level configuration */ -#define PWR_CR_PLS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */ -#define PWR_CR_PLS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */ -#define PWR_CR_PLS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */ -#define PWR_CR_PLS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */ -#define PWR_CR_PLS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */ -#define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */ -#define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */ -#define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */ - -#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */ - - -/******************* Bit definition for PWR_CSR register ********************/ -#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */ -#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */ -#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */ -#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */ - -/******************************************************************************/ -/* */ -/* Backup registers */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for BKP_DR1 register ********************/ -#define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR2 register ********************/ -#define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR3 register ********************/ -#define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR4 register ********************/ -#define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR5 register ********************/ -#define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR6 register ********************/ -#define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR7 register ********************/ -#define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR8 register ********************/ -#define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR9 register ********************/ -#define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR10 register *******************/ -#define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR11 register *******************/ -#define BKP_DR11_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR12 register *******************/ -#define BKP_DR12_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR13 register *******************/ -#define BKP_DR13_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR14 register *******************/ -#define BKP_DR14_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR15 register *******************/ -#define BKP_DR15_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR16 register *******************/ -#define BKP_DR16_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR17 register *******************/ -#define BKP_DR17_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/****************** Bit definition for BKP_DR18 register ********************/ -#define BKP_DR18_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR19 register *******************/ -#define BKP_DR19_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR20 register *******************/ -#define BKP_DR20_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR21 register *******************/ -#define BKP_DR21_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR22 register *******************/ -#define BKP_DR22_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR23 register *******************/ -#define BKP_DR23_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR24 register *******************/ -#define BKP_DR24_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR25 register *******************/ -#define BKP_DR25_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR26 register *******************/ -#define BKP_DR26_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR27 register *******************/ -#define BKP_DR27_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR28 register *******************/ -#define BKP_DR28_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR29 register *******************/ -#define BKP_DR29_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR30 register *******************/ -#define BKP_DR30_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR31 register *******************/ -#define BKP_DR31_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR32 register *******************/ -#define BKP_DR32_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR33 register *******************/ -#define BKP_DR33_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR34 register *******************/ -#define BKP_DR34_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR35 register *******************/ -#define BKP_DR35_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR36 register *******************/ -#define BKP_DR36_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR37 register *******************/ -#define BKP_DR37_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR38 register *******************/ -#define BKP_DR38_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR39 register *******************/ -#define BKP_DR39_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR40 register *******************/ -#define BKP_DR40_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR41 register *******************/ -#define BKP_DR41_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR42 register *******************/ -#define BKP_DR42_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/****************** Bit definition for BKP_RTCCR register *******************/ -#define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */ -#define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */ -#define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */ -#define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */ - -/******************** Bit definition for BKP_CR register ********************/ -#define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */ -#define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */ - -/******************* Bit definition for BKP_CSR register ********************/ -#define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */ -#define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */ -#define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */ -#define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */ -#define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */ - -/******************************************************************************/ -/* */ -/* Reset and Clock Control */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for RCC_CR register ********************/ -#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */ -#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */ -#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */ -#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */ -#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */ -#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */ -#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */ -#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */ -#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */ -#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */ - -#ifdef STM32F10X_CL - #define RCC_CR_PLL2ON ((uint32_t)0x04000000) /*!< PLL2 enable */ - #define RCC_CR_PLL2RDY ((uint32_t)0x08000000) /*!< PLL2 clock ready flag */ - #define RCC_CR_PLL3ON ((uint32_t)0x10000000) /*!< PLL3 enable */ - #define RCC_CR_PLL3RDY ((uint32_t)0x20000000) /*!< PLL3 clock ready flag */ -#endif /* STM32F10X_CL */ - -/******************* Bit definition for RCC_CFGR register *******************/ -/*!< SW configuration */ -#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ -#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - -#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ -#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ -#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ - -/*!< SWS configuration */ -#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ -#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ -#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ -#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ - -/*!< HPRE configuration */ -#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ -#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ -#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ -#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ -#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ -#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ -#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ -#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ -#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ -#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ - -/*!< PPRE1 configuration */ -#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */ -#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ - -#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ -#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ - -/*!< PPRE2 configuration */ -#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */ -#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */ -#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */ -#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */ - -#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ -#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ - -/*!< ADCPPRE configuration */ -#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */ -#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */ -#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */ - -#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */ -#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */ -#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */ -#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */ - -#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */ - -#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */ - -/*!< PLLMUL configuration */ -#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ -#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ -#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */ - -#ifdef STM32F10X_CL - #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ - #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ - - #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ - #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ - - #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock * 4 */ - #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock * 5 */ - #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock * 6 */ - #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock * 7 */ - #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock * 8 */ - #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock * 9 */ - #define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /*!< PLL input clock * 6.5 */ - - #define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) /*!< USB OTG FS prescaler */ - -/*!< MCO configuration */ - #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */ - #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ - #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - - #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ - #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ - #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ - #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ - #define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ - #define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /*!< PLL2 clock selected as MCO source*/ - #define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/ - #define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */ - #define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */ -#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ - #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ - - #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ - #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ - - #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ - #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ - #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ - #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ - #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ - #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ - #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ - #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ - #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ - #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ - #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ - #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ - #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ - #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ - #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ - -/*!< MCO configuration */ - #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ - #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ - #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - - #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ - #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ - #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ - #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ - #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ -#else - #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ - #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */ - - #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */ - #define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */ - - #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ - #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ - #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ - #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ - #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ - #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ - #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ - #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ - #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ - #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ - #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ - #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ - #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ - #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ - #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ - #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB Device prescaler */ - -/*!< MCO configuration */ - #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ - #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ - #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - - #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ - #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ - #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ - #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ - #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ -#endif /* STM32F10X_CL */ - -/*!<****************** Bit definition for RCC_CIR register ********************/ -#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ -#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ -#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ -#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ -#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ -#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ -#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ -#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ -#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ -#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ -#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ -#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ -#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ -#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ -#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ -#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ -#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ - -#ifdef STM32F10X_CL - #define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) /*!< PLL2 Ready Interrupt flag */ - #define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) /*!< PLL3 Ready Interrupt flag */ - #define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) /*!< PLL2 Ready Interrupt Enable */ - #define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) /*!< PLL3 Ready Interrupt Enable */ - #define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) /*!< PLL2 Ready Interrupt Clear */ - #define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) /*!< PLL3 Ready Interrupt Clear */ -#endif /* STM32F10X_CL */ - -/***************** Bit definition for RCC_APB2RSTR register *****************/ -#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */ -#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */ -#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */ -#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */ -#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */ -#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */ - -#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) -#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /*!< ADC 2 interface reset */ -#endif - -#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */ -#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */ -#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 Timer reset */ -#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 Timer reset */ -#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 Timer reset */ -#endif - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) - #define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */ -#endif /* STM32F10X_LD && STM32F10X_LD_VL */ - -#if defined (STM32F10X_HD) || defined (STM32F10X_XL) - #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ - #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ - #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */ - #define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) /*!< ADC3 interface reset */ -#endif - -#if defined (STM32F10X_HD_VL) - #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ - #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ -#endif - -#ifdef STM32F10X_XL - #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000) /*!< TIM9 Timer reset */ - #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000) /*!< TIM10 Timer reset */ - #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000) /*!< TIM11 Timer reset */ -#endif /* STM32F10X_XL */ - -/***************** Bit definition for RCC_APB1RSTR register *****************/ -#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */ -#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */ -#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */ -#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */ -#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */ - -#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) -#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */ -#endif - -#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */ -#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */ - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) - #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */ - #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */ - #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */ - #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */ -#endif /* STM32F10X_LD && STM32F10X_LD_VL */ - -#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined (STM32F10X_XL) - #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */ -#endif - -#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_XL) - #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ - #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ - #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ - #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ - #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ - #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ - #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ -#endif - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ - #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ - #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ - #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC interface reset */ -#endif - -#if defined (STM32F10X_HD_VL) - #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ - #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ - #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ - #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ - #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ - #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ - #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ -#endif - -#ifdef STM32F10X_CL - #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) /*!< CAN2 reset */ -#endif /* STM32F10X_CL */ - -#ifdef STM32F10X_XL - #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ - #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ - #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ -#endif /* STM32F10X_XL */ - -/****************** Bit definition for RCC_AHBENR register ******************/ -#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */ -#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */ -#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */ -#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */ - -/* CHIBIOS FIX */ -//#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_HD_VL) -#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_XL) - #define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */ -#endif - -#if defined (STM32F10X_HD) || defined (STM32F10X_XL) - #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ - #define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */ -#endif - -#if defined (STM32F10X_HD_VL) - #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ -#endif - -#ifdef STM32F10X_CL - #define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */ - #define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) /*!< ETHERNET MAC clock enable */ - #define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) /*!< ETHERNET MAC Tx clock enable */ - #define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) /*!< ETHERNET MAC Rx clock enable */ -#endif /* STM32F10X_CL */ - -/****************** Bit definition for RCC_APB2ENR register *****************/ -#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */ -#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */ -#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */ -#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */ -#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */ -#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */ - -#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) -#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /*!< ADC 2 interface clock enable */ -#endif - -#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */ -#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */ -#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 Timer clock enable */ -#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 Timer clock enable */ -#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 Timer clock enable */ -#endif - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) - #define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */ -#endif /* STM32F10X_LD && STM32F10X_LD_VL */ - -#if defined (STM32F10X_HD) || defined (STM32F10X_XL) - #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ - #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ - #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */ - #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) /*!< DMA1 clock enable */ -#endif - -#if defined (STM32F10X_HD_VL) - #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ - #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ -#endif - -#ifdef STM32F10X_XL - #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000) /*!< TIM9 Timer clock enable */ - #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000) /*!< TIM10 Timer clock enable */ - #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000) /*!< TIM11 Timer clock enable */ -#endif - -/***************** Bit definition for RCC_APB1ENR register ******************/ -#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/ -#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */ -#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ -#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */ -#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ - -#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) -#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */ -#endif - -#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */ -#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */ - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) - #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */ - #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */ - #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */ - #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */ -#endif /* STM32F10X_LD && STM32F10X_LD_VL */ - -/* CHIBIOS FIX */ -//#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) -#if defined (STM32F10X_XL) || defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) - #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */ -#endif - -/* CHIBIOS FIX */ -//#if defined (STM32F10X_HD) || defined (STM32F10X_CL) -#if defined (STM32F10X_XL) || defined (STM32F10X_HD) || defined (STM32F10X_CL) - #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ - #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ - #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ - #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ - #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ - #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ - #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ -#endif - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ - #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ - #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ - #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC interface clock enable */ -#endif - -#ifdef STM32F10X_HD_VL - #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ - #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ - #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ - #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ - #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ - #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ - #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ -#endif /* STM32F10X_HD_VL */ - -#ifdef STM32F10X_CL - #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) /*!< CAN2 clock enable */ -#endif /* STM32F10X_CL */ - -#ifdef STM32F10X_XL - #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ - #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ - #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ -#endif /* STM32F10X_XL */ - -/******************* Bit definition for RCC_BDCR register *******************/ -#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ -#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ -#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ - -#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ -#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -/*!< RTC congiguration */ -#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ -#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ -#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ -#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */ - -#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ -#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */ - -/******************* Bit definition for RCC_CSR register ********************/ -#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ -#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ -#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */ -#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ -#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */ -#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ -#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ -#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ -#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ - -#ifdef STM32F10X_CL -/******************* Bit definition for RCC_AHBRSTR register ****************/ - #define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) /*!< USB OTG FS reset */ - #define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) /*!< ETHERNET MAC reset */ - -/******************* Bit definition for RCC_CFGR2 register ******************/ -/*!< PREDIV1 configuration */ - #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ - #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ - #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - - #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ - #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ - #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ - #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ - #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ - #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ - #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ - #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ - #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ - #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ - #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ - #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ - #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ - #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ - #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ - #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ - -/*!< PREDIV2 configuration */ - #define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) /*!< PREDIV2[3:0] bits */ - #define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) /*!< Bit 0 */ - #define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - #define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) /*!< Bit 2 */ - #define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - - #define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /*!< PREDIV2 input clock not divided */ - #define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) /*!< PREDIV2 input clock divided by 2 */ - #define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) /*!< PREDIV2 input clock divided by 3 */ - #define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) /*!< PREDIV2 input clock divided by 4 */ - #define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) /*!< PREDIV2 input clock divided by 5 */ - #define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) /*!< PREDIV2 input clock divided by 6 */ - #define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) /*!< PREDIV2 input clock divided by 7 */ - #define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) /*!< PREDIV2 input clock divided by 8 */ - #define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) /*!< PREDIV2 input clock divided by 9 */ - #define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) /*!< PREDIV2 input clock divided by 10 */ - #define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) /*!< PREDIV2 input clock divided by 11 */ - #define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) /*!< PREDIV2 input clock divided by 12 */ - #define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) /*!< PREDIV2 input clock divided by 13 */ - #define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) /*!< PREDIV2 input clock divided by 14 */ - #define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) /*!< PREDIV2 input clock divided by 15 */ - #define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) /*!< PREDIV2 input clock divided by 16 */ - -/*!< PLL2MUL configuration */ - #define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) /*!< PLL2MUL[3:0] bits */ - #define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ - #define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - #define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) /*!< Bit 2 */ - #define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - - #define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) /*!< PLL2 input clock * 8 */ - #define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) /*!< PLL2 input clock * 9 */ - #define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) /*!< PLL2 input clock * 10 */ - #define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) /*!< PLL2 input clock * 11 */ - #define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) /*!< PLL2 input clock * 12 */ - #define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) /*!< PLL2 input clock * 13 */ - #define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) /*!< PLL2 input clock * 14 */ - #define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) /*!< PLL2 input clock * 16 */ - #define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) /*!< PLL2 input clock * 20 */ - -/*!< PLL3MUL configuration */ - #define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) /*!< PLL3MUL[3:0] bits */ - #define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ - #define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ - #define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - #define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) /*!< Bit 3 */ - - #define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) /*!< PLL3 input clock * 8 */ - #define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) /*!< PLL3 input clock * 9 */ - #define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) /*!< PLL3 input clock * 10 */ - #define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) /*!< PLL3 input clock * 11 */ - #define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) /*!< PLL3 input clock * 12 */ - #define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) /*!< PLL3 input clock * 13 */ - #define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) /*!< PLL3 input clock * 14 */ - #define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) /*!< PLL3 input clock * 16 */ - #define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) /*!< PLL3 input clock * 20 */ - - #define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) /*!< PREDIV1 entry clock source */ - #define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) /*!< PLL2 selected as PREDIV1 entry clock source */ - #define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /*!< HSE selected as PREDIV1 entry clock source */ - #define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) /*!< I2S2 entry clock source */ - #define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */ -#endif /* STM32F10X_CL */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -/******************* Bit definition for RCC_CFGR2 register ******************/ -/*!< PREDIV1 configuration */ - #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ - #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ - #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - - #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ - #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ - #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ - #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ - #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ - #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ - #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ - #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ - #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ - #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ - #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ - #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ - #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ - #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ - #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ - #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ -#endif - -/******************************************************************************/ -/* */ -/* General Purpose and Alternate Function I/O */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for GPIO_CRL register *******************/ -#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ - -#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ -#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - -#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ -#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ -#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ -#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */ - -#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ -#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ - -#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ -#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ - -#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ -#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - -#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ -#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ - -#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ -#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ -#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ - -#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ -#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */ - -#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ -#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */ -#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */ - -#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ -#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */ - -#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ -#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */ -#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */ - -#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ -#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */ - -#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ -#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */ -#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */ - -/******************* Bit definition for GPIO_CRH register *******************/ -#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ - -#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ -#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - -#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ -#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ -#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ -#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */ - -#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ -#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */ - -#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ -#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */ - -#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ -#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - -#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ -#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ - -#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ -#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ -#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */ - -#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ -#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */ - -#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ -#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */ -#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */ - -#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ -#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */ - -#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ -#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */ -#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */ - -#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ -#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */ - -#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ -#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */ -#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */ - -/*!<****************** Bit definition for GPIO_IDR register *******************/ -#define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */ -#define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */ -#define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */ -#define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */ -#define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */ -#define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */ -#define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */ -#define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */ -#define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */ -#define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */ -#define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */ -#define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */ -#define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */ -#define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */ -#define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */ -#define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */ - -/******************* Bit definition for GPIO_ODR register *******************/ -#define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */ -#define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */ -#define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */ -#define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */ -#define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */ -#define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */ -#define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */ -#define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */ -#define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */ -#define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */ -#define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */ -#define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */ -#define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */ -#define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */ -#define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */ -#define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */ - -/****************** Bit definition for GPIO_BSRR register *******************/ -#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */ -#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */ -#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */ -#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */ -#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */ -#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */ -#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */ -#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */ -#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */ -#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */ -#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */ -#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */ -#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */ -#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */ -#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */ -#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */ - -#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */ -#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */ -#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */ -#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */ -#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */ -#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */ -#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */ -#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */ -#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */ -#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */ -#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */ -#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */ -#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */ -#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */ -#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */ -#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */ - -/******************* Bit definition for GPIO_BRR register *******************/ -#define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */ -#define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */ -#define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */ -#define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */ -#define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */ -#define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */ -#define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */ -#define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */ -#define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */ -#define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */ -#define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */ -#define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */ -#define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */ -#define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */ -#define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */ -#define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */ - -/****************** Bit definition for GPIO_LCKR register *******************/ -#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */ -#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */ -#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */ -#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */ -#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */ -#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */ -#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */ -#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */ -#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */ -#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */ -#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */ -#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */ -#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */ -#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */ -#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */ -#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */ -#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */ - -/*----------------------------------------------------------------------------*/ - -/****************** Bit definition for AFIO_EVCR register *******************/ -#define AFIO_EVCR_PIN ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */ -#define AFIO_EVCR_PIN_0 ((uint8_t)0x01) /*!< Bit 0 */ -#define AFIO_EVCR_PIN_1 ((uint8_t)0x02) /*!< Bit 1 */ -#define AFIO_EVCR_PIN_2 ((uint8_t)0x04) /*!< Bit 2 */ -#define AFIO_EVCR_PIN_3 ((uint8_t)0x08) /*!< Bit 3 */ - -/*!< PIN configuration */ -#define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) /*!< Pin 0 selected */ -#define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) /*!< Pin 1 selected */ -#define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) /*!< Pin 2 selected */ -#define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) /*!< Pin 3 selected */ -#define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) /*!< Pin 4 selected */ -#define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) /*!< Pin 5 selected */ -#define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) /*!< Pin 6 selected */ -#define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) /*!< Pin 7 selected */ -#define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) /*!< Pin 8 selected */ -#define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) /*!< Pin 9 selected */ -#define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) /*!< Pin 10 selected */ -#define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) /*!< Pin 11 selected */ -#define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) /*!< Pin 12 selected */ -#define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) /*!< Pin 13 selected */ -#define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) /*!< Pin 14 selected */ -#define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) /*!< Pin 15 selected */ - -#define AFIO_EVCR_PORT ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */ -#define AFIO_EVCR_PORT_0 ((uint8_t)0x10) /*!< Bit 0 */ -#define AFIO_EVCR_PORT_1 ((uint8_t)0x20) /*!< Bit 1 */ -#define AFIO_EVCR_PORT_2 ((uint8_t)0x40) /*!< Bit 2 */ - -/*!< PORT configuration */ -#define AFIO_EVCR_PORT_PA ((uint8_t)0x00) /*!< Port A selected */ -#define AFIO_EVCR_PORT_PB ((uint8_t)0x10) /*!< Port B selected */ -#define AFIO_EVCR_PORT_PC ((uint8_t)0x20) /*!< Port C selected */ -#define AFIO_EVCR_PORT_PD ((uint8_t)0x30) /*!< Port D selected */ -#define AFIO_EVCR_PORT_PE ((uint8_t)0x40) /*!< Port E selected */ - -#define AFIO_EVCR_EVOE ((uint8_t)0x80) /*!< Event Output Enable */ - -/****************** Bit definition for AFIO_MAPR register *******************/ -#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */ -#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */ -#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */ -#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */ - -#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ -#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -/* USART3_REMAP configuration */ -#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ -#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ -#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ - -#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ -#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */ - -/*!< TIM1_REMAP configuration */ -#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ -#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ -#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ - -#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ -#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -/*!< TIM2_REMAP configuration */ -#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ -#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ -#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ -#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ - -#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ -#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */ - -/*!< TIM3_REMAP configuration */ -#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ -#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ -#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ - -#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */ - -#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ -#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */ - -/*!< CAN_REMAP configuration */ -#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ -#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ -#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ - -#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ -#define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */ -#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */ -#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */ -#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */ -#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */ - -/*!< SWJ_CFG configuration */ -#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ -#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - -#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ -#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ -#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */ -#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */ - -#ifdef STM32F10X_CL -/*!< ETH_REMAP configuration */ - #define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */ - -/*!< CAN2_REMAP configuration */ - #define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) /*!< CAN2_REMAP bit (CAN2 I/O remapping) */ - -/*!< MII_RMII_SEL configuration */ - #define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */ - -/*!< SPI3_REMAP configuration */ - #define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) /*!< SPI3_REMAP bit (SPI3 remapping) */ - -/*!< TIM2ITR1_IREMAP configuration */ - #define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */ - -/*!< PTP_PPS_REMAP configuration */ - #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x40000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */ -#endif - -/***************** Bit definition for AFIO_EXTICR1 register *****************/ -#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */ -#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */ -#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */ -#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */ - -/*!< EXTI0 configuration */ -#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */ -#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */ -#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */ -#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */ -#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */ -#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */ -#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */ - -/*!< EXTI1 configuration */ -#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */ -#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */ -#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */ -#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */ -#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */ -#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */ -#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */ - -/*!< EXTI2 configuration */ -#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */ -#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */ -#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */ -#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */ -#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */ -#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */ -#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */ - -/*!< EXTI3 configuration */ -#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */ -#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */ -#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */ -#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */ -#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */ -#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */ -#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */ - -/***************** Bit definition for AFIO_EXTICR2 register *****************/ -#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */ -#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */ -#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */ -#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */ - -/*!< EXTI4 configuration */ -#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */ -#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */ -#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */ -#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */ -#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */ -#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */ -#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */ - -/* EXTI5 configuration */ -#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */ -#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */ -#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */ -#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */ -#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */ -#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */ -#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */ - -/*!< EXTI6 configuration */ -#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */ -#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */ -#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */ -#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */ -#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */ -#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */ -#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */ - -/*!< EXTI7 configuration */ -#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */ -#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */ -#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */ -#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */ -#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */ -#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */ -#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */ - -/***************** Bit definition for AFIO_EXTICR3 register *****************/ -#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */ -#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */ -#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */ -#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */ - -/*!< EXTI8 configuration */ -#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */ -#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */ -#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */ -#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */ -#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */ -#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */ -#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */ - -/*!< EXTI9 configuration */ -#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */ -#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */ -#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */ -#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */ -#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */ -#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */ -#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */ - -/*!< EXTI10 configuration */ -#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */ -#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */ -#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */ -#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */ -#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */ -#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */ -#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */ - -/*!< EXTI11 configuration */ -#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */ -#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */ -#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */ -#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */ -#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */ -#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */ -#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */ - -/***************** Bit definition for AFIO_EXTICR4 register *****************/ -#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */ -#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */ -#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */ -#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */ - -/* EXTI12 configuration */ -#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */ -#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */ -#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */ -#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */ -#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */ -#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */ -#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */ - -/* EXTI13 configuration */ -#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */ -#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */ -#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */ -#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */ -#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */ -#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */ -#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */ - -/*!< EXTI14 configuration */ -#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */ -#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */ -#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */ -#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */ -#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */ -#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */ -#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */ - -/*!< EXTI15 configuration */ -#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */ -#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */ -#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */ -#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */ -#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */ -#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */ -#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -/****************** Bit definition for AFIO_MAPR2 register ******************/ -#define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) /*!< TIM15 remapping */ -#define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) /*!< TIM16 remapping */ -#define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) /*!< TIM17 remapping */ -#define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) /*!< CEC remapping */ -#define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /*!< TIM1_DMA remapping */ -#endif - -#ifdef STM32F10X_HD_VL -#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ -#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ -#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ -#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800) /*!< TIM6/TIM7 and DAC DMA remapping */ -#define AFIO_MAPR2_TIM12_REMAP ((uint32_t)0x00001000) /*!< TIM12 remapping */ -#define AFIO_MAPR2_MISC_REMAP ((uint32_t)0x00002000) /*!< Miscellaneous remapping */ -#endif - -#ifdef STM32F10X_XL -/****************** Bit definition for AFIO_MAPR2 register ******************/ -#define AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020) /*!< TIM9 remapping */ -#define AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040) /*!< TIM10 remapping */ -#define AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080) /*!< TIM11 remapping */ -#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ -#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ -#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ -#endif - -/******************************************************************************/ -/* */ -/* SystemTick */ -/* */ -/******************************************************************************/ - -/***************** Bit definition for SysTick_CTRL register *****************/ -#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */ -#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */ -#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */ -#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */ - -/***************** Bit definition for SysTick_LOAD register *****************/ -#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ - -/***************** Bit definition for SysTick_VAL register ******************/ -#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */ - -/***************** Bit definition for SysTick_CALIB register ****************/ -#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */ -#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */ -#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */ - -/******************************************************************************/ -/* */ -/* Nested Vectored Interrupt Controller */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for NVIC_ISER register *******************/ -#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */ -#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_ICER register *******************/ -#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */ -#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_ISPR register *******************/ -#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */ -#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_ICPR register *******************/ -#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */ -#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_IABR register *******************/ -#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */ -#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_PRI0 register *******************/ -#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */ -#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */ -#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */ -#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */ - -/****************** Bit definition for NVIC_PRI1 register *******************/ -#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */ -#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */ -#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */ -#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */ - -/****************** Bit definition for NVIC_PRI2 register *******************/ -#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */ -#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */ -#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */ -#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */ - -/****************** Bit definition for NVIC_PRI3 register *******************/ -#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */ -#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */ -#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */ -#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */ - -/****************** Bit definition for NVIC_PRI4 register *******************/ -#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */ -#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */ -#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */ -#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */ - -/****************** Bit definition for NVIC_PRI5 register *******************/ -#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */ -#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */ -#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */ -#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */ - -/****************** Bit definition for NVIC_PRI6 register *******************/ -#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */ -#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */ -#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */ -#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */ - -/****************** Bit definition for NVIC_PRI7 register *******************/ -#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */ -#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */ -#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */ -#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */ - -/****************** Bit definition for SCB_CPUID register *******************/ -#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */ -#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */ -#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */ -#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */ -#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */ - -/******************* Bit definition for SCB_ICSR register *******************/ -#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */ -#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ -#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */ -#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */ -#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ -#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */ -#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */ -#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */ -#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */ -#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */ - -/******************* Bit definition for SCB_VTOR register *******************/ -#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */ -#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */ - -/*!<***************** Bit definition for SCB_AIRCR register *******************/ -#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */ -#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */ -#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */ - -#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */ -#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */ - -/* prority group configuration */ -#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ -#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ - -#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */ -#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ - -/******************* Bit definition for SCB_SCR register ********************/ -#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */ -#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */ -#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */ - -/******************** Bit definition for SCB_CCR register *******************/ -#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ -#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ -#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */ -#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */ -#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */ -#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ - -/******************* Bit definition for SCB_SHPR register ********************/ -#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ -#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ -#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ -#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ - -/****************** Bit definition for SCB_SHCSR register *******************/ -#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */ -#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */ -#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */ -#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */ -#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */ -#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */ -#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */ -#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */ -#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */ -#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */ -#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */ -#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */ -#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */ -#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */ - -/******************* Bit definition for SCB_CFSR register *******************/ -/*!< MFSR */ -#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */ -#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */ -#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */ -#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */ -#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */ -/*!< BFSR */ -#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */ -#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */ -#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */ -#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */ -#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */ -#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */ -/*!< UFSR */ -#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to execute an undefined instruction */ -#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */ -#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */ -#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */ -#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */ -#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ - -/******************* Bit definition for SCB_HFSR register *******************/ -#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */ -#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ -#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */ - -/******************* Bit definition for SCB_DFSR register *******************/ -#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */ -#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */ -#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */ -#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */ -#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */ - -/******************* Bit definition for SCB_MMFAR register ******************/ -#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */ - -/******************* Bit definition for SCB_BFAR register *******************/ -#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */ - -/******************* Bit definition for SCB_afsr register *******************/ -#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */ - -/******************************************************************************/ -/* */ -/* External Interrupt/Event Controller */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for EXTI_IMR register *******************/ -#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ -#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ -#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ -#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ -#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ -#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ -#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ -#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ -#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ -#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ -#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ -#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ -#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ -#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ -#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ -#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ -#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ -#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ -#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ -#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ - -/******************* Bit definition for EXTI_EMR register *******************/ -#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ -#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ -#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ -#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ -#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ -#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ -#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ -#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ -#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ -#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ -#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ -#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ -#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ -#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ -#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ -#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ -#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ -#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ -#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ -#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ - -/****************** Bit definition for EXTI_RTSR register *******************/ -#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ -#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ -#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ -#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ -#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ -#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ -#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ -#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ -#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ -#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ -#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ -#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ -#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ -#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ -#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ -#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ -#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ -#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ -#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ -#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ - -/****************** Bit definition for EXTI_FTSR register *******************/ -#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ -#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ -#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ -#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ -#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ -#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ -#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ -#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ -#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ -#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ -#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ -#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ -#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ -#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ -#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ -#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ -#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ -#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ -#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ -#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ - -/****************** Bit definition for EXTI_SWIER register ******************/ -#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ -#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ -#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ -#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ -#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ -#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ -#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ -#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ -#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ -#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ -#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ -#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ -#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ -#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ -#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ -#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ -#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ -#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ -#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ -#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ - -/******************* Bit definition for EXTI_PR register ********************/ -#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ -#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */ -#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */ -#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */ -#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */ -#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */ -#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */ -#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */ -#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */ -#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */ -#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */ -#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */ -#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */ -#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */ -#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */ -#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ -#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ -#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ -#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ -#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ - -/******************************************************************************/ -/* */ -/* DMA Controller */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for DMA_ISR register ********************/ -#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */ -#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */ -#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */ -#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */ -#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */ -#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */ -#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */ -#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */ -#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */ -#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */ -#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */ -#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */ -#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */ -#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */ -#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */ -#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */ -#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */ -#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */ -#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */ -#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */ -#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */ -#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */ -#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */ -#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */ -#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */ -#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */ -#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */ -#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */ - -/******************* Bit definition for DMA_IFCR register *******************/ -#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */ -#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ -#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ -#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ -#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */ -#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */ -#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */ -#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */ -#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */ -#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */ -#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */ -#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */ -#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */ -#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */ -#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */ -#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */ -#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */ -#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */ -#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */ -#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */ -#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */ -#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */ -#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */ -#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */ -#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */ -#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */ -#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */ -#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */ - -/******************* Bit definition for DMA_CCR1 register *******************/ -#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/ -#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */ -#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ - -/******************* Bit definition for DMA_CCR2 register *******************/ -#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */ -#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ - -/******************* Bit definition for DMA_CCR3 register *******************/ -#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */ -#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ - -/*!<****************** Bit definition for DMA_CCR4 register *******************/ -#define DMA_CCR4_EN ((uint16_t)0x0001) /*!< Channel enable */ -#define DMA_CCR4_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR4_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR4_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR4_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR4_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR4_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR4_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR4_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR4_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR4_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR4_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ - -/****************** Bit definition for DMA_CCR5 register *******************/ -#define DMA_CCR5_EN ((uint16_t)0x0001) /*!< Channel enable */ -#define DMA_CCR5_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR5_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR5_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR5_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR5_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR5_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR5_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR5_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR5_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR5_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR5_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */ - -/******************* Bit definition for DMA_CCR6 register *******************/ -#define DMA_CCR6_EN ((uint16_t)0x0001) /*!< Channel enable */ -#define DMA_CCR6_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR6_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR6_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR6_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR6_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR6_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR6_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR6_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR6_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR6_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR6_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ - -/******************* Bit definition for DMA_CCR7 register *******************/ -#define DMA_CCR7_EN ((uint16_t)0x0001) /*!< Channel enable */ -#define DMA_CCR7_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR7_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR7_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR7_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR7_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR7_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR7_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR7_PSIZE , ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR7_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR7_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR7_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */ - -/****************** Bit definition for DMA_CNDTR1 register ******************/ -#define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ - -/****************** Bit definition for DMA_CNDTR2 register ******************/ -#define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ - -/****************** Bit definition for DMA_CNDTR3 register ******************/ -#define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ - -/****************** Bit definition for DMA_CNDTR4 register ******************/ -#define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ - -/****************** Bit definition for DMA_CNDTR5 register ******************/ -#define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ - -/****************** Bit definition for DMA_CNDTR6 register ******************/ -#define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ - -/****************** Bit definition for DMA_CNDTR7 register ******************/ -#define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ - -/****************** Bit definition for DMA_CPAR1 register *******************/ -#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ - -/****************** Bit definition for DMA_CPAR2 register *******************/ -#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ - -/****************** Bit definition for DMA_CPAR3 register *******************/ -#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ - - -/****************** Bit definition for DMA_CPAR4 register *******************/ -#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ - -/****************** Bit definition for DMA_CPAR5 register *******************/ -#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ - -/****************** Bit definition for DMA_CPAR6 register *******************/ -#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ - - -/****************** Bit definition for DMA_CPAR7 register *******************/ -#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ - -/****************** Bit definition for DMA_CMAR1 register *******************/ -#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ - -/****************** Bit definition for DMA_CMAR2 register *******************/ -#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ - -/****************** Bit definition for DMA_CMAR3 register *******************/ -#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ - - -/****************** Bit definition for DMA_CMAR4 register *******************/ -#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ - -/****************** Bit definition for DMA_CMAR5 register *******************/ -#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ - -/****************** Bit definition for DMA_CMAR6 register *******************/ -#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ - -/****************** Bit definition for DMA_CMAR7 register *******************/ -#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ - -/******************************************************************************/ -/* */ -/* Analog to Digital Converter */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD ((uint8_t)0x01) /*!< Analog watchdog flag */ -#define ADC_SR_EOC ((uint8_t)0x02) /*!< End of conversion */ -#define ADC_SR_JEOC ((uint8_t)0x04) /*!< Injected channel end of conversion */ -#define ADC_SR_JSTRT ((uint8_t)0x08) /*!< Injected channel Start flag */ -#define ADC_SR_STRT ((uint8_t)0x10) /*!< Regular channel Start flag */ - -/******************* Bit definition for ADC_CR1 register ********************/ -#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ -#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */ -#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */ -#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */ -#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */ -#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */ -#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */ -#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */ -#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */ - -#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */ -#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */ -#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */ - -#define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) /*!< DUALMOD[3:0] bits (Dual mode selection) */ -#define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) /*!< Bit 3 */ - -#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */ -#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */ - - -/******************* Bit definition for ADC_CR2 register ********************/ -#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */ -#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */ -#define ADC_CR2_CAL ((uint32_t)0x00000004) /*!< A/D Calibration */ -#define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /*!< Reset Calibration */ -#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */ -#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */ - -#define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /*!< JEXTSEL[2:0] bits (External event select for injected group) */ -#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /*!< External Trigger Conversion mode for injected channels */ - -#define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */ -#define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /*!< Bit 0 */ -#define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /*!< Bit 1 */ -#define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /*!< Bit 2 */ - -#define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /*!< External Trigger Conversion mode for regular channels */ -#define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /*!< Start Conversion of injected channels */ -#define ADC_CR2_SWSTART ((uint32_t)0x00400000) /*!< Start Conversion of regular channels */ -#define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */ - -/****************** Bit definition for ADC_SMPR1 register *******************/ -#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */ -#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */ -#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */ -#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */ -#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */ -#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */ -#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */ -#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */ -#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */ -#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */ - -/****************** Bit definition for ADC_SMPR2 register *******************/ -#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */ -#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */ -#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */ -#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */ -#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */ -#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */ -#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */ -#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */ -#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */ -#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */ -#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */ -#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */ - -/****************** Bit definition for ADC_JOFR1 register *******************/ -#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 1 */ - -/****************** Bit definition for ADC_JOFR2 register *******************/ -#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 2 */ - -/****************** Bit definition for ADC_JOFR3 register *******************/ -#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 3 */ - -/****************** Bit definition for ADC_JOFR4 register *******************/ -#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 4 */ - -/******************* Bit definition for ADC_HTR register ********************/ -#define ADC_HTR_HT ((uint16_t)0x0FFF) /*!< Analog watchdog high threshold */ - -/******************* Bit definition for ADC_LTR register ********************/ -#define ADC_LTR_LT ((uint16_t)0x0FFF) /*!< Analog watchdog low threshold */ - -/******************* Bit definition for ADC_SQR1 register *******************/ -#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */ -#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */ -#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */ -#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */ -#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */ -#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -/******************* Bit definition for ADC_SQR2 register *******************/ -#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */ -#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */ -#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */ -#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */ -#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */ -#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */ -#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */ -#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */ -#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */ -#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */ - -/******************* Bit definition for ADC_SQR3 register *******************/ -#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */ -#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */ -#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */ -#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */ -#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */ -#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */ -#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */ -#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */ -#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */ -#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */ - -/******************* Bit definition for ADC_JSQR register *******************/ -#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */ -#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */ -#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */ -#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */ -#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */ -#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */ - -/******************* Bit definition for ADC_JDR1 register *******************/ -#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ - -/******************* Bit definition for ADC_JDR2 register *******************/ -#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ - -/******************* Bit definition for ADC_JDR3 register *******************/ -#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ - -/******************* Bit definition for ADC_JDR4 register *******************/ -#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ - -/******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */ -#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!< ADC2 data */ - -/******************************************************************************/ -/* */ -/* Digital to Analog Converter */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for DAC_CR register ********************/ -#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */ -#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */ -#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */ - -#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ -#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ -#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ - -#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ -#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */ -#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */ -#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */ -#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */ - -#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ -#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */ -#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */ -#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */ - -#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ -#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */ -#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */ - -#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ -#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */ - -/***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!< DAC channel1 software trigger */ -#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!< DAC channel2 software trigger */ - -/***************** Bit definition for DAC_DHR12R1 register ******************/ -#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!< DAC channel1 12-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12L1 register ******************/ -#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!< DAC channel1 12-bit Left aligned data */ - -/****************** Bit definition for DAC_DHR8R1 register ******************/ -#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!< DAC channel1 8-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12R2 register ******************/ -#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!< DAC channel2 12-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12L2 register ******************/ -#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!< DAC channel2 12-bit Left aligned data */ - -/****************** Bit definition for DAC_DHR8R2 register ******************/ -#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!< DAC channel2 8-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12RD register ******************/ -#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */ -#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12LD register ******************/ -#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */ -#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */ - -/****************** Bit definition for DAC_DHR8RD register ******************/ -#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!< DAC channel1 8-bit Right aligned data */ -#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!< DAC channel2 8-bit Right aligned data */ - -/******************* Bit definition for DAC_DOR1 register *******************/ -#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!< DAC channel1 data output */ - -/******************* Bit definition for DAC_DOR2 register *******************/ -#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!< DAC channel2 data output */ - -/******************** Bit definition for DAC_SR register ********************/ -#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */ -#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */ - -/******************************************************************************/ -/* */ -/* CEC */ -/* */ -/******************************************************************************/ -/******************** Bit definition for CEC_CFGR register ******************/ -#define CEC_CFGR_PE ((uint16_t)0x0001) /*!< Peripheral Enable */ -#define CEC_CFGR_IE ((uint16_t)0x0002) /*!< Interrupt Enable */ -#define CEC_CFGR_BTEM ((uint16_t)0x0004) /*!< Bit Timing Error Mode */ -#define CEC_CFGR_BPEM ((uint16_t)0x0008) /*!< Bit Period Error Mode */ - -/******************** Bit definition for CEC_OAR register ******************/ -#define CEC_OAR_OA ((uint16_t)0x000F) /*!< OA[3:0]: Own Address */ -#define CEC_OAR_OA_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define CEC_OAR_OA_1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define CEC_OAR_OA_2 ((uint16_t)0x0004) /*!< Bit 2 */ -#define CEC_OAR_OA_3 ((uint16_t)0x0008) /*!< Bit 3 */ - -/******************** Bit definition for CEC_PRES register ******************/ -#define CEC_PRES_PRES ((uint16_t)0x3FFF) /*!< Prescaler Counter Value */ - -/******************** Bit definition for CEC_ESR register ******************/ -#define CEC_ESR_BTE ((uint16_t)0x0001) /*!< Bit Timing Error */ -#define CEC_ESR_BPE ((uint16_t)0x0002) /*!< Bit Period Error */ -#define CEC_ESR_RBTFE ((uint16_t)0x0004) /*!< Rx Block Transfer Finished Error */ -#define CEC_ESR_SBE ((uint16_t)0x0008) /*!< Start Bit Error */ -#define CEC_ESR_ACKE ((uint16_t)0x0010) /*!< Block Acknowledge Error */ -#define CEC_ESR_LINE ((uint16_t)0x0020) /*!< Line Error */ -#define CEC_ESR_TBTFE ((uint16_t)0x0040) /*!< Tx Block Transfer Finished Error */ - -/******************** Bit definition for CEC_CSR register ******************/ -#define CEC_CSR_TSOM ((uint16_t)0x0001) /*!< Tx Start Of Message */ -#define CEC_CSR_TEOM ((uint16_t)0x0002) /*!< Tx End Of Message */ -#define CEC_CSR_TERR ((uint16_t)0x0004) /*!< Tx Error */ -#define CEC_CSR_TBTRF ((uint16_t)0x0008) /*!< Tx Byte Transfer Request or Block Transfer Finished */ -#define CEC_CSR_RSOM ((uint16_t)0x0010) /*!< Rx Start Of Message */ -#define CEC_CSR_REOM ((uint16_t)0x0020) /*!< Rx End Of Message */ -#define CEC_CSR_RERR ((uint16_t)0x0040) /*!< Rx Error */ -#define CEC_CSR_RBTF ((uint16_t)0x0080) /*!< Rx Block Transfer Finished */ - -/******************** Bit definition for CEC_TXD register ******************/ -#define CEC_TXD_TXD ((uint16_t)0x00FF) /*!< Tx Data register */ - -/******************** Bit definition for CEC_RXD register ******************/ -#define CEC_RXD_RXD ((uint16_t)0x00FF) /*!< Rx Data register */ - -/******************************************************************************/ -/* */ -/* TIM */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for TIM_CR1 register ********************/ -#define TIM_CR1_CEN ((uint16_t)0x0001) /*!< Counter enable */ -#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!< Update disable */ -#define TIM_CR1_URS ((uint16_t)0x0004) /*!< Update request source */ -#define TIM_CR1_OPM ((uint16_t)0x0008) /*!< One pulse mode */ -#define TIM_CR1_DIR ((uint16_t)0x0010) /*!< Direction */ - -#define TIM_CR1_CMS ((uint16_t)0x0060) /*!< CMS[1:0] bits (Center-aligned mode selection) */ -#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!< Bit 0 */ -#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!< Bit 1 */ - -#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!< Auto-reload preload enable */ - -#define TIM_CR1_CKD ((uint16_t)0x0300) /*!< CKD[1:0] bits (clock division) */ -#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -/******************* Bit definition for TIM_CR2 register ********************/ -#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!< Capture/Compare Preloaded Control */ -#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!< Capture/Compare Control Update Selection */ -#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!< Capture/Compare DMA Selection */ - -#define TIM_CR2_MMS ((uint16_t)0x0070) /*!< MMS[2:0] bits (Master Mode Selection) */ -#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!< Bit 1 */ -#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!< Bit 2 */ - -#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!< TI1 Selection */ -#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!< Output Idle state 1 (OC1 output) */ -#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!< Output Idle state 1 (OC1N output) */ -#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!< Output Idle state 2 (OC2 output) */ -#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!< Output Idle state 2 (OC2N output) */ -#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!< Output Idle state 3 (OC3 output) */ -#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!< Output Idle state 3 (OC3N output) */ -#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!< Output Idle state 4 (OC4 output) */ - -/******************* Bit definition for TIM_SMCR register *******************/ -#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!< SMS[2:0] bits (Slave mode selection) */ -#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!< Bit 2 */ - -#define TIM_SMCR_TS ((uint16_t)0x0070) /*!< TS[2:0] bits (Trigger selection) */ -#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!< Bit 1 */ -#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!< Bit 2 */ - -#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!< Master/slave mode */ - -#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!< ETF[3:0] bits (External trigger filter) */ -#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!< Bit 1 */ -#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!< Bit 2 */ -#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!< Bit 3 */ - -#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!< ETPS[1:0] bits (External trigger prescaler) */ -#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!< External clock enable */ -#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!< External trigger polarity */ - -/******************* Bit definition for TIM_DIER register *******************/ -#define TIM_DIER_UIE ((uint16_t)0x0001) /*!< Update interrupt enable */ -#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt enable */ -#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt enable */ -#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt enable */ -#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt enable */ -#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!< COM interrupt enable */ -#define TIM_DIER_TIE ((uint16_t)0x0040) /*!< Trigger interrupt enable */ -#define TIM_DIER_BIE ((uint16_t)0x0080) /*!< Break interrupt enable */ -#define TIM_DIER_UDE ((uint16_t)0x0100) /*!< Update DMA request enable */ -#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!< Capture/Compare 1 DMA request enable */ -#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!< Capture/Compare 2 DMA request enable */ -#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!< Capture/Compare 3 DMA request enable */ -#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!< Capture/Compare 4 DMA request enable */ -#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!< COM DMA request enable */ -#define TIM_DIER_TDE ((uint16_t)0x4000) /*!< Trigger DMA request enable */ - -/******************** Bit definition for TIM_SR register ********************/ -#define TIM_SR_UIF ((uint16_t)0x0001) /*!< Update interrupt Flag */ -#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt Flag */ -#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt Flag */ -#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt Flag */ -#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt Flag */ -#define TIM_SR_COMIF ((uint16_t)0x0020) /*!< COM interrupt Flag */ -#define TIM_SR_TIF ((uint16_t)0x0040) /*!< Trigger interrupt Flag */ -#define TIM_SR_BIF ((uint16_t)0x0080) /*!< Break interrupt Flag */ -#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!< Capture/Compare 1 Overcapture Flag */ -#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!< Capture/Compare 2 Overcapture Flag */ -#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!< Capture/Compare 3 Overcapture Flag */ -#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!< Capture/Compare 4 Overcapture Flag */ - -/******************* Bit definition for TIM_EGR register ********************/ -#define TIM_EGR_UG ((uint8_t)0x01) /*!< Update Generation */ -#define TIM_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation */ -#define TIM_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation */ -#define TIM_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation */ -#define TIM_EGR_CC4G ((uint8_t)0x10) /*!< Capture/Compare 4 Generation */ -#define TIM_EGR_COMG ((uint8_t)0x20) /*!< Capture/Compare Control Update Generation */ -#define TIM_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation */ -#define TIM_EGR_BG ((uint8_t)0x80) /*!< Break Generation */ - -/****************** Bit definition for TIM_CCMR1 register *******************/ -#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!< CC1S[1:0] bits (Capture/Compare 1 Selection) */ -#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!< Bit 1 */ - -#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!< Output Compare 1 Fast enable */ -#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!< Output Compare 1 Preload enable */ - -#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!< OC1M[2:0] bits (Output Compare 1 Mode) */ -#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!< Bit 1 */ -#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!< Bit 2 */ - -#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!< Output Compare 1Clear Enable */ - -#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!< CC2S[1:0] bits (Capture/Compare 2 Selection) */ -#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!< Output Compare 2 Fast enable */ -#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!< Output Compare 2 Preload enable */ - -#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!< OC2M[2:0] bits (Output Compare 2 Mode) */ -#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!< Bit 1 */ -#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!< Bit 2 */ - -#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!< Output Compare 2 Clear Enable */ - -/*----------------------------------------------------------------------------*/ - -#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!< IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ -#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */ -#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */ - -#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!< IC1F[3:0] bits (Input Capture 1 Filter) */ -#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!< Bit 1 */ -#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!< Bit 2 */ -#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!< Bit 3 */ - -#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!< IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ -#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!< IC2F[3:0] bits (Input Capture 2 Filter) */ -#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!< Bit 1 */ -#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!< Bit 2 */ -#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!< Bit 3 */ - -/****************** Bit definition for TIM_CCMR2 register *******************/ -#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!< CC3S[1:0] bits (Capture/Compare 3 Selection) */ -#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!< Bit 1 */ - -#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!< Output Compare 3 Fast enable */ -#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!< Output Compare 3 Preload enable */ - -#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!< OC3M[2:0] bits (Output Compare 3 Mode) */ -#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!< Bit 1 */ -#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!< Bit 2 */ - -#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!< Output Compare 3 Clear Enable */ - -#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!< CC4S[1:0] bits (Capture/Compare 4 Selection) */ -#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!< Output Compare 4 Fast enable */ -#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!< Output Compare 4 Preload enable */ - -#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!< OC4M[2:0] bits (Output Compare 4 Mode) */ -#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!< Bit 1 */ -#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!< Bit 2 */ - -#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!< Output Compare 4 Clear Enable */ - -/*----------------------------------------------------------------------------*/ - -#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!< IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ -#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */ -#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */ - -#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!< IC3F[3:0] bits (Input Capture 3 Filter) */ -#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!< Bit 1 */ -#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!< Bit 2 */ -#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!< Bit 3 */ - -#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!< IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ -#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!< IC4F[3:0] bits (Input Capture 4 Filter) */ -#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!< Bit 1 */ -#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!< Bit 2 */ -#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!< Bit 3 */ - -/******************* Bit definition for TIM_CCER register *******************/ -#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!< Capture/Compare 1 output enable */ -#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!< Capture/Compare 1 output Polarity */ -#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!< Capture/Compare 1 Complementary output enable */ -#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!< Capture/Compare 1 Complementary output Polarity */ -#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!< Capture/Compare 2 output enable */ -#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!< Capture/Compare 2 output Polarity */ -#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!< Capture/Compare 2 Complementary output enable */ -#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!< Capture/Compare 2 Complementary output Polarity */ -#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!< Capture/Compare 3 output enable */ -#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!< Capture/Compare 3 output Polarity */ -#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!< Capture/Compare 3 Complementary output enable */ -#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!< Capture/Compare 3 Complementary output Polarity */ -#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!< Capture/Compare 4 output enable */ -#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!< Capture/Compare 4 output Polarity */ -#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!< Capture/Compare 4 Complementary output Polarity */ - -/******************* Bit definition for TIM_CNT register ********************/ -#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!< Counter Value */ - -/******************* Bit definition for TIM_PSC register ********************/ -#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!< Prescaler Value */ - -/******************* Bit definition for TIM_ARR register ********************/ -#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!< actual auto-reload Value */ - -/******************* Bit definition for TIM_RCR register ********************/ -#define TIM_RCR_REP ((uint8_t)0xFF) /*!< Repetition Counter Value */ - -/******************* Bit definition for TIM_CCR1 register *******************/ -#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!< Capture/Compare 1 Value */ - -/******************* Bit definition for TIM_CCR2 register *******************/ -#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!< Capture/Compare 2 Value */ - -/******************* Bit definition for TIM_CCR3 register *******************/ -#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!< Capture/Compare 3 Value */ - -/******************* Bit definition for TIM_CCR4 register *******************/ -#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!< Capture/Compare 4 Value */ - -/******************* Bit definition for TIM_BDTR register *******************/ -#define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!< DTG[0:7] bits (Dead-Time Generator set-up) */ -#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!< Bit 2 */ -#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!< Bit 3 */ -#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!< Bit 4 */ -#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!< Bit 5 */ -#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!< Bit 6 */ -#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!< Bit 7 */ - -#define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!< LOCK[1:0] bits (Lock Configuration) */ -#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!< Off-State Selection for Idle mode */ -#define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!< Off-State Selection for Run mode */ -#define TIM_BDTR_BKE ((uint16_t)0x1000) /*!< Break enable */ -#define TIM_BDTR_BKP ((uint16_t)0x2000) /*!< Break Polarity */ -#define TIM_BDTR_AOE ((uint16_t)0x4000) /*!< Automatic Output enable */ -#define TIM_BDTR_MOE ((uint16_t)0x8000) /*!< Main Output enable */ - -/******************* Bit definition for TIM_DCR register ********************/ -#define TIM_DCR_DBA ((uint16_t)0x001F) /*!< DBA[4:0] bits (DMA Base Address) */ -#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!< Bit 2 */ -#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!< Bit 3 */ -#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!< Bit 4 */ - -#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!< DBL[4:0] bits (DMA Burst Length) */ -#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!< Bit 1 */ -#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!< Bit 2 */ -#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!< Bit 3 */ -#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!< Bit 4 */ - -/******************* Bit definition for TIM_DMAR register *******************/ -#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!< DMA register for burst accesses */ - -/******************************************************************************/ -/* */ -/* Real-Time Clock */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for RTC_CRH register ********************/ -#define RTC_CRH_SECIE ((uint8_t)0x01) /*!< Second Interrupt Enable */ -#define RTC_CRH_ALRIE ((uint8_t)0x02) /*!< Alarm Interrupt Enable */ -#define RTC_CRH_OWIE ((uint8_t)0x04) /*!< OverfloW Interrupt Enable */ - -/******************* Bit definition for RTC_CRL register ********************/ -#define RTC_CRL_SECF ((uint8_t)0x01) /*!< Second Flag */ -#define RTC_CRL_ALRF ((uint8_t)0x02) /*!< Alarm Flag */ -#define RTC_CRL_OWF ((uint8_t)0x04) /*!< OverfloW Flag */ -#define RTC_CRL_RSF ((uint8_t)0x08) /*!< Registers Synchronized Flag */ -#define RTC_CRL_CNF ((uint8_t)0x10) /*!< Configuration Flag */ -#define RTC_CRL_RTOFF ((uint8_t)0x20) /*!< RTC operation OFF */ - -/******************* Bit definition for RTC_PRLH register *******************/ -#define RTC_PRLH_PRL ((uint16_t)0x000F) /*!< RTC Prescaler Reload Value High */ - -/******************* Bit definition for RTC_PRLL register *******************/ -#define RTC_PRLL_PRL ((uint16_t)0xFFFF) /*!< RTC Prescaler Reload Value Low */ - -/******************* Bit definition for RTC_DIVH register *******************/ -#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /*!< RTC Clock Divider High */ - -/******************* Bit definition for RTC_DIVL register *******************/ -#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /*!< RTC Clock Divider Low */ - -/******************* Bit definition for RTC_CNTH register *******************/ -#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /*!< RTC Counter High */ - -/******************* Bit definition for RTC_CNTL register *******************/ -#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /*!< RTC Counter Low */ - -/******************* Bit definition for RTC_ALRH register *******************/ -#define RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF) /*!< RTC Alarm High */ - -/******************* Bit definition for RTC_ALRL register *******************/ -#define RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF) /*!< RTC Alarm Low */ - -/******************************************************************************/ -/* */ -/* Independent WATCHDOG */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for IWDG_KR register ********************/ -#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */ - -/******************* Bit definition for IWDG_PR register ********************/ -#define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */ -#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */ -#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */ -#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */ - -/******************* Bit definition for IWDG_RLR register *******************/ -#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */ - -/******************* Bit definition for IWDG_SR register ********************/ -#define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */ -#define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */ - -/******************************************************************************/ -/* */ -/* Window WATCHDOG */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for WWDG_CR register ********************/ -#define WWDG_CR_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ -#define WWDG_CR_T0 ((uint8_t)0x01) /*!< Bit 0 */ -#define WWDG_CR_T1 ((uint8_t)0x02) /*!< Bit 1 */ -#define WWDG_CR_T2 ((uint8_t)0x04) /*!< Bit 2 */ -#define WWDG_CR_T3 ((uint8_t)0x08) /*!< Bit 3 */ -#define WWDG_CR_T4 ((uint8_t)0x10) /*!< Bit 4 */ -#define WWDG_CR_T5 ((uint8_t)0x20) /*!< Bit 5 */ -#define WWDG_CR_T6 ((uint8_t)0x40) /*!< Bit 6 */ - -#define WWDG_CR_WDGA ((uint8_t)0x80) /*!< Activation bit */ - -/******************* Bit definition for WWDG_CFR register *******************/ -#define WWDG_CFR_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */ -#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!< Bit 2 */ -#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!< Bit 3 */ -#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!< Bit 4 */ -#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!< Bit 5 */ -#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!< Bit 6 */ - -#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!< WDGTB[1:0] bits (Timer Base) */ -#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!< Bit 0 */ -#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!< Bit 1 */ - -#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */ - -/******************* Bit definition for WWDG_SR register ********************/ -#define WWDG_SR_EWIF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */ - -/******************************************************************************/ -/* */ -/* Flexible Static Memory Controller */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for FSMC_BCR1 register *******************/ -#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ -#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ - -#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ -#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ -#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ -#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ -#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ -#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ -#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ -#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ -#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ -#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ -#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ -#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ - -/****************** Bit definition for FSMC_BCR2 register *******************/ -#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ -#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ - -#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ -#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ -#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ -#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ -#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ -#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ -#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ -#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ -#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ -#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ -#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ -#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ - -/****************** Bit definition for FSMC_BCR3 register *******************/ -#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ -#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ - -#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ -#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ -#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ -#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ -#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit. */ -#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ -#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ -#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ -#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ -#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ -#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ -#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ - -/****************** Bit definition for FSMC_BCR4 register *******************/ -#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ -#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ - -#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ -#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ -#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ -#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ -#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ -#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ -#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ -#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ -#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ -#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ -#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ -#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ - -/****************** Bit definition for FSMC_BTR1 register ******************/ -#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ -#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ - -#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ -#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for FSMC_BTR2 register *******************/ -#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ -#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ - -#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ -#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/******************* Bit definition for FSMC_BTR3 register *******************/ -#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ -#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ - -#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ -#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for FSMC_BTR4 register *******************/ -#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ -#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ - -#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ -#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for FSMC_BWTR1 register ******************/ -#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ -#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for FSMC_BWTR2 register ******************/ -#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1*/ -#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ -#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for FSMC_BWTR3 register ******************/ -#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ -#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for FSMC_BWTR4 register ******************/ -#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ -#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for FSMC_PCR2 register *******************/ -#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ -#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ -#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!< Memory type */ - -#define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ -#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ - -#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ -#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ -#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ - -#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ -#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ -#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ -#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ - -#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[1:0] bits (ECC page size) */ -#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ -#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ -#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ - -/****************** Bit definition for FSMC_PCR3 register *******************/ -#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ -#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ -#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!< Memory type */ - -#define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ -#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ - -#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ -#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ -#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ - -#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ -#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ -#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ -#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ - -#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */ -#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ -#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ -#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ - -/****************** Bit definition for FSMC_PCR4 register *******************/ -#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ -#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ -#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!< Memory type */ - -#define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ -#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ - -#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ -#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ -#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ - -#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ -#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ -#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ -#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ - -#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */ -#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ -#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ -#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ - -/******************* Bit definition for FSMC_SR2 register *******************/ -#define FSMC_SR2_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ -#define FSMC_SR2_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ -#define FSMC_SR2_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ -#define FSMC_SR2_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ -#define FSMC_SR2_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ -#define FSMC_SR2_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ -#define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ - -/******************* Bit definition for FSMC_SR3 register *******************/ -#define FSMC_SR3_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ -#define FSMC_SR3_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ -#define FSMC_SR3_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ -#define FSMC_SR3_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ -#define FSMC_SR3_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ -#define FSMC_SR3_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ -#define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ - -/******************* Bit definition for FSMC_SR4 register *******************/ -#define FSMC_SR4_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ -#define FSMC_SR4_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ -#define FSMC_SR4_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ -#define FSMC_SR4_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ -#define FSMC_SR4_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ -#define FSMC_SR4_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ -#define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ - -/****************** Bit definition for FSMC_PMEM2 register ******************/ -#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!< MEMSET2[7:0] bits (Common memory 2 setup time) */ -#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!< MEMWAIT2[7:0] bits (Common memory 2 wait time) */ -#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!< MEMHOLD2[7:0] bits (Common memory 2 hold time) */ -#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!< MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */ -#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for FSMC_PMEM3 register ******************/ -#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!< MEMSET3[7:0] bits (Common memory 3 setup time) */ -#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!< MEMWAIT3[7:0] bits (Common memory 3 wait time) */ -#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!< MEMHOLD3[7:0] bits (Common memory 3 hold time) */ -#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!< MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */ -#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for FSMC_PMEM4 register ******************/ -#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!< MEMSET4[7:0] bits (Common memory 4 setup time) */ -#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!< MEMWAIT4[7:0] bits (Common memory 4 wait time) */ -#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!< MEMHOLD4[7:0] bits (Common memory 4 hold time) */ -#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!< MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */ -#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for FSMC_PATT2 register ******************/ -#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!< ATTSET2[7:0] bits (Attribute memory 2 setup time) */ -#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!< ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */ -#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!< ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */ -#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!< ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */ -#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for FSMC_PATT3 register ******************/ -#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!< ATTSET3[7:0] bits (Attribute memory 3 setup time) */ -#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!< ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */ -#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!< ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */ -#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!< ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */ -#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for FSMC_PATT4 register ******************/ -#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!< ATTSET4[7:0] bits (Attribute memory 4 setup time) */ -#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!< ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */ -#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!< ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */ -#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!< ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */ -#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for FSMC_PIO4 register *******************/ -#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!< IOSET4[7:0] bits (I/O 4 setup time) */ -#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!< IOWAIT4[7:0] bits (I/O 4 wait time) */ -#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!< IOHOLD4[7:0] bits (I/O 4 hold time) */ -#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!< IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */ -#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for FSMC_ECCR2 register ******************/ -#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!< ECC result */ - -/****************** Bit definition for FSMC_ECCR3 register ******************/ -#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!< ECC result */ - -/******************************************************************************/ -/* */ -/* SD host Interface */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for SDIO_POWER register ******************/ -#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!< PWRCTRL[1:0] bits (Power supply control bits) */ -#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!< Bit 0 */ -#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!< Bit 1 */ - -/****************** Bit definition for SDIO_CLKCR register ******************/ -#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!< Clock divide factor */ -#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!< Clock enable bit */ -#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!< Power saving configuration bit */ -#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!< Clock divider bypass enable bit */ - -#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */ -#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!< Bit 0 */ -#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!< Bit 1 */ - -#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!< SDIO_CK dephasing selection bit */ -#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!< HW Flow Control enable */ - -/******************* Bit definition for SDIO_ARG register *******************/ -#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!< Command argument */ - -/******************* Bit definition for SDIO_CMD register *******************/ -#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!< Command Index */ - -#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!< WAITRESP[1:0] bits (Wait for response bits) */ -#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */ -#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */ - -#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!< CPSM Waits for Interrupt Request */ -#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */ -#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!< Command path state machine (CPSM) Enable bit */ -#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!< SD I/O suspend command */ -#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!< Enable CMD completion */ -#define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!< Not Interrupt Enable */ -#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!< CE-ATA command */ - -/***************** Bit definition for SDIO_RESPCMD register *****************/ -#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!< Response command index */ - -/****************** Bit definition for SDIO_RESP0 register ******************/ -#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ - -/****************** Bit definition for SDIO_RESP1 register ******************/ -#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ - -/****************** Bit definition for SDIO_RESP2 register ******************/ -#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ - -/****************** Bit definition for SDIO_RESP3 register ******************/ -#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ - -/****************** Bit definition for SDIO_RESP4 register ******************/ -#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ - -/****************** Bit definition for SDIO_DTIMER register *****************/ -#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!< Data timeout period. */ - -/****************** Bit definition for SDIO_DLEN register *******************/ -#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!< Data length value */ - -/****************** Bit definition for SDIO_DCTRL register ******************/ -#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!< Data transfer enabled bit */ -#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!< Data transfer direction selection */ -#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!< Data transfer mode selection */ -#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!< DMA enabled bit */ - -#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!< DBLOCKSIZE[3:0] bits (Data block size) */ -#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!< Bit 1 */ -#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!< Bit 2 */ -#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!< Bit 3 */ - -#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!< Read wait start */ -#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!< Read wait stop */ -#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!< Read wait mode */ -#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!< SD I/O enable functions */ - -/****************** Bit definition for SDIO_DCOUNT register *****************/ -#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!< Data count value */ - -/****************** Bit definition for SDIO_STA register ********************/ -#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!< Command response received (CRC check failed) */ -#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!< Data block sent/received (CRC check failed) */ -#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!< Command response timeout */ -#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!< Data timeout */ -#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!< Transmit FIFO underrun error */ -#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!< Received FIFO overrun error */ -#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!< Command response received (CRC check passed) */ -#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!< Command sent (no response required) */ -#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!< Data end (data counter, SDIDCOUNT, is zero) */ -#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!< Start bit not detected on all data signals in wide bus mode */ -#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!< Data block sent/received (CRC check passed) */ -#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!< Command transfer in progress */ -#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!< Data transmit in progress */ -#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!< Data receive in progress */ -#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ -#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */ -#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!< Transmit FIFO full */ -#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!< Receive FIFO full */ -#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!< Transmit FIFO empty */ -#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!< Receive FIFO empty */ -#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!< Data available in transmit FIFO */ -#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!< Data available in receive FIFO */ -#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!< SDIO interrupt received */ -#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received for CMD61 */ - -/******************* Bit definition for SDIO_ICR register *******************/ -#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!< CCRCFAIL flag clear bit */ -#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!< DCRCFAIL flag clear bit */ -#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!< CTIMEOUT flag clear bit */ -#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!< DTIMEOUT flag clear bit */ -#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!< TXUNDERR flag clear bit */ -#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!< RXOVERR flag clear bit */ -#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!< CMDREND flag clear bit */ -#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!< CMDSENT flag clear bit */ -#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!< DATAEND flag clear bit */ -#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!< STBITERR flag clear bit */ -#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!< DBCKEND flag clear bit */ -#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!< SDIOIT flag clear bit */ -#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!< CEATAEND flag clear bit */ - -/****************** Bit definition for SDIO_MASK register *******************/ -#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!< Command CRC Fail Interrupt Enable */ -#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!< Data CRC Fail Interrupt Enable */ -#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!< Command TimeOut Interrupt Enable */ -#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!< Data TimeOut Interrupt Enable */ -#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!< Tx FIFO UnderRun Error Interrupt Enable */ -#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!< Rx FIFO OverRun Error Interrupt Enable */ -#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!< Command Response Received Interrupt Enable */ -#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!< Command Sent Interrupt Enable */ -#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!< Data End Interrupt Enable */ -#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!< Start Bit Error Interrupt Enable */ -#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!< Data Block End Interrupt Enable */ -#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!< Command Acting Interrupt Enable */ -#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!< Data Transmit Acting Interrupt Enable */ -#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!< Data receive acting interrupt enabled */ -#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!< Tx FIFO Half Empty interrupt Enable */ -#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!< Rx FIFO Half Full interrupt Enable */ -#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!< Tx FIFO Full interrupt Enable */ -#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!< Rx FIFO Full interrupt Enable */ -#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!< Tx FIFO Empty interrupt Enable */ -#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!< Rx FIFO Empty interrupt Enable */ -#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!< Data available in Tx FIFO interrupt Enable */ -#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!< Data available in Rx FIFO interrupt Enable */ -#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!< SDIO Mode Interrupt Received interrupt Enable */ -#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received Interrupt Enable */ - -/***************** Bit definition for SDIO_FIFOCNT register *****************/ -#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!< Remaining number of words to be written to or read from the FIFO */ - -/****************** Bit definition for SDIO_FIFO register *******************/ -#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!< Receive and transmit FIFO data */ - -/******************************************************************************/ -/* */ -/* USB Device FS */ -/* */ -/******************************************************************************/ - -/*!< Endpoint-specific registers */ -/******************* Bit definition for USB_EP0R register *******************/ -#define USB_EP0R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ - -#define USB_EP0R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define USB_EP0R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ -#define USB_EP0R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ -#define USB_EP0R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ - -#define USB_EP0R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ - -#define USB_EP0R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ - -#define USB_EP0R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USB_EP0R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ -#define USB_EP0R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ - -/******************* Bit definition for USB_EP1R register *******************/ -#define USB_EP1R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ - -#define USB_EP1R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define USB_EP1R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ -#define USB_EP1R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ -#define USB_EP1R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ - -#define USB_EP1R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ - -#define USB_EP1R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ - -#define USB_EP1R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USB_EP1R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ -#define USB_EP1R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ - -/******************* Bit definition for USB_EP2R register *******************/ -#define USB_EP2R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ - -#define USB_EP2R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define USB_EP2R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ -#define USB_EP2R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ -#define USB_EP2R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ - -#define USB_EP2R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ - -#define USB_EP2R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ - -#define USB_EP2R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USB_EP2R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ -#define USB_EP2R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ - -/******************* Bit definition for USB_EP3R register *******************/ -#define USB_EP3R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ - -#define USB_EP3R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define USB_EP3R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ -#define USB_EP3R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ -#define USB_EP3R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ - -#define USB_EP3R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ - -#define USB_EP3R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ - -#define USB_EP3R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USB_EP3R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ -#define USB_EP3R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ - -/******************* Bit definition for USB_EP4R register *******************/ -#define USB_EP4R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ - -#define USB_EP4R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define USB_EP4R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ -#define USB_EP4R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ -#define USB_EP4R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ - -#define USB_EP4R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ - -#define USB_EP4R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ - -#define USB_EP4R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USB_EP4R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ -#define USB_EP4R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ - -/******************* Bit definition for USB_EP5R register *******************/ -#define USB_EP5R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ - -#define USB_EP5R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define USB_EP5R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ -#define USB_EP5R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ -#define USB_EP5R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ - -#define USB_EP5R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ - -#define USB_EP5R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ - -#define USB_EP5R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USB_EP5R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ -#define USB_EP5R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ - -/******************* Bit definition for USB_EP6R register *******************/ -#define USB_EP6R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ - -#define USB_EP6R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define USB_EP6R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ -#define USB_EP6R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ -#define USB_EP6R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ - -#define USB_EP6R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ - -#define USB_EP6R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ - -#define USB_EP6R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USB_EP6R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ -#define USB_EP6R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ - -/******************* Bit definition for USB_EP7R register *******************/ -#define USB_EP7R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ - -#define USB_EP7R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define USB_EP7R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ -#define USB_EP7R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ -#define USB_EP7R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ - -#define USB_EP7R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ - -#define USB_EP7R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ - -#define USB_EP7R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USB_EP7R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ -#define USB_EP7R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ - -/*!< Common registers */ -/******************* Bit definition for USB_CNTR register *******************/ -#define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB Reset */ -#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power down */ -#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!< Low-power mode */ -#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force suspend */ -#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< Resume request */ -#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Interrupt Mask */ -#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Interrupt Mask */ -#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Interrupt Mask */ -#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< Suspend mode Interrupt Mask */ -#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< Wakeup Interrupt Mask */ -#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< Error Interrupt Mask */ -#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun Interrupt Mask */ -#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct Transfer Interrupt Mask */ - -/******************* Bit definition for USB_ISTR register *******************/ -#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< Endpoint Identifier */ -#define USB_ISTR_DIR ((uint16_t)0x0010) /*!< Direction of transaction */ -#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame */ -#define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame */ -#define USB_ISTR_RESET ((uint16_t)0x0400) /*!< USB RESET request */ -#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< Suspend mode request */ -#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< Wake up */ -#define USB_ISTR_ERR ((uint16_t)0x2000) /*!< Error */ -#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun */ -#define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct Transfer */ - -/******************* Bit definition for USB_FNR register ********************/ -#define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */ -#define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */ -#define USB_FNR_LCK ((uint16_t)0x2000) /*!< Locked */ -#define USB_FNR_RXDM ((uint16_t)0x4000) /*!< Receive Data - Line Status */ -#define USB_FNR_RXDP ((uint16_t)0x8000) /*!< Receive Data + Line Status */ - -/****************** Bit definition for USB_DADDR register *******************/ -#define USB_DADDR_ADD ((uint8_t)0x7F) /*!< ADD[6:0] bits (Device Address) */ -#define USB_DADDR_ADD0 ((uint8_t)0x01) /*!< Bit 0 */ -#define USB_DADDR_ADD1 ((uint8_t)0x02) /*!< Bit 1 */ -#define USB_DADDR_ADD2 ((uint8_t)0x04) /*!< Bit 2 */ -#define USB_DADDR_ADD3 ((uint8_t)0x08) /*!< Bit 3 */ -#define USB_DADDR_ADD4 ((uint8_t)0x10) /*!< Bit 4 */ -#define USB_DADDR_ADD5 ((uint8_t)0x20) /*!< Bit 5 */ -#define USB_DADDR_ADD6 ((uint8_t)0x40) /*!< Bit 6 */ - -#define USB_DADDR_EF ((uint8_t)0x80) /*!< Enable Function */ - -/****************** Bit definition for USB_BTABLE register ******************/ -#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /*!< Buffer Table */ - -/*!< Buffer descriptor table */ -/***************** Bit definition for USB_ADDR0_TX register *****************/ -#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 0 */ - -/***************** Bit definition for USB_ADDR1_TX register *****************/ -#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 1 */ - -/***************** Bit definition for USB_ADDR2_TX register *****************/ -#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 2 */ - -/***************** Bit definition for USB_ADDR3_TX register *****************/ -#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 3 */ - -/***************** Bit definition for USB_ADDR4_TX register *****************/ -#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 4 */ - -/***************** Bit definition for USB_ADDR5_TX register *****************/ -#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 5 */ - -/***************** Bit definition for USB_ADDR6_TX register *****************/ -#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 6 */ - -/***************** Bit definition for USB_ADDR7_TX register *****************/ -#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 7 */ - -/*----------------------------------------------------------------------------*/ - -/***************** Bit definition for USB_COUNT0_TX register ****************/ -#define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 0 */ - -/***************** Bit definition for USB_COUNT1_TX register ****************/ -#define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 1 */ - -/***************** Bit definition for USB_COUNT2_TX register ****************/ -#define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 2 */ - -/***************** Bit definition for USB_COUNT3_TX register ****************/ -#define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 3 */ - -/***************** Bit definition for USB_COUNT4_TX register ****************/ -#define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 4 */ - -/***************** Bit definition for USB_COUNT5_TX register ****************/ -#define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 5 */ - -/***************** Bit definition for USB_COUNT6_TX register ****************/ -#define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 6 */ - -/***************** Bit definition for USB_COUNT7_TX register ****************/ -#define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 7 */ - -/*----------------------------------------------------------------------------*/ - -/**************** Bit definition for USB_COUNT0_TX_0 register ***************/ -#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */ - -/**************** Bit definition for USB_COUNT0_TX_1 register ***************/ -#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */ - -/**************** Bit definition for USB_COUNT1_TX_0 register ***************/ -#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */ - -/**************** Bit definition for USB_COUNT1_TX_1 register ***************/ -#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */ - -/**************** Bit definition for USB_COUNT2_TX_0 register ***************/ -#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */ - -/**************** Bit definition for USB_COUNT2_TX_1 register ***************/ -#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */ - -/**************** Bit definition for USB_COUNT3_TX_0 register ***************/ -#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */ - -/**************** Bit definition for USB_COUNT3_TX_1 register ***************/ -#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */ - -/**************** Bit definition for USB_COUNT4_TX_0 register ***************/ -#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */ - -/**************** Bit definition for USB_COUNT4_TX_1 register ***************/ -#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */ - -/**************** Bit definition for USB_COUNT5_TX_0 register ***************/ -#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */ - -/**************** Bit definition for USB_COUNT5_TX_1 register ***************/ -#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */ - -/**************** Bit definition for USB_COUNT6_TX_0 register ***************/ -#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */ - -/**************** Bit definition for USB_COUNT6_TX_1 register ***************/ -#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */ - -/**************** Bit definition for USB_COUNT7_TX_0 register ***************/ -#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */ - -/**************** Bit definition for USB_COUNT7_TX_1 register ***************/ -#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */ - -/*----------------------------------------------------------------------------*/ - -/***************** Bit definition for USB_ADDR0_RX register *****************/ -#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 0 */ - -/***************** Bit definition for USB_ADDR1_RX register *****************/ -#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 1 */ - -/***************** Bit definition for USB_ADDR2_RX register *****************/ -#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 2 */ - -/***************** Bit definition for USB_ADDR3_RX register *****************/ -#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 3 */ - -/***************** Bit definition for USB_ADDR4_RX register *****************/ -#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 4 */ - -/***************** Bit definition for USB_ADDR5_RX register *****************/ -#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 5 */ - -/***************** Bit definition for USB_ADDR6_RX register *****************/ -#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 6 */ - -/***************** Bit definition for USB_ADDR7_RX register *****************/ -#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 7 */ - -/*----------------------------------------------------------------------------*/ - -/***************** Bit definition for USB_COUNT0_RX register ****************/ -#define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ - -#define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ -#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ -#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ -#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ - -#define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ - -/***************** Bit definition for USB_COUNT1_RX register ****************/ -#define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ - -#define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ -#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ -#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ -#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ - -#define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ - -/***************** Bit definition for USB_COUNT2_RX register ****************/ -#define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ - -#define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ -#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ -#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ -#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ - -#define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ - -/***************** Bit definition for USB_COUNT3_RX register ****************/ -#define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ - -#define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ -#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ -#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ -#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ - -#define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ - -/***************** Bit definition for USB_COUNT4_RX register ****************/ -#define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ - -#define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ -#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ -#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ -#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ - -#define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ - -/***************** Bit definition for USB_COUNT5_RX register ****************/ -#define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ - -#define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ -#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ -#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ -#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ - -#define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ - -/***************** Bit definition for USB_COUNT6_RX register ****************/ -#define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ - -#define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ -#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ -#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ -#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ - -#define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ - -/***************** Bit definition for USB_COUNT7_RX register ****************/ -#define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ - -#define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ -#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ -#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ -#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ - -#define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ - -/*----------------------------------------------------------------------------*/ - -/**************** Bit definition for USB_COUNT0_RX_0 register ***************/ -#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ - -#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT0_RX_1 register ***************/ -#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ - -#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ -#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ -#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ - -#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ - -/**************** Bit definition for USB_COUNT1_RX_0 register ***************/ -#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ - -#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT1_RX_1 register ***************/ -#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ - -#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ -#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ -#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ - -#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ - -/**************** Bit definition for USB_COUNT2_RX_0 register ***************/ -#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ - -#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT2_RX_1 register ***************/ -#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ - -#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ -#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ -#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ - -#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ - -/**************** Bit definition for USB_COUNT3_RX_0 register ***************/ -#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ - -#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT3_RX_1 register ***************/ -#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ - -#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ -#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ -#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ - -#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ - -/**************** Bit definition for USB_COUNT4_RX_0 register ***************/ -#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ - -#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT4_RX_1 register ***************/ -#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ - -#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ -#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ -#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ - -#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ - -/**************** Bit definition for USB_COUNT5_RX_0 register ***************/ -#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ - -#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT5_RX_1 register ***************/ -#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ - -#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ -#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ -#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ - -#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ - -/*************** Bit definition for USB_COUNT6_RX_0 register ***************/ -#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ - -#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT6_RX_1 register ***************/ -#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ - -#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ -#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ -#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ - -#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ - -/*************** Bit definition for USB_COUNT7_RX_0 register ****************/ -#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ - -#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ - -/*************** Bit definition for USB_COUNT7_RX_1 register ****************/ -#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ - -#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ -#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ -#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ - -#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ - -/******************************************************************************/ -/* */ -/* Controller Area Network */ -/* */ -/******************************************************************************/ - -/*!< CAN control and status registers */ -/******************* Bit definition for CAN_MCR register ********************/ -#define CAN_MCR_INRQ ((uint16_t)0x0001) /*!< Initialization Request */ -#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!< Sleep Mode Request */ -#define CAN_MCR_TXFP ((uint16_t)0x0004) /*!< Transmit FIFO Priority */ -#define CAN_MCR_RFLM ((uint16_t)0x0008) /*!< Receive FIFO Locked Mode */ -#define CAN_MCR_NART ((uint16_t)0x0010) /*!< No Automatic Retransmission */ -#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!< Automatic Wakeup Mode */ -#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!< Automatic Bus-Off Management */ -#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!< Time Triggered Communication Mode */ -#define CAN_MCR_RESET ((uint16_t)0x8000) /*!< CAN software master reset */ - -/******************* Bit definition for CAN_MSR register ********************/ -#define CAN_MSR_INAK ((uint16_t)0x0001) /*!< Initialization Acknowledge */ -#define CAN_MSR_SLAK ((uint16_t)0x0002) /*!< Sleep Acknowledge */ -#define CAN_MSR_ERRI ((uint16_t)0x0004) /*!< Error Interrupt */ -#define CAN_MSR_WKUI ((uint16_t)0x0008) /*!< Wakeup Interrupt */ -#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!< Sleep Acknowledge Interrupt */ -#define CAN_MSR_TXM ((uint16_t)0x0100) /*!< Transmit Mode */ -#define CAN_MSR_RXM ((uint16_t)0x0200) /*!< Receive Mode */ -#define CAN_MSR_SAMP ((uint16_t)0x0400) /*!< Last Sample Point */ -#define CAN_MSR_RX ((uint16_t)0x0800) /*!< CAN Rx Signal */ - -/******************* Bit definition for CAN_TSR register ********************/ -#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!< Request Completed Mailbox0 */ -#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!< Transmission OK of Mailbox0 */ -#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!< Arbitration Lost for Mailbox0 */ -#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!< Transmission Error of Mailbox0 */ -#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!< Abort Request for Mailbox0 */ -#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!< Request Completed Mailbox1 */ -#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!< Transmission OK of Mailbox1 */ -#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!< Arbitration Lost for Mailbox1 */ -#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!< Transmission Error of Mailbox1 */ -#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!< Abort Request for Mailbox 1 */ -#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!< Request Completed Mailbox2 */ -#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!< Transmission OK of Mailbox 2 */ -#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!< Arbitration Lost for mailbox 2 */ -#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!< Transmission Error of Mailbox 2 */ -#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!< Abort Request for Mailbox 2 */ -#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!< Mailbox Code */ - -#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!< TME[2:0] bits */ -#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!< Transmit Mailbox 0 Empty */ -#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!< Transmit Mailbox 1 Empty */ -#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!< Transmit Mailbox 2 Empty */ - -#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!< LOW[2:0] bits */ -#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!< Lowest Priority Flag for Mailbox 0 */ -#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!< Lowest Priority Flag for Mailbox 1 */ -#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!< Lowest Priority Flag for Mailbox 2 */ - -/******************* Bit definition for CAN_RF0R register *******************/ -#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!< FIFO 0 Message Pending */ -#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!< FIFO 0 Full */ -#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!< FIFO 0 Overrun */ -#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!< Release FIFO 0 Output Mailbox */ - -/******************* Bit definition for CAN_RF1R register *******************/ -#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!< FIFO 1 Message Pending */ -#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!< FIFO 1 Full */ -#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!< FIFO 1 Overrun */ -#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!< Release FIFO 1 Output Mailbox */ - -/******************** Bit definition for CAN_IER register *******************/ -#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!< Transmit Mailbox Empty Interrupt Enable */ -#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!< FIFO Message Pending Interrupt Enable */ -#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!< FIFO Full Interrupt Enable */ -#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!< FIFO Overrun Interrupt Enable */ -#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!< FIFO Message Pending Interrupt Enable */ -#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!< FIFO Full Interrupt Enable */ -#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!< FIFO Overrun Interrupt Enable */ -#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!< Error Warning Interrupt Enable */ -#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!< Error Passive Interrupt Enable */ -#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!< Bus-Off Interrupt Enable */ -#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!< Last Error Code Interrupt Enable */ -#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!< Error Interrupt Enable */ -#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!< Wakeup Interrupt Enable */ -#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!< Sleep Interrupt Enable */ - -/******************** Bit definition for CAN_ESR register *******************/ -#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!< Error Warning Flag */ -#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!< Error Passive Flag */ -#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!< Bus-Off Flag */ - -#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!< LEC[2:0] bits (Last Error Code) */ -#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!< Bit 2 */ - -#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!< Least significant byte of the 9-bit Transmit Error Counter */ -#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!< Receive Error Counter */ - -/******************* Bit definition for CAN_BTR register ********************/ -#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!< Baud Rate Prescaler */ -#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!< Time Segment 1 */ -#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!< Time Segment 2 */ -#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!< Resynchronization Jump Width */ -#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!< Loop Back Mode (Debug) */ -#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!< Silent Mode */ - -/*!< Mailbox registers */ -/****************** Bit definition for CAN_TI0R register ********************/ -#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ -#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ -#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ -#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ -#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ - -/****************** Bit definition for CAN_TDT0R register *******************/ -#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ -#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ -#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ - -/****************** Bit definition for CAN_TDL0R register *******************/ -#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ -#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ -#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ -#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ - -/****************** Bit definition for CAN_TDH0R register *******************/ -#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ -#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ -#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ -#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ - -/******************* Bit definition for CAN_TI1R register *******************/ -#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ -#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ -#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ -#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ -#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_TDT1R register ******************/ -#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ -#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ -#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ - -/******************* Bit definition for CAN_TDL1R register ******************/ -#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ -#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ -#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ -#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ - -/******************* Bit definition for CAN_TDH1R register ******************/ -#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ -#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ -#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ -#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ - -/******************* Bit definition for CAN_TI2R register *******************/ -#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ -#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ -#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ -#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */ -#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_TDT2R register ******************/ -#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ -#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ -#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ - -/******************* Bit definition for CAN_TDL2R register ******************/ -#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ -#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ -#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ -#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ - -/******************* Bit definition for CAN_TDH2R register ******************/ -#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ -#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ -#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ -#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ - -/******************* Bit definition for CAN_RI0R register *******************/ -#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ -#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ -#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ -#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_RDT0R register ******************/ -#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ -#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */ -#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ - -/******************* Bit definition for CAN_RDL0R register ******************/ -#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ -#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ -#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ -#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ - -/******************* Bit definition for CAN_RDH0R register ******************/ -#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ -#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ -#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ -#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ - -/******************* Bit definition for CAN_RI1R register *******************/ -#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ -#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ -#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */ -#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_RDT1R register ******************/ -#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ -#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */ -#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ - -/******************* Bit definition for CAN_RDL1R register ******************/ -#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ -#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ -#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ -#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ - -/******************* Bit definition for CAN_RDH1R register ******************/ -#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ -#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ -#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ -#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ - -/*!< CAN filter registers */ -/******************* Bit definition for CAN_FMR register ********************/ -#define CAN_FMR_FINIT ((uint8_t)0x01) /*!< Filter Init Mode */ - -/******************* Bit definition for CAN_FM1R register *******************/ -#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!< Filter Mode */ -#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!< Filter Init Mode bit 0 */ -#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!< Filter Init Mode bit 1 */ -#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!< Filter Init Mode bit 2 */ -#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!< Filter Init Mode bit 3 */ -#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!< Filter Init Mode bit 4 */ -#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!< Filter Init Mode bit 5 */ -#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!< Filter Init Mode bit 6 */ -#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!< Filter Init Mode bit 7 */ -#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!< Filter Init Mode bit 8 */ -#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!< Filter Init Mode bit 9 */ -#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!< Filter Init Mode bit 10 */ -#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!< Filter Init Mode bit 11 */ -#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!< Filter Init Mode bit 12 */ -#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!< Filter Init Mode bit 13 */ - -/******************* Bit definition for CAN_FS1R register *******************/ -#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!< Filter Scale Configuration */ -#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!< Filter Scale Configuration bit 0 */ -#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!< Filter Scale Configuration bit 1 */ -#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!< Filter Scale Configuration bit 2 */ -#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!< Filter Scale Configuration bit 3 */ -#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!< Filter Scale Configuration bit 4 */ -#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!< Filter Scale Configuration bit 5 */ -#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!< Filter Scale Configuration bit 6 */ -#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!< Filter Scale Configuration bit 7 */ -#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!< Filter Scale Configuration bit 8 */ -#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!< Filter Scale Configuration bit 9 */ -#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!< Filter Scale Configuration bit 10 */ -#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!< Filter Scale Configuration bit 11 */ -#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!< Filter Scale Configuration bit 12 */ -#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!< Filter Scale Configuration bit 13 */ - -/****************** Bit definition for CAN_FFA1R register *******************/ -#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!< Filter FIFO Assignment */ -#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!< Filter FIFO Assignment for Filter 0 */ -#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!< Filter FIFO Assignment for Filter 1 */ -#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!< Filter FIFO Assignment for Filter 2 */ -#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!< Filter FIFO Assignment for Filter 3 */ -#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!< Filter FIFO Assignment for Filter 4 */ -#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!< Filter FIFO Assignment for Filter 5 */ -#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!< Filter FIFO Assignment for Filter 6 */ -#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!< Filter FIFO Assignment for Filter 7 */ -#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!< Filter FIFO Assignment for Filter 8 */ -#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!< Filter FIFO Assignment for Filter 9 */ -#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!< Filter FIFO Assignment for Filter 10 */ -#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!< Filter FIFO Assignment for Filter 11 */ -#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!< Filter FIFO Assignment for Filter 12 */ -#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!< Filter FIFO Assignment for Filter 13 */ - -/******************* Bit definition for CAN_FA1R register *******************/ -#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!< Filter Active */ -#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!< Filter 0 Active */ -#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!< Filter 1 Active */ -#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!< Filter 2 Active */ -#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!< Filter 3 Active */ -#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!< Filter 4 Active */ -#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!< Filter 5 Active */ -#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!< Filter 6 Active */ -#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!< Filter 7 Active */ -#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!< Filter 8 Active */ -#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!< Filter 9 Active */ -#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!< Filter 10 Active */ -#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!< Filter 11 Active */ -#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!< Filter 12 Active */ -#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!< Filter 13 Active */ - -/******************* Bit definition for CAN_F0R1 register *******************/ -#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F1R1 register *******************/ -#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F2R1 register *******************/ -#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F3R1 register *******************/ -#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F4R1 register *******************/ -#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F5R1 register *******************/ -#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F6R1 register *******************/ -#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F7R1 register *******************/ -#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F8R1 register *******************/ -#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F9R1 register *******************/ -#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F10R1 register ******************/ -#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F11R1 register ******************/ -#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F12R1 register ******************/ -#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F13R1 register ******************/ -#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F0R2 register *******************/ -#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F1R2 register *******************/ -#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F2R2 register *******************/ -#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F3R2 register *******************/ -#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F4R2 register *******************/ -#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F5R2 register *******************/ -#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F6R2 register *******************/ -#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F7R2 register *******************/ -#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F8R2 register *******************/ -#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F9R2 register *******************/ -#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F10R2 register ******************/ -#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F11R2 register ******************/ -#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F12R2 register ******************/ -#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F13R2 register ******************/ -#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************************************************************************/ -/* */ -/* Serial Peripheral Interface */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for SPI_CR1 register ********************/ -#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */ -#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */ -#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */ - -#define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */ -#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */ -#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */ -#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */ - -#define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */ -#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */ -#define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */ -#define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */ -#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */ -#define SPI_CR1_DFF ((uint16_t)0x0800) /*!< Data Frame Format */ -#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */ -#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */ -#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */ -#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */ - -/******************* Bit definition for SPI_CR2 register ********************/ -#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!< Rx Buffer DMA Enable */ -#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!< Tx Buffer DMA Enable */ -#define SPI_CR2_SSOE ((uint8_t)0x04) /*!< SS Output Enable */ -#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!< Error Interrupt Enable */ -#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!< RX buffer Not Empty Interrupt Enable */ -#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!< Tx buffer Empty Interrupt Enable */ - -/******************** Bit definition for SPI_SR register ********************/ -#define SPI_SR_RXNE ((uint8_t)0x01) /*!< Receive buffer Not Empty */ -#define SPI_SR_TXE ((uint8_t)0x02) /*!< Transmit buffer Empty */ -#define SPI_SR_CHSIDE ((uint8_t)0x04) /*!< Channel side */ -#define SPI_SR_UDR ((uint8_t)0x08) /*!< Underrun flag */ -#define SPI_SR_CRCERR ((uint8_t)0x10) /*!< CRC Error flag */ -#define SPI_SR_MODF ((uint8_t)0x20) /*!< Mode fault */ -#define SPI_SR_OVR ((uint8_t)0x40) /*!< Overrun flag */ -#define SPI_SR_BSY ((uint8_t)0x80) /*!< Busy flag */ - -/******************** Bit definition for SPI_DR register ********************/ -#define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */ - -/******************* Bit definition for SPI_CRCPR register ******************/ -#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */ - -/****************** Bit definition for SPI_RXCRCR register ******************/ -#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */ - -/****************** Bit definition for SPI_TXCRCR register ******************/ -#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */ - -/****************** Bit definition for SPI_I2SCFGR register *****************/ -#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!< Channel length (number of bits per audio channel) */ - -#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!< DATLEN[1:0] bits (Data length to be transferred) */ -#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!< Bit 0 */ -#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!< Bit 1 */ - -#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!< steady state clock polarity */ - -#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!< I2SSTD[1:0] bits (I2S standard selection) */ -#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!< PCM frame synchronization */ - -#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!< I2SCFG[1:0] bits (I2S configuration mode) */ -#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!< I2S Enable */ -#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!< I2S mode selection */ - -/****************** Bit definition for SPI_I2SPR register *******************/ -#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!< I2S Linear prescaler */ -#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!< Odd factor for the prescaler */ -#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!< Master Clock Output Enable */ - -/******************************************************************************/ -/* */ -/* Inter-integrated Circuit Interface */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for I2C_CR1 register ********************/ -#define I2C_CR1_PE ((uint16_t)0x0001) /*!< Peripheral Enable */ -#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!< SMBus Mode */ -#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!< SMBus Type */ -#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!< ARP Enable */ -#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!< PEC Enable */ -#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!< General Call Enable */ -#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!< Clock Stretching Disable (Slave mode) */ -#define I2C_CR1_START ((uint16_t)0x0100) /*!< Start Generation */ -#define I2C_CR1_STOP ((uint16_t)0x0200) /*!< Stop Generation */ -#define I2C_CR1_ACK ((uint16_t)0x0400) /*!< Acknowledge Enable */ -#define I2C_CR1_POS ((uint16_t)0x0800) /*!< Acknowledge/PEC Position (for data reception) */ -#define I2C_CR1_PEC ((uint16_t)0x1000) /*!< Packet Error Checking */ -#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!< SMBus Alert */ -#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!< Software Reset */ - -/******************* Bit definition for I2C_CR2 register ********************/ -#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */ -#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!< Bit 2 */ -#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!< Bit 3 */ -#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!< Bit 4 */ -#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!< Bit 5 */ - -#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!< Error Interrupt Enable */ -#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!< Event Interrupt Enable */ -#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!< Buffer Interrupt Enable */ -#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!< DMA Requests Enable */ -#define I2C_CR2_LAST ((uint16_t)0x1000) /*!< DMA Last Transfer */ - -/******************* Bit definition for I2C_OAR1 register *******************/ -#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!< Interface Address */ -#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!< Interface Address */ - -#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!< Bit 2 */ -#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!< Bit 3 */ -#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!< Bit 4 */ -#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!< Bit 5 */ -#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!< Bit 6 */ -#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!< Bit 7 */ -#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!< Bit 8 */ -#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!< Bit 9 */ - -#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!< Addressing Mode (Slave mode) */ - -/******************* Bit definition for I2C_OAR2 register *******************/ -#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!< Dual addressing mode enable */ -#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!< Interface address */ - -/******************** Bit definition for I2C_DR register ********************/ -#define I2C_DR_DR ((uint8_t)0xFF) /*!< 8-bit Data Register */ - -/******************* Bit definition for I2C_SR1 register ********************/ -#define I2C_SR1_SB ((uint16_t)0x0001) /*!< Start Bit (Master mode) */ -#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!< Address sent (master mode)/matched (slave mode) */ -#define I2C_SR1_BTF ((uint16_t)0x0004) /*!< Byte Transfer Finished */ -#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!< 10-bit header sent (Master mode) */ -#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!< Stop detection (Slave mode) */ -#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!< Data Register not Empty (receivers) */ -#define I2C_SR1_TXE ((uint16_t)0x0080) /*!< Data Register Empty (transmitters) */ -#define I2C_SR1_BERR ((uint16_t)0x0100) /*!< Bus Error */ -#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!< Arbitration Lost (master mode) */ -#define I2C_SR1_AF ((uint16_t)0x0400) /*!< Acknowledge Failure */ -#define I2C_SR1_OVR ((uint16_t)0x0800) /*!< Overrun/Underrun */ -#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!< PEC Error in reception */ -#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!< Timeout or Tlow Error */ -#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!< SMBus Alert */ - -/******************* Bit definition for I2C_SR2 register ********************/ -#define I2C_SR2_MSL ((uint16_t)0x0001) /*!< Master/Slave */ -#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!< Bus Busy */ -#define I2C_SR2_TRA ((uint16_t)0x0004) /*!< Transmitter/Receiver */ -#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!< General Call Address (Slave mode) */ -#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!< SMBus Device Default Address (Slave mode) */ -#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!< SMBus Host Header (Slave mode) */ -#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!< Dual Flag (Slave mode) */ -#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!< Packet Error Checking Register */ - -/******************* Bit definition for I2C_CCR register ********************/ -#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */ -#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!< Fast Mode Duty Cycle */ -#define I2C_CCR_FS ((uint16_t)0x8000) /*!< I2C Master Mode Selection */ - -/****************** Bit definition for I2C_TRISE register *******************/ -#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ - -/******************************************************************************/ -/* */ -/* Universal Synchronous Asynchronous Receiver Transmitter */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for USART_SR register *******************/ -#define USART_SR_PE ((uint16_t)0x0001) /*!< Parity Error */ -#define USART_SR_FE ((uint16_t)0x0002) /*!< Framing Error */ -#define USART_SR_NE ((uint16_t)0x0004) /*!< Noise Error Flag */ -#define USART_SR_ORE ((uint16_t)0x0008) /*!< OverRun Error */ -#define USART_SR_IDLE ((uint16_t)0x0010) /*!< IDLE line detected */ -#define USART_SR_RXNE ((uint16_t)0x0020) /*!< Read Data Register Not Empty */ -#define USART_SR_TC ((uint16_t)0x0040) /*!< Transmission Complete */ -#define USART_SR_TXE ((uint16_t)0x0080) /*!< Transmit Data Register Empty */ -#define USART_SR_LBD ((uint16_t)0x0100) /*!< LIN Break Detection Flag */ -#define USART_SR_CTS ((uint16_t)0x0200) /*!< CTS Flag */ - -/******************* Bit definition for USART_DR register *******************/ -#define USART_DR_DR ((uint16_t)0x01FF) /*!< Data value */ - -/****************** Bit definition for USART_BRR register *******************/ -#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!< Fraction of USARTDIV */ -#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */ - -/****************** Bit definition for USART_CR1 register *******************/ -#define USART_CR1_SBK ((uint16_t)0x0001) /*!< Send Break */ -#define USART_CR1_RWU ((uint16_t)0x0002) /*!< Receiver wakeup */ -#define USART_CR1_RE ((uint16_t)0x0004) /*!< Receiver Enable */ -#define USART_CR1_TE ((uint16_t)0x0008) /*!< Transmitter Enable */ -#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!< IDLE Interrupt Enable */ -#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!< RXNE Interrupt Enable */ -#define USART_CR1_TCIE ((uint16_t)0x0040) /*!< Transmission Complete Interrupt Enable */ -#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!< PE Interrupt Enable */ -#define USART_CR1_PEIE ((uint16_t)0x0100) /*!< PE Interrupt Enable */ -#define USART_CR1_PS ((uint16_t)0x0200) /*!< Parity Selection */ -#define USART_CR1_PCE ((uint16_t)0x0400) /*!< Parity Control Enable */ -#define USART_CR1_WAKE ((uint16_t)0x0800) /*!< Wakeup method */ -#define USART_CR1_M ((uint16_t)0x1000) /*!< Word length */ -#define USART_CR1_UE ((uint16_t)0x2000) /*!< USART Enable */ -#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!< USART Oversmapling 8-bits */ - -/****************** Bit definition for USART_CR2 register *******************/ -#define USART_CR2_ADD ((uint16_t)0x000F) /*!< Address of the USART node */ -#define USART_CR2_LBDL ((uint16_t)0x0020) /*!< LIN Break Detection Length */ -#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!< LIN Break Detection Interrupt Enable */ -#define USART_CR2_LBCL ((uint16_t)0x0100) /*!< Last Bit Clock pulse */ -#define USART_CR2_CPHA ((uint16_t)0x0200) /*!< Clock Phase */ -#define USART_CR2_CPOL ((uint16_t)0x0400) /*!< Clock Polarity */ -#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!< Clock Enable */ - -#define USART_CR2_STOP ((uint16_t)0x3000) /*!< STOP[1:0] bits (STOP bits) */ -#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USART_CR2_LINEN ((uint16_t)0x4000) /*!< LIN mode enable */ - -/****************** Bit definition for USART_CR3 register *******************/ -#define USART_CR3_EIE ((uint16_t)0x0001) /*!< Error Interrupt Enable */ -#define USART_CR3_IREN ((uint16_t)0x0002) /*!< IrDA mode Enable */ -#define USART_CR3_IRLP ((uint16_t)0x0004) /*!< IrDA Low-Power */ -#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!< Half-Duplex Selection */ -#define USART_CR3_NACK ((uint16_t)0x0010) /*!< Smartcard NACK enable */ -#define USART_CR3_SCEN ((uint16_t)0x0020) /*!< Smartcard mode enable */ -#define USART_CR3_DMAR ((uint16_t)0x0040) /*!< DMA Enable Receiver */ -#define USART_CR3_DMAT ((uint16_t)0x0080) /*!< DMA Enable Transmitter */ -#define USART_CR3_RTSE ((uint16_t)0x0100) /*!< RTS Enable */ -#define USART_CR3_CTSE ((uint16_t)0x0200) /*!< CTS Enable */ -#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!< CTS Interrupt Enable */ -#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!< One Bit method */ - -/****************** Bit definition for USART_GTPR register ******************/ -#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */ -#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!< Bit 2 */ -#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!< Bit 3 */ -#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!< Bit 4 */ -#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!< Bit 5 */ -#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!< Bit 6 */ -#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!< Bit 7 */ - -#define USART_GTPR_GT ((uint16_t)0xFF00) /*!< Guard time value */ - -/******************************************************************************/ -/* */ -/* Debug MCU */ -/* */ -/******************************************************************************/ - -/**************** Bit definition for DBGMCU_IDCODE register *****************/ -#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */ - -#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */ -#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */ -#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */ -#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */ -#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */ -#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */ -#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */ -#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */ -#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */ -#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */ - -/****************** Bit definition for DBGMCU_CR register *******************/ -#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */ -#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */ -#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */ -#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Assignment Control */ - -#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */ -#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!< Bit 1 */ - -#define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /*!< Debug Independent Watchdog stopped when Core is halted */ -#define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /*!< Debug Window Watchdog stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /*!< TIM1 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /*!< TIM2 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /*!< TIM3 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /*!< TIM4 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) /*!< Debug CAN1 stopped when Core is halted */ -#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /*!< SMBUS timeout mode stopped when Core is halted */ -#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /*!< SMBUS timeout mode stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000) /*!< TIM8 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) /*!< TIM5 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) /*!< TIM6 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) /*!< TIM7 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) /*!< Debug CAN2 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) /*!< Debug TIM15 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) /*!< Debug TIM16 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) /*!< Debug TIM17 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) /*!< Debug TIM12 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) /*!< Debug TIM13 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) /*!< Debug TIM14 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) /*!< Debug TIM9 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) /*!< Debug TIM10 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) /*!< Debug TIM11 stopped when Core is halted */ - -/******************************************************************************/ -/* */ -/* FLASH and Option Bytes Registers */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for FLASH_ACR register ******************/ -#define FLASH_ACR_LATENCY ((uint8_t)0x03) /*!< LATENCY[2:0] bits (Latency) */ -#define FLASH_ACR_LATENCY_0 ((uint8_t)0x00) /*!< Bit 0 */ -#define FLASH_ACR_LATENCY_1 ((uint8_t)0x01) /*!< Bit 0 */ -#define FLASH_ACR_LATENCY_2 ((uint8_t)0x02) /*!< Bit 1 */ - -#define FLASH_ACR_HLFCYA ((uint8_t)0x08) /*!< Flash Half Cycle Access Enable */ -#define FLASH_ACR_PRFTBE ((uint8_t)0x10) /*!< Prefetch Buffer Enable */ -#define FLASH_ACR_PRFTBS ((uint8_t)0x20) /*!< Prefetch Buffer Status */ - -/****************** Bit definition for FLASH_KEYR register ******************/ -#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */ - -/***************** Bit definition for FLASH_OPTKEYR register ****************/ -#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */ - -/****************** Bit definition for FLASH_SR register *******************/ -#define FLASH_SR_BSY ((uint8_t)0x01) /*!< Busy */ -#define FLASH_SR_PGERR ((uint8_t)0x04) /*!< Programming Error */ -#define FLASH_SR_WRPRTERR ((uint8_t)0x10) /*!< Write Protection Error */ -#define FLASH_SR_EOP ((uint8_t)0x20) /*!< End of operation */ - -/******************* Bit definition for FLASH_CR register *******************/ -#define FLASH_CR_PG ((uint16_t)0x0001) /*!< Programming */ -#define FLASH_CR_PER ((uint16_t)0x0002) /*!< Page Erase */ -#define FLASH_CR_MER ((uint16_t)0x0004) /*!< Mass Erase */ -#define FLASH_CR_OPTPG ((uint16_t)0x0010) /*!< Option Byte Programming */ -#define FLASH_CR_OPTER ((uint16_t)0x0020) /*!< Option Byte Erase */ -#define FLASH_CR_STRT ((uint16_t)0x0040) /*!< Start */ -#define FLASH_CR_LOCK ((uint16_t)0x0080) /*!< Lock */ -#define FLASH_CR_OPTWRE ((uint16_t)0x0200) /*!< Option Bytes Write Enable */ -#define FLASH_CR_ERRIE ((uint16_t)0x0400) /*!< Error Interrupt Enable */ -#define FLASH_CR_EOPIE ((uint16_t)0x1000) /*!< End of operation interrupt enable */ - -/******************* Bit definition for FLASH_AR register *******************/ -#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */ - -/****************** Bit definition for FLASH_OBR register *******************/ -#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /*!< Option Byte Error */ -#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /*!< Read protection */ - -#define FLASH_OBR_USER ((uint16_t)0x03FC) /*!< User Option Bytes */ -#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /*!< WDG_SW */ -#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /*!< nRST_STOP */ -#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /*!< nRST_STDBY */ -#define FLASH_OBR_BFB2 ((uint16_t)0x0020) /*!< BFB2 */ - -/****************** Bit definition for FLASH_WRPR register ******************/ -#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */ - -/*----------------------------------------------------------------------------*/ - -/****************** Bit definition for FLASH_RDP register *******************/ -#define FLASH_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */ -#define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */ - -/****************** Bit definition for FLASH_USER register ******************/ -#define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */ -#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */ - -/****************** Bit definition for FLASH_Data0 register *****************/ -#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /*!< User data storage option byte */ -#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /*!< User data storage complemented option byte */ - -/****************** Bit definition for FLASH_Data1 register *****************/ -#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /*!< User data storage option byte */ -#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /*!< User data storage complemented option byte */ - -/****************** Bit definition for FLASH_WRP0 register ******************/ -#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ -#define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ - -/****************** Bit definition for FLASH_WRP1 register ******************/ -#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ -#define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ - -/****************** Bit definition for FLASH_WRP2 register ******************/ -#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ -#define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ - -/****************** Bit definition for FLASH_WRP3 register ******************/ -#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ -#define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ - -#ifdef STM32F10X_CL -/******************************************************************************/ -/* Ethernet MAC Registers bits definitions */ -/******************************************************************************/ -/* Bit definition for Ethernet MAC Control Register register */ -#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */ -#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */ -#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */ - #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ - #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ - #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ - #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ - #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ - #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ - #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ - #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ -#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */ -#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */ -#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */ -#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */ -#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */ -#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */ -#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */ -#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */ -#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling - a transmission attempt during retries after a collision: 0 =< r <2^k */ - #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */ - #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */ - #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */ - #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */ -#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */ -#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */ -#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */ - -/* Bit definition for Ethernet MAC Frame Filter Register */ -#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */ -#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */ -#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */ -#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */ -#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */ - #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ - #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ - #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ -#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */ -#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */ -#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */ -#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */ -#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */ -#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */ - -/* Bit definition for Ethernet MAC Hash Table High Register */ -#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */ - -/* Bit definition for Ethernet MAC Hash Table Low Register */ -#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */ - -/* Bit definition for Ethernet MAC MII Address Register */ -#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */ -#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */ -#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */ - #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */ - #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ - #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ -#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */ -#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */ - -/* Bit definition for Ethernet MAC MII Data Register */ -#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */ - -/* Bit definition for Ethernet MAC Flow Control Register */ -#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */ -#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */ -#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */ - #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ - #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */ - #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */ - #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ -#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */ -#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */ -#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */ -#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */ - -/* Bit definition for Ethernet MAC VLAN Tag Register */ -#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */ -#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ - -/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ -#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */ -/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. - Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ -/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask - Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask - Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask - Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask - Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - - RSVD - Filter1 Command - RSVD - Filter0 Command - Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset - Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 - Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ - -/* Bit definition for Ethernet MAC PMT Control and Status Register */ -#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ -#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */ -#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */ -#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */ -#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */ -#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */ -#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */ - -/* Bit definition for Ethernet MAC Status Register */ -#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */ -#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */ -#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */ -#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */ -#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */ - -/* Bit definition for Ethernet MAC Interrupt Mask Register */ -#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */ -#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */ - -/* Bit definition for Ethernet MAC Address0 High Register */ -#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */ - -/* Bit definition for Ethernet MAC Address0 Low Register */ -#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */ - -/* Bit definition for Ethernet MAC Address1 High Register */ -#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */ -#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */ -#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ - #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ - #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ - #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ - #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ - #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ - #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ -#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */ - -/* Bit definition for Ethernet MAC Address1 Low Register */ -#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */ - -/* Bit definition for Ethernet MAC Address2 High Register */ -#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */ -#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */ -#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ - #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ - #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ - #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ - #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ - #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ - #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ -#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */ - -/* Bit definition for Ethernet MAC Address2 Low Register */ -#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */ - -/* Bit definition for Ethernet MAC Address3 High Register */ -#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */ -#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */ -#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ - #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ - #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ - #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ - #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ - #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ - #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ -#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */ - -/* Bit definition for Ethernet MAC Address3 Low Register */ -#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */ - -/******************************************************************************/ -/* Ethernet MMC Registers bits definition */ -/******************************************************************************/ - -/* Bit definition for Ethernet MMC Contol Register */ -#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */ -#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */ -#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */ -#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */ - -/* Bit definition for Ethernet MMC Receive Interrupt Register */ -#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ -#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ -#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ - -/* Bit definition for Ethernet MMC Transmit Interrupt Register */ -#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ -#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ -#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ - -/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */ -#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ -#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ -#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ - -/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */ -#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ -#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ -#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ - -/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */ -#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ - -/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */ -#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ - -/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */ -#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */ - -/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */ -#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */ - -/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */ -#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ - -/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */ -#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */ - -/******************************************************************************/ -/* Ethernet PTP Registers bits definition */ -/******************************************************************************/ - -/* Bit definition for Ethernet PTP Time Stamp Contol Register */ -#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */ -#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */ -#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */ -#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */ -#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */ -#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */ - -/* Bit definition for Ethernet PTP Sub-Second Increment Register */ -#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */ - -/* Bit definition for Ethernet PTP Time Stamp High Register */ -#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */ - -/* Bit definition for Ethernet PTP Time Stamp Low Register */ -#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */ -#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */ - -/* Bit definition for Ethernet PTP Time Stamp High Update Register */ -#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */ - -/* Bit definition for Ethernet PTP Time Stamp Low Update Register */ -#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */ -#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */ - -/* Bit definition for Ethernet PTP Time Stamp Addend Register */ -#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */ - -/* Bit definition for Ethernet PTP Target Time High Register */ -#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */ - -/* Bit definition for Ethernet PTP Target Time Low Register */ -#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */ - -/******************************************************************************/ -/* Ethernet DMA Registers bits definition */ -/******************************************************************************/ - -/* Bit definition for Ethernet DMA Bus Mode Register */ -#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */ -#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */ -#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */ -#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */ - #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ - #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ - #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ - #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ - #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ - #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ - #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ - #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ - #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ - #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ - #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ - #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ -#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */ -#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ - #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */ - #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */ - #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */ - #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ -#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */ - #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ - #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ - #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ - #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ - #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ - #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ - #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ - #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ - #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ - #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ - #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ - #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ -#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */ -#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */ -#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */ - -/* Bit definition for Ethernet DMA Transmit Poll Demand Register */ -#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */ - -/* Bit definition for Ethernet DMA Receive Poll Demand Register */ -#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */ - -/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */ -#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */ - -/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */ -#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */ - -/* Bit definition for Ethernet DMA Status Register */ -#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */ -#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */ -#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */ -#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */ - /* combination with EBS[2:0] for GetFlagStatus function */ - #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ - #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ - #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ -#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */ - #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ - #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */ - #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */ - #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */ - #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */ - #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */ -#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */ - #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ - #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */ - #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */ - #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */ - #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */ - #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */ -#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */ -#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */ -#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */ -#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */ -#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */ -#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */ -#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */ -#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */ -#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */ -#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */ -#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */ -#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */ -#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */ -#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */ -#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */ - -/* Bit definition for Ethernet DMA Operation Mode Register */ -#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ -#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */ -#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */ -#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */ -#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */ -#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */ - #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ - #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ - #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ - #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ - #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ - #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ - #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ - #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ -#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */ -#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */ -#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */ -#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */ - #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ - #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ - #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ - #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ -#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */ -#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */ - -/* Bit definition for Ethernet DMA Interrupt Enable Register */ -#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */ -#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */ -#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */ -#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */ -#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */ -#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */ -#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */ -#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */ -#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */ -#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */ -#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */ -#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */ -#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */ -#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */ -#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */ - -/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */ -#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */ -#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */ -#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */ -#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */ - -/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */ -#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */ - -/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */ -#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */ - -/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */ -#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */ - -/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */ -#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */ -#endif /* STM32F10X_CL */ - -/** - * @} - */ - - /** - * @} - */ - -#ifdef USE_STDPERIPH_DRIVER - #include "stm32f10x_conf.h" -#endif - -/** @addtogroup Exported_macro - * @{ - */ - -#define SET_BIT(REG, BIT) ((REG) |= (BIT)) - -#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) - -#define READ_BIT(REG, BIT) ((REG) & (BIT)) - -#define CLEAR_REG(REG) ((REG) = (0x0)) - -#define WRITE_REG(REG, VAL) ((REG) = (VAL)) - -#define READ_REG(REG) ((REG)) - -#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_H */ - -/** - * @} - */ - - /** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/firmware/chibios/os/hal/platforms/STM32F4xx/adc_lld.c b/firmware/chibios/os/hal/platforms/STM32F4xx/adc_lld.c deleted file mode 100644 index 2ff062c059..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F4xx/adc_lld.c +++ /dev/null @@ -1,432 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F4xx/adc_lld.c - * @brief STM32F4xx/STM32F2xx ADC subsystem low level driver source. - * - * @addtogroup ADC - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_ADC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define ADC1_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_CHN) - -#define ADC2_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_ADC_ADC2_DMA_STREAM, STM32_ADC2_DMA_CHN) - -#define ADC3_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_ADC_ADC3_DMA_STREAM, STM32_ADC3_DMA_CHN) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief ADC1 driver identifier.*/ -#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__) -ADCDriver ADCD1; -#endif - -/** @brief ADC2 driver identifier.*/ -#if STM32_ADC_USE_ADC2 || defined(__DOXYGEN__) -ADCDriver ADCD2; -#endif - -/** @brief ADC3 driver identifier.*/ -#if STM32_ADC_USE_ADC3 || defined(__DOXYGEN__) -ADCDriver ADCD3; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -#include "error_handling.h" - -/** - * @brief ADC DMA ISR service routine. - * - * @param[in] adcp pointer to the @p ADCDriver object - * @param[in] flags pre-shifted content of the ISR register - */ -static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) { - - efiAssertVoid(getRemainingStack(chThdSelf()) > 64, "sys_adc"); - - /* DMA errors handling.*/ - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - /* DMA, this could help only if the DMA tries to access an unmapped - address space or violates alignment rules.*/ - _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE); - } - else { - /* It is possible that the conversion group has already be reset by the - ADC error handler, in this case this interrupt is spurious.*/ - if (adcp->grpp != NULL) { - if ((flags & STM32_DMA_ISR_TCIF) != 0) { - /* Transfer complete processing.*/ - _adc_isr_full_code(adcp); - } - else if ((flags & STM32_DMA_ISR_HTIF) != 0) { - /* Half transfer processing.*/ - _adc_isr_half_code(adcp); - } - } - } -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2 || STM32_ADC_USE_ADC3 || \ - defined(__DOXYGEN__) -/** - * @brief ADC interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(ADC1_2_3_IRQHandler) { - uint32_t sr; - - CH_IRQ_PROLOGUE(); - -#if STM32_ADC_USE_ADC1 - sr = ADC1->SR; - ADC1->SR = 0; - /* Note, an overflow may occur after the conversion ended before the driver - is able to stop the ADC, this is why the DMA channel is checked too.*/ - if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD1.dmastp) > 0)) { - /* ADC overflow condition, this could happen only if the DMA is unable - to read data fast enough.*/ - if (ADCD1.grpp != NULL) - _adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW); - } - /* TODO: Add here analog watchdog handling.*/ -#endif /* STM32_ADC_USE_ADC1 */ - -#if STM32_ADC_USE_ADC2 - sr = ADC2->SR; - ADC2->SR = 0; - /* Note, an overflow may occur after the conversion ended before the driver - is able to stop the ADC, this is why the DMA channel is checked too.*/ - if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD2.dmastp) > 0)) { - /* ADC overflow condition, this could happen only if the DMA is unable - to read data fast enough.*/ - if (ADCD2.grpp != NULL) - _adc_isr_error_code(&ADCD2, ADC_ERR_OVERFLOW); - } - /* TODO: Add here analog watchdog handling.*/ -#endif /* STM32_ADC_USE_ADC2 */ - -#if STM32_ADC_USE_ADC3 - sr = ADC3->SR; - ADC3->SR = 0; - /* Note, an overflow may occur after the conversion ended before the driver - is able to stop the ADC, this is why the DMA channel is checked too.*/ - if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD3.dmastp) > 0)) { - /* ADC overflow condition, this could happen only if the DMA is unable - to read data fast enough.*/ - if (ADCD3.grpp != NULL) - _adc_isr_error_code(&ADCD3, ADC_ERR_OVERFLOW); - } - /* TODO: Add here analog watchdog handling.*/ -#endif /* STM32_ADC_USE_ADC3 */ - - CH_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level ADC driver initialization. - * - * @notapi - */ -void adc_lld_init(void) { - -#if STM32_ADC_USE_ADC1 - /* Driver initialization.*/ - adcObjectInit(&ADCD1); - ADCD1.adc = ADC1; - ADCD1.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC1_DMA_STREAM); - ADCD1.dmamode = STM32_DMA_CR_CHSEL(ADC1_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | - STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; -#endif - -#if STM32_ADC_USE_ADC2 - /* Driver initialization.*/ - adcObjectInit(&ADCD2); - ADCD2.adc = ADC2; - ADCD2.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC2_DMA_STREAM); - ADCD2.dmamode = STM32_DMA_CR_CHSEL(ADC2_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_ADC_ADC2_DMA_PRIORITY) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | - STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; -#endif - -#if STM32_ADC_USE_ADC3 - /* Driver initialization.*/ - adcObjectInit(&ADCD3); - ADCD3.adc = ADC3; - ADCD3.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC3_DMA_STREAM); - ADCD3.dmamode = STM32_DMA_CR_CHSEL(ADC3_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_ADC_ADC3_DMA_PRIORITY) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | - STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; -#endif - - /* The shared vector is initialized on driver initialization and never - disabled.*/ - nvicEnableVector(ADC_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY)); -} - -/** - * @brief Configures and activates the ADC peripheral. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_start(ADCDriver *adcp) { - - /* If in stopped state then enables the ADC and DMA clocks.*/ - if (adcp->state == ADC_STOP) { -#if STM32_ADC_USE_ADC1 - if (&ADCD1 == adcp) { - bool_t b; - b = dmaStreamAllocate(adcp->dmastp, - STM32_ADC_ADC1_DMA_IRQ_PRIORITY, - (stm32_dmaisr_t)adc_lld_serve_rx_interrupt, - (void *)adcp); - chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated"); - dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR); - rccEnableADC1(FALSE); - } -#endif /* STM32_ADC_USE_ADC1 */ - -#if STM32_ADC_USE_ADC2 - if (&ADCD2 == adcp) { - bool_t b; - b = dmaStreamAllocate(adcp->dmastp, - STM32_ADC_ADC2_DMA_IRQ_PRIORITY, - (stm32_dmaisr_t)adc_lld_serve_rx_interrupt, - (void *)adcp); - chDbgAssert(!b, "adc_lld_start(), #2", "stream already allocated"); - dmaStreamSetPeripheral(adcp->dmastp, &ADC2->DR); - rccEnableADC2(FALSE); - } -#endif /* STM32_ADC_USE_ADC2 */ - -#if STM32_ADC_USE_ADC3 - if (&ADCD3 == adcp) { - bool_t b; - b = dmaStreamAllocate(adcp->dmastp, - STM32_ADC_ADC3_DMA_IRQ_PRIORITY, - (stm32_dmaisr_t)adc_lld_serve_rx_interrupt, - (void *)adcp); - chDbgAssert(!b, "adc_lld_start(), #3", "stream already allocated"); - dmaStreamSetPeripheral(adcp->dmastp, &ADC3->DR); - rccEnableADC3(FALSE); - } -#endif /* STM32_ADC_USE_ADC3 */ - - /* This is a common register but apparently it requires that at least one - of the ADCs is clocked in order to allow writing, see bug 3575297.*/ - ADC->CCR = (ADC->CCR & (ADC_CCR_TSVREFE | ADC_CCR_VBATE)) | - (STM32_ADC_ADCPRE << 16); - - /* ADC initial setup, starting the analog part here in order to reduce - the latency when starting a conversion.*/ - adcp->adc->CR1 = 0; - adcp->adc->CR2 = 0; - adcp->adc->CR2 = ADC_CR2_ADON; - } -} - -/** - * @brief Deactivates the ADC peripheral. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_stop(ADCDriver *adcp) { - - /* If in ready state then disables the ADC clock.*/ - if (adcp->state == ADC_READY) { - dmaStreamRelease(adcp->dmastp); - adcp->adc->CR1 = 0; - adcp->adc->CR2 = 0; - -#if STM32_ADC_USE_ADC1 - if (&ADCD1 == adcp) - rccDisableADC1(FALSE); -#endif - -#if STM32_ADC_USE_ADC2 - if (&ADCD2 == adcp) - rccDisableADC2(FALSE); -#endif - -#if STM32_ADC_USE_ADC3 - if (&ADCD3 == adcp) - rccDisableADC3(FALSE); -#endif - } -} - -/** - * @brief Starts an ADC conversion. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_start_conversion(ADCDriver *adcp) { - uint32_t mode; - uint32_t cr2; - const ADCConversionGroup *grpp = adcp->grpp; - - /* DMA setup.*/ - mode = adcp->dmamode; - if (grpp->circular) { - mode |= STM32_DMA_CR_CIRC; - if (adcp->depth > 1) { - /* If circular buffer depth > 1, then the half transfer interrupt - is enabled in order to allow streaming processing.*/ - mode |= STM32_DMA_CR_HTIE; - } - } - dmaStreamSetMemory0(adcp->dmastp, adcp->samples); - dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels * - (uint32_t)adcp->depth); - dmaStreamSetMode(adcp->dmastp, mode); - dmaStreamEnable(adcp->dmastp); - - /* ADC setup.*/ - adcp->adc->SR = 0; - adcp->adc->SMPR1 = grpp->smpr1; - adcp->adc->SMPR2 = grpp->smpr2; - adcp->adc->SQR1 = grpp->sqr1; - adcp->adc->SQR2 = grpp->sqr2; - adcp->adc->SQR3 = grpp->sqr3; - - /* ADC configuration and start.*/ - adcp->adc->CR1 = grpp->cr1 | ADC_CR1_OVRIE | ADC_CR1_SCAN; - - /* Enforcing the mandatory bits in CR2.*/ - cr2 = grpp->cr2 | ADC_CR2_DMA | ADC_CR2_DDS | ADC_CR2_ADON; - - /* The start method is different dependign if HW or SW triggered, the - start is performed using the method specified in the CR2 configuration.*/ - if ((cr2 & ADC_CR2_SWSTART) != 0) { - /* Initializing CR2 while keeping ADC_CR2_SWSTART at zero.*/ - adcp->adc->CR2 = (cr2 | ADC_CR2_CONT) & ~ADC_CR2_SWSTART; - - /* Finally enabling ADC_CR2_SWSTART.*/ - adcp->adc->CR2 = (cr2 | ADC_CR2_CONT); - } - else - adcp->adc->CR2 = cr2; -} - -/** - * @brief Stops an ongoing conversion. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_stop_conversion(ADCDriver *adcp) { - - dmaStreamDisable(adcp->dmastp); - adcp->adc->CR1 = 0; - adcp->adc->CR2 = 0; - adcp->adc->CR2 = ADC_CR2_ADON; -} - -/** - * @brief Enables the TSVREFE bit. - * @details The TSVREFE bit is required in order to sample the internal - * temperature sensor and internal reference voltage. - * @note This is an STM32-only functionality. - */ -void adcSTM32EnableTSVREFE(void) { - - ADC->CCR |= ADC_CCR_TSVREFE; -} - -/** - * @brief Disables the TSVREFE bit. - * @details The TSVREFE bit is required in order to sample the internal - * temperature sensor and internal reference voltage. - * @note This is an STM32-only functionality. - */ -void adcSTM32DisableTSVREFE(void) { - - ADC->CCR &= ~ADC_CCR_TSVREFE; -} - -/** - * @brief Enables the VBATE bit. - * @details The VBATE bit is required in order to sample the VBAT channel. - * @note This is an STM32-only functionality. - * @note This function is meant to be called after @p adcStart(). - */ -void adcSTM32EnableVBATE(void) { - - ADC->CCR |= ADC_CCR_VBATE; -} - -/** - * @brief Disables the VBATE bit. - * @details The VBATE bit is required in order to sample the VBAT channel. - * @note This is an STM32-only functionality. - * @note This function is meant to be called after @p adcStart(). - */ -void adcSTM32DisableVBATE(void) { - - ADC->CCR &= ~ADC_CCR_VBATE; -} - -#endif /* HAL_USE_ADC */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32F4xx/adc_lld.h b/firmware/chibios/os/hal/platforms/STM32F4xx/adc_lld.h deleted file mode 100644 index 28d16b3217..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F4xx/adc_lld.h +++ /dev/null @@ -1,567 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F4xx/adc_lld.h - * @brief STM32F4xx/STM32F2xx ADC subsystem low level driver header. - * - * @addtogroup ADC - * @{ - */ - -#ifndef _ADC_LLD_H_ -#define _ADC_LLD_H_ - -#if HAL_USE_ADC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name Absolute Maximum Ratings - * @{ - */ -/** - * @brief Minimum ADC clock frequency. - */ -#define STM32_ADCCLK_MIN 600000 - -/** - * @brief Maximum ADC clock frequency. - */ -#if defined(STM32F4XX) || defined(__DOXYGEN__) -#define STM32_ADCCLK_MAX 36000000 -#else -#define STM32_ADCCLK_MAX 30000000 -#endif -/** @} */ - -/** - * @name Triggers selection - * @{ - */ -#define ADC_CR2_EXTSEL_SRC(n) ((n) << 24) /**< @brief Trigger source. */ -/** @} */ - -/** - * @name ADC clock divider settings - * @{ - */ -#define ADC_CCR_ADCPRE_DIV2 0 -#define ADC_CCR_ADCPRE_DIV4 1 -#define ADC_CCR_ADCPRE_DIV6 2 -#define ADC_CCR_ADCPRE_DIV8 3 -/** @} */ - -/** - * @name Available analog channels - * @{ - */ -#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */ -#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */ -#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */ -#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */ -#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */ -#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */ -#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */ -#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */ -#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */ -#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */ -#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */ -#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */ -#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */ -#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */ -#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */ -#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */ -#define ADC_CHANNEL_SENSOR 16 /**< @brief Internal temperature sensor. - @note Available onADC1 only. */ -#define ADC_CHANNEL_VREFINT 17 /**< @brief Internal reference. - @note Available onADC1 only. */ -#define ADC_CHANNEL_VBAT 18 /**< @brief VBAT. - @note Available onADC1 only. */ -/** @} */ - -/** - * @name Sampling rates - * @{ - */ -#define ADC_SAMPLE_3 0 /**< @brief 3 cycles sampling time. */ -#define ADC_SAMPLE_15 1 /**< @brief 15 cycles sampling time. */ -#define ADC_SAMPLE_28 2 /**< @brief 28 cycles sampling time. */ -#define ADC_SAMPLE_56 3 /**< @brief 56 cycles sampling time. */ -#define ADC_SAMPLE_84 4 /**< @brief 84 cycles sampling time. */ -#define ADC_SAMPLE_112 5 /**< @brief 112 cycles sampling time. */ -#define ADC_SAMPLE_144 6 /**< @brief 144 cycles sampling time. */ -#define ADC_SAMPLE_480 7 /**< @brief 480 cycles sampling time. */ -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief ADC common clock divider. - * @note This setting is influenced by the VDDA voltage and other - * external conditions, please refer to the datasheet for more - * info.
- * See section 5.3.20 "12-bit ADC characteristics". - */ -#if !defined(STM32_ADC_ADCPRE) || defined(__DOXYGEN__) -#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV2 -#endif - -/** - * @brief ADC1 driver enable switch. - * @details If set to @p TRUE the support for ADC1 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__) -#define STM32_ADC_USE_ADC1 FALSE -#endif - -/** - * @brief ADC2 driver enable switch. - * @details If set to @p TRUE the support for ADC2 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_ADC_USE_ADC2) || defined(__DOXYGEN__) -#define STM32_ADC_USE_ADC2 FALSE -#endif - -/** - * @brief ADC3 driver enable switch. - * @details If set to @p TRUE the support for ADC3 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_ADC_USE_ADC3) || defined(__DOXYGEN__) -#define STM32_ADC_USE_ADC3 FALSE -#endif - -/** - * @brief DMA stream used for ADC1 operations. - */ -#if !defined(STM32_ADC_ADC1_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) -#endif - -/** - * @brief DMA stream used for ADC2 operations. - */ -#if !defined(STM32_ADC_ADC2_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#endif - -/** - * @brief DMA stream used for ADC3 operations. - */ -#if !defined(STM32_ADC_ADC3_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#endif - -/** - * @brief ADC1 DMA priority (0..3|lowest..highest). - */ -#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#endif - -/** - * @brief ADC2 DMA priority (0..3|lowest..highest). - */ -#if !defined(STM32_ADC_ADC2_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_ADC2_DMA_PRIORITY 2 -#endif - -/** - * @brief ADC3 DMA priority (0..3|lowest..highest). - */ -#if !defined(STM32_ADC_ADC3_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_ADC3_DMA_PRIORITY 2 -#endif - -/** - * @brief ADC interrupt priority level setting. - * @note This setting is shared among ADC1, ADC2 and ADC3 because - * all ADCs share the same vector. - */ -#if !defined(STM32_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_IRQ_PRIORITY 5 -#endif - -/** - * @brief ADC1 DMA interrupt priority level setting. - */ -#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 -#endif - -/** - * @brief ADC2 DMA interrupt priority level setting. - */ -#if !defined(STM32_ADC_ADC2_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 -#endif - -/** - * @brief ADC3 DMA interrupt priority level setting. - */ -#if !defined(STM32_ADC_ADC3_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 -#endif - -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1 -#error "ADC1 not present in the selected device" -#endif - -#if STM32_ADC_USE_ADC2 && !STM32_HAS_ADC2 -#error "ADC2 not present in the selected device" -#endif - -#if STM32_ADC_USE_ADC3 && !STM32_HAS_ADC3 -#error "ADC3 not present in the selected device" -#endif - -#if !STM32_ADC_USE_ADC1 && !STM32_ADC_USE_ADC2 && !STM32_ADC_USE_ADC3 -#error "ADC driver activated but no ADC peripheral assigned" -#endif - -#if STM32_ADC_USE_ADC1 && \ - !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_MSK) -#error "invalid DMA stream associated to ADC1" -#endif - -#if STM32_ADC_USE_ADC2 && \ - !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC2_DMA_STREAM, STM32_ADC2_DMA_MSK) -#error "invalid DMA stream associated to ADC2" -#endif - -#if STM32_ADC_USE_ADC3 && \ - !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC3_DMA_STREAM, STM32_ADC3_DMA_MSK) -#error "invalid DMA stream associated to ADC3" -#endif - -/* ADC clock related settings and checks.*/ -#if STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV2 -#define STM32_ADCCLK (STM32_PCLK2 / 2) -#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV4 -#define STM32_ADCCLK (STM32_PCLK2 / 4) -#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV6 -#define STM32_ADCCLK (STM32_PCLK2 / 6) -#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV8 -#define STM32_ADCCLK (STM32_PCLK2 / 8) -#else -#error "invalid STM32_ADC_ADCPRE value specified" -#endif - -#if (STM32_ADCCLK < STM32_ADCCLK_MIN) || (STM32_ADCCLK > STM32_ADCCLK_MAX) -#error "STM32_ADCCLK outside acceptable range (STM32_ADCCLK_MIN...STM32_ADCCLK_MAX)" -#endif - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief ADC sample data type. - */ -typedef uint16_t adcsample_t; - -/** - * @brief Channels number in a conversion group. - */ -typedef uint16_t adc_channels_num_t; - -/** - * @brief Possible ADC failure causes. - * @note Error codes are architecture dependent and should not relied - * upon. - */ -typedef enum { - ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */ - ADC_ERR_OVERFLOW = 1 /**< ADC overflow condition. */ -} adcerror_t; - -/** - * @brief Type of a structure representing an ADC driver. - */ -typedef struct ADCDriver ADCDriver; - -/** - * @brief ADC notification callback type. - * - * @param[in] adcp pointer to the @p ADCDriver object triggering the - * callback - * @param[in] buffer pointer to the most recent samples data - * @param[in] n number of buffer rows available starting from @p buffer - */ -typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n); - -/** - * @brief ADC error callback type. - * - * @param[in] adcp pointer to the @p ADCDriver object triggering the - * callback - * @param[in] err ADC error code - */ -typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err); - -/** - * @brief Conversion group configuration structure. - * @details This implementation-dependent structure describes a conversion - * operation. - * @note The use of this configuration structure requires knowledge of - * STM32 ADC cell registers interface, please refer to the STM32 - * reference manual for details. - */ -typedef struct { - /** - * @brief Enables the circular buffer mode for the group. - */ - bool_t circular; - /** - * @brief Number of the analog channels belonging to the conversion group. - */ - adc_channels_num_t num_channels; - /** - * @brief Callback function associated to the group or @p NULL. - */ - adccallback_t end_cb; - /** - * @brief Error callback or @p NULL. - */ - adcerrorcallback_t error_cb; - /* End of the mandatory fields.*/ - /** - * @brief ADC CR1 register initialization data. - * @note All the required bits must be defined into this field except - * @p ADC_CR1_SCAN that is enforced inside the driver. - */ - uint32_t cr1; - /** - * @brief ADC CR2 register initialization data. - * @note All the required bits must be defined into this field except - * @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are - * enforced inside the driver. - */ - uint32_t cr2; - /** - * @brief ADC SMPR1 register initialization data. - * @details In this field must be specified the sample times for channels - * 10...18. - */ - uint32_t smpr1; - /** - * @brief ADC SMPR2 register initialization data. - * @details In this field must be specified the sample times for channels - * 0...9. - */ - uint32_t smpr2; - /** - * @brief ADC SQR1 register initialization data. - * @details Conversion group sequence 13...16 + sequence length. - */ - uint32_t sqr1; - /** - * @brief ADC SQR2 register initialization data. - * @details Conversion group sequence 7...12. - */ - uint32_t sqr2; - /** - * @brief ADC SQR3 register initialization data. - * @details Conversion group sequence 1...6. - */ - uint32_t sqr3; -} ADCConversionGroup; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - uint32_t dummy; -} ADCConfig; - -/** - * @brief Structure representing an ADC driver. - */ -struct ADCDriver { - /** - * @brief Driver state. - */ - adcstate_t state; - /** - * @brief Current configuration data. - */ - const ADCConfig *config; - /** - * @brief Current samples buffer pointer or @p NULL. - */ - adcsample_t *samples; - /** - * @brief Current samples buffer depth or @p 0. - */ - size_t depth; - /** - * @brief Current conversion group pointer or @p NULL. - */ - const ADCConversionGroup *grpp; -#if ADC_USE_WAIT || defined(__DOXYGEN__) - /** - * @brief Waiting thread. - */ - Thread *thread; -#endif -#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) -#if CH_USE_MUTEXES || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the peripheral. - */ - Mutex mutex; -#elif CH_USE_SEMAPHORES - Semaphore semaphore; -#endif -#endif /* ADC_USE_MUTUAL_EXCLUSION */ -#if defined(ADC_DRIVER_EXT_FIELDS) - ADC_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the ADCx registers block. - */ - ADC_TypeDef *adc; - /** - * @brief Pointer to associated DMA channel. - */ - const stm32_dma_stream_t *dmastp; - /** - * @brief DMA mode bit mask. - */ - uint32_t dmamode; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Sequences building helper macros - * @{ - */ -/** - * @brief Number of channels in a conversion sequence. - */ -#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 20) - -#define ADC_SQR3_SQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */ -#define ADC_SQR3_SQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */ -#define ADC_SQR3_SQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */ -#define ADC_SQR3_SQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */ -#define ADC_SQR3_SQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */ -#define ADC_SQR3_SQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */ - -#define ADC_SQR2_SQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */ -#define ADC_SQR2_SQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */ -#define ADC_SQR2_SQ9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */ -#define ADC_SQR2_SQ10_N(n) ((n) << 15) /**< @brief 10th channel in seq.*/ -#define ADC_SQR2_SQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/ -#define ADC_SQR2_SQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/ - -#define ADC_SQR1_SQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/ -#define ADC_SQR1_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/ -#define ADC_SQR1_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/ -#define ADC_SQR1_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/ -/** @} */ - -/** - * @name Sampling rate settings helper macros - * @{ - */ -#define ADC_SMPR2_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */ -#define ADC_SMPR2_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */ -#define ADC_SMPR2_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */ -#define ADC_SMPR2_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */ -#define ADC_SMPR2_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */ -#define ADC_SMPR2_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */ -#define ADC_SMPR2_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */ -#define ADC_SMPR2_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */ -#define ADC_SMPR2_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */ -#define ADC_SMPR2_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */ - -#define ADC_SMPR1_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */ -#define ADC_SMPR1_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */ -#define ADC_SMPR1_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */ -#define ADC_SMPR1_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */ -#define ADC_SMPR1_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */ -#define ADC_SMPR1_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */ -#define ADC_SMPR1_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor - sampling time. */ -#define ADC_SMPR1_SMP_VREF(n) ((n) << 21) /**< @brief Voltage Reference - sampling time. */ -#define ADC_SMPR1_SMP_VBAT(n) ((n) << 24) /**< @brief VBAT sampling time. */ -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__) -extern ADCDriver ADCD1; -#endif - -#if STM32_ADC_USE_ADC2 && !defined(__DOXYGEN__) -extern ADCDriver ADCD2; -#endif - -#if STM32_ADC_USE_ADC3 && !defined(__DOXYGEN__) -extern ADCDriver ADCD3; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void adc_lld_init(void); - void adc_lld_start(ADCDriver *adcp); - void adc_lld_stop(ADCDriver *adcp); - void adc_lld_start_conversion(ADCDriver *adcp); - void adc_lld_stop_conversion(ADCDriver *adcp); - void adcSTM32EnableTSVREFE(void); - void adcSTM32DisableTSVREFE(void); - void adcSTM32EnableVBATE(void); - void adcSTM32DisableVBATE(void); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_ADC */ - -#endif /* _ADC_LLD_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32F4xx/ext_lld_isr.c b/firmware/chibios/os/hal/platforms/STM32F4xx/ext_lld_isr.c deleted file mode 100644 index b64842b91b..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F4xx/ext_lld_isr.c +++ /dev/null @@ -1,359 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F4xx/ext_lld_isr.c - * @brief STM32F4xx/STM32F2xx EXT subsystem low level driver ISR code. - * - * @addtogroup EXT - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -#include "ext_lld_isr.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief EXTI[0] interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(EXTI0_IRQHandler) { - - CH_IRQ_PROLOGUE(); - - EXTI->PR = (1 << 0); - EXTD1.config->channels[0].cb(&EXTD1, 0); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[1] interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(EXTI1_IRQHandler) { - - CH_IRQ_PROLOGUE(); - - EXTI->PR = (1 << 1); - EXTD1.config->channels[1].cb(&EXTD1, 1); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[2] interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(EXTI2_IRQHandler) { - - CH_IRQ_PROLOGUE(); - - EXTI->PR = (1 << 2); - EXTD1.config->channels[2].cb(&EXTD1, 2); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[3] interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(EXTI3_IRQHandler) { - - CH_IRQ_PROLOGUE(); - - EXTI->PR = (1 << 3); - EXTD1.config->channels[3].cb(&EXTD1, 3); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[4] interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(EXTI4_IRQHandler) { - - CH_IRQ_PROLOGUE(); - - EXTI->PR = (1 << 4); - EXTD1.config->channels[4].cb(&EXTD1, 4); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[5]...EXTI[9] interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(EXTI9_5_IRQHandler) { - uint32_t pr; - - CH_IRQ_PROLOGUE(); - - pr = EXTI->PR & ((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9)); - EXTI->PR = pr; - if (pr & (1 << 5)) - EXTD1.config->channels[5].cb(&EXTD1, 5); - if (pr & (1 << 6)) - EXTD1.config->channels[6].cb(&EXTD1, 6); - if (pr & (1 << 7)) - EXTD1.config->channels[7].cb(&EXTD1, 7); - if (pr & (1 << 8)) - EXTD1.config->channels[8].cb(&EXTD1, 8); - if (pr & (1 << 9)) - EXTD1.config->channels[9].cb(&EXTD1, 9); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[10]...EXTI[15] interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(EXTI15_10_IRQHandler) { - uint32_t pr; - - CH_IRQ_PROLOGUE(); - - pr = EXTI->PR & ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) | - (1 << 15)); - EXTI->PR = pr; - if (pr & (1 << 10)) - EXTD1.config->channels[10].cb(&EXTD1, 10); - if (pr & (1 << 11)) - EXTD1.config->channels[11].cb(&EXTD1, 11); - if (pr & (1 << 12)) - EXTD1.config->channels[12].cb(&EXTD1, 12); - if (pr & (1 << 13)) - EXTD1.config->channels[13].cb(&EXTD1, 13); - if (pr & (1 << 14)) - EXTD1.config->channels[14].cb(&EXTD1, 14); - if (pr & (1 << 15)) - EXTD1.config->channels[15].cb(&EXTD1, 15); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[16] interrupt handler (PVD). - * - * @isr - */ -CH_IRQ_HANDLER(PVD_IRQHandler) { - - CH_IRQ_PROLOGUE(); - - EXTI->PR = (1 << 16); - EXTD1.config->channels[16].cb(&EXTD1, 16); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[17] interrupt handler (RTC). - * - * @isr - */ -CH_IRQ_HANDLER(RTC_Alarm_IRQHandler) { - - CH_IRQ_PROLOGUE(); - - EXTI->PR = (1 << 17); - EXTD1.config->channels[17].cb(&EXTD1, 17); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[18] interrupt handler (OTG_FS_WKUP). - * - * @isr - */ -CH_IRQ_HANDLER(OTG_FS_WKUP_IRQHandler) { - - CH_IRQ_PROLOGUE(); - - EXTI->PR = (1 << 18); - EXTD1.config->channels[18].cb(&EXTD1, 18); - - CH_IRQ_EPILOGUE(); -} - -#if !defined(STM32F401xx) -/** - * @brief EXTI[19] interrupt handler (ETH_WKUP). - * - * @isr - */ -CH_IRQ_HANDLER(ETH_WKUP_IRQHandler) { - - CH_IRQ_PROLOGUE(); - - EXTI->PR = (1 << 19); - EXTD1.config->channels[19].cb(&EXTD1, 19); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[20] interrupt handler (OTG_HS_WKUP). - * - * @isr - */ -CH_IRQ_HANDLER(OTG_HS_WKUP_IRQHandler) { - - CH_IRQ_PROLOGUE(); - - EXTI->PR = (1 << 20); - EXTD1.config->channels[20].cb(&EXTD1, 20); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[21] interrupt handler (TAMPER_STAMP). - * - * @isr - */ -CH_IRQ_HANDLER(TAMPER_STAMP_IRQHandler) { - - CH_IRQ_PROLOGUE(); - - EXTI->PR = (1 << 21); - EXTD1.config->channels[21].cb(&EXTD1, 21); - - CH_IRQ_EPILOGUE(); -} -#endif /* !defined(STM32F401xx) */ - -/** - * @brief EXTI[22] interrupt handler (RTC_WKUP). - * - * @isr - */ -CH_IRQ_HANDLER(RTC_WKUP_IRQHandler) { - - CH_IRQ_PROLOGUE(); - - EXTI->PR = (1 << 22); - EXTD1.config->channels[22].cb(&EXTD1, 22); - - CH_IRQ_EPILOGUE(); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Enables EXTI IRQ sources. - * - * @notapi - */ -void ext_lld_exti_irq_enable(void) { - - nvicEnableVector(EXTI0_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI0_IRQ_PRIORITY)); - nvicEnableVector(EXTI1_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI1_IRQ_PRIORITY)); - nvicEnableVector(EXTI2_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI2_IRQ_PRIORITY)); - nvicEnableVector(EXTI3_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI3_IRQ_PRIORITY)); - nvicEnableVector(EXTI4_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_IRQ_PRIORITY)); - nvicEnableVector(EXTI9_5_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI5_9_IRQ_PRIORITY)); - nvicEnableVector(EXTI15_10_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI10_15_IRQ_PRIORITY)); - nvicEnableVector(PVD_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY)); - nvicEnableVector(RTC_Alarm_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY)); - nvicEnableVector(OTG_FS_WKUP_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY)); -#if !defined(STM32F401xx) - nvicEnableVector(ETH_WKUP_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY)); - nvicEnableVector(OTG_HS_WKUP_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI20_IRQ_PRIORITY)); - nvicEnableVector(TAMP_STAMP_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI21_IRQ_PRIORITY)); -#endif /* !defined(STM32F401xx) */ - nvicEnableVector(RTC_WKUP_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI22_IRQ_PRIORITY)); -} - -/** - * @brief Disables EXTI IRQ sources. - * - * @notapi - */ -void ext_lld_exti_irq_disable(void) { - - nvicDisableVector(EXTI0_IRQn); - nvicDisableVector(EXTI1_IRQn); - nvicDisableVector(EXTI2_IRQn); - nvicDisableVector(EXTI3_IRQn); - nvicDisableVector(EXTI4_IRQn); - nvicDisableVector(EXTI9_5_IRQn); - nvicDisableVector(EXTI15_10_IRQn); - nvicDisableVector(PVD_IRQn); - nvicDisableVector(RTC_Alarm_IRQn); - nvicDisableVector(OTG_FS_WKUP_IRQn); -#if !defined(STM32F401xx) - nvicDisableVector(ETH_WKUP_IRQn); - nvicDisableVector(OTG_HS_WKUP_IRQn); - nvicDisableVector(TAMP_STAMP_IRQn); -#endif /* !defined(STM32F401xx) */ - nvicDisableVector(RTC_WKUP_IRQn); -} - -#endif /* HAL_USE_EXT */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32F4xx/ext_lld_isr.h b/firmware/chibios/os/hal/platforms/STM32F4xx/ext_lld_isr.h deleted file mode 100644 index d961d32079..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F4xx/ext_lld_isr.h +++ /dev/null @@ -1,170 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F4xx/ext_lld_isr.h - * @brief STM32F4xx/STM32F2xx EXT subsystem low level driver ISR header. - * - * @addtogroup EXT - * @{ - */ - -#ifndef _EXT_LLD_ISR_H_ -#define _EXT_LLD_ISR_H_ - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief EXTI0 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI1 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI2 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI3 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI4 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI9..5 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI5_9_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI15..10 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI10_15_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI16 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI17 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI18 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI18_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI19 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI19_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI20 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI20_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI21 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI21_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI21_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI22 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI22_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI22_IRQ_PRIORITY 6 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void ext_lld_exti_irq_enable(void); - void ext_lld_exti_irq_disable(void); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_EXT */ - -#endif /* _EXT_LLD_ISR_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32F4xx/hal_lld.c b/firmware/chibios/os/hal/platforms/STM32F4xx/hal_lld.c deleted file mode 100644 index 07d3c61737..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F4xx/hal_lld.c +++ /dev/null @@ -1,275 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F4xx/hal_lld.c - * @brief STM32F4xx/STM32F2xx HAL subsystem low level driver source. - * - * @addtogroup HAL - * @{ - */ - -/* TODO: LSEBYP like in F3.*/ - -#include "ch.h" -#include "hal.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Initializes the backup domain. - * @note WARNING! Changing clock source impossible without resetting - * of the whole BKP domain. - */ -static void hal_lld_backup_domain_init(void) { - - /* Backup domain access enabled and left open.*/ - PWR->CR |= PWR_CR_DBP; - - /* Reset BKP domain if different clock source selected.*/ - if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) { - /* Backup domain reset.*/ - RCC->BDCR = RCC_BDCR_BDRST; - RCC->BDCR = 0; - } - -#if STM32_LSE_ENABLED -#if defined(STM32_LSE_BYPASS) - /* LSE Bypass.*/ - RCC->BDCR |= RCC_BDCR_LSEON | RCC_BDCR_LSEBYP; -#else - /* No LSE Bypass.*/ - RCC->BDCR |= RCC_BDCR_LSEON; -#endif - int waitCounter = 0; - while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0 && ++waitCounter BDCR & RCC_BDCR_RTCEN) == 0) { - /* Selects clock source.*/ - RCC->BDCR |= STM32_RTCSEL; - - /* RTC clock enabled.*/ - RCC->BDCR |= RCC_BDCR_RTCEN; - } -#endif /* HAL_USE_RTC */ - -#if STM32_BKPRAM_ENABLE - rccEnableBKPSRAM(false); - - PWR->CSR |= PWR_CSR_BRE; - while ((PWR->CSR & PWR_CSR_BRR) == 0) - ; /* Waits until the regulator is stable */ -#else - PWR->CSR &= ~PWR_CSR_BRE; -#endif /* STM32_BKPRAM_ENABLE */ -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level HAL driver initialization. - * - * @notapi - */ -void hal_lld_init(void) { - - /* Reset of all peripherals. AHB3 is not reseted because it could have - been initialized in the board initialization file (board.c).*/ - rccResetAHB1(~0); - rccResetAHB2(~0); - rccResetAPB1(~RCC_APB1RSTR_PWRRST); - rccResetAPB2(~0); - - /* SysTick initialization using the system clock.*/ - SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1; - SysTick->VAL = 0; - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk | - SysTick_CTRL_TICKINT_Msk; - - /* DWT cycle counter enable.*/ - SCS_DEMCR |= SCS_DEMCR_TRCENA; - DWT_CTRL |= DWT_CTRL_CYCCNTENA; - - /* PWR clock enabled.*/ - rccEnablePWRInterface(FALSE); - - /* Initializes the backup domain.*/ - hal_lld_backup_domain_init(); - -#if defined(STM32_DMA_REQUIRED) - dmaInit(); -#endif - - /* Programmable voltage detector enable.*/ -#if STM32_PVD_ENABLE - PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK); -#endif /* STM32_PVD_ENABLE */ -} - -/** - * @brief STM32F2xx clocks and PLL initialization. - * @note All the involved constants come from the file @p board.h. - * @note This function should be invoked just after the system reset. - * - * @special - */ -void stm32_clock_init(void) { - -#if !STM32_NO_INIT - /* PWR clock enable.*/ - RCC->APB1ENR = RCC_APB1ENR_PWREN; - - /* PWR initialization.*/ -#if defined(STM32F4XX) || defined(__DOXYGEN__) - PWR->CR = STM32_VOS; -#else - PWR->CR = 0; -#endif - - /* HSI setup, it enforces the reset situation in order to handle possible - problems with JTAG probes and re-initializations.*/ - RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */ - while (!(RCC->CR & RCC_CR_HSIRDY)) - ; /* Wait until HSI is stable. */ - - /* HSI is selected as new source without touching the other fields in - CFGR. Clearing the register has to be postponed after HSI is the - new source.*/ - RCC->CFGR &= ~RCC_CFGR_SW; /* Reset SW */ - RCC->CFGR |= RCC_CFGR_SWS_HSI; /* Select HSI as internal*/ - while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) - ; /* Wait until HSI is selected. */ - - /* Registers finally cleared to reset values.*/ - RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */ - RCC->CFGR = 0; /* CFGR reset value. */ - -#if STM32_HSE_ENABLED - /* HSE activation.*/ -#if defined(STM32_HSE_BYPASS) - /* HSE Bypass.*/ - RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP; -#else - /* No HSE Bypass.*/ - RCC->CR |= RCC_CR_HSEON; -#endif - while ((RCC->CR & RCC_CR_HSERDY) == 0) - ; /* Waits until HSE is stable. */ -#endif - -#if STM32_LSI_ENABLED - /* LSI activation.*/ - RCC->CSR |= RCC_CSR_LSION; - while ((RCC->CSR & RCC_CSR_LSIRDY) == 0) - ; /* Waits until LSI is stable. */ -#endif - -#if STM32_ACTIVATE_PLL - /* PLL activation.*/ - RCC->PLLCFGR = STM32_PLLQ | STM32_PLLSRC | STM32_PLLP | STM32_PLLN | - STM32_PLLM; - RCC->CR |= RCC_CR_PLLON; - - /* Synchronization with voltage regulator stabilization.*/ -#if defined(STM32F4XX) - while ((PWR->CSR & PWR_CSR_VOSRDY) == 0) - ; /* Waits until power regulator is stable. */ - -#if STM32_OVERDRIVE_REQUIRED - /* Overdrive activation performed after activating the PLL in order to save - time as recommended in RM in "Entering Over-drive mode" paragraph.*/ - PWR->CR |= PWR_CR_ODEN; - while (!(PWR->CSR & PWR_CSR_ODRDY)) - ; - PWR->CR |= PWR_CR_ODSWEN; - while (!(PWR->CSR & PWR_CSR_ODSWRDY)) - ; -#endif /* STM32_OVERDRIVE_REQUIRED */ -#endif /* defined(STM32F4XX) */ - - /* Waiting for PLL lock.*/ - while (!(RCC->CR & RCC_CR_PLLRDY)) - ; -#endif /* STM32_OVERDRIVE_REQUIRED */ - -#if STM32_ACTIVATE_PLLI2S - /* PLLI2S activation.*/ - RCC->PLLI2SCFGR = STM32_PLLI2SR | STM32_PLLI2SN; - RCC->CR |= RCC_CR_PLLI2SON; - - /* Waiting for PLL lock.*/ - while (!(RCC->CR & RCC_CR_PLLI2SRDY)) - ; -#endif - - /* Other clock-related settings (dividers, MCO etc).*/ - RCC->CFGR = STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL | - STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; - - /* Flash setup.*/ -#if defined(STM32_USE_REVISION_A_FIX) - /* Some old revisions of F4x MCUs randomly crashes with compiler - optimizations enabled AND flash caches enabled. */ - if ((DBGMCU->IDCODE == 0x20006411) && (SCB->CPUID == 0x410FC241)) - FLASH->ACR = FLASH_ACR_PRFTEN | STM32_FLASHBITS; - else - FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | - FLASH_ACR_DCEN | STM32_FLASHBITS; -#else - FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | - FLASH_ACR_DCEN | STM32_FLASHBITS; -#endif - - /* Switching to the configured clock source if it is different from MSI.*/ -#if (STM32_SW != STM32_SW_HSI) - RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */ - while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2)) - ; -#endif -#endif /* STM32_NO_INIT */ - - /* SYSCFG clock enabled here because it is a multi-functional unit shared - among multiple drivers.*/ - rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE); -} - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32F4xx/hal_lld.h b/firmware/chibios/os/hal/platforms/STM32F4xx/hal_lld.h deleted file mode 100644 index 9c6bde1be5..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F4xx/hal_lld.h +++ /dev/null @@ -1,1777 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F4xx/hal_lld.h - * @brief STM32F4xx/STM32F2xx HAL subsystem low level driver header. - * @pre This module requires the following macros to be defined in the - * @p board.h file: - * - STM32_LSECLK. - * - STM32_LSE_BYPASS (optionally). - * - STM32_HSECLK. - * - STM32_HSE_BYPASS (optionally). - * - STM32_VDD (as hundredths of Volt). - * . - * One of the following macros must also be defined: - * - STM32F2XX for High-performance STM32 F-2 devices. - * - STM32F401xx for High-performance STM32 F-4 devices. - * - STM32F40_41xxx for High-performance STM32 F-4 devices. - * - STM32F427_437xx for High-performance STM32 F-4 devices. - * - STM32F429_439xx for High-performance STM32 F-4 devices. - * . - * - * @addtogroup HAL - * @{ - */ - -#ifndef _HAL_LLD_H_ -#define _HAL_LLD_H_ - -#include "stm32.h" - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Defines the support for realtime counters in the HAL. - */ -#define HAL_IMPLEMENTS_COUNTERS TRUE - -/** - * @name Platform identification macros - * @{ - */ -#if defined(STM32F429_439xx) || defined(__DOXYGEN__) -#define PLATFORM_NAME "STM32F429/F439 High Performance with DSP and FPU" -#define STM32F4XX - -#elif defined(STM32F427_437xx) -#define PLATFORM_NAME "STM32F427/F437 High Performance with DSP and FPU" -#define STM32F4XX - -#elif defined(STM32F40_41xxx) -#define PLATFORM_NAME "STM32F407/F417 High Performance with DSP and FPU" -#define STM32F4XX - -#elif defined(STM32F401xx) -#define PLATFORM_NAME "STM32F401 High Performance with DSP and FPU" -#define STM32F4XX - -#elif defined(STM32F2XX) -#define PLATFORM_NAME "STM32F2xx High Performance" - -#else -#error "STM32F2xx/F4xx device not specified" -#endif -/** @} */ - -/** - * @name Absolute Maximum Ratings - * @{ - */ -/** - * @name Absolute Maximum Ratings - * @{ - */ -#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || \ - defined(__DOXYGEN__) -/** - * @brief Absolute maximum system clock. - */ -#define STM32_SYSCLK_MAX 180000000 - -/** - * @brief Maximum HSE clock frequency. - */ -#define STM32_HSECLK_MAX 26000000 - -/** - * @brief Maximum HSE clock frequency using an external source. - */ -#define STM32_HSECLK_BYP_MAX 50000000 - -/** - * @brief Minimum HSE clock frequency. - */ -#define STM32_HSECLK_MIN 4000000 - -/** - * @brief Minimum HSE clock frequency. - */ -#define STM32_HSECLK_BYP_MIN 1000000 - -/** - * @brief Maximum LSE clock frequency. - */ -#define STM32_LSECLK_MAX 32768 - -/** - * @brief Maximum LSE clock frequency. - */ -#define STM32_LSECLK_BYP_MAX 1000000 - -/** - * @brief Minimum LSE clock frequency. - */ -#define STM32_LSECLK_MIN 32768 - -/** - * @brief Maximum PLLs input clock frequency. - */ -#define STM32_PLLIN_MAX 2100000 - -/** - * @brief Minimum PLLs input clock frequency. - */ -#define STM32_PLLIN_MIN 950000 - -/** - * @brief Maximum PLLs VCO clock frequency. - */ -#define STM32_PLLVCO_MAX 432000000 - -/** - * @brief Maximum PLLs VCO clock frequency. - */ -#define STM32_PLLVCO_MIN 192000000 - -/** - * @brief Maximum PLL output clock frequency. - */ -#define STM32_PLLOUT_MAX 180000000 - -/** - * @brief Minimum PLL output clock frequency. - */ -#define STM32_PLLOUT_MIN 24000000 - -/** - * @brief Maximum APB1 clock frequency. - */ -#define STM32_PCLK1_MAX (STM32_PLLOUT_MAX /4) - -/** - * @brief Maximum APB2 clock frequency. - */ -#define STM32_PCLK2_MAX (STM32_PLLOUT_MAX / 2) - -/** - * @brief Maximum SPI/I2S clock frequency. - */ -#define STM32_SPII2S_MAX 45000000 -#endif /* STM32F40_41xxx */ - -#if defined(STM32F40_41xxx) || defined(__DOXYGEN__) -#define STM32_SYSCLK_MAX 168000000 -#define STM32_HSECLK_MAX 26000000 -#define STM32_HSECLK_BYP_MAX 50000000 -#define STM32_HSECLK_MIN 4000000 -#define STM32_HSECLK_BYP_MIN 1000000 -#define STM32_LSECLK_MAX 32768 -#define STM32_LSECLK_BYP_MAX 1000000 -#define STM32_LSECLK_MIN 32768 -#define STM32_PLLIN_MAX 2100000 -#define STM32_PLLIN_MIN 950000 -#define STM32_PLLVCO_MAX 432000000 -#define STM32_PLLVCO_MIN 192000000 -#define STM32_PLLOUT_MAX 168000000 -#define STM32_PLLOUT_MIN 24000000 -#define STM32_PCLK1_MAX 42000000 -#define STM32_PCLK2_MAX 84000000 -#define STM32_SPII2S_MAX 42000000 -#endif /* STM32F40_41xxx */ - -#if defined(STM32F401xx) || defined(__DOXYGEN__) -#define STM32_SYSCLK_MAX 84000000 -#define STM32_HSECLK_MAX 26000000 -#define STM32_HSECLK_BYP_MAX 50000000 -#define STM32_HSECLK_MIN 4000000 -#define STM32_HSECLK_BYP_MIN 1000000 -#define STM32_LSECLK_MAX 32768 -#define STM32_LSECLK_BYP_MAX 1000000 -#define STM32_LSECLK_MIN 32768 -#define STM32_PLLIN_MAX 2100000 -#define STM32_PLLIN_MIN 950000 -#define STM32_PLLVCO_MAX 432000000 -#define STM32_PLLVCO_MIN 192000000 -#define STM32_PLLOUT_MAX 84000000 -#define STM32_PLLOUT_MIN 24000000 -#define STM32_PCLK1_MAX 42000000 -#define STM32_PCLK2_MAX 84000000 -#define STM32_SPII2S_MAX 42000000 -#endif /* STM32F40_41xxx */ - -#if defined(STM32F2XX) -#define STM32_SYSCLK_MAX 120000000 -#define STM32_HSECLK_MAX 26000000 -#define STM32_HSECLK_BYP_MAX 26000000 -#define STM32_HSECLK_MIN 1000000 -#define STM32_HSECLK_BYP_MIN 1000000 -#define STM32_LSECLK_MAX 32768 -#define STM32_LSECLK_BYP_MAX 1000000 -#define STM32_LSECLK_MIN 32768 -#define STM32_PLLIN_MAX 2000000 -#define STM32_PLLIN_MIN 950000 -#define STM32_PLLVCO_MAX 432000000 -#define STM32_PLLVCO_MIN 192000000 -#define STM32_PLLOUT_MAX 120000000 -#define STM32_PLLOUT_MIN 24000000 -#define STM32_PCLK1_MAX 30000000 -#define STM32_PCLK2_MAX 60000000 -#define STM32_SPII2S_MAX 30000000 -#endif /* defined(STM32F2XX) */ -/** @} */ - -/** - * @name Internal clock sources - * @{ - */ -#define STM32_HSICLK 16000000 /**< High speed internal clock. */ -#define STM32_LSICLK 32000 /**< Low speed internal clock. */ -/** @} */ - -/** - * @name PWR_CR register bits definitions - * @{ - */ -#define STM32_VOS_SCALE3 (PWR_CR_VOS_0) -#define STM32_VOS_SCALE2 (PWR_CR_VOS_1) -#define STM32_VOS_SCALE1 (PWR_CR_VOS_1 | PWR_CR_VOS_0) -#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */ -#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */ -#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */ -#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 2. */ -#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 3. */ -#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 4. */ -#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 5. */ -#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 6. */ -#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 7. */ -/** @} */ - -/** - * @name RCC_PLLCFGR register bits definitions - * @{ - */ -#define STM32_PLLP_MASK (3 << 16) /**< PLLP mask. */ -#define STM32_PLLP_DIV2 (0 << 16) /**< PLL clock divided by 2. */ -#define STM32_PLLP_DIV4 (1 << 16) /**< PLL clock divided by 4. */ -#define STM32_PLLP_DIV6 (2 << 16) /**< PLL clock divided by 6. */ -#define STM32_PLLP_DIV8 (3 << 16) /**< PLL clock divided by 8. */ - -#define STM32_PLLSRC_HSI (0 << 22) /**< PLL clock source is HSI. */ -#define STM32_PLLSRC_HSE (1 << 22) /**< PLL clock source is HSE. */ -/** @} */ - -/** - * @name RCC_CFGR register bits definitions - * @{ - */ -#define STM32_SW_MASK (3 << 0) /**< SW mask. */ -#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */ -#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */ -#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */ - -#define STM32_HPRE_MASK (15 << 4) /**< HPRE mask. */ -#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */ -#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */ -#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */ -#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */ -#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */ -#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */ -#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */ -#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */ -#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */ - -#define STM32_PPRE1_MASK (7 << 10) /**< PPRE1 mask. */ -#define STM32_PPRE1_DIV1 (0 << 10) /**< HCLK divided by 1. */ -#define STM32_PPRE1_DIV2 (4 << 10) /**< HCLK divided by 2. */ -#define STM32_PPRE1_DIV4 (5 << 10) /**< HCLK divided by 4. */ -#define STM32_PPRE1_DIV8 (6 << 10) /**< HCLK divided by 8. */ -#define STM32_PPRE1_DIV16 (7 << 10) /**< HCLK divided by 16. */ - -#define STM32_PPRE2_MASK (7 << 13) /**< PPRE2 mask. */ -#define STM32_PPRE2_DIV1 (0 << 13) /**< HCLK divided by 1. */ -#define STM32_PPRE2_DIV2 (4 << 13) /**< HCLK divided by 2. */ -#define STM32_PPRE2_DIV4 (5 << 13) /**< HCLK divided by 4. */ -#define STM32_PPRE2_DIV8 (6 << 13) /**< HCLK divided by 8. */ -#define STM32_PPRE2_DIV16 (7 << 13) /**< HCLK divided by 16. */ - -#define STM32_RTCPRE_MASK (31 << 16) /**< RTCPRE mask. */ - -#define STM32_MCO1SEL_MASK (3 << 21) /**< MCO1 mask. */ -#define STM32_MCO1SEL_HSI (0 << 21) /**< HSI clock on MCO1 pin. */ -#define STM32_MCO1SEL_LSE (1 << 21) /**< LSE clock on MCO1 pin. */ -#define STM32_MCO1SEL_HSE (2 << 21) /**< HSE clock on MCO1 pin. */ -#define STM32_MCO1SEL_PLL (3 << 21) /**< PLL clock on MCO1 pin. */ - -#define STM32_I2SSRC_MASK (1 << 23) /**< I2CSRC mask. */ -#define STM32_I2SSRC_PLLI2S (0 << 23) /**< I2SSRC is PLLI2S. */ -#define STM32_I2SSRC_CKIN (1 << 23) /**< I2S_CKIN is PLLI2S. */ - -#define STM32_MCO1PRE_MASK (7 << 24) /**< MCO1PRE mask. */ -#define STM32_MCO1PRE_DIV1 (0 << 24) /**< MCO1 divided by 1. */ -#define STM32_MCO1PRE_DIV2 (4 << 24) /**< MCO1 divided by 2. */ -#define STM32_MCO1PRE_DIV3 (5 << 24) /**< MCO1 divided by 3. */ -#define STM32_MCO1PRE_DIV4 (6 << 24) /**< MCO1 divided by 4. */ -#define STM32_MCO1PRE_DIV5 (7 << 24) /**< MCO1 divided by 5. */ - -#define STM32_MCO2PRE_MASK (7 << 27) /**< MCO2PRE mask. */ -#define STM32_MCO2PRE_DIV1 (0 << 27) /**< MCO2 divided by 1. */ -#define STM32_MCO2PRE_DIV2 (4 << 27) /**< MCO2 divided by 2. */ -#define STM32_MCO2PRE_DIV3 (5 << 27) /**< MCO2 divided by 3. */ -#define STM32_MCO2PRE_DIV4 (6 << 27) /**< MCO2 divided by 4. */ -#define STM32_MCO2PRE_DIV5 (7 << 27) /**< MCO2 divided by 5. */ - -#define STM32_MCO2SEL_MASK (3U << 30) /**< MCO2 mask. */ -#define STM32_MCO2SEL_SYSCLK (0U << 30) /**< SYSCLK clock on MCO2 pin. */ -#define STM32_MCO2SEL_PLLI2S (1U << 30) /**< PLLI2S clock on MCO2 pin. */ -#define STM32_MCO2SEL_HSE (2U << 30) /**< HSE clock on MCO2 pin. */ -#define STM32_MCO2SEL_PLL (3U << 30) /**< PLL clock on MCO2 pin. */ - -#define STM32_RTC_NOCLOCK (0 << 8) /**< No clock. */ -#define STM32_RTC_LSE (1 << 8) /**< LSE used as RTC clock. */ -#define STM32_RTC_LSI (2 << 8) /**< LSI used as RTC clock. */ -#define STM32_RTC_HSE (3 << 8) /**< HSE divided by programmable - prescaler used as RTC clock*/ - -/** - * @name RCC_PLLI2SCFGR register bits definitions - * @{ - */ -#define STM32_PLLI2SN_MASK (511 << 6) /**< PLLI2SN mask. */ -#define STM32_PLLI2SR_MASK (7 << 28) /**< PLLI2SR mask. */ -/** @} */ - -/** - * @name RCC_BDCR register bits definitions - * @{ - */ -#define STM32_RTCSEL_MASK (3 << 8) /**< RTC source mask. */ -#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No RTC source. */ -#define STM32_RTCSEL_LSE (1 << 8) /**< RTC source is LSE. */ -#define STM32_RTCSEL_LSI (2 << 8) /**< RTC source is LSI. */ -#define STM32_RTCSEL_HSEDIV (3 << 8) /**< RTC source is HSE divided. */ -/** @} */ - -/*===========================================================================*/ -/* Platform capabilities. */ -/*===========================================================================*/ - -/** - * @name STM32F4xx capabilities - * @{ - */ -/* ADC attributes.*/ -#define STM32_HAS_ADC1 TRUE -#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) | \ - STM32_DMA_STREAM_ID_MSK(2, 4)) -#define STM32_ADC1_DMA_CHN 0x00000000 - -#define STM32_HAS_ADC2 TRUE -#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) | \ - STM32_DMA_STREAM_ID_MSK(2, 3)) -#define STM32_ADC2_DMA_CHN 0x00001100 - -#define STM32_HAS_ADC3 TRUE -#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) | \ - STM32_DMA_STREAM_ID_MSK(2, 1)) -#define STM32_ADC3_DMA_CHN 0x00000022 - -#define STM32_HAS_ADC4 FALSE -#define STM32_ADC4_DMA_MSK 0x00000000 -#define STM32_ADC4_DMA_CHN 0x00000000 - -/* CAN attributes.*/ -#define STM32_HAS_CAN1 TRUE -#define STM32_HAS_CAN2 TRUE -#define STM32_CAN_MAX_FILTERS 28 - -/* DAC attributes.*/ -#define STM32_HAS_DAC FALSE - -/* DMA attributes.*/ -#define STM32_ADVANCED_DMA TRUE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 TRUE - -/* ETH attributes.*/ -#if !defined(STM32F401xx) -#define STM32_HAS_ETH TRUE -#else /* defined(STM32F401xx) */ -#define STM32_HAS_ETH FALSE -#endif /* defined(STM32F401xx) */ - -/* EXTI attributes.*/ -#define STM32_EXTI_NUM_CHANNELS 23 - -/* GPIO attributes.*/ -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE TRUE -#define STM32_HAS_GPIOH TRUE -#if !defined(STM32F401xx) -#define STM32_HAS_GPIOF TRUE -#define STM32_HAS_GPIOG TRUE -#define STM32_HAS_GPIOI TRUE -#else /* defined(STM32F401xx) */ -#define STM32_HAS_GPIOF FALSE -#define STM32_HAS_GPIOG FALSE -#define STM32_HAS_GPIOI FALSE -#endif /* defined(STM32F401xx) */ - -/* I2C attributes.*/ -#define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) | \ - STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_I2C1_RX_DMA_CHN 0x00100001 -#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) | \ - STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_I2C1_TX_DMA_CHN 0x11000000 - -#define STM32_HAS_I2C2 TRUE -#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) | \ - STM32_DMA_STREAM_ID_MSK(1, 3)) -#define STM32_I2C2_RX_DMA_CHN 0x00007700 -#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_I2C2_TX_DMA_CHN 0x70000000 - -#define STM32_HAS_I2C3 TRUE -#define STM32_I2C3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) -#define STM32_I2C3_RX_DMA_CHN 0x00000300 -#define STM32_I2C3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_I2C3_TX_DMA_CHN 0x00030000 - -/* RTC attributes.*/ -#define STM32_HAS_RTC TRUE -#if defined(STM32F4XX) || defined(__DOXYGEN__) -#define STM32_RTC_HAS_SUBSECONDS TRUE -#else -#define STM32_RTC_HAS_SUBSECONDS FALSE -#endif -#define STM32_RTC_IS_CALENDAR TRUE - -/* SDIO attributes.*/ -#define STM32_HAS_SDIO TRUE -#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) | \ - STM32_DMA_STREAM_ID_MSK(2, 6)) -#define STM32_SDC_SDIO_DMA_CHN 0x04004000 - -/* SPI attributes.*/ -#define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) | \ - STM32_DMA_STREAM_ID_MSK(2, 2)) -#define STM32_SPI1_RX_DMA_CHN 0x00000303 -#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) | \ - STM32_DMA_STREAM_ID_MSK(2, 5)) -#define STM32_SPI1_TX_DMA_CHN 0x00303000 - -#define STM32_HAS_SPI2 TRUE -#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) -#define STM32_SPI2_RX_DMA_CHN 0x00000000 -#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_SPI2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI3 TRUE -#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) | \ - STM32_DMA_STREAM_ID_MSK(1, 2)) -#define STM32_SPI3_RX_DMA_CHN 0x00000000 -#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) | \ - STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_SPI3_TX_DMA_CHN 0x00000000 - -#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || \ - defined(STM32F401xx) -#define STM32_HAS_SPI4 TRUE -#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) | \ - STM32_DMA_STREAM_ID_MSK(2, 3)) -#define STM32_SPI4_RX_DMA_CHN 0x00005004 -#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) | \ - STM32_DMA_STREAM_ID_MSK(2, 4)) -#define STM32_SPI4_TX_DMA_CHN 0x00050040 -#else -#define STM32_HAS_SPI4 FALSE -#endif - -#if defined(STM32F427_437xx) || defined(STM32F429_439xx) -#define STM32_HAS_SPI5 TRUE -#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) | \ - STM32_DMA_STREAM_ID_MSK(2, 5)) -#define STM32_SPI5_RX_DMA_CHN 0x00702000 -#define STM32_SPI5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) | \ - STM32_DMA_STREAM_ID_MSK(2, 6)) -#define STM32_SPI5_TX_DMA_CHN 0x07020000 - -#define STM32_HAS_SPI6 TRUE -#define STM32_SPI6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6)) -#define STM32_SPI6_RX_DMA_CHN 0x01000000 -#define STM32_SPI6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5)) -#define STM32_SPI6_TX_DMA_CHN 0x00100000 - -#else /* !(defined(STM32F427_437xx) || defined(STM32F429_439xx)) */ -#define STM32_HAS_SPI5 FALSE -#define STM32_HAS_SPI6 FALSE -#endif /* !(defined(STM32F427_437xx) || defined(STM32F429_439xx)) */ - -/* TIM attributes.*/ -#define STM32_HAS_TIM1 TRUE -#define STM32_HAS_TIM2 TRUE -#define STM32_HAS_TIM3 TRUE -#define STM32_HAS_TIM4 TRUE -#define STM32_HAS_TIM5 TRUE -#if !defined(STM32F401xx) -#define STM32_HAS_TIM6 TRUE -#define STM32_HAS_TIM7 TRUE -#define STM32_HAS_TIM8 TRUE -#else /* defined(STM32F401xx) */ -#define STM32_HAS_TIM6 FALSE -#define STM32_HAS_TIM7 FALSE -#define STM32_HAS_TIM8 FALSE -#endif /* defined(STM32F401xx) */ -#define STM32_HAS_TIM9 TRUE -#define STM32_HAS_TIM10 TRUE -#define STM32_HAS_TIM11 TRUE -#if !defined(STM32F401xx) -#define STM32_HAS_TIM12 TRUE -#define STM32_HAS_TIM13 TRUE -#define STM32_HAS_TIM14 TRUE -#else /* defined(STM32F401xx) */ -#define STM32_HAS_TIM12 FALSE -#define STM32_HAS_TIM13 FALSE -#define STM32_HAS_TIM14 FALSE -#endif /* defined(STM32F401xx) */ -#define STM32_HAS_TIM15 FALSE -#define STM32_HAS_TIM16 FALSE -#define STM32_HAS_TIM17 FALSE -#define STM32_HAS_TIM18 FALSE -#define STM32_HAS_TIM19 FALSE - -/* USART attributes.*/ -#define STM32_HAS_USART1 TRUE -#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) | \ - STM32_DMA_STREAM_ID_MSK(2, 5)) -#define STM32_USART1_RX_DMA_CHN 0x00400400 -#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 7)) -#define STM32_USART1_TX_DMA_CHN 0x40000000 - -#define STM32_HAS_USART2 TRUE -#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_USART2_RX_DMA_CHN 0x00400000 -#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_USART2_TX_DMA_CHN 0x04000000 - -#if !defined(STM32F401xx) -#define STM32_HAS_USART3 TRUE -#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1)) -#define STM32_USART3_RX_DMA_CHN 0x00000040 -#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) | \ - STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_USART3_TX_DMA_CHN 0x00074000 - -#define STM32_HAS_UART4 TRUE -#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) -#define STM32_UART4_RX_DMA_CHN 0x00000400 -#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_UART4_TX_DMA_CHN 0x00040000 - -#define STM32_HAS_UART5 TRUE -#define STM32_UART5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0)) -#define STM32_UART5_RX_DMA_CHN 0x00000004 -#define STM32_UART5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_UART5_TX_DMA_CHN 0x40000000 - -#else /* defined(STM32F401xx) */ -#define STM32_HAS_USART3 FALSE -#define STM32_HAS_UART4 FALSE -#define STM32_HAS_UART5 FALSE -#endif /* defined(STM32F401xx) */ - -#define STM32_HAS_USART6 TRUE -#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) | \ - STM32_DMA_STREAM_ID_MSK(2, 2)) -#define STM32_USART6_RX_DMA_CHN 0x00000550 -#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) | \ - STM32_DMA_STREAM_ID_MSK(2, 7)) -#define STM32_USART6_TX_DMA_CHN 0x55000000 - -/* USB attributes.*/ -#define STM32_HAS_USB FALSE -#define STM32_HAS_OTG1 TRUE -#if !defined(STM32F401xx) -#define STM32_HAS_OTG2 TRUE -#else /* defined(STM32F401xx) */ -#define STM32_HAS_OTG2 FALSE -#endif /* defined(STM32F401xx) */ -/** @} */ - -/*===========================================================================*/ -/* Platform specific friendly IRQ names. */ -/*===========================================================================*/ - -/** - * @name IRQ VECTOR names - * @{ - */ -#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */ -#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line - detect. */ -#define TAMP_STAMP_IRQHandler Vector48 /**< Tamper and TimeStamp - through EXTI Line. */ -#define RTC_WKUP_IRQHandler Vector4C /**< RTC wakeup EXTI Line. */ -#define FLASH_IRQHandler Vector50 /**< Flash. */ -#define RCC_IRQHandler Vector54 /**< RCC. */ -#define EXTI0_IRQHandler Vector58 /**< EXTI Line 0. */ -#define EXTI1_IRQHandler Vector5C /**< EXTI Line 1. */ -#define EXTI2_IRQHandler Vector60 /**< EXTI Line 2. */ -#define EXTI3_IRQHandler Vector64 /**< EXTI Line 3. */ -#define EXTI4_IRQHandler Vector68 /**< EXTI Line 4. */ -#define DMA1_Stream0_IRQHandler Vector6C /**< DMA1 Stream 0. */ -#define DMA1_Stream1_IRQHandler Vector70 /**< DMA1 Stream 1. */ -#define DMA1_Stream2_IRQHandler Vector74 /**< DMA1 Stream 2. */ -#define DMA1_Stream3_IRQHandler Vector78 /**< DMA1 Stream 3. */ -#define DMA1_Stream4_IRQHandler Vector7C /**< DMA1 Stream 4. */ -#define DMA1_Stream5_IRQHandler Vector80 /**< DMA1 Stream 5. */ -#define DMA1_Stream6_IRQHandler Vector84 /**< DMA1 Stream 6. */ -#define ADC1_2_3_IRQHandler Vector88 /**< ADC1, ADC2 and ADC3. */ -#define CAN1_TX_IRQHandler Vector8C /**< CAN1 TX. */ -#define CAN1_RX0_IRQHandler Vector90 /**< CAN1 RX0. */ -#define CAN1_RX1_IRQHandler Vector94 /**< CAN1 RX1. */ -#define CAN1_SCE_IRQHandler Vector98 /**< CAN1 SCE. */ -#define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */ -#define TIM1_BRK_IRQHandler VectorA0 /**< TIM1 Break. */ -#define TIM1_UP_IRQHandler VectorA4 /**< TIM1 Update. */ -#define TIM1_TRG_COM_IRQHandler VectorA8 /**< TIM1 Trigger and - Commutation. */ -#define TIM1_CC_IRQHandler VectorAC /**< TIM1 Capture Compare. */ -#define TIM2_IRQHandler VectorB0 /**< TIM2. */ -#define TIM3_IRQHandler VectorB4 /**< TIM3. */ -#define TIM4_IRQHandler VectorB8 /**< TIM4. */ -#define I2C1_EV_IRQHandler VectorBC /**< I2C1 Event. */ -#define I2C1_ER_IRQHandler VectorC0 /**< I2C1 Error. */ -#define I2C2_EV_IRQHandler VectorC4 /**< I2C2 Event. */ -#define I2C2_ER_IRQHandler VectorC8 /**< I2C1 Error. */ -#define SPI1_IRQHandler VectorCC /**< SPI1. */ -#define SPI2_IRQHandler VectorD0 /**< SPI2. */ -#define USART1_IRQHandler VectorD4 /**< USART1. */ -#define USART2_IRQHandler VectorD8 /**< USART2. */ -#define USART3_IRQHandler VectorDC /**< USART3. */ -#define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */ -#define RTC_Alarm_IRQHandler VectorE4 /**< RTC alarms (A and B) - through EXTI line. */ -#define OTG_FS_WKUP_IRQHandler VectorE8 /**< USB OTG FS Wakeup through - EXTI line. */ -#define TIM8_BRK_IRQHandler VectorEC /**< TIM8 Break. */ -#define TIM8_UP_IRQHandler VectorF0 /**< TIM8 Update. */ -#define TIM8_TRG_COM_IRQHandler VectorF4 /**< TIM8 Trigger and - Commutation. */ -#define TIM8_CC_IRQHandler VectorF8 /**< TIM8 Capture Compare. */ -#define DMA1_Stream7_IRQHandler VectorFC /**< DMA1 Stream 7. */ -#define FSMC_IRQHandler Vector100 /**< FSMC. */ -#define SDIO_IRQHandler Vector104 /**< SDIO. */ -#define TIM5_IRQHandler Vector108 /**< TIM5. */ -#define SPI3_IRQHandler Vector10C /**< SPI3. */ -#define UART4_IRQHandler Vector110 /**< UART4. */ -#define UART5_IRQHandler Vector114 /**< UART5. */ -#define TIM6_IRQHandler Vector118 /**< TIM6. */ -#define TIM7_IRQHandler Vector11C /**< TIM7. */ -#define DMA2_Stream0_IRQHandler Vector120 /**< DMA2 Stream0. */ -#define DMA2_Stream1_IRQHandler Vector124 /**< DMA2 Stream1. */ -#define DMA2_Stream2_IRQHandler Vector128 /**< DMA2 Stream2. */ -#define DMA2_Stream3_IRQHandler Vector12C /**< DMA2 Stream3. */ -#define DMA2_Stream4_IRQHandler Vector130 /**< DMA2 Stream4. */ -#define ETH_IRQHandler Vector134 /**< Ethernet. */ -#define ETH_WKUP_IRQHandler Vector138 /**< Ethernet Wakeup through - EXTI line. */ -#define CAN2_TX_IRQHandler Vector13C /**< CAN2 TX. */ -#define CAN2_RX0_IRQHandler Vector140 /**< CAN2 RX0. */ -#define CAN2_RX1_IRQHandler Vector144 /**< CAN2 RX1. */ -#define CAN2_SCE_IRQHandler Vector148 /**< CAN2 SCE. */ -#define OTG_FS_IRQHandler Vector14C /**< USB OTG FS. */ -#define DMA2_Stream5_IRQHandler Vector150 /**< DMA2 Stream5. */ -#define DMA2_Stream6_IRQHandler Vector154 /**< DMA2 Stream6. */ -#define DMA2_Stream7_IRQHandler Vector158 /**< DMA2 Stream7. */ -#define USART6_IRQHandler Vector15C /**< USART6. */ -#define I2C3_EV_IRQHandler Vector160 /**< I2C3 Event. */ -#define I2C3_ER_IRQHandler Vector164 /**< I2C3 Error. */ -#define OTG_HS_EP1_OUT_IRQHandler Vector168 /**< USB OTG HS End Point 1 Out.*/ -#define OTG_HS_EP1_IN_IRQHandler Vector16C /**< USB OTG HS End Point 1 In. */ -#define OTG_HS_WKUP_IRQHandler Vector170 /**< USB OTG HS Wakeup through - EXTI line. */ -#define OTG_HS_IRQHandler Vector174 /**< USB OTG HS. */ -#define DCMI_IRQHandler Vector178 /**< DCMI. */ -#define CRYP_IRQHandler Vector17C /**< CRYP. */ -#define HASH_RNG_IRQHandler Vector180 /**< Hash and Rng. */ -#if defined(STM32F4XX) || defined(__DOXYGEN__) -#define FPU_IRQHandler Vector184 /**< Floating Point Unit. */ -#endif -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief Disables the PWR/RCC initialization in the HAL. - */ -#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__) -#define STM32_NO_INIT FALSE -#endif - -/** - * @brief Enables or disables the programmable voltage detector. - */ -#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__) -#define STM32_PVD_ENABLE FALSE -#endif - -/** - * @brief Sets voltage level for programmable voltage detector. - */ -#if !defined(STM32_PLS) || defined(__DOXYGEN__) -#define STM32_PLS STM32_PLS_LEV0 -#endif - -/** - * @brief Enables the backup RAM regulator. - */ -#if !defined(STM32_BKPRAM_ENABLE) || defined(__DOXYGEN__) -#define STM32_BKPRAM_ENABLE FALSE -#endif - -/** - * @brief Enables or disables the HSI clock source. - */ -#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__) -#define STM32_HSI_ENABLED TRUE -#endif - -/** - * @brief Enables or disables the LSI clock source. - */ -#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__) -#define STM32_LSI_ENABLED FALSE -#endif - -/** - * @brief Enables or disables the HSE clock source. - */ -#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__) -#define STM32_HSE_ENABLED TRUE -#endif - -/** - * @brief Enables or disables the LSE clock source. - */ -#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__) -#define STM32_LSE_ENABLED FALSE -#endif - -/** - * @brief USB/SDIO clock setting. - */ -#if !defined(STM32_CLOCK48_REQUIRED) || defined(__DOXYGEN__) -#define STM32_CLOCK48_REQUIRED TRUE -#endif - -/** - * @brief Main clock source selection. - * @note If the selected clock source is not the PLL then the PLL is not - * initialized and started. - * @note The default value is calculated for a 168MHz system clock from - * an external 8MHz HSE clock. - */ -#if !defined(STM32_SW) || defined(__DOXYGEN__) -#define STM32_SW STM32_SW_PLL -#endif - -#if defined(STM32F4XX) || defined(__DOXYGEN__) -/** - * @brief Clock source for the PLLs. - * @note This setting has only effect if the PLL is selected as the - * system clock source. - * @note The default value is calculated for a 168MHz system clock from - * an external 8MHz HSE clock. - */ -#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__) -#define STM32_PLLSRC STM32_PLLSRC_HSE -#endif - -/** - * @brief PLLM divider value. - * @note The allowed values are 2..63. - * @note The default value is calculated for a 168MHz system clock from - * an external 8MHz HSE clock. - */ -#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLM_VALUE 8 -#endif - -/** - * @brief PLLN multiplier value. - * @note The allowed values are 192..432. - * @note The default value is calculated for a 168MHz system clock from - * an external 8MHz HSE clock. - */ -#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLN_VALUE 336 -#endif - -/** - * @brief PLLP divider value. - * @note The allowed values are 2, 4, 6, 8. - * @note The default value is calculated for a 168MHz system clock from - * an external 8MHz HSE clock. - */ -#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLP_VALUE 2 -#endif - -/** - * @brief PLLQ multiplier value. - * @note The allowed values are 2..15. - * @note The default value is calculated for a 168MHz system clock from - * an external 8MHz HSE clock. - */ -#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLQ_VALUE 7 -#endif - -#else /* !defined(STM32F4XX) */ -/** - * @brief Clock source for the PLLs. - * @note This setting has only effect if the PLL is selected as the - * system clock source. - * @note The default value is calculated for a 120MHz system clock from - * an external 8MHz HSE clock. - */ -#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__) -#define STM32_PLLSRC STM32_PLLSRC_HSE -#endif - -/** - * @brief PLLM divider value. - * @note The allowed values are 2..63. - * @note The default value is calculated for a 120MHz system clock from - * an external 8MHz HSE clock. - */ -#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLM_VALUE 8 -#endif - -/** - * @brief PLLN multiplier value. - * @note The allowed values are 192..432. - * @note The default value is calculated for a 120MHz system clock from - * an external 8MHz HSE clock. - */ -#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLN_VALUE 240 -#endif - -/** - * @brief PLLP divider value. - * @note The allowed values are 2, 4, 6, 8. - * @note The default value is calculated for a 120MHz system clock from - * an external 8MHz HSE clock. - */ -#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLP_VALUE 2 -#endif - -/** - * @brief PLLQ multiplier value. - * @note The allowed values are 2..15. - * @note The default value is calculated for a 120MHz system clock from - * an external 8MHz HSE clock. - */ -#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLQ_VALUE 5 -#endif -#endif /* !defined(STM32F4XX) */ - -/** - * @brief AHB prescaler value. - */ -#if !defined(STM32_HPRE) || defined(__DOXYGEN__) -#define STM32_HPRE STM32_HPRE_DIV1 -#endif - -/** - * @brief APB1 prescaler value. - */ -#if !defined(STM32_PPRE1) || defined(__DOXYGEN__) -#define STM32_PPRE1 STM32_PPRE1_DIV4 -#endif - -/** - * @brief APB2 prescaler value. - */ -#if !defined(STM32_PPRE2) || defined(__DOXYGEN__) -#define STM32_PPRE2 STM32_PPRE2_DIV2 -#endif - -/** - * @brief RTC clock source. - */ -#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__) -#define STM32_RTCSEL STM32_RTCSEL_LSE -#endif - -/** - * @brief RTC HSE prescaler value. - */ -#if !defined(STM32_RTCPRE_VALUE) || defined(__DOXYGEN__) -#define STM32_RTCPRE_VALUE 8 -#endif - -/** - * @brief MC01 clock source value. - * @note The default value outputs HSI clock on MC01 pin. - */ -#if !defined(STM32_MCO1SEL) || defined(__DOXYGEN__) -#define STM32_MCO1SEL STM32_MCO1SEL_HSI -#endif - -/** - * @brief MC01 prescaler value. - * @note The default value outputs HSI clock on MC01 pin. - */ -#if !defined(STM32_MCO1PRE) || defined(__DOXYGEN__) -#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 -#endif - -/** - * @brief MC02 clock source value. - * @note The default value outputs SYSCLK / 5 on MC02 pin. - */ -#if !defined(STM32_MCO2SEL) || defined(__DOXYGEN__) -#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK -#endif - -/** - * @brief MC02 prescaler value. - * @note The default value outputs SYSCLK / 5 on MC02 pin. - */ -#if !defined(STM32_MCO2PRE) || defined(__DOXYGEN__) -#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 -#endif - -/** - * @brief I2S clock source. - */ -#if !defined(STM32_I2SSRC) || defined(__DOXYGEN__) -#define STM32_I2SSRC STM32_I2SSRC_CKIN -#endif - -/** - * @brief PLLI2SN multiplier value. - * @note The allowed values are 192..432. - */ -#if !defined(STM32_PLLI2SN_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLI2SN_VALUE 192 -#endif - -/** - * @brief PLLI2SR multiplier value. - * @note The allowed values are 2..7. - */ -#if !defined(STM32_PLLI2SR_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLI2SR_VALUE 5 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if defined(STM32F4XX) || defined(__DOXYGEN__) -/* - * Configuration-related checks. - */ -#if !defined(STM32F4xx_MCUCONF) -#error "Using a wrong mcuconf.h file, STM32F4xx_MCUCONF not defined" -#endif - -#else /* !defined(STM32F4XX) */ -/* - * Configuration-related checks. - */ -#if !defined(STM32F2xx_MCUCONF) -#error "Using a wrong mcuconf.h file, STM32F2xx_MCUCONF not defined" -#endif -#endif /* !defined(STM32F4XX) */ - -/** - * @brief Maximum frequency thresholds and wait states for flash access. - * @note The values are valid for 2.7V to 3.6V supply range. - */ -#if defined(STM32F429_439xx) || defined(STM32F427_437xx) || \ - defined(STM32F40_41xxx) || defined(__DOXYGEN__) -#if ((STM32_VDD >= 270) && (STM32_VDD <= 360)) || defined(__DOXYGEN__) -#define STM32_0WS_THRESHOLD 30000000 -#define STM32_1WS_THRESHOLD 60000000 -#define STM32_2WS_THRESHOLD 90000000 -#define STM32_3WS_THRESHOLD 120000000 -#define STM32_4WS_THRESHOLD 150000000 -#define STM32_5WS_THRESHOLD 180000000 -#define STM32_6WS_THRESHOLD 0 -#define STM32_7WS_THRESHOLD 0 -#define STM32_8WS_THRESHOLD 0 -#elif (STM32_VDD >= 240) && (STM32_VDD < 270) -#define STM32_0WS_THRESHOLD 24000000 -#define STM32_1WS_THRESHOLD 48000000 -#define STM32_2WS_THRESHOLD 72000000 -#define STM32_3WS_THRESHOLD 96000000 -#define STM32_4WS_THRESHOLD 120000000 -#define STM32_5WS_THRESHOLD 144000000 -#define STM32_6WS_THRESHOLD 168000000 -#define STM32_7WS_THRESHOLD 180000000 -#define STM32_8WS_THRESHOLD 0 -#elif (STM32_VDD >= 210) && (STM32_VDD < 240) -#define STM32_0WS_THRESHOLD 22000000 -#define STM32_1WS_THRESHOLD 44000000 -#define STM32_2WS_THRESHOLD 66000000 -#define STM32_3WS_THRESHOLD 88000000 -#define STM32_4WS_THRESHOLD 110000000 -#define STM32_5WS_THRESHOLD 132000000 -#define STM32_6WS_THRESHOLD 154000000 -#define STM32_7WS_THRESHOLD 176000000 -#define STM32_8WS_THRESHOLD 180000000 -#elif (STM32_VDD >= 180) && (STM32_VDD < 210) -#define STM32_0WS_THRESHOLD 20000000 -#define STM32_1WS_THRESHOLD 40000000 -#define STM32_2WS_THRESHOLD 60000000 -#define STM32_3WS_THRESHOLD 80000000 -#define STM32_4WS_THRESHOLD 100000000 -#define STM32_5WS_THRESHOLD 120000000 -#define STM32_6WS_THRESHOLD 140000000 -#define STM32_7WS_THRESHOLD 168000000 -#define STM32_8WS_THRESHOLD 0 -#else -#error "invalid VDD voltage specified" -#endif - -#elif defined(STM32F401xx) -#if (STM32_VDD >= 270) && (STM32_VDD <= 360) -#define STM32_0WS_THRESHOLD 30000000 -#define STM32_1WS_THRESHOLD 60000000 -#define STM32_2WS_THRESHOLD 84000000 -#define STM32_3WS_THRESHOLD 0 -#define STM32_4WS_THRESHOLD 0 -#define STM32_5WS_THRESHOLD 0 -#define STM32_6WS_THRESHOLD 0 -#define STM32_7WS_THRESHOLD 0 -#define STM32_8WS_THRESHOLD 0 -#elif (STM32_VDD >= 240) && (STM32_VDD < 270) -#define STM32_0WS_THRESHOLD 24000000 -#define STM32_1WS_THRESHOLD 48000000 -#define STM32_2WS_THRESHOLD 72000000 -#define STM32_3WS_THRESHOLD 84000000 -#define STM32_4WS_THRESHOLD 0 -#define STM32_5WS_THRESHOLD 0 -#define STM32_6WS_THRESHOLD 0 -#define STM32_7WS_THRESHOLD 0 -#define STM32_8WS_THRESHOLD 0 -#elif (STM32_VDD >= 210) && (STM32_VDD < 240) -#define STM32_0WS_THRESHOLD 18000000 -#define STM32_1WS_THRESHOLD 36000000 -#define STM32_2WS_THRESHOLD 54000000 -#define STM32_3WS_THRESHOLD 72000000 -#define STM32_4WS_THRESHOLD 84000000 -#define STM32_5WS_THRESHOLD 0 -#define STM32_6WS_THRESHOLD 0 -#define STM32_7WS_THRESHOLD 0 -#define STM32_8WS_THRESHOLD 0 -#elif (STM32_VDD >= 180) && (STM32_VDD < 210) -#define STM32_0WS_THRESHOLD 16000000 -#define STM32_1WS_THRESHOLD 32000000 -#define STM32_2WS_THRESHOLD 48000000 -#define STM32_3WS_THRESHOLD 64000000 -#define STM32_4WS_THRESHOLD 80000000 -#define STM32_5WS_THRESHOLD 84000000 -#define STM32_6WS_THRESHOLD 0 -#define STM32_7WS_THRESHOLD 0 -#define STM32_8WS_THRESHOLD 0 -#else -#error "invalid VDD voltage specified" -#endif - -#else /* STM32F2XX */ -#if (STM32_VDD >= 270) && (STM32_VDD <= 360) -#define STM32_0WS_THRESHOLD 30000000 -#define STM32_1WS_THRESHOLD 60000000 -#define STM32_2WS_THRESHOLD 90000000 -#define STM32_3WS_THRESHOLD 120000000 -#define STM32_4WS_THRESHOLD 0 -#define STM32_5WS_THRESHOLD 0 -#define STM32_6WS_THRESHOLD 0 -#define STM32_7WS_THRESHOLD 0 -#elif (STM32_VDD >= 240) && (STM32_VDD < 270) -#define STM32_0WS_THRESHOLD 24000000 -#define STM32_1WS_THRESHOLD 48000000 -#define STM32_2WS_THRESHOLD 72000000 -#define STM32_3WS_THRESHOLD 96000000 -#define STM32_4WS_THRESHOLD 120000000 -#define STM32_5WS_THRESHOLD 0 -#define STM32_6WS_THRESHOLD 0 -#define STM32_7WS_THRESHOLD 0 -#elif (STM32_VDD >= 210) && (STM32_VDD < 240) -#define STM32_0WS_THRESHOLD 18000000 -#define STM32_1WS_THRESHOLD 36000000 -#define STM32_2WS_THRESHOLD 54000000 -#define STM32_3WS_THRESHOLD 72000000 -#define STM32_4WS_THRESHOLD 90000000 -#define STM32_5WS_THRESHOLD 108000000 -#define STM32_6WS_THRESHOLD 120000000 -#define STM32_7WS_THRESHOLD 0 -#elif (STM32_VDD >= 180) && (STM32_VDD < 210) -#define STM32_0WS_THRESHOLD 16000000 -#define STM32_1WS_THRESHOLD 32000000 -#define STM32_2WS_THRESHOLD 48000000 -#define STM32_3WS_THRESHOLD 64000000 -#define STM32_4WS_THRESHOLD 80000000 -#define STM32_5WS_THRESHOLD 96000000 -#define STM32_6WS_THRESHOLD 112000000 -#define STM32_7WS_THRESHOLD 120000000 -#else -#error "invalid VDD voltage specified" -#endif -#endif /* STM32F2XX */ - -/* - * HSI related checks. - */ -#if STM32_HSI_ENABLED -#else /* !STM32_HSI_ENABLED */ - -#if STM32_SW == STM32_SW_HSI -#error "HSI not enabled, required by STM32_SW" -#endif - -#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI) -#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC" -#endif - -#if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || \ - ((STM32_MCO1SEL == STM32_MCO1SEL_PLL) && \ - (STM32_PLLSRC == STM32_PLLSRC_HSI)) -#error "HSI not enabled, required by STM32_MCO1SEL" -#endif - -#if (STM32_MCO2SEL == STM32_MCO2SEL_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI) -#error "HSI not enabled, required by STM32_MCO2SEL" -#endif - -#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) && \ - (STM32_PLLSRC == STM32_PLLSRC_HSI) -#error "HSI not enabled, required by STM32_I2SSRC" -#endif - -#endif /* !STM32_HSI_ENABLED */ - -/* - * HSE related checks. - */ -#if STM32_HSE_ENABLED - -#if STM32_HSECLK == 0 -#error "HSE frequency not defined" -#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX) -#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)" -#endif - -#else /* !STM32_HSE_ENABLED */ - -#if STM32_SW == STM32_SW_HSE -#error "HSE not enabled, required by STM32_SW" -#endif - -#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE) -#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC" -#endif - -#if (STM32_MCO1SEL == STM32_MCO1SEL_HSE) || \ - ((STM32_MCO1SEL == STM32_MCO1SEL_PLL) && \ - (STM32_PLLSRC == STM32_PLLSRC_HSE)) -#error "HSE not enabled, required by STM32_MCO1SEL" -#endif - -#if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || \ - ((STM32_MCO2SEL == STM32_MCO2SEL_PLL) && \ - (STM32_PLLSRC == STM32_PLLSRC_HSE)) -#error "HSE not enabled, required by STM32_MCO2SEL" -#endif - -#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) && \ - (STM32_PLLSRC == STM32_PLLSRC_HSE) -#error "HSE not enabled, required by STM32_I2SSRC" -#endif - -#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV -#error "HSE not enabled, required by STM32_RTCSEL" -#endif - -#endif /* !STM32_HSE_ENABLED */ - -/* - * LSI related checks. - */ -#if STM32_LSI_ENABLED -#else /* !STM32_LSI_ENABLED */ - -#if STM32_RTCSEL == STM32_RTCSEL_LSI -#error "LSI not enabled, required by STM32_RTCSEL" -#endif - -#endif /* !STM32_LSI_ENABLED */ - -/* - * LSE related checks. - */ -#if STM32_LSE_ENABLED - -#if (STM32_LSECLK == 0) -#error "LSE frequency not defined" -#endif - -#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX) -#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)" -#endif - -#else /* !STM32_LSE_ENABLED */ - -#if STM32_RTCSEL == STM32_RTCSEL_LSE -#error "LSE not enabled, required by STM32_RTCSEL" -#endif - -#endif /* !STM32_LSE_ENABLED */ - -/** - * @brief STM32_PLLM field. - */ -#if ((STM32_PLLM_VALUE >= 2) && (STM32_PLLM_VALUE <= 63)) || \ - defined(__DOXYGEN__) -#define STM32_PLLM (STM32_PLLM_VALUE << 0) -#else -#error "invalid STM32_PLLM_VALUE value specified" -#endif - -/** - * @brief PLLs input clock frequency. - */ -#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) -#define STM32_PLLCLKIN (STM32_HSECLK / STM32_PLLM_VALUE) -#elif STM32_PLLSRC == STM32_PLLSRC_HSI -#define STM32_PLLCLKIN (STM32_HSICLK / STM32_PLLM_VALUE) -#else -#error "invalid STM32_PLLSRC value specified" -#endif - -/* - * PLLs input frequency range check. - */ -#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX) -#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)" -#endif - -/* - * PLL enable check. - */ -#if STM32_CLOCK48_REQUIRED || \ - (STM32_SW == STM32_SW_PLL) || \ - (STM32_MCO1SEL == STM32_MCO1SEL_PLL) || \ - (STM32_MCO2SEL == STM32_MCO2SEL_PLL) || \ - defined(__DOXYGEN__) -/** - * @brief PLL activation flag. - */ -#define STM32_ACTIVATE_PLL TRUE -#else -#define STM32_ACTIVATE_PLL FALSE -#endif - -/** - * @brief STM32_PLLN field. - */ -#if ((STM32_PLLN_VALUE >= 64) && (STM32_PLLN_VALUE <= 432)) || \ - defined(__DOXYGEN__) -#define STM32_PLLN (STM32_PLLN_VALUE << 6) -#else -#error "invalid STM32_PLLN_VALUE value specified" -#endif - -/** - * @brief STM32_PLLP field. - */ -#if (STM32_PLLP_VALUE == 2) || defined(__DOXYGEN__) -#define STM32_PLLP (0 << 16) -#elif STM32_PLLP_VALUE == 4 -#define STM32_PLLP (1 << 16) -#elif STM32_PLLP_VALUE == 6 -#define STM32_PLLP (2 << 16) -#elif STM32_PLLP_VALUE == 8 -#define STM32_PLLP (3 << 16) -#else -#error "invalid STM32_PLLP_VALUE value specified" -#endif - -/** - * @brief STM32_PLLQ field. - */ -#if ((STM32_PLLQ_VALUE >= 2) && (STM32_PLLQ_VALUE <= 15)) || \ - defined(__DOXYGEN__) -#define STM32_PLLQ (STM32_PLLQ_VALUE << 24) -#else -#error "invalid STM32_PLLQ_VALUE value specified" -#endif - -/** - * @brief PLL VCO frequency. - */ -#define STM32_PLLVCO (STM32_PLLCLKIN * STM32_PLLN_VALUE) - -/* - * PLL VCO frequency range check. - */ -#if (STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX) -#error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)" -#endif - -/** - * @brief PLL output clock frequency. - */ -#define STM32_PLLCLKOUT (STM32_PLLVCO / STM32_PLLP_VALUE) - -/* - * PLL output frequency range check. - */ -#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX) -#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)" -#endif - -/** - * @brief System clock source. - */ -#if STM32_NO_INIT || defined(__DOXYGEN__) -#define STM32_SYSCLK STM32_HSICLK -#elif (STM32_SW == STM32_SW_HSI) -#define STM32_SYSCLK STM32_HSICLK -#elif (STM32_SW == STM32_SW_HSE) -#define STM32_SYSCLK STM32_HSECLK -#elif (STM32_SW == STM32_SW_PLL) -#define STM32_SYSCLK STM32_PLLCLKOUT -#else -#error "invalid STM32_SW value specified" -#endif - -/* Check on the system clock.*/ -#if STM32_SYSCLK > STM32_SYSCLK_MAX -#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)" -#endif - -/* Calculating VOS settings, it is different for each sub-platform.*/ -#if defined(STM32F429_439xx) || defined(STM32F427_437xx) || \ - defined(__DOXYGEN__) -#if STM32_SYSCLK <= 120000000 -#define STM32_VOS STM32_VOS_SCALE3 -#define STM32_OVERDRIVE_REQUIRED FALSE -#elif STM32_SYSCLK <= 144000000 -#define STM32_VOS STM32_VOS_SCALE2 -#define STM32_OVERDRIVE_REQUIRED FALSE -#elif STM32_SYSCLK <= 168000000 -#define STM32_VOS STM32_VOS_SCALE1 -#define STM32_OVERDRIVE_REQUIRED FALSE -#else -#define STM32_VOS STM32_VOS_SCALE1 -#define STM32_OVERDRIVE_REQUIRED TRUE -#endif - -#elif defined(STM32F40_41xxx) -#if STM32_SYSCLK <= 144000000 -#define STM32_VOS STM32_VOS_SCALE2 -#else -#define STM32_VOS STM32_VOS_SCALE1 -#endif -#define STM32_OVERDRIVE_REQUIRED FALSE - -#elif defined(STM32F401xx) -#if STM32_SYSCLK <= 60000000 -#define STM32_VOS STM32_VOS_SCALE3 -#else -#define STM32_VOS STM32_VOS_SCALE2 -#endif -#define STM32_OVERDRIVE_REQUIRED FALSE - -#else /* STM32F2XX */ -#define STM32_OVERDRIVE_REQUIRED FALSE -#endif - -/** - * @brief AHB frequency. - */ -#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__) -#define STM32_HCLK (STM32_SYSCLK / 1) -#elif STM32_HPRE == STM32_HPRE_DIV2 -#define STM32_HCLK (STM32_SYSCLK / 2) -#elif STM32_HPRE == STM32_HPRE_DIV4 -#define STM32_HCLK (STM32_SYSCLK / 4) -#elif STM32_HPRE == STM32_HPRE_DIV8 -#define STM32_HCLK (STM32_SYSCLK / 8) -#elif STM32_HPRE == STM32_HPRE_DIV16 -#define STM32_HCLK (STM32_SYSCLK / 16) -#elif STM32_HPRE == STM32_HPRE_DIV64 -#define STM32_HCLK (STM32_SYSCLK / 64) -#elif STM32_HPRE == STM32_HPRE_DIV128 -#define STM32_HCLK (STM32_SYSCLK / 128) -#elif STM32_HPRE == STM32_HPRE_DIV256 -#define STM32_HCLK (STM32_SYSCLK / 256) -#elif STM32_HPRE == STM32_HPRE_DIV512 -#define STM32_HCLK (STM32_SYSCLK / 512) -#else -#error "invalid STM32_HPRE value specified" -#endif - -/* - * AHB frequency check. - */ -#if STM32_HCLK > STM32_SYSCLK_MAX -#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)" -#endif - -/** - * @brief APB1 frequency. - */ -#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) -#define STM32_PCLK1 (STM32_HCLK / 1) -#elif STM32_PPRE1 == STM32_PPRE1_DIV2 -#define STM32_PCLK1 (STM32_HCLK / 2) -#elif STM32_PPRE1 == STM32_PPRE1_DIV4 -#define STM32_PCLK1 (STM32_HCLK / 4) -#elif STM32_PPRE1 == STM32_PPRE1_DIV8 -#define STM32_PCLK1 (STM32_HCLK / 8) -#elif STM32_PPRE1 == STM32_PPRE1_DIV16 -#define STM32_PCLK1 (STM32_HCLK / 16) -#else -#error "invalid STM32_PPRE1 value specified" -#endif - -/* - * APB1 frequency check. - */ -#if STM32_PCLK1 > STM32_PCLK1_MAX -#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)" -#endif - -/** - * @brief APB2 frequency. - */ -#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) -#define STM32_PCLK2 (STM32_HCLK / 1) -#elif STM32_PPRE2 == STM32_PPRE2_DIV2 -#define STM32_PCLK2 (STM32_HCLK / 2) -#elif STM32_PPRE2 == STM32_PPRE2_DIV4 -#define STM32_PCLK2 (STM32_HCLK / 4) -#elif STM32_PPRE2 == STM32_PPRE2_DIV8 -#define STM32_PCLK2 (STM32_HCLK / 8) -#elif STM32_PPRE2 == STM32_PPRE2_DIV16 -#define STM32_PCLK2 (STM32_HCLK / 16) -#else -#error "invalid STM32_PPRE2 value specified" -#endif - -/* - * APB2 frequency check. - */ -#if STM32_PCLK2 > STM32_PCLK2_MAX -#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)" -#endif - -/* - * PLLI2S enable check. - */ -#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) || defined(__DOXYGEN__) -/** - * @brief PLL activation flag. - */ -#define STM32_ACTIVATE_PLLI2S TRUE -#else -#define STM32_ACTIVATE_PLLI2S FALSE -#endif - -/** - * @brief STM32_PLLI2SN field. - */ -#if ((STM32_PLLI2SN_VALUE >= 192) && (STM32_PLLI2SN_VALUE <= 432)) || \ - defined(__DOXYGEN__) -#define STM32_PLLI2SN (STM32_PLLI2SN_VALUE << 6) -#else -#error "invalid STM32_PLLI2SN_VALUE value specified" -#endif - -/** - * @brief STM32_PLLI2SR field. - */ -#if ((STM32_PLLI2SR_VALUE >= 2) && (STM32_PLLI2SR_VALUE <= 7)) || \ - defined(__DOXYGEN__) -#define STM32_PLLI2SR (STM32_PLLI2SR_VALUE << 28) -#else -#error "invalid STM32_PLLI2SR_VALUE value specified" -#endif - -/** - * @brief PLL VCO frequency. - */ -#define STM32_PLLI2SVCO (STM32_PLLCLKIN * STM32_PLLI2SN_VALUE) - -/* - * PLLI2S VCO frequency range check. - */ -#if (STM32_PLLI2SVCO < STM32_PLLVCO_MIN) || \ - (STM32_PLLI2SVCO > STM32_PLLVCO_MAX) -#error "STM32_PLLI2SVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)" -#endif - -/** - * @brief PLLI2S output clock frequency. - */ -#define STM32_PLLI2SCLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SR_VALUE) - -/** - * @brief MCO1 divider clock. - */ -#if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || defined(__DOXYGEN__) -#define STM32_MCO1DIVCLK STM32_HSICLK -#elif STM32_MCO1SEL == STM32_MCO1SEL_LSE -#define STM32_MCO1DIVCLK STM32_LSECLK -#elif STM32_MCO1SEL == STM32_MCO1SEL_HSE -#define STM32_MCO1DIVCLK STM32_HSECLK -#elif STM32_MCO1SEL == STM32_MCO1SEL_PLL -#define STM32_MCO1DIVCLK STM32_PLLCLKOUT -#else -#error "invalid STM32_MCO1SEL value specified" -#endif - -/** - * @brief MCO1 output pin clock. - */ -#if (STM32_MCO1PRE == STM32_MCO1PRE_DIV1) || defined(__DOXYGEN__) -#define STM32_MCO1CLK STM32_MCO1DIVCLK -#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV2 -#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 2) -#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV3 -#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 3) -#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV4 -#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 4) -#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV5 -#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 5) -#else -#error "invalid STM32_MCO1PRE value specified" -#endif - -/** - * @brief MCO2 divider clock. - */ -#if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || defined(__DOXYGEN__) -#define STM32_MCO2DIVCLK STM32_HSECLK -#elif STM32_MCO2SEL == STM32_MCO2SEL_PLL -#define STM32_MCO2DIVCLK STM32_PLLCLKOUT -#elif STM32_MCO2SEL == STM32_MCO2SEL_SYSCLK -#define STM32_MCO2DIVCLK STM32_SYSCLK -#elif STM32_MCO2SEL == STM32_MCO2SEL_PLLI2S -#define STM32_MCO2DIVCLK STM32_PLLI2S -#else -#error "invalid STM32_MCO2SEL value specified" -#endif - -/** - * @brief MCO2 output pin clock. - */ -#if (STM32_MCO2PRE == STM32_MCO2PRE_DIV1) || defined(__DOXYGEN__) -#define STM32_MCO2CLK STM32_MCO2DIVCLK -#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV2 -#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 2) -#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV3 -#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 3) -#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV4 -#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 4) -#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV5 -#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 5) -#else -#error "invalid STM32_MCO2PRE value specified" -#endif - -/** - * @brief RTC HSE divider setting. - */ -#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \ - defined(__DOXYGEN__) -#define STM32_RTCPRE (STM32_RTCPRE_VALUE << 16) -#else -#error "invalid STM32_RTCPRE value specified" -#endif - -/** - * @brief HSE divider toward RTC clock. - */ -#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \ - defined(__DOXYGEN__) -#define STM32_HSEDIVCLK (STM32_HSECLK / STM32_RTCPRE_VALUE) -#else -#error "invalid STM32_RTCPRE value specified" -#endif - -/** - * @brief RTC clock. - */ -#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__) -#define STM32_RTCCLK 0 -#elif STM32_RTCSEL == STM32_RTCSEL_LSE -#define STM32_RTCCLK STM32_LSECLK -#elif STM32_RTCSEL == STM32_RTCSEL_LSI -#define STM32_RTCCLK STM32_LSICLK -#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV -#define STM32_RTCCLK STM32_HSEDIVCLK -#else -#error "invalid STM32_RTCSEL value specified" -#endif - -/** - * @brief 48MHz frequency. - */ -#if STM32_CLOCK48_REQUIRED || defined(__DOXYGEN__) -#define STM32_PLL48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE) -#else -#define STM32_PLL48CLK 0 -#endif - -/** - * @brief Timers 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14 clock. - */ -#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) -#define STM32_TIMCLK1 (STM32_PCLK1 * 1) -#else -#define STM32_TIMCLK1 (STM32_PCLK1 * 2) -#endif - -/** - * @brief Timers 1, 8 clock. - */ -#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) -#define STM32_TIMCLK2 (STM32_PCLK2 * 1) -#else -#define STM32_TIMCLK2 (STM32_PCLK2 * 2) -#endif - -/** - * @brief Flash settings. - */ -#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__) -#define STM32_FLASHBITS 0x00000000 -#elif STM32_HCLK <= STM32_1WS_THRESHOLD -#define STM32_FLASHBITS 0x00000001 -#elif STM32_HCLK <= STM32_2WS_THRESHOLD -#define STM32_FLASHBITS 0x00000002 -#elif STM32_HCLK <= STM32_3WS_THRESHOLD -#define STM32_FLASHBITS 0x00000003 -#elif STM32_HCLK <= STM32_4WS_THRESHOLD -#define STM32_FLASHBITS 0x00000004 -#elif STM32_HCLK <= STM32_5WS_THRESHOLD -#define STM32_FLASHBITS 0x00000005 -#elif STM32_HCLK <= STM32_6WS_THRESHOLD -#define STM32_FLASHBITS 0x00000006 -#elif STM32_HCLK <= STM32_7WS_THRESHOLD -#define STM32_FLASHBITS 0x00000007 -#else -#define STM32_FLASHBITS 0x00000008 -#endif - -/* There are differences in vector names in the various sub-families, - normalizing.*/ -#define TIM1_BRK_IRQn TIM1_BRK_TIM9_IRQn -#define TIM1_UP_IRQn TIM1_UP_TIM10_IRQn -#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM11_IRQn -#define TIM8_BRK_IRQn TIM8_BRK_TIM12_IRQn -#define TIM8_UP_IRQn TIM8_UP_TIM13_IRQn -#define TIM8_TRG_COM_IRQn TIM8_TRG_COM_TIM14_IRQn - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type representing a system clock frequency. - */ -typedef uint32_t halclock_t; - -/** - * @brief Type of the realtime free counter value. - */ -typedef uint32_t halrtcnt_t; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Returns the current value of the system free running counter. - * @note This service is implemented by returning the content of the - * DWT_CYCCNT register. - * - * @return The value of the system free running counter of - * type halrtcnt_t. - * - * @notapi - */ -#define hal_lld_get_counter_value() DWT_CYCCNT - -/** - * @brief Realtime counter frequency. - * @note The DWT_CYCCNT register is incremented directly by the system - * clock so this function returns STM32_HCLK. - * - * @return The realtime counter frequency of type halclock_t. - * - * @notapi - */ -#define hal_lld_get_counter_frequency() STM32_HCLK - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/* STM32 helpers and custom drivers.*/ -#include "stm32_isr.h" -#include "stm32_dma.h" -#include "stm32_rcc.h" - -#ifdef __cplusplus -extern "C" { -#endif - void hal_lld_init(void); - void stm32_clock_init(void); -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_LLD_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32F4xx/platform.dox b/firmware/chibios/os/hal/platforms/STM32F4xx/platform.dox deleted file mode 100644 index d64d5764d6..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F4xx/platform.dox +++ /dev/null @@ -1,364 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @defgroup STM32F4xx_DRIVERS STM32F4xx/STM32F2xx Drivers - * @details This section describes all the supported drivers on the STM32F4xx - * and STM32F2xx platform and the implementation details of the single - * drivers. - * - * @ingroup platforms - */ - -/** - * @defgroup STM32F4xx_HAL STM32F4xx Initialization Support - * @details The STM32F4xx HAL support is responsible for system initialization. - * - * @section stm32f4xx_hal_1 Supported HW resources - * - PLL1. - * - PLL2. - * - RCC. - * - Flash. - * . - * @section stm32f4xx_hal_2 STM32F4xx HAL driver implementation features - * - PLL startup and stabilization. - * - Clock tree initialization. - * - Clock source selection. - * - Flash wait states initialization based on the selected clock options. - * - SYSTICK initialization based on current clock and kernel required rate. - * - DMA support initialization. - * . - * @ingroup STM32F4xx_DRIVERS - */ - -/** - * @defgroup STM32F4xx_ADC STM32F4xx ADC Support - * @details The STM32F4xx ADC driver supports the ADC peripherals using DMA - * channels for maximum performance. - * - * @section stm32f4xx_adc_1 Supported HW resources - * - ADC1. - * - ADC2. - * - ADC3. - * - DMA2. - * . - * @section stm32f4xx_adc_2 STM32F4xx ADC driver implementation features - * - Clock stop for reduced power usage when the driver is in stop state. - * - Streaming conversion using DMA for maximum performance. - * - Programmable ADC interrupt priority level. - * - Programmable DMA bus priority for each DMA channel. - * - Programmable DMA interrupt priority for each DMA channel. - * - DMA and ADC errors detection. - * . - * @ingroup STM32F4xx_DRIVERS - */ - -/** - * @defgroup STM32F4xx_CAN STM32F4xx CAN Support - * @details The STM32F4xx CAN driver uses the CAN peripherals. - * - * @section stm32f4xx_can_1 Supported HW resources - * - bxCAN1. - * . - * @section stm32f4xx_can_2 STM32F4xx CAN driver implementation features - * - Clock stop for reduced power usage when the driver is in stop state. - * - Support for bxCAN sleep mode. - * - Programmable bxCAN interrupts priority level. - * . - * @ingroup STM32F4xx_DRIVERS - */ - -/** - * @defgroup STM32F4xx_EXT STM32F4xx EXT Support - * @details The STM32F4xx EXT driver uses the EXTI peripheral. - * - * @section stm32f4xx_ext_1 Supported HW resources - * - EXTI. - * . - * @section stm32f4xx_ext_2 STM32F4xx EXT driver implementation features - * - Each EXTI channel can be independently enabled and programmed. - * - Programmable EXTI interrupts priority level. - * - Capability to work as event sources (WFE) rather than interrupt sources. - * . - * @ingroup STM32F4xx_DRIVERS - */ - -/** - * @defgroup STM32F4xx_GPT STM32F4xx GPT Support - * @details The STM32F4xx GPT driver uses the TIMx peripherals. - * - * @section stm32f4xx_gpt_1 Supported HW resources - * - TIM1. - * - TIM2. - * - TIM3. - * - TIM4. - * - TIM5. - * - TIM8. - * . - * @section stm32f4xx_gpt_2 STM32F4xx GPT driver implementation features - * - Each timer can be independently enabled and programmed. Unused - * peripherals are left in low power mode. - * - Programmable TIMx interrupts priority level. - * . - * @ingroup STM32F4xx_DRIVERS - */ - -/** - * @defgroup STM32F4xx_ICU STM32F4xx ICU Support - * @details The STM32F4xx ICU driver uses the TIMx peripherals. - * - * @section stm32f4xx_icu_1 Supported HW resources - * - TIM1. - * - TIM2. - * - TIM3. - * - TIM4. - * - TIM5. - * - TIM8. - * . - * @section stm32f4xx_icu_2 STM32F4xx ICU driver implementation features - * - Each timer can be independently enabled and programmed. Unused - * peripherals are left in low power mode. - * - Programmable TIMx interrupts priority level. - * . - * @ingroup STM32F4xx_DRIVERS - */ - -/** - * @defgroup STM32F4xx_MAC STM32F4xx MAC Support - * @details The STM32F4xx MAC driver supports the ETH peripheral. - * - * @section stm32f4xx_mac_1 Supported HW resources - * - ETH. - * - PHY (external). - * . - * @section stm32f4xx_mac_2 STM32F4xx MAC driver implementation features - * - Dedicated DMA operations. - * - Support for checksum off-loading. - * . - * @ingroup STM32F4xx_DRIVERS - */ - -/** - * @defgroup STM32F4xx_PAL STM32F4xx PAL Support - * @details The STM32F4xx PAL driver uses the GPIO peripherals. - * - * @section stm32f4xx_pal_1 Supported HW resources - * - GPIOA. - * - GPIOB. - * - GPIOC. - * - GPIOD. - * - GPIOE. - * - GPIOF. - * - GPIOG. - * - GPIOH. - * - GPIOI. - * . - * @section stm32f4xx_pal_2 STM32F4xx PAL driver implementation features - * The PAL driver implementation fully supports the following hardware - * capabilities: - * - 16 bits wide ports. - * - Atomic set/reset functions. - * - Atomic set+reset function (atomic bus operations). - * - Output latched regardless of the pad setting. - * - Direct read of input pads regardless of the pad setting. - * . - * @section stm32f4xx_pal_3 Supported PAL setup modes - * The STM32F4xx PAL driver supports the following I/O modes: - * - @p PAL_MODE_RESET. - * - @p PAL_MODE_UNCONNECTED. - * - @p PAL_MODE_INPUT. - * - @p PAL_MODE_INPUT_PULLUP. - * - @p PAL_MODE_INPUT_PULLDOWN. - * - @p PAL_MODE_INPUT_ANALOG. - * - @p PAL_MODE_OUTPUT_PUSHPULL. - * - @p PAL_MODE_OUTPUT_OPENDRAIN. - * - @p PAL_MODE_ALTERNATE (non standard). - * . - * Any attempt to setup an invalid mode is ignored. - * - * @section stm32f4xx_pal_4 Suboptimal behavior - * The STM32F4xx GPIO is less than optimal in several areas, the limitations - * should be taken in account while using the PAL driver: - * - Pad/port toggling operations are not atomic. - * - Pad/group mode setup is not atomic. - * . - * @ingroup STM32F4xx_DRIVERS - */ - -/** - * @defgroup STM32F4xx_PWM STM32F4xx PWM Support - * @details The STM32F4xx PWM driver uses the TIMx peripherals. - * - * @section stm32f4xx_pwm_1 Supported HW resources - * - TIM1. - * - TIM2. - * - TIM3. - * - TIM4. - * - TIM5. - * - TIM8. - * . - * @section stm32f4xx_pwm_2 STM32F4xx PWM driver implementation features - * - Each timer can be independently enabled and programmed. Unused - * peripherals are left in low power mode. - * - Four independent PWM channels per timer. - * - Programmable TIMx interrupts priority level. - * . - * @ingroup STM32F4xx_DRIVERS - */ - -/** - * @defgroup STM32F4xx_SDC STM32F4xx SDC Support - * @details The STM32F4xx SDC driver uses the SDIO peripheral. - * - * @section stm32f4xx_sdc_1 Supported HW resources - * - SDIO. - * - DMA2. - * . - * @section stm32f4xx_sdc_2 STM32F4xx SDC driver implementation features - * - Clock stop for reduced power usage when the driver is in stop state. - * - Programmable interrupt priority. - * - DMA is used for receiving and transmitting. - * - Programmable DMA bus priority for each DMA channel. - * . - * @ingroup STM32F4xx_DRIVERS - */ - -/** - * @defgroup STM32F4xx_SERIAL STM32F4xx Serial Support - * @details The STM32F4xx Serial driver uses the USART/UART peripherals in a - * buffered, interrupt driven, implementation. - * - * @section stm32f4xx_serial_1 Supported HW resources - * The serial driver can support any of the following hardware resources: - * - USART1. - * - USART2. - * - USART3. - * - UART4. - * - UART5. - * - USART6. - * . - * @section stm32f4xx_serial_2 STM32F4xx Serial driver implementation features - * - Clock stop for reduced power usage when the driver is in stop state. - * - Each UART/USART can be independently enabled and programmed. Unused - * peripherals are left in low power mode. - * - Fully interrupt driven. - * - Programmable priority levels for each UART/USART. - * . - * @ingroup STM32F4xx_DRIVERS - */ - -/** - * @defgroup STM32F4xx_SPI STM32F4xx SPI Support - * @details The SPI driver supports the STM32F4xx SPI peripherals using DMA - * channels for maximum performance. - * - * @section stm32f4xx_spi_1 Supported HW resources - * - SPI1. - * - SPI2. - * - SPI3. - * - DMA1. - * - DMA2. - * . - * @section stm32f4xx_spi_2 STM32F4xx SPI driver implementation features - * - Clock stop for reduced power usage when the driver is in stop state. - * - Each SPI can be independently enabled and programmed. Unused - * peripherals are left in low power mode. - * - Programmable interrupt priority levels for each SPI. - * - DMA is used for receiving and transmitting. - * - Programmable DMA bus priority for each DMA channel. - * - Programmable DMA interrupt priority for each DMA channel. - * - Programmable DMA error hook. - * . - * @ingroup STM32F4xx_DRIVERS - */ - -/** - * @defgroup STM32F4xx_UART STM32F4xx UART Support - * @details The UART driver supports the STM32F4xx USART peripherals using DMA - * channels for maximum performance. - * - * @section stm32f4xx_uart_1 Supported HW resources - * The UART driver can support any of the following hardware resources: - * - USART1. - * - USART2. - * - USART3. - * - DMA1. - * - DMA2. - * . - * @section stm32f4xx_uart_2 STM32F4xx UART driver implementation features - * - Clock stop for reduced power usage when the driver is in stop state. - * - Each UART/USART can be independently enabled and programmed. Unused - * peripherals are left in low power mode. - * - Programmable interrupt priority levels for each UART/USART. - * - DMA is used for receiving and transmitting. - * - Programmable DMA bus priority for each DMA channel. - * - Programmable DMA interrupt priority for each DMA channel. - * - Programmable DMA error hook. - * . - * @ingroup STM32F4xx_DRIVERS - */ - -/** - * @defgroup STM32F4xx_PLATFORM_DRIVERS STM32F4xx Platform Drivers - * @details Platform support drivers. Platform drivers do not implement HAL - * standard driver templates, their role is to support platform - * specific functionalities. - * - * @ingroup STM32F4xx_DRIVERS - */ - -/** - * @defgroup STM32F4xx_DMA STM32F4xx DMA Support - * @details This DMA helper driver is used by the other drivers in order to - * access the shared DMA resources in a consistent way. - * - * @section stm32f4xx_dma_1 Supported HW resources - * The DMA driver can support any of the following hardware resources: - * - DMA1. - * - DMA2. - * . - * @section stm32f4xx_dma_2 STM32F4xx DMA driver implementation features - * - Exports helper functions/macros to the other drivers that share the - * DMA resource. - * - Automatic DMA clock stop when not in use by any driver. - * - DMA streams and interrupt vectors sharing among multiple drivers. - * . - * @ingroup STM32F4xx_PLATFORM_DRIVERS - */ - -/** - * @defgroup STM32F4xx_ISR STM32F4xx ISR Support - * @details This ISR helper driver is used by the other drivers in order to - * map ISR names to physical vector names. - * - * @ingroup STM32F4xx_PLATFORM_DRIVERS - */ - -/** - * @defgroup STM32F4xx_RCC STM32F4xx RCC Support - * @details This RCC helper driver is used by the other drivers in order to - * access the shared RCC resources in a consistent way. - * - * @section stm32f4xx_rcc_1 Supported HW resources - * - RCC. - * . - * @section stm32f4xx_rcc_2 STM32F4xx RCC driver implementation features - * - Peripherals reset. - * - Peripherals clock enable. - * - Peripherals clock disable. - * . - * @ingroup STM32F4xx_PLATFORM_DRIVERS - */ diff --git a/firmware/chibios/os/hal/platforms/STM32F4xx/platform.mk b/firmware/chibios/os/hal/platforms/STM32F4xx/platform.mk deleted file mode 100644 index 3c01889587..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F4xx/platform.mk +++ /dev/null @@ -1,30 +0,0 @@ -# List of all the STM32F2xx/STM32F4xx platform files. -PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F4xx/stm32_dma.c \ - ${CHIBIOS}/os/hal/platforms/STM32F4xx/hal_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32F4xx/adc_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32F4xx/ext_lld_isr.c \ - ${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/mac_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/sdc_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/I2Cv1/i2c_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/OTGv1/usb_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/RTCv2/rtc_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/SPIv1/spi_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/gpt_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/icu_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/pwm_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/USARTv1/serial_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/USARTv1/uart_lld.c - -# Required include directories -PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F4xx \ - ${CHIBIOS}/os/hal/platforms/STM32 \ - ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \ - ${CHIBIOS}/os/hal/platforms/STM32/I2Cv1 \ - ${CHIBIOS}/os/hal/platforms/STM32/OTGv1 \ - ${CHIBIOS}/os/hal/platforms/STM32/RTCv2 \ - ${CHIBIOS}/os/hal/platforms/STM32/SPIv1 \ - ${CHIBIOS}/os/hal/platforms/STM32/TIMv1 \ - ${CHIBIOS}/os/hal/platforms/STM32/USARTv1 diff --git a/firmware/chibios/os/hal/platforms/STM32F4xx/stm32_dma.c b/firmware/chibios/os/hal/platforms/STM32F4xx/stm32_dma.c deleted file mode 100644 index a601e7c83b..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F4xx/stm32_dma.c +++ /dev/null @@ -1,528 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F4xx/stm32_dma.c - * @brief Enhanced DMA helper driver code. - * - * @addtogroup STM32F4xx_DMA - * @details DMA sharing helper driver. In the STM32 the DMA streams are a - * shared resource, this driver allows to allocate and free DMA - * streams at runtime in order to allow all the other device - * drivers to coordinate the access to the resource. - * @note The DMA ISR handlers are all declared into this module because - * sharing, the various device drivers can associate a callback to - * ISRs when allocating streams. - * @{ - */ - -#include "ch.h" -#include "hal.h" - -/* The following macro is only defined if some driver requiring DMA services - has been enabled.*/ -#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/** - * @brief Mask of the DMA1 streams in @p dma_streams_mask. - */ -#define STM32_DMA1_STREAMS_MASK 0x000000FF - -/** - * @brief Mask of the DMA2 streams in @p dma_streams_mask. - */ -#define STM32_DMA2_STREAMS_MASK 0x0000FF00 - -/** - * @brief Post-reset value of the stream CR register. - */ -#define STM32_DMA_CR_RESET_VALUE 0x00000000 - -/** - * @brief Post-reset value of the stream FCR register. - */ -#define STM32_DMA_FCR_RESET_VALUE 0x00000021 - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief DMA streams descriptors. - * @details This table keeps the association between an unique stream - * identifier and the involved physical registers. - * @note Don't use this array directly, use the appropriate wrapper macros - * instead: @p STM32_DMA1_STREAM0, @p STM32_DMA1_STREAM1 etc. - */ -const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = { - {DMA1_Stream0, &DMA1->LIFCR, 0, 0, DMA1_Stream0_IRQn}, - {DMA1_Stream1, &DMA1->LIFCR, 6, 1, DMA1_Stream1_IRQn}, - {DMA1_Stream2, &DMA1->LIFCR, 16, 2, DMA1_Stream2_IRQn}, - {DMA1_Stream3, &DMA1->LIFCR, 22, 3, DMA1_Stream3_IRQn}, - {DMA1_Stream4, &DMA1->HIFCR, 0, 4, DMA1_Stream4_IRQn}, - {DMA1_Stream5, &DMA1->HIFCR, 6, 5, DMA1_Stream5_IRQn}, - {DMA1_Stream6, &DMA1->HIFCR, 16, 6, DMA1_Stream6_IRQn}, - {DMA1_Stream7, &DMA1->HIFCR, 22, 7, DMA1_Stream7_IRQn}, - {DMA2_Stream0, &DMA2->LIFCR, 0, 8, DMA2_Stream0_IRQn}, - {DMA2_Stream1, &DMA2->LIFCR, 6, 9, DMA2_Stream1_IRQn}, - {DMA2_Stream2, &DMA2->LIFCR, 16, 10, DMA2_Stream2_IRQn}, - {DMA2_Stream3, &DMA2->LIFCR, 22, 11, DMA2_Stream3_IRQn}, - {DMA2_Stream4, &DMA2->HIFCR, 0, 12, DMA2_Stream4_IRQn}, - {DMA2_Stream5, &DMA2->HIFCR, 6, 13, DMA2_Stream5_IRQn}, - {DMA2_Stream6, &DMA2->HIFCR, 16, 14, DMA2_Stream6_IRQn}, - {DMA2_Stream7, &DMA2->HIFCR, 22, 15, DMA2_Stream7_IRQn}, -}; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief DMA ISR redirector type. - */ -typedef struct { - stm32_dmaisr_t dma_func; /**< @brief DMA callback function. */ - void *dma_param; /**< @brief DMA callback parameter. */ -} dma_isr_redir_t; - -/** - * @brief Mask of the allocated streams. - */ -static uint32_t dma_streams_mask; - -/** - * @brief DMA IRQ redirectors. - */ -static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS]; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief DMA1 stream 0 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA1_Stream0_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA1->LISR >> 0) & STM32_DMA_ISR_MASK; - DMA1->LIFCR = flags << 0; - if (dma_isr_redir[0].dma_func) - dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 1 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA1_Stream1_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA1->LISR >> 6) & STM32_DMA_ISR_MASK; - DMA1->LIFCR = flags << 6; - if (dma_isr_redir[1].dma_func) - dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 2 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA1_Stream2_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA1->LISR >> 16) & STM32_DMA_ISR_MASK; - DMA1->LIFCR = flags << 16; - if (dma_isr_redir[2].dma_func) - dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 3 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA1_Stream3_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA1->LISR >> 22) & STM32_DMA_ISR_MASK; - DMA1->LIFCR = flags << 22; - if (dma_isr_redir[3].dma_func) - dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 4 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA1_Stream4_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA1->HISR >> 0) & STM32_DMA_ISR_MASK; - DMA1->HIFCR = flags << 0; - if (dma_isr_redir[4].dma_func) - dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 5 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA1_Stream5_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA1->HISR >> 6) & STM32_DMA_ISR_MASK; - DMA1->HIFCR = flags << 6; - if (dma_isr_redir[5].dma_func) - dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 6 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA1_Stream6_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA1->HISR >> 16) & STM32_DMA_ISR_MASK; - DMA1->HIFCR = flags << 16; - if (dma_isr_redir[6].dma_func) - dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 7 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA1_Stream7_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA1->HISR >> 22) & STM32_DMA_ISR_MASK; - DMA1->HIFCR = flags << 22; - if (dma_isr_redir[7].dma_func) - dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 0 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA2_Stream0_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA2->LISR >> 0) & STM32_DMA_ISR_MASK; - DMA2->LIFCR = flags << 0; - if (dma_isr_redir[8].dma_func) - dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 1 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA2_Stream1_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA2->LISR >> 6) & STM32_DMA_ISR_MASK; - DMA2->LIFCR = flags << 6; - if (dma_isr_redir[9].dma_func) - dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 2 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA2_Stream2_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA2->LISR >> 16) & STM32_DMA_ISR_MASK; - DMA2->LIFCR = flags << 16; - if (dma_isr_redir[10].dma_func) - dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 3 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA2_Stream3_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA2->LISR >> 22) & STM32_DMA_ISR_MASK; - DMA2->LIFCR = flags << 22; - if (dma_isr_redir[11].dma_func) - dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 4 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA2_Stream4_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA2->HISR >> 0) & STM32_DMA_ISR_MASK; - DMA2->HIFCR = flags << 0; - if (dma_isr_redir[12].dma_func) - dma_isr_redir[12].dma_func(dma_isr_redir[12].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 5 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA2_Stream5_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA2->HISR >> 6) & STM32_DMA_ISR_MASK; - DMA2->HIFCR = flags << 6; - if (dma_isr_redir[13].dma_func) - dma_isr_redir[13].dma_func(dma_isr_redir[13].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 6 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA2_Stream6_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA2->HISR >> 16) & STM32_DMA_ISR_MASK; - DMA2->HIFCR = flags << 16; - if (dma_isr_redir[14].dma_func) - dma_isr_redir[14].dma_func(dma_isr_redir[14].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 7 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA2_Stream7_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA2->HISR >> 22) & STM32_DMA_ISR_MASK; - DMA2->HIFCR = flags << 22; - if (dma_isr_redir[15].dma_func) - dma_isr_redir[15].dma_func(dma_isr_redir[15].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief STM32 DMA helper initialization. - * - * @init - */ -void dmaInit(void) { - int i; - - dma_streams_mask = 0; - for (i = 0; i < STM32_DMA_STREAMS; i++) { - _stm32_dma_streams[i].stream->CR = 0; - dma_isr_redir[i].dma_func = NULL; - } - DMA1->LIFCR = 0xFFFFFFFF; - DMA1->HIFCR = 0xFFFFFFFF; - DMA2->LIFCR = 0xFFFFFFFF; - DMA2->HIFCR = 0xFFFFFFFF; -} - -/** - * @brief Allocates a DMA stream. - * @details The stream is allocated and, if required, the DMA clock enabled. - * The function also enables the IRQ vector associated to the stream - * and initializes its priority. - * @pre The stream must not be already in use or an error is returned. - * @post The stream is allocated and the default ISR handler redirected - * to the specified function. - * @post The stream ISR vector is enabled and its priority configured. - * @post The stream must be freed using @p dmaStreamRelease() before it can - * be reused with another peripheral. - * @post The stream is in its post-reset state. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] priority IRQ priority mask for the DMA stream - * @param[in] func handling function pointer, can be @p NULL - * @param[in] param a parameter to be passed to the handling function - * @return The operation status. - * @retval FALSE no error, stream taken. - * @retval TRUE error, stream already taken. - * - * @special - */ -bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, - uint32_t priority, - stm32_dmaisr_t func, - void *param) { - - chDbgCheck(dmastp != NULL, "dmaStreamAllocate"); - - /* Checks if the stream is already taken.*/ - if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0) - return TRUE; - - /* Marks the stream as allocated.*/ - dma_isr_redir[dmastp->selfindex].dma_func = func; - dma_isr_redir[dmastp->selfindex].dma_param = param; - dma_streams_mask |= (1 << dmastp->selfindex); - - /* Enabling DMA clocks required by the current streams set.*/ - if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0) - rccEnableDMA1(FALSE); - if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0) - rccEnableDMA2(FALSE); - - /* Putting the stream in a safe state.*/ - dmaStreamDisable(dmastp); - dmastp->stream->CR = STM32_DMA_CR_RESET_VALUE; - dmastp->stream->FCR = STM32_DMA_FCR_RESET_VALUE; - - /* Enables the associated IRQ vector if a callback is defined.*/ - if (func != NULL) - nvicEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority)); - - return FALSE; -} - -/** - * @brief Releases a DMA stream. - * @details The stream is freed and, if required, the DMA clock disabled. - * Trying to release a unallocated stream is an illegal operation - * and is trapped if assertions are enabled. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post The stream is again available. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * - * @special - */ -void dmaStreamRelease(const stm32_dma_stream_t *dmastp) { - - chDbgCheck(dmastp != NULL, "dmaStreamRelease"); - - /* Check if the streams is not taken.*/ - chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0, - "dmaStreamRelease(), #1", "not allocated"); - - /* Disables the associated IRQ vector.*/ - nvicDisableVector(dmastp->vector); - - /* Marks the stream as not allocated.*/ - dma_streams_mask &= ~(1 << dmastp->selfindex); - - /* Shutting down clocks that are no more required, if any.*/ - if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0) - rccDisableDMA1(FALSE); - if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0) - rccDisableDMA2(FALSE); -} - -#endif /* STM32_DMA_REQUIRED */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32F4xx/stm32_dma.h b/firmware/chibios/os/hal/platforms/STM32F4xx/stm32_dma.h deleted file mode 100644 index 05e4927607..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F4xx/stm32_dma.h +++ /dev/null @@ -1,461 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F4xx/stm32_dma.h - * @brief Enhanced-DMA helper driver header. - * @note This file requires definitions from the ST STM32F4xx header file - * stm32f4xx.h. - * - * @addtogroup STM32F4xx_DMA - * @{ - */ - -#ifndef _STM32_DMA_H_ -#define _STM32_DMA_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Total number of DMA streams. - * @note This is the total number of streams among all the DMA units. - */ -#define STM32_DMA_STREAMS 16 - -/** - * @brief Mask of the ISR bits passed to the DMA callback functions. - */ -#define STM32_DMA_ISR_MASK 0x3D - -/** - * @brief Returns the channel associated to the specified stream. - * - * @param[in] id the unique numeric stream identifier - * @param[in] c a stream/channel association word, one channel per - * nibble - * @return Returns the channel associated to the stream. - */ -#define STM32_DMA_GETCHANNEL(id, c) (((c) >> (((id) & 7) * 4)) & 7) - -/** - * @brief Checks if a DMA priority is within the valid range. - * @param[in] prio DMA priority - * - * @retval The check result. - * @retval FALSE invalid DMA priority. - * @retval TRUE correct DMA priority. - */ -#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3)) - -/** - * @brief Returns an unique numeric identifier for a DMA stream. - * - * @param[in] dma the DMA unit number - * @param[in] stream the stream number - * @return An unique numeric stream identifier. - */ -#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1) * 8) + (stream)) - -/** - * @brief Returns a DMA stream identifier mask. - * - * - * @param[in] dma the DMA unit number - * @param[in] stream the stream number - * @return A DMA stream identifier mask. - */ -#define STM32_DMA_STREAM_ID_MSK(dma, stream) \ - (1 << STM32_DMA_STREAM_ID(dma, stream)) - -/** - * @brief Checks if a DMA stream unique identifier belongs to a mask. - * @param[in] id the stream numeric identifier - * @param[in] mask the stream numeric identifiers mask - * - * @retval The check result. - * @retval FALSE id does not belong to the mask. - * @retval TRUE id belongs to the mask. - */ -#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask))) - -/** - * @name DMA streams identifiers - * @{ - */ -/** - * @brief Returns a pointer to a stm32_dma_stream_t structure. - * - * @param[in] id the stream numeric identifier - * @return A pointer to the stm32_dma_stream_t constant structure - * associated to the DMA stream. - */ -#define STM32_DMA_STREAM(id) (&_stm32_dma_streams[id]) - -#define STM32_DMA1_STREAM0 STM32_DMA_STREAM(0) -#define STM32_DMA1_STREAM1 STM32_DMA_STREAM(1) -#define STM32_DMA1_STREAM2 STM32_DMA_STREAM(2) -#define STM32_DMA1_STREAM3 STM32_DMA_STREAM(3) -#define STM32_DMA1_STREAM4 STM32_DMA_STREAM(4) -#define STM32_DMA1_STREAM5 STM32_DMA_STREAM(5) -#define STM32_DMA1_STREAM6 STM32_DMA_STREAM(6) -#define STM32_DMA1_STREAM7 STM32_DMA_STREAM(7) -#define STM32_DMA2_STREAM0 STM32_DMA_STREAM(8) -#define STM32_DMA2_STREAM1 STM32_DMA_STREAM(9) -#define STM32_DMA2_STREAM2 STM32_DMA_STREAM(10) -#define STM32_DMA2_STREAM3 STM32_DMA_STREAM(11) -#define STM32_DMA2_STREAM4 STM32_DMA_STREAM(12) -#define STM32_DMA2_STREAM5 STM32_DMA_STREAM(13) -#define STM32_DMA2_STREAM6 STM32_DMA_STREAM(14) -#define STM32_DMA2_STREAM7 STM32_DMA_STREAM(15) -/** @} */ - -/** - * @name CR register constants common to all DMA types - * @{ - */ -#define STM32_DMA_CR_EN DMA_SxCR_EN -#define STM32_DMA_CR_TEIE DMA_SxCR_TEIE -#define STM32_DMA_CR_HTIE DMA_SxCR_HTIE -#define STM32_DMA_CR_TCIE DMA_SxCR_TCIE -#define STM32_DMA_CR_DIR_MASK DMA_SxCR_DIR -#define STM32_DMA_CR_DIR_P2M 0 -#define STM32_DMA_CR_DIR_M2P DMA_SxCR_DIR_0 -#define STM32_DMA_CR_DIR_M2M DMA_SxCR_DIR_1 -#define STM32_DMA_CR_CIRC DMA_SxCR_CIRC -#define STM32_DMA_CR_PINC DMA_SxCR_PINC -#define STM32_DMA_CR_MINC DMA_SxCR_MINC -#define STM32_DMA_CR_PSIZE_MASK DMA_SxCR_PSIZE -#define STM32_DMA_CR_PSIZE_BYTE 0 -#define STM32_DMA_CR_PSIZE_HWORD DMA_SxCR_PSIZE_0 -#define STM32_DMA_CR_PSIZE_WORD DMA_SxCR_PSIZE_1 -#define STM32_DMA_CR_MSIZE_MASK DMA_SxCR_MSIZE -#define STM32_DMA_CR_MSIZE_BYTE 0 -#define STM32_DMA_CR_MSIZE_HWORD DMA_SxCR_MSIZE_0 -#define STM32_DMA_CR_MSIZE_WORD DMA_SxCR_MSIZE_1 -#define STM32_DMA_CR_SIZE_MASK (STM32_DMA_CR_PSIZE_MASK | \ - STM32_DMA_CR_MSIZE_MASK) -#define STM32_DMA_CR_PL_MASK DMA_SxCR_PL -#define STM32_DMA_CR_PL(n) ((n) << 16) -/** @} */ - -/** - * @name CR register constants only found in STM32F2xx/STM32F4xx - * @{ - */ -#define STM32_DMA_CR_DMEIE DMA_SxCR_DMEIE -#define STM32_DMA_CR_PFCTRL DMA_SxCR_PFCTRL -#define STM32_DMA_CR_PINCOS DMA_SxCR_PINCOS -#define STM32_DMA_CR_DBM DMA_SxCR_DBM -#define STM32_DMA_CR_CT DMA_SxCR_CT -#define STM32_DMA_CR_PBURST_MASK DMA_SxCR_PBURST -#define STM32_DMA_CR_PBURST_SINGLE 0 -#define STM32_DMA_CR_PBURST_INCR4 DMA_SxCR_PBURST_0 -#define STM32_DMA_CR_PBURST_INCR8 DMA_SxCR_PBURST_1 -#define STM32_DMA_CR_PBURST_INCR16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) -#define STM32_DMA_CR_MBURST_MASK DMA_SxCR_MBURST -#define STM32_DMA_CR_MBURST_SINGLE 0 -#define STM32_DMA_CR_MBURST_INCR4 DMA_SxCR_MBURST_0 -#define STM32_DMA_CR_MBURST_INCR8 DMA_SxCR_MBURST_1 -#define STM32_DMA_CR_MBURST_INCR16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) -#define STM32_DMA_CR_CHSEL_MASK DMA_SxCR_CHSEL -#define STM32_DMA_CR_CHSEL(n) ((n) << 25) -/** @} */ - -/** - * @name FCR register constants only found in STM32F2xx/STM32F4xx - * @{ - */ -#define STM32_DMA_FCR_FEIE DMA_SxFCR_FEIE -#define STM32_DMA_FCR_FS_MASK DMA_SxFCR_FS -#define STM32_DMA_FCR_DMDIS DMA_SxFCR_DMDIS -#define STM32_DMA_FCR_FTH_MASK DMA_SxFCR_FTH -#define STM32_DMA_FCR_FTH_1Q 0 -#define STM32_DMA_FCR_FTH_HALF DMA_SxFCR_FTH_0 -#define STM32_DMA_FCR_FTH_3Q DMA_SxFCR_FTH_1 -#define STM32_DMA_FCR_FTH_FULL (DMA_SxFCR_FTH_0 | DMA_SxFCR_FTH_1) -/** @} */ - -/** - * @name Status flags passed to the ISR callbacks - */ -#define STM32_DMA_ISR_FEIF DMA_LISR_FEIF0 -#define STM32_DMA_ISR_DMEIF DMA_LISR_DMEIF0 -#define STM32_DMA_ISR_TEIF DMA_LISR_TEIF0 -#define STM32_DMA_ISR_HTIF DMA_LISR_HTIF0 -#define STM32_DMA_ISR_TCIF DMA_LISR_TCIF0 -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief STM32 DMA stream descriptor structure. - */ -typedef struct { - DMA_Stream_TypeDef *stream; /**< @brief Associated DMA stream. */ - volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */ - uint8_t ishift; /**< @brief Bits offset in xIFCR - register. */ - uint8_t selfindex; /**< @brief Index to self in array. */ - uint8_t vector; /**< @brief Associated IRQ vector. */ -} stm32_dma_stream_t; - -/** - * @brief STM32 DMA ISR function type. - * - * @param[in] p parameter for the registered function - * @param[in] flags pre-shifted content of the xISR register, the bits - * are aligned to bit zero - */ -typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Associates a peripheral data register to a DMA stream. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] addr value to be written in the PAR register - * - * @special - */ -#define dmaStreamSetPeripheral(dmastp, addr) { \ - (dmastp)->stream->PAR = (uint32_t)(addr); \ -} - -/** - * @brief Associates a memory destination to a DMA stream. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] addr value to be written in the M0AR register - * - * @special - */ -#define dmaStreamSetMemory0(dmastp, addr) { \ - (dmastp)->stream->M0AR = (uint32_t)(addr); \ -} - -/** - * @brief Associates an alternate memory destination to a DMA stream. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] addr value to be written in the M1AR register - * - * @special - */ -#define dmaStreamSetMemory1(dmastp, addr) { \ - (dmastp)->stream->M1AR = (uint32_t)(addr); \ -} - -/** - * @brief Sets the number of transfers to be performed. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] size value to be written in the CNDTR register - * - * @special - */ -#define dmaStreamSetTransactionSize(dmastp, size) { \ - (dmastp)->stream->NDTR = (uint32_t)(size); \ -} - -/** - * @brief Returns the number of transfers to be performed. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @return The number of transfers to be performed. - * - * @special - */ -#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->stream->NDTR)) - -/** - * @brief Programs the stream mode settings. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] mode value to be written in the CR register - * - * @special - */ -#define dmaStreamSetMode(dmastp, mode) { \ - (dmastp)->stream->CR = (uint32_t)(mode); \ -} - -/** - * @brief Programs the stream FIFO settings. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] mode value to be written in the FCR register - * - * @special - */ -#define dmaStreamSetFIFO(dmastp, mode) { \ - (dmastp)->stream->FCR = (uint32_t)(mode); \ -} - -/** - * @brief DMA stream enable. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * - * @special - */ -#define dmaStreamEnable(dmastp) { \ - (dmastp)->stream->CR |= STM32_DMA_CR_EN; \ -} - -/** - * @brief DMA stream disable. - * @details The function disables the specified stream, waits for the disable - * operation to complete and then clears any pending interrupt. - * @note This function can be invoked in both ISR or thread context. - * @note Interrupts enabling flags are set to zero after this call, see - * bug 3607518. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * - * @special - */ -#define dmaStreamDisable(dmastp) { \ - (dmastp)->stream->CR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | \ - STM32_DMA_CR_TEIE | STM32_DMA_CR_DMEIE | \ - STM32_DMA_CR_EN); \ - while (((dmastp)->stream->CR & STM32_DMA_CR_EN) != 0) \ - ; \ - dmaStreamClearInterrupt(dmastp); \ -} - -/** - * @brief DMA stream interrupt sources clear. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * - * @special - */ -#define dmaStreamClearInterrupt(dmastp) { \ - *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \ -} - -/** - * @brief Starts a memory to memory operation using the specified stream. - * @note The default transfer data mode is "byte to byte" but it can be - * changed by specifying extra options in the @p mode parameter. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] mode value to be written in the CCR register, this value - * is implicitly ORed with: - * - @p STM32_DMA_CR_MINC - * - @p STM32_DMA_CR_PINC - * - @p STM32_DMA_CR_DIR_M2M - * - @p STM32_DMA_CR_EN - * . - * @param[in] src source address - * @param[in] dst destination address - * @param[in] n number of data units to copy - */ -#define dmaStartMemCopy(dmastp, mode, src, dst, n) { \ - dmaStreamSetPeripheral(dmastp, src); \ - dmaStreamSetMemory0(dmastp, dst); \ - dmaStreamSetTransactionSize(dmastp, n); \ - dmaStreamSetMode(dmastp, (mode) | \ - STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \ - STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); \ -} - -/** - * @brief Polled wait for DMA transfer end. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - */ -#define dmaWaitCompletion(dmastp) { \ - while ((dmastp)->stream->NDTR > 0) \ - ; \ - dmaStreamDisable(dmastp); \ -} -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS]; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void dmaInit(void); - bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, - uint32_t priority, - stm32_dmaisr_t func, - void *param); - void dmaStreamRelease(const stm32_dma_stream_t *dmastp); -#ifdef __cplusplus -} -#endif - -#endif /* _STM32_DMA_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32F4xx/stm32_isr.h b/firmware/chibios/os/hal/platforms/STM32F4xx/stm32_isr.h deleted file mode 100644 index e8f45b0acc..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F4xx/stm32_isr.h +++ /dev/null @@ -1,174 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F4xx/stm32_isr.h - * @brief ISR remapper driver header. - * - * @addtogroup STM32F4xx_ISR - * @{ - */ - -#ifndef _STM32_ISR_H_ -#define _STM32_ISR_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name ISR names and numbers remapping - * @{ - */ -/* - * CAN units. - */ -#define STM32_CAN1_TX_HANDLER Vector8C -#define STM32_CAN1_RX0_HANDLER Vector90 -#define STM32_CAN1_RX1_HANDLER Vector94 -#define STM32_CAN1_SCE_HANDLER Vector98 -#define STM32_CAN2_TX_HANDLER Vector13C -#define STM32_CAN2_RX0_HANDLER Vector140 -#define STM32_CAN2_RX1_HANDLER Vector144 -#define STM32_CAN2_SCE_HANDLER Vector148 - -#define STM32_CAN1_TX_NUMBER 19 -#define STM32_CAN1_RX0_NUMBER 20 -#define STM32_CAN1_RX1_NUMBER 21 -#define STM32_CAN1_SCE_NUMBER 22 -#define STM32_CAN2_TX_NUMBER 63 -#define STM32_CAN2_RX0_NUMBER 64 -#define STM32_CAN2_RX1_NUMBER 65 -#define STM32_CAN2_SCE_NUMBER 66 - -/* - * I2C units. - */ -#define STM32_I2C1_EVENT_HANDLER VectorBC -#define STM32_I2C1_ERROR_HANDLER VectorC0 -#define STM32_I2C1_EVENT_NUMBER 31 -#define STM32_I2C1_ERROR_NUMBER 32 - -#define STM32_I2C2_EVENT_HANDLER VectorC4 -#define STM32_I2C2_ERROR_HANDLER VectorC8 -#define STM32_I2C2_EVENT_NUMBER 33 -#define STM32_I2C2_ERROR_NUMBER 34 - -#define STM32_I2C3_EVENT_HANDLER Vector160 -#define STM32_I2C3_ERROR_HANDLER Vector164 -#define STM32_I2C3_EVENT_NUMBER 72 -#define STM32_I2C3_ERROR_NUMBER 73 - -/* - * OTG units. - */ -#define STM32_OTG1_HANDLER Vector14C -#define STM32_OTG2_HANDLER Vector174 -#define STM32_OTG2_EP1OUT_HANDLER Vector168 -#define STM32_OTG2_EP1IN_HANDLER Vector16C - -#define STM32_OTG1_NUMBER 67 -#define STM32_OTG2_NUMBER 77 -#define STM32_OTG2_EP1OUT_NUMBER 74 -#define STM32_OTG2_EP1IN_NUMBER 75 - -/* - * SDIO unit. - */ -#define STM32_SDIO_HANDLER Vector104 - -#define STM32_SDIO_NUMBER 49 - -/* - * TIM units. - */ -#define STM32_TIM1_UP_HANDLER VectorA4 -#define STM32_TIM1_CC_HANDLER VectorAC -#define STM32_TIM2_HANDLER VectorB0 -#define STM32_TIM3_HANDLER VectorB4 -#define STM32_TIM4_HANDLER VectorB8 -#define STM32_TIM5_HANDLER Vector108 -#define STM32_TIM6_HANDLER Vector118 -#define STM32_TIM7_HANDLER Vector11C -#define STM32_TIM8_UP_HANDLER VectorF0 -#define STM32_TIM8_CC_HANDLER VectorF8 -#define STM32_TIM9_HANDLER VectorA0 -#define STM32_TIM11_HANDLER VectorA8 -#define STM32_TIM12_HANDLER VectorEC -#define STM32_TIM14_HANDLER VectorF4 - -#define STM32_TIM1_UP_NUMBER 25 -#define STM32_TIM1_CC_NUMBER 27 -#define STM32_TIM2_NUMBER 28 -#define STM32_TIM3_NUMBER 29 -#define STM32_TIM4_NUMBER 30 -#define STM32_TIM5_NUMBER 50 -#define STM32_TIM6_NUMBER 54 -#define STM32_TIM7_NUMBER 55 -#define STM32_TIM8_UP_NUMBER 44 -#define STM32_TIM8_CC_NUMBER 46 -#define STM32_TIM9_NUMBER 24 -#define STM32_TIM11_NUMBER 26 -#define STM32_TIM12_NUMBER 43 -#define STM32_TIM14_NUMBER 45 - -/* - * USART units. - */ -#define STM32_USART1_HANDLER VectorD4 -#define STM32_USART2_HANDLER VectorD8 -#define STM32_USART3_HANDLER VectorDC -#define STM32_UART4_HANDLER Vector110 -#define STM32_UART5_HANDLER Vector114 -#define STM32_USART6_HANDLER Vector15C - -#define STM32_USART1_NUMBER 37 -#define STM32_USART2_NUMBER 38 -#define STM32_USART3_NUMBER 39 -#define STM32_UART4_NUMBER 52 -#define STM32_UART5_NUMBER 53 -#define STM32_USART6_NUMBER 71 - -/* - * Ethernet - */ -#define ETH_IRQHandler Vector134 - -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#endif /* _STM32_ISR_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32F4xx/stm32_rcc.h b/firmware/chibios/os/hal/platforms/STM32F4xx/stm32_rcc.h deleted file mode 100644 index 91fce72cbf..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F4xx/stm32_rcc.h +++ /dev/null @@ -1,1400 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F4xx/stm32_rcc.h - * @brief RCC helper driver header. - * @note This file requires definitions from the ST header file - * @p stm32f4xx.h. - * - * @addtogroup STM32F4xx_RCC - * @{ - */ -#ifndef _STM32_RCC_ -#define _STM32_RCC_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Generic RCC operations - * @{ - */ -/** - * @brief Enables the clock of one or more peripheral on the APB1 bus. - * - * @param[in] mask APB1 peripherals mask - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableAPB1(mask, lp) { \ - RCC->APB1ENR |= (mask); \ - if (lp) \ - RCC->APB1LPENR |= (mask); \ -} - -/** - * @brief Disables the clock of one or more peripheral on the APB1 bus. - * - * @param[in] mask APB1 peripherals mask - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableAPB1(mask, lp) { \ - RCC->APB1ENR &= ~(mask); \ - if (lp) \ - RCC->APB1LPENR &= ~(mask); \ -} - -/** - * @brief Resets one or more peripheral on the APB1 bus. - * - * @param[in] mask APB1 peripherals mask - * - * @api - */ -#define rccResetAPB1(mask) { \ - RCC->APB1RSTR |= (mask); \ - RCC->APB1RSTR = 0; \ -} - -/** - * @brief Enables the clock of one or more peripheral on the APB2 bus. - * - * @param[in] mask APB2 peripherals mask - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableAPB2(mask, lp) { \ - RCC->APB2ENR |= (mask); \ - if (lp) \ - RCC->APB2LPENR |= (mask); \ -} - -/** - * @brief Disables the clock of one or more peripheral on the APB2 bus. - * - * @param[in] mask APB2 peripherals mask - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableAPB2(mask, lp) { \ - RCC->APB2ENR &= ~(mask); \ - if (lp) \ - RCC->APB2LPENR &= ~(mask); \ -} - -/** - * @brief Resets one or more peripheral on the APB2 bus. - * - * @param[in] mask APB2 peripherals mask - * - * @api - */ -#define rccResetAPB2(mask) { \ - RCC->APB2RSTR |= (mask); \ - RCC->APB2RSTR = 0; \ -} - -/** - * @brief Enables the clock of one or more peripheral on the AHB1 bus. - * - * @param[in] mask AHB1 peripherals mask - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableAHB1(mask, lp) { \ - RCC->AHB1ENR |= (mask); \ - if (lp) \ - RCC->AHB1LPENR |= (mask); \ -} - -/** - * @brief Disables the clock of one or more peripheral on the AHB1 bus. - * - * @param[in] mask AHB1 peripherals mask - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableAHB1(mask, lp) { \ - RCC->AHB1ENR &= ~(mask); \ - if (lp) \ - RCC->AHB1LPENR &= ~(mask); \ -} - -/** - * @brief Resets one or more peripheral on the AHB1 bus. - * - * @param[in] mask AHB1 peripherals mask - * - * @api - */ -#define rccResetAHB1(mask) { \ - RCC->AHB1RSTR |= (mask); \ - RCC->AHB1RSTR = 0; \ -} - -/** - * @brief Enables the clock of one or more peripheral on the AHB2 bus. - * - * @param[in] mask AHB2 peripherals mask - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableAHB2(mask, lp) { \ - RCC->AHB2ENR |= (mask); \ - if (lp) \ - RCC->AHB2LPENR |= (mask); \ -} - -/** - * @brief Disables the clock of one or more peripheral on the AHB2 bus. - * - * @param[in] mask AHB2 peripherals mask - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableAHB2(mask, lp) { \ - RCC->AHB2ENR &= ~(mask); \ - if (lp) \ - RCC->AHB2LPENR &= ~(mask); \ -} - -/** - * @brief Resets one or more peripheral on the AHB2 bus. - * - * @param[in] mask AHB2 peripherals mask - * - * @api - */ -#define rccResetAHB2(mask) { \ - RCC->AHB2RSTR |= (mask); \ - RCC->AHB2RSTR = 0; \ -} - -/** - * @brief Enables the clock of one or more peripheral on the AHB3 (FSMC) bus. - * - * @param[in] mask AHB3 peripherals mask - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableAHB3(mask, lp) { \ - RCC->AHB3ENR |= (mask); \ - if (lp) \ - RCC->AHB3LPENR |= (mask); \ -} - -/** - * @brief Disables the clock of one or more peripheral on the AHB3 (FSMC) bus. - * - * @param[in] mask AHB3 peripherals mask - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableAHB3(mask, lp) { \ - RCC->AHB3ENR &= ~(mask); \ - if (lp) \ - RCC->AHB3LPENR &= ~(mask); \ -} - -/** - * @brief Resets one or more peripheral on the AHB3 (FSMC) bus. - * - * @param[in] mask AHB3 peripherals mask - * - * @api - */ -#define rccResetAHB3(mask) { \ - RCC->AHB3RSTR |= (mask); \ - RCC->AHB3RSTR = 0; \ -} -/** @} */ - -/** - * @name ADC peripherals specific RCC operations - * @{ - */ -/** - * @brief Enables the ADC1 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp) - -/** - * @brief Disables the ADC1 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableADC1(lp) rccDisableAPB2(RCC_APB2ENR_ADC1EN, lp) - -/** - * @brief Resets the ADC1 peripheral. - * - * @api - */ -#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST) - -/** - * @brief Enables the ADC2 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableADC2(lp) rccEnableAPB2(RCC_APB2ENR_ADC2EN, lp) - -/** - * @brief Disables the ADC2 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableADC2(lp) rccDisableAPB2(RCC_APB2ENR_ADC2EN, lp) - -/** - * @brief Resets the ADC2 peripheral. - * - * @api - */ -#define rccResetADC2() rccResetAPB2(RCC_APB2RSTR_ADC2RST) - -/** - * @brief Enables the ADC3 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableADC3(lp) rccEnableAPB2(RCC_APB2ENR_ADC3EN, lp) - -/** - * @brief Disables the ADC3 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableADC3(lp) rccDisableAPB2(RCC_APB2ENR_ADC3EN, lp) - -/** - * @brief Resets the ADC3 peripheral. - * - * @api - */ -#define rccResetADC3() rccResetAPB2(RCC_APB2RSTR_ADC3RST) -/** @} */ - -/** - * @name DMA peripheral specific RCC operations - * @{ - */ -/** - * @brief Enables the DMA1 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableDMA1(lp) rccEnableAHB1(RCC_AHB1ENR_DMA1EN, lp) - -/** - * @brief Disables the DMA1 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableDMA1(lp) rccDisableAHB1(RCC_AHB1ENR_DMA1EN, lp) - -/** - * @brief Resets the DMA1 peripheral. - * - * @api - */ -#define rccResetDMA1() rccResetAHB1(RCC_AHB1RSTR_DMA1RST) - -/** - * @brief Enables the DMA2 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableDMA2(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2EN, lp) - -/** - * @brief Disables the DMA2 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableDMA2(lp) rccDisableAHB1(RCC_AHB1ENR_DMA2EN, lp) - -/** - * @brief Resets the DMA2 peripheral. - * - * @api - */ -#define rccResetDMA2() rccResetAHB1(RCC_AHB1RSTR_DMA2RST) -/** @} */ - -/** - * @name BKPSRAM specific RCC operations - * @{ - */ -/** - * @brief Enables the BKPSRAM peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableBKPSRAM(lp) rccEnableAHB1(RCC_AHB1ENR_BKPSRAMEN, lp) - -/** - * @brief Disables the BKPSRAM peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableBKPSRAM(lp) rccDisableAHB1(RCC_AHB1ENR_BKPSRAMEN, lp) -/** @} */ - -/** - * @name PWR interface specific RCC operations - * @{ - */ -/** - * @brief Enables the PWR interface clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp) - -/** - * @brief Disables PWR interface clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp) - -/** - * @brief Resets the PWR interface. - * - * @api - */ -#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST) -/** @} */ - - -/** - * @name CAN peripherals specific RCC operations - * @{ - */ -/** - * @brief Enables the CAN1 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableCAN1(lp) rccEnableAPB1(RCC_APB1ENR_CAN1EN, lp) - -/** - * @brief Disables the CAN1 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableCAN1(lp) rccDisableAPB1(RCC_APB1ENR_CAN1EN, lp) - -/** - * @brief Resets the CAN1 peripheral. - * - * @api - */ -#define rccResetCAN1() rccResetAPB1(RCC_APB1RSTR_CAN1RST) - -/** - * @brief Enables the CAN2 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableCAN2(lp) rccEnableAPB1(RCC_APB1ENR_CAN2EN, lp) - -/** - * @brief Disables the CAN2 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableCAN2(lp) rccDisableAPB1(RCC_APB1ENR_CAN2EN, lp) - -/** - * @brief Resets the CAN2 peripheral. - * - * @api - */ -#define rccResetCAN2() rccResetAPB1(RCC_APB1RSTR_CAN2RST) -/** @} */ - -/** - * @name ETH peripheral specific RCC operations - * @{ - */ -/** - * @brief Enables the ETH peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableETH(lp) rccEnableAHB1(RCC_AHB1ENR_ETHMACEN | \ - RCC_AHB1ENR_ETHMACTXEN | \ - RCC_AHB1ENR_ETHMACRXEN, lp) - -/** - * @brief Disables the ETH peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableETH(lp) rccDisableAHB1(RCC_AHB1ENR_ETHMACEN | \ - RCC_AHB1ENR_ETHMACTXEN | \ - RCC_AHB1ENR_ETHMACRXEN, lp) - -/** - * @brief Resets the ETH peripheral. - * - * @api - */ -#define rccResetETH() rccResetAHB1(RCC_AHB1RSTR_ETHMACRST) -/** @} */ - -/** - * @name I2C peripherals specific RCC operations - * @{ - */ -/** - * @brief Enables the I2C1 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp) - -/** - * @brief Disables the I2C1 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableI2C1(lp) rccDisableAPB1(RCC_APB1ENR_I2C1EN, lp) - -/** - * @brief Resets the I2C1 peripheral. - * - * @api - */ -#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST) - -/** - * @brief Enables the I2C2 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp) - -/** - * @brief Disables the I2C2 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableI2C2(lp) rccDisableAPB1(RCC_APB1ENR_I2C2EN, lp) - -/** - * @brief Resets the I2C2 peripheral. - * - * @api - */ -#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST) - -/** - * @brief Enables the I2C3 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableI2C3(lp) rccEnableAPB1(RCC_APB1ENR_I2C3EN, lp) - -/** - * @brief Disables the I2C3 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableI2C3(lp) rccDisableAPB1(RCC_APB1ENR_I2C3EN, lp) - -/** - * @brief Resets the I2C3 peripheral. - * - * @api - */ -#define rccResetI2C3() rccResetAPB1(RCC_APB1RSTR_I2C3RST) -/** @} */ - -/** - * @name OTG peripherals specific RCC operations - * @{ - */ -/** - * @brief Enables the OTG_FS peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableOTG_FS(lp) rccEnableAHB2(RCC_AHB2ENR_OTGFSEN, lp) - -/** - * @brief Disables the OTG_FS peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableOTG_FS(lp) rccDisableAHB2(RCC_AHB2ENR_OTGFSEN, lp) - -/** - * @brief Resets the OTG_FS peripheral. - * - * @api - */ -#define rccResetOTG_FS() rccResetAHB2(RCC_AHB2RSTR_OTGFSRST) - -/** - * @brief Enables the OTG_HS peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableOTG_HS(lp) rccEnableAHB1(RCC_AHB1ENR_OTGHSEN, lp) - -/** - * @brief Disables the OTG_HS peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableOTG_HS(lp) rccDisableAHB1(RCC_AHB1ENR_OTGHSEN, lp) - -/** - * @brief Resets the OTG_HS peripheral. - * - * @api - */ -#define rccResetOTG_HS() rccResetAHB1(RCC_AHB1RSTR_OTGHSRST) - -/** - * @brief Enables the OTG_HS peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableOTG_HSULPI(lp) rccEnableAHB1(RCC_AHB1ENR_OTGHSULPIEN, lp) - -/** - * @brief Disables the OTG_HS peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableOTG_HSULPI(lp) rccDisableAHB1(RCC_AHB1ENR_OTGHSULPIEN, lp) -/** @} */ - -/** - * @name SDIO peripheral specific RCC operations - * @{ - */ -/** - * @brief Enables the SDIO peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableSDIO(lp) rccEnableAPB2(RCC_APB2ENR_SDIOEN, lp) - -/** - * @brief Disables the SDIO peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableSDIO(lp) rccDisableAPB2(RCC_APB2ENR_SDIOEN, lp) - -/** - * @brief Resets the SDIO peripheral. - * @note Not supported in this family, does nothing. - * - * @api - */ -#define rccResetSDIO() rccResetAPB2(RCC_APB2RSTR_SDIORST) -/** @} */ - -/** - * @name SPI peripherals specific RCC operations - * @{ - */ -/** - * @brief Enables the SPI1 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp) - -/** - * @brief Disables the SPI1 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp) - -/** - * @brief Resets the SPI1 peripheral. - * - * @api - */ -#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST) - -/** - * @brief Enables the SPI2 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp) - -/** - * @brief Disables the SPI2 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableSPI2(lp) rccDisableAPB1(RCC_APB1ENR_SPI2EN, lp) - -/** - * @brief Resets the SPI2 peripheral. - * - * @api - */ -#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST) - -/** - * @brief Enables the SPI3 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableSPI3(lp) rccEnableAPB1(RCC_APB1ENR_SPI3EN, lp) - -/** - * @brief Disables the SPI3 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableSPI3(lp) rccDisableAPB1(RCC_APB1ENR_SPI3EN, lp) - -/** - * @brief Resets the SPI3 peripheral. - * - * @api - */ -#define rccResetSPI3() rccResetAPB1(RCC_APB1RSTR_SPI3RST) - -/** - * @brief Enables the SPI4 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableSPI4(lp) rccEnableAPB2(RCC_APB2ENR_SPI4EN, lp) - -/** - * @brief Disables the SPI4 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableSPI4(lp) rccDisableAPB2(RCC_APB2ENR_SPI4EN, lp) - -/** - * @brief Resets the SPI4 peripheral. - * - * @api - */ -#define rccResetSPI4() rccResetAPB2(RCC_APB2RSTR_SPI4RST) - -/** - * @brief Enables the SPI5 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableSPI5(lp) rccEnableAPB2(RCC_APB2ENR_SPI5EN, lp) - -/** - * @brief Disables the SPI5 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableSPI5(lp) rccDisableAPB2(RCC_APB2ENR_SPI5EN, lp) - -/** - * @brief Resets the SPI5 peripheral. - * - * @api - */ -#define rccResetSPI5() rccResetAPB2(RCC_APB2RSTR_SPI5RST) - -/** - * @brief Enables the SPI6 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableSPI6(lp) rccEnableAPB2(RCC_APB2ENR_SPI6EN, lp) - -/** - * @brief Disables the SPI6 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableSPI6(lp) rccDisableAPB2(RCC_APB2ENR_SPI6EN, lp) - -/** - * @brief Resets the SPI6 peripheral. - * - * @api - */ -#define rccResetSPI6() rccResetAPB2(RCC_APB2RSTR_SPI6RST) -/** @} */ - -/** - * @name TIM peripherals specific RCC operations - * @{ - */ -/** - * @brief Enables the TIM1 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp) - -/** - * @brief Disables the TIM1 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM1(lp) rccDisableAPB2(RCC_APB2ENR_TIM1EN, lp) - -/** - * @brief Resets the TIM1 peripheral. - * - * @api - */ -#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST) - -/** - * @brief Enables the TIM2 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp) - -/** - * @brief Disables the TIM2 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp) - -/** - * @brief Resets the TIM2 peripheral. - * - * @api - */ -#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST) - -/** - * @brief Enables the TIM3 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp) - -/** - * @brief Disables the TIM3 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp) - -/** - * @brief Resets the TIM3 peripheral. - * - * @api - */ -#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST) - -/** - * @brief Enables the TIM4 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM4(lp) rccEnableAPB1(RCC_APB1ENR_TIM4EN, lp) - -/** - * @brief Disables the TIM4 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM4(lp) rccDisableAPB1(RCC_APB1ENR_TIM4EN, lp) - -/** - * @brief Resets the TIM4 peripheral. - * - * @api - */ -#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST) - -/** - * @brief Enables the TIM5 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM5(lp) rccEnableAPB1(RCC_APB1ENR_TIM5EN, lp) - -/** - * @brief Disables the TIM5 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM5(lp) rccDisableAPB1(RCC_APB1ENR_TIM5EN, lp) - -/** - * @brief Resets the TIM5 peripheral. - * - * @api - */ -#define rccResetTIM5() rccResetAPB1(RCC_APB1RSTR_TIM5RST) - -/** - * @brief Enables the TIM6 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM6(lp) rccEnableAPB1(RCC_APB1ENR_TIM6EN, lp) - -/** - * @brief Disables the TIM6 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM6(lp) rccDisableAPB1(RCC_APB1ENR_TIM6EN, lp) - -/** - * @brief Resets the TIM6 peripheral. - * - * @api - */ -#define rccResetTIM6() rccResetAPB1(RCC_APB1RSTR_TIM6RST) - -/** - * @brief Enables the TIM7 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM7(lp) rccEnableAPB1(RCC_APB1ENR_TIM7EN, lp) - -/** - * @brief Disables the TIM7 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM7(lp) rccDisableAPB1(RCC_APB1ENR_TIM7EN, lp) - -/** - * @brief Resets the TIM7 peripheral. - * - * @api - */ -#define rccResetTIM7() rccResetAPB1(RCC_APB1RSTR_TIM7RST) - -/** - * @brief Enables the TIM8 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM8(lp) rccEnableAPB2(RCC_APB2ENR_TIM8EN, lp) - -/** - * @brief Disables the TIM8 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM8(lp) rccDisableAPB2(RCC_APB2ENR_TIM8EN, lp) - -/** - * @brief Resets the TIM8 peripheral. - * - * @api - */ -#define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST) - -/** - * @brief Enables the TIM9peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM9(lp) rccEnableAPB2(RCC_APB2ENR_TIM9EN, lp) - -/** - * @brief Disables the TIM9 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM9(lp) rccDisableAPB2(RCC_APB2ENR_TIM9EN, lp) - -/** - * @brief Resets the TIM9 peripheral. - * - * @api - */ -#define rccResetTIM9() rccResetAPB2(RCC_APB2RSTR_TIM9RST) - -/** - * @brief Enables the TIM11 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM11(lp) rccEnableAPB2(RCC_APB2ENR_TIM11EN, lp) - -/** - * @brief Disables the TIM11 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM11(lp) rccDisableAPB2(RCC_APB2ENR_TIM11EN, lp) - -/** - * @brief Resets the TIM11 peripheral. - * - * @api - */ -#define rccResetTIM11() rccResetAPB2(RCC_APB2RSTR_TIM11RST) - -/** - * @brief Enables the TIM12 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM12(lp) rccEnableAPB1(RCC_APB1ENR_TIM12EN, lp) - -/** - * @brief Disables the TIM12 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM12(lp) rccDisableAPB1(RCC_APB1ENR_TIM12EN, lp) - -/** - * @brief Resets the TIM12 peripheral. - * - * @api - */ -#define rccResetTIM12() rccResetAPB1(RCC_APB1RSTR_TIM12RST) - -/** - * @brief Enables the TIM14 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM14(lp) rccEnableAPB1(RCC_APB1ENR_TIM14EN, lp) - -/** - * @brief Disables the TIM14 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM14(lp) rccDisableAPB1(RCC_APB1ENR_TIM14EN, lp) - -/** - * @brief Resets the TIM14 peripheral. - * - * @api - */ -#define rccResetTIM14() rccResetAPB1(RCC_APB1RSTR_TIM14RST) -/** @} */ - -/** - * @name USART/UART peripherals specific RCC operations - * @{ - */ -/** - * @brief Enables the USART1 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp) - -/** - * @brief Disables the USART1 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp) - -/** - * @brief Resets the USART1 peripheral. - * - * @api - */ -#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST) - -/** - * @brief Enables the USART2 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp) - -/** - * @brief Disables the USART2 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableUSART2(lp) rccDisableAPB1(RCC_APB1ENR_USART2EN, lp) - -/** - * @brief Resets the USART2 peripheral. - * - * @api - */ -#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST) - -/** - * @brief Enables the USART3 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp) - -/** - * @brief Disables the USART3 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableUSART3(lp) rccDisableAPB1(RCC_APB1ENR_USART3EN, lp) - -/** - * @brief Resets the USART3 peripheral. - * - * @api - */ -#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST) - -/** - * @brief Enables the USART6 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableUSART6(lp) rccEnableAPB2(RCC_APB2ENR_USART6EN, lp) - -/** - * @brief Disables the USART6 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableUSART6(lp) rccDisableAPB2(RCC_APB2ENR_USART6EN, lp) - -/** - * @brief Enables the UART4 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableUART4(lp) rccEnableAPB1(RCC_APB1ENR_UART4EN, lp) - -/** - * @brief Disables the UART4 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableUART4(lp) rccDisableAPB1(RCC_APB1ENR_UART4EN, lp) - -/** - * @brief Resets the UART4 peripheral. - * - * @api - */ -#define rccResetUART4() rccResetAPB1(RCC_APB1RSTR_UART4RST) - -/** - * @brief Enables the UART5 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableUART5(lp) rccEnableAPB1(RCC_APB1ENR_UART5EN, lp) - -/** - * @brief Disables the UART5 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableUART5(lp) rccDisableAPB1(RCC_APB1ENR_UART5EN, lp) - -/** - * @brief Resets the UART5 peripheral. - * - * @api - */ -#define rccResetUART5() rccResetAPB1(RCC_APB1RSTR_UART5RST) - -/** - * @brief Resets the USART6 peripheral. - * - * @api - */ -#define rccResetUSART6() rccResetAPB2(RCC_APB2RSTR_USART6RST) -/** @} */ - -/** - * @name LTDC peripheral specific RCC operations - * @{ - */ -/** - * @brief Enables the LTDC peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableLTDC(lp) rccEnableAPB2(RCC_APB2ENR_LTDCEN, lp) - -/** - * @brief Disables the LTDC peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableLTDC(lp) rccDisableAPB2(RCC_APB2ENR_LTDCEN, lp) - -/** - * @brief Resets the LTDC peripheral. - * - * @api - */ -#define rccResetLTDC() rccResetAPB2(RCC_APB2RSTR_LTDCRST) -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif -#ifdef __cplusplus -} -#endif - -#endif /* _STM32_RCC_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/STM32F4xx/stm32f2xx.h b/firmware/chibios/os/hal/platforms/STM32F4xx/stm32f2xx.h deleted file mode 100644 index df82254bc4..0000000000 --- a/firmware/chibios/os/hal/platforms/STM32F4xx/stm32f2xx.h +++ /dev/null @@ -1,6881 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx.h - * @author MCD Application Team - * @version V1.0.0 - * @date 18-April-2011 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. - * This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for STM32F2xx devices. - * - * The file is the unique include file that the application programmer - * is using in the C source code, usually in main.c. This file contains: - * - Configuration section that allows to select: - * - The device used in the target application - * - To use or not the peripheral�s drivers in application code(i.e. - * code will be based on direct access to peripheral�s registers - * rather than drivers API), this option is controlled by - * "#define USE_STDPERIPH_DRIVER" - * - To change few application-specific parameters such as the HSE - * crystal frequency - * - Data structures and the address mapping for all peripherals - * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral�s registers hardware - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f2xx - * @{ - */ - -#ifndef __STM32F2xx_H -#define __STM32F2xx_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Library_configuration_section - * @{ - */ - -/* Uncomment the line below according to the target STM32 device used in your - application - */ - -#if !defined (STM32F2XX) - #define STM32F2XX -#endif - -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - */ - -#if !defined (STM32F2XX) - #error "Please select first the target STM32F2XX device used in your application (in stm32f2xx.h file)" -#endif - -#if !defined (USE_STDPERIPH_DRIVER) -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - /*#define USE_STDPERIPH_DRIVER*/ -#endif /* USE_STDPERIPH_DRIVER */ - -/** - * @brief In the following line adjust the value of External High Speed oscillator (HSE) - used in your application - - Tip: To avoid modifying this file each time you need to use different HSE, you - can define the HSE value in your toolchain compiler preprocessor. - */ -#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ - -/** - * @brief In the following line adjust the External High Speed oscillator (HSE) Startup - Timeout value - */ -#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ -#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ - -/** - * @brief STM32F2Xxx Standard Peripherals Library version number V1.0.0 - */ -#define __STM32F2XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32F2XX_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ -#define __STM32F2XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __STM32F2XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32F2XX_STDPERIPH_VERSION ((__STM32F2XX_STDPERIPH_VERSION_MAIN << 24)\ - |(__STM32F2XX_STDPERIPH_VERSION_SUB1 << 16)\ - |(__STM32F2XX_STDPERIPH_VERSION_SUB2 << 8)\ - |(__STM32F2XX_STDPERIPH_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ - -/** - * @brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ -#define __MPU_PRESENT 1 /*!< STM32F2XX provide an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< STM32F2XX uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * @brief STM32F2XX Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ****************************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ -/****** STM32 specific Interrupt Numbers **********************************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ - RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ - DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ - DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ - DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ - DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ - DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ - DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ - ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ - CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ - CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ - TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ - TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ - TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ - TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ - TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ - FSMC_IRQn = 48, /*!< FSMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ - TIM7_IRQn = 55, /*!< TIM7 global interrupt */ - DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ - DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ - DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ - DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ - DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ - ETH_IRQn = 61, /*!< Ethernet global Interrupt */ - ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ - CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ - CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ - CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ - CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ - OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ - DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ - DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ - DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ - USART6_IRQn = 71, /*!< USART6 global interrupt */ - I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ - I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ - OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ - OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ - OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ - OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ - DCMI_IRQn = 78, /*!< DCMI global interrupt */ - CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ - HASH_RNG_IRQn = 80 /*!< Hash and Rng global interrupt */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm3.h" -/* CHIBIOS FIX */ -/* #include "system_stm32f2xx.h" */ -#include - -/** @addtogroup Exported_types - * @{ - */ -/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ -typedef int32_t s32; -typedef int16_t s16; -typedef int8_t s8; - -typedef const int32_t sc32; /*!< Read Only */ -typedef const int16_t sc16; /*!< Read Only */ -typedef const int8_t sc8; /*!< Read Only */ - -typedef __IO int32_t vs32; -typedef __IO int16_t vs16; -typedef __IO int8_t vs8; - -typedef __I int32_t vsc32; /*!< Read Only */ -typedef __I int16_t vsc16; /*!< Read Only */ -typedef __I int8_t vsc8; /*!< Read Only */ - -typedef uint32_t u32; -typedef uint16_t u16; -typedef uint8_t u8; - -typedef const uint32_t uc32; /*!< Read Only */ -typedef const uint16_t uc16; /*!< Read Only */ -typedef const uint8_t uc8; /*!< Read Only */ - -typedef __IO uint32_t vu32; -typedef __IO uint16_t vu16; -typedef __IO uint8_t vu8; - -typedef __I uint32_t vuc32; /*!< Read Only */ -typedef __I uint16_t vuc16; /*!< Read Only */ -typedef __I uint8_t vuc8; /*!< Read Only */ - -typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; - -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; - -/** - * @} - */ - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ - __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ - __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ - __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ - __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ - __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ - __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ - __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ - __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ - __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ - __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ - __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ - __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ - __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ - __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ - __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ - __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ - __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ - __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual - AND triple modes, Address offset: ADC1 base address + 0x308 */ -} ADC_Common_TypeDef; - - -/** - * @brief Controller Area Network TxMailBox - */ - -typedef struct -{ - __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ - __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ - __IO uint32_t TDLR; /*!< CAN mailbox data low register */ - __IO uint32_t TDHR; /*!< CAN mailbox data high register */ -} CAN_TxMailBox_TypeDef; - -/** - * @brief Controller Area Network FIFOMailBox - */ - -typedef struct -{ - __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ - __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ - __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ - __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ -} CAN_FIFOMailBox_TypeDef; - -/** - * @brief Controller Area Network FilterRegister - */ - -typedef struct -{ - __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ - __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ -} CAN_FilterRegister_TypeDef; - -/** - * @brief Controller Area Network - */ - -typedef struct -{ - __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ - __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ - __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ - __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ - __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ - __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ - __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ - __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ - uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ - CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ - uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ - __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ - __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ - uint32_t RESERVED2; /*!< Reserved, 0x208 */ - __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ - uint32_t RESERVED3; /*!< Reserved, 0x210 */ - __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ - uint32_t RESERVED4; /*!< Reserved, 0x218 */ - __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ - uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ - CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ -} CAN_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - uint8_t RESERVED0; /*!< Reserved, 0x05 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -} CRC_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DCMI - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ - __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ - __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ - __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ - __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ - __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ - __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ - __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ - __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ - __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ - __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ -} DCMI_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DMA stream x configuration register */ - __IO uint32_t NDTR; /*!< DMA stream x number of data register */ - __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ - __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ - __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ - __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ -} DMA_Stream_TypeDef; - -typedef struct -{ - __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ - __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ - __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ - __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ -} DMA_TypeDef; - -/** - * @brief Ethernet MAC - */ - -typedef struct -{ - __IO uint32_t MACCR; - __IO uint32_t MACFFR; - __IO uint32_t MACHTHR; - __IO uint32_t MACHTLR; - __IO uint32_t MACMIIAR; - __IO uint32_t MACMIIDR; - __IO uint32_t MACFCR; - __IO uint32_t MACVLANTR; /* 8 */ - uint32_t RESERVED0[2]; - __IO uint32_t MACRWUFFR; /* 11 */ - __IO uint32_t MACPMTCSR; - uint32_t RESERVED1[2]; - __IO uint32_t MACSR; /* 15 */ - __IO uint32_t MACIMR; - __IO uint32_t MACA0HR; - __IO uint32_t MACA0LR; - __IO uint32_t MACA1HR; - __IO uint32_t MACA1LR; - __IO uint32_t MACA2HR; - __IO uint32_t MACA2LR; - __IO uint32_t MACA3HR; - __IO uint32_t MACA3LR; /* 24 */ - uint32_t RESERVED2[40]; - __IO uint32_t MMCCR; /* 65 */ - __IO uint32_t MMCRIR; - __IO uint32_t MMCTIR; - __IO uint32_t MMCRIMR; - __IO uint32_t MMCTIMR; /* 69 */ - uint32_t RESERVED3[14]; - __IO uint32_t MMCTGFSCCR; /* 84 */ - __IO uint32_t MMCTGFMSCCR; - uint32_t RESERVED4[5]; - __IO uint32_t MMCTGFCR; - uint32_t RESERVED5[10]; - __IO uint32_t MMCRFCECR; - __IO uint32_t MMCRFAECR; - uint32_t RESERVED6[10]; - __IO uint32_t MMCRGUFCR; - uint32_t RESERVED7[334]; - __IO uint32_t PTPTSCR; - __IO uint32_t PTPSSIR; - __IO uint32_t PTPTSHR; - __IO uint32_t PTPTSLR; - __IO uint32_t PTPTSHUR; - __IO uint32_t PTPTSLUR; - __IO uint32_t PTPTSAR; - __IO uint32_t PTPTTHR; - __IO uint32_t PTPTTLR; - __IO uint32_t RESERVED8; - __IO uint32_t PTPTSSR; /* added for STM32F2xx */ - uint32_t RESERVED9[565]; - __IO uint32_t DMABMR; - __IO uint32_t DMATPDR; - __IO uint32_t DMARPDR; - __IO uint32_t DMARDLAR; - __IO uint32_t DMATDLAR; - __IO uint32_t DMASR; - __IO uint32_t DMAOMR; - __IO uint32_t DMAIER; - __IO uint32_t DMAMFBOCR; - __IO uint32_t DMARSWTR; /* added for STM32F2xx */ - uint32_t RESERVED10[8]; - __IO uint32_t DMACHTDR; - __IO uint32_t DMACHRDR; - __IO uint32_t DMACHTBAR; - __IO uint32_t DMACHRBAR; -} ETH_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ - __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ - __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ - __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ - __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ - __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ -} EXTI_TypeDef; - -/** - * @brief FLASH Registers - */ - -typedef struct -{ - __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ - __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ - __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ - __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ - __IO uint32_t OPTCR; /*!< FLASH option control register, Address offset: 0x14 */ -} FLASH_TypeDef; - -/** - * @brief Flexible Static Memory Controller - */ - -typedef struct -{ - __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ -} FSMC_Bank1_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank1E - */ - -typedef struct -{ - __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ -} FSMC_Bank1E_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank2 - */ - -typedef struct -{ - __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ - __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ - __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ - __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ - uint32_t RESERVED0; /*!< Reserved, 0x70 */ - __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ -} FSMC_Bank2_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank3 - */ - -typedef struct -{ - __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ - __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ - __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ - __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ - uint32_t RESERVED0; /*!< Reserved, 0x90 */ - __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ -} FSMC_Bank3_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank4 - */ - -typedef struct -{ - __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ - __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ - __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ - __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ - __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ -} FSMC_Bank4_TypeDef; - -/** - * @brief General Purpose I/O - */ -/* CHIBIOS FIX */ -#if 0 -typedef struct -{ - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ - __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x24-0x28 */ -} GPIO_TypeDef; -#endif - -/** - * @brief System configuration controller - */ - -typedef struct -{ - __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ - __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ - __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ - uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ - __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ -} SYSCFG_TypeDef; - -/** - * @brief Inter-integrated Circuit Interface - */ - -typedef struct -{ - __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ - __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ - uint16_t RESERVED7; /*!< Reserved, 0x1E */ - __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ - uint16_t RESERVED8; /*!< Reserved, 0x22 */ -} I2C_TypeDef; - -/** - * @brief Independent WATCHDOG - */ - -typedef struct -{ - __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ - __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ - __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ -} IWDG_TypeDef; - -/** - * @brief Power Control - */ - -typedef struct -{ - __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ - __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ -} PWR_TypeDef; - -/** - * @brief Reset and Clock Control - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ - __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ - __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ - __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ - __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ - __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ - __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ - uint32_t RESERVED0; /*!< Reserved, 0x1C */ - __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ - __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ - uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ - __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ - __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ - __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ - uint32_t RESERVED2; /*!< Reserved, 0x3C */ - __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ - __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ - uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ - __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ - __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ - __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ - uint32_t RESERVED4; /*!< Reserved, 0x5C */ - __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ - __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ - uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ - __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ - __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ - uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ - __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ - __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ -} RCC_TypeDef; - -/** - * @brief Real-Time Clock - */ - -typedef struct -{ - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ - __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - uint32_t RESERVED1; /*!< Reserved, 0x28 */ - uint32_t RESERVED2; /*!< Reserved, 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - uint32_t RESERVED3; /*!< Reserved, 0x38 */ - uint32_t RESERVED4; /*!< Reserved, 0x3C */ - __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ - uint32_t RESERVED5; /*!< Reserved, 0x44 */ - uint32_t RESERVED6; /*!< Reserved, 0x48 */ - uint32_t RESERVED7; /*!< Reserved, 0x4C */ - __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ - __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ - __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ - __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ - __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ - __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ - __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ - __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ - __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ - __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ - __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ - __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ - __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ - __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ - __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ - __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ - __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ - __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ - __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ - __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ -} RTC_TypeDef; - -/** - * @brief SD host Interface - */ - -typedef struct -{ - __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ - __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ - __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ - __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ - __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ - __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ - __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ - __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ - __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ - __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ - __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ - __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ - __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ - __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ - __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ - __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ - uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ - __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ - uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ - __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ -} SDIO_TypeDef; - -/** - * @brief Serial Peripheral Interface - */ - -typedef struct -{ - __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ - __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ - uint16_t RESERVED7; /*!< Reserved, 0x1E */ - __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ - uint16_t RESERVED8; /*!< Reserved, 0x22 */ -} SPI_TypeDef; - -/** - * @brief TIM - */ - -typedef struct -{ - __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ - __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ - uint16_t RESERVED7; /*!< Reserved, 0x1E */ - __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ - uint16_t RESERVED8; /*!< Reserved, 0x22 */ - __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - uint16_t RESERVED9; /*!< Reserved, 0x2A */ - __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - uint16_t RESERVED10; /*!< Reserved, 0x32 */ - __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ - __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ - __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ - __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ - __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - uint16_t RESERVED11; /*!< Reserved, 0x46 */ - __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - uint16_t RESERVED12; /*!< Reserved, 0x4A */ - __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - uint16_t RESERVED13; /*!< Reserved, 0x4E */ - __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */ - uint16_t RESERVED14; /*!< Reserved, 0x52 */ -} TIM_TypeDef; - -/** - * @brief Universal Synchronous Asynchronous Receiver Transmitter - */ - -typedef struct -{ - __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ -} USART_TypeDef; - -/** - * @brief Window WATCHDOG - */ - -typedef struct -{ - __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ - __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ - __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ -} WWDG_TypeDef; - -/** - * @brief Crypto Processor - */ - -typedef struct -{ - __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */ - __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ - __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ - __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ - __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ - __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ - __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ - __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ - __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ - __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ - __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ - __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ - __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ - __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ - __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ - __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ - __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ - __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ -} CRYP_TypeDef; - -/** - * @brief HASH - */ - -typedef struct -{ - __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ - __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ - __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ - __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ - __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ - __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ - uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ - __IO uint32_t CSR[51]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1C0 */ -} HASH_TypeDef; - -/** - * @brief HASH - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ -} RNG_TypeDef; - -/** - * @} - */ - -/** @addtogroup Peripheral_memory_map - * @{ - */ - -#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ -#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ - -#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ - -#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ - -/*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) -#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) -#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) - -/*!< APB1 peripherals */ -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) -#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) -#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) -#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) -#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800) -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) -#define UART5_BASE (APB1PERIPH_BASE + 0x5000) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) -#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) -#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400) - -/*!< APB2 peripherals */ -#define TIM1_BASE (APB2PERIPH_BASE + 0x0000) -#define TIM8_BASE (APB2PERIPH_BASE + 0x0400) -#define USART1_BASE (APB2PERIPH_BASE + 0x1000) -#define USART6_BASE (APB2PERIPH_BASE + 0x1400) -#define ADC1_BASE (APB2PERIPH_BASE + 0x2000) -#define ADC2_BASE (APB2PERIPH_BASE + 0x2100) -#define ADC3_BASE (APB2PERIPH_BASE + 0x2200) -#define ADC_BASE (APB2PERIPH_BASE + 0x2300) -#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) -#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) -#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) -#define TIM9_BASE (APB2PERIPH_BASE + 0x4000) -#define TIM10_BASE (APB2PERIPH_BASE + 0x4400) -#define TIM11_BASE (APB2PERIPH_BASE + 0x4800) - -/*!< AHB1 peripherals */ -#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) -#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) -#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) -#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) -#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) -#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400) -#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) -#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) -#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) -#define CRC_BASE (AHB1PERIPH_BASE + 0x3000) -#define RCC_BASE (AHB1PERIPH_BASE + 0x3800) -#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) -#define BKPSRAM_BASE (AHB1PERIPH_BASE + 0x4000) -#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000) -#define DMA1_Stream0_BASE (DMA1_BASE + 0x010) -#define DMA1_Stream1_BASE (DMA1_BASE + 0x028) -#define DMA1_Stream2_BASE (DMA1_BASE + 0x040) -#define DMA1_Stream3_BASE (DMA1_BASE + 0x058) -#define DMA1_Stream4_BASE (DMA1_BASE + 0x070) -#define DMA1_Stream5_BASE (DMA1_BASE + 0x088) -#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0) -#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8) -#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400) -#define DMA2_Stream0_BASE (DMA2_BASE + 0x010) -#define DMA2_Stream1_BASE (DMA2_BASE + 0x028) -#define DMA2_Stream2_BASE (DMA2_BASE + 0x040) -#define DMA2_Stream3_BASE (DMA2_BASE + 0x058) -#define DMA2_Stream4_BASE (DMA2_BASE + 0x070) -#define DMA2_Stream5_BASE (DMA2_BASE + 0x088) -#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) -#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) -#define ETH_BASE (AHB1PERIPH_BASE + 0x8000) -#define ETH_MAC_BASE (ETH_BASE) -#define ETH_MMC_BASE (ETH_BASE + 0x0100) -#define ETH_PTP_BASE (ETH_BASE + 0x0700) -#define ETH_DMA_BASE (ETH_BASE + 0x1000) - -/*!< AHB2 peripherals */ -#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000) -#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000) -#define HASH_BASE (AHB2PERIPH_BASE + 0x60400) -#define RNG_BASE (AHB2PERIPH_BASE + 0x60800) - -/*!< FSMC Bankx registers base address */ -#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) -#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) -#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) -#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) -#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) - -/* Debug MCU registers base address */ -#define DBGMCU_BASE ((uint32_t )0xE0042000) - -/** - * @} - */ - -/** @addtogroup Peripheral_declaration - * @{ - */ -#define TIM2 ((TIM_TypeDef *) TIM2_BASE) -#define TIM3 ((TIM_TypeDef *) TIM3_BASE) -#define TIM4 ((TIM_TypeDef *) TIM4_BASE) -#define TIM5 ((TIM_TypeDef *) TIM5_BASE) -#define TIM6 ((TIM_TypeDef *) TIM6_BASE) -#define TIM7 ((TIM_TypeDef *) TIM7_BASE) -#define TIM12 ((TIM_TypeDef *) TIM12_BASE) -#define TIM13 ((TIM_TypeDef *) TIM13_BASE) -#define TIM14 ((TIM_TypeDef *) TIM14_BASE) -#define RTC ((RTC_TypeDef *) RTC_BASE) -#define WWDG ((WWDG_TypeDef *) WWDG_BASE) -#define IWDG ((IWDG_TypeDef *) IWDG_BASE) -#define SPI2 ((SPI_TypeDef *) SPI2_BASE) -#define SPI3 ((SPI_TypeDef *) SPI3_BASE) -#define USART2 ((USART_TypeDef *) USART2_BASE) -#define USART3 ((USART_TypeDef *) USART3_BASE) -#define UART4 ((USART_TypeDef *) UART4_BASE) -#define UART5 ((USART_TypeDef *) UART5_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define I2C3 ((I2C_TypeDef *) I2C3_BASE) -#define CAN1 ((CAN_TypeDef *) CAN1_BASE) -#define CAN2 ((CAN_TypeDef *) CAN2_BASE) -#define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) -#define TIM1 ((TIM_TypeDef *) TIM1_BASE) -#define TIM8 ((TIM_TypeDef *) TIM8_BASE) -#define USART1 ((USART_TypeDef *) USART1_BASE) -#define USART6 ((USART_TypeDef *) USART6_BASE) -#define ADC ((ADC_Common_TypeDef *) ADC_BASE) -#define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC2 ((ADC_TypeDef *) ADC2_BASE) -#define ADC3 ((ADC_TypeDef *) ADC3_BASE) -#define SDIO ((SDIO_TypeDef *) SDIO_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) -#define EXTI ((EXTI_TypeDef *) EXTI_BASE) -#define TIM9 ((TIM_TypeDef *) TIM9_BASE) -#define TIM10 ((TIM_TypeDef *) TIM10_BASE) -#define TIM11 ((TIM_TypeDef *) TIM11_BASE) -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) -#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) -#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) -#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) -#define CRC ((CRC_TypeDef *) CRC_BASE) -#define RCC ((RCC_TypeDef *) RCC_BASE) -#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) -#define DMA1 ((DMA_TypeDef *) DMA1_BASE) -#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) -#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) -#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) -#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) -#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) -#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) -#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) -#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) -#define DMA2 ((DMA_TypeDef *) DMA2_BASE) -#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) -#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) -#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) -#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) -#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) -#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) -#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) -#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) -#define ETH ((ETH_TypeDef *) ETH_BASE) -#define DCMI ((DCMI_TypeDef *) DCMI_BASE) -#define CRYP ((CRYP_TypeDef *) CRYP_BASE) -#define HASH ((HASH_TypeDef *) HASH_BASE) -#define RNG ((RNG_TypeDef *) RNG_BASE) -#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) -#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) -#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) -#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) -#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) -#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) - -/** - * @} - */ - -/** @addtogroup Exported_constants - * @{ - */ - - /** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ - -/******************************************************************************/ -/* Peripheral Registers_Bits_Definition */ -/******************************************************************************/ - -/******************************************************************************/ -/* */ -/* Analog to Digital Converter */ -/* */ -/******************************************************************************/ -/******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD ((uint8_t)0x01) /*!
© COPYRIGHT 2013 STMicroelectronics
- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f4xx - * @{ - */ - -#ifndef __STM32F4xx_H -#define __STM32F4xx_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Library_configuration_section - * @{ - */ - -/* Uncomment the line below according to the target STM32 device used in your - application - */ - -#if !defined (STM32F40_41xxx) && !defined (STM32F427_437xx) && !defined (STM32F429_439xx) && !defined (STM32F401xx) - /* #define STM32F40_41xxx */ /*!< STM32F405RG, STM32F405VG, STM32F405ZG, STM32F415RG, STM32F415VG, STM32F415ZG, - STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG, STM32F407IE, - STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */ - - /* #define STM32F427_437xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG, STM32F427II, - STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG, STM32F437II Devices */ - - /* #define STM32F429_439xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, - STM32F429NG, STM32F439NI, STM32F429IG, STM32F429II, STM32F439VG, STM32F439VI, - STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, STM32F439NI, - STM32F439IG and STM32F439II Devices */ - - /* #define STM32F401xx */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */ - -#endif - -/* Old STM32F40XX definition, maintained for legacy purpose */ -#ifdef STM32F40XX - #define STM32F40_41xxx -#endif /* STM32F40XX */ - -/* Old STM32F427X definition, maintained for legacy purpose */ -#ifdef STM32F427X - #define STM32F427_437xx -#endif /* STM32F427X */ - -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - */ - -#if !defined (STM32F40_41xxx) && !defined (STM32F427_437xx) && !defined (STM32F429_439xx) && !defined (STM32F401xx) - #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)" -#endif - -#if !defined (USE_STDPERIPH_DRIVER) -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - /*#define USE_STDPERIPH_DRIVER */ -#endif /* USE_STDPERIPH_DRIVER */ - -/** - * @brief In the following line adjust the value of External High Speed oscillator (HSE) - used in your application - - Tip: To avoid modifying this file each time you need to use different HSE, you - can define the HSE value in your toolchain compiler preprocessor. - */ - -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ - -#endif /* HSE_VALUE */ - -/** - * @brief In the following line adjust the External High Speed oscillator (HSE) Startup - Timeout value - */ -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint16_t)0x05000) /*!< Time out for HSE start up */ -#endif /* HSE_STARTUP_TIMEOUT */ - -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief STM32F4XX Standard Peripherals Library version number V1.2.0 - */ -#define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ -#define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __STM32F4XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\ - |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\ - |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\ - |(__STM32F4XX_STDPERIPH_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ - -/** - * @brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ -#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ - -/** - * @brief STM32F4XX Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ -typedef enum IRQn -{ -/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ -/****** STM32 specific Interrupt Numbers **********************************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ - RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ - DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ - DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ - DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ - DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ - DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ - DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ - ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ - -#if defined (STM32F40_41xxx) - CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ - CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ - TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ - TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ - TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ - TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ - TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ - FSMC_IRQn = 48, /*!< FSMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ - TIM7_IRQn = 55, /*!< TIM7 global interrupt */ - DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ - DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ - DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ - DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ - DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ - ETH_IRQn = 61, /*!< Ethernet global Interrupt */ - ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ - CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ - CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ - CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ - CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ - OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ - DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ - DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ - DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ - USART6_IRQn = 71, /*!< USART6 global interrupt */ - I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ - I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ - OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ - OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ - OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ - OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ - DCMI_IRQn = 78, /*!< DCMI global interrupt */ - CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ - HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ - FPU_IRQn = 81 /*!< FPU global interrupt */ -#endif /* STM32F40_41xxx */ - -#if defined (STM32F427_437xx) - CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ - CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ - TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ - TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ - TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ - TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ - TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ - FMC_IRQn = 48, /*!< FMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ - TIM7_IRQn = 55, /*!< TIM7 global interrupt */ - DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ - DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ - DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ - DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ - DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ - ETH_IRQn = 61, /*!< Ethernet global Interrupt */ - ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ - CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ - CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ - CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ - CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ - OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ - DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ - DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ - DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ - USART6_IRQn = 71, /*!< USART6 global interrupt */ - I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ - I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ - OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ - OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ - OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ - OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ - DCMI_IRQn = 78, /*!< DCMI global interrupt */ - CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ - HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ - FPU_IRQn = 81, /*!< FPU global interrupt */ - UART7_IRQn = 82, /*!< UART7 global interrupt */ - UART8_IRQn = 83, /*!< UART8 global interrupt */ - SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ - SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ - SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ - SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ - DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */ -#endif /* STM32F427_437xx */ - -#if defined (STM32F429_439xx) - CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ - CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ - TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ - TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ - TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ - TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ - TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ - FMC_IRQn = 48, /*!< FMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ - TIM7_IRQn = 55, /*!< TIM7 global interrupt */ - DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ - DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ - DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ - DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ - DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ - ETH_IRQn = 61, /*!< Ethernet global Interrupt */ - ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ - CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ - CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ - CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ - CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ - OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ - DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ - DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ - DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ - USART6_IRQn = 71, /*!< USART6 global interrupt */ - I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ - I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ - OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ - OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ - OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ - OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ - DCMI_IRQn = 78, /*!< DCMI global interrupt */ - CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ - HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ - FPU_IRQn = 81, /*!< FPU global interrupt */ - UART7_IRQn = 82, /*!< UART7 global interrupt */ - UART8_IRQn = 83, /*!< UART8 global interrupt */ - SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ - SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ - SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ - SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ - LTDC_IRQn = 88, /*!< LTDC global Interrupt */ - LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ - DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */ -#endif /* STM32F429_439xx */ - -#if defined (STM32F401xx) - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ - TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ - TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ - DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ - DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ - DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ - DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ - DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ - OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ - DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ - DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ - DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ - USART6_IRQn = 71, /*!< USART6 global interrupt */ - I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ - I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ - FPU_IRQn = 81, /*!< FPU global interrupt */ - SPI4_IRQn = 84 /*!< SPI4 global Interrupt */ -#endif /* STM32F401xx */ - -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ -/* CHIBIOS FIX */ -//#include "system_stm32f4xx.h" -#include - -/** @addtogroup Exported_types - * @{ - */ -/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ -typedef int32_t s32; -typedef int16_t s16; -typedef int8_t s8; - -typedef const int32_t sc32; /*!< Read Only */ -typedef const int16_t sc16; /*!< Read Only */ -typedef const int8_t sc8; /*!< Read Only */ - -typedef __IO int32_t vs32; -typedef __IO int16_t vs16; -typedef __IO int8_t vs8; - -typedef __I int32_t vsc32; /*!< Read Only */ -typedef __I int16_t vsc16; /*!< Read Only */ -typedef __I int8_t vsc8; /*!< Read Only */ - -typedef uint32_t u32; -typedef uint16_t u16; -typedef uint8_t u8; - -typedef const uint32_t uc32; /*!< Read Only */ -typedef const uint16_t uc16; /*!< Read Only */ -typedef const uint8_t uc8; /*!< Read Only */ - -typedef __IO uint32_t vu32; -typedef __IO uint16_t vu16; -typedef __IO uint8_t vu8; - -typedef __I uint32_t vuc32; /*!< Read Only */ -typedef __I uint16_t vuc16; /*!< Read Only */ -typedef __I uint8_t vuc8; /*!< Read Only */ - -typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; - -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; - -/** - * @} - */ - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ - __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ - __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ - __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ - __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ - __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ - __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ - __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ - __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ - __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ - __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ - __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ - __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ - __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ - __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ - __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ - __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ - __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ - __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual - AND triple modes, Address offset: ADC1 base address + 0x308 */ -} ADC_Common_TypeDef; - - -/** - * @brief Controller Area Network TxMailBox - */ - -typedef struct -{ - __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ - __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ - __IO uint32_t TDLR; /*!< CAN mailbox data low register */ - __IO uint32_t TDHR; /*!< CAN mailbox data high register */ -} CAN_TxMailBox_TypeDef; - -/** - * @brief Controller Area Network FIFOMailBox - */ - -typedef struct -{ - __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ - __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ - __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ - __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ -} CAN_FIFOMailBox_TypeDef; - -/** - * @brief Controller Area Network FilterRegister - */ - -typedef struct -{ - __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ - __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ -} CAN_FilterRegister_TypeDef; - -/** - * @brief Controller Area Network - */ - -typedef struct -{ - __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ - __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ - __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ - __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ - __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ - __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ - __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ - __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ - uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ - CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ - uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ - __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ - __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ - uint32_t RESERVED2; /*!< Reserved, 0x208 */ - __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ - uint32_t RESERVED3; /*!< Reserved, 0x210 */ - __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ - uint32_t RESERVED4; /*!< Reserved, 0x218 */ - __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ - uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ - CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ -} CAN_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - uint8_t RESERVED0; /*!< Reserved, 0x05 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -} CRC_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DCMI - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ - __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ - __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ - __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ - __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ - __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ - __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ - __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ - __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ - __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ - __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ -} DCMI_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DMA stream x configuration register */ - __IO uint32_t NDTR; /*!< DMA stream x number of data register */ - __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ - __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ - __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ - __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ -} DMA_Stream_TypeDef; - -typedef struct -{ - __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ - __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ - __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ - __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ -} DMA_TypeDef; - -/** - * @brief DMA2D Controller - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ - __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ - __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ - __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ - __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ - __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ - __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ - __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ - __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ - __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ - __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ - __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ - __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ - __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ - __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ - __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ - __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ - __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ - __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ - __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ - uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ - __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ - __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ -} DMA2D_TypeDef; - -/** - * @brief Ethernet MAC - */ - -typedef struct -{ - __IO uint32_t MACCR; - __IO uint32_t MACFFR; - __IO uint32_t MACHTHR; - __IO uint32_t MACHTLR; - __IO uint32_t MACMIIAR; - __IO uint32_t MACMIIDR; - __IO uint32_t MACFCR; - __IO uint32_t MACVLANTR; /* 8 */ - uint32_t RESERVED0[2]; - __IO uint32_t MACRWUFFR; /* 11 */ - __IO uint32_t MACPMTCSR; - uint32_t RESERVED1[2]; - __IO uint32_t MACSR; /* 15 */ - __IO uint32_t MACIMR; - __IO uint32_t MACA0HR; - __IO uint32_t MACA0LR; - __IO uint32_t MACA1HR; - __IO uint32_t MACA1LR; - __IO uint32_t MACA2HR; - __IO uint32_t MACA2LR; - __IO uint32_t MACA3HR; - __IO uint32_t MACA3LR; /* 24 */ - uint32_t RESERVED2[40]; - __IO uint32_t MMCCR; /* 65 */ - __IO uint32_t MMCRIR; - __IO uint32_t MMCTIR; - __IO uint32_t MMCRIMR; - __IO uint32_t MMCTIMR; /* 69 */ - uint32_t RESERVED3[14]; - __IO uint32_t MMCTGFSCCR; /* 84 */ - __IO uint32_t MMCTGFMSCCR; - uint32_t RESERVED4[5]; - __IO uint32_t MMCTGFCR; - uint32_t RESERVED5[10]; - __IO uint32_t MMCRFCECR; - __IO uint32_t MMCRFAECR; - uint32_t RESERVED6[10]; - __IO uint32_t MMCRGUFCR; - uint32_t RESERVED7[334]; - __IO uint32_t PTPTSCR; - __IO uint32_t PTPSSIR; - __IO uint32_t PTPTSHR; - __IO uint32_t PTPTSLR; - __IO uint32_t PTPTSHUR; - __IO uint32_t PTPTSLUR; - __IO uint32_t PTPTSAR; - __IO uint32_t PTPTTHR; - __IO uint32_t PTPTTLR; - __IO uint32_t RESERVED8; - __IO uint32_t PTPTSSR; - uint32_t RESERVED9[565]; - __IO uint32_t DMABMR; - __IO uint32_t DMATPDR; - __IO uint32_t DMARPDR; - __IO uint32_t DMARDLAR; - __IO uint32_t DMATDLAR; - __IO uint32_t DMASR; - __IO uint32_t DMAOMR; - __IO uint32_t DMAIER; - __IO uint32_t DMAMFBOCR; - __IO uint32_t DMARSWTR; - uint32_t RESERVED10[8]; - __IO uint32_t DMACHTDR; - __IO uint32_t DMACHRDR; - __IO uint32_t DMACHTBAR; - __IO uint32_t DMACHRBAR; -} ETH_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ - __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ - __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ - __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ - __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ - __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ -} EXTI_TypeDef; - -/** - * @brief FLASH Registers - */ - -typedef struct -{ - __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ - __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ - __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ - __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ - __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ - __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */ -} FLASH_TypeDef; - -#if defined (STM32F40_41xxx) -/** - * @brief Flexible Static Memory Controller - */ - -typedef struct -{ - __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ -} FSMC_Bank1_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank1E - */ - -typedef struct -{ - __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ -} FSMC_Bank1E_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank2 - */ - -typedef struct -{ - __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ - __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ - __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ - __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ - uint32_t RESERVED0; /*!< Reserved, 0x70 */ - __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ -} FSMC_Bank2_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank3 - */ - -typedef struct -{ - __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ - __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ - __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ - __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ - uint32_t RESERVED0; /*!< Reserved, 0x90 */ - __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ -} FSMC_Bank3_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank4 - */ - -typedef struct -{ - __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ - __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ - __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ - __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ - __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ -} FSMC_Bank4_TypeDef; -#endif /* STM32F40_41xxx */ - -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) -/** - * @brief Flexible Memory Controller - */ - -typedef struct -{ - __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ -} FMC_Bank1_TypeDef; - -/** - * @brief Flexible Memory Controller Bank1E - */ - -typedef struct -{ - __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ -} FMC_Bank1E_TypeDef; - -/** - * @brief Flexible Memory Controller Bank2 - */ - -typedef struct -{ - __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ - __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ - __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ - __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ - uint32_t RESERVED0; /*!< Reserved, 0x70 */ - __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ -} FMC_Bank2_TypeDef; - -/** - * @brief Flexible Memory Controller Bank3 - */ - -typedef struct -{ - __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ - __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ - __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ - __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ - uint32_t RESERVED0; /*!< Reserved, 0x90 */ - __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ -} FMC_Bank3_TypeDef; - -/** - * @brief Flexible Memory Controller Bank4 - */ - -typedef struct -{ - __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ - __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ - __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ - __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ - __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ -} FMC_Bank4_TypeDef; - -/** - * @brief Flexible Memory Controller Bank5_6 - */ - -typedef struct -{ - __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ - __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ - __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ - __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ - __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ -} FMC_Bank5_6_TypeDef; -#endif /* STM32F427_437xx || STM32F429_439xx */ - -/** - * @brief General Purpose I/O - */ - -/* CHIBIOS FIX */ -#if 0 -typedef struct -{ - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ - __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ -} GPIO_TypeDef; -#endif - -/** - * @brief System configuration controller - */ - -typedef struct -{ - __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ - __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ - __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ - uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ - __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ -} SYSCFG_TypeDef; - -/** - * @brief Inter-integrated Circuit Interface - */ - -typedef struct -{ - __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ - __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ - uint16_t RESERVED7; /*!< Reserved, 0x1E */ - __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ - uint16_t RESERVED8; /*!< Reserved, 0x22 */ - __IO uint16_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */ - uint16_t RESERVED9; /*!< Reserved, 0x26 */ -} I2C_TypeDef; - -/** - * @brief Independent WATCHDOG - */ - -typedef struct -{ - __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ - __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ - __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ -} IWDG_TypeDef; - -/** - * @brief LCD-TFT Display Controller - */ - -typedef struct -{ - uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ - __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ - __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ - __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ - __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ - __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ - uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ - __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ - uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ - __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ - uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ - __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ - __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ - __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ - __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ - __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ - __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ -} LTDC_TypeDef; - -/** - * @brief LCD-TFT Display layer x Controller - */ - -typedef struct -{ - __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ - __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ - __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ - __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ - __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ - __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ - __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ - __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ - uint32_t RESERVED0[2]; /*!< Reserved */ - __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ - __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ - __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ - uint32_t RESERVED1[3]; /*!< Reserved */ - __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ - -} LTDC_Layer_TypeDef; - -/** - * @brief Power Control - */ - -typedef struct -{ - __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ - __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ -} PWR_TypeDef; - -/** - * @brief Reset and Clock Control - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ - __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ - __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ - __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ - __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ - __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ - __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ - uint32_t RESERVED0; /*!< Reserved, 0x1C */ - __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ - __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ - uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ - __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ - __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ - __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ - uint32_t RESERVED2; /*!< Reserved, 0x3C */ - __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ - __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ - uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ - __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ - __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ - __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ - uint32_t RESERVED4; /*!< Reserved, 0x5C */ - __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ - __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ - uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ - __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ - __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ - uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ - __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ - __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ - __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */ - __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */ - -} RCC_TypeDef; - -/** - * @brief Real-Time Clock - */ - -typedef struct -{ - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ - __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ - __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */ - uint32_t RESERVED7; /*!< Reserved, 0x4C */ - __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ - __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ - __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ - __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ - __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ - __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ - __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ - __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ - __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ - __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ - __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ - __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ - __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ - __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ - __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ - __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ - __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ - __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ - __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ - __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ -} RTC_TypeDef; - - -/** - * @brief Serial Audio Interface - */ - -typedef struct -{ - __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ -} SAI_TypeDef; - -typedef struct -{ - __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ - __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ - __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ - __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ - __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ - __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ - __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ -} SAI_Block_TypeDef; - -/** - * @brief SD host Interface - */ - -typedef struct -{ - __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ - __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ - __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ - __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ - __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ - __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ - __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ - __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ - __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ - __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ - __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ - __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ - __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ - __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ - __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ - __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ - uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ - __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ - uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ - __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ -} SDIO_TypeDef; - -/** - * @brief Serial Peripheral Interface - */ - -typedef struct -{ - __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ - __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ - uint16_t RESERVED7; /*!< Reserved, 0x1E */ - __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ - uint16_t RESERVED8; /*!< Reserved, 0x22 */ -} SPI_TypeDef; - -/** - * @brief TIM - */ - -typedef struct -{ - __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ - __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ - uint16_t RESERVED7; /*!< Reserved, 0x1E */ - __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ - uint16_t RESERVED8; /*!< Reserved, 0x22 */ - __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - uint16_t RESERVED9; /*!< Reserved, 0x2A */ - __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - uint16_t RESERVED10; /*!< Reserved, 0x32 */ - __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ - __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ - __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ - __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ - __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - uint16_t RESERVED11; /*!< Reserved, 0x46 */ - __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - uint16_t RESERVED12; /*!< Reserved, 0x4A */ - __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - uint16_t RESERVED13; /*!< Reserved, 0x4E */ - __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */ - uint16_t RESERVED14; /*!< Reserved, 0x52 */ -} TIM_TypeDef; - -/** - * @brief Universal Synchronous Asynchronous Receiver Transmitter - */ - -typedef struct -{ - __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ -} USART_TypeDef; - -/** - * @brief Window WATCHDOG - */ - -typedef struct -{ - __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ - __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ - __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ -} WWDG_TypeDef; - -/** - * @brief Crypto Processor - */ - -typedef struct -{ - __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */ - __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ - __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ - __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ - __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ - __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ - __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ - __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ - __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ - __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ - __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ - __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ - __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ - __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ - __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ - __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ - __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ - __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ - __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */ - __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */ - __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */ - __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */ - __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */ - __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */ - __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */ - __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */ - __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */ - __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */ - __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */ - __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */ - __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */ - __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */ - __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */ - __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */ -} CRYP_TypeDef; - -/** - * @brief HASH - */ - -typedef struct -{ - __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ - __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ - __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ - __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ - __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ - __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ - uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ - __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ -} HASH_TypeDef; - -/** - * @brief HASH_DIGEST - */ - -typedef struct -{ - __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ -} HASH_DIGEST_TypeDef; - -/** - * @brief RNG - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ -} RNG_TypeDef; - -/** - * @} - */ - -/** @addtogroup Peripheral_memory_map - * @{ - */ -#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */ -#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */ -#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */ -#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */ -#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ -#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */ - -#if defined (STM32F40_41xxx) -#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ -#endif /* STM32F40_41xxx */ - -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) -#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */ -#endif /* STM32F427_437xx || STM32F429_439xx */ - -#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */ -#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */ -#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */ -#define SRAM3_BB_BASE ((uint32_t)0x22400000) /*!< SRAM3(64 KB) base address in the bit-band region */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ -#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */ - -/* Legacy defines */ -#define SRAM_BASE SRAM1_BASE -#define SRAM_BB_BASE SRAM1_BB_BASE - - -/*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) -#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) -#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) - -/*!< APB1 peripherals */ -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) -#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) -#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) -#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) -#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) -#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) -#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800) -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) -#define UART5_BASE (APB1PERIPH_BASE + 0x5000) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) -#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) -#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400) -#define UART7_BASE (APB1PERIPH_BASE + 0x7800) -#define UART8_BASE (APB1PERIPH_BASE + 0x7C00) - -/*!< APB2 peripherals */ -#define TIM1_BASE (APB2PERIPH_BASE + 0x0000) -#define TIM8_BASE (APB2PERIPH_BASE + 0x0400) -#define USART1_BASE (APB2PERIPH_BASE + 0x1000) -#define USART6_BASE (APB2PERIPH_BASE + 0x1400) -#define ADC1_BASE (APB2PERIPH_BASE + 0x2000) -#define ADC2_BASE (APB2PERIPH_BASE + 0x2100) -#define ADC3_BASE (APB2PERIPH_BASE + 0x2200) -#define ADC_BASE (APB2PERIPH_BASE + 0x2300) -#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) -#define SPI4_BASE (APB2PERIPH_BASE + 0x3400) -#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) -#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) -#define TIM9_BASE (APB2PERIPH_BASE + 0x4000) -#define TIM10_BASE (APB2PERIPH_BASE + 0x4400) -#define TIM11_BASE (APB2PERIPH_BASE + 0x4800) -#define SPI5_BASE (APB2PERIPH_BASE + 0x5000) -#define SPI6_BASE (APB2PERIPH_BASE + 0x5400) -#define SAI1_BASE (APB2PERIPH_BASE + 0x5800) -#define SAI1_Block_A_BASE (SAI1_BASE + 0x004) -#define SAI1_Block_B_BASE (SAI1_BASE + 0x024) -#define LTDC_BASE (APB2PERIPH_BASE + 0x6800) -#define LTDC_Layer1_BASE (LTDC_BASE + 0x84) -#define LTDC_Layer2_BASE (LTDC_BASE + 0x104) - -/*!< AHB1 peripherals */ -#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) -#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) -#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) -#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) -#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) -#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400) -#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) -#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) -#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) -#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400) -#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800) -#define CRC_BASE (AHB1PERIPH_BASE + 0x3000) -#define RCC_BASE (AHB1PERIPH_BASE + 0x3800) -#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) -#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000) -#define DMA1_Stream0_BASE (DMA1_BASE + 0x010) -#define DMA1_Stream1_BASE (DMA1_BASE + 0x028) -#define DMA1_Stream2_BASE (DMA1_BASE + 0x040) -#define DMA1_Stream3_BASE (DMA1_BASE + 0x058) -#define DMA1_Stream4_BASE (DMA1_BASE + 0x070) -#define DMA1_Stream5_BASE (DMA1_BASE + 0x088) -#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0) -#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8) -#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400) -#define DMA2_Stream0_BASE (DMA2_BASE + 0x010) -#define DMA2_Stream1_BASE (DMA2_BASE + 0x028) -#define DMA2_Stream2_BASE (DMA2_BASE + 0x040) -#define DMA2_Stream3_BASE (DMA2_BASE + 0x058) -#define DMA2_Stream4_BASE (DMA2_BASE + 0x070) -#define DMA2_Stream5_BASE (DMA2_BASE + 0x088) -#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) -#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) -#define ETH_BASE (AHB1PERIPH_BASE + 0x8000) -#define ETH_MAC_BASE (ETH_BASE) -#define ETH_MMC_BASE (ETH_BASE + 0x0100) -#define ETH_PTP_BASE (ETH_BASE + 0x0700) -#define ETH_DMA_BASE (ETH_BASE + 0x1000) -#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000) - -/*!< AHB2 peripherals */ -#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000) -#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000) -#define HASH_BASE (AHB2PERIPH_BASE + 0x60400) -#define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710) -#define RNG_BASE (AHB2PERIPH_BASE + 0x60800) - -#if defined (STM32F40_41xxx) -/*!< FSMC Bankx registers base address */ -#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) -#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) -#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) -#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) -#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) -#endif /* STM32F40_41xxx */ - -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) -/*!< FMC Bankx registers base address */ -#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) -#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) -#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060) -#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080) -#define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0) -#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140) -#endif /* STM32F427_437xx || STM32F429_439xx */ - -/* Debug MCU registers base address */ -#define DBGMCU_BASE ((uint32_t )0xE0042000) - -/** - * @} - */ - -/** @addtogroup Peripheral_declaration - * @{ - */ -#define TIM2 ((TIM_TypeDef *) TIM2_BASE) -#define TIM3 ((TIM_TypeDef *) TIM3_BASE) -#define TIM4 ((TIM_TypeDef *) TIM4_BASE) -#define TIM5 ((TIM_TypeDef *) TIM5_BASE) -#define TIM6 ((TIM_TypeDef *) TIM6_BASE) -#define TIM7 ((TIM_TypeDef *) TIM7_BASE) -#define TIM12 ((TIM_TypeDef *) TIM12_BASE) -#define TIM13 ((TIM_TypeDef *) TIM13_BASE) -#define TIM14 ((TIM_TypeDef *) TIM14_BASE) -#define RTC ((RTC_TypeDef *) RTC_BASE) -#define WWDG ((WWDG_TypeDef *) WWDG_BASE) -#define IWDG ((IWDG_TypeDef *) IWDG_BASE) -#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE) -#define SPI2 ((SPI_TypeDef *) SPI2_BASE) -#define SPI3 ((SPI_TypeDef *) SPI3_BASE) -#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) -#define USART2 ((USART_TypeDef *) USART2_BASE) -#define USART3 ((USART_TypeDef *) USART3_BASE) -#define UART4 ((USART_TypeDef *) UART4_BASE) -#define UART5 ((USART_TypeDef *) UART5_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define I2C3 ((I2C_TypeDef *) I2C3_BASE) -#define CAN1 ((CAN_TypeDef *) CAN1_BASE) -#define CAN2 ((CAN_TypeDef *) CAN2_BASE) -#define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) -#define UART7 ((USART_TypeDef *) UART7_BASE) -#define UART8 ((USART_TypeDef *) UART8_BASE) -#define TIM1 ((TIM_TypeDef *) TIM1_BASE) -#define TIM8 ((TIM_TypeDef *) TIM8_BASE) -#define USART1 ((USART_TypeDef *) USART1_BASE) -#define USART6 ((USART_TypeDef *) USART6_BASE) -#define ADC ((ADC_Common_TypeDef *) ADC_BASE) -#define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC2 ((ADC_TypeDef *) ADC2_BASE) -#define ADC3 ((ADC_TypeDef *) ADC3_BASE) -#define SDIO ((SDIO_TypeDef *) SDIO_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#define SPI4 ((SPI_TypeDef *) SPI4_BASE) -#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) -#define EXTI ((EXTI_TypeDef *) EXTI_BASE) -#define TIM9 ((TIM_TypeDef *) TIM9_BASE) -#define TIM10 ((TIM_TypeDef *) TIM10_BASE) -#define TIM11 ((TIM_TypeDef *) TIM11_BASE) -#define SPI5 ((SPI_TypeDef *) SPI5_BASE) -#define SPI6 ((SPI_TypeDef *) SPI6_BASE) -#define SAI1 ((SAI_TypeDef *) SAI1_BASE) -#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) -#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) -#define LTDC ((LTDC_TypeDef *)LTDC_BASE) -#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) -#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) -#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) -#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) -#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) -#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) -#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) -#define CRC ((CRC_TypeDef *) CRC_BASE) -#define RCC ((RCC_TypeDef *) RCC_BASE) -#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) -#define DMA1 ((DMA_TypeDef *) DMA1_BASE) -#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) -#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) -#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) -#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) -#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) -#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) -#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) -#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) -#define DMA2 ((DMA_TypeDef *) DMA2_BASE) -#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) -#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) -#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) -#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) -#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) -#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) -#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) -#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) -#define ETH ((ETH_TypeDef *) ETH_BASE) -#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE) -#define DCMI ((DCMI_TypeDef *) DCMI_BASE) -#define CRYP ((CRYP_TypeDef *) CRYP_BASE) -#define HASH ((HASH_TypeDef *) HASH_BASE) -#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE) -#define RNG ((RNG_TypeDef *) RNG_BASE) - -#if defined (STM32F40_41xxx) -#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) -#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) -#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) -#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) -#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) -#endif /* STM32F40_41xxx */ - -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) -#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) -#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) -#define FMC_Bank2 ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE) -#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) -#define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE) -#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) -#endif /* STM32F427_437xx || STM32F429_439xx */ - -#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) - -/** - * @} - */ - -/** @addtogroup Exported_constants - * @{ - */ - - /** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ - -/******************************************************************************/ -/* Peripheral Registers_Bits_Definition */ -/******************************************************************************/ - -/******************************************************************************/ -/* */ -/* Analog to Digital Converter */ -/* */ -/******************************************************************************/ -/******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD ((uint8_t)0x01) /*! - -#include "ch.h" -#include "hal.h" -#include "console.h" - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief Console driver 1. - */ -BaseChannel CD1; - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static size_t write(void *ip, const uint8_t *bp, size_t n) { - size_t ret; - - (void)ip; - ret = fwrite(bp, 1, n, stdout); - fflush(stdout); - return ret; -} - -static size_t read(void *ip, uint8_t *bp, size_t n) { - - (void)ip; - return fread(bp, 1, n, stdin); -} - -static msg_t put(void *ip, uint8_t b) { - - (void)ip; - - fputc(b, stdout); - fflush(stdout); - return RDY_OK; -} - -static msg_t get(void *ip) { - - (void)ip; - - return fgetc(stdin); -} - -static msg_t putt(void *ip, uint8_t b, systime_t time) { - - (void)ip; - (void)time; - fputc(b, stdout); - fflush(stdout); - return RDY_OK; -} - -static msg_t gett(void *ip, systime_t time) { - - (void)ip; - (void)time; - return fgetc(stdin); -} - -static size_t writet(void *ip, const uint8_t *bp, size_t n, systime_t time) { - size_t ret; - - (void)ip; - (void)time; - ret = fwrite(bp, 1, n, stdout); - fflush(stdout); - return ret; -} - -static size_t readt(void *ip, uint8_t *bp, size_t n, systime_t time) { - - (void)ip; - (void)time; - return fread(bp, 1, n, stdin); -} - -static const struct BaseChannelVMT vmt = { - write, read, put, get, - putt, gett, writet, readt -}; - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -void conInit(void) { - - CD1.vmt = &vmt; -} - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/Win32/console.h b/firmware/chibios/os/hal/platforms/Win32/console.h deleted file mode 100644 index 58f0f08ec9..0000000000 --- a/firmware/chibios/os/hal/platforms/Win32/console.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file console.h - * @brief Simulator console driver header. - * @{ - */ - -#ifndef _CONSOLE_H_ -#define _CONSOLE_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -extern BaseChannel CD1; - -#ifdef __cplusplus -extern "C" { -#endif - void conInit(void); -#ifdef __cplusplus -} -#endif - -#endif /* _CONSOLE_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/Win32/hal_lld.c b/firmware/chibios/os/hal/platforms/Win32/hal_lld.c deleted file mode 100644 index 4745b9dbad..0000000000 --- a/firmware/chibios/os/hal/platforms/Win32/hal_lld.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file Win32/hal_lld.c - * @brief Win32 HAL subsystem low level driver code. - * @addtogroup WIN32_HAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -static LARGE_INTEGER nextcnt; -static LARGE_INTEGER slice; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level HAL driver initialization. - */ -void hal_lld_init(void) { - WSADATA wsaData; - - /* Initialization.*/ - if (WSAStartup(2, &wsaData) != 0) { - printf("Unable to locate a winsock DLL\n"); - exit(1); - } - - printf("ChibiOS/RT simulator (Win32)\n"); - if (!QueryPerformanceFrequency(&slice)) { - printf("QueryPerformanceFrequency() error"); - exit(1); - } - slice.QuadPart /= CH_FREQUENCY; - QueryPerformanceCounter(&nextcnt); - nextcnt.QuadPart += slice.QuadPart; - - fflush(stdout); -} - -/** - * @brief Interrupt simulation. - */ -void ChkIntSources(void) { - LARGE_INTEGER n; - -#if HAL_USE_SERIAL - if (sd_lld_interrupt_pending()) { - dbg_check_lock(); - if (chSchIsPreemptionRequired()) - chSchDoReschedule(); - dbg_check_unlock(); - return; - } -#endif - - /* Interrupt Timer simulation (10ms interval).*/ - QueryPerformanceCounter(&n); - if (n.QuadPart > nextcnt.QuadPart) { - nextcnt.QuadPart += slice.QuadPart; - - CH_IRQ_PROLOGUE(); - - chSysLockFromIsr(); - chSysTimerHandlerI(); - chSysUnlockFromIsr(); - - CH_IRQ_EPILOGUE(); - - dbg_check_lock(); - if (chSchIsPreemptionRequired()) - chSchDoReschedule(); - dbg_check_unlock(); - } -} - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/Win32/hal_lld.h b/firmware/chibios/os/hal/platforms/Win32/hal_lld.h deleted file mode 100644 index 3208f3a7f1..0000000000 --- a/firmware/chibios/os/hal/platforms/Win32/hal_lld.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file Win32/hal_lld.h - * @brief WIN32 simulator HAL subsystem low level driver header. - * - * @addtogroup WIN32_HAL - * @{ - */ - -#ifndef _HAL_LLD_H_ -#define _HAL_LLD_H_ - -#include -#include - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Defines the support for realtime counters in the HAL. - */ -#define HAL_IMPLEMENTS_COUNTERS FALSE - -/** - * @brief Platform name. - */ -#define PLATFORM_NAME "Win32" - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void hal_lld_init(void); - void ChkIntSources(void); -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_LLD_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/Win32/pal_lld.c b/firmware/chibios/os/hal/platforms/Win32/pal_lld.c deleted file mode 100644 index c655931570..0000000000 --- a/firmware/chibios/os/hal/platforms/Win32/pal_lld.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file Win32/pal_lld.c - * @brief Win32 low level simulated PAL driver code. - * - * @addtogroup WIN32_PAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief VIO1 simulated port. - */ -sim_vio_port_t vio_port_1; - -/** - * @brief VIO2 simulated port. - */ -sim_vio_port_t vio_port_2; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Pads mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * - * @param[in] port the port identifier - * @param[in] mask the group mask - * @param[in] mode the mode - * - * @note This function is not meant to be invoked directly by the application - * code. - * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output with high - * state. - * @note This function does not alter the @p PINSELx registers. Alternate - * functions setup must be handled by device-specific code. - */ -void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - iomode_t mode) { - - switch (mode) { - case PAL_MODE_RESET: - case PAL_MODE_INPUT: - port->dir &= ~mask; - break; - case PAL_MODE_UNCONNECTED: - port->latch |= mask; - case PAL_MODE_OUTPUT_PUSHPULL: - port->dir |= mask; - break; - } -} - -#endif /* HAL_USE_PAL */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/Win32/pal_lld.h b/firmware/chibios/os/hal/platforms/Win32/pal_lld.h deleted file mode 100644 index a2c0e6edc1..0000000000 --- a/firmware/chibios/os/hal/platforms/Win32/pal_lld.h +++ /dev/null @@ -1,206 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file Win32/pal_lld.h - * @brief Win32 low level simulated PAL driver header. - * - * @addtogroup WIN32_PAL - * @{ - */ - -#ifndef _PAL_LLD_H_ -#define _PAL_LLD_H_ - -#if HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Unsupported modes and specific modes */ -/*===========================================================================*/ - -#undef PAL_MODE_INPUT_PULLUP -#undef PAL_MODE_INPUT_PULLDOWN -#undef PAL_MODE_OUTPUT_OPENDRAIN -#undef PAL_MODE_INPUT_ANALOG - -/*===========================================================================*/ -/* I/O Ports Types and constants. */ -/*===========================================================================*/ - -/** - * @brief VIO port structure. - */ -typedef struct { - /** - * @brief VIO_LATCH register. - * @details This register represents the output latch of the VIO port. - */ - uint32_t latch; - /** - * @brief VIO_PIN register. - * @details This register represents the logical level at the VIO port - * pin level. - */ - uint32_t pin; - /** - * @brief VIO_DIR register. - * @details Direction of the VIO port bits, 0=input, 1=output. - */ - uint32_t dir; -} sim_vio_port_t; - -/** - * @brief Virtual I/O ports static initializer. - * @details An instance of this structure must be passed to @p palInit() at - * system startup time in order to initialized the digital I/O - * subsystem. This represents only the initial setup, specific pads - * or whole ports can be reprogrammed at later time. - */ -typedef struct { - /** - * @brief Virtual port 1 setup data. - */ - sim_vio_port_t VP1Data; - /** - * @brief Virtual port 2 setup data. - */ - sim_vio_port_t VP2Data; -} PALConfig; - -/** - * @brief Width, in bits, of an I/O port. - */ -#define PAL_IOPORTS_WIDTH 32 - -/** - * @brief Whole port mask. - * @brief This macro specifies all the valid bits into a port. - */ -#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFF) - -/** - * @brief Digital I/O port sized unsigned type. - */ -typedef uint32_t ioportmask_t; - -/** - * @brief Digital I/O modes. - */ -typedef uint32_t iomode_t; - -/** - * @brief Port Identifier. - */ -typedef sim_vio_port_t *ioportid_t; - -/*===========================================================================*/ -/* I/O Ports Identifiers. */ -/*===========================================================================*/ - -/** - * @brief VIO port 1 identifier. - */ -#define IOPORT1 (&vio_port_1) - -/** - * @brief VIO port 2 identifier. - */ -#define IOPORT2 (&vio_port_2) - -/*===========================================================================*/ -/* Implementation, some of the following macros could be implemented as */ -/* functions, if so please put them in pal_lld.c. */ -/*===========================================================================*/ - -/** - * @brief Low level PAL subsystem initialization. - * - * @param[in] config architecture-dependent ports configuration - * - * @notapi - */ -#define pal_lld_init(config) \ - (vio_port_1 = (config)->VP1Data, \ - vio_port_2 = (config)->VP2Data) - -/** - * @brief Reads the physical I/O port states. - * - * @param[in] port port identifier - * @return The port bits. - * - * @notapi - */ -#define pal_lld_readport(port) ((port)->pin) - -/** - * @brief Reads the output latch. - * @details The purpose of this function is to read back the latched output - * value. - * - * @param[in] port port identifier - * @return The latched logical states. - * - * @notapi - */ -#define pal_lld_readlatch(port) ((port)->latch) - -/** - * @brief Writes a bits mask on a I/O port. - * - * @param[in] port port identifier - * @param[in] bits bits to be written on the specified port - * - * @notapi - */ -#define pal_lld_writeport(port, bits) ((port)->latch = (bits)) - -/** - * @brief Pads group mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] offset group bit offset within the port - * @param[in] mode group mode - * - * @notapi - */ -#define pal_lld_setgroupmode(port, mask, offset, mode) \ - _pal_lld_setgroupmode(port, mask << offset, mode) - -#if !defined(__DOXYGEN__) -extern sim_vio_port_t vio_port_1; -extern sim_vio_port_t vio_port_2; -extern const PALConfig pal_default_config; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - iomode_t mode); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_PAL */ - -#endif /* _PAL_LLD_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/Win32/platform.mk b/firmware/chibios/os/hal/platforms/Win32/platform.mk deleted file mode 100644 index afc92841cf..0000000000 --- a/firmware/chibios/os/hal/platforms/Win32/platform.mk +++ /dev/null @@ -1,7 +0,0 @@ -# List of all the Win32 platform files. -PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/Win32/hal_lld.c \ - ${CHIBIOS}/os/hal/platforms/Win32/pal_lld.c \ - ${CHIBIOS}/os/hal/platforms/Win32/serial_lld.c - -# Required include directories -PLATFORMINC = ${CHIBIOS}/os/hal/platforms/Win32 diff --git a/firmware/chibios/os/hal/platforms/Win32/serial_lld.c b/firmware/chibios/os/hal/platforms/Win32/serial_lld.c deleted file mode 100644 index 0109560aaa..0000000000 --- a/firmware/chibios/os/hal/platforms/Win32/serial_lld.c +++ /dev/null @@ -1,278 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file Win32/serial_lld.c - * @brief Win32 low level simulated serial driver code. - * @addtogroup WIN32_SERIAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief Serial driver 1 identifier.*/ -#if USE_WIN32_SERIAL1 || defined(__DOXYGEN__) -SerialDriver SD1; -#endif -/** @brief Serial driver 2 identifier.*/ -#if USE_WIN32_SERIAL2 || defined(__DOXYGEN__) -SerialDriver SD2; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** @brief Driver default configuration.*/ -static const SerialConfig default_config = { -}; - -static u_long nb = 1; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void init(SerialDriver *sdp, uint16_t port) { - struct sockaddr_in sad; - struct protoent *prtp; - - if ((prtp = getprotobyname("tcp")) == NULL) { - printf("%s: Error mapping protocol name to protocol number\n", sdp->com_name); - goto abort; - } - - sdp->com_listen = socket(PF_INET, SOCK_STREAM, prtp->p_proto); - if (sdp->com_listen == INVALID_SOCKET) { - printf("%s: Error creating simulator socket\n", sdp->com_name); - goto abort; - } - - if (ioctlsocket(sdp->com_listen, FIONBIO, &nb) != 0) { - printf("%s: Unable to setup non blocking mode on socket\n", sdp->com_name); - goto abort; - } - - memset(&sad, 0, sizeof(sad)); - sad.sin_family = AF_INET; - sad.sin_addr.s_addr = INADDR_ANY; - sad.sin_port = htons(port); - if (bind(sdp->com_listen, (struct sockaddr *)&sad, sizeof(sad))) { - printf("%s: Error binding socket\n", sdp->com_name); - goto abort; - } - - if (listen(sdp->com_listen, 1) != 0) { - printf("%s: Error listening socket\n", sdp->com_name); - goto abort; - } - printf("Full Duplex Channel %s listening on port %d\n", sdp->com_name, port); - return; - -abort: - if (sdp->com_listen != INVALID_SOCKET) - closesocket(sdp->com_listen); - WSACleanup(); - exit(1); -} - -static bool_t connint(SerialDriver *sdp) { - - if (sdp->com_data == INVALID_SOCKET) { - struct sockaddr addr; - int addrlen = sizeof(addr); - - if ((sdp->com_data = accept(sdp->com_listen, &addr, &addrlen)) == INVALID_SOCKET) - return FALSE; - - if (ioctlsocket(sdp->com_data, FIONBIO, &nb) != 0) { - printf("%s: Unable to setup non blocking mode on data socket\n", sdp->com_name); - goto abort; - } - chSysLockFromIsr(); - chnAddFlagsI(sdp, CHN_CONNECTED); - chSysUnlockFromIsr(); - return TRUE; - } - return FALSE; -abort: - if (sdp->com_listen != INVALID_SOCKET) - closesocket(sdp->com_listen); - if (sdp->com_data != INVALID_SOCKET) - closesocket(sdp->com_data); - WSACleanup(); - exit(1); -} - -static bool_t inint(SerialDriver *sdp) { - - if (sdp->com_data != INVALID_SOCKET) { - int i; - uint8_t data[32]; - - /* - * Input. - */ - int n = recv(sdp->com_data, data, sizeof(data), 0); - switch (n) { - case 0: - closesocket(sdp->com_data); - sdp->com_data = INVALID_SOCKET; - chSysLockFromIsr(); - chnAddFlagsI(sdp, CHN_DISCONNECTED); - chSysUnlockFromIsr(); - return FALSE; - case SOCKET_ERROR: - if (WSAGetLastError() == WSAEWOULDBLOCK) - return FALSE; - closesocket(sdp->com_data); - sdp->com_data = INVALID_SOCKET; - return FALSE; - } - for (i = 0; i < n; i++) { - chSysLockFromIsr(); - sdIncomingDataI(sdp, data[i]); - chSysUnlockFromIsr(); - } - return TRUE; - } - return FALSE; -} - -static bool_t outint(SerialDriver *sdp) { - - if (sdp->com_data != INVALID_SOCKET) { - int n; - uint8_t data[1]; - - /* - * Input. - */ - chSysLockFromIsr(); - n = sdRequestDataI(sdp); - chSysUnlockFromIsr(); - if (n < 0) - return FALSE; - data[0] = (uint8_t)n; - n = send(sdp->com_data, data, sizeof(data), 0); - switch (n) { - case 0: - closesocket(sdp->com_data); - sdp->com_data = INVALID_SOCKET; - chSysLockFromIsr(); - chnAddFlagsI(sdp, CHN_DISCONNECTED); - chSysUnlockFromIsr(); - return FALSE; - case SOCKET_ERROR: - if (WSAGetLastError() == WSAEWOULDBLOCK) - return FALSE; - closesocket(sdp->com_data); - sdp->com_data = INVALID_SOCKET; - return FALSE; - } - return TRUE; - } - return FALSE; -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * Low level serial driver initialization. - */ -void sd_lld_init(void) { - -#if USE_WIN32_SERIAL1 - sdObjectInit(&SD1, NULL, NULL); - SD1.com_listen = INVALID_SOCKET; - SD1.com_data = INVALID_SOCKET; - SD1.com_name = "SD1"; -#endif - -#if USE_WIN32_SERIAL1 - sdObjectInit(&SD2, NULL, NULL); - SD2.com_listen = INVALID_SOCKET; - SD2.com_data = INVALID_SOCKET; - SD2.com_name = "SD2"; -#endif -} - -/** - * @brief Low level serial driver configuration and (re)start. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] config the architecture-dependent serial driver configuration. - * If this parameter is set to @p NULL then a default - * configuration is used. - */ -void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { - - if (config == NULL) - config = &default_config; - -#if USE_WIN32_SERIAL1 - if (sdp == &SD1) - init(&SD1, SD1_PORT); -#endif - -#if USE_WIN32_SERIAL1 - if (sdp == &SD2) - init(&SD2, SD2_PORT); -#endif -} - -/** - * @brief Low level serial driver stop. - * @details De-initializes the USART, stops the associated clock, resets the - * interrupt vector. - * - * @param[in] sdp pointer to a @p SerialDriver object - */ -void sd_lld_stop(SerialDriver *sdp) { - - (void)sdp; -} - -bool_t sd_lld_interrupt_pending(void) { - bool_t b; - - CH_IRQ_PROLOGUE(); - - b = connint(&SD1) || connint(&SD2) || - inint(&SD1) || inint(&SD2) || - outint(&SD1) || outint(&SD2); - - CH_IRQ_EPILOGUE(); - - return b; -} - -#endif /* HAL_USE_SERIAL */ - -/** @} */ diff --git a/firmware/chibios/os/hal/platforms/Win32/serial_lld.h b/firmware/chibios/os/hal/platforms/Win32/serial_lld.h deleted file mode 100644 index e45cbf8046..0000000000 --- a/firmware/chibios/os/hal/platforms/Win32/serial_lld.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file Win32/serial_lld.h - * @brief Win32 low level simulated serial driver header. - * - * @addtogroup WIN32_SERIAL - * @{ - */ - -#ifndef _SERIAL_LLD_H_ -#define _SERIAL_LLD_H_ - -#if HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Serial buffers size. - * @details Configuration parameter, you can change the depth of the queue - * buffers depending on the requirements of your application. - */ -#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_BUFFERS_SIZE 1024 -#endif - -/** - * @brief SD1 driver enable switch. - * @details If set to @p TRUE the support for SD1 is included. - * @note The default is @p TRUE. - */ -#if !defined(USE_WIN32_SERIAL1) || defined(__DOXYGEN__) -#define USE_WIN32_SERIAL1 TRUE -#endif - -/** - * @brief SD2 driver enable switch. - * @details If set to @p TRUE the support for SD2 is included. - * @note The default is @p TRUE. - */ -#if !defined(USE_WIN32_SERIAL2) || defined(__DOXYGEN__) -#define USE_WIN32_SERIAL2 TRUE -#endif - -/** - * @brief Listen port for SD1. - */ -#if !defined(SD1_PORT) || defined(__DOXYGEN__) -#define SD1_PORT 29001 -#endif - -/** - * @brief Listen port for SD2. - */ -#if !defined(SD2_PORT) || defined(__DOXYGEN__) -#define SD2_PORT 29002 -#endif - -/*===========================================================================*/ -/* Unsupported event flags and custom events. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Generic Serial Driver configuration structure. - * @details An instance of this structure must be passed to @p sdStart() - * in order to configure and start a serial driver operations. - * @note This structure content is architecture dependent, each driver - * implementation defines its own version and the custom static - * initializers. - */ -typedef struct { -} SerialConfig; - -/** - * @brief @p SerialDriver specific data. - */ -#define _serial_driver_data \ - _base_asynchronous_channel_data \ - /* Driver state.*/ \ - sdstate_t state; \ - /* Input queue.*/ \ - InputQueue iqueue; \ - /* Output queue.*/ \ - OutputQueue oqueue; \ - /* Input circular buffer.*/ \ - uint8_t ib[SERIAL_BUFFERS_SIZE]; \ - /* Output circular buffer.*/ \ - uint8_t ob[SERIAL_BUFFERS_SIZE]; \ - /* End of the mandatory fields.*/ \ - /* Listen socket for simulated serial port.*/ \ - SOCKET com_listen; \ - /* Data socket for simulated serial port.*/ \ - SOCKET com_data; \ - /* Port readable name.*/ \ - const char *com_name; - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if USE_WIN32_SERIAL1 && !defined(__DOXYGEN__) -extern SerialDriver SD1; -#endif -#if USE_WIN32_SERIAL2 && !defined(__DOXYGEN__) -extern SerialDriver SD2; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void sd_lld_init(void); - void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); - void sd_lld_stop(SerialDriver *sdp); - bool_t sd_lld_interrupt_pending(void); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_SERIAL */ - -#endif /* _SERIAL_LLD_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/hal/src/adc.c b/firmware/chibios/os/hal/src/adc.c deleted file mode 100644 index bdb5cef6ce..0000000000 --- a/firmware/chibios/os/hal/src/adc.c +++ /dev/null @@ -1,350 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file adc.c - * @brief ADC Driver code. - * - * @addtogroup ADC - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_ADC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief ADC Driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void adcInit(void) { - - adc_lld_init(); -} - -/** - * @brief Initializes the standard part of a @p ADCDriver structure. - * - * @param[out] adcp pointer to the @p ADCDriver object - * - * @init - */ -void adcObjectInit(ADCDriver *adcp) { - - adcp->state = ADC_STOP; - adcp->config = NULL; - adcp->samples = NULL; - adcp->depth = 0; - adcp->grpp = NULL; -#if ADC_USE_WAIT - adcp->thread = NULL; -#endif /* ADC_USE_WAIT */ -#if ADC_USE_MUTUAL_EXCLUSION -#if CH_USE_MUTEXES - chMtxInit(&adcp->mutex); -#else - chSemInit(&adcp->semaphore, 1); -#endif -#endif /* ADC_USE_MUTUAL_EXCLUSION */ -#if defined(ADC_DRIVER_EXT_INIT_HOOK) - ADC_DRIVER_EXT_INIT_HOOK(adcp); -#endif -} - -/** - * @brief Configures and activates the ADC peripheral. - * - * @param[in] adcp pointer to the @p ADCDriver object - * @param[in] config pointer to the @p ADCConfig object. Depending on - * the implementation the value can be @p NULL. - * - * @api - */ -void adcStart(ADCDriver *adcp, const ADCConfig *config) { - - chDbgCheck(adcp != NULL, "adcStart"); - - chSysLock(); - chDbgAssert((adcp->state == ADC_STOP) || (adcp->state == ADC_READY), - "adcStart(), #1", "invalid state"); - adcp->config = config; - adc_lld_start(adcp); - adcp->state = ADC_READY; - chSysUnlock(); -} - -/** - * @brief Deactivates the ADC peripheral. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @api - */ -void adcStop(ADCDriver *adcp) { - - chDbgCheck(adcp != NULL, "adcStop"); - - chSysLock(); - chDbgAssert((adcp->state == ADC_STOP) || (adcp->state == ADC_READY), - "adcStop(), #1", "invalid state"); - adc_lld_stop(adcp); - adcp->state = ADC_STOP; - chSysUnlock(); -} - -/** - * @brief Starts an ADC conversion. - * @details Starts an asynchronous conversion operation. - * @note The buffer is organized as a matrix of M*N elements where M is the - * channels number configured into the conversion group and N is the - * buffer depth. The samples are sequentially written into the buffer - * with no gaps. - * - * @param[in] adcp pointer to the @p ADCDriver object - * @param[in] grpp pointer to a @p ADCConversionGroup object - * @param[out] samples pointer to the samples buffer - * @param[in] depth buffer depth (matrix rows number). The buffer depth - * must be one or an even number. - * - * @api - */ -void adcStartConversion(ADCDriver *adcp, - const ADCConversionGroup *grpp, - adcsample_t *samples, - size_t depth) { - - chSysLock(); - adcStartConversionI(adcp, grpp, samples, depth); - chSysUnlock(); -} - -/** - * @brief Starts an ADC conversion. - * @details Starts an asynchronous conversion operation. - * @post The callbacks associated to the conversion group will be invoked - * on buffer fill and error events. - * @note The buffer is organized as a matrix of M*N elements where M is the - * channels number configured into the conversion group and N is the - * buffer depth. The samples are sequentially written into the buffer - * with no gaps. - * - * @param[in] adcp pointer to the @p ADCDriver object - * @param[in] grpp pointer to a @p ADCConversionGroup object - * @param[out] samples pointer to the samples buffer - * @param[in] depth buffer depth (matrix rows number). The buffer depth - * must be one or an even number. - * - * @iclass - */ -void adcStartConversionI(ADCDriver *adcp, - const ADCConversionGroup *grpp, - adcsample_t *samples, - size_t depth) { - - chDbgCheckClassI(); - chDbgCheck((adcp != NULL) && (grpp != NULL) && (samples != NULL) && - ((depth == 1) || ((depth & 1) == 0)), - "adcStartConversionI"); - chDbgAssert((adcp->state == ADC_READY) || - (adcp->state == ADC_COMPLETE) || - (adcp->state == ADC_ERROR), - "adcStartConversionI(), #1", "not ready"); - - adcp->samples = samples; - adcp->depth = depth; - adcp->grpp = grpp; - adcp->state = ADC_ACTIVE; - adc_lld_start_conversion(adcp); -} - -/** - * @brief Stops an ongoing conversion. - * @details This function stops the currently ongoing conversion and returns - * the driver in the @p ADC_READY state. If there was no conversion - * being processed then the function does nothing. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @api - */ -void adcStopConversion(ADCDriver *adcp) { - - chDbgCheck(adcp != NULL, "adcStopConversion"); - - chSysLock(); - chDbgAssert((adcp->state == ADC_READY) || - (adcp->state == ADC_ACTIVE), - "adcStopConversion(), #1", "invalid state"); - if (adcp->state != ADC_READY) { - adc_lld_stop_conversion(adcp); - adcp->grpp = NULL; - adcp->state = ADC_READY; - _adc_reset_s(adcp); - } - chSysUnlock(); -} - -/** - * @brief Stops an ongoing conversion. - * @details This function stops the currently ongoing conversion and returns - * the driver in the @p ADC_READY state. If there was no conversion - * being processed then the function does nothing. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @iclass - */ -void adcStopConversionI(ADCDriver *adcp) { - - chDbgCheckClassI(); - chDbgCheck(adcp != NULL, "adcStopConversionI"); - chDbgAssert((adcp->state == ADC_READY) || - (adcp->state == ADC_ACTIVE) || - (adcp->state == ADC_COMPLETE), - "adcStopConversionI(), #1", "invalid state"); - - if (adcp->state != ADC_READY) { - adc_lld_stop_conversion(adcp); - adcp->grpp = NULL; - adcp->state = ADC_READY; - _adc_reset_i(adcp); - } -} - -#if ADC_USE_WAIT || defined(__DOXYGEN__) -/** - * @brief Performs an ADC conversion. - * @details Performs a synchronous conversion operation. - * @note The buffer is organized as a matrix of M*N elements where M is the - * channels number configured into the conversion group and N is the - * buffer depth. The samples are sequentially written into the buffer - * with no gaps. - * - * @param[in] adcp pointer to the @p ADCDriver object - * @param[in] grpp pointer to a @p ADCConversionGroup object - * @param[out] samples pointer to the samples buffer - * @param[in] depth buffer depth (matrix rows number). The buffer depth - * must be one or an even number. - * @return The operation result. - * @retval RDY_OK Conversion finished. - * @retval RDY_RESET The conversion has been stopped using - * @p acdStopConversion() or @p acdStopConversionI(), - * the result buffer may contain incorrect data. - * @retval RDY_TIMEOUT The conversion has been stopped because an hardware - * error. - * - * @api - */ -msg_t adcConvert(ADCDriver *adcp, - const ADCConversionGroup *grpp, - adcsample_t *samples, - size_t depth) { - msg_t msg; - - chSysLock(); - chDbgAssert(adcp->thread == NULL, "adcConvert(), #1", "already waiting"); - adcStartConversionI(adcp, grpp, samples, depth); - adcp->thread = chThdSelf(); - chSchGoSleepS(THD_STATE_SUSPENDED); - msg = chThdSelf()->p_u.rdymsg; - chSysUnlock(); - return msg; -} -#endif /* ADC_USE_WAIT */ - -#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) -/** - * @brief Gains exclusive access to the ADC peripheral. - * @details This function tries to gain ownership to the ADC bus, if the bus - * is already being used then the invoking thread is queued. - * @pre In order to use this function the option - * @p ADC_USE_MUTUAL_EXCLUSION must be enabled. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @api - */ -void adcAcquireBus(ADCDriver *adcp) { - - chDbgCheck(adcp != NULL, "adcAcquireBus"); - -#if CH_USE_MUTEXES - chMtxLock(&adcp->mutex); -#elif CH_USE_SEMAPHORES - chSemWait(&adcp->semaphore); -#endif -} - -/** - * @brief Releases exclusive access to the ADC peripheral. - * @pre In order to use this function the option - * @p ADC_USE_MUTUAL_EXCLUSION must be enabled. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @api - */ -void adcReleaseBus(ADCDriver *adcp) { - - chDbgCheck(adcp != NULL, "adcReleaseBus"); - -#if CH_USE_MUTEXES - (void)adcp; - chMtxUnlock(); -#elif CH_USE_SEMAPHORES - chSemSignal(&adcp->semaphore); -#endif -} -#endif /* ADC_USE_MUTUAL_EXCLUSION */ - -#endif /* HAL_USE_ADC */ - -/** @} */ diff --git a/firmware/chibios/os/hal/src/can.c b/firmware/chibios/os/hal/src/can.c deleted file mode 100644 index 81a2ed1f12..0000000000 --- a/firmware/chibios/os/hal/src/can.c +++ /dev/null @@ -1,292 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file can.c - * @brief CAN Driver code. - * - * @addtogroup CAN - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_CAN || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief CAN Driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void canInit(void) { - - can_lld_init(); -} - -/** - * @brief Initializes the standard part of a @p CANDriver structure. - * - * @param[out] canp pointer to the @p CANDriver object - * - * @init - */ -void canObjectInit(CANDriver *canp) { - - canp->state = CAN_STOP; - canp->config = NULL; - chSemInit(&canp->txsem, 0); - chSemInit(&canp->rxsem, 0); - chEvtInit(&canp->rxfull_event); - chEvtInit(&canp->txempty_event); - chEvtInit(&canp->error_event); -#if CAN_USE_SLEEP_MODE - chEvtInit(&canp->sleep_event); - chEvtInit(&canp->wakeup_event); -#endif /* CAN_USE_SLEEP_MODE */ -} - -/** - * @brief Configures and activates the CAN peripheral. - * @note Activating the CAN bus can be a slow operation this this function - * is not atomic, it waits internally for the initialization to - * complete. - * - * @param[in] canp pointer to the @p CANDriver object - * @param[in] config pointer to the @p CANConfig object. Depending on - * the implementation the value can be @p NULL. - * - * @api - */ -void canStart(CANDriver *canp, const CANConfig *config) { - - chDbgCheck(canp != NULL, "canStart"); - - chSysLock(); - chDbgAssert((canp->state == CAN_STOP) || - (canp->state == CAN_STARTING) || - (canp->state == CAN_READY), - "canStart(), #1", "invalid state"); - while (canp->state == CAN_STARTING) - chThdSleepS(1); - if (canp->state == CAN_STOP) { - canp->config = config; - can_lld_start(canp); - canp->state = CAN_READY; - } - chSysUnlock(); -} - -/** - * @brief Deactivates the CAN peripheral. - * - * @param[in] canp pointer to the @p CANDriver object - * - * @api - */ -void canStop(CANDriver *canp) { - - chDbgCheck(canp != NULL, "canStop"); - - chSysLock(); - chDbgAssert((canp->state == CAN_STOP) || (canp->state == CAN_READY), - "canStop(), #1", "invalid state"); - can_lld_stop(canp); - canp->state = CAN_STOP; - chSemResetI(&canp->rxsem, 0); - chSemResetI(&canp->txsem, 0); - chSchRescheduleS(); - chSysUnlock(); -} - -/** - * @brief Can frame transmission. - * @details The specified frame is queued for transmission, if the hardware - * queue is full then the invoking thread is queued. - * @note Trying to transmit while in sleep mode simply enqueues the thread. - * - * @param[in] canp pointer to the @p CANDriver object - * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox - * @param[in] ctfp pointer to the CAN frame to be transmitted - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation result. - * @retval RDY_OK the frame has been queued for transmission. - * @retval RDY_TIMEOUT The operation has timed out. - * @retval RDY_RESET The driver has been stopped while waiting. - * - * @api - */ -msg_t canTransmit(CANDriver *canp, - canmbx_t mailbox, - const CANTxFrame *ctfp, - systime_t timeout) { - - chDbgCheck((canp != NULL) && (ctfp != NULL) && (mailbox <= CAN_TX_MAILBOXES), - "canTransmit"); - - chSysLock(); - chDbgAssert((canp->state == CAN_READY) || (canp->state == CAN_SLEEP), - "canTransmit(), #1", "invalid state"); - while ((canp->state == CAN_SLEEP) || !can_lld_is_tx_empty(canp, mailbox)) { - msg_t msg = chSemWaitTimeoutS(&canp->txsem, timeout); - if (msg != RDY_OK) { - chSysUnlock(); - return msg; - } - } - can_lld_transmit(canp, mailbox, ctfp); - chSysUnlock(); - return RDY_OK; -} - -/** - * @brief Can frame receive. - * @details The function waits until a frame is received. - * @note Trying to receive while in sleep mode simply enqueues the thread. - * - * @param[in] canp pointer to the @p CANDriver object - * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox - * @param[out] crfp pointer to the buffer where the CAN frame is copied - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout (useful in an - * event driven scenario where a thread never blocks - * for I/O). - * - @a TIME_INFINITE no timeout. - * . - * @return The operation result. - * @retval RDY_OK a frame has been received and placed in the buffer. - * @retval RDY_TIMEOUT The operation has timed out. - * @retval RDY_RESET The driver has been stopped while waiting. - * - * @api - */ -msg_t canReceive(CANDriver *canp, - canmbx_t mailbox, - CANRxFrame *crfp, - systime_t timeout) { - - chDbgCheck((canp != NULL) && (crfp != NULL) && (mailbox <= CAN_RX_MAILBOXES), - "canReceive"); - - chSysLock(); - chDbgAssert((canp->state == CAN_READY) || (canp->state == CAN_SLEEP), - "canReceive(), #1", "invalid state"); - while ((canp->state == CAN_SLEEP) || !can_lld_is_rx_nonempty(canp, mailbox)) { - msg_t msg = chSemWaitTimeoutS(&canp->rxsem, timeout); - if (msg != RDY_OK) { - chSysUnlock(); - return msg; - } - } - can_lld_receive(canp, mailbox, crfp); - chSysUnlock(); - return RDY_OK; -} - -#if CAN_USE_SLEEP_MODE || defined(__DOXYGEN__) -/** - * @brief Enters the sleep mode. - * @details This function puts the CAN driver in sleep mode and broadcasts - * the @p sleep_event event source. - * @pre In order to use this function the option @p CAN_USE_SLEEP_MODE must - * be enabled and the @p CAN_SUPPORTS_SLEEP mode must be supported - * by the low level driver. - * - * @param[in] canp pointer to the @p CANDriver object - * - * @api - */ -void canSleep(CANDriver *canp) { - - chDbgCheck(canp != NULL, "canSleep"); - - chSysLock(); - chDbgAssert((canp->state == CAN_READY) || (canp->state == CAN_SLEEP), - "canSleep(), #1", "invalid state"); - if (canp->state == CAN_READY) { - can_lld_sleep(canp); - canp->state = CAN_SLEEP; - chEvtBroadcastI(&canp->sleep_event); - chSchRescheduleS(); - } - chSysUnlock(); -} - -/** - * @brief Enforces leaving the sleep mode. - * @note The sleep mode is supposed to be usually exited automatically by - * an hardware event. - * - * @param[in] canp pointer to the @p CANDriver object - */ -void canWakeup(CANDriver *canp) { - - chDbgCheck(canp != NULL, "canWakeup"); - - chSysLock(); - chDbgAssert((canp->state == CAN_READY) || (canp->state == CAN_SLEEP), - "canWakeup(), #1", "invalid state"); - if (canp->state == CAN_SLEEP) { - can_lld_wakeup(canp); - canp->state = CAN_READY; - chEvtBroadcastI(&canp->wakeup_event); - chSchRescheduleS(); - } - chSysUnlock(); -} -#endif /* CAN_USE_SLEEP_MODE */ - -#endif /* HAL_USE_CAN */ - -/** @} */ diff --git a/firmware/chibios/os/hal/src/ext.c b/firmware/chibios/os/hal/src/ext.c deleted file mode 100644 index e45ed2134d..0000000000 --- a/firmware/chibios/os/hal/src/ext.c +++ /dev/null @@ -1,214 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file ext.c - * @brief EXT Driver code. - * - * @addtogroup EXT - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief EXT Driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void extInit(void) { - - ext_lld_init(); -} - -/** - * @brief Initializes the standard part of a @p EXTDriver structure. - * - * @param[out] extp pointer to the @p EXTDriver object - * - * @init - */ -void extObjectInit(EXTDriver *extp) { - - extp->state = EXT_STOP; - extp->config = NULL; -} - -/** - * @brief Configures and activates the EXT peripheral. - * @post After activation all EXT channels are in the disabled state, - * use @p extChannelEnable() in order to activate them. - * - * @param[in] extp pointer to the @p EXTDriver object - * @param[in] config pointer to the @p EXTConfig object - * - * @api - */ -void extStart(EXTDriver *extp, const EXTConfig *config) { - - chDbgCheck((extp != NULL) && (config != NULL), "extStart"); - - chSysLock(); - chDbgAssert((extp->state == EXT_STOP) || (extp->state == EXT_ACTIVE), - "extStart(), #1", "invalid state"); - extp->config = config; - ext_lld_start(extp); - extp->state = EXT_ACTIVE; - chSysUnlock(); -} - -/** - * @brief Deactivates the EXT peripheral. - * - * @param[in] extp pointer to the @p EXTDriver object - * - * @api - */ -void extStop(EXTDriver *extp) { - - chDbgCheck(extp != NULL, "extStop"); - - chSysLock(); - chDbgAssert((extp->state == EXT_STOP) || (extp->state == EXT_ACTIVE), - "extStop(), #1", "invalid state"); - ext_lld_stop(extp); - extp->state = EXT_STOP; - chSysUnlock(); -} - -/** - * @brief Enables an EXT channel. - * @pre The channel must not be in @p EXT_CH_MODE_DISABLED mode. - * - * @param[in] extp pointer to the @p EXTDriver object - * @param[in] channel channel to be enabled - * - * @api - */ -void extChannelEnable(EXTDriver *extp, expchannel_t channel) { - - chDbgCheck((extp != NULL) && (channel < EXT_MAX_CHANNELS), - "extChannelEnable"); - - chSysLock(); - chDbgAssert((extp->state == EXT_ACTIVE) && - ((extp->config->channels[channel].mode & - EXT_CH_MODE_EDGES_MASK) != EXT_CH_MODE_DISABLED), - "extChannelEnable(), #1", "invalid state"); - extChannelEnableI(extp, channel); - chSysUnlock(); -} - -/** - * @brief Disables an EXT channel. - * @pre The channel must not be in @p EXT_CH_MODE_DISABLED mode. - * - * @param[in] extp pointer to the @p EXTDriver object - * @param[in] channel channel to be disabled - * - * @api - */ -void extChannelDisable(EXTDriver *extp, expchannel_t channel) { - - chDbgCheck((extp != NULL) && (channel < EXT_MAX_CHANNELS), - "extChannelDisable"); - - chSysLock(); - chDbgAssert((extp->state == EXT_ACTIVE) && - ((extp->config->channels[channel].mode & - EXT_CH_MODE_EDGES_MASK) != EXT_CH_MODE_DISABLED), - "extChannelDisable(), #1", "invalid state"); - extChannelDisableI(extp, channel); - chSysUnlock(); -} - -/** - * @brief Changes the operation mode of a channel. - * @note This function attempts to write over the current configuration - * structure that must have been not declared constant. This - * violates the @p const qualifier in @p extStart() but it is - * intentional. - * @note This function cannot be used if the configuration structure is - * declared @p const. - * @note The effect of this function on constant configuration structures - * is not defined. - * - * @param[in] extp pointer to the @p EXTDriver object - * @param[in] channel channel to be changed - * @param[in] extcp new configuration for the channel - * - * @iclass - */ -void extSetChannelModeI(EXTDriver *extp, - expchannel_t channel, - const EXTChannelConfig *extcp) { - EXTChannelConfig *oldcp; - - chDbgCheck((extp != NULL) && (channel < EXT_MAX_CHANNELS) && - (extcp != NULL), "extSetChannelModeI"); - - chDbgAssert(extp->state == EXT_ACTIVE, - "extSetChannelModeI(), #1", "invalid state"); - - /* Note that here the access is enforced as non-const, known access - violation.*/ - oldcp = (EXTChannelConfig *)&extp->config->channels[channel]; - - /* Overwiting the old channels configuration then the channel is reconfigured - by the low level driver.*/ - *oldcp = *extcp; - ext_lld_channel_enable(extp, channel); -} - -#endif /* HAL_USE_EXT */ - -/** @} */ diff --git a/firmware/chibios/os/hal/src/gpt.c b/firmware/chibios/os/hal/src/gpt.c deleted file mode 100644 index e9a3c0f21b..0000000000 --- a/firmware/chibios/os/hal/src/gpt.c +++ /dev/null @@ -1,275 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file gpt.c - * @brief GPT Driver code. - * - * @addtogroup GPT - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_GPT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief GPT Driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void gptInit(void) { - - gpt_lld_init(); -} - -/** - * @brief Initializes the standard part of a @p GPTDriver structure. - * - * @param[out] gptp pointer to the @p GPTDriver object - * - * @init - */ -void gptObjectInit(GPTDriver *gptp) { - - gptp->state = GPT_STOP; - gptp->config = NULL; -} - -/** - * @brief Configures and activates the GPT peripheral. - * - * @param[in] gptp pointer to the @p GPTDriver object - * @param[in] config pointer to the @p GPTConfig object - * - * @api - */ -void gptStart(GPTDriver *gptp, const GPTConfig *config) { - - chDbgCheck((gptp != NULL) && (config != NULL), "gptStart"); - - chSysLock(); - chDbgAssert((gptp->state == GPT_STOP) || (gptp->state == GPT_READY), - "gptStart(), #1", "invalid state"); - gptp->config = config; - gpt_lld_start(gptp); - gptp->state = GPT_READY; - chSysUnlock(); -} - -/** - * @brief Deactivates the GPT peripheral. - * - * @param[in] gptp pointer to the @p GPTDriver object - * - * @api - */ -void gptStop(GPTDriver *gptp) { - - chDbgCheck(gptp != NULL, "gptStop"); - - chSysLock(); - chDbgAssert((gptp->state == GPT_STOP) || (gptp->state == GPT_READY), - "gptStop(), #1", "invalid state"); - gpt_lld_stop(gptp); - gptp->state = GPT_STOP; - chSysUnlock(); -} - -/** - * @brief Changes the interval of GPT peripheral. - * @details This function changes the interval of a running GPT unit. - * @pre The GPT unit must have been activated using @p gptStart(). - * @pre The GPT unit must have been running in continuous mode using - * @p gptStartContinuous(). - * @post The GPT unit interval is changed to the new value. - * - * @param[in] gptp pointer to a @p GPTDriver object - * @param[in] interval new cycle time in timer ticks - * - * @api - */ -void gptChangeInterval(GPTDriver *gptp, gptcnt_t interval) { - - chDbgCheck(gptp != NULL, "gptChangeInterval"); - - chSysLock(); - chDbgAssert(gptp->state == GPT_CONTINUOUS, - "gptChangeInterval(), #1", "invalid state"); - gptChangeIntervalI(gptp, interval); - chSysUnlock(); -} - -/** - * @brief Starts the timer in continuous mode. - * - * @param[in] gptp pointer to the @p GPTDriver object - * @param[in] interval period in ticks - * - * @api - */ -void gptStartContinuous(GPTDriver *gptp, gptcnt_t interval) { - - chSysLock(); - gptStartContinuousI(gptp, interval); - chSysUnlock(); -} - -/** - * @brief Starts the timer in continuous mode. - * - * @param[in] gptp pointer to the @p GPTDriver object - * @param[in] interval period in ticks - * - * @iclass - */ -void gptStartContinuousI(GPTDriver *gptp, gptcnt_t interval) { - - chDbgCheckClassI(); - chDbgCheck(gptp != NULL, "gptStartContinuousI"); - chDbgAssert(gptp->state == GPT_READY, - "gptStartContinuousI(), #1", "invalid state"); - - gptp->state = GPT_CONTINUOUS; - gpt_lld_start_timer(gptp, interval); -} - -/** - * @brief Starts the timer in one shot mode. - * - * @param[in] gptp pointer to the @p GPTDriver object - * @param[in] interval time interval in ticks - * - * @api - */ -void gptStartOneShot(GPTDriver *gptp, gptcnt_t interval) { - - chSysLock(); - gptStartOneShotI(gptp, interval); - chSysUnlock(); -} - -/** - * @brief Starts the timer in one shot mode. - * - * @param[in] gptp pointer to the @p GPTDriver object - * @param[in] interval time interval in ticks - * - * @api - */ -void gptStartOneShotI(GPTDriver *gptp, gptcnt_t interval) { - - chDbgCheckClassI(); - chDbgCheck(gptp != NULL, "gptStartOneShotI"); - chDbgAssert(gptp->state == GPT_READY, - "gptStartOneShotI(), #1", "invalid state"); - - gptp->state = GPT_ONESHOT; - gpt_lld_start_timer(gptp, interval); -} - -/** - * @brief Stops the timer. - * - * @param[in] gptp pointer to the @p GPTDriver object - * - * @api - */ -void gptStopTimer(GPTDriver *gptp) { - - chSysLock(); - gptStopTimerI(gptp); - chSysUnlock(); -} - -/** - * @brief Stops the timer. - * - * @param[in] gptp pointer to the @p GPTDriver object - * - * @api - */ -void gptStopTimerI(GPTDriver *gptp) { - - chDbgCheckClassI(); - chDbgCheck(gptp != NULL, "gptStopTimerI"); - chDbgAssert((gptp->state == GPT_READY) || (gptp->state == GPT_CONTINUOUS) || - (gptp->state == GPT_ONESHOT), - "gptStopTimerI(), #1", "invalid state"); - - gptp->state = GPT_READY; - gpt_lld_stop_timer(gptp); -} - -/** - * @brief Starts the timer in one shot mode and waits for completion. - * @details This function specifically polls the timer waiting for completion - * in order to not have extra delays caused by interrupt servicing, - * this function is only recommended for short delays. - * @note The configured callback is not invoked when using this function. - * - * @param[in] gptp pointer to the @p GPTDriver object - * @param[in] interval time interval in ticks - * - * @api - */ -void gptPolledDelay(GPTDriver *gptp, gptcnt_t interval) { - - chDbgAssert(gptp->state == GPT_READY, - "gptPolledDelay(), #1", "invalid state"); - - gptp->state = GPT_ONESHOT; - gpt_lld_polled_delay(gptp, interval); - gptp->state = GPT_READY; -} - -#endif /* HAL_USE_GPT */ - -/** @} */ diff --git a/firmware/chibios/os/hal/src/hal.c b/firmware/chibios/os/hal/src/hal.c deleted file mode 100644 index e70d87fd63..0000000000 --- a/firmware/chibios/os/hal/src/hal.c +++ /dev/null @@ -1,201 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file hal.c - * @brief HAL subsystem code. - * - * @addtogroup HAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief HAL initialization. - * @details This function invokes the low level initialization code then - * initializes all the drivers enabled in the HAL. Finally the - * board-specific initialization is performed by invoking - * @p boardInit() (usually defined in @p board.c). - * - * @init - */ -void halInit(void) { - - hal_lld_init(); - -#if HAL_USE_TM || defined(__DOXYGEN__) - tmInit(); -#endif -#if HAL_USE_PAL || defined(__DOXYGEN__) - palInit(&pal_default_config); -#endif -#if HAL_USE_ADC || defined(__DOXYGEN__) - adcInit(); -#endif -#if HAL_USE_CAN || defined(__DOXYGEN__) - canInit(); -#endif -#if HAL_USE_EXT || defined(__DOXYGEN__) - extInit(); -#endif -#if HAL_USE_GPT || defined(__DOXYGEN__) - gptInit(); -#endif -#if HAL_USE_I2C || defined(__DOXYGEN__) - i2cInit(); -#endif -#if HAL_USE_ICU || defined(__DOXYGEN__) - icuInit(); -#endif -#if HAL_USE_MAC || defined(__DOXYGEN__) - macInit(); -#endif -#if HAL_USE_PWM || defined(__DOXYGEN__) - pwmInit(); -#endif -#if HAL_USE_SERIAL || defined(__DOXYGEN__) - sdInit(); -#endif -#if HAL_USE_SDC || defined(__DOXYGEN__) - sdcInit(); -#endif -#if HAL_USE_SPI || defined(__DOXYGEN__) - spiInit(); -#endif -#if HAL_USE_UART || defined(__DOXYGEN__) - uartInit(); -#endif -#if HAL_USE_USB || defined(__DOXYGEN__) - usbInit(); -#endif -#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) - mmcInit(); -#endif -#if HAL_USE_SERIAL_USB || defined(__DOXYGEN__) - sduInit(); -#endif -#if HAL_USE_RTC || defined(__DOXYGEN__) - rtcInit(); -#endif - /* Board specific initialization.*/ - boardInit(); -} - -#if HAL_IMPLEMENTS_COUNTERS || defined(__DOXYGEN__) -/** - * @brief Realtime window test. - * @details This function verifies if the current realtime counter value - * lies within the specified range or not. The test takes care - * of the realtime counter wrapping to zero on overflow. - * @note When start==end then the function returns always true because the - * whole time range is specified. - * @note This is an optional service that could not be implemented in - * all HAL implementations. - * @note This function can be called from any context. - * - * @par Example 1 - * Example of a guarded loop using the realtime counter. The loop implements - * a timeout after one second. - * @code - * halrtcnt_t start = halGetCounterValue(); - * halrtcnt_t timeout = start + S2RTT(1); - * while (my_condition) { - * if (!halIsCounterWithin(start, timeout) - * return TIMEOUT; - * // Do something. - * } - * // Continue. - * @endcode - * - * @par Example 2 - * Example of a loop that lasts exactly 50 microseconds. - * @code - * halrtcnt_t start = halGetCounterValue(); - * halrtcnt_t timeout = start + US2RTT(50); - * while (halIsCounterWithin(start, timeout)) { - * // Do something. - * } - * // Continue. - * @endcode - * - * @param[in] start the start of the time window (inclusive) - * @param[in] end the end of the time window (non inclusive) - * @retval TRUE current time within the specified time window. - * @retval FALSE current time not within the specified time window. - * - * @special - */ -bool_t halIsCounterWithin(halrtcnt_t start, halrtcnt_t end) { - halrtcnt_t now = halGetCounterValue(); - - return end > start ? (now >= start) && (now < end) : - (now >= start) || (now < end); -} - -/** - * @brief Polled delay. - * @note The real delays is always few cycles in excess of the specified - * value. - * @note This is an optional service that could not be implemented in - * all HAL implementations. - * @note This function can be called from any context. - * - * @param[in] ticks number of ticks - * - * @special - */ -void halPolledDelay(halrtcnt_t ticks) { - halrtcnt_t start = halGetCounterValue(); - halrtcnt_t timeout = start + (ticks); - while (halIsCounterWithin(start, timeout)) - ; -} -#endif /* HAL_IMPLEMENTS_COUNTERS */ - -/** @} */ diff --git a/firmware/chibios/os/hal/src/i2c.c b/firmware/chibios/os/hal/src/i2c.c deleted file mode 100644 index 5f6410222b..0000000000 --- a/firmware/chibios/os/hal/src/i2c.c +++ /dev/null @@ -1,310 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ -/* - Concepts and parts of this file have been contributed by Uladzimir Pylinsky - aka barthess. - */ - -/** - * @file i2c.c - * @brief I2C Driver code. - * - * @addtogroup I2C - * @{ - */ -#include "ch.h" -#include "hal.h" - -#if HAL_USE_I2C || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief I2C Driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void i2cInit(void) { - i2c_lld_init(); -} - -/** - * @brief Initializes the standard part of a @p I2CDriver structure. - * - * @param[out] i2cp pointer to the @p I2CDriver object - * - * @init - */ -void i2cObjectInit(I2CDriver *i2cp) { - - i2cp->state = I2C_STOP; - i2cp->config = NULL; - -#if I2C_USE_MUTUAL_EXCLUSION -#if CH_USE_MUTEXES - chMtxInit(&i2cp->mutex); -#else - chSemInit(&i2cp->semaphore, 1); -#endif /* CH_USE_MUTEXES */ -#endif /* I2C_USE_MUTUAL_EXCLUSION */ - -#if defined(I2C_DRIVER_EXT_INIT_HOOK) - I2C_DRIVER_EXT_INIT_HOOK(i2cp); -#endif -} - -/** - * @brief Configures and activates the I2C peripheral. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] config pointer to the @p I2CConfig object - * - * @api - */ -void i2cStart(I2CDriver *i2cp, const I2CConfig *config) { - - chDbgCheck((i2cp != NULL) && (config != NULL), "i2cStart"); - chDbgAssert((i2cp->state == I2C_STOP) || (i2cp->state == I2C_READY) || - (i2cp->state == I2C_LOCKED), - "i2cStart(), #1", - "invalid state"); - - chSysLock(); - i2cp->config = config; - i2c_lld_start(i2cp); - i2cp->state = I2C_READY; - chSysUnlock(); -} - -/** - * @brief Deactivates the I2C peripheral. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @api - */ -void i2cStop(I2CDriver *i2cp) { - - chDbgCheck(i2cp != NULL, "i2cStop"); - chDbgAssert((i2cp->state == I2C_STOP) || (i2cp->state == I2C_READY) || - (i2cp->state == I2C_LOCKED), - "i2cStop(), #1", - "invalid state"); - - chSysLock(); - i2c_lld_stop(i2cp); - i2cp->state = I2C_STOP; - chSysUnlock(); -} - -/** - * @brief Returns the errors mask associated to the previous operation. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * @return The errors mask. - * - * @api - */ -i2cflags_t i2cGetErrors(I2CDriver *i2cp) { - - chDbgCheck(i2cp != NULL, "i2cGetErrors"); - - return i2c_lld_get_errors(i2cp); -} - -/** - * @brief Sends data via the I2C bus. - * @details Function designed to realize "read-through-write" transfer - * paradigm. If you want transmit data without any further read, - * than set @b rxbytes field to 0. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] addr slave device address (7 bits) without R/W bit - * @param[in] txbuf pointer to transmit buffer - * @param[in] txbytes number of bytes to be transmitted - * @param[out] rxbuf pointer to receive buffer - * @param[in] rxbytes number of bytes to be received, set it to 0 if - * you want transmit only - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_INFINITE no timeout. - * . - * - * @return The operation status. - * @retval RDY_OK if the function succeeded. - * @retval RDY_RESET if one or more I2C errors occurred, the errors can - * be retrieved using @p i2cGetErrors(). - * @retval RDY_TIMEOUT if a timeout occurred before operation end. - * - * @api - */ -msg_t i2cMasterTransmitTimeout(I2CDriver *i2cp, - i2caddr_t addr, - const uint8_t *txbuf, - size_t txbytes, - uint8_t *rxbuf, - size_t rxbytes, - systime_t timeout) { - msg_t rdymsg; - - chDbgCheck((i2cp != NULL) && (addr != 0) && - (txbytes > 0) && (txbuf != NULL) && - ((rxbytes == 0) || ((rxbytes > 0) && (rxbuf != NULL))) && - (timeout != TIME_IMMEDIATE), - "i2cMasterTransmitTimeout"); - - chDbgAssert(i2cp->state == I2C_READY, - "i2cMasterTransmitTimeout(), #1", "not ready"); - - chSysLock(); - i2cp->errors = I2CD_NO_ERROR; - i2cp->state = I2C_ACTIVE_TX; - rdymsg = i2c_lld_master_transmit_timeout(i2cp, addr, txbuf, txbytes, - rxbuf, rxbytes, timeout); - if (rdymsg == RDY_TIMEOUT) - i2cp->state = I2C_LOCKED; - else - i2cp->state = I2C_READY; - chSysUnlock(); - return rdymsg; -} - -/** - * @brief Receives data from the I2C bus. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] addr slave device address (7 bits) without R/W bit - * @param[out] rxbuf pointer to receive buffer - * @param[in] rxbytes number of bytes to be received - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_INFINITE no timeout. - * . - * - * @return The operation status. - * @retval RDY_OK if the function succeeded. - * @retval RDY_RESET if one or more I2C errors occurred, the errors can - * be retrieved using @p i2cGetErrors(). - * @retval RDY_TIMEOUT if a timeout occurred before operation end. - * - * @api - */ -msg_t i2cMasterReceiveTimeout(I2CDriver *i2cp, - i2caddr_t addr, - uint8_t *rxbuf, - size_t rxbytes, - systime_t timeout){ - - msg_t rdymsg; - - chDbgCheck((i2cp != NULL) && (addr != 0) && - (rxbytes > 0) && (rxbuf != NULL) && - (timeout != TIME_IMMEDIATE), - "i2cMasterReceiveTimeout"); - - chDbgAssert(i2cp->state == I2C_READY, - "i2cMasterReceive(), #1", "not ready"); - - chSysLock(); - i2cp->errors = I2CD_NO_ERROR; - i2cp->state = I2C_ACTIVE_RX; - rdymsg = i2c_lld_master_receive_timeout(i2cp, addr, rxbuf, rxbytes, timeout); - if (rdymsg == RDY_TIMEOUT) - i2cp->state = I2C_LOCKED; - else - i2cp->state = I2C_READY; - chSysUnlock(); - return rdymsg; -} - -#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) -/** - * @brief Gains exclusive access to the I2C bus. - * @details This function tries to gain ownership to the I2C bus, if the bus - * is already being used then the invoking thread is queued. - * @pre In order to use this function the option @p I2C_USE_MUTUAL_EXCLUSION - * must be enabled. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @api - */ -void i2cAcquireBus(I2CDriver *i2cp) { - - chDbgCheck(i2cp != NULL, "i2cAcquireBus"); - -#if CH_USE_MUTEXES - chMtxLock(&i2cp->mutex); -#elif CH_USE_SEMAPHORES - chSemWait(&i2cp->semaphore); -#endif -} - -/** - * @brief Releases exclusive access to the I2C bus. - * @pre In order to use this function the option @p I2C_USE_MUTUAL_EXCLUSION - * must be enabled. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @api - */ -void i2cReleaseBus(I2CDriver *i2cp) { - - chDbgCheck(i2cp != NULL, "i2cReleaseBus"); - -#if CH_USE_MUTEXES - chMtxUnlock(); -#elif CH_USE_SEMAPHORES - chSemSignal(&i2cp->semaphore); -#endif -} -#endif /* I2C_USE_MUTUAL_EXCLUSION */ - -#endif /* HAL_USE_I2C */ - -/** @} */ diff --git a/firmware/chibios/os/hal/src/icu.c b/firmware/chibios/os/hal/src/icu.c deleted file mode 100644 index 698a776218..0000000000 --- a/firmware/chibios/os/hal/src/icu.c +++ /dev/null @@ -1,166 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file icu.c - * @brief ICU Driver code. - * - * @addtogroup ICU - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_ICU || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief ICU Driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void icuInit(void) { - - icu_lld_init(); -} - -/** - * @brief Initializes the standard part of a @p ICUDriver structure. - * - * @param[out] icup pointer to the @p ICUDriver object - * - * @init - */ -void icuObjectInit(ICUDriver *icup) { - - icup->state = ICU_STOP; - icup->config = NULL; -} - -/** - * @brief Configures and activates the ICU peripheral. - * - * @param[in] icup pointer to the @p ICUDriver object - * @param[in] config pointer to the @p ICUConfig object - * - * @api - */ -void icuStart(ICUDriver *icup, const ICUConfig *config) { - - chDbgCheck((icup != NULL) && (config != NULL), "icuStart"); - - chSysLock(); - chDbgAssert((icup->state == ICU_STOP) || (icup->state == ICU_READY), - "icuStart(), #1", "invalid state"); - icup->config = config; - icu_lld_start(icup); - icup->state = ICU_READY; - chSysUnlock(); -} - -/** - * @brief Deactivates the ICU peripheral. - * - * @param[in] icup pointer to the @p ICUDriver object - * - * @api - */ -void icuStop(ICUDriver *icup) { - - chDbgCheck(icup != NULL, "icuStop"); - - chSysLock(); - chDbgAssert((icup->state == ICU_STOP) || (icup->state == ICU_READY), - "icuStop(), #1", "invalid state"); - icu_lld_stop(icup); - icup->state = ICU_STOP; - chSysUnlock(); -} - -/** - * @brief Enables the input capture. - * - * @param[in] icup pointer to the @p ICUDriver object - * - * @api - */ -void icuEnable(ICUDriver *icup) { - - chDbgCheck(icup != NULL, "icuEnable"); - - chSysLock(); - chDbgAssert(icup->state == ICU_READY, "icuEnable(), #1", "invalid state"); - icu_lld_enable(icup); - icup->state = ICU_WAITING; - chSysUnlock(); -} - -/** - * @brief Disables the input capture. - * - * @param[in] icup pointer to the @p ICUDriver object - * - * @api - */ -void icuDisable(ICUDriver *icup) { - - chDbgCheck(icup != NULL, "icuDisable"); - - chSysLock(); - chDbgAssert((icup->state == ICU_READY) || (icup->state == ICU_WAITING) || - (icup->state == ICU_ACTIVE) || (icup->state == ICU_IDLE), - "icuDisable(), #1", "invalid state"); - icu_lld_disable(icup); - icup->state = ICU_READY; - chSysUnlock(); -} - -#endif /* HAL_USE_ICU */ - -/** @} */ diff --git a/firmware/chibios/os/hal/src/mac.c b/firmware/chibios/os/hal/src/mac.c deleted file mode 100644 index 64d576845d..0000000000 --- a/firmware/chibios/os/hal/src/mac.c +++ /dev/null @@ -1,279 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file mac.c - * @brief MAC Driver code. - * - * @addtogroup MAC - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_MAC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#if MAC_USE_ZERO_COPY && !MAC_SUPPORTS_ZERO_COPY -#error "MAC_USE_ZERO_COPY not supported by this implementation" -#endif - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief MAC Driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void macInit(void) { - - mac_lld_init(); -} - -/** - * @brief Initialize the standard part of a @p MACDriver structure. - * - * @param[out] macp pointer to the @p MACDriver object - * - * @init - */ -void macObjectInit(MACDriver *macp) { - - macp->state = MAC_STOP; - macp->config = NULL; - chSemInit(&macp->tdsem, 0); - chSemInit(&macp->rdsem, 0); -#if MAC_USE_EVENTS - chEvtInit(&macp->rdevent); -#endif -} - -/** - * @brief Configures and activates the MAC peripheral. - * - * @param[in] macp pointer to the @p MACDriver object - * @param[in] config pointer to the @p MACConfig object - * - * @api - */ -void macStart(MACDriver *macp, const MACConfig *config) { - - chDbgCheck((macp != NULL) && (config != NULL), "macStart"); - - chSysLock(); - chDbgAssert(macp->state == MAC_STOP, - "macStart(), #1", "invalid state"); - macp->config = config; - mac_lld_start(macp); - macp->state = MAC_ACTIVE; - chSysUnlock(); -} - -/** - * @brief Deactivates the MAC peripheral. - * - * @param[in] macp pointer to the @p MACDriver object - * - * @api - */ -void macStop(MACDriver *macp) { - - chDbgCheck(macp != NULL, "macStop"); - - chSysLock(); - chDbgAssert((macp->state == MAC_STOP) || (macp->state == MAC_ACTIVE), - "macStop(), #1", "invalid state"); - mac_lld_stop(macp); - macp->state = MAC_STOP; - chSysUnlock(); -} - -/** - * @brief Allocates a transmission descriptor. - * @details One of the available transmission descriptors is locked and - * returned. If a descriptor is not currently available then the - * invoking thread is queued until one is freed. - * - * @param[in] macp pointer to the @p MACDriver object - * @param[out] tdp pointer to a @p MACTransmitDescriptor structure - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval RDY_OK the descriptor was obtained. - * @retval RDY_TIMEOUT the operation timed out, descriptor not initialized. - * - * @api - */ -msg_t macWaitTransmitDescriptor(MACDriver *macp, - MACTransmitDescriptor *tdp, - systime_t time) { - msg_t msg; - systime_t now; - - chDbgCheck((macp != NULL) && (tdp != NULL), "macWaitTransmitDescriptor"); - chDbgAssert(macp->state == MAC_ACTIVE, "macWaitTransmitDescriptor(), #1", - "not active"); - - while (((msg = mac_lld_get_transmit_descriptor(macp, tdp)) != RDY_OK) && - (time > 0)) { - chSysLock(); - now = chTimeNow(); - if ((msg = chSemWaitTimeoutS(&macp->tdsem, time)) == RDY_TIMEOUT) { - chSysUnlock(); - break; - } - if (time != TIME_INFINITE) - time -= (chTimeNow() - now); - chSysUnlock(); - } - return msg; -} - -/** - * @brief Releases a transmit descriptor and starts the transmission of the - * enqueued data as a single frame. - * - * @param[in] tdp the pointer to the @p MACTransmitDescriptor structure - * - * @api - */ -void macReleaseTransmitDescriptor(MACTransmitDescriptor *tdp) { - - chDbgCheck((tdp != NULL), "macReleaseTransmitDescriptor"); - - mac_lld_release_transmit_descriptor(tdp); -} - -/** - * @brief Waits for a received frame. - * @details Stops until a frame is received and buffered. If a frame is - * not immediately available then the invoking thread is queued - * until one is received. - * - * @param[in] macp pointer to the @p MACDriver object - * @param[out] rdp pointer to a @p MACReceiveDescriptor structure - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval RDY_OK the descriptor was obtained. - * @retval RDY_TIMEOUT the operation timed out, descriptor not initialized. - * - * @api - */ -msg_t macWaitReceiveDescriptor(MACDriver *macp, - MACReceiveDescriptor *rdp, - systime_t time) { - msg_t msg; - systime_t now; - - chDbgCheck((macp != NULL) && (rdp != NULL), "macWaitReceiveDescriptor"); - chDbgAssert(macp->state == MAC_ACTIVE, "macWaitReceiveDescriptor(), #1", - "not active"); - - while (((msg = mac_lld_get_receive_descriptor(macp, rdp)) != RDY_OK) && - (time > 0)) { - chSysLock(); - now = chTimeNow(); - if ((msg = chSemWaitTimeoutS(&macp->rdsem, time)) == RDY_TIMEOUT) { - chSysUnlock(); - break; - } - if (time != TIME_INFINITE) - time -= (chTimeNow() - now); - chSysUnlock(); - } - return msg; -} - -/** - * @brief Releases a receive descriptor. - * @details The descriptor and its buffer are made available for more incoming - * frames. - * - * @param[in] rdp the pointer to the @p MACReceiveDescriptor structure - * - * @api - */ -void macReleaseReceiveDescriptor(MACReceiveDescriptor *rdp) { - - chDbgCheck((rdp != NULL), "macReleaseReceiveDescriptor"); - - mac_lld_release_receive_descriptor(rdp); -} - -/** - * @brief Updates and returns the link status. - * - * @param[in] macp pointer to the @p MACDriver object - * @return The link status. - * @retval TRUE if the link is active. - * @retval FALSE if the link is down. - * - * @api - */ -bool_t macPollLinkStatus(MACDriver *macp) { - - chDbgCheck((macp != NULL), "macPollLinkStatus"); - chDbgAssert(macp->state == MAC_ACTIVE, "macPollLinkStatus(), #1", - "not active"); - - return mac_lld_poll_link_status(macp); -} - -#endif /* HAL_USE_MAC */ - -/** @} */ diff --git a/firmware/chibios/os/hal/src/mmc_spi.c b/firmware/chibios/os/hal/src/mmc_spi.c deleted file mode 100644 index 05454f71d6..0000000000 --- a/firmware/chibios/os/hal/src/mmc_spi.c +++ /dev/null @@ -1,886 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ -/* - Parts of this file have been contributed by Matthias Blaicher. - */ - -/** - * @file mmc_spi.c - * @brief MMC over SPI driver code. - * - * @addtogroup MMC_SPI - * @{ - */ - -#include - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/* Forward declarations required by mmc_vmt.*/ -static bool_t mmc_read(void *instance, uint32_t startblk, - uint8_t *buffer, uint32_t n); -static bool_t mmc_write(void *instance, uint32_t startblk, - const uint8_t *buffer, uint32_t n); - -/** - * @brief Virtual methods table. - */ -static const struct MMCDriverVMT mmc_vmt = { - (bool_t (*)(void *))mmc_lld_is_card_inserted, - (bool_t (*)(void *))mmc_lld_is_write_protected, - (bool_t (*)(void *))mmcConnect, - (bool_t (*)(void *))mmcDisconnect, - mmc_read, - mmc_write, - (bool_t (*)(void *))mmcSync, - (bool_t (*)(void *, BlockDeviceInfo *))mmcGetInfo -}; - -/** - * @brief Lookup table for CRC-7 ( based on polynomial x^7 + x^3 + 1). - */ -static const uint8_t crc7_lookup_table[256] = { - 0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f, 0x48, 0x41, 0x5a, 0x53, - 0x6c, 0x65, 0x7e, 0x77, 0x19, 0x10, 0x0b, 0x02, 0x3d, 0x34, 0x2f, 0x26, - 0x51, 0x58, 0x43, 0x4a, 0x75, 0x7c, 0x67, 0x6e, 0x32, 0x3b, 0x20, 0x29, - 0x16, 0x1f, 0x04, 0x0d, 0x7a, 0x73, 0x68, 0x61, 0x5e, 0x57, 0x4c, 0x45, - 0x2b, 0x22, 0x39, 0x30, 0x0f, 0x06, 0x1d, 0x14, 0x63, 0x6a, 0x71, 0x78, - 0x47, 0x4e, 0x55, 0x5c, 0x64, 0x6d, 0x76, 0x7f, 0x40, 0x49, 0x52, 0x5b, - 0x2c, 0x25, 0x3e, 0x37, 0x08, 0x01, 0x1a, 0x13, 0x7d, 0x74, 0x6f, 0x66, - 0x59, 0x50, 0x4b, 0x42, 0x35, 0x3c, 0x27, 0x2e, 0x11, 0x18, 0x03, 0x0a, - 0x56, 0x5f, 0x44, 0x4d, 0x72, 0x7b, 0x60, 0x69, 0x1e, 0x17, 0x0c, 0x05, - 0x3a, 0x33, 0x28, 0x21, 0x4f, 0x46, 0x5d, 0x54, 0x6b, 0x62, 0x79, 0x70, - 0x07, 0x0e, 0x15, 0x1c, 0x23, 0x2a, 0x31, 0x38, 0x41, 0x48, 0x53, 0x5a, - 0x65, 0x6c, 0x77, 0x7e, 0x09, 0x00, 0x1b, 0x12, 0x2d, 0x24, 0x3f, 0x36, - 0x58, 0x51, 0x4a, 0x43, 0x7c, 0x75, 0x6e, 0x67, 0x10, 0x19, 0x02, 0x0b, - 0x34, 0x3d, 0x26, 0x2f, 0x73, 0x7a, 0x61, 0x68, 0x57, 0x5e, 0x45, 0x4c, - 0x3b, 0x32, 0x29, 0x20, 0x1f, 0x16, 0x0d, 0x04, 0x6a, 0x63, 0x78, 0x71, - 0x4e, 0x47, 0x5c, 0x55, 0x22, 0x2b, 0x30, 0x39, 0x06, 0x0f, 0x14, 0x1d, - 0x25, 0x2c, 0x37, 0x3e, 0x01, 0x08, 0x13, 0x1a, 0x6d, 0x64, 0x7f, 0x76, - 0x49, 0x40, 0x5b, 0x52, 0x3c, 0x35, 0x2e, 0x27, 0x18, 0x11, 0x0a, 0x03, - 0x74, 0x7d, 0x66, 0x6f, 0x50, 0x59, 0x42, 0x4b, 0x17, 0x1e, 0x05, 0x0c, - 0x33, 0x3a, 0x21, 0x28, 0x5f, 0x56, 0x4d, 0x44, 0x7b, 0x72, 0x69, 0x60, - 0x0e, 0x07, 0x1c, 0x15, 0x2a, 0x23, 0x38, 0x31, 0x46, 0x4f, 0x54, 0x5d, - 0x62, 0x6b, 0x70, 0x79 -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static bool_t mmc_read(void *instance, uint32_t startblk, - uint8_t *buffer, uint32_t n) { - - if (mmcStartSequentialRead((MMCDriver *)instance, startblk)) - return CH_FAILED; - while (n > 0) { - if (mmcSequentialRead((MMCDriver *)instance, buffer)) - return CH_FAILED; - buffer += MMCSD_BLOCK_SIZE; - n--; - } - if (mmcStopSequentialRead((MMCDriver *)instance)) - return CH_FAILED; - return CH_SUCCESS; -} - -static bool_t mmc_write(void *instance, uint32_t startblk, - const uint8_t *buffer, uint32_t n) { - - if (mmcStartSequentialWrite((MMCDriver *)instance, startblk)) - return CH_FAILED; - while (n > 0) { - if (mmcSequentialWrite((MMCDriver *)instance, buffer)) - return CH_FAILED; - buffer += MMCSD_BLOCK_SIZE; - n--; - } - if (mmcStopSequentialWrite((MMCDriver *)instance)) - return CH_FAILED; - return CH_SUCCESS; -} - -/** - * @brief Calculate the MMC standard CRC-7 based on a lookup table. - * - * @param[in] crc start value for CRC - * @param[in] buffer pointer to data buffer - * @param[in] len length of data - * @return Calculated CRC - */ -static uint8_t crc7(uint8_t crc, const uint8_t *buffer, size_t len) { - - while (len--) - crc = crc7_lookup_table[(crc << 1) ^ (*buffer++)]; - return crc; -} - -/** - * @brief Waits an idle condition. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * - * @notapi - */ -static void wait(MMCDriver *mmcp) { - int i; - uint8_t buf[4]; - - for (i = 0; i < 16; i++) { - spiReceive(mmcp->config->spip, 1, buf); - if (buf[0] == 0xFF) - return; - } - /* Looks like it is a long wait.*/ - while (TRUE) { - spiReceive(mmcp->config->spip, 1, buf); - if (buf[0] == 0xFF) - break; -#if MMC_NICE_WAITING - /* Trying to be nice with the other threads.*/ - chThdSleep(1); -#endif - } -} - -/** - * @brief Sends a command header. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @param[in] cmd the command id - * @param[in] arg the command argument - * - * @notapi - */ -static void send_hdr(MMCDriver *mmcp, uint8_t cmd, uint32_t arg) { - uint8_t buf[6]; - - /* Wait for the bus to become idle if a write operation was in progress.*/ - wait(mmcp); - - buf[0] = 0x40 | cmd; - buf[1] = arg >> 24; - buf[2] = arg >> 16; - buf[3] = arg >> 8; - buf[4] = arg; - /* Calculate CRC for command header, shift to right position, add stop bit.*/ - buf[5] = ((crc7(0, buf, 5) & 0x7F) << 1) | 0x01; - - spiSend(mmcp->config->spip, 6, buf); -} - -/** - * @brief Receives a single byte response. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @return The response as an @p uint8_t value. - * @retval 0xFF timed out. - * - * @notapi - */ -static uint8_t recvr1(MMCDriver *mmcp) { - int i; - uint8_t r1[1]; - - for (i = 0; i < 9; i++) { - spiReceive(mmcp->config->spip, 1, r1); - if (r1[0] != 0xFF) - return r1[0]; - } - return 0xFF; -} - -/** - * @brief Receives a three byte response. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @param[out] buffer pointer to four bytes wide buffer - * @return First response byte as an @p uint8_t value. - * @retval 0xFF timed out. - * - * @notapi - */ -static uint8_t recvr3(MMCDriver *mmcp, uint8_t* buffer) { - uint8_t r1; - - r1 = recvr1(mmcp); - spiReceive(mmcp->config->spip, 4, buffer); - - return r1; -} - -/** - * @brief Sends a command an returns a single byte response. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @param[in] cmd the command id - * @param[in] arg the command argument - * @return The response as an @p uint8_t value. - * @retval 0xFF timed out. - * - * @notapi - */ -static uint8_t send_command_R1(MMCDriver *mmcp, uint8_t cmd, uint32_t arg) { - uint8_t r1; - - spiSelect(mmcp->config->spip); - send_hdr(mmcp, cmd, arg); - r1 = recvr1(mmcp); - spiUnselect(mmcp->config->spip); - return r1; -} - -/** - * @brief Sends a command which returns a five bytes response (R3). - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @param[in] cmd the command id - * @param[in] arg the command argument - * @param[out] response pointer to four bytes wide uint8_t buffer - * @return The first byte of the response (R1) as an @p - * uint8_t value. - * @retval 0xFF timed out. - * - * @notapi - */ -static uint8_t send_command_R3(MMCDriver *mmcp, uint8_t cmd, uint32_t arg, - uint8_t *response) { - uint8_t r1; - - spiSelect(mmcp->config->spip); - send_hdr(mmcp, cmd, arg); - r1 = recvr3(mmcp, response); - spiUnselect(mmcp->config->spip); - return r1; -} - -/** - * @brief Reads the CSD. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @param[out] csd pointer to the CSD buffer - * - * @return The operation status. - * @retval CH_SUCCESS the operation succeeded. - * @retval CH_FAILED the operation failed. - * - * @notapi - */ -static bool_t read_CxD(MMCDriver *mmcp, uint8_t cmd, uint32_t cxd[4]) { - unsigned i; - uint8_t *bp, buf[16]; - - spiSelect(mmcp->config->spip); - send_hdr(mmcp, cmd, 0); - if (recvr1(mmcp) != 0x00) { - spiUnselect(mmcp->config->spip); - return CH_FAILED; - } - - /* Wait for data availability.*/ - for (i = 0; i < MMC_WAIT_DATA; i++) { - spiReceive(mmcp->config->spip, 1, buf); - if (buf[0] == 0xFE) { - uint32_t *wp; - - spiReceive(mmcp->config->spip, 16, buf); - bp = buf; - for (wp = &cxd[3]; wp >= cxd; wp--) { - *wp = ((uint32_t)bp[0] << 24) | ((uint32_t)bp[1] << 16) | - ((uint32_t)bp[2] << 8) | (uint32_t)bp[3]; - bp += 4; - } - - /* CRC ignored then end of transaction. */ - spiIgnore(mmcp->config->spip, 2); - spiUnselect(mmcp->config->spip); - - return CH_SUCCESS; - } - } - return CH_FAILED; -} - -/** - * @brief Waits that the card reaches an idle state. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * - * @notapi - */ -static void sync(MMCDriver *mmcp) { - uint8_t buf[1]; - - spiSelect(mmcp->config->spip); - while (TRUE) { - spiReceive(mmcp->config->spip, 1, buf); - if (buf[0] == 0xFF) - break; -#if MMC_NICE_WAITING - chThdSleep(1); /* Trying to be nice with the other threads.*/ -#endif - } - spiUnselect(mmcp->config->spip); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief MMC over SPI driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void mmcInit(void) { - -} - -/** - * @brief Initializes an instance. - * - * @param[out] mmcp pointer to the @p MMCDriver object - * - * @init - */ -void mmcObjectInit(MMCDriver *mmcp) { - - mmcp->vmt = &mmc_vmt; - mmcp->state = BLK_STOP; - mmcp->config = NULL; - mmcp->block_addresses = FALSE; -} - -/** - * @brief Configures and activates the MMC peripheral. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @param[in] config pointer to the @p MMCConfig object. - * - * @api - */ -void mmcStart(MMCDriver *mmcp, const MMCConfig *config) { - - chDbgCheck((mmcp != NULL) && (config != NULL), "mmcStart"); - chDbgAssert((mmcp->state == BLK_STOP) || (mmcp->state == BLK_ACTIVE), - "mmcStart(), #1", "invalid state"); - - mmcp->config = config; - mmcp->state = BLK_ACTIVE; -} - -/** - * @brief Disables the MMC peripheral. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * - * @api - */ -void mmcStop(MMCDriver *mmcp) { - - chDbgCheck(mmcp != NULL, "mmcStop"); - chDbgAssert((mmcp->state == BLK_STOP) || (mmcp->state == BLK_ACTIVE), - "mmcStop(), #1", "invalid state"); - - spiStop(mmcp->config->spip); - mmcp->state = BLK_STOP; -} - -/** - * @brief Performs the initialization procedure on the inserted card. - * @details This function should be invoked when a card is inserted and - * brings the driver in the @p MMC_READY state where it is possible - * to perform read and write operations. - * @note It is possible to invoke this function from the insertion event - * handler. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * - * @return The operation status. - * @retval CH_SUCCESS the operation succeeded and the driver is now - * in the @p MMC_READY state. - * @retval CH_FAILED the operation failed. - * - * @api - */ -bool_t mmcConnect(MMCDriver *mmcp) { - unsigned i; - uint8_t r3[4]; - - chDbgCheck(mmcp != NULL, "mmcConnect"); - - chDbgAssert((mmcp->state == BLK_ACTIVE) || (mmcp->state == BLK_READY), - "mmcConnect(), #1", "invalid state"); - - /* Connection procedure in progress.*/ - mmcp->state = BLK_CONNECTING; - mmcp->block_addresses = FALSE; - - /* Slow clock mode and 128 clock pulses.*/ - spiStart(mmcp->config->spip, mmcp->config->lscfg); - spiIgnore(mmcp->config->spip, 16); - - /* SPI mode selection.*/ - i = 0; - while (TRUE) { - if (send_command_R1(mmcp, MMCSD_CMD_GO_IDLE_STATE, 0) == 0x01) - break; - if (++i >= MMC_CMD0_RETRY) - goto failed; - chThdSleepMilliseconds(10); - } - - /* Try to detect if this is a high capacity card and switch to block - addresses if possible. - This method is based on "How to support SDC Ver2 and high capacity cards" - by ElmChan.*/ - if (send_command_R3(mmcp, MMCSD_CMD_SEND_IF_COND, - MMCSD_CMD8_PATTERN, r3) != 0x05) { - - /* Switch to SDHC mode.*/ - i = 0; - while (TRUE) { - if ((send_command_R1(mmcp, MMCSD_CMD_APP_CMD, 0) == 0x01) && - (send_command_R3(mmcp, MMCSD_CMD_APP_OP_COND, - 0x400001aa, r3) == 0x00)) - break; - - if (++i >= MMC_ACMD41_RETRY) - goto failed; - chThdSleepMilliseconds(10); - } - - /* Execute dedicated read on OCR register */ - send_command_R3(mmcp, MMCSD_CMD_READ_OCR, 0, r3); - - /* Check if CCS is set in response. Card operates in block mode if set.*/ - if (r3[0] & 0x40) - mmcp->block_addresses = TRUE; - } - - /* Initialization.*/ - i = 0; - while (TRUE) { - uint8_t b = send_command_R1(mmcp, MMCSD_CMD_INIT, 0); - if (b == 0x00) - break; - if (b != 0x01) - goto failed; - if (++i >= MMC_CMD1_RETRY) - goto failed; - chThdSleepMilliseconds(10); - } - - /* Initialization complete, full speed.*/ - spiStart(mmcp->config->spip, mmcp->config->hscfg); - - /* Setting block size.*/ - if (send_command_R1(mmcp, MMCSD_CMD_SET_BLOCKLEN, - MMCSD_BLOCK_SIZE) != 0x00) - goto failed; - - /* Determine capacity.*/ - if (read_CxD(mmcp, MMCSD_CMD_SEND_CSD, mmcp->csd)) - goto failed; - mmcp->capacity = mmcsdGetCapacity(mmcp->csd); - if (mmcp->capacity == 0) - goto failed; - - if (read_CxD(mmcp, MMCSD_CMD_SEND_CID, mmcp->cid)) - goto failed; - - mmcp->state = BLK_READY; - return CH_SUCCESS; - - /* Connection failed, state reset to BLK_ACTIVE.*/ -failed: - spiStop(mmcp->config->spip); - mmcp->state = BLK_ACTIVE; - return CH_FAILED; -} - -/** - * @brief Brings the driver in a state safe for card removal. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @return The operation status. - * - * @retval CH_SUCCESS the operation succeeded and the driver is now - * in the @p MMC_INSERTED state. - * @retval CH_FAILED the operation failed. - * - * @api - */ -bool_t mmcDisconnect(MMCDriver *mmcp) { - - chDbgCheck(mmcp != NULL, "mmcDisconnect"); - - chSysLock(); - chDbgAssert((mmcp->state == BLK_ACTIVE) || (mmcp->state == BLK_READY), - "mmcDisconnect(), #1", "invalid state"); - if (mmcp->state == BLK_ACTIVE) { - chSysUnlock(); - return CH_SUCCESS; - } - mmcp->state = BLK_DISCONNECTING; - chSysUnlock(); - - /* Wait for the pending write operations to complete.*/ - spiStart(mmcp->config->spip, mmcp->config->hscfg); - sync(mmcp); - - spiStop(mmcp->config->spip); - mmcp->state = BLK_ACTIVE; - return CH_SUCCESS; -} - -/** - * @brief Starts a sequential read. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @param[in] startblk first block to read - * - * @return The operation status. - * @retval CH_SUCCESS the operation succeeded. - * @retval CH_FAILED the operation failed. - * - * @api - */ -bool_t mmcStartSequentialRead(MMCDriver *mmcp, uint32_t startblk) { - - chDbgCheck(mmcp != NULL, "mmcStartSequentialRead"); - chDbgAssert(mmcp->state == BLK_READY, - "mmcStartSequentialRead(), #1", "invalid state"); - - /* Read operation in progress.*/ - mmcp->state = BLK_READING; - - /* (Re)starting the SPI in case it has been reprogrammed externally, it can - happen if the SPI bus is shared among multiple peripherals.*/ - spiStart(mmcp->config->spip, mmcp->config->hscfg); - spiSelect(mmcp->config->spip); - - if (mmcp->block_addresses) - send_hdr(mmcp, MMCSD_CMD_READ_MULTIPLE_BLOCK, startblk); - else - send_hdr(mmcp, MMCSD_CMD_READ_MULTIPLE_BLOCK, startblk * MMCSD_BLOCK_SIZE); - - if (recvr1(mmcp) != 0x00) { - spiStop(mmcp->config->spip); - mmcp->state = BLK_READY; - return CH_FAILED; - } - return CH_SUCCESS; -} - -/** - * @brief Reads a block within a sequential read operation. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @param[out] buffer pointer to the read buffer - * - * @return The operation status. - * @retval CH_SUCCESS the operation succeeded. - * @retval CH_FAILED the operation failed. - * - * @api - */ -bool_t mmcSequentialRead(MMCDriver *mmcp, uint8_t *buffer) { - int i; - - chDbgCheck((mmcp != NULL) && (buffer != NULL), "mmcSequentialRead"); - - if (mmcp->state != BLK_READING) - return CH_FAILED; - - for (i = 0; i < MMC_WAIT_DATA; i++) { - spiReceive(mmcp->config->spip, 1, buffer); - if (buffer[0] == 0xFE) { - spiReceive(mmcp->config->spip, MMCSD_BLOCK_SIZE, buffer); - /* CRC ignored. */ - spiIgnore(mmcp->config->spip, 2); - return CH_SUCCESS; - } - } - /* Timeout.*/ - spiUnselect(mmcp->config->spip); - spiStop(mmcp->config->spip); - mmcp->state = BLK_READY; - return CH_FAILED; -} - -/** - * @brief Stops a sequential read gracefully. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * - * @return The operation status. - * @retval CH_SUCCESS the operation succeeded. - * @retval CH_FAILED the operation failed. - * - * @api - */ -bool_t mmcStopSequentialRead(MMCDriver *mmcp) { - static const uint8_t stopcmd[] = {0x40 | MMCSD_CMD_STOP_TRANSMISSION, - 0, 0, 0, 0, 1, 0xFF}; - - chDbgCheck(mmcp != NULL, "mmcStopSequentialRead"); - - if (mmcp->state != BLK_READING) - return CH_FAILED; - - spiSend(mmcp->config->spip, sizeof(stopcmd), stopcmd); -/* result = recvr1(mmcp) != 0x00;*/ - /* Note, ignored r1 response, it can be not zero, unknown issue.*/ - (void) recvr1(mmcp); - - /* Read operation finished.*/ - spiUnselect(mmcp->config->spip); - mmcp->state = BLK_READY; - return CH_SUCCESS; -} - -/** - * @brief Starts a sequential write. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @param[in] startblk first block to write - * - * @return The operation status. - * @retval CH_SUCCESS the operation succeeded. - * @retval CH_FAILED the operation failed. - * - * @api - */ -bool_t mmcStartSequentialWrite(MMCDriver *mmcp, uint32_t startblk) { - - chDbgCheck(mmcp != NULL, "mmcStartSequentialWrite"); - chDbgAssert(mmcp->state == BLK_READY, - "mmcStartSequentialWrite(), #1", "invalid state"); - - /* Write operation in progress.*/ - mmcp->state = BLK_WRITING; - - spiStart(mmcp->config->spip, mmcp->config->hscfg); - spiSelect(mmcp->config->spip); - if (mmcp->block_addresses) - send_hdr(mmcp, MMCSD_CMD_WRITE_MULTIPLE_BLOCK, startblk); - else - send_hdr(mmcp, MMCSD_CMD_WRITE_MULTIPLE_BLOCK, - startblk * MMCSD_BLOCK_SIZE); - - if (recvr1(mmcp) != 0x00) { - spiStop(mmcp->config->spip); - mmcp->state = BLK_READY; - return CH_FAILED; - } - return CH_SUCCESS; -} - -/** - * @brief Writes a block within a sequential write operation. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @param[out] buffer pointer to the write buffer - * - * @return The operation status. - * @retval CH_SUCCESS the operation succeeded. - * @retval CH_FAILED the operation failed. - * - * @api - */ -bool_t mmcSequentialWrite(MMCDriver *mmcp, const uint8_t *buffer) { - static const uint8_t start[] = {0xFF, 0xFC}; - uint8_t b[1]; - - chDbgCheck((mmcp != NULL) && (buffer != NULL), "mmcSequentialWrite"); - - if (mmcp->state != BLK_WRITING) - return CH_FAILED; - - spiSend(mmcp->config->spip, sizeof(start), start); /* Data prologue. */ - spiSend(mmcp->config->spip, MMCSD_BLOCK_SIZE, buffer);/* Data. */ - spiIgnore(mmcp->config->spip, 2); /* CRC ignored. */ - spiReceive(mmcp->config->spip, 1, b); - if ((b[0] & 0x1F) == 0x05) { - wait(mmcp); - return CH_SUCCESS; - } - - /* Error.*/ - spiUnselect(mmcp->config->spip); - spiStop(mmcp->config->spip); - mmcp->state = BLK_READY; - return CH_FAILED; -} - -/** - * @brief Stops a sequential write gracefully. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * - * @return The operation status. - * @retval CH_SUCCESS the operation succeeded. - * @retval CH_FAILED the operation failed. - * - * @api - */ -bool_t mmcStopSequentialWrite(MMCDriver *mmcp) { - static const uint8_t stop[] = {0xFD, 0xFF}; - - chDbgCheck(mmcp != NULL, "mmcStopSequentialWrite"); - - if (mmcp->state != BLK_WRITING) - return CH_FAILED; - - spiSend(mmcp->config->spip, sizeof(stop), stop); - spiUnselect(mmcp->config->spip); - - /* Write operation finished.*/ - mmcp->state = BLK_READY; - return CH_SUCCESS; -} - -/** - * @brief Waits for card idle condition. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * - * @return The operation status. - * @retval CH_SUCCESS the operation succeeded. - * @retval CH_FAILED the operation failed. - * - * @api - */ -bool_t mmcSync(MMCDriver *mmcp) { - - chDbgCheck(mmcp != NULL, "mmcSync"); - - if (mmcp->state != BLK_READY) - return CH_FAILED; - - /* Synchronization operation in progress.*/ - mmcp->state = BLK_SYNCING; - - spiStart(mmcp->config->spip, mmcp->config->hscfg); - sync(mmcp); - - /* Synchronization operation finished.*/ - mmcp->state = BLK_READY; - return CH_SUCCESS; -} - -/** - * @brief Returns the media info. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @param[out] bdip pointer to a @p BlockDeviceInfo structure - * - * @return The operation status. - * @retval CH_SUCCESS the operation succeeded. - * @retval CH_FAILED the operation failed. - * - * @api - */ -bool_t mmcGetInfo(MMCDriver *mmcp, BlockDeviceInfo *bdip) { - - chDbgCheck((mmcp != NULL) && (bdip != NULL), "mmcGetInfo"); - - if (mmcp->state != BLK_READY) - return CH_FAILED; - - bdip->blk_num = mmcp->capacity; - bdip->blk_size = MMCSD_BLOCK_SIZE; - - return CH_SUCCESS; -} - -/** - * @brief Erases blocks. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @param[in] startblk starting block number - * @param[in] endblk ending block number - * - * @return The operation status. - * @retval CH_SUCCESS the operation succeeded. - * @retval CH_FAILED the operation failed. - * - * @api - */ -bool_t mmcErase(MMCDriver *mmcp, uint32_t startblk, uint32_t endblk) { - - chDbgCheck((mmcp != NULL), "mmcErase"); - - /* Erase operation in progress.*/ - mmcp->state = BLK_WRITING; - - /* Handling command differences between HC and normal cards.*/ - if (!mmcp->block_addresses) { - startblk *= MMCSD_BLOCK_SIZE; - endblk *= MMCSD_BLOCK_SIZE; - } - - if (send_command_R1(mmcp, MMCSD_CMD_ERASE_RW_BLK_START, startblk)) - goto failed; - - if (send_command_R1(mmcp, MMCSD_CMD_ERASE_RW_BLK_END, endblk)) - goto failed; - - if (send_command_R1(mmcp, MMCSD_CMD_ERASE, 0)) - goto failed; - - mmcp->state = BLK_READY; - return CH_SUCCESS; - - /* Command failed, state reset to BLK_ACTIVE.*/ -failed: - spiStop(mmcp->config->spip); - mmcp->state = BLK_READY; - return CH_FAILED; -} - -#endif /* HAL_USE_MMC_SPI */ - -/** @} */ diff --git a/firmware/chibios/os/hal/src/mmcsd.c b/firmware/chibios/os/hal/src/mmcsd.c deleted file mode 100644 index 6b21a6214d..0000000000 --- a/firmware/chibios/os/hal/src/mmcsd.c +++ /dev/null @@ -1,121 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file mmcsd.c - * @brief MMC/SD cards common code. - * - * @addtogroup MMCSD - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_MMC_SPI || HAL_USE_SDC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Gets a bit field from a words array. - * @note The bit zero is the LSb of the first word. - * - * @param[in] data pointer to the words array - * @param[in] end bit offset of the last bit of the field, inclusive - * @param[in] start bit offset of the first bit of the field, inclusive - * - * @return The bits field value, left aligned. - * - * @notapi - */ -static uint32_t mmcsd_get_slice(uint32_t *data, uint32_t end, uint32_t start) { - unsigned startidx, endidx, startoff; - uint32_t endmask; - - chDbgCheck((end >= start) && ((end - start) < 32), "mmcsd_get_slice"); - - startidx = start / 32; - startoff = start % 32; - endidx = end / 32; - endmask = (1 << ((end % 32) + 1)) - 1; - - /* One or two pieces?*/ - if (startidx < endidx) - return (data[startidx] >> startoff) | /* Two pieces case. */ - ((data[endidx] & endmask) << (32 - startoff)); - return (data[startidx] & endmask) >> startoff; /* One piece case. */ -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Extract card capacity from a CSD. - * @details The capacity is returned as number of available blocks. - * - * @param[in] csd the CSD record - * - * @return The card capacity. - * @retval 0 CSD format error - */ -uint32_t mmcsdGetCapacity(uint32_t csd[4]) { - - switch (csd[3] >> 30) { - uint32_t a, b, c; - case 0: - /* CSD version 1.0 */ - a = mmcsd_get_slice(csd, MMCSD_CSD_10_C_SIZE_SLICE); - b = mmcsd_get_slice(csd, MMCSD_CSD_10_C_SIZE_MULT_SLICE); - c = mmcsd_get_slice(csd, MMCSD_CSD_10_READ_BL_LEN_SLICE); - return (a + 1) << (b + 2) << (c - 9); /* 2^9 == MMCSD_BLOCK_SIZE. */ - case 1: - /* CSD version 2.0.*/ - return 1024 * (mmcsd_get_slice(csd, MMCSD_CSD_20_C_SIZE_SLICE) + 1); - default: - /* Reserved value detected.*/ - return 0; - } -} - -#endif /* HAL_USE_MMC_SPI || HAL_USE_SDC */ - -/** @} */ diff --git a/firmware/chibios/os/hal/src/pal.c b/firmware/chibios/os/hal/src/pal.c deleted file mode 100644 index 38ec087aa7..0000000000 --- a/firmware/chibios/os/hal/src/pal.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file pal.c - * @brief I/O Ports Abstraction Layer code. - * - * @addtogroup PAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Read from an I/O bus. - * @note The operation is not guaranteed to be atomic on all the - * architectures, for atomicity and/or portability reasons you may - * need to enclose port I/O operations between @p chSysLock() and - * @p chSysUnlock(). - * @note The function internally uses the @p palReadGroup() macro. The use - * of this function is preferred when you value code size, readability - * and error checking over speed. - * @note The function can be called from any context. - * - * @param[in] bus the I/O bus, pointer to a @p IOBus structure - * @return The bus logical states. - * - * @special - */ -ioportmask_t palReadBus(IOBus *bus) { - - chDbgCheck((bus != NULL) && (bus->offset < PAL_IOPORTS_WIDTH), - "palReadBus"); - - return palReadGroup(bus->portid, bus->mask, bus->offset); -} - -/** - * @brief Write to an I/O bus. - * @note The operation is not guaranteed to be atomic on all the - * architectures, for atomicity and/or portability reasons you may - * need to enclose port I/O operations between @p chSysLock() and - * @p chSysUnlock(). - * @note The default implementation is non atomic and not necessarily - * optimal. Low level drivers may optimize the function by using - * specific hardware or coding. - * @note The function can be called from any context. - * - * @param[in] bus the I/O bus, pointer to a @p IOBus structure - * @param[in] bits the bits to be written on the I/O bus. Values exceeding - * the bus width are masked so most significant bits are - * lost. - * - * @special - */ -void palWriteBus(IOBus *bus, ioportmask_t bits) { - - chDbgCheck((bus != NULL) && (bus->offset < PAL_IOPORTS_WIDTH), - "palWriteBus"); - - palWriteGroup(bus->portid, bus->mask, bus->offset, bits); -} - -/** - * @brief Programs a bus with the specified mode. - * @note The operation is not guaranteed to be atomic on all the - * architectures, for atomicity and/or portability reasons you may - * need to enclose port I/O operations between @p chSysLock() and - * @p chSysUnlock(). - * @note The default implementation is non atomic and not necessarily - * optimal. Low level drivers may optimize the function by using - * specific hardware or coding. - * @note The function can be called from any context. - * - * @param[in] bus the I/O bus, pointer to a @p IOBus structure - * @param[in] mode the mode - * - * @special - */ -void palSetBusMode(IOBus *bus, iomode_t mode) { - - chDbgCheck((bus != NULL) && (bus->offset < PAL_IOPORTS_WIDTH), - "palSetBusMode"); - - palSetGroupMode(bus->portid, bus->mask, bus->offset, mode); -} - -#endif /* HAL_USE_PAL */ - -/** @} */ diff --git a/firmware/chibios/os/hal/src/pwm.c b/firmware/chibios/os/hal/src/pwm.c deleted file mode 100644 index dbf403d9f3..0000000000 --- a/firmware/chibios/os/hal/src/pwm.c +++ /dev/null @@ -1,214 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file pwm.c - * @brief PWM Driver code. - * - * @addtogroup PWM - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_PWM || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief PWM Driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void pwmInit(void) { - - pwm_lld_init(); -} - -/** - * @brief Initializes the standard part of a @p PWMDriver structure. - * - * @param[out] pwmp pointer to a @p PWMDriver object - * - * @init - */ -void pwmObjectInit(PWMDriver *pwmp) { - - pwmp->state = PWM_STOP; - pwmp->config = NULL; -#if defined(PWM_DRIVER_EXT_INIT_HOOK) - PWM_DRIVER_EXT_INIT_HOOK(pwmp); -#endif -} - -/** - * @brief Configures and activates the PWM peripheral. - * @note Starting a driver that is already in the @p PWM_READY state - * disables all the active channels. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] config pointer to a @p PWMConfig object - * - * @api - */ -void pwmStart(PWMDriver *pwmp, const PWMConfig *config) { - - chDbgCheck((pwmp != NULL) && (config != NULL), "pwmStart"); - - chSysLock(); - chDbgAssert((pwmp->state == PWM_STOP) || (pwmp->state == PWM_READY), - "pwmStart(), #1", "invalid state"); - pwmp->config = config; - pwmp->period = config->period; - pwm_lld_start(pwmp); - pwmp->state = PWM_READY; - chSysUnlock(); -} - -/** - * @brief Deactivates the PWM peripheral. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * - * @api - */ -void pwmStop(PWMDriver *pwmp) { - - chDbgCheck(pwmp != NULL, "pwmStop"); - - chSysLock(); - chDbgAssert((pwmp->state == PWM_STOP) || (pwmp->state == PWM_READY), - "pwmStop(), #1", "invalid state"); - pwm_lld_stop(pwmp); - pwmp->state = PWM_STOP; - chSysUnlock(); -} - -/** - * @brief Changes the period the PWM peripheral. - * @details This function changes the period of a PWM unit that has already - * been activated using @p pwmStart(). - * @pre The PWM unit must have been activated using @p pwmStart(). - * @post The PWM unit period is changed to the new value. - * @note If a period is specified that is shorter than the pulse width - * programmed in one of the channels then the behavior is not - * guaranteed. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] period new cycle time in ticks - * - * @api - */ -void pwmChangePeriod(PWMDriver *pwmp, pwmcnt_t period) { - - chDbgCheck(pwmp != NULL, "pwmChangePeriod"); - - chSysLock(); - chDbgAssert(pwmp->state == PWM_READY, - "pwmChangePeriod(), #1", "invalid state"); - pwmChangePeriodI(pwmp, period); - chSysUnlock(); -} - -/** - * @brief Enables a PWM channel. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @post The channel is active using the specified configuration. - * @note Depending on the hardware implementation this function has - * effect starting on the next cycle (recommended implementation) - * or immediately (fallback implementation). - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) - * @param[in] width PWM pulse width as clock pulses number - * - * @api - */ -void pwmEnableChannel(PWMDriver *pwmp, - pwmchannel_t channel, - pwmcnt_t width) { - - chDbgCheck((pwmp != NULL) && (channel < PWM_CHANNELS), - "pwmEnableChannel"); - - chSysLock(); - chDbgAssert(pwmp->state == PWM_READY, - "pwmEnableChannel(), #1", "not ready"); - pwm_lld_enable_channel(pwmp, channel, width); - chSysUnlock(); -} - -/** - * @brief Disables a PWM channel. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @post The channel is disabled and its output line returned to the - * idle state. - * @note Depending on the hardware implementation this function has - * effect starting on the next cycle (recommended implementation) - * or immediately (fallback implementation). - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) - * - * @api - */ -void pwmDisableChannel(PWMDriver *pwmp, pwmchannel_t channel) { - - chDbgCheck((pwmp != NULL) && (channel < PWM_CHANNELS), - "pwmEnableChannel"); - - chSysLock(); - chDbgAssert(pwmp->state == PWM_READY, - "pwmDisableChannel(), #1", "not ready"); - pwm_lld_disable_channel(pwmp, channel); - chSysUnlock(); -} - -#endif /* HAL_USE_PWM */ - -/** @} */ diff --git a/firmware/chibios/os/hal/src/rtc.c b/firmware/chibios/os/hal/src/rtc.c deleted file mode 100644 index 35bccbe306..0000000000 --- a/firmware/chibios/os/hal/src/rtc.c +++ /dev/null @@ -1,197 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ -/* - Concepts and parts of this file have been contributed by Uladzimir Pylinsky - aka barthess. - */ - -/** - * @file rtc.c - * @brief RTC Driver code. - * - * @addtogroup RTC - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_RTC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief RTC Driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void rtcInit(void) { - - rtc_lld_init(); -} - -/** - * @brief Set current time. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[in] timespec pointer to a @p RTCTime structure - * - * @api - */ -void rtcSetTime(RTCDriver *rtcp, const RTCTime *timespec) { - - chDbgCheck((rtcp != NULL) && (timespec != NULL), "rtcSetTime"); - - chSysLock(); - rtcSetTimeI(rtcp, timespec); - chSysUnlock(); -} - -extern bool rtcWorks; - -/** - * @brief Get current time. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[out] timespec pointer to a @p RTCTime structure - * - * @api - */ -void rtcGetTime(RTCDriver *rtcp, RTCTime *timespec) { - - chDbgCheck((rtcp != NULL) && (timespec != NULL), "rtcGetTime"); - - if (!rtcWorks) - return; - chSysLock(); - rtcGetTimeI(rtcp, timespec); - chSysUnlock(); -} - -#if (RTC_ALARMS > 0) || defined(__DOXYGEN__) -/** - * @brief Set alarm time. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[in] alarm alarm identifier - * @param[in] alarmspec pointer to a @p RTCAlarm structure or @p NULL - * - * @api - */ -void rtcSetAlarm(RTCDriver *rtcp, - rtcalarm_t alarm, - const RTCAlarm *alarmspec) { - - chDbgCheck((rtcp != NULL) && (alarm < RTC_ALARMS), "rtcSetAlarm"); - - chSysLock(); - rtcSetAlarmI(rtcp, alarm, alarmspec); - chSysUnlock(); -} - -/** - * @brief Get current alarm. - * @note If an alarm has not been set then the returned alarm specification - * is not meaningful. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[in] alarm alarm identifier - * @param[out] alarmspec pointer to a @p RTCAlarm structure - * - * @api - */ -void rtcGetAlarm(RTCDriver *rtcp, - rtcalarm_t alarm, - RTCAlarm *alarmspec) { - - chDbgCheck((rtcp != NULL) && (alarm < RTC_ALARMS) && (alarmspec != NULL), - "rtcGetAlarm"); - - chSysLock(); - rtcGetAlarmI(rtcp, alarm, alarmspec); - chSysUnlock(); -} -#endif /* RTC_ALARMS > 0 */ - -#if RTC_SUPPORTS_CALLBACKS || defined(__DOXYGEN__) -/** - * @brief Enables or disables RTC callbacks. - * @details This function enables or disables the callback, use a @p NULL - * pointer in order to disable it. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[in] callback callback function pointer or @p NULL - * - * @api - */ -void rtcSetCallback(RTCDriver *rtcp, rtccb_t callback) { - - chDbgCheck((rtcp != NULL), "rtcSetCallback"); - - chSysLock(); - rtcSetCallbackI(rtcp, callback); - chSysUnlock(); -} -#endif /* RTC_SUPPORTS_CALLBACKS */ - -/** - * @brief Get current time in format suitable for usage in FatFS. - * - * @param[in] rtcp pointer to RTC driver structure - * @return FAT time value. - * - * @api - */ -uint32_t rtcGetTimeFat(RTCDriver *rtcp) { - - chDbgCheck((rtcp != NULL), "rtcSetTime"); - return rtc_lld_get_time_fat(rtcp); -} - -#endif /* HAL_USE_RTC */ - -/** @} */ diff --git a/firmware/chibios/os/hal/src/sdc.c b/firmware/chibios/os/hal/src/sdc.c deleted file mode 100644 index 55baa6e7a4..0000000000 --- a/firmware/chibios/os/hal/src/sdc.c +++ /dev/null @@ -1,587 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file sdc.c - * @brief SDC Driver code. - * - * @addtogroup SDC - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_SDC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief Virtual methods table. - */ -static const struct SDCDriverVMT sdc_vmt = { - (bool_t (*)(void *))sdc_lld_is_card_inserted, - (bool_t (*)(void *))sdc_lld_is_write_protected, - (bool_t (*)(void *))sdcConnect, - (bool_t (*)(void *))sdcDisconnect, - (bool_t (*)(void *, uint32_t, uint8_t *, uint32_t))sdcRead, - (bool_t (*)(void *, uint32_t, const uint8_t *, uint32_t))sdcWrite, - (bool_t (*)(void *))sdcSync, - (bool_t (*)(void *, BlockDeviceInfo *))sdcGetInfo -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Wait for the card to complete pending operations. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @return The operation status. - * @retval CH_SUCCESS operation succeeded. - * @retval CH_FAILED operation failed. - * - * @notapi - */ -bool_t _sdc_wait_for_transfer_state(SDCDriver *sdcp) { - uint32_t resp[1]; - - while (TRUE) { - if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_SEND_STATUS, - sdcp->rca, resp) || - MMCSD_R1_ERROR(resp[0])) - return CH_FAILED; - switch (MMCSD_R1_STS(resp[0])) { - case MMCSD_STS_TRAN: - return CH_SUCCESS; - case MMCSD_STS_DATA: - case MMCSD_STS_RCV: - case MMCSD_STS_PRG: -#if SDC_NICE_WAITING - chThdSleepMilliseconds(1); -#endif - continue; - default: - /* The card should have been initialized so any other state is not - valid and is reported as an error.*/ - return CH_FAILED; - } - } - /* If something going too wrong.*/ - return CH_FAILED; -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief SDC Driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void sdcInit(void) { - - sdc_lld_init(); -} - -/** - * @brief Initializes the standard part of a @p SDCDriver structure. - * - * @param[out] sdcp pointer to the @p SDCDriver object - * - * @init - */ -void sdcObjectInit(SDCDriver *sdcp) { - - sdcp->vmt = &sdc_vmt; - sdcp->state = BLK_STOP; - sdcp->errors = SDC_NO_ERROR; - sdcp->config = NULL; - sdcp->capacity = 0; -} - -/** - * @brief Configures and activates the SDC peripheral. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] config pointer to the @p SDCConfig object, can be @p NULL if - * the driver supports a default configuration or - * requires no configuration - * - * @api - */ -void sdcStart(SDCDriver *sdcp, const SDCConfig *config) { - - chDbgCheck(sdcp != NULL, "sdcStart"); - - chSysLock(); - chDbgAssert((sdcp->state == BLK_STOP) || (sdcp->state == BLK_ACTIVE), - "sdcStart(), #1", "invalid state"); - sdcp->config = config; - sdc_lld_start(sdcp); - sdcp->state = BLK_ACTIVE; - chSysUnlock(); -} - -/** - * @brief Deactivates the SDC peripheral. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @api - */ -void sdcStop(SDCDriver *sdcp) { - - chDbgCheck(sdcp != NULL, "sdcStop"); - - chSysLock(); - chDbgAssert((sdcp->state == BLK_STOP) || (sdcp->state == BLK_ACTIVE), - "sdcStop(), #1", "invalid state"); - sdc_lld_stop(sdcp); - sdcp->state = BLK_STOP; - chSysUnlock(); -} - -/** - * @brief Performs the initialization procedure on the inserted card. - * @details This function should be invoked when a card is inserted and - * brings the driver in the @p BLK_READY state where it is possible - * to perform read and write operations. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @return The operation status. - * @retval CH_SUCCESS operation succeeded. - * @retval CH_FAILED operation failed. - * - * @api - */ -bool_t sdcConnect(SDCDriver *sdcp) { - uint32_t resp[1]; - - chDbgCheck(sdcp != NULL, "sdcConnect"); - chDbgAssert((sdcp->state == BLK_ACTIVE) || (sdcp->state == BLK_READY), - "mmcConnect(), #1", "invalid state"); - - /* Connection procedure in progress.*/ - sdcp->state = BLK_CONNECTING; - - /* Card clock initialization.*/ - sdc_lld_start_clk(sdcp); - - /* Enforces the initial card state.*/ - sdc_lld_send_cmd_none(sdcp, MMCSD_CMD_GO_IDLE_STATE, 0); - - /* V2.0 cards detection.*/ - if (!sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_SEND_IF_COND, - MMCSD_CMD8_PATTERN, resp)) { - sdcp->cardmode = SDC_MODE_CARDTYPE_SDV20; - /* Voltage verification.*/ - if (((resp[0] >> 8) & 0xF) != 1) - goto failed; - if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_APP_CMD, 0, resp) || - MMCSD_R1_ERROR(resp[0])) - goto failed; - } - else { -#if SDC_MMC_SUPPORT - /* MMC or SD V1.1 detection.*/ - if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_APP_CMD, 0, resp) || - MMCSD_R1_ERROR(resp[0])) - sdcp->cardmode = SDC_MODE_CARDTYPE_MMC; - else -#endif /* SDC_MMC_SUPPORT */ - { - sdcp->cardmode = SDC_MODE_CARDTYPE_SDV11; - - /* Reset error flag illegal command.*/ - sdc_lld_send_cmd_none(sdcp, MMCSD_CMD_GO_IDLE_STATE, 0); - } - } - -#if SDC_MMC_SUPPORT - if ((sdcp->cardmode & SDC_MODE_CARDTYPE_MASK) == SDC_MODE_CARDTYPE_MMC) { - /* TODO: MMC initialization.*/ - goto failed; - } - else -#endif /* SDC_MMC_SUPPORT */ - { - unsigned i; - uint32_t ocr; - - /* SD initialization.*/ - if ((sdcp->cardmode & SDC_MODE_CARDTYPE_MASK) == SDC_MODE_CARDTYPE_SDV20) - ocr = 0xC0100000; - else - ocr = 0x80100000; - - /* SD-type initialization. */ - i = 0; - while (TRUE) { - if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_APP_CMD, 0, resp) || - MMCSD_R1_ERROR(resp[0])) - goto failed; - if (sdc_lld_send_cmd_short(sdcp, MMCSD_CMD_APP_OP_COND, ocr, resp)) - goto failed; - if ((resp[0] & 0x80000000) != 0) { - if (resp[0] & 0x40000000) - sdcp->cardmode |= SDC_MODE_HIGH_CAPACITY; - break; - } - if (++i >= SDC_INIT_RETRY) - goto failed; - chThdSleepMilliseconds(10); - } - } - - /* Reads CID.*/ - if (sdc_lld_send_cmd_long_crc(sdcp, MMCSD_CMD_ALL_SEND_CID, 0, sdcp->cid)) - goto failed; - - /* Asks for the RCA.*/ - if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_SEND_RELATIVE_ADDR, - 0, &sdcp->rca)) - goto failed; - - /* Reads CSD.*/ - if (sdc_lld_send_cmd_long_crc(sdcp, MMCSD_CMD_SEND_CSD, - sdcp->rca, sdcp->csd)) - goto failed; - - /* Switches to high speed.*/ - sdc_lld_set_data_clk(sdcp); - - /* Selects the card for operations.*/ - if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_SEL_DESEL_CARD, - sdcp->rca, resp)) - goto failed; - - /* Block length fixed at 512 bytes.*/ - if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_SET_BLOCKLEN, - MMCSD_BLOCK_SIZE, resp) || - MMCSD_R1_ERROR(resp[0])) - goto failed; - - /* Switches to wide bus mode.*/ - switch (sdcp->cardmode & SDC_MODE_CARDTYPE_MASK) { - case SDC_MODE_CARDTYPE_SDV11: - case SDC_MODE_CARDTYPE_SDV20: - sdc_lld_set_bus_mode(sdcp, SDC_MODE_4BIT); - if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_APP_CMD, sdcp->rca, resp) || - MMCSD_R1_ERROR(resp[0])) - goto failed; - if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_SET_BUS_WIDTH, 2, resp) || - MMCSD_R1_ERROR(resp[0])) - goto failed; - break; - } - - /* Determine capacity.*/ - sdcp->capacity = mmcsdGetCapacity(sdcp->csd); - if (sdcp->capacity == 0) - goto failed; - - /* Initialization complete.*/ - sdcp->state = BLK_READY; - return CH_SUCCESS; - - /* Connection failed, state reset to BLK_ACTIVE.*/ -failed: - sdc_lld_stop_clk(sdcp); - sdcp->state = BLK_ACTIVE; - return CH_FAILED; -} - -/** - * @brief Brings the driver in a state safe for card removal. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @return The operation status. - * @retval CH_SUCCESS operation succeeded. - * @retval CH_FAILED operation failed. - * - * @api - */ -bool_t sdcDisconnect(SDCDriver *sdcp) { - - chDbgCheck(sdcp != NULL, "sdcDisconnect"); - - chSysLock(); - chDbgAssert((sdcp->state == BLK_ACTIVE) || (sdcp->state == BLK_READY), - "sdcDisconnect(), #1", "invalid state"); - if (sdcp->state == BLK_ACTIVE) { - chSysUnlock(); - return CH_SUCCESS; - } - sdcp->state = BLK_DISCONNECTING; - chSysUnlock(); - - /* Waits for eventual pending operations completion.*/ - if (_sdc_wait_for_transfer_state(sdcp)) { - sdc_lld_stop_clk(sdcp); - sdcp->state = BLK_ACTIVE; - return CH_FAILED; - } - - /* Card clock stopped.*/ - sdc_lld_stop_clk(sdcp); - sdcp->state = BLK_ACTIVE; - return CH_SUCCESS; -} - -/** - * @brief Reads one or more blocks. - * @pre The driver must be in the @p BLK_READY state after a successful - * sdcConnect() invocation. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] startblk first block to read - * @param[out] buf pointer to the read buffer - * @param[in] n number of blocks to read - * - * @return The operation status. - * @retval CH_SUCCESS operation succeeded. - * @retval CH_FAILED operation failed. - * - * @api - */ -bool_t sdcRead(SDCDriver *sdcp, uint32_t startblk, - uint8_t *buf, uint32_t n) { - bool_t status; - - chDbgCheck((sdcp != NULL) && (buf != NULL) && (n > 0), "sdcRead"); - chDbgAssert(sdcp->state == BLK_READY, "sdcRead(), #1", "invalid state"); - - if ((startblk + n - 1) > sdcp->capacity){ - sdcp->errors |= SDC_OVERFLOW_ERROR; - return CH_FAILED; - } - - /* Read operation in progress.*/ - sdcp->state = BLK_READING; - - status = sdc_lld_read(sdcp, startblk, buf, n); - - /* Read operation finished.*/ - sdcp->state = BLK_READY; - return status; -} - -/** - * @brief Writes one or more blocks. - * @pre The driver must be in the @p BLK_READY state after a successful - * sdcConnect() invocation. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] startblk first block to write - * @param[out] buf pointer to the write buffer - * @param[in] n number of blocks to write - * - * @return The operation status. - * @retval CH_SUCCESS operation succeeded. - * @retval CH_FAILED operation failed. - * - * @api - */ -bool_t sdcWrite(SDCDriver *sdcp, uint32_t startblk, - const uint8_t *buf, uint32_t n) { - bool_t status; - - chDbgCheck((sdcp != NULL) && (buf != NULL) && (n > 0), "sdcWrite"); - chDbgAssert(sdcp->state == BLK_READY, "sdcWrite(), #1", "invalid state"); - - if ((startblk + n - 1) > sdcp->capacity){ - sdcp->errors |= SDC_OVERFLOW_ERROR; - return CH_FAILED; - } - - /* Write operation in progress.*/ - sdcp->state = BLK_WRITING; - - status = sdc_lld_write(sdcp, startblk, buf, n); - - /* Write operation finished.*/ - sdcp->state = BLK_READY; - return status; -} - -/** - * @brief Returns the errors mask associated to the previous operation. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @return The errors mask. - * - * @api - */ -sdcflags_t sdcGetAndClearErrors(SDCDriver *sdcp) { - sdcflags_t flags; - - chDbgCheck(sdcp != NULL, "sdcGetAndClearErrors"); - chDbgAssert(sdcp->state == BLK_READY, - "sdcGetAndClearErrors(), #1", "invalid state"); - - chSysLock(); - flags = sdcp->errors; - sdcp->errors = SDC_NO_ERROR; - chSysUnlock(); - return flags; -} - -/** - * @brief Waits for card idle condition. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @return The operation status. - * @retval CH_SUCCESS the operation succeeded. - * @retval CH_FAILED the operation failed. - * - * @api - */ -bool_t sdcSync(SDCDriver *sdcp) { - bool_t result; - - chDbgCheck(sdcp != NULL, "sdcSync"); - - if (sdcp->state != BLK_READY) - return CH_FAILED; - - /* Synchronization operation in progress.*/ - sdcp->state = BLK_SYNCING; - - result = sdc_lld_sync(sdcp); - - /* Synchronization operation finished.*/ - sdcp->state = BLK_READY; - return result; -} - -/** - * @brief Returns the media info. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[out] bdip pointer to a @p BlockDeviceInfo structure - * - * @return The operation status. - * @retval CH_SUCCESS the operation succeeded. - * @retval CH_FAILED the operation failed. - * - * @api - */ -bool_t sdcGetInfo(SDCDriver *sdcp, BlockDeviceInfo *bdip) { - - chDbgCheck((sdcp != NULL) && (bdip != NULL), "sdcGetInfo"); - - if (sdcp->state != BLK_READY) - return CH_FAILED; - - bdip->blk_num = sdcp->capacity; - bdip->blk_size = MMCSD_BLOCK_SIZE; - - return CH_SUCCESS; -} - - -/** - * @brief Erases the supplied blocks. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] startblk starting block number - * @param[in] endblk ending block number - * - * @return The operation status. - * @retval CH_SUCCESS the operation succeeded. - * @retval CH_FAILED the operation failed. - * - * @api - */ -bool_t sdcErase(SDCDriver *sdcp, uint32_t startblk, uint32_t endblk) { - uint32_t resp[1]; - - chDbgCheck((sdcp != NULL), "sdcErase"); - chDbgAssert(sdcp->state == BLK_READY, "sdcErase(), #1", "invalid state"); - - /* Erase operation in progress.*/ - sdcp->state = BLK_WRITING; - - /* Handling command differences between HC and normal cards.*/ - if (!(sdcp->cardmode & SDC_MODE_HIGH_CAPACITY)) { - startblk *= MMCSD_BLOCK_SIZE; - endblk *= MMCSD_BLOCK_SIZE; - } - - _sdc_wait_for_transfer_state(sdcp); - - if ((sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_ERASE_RW_BLK_START, - startblk, resp) != CH_SUCCESS) || - MMCSD_R1_ERROR(resp[0])) - goto failed; - - if ((sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_ERASE_RW_BLK_END, - endblk, resp) != CH_SUCCESS) || - MMCSD_R1_ERROR(resp[0])) - goto failed; - - if ((sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_ERASE, - 0, resp) != CH_SUCCESS) || - MMCSD_R1_ERROR(resp[0])) - goto failed; - - /* Quick sleep to allow it to transition to programming or receiving state */ - /* TODO: ??????????????????????????? */ - - /* Wait for it to return to transfer state to indicate it has finished erasing */ - _sdc_wait_for_transfer_state(sdcp); - - sdcp->state = BLK_READY; - return CH_SUCCESS; - -failed: - sdcp->state = BLK_READY; - return CH_FAILED; -} - -#endif /* HAL_USE_SDC */ - -/** @} */ diff --git a/firmware/chibios/os/hal/src/serial.c b/firmware/chibios/os/hal/src/serial.c deleted file mode 100644 index 533adb4372..0000000000 --- a/firmware/chibios/os/hal/src/serial.c +++ /dev/null @@ -1,253 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file serial.c - * @brief Serial Driver code. - * - * @addtogroup SERIAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/* - * Interface implementation, the following functions just invoke the equivalent - * queue-level function or macro. - */ - -static size_t write(void *ip, const uint8_t *bp, size_t n) { - - return chOQWriteTimeout(&((SerialDriver *)ip)->oqueue, bp, - n, TIME_INFINITE); -} - -static size_t read(void *ip, uint8_t *bp, size_t n) { - - return chIQReadTimeout(&((SerialDriver *)ip)->iqueue, bp, - n, TIME_INFINITE); -} - -static msg_t put(void *ip, uint8_t b) { - - return chOQPutTimeout(&((SerialDriver *)ip)->oqueue, b, TIME_INFINITE); -} - -static msg_t get(void *ip) { - - return chIQGetTimeout(&((SerialDriver *)ip)->iqueue, TIME_INFINITE); -} - -static msg_t putt(void *ip, uint8_t b, systime_t timeout) { - - return chOQPutTimeout(&((SerialDriver *)ip)->oqueue, b, timeout); -} - -static msg_t gett(void *ip, systime_t timeout) { - - return chIQGetTimeout(&((SerialDriver *)ip)->iqueue, timeout); -} - -static size_t writet(void *ip, const uint8_t *bp, size_t n, systime_t time) { - - return chOQWriteTimeout(&((SerialDriver *)ip)->oqueue, bp, n, time); -} - -static size_t readt(void *ip, uint8_t *bp, size_t n, systime_t time) { - - return chIQReadTimeout(&((SerialDriver *)ip)->iqueue, bp, n, time); -} - -static const struct SerialDriverVMT vmt = { - write, read, put, get, - putt, gett, writet, readt -}; - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Serial Driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void sdInit(void) { - - sd_lld_init(); -} - -/** - * @brief Initializes a generic full duplex driver object. - * @details The HW dependent part of the initialization has to be performed - * outside, usually in the hardware initialization code. - * - * @param[out] sdp pointer to a @p SerialDriver structure - * @param[in] inotify pointer to a callback function that is invoked when - * some data is read from the Queue. The value can be - * @p NULL. - * @param[in] onotify pointer to a callback function that is invoked when - * some data is written in the Queue. The value can be - * @p NULL. - * - * @init - */ -void sdObjectInit(SerialDriver *sdp, qnotify_t inotify, qnotify_t onotify) { - - sdp->vmt = &vmt; - chEvtInit(&sdp->event); - sdp->state = SD_STOP; - chIQInit(&sdp->iqueue, sdp->ib, SERIAL_BUFFERS_SIZE, inotify, sdp); - chOQInit(&sdp->oqueue, sdp->ob, SERIAL_BUFFERS_SIZE, onotify, sdp); -} - -/** - * @brief Configures and starts the driver. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] config the architecture-dependent serial driver configuration. - * If this parameter is set to @p NULL then a default - * configuration is used. - * - * @api - */ -void sdStart(SerialDriver *sdp, const SerialConfig *config) { - - chDbgCheck(sdp != NULL, "sdStart"); - - chSysLock(); - chDbgAssert((sdp->state == SD_STOP) || (sdp->state == SD_READY), - "sdStart(), #1", - "invalid state"); - sd_lld_start(sdp, config); - sdp->state = SD_READY; - chSysUnlock(); -} - -/** - * @brief Stops the driver. - * @details Any thread waiting on the driver's queues will be awakened with - * the message @p Q_RESET. - * - * @param[in] sdp pointer to a @p SerialDriver object - * - * @api - */ -void sdStop(SerialDriver *sdp) { - - chDbgCheck(sdp != NULL, "sdStop"); - - chSysLock(); - chDbgAssert((sdp->state == SD_STOP) || (sdp->state == SD_READY), - "sdStop(), #1", - "invalid state"); - sd_lld_stop(sdp); - sdp->state = SD_STOP; - chOQResetI(&sdp->oqueue); - chIQResetI(&sdp->iqueue); - chSchRescheduleS(); - chSysUnlock(); -} - -/** - * @brief Handles incoming data. - * @details This function must be called from the input interrupt service - * routine in order to enqueue incoming data and generate the - * related events. - * @note The incoming data event is only generated when the input queue - * becomes non-empty. - * @note In order to gain some performance it is suggested to not use - * this function directly but copy this code directly into the - * interrupt service routine. - * - * @param[in] sdp pointer to a @p SerialDriver structure - * @param[in] b the byte to be written in the driver's Input Queue - * - * @iclass - */ -void sdIncomingDataI(SerialDriver *sdp, uint8_t b) { - - chDbgCheckClassI(); - chDbgCheck(sdp != NULL, "sdIncomingDataI"); - - if (chIQIsEmptyI(&sdp->iqueue)) - chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE); - if (chIQPutI(&sdp->iqueue, b) < Q_OK) - chnAddFlagsI(sdp, SD_OVERRUN_ERROR); -} - -/** - * @brief Handles outgoing data. - * @details Must be called from the output interrupt service routine in order - * to get the next byte to be transmitted. - * @note In order to gain some performance it is suggested to not use - * this function directly but copy this code directly into the - * interrupt service routine. - * - * @param[in] sdp pointer to a @p SerialDriver structure - * @return The byte value read from the driver's output queue. - * @retval Q_EMPTY if the queue is empty (the lower driver usually - * disables the interrupt source when this happens). - * - * @iclass - */ -msg_t sdRequestDataI(SerialDriver *sdp) { - msg_t b; - - chDbgCheckClassI(); - chDbgCheck(sdp != NULL, "sdRequestDataI"); - - b = chOQGetI(&sdp->oqueue); - if (b < Q_OK) - chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); - return b; -} - -#endif /* HAL_USE_SERIAL */ - -/** @} */ diff --git a/firmware/chibios/os/hal/src/serial_usb.c b/firmware/chibios/os/hal/src/serial_usb.c deleted file mode 100644 index 565b2ce1a7..0000000000 --- a/firmware/chibios/os/hal/src/serial_usb.c +++ /dev/null @@ -1,421 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file serial_usb.c - * @brief Serial over USB Driver code. - * - * @addtogroup SERIAL_USB - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_SERIAL_USB || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/* - * Current Line Coding. - */ -static cdc_linecoding_t linecoding = { - {0x00, 0x96, 0x00, 0x00}, /* 38400. */ - LC_STOP_1, LC_PARITY_NONE, 8 -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/* - * Interface implementation. - */ - -static size_t write(void *ip, const uint8_t *bp, size_t n) { - - return chOQWriteTimeout(&((SerialUSBDriver *)ip)->oqueue, bp, - n, TIME_INFINITE); -} - -static size_t read(void *ip, uint8_t *bp, size_t n) { - - return chIQReadTimeout(&((SerialUSBDriver *)ip)->iqueue, bp, - n, TIME_INFINITE); -} - -static msg_t put(void *ip, uint8_t b) { - - return chOQPutTimeout(&((SerialUSBDriver *)ip)->oqueue, b, TIME_INFINITE); -} - -static msg_t get(void *ip) { - - return chIQGetTimeout(&((SerialUSBDriver *)ip)->iqueue, TIME_INFINITE); -} - -static msg_t putt(void *ip, uint8_t b, systime_t timeout) { - - return chOQPutTimeout(&((SerialUSBDriver *)ip)->oqueue, b, timeout); -} - -static msg_t gett(void *ip, systime_t timeout) { - - return chIQGetTimeout(&((SerialUSBDriver *)ip)->iqueue, timeout); -} - -static size_t writet(void *ip, const uint8_t *bp, size_t n, systime_t time) { - - return chOQWriteTimeout(&((SerialUSBDriver *)ip)->oqueue, bp, n, time); -} - -static size_t readt(void *ip, uint8_t *bp, size_t n, systime_t time) { - - return chIQReadTimeout(&((SerialUSBDriver *)ip)->iqueue, bp, n, time); -} - -static const struct SerialUSBDriverVMT vmt = { - write, read, put, get, - putt, gett, writet, readt -}; - -/** - * @brief Notification of data removed from the input queue. - */ -static void inotify(GenericQueue *qp) { - size_t n, maxsize; - SerialUSBDriver *sdup = chQGetLink(qp); - - /* If the USB driver is not in the appropriate state then transactions - must not be started.*/ - if ((usbGetDriverStateI(sdup->config->usbp) != USB_ACTIVE) || - (sdup->state != SDU_READY)) - return; - - /* If there is in the queue enough space to hold at least one packet and - a transaction is not yet started then a new transaction is started for - the available space.*/ - maxsize = sdup->config->usbp->epc[sdup->config->bulk_out]->out_maxsize; - if (!usbGetReceiveStatusI(sdup->config->usbp, sdup->config->bulk_out) && - ((n = chIQGetEmptyI(&sdup->iqueue)) >= maxsize)) { - chSysUnlock(); - - n = (n / maxsize) * maxsize; - usbPrepareQueuedReceive(sdup->config->usbp, - sdup->config->bulk_out, - &sdup->iqueue, n); - - chSysLock(); - usbStartReceiveI(sdup->config->usbp, sdup->config->bulk_out); - } -} - -/** - * @brief Notification of data inserted into the output queue. - */ -static void onotify(GenericQueue *qp) { - size_t n; - SerialUSBDriver *sdup = chQGetLink(qp); - - /* If the USB driver is not in the appropriate state then transactions - must not be started.*/ - if ((usbGetDriverStateI(sdup->config->usbp) != USB_ACTIVE) || - (sdup->state != SDU_READY)) - return; - - /* If there is not an ongoing transaction and the output queue contains - data then a new transaction is started.*/ - if (!usbGetTransmitStatusI(sdup->config->usbp, sdup->config->bulk_in) && - ((n = chOQGetFullI(&sdup->oqueue)) > 0)) { - chSysUnlock(); - - usbPrepareQueuedTransmit(sdup->config->usbp, - sdup->config->bulk_in, - &sdup->oqueue, n); - - chSysLock(); - usbStartTransmitI(sdup->config->usbp, sdup->config->bulk_in); - } -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Serial Driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void sduInit(void) { -} - -/** - * @brief Initializes a generic full duplex driver object. - * @details The HW dependent part of the initialization has to be performed - * outside, usually in the hardware initialization code. - * - * @param[out] sdup pointer to a @p SerialUSBDriver structure - * - * @init - */ -void sduObjectInit(SerialUSBDriver *sdup) { - - sdup->vmt = &vmt; - chEvtInit(&sdup->event); - sdup->state = SDU_STOP; - chIQInit(&sdup->iqueue, sdup->ib, SERIAL_USB_BUFFERS_SIZE, inotify, sdup); - chOQInit(&sdup->oqueue, sdup->ob, SERIAL_USB_BUFFERS_SIZE, onotify, sdup); -} - -/** - * @brief Configures and starts the driver. - * - * @param[in] sdup pointer to a @p SerialUSBDriver object - * @param[in] config the serial over USB driver configuration - * - * @api - */ -void sduStart(SerialUSBDriver *sdup, const SerialUSBConfig *config) { - USBDriver *usbp = config->usbp; - - chDbgCheck(sdup != NULL, "sduStart"); - - chSysLock(); - chDbgAssert((sdup->state == SDU_STOP) || (sdup->state == SDU_READY), - "sduStart(), #1", - "invalid state"); - usbp->in_params[config->bulk_in - 1] = sdup; - usbp->out_params[config->bulk_out - 1] = sdup; - usbp->in_params[config->int_in - 1] = sdup; - sdup->config = config; - sdup->state = SDU_READY; - chSysUnlock(); -} - -/** - * @brief Stops the driver. - * @details Any thread waiting on the driver's queues will be awakened with - * the message @p Q_RESET. - * - * @param[in] sdup pointer to a @p SerialUSBDriver object - * - * @api - */ -void sduStop(SerialUSBDriver *sdup) { - USBDriver *usbp = sdup->config->usbp; - - chDbgCheck(sdup != NULL, "sdStop"); - - chSysLock(); - - chDbgAssert((sdup->state == SDU_STOP) || (sdup->state == SDU_READY), - "sduStop(), #1", - "invalid state"); - - /* Driver in stopped state.*/ - usbp->in_params[sdup->config->bulk_in - 1] = NULL; - usbp->out_params[sdup->config->bulk_out - 1] = NULL; - usbp->in_params[sdup->config->int_in - 1] = NULL; - sdup->state = SDU_STOP; - - /* Queues reset in order to signal the driver stop to the application.*/ - chnAddFlagsI(sdup, CHN_DISCONNECTED); - chIQResetI(&sdup->iqueue); - chOQResetI(&sdup->oqueue); - chSchRescheduleS(); - - chSysUnlock(); -} - -/** - * @brief USB device configured handler. - * - * @param[in] sdup pointer to a @p SerialUSBDriver object - * - * @iclass - */ -void sduConfigureHookI(SerialUSBDriver *sdup) { - USBDriver *usbp = sdup->config->usbp; - - chIQResetI(&sdup->iqueue); - chOQResetI(&sdup->oqueue); - chnAddFlagsI(sdup, CHN_CONNECTED); - - /* Starts the first OUT transaction immediately.*/ - usbPrepareQueuedReceive(usbp, sdup->config->bulk_out, &sdup->iqueue, - usbp->epc[sdup->config->bulk_out]->out_maxsize); - usbStartReceiveI(usbp, sdup->config->bulk_out); -} - -/** - * @brief Default requests hook. - * @details Applications wanting to use the Serial over USB driver can use - * this function as requests hook in the USB configuration. - * The following requests are emulated: - * - CDC_GET_LINE_CODING. - * - CDC_SET_LINE_CODING. - * - CDC_SET_CONTROL_LINE_STATE. - * . - * - * @param[in] usbp pointer to the @p USBDriver object - * @return The hook status. - * @retval TRUE Message handled internally. - * @retval FALSE Message not handled. - */ -bool_t sduRequestsHook(USBDriver *usbp) { - - if ((usbp->setup[0] & USB_RTYPE_TYPE_MASK) == USB_RTYPE_TYPE_CLASS) { - switch (usbp->setup[1]) { - case CDC_GET_LINE_CODING: - usbSetupTransfer(usbp, (uint8_t *)&linecoding, sizeof(linecoding), NULL); - return TRUE; - case CDC_SET_LINE_CODING: - usbSetupTransfer(usbp, (uint8_t *)&linecoding, sizeof(linecoding), NULL); - return TRUE; - case CDC_SET_CONTROL_LINE_STATE: - /* Nothing to do, there are no control lines.*/ - usbSetupTransfer(usbp, NULL, 0, NULL); - return TRUE; - default: - return FALSE; - } - } - return FALSE; -} - -/** - * @brief Default data transmitted callback. - * @details The application must use this function as callback for the IN - * data endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - */ -void sduDataTransmitted(USBDriver *usbp, usbep_t ep) { - size_t n; - SerialUSBDriver *sdup = usbp->in_params[ep - 1]; - - if (sdup == NULL) - return; - - chSysLockFromIsr(); - chnAddFlagsI(sdup, CHN_OUTPUT_EMPTY); - - if ((n = chOQGetFullI(&sdup->oqueue)) > 0) { - /* The endpoint cannot be busy, we are in the context of the callback, - so it is safe to transmit without a check.*/ - chSysUnlockFromIsr(); - - usbPrepareQueuedTransmit(usbp, ep, &sdup->oqueue, n); - - chSysLockFromIsr(); - usbStartTransmitI(usbp, ep); - } - else if ((usbp->epc[ep]->in_state->txsize > 0) && - !(usbp->epc[ep]->in_state->txsize & - (usbp->epc[ep]->in_maxsize - 1))) { - /* Transmit zero sized packet in case the last one has maximum allowed - size. Otherwise the recipient may expect more data coming soon and - not return buffered data to app. See section 5.8.3 Bulk Transfer - Packet Size Constraints of the USB Specification document.*/ - chSysUnlockFromIsr(); - - usbPrepareQueuedTransmit(usbp, ep, &sdup->oqueue, 0); - - chSysLockFromIsr(); - usbStartTransmitI(usbp, ep); - } - - chSysUnlockFromIsr(); -} - -/** - * @brief Default data received callback. - * @details The application must use this function as callback for the OUT - * data endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - */ -void sduDataReceived(USBDriver *usbp, usbep_t ep) { - size_t n, maxsize; - SerialUSBDriver *sdup = usbp->out_params[ep - 1]; - - if (sdup == NULL) - return; - - chSysLockFromIsr(); - chnAddFlagsI(sdup, CHN_INPUT_AVAILABLE); - - /* Writes to the input queue can only happen when there is enough space - to hold at least one packet.*/ - maxsize = usbp->epc[ep]->out_maxsize; - if ((n = chIQGetEmptyI(&sdup->iqueue)) >= maxsize) { - /* The endpoint cannot be busy, we are in the context of the callback, - so a packet is in the buffer for sure.*/ - chSysUnlockFromIsr(); - - n = (n / maxsize) * maxsize; - usbPrepareQueuedReceive(usbp, ep, &sdup->iqueue, n); - - chSysLockFromIsr(); - usbStartReceiveI(usbp, ep); - } - - chSysUnlockFromIsr(); -} - -/** - * @brief Default data received callback. - * @details The application must use this function as callback for the IN - * interrupt endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - */ -void sduInterruptTransmitted(USBDriver *usbp, usbep_t ep) { - - (void)usbp; - (void)ep; -} - -#endif /* HAL_USE_SERIAL */ - -/** @} */ diff --git a/firmware/chibios/os/hal/src/spi.c b/firmware/chibios/os/hal/src/spi.c deleted file mode 100644 index 608c7b7d65..0000000000 --- a/firmware/chibios/os/hal/src/spi.c +++ /dev/null @@ -1,447 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file spi.c - * @brief SPI Driver code. - * - * @addtogroup SPI - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_SPI || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief SPI Driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void spiInit(void) { - - spi_lld_init(); -} - -/** - * @brief Initializes the standard part of a @p SPIDriver structure. - * - * @param[out] spip pointer to the @p SPIDriver object - * - * @init - */ -void spiObjectInit(SPIDriver *spip) { - - spip->state = SPI_STOP; - spip->config = NULL; -#if SPI_USE_WAIT - spip->thread = NULL; -#endif /* SPI_USE_WAIT */ -#if SPI_USE_MUTUAL_EXCLUSION -#if CH_USE_MUTEXES - chMtxInit(&spip->mutex); -#else - chSemInit(&spip->semaphore, 1); -#endif -#endif /* SPI_USE_MUTUAL_EXCLUSION */ -#if defined(SPI_DRIVER_EXT_INIT_HOOK) - SPI_DRIVER_EXT_INIT_HOOK(spip); -#endif -} - -/** - * @brief Configures and activates the SPI peripheral. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] config pointer to the @p SPIConfig object - * - * @api - */ -void spiStart(SPIDriver *spip, const SPIConfig *config) { - - chDbgCheck((spip != NULL) && (config != NULL), "spiStart"); - - chSysLock(); - chDbgAssert((spip->state == SPI_STOP) || (spip->state == SPI_READY), - "spiStart(), #1", "invalid state"); - spip->config = config; - spi_lld_start(spip); - spip->state = SPI_READY; - chSysUnlock(); -} - -/** - * @brief Deactivates the SPI peripheral. - * @note Deactivating the peripheral also enforces a release of the slave - * select line. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @api - */ -void spiStop(SPIDriver *spip) { - - chDbgCheck(spip != NULL, "spiStop"); - - chSysLock(); - chDbgAssert((spip->state == SPI_STOP) || (spip->state == SPI_READY), - "spiStop(), #1", "invalid state"); - spi_lld_unselect(spip); - spi_lld_stop(spip); - spip->state = SPI_STOP; - chSysUnlock(); -} - -/** - * @brief Asserts the slave select signal and prepares for transfers. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @api - */ -void spiSelect(SPIDriver *spip) { - - chDbgCheck(spip != NULL, "spiSelect"); - - chSysLock(); - chDbgAssert(spip->state == SPI_READY, "spiSelect(), #1", "not ready"); - spiSelectI(spip); - chSysUnlock(); -} - -/** - * @brief Deasserts the slave select signal. - * @details The previously selected peripheral is unselected. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @api - */ -void spiUnselect(SPIDriver *spip) { - - chDbgCheck(spip != NULL, "spiUnselect"); - - chSysLock(); - chDbgAssert(spip->state == SPI_READY, "spiUnselect(), #1", "not ready"); - spiUnselectI(spip); - chSysUnlock(); -} - -/** - * @brief Ignores data on the SPI bus. - * @details This asynchronous function starts the transmission of a series of - * idle words on the SPI bus and ignores the received data. - * @pre A slave must have been selected using @p spiSelect() or - * @p spiSelectI(). - * @post At the end of the operation the configured callback is invoked. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be ignored - * - * @api - */ -void spiStartIgnore(SPIDriver *spip, size_t n) { - - chDbgCheck((spip != NULL) && (n > 0), "spiStartIgnore"); - - chSysLock(); - chDbgAssert(spip->state == SPI_READY, "spiStartIgnore(), #1", "not ready"); - spiStartIgnoreI(spip, n); - chSysUnlock(); -} - -/** - * @brief Exchanges data on the SPI bus. - * @details This asynchronous function starts a simultaneous transmit/receive - * operation. - * @pre A slave must have been selected using @p spiSelect() or - * @p spiSelectI(). - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be exchanged - * @param[in] txbuf the pointer to the transmit buffer - * @param[out] rxbuf the pointer to the receive buffer - * - * @api - */ -void spiStartExchange(SPIDriver *spip, size_t n, - const void *txbuf, void *rxbuf) { - - chDbgCheck((spip != NULL) && (n > 0) && (rxbuf != NULL) && (txbuf != NULL), - "spiStartExchange"); - - chSysLock(); - chDbgAssert(spip->state == SPI_READY, "spiStartExchange(), #1", "not ready"); - spiStartExchangeI(spip, n, txbuf, rxbuf); - chSysUnlock(); -} - -/** - * @brief Sends data over the SPI bus. - * @details This asynchronous function starts a transmit operation. - * @pre A slave must have been selected using @p spiSelect() or - * @p spiSelectI(). - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to send - * @param[in] txbuf the pointer to the transmit buffer - * - * @api - */ -void spiStartSend(SPIDriver *spip, size_t n, const void *txbuf) { - - chDbgCheck((spip != NULL) && (n > 0) && (txbuf != NULL), - "spiStartSend"); - - chSysLock(); - chDbgAssert(spip->state == SPI_READY, "spiStartSend(), #1", "not ready"); - spiStartSendI(spip, n, txbuf); - chSysUnlock(); -} - -/** - * @brief Receives data from the SPI bus. - * @details This asynchronous function starts a receive operation. - * @pre A slave must have been selected using @p spiSelect() or - * @p spiSelectI(). - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to receive - * @param[out] rxbuf the pointer to the receive buffer - * - * @api - */ -void spiStartReceive(SPIDriver *spip, size_t n, void *rxbuf) { - - chDbgCheck((spip != NULL) && (n > 0) && (rxbuf != NULL), - "spiStartReceive"); - - chSysLock(); - chDbgAssert(spip->state == SPI_READY, "spiStartReceive(), #1", "not ready"); - spiStartReceiveI(spip, n, rxbuf); - chSysUnlock(); -} - -#if SPI_USE_WAIT || defined(__DOXYGEN__) -/** - * @brief Ignores data on the SPI bus. - * @details This synchronous function performs the transmission of a series of - * idle words on the SPI bus and ignores the received data. - * @pre In order to use this function the option @p SPI_USE_WAIT must be - * enabled. - * @pre In order to use this function the driver must have been configured - * without callbacks (@p end_cb = @p NULL). - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be ignored - * - * @api - */ -void spiIgnore(SPIDriver *spip, size_t n) { - - chDbgCheck((spip != NULL) && (n > 0), "spiIgnoreWait"); - - chSysLock(); - chDbgAssert(spip->state == SPI_READY, "spiIgnore(), #1", "not ready"); - chDbgAssert(spip->config->end_cb == NULL, "spiIgnore(), #2", "has callback"); - spiStartIgnoreI(spip, n); - _spi_wait_s(spip); - chSysUnlock(); -} - -/** - * @brief Exchanges data on the SPI bus. - * @details This synchronous function performs a simultaneous transmit/receive - * operation. - * @pre In order to use this function the option @p SPI_USE_WAIT must be - * enabled. - * @pre In order to use this function the driver must have been configured - * without callbacks (@p end_cb = @p NULL). - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be exchanged - * @param[in] txbuf the pointer to the transmit buffer - * @param[out] rxbuf the pointer to the receive buffer - * - * @api - */ -void spiExchange(SPIDriver *spip, size_t n, - const void *txbuf, void *rxbuf) { - - chDbgCheck((spip != NULL) && (n > 0) && (rxbuf != NULL) && (txbuf != NULL), - "spiExchange"); - - chSysLock(); - chDbgAssert(spip->state == SPI_READY, "spiExchange(), #1", "not ready"); - chDbgAssert(spip->config->end_cb == NULL, - "spiExchange(), #2", "has callback"); - spiStartExchangeI(spip, n, txbuf, rxbuf); - _spi_wait_s(spip); - chSysUnlock(); -} - -/** - * @brief Sends data over the SPI bus. - * @details This synchronous function performs a transmit operation. - * @pre In order to use this function the option @p SPI_USE_WAIT must be - * enabled. - * @pre In order to use this function the driver must have been configured - * without callbacks (@p end_cb = @p NULL). - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to send - * @param[in] txbuf the pointer to the transmit buffer - * - * @api - */ -void spiSend(SPIDriver *spip, size_t n, const void *txbuf) { - - chDbgCheck((spip != NULL) && (n > 0) && (txbuf != NULL), "spiSend"); - - chSysLock(); - chDbgAssert(spip->state == SPI_READY, "spiSend(), #1", "not ready"); - chDbgAssert(spip->config->end_cb == NULL, "spiSend(), #2", "has callback"); - spiStartSendI(spip, n, txbuf); - _spi_wait_s(spip); - chSysUnlock(); -} - -/** - * @brief Receives data from the SPI bus. - * @details This synchronous function performs a receive operation. - * @pre In order to use this function the option @p SPI_USE_WAIT must be - * enabled. - * @pre In order to use this function the driver must have been configured - * without callbacks (@p end_cb = @p NULL). - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to receive - * @param[out] rxbuf the pointer to the receive buffer - * - * @api - */ -void spiReceive(SPIDriver *spip, size_t n, void *rxbuf) { - - chDbgCheck((spip != NULL) && (n > 0) && (rxbuf != NULL), - "spiReceive"); - - chSysLock(); - chDbgAssert(spip->state == SPI_READY, "spiReceive(), #1", "not ready"); - chDbgAssert(spip->config->end_cb == NULL, - "spiReceive(), #2", "has callback"); - spiStartReceiveI(spip, n, rxbuf); - _spi_wait_s(spip); - chSysUnlock(); -} -#endif /* SPI_USE_WAIT */ - -#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) -/** - * @brief Gains exclusive access to the SPI bus. - * @details This function tries to gain ownership to the SPI bus, if the bus - * is already being used then the invoking thread is queued. - * @pre In order to use this function the option @p SPI_USE_MUTUAL_EXCLUSION - * must be enabled. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @api - */ -void spiAcquireBus(SPIDriver *spip) { - - chDbgCheck(spip != NULL, "spiAcquireBus"); - -#if CH_USE_MUTEXES - chMtxLock(&spip->mutex); -#elif CH_USE_SEMAPHORES - chSemWait(&spip->semaphore); -#endif -} - -/** - * @brief Releases exclusive access to the SPI bus. - * @pre In order to use this function the option @p SPI_USE_MUTUAL_EXCLUSION - * must be enabled. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @api - */ -void spiReleaseBus(SPIDriver *spip) { - - chDbgCheck(spip != NULL, "spiReleaseBus"); - -#if CH_USE_MUTEXES - (void)spip; - chMtxUnlock(); -#elif CH_USE_SEMAPHORES - chSemSignal(&spip->semaphore); -#endif -} -#endif /* SPI_USE_MUTUAL_EXCLUSION */ - -#endif /* HAL_USE_SPI */ - -/** @} */ diff --git a/firmware/chibios/os/hal/src/tm.c b/firmware/chibios/os/hal/src/tm.c deleted file mode 100644 index de69a55246..0000000000 --- a/firmware/chibios/os/hal/src/tm.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file tm.c - * @brief Time Measurement driver code. - * - * @addtogroup TM - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_TM || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief Subsystem calibration value. - */ -static halrtcnt_t measurement_offset; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Starts a measurement. - * - * @param[in,out] tmp pointer to a @p TimeMeasurement structure - * - * @notapi - */ -static void tm_start(TimeMeasurement *tmp) { - - tmp->last = halGetCounterValue(); -} - -/** - * @brief Stops a measurement. - * - * @param[in,out] tmp pointer to a @p TimeMeasurement structure - * - * @notapi - */ -static void tm_stop(TimeMeasurement *tmp) { - - halrtcnt_t now = halGetCounterValue(); - tmp->last = now - tmp->last - measurement_offset; - if (tmp->last > tmp->worst) - tmp->worst = tmp->last; - else if (tmp->last < tmp->best) - tmp->best = tmp->last; -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Initializes the Time Measurement unit. - * - * @init - */ -void tmInit(void) { - TimeMeasurement tm; - - /* Time Measurement subsystem calibration, it does a null measurement - and calculates the call overhead which is subtracted to real - measurements.*/ - measurement_offset = 0; - tmObjectInit(&tm); - tmStartMeasurement(&tm); - tmStopMeasurement(&tm); - measurement_offset = tm.last; -} - -/** - * @brief Initializes a @p TimeMeasurement object. - * - * @param[out] tmp pointer to a @p TimeMeasurement structure - * - * @init - */ -void tmObjectInit(TimeMeasurement *tmp) { - - tmp->start = tm_start; - tmp->stop = tm_stop; - tmp->last = (halrtcnt_t)0; - tmp->worst = (halrtcnt_t)0; - tmp->best = (halrtcnt_t)-1; -} - -#endif /* HAL_USE_TM */ - -/** @} */ diff --git a/firmware/chibios/os/hal/src/uart.c b/firmware/chibios/os/hal/src/uart.c deleted file mode 100644 index e8b8479351..0000000000 --- a/firmware/chibios/os/hal/src/uart.c +++ /dev/null @@ -1,360 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file uart.c - * @brief UART Driver code. - * - * @addtogroup UART - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_UART || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief UART Driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void uartInit(void) { - - uart_lld_init(); -} - -/** - * @brief Initializes the standard part of a @p UARTDriver structure. - * - * @param[out] uartp pointer to the @p UARTDriver object - * - * @init - */ -void uartObjectInit(UARTDriver *uartp) { - - uartp->state = UART_STOP; - uartp->txstate = UART_TX_IDLE; - uartp->rxstate = UART_RX_IDLE; - uartp->config = NULL; - /* Optional, user-defined initializer.*/ -#if defined(UART_DRIVER_EXT_INIT_HOOK) - UART_DRIVER_EXT_INIT_HOOK(uartp); -#endif -} - -/** - * @brief Configures and activates the UART peripheral. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] config pointer to the @p UARTConfig object - * - * @api - */ -void uartStart(UARTDriver *uartp, const UARTConfig *config) { - - chDbgCheck((uartp != NULL) && (config != NULL), "uartStart"); - - chSysLock(); - chDbgAssert((uartp->state == UART_STOP) || (uartp->state == UART_READY), - "uartStart(), #1", "invalid state"); - - uartp->config = config; - uart_lld_start(uartp); - uartp->state = UART_READY; - chSysUnlock(); -} - -/** - * @brief Deactivates the UART peripheral. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @api - */ -void uartStop(UARTDriver *uartp) { - - chDbgCheck(uartp != NULL, "uartStop"); - - chSysLock(); - chDbgAssert((uartp->state == UART_STOP) || (uartp->state == UART_READY), - "uartStop(), #1", "invalid state"); - - uart_lld_stop(uartp); - uartp->state = UART_STOP; - uartp->txstate = UART_TX_IDLE; - uartp->rxstate = UART_RX_IDLE; - chSysUnlock(); -} - -/** - * @brief Starts a transmission on the UART peripheral. - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] n number of data frames to send - * @param[in] txbuf the pointer to the transmit buffer - * - * @api - */ -void uartStartSend(UARTDriver *uartp, size_t n, const void *txbuf) { - - chDbgCheck((uartp != NULL) && (n > 0) && (txbuf != NULL), - "uartStartSend"); - - chSysLock(); - chDbgAssert(uartp->state == UART_READY, - "uartStartSend(), #1", "is active"); - chDbgAssert(uartp->txstate != UART_TX_ACTIVE, - "uartStartSend(), #2", "tx active"); - - uart_lld_start_send(uartp, n, txbuf); - uartp->txstate = UART_TX_ACTIVE; - chSysUnlock(); -} - -/** - * @brief Starts a transmission on the UART peripheral. - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * @note This function has to be invoked from a lock zone. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] n number of data frames to send - * @param[in] txbuf the pointer to the transmit buffer - * - * @iclass - */ -void uartStartSendI(UARTDriver *uartp, size_t n, const void *txbuf) { - - chDbgCheckClassI(); - chDbgCheck((uartp != NULL) && (n > 0) && (txbuf != NULL), - "uartStartSendI"); - chDbgAssert(uartp->state == UART_READY, - "uartStartSendI(), #1", "is active"); - chDbgAssert(uartp->txstate != UART_TX_ACTIVE, - "uartStartSendI(), #2", "tx active"); - - uart_lld_start_send(uartp, n, txbuf); - uartp->txstate = UART_TX_ACTIVE; -} - -/** - * @brief Stops any ongoing transmission. - * @note Stopping a transmission also suppresses the transmission callbacks. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @return The number of data frames not transmitted by the - * stopped transmit operation. - * @retval 0 There was no transmit operation in progress. - * - * @api - */ -size_t uartStopSend(UARTDriver *uartp) { - size_t n; - - chDbgCheck(uartp != NULL, "uartStopSend"); - - chSysLock(); - chDbgAssert(uartp->state == UART_READY, "uartStopSend(), #1", "not active"); - - if (uartp->txstate == UART_TX_ACTIVE) { - n = uart_lld_stop_send(uartp); - uartp->txstate = UART_TX_IDLE; - } - else - n = 0; - chSysUnlock(); - return n; -} - -/** - * @brief Stops any ongoing transmission. - * @note Stopping a transmission also suppresses the transmission callbacks. - * @note This function has to be invoked from a lock zone. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @return The number of data frames not transmitted by the - * stopped transmit operation. - * @retval 0 There was no transmit operation in progress. - * - * @iclass - */ -size_t uartStopSendI(UARTDriver *uartp) { - - chDbgCheckClassI(); - chDbgCheck(uartp != NULL, "uartStopSendI"); - chDbgAssert(uartp->state == UART_READY, "uartStopSendI(), #1", "not active"); - - if (uartp->txstate == UART_TX_ACTIVE) { - size_t n = uart_lld_stop_send(uartp); - uartp->txstate = UART_TX_IDLE; - return n; - } - return 0; -} - -/** - * @brief Starts a receive operation on the UART peripheral. - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] n number of data frames to send - * @param[in] rxbuf the pointer to the receive buffer - * - * @api - */ -void uartStartReceive(UARTDriver *uartp, size_t n, void *rxbuf) { - - chDbgCheck((uartp != NULL) && (n > 0) && (rxbuf != NULL), - "uartStartReceive"); - - chSysLock(); - chDbgAssert(uartp->state == UART_READY, - "uartStartReceive(), #1", "is active"); - chDbgAssert(uartp->rxstate != UART_RX_ACTIVE, - "uartStartReceive(), #2", "rx active"); - - uart_lld_start_receive(uartp, n, rxbuf); - uartp->rxstate = UART_RX_ACTIVE; - chSysUnlock(); -} - -/** - * @brief Starts a receive operation on the UART peripheral. - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * @note This function has to be invoked from a lock zone. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] n number of data frames to send - * @param[out] rxbuf the pointer to the receive buffer - * - * @iclass - */ -void uartStartReceiveI(UARTDriver *uartp, size_t n, void *rxbuf) { - - chDbgCheckClassI(); - chDbgCheck((uartp != NULL) && (n > 0) && (rxbuf != NULL), - "uartStartReceiveI"); - chDbgAssert(uartp->state == UART_READY, - "uartStartReceiveI(), #1", "is active"); - chDbgAssert(uartp->rxstate != UART_RX_ACTIVE, - "uartStartReceiveI(), #2", "rx active"); - - uart_lld_start_receive(uartp, n, rxbuf); - uartp->rxstate = UART_RX_ACTIVE; -} - -/** - * @brief Stops any ongoing receive operation. - * @note Stopping a receive operation also suppresses the receive callbacks. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @return The number of data frames not received by the - * stopped receive operation. - * @retval 0 There was no receive operation in progress. - * - * @api - */ -size_t uartStopReceive(UARTDriver *uartp) { - size_t n; - - chDbgCheck(uartp != NULL, "uartStopReceive"); - - chSysLock(); - chDbgAssert(uartp->state == UART_READY, - "uartStopReceive(), #1", "not active"); - - if (uartp->rxstate == UART_RX_ACTIVE) { - n = uart_lld_stop_receive(uartp); - uartp->rxstate = UART_RX_IDLE; - } - else - n = 0; - chSysUnlock(); - return n; -} - -/** - * @brief Stops any ongoing receive operation. - * @note Stopping a receive operation also suppresses the receive callbacks. - * @note This function has to be invoked from a lock zone. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @return The number of data frames not received by the - * stopped receive operation. - * @retval 0 There was no receive operation in progress. - * - * @iclass - */ -size_t uartStopReceiveI(UARTDriver *uartp) { - - chDbgCheckClassI(); - chDbgCheck(uartp != NULL, "uartStopReceiveI"); - chDbgAssert(uartp->state == UART_READY, - "uartStopReceiveI(), #1", "not active"); - - if (uartp->rxstate == UART_RX_ACTIVE) { - size_t n = uart_lld_stop_receive(uartp); - uartp->rxstate = UART_RX_IDLE; - return n; - } - return 0; -} - -#endif /* HAL_USE_UART */ - -/** @} */ diff --git a/firmware/chibios/os/hal/src/usb.c b/firmware/chibios/os/hal/src/usb.c deleted file mode 100644 index db1bf4341a..0000000000 --- a/firmware/chibios/os/hal/src/usb.c +++ /dev/null @@ -1,810 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file usb.c - * @brief USB Driver code. - * - * @addtogroup USB - * @{ - */ - -#include - -#include "ch.h" -#include "hal.h" -#include "usb.h" - -#if HAL_USE_USB || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -static const uint8_t zero_status[] = {0x00, 0x00}; -static const uint8_t active_status[] ={0x00, 0x00}; -static const uint8_t halted_status[] = {0x01, 0x00}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief SET ADDRESS transaction callback. - * - * @param[in] usbp pointer to the @p USBDriver object - */ -static void set_address(USBDriver *usbp) { - - usbp->address = usbp->setup[2]; - usb_lld_set_address(usbp); - _usb_isr_invoke_event_cb(usbp, USB_EVENT_ADDRESS); - usbp->state = USB_SELECTED; -} - -/** - * @brief Standard requests handler. - * @details This is the standard requests default handler, most standard - * requests are handled here, the user can override the standard - * handling using the @p requests_hook_cb hook in the - * @p USBConfig structure. - * - * @param[in] usbp pointer to the @p USBDriver object - * @return The request handling exit code. - * @retval FALSE Request not recognized by the handler or error. - * @retval TRUE Request handled. - */ -static bool_t default_handler(USBDriver *usbp) { - const USBDescriptor *dp; - - /* Decoding the request.*/ - switch (((usbp->setup[0] & (USB_RTYPE_RECIPIENT_MASK | - USB_RTYPE_TYPE_MASK)) | - (usbp->setup[1] << 8))) { - case USB_RTYPE_RECIPIENT_DEVICE | (USB_REQ_GET_STATUS << 8): - /* Just returns the current status word.*/ - usbSetupTransfer(usbp, (uint8_t *)&usbp->status, 2, NULL); - return TRUE; - case USB_RTYPE_RECIPIENT_DEVICE | (USB_REQ_CLEAR_FEATURE << 8): - /* Only the DEVICE_REMOTE_WAKEUP is handled here, any other feature - number is handled as an error.*/ - if (usbp->setup[2] == USB_FEATURE_DEVICE_REMOTE_WAKEUP) { - usbp->status &= ~2; - usbSetupTransfer(usbp, NULL, 0, NULL); - return TRUE; - } - return FALSE; - case USB_RTYPE_RECIPIENT_DEVICE | (USB_REQ_SET_FEATURE << 8): - /* Only the DEVICE_REMOTE_WAKEUP is handled here, any other feature - number is handled as an error.*/ - if (usbp->setup[2] == USB_FEATURE_DEVICE_REMOTE_WAKEUP) { - usbp->status |= 2; - usbSetupTransfer(usbp, NULL, 0, NULL); - return TRUE; - } - return FALSE; - case USB_RTYPE_RECIPIENT_DEVICE | (USB_REQ_SET_ADDRESS << 8): - /* The SET_ADDRESS handling can be performed here or postponed after - the status packed depending on the USB_SET_ADDRESS_MODE low - driver setting.*/ -#if USB_SET_ADDRESS_MODE == USB_EARLY_SET_ADDRESS - if ((usbp->setup[0] == USB_RTYPE_RECIPIENT_DEVICE) && - (usbp->setup[1] == USB_REQ_SET_ADDRESS)) - set_address(usbp); - usbSetupTransfer(usbp, NULL, 0, NULL); -#else - usbSetupTransfer(usbp, NULL, 0, set_address); -#endif - return TRUE; - case USB_RTYPE_RECIPIENT_DEVICE | (USB_REQ_GET_DESCRIPTOR << 8): - /* Handling descriptor requests from the host.*/ - dp = usbp->config->get_descriptor_cb( - usbp, usbp->setup[3], usbp->setup[2], - usbFetchWord(&usbp->setup[4])); - if (dp == NULL) - return FALSE; - usbSetupTransfer(usbp, (uint8_t *)dp->ud_string, dp->ud_size, NULL); - return TRUE; - case USB_RTYPE_RECIPIENT_DEVICE | (USB_REQ_GET_CONFIGURATION << 8): - /* Returning the last selected configuration.*/ - usbSetupTransfer(usbp, &usbp->configuration, 1, NULL); - return TRUE; - case USB_RTYPE_RECIPIENT_DEVICE | (USB_REQ_SET_CONFIGURATION << 8): - /* Handling configuration selection from the host.*/ - usbp->configuration = usbp->setup[2]; - if (usbp->configuration == 0) - usbp->state = USB_SELECTED; - else - usbp->state = USB_ACTIVE; - _usb_isr_invoke_event_cb(usbp, USB_EVENT_CONFIGURED); - usbSetupTransfer(usbp, NULL, 0, NULL); - return TRUE; - case USB_RTYPE_RECIPIENT_INTERFACE | (USB_REQ_GET_STATUS << 8): - case USB_RTYPE_RECIPIENT_ENDPOINT | (USB_REQ_SYNCH_FRAME << 8): - /* Just sending two zero bytes, the application can change the behavior - using a hook..*/ - usbSetupTransfer(usbp, (uint8_t *)zero_status, 2, NULL); - return TRUE; - case USB_RTYPE_RECIPIENT_ENDPOINT | (USB_REQ_GET_STATUS << 8): - /* Sending the EP status.*/ - if (usbp->setup[4] & 0x80) { - switch (usb_lld_get_status_in(usbp, usbp->setup[4] & 0x0F)) { - case EP_STATUS_STALLED: - usbSetupTransfer(usbp, (uint8_t *)halted_status, 2, NULL); - return TRUE; - case EP_STATUS_ACTIVE: - usbSetupTransfer(usbp, (uint8_t *)active_status, 2, NULL); - return TRUE; - default: - return FALSE; - } - } - else { - switch (usb_lld_get_status_out(usbp, usbp->setup[4] & 0x0F)) { - case EP_STATUS_STALLED: - usbSetupTransfer(usbp, (uint8_t *)halted_status, 2, NULL); - return TRUE; - case EP_STATUS_ACTIVE: - usbSetupTransfer(usbp, (uint8_t *)active_status, 2, NULL); - return TRUE; - default: - return FALSE; - } - } - case USB_RTYPE_RECIPIENT_ENDPOINT | (USB_REQ_CLEAR_FEATURE << 8): - /* Only ENDPOINT_HALT is handled as feature.*/ - if (usbp->setup[2] != USB_FEATURE_ENDPOINT_HALT) - return FALSE; - /* Clearing the EP status, not valid for EP0, it is ignored in that case.*/ - if ((usbp->setup[4] & 0x0F) > 0) { - if (usbp->setup[4] & 0x80) - usb_lld_clear_in(usbp, usbp->setup[4] & 0x0F); - else - usb_lld_clear_out(usbp, usbp->setup[4] & 0x0F); - } - usbSetupTransfer(usbp, NULL, 0, NULL); - return TRUE; - case USB_RTYPE_RECIPIENT_ENDPOINT | (USB_REQ_SET_FEATURE << 8): - /* Only ENDPOINT_HALT is handled as feature.*/ - if (usbp->setup[2] != USB_FEATURE_ENDPOINT_HALT) - return FALSE; - /* Stalling the EP, not valid for EP0, it is ignored in that case.*/ - if ((usbp->setup[4] & 0x0F) > 0) { - if (usbp->setup[4] & 0x80) - usb_lld_stall_in(usbp, usbp->setup[4] & 0x0F); - else - usb_lld_stall_out(usbp, usbp->setup[4] & 0x0F); - } - usbSetupTransfer(usbp, NULL, 0, NULL); - return TRUE; - case USB_RTYPE_RECIPIENT_DEVICE | (USB_REQ_SET_DESCRIPTOR << 8): - case USB_RTYPE_RECIPIENT_INTERFACE | (USB_REQ_CLEAR_FEATURE << 8): - case USB_RTYPE_RECIPIENT_INTERFACE | (USB_REQ_SET_FEATURE << 8): - case USB_RTYPE_RECIPIENT_INTERFACE | (USB_REQ_GET_INTERFACE << 8): - case USB_RTYPE_RECIPIENT_INTERFACE | (USB_REQ_SET_INTERFACE << 8): - /* All the above requests are not handled here, if you need them then - use the hook mechanism and provide handling.*/ - default: - return FALSE; - } -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief USB Driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void usbInit(void) { - - usb_lld_init(); -} - -/** - * @brief Initializes the standard part of a @p USBDriver structure. - * - * @param[out] usbp pointer to the @p USBDriver object - * - * @init - */ -void usbObjectInit(USBDriver *usbp) { - unsigned i; - - usbp->state = USB_STOP; - usbp->config = NULL; - for (i = 0; i < USB_MAX_ENDPOINTS; i++) { - usbp->in_params[i] = NULL; - usbp->out_params[i] = NULL; - } - usbp->transmitting = 0; - usbp->receiving = 0; -} - -/** - * @brief Configures and activates the USB peripheral. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] config pointer to the @p USBConfig object - * - * @api - */ -void usbStart(USBDriver *usbp, const USBConfig *config) { - unsigned i; - - chDbgCheck((usbp != NULL) && (config != NULL), "usbStart"); - - chSysLock(); - chDbgAssert((usbp->state == USB_STOP) || (usbp->state == USB_READY), - "usbStart(), #1", "invalid state"); - usbp->config = config; - for (i = 0; i <= USB_MAX_ENDPOINTS; i++) - usbp->epc[i] = NULL; - usb_lld_start(usbp); - usbp->state = USB_READY; - chSysUnlock(); -} - -/** - * @brief Deactivates the USB peripheral. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @api - */ -void usbStop(USBDriver *usbp) { - - chDbgCheck(usbp != NULL, "usbStop"); - - chSysLock(); - chDbgAssert((usbp->state == USB_STOP) || (usbp->state == USB_READY) || - (usbp->state == USB_SELECTED) || (usbp->state == USB_ACTIVE), - "usbStop(), #1", "invalid state"); - usb_lld_stop(usbp); - usbp->state = USB_STOP; - chSysUnlock(); -} - -/** - * @brief Enables an endpoint. - * @details This function enables an endpoint, both IN and/or OUT directions - * depending on the configuration structure. - * @note This function must be invoked in response of a SET_CONFIGURATION - * or SET_INTERFACE message. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @param[in] epcp the endpoint configuration - * - * @iclass - */ -void usbInitEndpointI(USBDriver *usbp, usbep_t ep, - const USBEndpointConfig *epcp) { - - chDbgCheckClassI(); - chDbgCheck((usbp != NULL) && (epcp != NULL), "usbInitEndpointI"); - chDbgAssert(usbp->state == USB_ACTIVE, - "usbEnableEndpointI(), #1", "invalid state"); - chDbgAssert(usbp->epc[ep] == NULL, - "usbEnableEndpointI(), #2", "already initialized"); - - /* Logically enabling the endpoint in the USBDriver structure.*/ - if (epcp->in_state != NULL) - memset(epcp->in_state, 0, sizeof(USBInEndpointState)); - if (epcp->out_state != NULL) - memset(epcp->out_state, 0, sizeof(USBOutEndpointState)); - - usbp->epc[ep] = epcp; - - /* Low level endpoint activation.*/ - usb_lld_init_endpoint(usbp, ep); -} - -/** - * @brief Disables all the active endpoints. - * @details This function disables all the active endpoints except the - * endpoint zero. - * @note This function must be invoked in response of a SET_CONFIGURATION - * message with configuration number zero. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @iclass - */ -void usbDisableEndpointsI(USBDriver *usbp) { - unsigned i; - - chDbgCheckClassI(); - chDbgCheck(usbp != NULL, "usbDisableEndpointsI"); - chDbgAssert(usbp->state == USB_SELECTED, - "usbDisableEndpointsI(), #1", "invalid state"); - - usbp->transmitting &= ~1; - usbp->receiving &= ~1; - for (i = 1; i <= USB_MAX_ENDPOINTS; i++) - usbp->epc[i] = NULL; - - /* Low level endpoints deactivation.*/ - usb_lld_disable_endpoints(usbp); -} - -/** - * @brief Prepares for a receive transaction on an OUT endpoint. - * @post The endpoint is ready for @p usbStartReceiveI(). - * @note This function can be called both in ISR and thread context. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @param[out] buf buffer where to copy the received data - * @param[in] n transaction size - * - * @special - */ -void usbPrepareReceive(USBDriver *usbp, usbep_t ep, uint8_t *buf, size_t n) { - USBOutEndpointState *osp = usbp->epc[ep]->out_state; - - osp->rxqueued = FALSE; - osp->mode.linear.rxbuf = buf; - osp->rxsize = n; - osp->rxcnt = 0; - - usb_lld_prepare_receive(usbp, ep); -} - -/** - * @brief Prepares for a transmit transaction on an IN endpoint. - * @post The endpoint is ready for @p usbStartTransmitI(). - * @note This function can be called both in ISR and thread context. - * @note The queue must contain at least the amount of data specified - * as transaction size. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @param[in] buf buffer where to fetch the data to be transmitted - * @param[in] n transaction size - * - * @special - */ -void usbPrepareTransmit(USBDriver *usbp, usbep_t ep, - const uint8_t *buf, size_t n) { - USBInEndpointState *isp = usbp->epc[ep]->in_state; - - isp->txqueued = FALSE; - isp->mode.linear.txbuf = buf; - isp->txsize = n; - isp->txcnt = 0; - - usb_lld_prepare_transmit(usbp, ep); -} - -/** - * @brief Prepares for a receive transaction on an OUT endpoint. - * @post The endpoint is ready for @p usbStartReceiveI(). - * @note This function can be called both in ISR and thread context. - * @note The queue must have enough free space to accommodate the - * specified transaction size rounded to the next packet size - * boundary. For example if the transaction size is 1 and the - * packet size is 64 then the queue must have space for at least - * 64 bytes. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @param[in] iqp input queue to be filled with incoming data - * @param[in] n transaction size - * - * @special - */ -void usbPrepareQueuedReceive(USBDriver *usbp, usbep_t ep, - InputQueue *iqp, size_t n) { - USBOutEndpointState *osp = usbp->epc[ep]->out_state; - - osp->rxqueued = TRUE; - osp->mode.queue.rxqueue = iqp; - osp->rxsize = n; - osp->rxcnt = 0; - - usb_lld_prepare_receive(usbp, ep); -} - -/** - * @brief Prepares for a transmit transaction on an IN endpoint. - * @post The endpoint is ready for @p usbStartTransmitI(). - * @note This function can be called both in ISR and thread context. - * @note The transmit transaction size is equal to the data contained - * in the queue. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @param[in] oqp output queue to be fetched for outgoing data - * @param[in] n transaction size - * - * @special - */ -void usbPrepareQueuedTransmit(USBDriver *usbp, usbep_t ep, - OutputQueue *oqp, size_t n) { - USBInEndpointState *isp = usbp->epc[ep]->in_state; - - isp->txqueued = TRUE; - isp->mode.queue.txqueue = oqp; - isp->txsize = n; - isp->txcnt = 0; - - usb_lld_prepare_transmit(usbp, ep); -} - -/** - * @brief Starts a receive transaction on an OUT endpoint. - * @post The endpoint callback is invoked when the transfer has been - * completed. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @return The operation status. - * @retval FALSE Operation started successfully. - * @retval TRUE Endpoint busy, operation not started. - * - * @iclass - */ -bool_t usbStartReceiveI(USBDriver *usbp, usbep_t ep) { - - chDbgCheckClassI(); - chDbgCheck(usbp != NULL, "usbStartReceiveI"); - - if (usbGetReceiveStatusI(usbp, ep)) - return TRUE; - - usbp->receiving |= (1 << ep); - usb_lld_start_out(usbp, ep); - return FALSE; -} - -/** - * @brief Starts a transmit transaction on an IN endpoint. - * @post The endpoint callback is invoked when the transfer has been - * completed. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @return The operation status. - * @retval FALSE Operation started successfully. - * @retval TRUE Endpoint busy, operation not started. - * - * @iclass - */ -bool_t usbStartTransmitI(USBDriver *usbp, usbep_t ep) { - - chDbgCheckClassI(); - chDbgCheck(usbp != NULL, "usbStartTransmitI"); - - if (usbGetTransmitStatusI(usbp, ep)) - return TRUE; - - usbp->transmitting |= (1 << ep); - usb_lld_start_in(usbp, ep); - return FALSE; -} - -/** - * @brief Stalls an OUT endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @return The operation status. - * @retval FALSE Endpoint stalled. - * @retval TRUE Endpoint busy, not stalled. - * - * @iclass - */ -bool_t usbStallReceiveI(USBDriver *usbp, usbep_t ep) { - - chDbgCheckClassI(); - chDbgCheck(usbp != NULL, "usbStallReceiveI"); - - if (usbGetReceiveStatusI(usbp, ep)) - return TRUE; - - usb_lld_stall_out(usbp, ep); - return FALSE; -} - -/** - * @brief Stalls an IN endpoint. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * - * @return The operation status. - * @retval FALSE Endpoint stalled. - * @retval TRUE Endpoint busy, not stalled. - * - * @iclass - */ -bool_t usbStallTransmitI(USBDriver *usbp, usbep_t ep) { - - chDbgCheckClassI(); - chDbgCheck(usbp != NULL, "usbStallTransmitI"); - - if (usbGetTransmitStatusI(usbp, ep)) - return TRUE; - - usb_lld_stall_in(usbp, ep); - return FALSE; -} - -/** - * @brief USB reset routine. - * @details This function must be invoked when an USB bus reset condition is - * detected. - * - * @param[in] usbp pointer to the @p USBDriver object - * - * @notapi - */ -void _usb_reset(USBDriver *usbp) { - unsigned i; - - usbp->state = USB_READY; - usbp->status = 0; - usbp->address = 0; - usbp->configuration = 0; - usbp->transmitting = 0; - usbp->receiving = 0; - - /* Invalidates all endpoints into the USBDriver structure.*/ - for (i = 0; i <= USB_MAX_ENDPOINTS; i++) - usbp->epc[i] = NULL; - - /* EP0 state machine initialization.*/ - usbp->ep0state = USB_EP0_WAITING_SETUP; - - /* Low level reset.*/ - usb_lld_reset(usbp); -} - -/** - * @brief Default EP0 SETUP callback. - * @details This function is used by the low level driver as default handler - * for EP0 SETUP events. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number, always zero - * - * @notapi - */ -void _usb_ep0setup(USBDriver *usbp, usbep_t ep) { - size_t max; - - usbp->ep0state = USB_EP0_WAITING_SETUP; - usbReadSetup(usbp, ep, usbp->setup); - - /* First verify if the application has an handler installed for this - request.*/ - if (!(usbp->config->requests_hook_cb) || - !(usbp->config->requests_hook_cb(usbp))) { - /* Invoking the default handler, if this fails then stalls the - endpoint zero as error.*/ - if (((usbp->setup[0] & USB_RTYPE_TYPE_MASK) != USB_RTYPE_TYPE_STD) || - !default_handler(usbp)) { - /* Error response, the state machine goes into an error state, the low - level layer will have to reset it to USB_EP0_WAITING_SETUP after - receiving a SETUP packet.*/ - usb_lld_stall_in(usbp, 0); - usb_lld_stall_out(usbp, 0); - _usb_isr_invoke_event_cb(usbp, USB_EVENT_STALLED); - usbp->ep0state = USB_EP0_ERROR; - return; - } - } -#if (USB_SET_ADDRESS_ACK_HANDLING == USB_SET_ADDRESS_ACK_HW) - if (usbp->setup[1] == USB_REQ_SET_ADDRESS) { - /* Zero-length packet sent by hardware */ - return; - } -#endif - /* Transfer preparation. The request handler must have populated - correctly the fields ep0next, ep0n and ep0endcb using the macro - usbSetupTransfer().*/ - max = usbFetchWord(&usbp->setup[6]); - /* The transfer size cannot exceed the specified amount.*/ - if (usbp->ep0n > max) - usbp->ep0n = max; - if ((usbp->setup[0] & USB_RTYPE_DIR_MASK) == USB_RTYPE_DIR_DEV2HOST) { - /* IN phase.*/ - if (usbp->ep0n > 0) { - /* Starts the transmit phase.*/ - usbp->ep0state = USB_EP0_TX; - usbPrepareTransmit(usbp, 0, usbp->ep0next, usbp->ep0n); - chSysLockFromIsr(); - usbStartTransmitI(usbp, 0); - chSysUnlockFromIsr(); - } - else { - /* No transmission phase, directly receiving the zero sized status - packet.*/ - usbp->ep0state = USB_EP0_WAITING_STS; -#if (USB_EP0_STATUS_STAGE == USB_EP0_STATUS_STAGE_SW) - usbPrepareReceive(usbp, 0, NULL, 0); - chSysLockFromIsr(); - usbStartReceiveI(usbp, 0); - chSysUnlockFromIsr(); -#else - usb_lld_end_setup(usbp, ep); -#endif - } - } - else { - /* OUT phase.*/ - if (usbp->ep0n > 0) { - /* Starts the receive phase.*/ - usbp->ep0state = USB_EP0_RX; - usbPrepareReceive(usbp, 0, usbp->ep0next, usbp->ep0n); - chSysLockFromIsr(); - usbStartReceiveI(usbp, 0); - chSysUnlockFromIsr(); - } - else { - /* No receive phase, directly sending the zero sized status - packet.*/ - usbp->ep0state = USB_EP0_SENDING_STS; -#if (USB_EP0_STATUS_STAGE == USB_EP0_STATUS_STAGE_SW) - usbPrepareTransmit(usbp, 0, NULL, 0); - chSysLockFromIsr(); - usbStartTransmitI(usbp, 0); - chSysUnlockFromIsr(); -#else - usb_lld_end_setup(usbp, ep); -#endif - } - } -} - -/** - * @brief Default EP0 IN callback. - * @details This function is used by the low level driver as default handler - * for EP0 IN events. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number, always zero - * - * @notapi - */ -void _usb_ep0in(USBDriver *usbp, usbep_t ep) { - size_t max; - - (void)ep; - switch (usbp->ep0state) { - case USB_EP0_TX: - max = usbFetchWord(&usbp->setup[6]); - /* If the transmitted size is less than the requested size and it is a - multiple of the maximum packet size then a zero size packet must be - transmitted.*/ - if ((usbp->ep0n < max) && ((usbp->ep0n % usbp->epc[0]->in_maxsize) == 0)) { - usbPrepareTransmit(usbp, 0, NULL, 0); - chSysLockFromIsr(); - usbStartTransmitI(usbp, 0); - chSysUnlockFromIsr(); - usbp->ep0state = USB_EP0_WAITING_TX0; - return; - } - /* Falls into, it is intentional.*/ - case USB_EP0_WAITING_TX0: - /* Transmit phase over, receiving the zero sized status packet.*/ - usbp->ep0state = USB_EP0_WAITING_STS; -#if (USB_EP0_STATUS_STAGE == USB_EP0_STATUS_STAGE_SW) - usbPrepareReceive(usbp, 0, NULL, 0); - chSysLockFromIsr(); - usbStartReceiveI(usbp, 0); - chSysUnlockFromIsr(); -#else - usb_lld_end_setup(usbp, ep); -#endif - return; - case USB_EP0_SENDING_STS: - /* Status packet sent, invoking the callback if defined.*/ - if (usbp->ep0endcb != NULL) - usbp->ep0endcb(usbp); - usbp->ep0state = USB_EP0_WAITING_SETUP; - return; - default: - ; - } - /* Error response, the state machine goes into an error state, the low - level layer will have to reset it to USB_EP0_WAITING_SETUP after - receiving a SETUP packet.*/ - usb_lld_stall_in(usbp, 0); - usb_lld_stall_out(usbp, 0); - _usb_isr_invoke_event_cb(usbp, USB_EVENT_STALLED); - usbp->ep0state = USB_EP0_ERROR; -} - -/** - * @brief Default EP0 OUT callback. - * @details This function is used by the low level driver as default handler - * for EP0 OUT events. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number, always zero - * - * @notapi - */ -void _usb_ep0out(USBDriver *usbp, usbep_t ep) { - - (void)ep; - switch (usbp->ep0state) { - case USB_EP0_RX: - /* Receive phase over, sending the zero sized status packet.*/ - usbp->ep0state = USB_EP0_SENDING_STS; -#if (USB_EP0_STATUS_STAGE == USB_EP0_STATUS_STAGE_SW) - usbPrepareTransmit(usbp, 0, NULL, 0); - chSysLockFromIsr(); - usbStartTransmitI(usbp, 0); - chSysUnlockFromIsr(); -#else - usb_lld_end_setup(usbp, ep); -#endif - return; - case USB_EP0_WAITING_STS: - /* Status packet received, it must be zero sized, invoking the callback - if defined.*/ -#if (USB_EP0_STATUS_STAGE == USB_EP0_STATUS_STAGE_SW) - if (usbGetReceiveTransactionSizeI(usbp, 0) != 0) - break; -#endif - if (usbp->ep0endcb != NULL) - usbp->ep0endcb(usbp); - usbp->ep0state = USB_EP0_WAITING_SETUP; - return; - default: - ; - } - /* Error response, the state machine goes into an error state, the low - level layer will have to reset it to USB_EP0_WAITING_SETUP after - receiving a SETUP packet.*/ - usb_lld_stall_in(usbp, 0); - usb_lld_stall_out(usbp, 0); - _usb_isr_invoke_event_cb(usbp, USB_EVENT_STALLED); - usbp->ep0state = USB_EP0_ERROR; -} - -#endif /* HAL_USE_USB */ - -/** @} */ diff --git a/firmware/chibios/os/kernel/include/ch.h b/firmware/chibios/os/kernel/include/ch.h deleted file mode 100644 index c2a14646aa..0000000000 --- a/firmware/chibios/os/kernel/include/ch.h +++ /dev/null @@ -1,150 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file ch.h - * @brief ChibiOS/RT main include file. - * @details This header includes all the required kernel headers so it is the - * only kernel header you usually want to include in your application. - * - * @addtogroup kernel_info - * @details Kernel related info. - * @{ - */ - -#ifndef _CH_H_ -#define _CH_H_ - -/** - * @brief ChibiOS/RT identification macro. - */ -#define _CHIBIOS_RT_ - -/** - * @brief Kernel version string. - */ -#define CH_KERNEL_VERSION "2.6.8" - -/** - * @name Kernel version - * @{ - */ -/** - * @brief Kernel version major number. - */ -#define CH_KERNEL_MAJOR 2 - -/** - * @brief Kernel version minor number. - */ -#define CH_KERNEL_MINOR 6 - -/** - * @brief Kernel version patch number. - */ -#define CH_KERNEL_PATCH 8 -/** @} */ - -/** - * @name Common constants - */ -/** - * @brief Generic 'false' boolean constant. - */ -#if !defined(FALSE) || defined(__DOXYGEN__) -#define FALSE 0 -#endif - -/** - * @brief Generic 'true' boolean constant. - */ -#if !defined(TRUE) || defined(__DOXYGEN__) -#define TRUE (!FALSE) -#endif - -/** - * @brief Generic success constant. - * @details This constant is functionally equivalent to @p FALSE but more - * readable, it can be used as return value of all those functions - * returning a @p bool_t as a status indicator. - */ -#if !defined(CH_SUCCESS) || defined(__DOXYGEN__) -#define CH_SUCCESS FALSE -#endif - -/** - * @brief Generic failure constant. - * @details This constant is functionally equivalent to @p TRUE but more - * readable, it can be used as return value of all those functions - * returning a @p bool_t as a status indicator. - */ -#if !defined(CH_FAILED) || defined(__DOXYGEN__) -#define CH_FAILED TRUE -#endif -/** @} */ - -#include "chconf.h" -#include "chtypes.h" -#include "chlists.h" -#include "chcore.h" -#include "chsys.h" -#include "chvt.h" -#include "chschd.h" -#include "chsem.h" -#include "chbsem.h" -#include "chmtx.h" -#include "chcond.h" -#include "chevents.h" -#include "chmsg.h" -#include "chmboxes.h" -#include "chmemcore.h" -#include "chheap.h" -#include "chmempools.h" -#include "chthreads.h" -#include "chdynamic.h" -#include "chregistry.h" -#include "chinline.h" -#include "chqueues.h" -#include "chstreams.h" -#include "chfiles.h" -#include "chdebug.h" - -#if !defined(__DOXYGEN__) -extern WORKING_AREA(_idle_thread_wa, PORT_IDLE_THREAD_STACK_SIZE); -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void _idle_thread(void *p); -#ifdef __cplusplus -} -#endif - -#endif /* _CH_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/kernel/include/chbsem.h b/firmware/chibios/os/kernel/include/chbsem.h deleted file mode 100644 index 539d473ed5..0000000000 --- a/firmware/chibios/os/kernel/include/chbsem.h +++ /dev/null @@ -1,258 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chbsem.h - * @brief Binary semaphores structures and macros. - * - * @addtogroup binary_semaphores - * @details Binary semaphores related APIs and services. - * - *

Operation mode

- * Binary semaphores are implemented as a set of macros that use the - * existing counting semaphores primitives. The difference between - * counting and binary semaphores is that the counter of binary - * semaphores is not allowed to grow above the value 1. Repeated - * signal operation are ignored. A binary semaphore can thus have - * only two defined states: - * - Taken, when its counter has a value of zero or lower - * than zero. A negative number represent the number of threads - * queued on the binary semaphore. - * - Not taken, when its counter has a value of one. - * . - * Binary semaphores are different from mutexes because there is no - * the concept of ownership, a binary semaphore can be taken by a - * thread and signaled by another thread or an interrupt handler, - * mutexes can only be taken and released by the same thread. Another - * difference is that binary semaphores, unlike mutexes, do not - * implement the priority inheritance protocol.
- * In order to use the binary semaphores APIs the @p CH_USE_SEMAPHORES - * option must be enabled in @p chconf.h. - * @{ - */ - -#ifndef _CHBSEM_H_ -#define _CHBSEM_H_ - -#if CH_USE_SEMAPHORES || defined(__DOXYGEN__) - -/** - * @extends Semaphore - * - * @brief Binary semaphore type. - */ -typedef struct { - Semaphore bs_sem; -} BinarySemaphore; - -/** - * @brief Data part of a static semaphore initializer. - * @details This macro should be used when statically initializing a semaphore - * that is part of a bigger structure. - * - * @param[in] name the name of the semaphore variable - * @param[in] taken the semaphore initial state - */ -#define _BSEMAPHORE_DATA(name, taken) \ - {_SEMAPHORE_DATA(name.bs_sem, ((taken) ? 0 : 1))} - -/** - * @brief Static semaphore initializer. - * @details Statically initialized semaphores require no explicit - * initialization using @p chBSemInit(). - * - * @param[in] name the name of the semaphore variable - * @param[in] taken the semaphore initial state - */ -#define BSEMAPHORE_DECL(name, taken) \ - BinarySemaphore name = _BSEMAPHORE_DATA(name, taken) - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Initializes a binary semaphore. - * - * @param[out] bsp pointer to a @p BinarySemaphore structure - * @param[in] taken initial state of the binary semaphore: - * - @a FALSE, the initial state is not taken. - * - @a TRUE, the initial state is taken. - * . - * - * @init - */ -#define chBSemInit(bsp, taken) chSemInit(&(bsp)->bs_sem, (taken) ? 0 : 1) - -/** - * @brief Wait operation on the binary semaphore. - * - * @param[in] bsp pointer to a @p BinarySemaphore structure - * @return A message specifying how the invoking thread has been - * released from the semaphore. - * @retval RDY_OK if the binary semaphore has been successfully taken. - * @retval RDY_RESET if the binary semaphore has been reset using - * @p bsemReset(). - * - * @api - */ -#define chBSemWait(bsp) chSemWait(&(bsp)->bs_sem) - -/** - * @brief Wait operation on the binary semaphore. - * - * @param[in] bsp pointer to a @p BinarySemaphore structure - * @return A message specifying how the invoking thread has been - * released from the semaphore. - * @retval RDY_OK if the binary semaphore has been successfully taken. - * @retval RDY_RESET if the binary semaphore has been reset using - * @p bsemReset(). - * - * @sclass - */ -#define chBSemWaitS(bsp) chSemWaitS(&(bsp)->bs_sem) - -/** - * @brief Wait operation on the binary semaphore. - * - * @param[in] bsp pointer to a @p BinarySemaphore structure - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return A message specifying how the invoking thread has been - * released from the semaphore. - * @retval RDY_OK if the binary semaphore has been successfully taken. - * @retval RDY_RESET if the binary semaphore has been reset using - * @p bsemReset(). - * @retval RDY_TIMEOUT if the binary semaphore has not been signaled or reset - * within the specified timeout. - * - * @api - */ -#define chBSemWaitTimeout(bsp, time) chSemWaitTimeout(&(bsp)->bs_sem, (time)) - -/** - * @brief Wait operation on the binary semaphore. - * - * @param[in] bsp pointer to a @p BinarySemaphore structure - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return A message specifying how the invoking thread has been - * released from the semaphore. - * @retval RDY_OK if the binary semaphore has been successfully taken. - * @retval RDY_RESET if the binary semaphore has been reset using - * @p bsemReset(). - * @retval RDY_TIMEOUT if the binary semaphore has not been signaled or reset - * within the specified timeout. - * - * @sclass - */ -#define chBSemWaitTimeoutS(bsp, time) chSemWaitTimeoutS(&(bsp)->bs_sem, (time)) - -/** - * @brief Reset operation on the binary semaphore. - * @note The released threads can recognize they were waked up by a reset - * rather than a signal because the @p bsemWait() will return - * @p RDY_RESET instead of @p RDY_OK. - * - * @param[in] bsp pointer to a @p BinarySemaphore structure - * @param[in] taken new state of the binary semaphore - * - @a FALSE, the new state is not taken. - * - @a TRUE, the new state is taken. - * . - * - * @api - */ -#define chBSemReset(bsp, taken) chSemReset(&(bsp)->bs_sem, (taken) ? 0 : 1) - -/** - * @brief Reset operation on the binary semaphore. - * @note The released threads can recognize they were waked up by a reset - * rather than a signal because the @p bsemWait() will return - * @p RDY_RESET instead of @p RDY_OK. - * @note This function does not reschedule. - * - * @param[in] bsp pointer to a @p BinarySemaphore structure - * @param[in] taken new state of the binary semaphore - * - @a FALSE, the new state is not taken. - * - @a TRUE, the new state is taken. - * . - * - * @iclass - */ -#define chBSemResetI(bsp, taken) chSemResetI(&(bsp)->bs_sem, (taken) ? 0 : 1) - -/** - * @brief Performs a signal operation on a binary semaphore. - * - * @param[in] bsp pointer to a @p BinarySemaphore structure - * - * @api - */ -#define chBSemSignal(bsp) { \ - chSysLock(); \ - chBSemSignalI((bsp)); \ - chSchRescheduleS(); \ - chSysUnlock(); \ -} - -/** - * @brief Performs a signal operation on a binary semaphore. - * @note This function does not reschedule. - * - * @param[in] bsp pointer to a @p BinarySemaphore structure - * - * @iclass - */ -#define chBSemSignalI(bsp) { \ - if ((bsp)->bs_sem.s_cnt < 1) \ - chSemSignalI(&(bsp)->bs_sem); \ -} - -/** - * @brief Returns the binary semaphore current state. - * - * @param[in] bsp pointer to a @p BinarySemaphore structure - * @return The binary semaphore current state. - * @retval FALSE if the binary semaphore is not taken. - * @retval TRUE if the binary semaphore is taken. - * - * @iclass - */ -#define chBSemGetStateI(bsp) ((bsp)->bs_sem.s_cnt > 0 ? FALSE : TRUE) -/** @} */ - -#endif /* CH_USE_SEMAPHORES */ - -#endif /* _CHBSEM_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/kernel/include/chcond.h b/firmware/chibios/os/kernel/include/chcond.h deleted file mode 100644 index 5949b31187..0000000000 --- a/firmware/chibios/os/kernel/include/chcond.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ -/* - Concepts and parts of this file have been contributed by Leon Woestenberg. - */ - -/** - * @file chcond.h - * @brief Condition Variables macros and structures. - * - * @addtogroup condvars - * @{ - */ - -#ifndef _CHCOND_H_ -#define _CHCOND_H_ - -#if CH_USE_CONDVARS || defined(__DOXYGEN__) - -/* - * Module dependencies check. - */ -#if !CH_USE_MUTEXES -#error "CH_USE_CONDVARS requires CH_USE_MUTEXES" -#endif - -/** - * @brief CondVar structure. - */ -typedef struct CondVar { - ThreadsQueue c_queue; /**< @brief CondVar threads queue.*/ -} CondVar; - -#ifdef __cplusplus -extern "C" { -#endif - void chCondInit(CondVar *cp); - void chCondSignal(CondVar *cp); - void chCondSignalI(CondVar *cp); - void chCondBroadcast(CondVar *cp); - void chCondBroadcastI(CondVar *cp); - msg_t chCondWait(CondVar *cp); - msg_t chCondWaitS(CondVar *cp); -#if CH_USE_CONDVARS_TIMEOUT - msg_t chCondWaitTimeout(CondVar *cp, systime_t time); - msg_t chCondWaitTimeoutS(CondVar *cp, systime_t time); -#endif -#ifdef __cplusplus -} -#endif - -/** - * @brief Data part of a static condition variable initializer. - * @details This macro should be used when statically initializing a condition - * variable that is part of a bigger structure. - * - * @param[in] name the name of the condition variable - */ -#define _CONDVAR_DATA(name) {_THREADSQUEUE_DATA(name.c_queue)} - -/** - * @brief Static condition variable initializer. - * @details Statically initialized condition variables require no explicit - * initialization using @p chCondInit(). - * - * @param[in] name the name of the condition variable - */ -#define CONDVAR_DECL(name) CondVar name = _CONDVAR_DATA(name) - -#endif /* CH_USE_CONDVARS */ - -#endif /* _CHCOND_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/kernel/include/chdebug.h b/firmware/chibios/os/kernel/include/chdebug.h deleted file mode 100644 index aee596a9ca..0000000000 --- a/firmware/chibios/os/kernel/include/chdebug.h +++ /dev/null @@ -1,265 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chdebug.h - * @brief Debug macros and structures. - * - * @addtogroup debug - * @{ - */ - -#ifndef _CHDEBUG_H_ -#define _CHDEBUG_H_ - -#if CH_DBG_ENABLE_ASSERTS || CH_DBG_ENABLE_CHECKS || \ - CH_DBG_ENABLE_STACK_CHECK || CH_DBG_SYSTEM_STATE_CHECK -#define CH_DBG_ENABLED TRUE -#else -#define CH_DBG_ENABLED FALSE -#endif - -#define __QUOTE_THIS(p) #p - -/*===========================================================================*/ -/** - * @name Debug related settings - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Trace buffer entries. - */ -#ifndef CH_TRACE_BUFFER_SIZE -#define CH_TRACE_BUFFER_SIZE 64 -#endif - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -void chDbgPanic3(const char *msg, const char * file, int line); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -/** - * @brief Fill value for thread stack area in debug mode. - */ -#ifndef CH_STACK_FILL_VALUE -#define CH_STACK_FILL_VALUE 0x55 -#endif - -/** - * @brief Fill value for thread area in debug mode. - * @note The chosen default value is 0xFF in order to make evident which - * thread fields were not initialized when inspecting the memory with - * a debugger. A uninitialized field is not an error in itself but it - * better to know it. - */ -#ifndef CH_THREAD_FILL_VALUE -#define CH_THREAD_FILL_VALUE 0xFF -#endif - -/** @} */ - -/*===========================================================================*/ -/* System state checker related code and variables. */ -/*===========================================================================*/ - -#if !CH_DBG_SYSTEM_STATE_CHECK -#define dbg_enter_lock() -#define dbg_leave_lock() -#define dbg_check_disable() -#define dbg_check_suspend() -#define dbg_check_enable() -#define dbg_check_lock() -#define dbg_check_unlock() -#define dbg_check_lock_from_isr() -#define dbg_check_unlock_from_isr() -#define dbg_check_enter_isr() -#define dbg_check_leave_isr() -#define chDbgCheckClassI() -#define chDbgCheckClassS() -#else -#define dbg_enter_lock() {dbg_lock_cnt = 1;ON_LOCK_HOOK;} -#define dbg_leave_lock() {ON_UNLOCK_HOOK;dbg_lock_cnt = 0;} -#endif - -/*===========================================================================*/ -/* Trace related structures and macros. */ -/*===========================================================================*/ - -#if CH_DBG_ENABLE_TRACE || defined(__DOXYGEN__) -/** - * @brief Trace buffer record. - */ -typedef struct { - systime_t se_time; /**< @brief Time of the switch event. */ - Thread *se_tp; /**< @brief Switched in thread. */ - void *se_wtobjp; /**< @brief Object where going to sleep.*/ - uint8_t se_state; /**< @brief Switched out thread state. */ -} ch_swc_event_t; - -/** - * @brief Trace buffer header. - */ -typedef struct { - unsigned tb_size; /**< @brief Trace buffer size (entries).*/ - ch_swc_event_t *tb_ptr; /**< @brief Pointer to the buffer front.*/ - /** @brief Ring buffer.*/ - ch_swc_event_t tb_buffer[CH_TRACE_BUFFER_SIZE]; -} ch_trace_buffer_t; - -#if !defined(__DOXYGEN__) -extern ch_trace_buffer_t dbg_trace_buffer; -#endif - -#endif /* CH_DBG_ENABLE_TRACE */ - -#if !CH_DBG_ENABLE_TRACE -/* When the trace feature is disabled this function is replaced by an empty - macro.*/ -#define dbg_trace(otp) -#endif - -/*===========================================================================*/ -/* Parameters checking related macros. */ -/*===========================================================================*/ - -#if CH_DBG_ENABLE_CHECKS || defined(__DOXYGEN__) -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Function parameters check. - * @details If the condition check fails then the kernel panics and halts. - * @note The condition is tested only if the @p CH_DBG_ENABLE_CHECKS switch - * is specified in @p chconf.h else the macro does nothing. - * - * @param[in] c the condition to be verified to be true - * @param[in] func the undecorated function name - * - * @api - */ -#if !defined(chDbgCheck) -#define chDbgCheck(c, func) { \ - if (!(c)) \ - chDbgPanic(__QUOTE_THIS(func)"()"); \ -} -#endif /* !defined(chDbgCheck) */ -/** @} */ -#else /* !CH_DBG_ENABLE_CHECKS */ -#define chDbgCheck(c, func) { \ - (void)(c), (void)__QUOTE_THIS(func)"()"; \ -} -#endif /* !CH_DBG_ENABLE_CHECKS */ - -/*===========================================================================*/ -/* Assertions related macros. */ -/*===========================================================================*/ - -#if CH_DBG_ENABLE_ASSERTS || defined(__DOXYGEN__) -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Condition assertion. - * @details If the condition check fails then the kernel panics with the - * specified message and halts. - * @note The condition is tested only if the @p CH_DBG_ENABLE_ASSERTS switch - * is specified in @p chconf.h else the macro does nothing. - * @note The convention for the message is the following:
- * @(), #@ - * @note The remark string is not currently used except for putting a - * comment in the code about the assertion. - * - * @param[in] c the condition to be verified to be true - * @param[in] m the text message - * @param[in] r a remark string - * - * @api - */ -#if !defined(chDbgAssert) -#define chDbgAssert(c, m, r) { \ - if (!(c)) \ - chDbgPanic(m); \ -} -#endif /* !defined(chDbgAssert) */ -/** @} */ -#else /* !CH_DBG_ENABLE_ASSERTS */ -#define chDbgAssert(c, m, r) {(void)(c);} -#endif /* !CH_DBG_ENABLE_ASSERTS */ - -/*===========================================================================*/ -/* Panic related macros. */ -/*===========================================================================*/ - -#if !CH_DBG_ENABLED -/* When the debug features are disabled this function is replaced by an empty - macro.*/ -#define chDbgPanic(msg) {} -#endif - -#ifdef __cplusplus -extern "C" { -#endif -#if CH_DBG_SYSTEM_STATE_CHECK - extern cnt_t dbg_isr_cnt; - extern cnt_t dbg_lock_cnt; - void dbg_check_disable(void); - void dbg_check_suspend(void); - void dbg_check_enable(void); - void dbg_check_lock(void); - void dbg_check_unlock(void); - void dbg_check_lock_from_isr(void); - void dbg_check_unlock_from_isr(void); - void dbg_check_enter_isr(void); - void dbg_check_leave_isr(void); - void chDbgCheckClassI(void); - void chDbgCheckClassS(void); -#endif -#if CH_DBG_ENABLE_TRACE || defined(__DOXYGEN__) - void _trace_init(void); - void dbg_trace(Thread *otp); -#endif -#if CH_DBG_ENABLED - extern const char *dbg_panic_msg; - void chDbgPanic(const char *msg); -#endif -#ifdef __cplusplus -} -#endif - -#endif /* _CHDEBUG_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/kernel/include/chdynamic.h b/firmware/chibios/os/kernel/include/chdynamic.h deleted file mode 100644 index 1eeebe4893..0000000000 --- a/firmware/chibios/os/kernel/include/chdynamic.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chdynamic.h - * @brief Dynamic threads macros and structures. - * - * @addtogroup dynamic_threads - * @{ - */ - -#ifndef _CHDYNAMIC_H_ -#define _CHDYNAMIC_H_ - -#if CH_USE_DYNAMIC || defined(__DOXYGEN__) - -/* - * Module dependencies check. - */ -#if CH_USE_DYNAMIC && !CH_USE_WAITEXIT -#error "CH_USE_DYNAMIC requires CH_USE_WAITEXIT" -#endif -#if CH_USE_DYNAMIC && !CH_USE_HEAP && !CH_USE_MEMPOOLS -#error "CH_USE_DYNAMIC requires CH_USE_HEAP and/or CH_USE_MEMPOOLS" -#endif - -/* - * Dynamic threads APIs. - */ -#ifdef __cplusplus -extern "C" { -#endif - Thread *chThdAddRef(Thread *tp); - void chThdRelease(Thread *tp); -#if CH_USE_HEAP - Thread *chThdCreateFromHeap(MemoryHeap *heapp, size_t size, - tprio_t prio, tfunc_t pf, void *arg); -#endif -#if CH_USE_MEMPOOLS - Thread *chThdCreateFromMemoryPool(MemoryPool *mp, tprio_t prio, - tfunc_t pf, void *arg); -#endif -#ifdef __cplusplus -} -#endif - -#endif /* CH_USE_DYNAMIC */ - -#endif /* _CHDYNAMIC_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/kernel/include/chevents.h b/firmware/chibios/os/kernel/include/chevents.h deleted file mode 100644 index 026351e6c5..0000000000 --- a/firmware/chibios/os/kernel/include/chevents.h +++ /dev/null @@ -1,212 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ -/* - Concepts and parts of this file have been contributed by Scott (skute). - */ - -/** - * @file chevents.h - * @brief Events macros and structures. - * - * @addtogroup events - * @{ - */ - -#ifndef _CHEVENTS_H_ -#define _CHEVENTS_H_ - -#if CH_USE_EVENTS || defined(__DOXYGEN__) - -typedef struct EventListener EventListener; - -/** - * @brief Event Listener structure. - */ -struct EventListener { - EventListener *el_next; /**< @brief Next Event Listener - registered on the Event - Source. */ - Thread *el_listener; /**< @brief Thread interested in the - Event Source. */ - eventmask_t el_mask; /**< @brief Event flags mask associated - by the thread to the Event - Source. */ - flagsmask_t el_flags; /**< @brief Flags added to the listener - by the event source. */ -}; - -/** - * @brief Event Source structure. - */ -typedef struct EventSource { - EventListener *es_next; /**< @brief First Event Listener - registered on the Event - Source. */ -} EventSource; - -/** - * @brief Event Handler callback function. - */ -typedef void (*evhandler_t)(eventid_t); - -/** - * @brief Data part of a static event source initializer. - * @details This macro should be used when statically initializing an event - * source that is part of a bigger structure. - * @param name the name of the event source variable - */ -#define _EVENTSOURCE_DATA(name) {(void *)(&name)} - -/** - * @brief Static event source initializer. - * @details Statically initialized event sources require no explicit - * initialization using @p chEvtInit(). - * - * @param name the name of the event source variable - */ -#define EVENTSOURCE_DECL(name) EventSource name = _EVENTSOURCE_DATA(name) - -/** - * @brief All events allowed mask. - */ -#define ALL_EVENTS ((eventmask_t)-1) - -/** - * @brief Returns an event mask from an event identifier. - */ -#define EVENT_MASK(eid) ((eventmask_t)(1 << (eid))) - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Registers an Event Listener on an Event Source. - * @note Multiple Event Listeners can use the same event identifier, the - * listener will share the callback function. - * - * @param[in] esp pointer to the @p EventSource structure - * @param[out] elp pointer to the @p EventListener structure - * @param[in] eid numeric identifier assigned to the Event Listener. The - * identifier is used as index for the event callback - * function. - * The value must range between zero and the size, in bit, - * of the @p eventmask_t type minus one. - * - * @api - */ -#define chEvtRegister(esp, elp, eid) \ - chEvtRegisterMask(esp, elp, EVENT_MASK(eid)) - -/** - * @brief Initializes an Event Source. - * @note This function can be invoked before the kernel is initialized - * because it just prepares a @p EventSource structure. - * - * @param[out] esp pointer to the @p EventSource structure - * - * @init - */ -#define chEvtInit(esp) \ - ((esp)->es_next = (EventListener *)(void *)(esp)) - -/** - * @brief Verifies if there is at least one @p EventListener registered. - * - * @param[in] esp pointer to the @p EventSource structure - * - * @iclass - */ -#define chEvtIsListeningI(esp) \ - ((void *)(esp) != (void *)(esp)->es_next) - -/** - * @brief Signals all the Event Listeners registered on the specified Event - * Source. - * - * @param[in] esp pointer to the @p EventSource structure - * - * @api - */ -#define chEvtBroadcast(esp) chEvtBroadcastFlags(esp, 0) - -/** - * @brief Signals all the Event Listeners registered on the specified Event - * Source. - * @post This function does not reschedule so a call to a rescheduling - * function must be performed before unlocking the kernel. Note that - * interrupt handlers always reschedule on exit so an explicit - * reschedule must not be performed in ISRs. - * - * @param[in] esp pointer to the @p EventSource structure - * - * @iclass - */ -#define chEvtBroadcastI(esp) chEvtBroadcastFlagsI(esp, 0) -/** @} */ - -#ifdef __cplusplus -extern "C" { -#endif - void chEvtRegisterMask(EventSource *esp, - EventListener *elp, - eventmask_t mask); - void chEvtUnregister(EventSource *esp, EventListener *elp); - eventmask_t chEvtGetAndClearEvents(eventmask_t mask); - eventmask_t chEvtAddEvents(eventmask_t mask); - flagsmask_t chEvtGetAndClearFlags(EventListener *elp); - flagsmask_t chEvtGetAndClearFlagsI(EventListener *elp); - void chEvtSignal(Thread *tp, eventmask_t mask); - void chEvtSignalI(Thread *tp, eventmask_t mask); - void chEvtBroadcastFlags(EventSource *esp, flagsmask_t flags); - void chEvtBroadcastFlagsI(EventSource *esp, flagsmask_t flags); - void chEvtDispatch(const evhandler_t *handlers, eventmask_t mask); -#if CH_OPTIMIZE_SPEED || !CH_USE_EVENTS_TIMEOUT - eventmask_t chEvtWaitOne(eventmask_t mask); - eventmask_t chEvtWaitAny(eventmask_t mask); - eventmask_t chEvtWaitAll(eventmask_t mask); -#endif -#if CH_USE_EVENTS_TIMEOUT - eventmask_t chEvtWaitOneTimeout(eventmask_t mask, systime_t time); - eventmask_t chEvtWaitAnyTimeout(eventmask_t mask, systime_t time); - eventmask_t chEvtWaitAllTimeout(eventmask_t mask, systime_t time); -#endif -#ifdef __cplusplus -} -#endif - -#if !CH_OPTIMIZE_SPEED && CH_USE_EVENTS_TIMEOUT -#define chEvtWaitOne(mask) chEvtWaitOneTimeout(mask, TIME_INFINITE) -#define chEvtWaitAny(mask) chEvtWaitAnyTimeout(mask, TIME_INFINITE) -#define chEvtWaitAll(mask) chEvtWaitAllTimeout(mask, TIME_INFINITE) -#endif - -#endif /* CH_USE_EVENTS */ - -#endif /* _CHEVENTS_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/kernel/include/chfiles.h b/firmware/chibios/os/kernel/include/chfiles.h deleted file mode 100644 index cddcf27c93..0000000000 --- a/firmware/chibios/os/kernel/include/chfiles.h +++ /dev/null @@ -1,172 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chfiles.h - * @brief Data files. - * @details This header defines abstract interfaces useful to access generic - * data files in a standardized way. - * - * @addtogroup data_files - * @details This module define an abstract interface for generic data files by - * extending the @p BaseSequentialStream interface. Note that no code - * is present, data files are just abstract interface-like structures, - * you should look at the systems as to a set of abstract C++ classes - * (even if written in C). This system has the advantage to make the - * access to streams independent from the implementation logic.
- * The data files interface can be used as base class for high level - * object types such as an API for a File System implementation. - * @{ - */ - -#ifndef _CHFILES_H_ -#define _CHFILES_H_ - -/** - * @brief No error return code. - */ -#define FILE_OK 0 - -/** - * @brief Error code from the file stream methods. - */ -#define FILE_ERROR 0xFFFFFFFFUL - -/** - * @brief File offset type. - */ -typedef uint32_t fileoffset_t; - -/** - * @brief BaseFileStream specific methods. - */ -#define _base_file_stream_methods \ - _base_sequential_stream_methods \ - /* File close method.*/ \ - uint32_t (*close)(void *instance); \ - /* Get last error code method.*/ \ - int (*geterror)(void *instance); \ - /* File get size method.*/ \ - fileoffset_t (*getsize)(void *instance); \ - /* File get current position method.*/ \ - fileoffset_t (*getposition)(void *instance); \ - /* File seek method.*/ \ - uint32_t (*lseek)(void *instance, fileoffset_t offset); - -/** - * @brief @p BaseFileStream specific data. - * @note It is empty because @p BaseFileStream is only an interface - * without implementation. - */ -#define _base_file_stream_data \ - _base_sequential_stream_data - -/** - * @extends BaseSequentialStreamVMT - * - * @brief @p BaseFileStream virtual methods table. - */ -struct BaseFileStreamVMT { - _base_file_stream_methods -}; - -/** - * @extends BaseSequentialStream - * - * @brief Base file stream class. - * @details This class represents a generic file data stream. - */ -typedef struct { - /** @brief Virtual Methods Table.*/ - const struct BaseFileStreamVMT *vmt; - _base_file_stream_data -} BaseFileStream; - -/** - * @name Macro Functions (BaseFileStream) - * @{ - */ -/** - * @brief Base file Stream close. - * @details The function closes a file stream. - * - * @param[in] ip pointer to a @p BaseFileStream or derived class - * @return The operation status. - * @retval FILE_OK no error. - * @retval FILE_ERROR operation failed. - * - * @api - */ -#define chFileStreamClose(ip) ((ip)->vmt->close(ip)) - -/** - * @brief Returns an implementation dependent error code. - * - * @param[in] ip pointer to a @p BaseFileStream or derived class - * @return Implementation dependent error code. - * - * @api - */ -#define chFileStreamGetError(ip) ((ip)->vmt->geterror(ip)) - -/** - * @brief Returns the current file size. - * - * @param[in] ip pointer to a @p BaseFileStream or derived class - * @return The file size. - * - * @api - */ -#define chFileStreamGetSize(ip) ((ip)->vmt->getsize(ip)) - -/** - * @brief Returns the current file pointer position. - * - * @param[in] ip pointer to a @p BaseFileStream or derived class - * @return The current position inside the file. - * - * @api - */ -#define chFileStreamGetPosition(ip) ((ip)->vmt->getposition(ip)) - -/** - * @brief Moves the file current pointer to an absolute position. - * - * @param[in] ip pointer to a @p BaseFileStream or derived class - * @param[in] offset new absolute position - * @return The operation status. - * @retval FILE_OK no error. - * @retval FILE_ERROR operation failed. - * - * @api - */ -#define chFileStreamSeek(ip, offset) ((ip)->vmt->lseek(ip, offset)) -/** @} */ - -#endif /* _CHFILES_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/kernel/include/chheap.h b/firmware/chibios/os/kernel/include/chheap.h deleted file mode 100644 index 110b5aba10..0000000000 --- a/firmware/chibios/os/kernel/include/chheap.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chheap.h - * @brief Heaps macros and structures. - * - * @addtogroup heaps - * @{ - */ - -#ifndef _CHHEAP_H_ -#define _CHHEAP_H_ - -#if CH_USE_HEAP || defined(__DOXYGEN__) - -/* - * Module dependencies check. - */ -#if !CH_USE_MEMCORE && !CH_USE_MALLOC_HEAP -#error "CH_USE_HEAP requires CH_USE_MEMCORE or CH_USE_MALLOC_HEAP" -#endif - -#if !CH_USE_MUTEXES && !CH_USE_SEMAPHORES -#error "CH_USE_HEAP requires CH_USE_MUTEXES and/or CH_USE_SEMAPHORES" -#endif - -typedef struct memory_heap MemoryHeap; - -/** - * @brief Memory heap block header. - */ -union heap_header { - stkalign_t align; - struct { - union { - union heap_header *next; /**< @brief Next block in free list. */ - MemoryHeap *heap; /**< @brief Block owner heap. */ - } u; /**< @brief Overlapped fields. */ - size_t size; /**< @brief Size of the memory block. */ - } h; -}; - -/** - * @brief Structure describing a memory heap. - */ -struct memory_heap { - memgetfunc_t h_provider; /**< @brief Memory blocks provider for - this heap. */ - union heap_header h_free; /**< @brief Free blocks list header. */ -#if CH_USE_MUTEXES - Mutex h_mtx; /**< @brief Heap access mutex. */ -#else - Semaphore h_sem; /**< @brief Heap access semaphore. */ -#endif -}; - -#ifdef __cplusplus -extern "C" { -#endif - void _heap_init(void); -#if !CH_USE_MALLOC_HEAP - void chHeapInit(MemoryHeap *heapp, void *buf, size_t size); -#endif - void *chHeapAlloc(MemoryHeap *heapp, size_t size); - void chHeapFree(void *p); - size_t chHeapStatus(MemoryHeap *heapp, size_t *sizep); -#ifdef __cplusplus -} -#endif - -#endif /* CH_USE_HEAP */ - -#endif /* _CHHEAP_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/kernel/include/chinline.h b/firmware/chibios/os/kernel/include/chinline.h deleted file mode 100644 index bd617672cf..0000000000 --- a/firmware/chibios/os/kernel/include/chinline.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chinline.h - * @brief Kernel inlined functions. - * @details In this file there are a set of inlined functions if the - * @p CH_OPTIMIZE_SPEED is enabled. - */ - -#ifndef _CHINLINE_H_ -#define _CHINLINE_H_ - -/* If the performance code path has been chosen then all the following - functions are inlined into the various kernel modules.*/ -#if CH_OPTIMIZE_SPEED -static INLINE void prio_insert(Thread *tp, ThreadsQueue *tqp) { - - Thread *cp = (Thread *)tqp; - do { - cp = cp->p_next; - } while ((cp != (Thread *)tqp) && (cp->p_prio >= tp->p_prio)); - tp->p_next = cp; - tp->p_prev = cp->p_prev; - tp->p_prev->p_next = cp->p_prev = tp; -} - -static INLINE void queue_insert(Thread *tp, ThreadsQueue *tqp) { - - tp->p_next = (Thread *)tqp; - tp->p_prev = tqp->p_prev; - tp->p_prev->p_next = tqp->p_prev = tp; -} - -static INLINE Thread *fifo_remove(ThreadsQueue *tqp) { - Thread *tp = tqp->p_next; - - (tqp->p_next = tp->p_next)->p_prev = (Thread *)tqp; - return tp; -} - -static INLINE Thread *lifo_remove(ThreadsQueue *tqp) { - Thread *tp = tqp->p_prev; - - (tqp->p_prev = tp->p_prev)->p_next = (Thread *)tqp; - return tp; -} - -static INLINE Thread *dequeue(Thread *tp) { - - tp->p_prev->p_next = tp->p_next; - tp->p_next->p_prev = tp->p_prev; - return tp; -} - -static INLINE void list_insert(Thread *tp, ThreadsList *tlp) { - - tp->p_next = tlp->p_next; - tlp->p_next = tp; -} - -static INLINE Thread *list_remove(ThreadsList *tlp) { - - Thread *tp = tlp->p_next; - tlp->p_next = tp->p_next; - return tp; -} -#endif /* CH_OPTIMIZE_SPEED */ - -#endif /* _CHINLINE_H_ */ diff --git a/firmware/chibios/os/kernel/include/chlists.h b/firmware/chibios/os/kernel/include/chlists.h deleted file mode 100644 index 833a61e6e2..0000000000 --- a/firmware/chibios/os/kernel/include/chlists.h +++ /dev/null @@ -1,134 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chlists.h - * @brief Thread queues/lists macros and structures. - * @note All the macros present in this module, while public, are not - * an OS API and should not be directly used in the user applications - * code. - * - * @addtogroup internals - * @{ - */ - -#ifndef _CHLISTS_H_ -#define _CHLISTS_H_ - -typedef struct Thread Thread; - -/** - * @brief Threads queue initialization. - * - * @notapi - */ -#define queue_init(tqp) ((tqp)->p_next = (tqp)->p_prev = (Thread *)(tqp)); - -/** - * @brief Threads list initialization. - * - * @notapi - */ -#define list_init(tlp) ((tlp)->p_next = (Thread *)(tlp)) - -/** - * @brief Evaluates to @p TRUE if the specified threads queue or list is - * empty. - * - * @notapi - */ -#define isempty(p) ((p)->p_next == (Thread *)(p)) - -/** - * @brief Evaluates to @p TRUE if the specified threads queue or list is - * not empty. - * - * @notapi - */ -#define notempty(p) ((p)->p_next != (Thread *)(p)) - -/** - * @brief Data part of a static threads queue initializer. - * @details This macro should be used when statically initializing a threads - * queue that is part of a bigger structure. - * - * @param[in] name the name of the threads queue variable - */ -#define _THREADSQUEUE_DATA(name) {(Thread *)&name, (Thread *)&name} - -/** - * @brief Static threads queue initializer. - * @details Statically initialized threads queues require no explicit - * initialization using @p queue_init(). - * - * @param[in] name the name of the threads queue variable - */ -#define THREADSQUEUE_DECL(name) ThreadsQueue name = _THREADSQUEUE_DATA(name) - -/** - * @extends ThreadsList - * - * @brief Generic threads bidirectional linked list header and element. - */ -typedef struct { - Thread *p_next; /**< First @p Thread in the queue, or - @p ThreadQueue when empty. */ - Thread *p_prev; /**< Last @p Thread in the queue, or - @p ThreadQueue when empty. */ -} ThreadsQueue; - -/** - * @brief Generic threads single link list, it works like a stack. - */ -typedef struct { - - Thread *p_next; /**< Last pushed @p Thread on the stack - list, or pointer to itself if - empty. */ -} ThreadsList; - -#if !CH_OPTIMIZE_SPEED - -#ifdef __cplusplus -extern "C" { -#endif - void prio_insert(Thread *tp, ThreadsQueue *tqp); - void queue_insert(Thread *tp, ThreadsQueue *tqp); - Thread *fifo_remove(ThreadsQueue *tqp); - Thread *lifo_remove(ThreadsQueue *tqp); - Thread *dequeue(Thread *tp); - void list_insert(Thread *tp, ThreadsList *tlp); - Thread *list_remove(ThreadsList *tlp); -#ifdef __cplusplus -} -#endif - -#endif /* !CH_OPTIMIZE_SPEED */ - -#endif /* _CHLISTS_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/kernel/include/chmboxes.h b/firmware/chibios/os/kernel/include/chmboxes.h deleted file mode 100644 index 4245b12e37..0000000000 --- a/firmware/chibios/os/kernel/include/chmboxes.h +++ /dev/null @@ -1,170 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chmboxes.h - * @brief Mailboxes macros and structures. - * - * @addtogroup mailboxes - * @{ - */ - -#ifndef _CHMBOXES_H_ -#define _CHMBOXES_H_ - -#if CH_USE_MAILBOXES || defined(__DOXYGEN__) - -/* - * Module dependencies check. - */ -#if !CH_USE_SEMAPHORES -#error "CH_USE_MAILBOXES requires CH_USE_SEMAPHORES" -#endif - -/** - * @brief Structure representing a mailbox object. - */ -typedef struct { - msg_t *mb_buffer; /**< @brief Pointer to the mailbox - buffer. */ - msg_t *mb_top; /**< @brief Pointer to the location - after the buffer. */ - msg_t *mb_wrptr; /**< @brief Write pointer. */ - msg_t *mb_rdptr; /**< @brief Read pointer. */ - Semaphore mb_fullsem; /**< @brief Full counter - @p Semaphore. */ - Semaphore mb_emptysem; /**< @brief Empty counter - @p Semaphore. */ -} Mailbox; - -#ifdef __cplusplus -extern "C" { -#endif - void chMBInit(Mailbox *mbp, msg_t *buf, cnt_t n); - void chMBReset(Mailbox *mbp); - msg_t chMBPost(Mailbox *mbp, msg_t msg, systime_t timeout); - msg_t chMBPostS(Mailbox *mbp, msg_t msg, systime_t timeout); - msg_t chMBPostI(Mailbox *mbp, msg_t msg); - msg_t chMBPostAhead(Mailbox *mbp, msg_t msg, systime_t timeout); - msg_t chMBPostAheadS(Mailbox *mbp, msg_t msg, systime_t timeout); - msg_t chMBPostAheadI(Mailbox *mbp, msg_t msg); - msg_t chMBFetch(Mailbox *mbp, msg_t *msgp, systime_t timeout); - msg_t chMBFetchS(Mailbox *mbp, msg_t *msgp, systime_t timeout); - msg_t chMBFetchI(Mailbox *mbp, msg_t *msgp); -#ifdef __cplusplus -} -#endif - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Returns the mailbox buffer size. - * - * @param[in] mbp the pointer to an initialized Mailbox object - * - * @iclass - */ -#define chMBSizeI(mbp) \ - ((mbp)->mb_top - (mbp)->mb_buffer) - -/** - * @brief Returns the number of free message slots into a mailbox. - * @note Can be invoked in any system state but if invoked out of a locked - * state then the returned value may change after reading. - * @note The returned value can be less than zero when there are waiting - * threads on the internal semaphore. - * - * @param[in] mbp the pointer to an initialized Mailbox object - * @return The number of empty message slots. - * - * @iclass - */ -#define chMBGetFreeCountI(mbp) chSemGetCounterI(&(mbp)->mb_emptysem) - -/** - * @brief Returns the number of used message slots into a mailbox. - * @note Can be invoked in any system state but if invoked out of a locked - * state then the returned value may change after reading. - * @note The returned value can be less than zero when there are waiting - * threads on the internal semaphore. - * - * @param[in] mbp the pointer to an initialized Mailbox object - * @return The number of queued messages. - * - * @iclass - */ -#define chMBGetUsedCountI(mbp) chSemGetCounterI(&(mbp)->mb_fullsem) - -/** - * @brief Returns the next message in the queue without removing it. - * @pre A message must be waiting in the queue for this function to work - * or it would return garbage. The correct way to use this macro is - * to use @p chMBGetFullCountI() and then use this macro, all within - * a lock state. - * - * @iclass - */ -#define chMBPeekI(mbp) (*(mbp)->mb_rdptr) -/** @} */ - -/** - * @brief Data part of a static mailbox initializer. - * @details This macro should be used when statically initializing a - * mailbox that is part of a bigger structure. - * - * @param[in] name the name of the mailbox variable - * @param[in] buffer pointer to the mailbox buffer area - * @param[in] size size of the mailbox buffer area - */ -#define _MAILBOX_DATA(name, buffer, size) { \ - (msg_t *)(buffer), \ - (msg_t *)(buffer) + size, \ - (msg_t *)(buffer), \ - (msg_t *)(buffer), \ - _SEMAPHORE_DATA(name.mb_fullsem, 0), \ - _SEMAPHORE_DATA(name.mb_emptysem, size), \ -} - -/** - * @brief Static mailbox initializer. - * @details Statically initialized mailboxes require no explicit - * initialization using @p chMBInit(). - * - * @param[in] name the name of the mailbox variable - * @param[in] buffer pointer to the mailbox buffer area - * @param[in] size size of the mailbox buffer area - */ -#define MAILBOX_DECL(name, buffer, size) \ - Mailbox name = _MAILBOX_DATA(name, buffer, size) - -#endif /* CH_USE_MAILBOXES */ - -#endif /* _CHMBOXES_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/kernel/include/chmemcore.h b/firmware/chibios/os/kernel/include/chmemcore.h deleted file mode 100644 index 66780fb5b6..0000000000 --- a/firmware/chibios/os/kernel/include/chmemcore.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chmemcore.h - * @brief Core memory manager macros and structures. - * - * @addtogroup memcore - * @{ - */ - -#ifndef _CHMEMCORE_H_ -#define _CHMEMCORE_H_ - -/** - * @brief Memory get function. - * @note This type must be assignment compatible with the @p chMemAlloc() - * function. - */ -typedef void *(*memgetfunc_t)(size_t size); - -/** - * @name Alignment support macros - */ -/** - * @brief Alignment size constant. - */ -#define MEM_ALIGN_SIZE sizeof(stkalign_t) - -/** - * @brief Alignment mask constant. - */ -#define MEM_ALIGN_MASK (MEM_ALIGN_SIZE - 1) - -/** - * @brief Alignment helper macro. - */ -#define MEM_ALIGN_PREV(p) ((size_t)(p) & ~MEM_ALIGN_MASK) - -/** - * @brief Alignment helper macro. - */ -#define MEM_ALIGN_NEXT(p) MEM_ALIGN_PREV((size_t)(p) + MEM_ALIGN_MASK) - -/** - * @brief Returns whatever a pointer or memory size is aligned to - * the type @p align_t. - */ -#define MEM_IS_ALIGNED(p) (((size_t)(p) & MEM_ALIGN_MASK) == 0) -/** @} */ - -#if CH_USE_MEMCORE || defined(__DOXYGEN__) - -#ifdef __cplusplus -extern "C" { -#endif - void _core_init(void); - void *chCoreAlloc(size_t size); - void *chCoreAllocI(size_t size); - size_t chCoreStatus(void); -#ifdef __cplusplus -} -#endif - -#endif /* CH_USE_MEMCORE */ - -#endif /* _CHMEMCORE_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/kernel/include/chmempools.h b/firmware/chibios/os/kernel/include/chmempools.h deleted file mode 100644 index 0edc8d0ac2..0000000000 --- a/firmware/chibios/os/kernel/include/chmempools.h +++ /dev/null @@ -1,141 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chmempools.h - * @brief Memory Pools macros and structures. - * - * @addtogroup pools - * @{ - */ - -#ifndef _CHMEMPOOLS_H_ -#define _CHMEMPOOLS_H_ - -#if CH_USE_MEMPOOLS || defined(__DOXYGEN__) - -/** - * @brief Memory pool free object header. - */ -struct pool_header { - struct pool_header *ph_next; /**< @brief Pointer to the next pool - header in the list. */ -}; - -/** - * @brief Memory pool descriptor. - */ -typedef struct { - struct pool_header *mp_next; /**< @brief Pointer to the header. */ - size_t mp_object_size; /**< @brief Memory pool objects - size. */ - memgetfunc_t mp_provider; /**< @brief Memory blocks provider for - this pool. */ -} MemoryPool; - -/** - * @brief Data part of a static memory pool initializer. - * @details This macro should be used when statically initializing a - * memory pool that is part of a bigger structure. - * - * @param[in] name the name of the memory pool variable - * @param[in] size size of the memory pool contained objects - * @param[in] provider memory provider function for the memory pool - */ -#define _MEMORYPOOL_DATA(name, size, provider) \ - {NULL, size, provider} - -/** - * @brief Static memory pool initializer in hungry mode. - * @details Statically initialized memory pools require no explicit - * initialization using @p chPoolInit(). - * - * @param[in] name the name of the memory pool variable - * @param[in] size size of the memory pool contained objects - * @param[in] provider memory provider function for the memory pool or @p NULL - * if the pool is not allowed to grow automatically - */ -#define MEMORYPOOL_DECL(name, size, provider) \ - MemoryPool name = _MEMORYPOOL_DATA(name, size, provider) - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Adds an object to a memory pool. - * @pre The memory pool must be already been initialized. - * @pre The added object must be of the right size for the specified - * memory pool. - * @pre The added object must be memory aligned to the size of - * @p stkalign_t type. - * @note This function is just an alias for @p chPoolFree() and has been - * added for clarity. - * - * @param[in] mp pointer to a @p MemoryPool structure - * @param[in] objp the pointer to the object to be added - * - * @api - */ -#define chPoolAdd(mp, objp) chPoolFree(mp, objp) - -/** - * @brief Adds an object to a memory pool. - * @pre The memory pool must be already been initialized. - * @pre The added object must be of the right size for the specified - * memory pool. - * @pre The added object must be memory aligned to the size of - * @p stkalign_t type. - * @note This function is just an alias for @p chPoolFree() and has been - * added for clarity. - * - * @param[in] mp pointer to a @p MemoryPool structure - * @param[in] objp the pointer to the object to be added - * - * @iclass - */ -#define chPoolAddI(mp, objp) chPoolFreeI(mp, objp) -/** @} */ - -#ifdef __cplusplus -extern "C" { -#endif - void chPoolInit(MemoryPool *mp, size_t size, memgetfunc_t provider); - void chPoolLoadArray(MemoryPool *mp, void *p, size_t n); - void *chPoolAllocI(MemoryPool *mp); - void *chPoolAlloc(MemoryPool *mp); - void chPoolFreeI(MemoryPool *mp, void *objp); - void chPoolFree(MemoryPool *mp, void *objp); -#ifdef __cplusplus -} -#endif - -#endif /* CH_USE_MEMPOOLS */ - -#endif /* _CHMEMPOOLS_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/kernel/include/chmsg.h b/firmware/chibios/os/kernel/include/chmsg.h deleted file mode 100644 index 3e73db8fc2..0000000000 --- a/firmware/chibios/os/kernel/include/chmsg.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chmsg.h - * @brief Messages macros and structures. - * - * @addtogroup messages - * @{ - */ - -#ifndef _CHMSG_H_ -#define _CHMSG_H_ - -#if CH_USE_MESSAGES || defined(__DOXYGEN__) - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Evaluates to TRUE if the thread has pending messages. - * - * @iclass - */ -#define chMsgIsPendingI(tp) \ - ((tp)->p_msgqueue.p_next != (Thread *)&(tp)->p_msgqueue) - -/** - * @brief Returns the message carried by the specified thread. - * @pre This function must be invoked immediately after exiting a call - * to @p chMsgWait(). - * - * @param[in] tp pointer to the thread - * @return The message carried by the sender. - * - * @api - */ -#define chMsgGet(tp) ((tp)->p_msg) - -/** - * @brief Releases the thread waiting on top of the messages queue. - * @pre Invoke this function only after a message has been received - * using @p chMsgWait(). - * - * @param[in] tp pointer to the thread - * @param[in] msg message to be returned to the sender - * - * @sclass - */ -#define chMsgReleaseS(tp, msg) chSchWakeupS(tp, msg) -/** @} */ - -#ifdef __cplusplus -extern "C" { -#endif - msg_t chMsgSend(Thread *tp, msg_t msg); - Thread * chMsgWait(void); - void chMsgRelease(Thread *tp, msg_t msg); -#ifdef __cplusplus -} -#endif - -#endif /* CH_USE_MESSAGES */ - -#endif /* _CHMSG_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/kernel/include/chmtx.h b/firmware/chibios/os/kernel/include/chmtx.h deleted file mode 100644 index b4fcd97473..0000000000 --- a/firmware/chibios/os/kernel/include/chmtx.h +++ /dev/null @@ -1,103 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chmtx.h - * @brief Mutexes macros and structures. - * - * @addtogroup mutexes - * @{ - */ - -#ifndef _CHMTX_H_ -#define _CHMTX_H_ - -#if CH_USE_MUTEXES || defined(__DOXYGEN__) - -/** - * @brief Mutex structure. - */ -typedef struct Mutex { - ThreadsQueue m_queue; /**< @brief Queue of the threads sleeping - on this Mutex. */ - Thread *m_owner; /**< @brief Owner @p Thread pointer or - @p NULL. */ - struct Mutex *m_next; /**< @brief Next @p Mutex into an - owner-list or @p NULL. */ -} Mutex; - -#ifdef __cplusplus -extern "C" { -#endif - void chMtxInit(Mutex *mp); - void chMtxLock(Mutex *mp); - void chMtxLockS(Mutex *mp); - bool_t chMtxTryLock(Mutex *mp); - bool_t chMtxTryLockS(Mutex *mp); - Mutex *chMtxUnlock(void); - Mutex *chMtxUnlockS(void); - void chMtxUnlockAll(void); -#ifdef __cplusplus -} -#endif - -/** - * @brief Data part of a static mutex initializer. - * @details This macro should be used when statically initializing a mutex - * that is part of a bigger structure. - * - * @param[in] name the name of the mutex variable - */ -#define _MUTEX_DATA(name) {_THREADSQUEUE_DATA(name.m_queue), NULL, NULL} - -/** - * @brief Static mutex initializer. - * @details Statically initialized mutexes require no explicit initialization - * using @p chMtxInit(). - * - * @param[in] name the name of the mutex variable - */ -#define MUTEX_DECL(name) Mutex name = _MUTEX_DATA(name) - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Returns @p TRUE if the mutex queue contains at least a waiting - * thread. - * - * @sclass - */ -#define chMtxQueueNotEmptyS(mp) notempty(&(mp)->m_queue) -/** @} */ - -#endif /* CH_USE_MUTEXES */ - -#endif /* _CHMTX_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/kernel/include/chqueues.h b/firmware/chibios/os/kernel/include/chqueues.h deleted file mode 100644 index b7ad17e2be..0000000000 --- a/firmware/chibios/os/kernel/include/chqueues.h +++ /dev/null @@ -1,376 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chqueues.h - * @brief I/O Queues macros and structures. - * - * @addtogroup io_queues - * @{ - */ - -#ifndef _CHQUEUES_H_ -#define _CHQUEUES_H_ - -#if CH_USE_QUEUES || defined(__DOXYGEN__) - -/** - * @name Queue functions returned status value - * @{ - */ -#define Q_OK RDY_OK /**< @brief Operation successful. */ -#define Q_TIMEOUT RDY_TIMEOUT /**< @brief Timeout condition. */ -#define Q_RESET RDY_RESET /**< @brief Queue has been reset. */ -#define Q_EMPTY -3 /**< @brief Queue empty. */ -#define Q_FULL -4 /**< @brief Queue full, */ -/** @} */ - -/** - * @brief Type of a generic I/O queue structure. - */ -typedef struct GenericQueue GenericQueue; - -/** @brief Queue notification callback type.*/ -typedef void (*qnotify_t)(GenericQueue *qp); - -/** - * @brief Generic I/O queue structure. - * @details This structure represents a generic Input or Output asymmetrical - * queue. The queue is asymmetrical because one end is meant to be - * accessed from a thread context, and thus can be blocking, the other - * end is accessible from interrupt handlers or from within a kernel - * lock zone (see I-Locked and S-Locked states in - * @ref system_states) and is non-blocking. - */ -struct GenericQueue { - ThreadsQueue q_waiting; /**< @brief Queue of waiting threads. */ - size_t q_counter; /**< @brief Resources counter. */ - uint8_t *q_buffer; /**< @brief Pointer to the queue buffer.*/ - uint8_t *q_top; /**< @brief Pointer to the first location - after the buffer. */ - uint8_t *q_wrptr; /**< @brief Write pointer. */ - uint8_t *q_rdptr; /**< @brief Read pointer. */ - qnotify_t q_notify; /**< @brief Data notification callback. */ - void *q_link; /**< @brief Application defined field. */ -}; - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Returns the queue's buffer size. - * - * @param[in] qp pointer to a @p GenericQueue structure. - * @return The buffer size. - * - * @iclass - */ -#define chQSizeI(qp) ((size_t)((qp)->q_top - (qp)->q_buffer)) - -/** - * @brief Queue space. - * @details Returns the used space if used on an input queue or the empty - * space if used on an output queue. - * - * @param[in] qp pointer to a @p GenericQueue structure. - * @return The buffer space. - * - * @iclass - */ -#define chQSpaceI(qp) ((qp)->q_counter) - -/** - * @brief Returns the queue application-defined link. - * @note This function can be called in any context. - * - * @param[in] qp pointer to a @p GenericQueue structure. - * @return The application-defined link. - * - * @special - */ -#define chQGetLink(qp) ((qp)->q_link) -/** @} */ - -/** - * @extends GenericQueue - * - * @brief Type of an input queue structure. - * @details This structure represents a generic asymmetrical input queue. - * Writing to the queue is non-blocking and can be performed from - * interrupt handlers or from within a kernel lock zone (see - * I-Locked and S-Locked states in @ref system_states). - * Reading the queue can be a blocking operation and is supposed to - * be performed by a system thread. - */ -typedef GenericQueue InputQueue; - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Returns the filled space into an input queue. - * - * @param[in] iqp pointer to an @p InputQueue structure - * @return The number of full bytes in the queue. - * @retval 0 if the queue is empty. - * - * @iclass - */ -#define chIQGetFullI(iqp) chQSpaceI(iqp) - -/** - * @brief Returns the empty space into an input queue. - * - * @param[in] iqp pointer to an @p InputQueue structure - * @return The number of empty bytes in the queue. - * @retval 0 if the queue is full. - * - * @iclass - */ -#define chIQGetEmptyI(iqp) (chQSizeI(iqp) - chQSpaceI(iqp)) - -/** - * @brief Evaluates to @p TRUE if the specified input queue is empty. - * - * @param[in] iqp pointer to an @p InputQueue structure. - * @return The queue status. - * @retval FALSE if the queue is not empty. - * @retval TRUE if the queue is empty. - * - * @iclass - */ -#define chIQIsEmptyI(iqp) ((bool_t)(chQSpaceI(iqp) <= 0)) - -/** - * @brief Evaluates to @p TRUE if the specified input queue is full. - * - * @param[in] iqp pointer to an @p InputQueue structure. - * @return The queue status. - * @retval FALSE if the queue is not full. - * @retval TRUE if the queue is full. - * - * @iclass - */ -#define chIQIsFullI(iqp) ((bool_t)(((iqp)->q_wrptr == (iqp)->q_rdptr) && \ - ((iqp)->q_counter != 0))) - -/** - * @brief Input queue read. - * @details This function reads a byte value from an input queue. If the queue - * is empty then the calling thread is suspended until a byte arrives - * in the queue. - * - * @param[in] iqp pointer to an @p InputQueue structure - * @return A byte value from the queue. - * @retval Q_RESET if the queue has been reset. - * - * @api - */ -#define chIQGet(iqp) chIQGetTimeout(iqp, TIME_INFINITE) -/** @} */ - -/** - * @brief Data part of a static input queue initializer. - * @details This macro should be used when statically initializing an - * input queue that is part of a bigger structure. - * - * @param[in] name the name of the input queue variable - * @param[in] buffer pointer to the queue buffer area - * @param[in] size size of the queue buffer area - * @param[in] inotify input notification callback pointer - * @param[in] link application defined pointer - */ -#define _INPUTQUEUE_DATA(name, buffer, size, inotify, link) { \ - _THREADSQUEUE_DATA(name), \ - 0, \ - (uint8_t *)(buffer), \ - (uint8_t *)(buffer) + (size), \ - (uint8_t *)(buffer), \ - (uint8_t *)(buffer), \ - (inotify), \ - (link) \ -} - -/** - * @brief Static input queue initializer. - * @details Statically initialized input queues require no explicit - * initialization using @p chIQInit(). - * - * @param[in] name the name of the input queue variable - * @param[in] buffer pointer to the queue buffer area - * @param[in] size size of the queue buffer area - * @param[in] inotify input notification callback pointer - * @param[in] link application defined pointer - */ -#define INPUTQUEUE_DECL(name, buffer, size, inotify, link) \ - InputQueue name = _INPUTQUEUE_DATA(name, buffer, size, inotify, link) - -/** - * @extends GenericQueue - * - * @brief Type of an output queue structure. - * @details This structure represents a generic asymmetrical output queue. - * Reading from the queue is non-blocking and can be performed from - * interrupt handlers or from within a kernel lock zone (see - * I-Locked and S-Locked states in @ref system_states). - * Writing the queue can be a blocking operation and is supposed to - * be performed by a system thread. - */ -typedef GenericQueue OutputQueue; - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Returns the filled space into an output queue. - * - * @param[in] oqp pointer to an @p OutputQueue structure - * @return The number of full bytes in the queue. - * @retval 0 if the queue is empty. - * - * @iclass - */ -#define chOQGetFullI(oqp) (chQSizeI(oqp) - chQSpaceI(oqp)) - -/** - * @brief Returns the empty space into an output queue. - * - * @param[in] oqp pointer to an @p OutputQueue structure - * @return The number of empty bytes in the queue. - * @retval 0 if the queue is full. - * - * @iclass - */ -#define chOQGetEmptyI(oqp) chQSpaceI(oqp) - -/** - * @brief Evaluates to @p TRUE if the specified output queue is empty. - * - * @param[in] oqp pointer to an @p OutputQueue structure. - * @return The queue status. - * @retval FALSE if the queue is not empty. - * @retval TRUE if the queue is empty. - * - * @iclass - */ -#define chOQIsEmptyI(oqp) ((bool_t)(((oqp)->q_wrptr == (oqp)->q_rdptr) && \ - ((oqp)->q_counter != 0))) - -/** - * @brief Evaluates to @p TRUE if the specified output queue is full. - * - * @param[in] oqp pointer to an @p OutputQueue structure. - * @return The queue status. - * @retval FALSE if the queue is not full. - * @retval TRUE if the queue is full. - * - * @iclass - */ -#define chOQIsFullI(oqp) ((bool_t)(chQSpaceI(oqp) <= 0)) - -/** - * @brief Output queue write. - * @details This function writes a byte value to an output queue. If the queue - * is full then the calling thread is suspended until there is space - * in the queue. - * - * @param[in] oqp pointer to an @p OutputQueue structure - * @param[in] b the byte value to be written in the queue - * @return The operation status. - * @retval Q_OK if the operation succeeded. - * @retval Q_RESET if the queue has been reset. - * - * @api - */ -#define chOQPut(oqp, b) chOQPutTimeout(oqp, b, TIME_INFINITE) - /** @} */ - -/** - * @brief Data part of a static output queue initializer. - * @details This macro should be used when statically initializing an - * output queue that is part of a bigger structure. - * - * @param[in] name the name of the output queue variable - * @param[in] buffer pointer to the queue buffer area - * @param[in] size size of the queue buffer area - * @param[in] onotify output notification callback pointer - * @param[in] link application defined pointer - */ -#define _OUTPUTQUEUE_DATA(name, buffer, size, onotify, link) { \ - _THREADSQUEUE_DATA(name), \ - (size), \ - (uint8_t *)(buffer), \ - (uint8_t *)(buffer) + (size), \ - (uint8_t *)(buffer), \ - (uint8_t *)(buffer), \ - (onotify), \ - (link) \ -} - -/** - * @brief Static output queue initializer. - * @details Statically initialized output queues require no explicit - * initialization using @p chOQInit(). - * - * @param[in] name the name of the output queue variable - * @param[in] buffer pointer to the queue buffer area - * @param[in] size size of the queue buffer area - * @param[in] onotify output notification callback pointer - * @param[in] link application defined pointer - */ -#define OUTPUTQUEUE_DECL(name, buffer, size, onotify, link) \ - OutputQueue name = _OUTPUTQUEUE_DATA(name, buffer, size, onotify, link) - -#ifdef __cplusplus -extern "C" { -#endif - void chIQInit(InputQueue *iqp, uint8_t *bp, size_t size, qnotify_t infy, - void *link); - void chIQResetI(InputQueue *iqp); - msg_t chIQPutI(InputQueue *iqp, uint8_t b); - msg_t chIQGetTimeout(InputQueue *iqp, systime_t time); - size_t chIQReadTimeout(InputQueue *iqp, uint8_t *bp, - size_t n, systime_t time); - - void chOQInit(OutputQueue *oqp, uint8_t *bp, size_t size, qnotify_t onfy, - void *link); - void chOQResetI(OutputQueue *oqp); - msg_t chOQPutTimeout(OutputQueue *oqp, uint8_t b, systime_t time); - msg_t chOQGetI(OutputQueue *oqp); - size_t chOQWriteTimeout(OutputQueue *oqp, const uint8_t *bp, - size_t n, systime_t time); -#ifdef __cplusplus -} -#endif -#endif /* CH_USE_QUEUES */ - -#endif /* _CHQUEUES_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/kernel/include/chregistry.h b/firmware/chibios/os/kernel/include/chregistry.h deleted file mode 100644 index 0bd2fa760d..0000000000 --- a/firmware/chibios/os/kernel/include/chregistry.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chregistry.h - * @brief Threads registry macros and structures. - * - * @addtogroup registry - * @{ - */ - -#ifndef _CHREGISTRY_H_ -#define _CHREGISTRY_H_ - -#if CH_USE_REGISTRY || defined(__DOXYGEN__) - -/** - * @brief ChibiOS/RT memory signature record. - */ -typedef struct { - char ch_identifier[4]; /**< @brief Always set to "main". */ - uint8_t ch_zero; /**< @brief Must be zero. */ - uint8_t ch_size; /**< @brief Size of this structure. */ - uint16_t ch_version; /**< @brief Encoded ChibiOS/RT version. */ - uint8_t ch_ptrsize; /**< @brief Size of a pointer. */ - uint8_t ch_timesize; /**< @brief Size of a @p systime_t. */ - uint8_t ch_threadsize; /**< @brief Size of a @p Thread struct. */ - uint8_t cf_off_prio; /**< @brief Offset of @p p_prio field. */ - uint8_t cf_off_ctx; /**< @brief Offset of @p p_ctx field. */ - uint8_t cf_off_newer; /**< @brief Offset of @p p_newer field. */ - uint8_t cf_off_older; /**< @brief Offset of @p p_older field. */ - uint8_t cf_off_name; /**< @brief Offset of @p p_name field. */ - uint8_t cf_off_stklimit; /**< @brief Offset of @p p_stklimit - field. */ - uint8_t cf_off_state; /**< @brief Offset of @p p_state field. */ - uint8_t cf_off_flags; /**< @brief Offset of @p p_flags field. */ - uint8_t cf_off_refs; /**< @brief Offset of @p p_refs field. */ - uint8_t cf_off_preempt; /**< @brief Offset of @p p_preempt - field. */ - uint8_t cf_off_time; /**< @brief Offset of @p p_time field. */ -} chdebug_t; - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Sets the current thread name. - * @pre This function only stores the pointer to the name if the option - * @p CH_USE_REGISTRY is enabled else no action is performed. - * - * @param[in] p thread name as a zero terminated string - * - * @api - */ -#define chRegSetThreadName(p) (currp->p_name = (p)) - -/** - * @brief Returns the name of the specified thread. - * @pre This function only returns the pointer to the name if the option - * @p CH_USE_REGISTRY is enabled else @p NULL is returned. - * - * @param[in] tp pointer to the thread - * - * @return Thread name as a zero terminated string. - * @retval NULL if the thread name has not been set. - */ -#define chRegGetThreadName(tp) ((tp)->p_name) -/** @} */ -#else /* !CH_USE_REGISTRY */ -#define chRegSetThreadName(p) -#define chRegGetThreadName(tp) NULL -#endif /* !CH_USE_REGISTRY */ - -#if CH_USE_REGISTRY || defined(__DOXYGEN__) -/** - * @brief Removes a thread from the registry list. - * @note This macro is not meant for use in application code. - * - * @param[in] tp thread to remove from the registry - */ -#define REG_REMOVE(tp) { \ - (tp)->p_older->p_newer = (tp)->p_newer; \ - (tp)->p_newer->p_older = (tp)->p_older; \ -} - -/** - * @brief Adds a thread to the registry list. - * @note This macro is not meant for use in application code. - * - * @param[in] tp thread to add to the registry - */ -#define REG_INSERT(tp) { \ - (tp)->p_newer = (Thread *)&rlist; \ - (tp)->p_older = rlist.r_older; \ - (tp)->p_older->p_newer = rlist.r_older = (tp); \ -} - -#ifdef __cplusplus -extern "C" { -#endif - extern ROMCONST chdebug_t ch_debug; - Thread *chRegFirstThread(void); - Thread *chRegNextThread(Thread *tp); -#ifdef __cplusplus -} -#endif - -#endif /* CH_USE_REGISTRY */ - -#endif /* _CHREGISTRY_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/kernel/include/chschd.h b/firmware/chibios/os/kernel/include/chschd.h deleted file mode 100644 index 89a00f9eed..0000000000 --- a/firmware/chibios/os/kernel/include/chschd.h +++ /dev/null @@ -1,244 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chschd.h - * @brief Scheduler macros and structures. - * - * @addtogroup scheduler - * @{ - */ - -#ifndef _CHSCHD_H_ -#define _CHSCHD_H_ - -/** - * @name Wakeup status codes - * @{ - */ -#define RDY_OK 0 /**< @brief Normal wakeup message. */ -#define RDY_TIMEOUT -1 /**< @brief Wakeup caused by a timeout - condition. */ -#define RDY_RESET -2 /**< @brief Wakeup caused by a reset - condition. */ -/** @} */ - -/** - * @name Priority constants - * @{ - */ -#define NOPRIO 0 /**< @brief Ready list header priority. */ -#define IDLEPRIO 1 /**< @brief Idle thread priority. */ -#define LOWPRIO 2 /**< @brief Lowest user priority. */ -#define NORMALPRIO 64 /**< @brief Normal user priority. */ -#define HIGHPRIO 127 /**< @brief Highest user priority. */ -#define ABSPRIO 255 /**< @brief Greatest possible priority. */ -/** @} */ - -/** - * @name Special time constants - * @{ - */ -/** - * @brief Zero time specification for some functions with a timeout - * specification. - * @note Not all functions accept @p TIME_IMMEDIATE as timeout parameter, - * see the specific function documentation. - */ -#define TIME_IMMEDIATE ((systime_t)0) - -/** - * @brief Infinite time specification for all functions with a timeout - * specification. - */ -#define TIME_INFINITE ((systime_t)-1) -/** @} */ - -/** - * @brief Returns the priority of the first thread on the given ready list. - * - * @notapi - */ -#define firstprio(rlp) ((rlp)->p_next->p_prio) - -/** - * @extends ThreadsQueue - * - * @brief Ready list header. - */ -#if !defined(PORT_OPTIMIZED_READYLIST_STRUCT) || defined(__DOXYGEN__) -typedef struct { - ThreadsQueue r_queue; /**< @brief Threads queue. */ - tprio_t r_prio; /**< @brief This field must be - initialized to zero. */ - struct context r_ctx; /**< @brief Not used, present because - offsets. */ -#if CH_USE_REGISTRY || defined(__DOXYGEN__) - Thread *r_newer; /**< @brief Newer registry element. */ - Thread *r_older; /**< @brief Older registry element. */ -#endif - /* End of the fields shared with the Thread structure.*/ - Thread *r_current; /**< @brief The currently running - thread. */ -} ReadyList; -#endif /* !defined(PORT_OPTIMIZED_READYLIST_STRUCT) */ - -#if !defined(PORT_OPTIMIZED_RLIST_EXT) && !defined(__DOXYGEN__) -extern ReadyList rlist; -#endif /* !defined(PORT_OPTIMIZED_RLIST_EXT) */ - -/** - * @brief Current thread pointer access macro. - * @note This macro is not meant to be used in the application code but - * only from within the kernel, use the @p chThdSelf() API instead. - * @note It is forbidden to use this macro in order to change the pointer - * (currp = something), use @p setcurrp() instead. - */ -#if !defined(PORT_OPTIMIZED_CURRP) || defined(__DOXYGEN__) -#define currp rlist.r_current -#endif /* !defined(PORT_OPTIMIZED_CURRP) */ - -/** - * @brief Current thread pointer change macro. - * @note This macro is not meant to be used in the application code but - * only from within the kernel. - * - * @notapi - */ -#if !defined(PORT_OPTIMIZED_SETCURRP) || defined(__DOXYGEN__) -#define setcurrp(tp) (currp = (tp)) -#endif /* !defined(PORT_OPTIMIZED_SETCURRP) */ - -/* - * Scheduler APIs. - */ -#ifdef __cplusplus -extern "C" { -#endif - void _scheduler_init(void); -#if !defined(PORT_OPTIMIZED_READYI) - Thread *chSchReadyI(Thread *tp); -#endif -#if !defined(PORT_OPTIMIZED_GOSLEEPS) - void chSchGoSleepS(tstate_t newstate); -#endif -#if !defined(PORT_OPTIMIZED_GOSLEEPTIMEOUTS) - msg_t chSchGoSleepTimeoutS(tstate_t newstate, systime_t time); -#endif -#if !defined(PORT_OPTIMIZED_WAKEUPS) - void chSchWakeupS(Thread *tp, msg_t msg); -#endif -#if !defined(PORT_OPTIMIZED_RESCHEDULES) - void chSchRescheduleS(void); -#endif -#if !defined(PORT_OPTIMIZED_ISPREEMPTIONREQUIRED) - bool_t chSchIsPreemptionRequired(void); -#endif -#if !defined(PORT_OPTIMIZED_DORESCHEDULEBEHIND) || defined(__DOXYGEN__) - void chSchDoRescheduleBehind(void); -#endif -#if !defined(PORT_OPTIMIZED_DORESCHEDULEAHEAD) || defined(__DOXYGEN__) - void chSchDoRescheduleAhead(void); -#endif -#if !defined(PORT_OPTIMIZED_DORESCHEDULE) - void chSchDoReschedule(void); -#endif -#ifdef __cplusplus -} -#endif - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Determines if the current thread must reschedule. - * @details This function returns @p TRUE if there is a ready thread with - * higher priority. - * - * @iclass - */ -#if !defined(PORT_OPTIMIZED_ISRESCHREQUIREDI) || defined(__DOXYGEN__) -#define chSchIsRescRequiredI() (firstprio(&rlist.r_queue) > currp->p_prio) -#endif /* !defined(PORT_OPTIMIZED_ISRESCHREQUIREDI) */ - -/** - * @brief Determines if yielding is possible. - * @details This function returns @p TRUE if there is a ready thread with - * equal or higher priority. - * - * @sclass - */ -#if !defined(PORT_OPTIMIZED_CANYIELDS) || defined(__DOXYGEN__) -#define chSchCanYieldS() (firstprio(&rlist.r_queue) >= currp->p_prio) -#endif /* !defined(PORT_OPTIMIZED_CANYIELDS) */ - -/** - * @brief Yields the time slot. - * @details Yields the CPU control to the next thread in the ready list with - * equal or higher priority, if any. - * - * @sclass - */ -#if !defined(PORT_OPTIMIZED_DOYIELDS) || defined(__DOXYGEN__) -#define chSchDoYieldS() { \ - if (chSchCanYieldS()) \ - chSchDoRescheduleBehind(); \ -} -#endif /* !defined(PORT_OPTIMIZED_DOYIELDS) */ - -/** - * @brief Inline-able preemption code. - * @details This is the common preemption code, this function must be invoked - * exclusively from the port layer. - * - * @special - */ -#if (CH_TIME_QUANTUM > 0) || defined(__DOXYGEN__) -#define chSchPreemption() { \ - tprio_t p1 = firstprio(&rlist.r_queue); \ - tprio_t p2 = currp->p_prio; \ - if (currp->p_preempt) { \ - if (p1 > p2) \ - chSchDoRescheduleAhead(); \ - } \ - else { \ - if (p1 >= p2) \ - chSchDoRescheduleBehind(); \ - } \ -} -#else /* CH_TIME_QUANTUM == 0 */ -#define chSchPreemption() { \ - if (p1 >= p2) \ - chSchDoRescheduleAhead(); \ -} -#endif /* CH_TIME_QUANTUM == 0 */ -/** @} */ - -#endif /* _CHSCHD_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/kernel/include/chsem.h b/firmware/chibios/os/kernel/include/chsem.h deleted file mode 100644 index d8de2c8cd8..0000000000 --- a/firmware/chibios/os/kernel/include/chsem.h +++ /dev/null @@ -1,125 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chsem.h - * @brief Semaphores macros and structures. - * - * @addtogroup semaphores - * @{ - */ - -#ifndef _CHSEM_H_ -#define _CHSEM_H_ - -#if CH_USE_SEMAPHORES || defined(__DOXYGEN__) - -/** - * @brief Semaphore structure. - */ -typedef struct Semaphore { - ThreadsQueue s_queue; /**< @brief Queue of the threads sleeping - on this semaphore. */ - cnt_t s_cnt; /**< @brief The semaphore counter. */ -} Semaphore; - -#ifdef __cplusplus -extern "C" { -#endif - void chSemInit(Semaphore *sp, cnt_t n); - void chSemReset(Semaphore *sp, cnt_t n); - void chSemResetI(Semaphore *sp, cnt_t n); - msg_t chSemWait(Semaphore *sp); - msg_t chSemWaitS(Semaphore *sp); - msg_t chSemWaitTimeout(Semaphore *sp, systime_t time); - msg_t chSemWaitTimeoutS(Semaphore *sp, systime_t time); - void chSemSignal(Semaphore *sp); - void chSemSignalI(Semaphore *sp); - void chSemAddCounterI(Semaphore *sp, cnt_t n); -#if CH_USE_SEMSW - msg_t chSemSignalWait(Semaphore *sps, Semaphore *spw); -#endif -#ifdef __cplusplus -} -#endif - -/** - * @brief Data part of a static semaphore initializer. - * @details This macro should be used when statically initializing a semaphore - * that is part of a bigger structure. - * - * @param[in] name the name of the semaphore variable - * @param[in] n the counter initial value, this value must be - * non-negative - */ -#define _SEMAPHORE_DATA(name, n) {_THREADSQUEUE_DATA(name.s_queue), n} - -/** - * @brief Static semaphore initializer. - * @details Statically initialized semaphores require no explicit - * initialization using @p chSemInit(). - * - * @param[in] name the name of the semaphore variable - * @param[in] n the counter initial value, this value must be - * non-negative - */ -#define SEMAPHORE_DECL(name, n) Semaphore name = _SEMAPHORE_DATA(name, n) - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Decreases the semaphore counter. - * @details This macro can be used when the counter is known to be positive. - * - * @iclass - */ -#define chSemFastWaitI(sp) ((sp)->s_cnt--) - -/** - * @brief Increases the semaphore counter. - * @details This macro can be used when the counter is known to be not - * negative. - * - * @iclass - */ -#define chSemFastSignalI(sp) ((sp)->s_cnt++) - -/** - * @brief Returns the semaphore counter current value. - * - * @iclass - */ -#define chSemGetCounterI(sp) ((sp)->s_cnt) -/** @} */ - -#endif /* CH_USE_SEMAPHORES */ - -#endif /* _CHSEM_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/kernel/include/chstreams.h b/firmware/chibios/os/kernel/include/chstreams.h deleted file mode 100644 index 83364f431f..0000000000 --- a/firmware/chibios/os/kernel/include/chstreams.h +++ /dev/null @@ -1,154 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chstreams.h - * @brief Data streams. - * @details This header defines abstract interfaces useful to access generic - * data streams in a standardized way. - * - * @addtogroup data_streams - * @details This module define an abstract interface for generic data streams. - * Note that no code is present, just abstract interfaces-like - * structures, you should look at the system as to a set of - * abstract C++ classes (even if written in C). This system - * has then advantage to make the access to data streams - * independent from the implementation logic.
- * The stream interface can be used as base class for high level - * object types such as files, sockets, serial ports, pipes etc. - * @{ - */ - -#ifndef _CHSTREAMS_H_ -#define _CHSTREAMS_H_ - -/** - * @brief BaseSequentialStream specific methods. - */ -#define _base_sequential_stream_methods \ - /* Stream write buffer method.*/ \ - size_t (*write)(void *instance, const uint8_t *bp, size_t n); \ - /* Stream read buffer method.*/ \ - size_t (*read)(void *instance, uint8_t *bp, size_t n); \ - /* Channel put method, blocking.*/ \ - msg_t (*put)(void *instance, uint8_t b); \ - /* Channel get method, blocking.*/ \ - msg_t (*get)(void *instance); \ - -/** - * @brief @p BaseSequentialStream specific data. - * @note It is empty because @p BaseSequentialStream is only an interface - * without implementation. - */ -#define _base_sequential_stream_data - -/** - * @brief @p BaseSequentialStream virtual methods table. - */ -struct BaseSequentialStreamVMT { - _base_sequential_stream_methods -}; - -/** - * @brief Base stream class. - * @details This class represents a generic blocking unbuffered sequential - * data stream. - */ -typedef struct { - /** @brief Virtual Methods Table.*/ - const struct BaseSequentialStreamVMT *vmt; - _base_sequential_stream_data -} BaseSequentialStream; - -/** - * @name Macro Functions (BaseSequentialStream) - * @{ - */ -/** - * @brief Sequential Stream write. - * @details The function writes data from a buffer to a stream. - * - * @param[in] ip pointer to a @p BaseSequentialStream or derived class - * @param[in] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred - * @return The number of bytes transferred. The return value can - * be less than the specified number of bytes if an - * end-of-file condition has been met. - * - * @api - */ -#define chSequentialStreamWrite(ip, bp, n) ((ip)->vmt->write(ip, bp, n)) - -/** - * @brief Sequential Stream read. - * @details The function reads data from a stream into a buffer. - * - * @param[in] ip pointer to a @p BaseSequentialStream or derived class - * @param[out] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred - * @return The number of bytes transferred. The return value can - * be less than the specified number of bytes if an - * end-of-file condition has been met. - * - * @api - */ -#define chSequentialStreamRead(ip, bp, n) ((ip)->vmt->read(ip, bp, n)) - -/** - * @brief Sequential Stream blocking byte write. - * @details This function writes a byte value to a channel. If the channel - * is not ready to accept data then the calling thread is suspended. - * - * @param[in] ip pointer to a @p BaseSequentialStream or derived class - * @param[in] b the byte value to be written to the channel - * - * @return The operation status. - * @retval Q_OK if the operation succeeded. - * @retval Q_RESET if an end-of-file condition has been met. - * - * @api - */ -#define chSequentialStreamPut(ip, b) ((ip)->vmt->put(ip, b)) - -/** - * @brief Sequential Stream blocking byte read. - * @details This function reads a byte value from a channel. If the data - * is not available then the calling thread is suspended. - * - * @param[in] ip pointer to a @p BaseSequentialStream or derived class - * - * @return A byte value from the queue. - * @retval Q_RESET if an end-of-file condition has been met. - * - * @api - */ -#define chSequentialStreamGet(ip) ((ip)->vmt->get(ip)) -/** @} */ - -#endif /* _CHSTREAMS_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/kernel/include/chsys.h b/firmware/chibios/os/kernel/include/chsys.h deleted file mode 100644 index e72a9a3ebe..0000000000 --- a/firmware/chibios/os/kernel/include/chsys.h +++ /dev/null @@ -1,254 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chsys.h - * @brief System related macros and structures. - * - * @addtogroup system - * @{ - */ - -#ifndef _CHSYS_H_ -#define _CHSYS_H_ - -/** - * @name Macro Functions - * @{ - */ -#if !CH_NO_IDLE_THREAD || defined(__DOXYGEN__) -/** - * @brief Returns a pointer to the idle thread. - * @pre In order to use this function the option @p CH_NO_IDLE_THREAD - * must be disabled. - * @note The reference counter of the idle thread is not incremented but - * it is not strictly required being the idle thread a static - * object. - * - * @return Pointer to the idle thread. - * - * @api - */ -#define chSysGetIdleThread() (rlist.r_queue.p_prev) -#endif - -/** - * @brief Halts the system. - * @details This function is invoked by the operating system when an - * unrecoverable error is detected, for example because a programming - * error in the application code that triggers an assertion while - * in debug mode. - * @note Can be invoked from any system state. - * - * @special - */ -#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) -#define chSysHalt() port_halt() -#else -#define chSysHalt() { \ - SYSTEM_HALT_HOOK(); \ - port_halt(); \ -} -#endif - -/** - * @brief Performs a context switch. - * @note Not a user function, it is meant to be invoked by the scheduler - * itself or from within the port layer. - * - * @param[in] ntp the thread to be switched in - * @param[in] otp the thread to be switched out - * - * @special - */ -#define chSysSwitch(ntp, otp) { \ - dbg_trace(otp); \ - THREAD_CONTEXT_SWITCH_HOOK(ntp, otp); \ - port_switch(ntp, otp); \ -} - -/** - * @brief Raises the system interrupt priority mask to the maximum level. - * @details All the maskable interrupt sources are disabled regardless their - * hardware priority. - * @note Do not invoke this API from within a kernel lock. - * - * @special - */ -#define chSysDisable() { \ - port_disable(); \ - dbg_check_disable(); \ -} - -/** - * @brief Raises the system interrupt priority mask to system level. - * @details The interrupt sources that should not be able to preempt the kernel - * are disabled, interrupt sources with higher priority are still - * enabled. - * @note Do not invoke this API from within a kernel lock. - * @note This API is no replacement for @p chSysLock(), the @p chSysLock() - * could do more than just disable the interrupts. - * - * @special - */ -#define chSysSuspend() { \ - port_suspend(); \ - dbg_check_suspend(); \ -} - -/** - * @brief Lowers the system interrupt priority mask to user level. - * @details All the interrupt sources are enabled. - * @note Do not invoke this API from within a kernel lock. - * @note This API is no replacement for @p chSysUnlock(), the - * @p chSysUnlock() could do more than just enable the interrupts. - * - * @special - */ -#define chSysEnable() { \ - dbg_check_enable(); \ - port_enable(); \ -} - -/** - * @brief Enters the kernel lock mode. - * - * @special - */ -#define chSysLock() { \ - port_lock(); \ - dbg_check_lock(); \ -} - -/** - * @brief Leaves the kernel lock mode. - * - * @special - */ -#define chSysUnlock() { \ - dbg_check_unlock(); \ - port_unlock(); \ -} - -/** - * @brief Enters the kernel lock mode from within an interrupt handler. - * @note This API may do nothing on some architectures, it is required - * because on ports that support preemptable interrupt handlers - * it is required to raise the interrupt mask to the same level of - * the system mutual exclusion zone.
- * It is good practice to invoke this API before invoking any I-class - * syscall from an interrupt handler. - * @note This API must be invoked exclusively from interrupt handlers. - * - * @special - */ -#define chSysLockFromIsr() { \ - port_lock_from_isr(); \ - dbg_check_lock_from_isr(); \ -} - -/** - * @brief Leaves the kernel lock mode from within an interrupt handler. - * - * @note This API may do nothing on some architectures, it is required - * because on ports that support preemptable interrupt handlers - * it is required to raise the interrupt mask to the same level of - * the system mutual exclusion zone.
- * It is good practice to invoke this API after invoking any I-class - * syscall from an interrupt handler. - * @note This API must be invoked exclusively from interrupt handlers. - * - * @special - */ -#define chSysUnlockFromIsr() { \ - dbg_check_unlock_from_isr(); \ - port_unlock_from_isr(); \ -} -/** @} */ - -/** - * @name ISRs abstraction macros - */ -/** - * @brief IRQ handler enter code. - * @note Usually IRQ handlers functions are also declared naked. - * @note On some architectures this macro can be empty. - * - * @special - */ -#define CH_IRQ_PROLOGUE() \ - PORT_IRQ_PROLOGUE(); \ - dbg_check_enter_isr(); - -/** - * @brief IRQ handler exit code. - * @note Usually IRQ handlers function are also declared naked. - * @note This macro usually performs the final reschedule by using - * @p chSchIsPreemptionRequired() and @p chSchDoReschedule(). - * - * @special - */ -#define CH_IRQ_EPILOGUE() \ - dbg_check_leave_isr(); \ - PORT_IRQ_EPILOGUE(); - -/** - * @brief Standard normal IRQ handler declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - * - * @special - */ -#define CH_IRQ_HANDLER(id) PORT_IRQ_HANDLER(id) -/** @} */ - -/** - * @name Fast ISRs abstraction macros - */ -/** - * @brief Standard fast IRQ handler declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - * @note Not all architectures support fast interrupts. - * - * @special - */ -#define CH_FAST_IRQ_HANDLER(id) PORT_FAST_IRQ_HANDLER(id) -/** @} */ - -#ifdef __cplusplus -extern "C" { -#endif - void chSysInit(void); - void chSysTimerHandlerI(void); -#ifdef __cplusplus -} -#endif - -#endif /* _CHSYS_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/kernel/include/chthreads.h b/firmware/chibios/os/kernel/include/chthreads.h deleted file mode 100644 index cc942bb53e..0000000000 --- a/firmware/chibios/os/kernel/include/chthreads.h +++ /dev/null @@ -1,387 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chthreads.h - * @brief Threads macros and structures. - * - * @addtogroup threads - * @{ - */ - -#ifndef _CHTHREADS_H_ -#define _CHTHREADS_H_ - -/** - * @name Thread states - * @{ - */ -#define THD_STATE_READY 0 /**< @brief Waiting on the ready list. */ -#define THD_STATE_CURRENT 1 /**< @brief Currently running. */ -#define THD_STATE_SUSPENDED 2 /**< @brief Created in suspended state. */ -#define THD_STATE_WTSEM 3 /**< @brief Waiting on a semaphore. */ -#define THD_STATE_WTMTX 4 /**< @brief Waiting on a mutex. */ -#define THD_STATE_WTCOND 5 /**< @brief Waiting on a condition - variable. */ -#define THD_STATE_SLEEPING 6 /**< @brief Waiting in @p chThdSleep() - or @p chThdSleepUntil(). */ -#define THD_STATE_WTEXIT 7 /**< @brief Waiting in @p chThdWait(). */ -#define THD_STATE_WTOREVT 8 /**< @brief Waiting for an event. */ -#define THD_STATE_WTANDEVT 9 /**< @brief Waiting for several events. */ -#define THD_STATE_SNDMSGQ 10 /**< @brief Sending a message, in queue.*/ -#define THD_STATE_SNDMSG 11 /**< @brief Sent a message, waiting - answer. */ -#define THD_STATE_WTMSG 12 /**< @brief Waiting for a message. */ -#define THD_STATE_WTQUEUE 13 /**< @brief Waiting on an I/O queue. */ -#define THD_STATE_FINAL 14 /**< @brief Thread terminated. */ - -/** - * @brief Thread states as array of strings. - * @details Each element in an array initialized with this macro can be - * indexed using the numeric thread state values. - */ -#define THD_STATE_NAMES \ - "READY", "CURRENT", "SUSPENDED", "WTSEM", "WTMTX", "WTCOND", "SLEEPING", \ - "WTEXIT", "WTOREVT", "WTANDEVT", "SNDMSGQ", "SNDMSG", "WTMSG", "WTQUEUE", \ - "FINAL" -/** @} */ - -/** - * @name Thread flags and attributes - * @{ - */ -#define THD_MEM_MODE_MASK 3 /**< @brief Thread memory mode mask. */ -#define THD_MEM_MODE_STATIC 0 /**< @brief Static thread. */ -#define THD_MEM_MODE_HEAP 1 /**< @brief Thread allocated from a - Memory Heap. */ -#define THD_MEM_MODE_MEMPOOL 2 /**< @brief Thread allocated from a - Memory Pool. */ -#define THD_TERMINATE 4 /**< @brief Termination requested flag. */ -/** @} */ - -/** - * @extends ThreadsQueue - * - * @brief Structure representing a thread. - * @note Not all the listed fields are always needed, by switching off some - * not needed ChibiOS/RT subsystems it is possible to save RAM space - * by shrinking the @p Thread structure. - */ -struct Thread { - Thread *p_next; /**< @brief Next in the list/queue. */ - /* End of the fields shared with the ThreadsList structure. */ - Thread *p_prev; /**< @brief Previous in the queue. */ - /* End of the fields shared with the ThreadsQueue structure. */ - tprio_t p_prio; /**< @brief Thread priority. */ - struct context p_ctx; /**< @brief Processor context. */ -#if CH_USE_REGISTRY || defined(__DOXYGEN__) - Thread *p_newer; /**< @brief Newer registry element. */ - Thread *p_older; /**< @brief Older registry element. */ -#endif - /* End of the fields shared with the ReadyList structure. */ -#if CH_USE_REGISTRY || defined(__DOXYGEN__) - /** - * @brief Thread name or @p NULL. - */ - const char *p_name; -#endif -#if CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__) - /** - * @brief Thread stack boundary. - */ - stkalign_t *p_stklimit; -#endif - /** - * @brief Current thread state. - */ - tstate_t p_state; - /** - * @brief Various thread flags. - */ - tmode_t p_flags; -#if CH_USE_DYNAMIC || defined(__DOXYGEN__) - /** - * @brief References to this thread. - */ - trefs_t p_refs; -#endif - /** - * @brief Number of ticks remaining to this thread. - */ -#if (CH_TIME_QUANTUM > 0) || defined(__DOXYGEN__) - tslices_t p_preempt; -#endif -#if CH_DBG_THREADS_PROFILING || defined(__DOXYGEN__) - /** - * @brief Thread consumed time in ticks. - * @note This field can overflow. - */ - volatile systime_t p_time; -#endif - /** - * @brief State-specific fields. - * @note All the fields declared in this union are only valid in the - * specified state or condition and are thus volatile. - */ - union { - /** - * @brief Thread wakeup code. - * @note This field contains the low level message sent to the thread - * by the waking thread or interrupt handler. The value is valid - * after exiting the @p chSchWakeupS() function. - */ - msg_t rdymsg; - /** - * @brief Thread exit code. - * @note The thread termination code is stored in this field in order - * to be retrieved by the thread performing a @p chThdWait() on - * this thread. - */ - msg_t exitcode; - /** - * @brief Pointer to a generic "wait" object. - * @note This field is used to get a generic pointer to a synchronization - * object and is valid when the thread is in one of the wait - * states. - */ - void *wtobjp; -#if CH_USE_EVENTS || defined(__DOXYGEN__) - /** - * @brief Enabled events mask. - * @note This field is only valid while the thread is in the - * @p THD_STATE_WTOREVT or @p THD_STATE_WTANDEVT states. - */ - eventmask_t ewmask; -#endif - } p_u; -#if CH_USE_WAITEXIT || defined(__DOXYGEN__) - /** - * @brief Termination waiting list. - */ - ThreadsList p_waiting; -#endif -#if CH_USE_MESSAGES || defined(__DOXYGEN__) - /** - * @brief Messages queue. - */ - ThreadsQueue p_msgqueue; - /** - * @brief Thread message. - */ - msg_t p_msg; -#endif -#if CH_USE_EVENTS || defined(__DOXYGEN__) - /** - * @brief Pending events mask. - */ - eventmask_t p_epending; -#endif -#if CH_USE_MUTEXES || defined(__DOXYGEN__) - /** - * @brief List of the mutexes owned by this thread. - * @note The list is terminated by a @p NULL in this field. - */ - Mutex *p_mtxlist; - /** - * @brief Thread's own, non-inherited, priority. - */ - tprio_t p_realprio; -#endif -#if (CH_USE_DYNAMIC && CH_USE_MEMPOOLS) || defined(__DOXYGEN__) - /** - * @brief Memory Pool where the thread workspace is returned. - */ - void *p_mpool; -#endif -#if defined(THREAD_EXT_FIELDS) - /* Extra fields defined in chconf.h.*/ - THREAD_EXT_FIELDS -#endif -}; - -/** - * @brief Thread function. - */ -typedef msg_t (*tfunc_t)(void *); - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Returns a pointer to the current @p Thread. - * @note Can be invoked in any context. - * - * @special - */ -#define chThdSelf() currp - -/** - * @brief Returns the current thread priority. - * @note Can be invoked in any context. - * - * @special - */ -#define chThdGetPriority() (currp->p_prio) - -/** - * @brief Returns the number of ticks consumed by the specified thread. - * @note This function is only available when the - * @p CH_DBG_THREADS_PROFILING configuration option is enabled. - * @note Can be invoked in any context. - * - * @param[in] tp pointer to the thread - * - * @special - */ -#define chThdGetTicks(tp) ((tp)->p_time) - -/** - * @brief Returns the pointer to the @p Thread local storage area, if any. - * @note Can be invoked in any context. - * - * @special - */ -#define chThdLS() (void *)(currp + 1) - -/** - * @brief Verifies if the specified thread is in the @p THD_STATE_FINAL state. - * @note Can be invoked in any context. - * - * @param[in] tp pointer to the thread - * @retval TRUE thread terminated. - * @retval FALSE thread not terminated. - * - * @special - */ -#define chThdTerminated(tp) ((tp)->p_state == THD_STATE_FINAL) - -/** - * @brief Verifies if the current thread has a termination request pending. - * @note Can be invoked in any context. - * - * @retval 0 termination request not pending. - * @retval !0 termination request pending. - * - * @special - */ -#define chThdShouldTerminate() (currp->p_flags & THD_TERMINATE) - -/** - * @brief Resumes a thread created with @p chThdCreateI(). - * - * @param[in] tp pointer to the thread - * - * @iclass - */ -#define chThdResumeI(tp) chSchReadyI(tp) - -/** - * @brief Suspends the invoking thread for the specified time. - * - * @param[in] time the delay in system ticks, the special values are - * handled as follow: - * - @a TIME_INFINITE the thread enters an infinite sleep - * state. - * - @a TIME_IMMEDIATE this value is not allowed. - * . - * - * @sclass - */ -#define chThdSleepS(time) chSchGoSleepTimeoutS(THD_STATE_SLEEPING, time) - -/** - * @brief Delays the invoking thread for the specified number of seconds. - * @note The specified time is rounded up to a value allowed by the real - * system tick clock. - * @note The maximum specifiable value is implementation dependent. - * - * @param[in] sec time in seconds, must be different from zero - * - * @api - */ -#define chThdSleepSeconds(sec) chThdSleep(S2ST(sec)) - -/** - * @brief Delays the invoking thread for the specified number of - * milliseconds. - * @note The specified time is rounded up to a value allowed by the real - * system tick clock. - * @note The maximum specifiable value is implementation dependent. - * - * @param[in] msec time in milliseconds, must be different from zero - * - * @api - */ -#define chThdSleepMilliseconds(msec) chThdSleep(MS2ST(msec)) - -/** - * @brief Delays the invoking thread for the specified number of - * microseconds. - * @note The specified time is rounded up to a value allowed by the real - * system tick clock. - * @note The maximum specifiable value is implementation dependent. - * - * @param[in] usec time in microseconds, must be different from zero - * - * @api - */ -#define chThdSleepMicroseconds(usec) chThdSleep(US2ST(usec)) -/** @} */ - -/* - * Threads APIs. - */ -#ifdef __cplusplus -extern "C" { -#endif - Thread *_thread_init(Thread *tp, tprio_t prio); -#if CH_DBG_FILL_THREADS - void _thread_memfill(uint8_t *startp, uint8_t *endp, uint8_t v); -#endif - Thread *chThdCreateI(void *wsp, size_t size, - tprio_t prio, tfunc_t pf, void *arg); - Thread *chThdCreateStatic(void *wsp, size_t size, - tprio_t prio, tfunc_t pf, void *arg); - tprio_t chThdSetPriority(tprio_t newprio); - Thread *chThdResume(Thread *tp); - void chThdTerminate(Thread *tp); - void chThdSleep(systime_t time); - void chThdSleepUntil(systime_t time); - void chThdYield(void); - void chThdExit(msg_t msg); - void chThdExitS(msg_t msg); -#if CH_USE_WAITEXIT - msg_t chThdWait(Thread *tp); -#endif -#ifdef __cplusplus -} -#endif - -#endif /* _CHTHREADS_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/kernel/include/chvt.h b/firmware/chibios/os/kernel/include/chvt.h deleted file mode 100644 index 506cd45b60..0000000000 --- a/firmware/chibios/os/kernel/include/chvt.h +++ /dev/null @@ -1,264 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chvt.h - * @brief Time macros and structures. - * - * @addtogroup time - * @{ - */ - -#ifndef _CHVT_H_ -#define _CHVT_H_ - -/** - * @name Time conversion utilities - * @{ - */ -/** - * @brief Seconds to system ticks. - * @details Converts from seconds to system ticks number. - * @note The result is rounded upward to the next tick boundary. - * - * @param[in] sec number of seconds - * @return The number of ticks. - * - * @api - */ -#define S2ST(sec) \ - ((systime_t)((sec) * CH_FREQUENCY)) - -/** - * @brief Milliseconds to system ticks. - * @details Converts from milliseconds to system ticks number. - * @note The result is rounded upward to the next tick boundary. - * - * WARNING! this macro does evil things in case of zero parameter! - * - * @param[in] msec number of milliseconds - * @return The number of ticks. - * - * @api - */ -#define MS2ST(msec) \ - ((systime_t)(((((uint32_t)(msec)) * ((uint32_t)CH_FREQUENCY) - 1UL) / \ - 1000UL) + 1UL)) - -/** - * @brief Microseconds to system ticks. - * @details Converts from microseconds to system ticks number. - * @note The result is rounded upward to the next tick boundary. - * - * @param[in] usec number of microseconds - * @return The number of ticks. - * - * @api - */ -#define US2ST(usec) \ - ((systime_t)(((((uint32_t)(usec)) * ((uint32_t)CH_FREQUENCY) - 1UL) / \ - 1000000UL) + 1UL)) -/** @} */ - -/** - * @brief Virtual Timer callback function. - */ -typedef void (*vtfunc_t)(void *); - -/** - * @brief Virtual Timer structure type. - */ -typedef struct VirtualTimer VirtualTimer; - -/** - * @extends VTList - * - * @brief Virtual Timer descriptor structure. - */ -struct VirtualTimer { - VirtualTimer *vt_next; /**< @brief Next timer in the delta - list. */ - VirtualTimer *vt_prev; /**< @brief Previous timer in the delta - list. */ - systime_t vt_time; /**< @brief Time delta before timeout. */ - vtfunc_t vt_func; /**< @brief Timer callback function - pointer. */ - void *vt_par; /**< @brief Timer callback function - parameter. */ -}; - -/** - * @brief Virtual timers list header. - * @note The delta list is implemented as a double link bidirectional list - * in order to make the unlink time constant, the reset of a virtual - * timer is often used in the code. - */ -typedef struct { - VirtualTimer *vt_next; /**< @brief Next timer in the delta - list. */ - VirtualTimer *vt_prev; /**< @brief Last timer in the delta - list. */ - systime_t vt_time; /**< @brief Must be initialized to -1. */ - volatile systime_t vt_systime; /**< @brief System Time counter. */ -} VTList; - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Virtual timers ticker. - * @note The system lock is released before entering the callback and - * re-acquired immediately after. It is callback's responsibility - * to acquire the lock if needed. This is done in order to reduce - * interrupts jitter when many timers are in use. - * - * @iclass - */ -#define chVTDoTickI() { \ - vtlist.vt_systime++; \ - if (&vtlist != (VTList *)vtlist.vt_next) { \ - VirtualTimer *vtp; \ - \ - --vtlist.vt_next->vt_time; \ - while (!(vtp = vtlist.vt_next)->vt_time) { \ - vtfunc_t fn = vtp->vt_func; \ - vtp->vt_func = (vtfunc_t)NULL; \ - vtp->vt_next->vt_prev = (void *)&vtlist; \ - (&vtlist)->vt_next = vtp->vt_next; \ - chSysUnlockFromIsr(); \ - fn(vtp->vt_par); \ - chSysLockFromIsr(); \ - } \ - } \ -} - -/** - * @brief Returns @p TRUE if the specified timer is armed. - * - * @iclass - */ -#define chVTIsArmedI(vtp) ((vtp)->vt_func != NULL) - -/** - * @brief Enables a virtual timer. - * @note The associated function is invoked from interrupt context. - * - * @param[out] vtp the @p VirtualTimer structure pointer - * @param[in] time the number of ticks before the operation timeouts, the - * special values are handled as follow: - * - @a TIME_INFINITE is allowed but interpreted as a - * normal time specification. - * - @a TIME_IMMEDIATE this value is not allowed. - * . - * @param[in] vtfunc the timer callback function. After invoking the - * callback the timer is disabled and the structure can - * be disposed or reused. - * @param[in] par a parameter that will be passed to the callback - * function - * - * @api - */ -#define chVTSet(vtp, time, vtfunc, par) { \ - chSysLock(); \ - chVTSetI(vtp, time, vtfunc, par); \ - chSysUnlock(); \ -} - -/** - * @brief Disables a Virtual Timer. - * @note The timer is first checked and disabled only if armed. - * - * @param[in] vtp the @p VirtualTimer structure pointer - * - * @api - */ -#define chVTReset(vtp) { \ - chSysLock(); \ - if (chVTIsArmedI(vtp)) \ - chVTResetI(vtp); \ - chSysUnlock(); \ -} - -/** - * @brief Current system time. - * @details Returns the number of system ticks since the @p chSysInit() - * invocation. - * @note The counter can reach its maximum and then restart from zero. - * @note This function is designed to work with the @p chThdSleepUntil(). - * - * @return The system time in ticks. - * - * @api - */ -#define chTimeNow() (vtlist.vt_systime) - -/** - * @brief Returns the elapsed time since the specified start time. - * - * @param[in] start start time - * @return The elapsed time. - * - * @api - */ -#define chTimeElapsedSince(start) (chTimeNow() - (start)) - -/** - * @brief Checks if the current system time is within the specified time - * window. - * @note When start==end then the function returns always true because the - * whole time range is specified. - * - * @param[in] start the start of the time window (inclusive) - * @param[in] end the end of the time window (non inclusive) - * @retval TRUE current time within the specified time window. - * @retval FALSE current time not within the specified time window. - * - * @api - */ -#define chTimeIsWithin(start, end) \ - (chTimeElapsedSince(start) < ((end) - (start))) -/** @} */ - -extern VTList vtlist; - -/* - * Virtual Timers APIs. - */ -#ifdef __cplusplus -extern "C" { -#endif - void _vt_init(void); - void chVTSetI(VirtualTimer *vtp, systime_t time, vtfunc_t vtfunc, void *par); - void chVTResetI(VirtualTimer *vtp); -#ifdef __cplusplus -} -#endif - -#endif /* _CHVT_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/kernel/kernel.mk b/firmware/chibios/os/kernel/kernel.mk deleted file mode 100644 index 1f9a046438..0000000000 --- a/firmware/chibios/os/kernel/kernel.mk +++ /dev/null @@ -1,23 +0,0 @@ -# List of all the ChibiOS/RT kernel files, there is no need to remove the files -# from this list, you can disable parts of the kernel by editing chconf.h. -KERNSRC = ${CHIBIOS}/os/kernel/src/chsys.c \ - ${CHIBIOS}/os/kernel/src/chdebug.c \ - ${CHIBIOS}/os/kernel/src/chlists.c \ - ${CHIBIOS}/os/kernel/src/chvt.c \ - ${CHIBIOS}/os/kernel/src/chschd.c \ - ${CHIBIOS}/os/kernel/src/chthreads.c \ - ${CHIBIOS}/os/kernel/src/chdynamic.c \ - ${CHIBIOS}/os/kernel/src/chregistry.c \ - ${CHIBIOS}/os/kernel/src/chsem.c \ - ${CHIBIOS}/os/kernel/src/chmtx.c \ - ${CHIBIOS}/os/kernel/src/chcond.c \ - ${CHIBIOS}/os/kernel/src/chevents.c \ - ${CHIBIOS}/os/kernel/src/chmsg.c \ - ${CHIBIOS}/os/kernel/src/chmboxes.c \ - ${CHIBIOS}/os/kernel/src/chqueues.c \ - ${CHIBIOS}/os/kernel/src/chmemcore.c \ - ${CHIBIOS}/os/kernel/src/chheap.c \ - ${CHIBIOS}/os/kernel/src/chmempools.c - -# Required include directories -KERNINC = ${CHIBIOS}/os/kernel/include diff --git a/firmware/chibios/os/kernel/src/chcond.c b/firmware/chibios/os/kernel/src/chcond.c deleted file mode 100644 index a8128c07e4..0000000000 --- a/firmware/chibios/os/kernel/src/chcond.c +++ /dev/null @@ -1,292 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ -/* - Concepts and parts of this file have been contributed by Leon Woestenberg. - */ - -/** - * @file chcond.c - * @brief Condition Variables code. - * - * @addtogroup condvars Condition Variables - * @details This module implements the Condition Variables mechanism. Condition - * variables are an extensions to the Mutex subsystem and cannot - * work alone. - *

Operation mode

- * The condition variable is a synchronization object meant to be - * used inside a zone protected by a @p Mutex. Mutexes and CondVars - * together can implement a Monitor construct. - * @pre In order to use the condition variable APIs the @p CH_USE_CONDVARS - * option must be enabled in @p chconf.h. - * @{ - */ - -#include "ch.h" - -#if (CH_USE_CONDVARS && CH_USE_MUTEXES) || defined(__DOXYGEN__) - -/** - * @brief Initializes s @p CondVar structure. - * - * @param[out] cp pointer to a @p CondVar structure - * - * @init - */ -void chCondInit(CondVar *cp) { - - chDbgCheck(cp != NULL, "chCondInit"); - - queue_init(&cp->c_queue); -} - -/** - * @brief Signals one thread that is waiting on the condition variable. - * - * @param[in] cp pointer to the @p CondVar structure - * - * @api - */ -void chCondSignal(CondVar *cp) { - - chDbgCheck(cp != NULL, "chCondSignal"); - - chSysLock(); - if (notempty(&cp->c_queue)) - chSchWakeupS(fifo_remove(&cp->c_queue), RDY_OK); - chSysUnlock(); -} - -/** - * @brief Signals one thread that is waiting on the condition variable. - * @post This function does not reschedule so a call to a rescheduling - * function must be performed before unlocking the kernel. Note that - * interrupt handlers always reschedule on exit so an explicit - * reschedule must not be performed in ISRs. - * - * @param[in] cp pointer to the @p CondVar structure - * - * @iclass - */ -void chCondSignalI(CondVar *cp) { - - chDbgCheckClassI(); - chDbgCheck(cp != NULL, "chCondSignalI"); - - if (notempty(&cp->c_queue)) - chSchReadyI(fifo_remove(&cp->c_queue))->p_u.rdymsg = RDY_OK; -} - -/** - * @brief Signals all threads that are waiting on the condition variable. - * - * @param[in] cp pointer to the @p CondVar structure - * - * @api - */ -void chCondBroadcast(CondVar *cp) { - - chSysLock(); - chCondBroadcastI(cp); - chSchRescheduleS(); - chSysUnlock(); -} - -/** - * @brief Signals all threads that are waiting on the condition variable. - * @post This function does not reschedule so a call to a rescheduling - * function must be performed before unlocking the kernel. Note that - * interrupt handlers always reschedule on exit so an explicit - * reschedule must not be performed in ISRs. - * - * @param[in] cp pointer to the @p CondVar structure - * - * @iclass - */ -void chCondBroadcastI(CondVar *cp) { - - chDbgCheckClassI(); - chDbgCheck(cp != NULL, "chCondBroadcastI"); - - /* Empties the condition variable queue and inserts all the Threads into the - ready list in FIFO order. The wakeup message is set to @p RDY_RESET in - order to make a chCondBroadcast() detectable from a chCondSignal().*/ - while (cp->c_queue.p_next != (void *)&cp->c_queue) - chSchReadyI(fifo_remove(&cp->c_queue))->p_u.rdymsg = RDY_RESET; -} - -/** - * @brief Waits on the condition variable releasing the mutex lock. - * @details Releases the currently owned mutex, waits on the condition - * variable, and finally acquires the mutex again. All the sequence - * is performed atomically. - * @pre The invoking thread must have at least one owned mutex. - * - * @param[in] cp pointer to the @p CondVar structure - * @return A message specifying how the invoking thread has been - * released from the condition variable. - * @retval RDY_OK if the condvar has been signaled using - * @p chCondSignal(). - * @retval RDY_RESET if the condvar has been signaled using - * @p chCondBroadcast(). - * - * @api - */ -msg_t chCondWait(CondVar *cp) { - msg_t msg; - - chSysLock(); - msg = chCondWaitS(cp); - chSysUnlock(); - return msg; -} - -/** - * @brief Waits on the condition variable releasing the mutex lock. - * @details Releases the currently owned mutex, waits on the condition - * variable, and finally acquires the mutex again. All the sequence - * is performed atomically. - * @pre The invoking thread must have at least one owned mutex. - * - * @param[in] cp pointer to the @p CondVar structure - * @return A message specifying how the invoking thread has been - * released from the condition variable. - * @retval RDY_OK if the condvar has been signaled using - * @p chCondSignal(). - * @retval RDY_RESET if the condvar has been signaled using - * @p chCondBroadcast(). - * - * @sclass - */ -msg_t chCondWaitS(CondVar *cp) { - Thread *ctp = currp; - Mutex *mp; - msg_t msg; - - chDbgCheckClassS(); - chDbgCheck(cp != NULL, "chCondWaitS"); - chDbgAssert(ctp->p_mtxlist != NULL, - "chCondWaitS(), #1", - "not owning a mutex"); - - mp = chMtxUnlockS(); - ctp->p_u.wtobjp = cp; - prio_insert(ctp, &cp->c_queue); - chSchGoSleepS(THD_STATE_WTCOND); - msg = ctp->p_u.rdymsg; - chMtxLockS(mp); - return msg; -} - -#if CH_USE_CONDVARS_TIMEOUT || defined(__DOXYGEN__) -/** - * @brief Waits on the condition variable releasing the mutex lock. - * @details Releases the currently owned mutex, waits on the condition - * variable, and finally acquires the mutex again. All the sequence - * is performed atomically. - * @pre The invoking thread must have at least one owned mutex. - * @pre The configuration option @p CH_USE_CONDVARS_TIMEOUT must be enabled - * in order to use this function. - * @post Exiting the function because a timeout does not re-acquire the - * mutex, the mutex ownership is lost. - * - * @param[in] cp pointer to the @p CondVar structure - * @param[in] time the number of ticks before the operation timeouts, the - * special values are handled as follow: - * - @a TIME_INFINITE no timeout. - * - @a TIME_IMMEDIATE this value is not allowed. - * . - * @return A message specifying how the invoking thread has been - * released from the condition variable. - * @retval RDY_OK if the condvar has been signaled using - * @p chCondSignal(). - * @retval RDY_RESET if the condvar has been signaled using - * @p chCondBroadcast(). - * @retval RDY_TIMEOUT if the condvar has not been signaled within the - * specified timeout. - * - * @api - */ -msg_t chCondWaitTimeout(CondVar *cp, systime_t time) { - msg_t msg; - - chSysLock(); - msg = chCondWaitTimeoutS(cp, time); - chSysUnlock(); - return msg; -} - -/** - * @brief Waits on the condition variable releasing the mutex lock. - * @details Releases the currently owned mutex, waits on the condition - * variable, and finally acquires the mutex again. All the sequence - * is performed atomically. - * @pre The invoking thread must have at least one owned mutex. - * @pre The configuration option @p CH_USE_CONDVARS_TIMEOUT must be enabled - * in order to use this function. - * @post Exiting the function because a timeout does not re-acquire the - * mutex, the mutex ownership is lost. - * - * @param[in] cp pointer to the @p CondVar structure - * @param[in] time the number of ticks before the operation timeouts, the - * special values are handled as follow: - * - @a TIME_INFINITE no timeout. - * - @a TIME_IMMEDIATE this value is not allowed. - * . - * @return A message specifying how the invoking thread has been - * released from the condition variable. - * @retval RDY_OK if the condvar has been signaled using - * @p chCondSignal(). - * @retval RDY_RESET if the condvar has been signaled using - * @p chCondBroadcast(). - * @retval RDY_TIMEOUT if the condvar has not been signaled within the - * specified timeout. - * - * @sclass - */ -msg_t chCondWaitTimeoutS(CondVar *cp, systime_t time) { - Mutex *mp; - msg_t msg; - - chDbgCheckClassS(); - chDbgCheck((cp != NULL) && (time != TIME_IMMEDIATE), "chCondWaitTimeoutS"); - chDbgAssert(currp->p_mtxlist != NULL, - "chCondWaitTimeoutS(), #1", - "not owning a mutex"); - - mp = chMtxUnlockS(); - currp->p_u.wtobjp = cp; - prio_insert(currp, &cp->c_queue); - msg = chSchGoSleepTimeoutS(THD_STATE_WTCOND, time); - if (msg != RDY_TIMEOUT) - chMtxLockS(mp); - return msg; -} -#endif /* CH_USE_CONDVARS_TIMEOUT */ - -#endif /* CH_USE_CONDVARS && CH_USE_MUTEXES */ - -/** @} */ diff --git a/firmware/chibios/os/kernel/src/chdebug.c b/firmware/chibios/os/kernel/src/chdebug.c deleted file mode 100644 index b6197a56b4..0000000000 --- a/firmware/chibios/os/kernel/src/chdebug.c +++ /dev/null @@ -1,282 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chdebug.c - * @brief ChibiOS/RT Debug code. - * - * @addtogroup debug - * @details Debug APIs and services: - * - Runtime system state and call protocol check. The following - * panic messages can be generated: - * - SV#1, misplaced @p chSysDisable(). - * - SV#2, misplaced @p chSysSuspend() - * - SV#3, misplaced @p chSysEnable(). - * - SV#4, misplaced @p chSysLock(). - * - SV#5, misplaced @p chSysUnlock(). - * - SV#6, misplaced @p chSysLockFromIsr(). - * - SV#7, misplaced @p chSysUnlockFromIsr(). - * - SV#8, misplaced @p CH_IRQ_PROLOGUE(). - * - SV#9, misplaced @p CH_IRQ_EPILOGUE(). - * - SV#10, misplaced I-class function. - * - SV#11, misplaced S-class function. - * . - * - Trace buffer. - * - Parameters check. - * - Kernel assertions. - * - Kernel panics. - * . - * @note Stack checks are not implemented in this module but in the port - * layer in an architecture-dependent way. - * @{ - */ - -#include "ch.h" - -/*===========================================================================*/ -/* System state checker related code and variables. */ -/*===========================================================================*/ - -#if CH_DBG_SYSTEM_STATE_CHECK || defined(__DOXYGEN__) - -/** - * @brief ISR nesting level. - */ -cnt_t dbg_isr_cnt; - -/** - * @brief Lock nesting level. - */ -cnt_t dbg_lock_cnt; - -/** - * @brief Guard code for @p chSysDisable(). - * - * @notapi - */ -void dbg_check_disable(void) { - - if ((dbg_isr_cnt != 0) || (dbg_lock_cnt != 0)) - chDbgPanic("SV#1"); -} - -/** - * @brief Guard code for @p chSysSuspend(). - * - * @notapi - */ -void dbg_check_suspend(void) { - - if ((dbg_isr_cnt != 0) || (dbg_lock_cnt != 0)) - chDbgPanic("SV#2"); -} - -/** - * @brief Guard code for @p chSysEnable(). - * - * @notapi - */ -void dbg_check_enable(void) { - - if ((dbg_isr_cnt != 0) || (dbg_lock_cnt != 0)) - chDbgPanic("SV#3"); -} - -/** - * @brief Guard code for @p chSysLock(). - * - * @notapi - */ -void dbg_check_lock(void) { - - if ((dbg_isr_cnt != 0) || (dbg_lock_cnt != 0)) - chDbgPanic("SV#4 misplaced chSysLock()"); - dbg_enter_lock(); -} - -/** - * @brief Guard code for @p chSysUnlock(). - * - * @notapi - */ -void dbg_check_unlock(void) { - - if ((dbg_isr_cnt != 0) || (dbg_lock_cnt <= 0)) - chDbgPanic("SV#5"); - dbg_leave_lock(); -} - -/** - * @brief Guard code for @p chSysLockFromIsr(). - * - * @notapi - */ -void dbg_check_lock_from_isr(void) { - - if ((dbg_isr_cnt <= 0) || (dbg_lock_cnt != 0)) - chDbgPanic("SV#6 misplaced chSysLockFromIsr"); - dbg_enter_lock(); -} - -/** - * @brief Guard code for @p chSysUnlockFromIsr(). - * - * @notapi - */ -void dbg_check_unlock_from_isr(void) { - - if ((dbg_isr_cnt <= 0) || (dbg_lock_cnt <= 0)) - chDbgPanic("SV#7"); - dbg_leave_lock(); -} - -extern int maxNesting; - -/** - * @brief Guard code for @p CH_IRQ_PROLOGUE(). - * - * @notapi - */ -void dbg_check_enter_isr(void) { - port_lock_from_isr(); - if ((dbg_isr_cnt < 0) || (dbg_lock_cnt != 0)) - chDbgPanic("SV#8"); - dbg_isr_cnt++; - if (dbg_isr_cnt > maxNesting) - maxNesting = dbg_isr_cnt; - port_unlock_from_isr(); -} - -/** - * @brief Guard code for @p CH_IRQ_EPILOGUE(). - * - * @notapi - */ -void dbg_check_leave_isr(void) { - - port_lock_from_isr(); - if ((dbg_isr_cnt <= 0) || (dbg_lock_cnt != 0)) - chDbgPanic("SV#9"); - dbg_isr_cnt--; - port_unlock_from_isr(); -} - -/** - * @brief I-class functions context check. - * @details Verifies that the system is in an appropriate state for invoking - * an I-class API function. A panic is generated if the state is - * not compatible. - * - * @api - */ -void chDbgCheckClassI(void) { - - if ((dbg_isr_cnt < 0) || (dbg_lock_cnt <= 0)) - chDbgPanic("SV#10 misplaced I-class function"); -} - -/** - * @brief S-class functions context check. - * @details Verifies that the system is in an appropriate state for invoking - * an S-class API function. A panic is generated if the state is - * not compatible. - * - * @api - */ -void chDbgCheckClassS(void) { - - if ((dbg_isr_cnt != 0) || (dbg_lock_cnt <= 0)) - chDbgPanic("SV#11"); -} - -#endif /* CH_DBG_SYSTEM_STATE_CHECK */ - -/*===========================================================================*/ -/* Trace related code and variables. */ -/*===========================================================================*/ - -#if CH_DBG_ENABLE_TRACE || defined(__DOXYGEN__) -/** - * @brief Public trace buffer. - */ -ch_trace_buffer_t dbg_trace_buffer; - -/** - * @brief Trace circular buffer subsystem initialization. - * @note Internal use only. - */ -void _trace_init(void) { - - dbg_trace_buffer.tb_size = CH_TRACE_BUFFER_SIZE; - dbg_trace_buffer.tb_ptr = &dbg_trace_buffer.tb_buffer[0]; -} - -/** - * @brief Inserts in the circular debug trace buffer a context switch record. - * - * @param[in] otp the thread being switched out - * - * @notapi - */ -void dbg_trace(Thread *otp) { - - dbg_trace_buffer.tb_ptr->se_time = chTimeNow(); - dbg_trace_buffer.tb_ptr->se_tp = currp; - dbg_trace_buffer.tb_ptr->se_wtobjp = otp->p_u.wtobjp; - dbg_trace_buffer.tb_ptr->se_state = (uint8_t)otp->p_state; - if (++dbg_trace_buffer.tb_ptr >= - &dbg_trace_buffer.tb_buffer[CH_TRACE_BUFFER_SIZE]) - dbg_trace_buffer.tb_ptr = &dbg_trace_buffer.tb_buffer[0]; -} -#endif /* CH_DBG_ENABLE_TRACE */ - -/*===========================================================================*/ -/* Panic related code and variables. */ -/*===========================================================================*/ - -#if CH_DBG_ENABLED || defined(__DOXYGEN__) -/** - * @brief Pointer to the panic message. - * @details This pointer is meant to be accessed through the debugger, it is - * written once and then the system is halted. - */ -const char *dbg_panic_msg; - -/** - * @brief Prints a panic message on the console and then halts the system. - * - * @param[in] msg the pointer to the panic message string - */ - -void chDbgPanic3(const char *msg, const char * file, int line); - -void chDbgPanic(const char *msg) { - chDbgPanic3(msg, __FILE__, __LINE__); -} -#endif /* CH_DBG_ENABLED */ - -/** @} */ diff --git a/firmware/chibios/os/kernel/src/chdynamic.c b/firmware/chibios/os/kernel/src/chdynamic.c deleted file mode 100644 index e664e78226..0000000000 --- a/firmware/chibios/os/kernel/src/chdynamic.c +++ /dev/null @@ -1,211 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chdynamic.c - * @brief Dynamic threads code. - * - * @addtogroup dynamic_threads - * @details Dynamic threads related APIs and services. - * @{ - */ - -#include "ch.h" - -#if CH_USE_DYNAMIC || defined(__DOXYGEN__) - -/** - * @brief Adds a reference to a thread object. - * @pre The configuration option @p CH_USE_DYNAMIC must be enabled in order - * to use this function. - * - * @param[in] tp pointer to the thread - * @return The same thread pointer passed as parameter - * representing the new reference. - * - * @api - */ -Thread *chThdAddRef(Thread *tp) { - - chSysLock(); - chDbgAssert(tp->p_refs < 255, "chThdAddRef(), #1", "too many references"); - tp->p_refs++; - chSysUnlock(); - return tp; -} - -/** - * @brief Releases a reference to a thread object. - * @details If the references counter reaches zero and the thread - * is in the @p THD_STATE_FINAL state then the thread's memory is - * returned to the proper allocator. - * @pre The configuration option @p CH_USE_DYNAMIC must be enabled in order - * to use this function. - * @note Static threads are not affected. - * - * @param[in] tp pointer to the thread - * - * @api - */ -void chThdRelease(Thread *tp) { - trefs_t refs; - - chSysLock(); - chDbgAssert(tp->p_refs > 0, "chThdRelease(), #1", "not referenced"); - refs = --tp->p_refs; - chSysUnlock(); - - /* If the references counter reaches zero and the thread is in its - terminated state then the memory can be returned to the proper - allocator. Of course static threads are not affected.*/ - if ((refs == 0) && (tp->p_state == THD_STATE_FINAL)) { - switch (tp->p_flags & THD_MEM_MODE_MASK) { -#if CH_USE_HEAP - case THD_MEM_MODE_HEAP: -#if CH_USE_REGISTRY - REG_REMOVE(tp); -#endif - chHeapFree(tp); - break; -#endif -#if CH_USE_MEMPOOLS - case THD_MEM_MODE_MEMPOOL: -#if CH_USE_REGISTRY - REG_REMOVE(tp); -#endif - chPoolFree(tp->p_mpool, tp); - break; -#endif - } - } -} - -#if CH_USE_HEAP || defined(__DOXYGEN__) -/** - * @brief Creates a new thread allocating the memory from the heap. - * @pre The configuration options @p CH_USE_DYNAMIC and @p CH_USE_HEAP - * must be enabled in order to use this function. - * @note A thread can terminate by calling @p chThdExit() or by simply - * returning from its main function. - * @note The memory allocated for the thread is not released when the thread - * terminates but when a @p chThdWait() is performed. - * - * @param[in] heapp heap from which allocate the memory or @p NULL for the - * default heap - * @param[in] size size of the working area to be allocated - * @param[in] prio the priority level for the new thread - * @param[in] pf the thread function - * @param[in] arg an argument passed to the thread function. It can be - * @p NULL. - * @return The pointer to the @p Thread structure allocated for - * the thread into the working space area. - * @retval NULL if the memory cannot be allocated. - * - * @api - */ -Thread *chThdCreateFromHeap(MemoryHeap *heapp, size_t size, - tprio_t prio, tfunc_t pf, void *arg) { - void *wsp; - Thread *tp; - - wsp = chHeapAlloc(heapp, size); - if (wsp == NULL) - return NULL; - -#if CH_DBG_FILL_THREADS - _thread_memfill((uint8_t *)wsp, - (uint8_t *)wsp + sizeof(Thread), - CH_THREAD_FILL_VALUE); - _thread_memfill((uint8_t *)wsp + sizeof(Thread), - (uint8_t *)wsp + size, - CH_STACK_FILL_VALUE); -#endif - - chSysLock(); - tp = chThdCreateI(wsp, size, prio, pf, arg); - tp->p_flags = THD_MEM_MODE_HEAP; - chSchWakeupS(tp, RDY_OK); - chSysUnlock(); - return tp; -} -#endif /* CH_USE_HEAP */ - -#if CH_USE_MEMPOOLS || defined(__DOXYGEN__) -/** - * @brief Creates a new thread allocating the memory from the specified - * memory pool. - * @pre The configuration options @p CH_USE_DYNAMIC and @p CH_USE_MEMPOOLS - * must be enabled in order to use this function. - * @note A thread can terminate by calling @p chThdExit() or by simply - * returning from its main function. - * @note The memory allocated for the thread is not released when the thread - * terminates but when a @p chThdWait() is performed. - * - * @param[in] mp pointer to the memory pool object - * @param[in] prio the priority level for the new thread - * @param[in] pf the thread function - * @param[in] arg an argument passed to the thread function. It can be - * @p NULL. - * @return The pointer to the @p Thread structure allocated for - * the thread into the working space area. - * @retval NULL if the memory pool is empty. - * - * @api - */ -Thread *chThdCreateFromMemoryPool(MemoryPool *mp, tprio_t prio, - tfunc_t pf, void *arg) { - void *wsp; - Thread *tp; - - chDbgCheck(mp != NULL, "chThdCreateFromMemoryPool"); - - wsp = chPoolAlloc(mp); - if (wsp == NULL) - return NULL; - -#if CH_DBG_FILL_THREADS - _thread_memfill((uint8_t *)wsp, - (uint8_t *)wsp + sizeof(Thread), - CH_THREAD_FILL_VALUE); - _thread_memfill((uint8_t *)wsp + sizeof(Thread), - (uint8_t *)wsp + mp->mp_object_size, - CH_STACK_FILL_VALUE); -#endif - - chSysLock(); - tp = chThdCreateI(wsp, mp->mp_object_size, prio, pf, arg); - tp->p_flags = THD_MEM_MODE_MEMPOOL; - tp->p_mpool = mp; - chSchWakeupS(tp, RDY_OK); - chSysUnlock(); - return tp; -} -#endif /* CH_USE_MEMPOOLS */ - -#endif /* CH_USE_DYNAMIC */ - -/** @} */ diff --git a/firmware/chibios/os/kernel/src/chevents.c b/firmware/chibios/os/kernel/src/chevents.c deleted file mode 100644 index 77b8473e96..0000000000 --- a/firmware/chibios/os/kernel/src/chevents.c +++ /dev/null @@ -1,555 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ -/* - Concepts and parts of this file have been contributed by Scott (skute). - */ - -/** - * @file chevents.c - * @brief Events code. - * - * @addtogroup events - * @details Event Flags, Event Sources and Event Listeners. - *

Operation mode

- * Each thread has a mask of pending event flags inside its @p Thread - * structure. - * Operations defined for event flags: - * - Wait, the invoking thread goes to sleep until a certain - * AND/OR combination of event flags becomes pending. - * - Clear, a mask of event flags is cleared from the pending - * events mask, the cleared event flags mask is returned (only the - * flags that were actually pending and then cleared). - * - Signal, an event mask is directly ORed to the mask of the - * signaled thread. - * - Broadcast, each thread registered on an Event Source is - * signaled with the event flags specified in its Event Listener. - * - Dispatch, an events mask is scanned and for each bit set - * to one an associated handler function is invoked. Bit masks are - * scanned from bit zero upward. - * . - * An Event Source is a special object that can be "broadcasted" by - * a thread or an interrupt service routine. Broadcasting an Event - * Source has the effect that all the threads registered on the - * Event Source will be signaled with an events mask.
- * An unlimited number of Event Sources can exists in a system and - * each thread can be listening on an unlimited number of - * them. - * @pre In order to use the Events APIs the @p CH_USE_EVENTS option must be - * enabled in @p chconf.h. - * @post Enabling events requires 1-4 (depending on the architecture) - * extra bytes in the @p Thread structure. - * @{ - */ - -#include "ch.h" - -#if CH_USE_EVENTS || defined(__DOXYGEN__) -/** - * @brief Registers an Event Listener on an Event Source. - * @details Once a thread has registered as listener on an event source it - * will be notified of all events broadcasted there. - * @note Multiple Event Listeners can specify the same bits to be ORed to - * different threads. - * - * @param[in] esp pointer to the @p EventSource structure - * @param[out] elp pointer to the @p EventListener structure - * @param[in] mask the mask of event flags to be ORed to the thread when - * the event source is broadcasted - * - * @api - */ -void chEvtRegisterMask(EventSource *esp, EventListener *elp, eventmask_t mask) { - - chDbgCheck((esp != NULL) && (elp != NULL), "chEvtRegisterMask"); - - chSysLock(); - elp->el_next = esp->es_next; - esp->es_next = elp; - elp->el_listener = currp; - elp->el_mask = mask; - elp->el_flags = 0; - chSysUnlock(); -} - -/** - * @brief Unregisters an Event Listener from its Event Source. - * @note If the event listener is not registered on the specified event - * source then the function does nothing. - * @note For optimal performance it is better to perform the unregister - * operations in inverse order of the register operations (elements - * are found on top of the list). - * - * @param[in] esp pointer to the @p EventSource structure - * @param[in] elp pointer to the @p EventListener structure - * - * @api - */ -void chEvtUnregister(EventSource *esp, EventListener *elp) { - EventListener *p; - - chDbgCheck((esp != NULL) && (elp != NULL), "chEvtUnregister"); - - p = (EventListener *)esp; - chSysLock(); - while (p->el_next != (EventListener *)esp) { - if (p->el_next == elp) { - p->el_next = elp->el_next; - break; - } - p = p->el_next; - } - chSysUnlock(); -} - -/** - * @brief Clears the pending events specified in the mask. - * - * @param[in] mask the events to be cleared - * @return The pending events that were cleared. - * - * @api - */ -eventmask_t chEvtGetAndClearEvents(eventmask_t mask) { - eventmask_t m; - - chSysLock(); - - m = currp->p_epending & mask; - currp->p_epending &= ~mask; - - chSysUnlock(); - return m; -} - -/** - * @brief Adds (OR) a set of event flags on the current thread, this is - * @b much faster than using @p chEvtBroadcast() or @p chEvtSignal(). - * - * @param[in] mask the event flags to be added - * @return The current pending events mask. - * - * @api - */ -eventmask_t chEvtAddEvents(eventmask_t mask) { - - chSysLock(); - - mask = (currp->p_epending |= mask); - - chSysUnlock(); - return mask; -} - -/** - * @brief Signals all the Event Listeners registered on the specified Event - * Source. - * @details This function variants ORs the specified event flags to all the - * threads registered on the @p EventSource in addition to the event - * flags specified by the threads themselves in the - * @p EventListener objects. - * @post This function does not reschedule so a call to a rescheduling - * function must be performed before unlocking the kernel. Note that - * interrupt handlers always reschedule on exit so an explicit - * reschedule must not be performed in ISRs. - * - * @param[in] esp pointer to the @p EventSource structure - * @param[in] flags the flags set to be added to the listener flags mask - * - * @iclass - */ -void chEvtBroadcastFlagsI(EventSource *esp, flagsmask_t flags) { - EventListener *elp; - - chDbgCheckClassI(); - chDbgCheck(esp != NULL, "chEvtBroadcastMaskI"); - - elp = esp->es_next; - while (elp != (EventListener *)esp) { - elp->el_flags |= flags; - chEvtSignalI(elp->el_listener, elp->el_mask); - elp = elp->el_next; - } -} - -/** - * @brief Returns the flags associated to an @p EventListener. - * @details The flags are returned and the @p EventListener flags mask is - * cleared. - * - * @param[in] elp pointer to the @p EventListener structure - * @return The flags added to the listener by the associated - * event source. - * - * @api - */ -flagsmask_t chEvtGetAndClearFlags(EventListener *elp) { - flagsmask_t flags; - - chSysLock(); - - flags = elp->el_flags; - elp->el_flags = 0; - - chSysUnlock(); - return flags; -} - -/** - * @brief Adds a set of event flags directly to specified @p Thread. - * - * @param[in] tp the thread to be signaled - * @param[in] mask the event flags set to be ORed - * - * @api - */ -void chEvtSignal(Thread *tp, eventmask_t mask) { - - chDbgCheck(tp != NULL, "chEvtSignal"); - - chSysLock(); - chEvtSignalI(tp, mask); - chSchRescheduleS(); - chSysUnlock(); -} - -/** - * @brief Adds a set of event flags directly to specified @p Thread. - * @post This function does not reschedule so a call to a rescheduling - * function must be performed before unlocking the kernel. Note that - * interrupt handlers always reschedule on exit so an explicit - * reschedule must not be performed in ISRs. - * - * @param[in] tp the thread to be signaled - * @param[in] mask the event flags set to be ORed - * - * @iclass - */ -void chEvtSignalI(Thread *tp, eventmask_t mask) { - - chDbgCheckClassI(); - chDbgCheck(tp != NULL, "chEvtSignalI"); - - tp->p_epending |= mask; - /* Test on the AND/OR conditions wait states.*/ - if (((tp->p_state == THD_STATE_WTOREVT) && - ((tp->p_epending & tp->p_u.ewmask) != 0)) || - ((tp->p_state == THD_STATE_WTANDEVT) && - ((tp->p_epending & tp->p_u.ewmask) == tp->p_u.ewmask))) - chSchReadyI(tp)->p_u.rdymsg = RDY_OK; -} - -/** - * @brief Signals all the Event Listeners registered on the specified Event - * Source. - * @details This function variants ORs the specified event flags to all the - * threads registered on the @p EventSource in addition to the event - * flags specified by the threads themselves in the - * @p EventListener objects. - * - * @param[in] esp pointer to the @p EventSource structure - * @param[in] flags the flags set to be added to the listener flags mask - * - * @api - */ -void chEvtBroadcastFlags(EventSource *esp, flagsmask_t flags) { - - chSysLock(); - chEvtBroadcastFlagsI(esp, flags); - chSchRescheduleS(); - chSysUnlock(); -} - -/** - * @brief Returns the flags associated to an @p EventListener. - * @details The flags are returned and the @p EventListener flags mask is - * cleared. - * - * @param[in] elp pointer to the @p EventListener structure - * @return The flags added to the listener by the associated - * event source. - * - * @iclass - */ -flagsmask_t chEvtGetAndClearFlagsI(EventListener *elp) { - flagsmask_t flags; - - flags = elp->el_flags; - elp->el_flags = 0; - - return flags; -} - -/** - * @brief Invokes the event handlers associated to an event flags mask. - * - * @param[in] mask mask of the event flags to be dispatched - * @param[in] handlers an array of @p evhandler_t. The array must have size - * equal to the number of bits in eventmask_t. - * - * @api - */ -void chEvtDispatch(const evhandler_t *handlers, eventmask_t mask) { - eventid_t eid; - - chDbgCheck(handlers != NULL, "chEvtDispatch"); - - eid = 0; - while (mask) { - if (mask & EVENT_MASK(eid)) { - chDbgAssert(handlers[eid] != NULL, - "chEvtDispatch(), #1", - "null handler"); - mask &= ~EVENT_MASK(eid); - handlers[eid](eid); - } - eid++; - } -} - -#if CH_OPTIMIZE_SPEED || !CH_USE_EVENTS_TIMEOUT || defined(__DOXYGEN__) -/** - * @brief Waits for exactly one of the specified events. - * @details The function waits for one event among those specified in - * @p mask to become pending then the event is cleared and returned. - * @note One and only one event is served in the function, the one with the - * lowest event id. The function is meant to be invoked into a loop in - * order to serve all the pending events.
- * This means that Event Listeners with a lower event identifier have - * an higher priority. - * - * @param[in] mask mask of the event flags that the function should wait - * for, @p ALL_EVENTS enables all the events - * @return The mask of the lowest id served and cleared event. - * - * @api - */ -eventmask_t chEvtWaitOne(eventmask_t mask) { - Thread *ctp = currp; - eventmask_t m; - - chSysLock(); - - if ((m = (ctp->p_epending & mask)) == 0) { - ctp->p_u.ewmask = mask; - chSchGoSleepS(THD_STATE_WTOREVT); - m = ctp->p_epending & mask; - } - m ^= m & (m - 1); - ctp->p_epending &= ~m; - - chSysUnlock(); - return m; -} - -/** - * @brief Waits for any of the specified events. - * @details The function waits for any event among those specified in - * @p mask to become pending then the events are cleared and returned. - * - * @param[in] mask mask of the event flags that the function should wait - * for, @p ALL_EVENTS enables all the events - * @return The mask of the served and cleared events. - * - * @api - */ -eventmask_t chEvtWaitAny(eventmask_t mask) { - Thread *ctp = currp; - eventmask_t m; - - chSysLock(); - - if ((m = (ctp->p_epending & mask)) == 0) { - ctp->p_u.ewmask = mask; - chSchGoSleepS(THD_STATE_WTOREVT); - m = ctp->p_epending & mask; - } - ctp->p_epending &= ~m; - - chSysUnlock(); - return m; -} - -/** - * @brief Waits for all the specified events. - * @details The function waits for all the events specified in @p mask to - * become pending then the events are cleared and returned. - * - * @param[in] mask mask of the event flags that the function should wait - * for, @p ALL_EVENTS requires all the events - * @return The mask of the served and cleared events. - * - * @api - */ -eventmask_t chEvtWaitAll(eventmask_t mask) { - Thread *ctp = currp; - - chSysLock(); - - if ((ctp->p_epending & mask) != mask) { - ctp->p_u.ewmask = mask; - chSchGoSleepS(THD_STATE_WTANDEVT); - } - ctp->p_epending &= ~mask; - - chSysUnlock(); - return mask; -} -#endif /* CH_OPTIMIZE_SPEED || !CH_USE_EVENTS_TIMEOUT */ - -#if CH_USE_EVENTS_TIMEOUT || defined(__DOXYGEN__) -/** - * @brief Waits for exactly one of the specified events. - * @details The function waits for one event among those specified in - * @p mask to become pending then the event is cleared and returned. - * @note One and only one event is served in the function, the one with the - * lowest event id. The function is meant to be invoked into a loop in - * order to serve all the pending events.
- * This means that Event Listeners with a lower event identifier have - * an higher priority. - * - * @param[in] mask mask of the event flags that the function should wait - * for, @p ALL_EVENTS enables all the events - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The mask of the lowest id served and cleared event. - * @retval 0 if the operation has timed out. - * - * @api - */ -eventmask_t chEvtWaitOneTimeout(eventmask_t mask, systime_t time) { - Thread *ctp = currp; - eventmask_t m; - - chSysLock(); - - if ((m = (ctp->p_epending & mask)) == 0) { - if (TIME_IMMEDIATE == time) { - chSysUnlock(); - return (eventmask_t)0; - } - ctp->p_u.ewmask = mask; - if (chSchGoSleepTimeoutS(THD_STATE_WTOREVT, time) < RDY_OK) { - chSysUnlock(); - return (eventmask_t)0; - } - m = ctp->p_epending & mask; - } - m ^= m & (m - 1); - ctp->p_epending &= ~m; - - chSysUnlock(); - return m; -} - -/** - * @brief Waits for any of the specified events. - * @details The function waits for any event among those specified in - * @p mask to become pending then the events are cleared and - * returned. - * - * @param[in] mask mask of the event flags that the function should wait - * for, @p ALL_EVENTS enables all the events - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The mask of the served and cleared events. - * @retval 0 if the operation has timed out. - * - * @api - */ -eventmask_t chEvtWaitAnyTimeout(eventmask_t mask, systime_t time) { - Thread *ctp = currp; - eventmask_t m; - - chSysLock(); - - if ((m = (ctp->p_epending & mask)) == 0) { - if (TIME_IMMEDIATE == time) { - chSysUnlock(); - return (eventmask_t)0; - } - ctp->p_u.ewmask = mask; - if (chSchGoSleepTimeoutS(THD_STATE_WTOREVT, time) < RDY_OK) { - chSysUnlock(); - return (eventmask_t)0; - } - m = ctp->p_epending & mask; - } - ctp->p_epending &= ~m; - - chSysUnlock(); - return m; -} - -/** - * @brief Waits for all the specified events. - * @details The function waits for all the events specified in @p mask to - * become pending then the events are cleared and returned. - * - * @param[in] mask mask of the event flags that the function should wait - * for, @p ALL_EVENTS requires all the events - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The mask of the served and cleared events. - * @retval 0 if the operation has timed out. - * - * @api - */ -eventmask_t chEvtWaitAllTimeout(eventmask_t mask, systime_t time) { - Thread *ctp = currp; - - chSysLock(); - - if ((ctp->p_epending & mask) != mask) { - if (TIME_IMMEDIATE == time) { - chSysUnlock(); - return (eventmask_t)0; - } - ctp->p_u.ewmask = mask; - if (chSchGoSleepTimeoutS(THD_STATE_WTANDEVT, time) < RDY_OK) { - chSysUnlock(); - return (eventmask_t)0; - } - } - ctp->p_epending &= ~mask; - - chSysUnlock(); - return mask; -} -#endif /* CH_USE_EVENTS_TIMEOUT */ - -#endif /* CH_USE_EVENTS */ - -/** @} */ diff --git a/firmware/chibios/os/kernel/src/chheap.c b/firmware/chibios/os/kernel/src/chheap.c deleted file mode 100644 index d2b18e15ae..0000000000 --- a/firmware/chibios/os/kernel/src/chheap.c +++ /dev/null @@ -1,325 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chheap.c - * @brief Heaps code. - * - * @addtogroup heaps - * @details Heap Allocator related APIs. - *

Operation mode

- * The heap allocator implements a first-fit strategy and its APIs - * are functionally equivalent to the usual @p malloc() and @p free() - * library functions. The main difference is that the OS heap APIs - * are guaranteed to be thread safe.
- * By enabling the @p CH_USE_MALLOC_HEAP option the heap manager - * will use the runtime-provided @p malloc() and @p free() as - * back end for the heap APIs instead of the system provided - * allocator. - * @pre In order to use the heap APIs the @p CH_USE_HEAP option must - * be enabled in @p chconf.h. - * @{ - */ - -#include "ch.h" - -#if CH_USE_HEAP || defined(__DOXYGEN__) - -#if !CH_USE_MALLOC_HEAP || defined(__DOXYGEN__) - -/* - * Defaults on the best synchronization mechanism available. - */ -#if CH_USE_MUTEXES || defined(__DOXYGEN__) -#define H_LOCK(h) chMtxLock(&(h)->h_mtx) -#define H_UNLOCK(h) chMtxUnlock() -#else -#define H_LOCK(h) chSemWait(&(h)->h_sem) -#define H_UNLOCK(h) chSemSignal(&(h)->h_sem) -#endif - -/** - * @brief Default heap descriptor. - */ -static MemoryHeap default_heap; - -/** - * @brief Initializes the default heap. - * - * @notapi - */ -void _heap_init(void) { - default_heap.h_provider = chCoreAlloc; - default_heap.h_free.h.u.next = (union heap_header *)NULL; - default_heap.h_free.h.size = 0; -#if CH_USE_MUTEXES || defined(__DOXYGEN__) - chMtxInit(&default_heap.h_mtx); -#else - chSemInit(&default_heap.h_sem, 1); -#endif -} - -/** - * @brief Initializes a memory heap from a static memory area. - * @pre Both the heap buffer base and the heap size must be aligned to - * the @p stkalign_t type size. - * @pre In order to use this function the option @p CH_USE_MALLOC_HEAP - * must be disabled. - * - * @param[out] heapp pointer to the memory heap descriptor to be initialized - * @param[in] buf heap buffer base - * @param[in] size heap size - * - * @init - */ -void chHeapInit(MemoryHeap *heapp, void *buf, size_t size) { - union heap_header *hp; - - chDbgCheck(MEM_IS_ALIGNED(buf) && MEM_IS_ALIGNED(size), "chHeapInit"); - - heapp->h_provider = (memgetfunc_t)NULL; - heapp->h_free.h.u.next = hp = buf; - heapp->h_free.h.size = 0; - hp->h.u.next = NULL; - hp->h.size = size - sizeof(union heap_header); -#if CH_USE_MUTEXES || defined(__DOXYGEN__) - chMtxInit(&heapp->h_mtx); -#else - chSemInit(&heapp->h_sem, 1); -#endif -} - -/** - * @brief Allocates a block of memory from the heap by using the first-fit - * algorithm. - * @details The allocated block is guaranteed to be properly aligned for a - * pointer data type (@p stkalign_t). - * - * @param[in] heapp pointer to a heap descriptor or @p NULL in order to - * access the default heap. - * @param[in] size the size of the block to be allocated. Note that the - * allocated block may be a bit bigger than the requested - * size for alignment and fragmentation reasons. - * @return A pointer to the allocated block. - * @retval NULL if the block cannot be allocated. - * - * @api - */ -void *chHeapAlloc(MemoryHeap *heapp, size_t size) { - union heap_header *qp, *hp, *fp; - - if (heapp == NULL) - heapp = &default_heap; - - size = MEM_ALIGN_NEXT(size); - qp = &heapp->h_free; - H_LOCK(heapp); - - while (qp->h.u.next != NULL) { - hp = qp->h.u.next; - if (hp->h.size >= size) { - if (hp->h.size < size + sizeof(union heap_header)) { - /* Gets the whole block even if it is slightly bigger than the - requested size because the fragment would be too small to be - useful.*/ - qp->h.u.next = hp->h.u.next; - } - else { - /* Block bigger enough, must split it.*/ - fp = (void *)((uint8_t *)(hp) + sizeof(union heap_header) + size); - fp->h.u.next = hp->h.u.next; - fp->h.size = hp->h.size - sizeof(union heap_header) - size; - qp->h.u.next = fp; - hp->h.size = size; - } - hp->h.u.heap = heapp; - - H_UNLOCK(heapp); - return (void *)(hp + 1); - } - qp = hp; - } - - H_UNLOCK(heapp); - - /* More memory is required, tries to get it from the associated provider - else fails.*/ - if (heapp->h_provider) { - hp = heapp->h_provider(size + sizeof(union heap_header)); - if (hp != NULL) { - hp->h.u.heap = heapp; - hp->h.size = size; - hp++; - return (void *)hp; - } - } - return NULL; -} - -#define LIMIT(p) (union heap_header *)((uint8_t *)(p) + \ - sizeof(union heap_header) + \ - (p)->h.size) - -/** - * @brief Frees a previously allocated memory block. - * - * @param[in] p pointer to the memory block to be freed - * - * @api - */ -void chHeapFree(void *p) { - union heap_header *qp, *hp; - MemoryHeap *heapp; - - chDbgCheck(p != NULL, "chHeapFree"); - - hp = (union heap_header *)p - 1; - heapp = hp->h.u.heap; - qp = &heapp->h_free; - H_LOCK(heapp); - - while (TRUE) { - chDbgAssert((hp < qp) || (hp >= LIMIT(qp)), - "chHeapFree(), #1", - "within free block"); - - if (((qp == &heapp->h_free) || (hp > qp)) && - ((qp->h.u.next == NULL) || (hp < qp->h.u.next))) { - /* Insertion after qp.*/ - hp->h.u.next = qp->h.u.next; - qp->h.u.next = hp; - /* Verifies if the newly inserted block should be merged.*/ - if (LIMIT(hp) == hp->h.u.next) { - /* Merge with the next block.*/ - hp->h.size += hp->h.u.next->h.size + sizeof(union heap_header); - hp->h.u.next = hp->h.u.next->h.u.next; - } - if ((LIMIT(qp) == hp)) { - /* Merge with the previous block.*/ - qp->h.size += hp->h.size + sizeof(union heap_header); - qp->h.u.next = hp->h.u.next; - } - break; - } - qp = qp->h.u.next; - } - - H_UNLOCK(heapp); - return; -} - -/** - * @brief Reports the heap status. - * @note This function is meant to be used in the test suite, it should - * not be really useful for the application code. - * @note This function is not implemented when the @p CH_USE_MALLOC_HEAP - * configuration option is used (it always returns zero). - * - * @param[in] heapp pointer to a heap descriptor or @p NULL in order to - * access the default heap. - * @param[in] sizep pointer to a variable that will receive the total - * fragmented free space - * @return The number of fragments in the heap. - * - * @api - */ -size_t chHeapStatus(MemoryHeap *heapp, size_t *sizep) { - union heap_header *qp; - size_t n, sz; - - if (heapp == NULL) - heapp = &default_heap; - - H_LOCK(heapp); - - sz = 0; - for (n = 0, qp = &heapp->h_free; qp->h.u.next; n++, qp = qp->h.u.next) - sz += qp->h.u.next->h.size; - if (sizep) - *sizep = sz; - - H_UNLOCK(heapp); - return n; -} - -#else /* CH_USE_MALLOC_HEAP */ - -#include - -#if CH_USE_MUTEXES -#define H_LOCK() chMtxLock(&hmtx) -#define H_UNLOCK() chMtxUnlock() -static Mutex hmtx; -#elif CH_USE_SEMAPHORES -#define H_LOCK() chSemWait(&hsem) -#define H_UNLOCK() chSemSignal(&hsem) -static Semaphore hsem; -#endif - -void _heap_init(void) { - -#if CH_USE_MUTEXES - chMtxInit(&hmtx); -#else - chSemInit(&hsem, 1); -#endif -} - -void *chHeapAlloc(MemoryHeap *heapp, size_t size) { - void *p; - - chDbgCheck(heapp == NULL, "chHeapAlloc"); - - H_LOCK(); - p = malloc(size); - H_UNLOCK(); - return p; -} - -void chHeapFree(void *p) { - - chDbgCheck(p != NULL, "chHeapFree"); - - H_LOCK(); - free(p); - H_UNLOCK(); -} - -size_t chHeapStatus(MemoryHeap *heapp, size_t *sizep) { - - chDbgCheck(heapp == NULL, "chHeapStatus"); - - if (sizep) - *sizep = 0; - return 0; -} - -#endif /* CH_USE_MALLOC_HEAP */ - -#endif /* CH_USE_HEAP */ - -/** @} */ diff --git a/firmware/chibios/os/kernel/src/chlists.c b/firmware/chibios/os/kernel/src/chlists.c deleted file mode 100644 index 4139a80784..0000000000 --- a/firmware/chibios/os/kernel/src/chlists.c +++ /dev/null @@ -1,163 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chlists.c - * @brief Thread queues/lists code. - * - * @addtogroup internals - * @details All the functions present in this module, while public, are not - * OS APIs and should not be directly used in the user applications - * code. - * @{ - */ -#include "ch.h" - -#if !CH_OPTIMIZE_SPEED || defined(__DOXYGEN__) -/** - * @brief Inserts a thread into a priority ordered queue. - * @note The insertion is done by scanning the list from the highest - * priority toward the lowest. - * - * @param[in] tp the pointer to the thread to be inserted in the list - * @param[in] tqp the pointer to the threads list header - * - * @notapi - */ -void prio_insert(Thread *tp, ThreadsQueue *tqp) { - - /* cp iterates over the queue.*/ - Thread *cp = (Thread *)tqp; - do { - /* Iterate to next thread in queue.*/ - cp = cp->p_next; - /* Not end of queue? and cp has equal or higher priority than tp?.*/ - } while ((cp != (Thread *)tqp) && (cp->p_prio >= tp->p_prio)); - /* Insertion on p_prev.*/ - tp->p_next = cp; - tp->p_prev = cp->p_prev; - tp->p_prev->p_next = cp->p_prev = tp; -} - -/** - * @brief Inserts a Thread into a queue. - * - * @param[in] tp the pointer to the thread to be inserted in the list - * @param[in] tqp the pointer to the threads list header - * - * @notapi - */ -void queue_insert(Thread *tp, ThreadsQueue *tqp) { - - tp->p_next = (Thread *)tqp; - tp->p_prev = tqp->p_prev; - tp->p_prev->p_next = tqp->p_prev = tp; -} - -/** - * @brief Removes the first-out Thread from a queue and returns it. - * @note If the queue is priority ordered then this function returns the - * thread with the highest priority. - * - * @param[in] tqp the pointer to the threads list header - * @return The removed thread pointer. - * - * @notapi - */ -Thread *fifo_remove(ThreadsQueue *tqp) { - Thread *tp = tqp->p_next; - - (tqp->p_next = tp->p_next)->p_prev = (Thread *)tqp; - return tp; -} - -/** - * @brief Removes the last-out Thread from a queue and returns it. - * @note If the queue is priority ordered then this function returns the - * thread with the lowest priority. - * - * @param[in] tqp the pointer to the threads list header - * @return The removed thread pointer. - * - * @notapi - */ -Thread *lifo_remove(ThreadsQueue *tqp) { - Thread *tp = tqp->p_prev; - - (tqp->p_prev = tp->p_prev)->p_next = (Thread *)tqp; - return tp; -} - -/** - * @brief Removes a Thread from a queue and returns it. - * @details The thread is removed from the queue regardless of its relative - * position and regardless the used insertion method. - * - * @param[in] tp the pointer to the thread to be removed from the queue - * @return The removed thread pointer. - * - * @notapi - */ -Thread *dequeue(Thread *tp) { - - tp->p_prev->p_next = tp->p_next; - tp->p_next->p_prev = tp->p_prev; - return tp; -} - -/** - * @brief Pushes a Thread on top of a stack list. - * - * @param[in] tp the pointer to the thread to be inserted in the list - * @param[in] tlp the pointer to the threads list header - * - * @notapi - */ -void list_insert(Thread *tp, ThreadsList *tlp) { - - tp->p_next = tlp->p_next; - tlp->p_next = tp; -} - -/** - * @brief Pops a Thread from the top of a stack list and returns it. - * @pre The list must be non-empty before calling this function. - * - * @param[in] tlp the pointer to the threads list header - * @return The removed thread pointer. - * - * @notapi - */ -Thread *list_remove(ThreadsList *tlp) { - - Thread *tp = tlp->p_next; - tlp->p_next = tp->p_next; - return tp; -} -#endif /* CH_OPTIMIZE_SPEED */ - -/** @} */ diff --git a/firmware/chibios/os/kernel/src/chmboxes.c b/firmware/chibios/os/kernel/src/chmboxes.c deleted file mode 100644 index 1e8855b614..0000000000 --- a/firmware/chibios/os/kernel/src/chmboxes.c +++ /dev/null @@ -1,383 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chmboxes.c - * @brief Mailboxes code. - * - * @addtogroup mailboxes - * @details Asynchronous messages. - *

Operation mode

- * A mailbox is an asynchronous communication mechanism.
- * Operations defined for mailboxes: - * - Post: Posts a message on the mailbox in FIFO order. - * - Post Ahead: Posts a message on the mailbox with urgent - * priority. - * - Fetch: A message is fetched from the mailbox and removed - * from the queue. - * - Reset: The mailbox is emptied and all the stored messages - * are lost. - * . - * A message is a variable of type msg_t that is guaranteed to have - * the same size of and be compatible with (data) pointers (anyway an - * explicit cast is needed). - * If larger messages need to be exchanged then a pointer to a - * structure can be posted in the mailbox but the posting side has - * no predefined way to know when the message has been processed. A - * possible approach is to allocate memory (from a memory pool for - * example) from the posting side and free it on the fetching side. - * Another approach is to set a "done" flag into the structure pointed - * by the message. - * @pre In order to use the mailboxes APIs the @p CH_USE_MAILBOXES option - * must be enabled in @p chconf.h. - * @{ - */ - -#include "ch.h" - -#if CH_USE_MAILBOXES || defined(__DOXYGEN__) -/** - * @brief Initializes a Mailbox object. - * - * @param[out] mbp the pointer to the Mailbox structure to be initialized - * @param[in] buf pointer to the messages buffer as an array of @p msg_t - * @param[in] n number of elements in the buffer array - * - * @init - */ -void chMBInit(Mailbox *mbp, msg_t *buf, cnt_t n) { - - chDbgCheck((mbp != NULL) && (buf != NULL) && (n > 0), "chMBInit"); - - mbp->mb_buffer = mbp->mb_wrptr = mbp->mb_rdptr = buf; - mbp->mb_top = &buf[n]; - chSemInit(&mbp->mb_emptysem, n); - chSemInit(&mbp->mb_fullsem, 0); -} - -/** - * @brief Resets a Mailbox object. - * @details All the waiting threads are resumed with status @p RDY_RESET and - * the queued messages are lost. - * - * @param[in] mbp the pointer to an initialized Mailbox object - * - * @api - */ -void chMBReset(Mailbox *mbp) { - - chDbgCheck(mbp != NULL, "chMBReset"); - - chSysLock(); - mbp->mb_wrptr = mbp->mb_rdptr = mbp->mb_buffer; - chSemResetI(&mbp->mb_emptysem, mbp->mb_top - mbp->mb_buffer); - chSemResetI(&mbp->mb_fullsem, 0); - chSchRescheduleS(); - chSysUnlock(); -} - -/** - * @brief Posts a message into a mailbox. - * @details The invoking thread waits until a empty slot in the mailbox becomes - * available or the specified time runs out. - * - * @param[in] mbp the pointer to an initialized Mailbox object - * @param[in] msg the message to be posted on the mailbox - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval RDY_OK if a message has been correctly posted. - * @retval RDY_RESET if the mailbox has been reset while waiting. - * @retval RDY_TIMEOUT if the operation has timed out. - * - * @api - */ -msg_t chMBPost(Mailbox *mbp, msg_t msg, systime_t time) { - msg_t rdymsg; - - chSysLock(); - rdymsg = chMBPostS(mbp, msg, time); - chSysUnlock(); - return rdymsg; -} - -/** - * @brief Posts a message into a mailbox. - * @details The invoking thread waits until a empty slot in the mailbox becomes - * available or the specified time runs out. - * - * @param[in] mbp the pointer to an initialized Mailbox object - * @param[in] msg the message to be posted on the mailbox - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval RDY_OK if a message has been correctly posted. - * @retval RDY_RESET if the mailbox has been reset while waiting. - * @retval RDY_TIMEOUT if the operation has timed out. - * - * @sclass - */ -msg_t chMBPostS(Mailbox *mbp, msg_t msg, systime_t time) { - msg_t rdymsg; - - chDbgCheckClassS(); - chDbgCheck(mbp != NULL, "chMBPostS"); - - rdymsg = chSemWaitTimeoutS(&mbp->mb_emptysem, time); - if (rdymsg == RDY_OK) { - *mbp->mb_wrptr++ = msg; - if (mbp->mb_wrptr >= mbp->mb_top) - mbp->mb_wrptr = mbp->mb_buffer; - chSemSignalI(&mbp->mb_fullsem); - chSchRescheduleS(); - } - return rdymsg; -} - -/** - * @brief Posts a message into a mailbox. - * @details This variant is non-blocking, the function returns a timeout - * condition if the queue is full. - * - * @param[in] mbp the pointer to an initialized Mailbox object - * @param[in] msg the message to be posted on the mailbox - * @return The operation status. - * @retval RDY_OK if a message has been correctly posted. - * @retval RDY_TIMEOUT if the mailbox is full and the message cannot be - * posted. - * - * @iclass - */ -msg_t chMBPostI(Mailbox *mbp, msg_t msg) { - - chDbgCheckClassI(); - chDbgCheck(mbp != NULL, "chMBPostI"); - - if (chSemGetCounterI(&mbp->mb_emptysem) <= 0) - return RDY_TIMEOUT; - chSemFastWaitI(&mbp->mb_emptysem); - *mbp->mb_wrptr++ = msg; - if (mbp->mb_wrptr >= mbp->mb_top) - mbp->mb_wrptr = mbp->mb_buffer; - chSemSignalI(&mbp->mb_fullsem); - return RDY_OK; -} - -/** - * @brief Posts an high priority message into a mailbox. - * @details The invoking thread waits until a empty slot in the mailbox becomes - * available or the specified time runs out. - * - * @param[in] mbp the pointer to an initialized Mailbox object - * @param[in] msg the message to be posted on the mailbox - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval RDY_OK if a message has been correctly posted. - * @retval RDY_RESET if the mailbox has been reset while waiting. - * @retval RDY_TIMEOUT if the operation has timed out. - * - * @api - */ -msg_t chMBPostAhead(Mailbox *mbp, msg_t msg, systime_t time) { - msg_t rdymsg; - - chSysLock(); - rdymsg = chMBPostAheadS(mbp, msg, time); - chSysUnlock(); - return rdymsg; -} - -/** - * @brief Posts an high priority message into a mailbox. - * @details The invoking thread waits until a empty slot in the mailbox becomes - * available or the specified time runs out. - * - * @param[in] mbp the pointer to an initialized Mailbox object - * @param[in] msg the message to be posted on the mailbox - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval RDY_OK if a message has been correctly posted. - * @retval RDY_RESET if the mailbox has been reset while waiting. - * @retval RDY_TIMEOUT if the operation has timed out. - * - * @sclass - */ -msg_t chMBPostAheadS(Mailbox *mbp, msg_t msg, systime_t time) { - msg_t rdymsg; - - chDbgCheckClassS(); - chDbgCheck(mbp != NULL, "chMBPostAheadS"); - - rdymsg = chSemWaitTimeoutS(&mbp->mb_emptysem, time); - if (rdymsg == RDY_OK) { - if (--mbp->mb_rdptr < mbp->mb_buffer) - mbp->mb_rdptr = mbp->mb_top - 1; - *mbp->mb_rdptr = msg; - chSemSignalI(&mbp->mb_fullsem); - chSchRescheduleS(); - } - return rdymsg; -} - -/** - * @brief Posts an high priority message into a mailbox. - * @details This variant is non-blocking, the function returns a timeout - * condition if the queue is full. - * - * @param[in] mbp the pointer to an initialized Mailbox object - * @param[in] msg the message to be posted on the mailbox - * @return The operation status. - * @retval RDY_OK if a message has been correctly posted. - * @retval RDY_TIMEOUT if the mailbox is full and the message cannot be - * posted. - * - * @iclass - */ -msg_t chMBPostAheadI(Mailbox *mbp, msg_t msg) { - - chDbgCheckClassI(); - chDbgCheck(mbp != NULL, "chMBPostAheadI"); - - if (chSemGetCounterI(&mbp->mb_emptysem) <= 0) - return RDY_TIMEOUT; - chSemFastWaitI(&mbp->mb_emptysem); - if (--mbp->mb_rdptr < mbp->mb_buffer) - mbp->mb_rdptr = mbp->mb_top - 1; - *mbp->mb_rdptr = msg; - chSemSignalI(&mbp->mb_fullsem); - return RDY_OK; -} - -/** - * @brief Retrieves a message from a mailbox. - * @details The invoking thread waits until a message is posted in the mailbox - * or the specified time runs out. - * - * @param[in] mbp the pointer to an initialized Mailbox object - * @param[out] msgp pointer to a message variable for the received message - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval RDY_OK if a message has been correctly fetched. - * @retval RDY_RESET if the mailbox has been reset while waiting. - * @retval RDY_TIMEOUT if the operation has timed out. - * - * @api - */ -msg_t chMBFetch(Mailbox *mbp, msg_t *msgp, systime_t time) { - msg_t rdymsg; - - chSysLock(); - rdymsg = chMBFetchS(mbp, msgp, time); - chSysUnlock(); - return rdymsg; -} - -/** - * @brief Retrieves a message from a mailbox. - * @details The invoking thread waits until a message is posted in the mailbox - * or the specified time runs out. - * - * @param[in] mbp the pointer to an initialized Mailbox object - * @param[out] msgp pointer to a message variable for the received message - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval RDY_OK if a message has been correctly fetched. - * @retval RDY_RESET if the mailbox has been reset while waiting. - * @retval RDY_TIMEOUT if the operation has timed out. - * - * @sclass - */ -msg_t chMBFetchS(Mailbox *mbp, msg_t *msgp, systime_t time) { - msg_t rdymsg; - - chDbgCheckClassS(); - chDbgCheck((mbp != NULL) && (msgp != NULL), "chMBFetchS"); - - rdymsg = chSemWaitTimeoutS(&mbp->mb_fullsem, time); - if (rdymsg == RDY_OK) { - *msgp = *mbp->mb_rdptr++; - if (mbp->mb_rdptr >= mbp->mb_top) - mbp->mb_rdptr = mbp->mb_buffer; - chSemSignalI(&mbp->mb_emptysem); - chSchRescheduleS(); - } - return rdymsg; -} - -/** - * @brief Retrieves a message from a mailbox. - * @details This variant is non-blocking, the function returns a timeout - * condition if the queue is empty. - * - * @param[in] mbp the pointer to an initialized Mailbox object - * @param[out] msgp pointer to a message variable for the received message - * @return The operation status. - * @retval RDY_OK if a message has been correctly fetched. - * @retval RDY_TIMEOUT if the mailbox is empty and a message cannot be - * fetched. - * - * @iclass - */ -msg_t chMBFetchI(Mailbox *mbp, msg_t *msgp) { - - chDbgCheckClassI(); - chDbgCheck((mbp != NULL) && (msgp != NULL), "chMBFetchI"); - - if (chSemGetCounterI(&mbp->mb_fullsem) <= 0) - return RDY_TIMEOUT; - chSemFastWaitI(&mbp->mb_fullsem); - *msgp = *mbp->mb_rdptr++; - if (mbp->mb_rdptr >= mbp->mb_top) - mbp->mb_rdptr = mbp->mb_buffer; - chSemSignalI(&mbp->mb_emptysem); - return RDY_OK; -} -#endif /* CH_USE_MAILBOXES */ - -/** @} */ diff --git a/firmware/chibios/os/kernel/src/chmemcore.c b/firmware/chibios/os/kernel/src/chmemcore.c deleted file mode 100644 index 9a744627c5..0000000000 --- a/firmware/chibios/os/kernel/src/chmemcore.c +++ /dev/null @@ -1,138 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chmemcore.c - * @brief Core memory manager code. - * - * @addtogroup memcore - * @details Core Memory Manager related APIs and services. - *

Operation mode

- * The core memory manager is a simplified allocator that only - * allows to allocate memory blocks without the possibility to - * free them.
- * This allocator is meant as a memory blocks provider for the - * other allocators such as: - * - C-Runtime allocator (through a compiler specific adapter module). - * - Heap allocator (see @ref heaps). - * - Memory pools allocator (see @ref pools). - * . - * By having a centralized memory provider the various allocators - * can coexist and share the main memory.
- * This allocator, alone, is also useful for very simple - * applications that just require a simple way to get memory - * blocks. - * @pre In order to use the core memory manager APIs the @p CH_USE_MEMCORE - * option must be enabled in @p chconf.h. - * @{ - */ - -#include "ch.h" - -#if CH_USE_MEMCORE || defined(__DOXYGEN__) - -static uint8_t *nextmem; -static uint8_t *endmem; - -/** - * @brief Low level memory manager initialization. - * - * @notapi - */ -void _core_init(void) { -#if CH_MEMCORE_SIZE == 0 - extern uint8_t __heap_base__[]; - extern uint8_t __heap_end__[]; - nextmem = (uint8_t *)MEM_ALIGN_NEXT(__heap_base__); - endmem = (uint8_t *)MEM_ALIGN_PREV(__heap_end__); -#else - static stkalign_t buffer[MEM_ALIGN_NEXT(CH_MEMCORE_SIZE)/MEM_ALIGN_SIZE]; - nextmem = (uint8_t *)&buffer[0]; - endmem = (uint8_t *)&buffer[MEM_ALIGN_NEXT(CH_MEMCORE_SIZE)/MEM_ALIGN_SIZE]; -#endif -} - -/** - * @brief Allocates a memory block. - * @details The size of the returned block is aligned to the alignment - * type so it is not possible to allocate less - * than MEM_ALIGN_SIZE. - * - * @param[in] size the size of the block to be allocated - * @return A pointer to the allocated memory block. - * @retval NULL allocation failed, core memory exhausted. - * - * @api - */ -void *chCoreAlloc(size_t size) { - void *p; - - chSysLock(); - p = chCoreAllocI(size); - chSysUnlock(); - return p; -} - -/** - * @brief Allocates a memory block. - * @details The size of the returned block is aligned to the alignment - * type so it is not possible to allocate less than - * MEM_ALIGN_SIZE. - * - * @param[in] size the size of the block to be allocated. - * @return A pointer to the allocated memory block. - * @retval NULL allocation failed, core memory exhausted. - * - * @iclass - */ -void *chCoreAllocI(size_t size) { - void *p; - - chDbgCheckClassI(); - - size = MEM_ALIGN_NEXT(size); - if ((size_t)(endmem - nextmem) < size) - return NULL; - p = nextmem; - nextmem += size; - return p; -} - -/** - * @brief Core memory status. - * - * @return The size, in bytes, of the free core memory. - * - * @api - */ -size_t chCoreStatus(void) { - - return (size_t)(endmem - nextmem); -} -#endif /* CH_USE_MEMCORE */ - -/** @} */ diff --git a/firmware/chibios/os/kernel/src/chmempools.c b/firmware/chibios/os/kernel/src/chmempools.c deleted file mode 100644 index 842e20aa34..0000000000 --- a/firmware/chibios/os/kernel/src/chmempools.c +++ /dev/null @@ -1,180 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chmempools.c - * @brief Memory Pools code. - * - * @addtogroup pools - * @details Memory Pools related APIs and services. - *

Operation mode

- * The Memory Pools APIs allow to allocate/free fixed size objects in - * constant time and reliably without memory fragmentation - * problems.
- * Memory Pools do not enforce any alignment constraint on the - * contained object however the objects must be properly aligned - * to contain a pointer to void. - * @pre In order to use the memory pools APIs the @p CH_USE_MEMPOOLS option - * must be enabled in @p chconf.h. - * @{ - */ - -#include "ch.h" - -#if CH_USE_MEMPOOLS || defined(__DOXYGEN__) -/** - * @brief Initializes an empty memory pool. - * - * @param[out] mp pointer to a @p MemoryPool structure - * @param[in] size the size of the objects contained in this memory pool, - * the minimum accepted size is the size of a pointer to - * void. - * @param[in] provider memory provider function for the memory pool or - * @p NULL if the pool is not allowed to grow - * automatically - * - * @init - */ -void chPoolInit(MemoryPool *mp, size_t size, memgetfunc_t provider) { - - chDbgCheck((mp != NULL) && (size >= sizeof(void *)), "chPoolInit"); - - mp->mp_next = NULL; - mp->mp_object_size = size; - mp->mp_provider = provider; -} - -/** - * @brief Loads a memory pool with an array of static objects. - * @pre The memory pool must be already been initialized. - * @pre The array elements must be of the right size for the specified - * memory pool. - * @post The memory pool contains the elements of the input array. - * - * @param[in] mp pointer to a @p MemoryPool structure - * @param[in] p pointer to the array first element - * @param[in] n number of elements in the array - * - * @api - */ -void chPoolLoadArray(MemoryPool *mp, void *p, size_t n) { - - chDbgCheck((mp != NULL) && (n != 0), "chPoolLoadArray"); - - while (n) { - chPoolAdd(mp, p); - p = (void *)(((uint8_t *)p) + mp->mp_object_size); - n--; - } -} - -/** - * @brief Allocates an object from a memory pool. - * @pre The memory pool must be already been initialized. - * - * @param[in] mp pointer to a @p MemoryPool structure - * @return The pointer to the allocated object. - * @retval NULL if pool is empty. - * - * @iclass - */ -void *chPoolAllocI(MemoryPool *mp) { - void *objp; - - chDbgCheckClassI(); - chDbgCheck(mp != NULL, "chPoolAllocI"); - - if ((objp = mp->mp_next) != NULL) - mp->mp_next = mp->mp_next->ph_next; - else if (mp->mp_provider != NULL) - objp = mp->mp_provider(mp->mp_object_size); - return objp; -} - -/** - * @brief Allocates an object from a memory pool. - * @pre The memory pool must be already been initialized. - * - * @param[in] mp pointer to a @p MemoryPool structure - * @return The pointer to the allocated object. - * @retval NULL if pool is empty. - * - * @api - */ -void *chPoolAlloc(MemoryPool *mp) { - void *objp; - - chSysLock(); - objp = chPoolAllocI(mp); - chSysUnlock(); - return objp; -} - -/** - * @brief Releases an object into a memory pool. - * @pre The memory pool must be already been initialized. - * @pre The freed object must be of the right size for the specified - * memory pool. - * @pre The object must be properly aligned to contain a pointer to void. - * - * @param[in] mp pointer to a @p MemoryPool structure - * @param[in] objp the pointer to the object to be released - * - * @iclass - */ -void chPoolFreeI(MemoryPool *mp, void *objp) { - struct pool_header *php = objp; - - chDbgCheckClassI(); - chDbgCheck((mp != NULL) && (objp != NULL), "chPoolFreeI"); - - php->ph_next = mp->mp_next; - mp->mp_next = php; -} - -/** - * @brief Releases an object into a memory pool. - * @pre The memory pool must be already been initialized. - * @pre The freed object must be of the right size for the specified - * memory pool. - * @pre The object must be properly aligned to contain a pointer to void. - * - * @param[in] mp pointer to a @p MemoryPool structure - * @param[in] objp the pointer to the object to be released - * - * @api - */ -void chPoolFree(MemoryPool *mp, void *objp) { - - chSysLock(); - chPoolFreeI(mp, objp); - chSysUnlock(); -} - -#endif /* CH_USE_MEMPOOLS */ - -/** @} */ diff --git a/firmware/chibios/os/kernel/src/chmsg.c b/firmware/chibios/os/kernel/src/chmsg.c deleted file mode 100644 index e18c09633c..0000000000 --- a/firmware/chibios/os/kernel/src/chmsg.c +++ /dev/null @@ -1,139 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chmsg.c - * @brief Messages code. - * - * @addtogroup messages - * @details Synchronous inter-thread messages APIs and services. - *

Operation Mode

- * Synchronous messages are an easy to use and fast IPC mechanism, - * threads can both act as message servers and/or message clients, - * the mechanism allows data to be carried in both directions. Note - * that messages are not copied between the client and server threads - * but just a pointer passed so the exchange is very time - * efficient.
- * Messages are scalar data types of type @p msg_t that are guaranteed - * to be size compatible with data pointers. Note that on some - * architectures function pointers can be larger that @p msg_t.
- * Messages are usually processed in FIFO order but it is possible to - * process them in priority order by enabling the - * @p CH_USE_MESSAGES_PRIORITY option in @p chconf.h.
- * @pre In order to use the message APIs the @p CH_USE_MESSAGES option - * must be enabled in @p chconf.h. - * @post Enabling messages requires 6-12 (depending on the architecture) - * extra bytes in the @p Thread structure. - * @{ - */ - -#include "ch.h" - -#if CH_USE_MESSAGES || defined(__DOXYGEN__) - -#if CH_USE_MESSAGES_PRIORITY -#define msg_insert(tp, qp) prio_insert(tp, qp) -#else -#define msg_insert(tp, qp) queue_insert(tp, qp) -#endif - -/** - * @brief Sends a message to the specified thread. - * @details The sender is stopped until the receiver executes a - * @p chMsgRelease()after receiving the message. - * - * @param[in] tp the pointer to the thread - * @param[in] msg the message - * @return The answer message from @p chMsgRelease(). - * - * @api - */ -msg_t chMsgSend(Thread *tp, msg_t msg) { - Thread *ctp = currp; - - chDbgCheck(tp != NULL, "chMsgSend"); - - chSysLock(); - ctp->p_msg = msg; - ctp->p_u.wtobjp = &tp->p_msgqueue; - msg_insert(ctp, &tp->p_msgqueue); - if (tp->p_state == THD_STATE_WTMSG) - chSchReadyI(tp); - chSchGoSleepS(THD_STATE_SNDMSGQ); - msg = ctp->p_u.rdymsg; - chSysUnlock(); - return msg; -} - -/** - * @brief Suspends the thread and waits for an incoming message. - * @post After receiving a message the function @p chMsgGet() must be - * called in order to retrieve the message and then @p chMsgRelease() - * must be invoked in order to acknowledge the reception and send - * the answer. - * @note If the message is a pointer then you can assume that the data - * pointed by the message is stable until you invoke @p chMsgRelease() - * because the sending thread is suspended until then. - * - * @return A reference to the thread carrying the message. - * - * @api - */ -Thread *chMsgWait(void) { - Thread *tp; - - chSysLock(); - if (!chMsgIsPendingI(currp)) - chSchGoSleepS(THD_STATE_WTMSG); - tp = fifo_remove(&currp->p_msgqueue); - tp->p_state = THD_STATE_SNDMSG; - chSysUnlock(); - return tp; -} - -/** - * @brief Releases a sender thread specifying a response message. - * @pre Invoke this function only after a message has been received - * using @p chMsgWait(). - * - * @param[in] tp pointer to the thread - * @param[in] msg message to be returned to the sender - * - * @api - */ -void chMsgRelease(Thread *tp, msg_t msg) { - - chSysLock(); - chDbgAssert(tp->p_state == THD_STATE_SNDMSG, - "chMsgRelease(), #1", "invalid state"); - chMsgReleaseS(tp, msg); - chSysUnlock(); -} - -#endif /* CH_USE_MESSAGES */ - -/** @} */ diff --git a/firmware/chibios/os/kernel/src/chmtx.c b/firmware/chibios/os/kernel/src/chmtx.c deleted file mode 100644 index 08b7de5885..0000000000 --- a/firmware/chibios/os/kernel/src/chmtx.c +++ /dev/null @@ -1,400 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chmtx.c - * @brief Mutexes code. - * - * @addtogroup mutexes - * @details Mutexes related APIs and services. - * - *

Operation mode

- * A mutex is a threads synchronization object that can be in two - * distinct states: - * - Not owned (unlocked). - * - Owned by a thread (locked). - * . - * Operations defined for mutexes: - * - Lock: The mutex is checked, if the mutex is not owned by - * some other thread then it is associated to the locking thread - * else the thread is queued on the mutex in a list ordered by - * priority. - * - Unlock: The mutex is released by the owner and the highest - * priority thread waiting in the queue, if any, is resumed and made - * owner of the mutex. - * . - *

Constraints

- * In ChibiOS/RT the Unlock operations are always performed in - * lock-reverse order. The unlock API does not even have a parameter, - * the mutex to unlock is selected from an internal, per-thread, stack - * of owned mutexes. This both improves the performance and is - * required for an efficient implementation of the priority - * inheritance mechanism. - * - *

The priority inversion problem

- * The mutexes in ChibiOS/RT implements the full priority - * inheritance mechanism in order handle the priority inversion - * problem.
- * When a thread is queued on a mutex, any thread, directly or - * indirectly, holding the mutex gains the same priority of the - * waiting thread (if their priority was not already equal or higher). - * The mechanism works with any number of nested mutexes and any - * number of involved threads. The algorithm complexity (worst case) - * is N with N equal to the number of nested mutexes. - * @pre In order to use the mutex APIs the @p CH_USE_MUTEXES option - * must be enabled in @p chconf.h. - * @post Enabling mutexes requires 5-12 (depending on the architecture) - * extra bytes in the @p Thread structure. - * @{ - */ - -#include "ch.h" - -#if CH_USE_MUTEXES || defined(__DOXYGEN__) - -/** - * @brief Initializes s @p Mutex structure. - * - * @param[out] mp pointer to a @p Mutex structure - * - * @init - */ -void chMtxInit(Mutex *mp) { - - chDbgCheck(mp != NULL, "chMtxInit"); - - queue_init(&mp->m_queue); - mp->m_owner = NULL; -} - -/** - * @brief Locks the specified mutex. - * @post The mutex is locked and inserted in the per-thread stack of owned - * mutexes. - * - * @param[in] mp pointer to the @p Mutex structure - * - * @api - */ -void chMtxLock(Mutex *mp) { - - chSysLock(); - - chMtxLockS(mp); - - chSysUnlock(); -} - -/** - * @brief Locks the specified mutex. - * @post The mutex is locked and inserted in the per-thread stack of owned - * mutexes. - * - * @param[in] mp pointer to the @p Mutex structure - * - * @sclass - */ -void chMtxLockS(Mutex *mp) { - Thread *ctp = currp; - - chDbgCheckClassS(); - chDbgCheck(mp != NULL, "chMtxLockS"); - - /* Is the mutex already locked? */ - if (mp->m_owner != NULL) { - /* Priority inheritance protocol; explores the thread-mutex dependencies - boosting the priority of all the affected threads to equal the priority - of the running thread requesting the mutex.*/ - Thread *tp = mp->m_owner; - /* Does the running thread have higher priority than the mutex - owning thread? */ - while (tp->p_prio < ctp->p_prio) { - /* Make priority of thread tp match the running thread's priority.*/ - tp->p_prio = ctp->p_prio; - /* The following states need priority queues reordering.*/ - switch (tp->p_state) { - case THD_STATE_WTMTX: - /* Re-enqueues the mutex owner with its new priority.*/ - prio_insert(dequeue(tp), (ThreadsQueue *)tp->p_u.wtobjp); - tp = ((Mutex *)tp->p_u.wtobjp)->m_owner; - continue; -#if CH_USE_CONDVARS || \ - (CH_USE_SEMAPHORES && CH_USE_SEMAPHORES_PRIORITY) || \ - (CH_USE_MESSAGES && CH_USE_MESSAGES_PRIORITY) -#if CH_USE_CONDVARS - case THD_STATE_WTCOND: -#endif -#if CH_USE_SEMAPHORES && CH_USE_SEMAPHORES_PRIORITY - case THD_STATE_WTSEM: -#endif -#if CH_USE_MESSAGES && CH_USE_MESSAGES_PRIORITY - case THD_STATE_SNDMSGQ: -#endif - /* Re-enqueues tp with its new priority on the queue.*/ - prio_insert(dequeue(tp), (ThreadsQueue *)tp->p_u.wtobjp); - break; -#endif - case THD_STATE_READY: -#if CH_DBG_ENABLE_ASSERTS - /* Prevents an assertion in chSchReadyI().*/ - tp->p_state = THD_STATE_CURRENT; -#endif - /* Re-enqueues tp with its new priority on the ready list.*/ - chSchReadyI(dequeue(tp)); - break; - } - break; - } - /* Sleep on the mutex.*/ - prio_insert(ctp, &mp->m_queue); - ctp->p_u.wtobjp = mp; - chSchGoSleepS(THD_STATE_WTMTX); - /* It is assumed that the thread performing the unlock operation assigns - the mutex to this thread.*/ - chDbgAssert(mp->m_owner == ctp, "chMtxLockS(), #1", "not owner"); - chDbgAssert(ctp->p_mtxlist == mp, "chMtxLockS(), #2", "not owned"); - } - else { - /* It was not owned, inserted in the owned mutexes list.*/ - mp->m_owner = ctp; - mp->m_next = ctp->p_mtxlist; - ctp->p_mtxlist = mp; - } -} - -/** - * @brief Tries to lock a mutex. - * @details This function attempts to lock a mutex, if the mutex is already - * locked by another thread then the function exits without waiting. - * @post The mutex is locked and inserted in the per-thread stack of owned - * mutexes. - * @note This function does not have any overhead related to the - * priority inheritance mechanism because it does not try to - * enter a sleep state. - * - * @param[in] mp pointer to the @p Mutex structure - * @return The operation status. - * @retval TRUE if the mutex has been successfully acquired - * @retval FALSE if the lock attempt failed. - * - * @api - */ -bool_t chMtxTryLock(Mutex *mp) { - bool_t b; - - chSysLock(); - - b = chMtxTryLockS(mp); - - chSysUnlock(); - return b; -} - -/** - * @brief Tries to lock a mutex. - * @details This function attempts to lock a mutex, if the mutex is already - * taken by another thread then the function exits without waiting. - * @post The mutex is locked and inserted in the per-thread stack of owned - * mutexes. - * @note This function does not have any overhead related to the - * priority inheritance mechanism because it does not try to - * enter a sleep state. - * - * @param[in] mp pointer to the @p Mutex structure - * @return The operation status. - * @retval TRUE if the mutex has been successfully acquired - * @retval FALSE if the lock attempt failed. - * - * @sclass - */ -bool_t chMtxTryLockS(Mutex *mp) { - - chDbgCheckClassS(); - chDbgCheck(mp != NULL, "chMtxTryLockS"); - - if (mp->m_owner != NULL) - return FALSE; - mp->m_owner = currp; - mp->m_next = currp->p_mtxlist; - currp->p_mtxlist = mp; - return TRUE; -} - -/** - * @brief Unlocks the next owned mutex in reverse lock order. - * @pre The invoking thread must have at least one owned mutex. - * @post The mutex is unlocked and removed from the per-thread stack of - * owned mutexes. - * - * @return A pointer to the unlocked mutex. - * - * @api - */ -Mutex *chMtxUnlock(void) { - Thread *ctp = currp; - Mutex *ump, *mp; - - chSysLock(); - chDbgAssert(ctp->p_mtxlist != NULL, - "chMtxUnlock(), #1", - "owned mutexes list empty"); - chDbgAssert(ctp->p_mtxlist->m_owner == ctp, - "chMtxUnlock(), #2", - "ownership failure"); - /* Removes the top Mutex from the Thread's owned mutexes list and marks it - as not owned.*/ - ump = ctp->p_mtxlist; - ctp->p_mtxlist = ump->m_next; - /* If a thread is waiting on the mutex then the fun part begins.*/ - if (chMtxQueueNotEmptyS(ump)) { - Thread *tp; - - /* Recalculates the optimal thread priority by scanning the owned - mutexes list.*/ - tprio_t newprio = ctp->p_realprio; - mp = ctp->p_mtxlist; - while (mp != NULL) { - /* If the highest priority thread waiting in the mutexes list has a - greater priority than the current thread base priority then the final - priority will have at least that priority.*/ - if (chMtxQueueNotEmptyS(mp) && (mp->m_queue.p_next->p_prio > newprio)) - newprio = mp->m_queue.p_next->p_prio; - mp = mp->m_next; - } - /* Assigns to the current thread the highest priority among all the - waiting threads.*/ - ctp->p_prio = newprio; - /* Awakens the highest priority thread waiting for the unlocked mutex and - assigns the mutex to it.*/ - tp = fifo_remove(&ump->m_queue); - ump->m_owner = tp; - ump->m_next = tp->p_mtxlist; - tp->p_mtxlist = ump; - chSchWakeupS(tp, RDY_OK); - } - else - ump->m_owner = NULL; - chSysUnlock(); - return ump; -} - -/** - * @brief Unlocks the next owned mutex in reverse lock order. - * @pre The invoking thread must have at least one owned mutex. - * @post The mutex is unlocked and removed from the per-thread stack of - * owned mutexes. - * @post This function does not reschedule so a call to a rescheduling - * function must be performed before unlocking the kernel. - * - * @return A pointer to the unlocked mutex. - * - * @sclass - */ -Mutex *chMtxUnlockS(void) { - Thread *ctp = currp; - Mutex *ump, *mp; - - chDbgCheckClassS(); - chDbgAssert(ctp->p_mtxlist != NULL, - "chMtxUnlockS(), #1", - "owned mutexes list empty"); - chDbgAssert(ctp->p_mtxlist->m_owner == ctp, - "chMtxUnlockS(), #2", - "ownership failure"); - - /* Removes the top Mutex from the owned mutexes list and marks it as not - owned.*/ - ump = ctp->p_mtxlist; - ctp->p_mtxlist = ump->m_next; - /* If a thread is waiting on the mutex then the fun part begins.*/ - if (chMtxQueueNotEmptyS(ump)) { - Thread *tp; - - /* Recalculates the optimal thread priority by scanning the owned - mutexes list.*/ - tprio_t newprio = ctp->p_realprio; - mp = ctp->p_mtxlist; - while (mp != NULL) { - /* If the highest priority thread waiting in the mutexes list has a - greater priority than the current thread base priority then the final - priority will have at least that priority.*/ - if (chMtxQueueNotEmptyS(mp) && (mp->m_queue.p_next->p_prio > newprio)) - newprio = mp->m_queue.p_next->p_prio; - mp = mp->m_next; - } - ctp->p_prio = newprio; - /* Awakens the highest priority thread waiting for the unlocked mutex and - assigns the mutex to it.*/ - tp = fifo_remove(&ump->m_queue); - ump->m_owner = tp; - ump->m_next = tp->p_mtxlist; - tp->p_mtxlist = ump; - chSchReadyI(tp); - } - else - ump->m_owner = NULL; - return ump; -} - -/** - * @brief Unlocks all the mutexes owned by the invoking thread. - * @post The stack of owned mutexes is emptied and all the found - * mutexes are unlocked. - * @note This function is MUCH MORE efficient than releasing the - * mutexes one by one and not just because the call overhead, - * this function does not have any overhead related to the priority - * inheritance mechanism. - * - * @api - */ -void chMtxUnlockAll(void) { - Thread *ctp = currp; - - chSysLock(); - if (ctp->p_mtxlist != NULL) { - do { - Mutex *ump = ctp->p_mtxlist; - ctp->p_mtxlist = ump->m_next; - if (chMtxQueueNotEmptyS(ump)) { - Thread *tp = fifo_remove(&ump->m_queue); - ump->m_owner = tp; - ump->m_next = tp->p_mtxlist; - tp->p_mtxlist = ump; - chSchReadyI(tp); - } - else - ump->m_owner = NULL; - } while (ctp->p_mtxlist != NULL); - ctp->p_prio = ctp->p_realprio; - chSchRescheduleS(); - } - chSysUnlock(); -} - -#endif /* CH_USE_MUTEXES */ - -/** @} */ diff --git a/firmware/chibios/os/kernel/src/chqueues.c b/firmware/chibios/os/kernel/src/chqueues.c deleted file mode 100644 index 22986badef..0000000000 --- a/firmware/chibios/os/kernel/src/chqueues.c +++ /dev/null @@ -1,438 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chqueues.c - * @brief I/O Queues code. - * - * @addtogroup io_queues - * @details ChibiOS/RT queues are mostly used in serial-like device drivers. - * The device drivers are usually designed to have a lower side - * (lower driver, it is usually an interrupt service routine) and an - * upper side (upper driver, accessed by the application threads).
- * There are several kind of queues:
- * - Input queue, unidirectional queue where the writer is the - * lower side and the reader is the upper side. - * - Output queue, unidirectional queue where the writer is the - * upper side and the reader is the lower side. - * - Full duplex queue, bidirectional queue. Full duplex queues - * are implemented by pairing an input queue and an output queue - * together. - * . - * @pre In order to use the I/O queues the @p CH_USE_QUEUES option must - * be enabled in @p chconf.h. - * @{ - */ - -#include "ch.h" - -#if CH_USE_QUEUES || defined(__DOXYGEN__) - -/** - * @brief Puts the invoking thread into the queue's threads queue. - * - * @param[out] qp pointer to an @p GenericQueue structure - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return A message specifying how the invoking thread has been - * released from threads queue. - * @retval Q_OK is the normal exit, thread signaled. - * @retval Q_RESET if the queue has been reset. - * @retval Q_TIMEOUT if the queue operation timed out. - */ -static msg_t qwait(GenericQueue *qp, systime_t time) { - - if (TIME_IMMEDIATE == time) - return Q_TIMEOUT; - currp->p_u.wtobjp = qp; - queue_insert(currp, &qp->q_waiting); - return chSchGoSleepTimeoutS(THD_STATE_WTQUEUE, time); -} - -/** - * @brief Initializes an input queue. - * @details A Semaphore is internally initialized and works as a counter of - * the bytes contained in the queue. - * @note The callback is invoked from within the S-Locked system state, - * see @ref system_states. - * - * @param[out] iqp pointer to an @p InputQueue structure - * @param[in] bp pointer to a memory area allocated as queue buffer - * @param[in] size size of the queue buffer - * @param[in] infy pointer to a callback function that is invoked when - * data is read from the queue. The value can be @p NULL. - * @param[in] link application defined pointer - * - * @init - */ -void chIQInit(InputQueue *iqp, uint8_t *bp, size_t size, qnotify_t infy, - void *link) { - - queue_init(&iqp->q_waiting); - iqp->q_counter = 0; - iqp->q_buffer = iqp->q_rdptr = iqp->q_wrptr = bp; - iqp->q_top = bp + size; - iqp->q_notify = infy; - iqp->q_link = link; -} - -/** - * @brief Resets an input queue. - * @details All the data in the input queue is erased and lost, any waiting - * thread is resumed with status @p Q_RESET. - * @note A reset operation can be used by a low level driver in order to - * obtain immediate attention from the high level layers. - * - * @param[in] iqp pointer to an @p InputQueue structure - * - * @iclass - */ -void chIQResetI(InputQueue *iqp) { - - chDbgCheckClassI(); - - iqp->q_rdptr = iqp->q_wrptr = iqp->q_buffer; - iqp->q_counter = 0; - while (notempty(&iqp->q_waiting)) - chSchReadyI(fifo_remove(&iqp->q_waiting))->p_u.rdymsg = Q_RESET; -} - -/** - * @brief Input queue write. - * @details A byte value is written into the low end of an input queue. - * - * @param[in] iqp pointer to an @p InputQueue structure - * @param[in] b the byte value to be written in the queue - * @return The operation status. - * @retval Q_OK if the operation has been completed with success. - * @retval Q_FULL if the queue is full and the operation cannot be - * completed. - * - * @iclass - */ -msg_t chIQPutI(InputQueue *iqp, uint8_t b) { - - chDbgCheckClassI(); - - if (chIQIsFullI(iqp)) - return Q_FULL; - - iqp->q_counter++; - *iqp->q_wrptr++ = b; - if (iqp->q_wrptr >= iqp->q_top) - iqp->q_wrptr = iqp->q_buffer; - - if (notempty(&iqp->q_waiting)) - chSchReadyI(fifo_remove(&iqp->q_waiting))->p_u.rdymsg = Q_OK; - - return Q_OK; -} - -/** - * @brief Input queue read with timeout. - * @details This function reads a byte value from an input queue. If the queue - * is empty then the calling thread is suspended until a byte arrives - * in the queue or a timeout occurs. - * @note The callback is invoked before reading the character from the - * buffer or before entering the state @p THD_STATE_WTQUEUE. - * - * @param[in] iqp pointer to an @p InputQueue structure - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return A byte value from the queue. - * @retval Q_TIMEOUT if the specified time expired. - * @retval Q_RESET if the queue has been reset. - * - * @api - */ -msg_t chIQGetTimeout(InputQueue *iqp, systime_t time) { - uint8_t b; - - chSysLock(); - if (iqp->q_notify) - iqp->q_notify(iqp); - - while (chIQIsEmptyI(iqp)) { - msg_t msg; - if ((msg = qwait((GenericQueue *)iqp, time)) < Q_OK) { - chSysUnlock(); - return msg; - } - } - - iqp->q_counter--; - b = *iqp->q_rdptr++; - if (iqp->q_rdptr >= iqp->q_top) - iqp->q_rdptr = iqp->q_buffer; - - chSysUnlock(); - return b; -} - -/** - * @brief Input queue read with timeout. - * @details The function reads data from an input queue into a buffer. The - * operation completes when the specified amount of data has been - * transferred or after the specified timeout or if the queue has - * been reset. - * @note The function is not atomic, if you need atomicity it is suggested - * to use a semaphore or a mutex for mutual exclusion. - * @note The callback is invoked before reading each character from the - * buffer or before entering the state @p THD_STATE_WTQUEUE. - * - * @param[in] iqp pointer to an @p InputQueue structure - * @param[out] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred, the - * value 0 is reserved - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The number of bytes effectively transferred. - * - * @api - */ -size_t chIQReadTimeout(InputQueue *iqp, uint8_t *bp, - size_t n, systime_t time) { - qnotify_t nfy = iqp->q_notify; - size_t r = 0; - - chDbgCheck(n > 0, "chIQReadTimeout"); - - chSysLock(); - while (TRUE) { - if (nfy) - nfy(iqp); - - while (chIQIsEmptyI(iqp)) { - if (qwait((GenericQueue *)iqp, time) != Q_OK) { - chSysUnlock(); - return r; - } - } - - iqp->q_counter--; - *bp++ = *iqp->q_rdptr++; - if (iqp->q_rdptr >= iqp->q_top) - iqp->q_rdptr = iqp->q_buffer; - - chSysUnlock(); /* Gives a preemption chance in a controlled point.*/ - r++; - if (--n == 0) - return r; - - chSysLock(); - } -} - -/** - * @brief Initializes an output queue. - * @details A Semaphore is internally initialized and works as a counter of - * the free bytes in the queue. - * @note The callback is invoked from within the S-Locked system state, - * see @ref system_states. - * - * @param[out] oqp pointer to an @p OutputQueue structure - * @param[in] bp pointer to a memory area allocated as queue buffer - * @param[in] size size of the queue buffer - * @param[in] onfy pointer to a callback function that is invoked when - * data is written to the queue. The value can be @p NULL. - * @param[in] link application defined pointer - * - * @init - */ -void chOQInit(OutputQueue *oqp, uint8_t *bp, size_t size, qnotify_t onfy, - void *link) { - - queue_init(&oqp->q_waiting); - oqp->q_counter = size; - oqp->q_buffer = oqp->q_rdptr = oqp->q_wrptr = bp; - oqp->q_top = bp + size; - oqp->q_notify = onfy; - oqp->q_link = link; -} - -/** - * @brief Resets an output queue. - * @details All the data in the output queue is erased and lost, any waiting - * thread is resumed with status @p Q_RESET. - * @note A reset operation can be used by a low level driver in order to - * obtain immediate attention from the high level layers. - * - * @param[in] oqp pointer to an @p OutputQueue structure - * - * @iclass - */ -void chOQResetI(OutputQueue *oqp) { - - chDbgCheckClassI(); - - oqp->q_rdptr = oqp->q_wrptr = oqp->q_buffer; - oqp->q_counter = chQSizeI(oqp); - while (notempty(&oqp->q_waiting)) - chSchReadyI(fifo_remove(&oqp->q_waiting))->p_u.rdymsg = Q_RESET; -} - -/** - * @brief Output queue write with timeout. - * @details This function writes a byte value to an output queue. If the queue - * is full then the calling thread is suspended until there is space - * in the queue or a timeout occurs. - * @note The callback is invoked after writing the character into the - * buffer. - * - * @param[in] oqp pointer to an @p OutputQueue structure - * @param[in] b the byte value to be written in the queue - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval Q_OK if the operation succeeded. - * @retval Q_TIMEOUT if the specified time expired. - * @retval Q_RESET if the queue has been reset. - * - * @api - */ -msg_t chOQPutTimeout(OutputQueue *oqp, uint8_t b, systime_t time) { - - chSysLock(); - while (chOQIsFullI(oqp)) { - msg_t msg; - - if ((msg = qwait((GenericQueue *)oqp, time)) < Q_OK) { - chSysUnlock(); - return msg; - } - } - - oqp->q_counter--; - *oqp->q_wrptr++ = b; - if (oqp->q_wrptr >= oqp->q_top) - oqp->q_wrptr = oqp->q_buffer; - - if (oqp->q_notify) - oqp->q_notify(oqp); - - chSysUnlock(); - return Q_OK; -} - -/** - * @brief Output queue read. - * @details A byte value is read from the low end of an output queue. - * - * @param[in] oqp pointer to an @p OutputQueue structure - * @return The byte value from the queue. - * @retval Q_EMPTY if the queue is empty. - * - * @iclass - */ -msg_t chOQGetI(OutputQueue *oqp) { - uint8_t b; - - chDbgCheckClassI(); - - if (chOQIsEmptyI(oqp)) - return Q_EMPTY; - - oqp->q_counter++; - b = *oqp->q_rdptr++; - if (oqp->q_rdptr >= oqp->q_top) - oqp->q_rdptr = oqp->q_buffer; - - if (notempty(&oqp->q_waiting)) - chSchReadyI(fifo_remove(&oqp->q_waiting))->p_u.rdymsg = Q_OK; - - return b; -} - -/** - * @brief Output queue write with timeout. - * @details The function writes data from a buffer to an output queue. The - * operation completes when the specified amount of data has been - * transferred or after the specified timeout or if the queue has - * been reset. - * @note The function is not atomic, if you need atomicity it is suggested - * to use a semaphore or a mutex for mutual exclusion. - * @note The callback is invoked after writing each character into the - * buffer. - * - * @param[in] oqp pointer to an @p OutputQueue structure - * @param[in] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred, the - * value 0 is reserved - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The number of bytes effectively transferred. - * - * @api - */ -size_t chOQWriteTimeout(OutputQueue *oqp, const uint8_t *bp, - size_t n, systime_t time) { - qnotify_t nfy = oqp->q_notify; - size_t w = 0; - - chDbgCheck(n > 0, "chOQWriteTimeout"); - - chSysLock(); - while (TRUE) { - while (chOQIsFullI(oqp)) { - if (qwait((GenericQueue *)oqp, time) != Q_OK) { - chSysUnlock(); - return w; - } - } - oqp->q_counter--; - *oqp->q_wrptr++ = *bp++; - if (oqp->q_wrptr >= oqp->q_top) - oqp->q_wrptr = oqp->q_buffer; - - if (nfy) - nfy(oqp); - - chSysUnlock(); /* Gives a preemption chance in a controlled point.*/ - w++; - if (--n == 0) - return w; - chSysLock(); - } -} -#endif /* CH_USE_QUEUES */ - -/** @} */ diff --git a/firmware/chibios/os/kernel/src/chregistry.c b/firmware/chibios/os/kernel/src/chregistry.c deleted file mode 100644 index 36c5133c23..0000000000 --- a/firmware/chibios/os/kernel/src/chregistry.c +++ /dev/null @@ -1,163 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chregistry.c - * @brief Threads registry code. - * - * @addtogroup registry - * @details Threads Registry related APIs and services. - * - *

Operation mode

- * The Threads Registry is a double linked list that holds all the - * active threads in the system.
- * Operations defined for the registry: - * - First, returns the first, in creation order, active thread - * in the system. - * - Next, returns the next, in creation order, active thread - * in the system. - * . - * The registry is meant to be mainly a debug feature, for example, - * using the registry a debugger can enumerate the active threads - * in any given moment or the shell can print the active threads - * and their state.
- * Another possible use is for centralized threads memory management, - * terminating threads can pulse an event source and an event handler - * can perform a scansion of the registry in order to recover the - * memory. - * @pre In order to use the threads registry the @p CH_USE_REGISTRY option - * must be enabled in @p chconf.h. - * @{ - */ -#include "ch.h" - -#if CH_USE_REGISTRY || defined(__DOXYGEN__) - -#define _offsetof(st, m) \ - ((size_t)((char *)&((st *)0)->m - (char *)0)) - -/* - * OS signature in ROM plus debug-related information. - */ -ROMCONST chdebug_t ch_debug = { - "main", - (uint8_t)0, - (uint8_t)sizeof (chdebug_t), - (uint16_t)((CH_KERNEL_MAJOR << 11) | - (CH_KERNEL_MINOR << 6) | - (CH_KERNEL_PATCH << 0)), - (uint8_t)sizeof (void *), - (uint8_t)sizeof (systime_t), - (uint8_t)sizeof (Thread), - (uint8_t)_offsetof(Thread, p_prio), - (uint8_t)_offsetof(Thread, p_ctx), - (uint8_t)_offsetof(Thread, p_newer), - (uint8_t)_offsetof(Thread, p_older), - (uint8_t)_offsetof(Thread, p_name), -#if CH_DBG_ENABLE_STACK_CHECK - (uint8_t)_offsetof(Thread, p_stklimit), -#else - (uint8_t)0, -#endif - (uint8_t)_offsetof(Thread, p_state), - (uint8_t)_offsetof(Thread, p_flags), -#if CH_USE_DYNAMIC - (uint8_t)_offsetof(Thread, p_refs), -#else - (uint8_t)0, -#endif -#if CH_TIME_QUANTUM > 0 - (uint8_t)_offsetof(Thread, p_preempt), -#else - (uint8_t)0, -#endif -#if CH_DBG_THREADS_PROFILING - (uint8_t)_offsetof(Thread, p_time) -#else - (uint8_t)0 -#endif -}; - -/** - * @brief Returns the first thread in the system. - * @details Returns the most ancient thread in the system, usually this is - * the main thread unless it terminated. A reference is added to the - * returned thread in order to make sure its status is not lost. - * @note This function cannot return @p NULL because there is always at - * least one thread in the system. - * - * @return A reference to the most ancient thread. - * - * @api - */ -Thread *chRegFirstThread(void) { - Thread *tp; - - chSysLock(); - tp = rlist.r_newer; -#if CH_USE_DYNAMIC - tp->p_refs++; -#endif - chSysUnlock(); - return tp; -} - -/** - * @brief Returns the thread next to the specified one. - * @details The reference counter of the specified thread is decremented and - * the reference counter of the returned thread is incremented. - * - * @param[in] tp pointer to the thread - * @return A reference to the next thread. - * @retval NULL if there is no next thread. - * - * @api - */ -Thread *chRegNextThread(Thread *tp) { - Thread *ntp; - - chSysLock(); - ntp = tp->p_newer; - if (ntp == (Thread *)&rlist) - ntp = NULL; -#if CH_USE_DYNAMIC - else { - chDbgAssert(ntp->p_refs < 255, "chRegNextThread(), #1", - "too many references"); - ntp->p_refs++; - } -#endif - chSysUnlock(); -#if CH_USE_DYNAMIC - chThdRelease(tp); -#endif - return ntp; -} - -#endif /* CH_USE_REGISTRY */ - -/** @} */ diff --git a/firmware/chibios/os/kernel/src/chschd.c b/firmware/chibios/os/kernel/src/chschd.c deleted file mode 100644 index a725f07ad1..0000000000 --- a/firmware/chibios/os/kernel/src/chschd.c +++ /dev/null @@ -1,385 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chschd.c - * @brief Scheduler code. - * - * @addtogroup scheduler - * @details This module provides the default portable scheduler code, - * scheduler functions can be individually captured by the port - * layer in order to provide architecture optimized equivalents. - * When a function is captured its default code is not built into - * the OS image, the optimized version is included instead. - * @{ - */ - -#include "ch.h" - -/** - * @brief Ready list header. - */ -#if !defined(PORT_OPTIMIZED_RLIST_VAR) || defined(__DOXYGEN__) -ReadyList rlist; -#endif /* !defined(PORT_OPTIMIZED_RLIST_VAR) */ - -/** - * @brief Scheduler initialization. - * - * @notapi - */ -void _scheduler_init(void) { - - queue_init(&rlist.r_queue); - rlist.r_prio = NOPRIO; -#if CH_USE_REGISTRY - rlist.r_newer = rlist.r_older = (Thread *)&rlist; -#endif -} - -/** - * @brief Inserts a thread in the Ready List. - * @details The thread is positioned behind all threads with higher or equal - * priority. - * @pre The thread must not be already inserted in any list through its - * @p p_next and @p p_prev or list corruption would occur. - * @post This function does not reschedule so a call to a rescheduling - * function must be performed before unlocking the kernel. Note that - * interrupt handlers always reschedule on exit so an explicit - * reschedule must not be performed in ISRs. - * - * @param[in] tp the thread to be made ready - * @return The thread pointer. - * - * @iclass - */ -#if !defined(PORT_OPTIMIZED_READYI) || defined(__DOXYGEN__) -Thread *chSchReadyI(Thread *tp) { - Thread *cp; - - chDbgCheckClassI(); - - /* Integrity checks.*/ - chDbgAssert((tp->p_state != THD_STATE_READY) && - (tp->p_state != THD_STATE_FINAL), - "chSchReadyI(), #1", - "invalid state"); - - tp->p_state = THD_STATE_READY; - cp = (Thread *)&rlist.r_queue; - do { - cp = cp->p_next; - } while (cp->p_prio >= tp->p_prio); - /* Insertion on p_prev.*/ - tp->p_next = cp; - tp->p_prev = cp->p_prev; - tp->p_prev->p_next = cp->p_prev = tp; - return tp; -} -#endif /* !defined(PORT_OPTIMIZED_READYI) */ - -/** - * @brief Puts the current thread to sleep into the specified state. - * @details The thread goes into a sleeping state. The possible - * @ref thread_states are defined into @p threads.h. - * - * @param[in] newstate the new thread state - * - * @sclass - */ -#if !defined(PORT_OPTIMIZED_GOSLEEPS) || defined(__DOXYGEN__) -void chSchGoSleepS(tstate_t newstate) { - Thread *otp; - - chDbgCheckClassS(); - - (otp = currp)->p_state = newstate; -#if CH_TIME_QUANTUM > 0 - /* The thread is renouncing its remaining time slices so it will have a new - time quantum when it will wakeup.*/ - otp->p_preempt = CH_TIME_QUANTUM; -#endif - setcurrp(fifo_remove(&rlist.r_queue)); - currp->p_state = THD_STATE_CURRENT; - chSysSwitch(currp, otp); -} -#endif /* !defined(PORT_OPTIMIZED_GOSLEEPS) */ - -#if !defined(PORT_OPTIMIZED_GOSLEEPTIMEOUTS) || defined(__DOXYGEN__) -/* - * Timeout wakeup callback. - */ -static void wakeup(void *p) { - Thread *tp = (Thread *)p; - - chSysLockFromIsr(); - switch (tp->p_state) { - case THD_STATE_READY: - /* Handling the special case where the thread has been made ready by - another thread with higher priority.*/ - chSysUnlockFromIsr(); - return; -#if CH_USE_SEMAPHORES || CH_USE_QUEUES || \ - (CH_USE_CONDVARS && CH_USE_CONDVARS_TIMEOUT) -#if CH_USE_SEMAPHORES - case THD_STATE_WTSEM: - chSemFastSignalI((Semaphore *)tp->p_u.wtobjp); - /* Falls into, intentional. */ -#endif -#if CH_USE_QUEUES - case THD_STATE_WTQUEUE: -#endif -#if CH_USE_CONDVARS && CH_USE_CONDVARS_TIMEOUT - case THD_STATE_WTCOND: -#endif - /* States requiring dequeuing.*/ - dequeue(tp); -#endif - } - tp->p_u.rdymsg = RDY_TIMEOUT; - chSchReadyI(tp); - chSysUnlockFromIsr(); -} - -/** - * @brief Puts the current thread to sleep into the specified state with - * timeout specification. - * @details The thread goes into a sleeping state, if it is not awakened - * explicitly within the specified timeout then it is forcibly - * awakened with a @p RDY_TIMEOUT low level message. The possible - * @ref thread_states are defined into @p threads.h. - * - * @param[in] newstate the new thread state - * @param[in] time the number of ticks before the operation timeouts, the - * special values are handled as follow: - * - @a TIME_INFINITE the thread enters an infinite sleep - * state, this is equivalent to invoking - * @p chSchGoSleepS() but, of course, less efficient. - * - @a TIME_IMMEDIATE this value is not allowed. - * . - * @return The wakeup message. - * @retval RDY_TIMEOUT if a timeout occurs. - * - * @sclass - */ -msg_t chSchGoSleepTimeoutS(tstate_t newstate, systime_t time) { - - chDbgCheckClassS(); - - if (TIME_INFINITE != time) { - VirtualTimer vt; - - chVTSetI(&vt, time, wakeup, currp); - chSchGoSleepS(newstate); - if (chVTIsArmedI(&vt)) - chVTResetI(&vt); - } - else - chSchGoSleepS(newstate); - return currp->p_u.rdymsg; -} -#endif /* !defined(PORT_OPTIMIZED_GOSLEEPTIMEOUTS) */ - -/** - * @brief Wakes up a thread. - * @details The thread is inserted into the ready list or immediately made - * running depending on its relative priority compared to the current - * thread. - * @pre The thread must not be already inserted in any list through its - * @p p_next and @p p_prev or list corruption would occur. - * @note It is equivalent to a @p chSchReadyI() followed by a - * @p chSchRescheduleS() but much more efficient. - * @note The function assumes that the current thread has the highest - * priority. - * - * @param[in] ntp the Thread to be made ready - * @param[in] msg message to the awakened thread - * - * @sclass - */ -#if !defined(PORT_OPTIMIZED_WAKEUPS) || defined(__DOXYGEN__) -void chSchWakeupS(Thread *ntp, msg_t msg) { - - chDbgCheckClassS(); - - ntp->p_u.rdymsg = msg; - /* If the waken thread has a not-greater priority than the current - one then it is just inserted in the ready list else it made - running immediately and the invoking thread goes in the ready - list instead.*/ - if (ntp->p_prio <= currp->p_prio) - chSchReadyI(ntp); - else { - Thread *otp = chSchReadyI(currp); - setcurrp(ntp); - ntp->p_state = THD_STATE_CURRENT; - chSysSwitch(ntp, otp); - } -} -#endif /* !defined(PORT_OPTIMIZED_WAKEUPS) */ - -/** - * @brief Performs a reschedule if a higher priority thread is runnable. - * @details If a thread with a higher priority than the current thread is in - * the ready list then make the higher priority thread running. - * - * @sclass - */ -#if !defined(PORT_OPTIMIZED_RESCHEDULES) || defined(__DOXYGEN__) -void chSchRescheduleS(void) { - - chDbgCheckClassS(); - - if (chSchIsRescRequiredI()) - chSchDoRescheduleAhead(); -} -#endif /* !defined(PORT_OPTIMIZED_RESCHEDULES) */ - -/** - * @brief Evaluates if preemption is required. - * @details The decision is taken by comparing the relative priorities and - * depending on the state of the round robin timeout counter. - * @note Not a user function, it is meant to be invoked by the scheduler - * itself or from within the port layer. - * - * @retval TRUE if there is a thread that must go in running state - * immediately. - * @retval FALSE if preemption is not required. - * - * @special - */ -#if !defined(PORT_OPTIMIZED_ISPREEMPTIONREQUIRED) || defined(__DOXYGEN__) -bool_t chSchIsPreemptionRequired(void) { - tprio_t p1 = firstprio(&rlist.r_queue); - tprio_t p2 = currp->p_prio; -#if CH_TIME_QUANTUM > 0 - /* If the running thread has not reached its time quantum, reschedule only - if the first thread on the ready queue has a higher priority. - Otherwise, if the running thread has used up its time quantum, reschedule - if the first thread on the ready queue has equal or higher priority.*/ - return currp->p_preempt ? p1 > p2 : p1 >= p2; -#else - /* If the round robin preemption feature is not enabled then performs a - simpler comparison.*/ - return p1 > p2; -#endif -} -#endif /* !defined(PORT_OPTIMIZED_ISPREEMPTIONREQUIRED) */ - -/** - * @brief Switches to the first thread on the runnable queue. - * @details The current thread is positioned in the ready list behind all - * threads having the same priority. The thread regains its time - * quantum. - * @note Not a user function, it is meant to be invoked by the scheduler - * itself or from within the port layer. - * - * @special - */ -#if !defined(PORT_OPTIMIZED_DORESCHEDULEBEHIND) || defined(__DOXYGEN__) -void chSchDoRescheduleBehind(void) { - Thread *otp; - - otp = currp; - /* Picks the first thread from the ready queue and makes it current.*/ - setcurrp(fifo_remove(&rlist.r_queue)); - currp->p_state = THD_STATE_CURRENT; -#if CH_TIME_QUANTUM > 0 - otp->p_preempt = CH_TIME_QUANTUM; -#endif - chSchReadyI(otp); - chSysSwitch(currp, otp); -} -#endif /* !defined(PORT_OPTIMIZED_DORESCHEDULEBEHIND) */ - -/** - * @brief Switches to the first thread on the runnable queue. - * @details The current thread is positioned in the ready list ahead of all - * threads having the same priority. - * @note Not a user function, it is meant to be invoked by the scheduler - * itself or from within the port layer. - * - * @special - */ -#if !defined(PORT_OPTIMIZED_DORESCHEDULEAHEAD) || defined(__DOXYGEN__) -void chSchDoRescheduleAhead(void) { - Thread *otp, *cp; - - otp = currp; - /* Picks the first thread from the ready queue and makes it current.*/ - setcurrp(fifo_remove(&rlist.r_queue)); - currp->p_state = THD_STATE_CURRENT; - - otp->p_state = THD_STATE_READY; - cp = (Thread *)&rlist.r_queue; - do { - cp = cp->p_next; - } while (cp->p_prio > otp->p_prio); - /* Insertion on p_prev.*/ - otp->p_next = cp; - otp->p_prev = cp->p_prev; - otp->p_prev->p_next = cp->p_prev = otp; - - chSysSwitch(currp, otp); -} -#endif /* !defined(PORT_OPTIMIZED_DORESCHEDULEAHEAD) */ - -/** - * @brief Switches to the first thread on the runnable queue. - * @details The current thread is positioned in the ready list behind or - * ahead of all threads having the same priority depending on - * if it used its whole time slice. - * @note Not a user function, it is meant to be invoked by the scheduler - * itself or from within the port layer. - * - * @special - */ -#if !defined(PORT_OPTIMIZED_DORESCHEDULE) || defined(__DOXYGEN__) -void chSchDoReschedule(void) { - -#if CH_TIME_QUANTUM > 0 - /* If CH_TIME_QUANTUM is enabled then there are two different scenarios to - handle on preemption: time quantum elapsed or not.*/ - if (currp->p_preempt == 0) { - /* The thread consumed its time quantum so it is enqueued behind threads - with same priority level, however, it acquires a new time quantum.*/ - chSchDoRescheduleBehind(); - } - else { - /* The thread didn't consume all its time quantum so it is put ahead of - threads with equal priority and does not acquire a new time quantum.*/ - chSchDoRescheduleAhead(); - } -#else /* !(CH_TIME_QUANTUM > 0) */ - /* If the round-robin mechanism is disabled then the thread goes always - ahead of its peers.*/ - chSchDoRescheduleAhead(); -#endif /* !(CH_TIME_QUANTUM > 0) */ -} -#endif /* !defined(PORT_OPTIMIZED_DORESCHEDULE) */ - -/** @} */ diff --git a/firmware/chibios/os/kernel/src/chsem.c b/firmware/chibios/os/kernel/src/chsem.c deleted file mode 100644 index 19408bf0b8..0000000000 --- a/firmware/chibios/os/kernel/src/chsem.c +++ /dev/null @@ -1,400 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chsem.c - * @brief Semaphores code. - * - * @addtogroup semaphores - * @details Semaphores related APIs and services. - * - *

Operation mode

- * Semaphores are a flexible synchronization primitive, ChibiOS/RT - * implements semaphores in their "counting semaphores" variant as - * defined by Edsger Dijkstra plus several enhancements like: - * - Wait operation with timeout. - * - Reset operation. - * - Atomic wait+signal operation. - * - Return message from the wait operation (OK, RESET, TIMEOUT). - * . - * The binary semaphores variant can be easily implemented using - * counting semaphores.
- * Operations defined for semaphores: - * - Signal: The semaphore counter is increased and if the - * result is non-positive then a waiting thread is removed from - * the semaphore queue and made ready for execution. - * - Wait: The semaphore counter is decreased and if the result - * becomes negative the thread is queued in the semaphore and - * suspended. - * - Reset: The semaphore counter is reset to a non-negative - * value and all the threads in the queue are released. - * . - * Semaphores can be used as guards for mutual exclusion zones - * (note that mutexes are recommended for this kind of use) but - * also have other uses, queues guards and counters for example.
- * Semaphores usually use a FIFO queuing strategy but it is possible - * to make them order threads by priority by enabling - * @p CH_USE_SEMAPHORES_PRIORITY in @p chconf.h. - * @pre In order to use the semaphore APIs the @p CH_USE_SEMAPHORES - * option must be enabled in @p chconf.h. - * @{ - */ - -#include "ch.h" - -#if CH_USE_SEMAPHORES || defined(__DOXYGEN__) - -#if CH_USE_SEMAPHORES_PRIORITY -#define sem_insert(tp, qp) prio_insert(tp, qp) -#else -#define sem_insert(tp, qp) queue_insert(tp, qp) -#endif - -/** - * @brief Initializes a semaphore with the specified counter value. - * - * @param[out] sp pointer to a @p Semaphore structure - * @param[in] n initial value of the semaphore counter. Must be - * non-negative. - * - * @init - */ -void chSemInit(Semaphore *sp, cnt_t n) { - - chDbgCheck((sp != NULL) && (n >= 0), "chSemInit"); - - queue_init(&sp->s_queue); - sp->s_cnt = n; -} - -/** - * @brief Performs a reset operation on the semaphore. - * @post After invoking this function all the threads waiting on the - * semaphore, if any, are released and the semaphore counter is set - * to the specified, non negative, value. - * @note The released threads can recognize they were waked up by a reset - * rather than a signal because the @p chSemWait() will return - * @p RDY_RESET instead of @p RDY_OK. - * - * @param[in] sp pointer to a @p Semaphore structure - * @param[in] n the new value of the semaphore counter. The value must - * be non-negative. - * - * @api - */ -void chSemReset(Semaphore *sp, cnt_t n) { - - chSysLock(); - chSemResetI(sp, n); - chSchRescheduleS(); - chSysUnlock(); -} - -/** - * @brief Performs a reset operation on the semaphore. - * @post After invoking this function all the threads waiting on the - * semaphore, if any, are released and the semaphore counter is set - * to the specified, non negative, value. - * @post This function does not reschedule so a call to a rescheduling - * function must be performed before unlocking the kernel. Note that - * interrupt handlers always reschedule on exit so an explicit - * reschedule must not be performed in ISRs. - * @note The released threads can recognize they were waked up by a reset - * rather than a signal because the @p chSemWait() will return - * @p RDY_RESET instead of @p RDY_OK. - * - * @param[in] sp pointer to a @p Semaphore structure - * @param[in] n the new value of the semaphore counter. The value must - * be non-negative. - * - * @iclass - */ -void chSemResetI(Semaphore *sp, cnt_t n) { - cnt_t cnt; - - chDbgCheckClassI(); - chDbgCheck((sp != NULL) && (n >= 0), "chSemResetI"); - chDbgAssert(((sp->s_cnt >= 0) && isempty(&sp->s_queue)) || - ((sp->s_cnt < 0) && notempty(&sp->s_queue)), - "chSemResetI(), #1", - "inconsistent semaphore"); - - cnt = sp->s_cnt; - sp->s_cnt = n; - while (++cnt <= 0) - chSchReadyI(lifo_remove(&sp->s_queue))->p_u.rdymsg = RDY_RESET; -} - -/** - * @brief Performs a wait operation on a semaphore. - * - * @param[in] sp pointer to a @p Semaphore structure - * @return A message specifying how the invoking thread has been - * released from the semaphore. - * @retval RDY_OK if the thread has not stopped on the semaphore or the - * semaphore has been signaled. - * @retval RDY_RESET if the semaphore has been reset using @p chSemReset(). - * - * @api - */ -msg_t chSemWait(Semaphore *sp) { - msg_t msg; - - chSysLock(); - msg = chSemWaitS(sp); - chSysUnlock(); - return msg; -} - -/** - * @brief Performs a wait operation on a semaphore. - * - * @param[in] sp pointer to a @p Semaphore structure - * @return A message specifying how the invoking thread has been - * released from the semaphore. - * @retval RDY_OK if the thread has not stopped on the semaphore or the - * semaphore has been signaled. - * @retval RDY_RESET if the semaphore has been reset using @p chSemReset(). - * - * @sclass - */ -msg_t chSemWaitS(Semaphore *sp) { - - chDbgCheckClassS(); - chDbgCheck(sp != NULL, "chSemWaitS"); - chDbgAssert(((sp->s_cnt >= 0) && isempty(&sp->s_queue)) || - ((sp->s_cnt < 0) && notempty(&sp->s_queue)), - "chSemWaitS(), #1", - "inconsistent semaphore"); - - if (--sp->s_cnt < 0) { - currp->p_u.wtobjp = sp; - sem_insert(currp, &sp->s_queue); - chSchGoSleepS(THD_STATE_WTSEM); - return currp->p_u.rdymsg; - } - return RDY_OK; -} - -/** - * @brief Performs a wait operation on a semaphore with timeout specification. - * - * @param[in] sp pointer to a @p Semaphore structure - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return A message specifying how the invoking thread has been - * released from the semaphore. - * @retval RDY_OK if the thread has not stopped on the semaphore or the - * semaphore has been signaled. - * @retval RDY_RESET if the semaphore has been reset using @p chSemReset(). - * @retval RDY_TIMEOUT if the semaphore has not been signaled or reset within - * the specified timeout. - * - * @api - */ -msg_t chSemWaitTimeout(Semaphore *sp, systime_t time) { - msg_t msg; - - chSysLock(); - msg = chSemWaitTimeoutS(sp, time); - chSysUnlock(); - return msg; -} - -/** - * @brief Performs a wait operation on a semaphore with timeout specification. - * - * @param[in] sp pointer to a @p Semaphore structure - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return A message specifying how the invoking thread has been - * released from the semaphore. - * @retval RDY_OK if the thread has not stopped on the semaphore or the - * semaphore has been signaled. - * @retval RDY_RESET if the semaphore has been reset using @p chSemReset(). - * @retval RDY_TIMEOUT if the semaphore has not been signaled or reset within - * the specified timeout. - * - * @sclass - */ -msg_t chSemWaitTimeoutS(Semaphore *sp, systime_t time) { - - chDbgCheckClassS(); - chDbgCheck(sp != NULL, "chSemWaitTimeoutS"); - chDbgAssert(((sp->s_cnt >= 0) && isempty(&sp->s_queue)) || - ((sp->s_cnt < 0) && notempty(&sp->s_queue)), - "chSemWaitTimeoutS(), #1", - "inconsistent semaphore"); - - if (--sp->s_cnt < 0) { - if (TIME_IMMEDIATE == time) { - sp->s_cnt++; - return RDY_TIMEOUT; - } - currp->p_u.wtobjp = sp; - sem_insert(currp, &sp->s_queue); - return chSchGoSleepTimeoutS(THD_STATE_WTSEM, time); - } - return RDY_OK; -} - -/** - * @brief Performs a signal operation on a semaphore. - * - * @param[in] sp pointer to a @p Semaphore structure - * - * @api - */ -void chSemSignal(Semaphore *sp) { - - chDbgCheck(sp != NULL, "chSemSignal"); - chDbgAssert(((sp->s_cnt >= 0) && isempty(&sp->s_queue)) || - ((sp->s_cnt < 0) && notempty(&sp->s_queue)), - "chSemSignal(), #1", - "inconsistent semaphore"); - - chSysLock(); - if (++sp->s_cnt <= 0) - chSchWakeupS(fifo_remove(&sp->s_queue), RDY_OK); - chSysUnlock(); -} - -/** - * @brief Performs a signal operation on a semaphore. - * @post This function does not reschedule so a call to a rescheduling - * function must be performed before unlocking the kernel. Note that - * interrupt handlers always reschedule on exit so an explicit - * reschedule must not be performed in ISRs. - * - * @param[in] sp pointer to a @p Semaphore structure - * - * @iclass - */ -void chSemSignalI(Semaphore *sp) { - - chDbgCheckClassI(); - chDbgCheck(sp != NULL, "chSemSignalI"); - chDbgAssert(((sp->s_cnt >= 0) && isempty(&sp->s_queue)) || - ((sp->s_cnt < 0) && notempty(&sp->s_queue)), - "chSemSignalI(), #1", - "inconsistent semaphore"); - - if (++sp->s_cnt <= 0) { - /* Note, it is done this way in order to allow a tail call on - chSchReadyI().*/ - Thread *tp = fifo_remove(&sp->s_queue); - tp->p_u.rdymsg = RDY_OK; - chSchReadyI(tp); - } -} - -/** - * @brief Adds the specified value to the semaphore counter. - * @post This function does not reschedule so a call to a rescheduling - * function must be performed before unlocking the kernel. Note that - * interrupt handlers always reschedule on exit so an explicit - * reschedule must not be performed in ISRs. - * - * @param[in] sp pointer to a @p Semaphore structure - * @param[in] n value to be added to the semaphore counter. The value - * must be positive. - * - * @iclass - */ -void chSemAddCounterI(Semaphore *sp, cnt_t n) { - - chDbgCheckClassI(); - chDbgCheck((sp != NULL) && (n > 0), "chSemAddCounterI"); - chDbgAssert(((sp->s_cnt >= 0) && isempty(&sp->s_queue)) || - ((sp->s_cnt < 0) && notempty(&sp->s_queue)), - "chSemAddCounterI(), #1", - "inconsistent semaphore"); - - while (n > 0) { - if (++sp->s_cnt <= 0) - chSchReadyI(fifo_remove(&sp->s_queue))->p_u.rdymsg = RDY_OK; - n--; - } -} - -#if CH_USE_SEMSW || defined(__DOXYGEN__) -/** - * @brief Performs atomic signal and wait operations on two semaphores. - * @pre The configuration option @p CH_USE_SEMSW must be enabled in order - * to use this function. - * - * @param[in] sps pointer to a @p Semaphore structure to be signaled - * @param[in] spw pointer to a @p Semaphore structure to wait on - * @return A message specifying how the invoking thread has been - * released from the semaphore. - * @retval RDY_OK if the thread has not stopped on the semaphore or the - * semaphore has been signaled. - * @retval RDY_RESET if the semaphore has been reset using @p chSemReset(). - * - * @api - */ -msg_t chSemSignalWait(Semaphore *sps, Semaphore *spw) { - msg_t msg; - - chDbgCheck((sps != NULL) && (spw != NULL), "chSemSignalWait"); - chDbgAssert(((sps->s_cnt >= 0) && isempty(&sps->s_queue)) || - ((sps->s_cnt < 0) && notempty(&sps->s_queue)), - "chSemSignalWait(), #1", - "inconsistent semaphore"); - chDbgAssert(((spw->s_cnt >= 0) && isempty(&spw->s_queue)) || - ((spw->s_cnt < 0) && notempty(&spw->s_queue)), - "chSemSignalWait(), #2", - "inconsistent semaphore"); - - chSysLock(); - if (++sps->s_cnt <= 0) - chSchReadyI(fifo_remove(&sps->s_queue))->p_u.rdymsg = RDY_OK; - if (--spw->s_cnt < 0) { - Thread *ctp = currp; - sem_insert(ctp, &spw->s_queue); - ctp->p_u.wtobjp = spw; - chSchGoSleepS(THD_STATE_WTSEM); - msg = ctp->p_u.rdymsg; - } - else { - chSchRescheduleS(); - msg = RDY_OK; - } - chSysUnlock(); - return msg; -} -#endif /* CH_USE_SEMSW */ - -#endif /* CH_USE_SEMAPHORES */ - -/** @} */ diff --git a/firmware/chibios/os/kernel/src/chsys.c b/firmware/chibios/os/kernel/src/chsys.c deleted file mode 100644 index a91dddff55..0000000000 --- a/firmware/chibios/os/kernel/src/chsys.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chsys.c - * @brief System related code. - * - * @addtogroup system - * @details System related APIs and services: - * - Initialization. - * - Locks. - * - Interrupt Handling. - * - Power Management. - * - Abnormal Termination. - * . - * @{ - */ - -#include "ch.h" - -#if !CH_NO_IDLE_THREAD || defined(__DOXYGEN__) -/** - * @brief Idle thread working area. - */ -WORKING_AREA(_idle_thread_wa, PORT_IDLE_THREAD_STACK_SIZE); - -/** - * @brief This function implements the idle thread infinite loop. - * @details The function puts the processor in the lowest power mode capable - * to serve interrupts.
- * The priority is internally set to the minimum system value so - * that this thread is executed only if there are no other ready - * threads in the system. - * - * @param[in] p the thread parameter, unused in this scenario - */ -void _idle_thread(void *p) { - - (void)p; - chRegSetThreadName("idle"); - while (TRUE) { - port_wait_for_interrupt(); - IDLE_LOOP_HOOK(); - } -} -#endif /* CH_NO_IDLE_THREAD */ - -/** - * @brief ChibiOS/RT initialization. - * @details After executing this function the current instructions stream - * becomes the main thread. - * @pre Interrupts must be still disabled when @p chSysInit() is invoked - * and are internally enabled. - * @post The main thread is created with priority @p NORMALPRIO. - * @note This function has special, architecture-dependent, requirements, - * see the notes into the various port reference manuals. - * - * @special - */ -void chSysInit(void) { - static Thread mainthread; -#if CH_DBG_ENABLE_STACK_CHECK - extern stkalign_t __main_thread_stack_base__; -#endif - - port_init(); - _scheduler_init(); - _vt_init(); -#if CH_USE_MEMCORE - _core_init(); -#endif -#if CH_USE_HEAP - _heap_init(); -#endif -#if CH_DBG_ENABLE_TRACE - _trace_init(); -#endif - - /* Now this instructions flow becomes the main thread.*/ - setcurrp(_thread_init(&mainthread, NORMALPRIO)); - currp->p_state = THD_STATE_CURRENT; -#if CH_DBG_ENABLE_STACK_CHECK - /* This is a special case because the main thread Thread structure is not - adjacent to its stack area.*/ - currp->p_stklimit = &__main_thread_stack_base__; -#endif - chSysEnable(); - - /* Note, &ch_debug points to the string "main" if the registry is - active, else the parameter is ignored.*/ - chRegSetThreadName((const char *)&ch_debug); - -#if !CH_NO_IDLE_THREAD - /* This thread has the lowest priority in the system, its role is just to - serve interrupts in its context while keeping the lowest energy saving - mode compatible with the system status.*/ - chThdCreateStatic(_idle_thread_wa, sizeof(_idle_thread_wa), IDLEPRIO, - (tfunc_t)_idle_thread, NULL); -#endif -} - -/** - * @brief Handles time ticks for round robin preemption and timer increments. - * @details Decrements the remaining time quantum of the running thread - * and preempts it when the quantum is used up. Increments system - * time and manages the timers. - * @note The frequency of the timer determines the system tick granularity - * and, together with the @p CH_TIME_QUANTUM macro, the round robin - * interval. - * - * @iclass - */ -void chSysTimerHandlerI(void) { - - chDbgCheckClassI(); - -#if CH_TIME_QUANTUM > 0 - /* Running thread has not used up quantum yet? */ - if (currp->p_preempt > 0) - /* Decrement remaining quantum.*/ - currp->p_preempt--; -#endif -#if CH_DBG_THREADS_PROFILING - currp->p_time++; -#endif - chVTDoTickI(); -#if defined(SYSTEM_TICK_EVENT_HOOK) - SYSTEM_TICK_EVENT_HOOK(); -#endif -} - -/** @} */ diff --git a/firmware/chibios/os/kernel/src/chthreads.c b/firmware/chibios/os/kernel/src/chthreads.c deleted file mode 100644 index 57ae565667..0000000000 --- a/firmware/chibios/os/kernel/src/chthreads.c +++ /dev/null @@ -1,443 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chthreads.c - * @brief Threads code. - * - * @addtogroup threads - * @details Threads related APIs and services. - * - *

Operation mode

- * A thread is an abstraction of an independent instructions flow. - * In ChibiOS/RT a thread is represented by a "C" function owning - * a processor context, state informations and a dedicated stack - * area. In this scenario static variables are shared among all - * threads while automatic variables are local to the thread.
- * Operations defined for threads: - * - Create, a thread is started on the specified thread - * function. This operation is available in multiple variants, - * both static and dynamic. - * - Exit, a thread terminates by returning from its top - * level function or invoking a specific API, the thread can - * return a value that can be retrieved by other threads. - * - Wait, a thread waits for the termination of another - * thread and retrieves its return value. - * - Resume, a thread created in suspended state is started. - * - Sleep, the execution of a thread is suspended for the - * specified amount of time or the specified future absolute time - * is reached. - * - SetPriority, a thread changes its own priority level. - * - Yield, a thread voluntarily renounces to its time slot. - * . - * The threads subsystem is implicitly included in kernel however - * some of its part may be excluded by disabling them in @p chconf.h, - * see the @p CH_USE_WAITEXIT and @p CH_USE_DYNAMIC configuration - * options. - * @{ - */ - -#include "ch.h" - -/** - * @brief Initializes a thread structure. - * @note This is an internal functions, do not use it in application code. - * - * @param[in] tp pointer to the thread - * @param[in] prio the priority level for the new thread - * @return The same thread pointer passed as parameter. - * - * @notapi - */ -Thread *_thread_init(Thread *tp, tprio_t prio) { - - tp->p_prio = prio; - tp->p_state = THD_STATE_SUSPENDED; - tp->p_flags = THD_MEM_MODE_STATIC; -#if CH_TIME_QUANTUM > 0 - tp->p_preempt = CH_TIME_QUANTUM; -#endif -#if CH_USE_MUTEXES - tp->p_realprio = prio; - tp->p_mtxlist = NULL; -#endif -#if CH_USE_EVENTS - tp->p_epending = 0; -#endif -#if CH_DBG_THREADS_PROFILING - tp->p_time = 0; -#endif -#if CH_USE_DYNAMIC - tp->p_refs = 1; -#endif -#if CH_USE_REGISTRY - tp->p_name = NULL; - REG_INSERT(tp); -#endif -#if CH_USE_WAITEXIT - list_init(&tp->p_waiting); -#endif -#if CH_USE_MESSAGES - queue_init(&tp->p_msgqueue); -#endif -#if CH_DBG_ENABLE_STACK_CHECK - tp->p_stklimit = (stkalign_t *)(tp + 1); -#endif -#if defined(THREAD_EXT_INIT_HOOK) - THREAD_EXT_INIT_HOOK(tp); -#endif - return tp; -} - -#if CH_DBG_FILL_THREADS || defined(__DOXYGEN__) -/** - * @brief Memory fill utility. - * - * @param[in] startp first address to fill - * @param[in] endp last address to fill +1 - * @param[in] v filler value - * - * @notapi - */ -void _thread_memfill(uint8_t *startp, uint8_t *endp, uint8_t v) { - - while (startp < endp) - *startp++ = v; -} -#endif /* CH_DBG_FILL_THREADS */ - -/** - * @brief Creates a new thread into a static memory area. - * @details The new thread is initialized but not inserted in the ready list, - * the initial state is @p THD_STATE_SUSPENDED. - * @post The initialized thread can be subsequently started by invoking - * @p chThdResume(), @p chThdResumeI() or @p chSchWakeupS() - * depending on the execution context. - * @note A thread can terminate by calling @p chThdExit() or by simply - * returning from its main function. - * @note Threads created using this function do not obey to the - * @p CH_DBG_FILL_THREADS debug option because it would keep - * the kernel locked for too much time. - * - * @param[out] wsp pointer to a working area dedicated to the thread stack - * @param[in] size size of the working area - * @param[in] prio the priority level for the new thread - * @param[in] pf the thread function - * @param[in] arg an argument passed to the thread function. It can be - * @p NULL. - * @return The pointer to the @p Thread structure allocated for - * the thread into the working space area. - * - * @iclass - */ -Thread *chThdCreateI(void *wsp, size_t size, - tprio_t prio, tfunc_t pf, void *arg) { - /* Thread structure is laid out in the lower part of the thread workspace.*/ - Thread *tp = wsp; - - chDbgCheckClassI(); - - chDbgCheck((wsp != NULL) && (size >= THD_WA_SIZE(0)) && - (prio <= HIGHPRIO) && (pf != NULL), - "chThdCreateI"); - SETUP_CONTEXT(wsp, size, pf, arg); - return _thread_init(tp, prio); -} - -/** - * @brief Creates a new thread into a static memory area. - * @note A thread can terminate by calling @p chThdExit() or by simply - * returning from its main function. - * - * @param[out] wsp pointer to a working area dedicated to the thread stack - * @param[in] size size of the working area - * @param[in] prio the priority level for the new thread - * @param[in] pf the thread function - * @param[in] arg an argument passed to the thread function. It can be - * @p NULL. - * @return The pointer to the @p Thread structure allocated for - * the thread into the working space area. - * - * @api - */ -Thread *chThdCreateStatic(void *wsp, size_t size, - tprio_t prio, tfunc_t pf, void *arg) { - Thread *tp; - -#if CH_DBG_FILL_THREADS - _thread_memfill((uint8_t *)wsp, - (uint8_t *)wsp + sizeof(Thread), - CH_THREAD_FILL_VALUE); - _thread_memfill((uint8_t *)wsp + sizeof(Thread), - (uint8_t *)wsp + size, - CH_STACK_FILL_VALUE); -#endif - chSysLock(); - chSchWakeupS(tp = chThdCreateI(wsp, size, prio, pf, arg), RDY_OK); - chSysUnlock(); - return tp; -} - -/** - * @brief Changes the running thread priority level then reschedules if - * necessary. - * @note The function returns the real thread priority regardless of the - * current priority that could be higher than the real priority - * because the priority inheritance mechanism. - * - * @param[in] newprio the new priority level of the running thread - * @return The old priority level. - * - * @api - */ -tprio_t chThdSetPriority(tprio_t newprio) { - tprio_t oldprio; - - chDbgCheck(newprio <= HIGHPRIO, "chThdSetPriority"); - - chSysLock(); -#if CH_USE_MUTEXES - oldprio = currp->p_realprio; - if ((currp->p_prio == currp->p_realprio) || (newprio > currp->p_prio)) - currp->p_prio = newprio; - currp->p_realprio = newprio; -#else - oldprio = currp->p_prio; - currp->p_prio = newprio; -#endif - chSchRescheduleS(); - chSysUnlock(); - return oldprio; -} - -/** - * @brief Resumes a suspended thread. - * @pre The specified thread pointer must refer to an initialized thread - * in the @p THD_STATE_SUSPENDED state. - * @post The specified thread is immediately started or put in the ready - * list depending on the relative priority levels. - * @note Use this function to start threads created with @p chThdCreateI(). - * - * @param[in] tp pointer to the thread - * @return The pointer to the thread. - * - * @api - */ -Thread *chThdResume(Thread *tp) { - - chSysLock(); - chDbgAssert(tp->p_state == THD_STATE_SUSPENDED, - "chThdResume(), #1", - "thread not in THD_STATE_SUSPENDED state"); - chSchWakeupS(tp, RDY_OK); - chSysUnlock(); - return tp; -} - -/** - * @brief Requests a thread termination. - * @pre The target thread must be written to invoke periodically - * @p chThdShouldTerminate() and terminate cleanly if it returns - * @p TRUE. - * @post The specified thread will terminate after detecting the termination - * condition. - * - * @param[in] tp pointer to the thread - * - * @api - */ -void chThdTerminate(Thread *tp) { - - chSysLock(); - tp->p_flags |= THD_TERMINATE; - chSysUnlock(); -} - -/** - * @brief Suspends the invoking thread for the specified time. - * - * @param[in] time the delay in system ticks, the special values are - * handled as follow: - * - @a TIME_INFINITE the thread enters an infinite sleep - * state. - * - @a TIME_IMMEDIATE this value is not allowed. - * . - * - * @api - */ -void chThdSleep(systime_t time) { - - chDbgCheck(time != TIME_IMMEDIATE, "chThdSleep"); - - chSysLock(); - chThdSleepS(time); - chSysUnlock(); -} - -/** - * @brief Suspends the invoking thread until the system time arrives to the - * specified value. - * - * @param[in] time absolute system time - * - * @api - */ -void chThdSleepUntil(systime_t time) { - - chSysLock(); - if ((time -= chTimeNow()) > 0) - chThdSleepS(time); - chSysUnlock(); -} - -/** - * @brief Yields the time slot. - * @details Yields the CPU control to the next thread in the ready list with - * equal priority, if any. - * - * @api - */ -void chThdYield(void) { - - chSysLock(); - chSchDoYieldS(); - chSysUnlock(); -} - -/** - * @brief Terminates the current thread. - * @details The thread goes in the @p THD_STATE_FINAL state holding the - * specified exit status code, other threads can retrieve the - * exit status code by invoking the function @p chThdWait(). - * @post Eventual code after this function will never be executed, - * this function never returns. The compiler has no way to - * know this so do not assume that the compiler would remove - * the dead code. - * - * @param[in] msg thread exit code - * - * @api - */ -void chThdExit(msg_t msg) { - - chSysLock(); - chThdExitS(msg); - /* The thread never returns here.*/ -} - -/** - * @brief Terminates the current thread. - * @details The thread goes in the @p THD_STATE_FINAL state holding the - * specified exit status code, other threads can retrieve the - * exit status code by invoking the function @p chThdWait(). - * @post Eventual code after this function will never be executed, - * this function never returns. The compiler has no way to - * know this so do not assume that the compiler would remove - * the dead code. - * - * @param[in] msg thread exit code - * - * @sclass - */ -void chThdExitS(msg_t msg) { - Thread *tp = currp; - - tp->p_u.exitcode = msg; -#if defined(THREAD_EXT_EXIT_HOOK) - THREAD_EXT_EXIT_HOOK(tp); -#endif -#if CH_USE_WAITEXIT - while (notempty(&tp->p_waiting)) - chSchReadyI(list_remove(&tp->p_waiting)); -#endif -#if CH_USE_REGISTRY - /* Static threads are immediately removed from the registry because - there is no memory to recover.*/ - if ((tp->p_flags & THD_MEM_MODE_MASK) == THD_MEM_MODE_STATIC) - REG_REMOVE(tp); -#endif - chSchGoSleepS(THD_STATE_FINAL); - /* The thread never returns here.*/ - chDbgAssert(FALSE, "chThdExitS(), #1", "zombies apocalypse"); -} - -#if CH_USE_WAITEXIT || defined(__DOXYGEN__) -/** - * @brief Blocks the execution of the invoking thread until the specified - * thread terminates then the exit code is returned. - * @details This function waits for the specified thread to terminate then - * decrements its reference counter, if the counter reaches zero then - * the thread working area is returned to the proper allocator.
- * The memory used by the exited thread is handled in different ways - * depending on the API that spawned the thread: - * - If the thread was spawned by @p chThdCreateStatic() or by - * @p chThdCreateI() then nothing happens and the thread working - * area is not released or modified in any way. This is the - * default, totally static, behavior. - * - If the thread was spawned by @p chThdCreateFromHeap() then - * the working area is returned to the system heap. - * - If the thread was spawned by @p chThdCreateFromMemoryPool() - * then the working area is returned to the owning memory pool. - * . - * @pre The configuration option @p CH_USE_WAITEXIT must be enabled in - * order to use this function. - * @post Enabling @p chThdWait() requires 2-4 (depending on the - * architecture) extra bytes in the @p Thread structure. - * @post After invoking @p chThdWait() the thread pointer becomes invalid - * and must not be used as parameter for further system calls. - * @note If @p CH_USE_DYNAMIC is not specified this function just waits for - * the thread termination, no memory allocators are involved. - * - * @param[in] tp pointer to the thread - * @return The exit code from the terminated thread. - * - * @api - */ -msg_t chThdWait(Thread *tp) { - msg_t msg; - - chDbgCheck(tp != NULL, "chThdWait"); - - chSysLock(); - chDbgAssert(tp != currp, "chThdWait(), #1", "waiting self"); -#if CH_USE_DYNAMIC - chDbgAssert(tp->p_refs > 0, "chThdWait(), #2", "not referenced"); -#endif - if (tp->p_state != THD_STATE_FINAL) { - list_insert(currp, &tp->p_waiting); - chSchGoSleepS(THD_STATE_WTEXIT); - } - msg = tp->p_u.exitcode; - chSysUnlock(); -#if CH_USE_DYNAMIC - chThdRelease(tp); -#endif - return msg; -} -#endif /* CH_USE_WAITEXIT */ - -/** @} */ diff --git a/firmware/chibios/os/kernel/src/chvt.c b/firmware/chibios/os/kernel/src/chvt.c deleted file mode 100644 index c1c694560d..0000000000 --- a/firmware/chibios/os/kernel/src/chvt.c +++ /dev/null @@ -1,121 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chvt.c - * @brief Time and Virtual Timers related code. - * - * @addtogroup time - * @details Time and Virtual Timers related APIs and services. - * @{ - */ - -#include "ch.h" - -/** - * @brief Virtual timers delta list header. - */ -VTList vtlist; - -/** - * @brief Virtual Timers initialization. - * @note Internal use only. - * - * @notapi - */ -void _vt_init(void) { - - vtlist.vt_next = vtlist.vt_prev = (void *)&vtlist; - vtlist.vt_time = (systime_t)-1; - vtlist.vt_systime = 0; -} - -/** - * @brief Enables a virtual timer. - * @note The associated function is invoked from interrupt context. - * - * @param[out] vtp the @p VirtualTimer structure pointer - * @param[in] time the number of ticks before the operation timeouts, the - * special values are handled as follow: - * - @a TIME_INFINITE is allowed but interpreted as a - * normal time specification. - * - @a TIME_IMMEDIATE this value is not allowed. - * . - * @param[in] vtfunc the timer callback function. After invoking the - * callback the timer is disabled and the structure can - * be disposed or reused. - * @param[in] par a parameter that will be passed to the callback - * function - * - * @iclass - */ -void chVTSetI(VirtualTimer *vtp, systime_t time, vtfunc_t vtfunc, void *par) { - VirtualTimer *p; - - chDbgCheckClassI(); - chDbgCheck((vtp != NULL) && (vtfunc != NULL) && (time != TIME_IMMEDIATE), - "chVTSetI"); - - vtp->vt_par = par; - vtp->vt_func = vtfunc; - p = vtlist.vt_next; - while (p->vt_time < time) { - time -= p->vt_time; - p = p->vt_next; - } - - vtp->vt_prev = (vtp->vt_next = p)->vt_prev; - vtp->vt_prev->vt_next = p->vt_prev = vtp; - vtp->vt_time = time; - if (p != (void *)&vtlist) - p->vt_time -= time; -} - -/** - * @brief Disables a Virtual Timer. - * @note The timer MUST be active when this function is invoked. - * - * @param[in] vtp the @p VirtualTimer structure pointer - * - * @iclass - */ -void chVTResetI(VirtualTimer *vtp) { - - chDbgCheckClassI(); - chDbgCheck(vtp != NULL, "chVTResetI"); - chDbgAssert(vtp->vt_func != NULL, - "chVTResetI(), #1", - "timer not set or already triggered"); - - if (vtp->vt_next != (void *)&vtlist) - vtp->vt_next->vt_time += vtp->vt_time; - vtp->vt_prev->vt_next = vtp->vt_next; - vtp->vt_next->vt_prev = vtp->vt_prev; - vtp->vt_func = (vtfunc_t)NULL; -} - -/** @} */ diff --git a/firmware/chibios/os/ports/GCC/ARMCMx/STM32F0xx/cmparams.h b/firmware/chibios/os/ports/GCC/ARMCMx/STM32F0xx/cmparams.h deleted file mode 100644 index e4ba798c44..0000000000 --- a/firmware/chibios/os/ports/GCC/ARMCMx/STM32F0xx/cmparams.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file GCC/ARMCMx/STM32F0xx/cmparams.h - * @brief ARM Cortex-M0 parameters for the STM32F0xx. - * - * @defgroup ARMCMx_STM32F0xx STM32F0xx Specific Parameters - * @ingroup ARMCMx_SPECIFIC - * @details This file contains the Cortex-M0 specific parameters for the - * STM32F0xx platform. - * @{ - */ - -#ifndef _CMPARAMS_H_ -#define _CMPARAMS_H_ - -/** - * @brief Cortex core model. - */ -#define CORTEX_MODEL CORTEX_M0 - -/** - * @brief Systick unit presence. - */ -#define CORTEX_HAS_ST TRUE - -/** - * @brief Memory Protection unit presence. - */ -#define CORTEX_HAS_MPU FALSE - -/** - * @brief Floating Point unit presence. - */ -#define CORTEX_HAS_FPU FALSE - -/** - * @brief Number of bits in priority masks. - */ -#define CORTEX_PRIORITY_BITS 2 - -#endif /* _CMPARAMS_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/ports/GCC/ARMCMx/STM32F0xx/port.mk b/firmware/chibios/os/ports/GCC/ARMCMx/STM32F0xx/port.mk deleted file mode 100644 index 836d56ada3..0000000000 --- a/firmware/chibios/os/ports/GCC/ARMCMx/STM32F0xx/port.mk +++ /dev/null @@ -1,15 +0,0 @@ -# List of the ChibiOS/RT Cortex-M0 STM32 port files. -PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \ - $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F0xx/vectors.c \ - ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \ - ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v6m.c \ - ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c - -PORTASM = - -PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \ - ${CHIBIOS}/os/ports/common/ARMCMx \ - ${CHIBIOS}/os/ports/GCC/ARMCMx \ - ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F0xx - -PORTLD = ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F0xx/ld diff --git a/firmware/chibios/os/ports/GCC/ARMCMx/STM32F0xx/vectors.c b/firmware/chibios/os/ports/GCC/ARMCMx/STM32F0xx/vectors.c deleted file mode 100644 index 2c5eb8323b..0000000000 --- a/firmware/chibios/os/ports/GCC/ARMCMx/STM32F0xx/vectors.c +++ /dev/null @@ -1,205 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file GCC/ARMCMx/STM32F0xx/vectors.c - * @brief Interrupt vectors for the STM32F0xx family. - * - * @defgroup ARMCMx_STM32F0xx_VECTORS STM32F0xx Interrupt Vectors - * @ingroup ARMCMx_SPECIFIC - * @details Interrupt vectors for the STM32F0xx family. - * @{ - */ - -#include "ch.h" - -/** - * @brief Type of an IRQ vector. - */ -typedef void (*irq_vector_t)(void); - -/** - * @brief Type of a structure representing the whole vectors table. - */ -typedef struct { - uint32_t *init_stack; - irq_vector_t reset_vector; - irq_vector_t nmi_vector; - irq_vector_t hardfault_vector; - irq_vector_t memmanage_vector; - irq_vector_t busfault_vector; - irq_vector_t usagefault_vector; - irq_vector_t vector1c; - irq_vector_t vector20; - irq_vector_t vector24; - irq_vector_t vector28; - irq_vector_t svcall_vector; - irq_vector_t debugmonitor_vector; - irq_vector_t vector34; - irq_vector_t pendsv_vector; - irq_vector_t systick_vector; - irq_vector_t vectors[32]; -} vectors_t; - -#if !defined(__DOXYGEN__) -extern uint32_t __main_stack_end__; -extern void ResetHandler(void); -extern void NMIVector(void); -extern void HardFaultVector(void); -extern void MemManageVector(void); -extern void BusFaultVector(void); -extern void UsageFaultVector(void); -extern void Vector1C(void); -extern void Vector20(void); -extern void Vector24(void); -extern void Vector28(void); -extern void SVCallVector(void); -extern void DebugMonitorVector(void); -extern void Vector34(void); -extern void PendSVVector(void); -extern void SysTickVector(void); -extern void Vector40(void); -extern void Vector44(void); -extern void Vector48(void); -extern void Vector4C(void); -extern void Vector50(void); -extern void Vector54(void); -extern void Vector58(void); -extern void Vector5C(void); -extern void Vector60(void); -extern void Vector64(void); -extern void Vector68(void); -extern void Vector6C(void); -extern void Vector70(void); -extern void Vector74(void); -extern void Vector78(void); -extern void Vector7C(void); -extern void Vector80(void); -extern void Vector84(void); -extern void Vector88(void); -extern void Vector8C(void); -extern void Vector90(void); -extern void Vector94(void); -extern void Vector98(void); -extern void Vector9C(void); -extern void VectorA0(void); -extern void VectorA4(void); -extern void VectorA8(void); -extern void VectorAC(void); -extern void VectorB0(void); -extern void VectorB4(void); -extern void VectorB8(void); -extern void VectorBC(void); -#endif - -/** - * @brief STM32 vectors table. - */ -#if !defined(__DOXYGEN__) -__attribute__ ((section("vectors"))) -#endif -vectors_t _vectors = { - &__main_stack_end__,ResetHandler, NMIVector, HardFaultVector, - MemManageVector, BusFaultVector, UsageFaultVector, Vector1C, - Vector20, Vector24, Vector28, SVCallVector, - DebugMonitorVector, Vector34, PendSVVector, SysTickVector, - { - Vector40, Vector44, Vector48, Vector4C, - Vector50, Vector54, Vector58, Vector5C, - Vector60, Vector64, Vector68, Vector6C, - Vector70, Vector74, Vector78, Vector7C, - Vector80, Vector84, Vector88, Vector8C, - Vector90, Vector94, Vector98, Vector9C, - VectorA0, VectorA4, VectorA8, VectorAC, - VectorB0, VectorB4, VectorB8, VectorBC - } -}; - -/** - * @brief Unhandled exceptions handler. - * @details Any undefined exception vector points to this function by default. - * This function simply stops the system into an infinite loop. - * - * @notapi - */ -#if !defined(__DOXYGEN__) -__attribute__ ((naked)) -#endif -void _unhandled_exception(void) { - - while (TRUE) - ; -} - -void NMIVector(void) __attribute__((weak, alias("_unhandled_exception"))); -void HardFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); -void MemManageVector(void) __attribute__((weak, alias("_unhandled_exception"))); -void BusFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); -void UsageFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector1C(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector20(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector24(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector28(void) __attribute__((weak, alias("_unhandled_exception"))); -void SVCallVector(void) __attribute__((weak, alias("_unhandled_exception"))); -void DebugMonitorVector(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector34(void) __attribute__((weak, alias("_unhandled_exception"))); -void PendSVVector(void) __attribute__((weak, alias("_unhandled_exception"))); -void SysTickVector(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector40(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector44(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector48(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector4C(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector50(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector54(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector58(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector5C(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector60(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector64(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector68(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector6C(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector70(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector74(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector78(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector7C(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector80(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector84(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector88(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector8C(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector90(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector94(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector98(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector9C(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorA0(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorA4(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorA8(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorAC(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorB0(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorB4(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorB8(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorBC(void) __attribute__((weak, alias("_unhandled_exception"))); - -/** @} */ diff --git a/firmware/chibios/os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h b/firmware/chibios/os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h deleted file mode 100644 index 7b76e135c6..0000000000 --- a/firmware/chibios/os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file GCC/ARMCMx/STM32F1xx/cmparams.h - * @brief ARM Cortex-M3 parameters for the STM32F1xx. - * - * @defgroup ARMCMx_STM32F1xx STM32F1xx Specific Parameters - * @ingroup ARMCMx_SPECIFIC - * @details This file contains the Cortex-M3 specific parameters for the - * STM32F1xx platform. - * @{ - */ - -#ifndef _CMPARAMS_H_ -#define _CMPARAMS_H_ - -/** - * @brief Cortex core model. - */ -#define CORTEX_MODEL CORTEX_M3 - -/** - * @brief Systick unit presence. - */ -#define CORTEX_HAS_ST TRUE - -/** - * @brief Memory Protection unit presence. - */ -#define CORTEX_HAS_MPU FALSE - -/** - * @brief Floating Point unit presence. - */ -#define CORTEX_HAS_FPU FALSE - -/** - * @brief Number of bits in priority masks. - */ -#define CORTEX_PRIORITY_BITS 4 - -#endif /* _CMPARAMS_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/ports/GCC/ARMCMx/STM32F1xx/port.mk b/firmware/chibios/os/ports/GCC/ARMCMx/STM32F1xx/port.mk deleted file mode 100644 index 51a2cf4a0d..0000000000 --- a/firmware/chibios/os/ports/GCC/ARMCMx/STM32F1xx/port.mk +++ /dev/null @@ -1,15 +0,0 @@ -# List of the ChibiOS/RT Cortex-M3 STM32 port files. -PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \ - $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/vectors.c \ - ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \ - ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \ - ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c - -PORTASM = - -PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \ - ${CHIBIOS}/os/ports/common/ARMCMx \ - ${CHIBIOS}/os/ports/GCC/ARMCMx \ - ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F1xx - -PORTLD = ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F1xx/ld diff --git a/firmware/chibios/os/ports/GCC/ARMCMx/STM32F1xx/vectors.c b/firmware/chibios/os/ports/GCC/ARMCMx/STM32F1xx/vectors.c deleted file mode 100644 index 7570147034..0000000000 --- a/firmware/chibios/os/ports/GCC/ARMCMx/STM32F1xx/vectors.c +++ /dev/null @@ -1,337 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file GCC/ARMCMx/STM32F1xx/vectors.c - * @brief Interrupt vectors for the STM32F1xx family. - * - * @defgroup ARMCMx_STM32F1xx_VECTORS STM32F1xx Interrupt Vectors - * @ingroup ARMCMx_SPECIFIC - * @details Interrupt vectors for the STM32F1xx family. - * One of the following macros must be defined on the - * compiler command line or in a file named board.h: - * - @p STM32F10X_LD - * - @p STM32F10X_LD_VL - * - @p STM32F10X_MD - * - @p STM32F10X_MD_VL - * - @p STM32F10X_HD - * - @p STM32F10X_XL - * - @p STM32F10X_CL - * . - * This is required in order to include a vectors table with - * the correct length for the specified STM32 model. - * @{ - */ - -#include "ch.h" - -#if !defined(STM32F10X_LD) && !defined(STM32F10X_LD_VL) && \ - !defined(STM32F10X_MD) && !defined(STM32F10X_MD_VL) && \ - !defined(STM32F10X_HD) && !defined(STM32F10X_XL) && \ - !defined(STM32F10X_CL) -#include "board.h" -#endif - -#if defined(STM32F10X_MD_VL) || defined(__DOXYGEN__) -#define NUM_VECTORS 46 -#elif defined(STM32F10X_HD) || defined(STM32F10X_XL) -#define NUM_VECTORS 60 -#elif defined(STM32F10X_CL) -#define NUM_VECTORS 68 -#else -#define NUM_VECTORS 43 -#endif - -/** - * @brief Type of an IRQ vector. - */ -typedef void (*irq_vector_t)(void); - -/** - * @brief Type of a structure representing the whole vectors table. - */ -typedef struct { - uint32_t *init_stack; - irq_vector_t reset_vector; - irq_vector_t nmi_vector; - irq_vector_t hardfault_vector; - irq_vector_t memmanage_vector; - irq_vector_t busfault_vector; - irq_vector_t usagefault_vector; - irq_vector_t vector1c; - irq_vector_t vector20; - irq_vector_t vector24; - irq_vector_t vector28; - irq_vector_t svcall_vector; - irq_vector_t debugmonitor_vector; - irq_vector_t vector34; - irq_vector_t pendsv_vector; - irq_vector_t systick_vector; - irq_vector_t vectors[NUM_VECTORS]; -} vectors_t; - -#if !defined(__DOXYGEN__) -extern uint32_t __main_stack_end__; -extern void ResetHandler(void); -extern void NMIVector(void); -extern void HardFaultVector(void); -extern void MemManageVector(void); -extern void BusFaultVector(void); -extern void UsageFaultVector(void); -extern void Vector1C(void); -extern void Vector20(void); -extern void Vector24(void); -extern void Vector28(void); -extern void SVCallVector(void); -extern void DebugMonitorVector(void); -extern void Vector34(void); -extern void PendSVVector(void); -extern void SysTickVector(void); -extern void Vector40(void); -extern void Vector44(void); -extern void Vector48(void); -extern void Vector4C(void); -extern void Vector50(void); -extern void Vector54(void); -extern void Vector58(void); -extern void Vector5C(void); -extern void Vector60(void); -extern void Vector64(void); -extern void Vector68(void); -extern void Vector6C(void); -extern void Vector70(void); -extern void Vector74(void); -extern void Vector78(void); -extern void Vector7C(void); -extern void Vector80(void); -extern void Vector84(void); -extern void Vector88(void); -extern void Vector8C(void); -extern void Vector90(void); -extern void Vector94(void); -extern void Vector98(void); -extern void Vector9C(void); -extern void VectorA0(void); -extern void VectorA4(void); -extern void VectorA8(void); -extern void VectorAC(void); -extern void VectorB0(void); -extern void VectorB4(void); -extern void VectorB8(void); -extern void VectorBC(void); -extern void VectorC0(void); -extern void VectorC4(void); -extern void VectorC8(void); -extern void VectorCC(void); -extern void VectorD0(void); -extern void VectorD4(void); -extern void VectorD8(void); -extern void VectorDC(void); -extern void VectorE0(void); -extern void VectorE4(void); -extern void VectorE8(void); -#if defined(STM32F10X_MD_VL) || defined(STM32F10X_HD) || \ - defined(STM32F10X_XL) || defined(STM32F10X_CL) -extern void VectorEC(void); -extern void VectorF0(void); -extern void VectorF4(void); -#endif -#if defined(STM32F10X_HD) || defined(STM32F10X_XL) || defined(STM32F10X_CL) -extern void VectorF8(void); -extern void VectorFC(void); -extern void Vector100(void); -extern void Vector104(void); -extern void Vector108(void); -extern void Vector10C(void); -extern void Vector110(void); -extern void Vector114(void); -extern void Vector118(void); -extern void Vector11C(void); -extern void Vector120(void); -extern void Vector124(void); -extern void Vector128(void); -extern void Vector12C(void); -#endif -#if defined(STM32F10X_CL) -extern void Vector130(void); -extern void Vector134(void); -extern void Vector138(void); -extern void Vector13C(void); -extern void Vector140(void); -extern void Vector144(void); -extern void Vector148(void); -extern void Vector14C(void); -#endif -#endif - -/** - * @brief STM32 vectors table. - */ -#if !defined(__DOXYGEN__) -__attribute__ ((section("vectors"))) -#endif -vectors_t _vectors = { - &__main_stack_end__,ResetHandler, NMIVector, HardFaultVector, - MemManageVector, BusFaultVector, UsageFaultVector, Vector1C, - Vector20, Vector24, Vector28, SVCallVector, - DebugMonitorVector, Vector34, PendSVVector, SysTickVector, - { - Vector40, Vector44, Vector48, Vector4C, - Vector50, Vector54, Vector58, Vector5C, - Vector60, Vector64, Vector68, Vector6C, - Vector70, Vector74, Vector78, Vector7C, - Vector80, Vector84, Vector88, Vector8C, - Vector90, Vector94, Vector98, Vector9C, - VectorA0, VectorA4, VectorA8, VectorAC, - VectorB0, VectorB4, VectorB8, VectorBC, - VectorC0, VectorC4, VectorC8, VectorCC, - VectorD0, VectorD4, VectorD8, VectorDC, - VectorE0, VectorE4, VectorE8, -#if defined(STM32F10X_MD_VL) || defined(STM32F10X_HD) || \ - defined(STM32F10X_XL) || defined(STM32F10X_CL) - VectorEC, VectorF0, VectorF4, -#endif -#if defined(STM32F10X_HD) || defined(STM32F10X_XL) || defined(STM32F10X_CL) - VectorF8, VectorFC, Vector100, Vector104, - Vector108, Vector10C, Vector110, Vector114, - Vector118, Vector11C, Vector120, Vector124, - Vector128, Vector12C, -#endif -#if defined(STM32F10X_CL) - Vector130, Vector134, Vector138, Vector13C, - Vector140, Vector144, Vector148, Vector14C -#endif - } -}; - -/** - * @brief Unhandled exceptions handler. - * @details Any undefined exception vector points to this function by default. - * This function simply stops the system into an infinite loop. - * - * @notapi - */ -#if !defined(__DOXYGEN__) -__attribute__ ((naked)) -#endif -void _unhandled_exception(void) { - - while (TRUE) - ; -} - -void NMIVector(void) __attribute__((weak, alias("_unhandled_exception"))); -void HardFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); -void MemManageVector(void) __attribute__((weak, alias("_unhandled_exception"))); -void BusFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); -void UsageFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector1C(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector20(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector24(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector28(void) __attribute__((weak, alias("_unhandled_exception"))); -void SVCallVector(void) __attribute__((weak, alias("_unhandled_exception"))); -void DebugMonitorVector(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector34(void) __attribute__((weak, alias("_unhandled_exception"))); -void PendSVVector(void) __attribute__((weak, alias("_unhandled_exception"))); -void SysTickVector(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector40(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector44(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector48(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector4C(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector50(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector54(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector58(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector5C(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector60(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector64(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector68(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector6C(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector70(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector74(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector78(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector7C(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector80(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector84(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector88(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector8C(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector90(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector94(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector98(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector9C(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorA0(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorA4(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorA8(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorAC(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorB0(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorB4(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorB8(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorBC(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorC0(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorC4(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorC8(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorCC(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorD0(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorD4(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorD8(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorDC(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorE0(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorE4(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorE8(void) __attribute__((weak, alias("_unhandled_exception"))); -#if defined(STM32F10X_MD_VL) || defined(STM32F10X_HD) || \ - defined(STM32F10X_XL) || defined(STM32F10X_CL) -void VectorEC(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorF0(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorF4(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if defined(STM32F10X_HD) || defined(STM32F10X_XL) || defined(STM32F10X_CL) -void VectorF8(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorFC(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector100(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector104(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector108(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector10C(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector110(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector114(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector118(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector11C(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector120(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector124(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector128(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector12C(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif -#if defined(STM32F10X_CL) -void Vector130(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector134(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector138(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector13C(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector140(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector144(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector148(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector14C(void) __attribute__((weak, alias("_unhandled_exception"))); -#endif - -/** @} */ diff --git a/firmware/chibios/os/ports/GCC/ARMCMx/STM32F4xx/cmparams.h b/firmware/chibios/os/ports/GCC/ARMCMx/STM32F4xx/cmparams.h deleted file mode 100644 index c3fdc417d1..0000000000 --- a/firmware/chibios/os/ports/GCC/ARMCMx/STM32F4xx/cmparams.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file GCC/ARMCMx/STM32F4xx/cmparams.h - * @brief ARM Cortex-M4 parameters for the STM32F4xx. - * - * @defgroup ARMCMx_STM32F4xx STM32F4xx Specific Parameters - * @ingroup ARMCMx_SPECIFIC - * @details This file contains the Cortex-M4 specific parameters for the - * STM32F4xx platform. - * @{ - */ - -#ifndef _CMPARAMS_H_ -#define _CMPARAMS_H_ - -/** - * @brief Cortex core model. - */ -#define CORTEX_MODEL CORTEX_M4 - -/** - * @brief Systick unit presence. - */ -#define CORTEX_HAS_ST TRUE - -/** - * @brief Memory Protection unit presence. - */ -#define CORTEX_HAS_MPU TRUE - -/** - * @brief Floating Point unit presence. - */ -#define CORTEX_HAS_FPU TRUE - -/** - * @brief Number of bits in priority masks. - */ -#define CORTEX_PRIORITY_BITS 4 - -#endif /* _CMPARAMS_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/ports/GCC/ARMCMx/STM32F4xx/port.mk b/firmware/chibios/os/ports/GCC/ARMCMx/STM32F4xx/port.mk deleted file mode 100644 index 3fd6a41304..0000000000 --- a/firmware/chibios/os/ports/GCC/ARMCMx/STM32F4xx/port.mk +++ /dev/null @@ -1,15 +0,0 @@ -# List of the ChibiOS/RT Cortex-M4 STM32 port files. -PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \ - $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/vectors.c \ - ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \ - ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \ - ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c - -PORTASM = - -PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \ - ${CHIBIOS}/os/ports/common/ARMCMx \ - ${CHIBIOS}/os/ports/GCC/ARMCMx \ - ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F4xx - -PORTLD = ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F4xx/ld diff --git a/firmware/chibios/os/ports/GCC/ARMCMx/STM32F4xx/vectors.c b/firmware/chibios/os/ports/GCC/ARMCMx/STM32F4xx/vectors.c deleted file mode 100644 index e3367f0995..0000000000 --- a/firmware/chibios/os/ports/GCC/ARMCMx/STM32F4xx/vectors.c +++ /dev/null @@ -1,338 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file GCC/ARMCMx/STM32F4xx/vectors.c - * @brief Interrupt vectors for the STM32F4xx family. - * - * @defgroup ARMCMx_STM32F4xx_VECTORS STM32F4xx Interrupt Vectors - * @ingroup ARMCMx_SPECIFIC - * @details Interrupt vectors for the STM32F4xx family. - * @{ - */ - -#include "ch.h" - -/** - * @brief Type of an IRQ vector. - */ -typedef void (*irq_vector_t)(void); - -/** - * @brief Type of a structure representing the whole vectors table. - */ -typedef struct { - uint32_t *init_stack; - irq_vector_t reset_vector; - irq_vector_t nmi_vector; - irq_vector_t hardfault_vector; - irq_vector_t memmanage_vector; - irq_vector_t busfault_vector; - irq_vector_t usagefault_vector; - irq_vector_t vector1c; - irq_vector_t vector20; - irq_vector_t vector24; - irq_vector_t vector28; - irq_vector_t svcall_vector; - irq_vector_t debugmonitor_vector; - irq_vector_t vector34; - irq_vector_t pendsv_vector; - irq_vector_t systick_vector; - irq_vector_t vectors[91]; -} vectors_t; - -#if !defined(__DOXYGEN__) -extern uint32_t __main_stack_end__; -extern void ResetHandler(void); -extern void NMIVector(void); -extern void HardFaultVector(void); -extern void MemManageVector(void); -extern void BusFaultVector(void); -extern void UsageFaultVector(void); -extern void Vector1C(void); -extern void Vector20(void); -extern void Vector24(void); -extern void Vector28(void); -extern void SVCallVector(void); -extern void DebugMonitorVector(void); -extern void Vector34(void); -extern void PendSVVector(void); -extern void SysTickVector(void); -extern void Vector40(void); -extern void Vector44(void); -extern void Vector48(void); -extern void Vector4C(void); -extern void Vector50(void); -extern void Vector54(void); -extern void Vector58(void); -extern void Vector5C(void); -extern void Vector60(void); -extern void Vector64(void); -extern void Vector68(void); -extern void Vector6C(void); -extern void Vector70(void); -extern void Vector74(void); -extern void Vector78(void); -extern void Vector7C(void); -extern void Vector80(void); -extern void Vector84(void); -extern void Vector88(void); -extern void Vector8C(void); -extern void Vector90(void); -extern void Vector94(void); -extern void Vector98(void); -extern void Vector9C(void); -extern void VectorA0(void); -extern void VectorA4(void); -extern void VectorA8(void); -extern void VectorAC(void); -extern void VectorB0(void); -extern void VectorB4(void); -extern void VectorB8(void); -extern void VectorBC(void); -extern void VectorC0(void); -extern void VectorC4(void); -extern void VectorC8(void); -extern void VectorCC(void); -extern void VectorD0(void); -extern void VectorD4(void); -extern void VectorD8(void); -extern void VectorDC(void); -extern void VectorE0(void); -extern void VectorE4(void); -extern void VectorE8(void); -extern void VectorEC(void); -extern void VectorF0(void); -extern void VectorF4(void); -extern void VectorF8(void); -extern void VectorFC(void); -extern void Vector100(void); -extern void Vector104(void); -extern void Vector108(void); -extern void Vector10C(void); -extern void Vector110(void); -extern void Vector114(void); -extern void Vector118(void); -extern void Vector11C(void); -extern void Vector120(void); -extern void Vector124(void); -extern void Vector128(void); -extern void Vector12C(void); -extern void Vector130(void); -extern void Vector134(void); -extern void Vector138(void); -extern void Vector13C(void); -extern void Vector140(void); -extern void Vector144(void); -extern void Vector148(void); -extern void Vector14C(void); -extern void Vector150(void); -extern void Vector154(void); -extern void Vector158(void); -extern void Vector15C(void); -extern void Vector160(void); -extern void Vector164(void); -extern void Vector168(void); -extern void Vector16C(void); -extern void Vector170(void); -extern void Vector174(void); -extern void Vector178(void); -extern void Vector17C(void); -extern void Vector180(void); -extern void Vector184(void); -extern void Vector188(void); -extern void Vector18C(void); -extern void Vector190(void); -extern void Vector194(void); -extern void Vector198(void); -extern void Vector19C(void); -extern void Vector1A0(void); -extern void Vector1A4(void); -extern void Vector1A8(void); -#endif - -/** - * @brief STM32 vectors table. - */ -#if !defined(__DOXYGEN__) -__attribute__ ((section("vectors"))) -#endif -vectors_t _vectors = { - &__main_stack_end__,ResetHandler, NMIVector, HardFaultVector, - MemManageVector, BusFaultVector, UsageFaultVector, Vector1C, - Vector20, Vector24, Vector28, SVCallVector, - DebugMonitorVector, Vector34, PendSVVector, SysTickVector, - { - Vector40, Vector44, Vector48, Vector4C, - Vector50, Vector54, Vector58, Vector5C, - Vector60, Vector64, Vector68, Vector6C, - Vector70, Vector74, Vector78, Vector7C, - Vector80, Vector84, Vector88, Vector8C, - Vector90, Vector94, Vector98, Vector9C, - VectorA0, VectorA4, VectorA8, VectorAC, - VectorB0, VectorB4, VectorB8, VectorBC, - VectorC0, VectorC4, VectorC8, VectorCC, - VectorD0, VectorD4, VectorD8, VectorDC, - VectorE0, VectorE4, VectorE8, VectorEC, - VectorF0, VectorF4, VectorF8, VectorFC, - Vector100, Vector104, Vector108, Vector10C, - Vector110, Vector114, Vector118, Vector11C, - Vector120, Vector124, Vector128, Vector12C, - Vector130, Vector134, Vector138, Vector13C, - Vector140, Vector144, Vector148, Vector14C, - Vector150, Vector154, Vector158, Vector15C, - Vector160, Vector164, Vector168, Vector16C, - Vector170, Vector174, Vector178, Vector17C, - Vector180, Vector184, Vector188, Vector18C, - Vector190, Vector194, Vector198, Vector19C, - Vector1A0, Vector1A4, Vector1A8 - } -}; - -/** - * @brief Unhandled exceptions handler. - * @details Any undefined exception vector points to this function by default. - * This function simply stops the system into an infinite loop. - * - * @notapi - */ -#if !defined(__DOXYGEN__) -__attribute__ ((naked)) -#endif -void _unhandled_exception(void) { - - while (TRUE) - ; -} - -void NMIVector(void) __attribute__((weak, alias("_unhandled_exception"))); -void HardFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); -void MemManageVector(void) __attribute__((weak, alias("_unhandled_exception"))); -void BusFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); -void UsageFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector1C(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector20(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector24(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector28(void) __attribute__((weak, alias("_unhandled_exception"))); -void SVCallVector(void) __attribute__((weak, alias("_unhandled_exception"))); -void DebugMonitorVector(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector34(void) __attribute__((weak, alias("_unhandled_exception"))); -void PendSVVector(void) __attribute__((weak, alias("_unhandled_exception"))); -void SysTickVector(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector40(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector44(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector48(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector4C(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector50(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector54(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector58(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector5C(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector60(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector64(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector68(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector6C(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector70(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector74(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector78(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector7C(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector80(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector84(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector88(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector8C(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector90(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector94(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector98(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector9C(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorA0(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorA4(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorA8(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorAC(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorB0(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorB4(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorB8(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorBC(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorC0(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorC4(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorC8(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorCC(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorD0(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorD4(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorD8(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorDC(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorE0(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorE4(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorE8(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorEC(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorF0(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorF4(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorF8(void) __attribute__((weak, alias("_unhandled_exception"))); -void VectorFC(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector100(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector104(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector108(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector10C(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector110(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector114(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector118(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector11C(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector120(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector124(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector128(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector12C(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector130(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector134(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector138(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector13C(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector140(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector144(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector148(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector14C(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector150(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector154(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector158(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector15C(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector160(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector164(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector168(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector16C(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector170(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector174(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector178(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector17C(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector180(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector184(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector188(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector18C(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector190(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector194(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector198(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector19C(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector1A0(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector1A4(void) __attribute__((weak, alias("_unhandled_exception"))); -void Vector1A8(void) __attribute__((weak, alias("_unhandled_exception"))); - -/** @} */ diff --git a/firmware/chibios/os/ports/GCC/ARMCMx/chcore.c b/firmware/chibios/os/ports/GCC/ARMCMx/chcore.c deleted file mode 100644 index b826d132b2..0000000000 --- a/firmware/chibios/os/ports/GCC/ARMCMx/chcore.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file GCC/ARMCMx/chcore.c - * @brief ARM Cortex-Mx port code. - * - * @addtogroup ARMCMx_CORE - * @{ - */ - -#include "ch.h" - -/** - * @brief Halts the system. - * @note The function is declared as a weak symbol, it is possible - * to redefine it in your application code. - */ -#if !defined(__DOXYGEN__) -__attribute__((weak)) -#endif -void port_halt(void) { - - port_disable(); - while (TRUE) { - } -} - -/** @} */ diff --git a/firmware/chibios/os/ports/GCC/ARMCMx/chcore.h b/firmware/chibios/os/ports/GCC/ARMCMx/chcore.h deleted file mode 100644 index d1c542f9cb..0000000000 --- a/firmware/chibios/os/ports/GCC/ARMCMx/chcore.h +++ /dev/null @@ -1,195 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file GCC/ARMCMx/chcore.h - * @brief ARM Cortex-Mx port macros and structures. - * - * @addtogroup ARMCMx_CORE - * @{ - */ - -#ifndef _CHCORE_H_ -#define _CHCORE_H_ - -/*===========================================================================*/ -/* Port constants (common). */ -/*===========================================================================*/ - -/* Added to make the header stand-alone when included from asm.*/ -#ifndef FALSE -#define FALSE 0 -#endif -#ifndef TRUE -#define TRUE (!FALSE) -#endif - -#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */ -#define CORTEX_M1 1 /**< @brief Cortex-M1 variant. */ -#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */ -#define CORTEX_M4 4 /**< @brief Cortex-M4 variant. */ - -/* Inclusion of the Cortex-Mx implementation specific parameters.*/ -#include "cmparams.h" - -/* Cortex model check, only M0 and M3 supported right now.*/ -#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M3) || \ - (CORTEX_MODEL == CORTEX_M4) -#elif (CORTEX_MODEL == CORTEX_M1) -#warning "untested Cortex-M model" -#else -#error "unknown or unsupported Cortex-M model" -#endif - -/** - * @brief Total priority levels. - */ -#define CORTEX_PRIORITY_LEVELS (1 << CORTEX_PRIORITY_BITS) - -/** - * @brief Minimum priority level. - * @details This minimum priority level is calculated from the number of - * priority bits supported by the specific Cortex-Mx implementation. - */ -#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1) - -/** - * @brief Maximum priority level. - * @details The maximum allowed priority level is always zero. - */ -#define CORTEX_MAXIMUM_PRIORITY 0 - -/*===========================================================================*/ -/* Port macros (common). */ -/*===========================================================================*/ - -/** - * @brief Priority level verification macro. - */ -#define CORTEX_IS_VALID_PRIORITY(n) \ - (((n) >= 0) && ((n) < CORTEX_PRIORITY_LEVELS)) - -/** - * @brief Priority level verification macro. - */ -#define CORTEX_IS_VALID_KERNEL_PRIORITY(n) \ - (((n) >= CORTEX_MAX_KERNEL_PRIORITY) && ((n) < CORTEX_PRIORITY_LEVELS)) - -/** - * @brief Priority level to priority mask conversion macro. - */ -#define CORTEX_PRIORITY_MASK(n) \ - ((n) << (8 - CORTEX_PRIORITY_BITS)) - -/*===========================================================================*/ -/* Port configurable parameters (common). */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Port derived parameters (common). */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Port exported info (common). */ -/*===========================================================================*/ - -/** - * @brief Macro defining a generic ARM architecture. - */ -#define CH_ARCHITECTURE_ARM - -/** - * @brief Name of the compiler supported by this port. - */ -#define CH_COMPILER_NAME "GCC " __VERSION__ - -/*===========================================================================*/ -/* Port implementation part (common). */ -/*===========================================================================*/ - -/* Includes the sub-architecture-specific part.*/ -#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M1) -#include "chcore_v6m.h" -#elif (CORTEX_MODEL == CORTEX_M3) || (CORTEX_MODEL == CORTEX_M4) -#include "chcore_v7m.h" -#endif - -#if !defined(_FROM_ASM_) - -#include "nvic.h" - -/* The following declarations are there just for Doxygen documentation, the - real declarations are inside the sub-headers.*/ -#if defined(__DOXYGEN__) - -/** - * @brief Stack and memory alignment enforcement. - * @note In this architecture the stack alignment is enforced to 64 bits, - * 32 bits alignment is supported by hardware but deprecated by ARM, - * the implementation choice is to not offer the option. - */ -typedef uint64_t stkalign_t; - -/** - * @brief Interrupt saved context. - * @details This structure represents the stack frame saved during a - * preemption-capable interrupt handler. - * @note It is implemented to match the Cortex-Mx exception context. - */ -struct extctx {}; - -/** - * @brief System saved context. - * @details This structure represents the inner stack frame during a context - * switching. - */ -struct intctx {}; - -#endif /* defined(__DOXYGEN__) */ - -/** - * @brief Excludes the default @p chSchIsPreemptionRequired()implementation. - */ -#define PORT_OPTIMIZED_ISPREEMPTIONREQUIRED - -#if (CH_TIME_QUANTUM > 0) || defined(__DOXYGEN__) -/** - * @brief Inline-able version of this kernel function. - */ -#define chSchIsPreemptionRequired() \ - (currp->p_preempt ? firstprio(&rlist.r_queue) > currp->p_prio : \ - firstprio(&rlist.r_queue) >= currp->p_prio) -#else /* CH_TIME_QUANTUM == 0 */ -#define chSchIsPreemptionRequired() \ - (firstprio(&rlist.r_queue) > currp->p_prio) -#endif /* CH_TIME_QUANTUM == 0 */ - -#endif /* _FROM_ASM_ */ - -#endif /* _CHCORE_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/ports/GCC/ARMCMx/chcore_v6m.c b/firmware/chibios/os/ports/GCC/ARMCMx/chcore_v6m.c deleted file mode 100644 index 33bb8ab453..0000000000 --- a/firmware/chibios/os/ports/GCC/ARMCMx/chcore_v6m.c +++ /dev/null @@ -1,206 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file GCC/ARMCMx/chcore_v6m.c - * @brief ARMv6-M architecture port code. - * - * @addtogroup ARMCMx_V6M_CORE - * @{ - */ - -#include "ch.h" - -/*===========================================================================*/ -/* Port interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief System Timer vector. - * @details This interrupt is used as system tick. - * @note The timer must be initialized in the startup code. - */ -CH_IRQ_HANDLER(SysTickVector) { - - CH_IRQ_PROLOGUE(); - - chSysLockFromIsr(); - chSysTimerHandlerI(); - chSysUnlockFromIsr(); - - CH_IRQ_EPILOGUE(); -} - -#if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__) -/** - * @brief NMI vector. - * @details The NMI vector is used for exception mode re-entering after a - * context switch. - */ -void NMIVector(void) { - register struct extctx *ctxp; - - /* Discarding the current exception context and positioning the stack to - point to the real one.*/ - asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory"); - ctxp++; - asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory"); - port_unlock_from_isr(); -} -#endif /* !CORTEX_ALTERNATE_SWITCH */ - -#if CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__) -/** - * @brief PendSV vector. - * @details The PendSV vector is used for exception mode re-entering after a - * context switch. - */ -void PendSVVector(void) { - register struct extctx *ctxp; - - /* Discarding the current exception context and positioning the stack to - point to the real one.*/ - asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory"); - ctxp++; - asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory"); -} -#endif /* CORTEX_ALTERNATE_SWITCH */ - -/*===========================================================================*/ -/* Port exported functions. */ -/*===========================================================================*/ - -/** - * @brief IRQ epilogue code. - * - * @param[in] lr value of the @p LR register on ISR entry - */ -void _port_irq_epilogue(regarm_t lr) { - - if (lr != (regarm_t)0xFFFFFFF1) { - register struct extctx *ctxp; - - port_lock_from_isr(); - /* Adding an artificial exception return context, there is no need to - populate it fully.*/ - asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory"); - ctxp--; - asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory"); - ctxp->xpsr = (regarm_t)0x01000000; - - /* The exit sequence is different depending on if a preemption is - required or not.*/ - if (chSchIsPreemptionRequired()) { - /* Preemption is required we need to enforce a context switch.*/ - ctxp->pc = (void *)_port_switch_from_isr; - } - else { - /* Preemption not required, we just need to exit the exception - atomically.*/ - ctxp->pc = (void *)_port_exit_from_isr; - } - - /* Note, returning without unlocking is intentional, this is done in - order to keep the rest of the context switch atomic.*/ - } -} - -/** - * @brief Post-IRQ switch code. - * @details The switch is performed in thread context then an NMI exception - * is enforced in order to return to the exact point before the - * preemption. - */ -#if !defined(__DOXYGEN__) -__attribute__((naked)) -#endif -void _port_switch_from_isr(void) { - - dbg_check_lock(); - chSchDoReschedule(); - dbg_check_unlock(); - asm volatile ("_port_exit_from_isr:" : : : "memory"); -#if CORTEX_ALTERNATE_SWITCH - SCB_ICSR = ICSR_PENDSVSET; - port_unlock(); -#else - SCB_ICSR = ICSR_NMIPENDSET; -#endif - /* The following loop should never be executed, the exception will kick in - immediately.*/ - while (TRUE) - ; -} - -/** - * @brief Performs a context switch between two threads. - * @details This is the most critical code in any port, this function - * is responsible for the context switch between 2 threads. - * @note The implementation of this code affects directly the context - * switch performance so optimize here as much as you can. - * - * @param[in] ntp the thread to be switched in - * @param[in] otp the thread to be switched out - */ -#if !defined(__DOXYGEN__) -__attribute__((naked)) -#endif -void _port_switch(Thread *ntp, Thread *otp) { - register struct intctx *r13 asm ("r13"); - - asm volatile ("push {r4, r5, r6, r7, lr} \n\t" - "mov r4, r8 \n\t" - "mov r5, r9 \n\t" - "mov r6, r10 \n\t" - "mov r7, r11 \n\t" - "push {r4, r5, r6, r7}" : : : "memory"); - - otp->p_ctx.r13 = r13; - r13 = ntp->p_ctx.r13; - - asm volatile ("pop {r4, r5, r6, r7} \n\t" - "mov r8, r4 \n\t" - "mov r9, r5 \n\t" - "mov r10, r6 \n\t" - "mov r11, r7 \n\t" - "pop {r4, r5, r6, r7, pc}" : : "r" (r13) : "memory"); -} - -/** - * @brief Start a thread by invoking its work function. - * @details If the work function returns @p chThdExit() is automatically - * invoked. - */ -void _port_thread_start(void) { - - chSysUnlock(); - asm volatile ("mov r0, r5 \n\t" - "blx r4 \n\t" - "bl chThdExit"); -} - -/** @} */ diff --git a/firmware/chibios/os/ports/GCC/ARMCMx/chcore_v6m.h b/firmware/chibios/os/ports/GCC/ARMCMx/chcore_v6m.h deleted file mode 100644 index be2d4f8e7b..0000000000 --- a/firmware/chibios/os/ports/GCC/ARMCMx/chcore_v6m.h +++ /dev/null @@ -1,385 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file GCC/ARMCMx/chcore_v6m.h - * @brief ARMv6-M architecture port macros and structures. - * - * @addtogroup ARMCMx_V6M_CORE - * @{ - */ - -#ifndef _CHCORE_V6M_H_ -#define _CHCORE_V6M_H_ - -/*===========================================================================*/ -/* Port constants. */ -/*===========================================================================*/ - -/** - * @brief PendSV priority level. - * @note This priority is enforced to be equal to @p 0, - * this handler always has the highest priority that cannot preempt - * the kernel. - */ -#define CORTEX_PRIORITY_PENDSV 0 - -/*===========================================================================*/ -/* Port macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Port configurable parameters. */ -/*===========================================================================*/ - -/** - * @brief Stack size for the system idle thread. - * @details This size depends on the idle thread implementation, usually - * the idle thread should take no more space than those reserved - * by @p PORT_INT_REQUIRED_STACK. - * @note In this port it is set to 16 because the idle thread does have - * a stack frame when compiling without optimizations. You may - * reduce this value to zero when compiling with optimizations. - */ -#if !defined(PORT_IDLE_THREAD_STACK_SIZE) -#define PORT_IDLE_THREAD_STACK_SIZE 16 -#endif - -/** - * @brief Per-thread stack overhead for interrupts servicing. - * @details This constant is used in the calculation of the correct working - * area size. - * @note In this port this value is conservatively set to 64 because the - * function @p chSchDoReschedule() can have a stack frame, especially - * with compiler optimizations disabled. The value can be reduced - * when compiler optimizations are enabled. - */ -#if !defined(PORT_INT_REQUIRED_STACK) -#define PORT_INT_REQUIRED_STACK 64 -#endif - -/** - * @brief Enables the use of the WFI instruction in the idle thread loop. - */ -#if !defined(CORTEX_ENABLE_WFI_IDLE) -#define CORTEX_ENABLE_WFI_IDLE FALSE -#endif - -/** - * @brief SYSTICK handler priority. - * @note The default SYSTICK handler priority is calculated as the priority - * level in the middle of the numeric priorities range. - */ -#if !defined(CORTEX_PRIORITY_SYSTICK) -#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1) -#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK) -/* If it is externally redefined then better perform a validity check on it.*/ -#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK" -#endif - -/** - * @brief Alternate preemption method. - * @details Activating this option will make the Kernel use the PendSV - * handler for preemption instead of the NMI handler. - */ -#ifndef CORTEX_ALTERNATE_SWITCH -#define CORTEX_ALTERNATE_SWITCH FALSE -#endif - -/*===========================================================================*/ -/* Port derived parameters. */ -/*===========================================================================*/ - -/** - * @brief Maximum usable priority for normal ISRs. - */ -#if CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__) -#define CORTEX_MAX_KERNEL_PRIORITY 1 -#else -#define CORTEX_MAX_KERNEL_PRIORITY 0 -#endif - -/*===========================================================================*/ -/* Port exported info. */ -/*===========================================================================*/ - -/** - * @brief Macro defining the specific ARM architecture. - */ -#define CH_ARCHITECTURE_ARM_v6M - -/** - * @brief Name of the implemented architecture. - */ -#define CH_ARCHITECTURE_NAME "ARMv6-M" - -/** - * @brief Name of the architecture variant. - */ -#if (CORTEX_MODEL == CORTEX_M0) || defined(__DOXYGEN__) -#define CH_CORE_VARIANT_NAME "Cortex-M0" -#elif (CORTEX_MODEL == CORTEX_M1) -#define CH_CORE_VARIANT_NAME "Cortex-M1" -#endif - -/** - * @brief Port-specific information string. - */ -#if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__) -#define CH_PORT_INFO "Preemption through NMI" -#else -#define CH_PORT_INFO "Preemption through PendSV" -#endif - -/*===========================================================================*/ -/* Port implementation part. */ -/*===========================================================================*/ - -#if !defined(_FROM_ASM_) - -/** - * @brief Generic ARM register. - */ -typedef void *regarm_t; - - /* The documentation of the following declarations is in chconf.h in order - to not have duplicated structure names into the documentation.*/ -#if !defined(__DOXYGEN__) - -typedef uint64_t stkalign_t __attribute__ ((aligned (8))); - -struct extctx { - regarm_t r0; - regarm_t r1; - regarm_t r2; - regarm_t r3; - regarm_t r12; - regarm_t lr_thd; - regarm_t pc; - regarm_t xpsr; -}; - -struct intctx { - regarm_t r8; - regarm_t r9; - regarm_t r10; - regarm_t r11; - regarm_t r4; - regarm_t r5; - regarm_t r6; - regarm_t r7; - regarm_t lr; -}; - -#endif /* !defined(__DOXYGEN__) */ - -/** - * @brief Platform dependent part of the @p Thread structure. - * @details In this port the structure just holds a pointer to the @p intctx - * structure representing the stack pointer at context switch time. - */ -struct context { - struct intctx *r13; -}; - -/** - * @brief Platform dependent part of the @p chThdCreateI() API. - * @details This code usually setup the context switching frame represented - * by an @p intctx structure. - */ -#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ - tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \ - wsize - \ - sizeof(struct intctx)); \ - tp->p_ctx.r13->r4 = (void *)(pf); \ - tp->p_ctx.r13->r5 = (void *)(arg); \ - tp->p_ctx.r13->lr = (void *)(_port_thread_start); \ -} - -/** - * @brief Enforces a correct alignment for a stack area size value. - */ -#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) - -/** - * @brief Computes the thread working area global size. - */ -#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ - sizeof(struct intctx) + \ - sizeof(struct extctx) + \ - (n) + (PORT_INT_REQUIRED_STACK)) - -/** - * @brief Static working area allocation. - * @details This macro is used to allocate a static thread working area - * aligned as both position and size. - */ -#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] - -/** - * @brief IRQ prologue code. - * @details This macro must be inserted at the start of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_PROLOGUE() \ - regarm_t _saved_lr; \ - asm volatile ("mov %0, lr" : "=r" (_saved_lr) : : "memory") - -/** - * @brief IRQ epilogue code. - * @details This macro must be inserted at the end of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_EPILOGUE() _port_irq_epilogue(_saved_lr) - -/** - * @brief IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_IRQ_HANDLER(id) void id(void) - -/** - * @brief Fast IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_FAST_IRQ_HANDLER(id) void id(void) - -int getRemainingStack(Thread *otp); - -/** - * @brief Port-related initialization code. - */ -#define port_init() { \ - SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \ - nvicSetSystemHandlerPriority(HANDLER_PENDSV, \ - CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); \ - nvicSetSystemHandlerPriority(HANDLER_SYSTICK, \ - CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \ -} - -/** - * @brief Kernel-lock action. - * @details Usually this function just disables interrupts but may perform - * more actions. - */ -#define port_lock() asm volatile ("cpsid i" : : : "memory") - -/** - * @brief Kernel-unlock action. - * @details Usually this function just enables interrupts but may perform - * more actions. - */ -#define port_unlock() asm volatile ("cpsie i" : : : "memory") - -/** - * @brief Kernel-lock action from an interrupt handler. - * @details This function is invoked before invoking I-class APIs from - * interrupt handlers. The implementation is architecture dependent, - * in its simplest form it is void. - * @note Same as @p port_lock() in this port. - */ -#define port_lock_from_isr() port_lock() - -/** - * @brief Kernel-unlock action from an interrupt handler. - * @details This function is invoked after invoking I-class APIs from interrupt - * handlers. The implementation is architecture dependent, in its - * simplest form it is void. - * @note Same as @p port_lock() in this port. - */ -#define port_unlock_from_isr() port_unlock() - -/** - * @brief Disables all the interrupt sources. - */ -#define port_disable() asm volatile ("cpsid i" : : : "memory") - -/** - * @brief Disables the interrupt sources below kernel-level priority. - */ -#define port_suspend() asm volatile ("cpsid i" : : : "memory") - -/** - * @brief Enables all the interrupt sources. - */ -#define port_enable() asm volatile ("cpsie i" : : : "memory") - -/** - * @brief Enters an architecture-dependent IRQ-waiting mode. - * @details The function is meant to return when an interrupt becomes pending. - * The simplest implementation is an empty function or macro but this - * would not take advantage of architecture-specific power saving - * modes. - * @note Implemented as an inlined @p WFI instruction. - */ -#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__) -#define port_wait_for_interrupt() asm volatile ("wfi" : : : "memory") -#else -#define port_wait_for_interrupt() -#endif - -/** - * @brief Performs a context switch between two threads. - * @details This is the most critical code in any port, this function - * is responsible for the context switch between 2 threads. - * @note The implementation of this code affects directly the context - * switch performance so optimize here as much as you can. - * - * @param[in] ntp the thread to be switched in - * @param[in] otp the thread to be switched out - */ -#if !CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__) -#define port_switch(ntp, otp) _port_switch(ntp, otp) -#else -#define port_switch(ntp, otp) { \ - register struct intctx *r13 asm ("r13"); \ - if ((stkalign_t *)(r13 - 1) < otp->p_stklimit) \ - chDbgPanic("stack overflow"); \ - _port_switch(ntp, otp); \ -} -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void port_halt(void); - void _port_irq_epilogue(regarm_t lr); - void _port_switch_from_isr(void); - void _port_exit_from_isr(void); - void _port_switch(Thread *ntp, Thread *otp); - void _port_thread_start(void); -#ifdef __cplusplus -} -#endif - -#endif /* _FROM_ASM_ */ - -#endif /* _CHCORE_V6M_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/ports/GCC/ARMCMx/chcore_v7m.c b/firmware/chibios/os/ports/GCC/ARMCMx/chcore_v7m.c deleted file mode 100644 index fff6939f0f..0000000000 --- a/firmware/chibios/os/ports/GCC/ARMCMx/chcore_v7m.c +++ /dev/null @@ -1,260 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file GCC/ARMCMx/chcore_v7m.c - * @brief ARMv7-M architecture port code. - * - * @addtogroup ARMCMx_V7M_CORE - * @{ - */ - -#include "ch.h" - -/*===========================================================================*/ -/* Port interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief System Timer vector. - * @details This interrupt is used as system tick. - * @note The timer must be initialized in the startup code. - */ -CH_IRQ_HANDLER(SysTickVector) { - - CH_IRQ_PROLOGUE(); - - chSysLockFromIsr(); - chSysTimerHandlerI(); - chSysUnlockFromIsr(); - - CH_IRQ_EPILOGUE(); -} - -#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) -/** - * @brief SVCall vector. - * @details The SVCall vector is used for exception mode re-entering after a - * context switch. - * @note The SVCallVector vector is only used in advanced kernel mode. - */ -void SVCallVector(void) { - struct extctx *ctxp; - -#if CORTEX_USE_FPU - /* Enforcing unstacking of the FP part of the context.*/ - SCB_FPCCR &= ~FPCCR_LSPACT; -#endif - - /* Current PSP value.*/ - asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory"); - - /* Discarding the current exception context and positioning the stack to - point to the real one.*/ - ctxp++; - - /* Restoring real position of the original stack frame.*/ - asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory"); - port_unlock_from_isr(); -} -#endif /* !CORTEX_SIMPLIFIED_PRIORITY */ - -#if CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) -/** - * @brief PendSV vector. - * @details The PendSV vector is used for exception mode re-entering after a - * context switch. - * @note The PendSV vector is only used in compact kernel mode. - */ -void PendSVVector(void) { - struct extctx *ctxp; - -#if CORTEX_USE_FPU - /* Enforcing unstacking of the FP part of the context.*/ - SCB_FPCCR &= ~FPCCR_LSPACT; -#endif - - /* Current PSP value.*/ - asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory"); - - /* Discarding the current exception context and positioning the stack to - point to the real one.*/ - ctxp++; - - /* Restoring real position of the original stack frame.*/ - asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory"); -} -#endif /* CORTEX_SIMPLIFIED_PRIORITY */ - -/*===========================================================================*/ -/* Port exported functions. */ -/*===========================================================================*/ - -/** - * @brief Port-related initialization code. - */ -void _port_init(void) { - - /* Initialization of the vector table and priority related settings.*/ - SCB_VTOR = CORTEX_VTOR_INIT; - SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(CORTEX_PRIGROUP_INIT); - - /* Initialization of the system vectors used by the port.*/ - nvicSetSystemHandlerPriority(HANDLER_SVCALL, - CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL)); - nvicSetSystemHandlerPriority(HANDLER_PENDSV, - CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); - nvicSetSystemHandlerPriority(HANDLER_SYSTICK, - CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); -} - -#if !CH_OPTIMIZE_SPEED -void _port_lock(void) { - register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; - asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory"); -} - -void _port_unlock(void) { - register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED; - asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory"); -} -#endif - -/** - * @brief Exception exit redirection to _port_switch_from_isr(). - */ -void _port_irq_epilogue(void) { - - port_lock_from_isr(); - if ((SCB_ICSR & ICSR_RETTOBASE) != 0) { - struct extctx *ctxp; - -#if CORTEX_USE_FPU - /* Enforcing a lazy FPU state save. Note, it goes in the original - context because the FPCAR register has not been modified.*/ - asm volatile ("vmrs APSR_nzcv, FPSCR" : : : "memory"); -#endif - - /* Current PSP value.*/ - asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory"); - - /* Adding an artificial exception return context, there is no need to - populate it fully.*/ - ctxp--; - ctxp->xpsr = (regarm_t)0x01000000; -#if CORTEX_USE_FPU - ctxp->fpscr = (regarm_t)SCB_FPDSCR; -#endif - asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory"); - - /* The exit sequence is different depending on if a preemption is - required or not.*/ - if (chSchIsPreemptionRequired()) { - /* Preemption is required we need to enforce a context switch.*/ - ctxp->pc = (regarm_t)_port_switch_from_isr; - } - else { - /* Preemption not required, we just need to exit the exception - atomically.*/ - ctxp->pc = (regarm_t)_port_exit_from_isr; - } - - /* Note, returning without unlocking is intentional, this is done in - order to keep the rest of the context switch atomic.*/ - return; - } - port_unlock_from_isr(); -} - -/** - * @brief Post-IRQ switch code. - * @details Exception handlers return here for context switching. - */ -#if !defined(__DOXYGEN__) -__attribute__((naked)) -#endif -void _port_switch_from_isr(void) { - - dbg_check_lock(); - chSchDoReschedule(); - dbg_check_unlock(); - asm volatile ("_port_exit_from_isr:" : : : "memory"); -#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) - asm volatile ("svc #0"); -#else /* CORTEX_SIMPLIFIED_PRIORITY */ - SCB_ICSR = ICSR_PENDSVSET; - port_unlock(); - while (TRUE) - ; -#endif /* CORTEX_SIMPLIFIED_PRIORITY */ -} - -/** - * @brief Performs a context switch between two threads. - * @details This is the most critical code in any port, this function - * is responsible for the context switch between 2 threads. - * @note The implementation of this code affects directly the context - * switch performance so optimize here as much as you can. - * - * @param[in] ntp the thread to be switched in - * @param[in] otp the thread to be switched out - */ -#if !defined(__DOXYGEN__) -__attribute__((naked)) -#endif -void _port_switch(Thread *ntp, Thread *otp) { - - asm volatile ("push {r4, r5, r6, r7, r8, r9, r10, r11, lr}" - : : : "memory"); -#if CORTEX_USE_FPU - asm volatile ("vpush {s16-s31}" : : : "memory"); -#endif - - asm volatile ("str sp, [%1, #12] \n\t" - "ldr sp, [%0, #12]" : : "r" (ntp), "r" (otp)); - -#if CORTEX_USE_FPU - asm volatile ("vpop {s16-s31}" : : : "memory"); -#endif - asm volatile ("pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}" - : : : "memory"); -} - -/** - * @brief Start a thread by invoking its work function. - * @details If the work function returns @p chThdExit() is automatically - * invoked. - */ -void _port_thread_start(void) { - - chSysUnlock(); - asm volatile ("mov r0, r5 \n\t" - "blx r4 \n\t" - "bl chThdExit"); -} - -/** @} */ diff --git a/firmware/chibios/os/ports/GCC/ARMCMx/chcore_v7m.h b/firmware/chibios/os/ports/GCC/ARMCMx/chcore_v7m.h deleted file mode 100644 index 1125859e21..0000000000 --- a/firmware/chibios/os/ports/GCC/ARMCMx/chcore_v7m.h +++ /dev/null @@ -1,543 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file GCC/ARMCMx/chcore_v7m.h - * @brief ARMv7-M architecture port macros and structures. - * - * @addtogroup ARMCMx_V7M_CORE - * @{ - */ - -#ifndef _CHCORE_V7M_H_ -#define _CHCORE_V7M_H_ - -/*===========================================================================*/ -/* Port constants. */ -/*===========================================================================*/ - -/** - * @brief Disabled value for BASEPRI register. - */ -#define CORTEX_BASEPRI_DISABLED 0 - -/*===========================================================================*/ -/* Port macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Port configurable parameters. */ -/*===========================================================================*/ - -/** - * @brief Stack size for the system idle thread. - * @details This size depends on the idle thread implementation, usually - * the idle thread should take no more space than those reserved - * by @p PORT_INT_REQUIRED_STACK. - * @note In this port it is set to 16 because the idle thread does have - * a stack frame when compiling without optimizations. You may - * reduce this value to zero when compiling with optimizations. - */ -#if !defined(PORT_IDLE_THREAD_STACK_SIZE) -#define PORT_IDLE_THREAD_STACK_SIZE 16 -#endif - -/** - * @brief Per-thread stack overhead for interrupts servicing. - * @details This constant is used in the calculation of the correct working - * area size. - * @note In this port this value is conservatively set to 64 because the - * function @p chSchDoReschedule() can have a stack frame, especially - * with compiler optimizations disabled. The value can be reduced - * when compiler optimizations are enabled. - */ -#if !defined(PORT_INT_REQUIRED_STACK) -#define PORT_INT_REQUIRED_STACK 64 -#endif - -/** - * @brief Enables the use of the WFI instruction in the idle thread loop. - */ -#if !defined(CORTEX_ENABLE_WFI_IDLE) -#define CORTEX_ENABLE_WFI_IDLE FALSE -#endif - -/** - * @brief SYSTICK handler priority. - * @note The default SYSTICK handler priority is calculated as the priority - * level in the middle of the numeric priorities range. - */ -#if !defined(CORTEX_PRIORITY_SYSTICK) -#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1) -#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK) -/* If it is externally redefined then better perform a validity check on it.*/ -#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK" -#endif - -/** - * @brief FPU support in context switch. - * @details Activating this option activates the FPU support in the kernel. - */ -#if !defined(CORTEX_USE_FPU) -#define CORTEX_USE_FPU CORTEX_HAS_FPU -#elif CORTEX_USE_FPU && !CORTEX_HAS_FPU -/* This setting requires an FPU presence check in case it is externally - redefined.*/ -#error "the selected core does not have an FPU" -#endif - -/** - * @brief Simplified priority handling flag. - * @details Activating this option makes the Kernel work in compact mode. - */ -#if !defined(CORTEX_SIMPLIFIED_PRIORITY) -#define CORTEX_SIMPLIFIED_PRIORITY FALSE -#endif - -/** - * @brief SVCALL handler priority. - * @note The default SVCALL handler priority is defaulted to - * @p CORTEX_MAXIMUM_PRIORITY+1, this reserves the - * @p CORTEX_MAXIMUM_PRIORITY priority level as fast interrupts - * priority level. - */ -#if !defined(CORTEX_PRIORITY_SVCALL) -#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1) -#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL) -/* If it is externally redefined then better perform a validity check on it.*/ -#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL" -#endif - -/** - * @brief NVIC VTOR initialization expression. - */ -#if !defined(CORTEX_VTOR_INIT) || defined(__DOXYGEN__) -#define CORTEX_VTOR_INIT 0x00000000 -#endif - -/** - * @brief NVIC PRIGROUP initialization expression. - * @details The default assigns all available priority bits as preemption - * priority with no sub-priority. - */ -#if !defined(CORTEX_PRIGROUP_INIT) || defined(__DOXYGEN__) -#define CORTEX_PRIGROUP_INIT (7 - CORTEX_PRIORITY_BITS) -#endif - -/*===========================================================================*/ -/* Port derived parameters. */ -/*===========================================================================*/ - -#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) -/** - * @brief Maximum usable priority for normal ISRs. - */ -#define CORTEX_MAX_KERNEL_PRIORITY (CORTEX_PRIORITY_SVCALL + 1) - -/** - * @brief BASEPRI level within kernel lock. - * @note In compact kernel mode this constant value is enforced to zero. - */ -#define CORTEX_BASEPRI_KERNEL \ - CORTEX_PRIORITY_MASK(CORTEX_MAX_KERNEL_PRIORITY) -#else - -#define CORTEX_MAX_KERNEL_PRIORITY 1 -#define CORTEX_BASEPRI_KERNEL 0 -#endif - -/** - * @brief PendSV priority level. - * @note This priority is enforced to be equal to - * @p CORTEX_MAX_KERNEL_PRIORITY, this handler always have the - * highest priority that cannot preempt the kernel. - */ -#define CORTEX_PRIORITY_PENDSV CORTEX_MAX_KERNEL_PRIORITY - -/*===========================================================================*/ -/* Port exported info. */ -/*===========================================================================*/ - -#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__) -/** - * @brief Macro defining the specific ARM architecture. - */ -#define CH_ARCHITECTURE_ARM_v7M - -/** - * @brief Name of the implemented architecture. - */ -#define CH_ARCHITECTURE_NAME "ARMv7-M" - -/** - * @brief Name of the architecture variant. - */ -#define CH_CORE_VARIANT_NAME "Cortex-M3" - -#elif (CORTEX_MODEL == CORTEX_M4) -#define CH_ARCHITECTURE_ARM_v7ME -#define CH_ARCHITECTURE_NAME "ARMv7-ME" -#if CORTEX_USE_FPU -#define CH_CORE_VARIANT_NAME "Cortex-M4F" -#else -#define CH_CORE_VARIANT_NAME "Cortex-M4" -#endif -#endif - -/** - * @brief Port-specific information string. - */ -#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) -#define CH_PORT_INFO "Advanced kernel mode" -#else -#define CH_PORT_INFO "Compact kernel mode" -#endif - -/*===========================================================================*/ -/* Port implementation part. */ -/*===========================================================================*/ - -#if !defined(_FROM_ASM_) - -/** - * @brief Generic ARM register. - */ -typedef void *regarm_t; - -/* The documentation of the following declarations is in chconf.h in order - to not have duplicated structure names into the documentation.*/ -#if !defined(__DOXYGEN__) - -typedef uint64_t stkalign_t __attribute__ ((aligned (8))); - -struct extctx { - regarm_t r0; - regarm_t r1; - regarm_t r2; - regarm_t r3; - regarm_t r12; - regarm_t lr_thd; - regarm_t pc; - regarm_t xpsr; -#if CORTEX_USE_FPU - regarm_t s0; - regarm_t s1; - regarm_t s2; - regarm_t s3; - regarm_t s4; - regarm_t s5; - regarm_t s6; - regarm_t s7; - regarm_t s8; - regarm_t s9; - regarm_t s10; - regarm_t s11; - regarm_t s12; - regarm_t s13; - regarm_t s14; - regarm_t s15; - regarm_t fpscr; - regarm_t reserved; -#endif /* CORTEX_USE_FPU */ -}; - -struct intctx { -#if CORTEX_USE_FPU - regarm_t s16; - regarm_t s17; - regarm_t s18; - regarm_t s19; - regarm_t s20; - regarm_t s21; - regarm_t s22; - regarm_t s23; - regarm_t s24; - regarm_t s25; - regarm_t s26; - regarm_t s27; - regarm_t s28; - regarm_t s29; - regarm_t s30; - regarm_t s31; -#endif /* CORTEX_USE_FPU */ - regarm_t r4; - regarm_t r5; - regarm_t r6; - regarm_t r7; - regarm_t r8; - regarm_t r9; - regarm_t r10; - regarm_t r11; - regarm_t lr; -}; - -#endif /* !defined(__DOXYGEN__) */ - -/** - * @brief Platform dependent part of the @p Thread structure. - * @details In this port the structure just holds a pointer to the @p intctx - * structure representing the stack pointer at context switch time. - */ -struct context { - struct intctx *r13; -}; - -/** - * @brief Platform dependent part of the @p chThdCreateI() API. - * @details This code usually setup the context switching frame represented - * by an @p intctx structure. - */ -#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ - tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \ - wsize - \ - sizeof(struct intctx)); \ - tp->p_ctx.r13->r4 = (void *)(pf); \ - tp->p_ctx.r13->r5 = (void *)(arg); \ - tp->p_ctx.r13->lr = (void *)(_port_thread_start); \ -} - -/** - * @brief Enforces a correct alignment for a stack area size value. - */ -#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) - -/** - * @brief Computes the thread working area global size. - */ -#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ - sizeof(struct intctx) + \ - sizeof(struct extctx) + \ - (n) + (PORT_INT_REQUIRED_STACK)) - -/** - * @brief Static working area allocation. - * @details This macro is used to allocate a static thread working area - * aligned as both position and size. - */ -#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] - -/** - * @brief IRQ prologue code. - * @details This macro must be inserted at the start of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_PROLOGUE() - -/** - * @brief IRQ epilogue code. - * @details This macro must be inserted at the end of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_EPILOGUE() _port_irq_epilogue() - -/** - * @brief IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_IRQ_HANDLER(id) void id(void) - -/** - * @brief Fast IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_FAST_IRQ_HANDLER(id) void id(void) - -/** - * @brief Port-related initialization code. - */ -#define port_init() _port_init() - -/** - * @brief Kernel-lock action. - * @details Usually this function just disables interrupts but may perform - * more actions. - * @note In this port this it raises the base priority to kernel level. - */ -#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) -#if CH_OPTIMIZE_SPEED || defined(__DOXYGEN__) -#define port_lock() { \ - register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; \ - asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory"); \ -} -#else /* !CH_OPTIMIZE_SPEED */ -#define port_lock() { \ - asm volatile ("bl _port_lock" : : : "r3", "lr", "memory"); \ -} -#endif /* !CH_OPTIMIZE_SPEED */ -#else /* CORTEX_SIMPLIFIED_PRIORITY */ -#define port_lock() asm volatile ("cpsid i" : : : "memory") -#endif /* CORTEX_SIMPLIFIED_PRIORITY */ - -/** - * @brief Kernel-unlock action. - * @details Usually this function just enables interrupts but may perform - * more actions. - * @note In this port this it lowers the base priority to user level. - */ -#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) -#if CH_OPTIMIZE_SPEED || defined(__DOXYGEN__) -#define port_unlock() { \ - register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED; \ - asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory"); \ -} -#else /* !CH_OPTIMIZE_SPEED */ -#define port_unlock() { \ - asm volatile ("bl _port_unlock" : : : "r3", "lr", "memory"); \ -} -#endif /* !CH_OPTIMIZE_SPEED */ -#else /* CORTEX_SIMPLIFIED_PRIORITY */ -#define port_unlock() asm volatile ("cpsie i" : : : "memory") -#endif /* CORTEX_SIMPLIFIED_PRIORITY */ - -/** - * @brief Kernel-lock action from an interrupt handler. - * @details This function is invoked before invoking I-class APIs from - * interrupt handlers. The implementation is architecture dependent, - * in its simplest form it is void. - * @note Same as @p port_lock() in this port. - */ -#define port_lock_from_isr() port_lock() - -/** - * @brief Kernel-unlock action from an interrupt handler. - * @details This function is invoked after invoking I-class APIs from interrupt - * handlers. The implementation is architecture dependent, in its - * simplest form it is void. - * @note Same as @p port_unlock() in this port. - */ -#define port_unlock_from_isr() port_unlock() - -/** - * @brief Disables all the interrupt sources. - * @note Of course non-maskable interrupt sources are not included. - * @note In this port it disables all the interrupt sources by raising - * the priority mask to level 0. - */ -#define port_disable() asm volatile ("cpsid i" : : : "memory") - -/** - * @brief Disables the interrupt sources below kernel-level priority. - * @note Interrupt sources above kernel level remains enabled. - * @note In this port it raises/lowers the base priority to kernel level. - */ -#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) -#define port_suspend() { \ - register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; \ - asm volatile ("msr BASEPRI, %0 \n\t" \ - "cpsie i" : : "r" (tmp) : "memory"); \ -} -#else /* CORTEX_SIMPLIFIED_PRIORITY */ -#define port_suspend() asm volatile ("cpsid i" : : : "memory") -#endif /* CORTEX_SIMPLIFIED_PRIORITY */ - -/** - * @brief Enables all the interrupt sources. - * @note In this port it lowers the base priority to user level. - */ -#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) -#define port_enable() { \ - register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED; \ - asm volatile ("msr BASEPRI, %0 \n\t" \ - "cpsie i" : : "r" (tmp) : "memory"); \ -} -#else /* CORTEX_SIMPLIFIED_PRIORITY */ -#define port_enable() asm volatile ("cpsie i" : : : "memory") -#endif /* CORTEX_SIMPLIFIED_PRIORITY */ - -/** - * @brief Enters an architecture-dependent IRQ-waiting mode. - * @details The function is meant to return when an interrupt becomes pending. - * The simplest implementation is an empty function or macro but this - * would not take advantage of architecture-specific power saving - * modes. - * @note Implemented as an inlined @p WFI instruction. - */ -#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__) -#define port_wait_for_interrupt() { \ - asm volatile ("wfi" : : : "memory"); \ -} -#else -#define port_wait_for_interrupt() -#endif - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -void chDbgStackOverflowPanic(Thread *otp); -int getRemainingStack(Thread *otp); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -/** - * @brief Performs a context switch between two threads. - * @details This is the most critical code in any port, this function - * is responsible for the context switch between 2 threads. - * @note The implementation of this code affects directly the context - * switch performance so optimize here as much as you can. - * - * @param[in] ntp the thread to be switched in - * @param[in] otp the thread to be switched out - */ -#if !CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__) -#define port_switch(ntp, otp) _port_switch(ntp, otp) -#else -#define port_switch(ntp, otp) { \ - if (getRemainingStack(otp) < 0) \ - chDbgStackOverflowPanic(otp); \ - _port_switch(ntp, otp); \ -} -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void port_halt(void); - void _port_init(void); - void _port_irq_epilogue(void); - void _port_switch_from_isr(void); - void _port_exit_from_isr(void); - void _port_switch(Thread *ntp, Thread *otp); - void _port_thread_start(void); -#if !CH_OPTIMIZE_SPEED - void _port_lock(void); - void _port_unlock(void); -#endif -#ifdef __cplusplus -} -#endif - -#endif /* _FROM_ASM_ */ - -#endif /* _CHCORE_V7M_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/ports/GCC/ARMCMx/chtypes.h b/firmware/chibios/os/ports/GCC/ARMCMx/chtypes.h deleted file mode 100644 index 4024cbd75b..0000000000 --- a/firmware/chibios/os/ports/GCC/ARMCMx/chtypes.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file GCC/ARMCMx/chtypes.h - * @brief ARM Cortex-Mx port system types. - * - * @addtogroup ARMCMx_CORE - * @{ - */ - -#ifndef _CHTYPES_H_ -#define _CHTYPES_H_ - -#include -#include -#include - -typedef bool bool_t; /**< Fast boolean type. */ -typedef uint8_t tmode_t; /**< Thread flags. */ -typedef uint8_t tstate_t; /**< Thread state. */ -typedef uint8_t trefs_t; /**< Thread references counter. */ -typedef uint8_t tslices_t; /**< Thread time slices counter. */ -typedef uint32_t tprio_t; /**< Thread priority. */ -typedef int32_t msg_t; /**< Inter-thread message. */ -typedef int32_t eventid_t; /**< Event Id. */ -typedef uint32_t eventmask_t; /**< Event mask. */ -typedef uint32_t flagsmask_t; /**< Event flags. */ -typedef uint32_t systime_t; /**< System time. */ -typedef int32_t cnt_t; /**< Resources counter. */ - -/** - * @brief Inline function modifier. - */ -#define INLINE inline - -/** - * @brief ROM constant modifier. - * @note It is set to use the "const" keyword in this port. - */ -#define ROMCONST const - -/** - * @brief Packed structure modifier (within). - * @note It uses the "packed" GCC attribute. - */ -#define PACK_STRUCT_STRUCT __attribute__((packed)) - -/** - * @brief Packed structure modifier (before). - * @note Empty in this port. - */ -#define PACK_STRUCT_BEGIN - -/** - * @brief Packed structure modifier (after). - * @note Empty in this port. - */ -#define PACK_STRUCT_END - -/** - * @brief Packed variable specifier. - */ -#define PACKED_VAR __attribute__((packed)) - -#endif /* _CHTYPES_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/ports/GCC/ARMCMx/crt0.c b/firmware/chibios/os/ports/GCC/ARMCMx/crt0.c deleted file mode 100644 index 48a167a950..0000000000 --- a/firmware/chibios/os/ports/GCC/ARMCMx/crt0.c +++ /dev/null @@ -1,361 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file ARMCMx/crt0.c - * @brief Generic ARMvx-M (Cortex-M0/M1/M3/M4) startup file for ChibiOS/RT. - * - * @addtogroup ARMCMx_STARTUP - * @{ - */ - -#include - -#if !defined(FALSE) -#define FALSE 0 -#endif - -#if !defined(TRUE) -#define TRUE (!FALSE) -#endif - -#define SCB_CPACR *((uint32_t *)0xE000ED88U) -#define SCB_FPCCR *((uint32_t *)0xE000EF34U) -#define SCB_FPDSCR *((uint32_t *)0xE000EF3CU) -#define FPCCR_ASPEN (0x1U << 31) -#define FPCCR_LSPEN (0x1U << 30) - -typedef void (*funcp_t)(void); -typedef funcp_t * funcpp_t; - -#define SYMVAL(sym) (uint32_t)(((uint8_t *)&(sym)) - ((uint8_t *)0)) - -/* - * Area fill code, it is a macro because here functions cannot be called - * until stacks are initialized. - */ -#define fill32(start, end, filler) { \ - uint32_t *p1 = start; \ - uint32_t *p2 = end; \ - while (p1 < p2) \ - *p1++ = filler; \ -} - -/*===========================================================================*/ -/** - * @name Startup settings - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Control special register initialization value. - * @details The system is setup to run in privileged mode using the PSP - * stack (dual stack mode). - */ -#if !defined(CRT0_CONTROL_INIT) || defined(__DOXYGEN__) -#define CRT0_CONTROL_INIT 0x00000002 -#endif - -/** - * @brief Stack segments initialization switch. - */ -#if !defined(CRT0_STACKS_FILL_PATTERN) || defined(__DOXYGEN__) -#define CRT0_STACKS_FILL_PATTERN 0x55555555 -#endif - -/** - * @brief Stack segments initialization switch. - */ -#if !defined(CRT0_INIT_STACKS) || defined(__DOXYGEN__) -#define CRT0_INIT_STACKS TRUE -#endif - -/** - * @brief DATA segment initialization switch. - */ -#if !defined(CRT0_INIT_DATA) || defined(__DOXYGEN__) -#define CRT0_INIT_DATA TRUE -#endif - -/** - * @brief BSS segment initialization switch. - */ -#if !defined(CRT0_INIT_BSS) || defined(__DOXYGEN__) -#define CRT0_INIT_BSS TRUE -#endif - -/** - * @brief Constructors invocation switch. - */ -#if !defined(CRT0_CALL_CONSTRUCTORS) || defined(__DOXYGEN__) -#define CRT0_CALL_CONSTRUCTORS TRUE -#endif - -/** - * @brief Destructors invocation switch. - */ -#if !defined(CRT0_CALL_DESTRUCTORS) || defined(__DOXYGEN__) -#define CRT0_CALL_DESTRUCTORS TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Symbols from the scatter file - */ -/*===========================================================================*/ - -/** - * @brief Main stack lower boundary. - * @details This symbol must be exported by the linker script and represents - * the main stack lower boundary. - */ -extern uint32_t __main_stack_base__; - -/** - * - * @brief Main stack initial position. - * @details This symbol must be exported by the linker script and represents - * the main stack initial position. - */ -extern uint32_t __main_stack_end__; - -/** - * @brief Process stack lower boundary. - * @details This symbol must be exported by the linker script and represents - * the process stack lower boundary. - */ -extern uint32_t __process_stack_base__; - -/** - * @brief Process stack initial position. - * @details This symbol must be exported by the linker script and represents - * the process stack initial position. - */ -extern uint32_t __process_stack_end__; - -/** - * @brief ROM image of the data segment start. - * @pre The symbol must be aligned to a 32 bits boundary. - */ -extern uint32_t _textdata; - -/** - * @brief Data segment start. - * @pre The symbol must be aligned to a 32 bits boundary. - */ -extern uint32_t _data; - -/** - * @brief Data segment end. - * @pre The symbol must be aligned to a 32 bits boundary. - */ -extern uint32_t _edata; - -/** - * @brief BSS segment start. - * @pre The symbol must be aligned to a 32 bits boundary. - */ -extern uint32_t _bss_start; - -/** - * @brief BSS segment end. - * @pre The symbol must be aligned to a 32 bits boundary. - */ -extern uint32_t _bss_end; - -/** - * @brief Constructors table start. - * @pre The symbol must be aligned to a 32 bits boundary. - */ -extern funcp_t __init_array_start; - -/** - * @brief Constructors table end. - * @pre The symbol must be aligned to a 32 bits boundary. - */ -extern funcp_t __init_array_end; - -/** - * @brief Destructors table start. - * @pre The symbol must be aligned to a 32 bits boundary. - */ -extern funcp_t __fini_array_start; - -/** - * @brief Destructors table end. - * @pre The symbol must be aligned to a 32 bits boundary. - */ -extern funcp_t __fini_array_end; - -/** @} */ - -/** - * @brief Application @p main() function. - */ -extern void main(void); - -/** - * @brief Early initialization. - * @details This hook is invoked immediately after the stack initialization - * and before the DATA and BSS segments initialization. The - * default behavior is to do nothing. - * @note This function is a weak symbol. - */ -#if !defined(__DOXYGEN__) -__attribute__((weak)) -#endif -void __early_init(void) {} - -/** - * @brief Late initialization. - * @details This hook is invoked after the DATA and BSS segments - * initialization and before any static constructor. The - * default behavior is to do nothing. - * @note This function is a weak symbol. - */ -#if !defined(__DOXYGEN__) -__attribute__((weak)) -#endif -void __late_init(void) {} - -/** - * @brief Default @p main() function exit handler. - * @details This handler is invoked or the @p main() function exit. The - * default behavior is to enter an infinite loop. - * @note This function is a weak symbol. - */ -#if !defined(__DOXYGEN__) -__attribute__((weak, naked)) -#endif -void _default_exit(void) { - while (1) - ; -} - -/** - * @brief Reset vector. - */ -#if !defined(__DOXYGEN__) -__attribute__((naked)) -#endif -void ResetHandler(void) { - uint32_t psp, reg; - - /* Process Stack initialization, it is allocated starting from the - symbol __process_stack_end__ and its lower limit is the symbol - __process_stack_base__.*/ - asm volatile ("cpsid i"); - psp = SYMVAL(__process_stack_end__); - asm volatile ("msr PSP, %0" : : "r" (psp)); - -#if CORTEX_USE_FPU - /* Initializing the FPU context save in lazy mode.*/ - SCB_FPCCR = FPCCR_ASPEN | FPCCR_LSPEN; - - /* CP10 and CP11 set to full access.*/ - SCB_CPACR |= 0x00F00000; - - /* FPSCR and FPDSCR initially zero.*/ - reg = 0; - asm volatile ("vmsr FPSCR, %0" : : "r" (reg) : "memory"); - SCB_FPDSCR = reg; - - /* CPU mode initialization, enforced FPCA bit.*/ - reg = CRT0_CONTROL_INIT | 4; -#else - /* CPU mode initialization.*/ - reg = CRT0_CONTROL_INIT; -#endif - asm volatile ("msr CONTROL, %0" : : "r" (reg)); - asm volatile ("isb"); - -#if CRT0_INIT_STACKS - /* Main and Process stacks initialization.*/ - fill32(&__main_stack_base__, - &__main_stack_end__, - CRT0_STACKS_FILL_PATTERN); - fill32(&__process_stack_base__, - &__process_stack_end__, - CRT0_STACKS_FILL_PATTERN); -#endif - - /* Early initialization hook invocation.*/ - __early_init(); - -#if CRT0_INIT_DATA - /* DATA segment initialization.*/ - { - uint32_t *tp, *dp; - - tp = &_textdata; - dp = &_data; - while (dp < &_edata) - *dp++ = *tp++; - } -#endif - -#if CRT0_INIT_BSS - /* BSS segment initialization.*/ - fill32(&_bss_start, &_bss_end, 0); -#endif - - /* Late initialization hook invocation.*/ - __late_init(); - -#if CRT0_CALL_CONSTRUCTORS - /* Constructors invocation.*/ - { - funcpp_t fpp = &__init_array_start; - while (fpp < &__init_array_end) { - (*fpp)(); - fpp++; - } - } -#endif - - /* Invoking application main() function.*/ - main(); - -#if CRT0_CALL_DESTRUCTORS - /* Destructors invocation.*/ - { - funcpp_t fpp = &__fini_array_start; - while (fpp < &__fini_array_end) { - (*fpp)(); - fpp++; - } - } -#endif - - /* Invoking the exit handler.*/ - _default_exit(); -} - -/** @} */ diff --git a/firmware/chibios/os/ports/GCC/ARMCMx/rules.mk b/firmware/chibios/os/ports/GCC/ARMCMx/rules.mk deleted file mode 100644 index 438130af76..0000000000 --- a/firmware/chibios/os/ports/GCC/ARMCMx/rules.mk +++ /dev/null @@ -1,253 +0,0 @@ -# ARM Cortex-Mx common makefile scripts and rules. - -############################################################################## -# Processing options coming from the upper Makefile. -# - -# Compiler options -OPT = $(USE_OPT) -COPT = $(USE_COPT) -CPPOPT = $(USE_CPPOPT) - -# Garbage collection -ifeq ($(USE_LINK_GC),yes) - OPT += -ffunction-sections -fdata-sections -fno-common - LDOPT := ,--gc-sections -else - LDOPT := -endif - -# Linker extra options -ifneq ($(USE_LDOPT),) - LDOPT := $(LDOPT),$(USE_LDOPT) -endif - -# Link time optimizations -ifeq ($(USE_LTO),yes) - OPT += -flto -endif - -# FPU-related options -ifeq ($(USE_FPU),) - USE_FPU = no -endif -ifneq ($(USE_FPU),no) - OPT += -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 -fsingle-precision-constant - DDEFS += -DCORTEX_USE_FPU=TRUE - DADEFS += -DCORTEX_USE_FPU=TRUE -else - DDEFS += -DCORTEX_USE_FPU=FALSE - DADEFS += -DCORTEX_USE_FPU=FALSE -endif - -# Output directory and files -ifeq ($(BUILDDIR),) - BUILDDIR = build -endif -ifeq ($(BUILDDIR),.) - BUILDDIR = build -endif -OUTFILES = $(BUILDDIR)/$(PROJECT).elf $(BUILDDIR)/$(PROJECT).hex \ - $(BUILDDIR)/$(PROJECT).bin $(BUILDDIR)/$(PROJECT).dmp - -# Source files groups and paths -ifeq ($(USE_THUMB),yes) - TCSRC += $(CSRC) - TCPPSRC += $(CPPSRC) -else - ACSRC += $(CSRC) - ACPPSRC += $(CPPSRC) -endif -ASRC = $(ACSRC)$(ACPPSRC) -TSRC = $(TCSRC)$(TCPPSRC) -SRCPATHS = $(sort $(dir $(ASMXSRC)) $(dir $(ASMSRC)) $(dir $(ASRC)) $(dir $(TSRC))) - -# Various directories -OBJDIR = $(BUILDDIR)/obj -LSTDIR = $(BUILDDIR)/lst - -# Object files groups -ACOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ACSRC:.c=.o))) -ACPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ACPPSRC:.cpp=.o))) -TCOBJS = $(addprefix $(OBJDIR)/, $(notdir $(TCSRC:.c=.o))) -TCPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(TCPPSRC:.cpp=.o))) -ASMOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMSRC:.s=.o))) -ASMXOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMXSRC:.S=.o))) -OBJS = $(ASMXOBJS) $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS) - -# Paths -IINCDIR = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR)) -LLIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) - -# Macros -DEFS = $(DDEFS) $(UDEFS) -ADEFS = $(DADEFS) $(UADEFS) - -# Libs -LIBS = $(DLIBS) $(ULIBS) - -# Various settings -MCFLAGS = -mcpu=$(MCU) -ODFLAGS = -x --syms -ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS) -ASXFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS) -CFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS) -CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS) -LDFLAGS = $(MCFLAGS) $(OPT) -nostartfiles $(LLIBDIR) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--library-path=$(RULESPATH),--script=$(LDSCRIPT)$(LDOPT) - -# Thumb interwork enabled only if needed because it kills performance. -ifneq ($(TSRC),) - CFLAGS += -DTHUMB_PRESENT - CPPFLAGS += -DTHUMB_PRESENT - ASFLAGS += -DTHUMB_PRESENT - ifneq ($(ASRC),) - # Mixed ARM and THUMB mode. - CFLAGS += -mthumb-interwork - CPPFLAGS += -mthumb-interwork - ASFLAGS += -mthumb-interwork - LDFLAGS += -mthumb-interwork - else - # Pure THUMB mode, THUMB C code cannot be called by ARM asm code directly. - CFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING - CPPFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING - ASFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -mthumb - LDFLAGS += -mno-thumb-interwork -mthumb - endif -else - # Pure ARM mode - CFLAGS += -mno-thumb-interwork - CPPFLAGS += -mno-thumb-interwork - ASFLAGS += -mno-thumb-interwork - LDFLAGS += -mno-thumb-interwork -endif - -# Generate dependency information -ASFLAGS += -MD -MP -MF .dep/$(@F).d -CFLAGS += -MD -MP -MF .dep/$(@F).d -CPPFLAGS += -MD -MP -MF .dep/$(@F).d - -# Paths where to search for sources -VPATH = $(SRCPATHS) - -# -# Makefile rules -# - -all: $(OBJS) $(OUTFILES) MAKE_ALL_RULE_HOOK - -MAKE_ALL_RULE_HOOK: - -$(OBJS): | $(BUILDDIR) - -$(BUILDDIR) $(OBJDIR) $(LSTDIR): -ifneq ($(USE_VERBOSE_COMPILE),yes) - @echo Compiler Options - @echo $(CC) -c $(CFLAGS) -I. $(IINCDIR) main.c -o main.o - @echo -endif - mkdir -p $(OBJDIR) - mkdir -p $(LSTDIR) - -$(ACPPOBJS) : $(OBJDIR)/%.o : %.cpp Makefile -ifeq ($(USE_VERBOSE_COMPILE),yes) - @echo - $(CPPC) -c $(CPPFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@ -else - @echo Compiling $( $@ -else - @echo Creating $@ - @$(OD) $(ODFLAGS) $< > $@ - @echo - @$(SZ) $< - @echo - @echo Done -endif - -clean: - @echo Cleaning - -rm -fR .dep $(BUILDDIR) - @echo - @echo Done - -# -# Include the dependency files, should be the last of the makefile -# --include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) - -# *** EOF *** diff --git a/firmware/chibios/os/ports/GCC/SIMIA32/chcore.c b/firmware/chibios/os/ports/GCC/SIMIA32/chcore.c deleted file mode 100644 index 10b3bb3479..0000000000 --- a/firmware/chibios/os/ports/GCC/SIMIA32/chcore.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @addtogroup SIMIA32_CORE - * @{ - */ - -#include - -#include "ch.h" -#include "hal.h" - -/** - * Performs a context switch between two threads. - * @param otp the thread to be switched out - * @param ntp the thread to be switched in - */ -__attribute__((used)) -static void __dummy(Thread *ntp, Thread *otp) { - (void)ntp; (void)otp; - - asm volatile ( -#if defined(WIN32) - ".globl @port_switch@8 \n\t" - "@port_switch@8:" -#elif defined(__APPLE__) - ".globl _port_switch \n\t" - "_port_switch:" -#else - ".globl port_switch \n\t" - "port_switch:" -#endif - "push %ebp \n\t" - "push %esi \n\t" - "push %edi \n\t" - "push %ebx \n\t" - "movl %esp, 12(%edx) \n\t" - "movl 12(%ecx), %esp \n\t" - "pop %ebx \n\t" - "pop %edi \n\t" - "pop %esi \n\t" - "pop %ebp \n\t" - "ret"); -} - -/** - * Halts the system. In this implementation it just exits the simulation. - */ -__attribute__((fastcall)) -void port_halt(void) { - - exit(2); -} - -/** - * @brief Start a thread by invoking its work function. - * @details If the work function returns @p chThdExit() is automatically - * invoked. - */ -__attribute__((cdecl, noreturn)) -void _port_thread_start(msg_t (*pf)(void *), void *p) { - - chSysUnlock(); - chThdExit(pf(p)); - while(1); -} - -/** @} */ diff --git a/firmware/chibios/os/ports/GCC/SIMIA32/chcore.h b/firmware/chibios/os/ports/GCC/SIMIA32/chcore.h deleted file mode 100644 index a497e34774..0000000000 --- a/firmware/chibios/os/ports/GCC/SIMIA32/chcore.h +++ /dev/null @@ -1,250 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @addtogroup SIMIA32_CORE - * @{ - */ - -#ifndef _CHCORE_H_ -#define _CHCORE_H_ - -#if CH_DBG_ENABLE_STACK_CHECK -#error "option CH_DBG_ENABLE_STACK_CHECK not supported by this port" -#endif - -/** - * Macro defining the a simulated architecture into x86. - */ -#define CH_ARCHITECTURE_SIMIA32 - -/** - * Name of the implemented architecture. - */ -#define CH_ARCHITECTURE_NAME "Simulator" - -/** - * @brief Name of the architecture variant (optional). - */ -#define CH_CORE_VARIANT_NAME "x86 (integer only)" - -/** - * @brief Name of the compiler supported by this port. - */ -#define CH_COMPILER_NAME "GCC " __VERSION__ - -/** - * @brief Port-specific information string. - */ -#define CH_PORT_INFO "No preemption" - -/** - * 16 bytes stack alignment. - */ -typedef struct { - uint8_t a[16]; -} stkalign_t __attribute__((aligned(16))); - -/** - * Generic x86 register. - */ -typedef void *regx86; - -/** - * Interrupt saved context. - * This structure represents the stack frame saved during a preemption-capable - * interrupt handler. - */ -struct extctx { -}; - -/** - * System saved context. - * @note In this demo the floating point registers are not saved. - */ -struct intctx { - regx86 ebx; - regx86 edi; - regx86 esi; - regx86 ebp; - regx86 eip; -}; - -/** - * Platform dependent part of the @p Thread structure. - * This structure usually contains just the saved stack pointer defined as a - * pointer to a @p intctx structure. - */ -struct context { - struct intctx volatile *esp; -}; - -#define APUSH(p, a) (p) -= sizeof(void *), *(void **)(p) = (void*)(a) - -/* Darwin requires the stack to be aligned to a 16-byte boundary at - * the time of a call instruction (in case the called function needs - * to save MMX registers). This aligns to 'mod' module 16, so that we'll end - * up with the right alignment after pushing the args. */ -#define AALIGN(p, mask, mod) p = (void *)((((uintptr_t)(p) - mod) & ~mask) + mod) - -/** - * Platform dependent part of the @p chThdCreateI() API. - * This code usually setup the context switching frame represented by a - * @p intctx structure. - */ -#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ - uint8_t *esp = (uint8_t *)workspace + wsize; \ - APUSH(esp, 0); \ - uint8_t *savebp = esp; \ - AALIGN(esp, 15, 8); \ - APUSH(esp, arg); \ - APUSH(esp, pf); \ - APUSH(esp, 0); \ - esp -= sizeof(struct intctx); \ - ((struct intctx *)esp)->eip = _port_thread_start; \ - ((struct intctx *)esp)->ebx = 0; \ - ((struct intctx *)esp)->edi = 0; \ - ((struct intctx *)esp)->esi = 0; \ - ((struct intctx *)esp)->ebp = savebp; \ - tp->p_ctx.esp = (struct intctx *)esp; \ -} - -/** - * Stack size for the system idle thread. - */ -#ifndef PORT_IDLE_THREAD_STACK_SIZE -#define PORT_IDLE_THREAD_STACK_SIZE 256 -#endif - -/** - * Per-thread stack overhead for interrupts servicing, it is used in the - * calculation of the correct working area size. - * It requires stack space because the simulated "interrupt handlers" can - * invoke host library functions inside so it better have a lot of space. - */ -#ifndef PORT_INT_REQUIRED_STACK -#define PORT_INT_REQUIRED_STACK 16384 -#endif - -/** - * Enforces a correct alignment for a stack area size value. - */ -#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) - - /** - * Computes the thread working area global size. - */ -#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ - sizeof(void *) * 4 + \ - sizeof(struct intctx) + \ - sizeof(struct extctx) + \ - (n) + (PORT_INT_REQUIRED_STACK)) - -/** - * Macro used to allocate a thread working area aligned as both position and - * size. - */ -#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] - -/** - * IRQ prologue code, inserted at the start of all IRQ handlers enabled to - * invoke system APIs. - */ -#define PORT_IRQ_PROLOGUE() - -/** - * IRQ epilogue code, inserted at the end of all IRQ handlers enabled to - * invoke system APIs. - */ -#define PORT_IRQ_EPILOGUE() - -/** - * IRQ handler function declaration. - */ -#define PORT_IRQ_HANDLER(id) void id(void) - -/** - * Simulator initialization. - */ -#define port_init() - -/** - * Does nothing in this simulator. - */ -#define port_lock() asm volatile("nop") - -/** - * Does nothing in this simulator. - */ -#define port_unlock() asm volatile("nop") - -/** - * Does nothing in this simulator. - */ -#define port_lock_from_isr() - -/** - * Does nothing in this simulator. - */ -#define port_unlock_from_isr() - -/** - * Does nothing in this simulator. - */ -#define port_disable() - -/** - * Does nothing in this simulator. - */ -#define port_suspend() - -/** - * Does nothing in this simulator. - */ -#define port_enable() - -/** - * In the simulator this does a polling pass on the simulated interrupt - * sources. - */ -#define port_wait_for_interrupt() ChkIntSources() - -#ifdef __cplusplus -extern "C" { -#endif - __attribute__((fastcall)) void port_switch(Thread *ntp, Thread *otp); - __attribute__((fastcall)) void port_halt(void); - __attribute__((cdecl, noreturn)) void _port_thread_start(msg_t (*pf)(void *), - void *p); - void ChkIntSources(void); -#ifdef __cplusplus -} -#endif - -#endif /* _CHCORE_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/ports/GCC/SIMIA32/chtypes.h b/firmware/chibios/os/ports/GCC/SIMIA32/chtypes.h deleted file mode 100644 index 0a956e0140..0000000000 --- a/firmware/chibios/os/ports/GCC/SIMIA32/chtypes.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#ifndef _CHTYPES_H_ -#define _CHTYPES_H_ - -#include -#include -#include - -typedef bool bool_t; /**< Fast boolean type. */ -typedef uint8_t tmode_t; /**< Thread flags. */ -typedef uint8_t tstate_t; /**< Thread state. */ -typedef uint8_t trefs_t; /**< Thread references counter. */ -typedef uint8_t tslices_t; /**< Thread time slices counter. */ -typedef uint32_t tprio_t; /**< Thread priority. */ -typedef int32_t msg_t; /**< Inter-thread message. */ -typedef int32_t eventid_t; /**< Event Id. */ -typedef uint32_t eventmask_t; /**< Event mask. */ -typedef uint32_t flagsmask_t; /**< Event flags. */ -typedef uint32_t systime_t; /**< System time. */ -typedef int32_t cnt_t; /**< Resources counter. */ - -/** - * @brief Inline function modifier. - */ -#define INLINE inline - -/** - * @brief ROM constant modifier. - * @note It is set to use the "const" keyword in this port. - */ -#define ROMCONST const - -/** - * @brief Packed structure modifier (within). - * @note It uses the "packed" GCC attribute. - */ -#define PACK_STRUCT_STRUCT __attribute__((packed)) - -/** - * @brief Packed structure modifier (before). - * @note Empty in this port. - */ -#define PACK_STRUCT_BEGIN - -/** - * @brief Packed structure modifier (after). - * @note Empty in this port. - */ -#define PACK_STRUCT_END - -#endif /* _CHTYPES_H_ */ diff --git a/firmware/chibios/os/ports/GCC/SIMIA32/port.mk b/firmware/chibios/os/ports/GCC/SIMIA32/port.mk deleted file mode 100644 index 04b9953418..0000000000 --- a/firmware/chibios/os/ports/GCC/SIMIA32/port.mk +++ /dev/null @@ -1,6 +0,0 @@ -# List of the ChibiOS/RT SIMIA32 port files. -PORTSRC = ${CHIBIOS}/os/ports/GCC/SIMIA32/chcore.c - -PORTASM = - -PORTINC = ${CHIBIOS}/os/ports/GCC/SIMIA32 diff --git a/firmware/chibios/os/ports/IAR/ARMCMx/STM32F0xx/cmparams.h b/firmware/chibios/os/ports/IAR/ARMCMx/STM32F0xx/cmparams.h deleted file mode 100644 index a4df125018..0000000000 --- a/firmware/chibios/os/ports/IAR/ARMCMx/STM32F0xx/cmparams.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file IAR/ARMCMx/STM32F1xx/cmparams.h - * @brief ARM Cortex-M3 parameters for the STM32F1xx. - * - * @defgroup IAR_ARMCMx_STM32F1xx STM32F1xx Specific Parameters - * @ingroup IAR_ARMCMx_SPECIFIC - * @details This file contains the Cortex-M3 specific parameters for the - * STM32F1xx platform. - * @{ - */ - -#ifndef _CMPARAMS_H_ -#define _CMPARAMS_H_ - -/** - * @brief Cortex core model. - */ -#define CORTEX_MODEL CORTEX_M3 - -/** - * @brief Systick unit presence. - */ -#define CORTEX_HAS_ST TRUE - -/** - * @brief Memory Protection unit presence. - */ -#define CORTEX_HAS_MPU FALSE - -/** - * @brief Floating Point unit presence. - */ -#define CORTEX_HAS_FPU FALSE - -/** - * @brief Number of bits in priority masks. - */ -#define CORTEX_PRIORITY_BITS 4 - -#endif /* _CMPARAMS_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/ports/IAR/ARMCMx/STM32F0xx/vectors.s b/firmware/chibios/os/ports/IAR/ARMCMx/STM32F0xx/vectors.s deleted file mode 100644 index 6f765b2cb9..0000000000 --- a/firmware/chibios/os/ports/IAR/ARMCMx/STM32F0xx/vectors.s +++ /dev/null @@ -1,317 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#if !defined(STM32F10X_LD) && !defined(STM32F10X_LD_VL) && \ - !defined(STM32F10X_MD) && !defined(STM32F10X_MD_VL) && \ - !defined(STM32F10X_HD) && !defined(STM32F10X_XL) && \ - !defined(STM32F10X_CL) -#define _FROM_ASM_ -#include "board.h" -#endif - - MODULE ?vectors - - AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE - PRESERVE8 - - SECTION IRQSTACK:DATA:NOROOT(3) - SECTION .intvec:CODE:NOROOT(3) - - EXTERN __iar_program_start - PUBLIC __vector_table - - DATA - -__vector_table: - DCD SFE(IRQSTACK) - DCD __iar_program_start - DCD NMIVector - DCD HardFaultVector - DCD MemManageVector - DCD BusFaultVector - DCD UsageFaultVector - DCD Vector1C - DCD Vector20 - DCD Vector24 - DCD Vector28 - DCD SVCallVector - DCD DebugMonitorVector - DCD Vector34 - DCD PendSVVector - DCD SysTickVector - DCD Vector40 - DCD Vector44 - DCD Vector48 - DCD Vector4C - DCD Vector50 - DCD Vector54 - DCD Vector58 - DCD Vector5C - DCD Vector60 - DCD Vector64 - DCD Vector68 - DCD Vector6C - DCD Vector70 - DCD Vector74 - DCD Vector78 - DCD Vector7C - DCD Vector80 - DCD Vector84 - DCD Vector88 - DCD Vector8C - DCD Vector90 - DCD Vector94 - DCD Vector98 - DCD Vector9C - DCD VectorA0 - DCD VectorA4 - DCD VectorA8 - DCD VectorAC - DCD VectorB0 - DCD VectorB4 - DCD VectorB8 - DCD VectorBC - DCD VectorC0 - DCD VectorC4 - DCD VectorC8 - DCD VectorCC - DCD VectorD0 - DCD VectorD4 - DCD VectorD8 - DCD VectorDC - DCD VectorE0 - DCD VectorE4 - DCD VectorE8 -#if defined(STM32F10X_MD_VL) || defined(STM32F10X_HD) || \ - defined(STM32F10X_XL) || defined(STM32F10X_CL) - DCD VectorEC - DCD VectorF0 - DCD VectorF4 -#endif -#if defined(STM32F10X_HD) || defined(STM32F10X_XL) || defined(STM32F10X_CL) - DCD VectorF8 - DCD VectorFC - DCD Vector100 - DCD Vector104 - DCD Vector108 - DCD Vector10C - DCD Vector110 - DCD Vector114 - DCD Vector118 - DCD Vector11C - DCD Vector120 - DCD Vector124 - DCD Vector128 - DCD Vector12C -#endif -#if defined(STM32F10X_CL) - DCD Vector130 - DCD Vector134 - DCD Vector138 - DCD Vector13C - DCD Vector140 - DCD Vector144 - DCD Vector148 - DCD Vector14C -#endif - -/* - * Default interrupt handlers. - */ - PUBWEAK NMIVector - PUBWEAK HardFaultVector - PUBWEAK MemManageVector - PUBWEAK BusFaultVector - PUBWEAK UsageFaultVector - PUBWEAK Vector1C - PUBWEAK Vector20 - PUBWEAK Vector24 - PUBWEAK Vector28 - PUBWEAK SVCallVector - PUBWEAK DebugMonitorVector - PUBWEAK Vector34 - PUBWEAK PendSVVector - PUBWEAK SysTickVector - PUBWEAK Vector40 - PUBWEAK Vector44 - PUBWEAK Vector48 - PUBWEAK Vector4C - PUBWEAK Vector50 - PUBWEAK Vector54 - PUBWEAK Vector58 - PUBWEAK Vector5C - PUBWEAK Vector60 - PUBWEAK Vector64 - PUBWEAK Vector68 - PUBWEAK Vector6C - PUBWEAK Vector70 - PUBWEAK Vector74 - PUBWEAK Vector78 - PUBWEAK Vector7C - PUBWEAK Vector80 - PUBWEAK Vector84 - PUBWEAK Vector88 - PUBWEAK Vector8C - PUBWEAK Vector90 - PUBWEAK Vector94 - PUBWEAK Vector98 - PUBWEAK Vector9C - PUBWEAK VectorA0 - PUBWEAK VectorA4 - PUBWEAK VectorA8 - PUBWEAK VectorAC - PUBWEAK VectorB0 - PUBWEAK VectorB4 - PUBWEAK VectorB8 - PUBWEAK VectorBC - PUBWEAK VectorC0 - PUBWEAK VectorC4 - PUBWEAK VectorC8 - PUBWEAK VectorCC - PUBWEAK VectorD0 - PUBWEAK VectorD4 - PUBWEAK VectorD8 - PUBWEAK VectorDC - PUBWEAK VectorE0 - PUBWEAK VectorE4 - PUBWEAK VectorE8 - PUBWEAK VectorEC - PUBWEAK VectorF0 - PUBWEAK VectorF4 - PUBWEAK VectorF8 - PUBWEAK VectorFC - PUBWEAK Vector100 - PUBWEAK Vector104 - PUBWEAK Vector108 - PUBWEAK Vector10C - PUBWEAK Vector110 - PUBWEAK Vector114 - PUBWEAK Vector118 - PUBWEAK Vector11C - PUBWEAK Vector120 - PUBWEAK Vector124 - PUBWEAK Vector128 - PUBWEAK Vector12C - PUBWEAK Vector130 - PUBWEAK Vector134 - PUBWEAK Vector138 - PUBWEAK Vector13C - PUBWEAK Vector140 - PUBWEAK Vector144 - PUBWEAK Vector148 - PUBWEAK Vector14C - PUBLIC _unhandled_exception - - SECTION .text:CODE:REORDER(1) - THUMB - -NMIVector -HardFaultVector -MemManageVector -BusFaultVector -UsageFaultVector -Vector1C -Vector20 -Vector24 -Vector28 -SVCallVector -DebugMonitorVector -Vector34 -PendSVVector -SysTickVector -Vector40 -Vector44 -Vector48 -Vector4C -Vector50 -Vector54 -Vector58 -Vector5C -Vector60 -Vector64 -Vector68 -Vector6C -Vector70 -Vector74 -Vector78 -Vector7C -Vector80 -Vector84 -Vector88 -Vector8C -Vector90 -Vector94 -Vector98 -Vector9C -VectorA0 -VectorA4 -VectorA8 -VectorAC -VectorB0 -VectorB4 -VectorB8 -VectorBC -VectorC0 -VectorC4 -VectorC8 -VectorCC -VectorD0 -VectorD4 -VectorD8 -VectorDC -VectorE0 -VectorE4 -VectorE8 -VectorEC -VectorF0 -VectorF4 -VectorF8 -VectorFC -Vector100 -Vector104 -Vector108 -Vector10C -Vector110 -Vector114 -Vector118 -Vector11C -Vector120 -Vector124 -Vector128 -Vector12C -Vector130 -Vector134 -Vector138 -Vector13C -Vector140 -Vector144 -Vector148 -Vector14C -_unhandled_exception - b _unhandled_exception - - END diff --git a/firmware/chibios/os/ports/IAR/ARMCMx/STM32F4xx/cmparams.h b/firmware/chibios/os/ports/IAR/ARMCMx/STM32F4xx/cmparams.h deleted file mode 100644 index 598358a8a1..0000000000 --- a/firmware/chibios/os/ports/IAR/ARMCMx/STM32F4xx/cmparams.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file IAR/ARMCMx/STM32F4xx/cmparams.h - * @brief ARM Cortex-M3 parameters for the STM32F4xx. - * - * @defgroup IAR_ARMCMx_STM32F4xx STM32F4xx Specific Parameters - * @ingroup IAR_ARMCMx_SPECIFIC - * @details This file contains the Cortex-M4 specific parameters for the - * STM32F4xx platform. - * @{ - */ - -#ifndef _CMPARAMS_H_ -#define _CMPARAMS_H_ - -/** - * @brief Cortex core model. - */ -#define CORTEX_MODEL CORTEX_M4 - -/** - * @brief Systick unit presence. - */ -#define CORTEX_HAS_ST TRUE - -/** - * @brief Memory Protection unit presence. - */ -#define CORTEX_HAS_MPU TRUE - -/** - * @brief Floating Point unit presence. - */ -#define CORTEX_HAS_FPU TRUE - -/** - * @brief Number of bits in priority masks. - */ -#define CORTEX_PRIORITY_BITS 4 - -#endif /* _CMPARAMS_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/ports/IAR/ARMCMx/STM32F4xx/vectors.s b/firmware/chibios/os/ports/IAR/ARMCMx/STM32F4xx/vectors.s deleted file mode 100644 index 8582897b78..0000000000 --- a/firmware/chibios/os/ports/IAR/ARMCMx/STM32F4xx/vectors.s +++ /dev/null @@ -1,344 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - - MODULE ?vectors - - AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE - PRESERVE8 - - SECTION IRQSTACK:DATA:NOROOT(3) - SECTION .intvec:CODE:NOROOT(3) - - EXTERN __iar_program_start - PUBLIC __vector_table - - DATA - -__vector_table: - DCD SFE(IRQSTACK) - DCD __iar_program_start - DCD NMIVector - DCD HardFaultVector - DCD MemManageVector - DCD BusFaultVector - DCD UsageFaultVector - DCD Vector1C - DCD Vector20 - DCD Vector24 - DCD Vector28 - DCD SVCallVector - DCD DebugMonitorVector - DCD Vector34 - DCD PendSVVector - DCD SysTickVector - DCD Vector40 - DCD Vector44 - DCD Vector48 - DCD Vector4C - DCD Vector50 - DCD Vector54 - DCD Vector58 - DCD Vector5C - DCD Vector60 - DCD Vector64 - DCD Vector68 - DCD Vector6C - DCD Vector70 - DCD Vector74 - DCD Vector78 - DCD Vector7C - DCD Vector80 - DCD Vector84 - DCD Vector88 - DCD Vector8C - DCD Vector90 - DCD Vector94 - DCD Vector98 - DCD Vector9C - DCD VectorA0 - DCD VectorA4 - DCD VectorA8 - DCD VectorAC - DCD VectorB0 - DCD VectorB4 - DCD VectorB8 - DCD VectorBC - DCD VectorC0 - DCD VectorC4 - DCD VectorC8 - DCD VectorCC - DCD VectorD0 - DCD VectorD4 - DCD VectorD8 - DCD VectorDC - DCD VectorE0 - DCD VectorE4 - DCD VectorE8 - DCD VectorEC - DCD VectorF0 - DCD VectorF4 - DCD VectorF8 - DCD VectorFC - DCD Vector100 - DCD Vector104 - DCD Vector108 - DCD Vector10C - DCD Vector110 - DCD Vector114 - DCD Vector118 - DCD Vector11C - DCD Vector120 - DCD Vector124 - DCD Vector128 - DCD Vector12C - DCD Vector130 - DCD Vector134 - DCD Vector138 - DCD Vector13C - DCD Vector140 - DCD Vector144 - DCD Vector148 - DCD Vector14C - DCD Vector150 - DCD Vector154 - DCD Vector158 - DCD Vector15C - DCD Vector160 - DCD Vector164 - DCD Vector168 - DCD Vector16C - DCD Vector170 - DCD Vector174 - DCD Vector178 - DCD Vector17C - DCD Vector180 - DCD Vector184 - -/* - * Default interrupt handlers. - */ - PUBWEAK NMIVector - PUBWEAK HardFaultVector - PUBWEAK MemManageVector - PUBWEAK BusFaultVector - PUBWEAK UsageFaultVector - PUBWEAK Vector1C - PUBWEAK Vector20 - PUBWEAK Vector24 - PUBWEAK Vector28 - PUBWEAK SVCallVector - PUBWEAK DebugMonitorVector - PUBWEAK Vector34 - PUBWEAK PendSVVector - PUBWEAK SysTickVector - PUBWEAK Vector40 - PUBWEAK Vector44 - PUBWEAK Vector48 - PUBWEAK Vector4C - PUBWEAK Vector50 - PUBWEAK Vector54 - PUBWEAK Vector58 - PUBWEAK Vector5C - PUBWEAK Vector60 - PUBWEAK Vector64 - PUBWEAK Vector68 - PUBWEAK Vector6C - PUBWEAK Vector70 - PUBWEAK Vector74 - PUBWEAK Vector78 - PUBWEAK Vector7C - PUBWEAK Vector80 - PUBWEAK Vector84 - PUBWEAK Vector88 - PUBWEAK Vector8C - PUBWEAK Vector90 - PUBWEAK Vector94 - PUBWEAK Vector98 - PUBWEAK Vector9C - PUBWEAK VectorA0 - PUBWEAK VectorA4 - PUBWEAK VectorA8 - PUBWEAK VectorAC - PUBWEAK VectorB0 - PUBWEAK VectorB4 - PUBWEAK VectorB8 - PUBWEAK VectorBC - PUBWEAK VectorC0 - PUBWEAK VectorC4 - PUBWEAK VectorC8 - PUBWEAK VectorCC - PUBWEAK VectorD0 - PUBWEAK VectorD4 - PUBWEAK VectorD8 - PUBWEAK VectorDC - PUBWEAK VectorE0 - PUBWEAK VectorE4 - PUBWEAK VectorE8 - PUBWEAK VectorEC - PUBWEAK VectorF0 - PUBWEAK VectorF4 - PUBWEAK VectorF8 - PUBWEAK VectorFC - PUBWEAK Vector100 - PUBWEAK Vector104 - PUBWEAK Vector108 - PUBWEAK Vector10C - PUBWEAK Vector110 - PUBWEAK Vector114 - PUBWEAK Vector118 - PUBWEAK Vector11C - PUBWEAK Vector120 - PUBWEAK Vector124 - PUBWEAK Vector128 - PUBWEAK Vector12C - PUBWEAK Vector130 - PUBWEAK Vector134 - PUBWEAK Vector138 - PUBWEAK Vector13C - PUBWEAK Vector140 - PUBWEAK Vector144 - PUBWEAK Vector148 - PUBWEAK Vector14C - PUBWEAK Vector150 - PUBWEAK Vector154 - PUBWEAK Vector158 - PUBWEAK Vector15C - PUBWEAK Vector160 - PUBWEAK Vector164 - PUBWEAK Vector168 - PUBWEAK Vector16C - PUBWEAK Vector170 - PUBWEAK Vector174 - PUBWEAK Vector178 - PUBWEAK Vector17C - PUBWEAK Vector180 - PUBWEAK Vector184 - PUBLIC _unhandled_exception - - SECTION .text:CODE:REORDER(1) - THUMB - -NMIVector -HardFaultVector -MemManageVector -BusFaultVector -UsageFaultVector -Vector1C -Vector20 -Vector24 -Vector28 -SVCallVector -DebugMonitorVector -Vector34 -PendSVVector -SysTickVector -Vector40 -Vector44 -Vector48 -Vector4C -Vector50 -Vector54 -Vector58 -Vector5C -Vector60 -Vector64 -Vector68 -Vector6C -Vector70 -Vector74 -Vector78 -Vector7C -Vector80 -Vector84 -Vector88 -Vector8C -Vector90 -Vector94 -Vector98 -Vector9C -VectorA0 -VectorA4 -VectorA8 -VectorAC -VectorB0 -VectorB4 -VectorB8 -VectorBC -VectorC0 -VectorC4 -VectorC8 -VectorCC -VectorD0 -VectorD4 -VectorD8 -VectorDC -VectorE0 -VectorE4 -VectorE8 -VectorEC -VectorF0 -VectorF4 -VectorF8 -VectorFC -Vector100 -Vector104 -Vector108 -Vector10C -Vector110 -Vector114 -Vector118 -Vector11C -Vector120 -Vector124 -Vector128 -Vector12C -Vector130 -Vector134 -Vector138 -Vector13C -Vector140 -Vector144 -Vector148 -Vector14C -Vector150 -Vector154 -Vector158 -Vector15C -Vector160 -Vector164 -Vector168 -Vector16C -Vector170 -Vector174 -Vector178 -Vector17C -Vector180 -Vector184 -_unhandled_exception - b _unhandled_exception - - END diff --git a/firmware/chibios/os/ports/IAR/ARMCMx/chcore.c b/firmware/chibios/os/ports/IAR/ARMCMx/chcore.c deleted file mode 100644 index 1c543d9261..0000000000 --- a/firmware/chibios/os/ports/IAR/ARMCMx/chcore.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file IAR/ARMCMx/chcore.c - * @brief ARM Cortex-Mx port code. - * - * @addtogroup IAR_ARMCMx_CORE - * @{ - */ - -#include "ch.h" - -/** - * @brief Halts the system. - * @note The function is declared as a weak symbol, it is possible - * to redefine it in your application code. - */ -#if !defined(__DOXYGEN__) -__weak -#endif -void port_halt(void) { - - port_disable(); - while (TRUE) { - } -} - -/** @} */ diff --git a/firmware/chibios/os/ports/IAR/ARMCMx/chcore.h b/firmware/chibios/os/ports/IAR/ARMCMx/chcore.h deleted file mode 100644 index d73b0b2e41..0000000000 --- a/firmware/chibios/os/ports/IAR/ARMCMx/chcore.h +++ /dev/null @@ -1,196 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file IAR/ARMCMx/chcore.h - * @brief ARM Cortex-Mx port macros and structures. - * - * @addtogroup IAR_ARMCMx_CORE - * @{ - */ - -#ifndef _CHCORE_H_ -#define _CHCORE_H_ - -/*===========================================================================*/ -/* Port constants (common). */ -/*===========================================================================*/ - -/* Added to make the header stand-alone when included from asm.*/ -#ifndef FALSE -#define FALSE 0 -#endif -#ifndef TRUE -#define TRUE (!FALSE) -#endif - -#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */ -#define CORTEX_M1 1 /**< @brief Cortex-M1 variant. */ -#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */ -#define CORTEX_M4 4 /**< @brief Cortex-M4 variant. */ - -/* Inclusion of the Cortex-Mx implementation specific parameters.*/ -#include "cmparams.h" - -/* Cortex model check, only M0 and M3 supported right now.*/ -#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M3) || \ - (CORTEX_MODEL == CORTEX_M4) -#elif (CORTEX_MODEL == CORTEX_M1) -#error "untested Cortex-M model" -#else -#error "unknown or unsupported Cortex-M model" -#endif - -/** - * @brief Total priority levels. - */ -#define CORTEX_PRIORITY_LEVELS (1 << CORTEX_PRIORITY_BITS) - -/** - * @brief Minimum priority level. - * @details This minimum priority level is calculated from the number of - * priority bits supported by the specific Cortex-Mx implementation. - */ -#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1) - -/** - * @brief Maximum priority level. - * @details The maximum allowed priority level is always zero. - */ -#define CORTEX_MAXIMUM_PRIORITY 0 - -/*===========================================================================*/ -/* Port macros (common). */ -/*===========================================================================*/ - -/** - * @brief Priority level verification macro. - */ -#define CORTEX_IS_VALID_PRIORITY(n) \ - (((n) >= 0) && ((n) < CORTEX_PRIORITY_LEVELS)) - -/** - * @brief Priority level verification macro. - */ -#define CORTEX_IS_VALID_KERNEL_PRIORITY(n) \ - (((n) >= CORTEX_MAX_KERNEL_PRIORITY) && ((n) < CORTEX_PRIORITY_LEVELS)) - -/** - * @brief Priority level to priority mask conversion macro. - */ -#define CORTEX_PRIORITY_MASK(n) \ - ((n) << (8 - CORTEX_PRIORITY_BITS)) - -/*===========================================================================*/ -/* Port configurable parameters (common). */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Port derived parameters (common). */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Port exported info (common). */ -/*===========================================================================*/ - -/** - * @brief Macro defining a generic ARM architecture. - */ -#define CH_ARCHITECTURE_ARM - -/** - * @brief Name of the compiler supported by this port. - */ -#define CH_COMPILER_NAME "IAR" - -/*===========================================================================*/ -/* Port implementation part (common). */ -/*===========================================================================*/ - -/* Includes the sub-architecture-specific part.*/ -#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M1) -#include "chcore_v6m.h" -#elif (CORTEX_MODEL == CORTEX_M3) || (CORTEX_MODEL == CORTEX_M4) -#include "chcore_v7m.h" -#endif - -#if !defined(_FROM_ASM_) - -#include -#include "nvic.h" - -/* The following declarations are there just for Doxygen documentation, the - real declarations are inside the sub-headers.*/ -#if defined(__DOXYGEN__) - -/** - * @brief Stack and memory alignment enforcement. - * @note In this architecture the stack alignment is enforced to 64 bits, - * 32 bits alignment is supported by hardware but deprecated by ARM, - * the implementation choice is to not offer the option. - */ -typedef uint64_t stkalign_t; - -/** - * @brief Interrupt saved context. - * @details This structure represents the stack frame saved during a - * preemption-capable interrupt handler. - * @note It is implemented to match the Cortex-Mx exception context. - */ -struct extctx {}; - -/** - * @brief System saved context. - * @details This structure represents the inner stack frame during a context - * switching. - */ -struct intctx {}; - -#endif /* defined(__DOXYGEN__) */ - -/** - * @brief Excludes the default @p chSchIsPreemptionRequired()implementation. - */ -#define PORT_OPTIMIZED_ISPREEMPTIONREQUIRED - -#if (CH_TIME_QUANTUM > 0) || defined(__DOXYGEN__) -/** - * @brief Inline-able version of this kernel function. - */ -#define chSchIsPreemptionRequired() \ - (currp->p_preempt ? firstprio(&rlist.r_queue) > currp->p_prio : \ - firstprio(&rlist.r_queue) >= currp->p_prio) -#else /* CH_TIME_QUANTUM == 0 */ -#define chSchIsPreemptionRequired() \ - (firstprio(&rlist.r_queue) > currp->p_prio) -#endif /* CH_TIME_QUANTUM == 0 */ - -#endif /* _FROM_ASM_ */ - -#endif /* _CHCORE_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/ports/IAR/ARMCMx/chcore_v6m.c b/firmware/chibios/os/ports/IAR/ARMCMx/chcore_v6m.c deleted file mode 100644 index f65976ae5e..0000000000 --- a/firmware/chibios/os/ports/IAR/ARMCMx/chcore_v6m.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file IAR/ARMCMx/chcore_v6m.c - * @brief ARMv6-M architecture port code. - * - * @addtogroup IAR_ARMCMx_V6M_CORE - * @{ - */ - -#include "ch.h" - -/*===========================================================================*/ -/* Port interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief System Timer vector. - * @details This interrupt is used as system tick. - * @note The timer must be initialized in the startup code. - */ -CH_IRQ_HANDLER(SysTickVector) { - - CH_IRQ_PROLOGUE(); - - chSysLockFromIsr(); - chSysTimerHandlerI(); - chSysUnlockFromIsr(); - - CH_IRQ_EPILOGUE(); -} - -#if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__) -/** - * @brief NMI vector. - * @details The NMI vector is used for exception mode re-entering after a - * context switch. - */ -void NMIVector(void) { - register struct extctx *ctxp; - - /* Discarding the current exception context and positioning the stack to - point to the real one.*/ - ctxp = (struct extctx *)__get_PSP(); - ctxp++; - __set_PSP((unsigned long)ctxp); - port_unlock_from_isr(); -} -#endif /* !CORTEX_ALTERNATE_SWITCH */ - -#if CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__) -/** - * @brief PendSV vector. - * @details The PendSV vector is used for exception mode re-entering after a - * context switch. - */ -void PendSVVector(void) { - register struct extctx *ctxp; - - /* Discarding the current exception context and positioning the stack to - point to the real one.*/ - ctxp = (struct extctx *)__get_PSP(); - ctxp++; - __set_PSP((unsigned long)ctxp); -} -#endif /* CORTEX_ALTERNATE_SWITCH */ - -/*===========================================================================*/ -/* Port exported functions. */ -/*===========================================================================*/ - -/** - * @brief IRQ epilogue code. - * - * @param[in] lr value of the @p LR register on ISR entry - */ -void _port_irq_epilogue(regarm_t lr) { - - if (lr != (regarm_t)0xFFFFFFF1) { - register struct extctx *ctxp; - - port_lock_from_isr(); - /* Adding an artificial exception return context, there is no need to - populate it fully.*/ - ctxp = (struct extctx *)__get_PSP(); - ctxp--; - __set_PSP((unsigned long)ctxp); - ctxp->xpsr = (regarm_t)0x01000000; - - /* The exit sequence is different depending on if a preemption is - required or not.*/ - if (chSchIsPreemptionRequired()) { - /* Preemption is required we need to enforce a context switch.*/ - ctxp->pc = (regarm_t)_port_switch_from_isr; - } - else { - /* Preemption not required, we just need to exit the exception - atomically.*/ - ctxp->pc = (regarm_t)_port_exit_from_isr; - } - - /* Note, returning without unlocking is intentional, this is done in - order to keep the rest of the context switch atomic.*/ - } -} - -/** @} */ diff --git a/firmware/chibios/os/ports/IAR/ARMCMx/chcore_v6m.h b/firmware/chibios/os/ports/IAR/ARMCMx/chcore_v6m.h deleted file mode 100644 index 9db4bb64dc..0000000000 --- a/firmware/chibios/os/ports/IAR/ARMCMx/chcore_v6m.h +++ /dev/null @@ -1,386 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file IAR/ARMCMx/chcore_v6m.h - * @brief ARMv6-M architecture port macros and structures. - * - * @addtogroup IAR_ARMCMx_V6M_CORE - * @{ - */ - -#ifndef _CHCORE_V6M_H_ -#define _CHCORE_V6M_H_ - -/*===========================================================================*/ -/* Port constants. */ -/*===========================================================================*/ - -/** - * @brief PendSV priority level. - * @note This priority is enforced to be equal to @p 0, - * this handler always has the highest priority that cannot preempt - * the kernel. - */ -#define CORTEX_PRIORITY_PENDSV 0 - -/*===========================================================================*/ -/* Port macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Port configurable parameters. */ -/*===========================================================================*/ - -/** - * @brief Stack size for the system idle thread. - * @details This size depends on the idle thread implementation, usually - * the idle thread should take no more space than those reserved - * by @p PORT_INT_REQUIRED_STACK. - * @note In this port it is set to 16 because the idle thread does have - * a stack frame when compiling without optimizations. You may - * reduce this value to zero when compiling with optimizations. - */ -#if !defined(PORT_IDLE_THREAD_STACK_SIZE) -#define PORT_IDLE_THREAD_STACK_SIZE 16 -#endif - -/** - * @brief Per-thread stack overhead for interrupts servicing. - * @details This constant is used in the calculation of the correct working - * area size. - * @note In this port this value is conservatively set to 32 because the - * function @p chSchDoReschedule() can have a stack frame, especially - * with compiler optimizations disabled. The value can be reduced - * when compiler optimizations are enabled. - */ -#if !defined(PORT_INT_REQUIRED_STACK) -#define PORT_INT_REQUIRED_STACK 32 -#endif - -/** - * @brief Enables the use of the WFI instruction in the idle thread loop. - */ -#if !defined(CORTEX_ENABLE_WFI_IDLE) -#define CORTEX_ENABLE_WFI_IDLE FALSE -#endif - -/** - * @brief SYSTICK handler priority. - * @note The default SYSTICK handler priority is calculated as the priority - * level in the middle of the numeric priorities range. - */ -#if !defined(CORTEX_PRIORITY_SYSTICK) -#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1) -#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK) -/* If it is externally redefined then better perform a validity check on it.*/ -#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK" -#endif - -/** - * @brief Alternate preemption method. - * @details Activating this option will make the Kernel use the PendSV - * handler for preemption instead of the NMI handler. - */ -#ifndef CORTEX_ALTERNATE_SWITCH -#define CORTEX_ALTERNATE_SWITCH FALSE -#endif - -/*===========================================================================*/ -/* Port derived parameters. */ -/*===========================================================================*/ - -/** - * @brief Maximum usable priority for normal ISRs. - */ -#if CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__) -#define CORTEX_MAX_KERNEL_PRIORITY 1 -#else -#define CORTEX_MAX_KERNEL_PRIORITY 0 -#endif - -/*===========================================================================*/ -/* Port exported info. */ -/*===========================================================================*/ - -/** - * @brief Macro defining the specific ARM architecture. - */ -#define CH_ARCHITECTURE_ARM_v6M - -/** - * @brief Name of the implemented architecture. - */ -#define CH_ARCHITECTURE_NAME "ARMv6-M" - -/** - * @brief Name of the architecture variant. - */ -#if (CORTEX_MODEL == CORTEX_M0) || defined(__DOXYGEN__) -#define CH_CORE_VARIANT_NAME "Cortex-M0" -#elif (CORTEX_MODEL == CORTEX_M1) -#define CH_CORE_VARIANT_NAME "Cortex-M1" -#endif - -/** - * @brief Port-specific information string. - */ -#if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__) -#define CH_PORT_INFO "Preemption through NMI" -#else -#define CH_PORT_INFO "Preemption through PendSV" -#endif - -/*===========================================================================*/ -/* Port implementation part. */ -/*===========================================================================*/ - -#if !defined(_FROM_ASM_) - -/** - * @brief Generic ARM register. - */ -typedef void *regarm_t; - -/** - * @brief Stack and memory alignment enforcement. - * @note In this architecture the stack alignment is enforced to 64 bits, - * 32 bits alignment is supported by hardware but deprecated by ARM, - * the implementation choice is to not offer the option. - */ -typedef uint64_t stkalign_t; - - /* The documentation of the following declarations is in chconf.h in order - to not have duplicated structure names into the documentation.*/ -#if !defined(__DOXYGEN__) - -struct extctx { - regarm_t r0; - regarm_t r1; - regarm_t r2; - regarm_t r3; - regarm_t r12; - regarm_t lr_thd; - regarm_t pc; - regarm_t xpsr; -}; - -struct intctx { - regarm_t r8; - regarm_t r9; - regarm_t r10; - regarm_t r11; - regarm_t r4; - regarm_t r5; - regarm_t r6; - regarm_t r7; - regarm_t lr; -}; - -#endif /* !defined(__DOXYGEN__) */ - -/** - * @brief Platform dependent part of the @p Thread structure. - * @details In this port the structure just holds a pointer to the @p intctx - * structure representing the stack pointer at context switch time. - */ -struct context { - struct intctx *r13; -}; - -/** - * @brief Platform dependent part of the @p chThdCreateI() API. - * @details This code usually setup the context switching frame represented - * by an @p intctx structure. - */ -#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ - tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \ - wsize - \ - sizeof(struct intctx)); \ - tp->p_ctx.r13->r4 = (regarm_t)pf; \ - tp->p_ctx.r13->r5 = (regarm_t)arg; \ - tp->p_ctx.r13->lr = (regarm_t)_port_thread_start; \ -} - -/** - * @brief Enforces a correct alignment for a stack area size value. - */ -#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) - -/** - * @brief Computes the thread working area global size. - */ -#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ - sizeof(struct intctx) + \ - sizeof(struct extctx) + \ - (n) + (PORT_INT_REQUIRED_STACK)) - -/** - * @brief Static working area allocation. - * @details This macro is used to allocate a static thread working area - * aligned as both position and size. - */ -#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] - -/** - * @brief IRQ prologue code. - * @details This macro must be inserted at the start of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_PROLOGUE() regarm_t _saved_lr = (regarm_t)__get_LR() - -/** - * @brief IRQ epilogue code. - * @details This macro must be inserted at the end of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_EPILOGUE() _port_irq_epilogue(_saved_lr) - -/** - * @brief IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_IRQ_HANDLER(id) void id(void) - -/** - * @brief Fast IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_FAST_IRQ_HANDLER(id) void id(void) - -/** - * @brief Port-related initialization code. - */ -#define port_init() { \ - SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \ - nvicSetSystemHandlerPriority(HANDLER_PENDSV, \ - CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); \ - nvicSetSystemHandlerPriority(HANDLER_SYSTICK, \ - CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \ -} - -/** - * @brief Kernel-lock action. - * @details Usually this function just disables interrupts but may perform - * more actions. - */ -#define port_lock() __disable_interrupt() - -/** - * @brief Kernel-unlock action. - * @details Usually this function just enables interrupts but may perform - * more actions. - */ -#define port_unlock() __enable_interrupt() - -/** - * @brief Kernel-lock action from an interrupt handler. - * @details This function is invoked before invoking I-class APIs from - * interrupt handlers. The implementation is architecture dependent, - * in its simplest form it is void. - * @note Same as @p port_lock() in this port. - */ -#define port_lock_from_isr() port_lock() - -/** - * @brief Kernel-unlock action from an interrupt handler. - * @details This function is invoked after invoking I-class APIs from interrupt - * handlers. The implementation is architecture dependent, in its - * simplest form it is void. - * @note Same as @p port_lock() in this port. - */ -#define port_unlock_from_isr() port_unlock() - -/** - * @brief Disables all the interrupt sources. - */ -#define port_disable() __disable_interrupt() - -/** - * @brief Disables the interrupt sources below kernel-level priority. - */ -#define port_suspend() __disable_interrupt() - -/** - * @brief Enables all the interrupt sources. - */ -#define port_enable() __enable_interrupt() - -/** - * @brief Enters an architecture-dependent IRQ-waiting mode. - * @details The function is meant to return when an interrupt becomes pending. - * The simplest implementation is an empty function or macro but this - * would not take advantage of architecture-specific power saving - * modes. - * @note Implemented as an inlined @p WFI instruction. - */ -#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__) -#define port_wait_for_interrupt() asm ("wfi") -#else -#define port_wait_for_interrupt() -#endif - -/** - * @brief Performs a context switch between two threads. - * @details This is the most critical code in any port, this function - * is responsible for the context switch between 2 threads. - * @note The implementation of this code affects directly the context - * switch performance so optimize here as much as you can. - * - * @param[in] ntp the thread to be switched in - * @param[in] otp the thread to be switched out - */ -#if !CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__) -#define port_switch(ntp, otp) _port_switch(ntp, otp) -#else -#define port_switch(ntp, otp) { \ - if ((stkalign_t *)(__get_SP() - sizeof(struct intctx)) < otp->p_stklimit) \ - chDbgPanic("stack overflow"); \ - _port_switch(ntp, otp); \ -} -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void port_halt(void); - void _port_irq_epilogue(regarm_t lr); - void _port_switch_from_isr(void); - void _port_exit_from_isr(void); - void _port_switch(Thread *ntp, Thread *otp); - void _port_thread_start(void); -#ifdef __cplusplus -} -#endif - -#endif /* _FROM_ASM_ */ - -#endif /* _CHCORE_V6M_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/ports/IAR/ARMCMx/chcore_v7m.c b/firmware/chibios/os/ports/IAR/ARMCMx/chcore_v7m.c deleted file mode 100644 index 48504c64c6..0000000000 --- a/firmware/chibios/os/ports/IAR/ARMCMx/chcore_v7m.c +++ /dev/null @@ -1,198 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file IAR/ARMCMx/chcore_v7m.c - * @brief ARMv7-M architecture port code. - * - * @addtogroup IAR_ARMCMx_V7M_CORE - * @{ - */ - -#include "ch.h" - -/*===========================================================================*/ -/* Port interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief System Timer vector. - * @details This interrupt is used as system tick. - * @note The timer must be initialized in the startup code. - */ -CH_IRQ_HANDLER(SysTickVector) { - - CH_IRQ_PROLOGUE(); - - chSysLockFromIsr(); - chSysTimerHandlerI(); - chSysUnlockFromIsr(); - - CH_IRQ_EPILOGUE(); -} - -#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) -/** - * @brief SVC vector. - * @details The SVC vector is used for exception mode re-entering after a - * context switch. - * @note The PendSV vector is only used in advanced kernel mode. - */ -void SVCallVector(void) { - struct extctx *ctxp; - -#if CORTEX_USE_FPU - /* Enforcing unstacking of the FP part of the context.*/ - SCB_FPCCR &= ~FPCCR_LSPACT; -#endif - - /* Current PSP value.*/ - ctxp = (struct extctx *)__get_PSP(); - - /* Discarding the current exception context and positioning the stack to - point to the real one.*/ - ctxp++; - - /* Restoring real position of the original stack frame.*/ - __set_PSP((unsigned long)ctxp); - port_unlock_from_isr(); -} -#endif /* !CORTEX_SIMPLIFIED_PRIORITY */ - -#if CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) -/** - * @brief PendSV vector. - * @details The PendSV vector is used for exception mode re-entering after a - * context switch. - * @note The PendSV vector is only used in compact kernel mode. - */ -void PendSVVector(void) { - struct extctx *ctxp; - -#if CORTEX_USE_FPU - /* Enforcing unstacking of the FP part of the context.*/ - SCB_FPCCR &= ~FPCCR_LSPACT; -#endif - - /* Current PSP value.*/ - ctxp = (struct extctx *)__get_PSP(); - - /* Discarding the current exception context and positioning the stack to - point to the real one.*/ - ctxp++; - - /* Restoring real position of the original stack frame.*/ - __set_PSP((unsigned long)ctxp); -} -#endif /* CORTEX_SIMPLIFIED_PRIORITY */ - -/*===========================================================================*/ -/* Port exported functions. */ -/*===========================================================================*/ - -/** - * @brief Port-related initialization code. - */ -void _port_init(void) { - - /* Initialization of the vector table and priority related settings.*/ - SCB_VTOR = CORTEX_VTOR_INIT; - SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(CORTEX_PRIGROUP_INIT); - -#if CORTEX_USE_FPU - { - /* Initializing the FPU context save in lazy mode.*/ - SCB_FPCCR = FPCCR_ASPEN | FPCCR_LSPEN; - - /* CP10 and CP11 set to full access.*/ - SCB_CPACR |= 0x00F00000; - - /* Enables FPU context save/restore on exception entry/exit (FPCA bit).*/ - __set_CONTROL(__get_CONTROL() | 4); - - /* FPSCR and FPDSCR initially zero.*/ - __set_FPSCR(0); - SCB_FPDSCR = 0; - } -#endif - - /* Initialization of the system vectors used by the port.*/ - nvicSetSystemHandlerPriority(HANDLER_SVCALL, - CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL)); - nvicSetSystemHandlerPriority(HANDLER_PENDSV, - CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); - nvicSetSystemHandlerPriority(HANDLER_SYSTICK, - CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); -} - -/** - * @brief Exception exit redirection to _port_switch_from_isr(). - */ -void _port_irq_epilogue(void) { - - port_lock_from_isr(); - if ((SCB_ICSR & ICSR_RETTOBASE) != 0) { - struct extctx *ctxp; - -#if CORTEX_USE_FPU - /* Enforcing a lazy FPU state save. Note, it goes in the original - context because the FPCAR register has not been modified.*/ - (void)__get_FPSCR(); -#endif - - /* Current PSP value.*/ - ctxp = (struct extctx *)__get_PSP(); - - /* Adding an artificial exception return context, there is no need to - populate it fully.*/ - ctxp--; - ctxp->xpsr = (regarm_t)0x01000000; -#if CORTEX_USE_FPU - ctxp->fpscr = (regarm_t)SCB_FPDSCR; -#endif - __set_PSP((unsigned long)ctxp); - - /* The exit sequence is different depending on if a preemption is - required or not.*/ - if (chSchIsPreemptionRequired()) { - /* Preemption is required we need to enforce a context switch.*/ - ctxp->pc = (regarm_t)_port_switch_from_isr; - } - else { - /* Preemption not required, we just need to exit the exception - atomically.*/ - ctxp->pc = (regarm_t)_port_exit_from_isr; - } - - /* Note, returning without unlocking is intentional, this is done in - order to keep the rest of the context switch atomic.*/ - return; - } - port_unlock_from_isr(); -} - -/** @} */ diff --git a/firmware/chibios/os/ports/IAR/ARMCMx/chcore_v7m.h b/firmware/chibios/os/ports/IAR/ARMCMx/chcore_v7m.h deleted file mode 100644 index fa315c31ce..0000000000 --- a/firmware/chibios/os/ports/IAR/ARMCMx/chcore_v7m.h +++ /dev/null @@ -1,522 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file IAR/ARMCMx/chcore_v7m.h - * @brief ARMv7-M architecture port macros and structures. - * - * @addtogroup IAR_ARMCMx_V7M_CORE - * @{ - */ - -#ifndef _CHCORE_V7M_H_ -#define _CHCORE_V7M_H_ - -/*===========================================================================*/ -/* Port constants. */ -/*===========================================================================*/ - -/** - * @brief Disabled value for BASEPRI register. - */ -#define CORTEX_BASEPRI_DISABLED 0 - -/*===========================================================================*/ -/* Port macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Port configurable parameters. */ -/*===========================================================================*/ - -/** - * @brief Stack size for the system idle thread. - * @details This size depends on the idle thread implementation, usually - * the idle thread should take no more space than those reserved - * by @p PORT_INT_REQUIRED_STACK. - * @note In this port it is set to 16 because the idle thread does have - * a stack frame when compiling without optimizations. You may - * reduce this value to zero when compiling with optimizations. - */ -#if !defined(PORT_IDLE_THREAD_STACK_SIZE) -#define PORT_IDLE_THREAD_STACK_SIZE 16 -#endif - -/** - * @brief Per-thread stack overhead for interrupts servicing. - * @details This constant is used in the calculation of the correct working - * area size. - * @note In this port this value is conservatively set to 32 because the - * function @p chSchDoReschedule() can have a stack frame, especially - * with compiler optimizations disabled. The value can be reduced - * when compiler optimizations are enabled. - */ -#if !defined(PORT_INT_REQUIRED_STACK) -#define PORT_INT_REQUIRED_STACK 32 -#endif - -/** - * @brief Enables the use of the WFI instruction in the idle thread loop. - */ -#if !defined(CORTEX_ENABLE_WFI_IDLE) -#define CORTEX_ENABLE_WFI_IDLE FALSE -#endif - -/** - * @brief SYSTICK handler priority. - * @note The default SYSTICK handler priority is calculated as the priority - * level in the middle of the numeric priorities range. - */ -#if !defined(CORTEX_PRIORITY_SYSTICK) -#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1) -#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK) -/* If it is externally redefined then better perform a validity check on it.*/ -#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK" -#endif - -/** - * @brief FPU support in context switch. - * @details Activating this option activates the FPU support in the kernel. - */ -#if !defined(CORTEX_USE_FPU) -#define CORTEX_USE_FPU CORTEX_HAS_FPU -#elif CORTEX_USE_FPU && !CORTEX_HAS_FPU -/* This setting requires an FPU presence check in case it is externally - redefined.*/ -#error "the selected core does not have an FPU" -#endif - -/** - * @brief Simplified priority handling flag. - * @details Activating this option makes the Kernel work in compact mode. - */ -#if !defined(CORTEX_SIMPLIFIED_PRIORITY) -#define CORTEX_SIMPLIFIED_PRIORITY FALSE -#endif - -/** - * @brief SVCALL handler priority. - * @note The default SVCALL handler priority is defaulted to - * @p CORTEX_MAXIMUM_PRIORITY+1, this reserves the - * @p CORTEX_MAXIMUM_PRIORITY priority level as fast interrupts - * priority level. - */ -#if !defined(CORTEX_PRIORITY_SVCALL) -#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1) -#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL) -/* If it is externally redefined then better perform a validity check on it.*/ -#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL" -#endif - -/** - * @brief NVIC VTOR initialization expression. - */ -#if !defined(CORTEX_VTOR_INIT) || defined(__DOXYGEN__) -#define CORTEX_VTOR_INIT 0x00000000 -#endif - -/** - * @brief NVIC PRIGROUP initialization expression. - * @details The default assigns all available priority bits as preemption - * priority with no sub-priority. - */ -#if !defined(CORTEX_PRIGROUP_INIT) || defined(__DOXYGEN__) -#define CORTEX_PRIGROUP_INIT (7 - CORTEX_PRIORITY_BITS) -#endif - -/*===========================================================================*/ -/* Port derived parameters. */ -/*===========================================================================*/ - -#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) -/** - * @brief Maximum usable priority for normal ISRs. - */ -#define CORTEX_MAX_KERNEL_PRIORITY (CORTEX_PRIORITY_SVCALL + 1) - -/** - * @brief BASEPRI level within kernel lock. - * @note In compact kernel mode this constant value is enforced to zero. - */ -#define CORTEX_BASEPRI_KERNEL \ - CORTEX_PRIORITY_MASK(CORTEX_MAX_KERNEL_PRIORITY) -#else - -#define CORTEX_MAX_KERNEL_PRIORITY 1 -#define CORTEX_BASEPRI_KERNEL 0 -#endif - -/** - * @brief PendSV priority level. - * @note This priority is enforced to be equal to - * @p CORTEX_MAX_KERNEL_PRIORITY, this handler always have the - * highest priority that cannot preempt the kernel. - */ -#define CORTEX_PRIORITY_PENDSV CORTEX_MAX_KERNEL_PRIORITY - -/*===========================================================================*/ -/* Port exported info. */ -/*===========================================================================*/ - -#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__) -/** - * @brief Macro defining the specific ARM architecture. - */ -#define CH_ARCHITECTURE_ARM_v7M - -/** - * @brief Name of the implemented architecture. - */ -#define CH_ARCHITECTURE_NAME "ARMv7-M" - -/** - * @brief Name of the architecture variant. - */ -#define CH_CORE_VARIANT_NAME "Cortex-M3" - -#elif (CORTEX_MODEL == CORTEX_M4) -#define CH_ARCHITECTURE_ARM_v7ME -#define CH_ARCHITECTURE_NAME "ARMv7-ME" -#if CORTEX_USE_FPU -#define CH_CORE_VARIANT_NAME "Cortex-M4F" -#else -#define CH_CORE_VARIANT_NAME "Cortex-M4" -#endif -#endif - -/** - * @brief Port-specific information string. - */ -#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) -#define CH_PORT_INFO "Advanced kernel mode" -#else -#define CH_PORT_INFO "Compact kernel mode" -#endif - -/*===========================================================================*/ -/* Port implementation part. */ -/*===========================================================================*/ - -#if !defined(_FROM_ASM_) - -/** - * @brief Generic ARM register. - */ -typedef void *regarm_t; - -/** - * @brief Stack and memory alignment enforcement. - * @note In this architecture the stack alignment is enforced to 64 bits, - * 32 bits alignment is supported by hardware but deprecated by ARM, - * the implementation choice is to not offer the option. - */ -typedef uint64_t stkalign_t; - -/* The documentation of the following declarations is in chconf.h in order - to not have duplicated structure names into the documentation.*/ -#if !defined(__DOXYGEN__) - -struct extctx { - regarm_t r0; - regarm_t r1; - regarm_t r2; - regarm_t r3; - regarm_t r12; - regarm_t lr_thd; - regarm_t pc; - regarm_t xpsr; -#if CORTEX_USE_FPU - regarm_t s0; - regarm_t s1; - regarm_t s2; - regarm_t s3; - regarm_t s4; - regarm_t s5; - regarm_t s6; - regarm_t s7; - regarm_t s8; - regarm_t s9; - regarm_t s10; - regarm_t s11; - regarm_t s12; - regarm_t s13; - regarm_t s14; - regarm_t s15; - regarm_t fpscr; - regarm_t reserved; -#endif /* CORTEX_USE_FPU */ -}; - -struct intctx { -#if CORTEX_USE_FPU - regarm_t s16; - regarm_t s17; - regarm_t s18; - regarm_t s19; - regarm_t s20; - regarm_t s21; - regarm_t s22; - regarm_t s23; - regarm_t s24; - regarm_t s25; - regarm_t s26; - regarm_t s27; - regarm_t s28; - regarm_t s29; - regarm_t s30; - regarm_t s31; -#endif /* CORTEX_USE_FPU */ - regarm_t r4; - regarm_t r5; - regarm_t r6; - regarm_t r7; - regarm_t r8; - regarm_t r9; - regarm_t r10; - regarm_t r11; - regarm_t lr; -}; - -#endif /* !defined(__DOXYGEN__) */ - -/** - * @brief Platform dependent part of the @p Thread structure. - * @details In this port the structure just holds a pointer to the @p intctx - * structure representing the stack pointer at context switch time. - */ -struct context { - struct intctx *r13; -}; - -/** - * @brief Platform dependent part of the @p chThdCreateI() API. - * @details This code usually setup the context switching frame represented - * by an @p intctx structure. - */ -#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ - tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \ - wsize - \ - sizeof(struct intctx)); \ - tp->p_ctx.r13->r4 = (regarm_t)pf; \ - tp->p_ctx.r13->r5 = (regarm_t)arg; \ - tp->p_ctx.r13->lr = (regarm_t)_port_thread_start; \ -} - -/** - * @brief Enforces a correct alignment for a stack area size value. - */ -#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) - -/** - * @brief Computes the thread working area global size. - */ -#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ - sizeof(struct intctx) + \ - sizeof(struct extctx) + \ - (n) + (PORT_INT_REQUIRED_STACK)) - -/** - * @brief Static working area allocation. - * @details This macro is used to allocate a static thread working area - * aligned as both position and size. - */ -#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] - -/** - * @brief IRQ prologue code. - * @details This macro must be inserted at the start of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_PROLOGUE() - -/** - * @brief IRQ epilogue code. - * @details This macro must be inserted at the end of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_EPILOGUE() _port_irq_epilogue() - -/** - * @brief IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_IRQ_HANDLER(id) void id(void) - -/** - * @brief Fast IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_FAST_IRQ_HANDLER(id) void id(void) - -/** - * @brief Port-related initialization code. - */ -#define port_init() _port_init() - -/** - * @brief Kernel-lock action. - * @details Usually this function just disables interrupts but may perform - * more actions. - * @note In this port this it raises the base priority to kernel level. - */ -#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) -#define port_lock() __set_BASEPRI(CORTEX_BASEPRI_KERNEL) -#else /* CORTEX_SIMPLIFIED_PRIORITY */ -#define port_lock() __disable_interrupt() -#endif /* CORTEX_SIMPLIFIED_PRIORITY */ - -/** - * @brief Kernel-unlock action. - * @details Usually this function just enables interrupts but may perform - * more actions. - * @note In this port this it lowers the base priority to user level. - */ -#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) -#define port_unlock() __set_BASEPRI(CORTEX_BASEPRI_DISABLED) -#else /* CORTEX_SIMPLIFIED_PRIORITY */ -#define port_unlock() __enable_interrupt() -#endif /* CORTEX_SIMPLIFIED_PRIORITY */ - -/** - * @brief Kernel-lock action from an interrupt handler. - * @details This function is invoked before invoking I-class APIs from - * interrupt handlers. The implementation is architecture dependent, - * in its simplest form it is void. - * @note Same as @p port_lock() in this port. - */ -#define port_lock_from_isr() port_lock() - -/** - * @brief Kernel-unlock action from an interrupt handler. - * @details This function is invoked after invoking I-class APIs from interrupt - * handlers. The implementation is architecture dependent, in its - * simplest form it is void. - * @note Same as @p port_unlock() in this port. - */ -#define port_unlock_from_isr() port_unlock() - -/** - * @brief Disables all the interrupt sources. - * @note Of course non-maskable interrupt sources are not included. - * @note In this port it disables all the interrupt sources by raising - * the priority mask to level 0. - */ -#define port_disable() __disable_interrupt() - -/** - * @brief Disables the interrupt sources below kernel-level priority. - * @note Interrupt sources above kernel level remains enabled. - * @note In this port it raises/lowers the base priority to kernel level. - */ -#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) -#define port_suspend() { \ - __set_BASEPRI(CORTEX_BASEPRI_KERNEL); \ - __enable_interrupt(); \ -} -#else /* CORTEX_SIMPLIFIED_PRIORITY */ -#define port_suspend() __disable_interrupt() -#endif /* CORTEX_SIMPLIFIED_PRIORITY */ - -/** - * @brief Enables all the interrupt sources. - * @note In this port it lowers the base priority to user level. - */ -#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) -#define port_enable() { \ - __set_BASEPRI(CORTEX_BASEPRI_DISABLED); \ - __enable_interrupt(); \ -} -#else /* CORTEX_SIMPLIFIED_PRIORITY */ -#define port_enable() __enable_interrupt() -#endif /* CORTEX_SIMPLIFIED_PRIORITY */ - -/** - * @brief Enters an architecture-dependent IRQ-waiting mode. - * @details The function is meant to return when an interrupt becomes pending. - * The simplest implementation is an empty function or macro but this - * would not take advantage of architecture-specific power saving - * modes. - * @note Implemented as an inlined @p WFI instruction. - */ -#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__) -#define port_wait_for_interrupt() asm ("wfi") -#else -#define port_wait_for_interrupt() -#endif - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -int getRemainingStack(Thread *otp); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -/** - * @brief Performs a context switch between two threads. - * @details This is the most critical code in any port, this function - * is responsible for the context switch between 2 threads. - * @note The implementation of this code affects directly the context - * switch performance so optimize here as much as you can. - * - * @param[in] ntp the thread to be switched in - * @param[in] otp the thread to be switched out - */ -#if !CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__) -#define port_switch(ntp, otp) _port_switch(ntp, otp) -#else -#define port_switch(ntp, otp) { \ - if (getRemainingStack(otp) < 0) \ - chDbgPanic("stack overflow"); \ - _port_switch(ntp, otp); \ -} -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void port_halt(void); - void _port_init(void); - void _port_irq_epilogue(void); - void _port_switch_from_isr(void); - void _port_exit_from_isr(void); - void _port_switch(Thread *ntp, Thread *otp); - void _port_thread_start(void); -#ifdef __cplusplus -} -#endif - -#endif /* _FROM_ASM_ */ - -#endif /* _CHCORE_V7M_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/ports/IAR/ARMCMx/chcoreasm_v6m.s b/firmware/chibios/os/ports/IAR/ARMCMx/chcoreasm_v6m.s deleted file mode 100644 index 944e9857c6..0000000000 --- a/firmware/chibios/os/ports/IAR/ARMCMx/chcoreasm_v6m.s +++ /dev/null @@ -1,118 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - - MODULE ?chcoreasm_v6m - - AAPCS INTERWORK, VFP_COMPATIBLE - PRESERVE8 - -/* - * Imports the Cortex-Mx configuration headers. - */ -#define _FROM_ASM_ -#include "chconf.h" -#include "chcore.h" - -CONTEXT_OFFSET SET 12 -SCB_ICSR SET 0xE000ED04 - - SECTION .text:CODE:NOROOT(2) - - EXTERN chThdExit - EXTERN chSchDoReschedule -#if CH_DBG_SYSTEM_STATE_CHECK - EXTERN dbg_check_unlock - EXTERN dbg_check_lock -#endif - - THUMB - -/* - * Performs a context switch between two threads. - */ - PUBLIC _port_switch -_port_switch: - push {r4, r5, r6, r7, lr} - mov r4, r8 - mov r5, r9 - mov r6, r10 - mov r7, r11 - push {r4, r5, r6, r7} - mov r3, sp - str r3, [r1, #CONTEXT_OFFSET] - ldr r3, [r0, #CONTEXT_OFFSET] - mov sp, r3 - pop {r4, r5, r6, r7} - mov r8, r4 - mov r9, r5 - mov r10, r6 - mov r11, r7 - pop {r4, r5, r6, r7, pc} - -/* - * Start a thread by invoking its work function. - * If the work function returns @p chThdExit() is automatically invoked. - */ - PUBLIC _port_thread_start -_port_thread_start: -#if CH_DBG_SYSTEM_STATE_CHECK - bl dbg_check_unlock -#endif - cpsie i - mov r0, r5 - blx r4 - bl chThdExit - -/* - * Post-IRQ switch code. - * Exception handlers return here for context switching. - */ - PUBLIC _port_switch_from_isr - PUBLIC _port_exit_from_isr -_port_switch_from_isr: -#if CH_DBG_SYSTEM_STATE_CHECK - bl dbg_check_lock -#endif - bl chSchDoReschedule -#if CH_DBG_SYSTEM_STATE_CHECK - bl dbg_check_unlock -#endif -_port_exit_from_isr: - ldr r2, =SCB_ICSR - movs r3, #128 -#if CORTEX_ALTERNATE_SWITCH - lsls r3, r3, #21 - str r3, [r2, #0] - cpsie i -#else - lsls r3, r3, #24 - str r3, [r2, #0] -#endif -waithere: - b waithere - - END diff --git a/firmware/chibios/os/ports/IAR/ARMCMx/chcoreasm_v7m.s b/firmware/chibios/os/ports/IAR/ARMCMx/chcoreasm_v7m.s deleted file mode 100644 index c7f0436563..0000000000 --- a/firmware/chibios/os/ports/IAR/ARMCMx/chcoreasm_v7m.s +++ /dev/null @@ -1,116 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - - MODULE ?chcoreasm_v7m - - AAPCS INTERWORK, VFP_COMPATIBLE - PRESERVE8 - -/* - * Imports the Cortex-Mx configuration headers. - */ -#define _FROM_ASM_ -#include "config\stm32f4ems\chconf.h" -#include "chcore.h" - -CONTEXT_OFFSET SET 12 -SCB_ICSR SET 0xE000ED04 -ICSR_PENDSVSET SET 0x10000000 - - SECTION .text:CODE:NOROOT(2) - - EXTERN chThdExit - EXTERN chSchDoReschedule -#if CH_DBG_SYSTEM_STATE_CHECK - EXTERN dbg_check_unlock - EXTERN dbg_check_lock -#endif - - THUMB - -/* - * Performs a context switch between two threads. - */ - PUBLIC _port_switch -_port_switch: - push {r4, r5, r6, r7, r8, r9, r10, r11, lr} -#if CORTEX_USE_FPU - vpush {s16-s31} -#endif - str sp, [r1, #CONTEXT_OFFSET] - ldr sp, [r0, #CONTEXT_OFFSET] -#if CORTEX_USE_FPU - vpop {s16-s31} -#endif - pop {r4, r5, r6, r7, r8, r9, r10, r11, pc} - -/* - * Start a thread by invoking its work function. - * If the work function returns @p chThdExit() is automatically invoked. - */ - PUBLIC _port_thread_start -_port_thread_start: -#if CH_DBG_SYSTEM_STATE_CHECK - bl dbg_check_unlock -#endif -#if CORTEX_SIMPLIFIED_PRIORITY - cpsie i -#else - movs r3, #CORTEX_BASEPRI_DISABLED - msr BASEPRI, r3 -#endif - mov r0, r5 - blx r4 - bl chThdExit - -/* - * Post-IRQ switch code. - * Exception handlers return here for context switching. - */ - PUBLIC _port_switch_from_isr - PUBLIC _port_exit_from_isr -_port_switch_from_isr: -#if CH_DBG_SYSTEM_STATE_CHECK - bl dbg_check_lock -#endif - bl chSchDoReschedule -#if CH_DBG_SYSTEM_STATE_CHECK - bl dbg_check_unlock -#endif -_port_exit_from_isr: -#if CORTEX_SIMPLIFIED_PRIORITY - mov r3, #LWRD SCB_ICSR - movt r3, #HWRD SCB_ICSR - mov r2, #ICSR_PENDSVSET - str r2, [r3] - cpsie i -.L3: b .L3 -#else - svc #0 -#endif - - END diff --git a/firmware/chibios/os/ports/IAR/ARMCMx/chtypes.h b/firmware/chibios/os/ports/IAR/ARMCMx/chtypes.h deleted file mode 100644 index 98ac8ac344..0000000000 --- a/firmware/chibios/os/ports/IAR/ARMCMx/chtypes.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file IAR/ARMCMx/chtypes.h - * @brief ARM Cortex-Mx port system types. - * - * @addtogroup IAR_ARMCMx_CORE - * @{ - */ - -#ifndef _CHTYPES_H_ -#define _CHTYPES_H_ - -#include -#include -#include - -typedef bool bool_t; /**< Fast boolean type. */ -typedef uint8_t tmode_t; /**< Thread flags. */ -typedef uint8_t tstate_t; /**< Thread state. */ -typedef uint8_t trefs_t; /**< Thread references counter. */ -typedef uint8_t tslices_t; /**< Thread time slices counter. */ -typedef uint32_t tprio_t; /**< Thread priority. */ -typedef int32_t msg_t; /**< Inter-thread message. */ -typedef int32_t eventid_t; /**< Event Id. */ -typedef uint32_t eventmask_t; /**< Event mask. */ -typedef uint32_t flagsmask_t; /**< Event flags. */ -typedef uint32_t systime_t; /**< System time. */ -typedef int32_t cnt_t; /**< Resources counter. */ - -/** - * @brief Inline function modifier. - */ -#define INLINE inline - -/** - * @brief ROM constant modifier. - * @note It is set to use the "const" keyword in this port. - */ -#define ROMCONST const - -/** - * @brief Packed structure modifier (within). - * @note Empty in this port. - */ -#define PACK_STRUCT_STRUCT - -/** - * @brief Packed structure modifier (before). - */ -#define PACK_STRUCT_BEGIN __packed - -/** - * @brief Packed structure modifier (after). - * @note Empty in this port. - */ -#define PACK_STRUCT_END - -/** - * @brief Packed variable specifier. - */ -#define PACKED_VAR __packed - -#endif /* _CHTYPES_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/ports/IAR/ARMCMx/cstartup.s b/firmware/chibios/os/ports/IAR/ARMCMx/cstartup.s deleted file mode 100644 index 07db297209..0000000000 --- a/firmware/chibios/os/ports/IAR/ARMCMx/cstartup.s +++ /dev/null @@ -1,77 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - - MODULE ?cstartup - -CONTROL_MODE_PRIVILEGED SET 0 -CONTROL_MODE_UNPRIVILEGED SET 1 -CONTROL_USE_MSP SET 0 -CONTROL_USE_PSP SET 2 - - AAPCS INTERWORK, VFP_COMPATIBLE, ROPI - PRESERVE8 - - SECTION .intvec:CODE:NOROOT(3) - - SECTION .ccm:CODE:NOROOT(2) - - SECTION CSTACK:DATA:NOROOT(3) - PUBLIC __main_thread_stack_base__ -__main_thread_stack_base__: - PUBLIC __heap_end__ -__heap_end__: - - SECTION SYSHEAP:DATA:NOROOT(3) - PUBLIC __heap_base__ -__heap_base__: - - PUBLIC __iar_program_start - EXTERN __vector_table - EXTWEAK __iar_init_core - EXTWEAK __iar_init_vfp - EXTERN __cmain - - SECTION .text:CODE:REORDER(2) - REQUIRE __vector_table - THUMB -__iar_program_start: - cpsid i - ldr r0, =SFE(CSTACK) - msr PSP, r0 - movs r0, #CONTROL_MODE_PRIVILEGED | CONTROL_USE_PSP - msr CONTROL, r0 - isb - bl __early_init - bl __iar_init_core - bl __iar_init_vfp - b __cmain - - PUBWEAK __early_init -__early_init: - bx lr - - END diff --git a/firmware/chibios/os/ports/common/ARMCMx/CMSIS/include/arm_common_tables.h b/firmware/chibios/os/ports/common/ARMCMx/CMSIS/include/arm_common_tables.h deleted file mode 100644 index 8c35ef2bd5..0000000000 --- a/firmware/chibios/os/ports/common/ARMCMx/CMSIS/include/arm_common_tables.h +++ /dev/null @@ -1,38 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 11. November 2010 -* $Revision: V1.0.2 -* -* Project: CMSIS DSP Library -* Title: arm_common_tables.h -* -* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions -* -* Target Processor: Cortex-M4/Cortex-M3 -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. -* -------------------------------------------------------------------- */ - -#ifndef _ARM_COMMON_TABLES_H -#define _ARM_COMMON_TABLES_H - -#include "arm_math.h" - -extern const uint16_t armBitRevTable[1024]; -extern const q15_t armRecipTableQ15[64]; -extern const q31_t armRecipTableQ31[64]; -extern const q31_t realCoefAQ31[1024]; -extern const q31_t realCoefBQ31[1024]; -extern const float32_t twiddleCoef[6144]; -extern const q31_t twiddleCoefQ31[6144]; -extern const q15_t twiddleCoefQ15[6144]; - -#endif /* ARM_COMMON_TABLES_H */ diff --git a/firmware/chibios/os/ports/common/ARMCMx/CMSIS/include/arm_math.h b/firmware/chibios/os/ports/common/ARMCMx/CMSIS/include/arm_math.h deleted file mode 100644 index f9b2c5ee29..0000000000 --- a/firmware/chibios/os/ports/common/ARMCMx/CMSIS/include/arm_math.h +++ /dev/null @@ -1,7578 +0,0 @@ -/* ---------------------------------------------------------------------- - * Copyright (C) 2010-2011 ARM Limited. All rights reserved. - * - * $Date: 15. February 2012 - * $Revision: V1.1.0 - * - * Project: CMSIS DSP Library - * Title: arm_math.h - * - * Description: Public header file for CMSIS DSP Library - * - * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 - * - * Version 1.1.0 2012/02/15 - * Updated with more optimizations, bug fixes and minor API changes. - * - * Version 1.0.10 2011/7/15 - * Big Endian support added and Merged M0 and M3/M4 Source code. - * - * Version 1.0.3 2010/11/29 - * Re-organized the CMSIS folders and updated documentation. - * - * Version 1.0.2 2010/11/11 - * Documentation updated. - * - * Version 1.0.1 2010/10/05 - * Production release and review comments incorporated. - * - * Version 1.0.0 2010/09/20 - * Production release and review comments incorporated. - * -------------------------------------------------------------------- */ - -/** - \mainpage CMSIS DSP Software Library - * - * Introduction - * - * This user manual describes the CMSIS DSP software library, - * a suite of common signal processing functions for use on Cortex-M processor based devices. - * - * The library is divided into a number of functions each covering a specific category: - * - Basic math functions - * - Fast math functions - * - Complex math functions - * - Filters - * - Matrix functions - * - Transforms - * - Motor control functions - * - Statistical functions - * - Support functions - * - Interpolation functions - * - * The library has separate functions for operating on 8-bit integers, 16-bit integers, - * 32-bit integer and 32-bit floating-point values. - * - * Pre-processor Macros - * - * Each library project have differant pre-processor macros. - * - * - UNALIGNED_SUPPORT_DISABLE: - * - * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access - * - * - ARM_MATH_BIG_ENDIAN: - * - * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. - * - * - ARM_MATH_MATRIX_CHECK: - * - * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices - * - * - ARM_MATH_ROUNDING: - * - * Define macro ARM_MATH_ROUNDING for rounding on support functions - * - * - ARM_MATH_CMx: - * - * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target - * and ARM_MATH_CM0 for building library on cortex-M0 target. - * - * - __FPU_PRESENT: - * - * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries - * - * Toolchain Support - * - * The library has been developed and tested with MDK-ARM version 4.23. - * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. - * - * Using the Library - * - * The library installer contains prebuilt versions of the libraries in the Lib folder. - * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) - * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) - * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) - * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) - * - arm_cortexM0l_math.lib (Little endian on Cortex-M0) - * - arm_cortexM0b_math.lib (Big endian on Cortex-M3) - * - * The library functions are declared in the public file arm_math.h which is placed in the Include folder. - * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single - * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. - * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or - * ARM_MATH_CM0 depending on the target processor in the application. - * - * Examples - * - * The library ships with a number of examples which demonstrate how to use the library functions. - * - * Building the Library - * - * The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. - * - arm_cortexM0b_math.uvproj - * - arm_cortexM0l_math.uvproj - * - arm_cortexM3b_math.uvproj - * - arm_cortexM3l_math.uvproj - * - arm_cortexM4b_math.uvproj - * - arm_cortexM4l_math.uvproj - * - arm_cortexM4bf_math.uvproj - * - arm_cortexM4lf_math.uvproj - * - * - * The project can be built by opening the appropriate project in MDK-ARM 4.23 chain and defining the optional pre processor MACROs detailed above. - * - * Copyright Notice - * - * Copyright (C) 2010 ARM Limited. All rights reserved. - */ - - -/** - * @defgroup groupMath Basic Math Functions - */ - -/** - * @defgroup groupFastMath Fast Math Functions - * This set of functions provides a fast approximation to sine, cosine, and square root. - * As compared to most of the other functions in the CMSIS math library, the fast math functions - * operate on individual values and not arrays. - * There are separate functions for Q15, Q31, and floating-point data. - * - */ - -/** - * @defgroup groupCmplxMath Complex Math Functions - * This set of functions operates on complex data vectors. - * The data in the complex arrays is stored in an interleaved fashion - * (real, imag, real, imag, ...). - * In the API functions, the number of samples in a complex array refers - * to the number of complex values; the array contains twice this number of - * real values. - */ - -/** - * @defgroup groupFilters Filtering Functions - */ - -/** - * @defgroup groupMatrix Matrix Functions - * - * This set of functions provides basic matrix math operations. - * The functions operate on matrix data structures. For example, - * the type - * definition for the floating-point matrix structure is shown - * below: - * 
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- *
- * There are similar definitions for Q15 and Q31 data types. - * - * The structure specifies the size of the matrix and then points to - * an array of data. The array is of size numRows X numCols - * and the values are arranged in row order. That is, the - * matrix element (i, j) is stored at: - * 
- *     pData[i*numCols + j]
- *
- * - * \par Init Functions - * There is an associated initialization function for each type of matrix - * data structure. - * The initialization function sets the values of the internal structure fields. - * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() - * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. - * - * \par - * Use of the initialization function is optional. However, if initialization function is used - * then the instance structure cannot be placed into a const data section. - * To place the instance structure in a const data - * section, manually initialize the data structure. For example: - * 
- * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
- *
- * where nRows specifies the number of rows, nColumns - * specifies the number of columns, and pData points to the - * data array. - * - * \par Size Checking - * By default all of the matrix functions perform size checking on the input and - * output matrices. For example, the matrix addition function verifies that the - * two input matrices and the output matrix all have the same number of rows and - * columns. If the size check fails the functions return: - * 
- *     ARM_MATH_SIZE_MISMATCH
- *
- * Otherwise the functions return - * 
- *     ARM_MATH_SUCCESS
- *
- * There is some overhead associated with this matrix size checking. - * The matrix size checking is enabled via the \#define - * 
- *     ARM_MATH_MATRIX_CHECK
- *
- * within the library project settings. By default this macro is defined - * and size checking is enabled. By changing the project settings and - * undefining this macro size checking is eliminated and the functions - * run a bit faster. With size checking disabled the functions always - * return ARM_MATH_SUCCESS. - */ - -/** - * @defgroup groupTransforms Transform Functions - */ - -/** - * @defgroup groupController Controller Functions - */ - -/** - * @defgroup groupStats Statistics Functions - */ -/** - * @defgroup groupSupport Support Functions - */ - -/** - * @defgroup groupInterpolation Interpolation Functions - * These functions perform 1- and 2-dimensional interpolation of data. - * Linear interpolation is used for 1-dimensional data and - * bilinear interpolation is used for 2-dimensional data. - */ - -/** - * @defgroup groupExamples Examples - */ -#ifndef _ARM_MATH_H -#define _ARM_MATH_H - -/* CHIBIOS FIX BEGIN */ -#include "board.h" -#if defined(STM32F4XX) -#define ARM_MATH_CM4 -#define __FPU_PRESENT 1 -#elif (defined(STM32F10X_LD) || defined(STM32F10X_LD_VL) || \ - defined(STM32F10X_MD) || defined(STM32F10X_MD_VL) || \ - defined(STM32F10X_HD) || defined(STM32F10X_XL) || \ - defined(STM32F10X_CL)) -#define ARM_MATH_CM3 -#elif defined(STM32F0XX) -#define ARM_MATH_CM0 -#endif -/* CHIBIOS FIX END */ - -#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ - -#if defined (ARM_MATH_CM4) -#include "core_cm4.h" -#elif defined (ARM_MATH_CM3) -#include "core_cm3.h" -#elif defined (ARM_MATH_CM0) -#include "core_cm0.h" -#else -#include "ARMCM4.h" -#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....." -#endif - -#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ -#include "string.h" -#include "math.h" -#ifdef __cplusplus -extern "C" -{ -#endif - - - /** - * @brief Macros required for reciprocal calculation in Normalized LMS - */ - -#define DELTA_Q31 (0x100) -#define DELTA_Q15 0x5 -#define INDEX_MASK 0x0000003F -#ifndef PI -#define PI 3.14159265358979f -#endif - - /** - * @brief Macros required for SINE and COSINE Fast math approximations - */ - -#define TABLE_SIZE 256 -#define TABLE_SPACING_Q31 0x800000 -#define TABLE_SPACING_Q15 0x80 - - /** - * @brief Macros required for SINE and COSINE Controller functions - */ - /* 1.31(q31) Fixed value of 2/360 */ - /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ -#define INPUT_SPACING 0xB60B61 - - /** - * @brief Macro for Unaligned Support - */ -#ifndef UNALIGNED_SUPPORT_DISABLE - #define ALIGN4 -#else - #if defined (__GNUC__) - #define ALIGN4 __attribute__((aligned(4))) - #else - #define ALIGN4 __align(4) - #endif -#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ - - /** - * @brief Error status returned by some functions in the library. - */ - - typedef enum - { - ARM_MATH_SUCCESS = 0, /**< No error */ - ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ - ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ - ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ - ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ - ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ - ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ - } arm_status; - - /** - * @brief 8-bit fractional data type in 1.7 format. - */ - typedef int8_t q7_t; - - /** - * @brief 16-bit fractional data type in 1.15 format. - */ - typedef int16_t q15_t; - - /** - * @brief 32-bit fractional data type in 1.31 format. - */ - typedef int32_t q31_t; - - /** - * @brief 64-bit fractional data type in 1.63 format. - */ - typedef int64_t q63_t; - - /** - * @brief 32-bit floating-point type definition. - */ - typedef float float32_t; - - /** - * @brief 64-bit floating-point type definition. - */ - typedef double float64_t; - - /** - * @brief definition to read/write two 16 bit values. - */ -#if defined (__GNUC__) - #define __SIMD32(addr) (*( int32_t **) & (addr)) - #define _SIMD32_OFFSET(addr) (*( int32_t * ) (addr)) -#else - #define __SIMD32(addr) (*(__packed int32_t **) & (addr)) - #define _SIMD32_OFFSET(addr) (*(__packed int32_t * ) (addr)) -#endif - - #define __SIMD64(addr) (*(int64_t **) & (addr)) - -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) - /** - * @brief definition to pack two 16 bit values. - */ -#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ - (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) -#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ - (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) - -#endif - - - /** - * @brief definition to pack four 8 bit values. - */ -#ifndef ARM_MATH_BIG_ENDIAN - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) -#else - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) - -#endif - - - /** - * @brief Clips Q63 to Q31 values. - */ - __STATIC_INLINE q31_t clip_q63_to_q31( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; - } - - /** - * @brief Clips Q63 to Q15 values. - */ - __STATIC_INLINE q15_t clip_q63_to_q15( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); - } - - /** - * @brief Clips Q31 to Q7 values. - */ - __STATIC_INLINE q7_t clip_q31_to_q7( - q31_t x) - { - return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? - ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; - } - - /** - * @brief Clips Q31 to Q15 values. - */ - __STATIC_INLINE q15_t clip_q31_to_q15( - q31_t x) - { - return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? - ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; - } - - /** - * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. - */ - - __STATIC_INLINE q63_t mult32x64( - q63_t x, - q31_t y) - { - return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + - (((q63_t) (x >> 32) * y))); - } - - -#if defined (ARM_MATH_CM0) && defined ( __CC_ARM ) -#define __CLZ __clz -#endif - -#if defined (ARM_MATH_CM0) && defined ( __TASKING__ ) -/* No need to redefine __CLZ */ -#endif - -#if defined (ARM_MATH_CM0) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) ) - - __STATIC_INLINE uint32_t __CLZ(q31_t data); - - - __STATIC_INLINE uint32_t __CLZ(q31_t data) - { - uint32_t count = 0; - uint32_t mask = 0x80000000; - - while((data & mask) == 0) - { - count += 1u; - mask = mask >> 1u; - } - - return (count); - - } - -#endif - - /** - * @brief Function to Calculates 1/in(reciprocal) value of Q31 Data type. - */ - - __STATIC_INLINE uint32_t arm_recip_q31( - q31_t in, - q31_t * dst, - q31_t * pRecipTable) - { - - uint32_t out, tempVal; - uint32_t index, i; - uint32_t signBits; - - if(in > 0) - { - signBits = __CLZ(in) - 1; - } - else - { - signBits = __CLZ(-in) - 1; - } - - /* Convert input sample to 1.31 format */ - in = in << signBits; - - /* calculation of index for initial approximated Val */ - index = (uint32_t) (in >> 24u); - index = (index & INDEX_MASK); - - /* 1.31 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (q31_t) (((q63_t) in * out) >> 31u); - tempVal = 0x7FFFFFFF - tempVal; - /* 1.31 with exp 1 */ - //out = (q31_t) (((q63_t) out * tempVal) >> 30u); - out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1u); - - } - - /** - * @brief Function to Calculates 1/in(reciprocal) value of Q15 Data type. - */ - __STATIC_INLINE uint32_t arm_recip_q15( - q15_t in, - q15_t * dst, - q15_t * pRecipTable) - { - - uint32_t out = 0, tempVal = 0; - uint32_t index = 0, i = 0; - uint32_t signBits = 0; - - if(in > 0) - { - signBits = __CLZ(in) - 17; - } - else - { - signBits = __CLZ(-in) - 17; - } - - /* Convert input sample to 1.15 format */ - in = in << signBits; - - /* calculation of index for initial approximated Val */ - index = in >> 8; - index = (index & INDEX_MASK); - - /* 1.15 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0; i < 2; i++) - { - tempVal = (q15_t) (((q31_t) in * out) >> 15); - tempVal = 0x7FFF - tempVal; - /* 1.15 with exp 1 */ - out = (q15_t) (((q31_t) out * tempVal) >> 14); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1); - - } - - - /* - * @brief C custom defined intrinisic function for only M0 processors - */ -#if defined(ARM_MATH_CM0) - - __STATIC_INLINE q31_t __SSAT( - q31_t x, - uint32_t y) - { - int32_t posMax, negMin; - uint32_t i; - - posMax = 1; - for (i = 0; i < (y - 1); i++) - { - posMax = posMax * 2; - } - - if(x > 0) - { - posMax = (posMax - 1); - - if(x > posMax) - { - x = posMax; - } - } - else - { - negMin = -posMax; - - if(x < negMin) - { - x = negMin; - } - } - return (x); - - - } - -#endif /* end of ARM_MATH_CM0 */ - - - - /* - * @brief C custom defined intrinsic function for M3 and M0 processors - */ -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) - - /* - * @brief C custom defined QADD8 for M3 and M0 processors - */ - __STATIC_INLINE q31_t __QADD8( - q31_t x, - q31_t y) - { - - q31_t sum; - q7_t r, s, t, u; - - r = (q7_t) x; - s = (q7_t) y; - - r = __SSAT((q31_t) (r + s), 8); - s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); - t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); - u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); - - sum = - (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | - (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); - - return sum; - - } - - /* - * @brief C custom defined QSUB8 for M3 and M0 processors - */ - __STATIC_INLINE q31_t __QSUB8( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s, t, u; - - r = (q7_t) x; - s = (q7_t) y; - - r = __SSAT((r - s), 8); - s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; - t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; - u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; - - sum = - (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & - 0x000000FF); - - return sum; - } - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - __STATIC_INLINE q31_t __QADD16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = __SSAT(r + s, 16); - s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - - } - - /* - * @brief C custom defined SHADD16 for M3 and M0 processors - */ - __STATIC_INLINE q31_t __SHADD16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) + (s >> 1)); - s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - - } - - /* - * @brief C custom defined QSUB16 for M3 and M0 processors - */ - __STATIC_INLINE q31_t __QSUB16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = __SSAT(r - s, 16); - s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - /* - * @brief C custom defined SHSUB16 for M3 and M0 processors - */ - __STATIC_INLINE q31_t __SHSUB16( - q31_t x, - q31_t y) - { - - q31_t diff; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) - (s >> 1)); - s = (((x >> 17) - (y >> 17)) << 16); - - diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return diff; - } - - /* - * @brief C custom defined QASX for M3 and M0 processors - */ - __STATIC_INLINE q31_t __QASX( - q31_t x, - q31_t y) - { - - q31_t sum = 0; - - sum = - ((sum + - clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) + - clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16))); - - return sum; - } - - /* - * @brief C custom defined SHASX for M3 and M0 processors - */ - __STATIC_INLINE q31_t __SHASX( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) - (y >> 17)); - s = (((x >> 17) + (s >> 1)) << 16); - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - - /* - * @brief C custom defined QSAX for M3 and M0 processors - */ - __STATIC_INLINE q31_t __QSAX( - q31_t x, - q31_t y) - { - - q31_t sum = 0; - - sum = - ((sum + - clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) + - clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16))); - - return sum; - } - - /* - * @brief C custom defined SHSAX for M3 and M0 processors - */ - __STATIC_INLINE q31_t __SHSAX( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) + (y >> 17)); - s = (((x >> 17) - (s >> 1)) << 16); - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - /* - * @brief C custom defined SMUSDX for M3 and M0 processors - */ - __STATIC_INLINE q31_t __SMUSDX( - q31_t x, - q31_t y) - { - - return ((q31_t) (((short) x * (short) (y >> 16)) - - ((short) (x >> 16) * (short) y))); - } - - /* - * @brief C custom defined SMUADX for M3 and M0 processors - */ - __STATIC_INLINE q31_t __SMUADX( - q31_t x, - q31_t y) - { - - return ((q31_t) (((short) x * (short) (y >> 16)) + - ((short) (x >> 16) * (short) y))); - } - - /* - * @brief C custom defined QADD for M3 and M0 processors - */ - __STATIC_INLINE q31_t __QADD( - q31_t x, - q31_t y) - { - return clip_q63_to_q31((q63_t) x + y); - } - - /* - * @brief C custom defined QSUB for M3 and M0 processors - */ - __STATIC_INLINE q31_t __QSUB( - q31_t x, - q31_t y) - { - return clip_q63_to_q31((q63_t) x - y); - } - - /* - * @brief C custom defined SMLAD for M3 and M0 processors - */ - __STATIC_INLINE q31_t __SMLAD( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum + ((short) (x >> 16) * (short) (y >> 16)) + - ((short) x * (short) y)); - } - - /* - * @brief C custom defined SMLADX for M3 and M0 processors - */ - __STATIC_INLINE q31_t __SMLADX( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum + ((short) (x >> 16) * (short) (y)) + - ((short) x * (short) (y >> 16))); - } - - /* - * @brief C custom defined SMLSDX for M3 and M0 processors - */ - __STATIC_INLINE q31_t __SMLSDX( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum - ((short) (x >> 16) * (short) (y)) + - ((short) x * (short) (y >> 16))); - } - - /* - * @brief C custom defined SMLALD for M3 and M0 processors - */ - __STATIC_INLINE q63_t __SMLALD( - q31_t x, - q31_t y, - q63_t sum) - { - - return (sum + ((short) (x >> 16) * (short) (y >> 16)) + - ((short) x * (short) y)); - } - - /* - * @brief C custom defined SMLALDX for M3 and M0 processors - */ - __STATIC_INLINE q63_t __SMLALDX( - q31_t x, - q31_t y, - q63_t sum) - { - - return (sum + ((short) (x >> 16) * (short) y)) + - ((short) x * (short) (y >> 16)); - } - - /* - * @brief C custom defined SMUAD for M3 and M0 processors - */ - __STATIC_INLINE q31_t __SMUAD( - q31_t x, - q31_t y) - { - - return (((x >> 16) * (y >> 16)) + - (((x << 16) >> 16) * ((y << 16) >> 16))); - } - - /* - * @brief C custom defined SMUSD for M3 and M0 processors - */ - __STATIC_INLINE q31_t __SMUSD( - q31_t x, - q31_t y) - { - - return (-((x >> 16) * (y >> 16)) + - (((x << 16) >> 16) * ((y << 16) >> 16))); - } - - - /* - * @brief C custom defined SXTB16 for M3 and M0 processors - */ - __STATIC_INLINE q31_t __SXTB16( - q31_t x) - { - - return ((((x << 24) >> 24) & 0x0000FFFF) | - (((x << 8) >> 8) & 0xFFFF0000)); - } - - -#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) */ - - - /** - * @brief Instance structure for the Q7 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q7; - - /** - * @brief Instance structure for the Q15 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_f32; - - - /** - * @brief Processing function for the Q7 FIR filter. - * @param[in] *S points to an instance of the Q7 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q7( - const arm_fir_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 FIR filter. - * @param[in,out] *S points to an instance of the Q7 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed. - * @return none - */ - void arm_fir_init_q7( - arm_fir_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR filter. - * @param[in] *S points to an instance of the Q15 FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_fast_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q15 FIR filter. - * @param[in,out] *S points to an instance of the Q15 FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if - * numTaps is not a supported value. - */ - - arm_status arm_fir_init_q15( - arm_fir_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR filter. - * @param[in] *S points to an instance of the Q31 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_fast_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR filter. - * @param[in,out] *S points to an instance of the Q31 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return none. - */ - void arm_fir_init_q31( - arm_fir_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the floating-point FIR filter. - * @param[in] *S points to an instance of the floating-point FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_f32( - const arm_fir_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point FIR filter. - * @param[in,out] *S points to an instance of the floating-point FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return none. - */ - void arm_fir_init_f32( - arm_fir_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 Biquad cascade filter. - */ - typedef struct - { - int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - - } arm_biquad_casd_df1_inst_q15; - - - /** - * @brief Instance structure for the Q31 Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - - } arm_biquad_casd_df1_inst_q31; - - /** - * @brief Instance structure for the floating-point Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - - - } arm_biquad_casd_df1_inst_f32; - - - - /** - * @brief Processing function for the Q15 Biquad cascade filter. - * @param[in] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q15 Biquad cascade filter. - * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cascade_df1_init_q15( - arm_biquad_casd_df1_inst_q15 * S, - uint8_t numStages, - q15_t * pCoeffs, - q15_t * pState, - int8_t postShift); - - - /** - * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_fast_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 Biquad cascade filter - * @param[in] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_fast_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 Biquad cascade filter. - * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cascade_df1_init_q31( - arm_biquad_casd_df1_inst_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q31_t * pState, - int8_t postShift); - - /** - * @brief Processing function for the floating-point Biquad cascade filter. - * @param[in] *S points to an instance of the floating-point Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_f32( - const arm_biquad_casd_df1_inst_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point Biquad cascade filter. - * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_df1_init_f32( - arm_biquad_casd_df1_inst_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float32_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f32; - - /** - * @brief Instance structure for the Q15 matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q15_t *pData; /**< points to the data of the matrix. */ - - } arm_matrix_instance_q15; - - /** - * @brief Instance structure for the Q31 matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q31_t *pData; /**< points to the data of the matrix. */ - - } arm_matrix_instance_q31; - - - - /** - * @brief Floating-point matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_f32( - const arm_matrix_instance_f32 * pSrc, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_q15( - const arm_matrix_instance_q15 * pSrc, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_q31( - const arm_matrix_instance_q31 * pSrc, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - /** - * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @param[in] *pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_fast_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - /** - * @brief Q31 matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - /** - * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_fast_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - /** - * @brief Floating-point matrix scaling. - * @param[in] *pSrc points to the input matrix - * @param[in] scale scale factor - * @param[out] *pDst points to the output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_f32( - const arm_matrix_instance_f32 * pSrc, - float32_t scale, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix scaling. - * @param[in] *pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_q15( - const arm_matrix_instance_q15 * pSrc, - q15_t scaleFract, - int32_t shift, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix scaling. - * @param[in] *pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_q31( - const arm_matrix_instance_q31 * pSrc, - q31_t scaleFract, - int32_t shift, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_q31( - arm_matrix_instance_q31 * S, - uint16_t nRows, - uint16_t nColumns, - q31_t * pData); - - /** - * @brief Q15 matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_q15( - arm_matrix_instance_q15 * S, - uint16_t nRows, - uint16_t nColumns, - q15_t * pData); - - /** - * @brief Floating-point matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_f32( - arm_matrix_instance_f32 * S, - uint16_t nRows, - uint16_t nColumns, - float32_t * pData); - - - - /** - * @brief Instance structure for the Q15 PID Control. - */ - typedef struct - { - q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ -#ifdef ARM_MATH_CM0 - q15_t A1; - q15_t A2; -#else - q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ -#endif - q15_t state[3]; /**< The state array of length 3. */ - q15_t Kp; /**< The proportional gain. */ - q15_t Ki; /**< The integral gain. */ - q15_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q15; - - /** - * @brief Instance structure for the Q31 PID Control. - */ - typedef struct - { - q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - q31_t A2; /**< The derived gain, A2 = Kd . */ - q31_t state[3]; /**< The state array of length 3. */ - q31_t Kp; /**< The proportional gain. */ - q31_t Ki; /**< The integral gain. */ - q31_t Kd; /**< The derivative gain. */ - - } arm_pid_instance_q31; - - /** - * @brief Instance structure for the floating-point PID Control. - */ - typedef struct - { - float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - float32_t A2; /**< The derived gain, A2 = Kd . */ - float32_t state[3]; /**< The state array of length 3. */ - float32_t Kp; /**< The proportional gain. */ - float32_t Ki; /**< The integral gain. */ - float32_t Kd; /**< The derivative gain. */ - } arm_pid_instance_f32; - - - - /** - * @brief Initialization function for the floating-point PID Control. - * @param[in,out] *S points to an instance of the PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_f32( - arm_pid_instance_f32 * S, - int32_t resetStateFlag); - - /** - * @brief Reset function for the floating-point PID Control. - * @param[in,out] *S is an instance of the floating-point PID Control structure - * @return none - */ - void arm_pid_reset_f32( - arm_pid_instance_f32 * S); - - - /** - * @brief Initialization function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_q31( - arm_pid_instance_q31 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q31 PID Control structure - * @return none - */ - - void arm_pid_reset_q31( - arm_pid_instance_q31 * S); - - /** - * @brief Initialization function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_q15( - arm_pid_instance_q15 * S, - int32_t resetStateFlag); - - /** - * @brief Reset function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the q15 PID Control structure - * @return none - */ - void arm_pid_reset_q15( - arm_pid_instance_q15 * S); - - - /** - * @brief Instance structure for the floating-point Linear Interpolate function. - */ - typedef struct - { - uint32_t nValues; /**< nValues */ - float32_t x1; /**< x1 */ - float32_t xSpacing; /**< xSpacing */ - float32_t *pYData; /**< pointer to the table of Y values */ - } arm_linear_interp_instance_f32; - - /** - * @brief Instance structure for the floating-point bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - float32_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_f32; - - /** - * @brief Instance structure for the Q31 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q31_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q31; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q15_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q15; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q7_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q7; - - - /** - * @brief Q7 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q15; - - /** - * @brief Instance structure for the Q31 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q31; - - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix4_instance_f32; - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q15; - - /** - * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q31; - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix2_instance_f32; - - - /** - * @brief Processing function for the Q15 CFFT/CIFFT. - * @param[in] *S points to an instance of the Q15 CFFT/CIFFT structure. - * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. - * @return none. - */ - - void arm_cfft_radix4_q15( - const arm_cfft_radix4_instance_q15 * S, - q15_t * pSrc); - - /** - * @brief Processing function for the Q15 CFFT/CIFFT. - * @param[in] *S points to an instance of the Q15 CFFT/CIFFT structure. - * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. - * @return none. - */ - - void arm_cfft_radix2_q15( - const arm_cfft_radix2_instance_q15 * S, - q15_t * pSrc); - - /** - * @brief Initialization function for the Q15 CFFT/CIFFT. - * @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure. - * @param[in] fftLen length of the FFT. - * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. - */ - - arm_status arm_cfft_radix4_init_q15( - arm_cfft_radix4_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Initialization function for the Q15 CFFT/CIFFT. - * @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure. - * @param[in] fftLen length of the FFT. - * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. - */ - - arm_status arm_cfft_radix2_init_q15( - arm_cfft_radix2_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Processing function for the Q31 CFFT/CIFFT. - * @param[in] *S points to an instance of the Q31 CFFT/CIFFT structure. - * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. - * @return none. - */ - - void arm_cfft_radix4_q31( - const arm_cfft_radix4_instance_q31 * S, - q31_t * pSrc); - - /** - * @brief Initialization function for the Q31 CFFT/CIFFT. - * @param[in,out] *S points to an instance of the Q31 CFFT/CIFFT structure. - * @param[in] fftLen length of the FFT. - * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. - */ - - arm_status arm_cfft_radix4_init_q31( - arm_cfft_radix4_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Processing function for the Radix-2 Q31 CFFT/CIFFT. - * @param[in] *S points to an instance of the Radix-2 Q31 CFFT/CIFFT structure. - * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. - * @return none. - */ - - void arm_cfft_radix2_q31( - const arm_cfft_radix2_instance_q31 * S, - q31_t * pSrc); - - /** - * @brief Initialization function for the Radix-2 Q31 CFFT/CIFFT. - * @param[in,out] *S points to an instance of the Radix-2 Q31 CFFT/CIFFT structure. - * @param[in] fftLen length of the FFT. - * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. - */ - - arm_status arm_cfft_radix2_init_q31( - arm_cfft_radix2_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - - - /** - * @brief Processing function for the floating-point CFFT/CIFFT. - * @param[in] *S points to an instance of the floating-point CFFT/CIFFT structure. - * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. - * @return none. - */ - - void arm_cfft_radix2_f32( - const arm_cfft_radix2_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Initialization function for the floating-point CFFT/CIFFT. - * @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure. - * @param[in] fftLen length of the FFT. - * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. - */ - - arm_status arm_cfft_radix2_init_f32( - arm_cfft_radix2_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Processing function for the floating-point CFFT/CIFFT. - * @param[in] *S points to an instance of the floating-point CFFT/CIFFT structure. - * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. - * @return none. - */ - - void arm_cfft_radix4_f32( - const arm_cfft_radix4_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Initialization function for the floating-point CFFT/CIFFT. - * @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure. - * @param[in] fftLen length of the FFT. - * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. - */ - - arm_status arm_cfft_radix4_init_f32( - arm_cfft_radix4_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - - - /*---------------------------------------------------------------------- - * Internal functions prototypes FFT function - ----------------------------------------------------------------------*/ - - /** - * @brief Core function for the floating-point CFFT butterfly process. - * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef points to the twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ - - void arm_radix4_butterfly_f32( - float32_t * pSrc, - uint16_t fftLen, - float32_t * pCoef, - uint16_t twidCoefModifier); - - /** - * @brief Core function for the floating-point CIFFT butterfly process. - * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef points to twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @param[in] onebyfftLen value of 1/fftLen. - * @return none. - */ - - void arm_radix4_butterfly_inverse_f32( - float32_t * pSrc, - uint16_t fftLen, - float32_t * pCoef, - uint16_t twidCoefModifier, - float32_t onebyfftLen); - - /** - * @brief In-place bit reversal function. - * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. - * @param[in] fftSize length of the FFT. - * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table. - * @param[in] *pBitRevTab points to the bit reversal table. - * @return none. - */ - - void arm_bitreversal_f32( - float32_t * pSrc, - uint16_t fftSize, - uint16_t bitRevFactor, - uint16_t * pBitRevTab); - - /** - * @brief Core function for the Q31 CFFT butterfly process. - * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef points to Twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ - - void arm_radix4_butterfly_q31( - q31_t * pSrc, - uint32_t fftLen, - q31_t * pCoef, - uint32_t twidCoefModifier); - - /** - * @brief Core function for the f32 FFT butterfly process. - * @param[in, out] *pSrc points to the in-place buffer of f32 data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef points to Twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ - - void arm_radix2_butterfly_f32( - float32_t * pSrc, - uint32_t fftLen, - float32_t * pCoef, - uint16_t twidCoefModifier); - - /** - * @brief Core function for the Radix-2 Q31 CFFT butterfly process. - * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef points to Twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ - - void arm_radix2_butterfly_q31( - q31_t * pSrc, - uint32_t fftLen, - q31_t * pCoef, - uint16_t twidCoefModifier); - - /** - * @brief Core function for the Radix-2 Q15 CFFT butterfly process. - * @param[in, out] *pSrc points to the in-place buffer of Q15 data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef points to Twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ - - void arm_radix2_butterfly_q15( - q15_t * pSrc, - uint32_t fftLen, - q15_t * pCoef, - uint16_t twidCoefModifier); - - /** - * @brief Core function for the Radix-2 Q15 CFFT Inverse butterfly process. - * @param[in, out] *pSrc points to the in-place buffer of Q15 data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef points to Twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ - - void arm_radix2_butterfly_inverse_q15( - q15_t * pSrc, - uint32_t fftLen, - q15_t * pCoef, - uint16_t twidCoefModifier); - - /** - * @brief Core function for the Radix-2 Q31 CFFT Inverse butterfly process. - * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef points to Twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ - - void arm_radix2_butterfly_inverse_q31( - q31_t * pSrc, - uint32_t fftLen, - q31_t * pCoef, - uint16_t twidCoefModifier); - - /** - * @brief Core function for the f32 IFFT butterfly process. - * @param[in, out] *pSrc points to the in-place buffer of f32 data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef points to Twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @param[in] onebyfftLen 1/fftLenfth - * @return none. - */ - - void arm_radix2_butterfly_inverse_f32( - float32_t * pSrc, - uint32_t fftLen, - float32_t * pCoef, - uint16_t twidCoefModifier, - float32_t onebyfftLen); - - /** - * @brief Core function for the Q31 CIFFT butterfly process. - * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef points to twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ - - void arm_radix4_butterfly_inverse_q31( - q31_t * pSrc, - uint32_t fftLen, - q31_t * pCoef, - uint32_t twidCoefModifier); - - /** - * @brief In-place bit reversal function. - * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. - * @param[in] fftLen length of the FFT. - * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table - * @param[in] *pBitRevTab points to bit reversal table. - * @return none. - */ - - void arm_bitreversal_q31( - q31_t * pSrc, - uint32_t fftLen, - uint16_t bitRevFactor, - uint16_t * pBitRevTab); - - /** - * @brief Core function for the Q15 CFFT butterfly process. - * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef16 points to twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ - - void arm_radix4_butterfly_q15( - q15_t * pSrc16, - uint32_t fftLen, - q15_t * pCoef16, - uint32_t twidCoefModifier); - - - /** - * @brief Core function for the Q15 CIFFT butterfly process. - * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef16 points to twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ - - void arm_radix4_butterfly_inverse_q15( - q15_t * pSrc16, - uint32_t fftLen, - q15_t * pCoef16, - uint32_t twidCoefModifier); - - /** - * @brief In-place bit reversal function. - * @param[in, out] *pSrc points to the in-place buffer of Q15 data type. - * @param[in] fftLen length of the FFT. - * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table - * @param[in] *pBitRevTab points to bit reversal table. - * @return none. - */ - - void arm_bitreversal_q15( - q15_t * pSrc, - uint32_t fftLen, - uint16_t bitRevFactor, - uint16_t * pBitRevTab); - - - /** - * @brief Instance structure for the Q15 RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint32_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q15; - - /** - * @brief Instance structure for the Q31 RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint32_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q31; - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint16_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_f32; - - /** - * @brief Processing function for the Q15 RFFT/RIFFT. - * @param[in] *S points to an instance of the Q15 RFFT/RIFFT structure. - * @param[in] *pSrc points to the input buffer. - * @param[out] *pDst points to the output buffer. - * @return none. - */ - - void arm_rfft_q15( - const arm_rfft_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst); - - /** - * @brief Initialization function for the Q15 RFFT/RIFFT. - * @param[in, out] *S points to an instance of the Q15 RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of the Q15 CFFT/CIFFT structure. - * @param[in] fftLenReal length of the FFT. - * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. - */ - - arm_status arm_rfft_init_q15( - arm_rfft_instance_q15 * S, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - /** - * @brief Processing function for the Q31 RFFT/RIFFT. - * @param[in] *S points to an instance of the Q31 RFFT/RIFFT structure. - * @param[in] *pSrc points to the input buffer. - * @param[out] *pDst points to the output buffer. - * @return none. - */ - - void arm_rfft_q31( - const arm_rfft_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst); - - /** - * @brief Initialization function for the Q31 RFFT/RIFFT. - * @param[in, out] *S points to an instance of the Q31 RFFT/RIFFT structure. - * @param[in, out] *S_CFFT points to an instance of the Q31 CFFT/CIFFT structure. - * @param[in] fftLenReal length of the FFT. - * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. - */ - - arm_status arm_rfft_init_q31( - arm_rfft_instance_q31 * S, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - /** - * @brief Initialization function for the floating-point RFFT/RIFFT. - * @param[in,out] *S points to an instance of the floating-point RFFT/RIFFT structure. - * @param[in,out] *S_CFFT points to an instance of the floating-point CFFT/CIFFT structure. - * @param[in] fftLenReal length of the FFT. - * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. - */ - - arm_status arm_rfft_init_f32( - arm_rfft_instance_f32 * S, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - /** - * @brief Processing function for the floating-point RFFT/RIFFT. - * @param[in] *S points to an instance of the floating-point RFFT/RIFFT structure. - * @param[in] *pSrc points to the input buffer. - * @param[out] *pDst points to the output buffer. - * @return none. - */ - - void arm_rfft_f32( - const arm_rfft_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst); - - /** - * @brief Instance structure for the floating-point DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - float32_t normalize; /**< normalizing factor. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - float32_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_f32; - - /** - * @brief Initialization function for the floating-point DCT4/IDCT4. - * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. - */ - - arm_status arm_dct4_init_f32( - arm_dct4_instance_f32 * S, - arm_rfft_instance_f32 * S_RFFT, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint16_t N, - uint16_t Nby2, - float32_t normalize); - - /** - * @brief Processing function for the floating-point DCT4/IDCT4. - * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_f32( - const arm_dct4_instance_f32 * S, - float32_t * pState, - float32_t * pInlineBuffer); - - /** - * @brief Instance structure for the Q31 DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - q31_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q31; - - /** - * @brief Initialization function for the Q31 DCT4/IDCT4. - * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure - * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - - arm_status arm_dct4_init_q31( - arm_dct4_instance_q31 * S, - arm_rfft_instance_q31 * S_RFFT, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); - - /** - * @brief Processing function for the Q31 DCT4/IDCT4. - * @param[in] *S points to an instance of the Q31 DCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_q31( - const arm_dct4_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); - - /** - * @brief Instance structure for the Q15 DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - q15_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q15; - - /** - * @brief Initialization function for the Q15 DCT4/IDCT4. - * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - - arm_status arm_dct4_init_q15( - arm_dct4_instance_q15 * S, - arm_rfft_instance_q15 * S_RFFT, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize); - - /** - * @brief Processing function for the Q15 DCT4/IDCT4. - * @param[in] *S points to an instance of the Q15 DCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_q15( - const arm_dct4_instance_q15 * S, - q15_t * pState, - q15_t * pInlineBuffer); - - /** - * @brief Floating-point vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a floating-point vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scale scale factor to be applied - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_f32( - float32_t * pSrc, - float32_t scale, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q7 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q7( - q7_t * pSrc, - q7_t scaleFract, - int8_t shift, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q15 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q15( - q15_t * pSrc, - q15_t scaleFract, - int8_t shift, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q31 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q31( - q31_t * pSrc, - q31_t scaleFract, - int8_t shift, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Dot product of floating-point vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t blockSize, - float32_t * result); - - /** - * @brief Dot product of Q7 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q7( - q7_t * pSrcA, - q7_t * pSrcB, - uint32_t blockSize, - q31_t * result); - - /** - * @brief Dot product of Q15 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - /** - * @brief Dot product of Q31 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - /** - * @brief Shifts the elements of a Q7 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q7( - q7_t * pSrc, - int8_t shiftBits, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Shifts the elements of a Q15 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q15( - q15_t * pSrc, - int8_t shiftBits, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Shifts the elements of a Q31 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q31( - q31_t * pSrc, - int8_t shiftBits, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a floating-point vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_f32( - float32_t * pSrc, - float32_t offset, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q7 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q7( - q7_t * pSrc, - q7_t offset, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q15 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q15( - q15_t * pSrc, - q15_t offset, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q31 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q31( - q31_t * pSrc, - q31_t offset, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a floating-point vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q7 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q15 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q31 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - /** - * @brief Copies the elements of a floating-point vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q7 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q15 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q31 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - /** - * @brief Fills a constant value into a floating-point vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_f32( - float32_t value, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q7 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q7( - q7_t value, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q15 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q15( - q15_t value, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q31 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q31( - q31_t value, - q31_t * pDst, - uint32_t blockSize); - -/** - * @brief Convolution of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return none. - */ - - - void arm_conv_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return none. - */ - - void arm_conv_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - - /** - * @brief Convolution of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return none. - */ - - void arm_conv_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Partial convolution of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Partial convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Partial convolution of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q7 sequences - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Partial convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - - /** - * @brief Instance structure for the Q15 FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - - } arm_fir_decimate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - - } arm_fir_decimate_instance_f32; - - - - /** - * @brief Processing function for the floating-point FIR decimator. - * @param[in] *S points to an instance of the floating-point FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_f32( - const arm_fir_decimate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR decimator. - * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_f32( - arm_fir_decimate_instance_f32 * S, - uint16_t numTaps, - uint8_t M, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 FIR decimator. - * @param[in] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_fast_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @brief Initialization function for the Q15 FIR decimator. - * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_q15( - arm_fir_decimate_instance_q15 * S, - uint16_t numTaps, - uint8_t M, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator. - * @param[in] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_q31( - const arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_fast_q31( - arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR decimator. - * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_q31( - arm_fir_decimate_instance_q31 * S, - uint16_t numTaps, - uint8_t M, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - - /** - * @brief Instance structure for the Q15 FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ - } arm_fir_interpolate_instance_f32; - - - /** - * @brief Processing function for the Q15 FIR interpolator. - * @param[in] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_q15( - const arm_fir_interpolate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR interpolator. - * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_q15( - arm_fir_interpolate_instance_q15 * S, - uint8_t L, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR interpolator. - * @param[in] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_q31( - const arm_fir_interpolate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR interpolator. - * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_q31( - arm_fir_interpolate_instance_q31 * S, - uint8_t L, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR interpolator. - * @param[in] *S points to an instance of the floating-point FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_f32( - const arm_fir_interpolate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point FIR interpolator. - * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_f32( - arm_fir_interpolate_instance_f32 * S, - uint8_t L, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - /** - * @brief Instance structure for the high precision Q31 Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ - - } arm_biquad_cas_df1_32x64_ins_q31; - - - /** - * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cas_df1_32x64_q31( - const arm_biquad_cas_df1_32x64_ins_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cas_df1_32x64_init_q31( - arm_biquad_cas_df1_32x64_ins_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q63_t * pState, - uint8_t postShift); - - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f32; - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] *S points to an instance of the filter data structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df2T_f32( - const arm_biquad_cascade_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] *S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_df2T_init_f32( - arm_biquad_cascade_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - - /** - * @brief Instance structure for the Q15 FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_f32; - - /** - * @brief Initialization function for the Q15 FIR lattice filter. - * @param[in] *S points to an instance of the Q15 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_q15( - arm_fir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pCoeffs, - q15_t * pState); - - - /** - * @brief Processing function for the Q15 FIR lattice filter. - * @param[in] *S points to an instance of the Q15 FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_lattice_q15( - const arm_fir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR lattice filter. - * @param[in] *S points to an instance of the Q31 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_q31( - arm_fir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pCoeffs, - q31_t * pState); - - - /** - * @brief Processing function for the Q31 FIR lattice filter. - * @param[in] *S points to an instance of the Q31 FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_fir_lattice_q31( - const arm_fir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - -/** - * @brief Initialization function for the floating-point FIR lattice filter. - * @param[in] *S points to an instance of the floating-point FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_f32( - arm_fir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - /** - * @brief Processing function for the floating-point FIR lattice filter. - * @param[in] *S points to an instance of the floating-point FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_fir_lattice_f32( - const arm_fir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Instance structure for the Q15 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_f32; - - /** - * @brief Processing function for the floating-point IIR lattice filter. - * @param[in] *S points to an instance of the floating-point IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_f32( - const arm_iir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point IIR lattice filter. - * @param[in] *S points to an instance of the floating-point IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_init_f32( - arm_iir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pkCoeffs, - float32_t * pvCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 IIR lattice filter. - * @param[in] *S points to an instance of the Q31 IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_q31( - const arm_iir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 IIR lattice filter. - * @param[in] *S points to an instance of the Q31 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_init_q31( - arm_iir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pkCoeffs, - q31_t * pvCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 IIR lattice filter. - * @param[in] *S points to an instance of the Q15 IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_q15( - const arm_iir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 IIR lattice filter. - * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process per call. - * @return none. - */ - - void arm_iir_lattice_init_q15( - arm_iir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pkCoeffs, - q15_t * pvCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Instance structure for the floating-point LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that controls filter coefficient updates. */ - } arm_lms_instance_f32; - - /** - * @brief Processing function for floating-point LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_f32( - const arm_lms_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for floating-point LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to the coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_init_f32( - arm_lms_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - /** - * @brief Instance structure for the Q15 LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q15; - - - /** - * @brief Initialization function for the Q15 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to the coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_init_q15( - arm_lms_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint32_t postShift); - - /** - * @brief Processing function for Q15 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_q15( - const arm_lms_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - - } arm_lms_instance_q31; - - /** - * @brief Processing function for Q31 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_q31( - const arm_lms_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for Q31 LMS filter. - * @param[in] *S points to an instance of the Q31 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_init_q31( - arm_lms_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint32_t postShift); - - /** - * @brief Instance structure for the floating-point normalized LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that control filter coefficient updates. */ - float32_t energy; /**< saves previous frame energy. */ - float32_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_f32; - - /** - * @brief Processing function for floating-point normalized LMS filter. - * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_f32( - arm_lms_norm_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for floating-point normalized LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_init_f32( - arm_lms_norm_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q31_t *recipTable; /**< points to the reciprocal initial value table. */ - q31_t energy; /**< saves previous frame energy. */ - q31_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q31; - - /** - * @brief Processing function for Q31 normalized LMS filter. - * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_q31( - arm_lms_norm_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for Q31 normalized LMS filter. - * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_norm_init_q31( - arm_lms_norm_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint8_t postShift); - - /** - * @brief Instance structure for the Q15 normalized LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q15_t *recipTable; /**< Points to the reciprocal initial value table. */ - q15_t energy; /**< saves previous frame energy. */ - q15_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q15; - - /** - * @brief Processing function for Q15 normalized LMS filter. - * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_q15( - arm_lms_norm_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q15 normalized LMS filter. - * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_norm_init_q15( - arm_lms_norm_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint8_t postShift); - - /** - * @brief Correlation of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Correlation of Q15 sequences - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @return none. - */ - void arm_correlate_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - - /** - * @brief Correlation of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @return none. - */ - - void arm_correlate_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - /** - * @brief Correlation of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return none. - */ - - void arm_correlate_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Instance structure for the floating-point sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_f32; - - /** - * @brief Instance structure for the Q31 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q31; - - /** - * @brief Instance structure for the Q15 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q15; - - /** - * @brief Instance structure for the Q7 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q7; - - /** - * @brief Processing function for the floating-point sparse FIR filter. - * @param[in] *S points to an instance of the floating-point sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_f32( - arm_fir_sparse_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - float32_t * pScratchIn, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point sparse FIR filter. - * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_f32( - arm_fir_sparse_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 sparse FIR filter. - * @param[in] *S points to an instance of the Q31 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q31( - arm_fir_sparse_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - q31_t * pScratchIn, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q31( - arm_fir_sparse_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 sparse FIR filter. - * @param[in] *S points to an instance of the Q15 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] *pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q15( - arm_fir_sparse_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - q15_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q15( - arm_fir_sparse_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q7 sparse FIR filter. - * @param[in] *S points to an instance of the Q7 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] *pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q7( - arm_fir_sparse_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - q7_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q7 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q7( - arm_fir_sparse_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /* - * @brief Floating-point sin_cos function. - * @param[in] theta input value in degrees - * @param[out] *pSinVal points to the processed sine output. - * @param[out] *pCosVal points to the processed cos output. - * @return none. - */ - - void arm_sin_cos_f32( - float32_t theta, - float32_t * pSinVal, - float32_t * pCcosVal); - - /* - * @brief Q31 sin_cos function. - * @param[in] theta scaled input value in degrees - * @param[out] *pSinVal points to the processed sine output. - * @param[out] *pCosVal points to the processed cosine output. - * @return none. - */ - - void arm_sin_cos_q31( - q31_t theta, - q31_t * pSinVal, - q31_t * pCosVal); - - - /** - * @brief Floating-point complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - - /** - * @brief Floating-point complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup PID PID Motor Control - * - * A Proportional Integral Derivative (PID) controller is a generic feedback control - * loop mechanism widely used in industrial control systems. - * A PID controller is the most commonly used type of feedback controller. - * - * This set of functions implements (PID) controllers - * for Q15, Q31, and floating-point data types. The functions operate on a single sample - * of data and each call to the function returns a single processed value. - * S points to an instance of the PID control data structure. in - * is the input sample value. The functions return the output value. - * - * \par Algorithm: - * 
-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd
- * - * \par - * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant - * - * \par - * \image html PID.gif "Proportional Integral Derivative Controller" - * - * \par - * The PID controller calculates an "error" value as the difference between - * the measured output and the reference input. - * The controller attempts to minimize the error by adjusting the process control inputs. - * The proportional value determines the reaction to the current error, - * the integral value determines the reaction based on the sum of recent errors, - * and the derivative value determines the reaction based on the rate at which the error has been changing. - * - * \par Instance Structure - * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. - * A separate instance structure must be defined for each PID Controller. - * There are separate instance structure declarations for each of the 3 supported data types. - * - * \par Reset Functions - * There is also an associated reset function for each data type which clears the state array. - * - * \par Initialization Functions - * There is also an associated initialization function for each data type. - * The initialization function performs the following operations: - * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. - * - Zeros out the values in the state buffer. - * - * \par - * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. - * - * \par Fixed-Point Behavior - * Care must be taken when using the fixed-point versions of the PID Controller functions. - * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup PID - * @{ - */ - - /** - * @brief Process function for the floating-point PID Control. - * @param[in,out] *S is an instance of the floating-point PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - */ - - - __STATIC_INLINE float32_t arm_pid_f32( - arm_pid_instance_f32 * S, - float32_t in) - { - float32_t out; - - /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ - out = (S->A0 * in) + - (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q31 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 64-bit accumulator. - * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. - * Thus, if the accumulator result overflows it wraps around rather than clip. - * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. - * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. - */ - - __STATIC_INLINE q31_t arm_pid_q31( - arm_pid_instance_q31 * S, - q31_t in) - { - q63_t acc; - q31_t out; - - /* acc = A0 * x[n] */ - acc = (q63_t) S->A0 * in; - - /* acc += A1 * x[n-1] */ - acc += (q63_t) S->A1 * S->state[0]; - - /* acc += A2 * x[n-2] */ - acc += (q63_t) S->A2 * S->state[1]; - - /* convert output to 1.31 format to add y[n-1] */ - out = (q31_t) (acc >> 31u); - - /* out += y[n-1] */ - out += S->state[2]; - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using a 64-bit internal accumulator. - * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. - * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. - * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. - * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. - * Lastly, the accumulator is saturated to yield a result in 1.15 format. - */ - - __STATIC_INLINE q15_t arm_pid_q15( - arm_pid_instance_q15 * S, - q15_t in) - { - q63_t acc; - q15_t out; - - /* Implementation of PID controller */ - -#ifdef ARM_MATH_CM0 - - /* acc = A0 * x[n] */ - acc = ((q31_t) S->A0) * in; - -#else - - /* acc = A0 * x[n] */ - acc = (q31_t) __SMUAD(S->A0, in); - -#endif - -#ifdef ARM_MATH_CM0 - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc += (q31_t) S->A1 * S->state[0]; - acc += (q31_t) S->A2 * S->state[1]; - -#else - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc = __SMLALD(S->A1, (q31_t) __SIMD32(S->state), acc); - -#endif - - /* acc += y[n-1] */ - acc += (q31_t) S->state[2] << 15; - - /* saturate the output */ - out = (q15_t) (__SSAT((acc >> 15), 16)); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @} end of PID group - */ - - - /** - * @brief Floating-point matrix inverse. - * @param[in] *src points to the instance of the input floating-point matrix structure. - * @param[out] *dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - - arm_status arm_mat_inverse_f32( - const arm_matrix_instance_f32 * src, - arm_matrix_instance_f32 * dst); - - - - /** - * @ingroup groupController - */ - - - /** - * @defgroup clarke Vector Clarke Transform - * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. - * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents - * in the two-phase orthogonal stator axis Ialpha and Ibeta. - * When Ialpha is superposed with Ia as shown in the figure below - * \image html clarke.gif Stator current space vector and its components in (a,b). - * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta - * can be calculated using only Ia and Ib. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeFormula.gif - * where Ia and Ib are the instantaneous stator phases and - * pIalpha and pIbeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup clarke - * @{ - */ - - /** - * - * @brief Floating-point Clarke transform - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @return none. - */ - - __STATIC_INLINE void arm_clarke_f32( - float32_t Ia, - float32_t Ib, - float32_t * pIalpha, - float32_t * pIbeta) - { - /* Calculate pIalpha using the equation, pIalpha = Ia */ - *pIalpha = Ia; - - /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ - *pIbeta = - ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); - - } - - /** - * @brief Clarke transform for Q31 version - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - - __STATIC_INLINE void arm_clarke_q31( - q31_t Ia, - q31_t Ib, - q31_t * pIalpha, - q31_t * pIbeta) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIalpha from Ia by equation pIalpha = Ia */ - *pIalpha = Ia; - - /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); - - /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ - product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); - - /* pIbeta is calculated by adding the intermediate products */ - *pIbeta = __QADD(product1, product2); - } - - /** - * @} end of clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q31 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_q7_to_q31( - q7_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_clarke Vector Inverse Clarke Transform - * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeInvFormula.gif - * where pIa and pIb are the instantaneous stator phases and - * Ialpha and Ibeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_clarke - * @{ - */ - - /** - * @brief Floating-point Inverse Clarke transform - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] *pIa points to output three-phase coordinate a - * @param[out] *pIb points to output three-phase coordinate b - * @return none. - */ - - - __STATIC_INLINE void arm_inv_clarke_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pIa, - float32_t * pIb) - { - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ - *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; - - } - - /** - * @brief Inverse Clarke transform for Q31 version - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] *pIa points to output three-phase coordinate a - * @param[out] *pIb points to output three-phase coordinate b - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the subtraction, hence there is no risk of overflow. - */ - - __STATIC_INLINE void arm_inv_clarke_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pIa, - q31_t * pIb) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); - - /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); - - /* pIb is calculated by subtracting the products */ - *pIb = __QSUB(product2, product1); - - } - - /** - * @} end of inv_clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q15 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_q7_to_q15( - q7_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup park Vector Park Transform - * - * Forward Park transform converts the input two-coordinate vector to flux and torque components. - * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents - * from the stationary to the moving reference frame and control the spatial relationship between - * the stator vector current and rotor flux vector. - * If we consider the d axis aligned with the rotor flux, the diagram below shows the - * current vector and the relationship from the two reference frames: - * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkFormula.gif - * where Ialpha and Ibeta are the stator vector components, - * pId and pIq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup park - * @{ - */ - - /** - * @brief Floating-point Park transform - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] *pId points to output rotor reference frame d - * @param[out] *pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * The function implements the forward Park transform. - * - */ - - __STATIC_INLINE void arm_park_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pId, - float32_t * pIq, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ - *pId = Ialpha * cosVal + Ibeta * sinVal; - - /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ - *pIq = -Ialpha * sinVal + Ibeta * cosVal; - - } - - /** - * @brief Park transform for Q31 version - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] *pId points to output rotor reference frame d - * @param[out] *pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition and subtraction, hence there is no risk of overflow. - */ - - - __STATIC_INLINE void arm_park_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pId, - q31_t * pIq, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Ialpha * cosVal) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * sinVal) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Ialpha * sinVal) */ - product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * cosVal) */ - product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); - - /* Calculate pId by adding the two intermediate products 1 and 2 */ - *pId = __QADD(product1, product2); - - /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ - *pIq = __QSUB(product4, product3); - } - - /** - * @} end of park group - */ - - /** - * @brief Converts the elements of the Q7 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q7_to_float( - q7_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_park Vector Inverse Park transform - * Inverse Park transform converts the input flux and torque components to two-coordinate vector. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkInvFormula.gif - * where pIalpha and pIbeta are the stator vector components, - * Id and Iq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_park - * @{ - */ - - /** - * @brief Floating-point Inverse Park transform - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - */ - - __STATIC_INLINE void arm_inv_park_f32( - float32_t Id, - float32_t Iq, - float32_t * pIalpha, - float32_t * pIbeta, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ - *pIalpha = Id * cosVal - Iq * sinVal; - - /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ - *pIbeta = Id * sinVal + Iq * cosVal; - - } - - - /** - * @brief Inverse Park transform for Q31 version - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - - - __STATIC_INLINE void arm_inv_park_q31( - q31_t Id, - q31_t Iq, - q31_t * pIalpha, - q31_t * pIbeta, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Id * cosVal) */ - product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Iq * sinVal) */ - product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Id * sinVal) */ - product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Iq * cosVal) */ - product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); - - /* Calculate pIalpha by using the two intermediate products 1 and 2 */ - *pIalpha = __QSUB(product1, product2); - - /* Calculate pIbeta by using the two intermediate products 3 and 4 */ - *pIbeta = __QADD(product4, product3); - - } - - /** - * @} end of Inverse park group - */ - - - /** - * @brief Converts the elements of the Q31 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_float( - q31_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup LinearInterpolate Linear Interpolation - * - * Linear interpolation is a method of curve fitting using linear polynomials. - * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line - * - * \par - * \image html LinearInterp.gif "Linear interpolation" - * - * \par - * A Linear Interpolate function calculates an output value(y), for the input(x) - * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) - * - * \par Algorithm: - * 
-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   *
- * - * \par - * This set of functions implements Linear interpolation process - * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single - * sample of data and each call to the function returns a single processed value. - * S points to an instance of the Linear Interpolate function data structure. - * x is the input sample value. The functions returns the output value. - * - * \par - * if x is outside of the table boundary, Linear interpolation returns first value of the table - * if x is below input range and returns last value of table if x is above range. - */ - - /** - * @addtogroup LinearInterpolate - * @{ - */ - - /** - * @brief Process function for the floating-point Linear Interpolation Function. - * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure - * @param[in] x input sample to process - * @return y processed output sample. - * - */ - - __STATIC_INLINE float32_t arm_linear_interp_f32( - arm_linear_interp_instance_f32 * S, - float32_t x) - { - - float32_t y; - float32_t x0, x1; /* Nearest input values */ - float32_t y0, y1; /* Nearest output values */ - float32_t xSpacing = S->xSpacing; /* spacing between input values */ - int32_t i; /* Index variable */ - float32_t *pYData = S->pYData; /* pointer to output table */ - - /* Calculation of index */ - i = (x - S->x1) / xSpacing; - - if(i < 0) - { - /* Iniatilize output for below specified range as least output value of table */ - y = pYData[0]; - } - /* CHIBIOS FIX BEGIN */ - else if(i >= (int32_t)S->nValues) - /* CHIBIOS FIX END */ - { - /* Iniatilize output for above specified range as last output value of table */ - y = pYData[S->nValues - 1]; - } - else - { - /* Calculation of nearest input values */ - x0 = S->x1 + i * xSpacing; - x1 = S->x1 + (i + 1) * xSpacing; - - /* Read of nearest output values */ - y0 = pYData[i]; - y1 = pYData[i + 1]; - - /* Calculation of output */ - y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); - - } - - /* returns output value */ - return (y); - } - - /** - * - * @brief Process function for the Q31 Linear Interpolation Function. - * @param[in] *pYData pointer to Q31 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - - - __STATIC_INLINE q31_t arm_linear_interp_q31( - q31_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q31_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20); - /* CHIBIOS FIX BEGIN */ - if(index >= ((int32_t)nValues - 1)) - /* CHIBIOS FIX END */ - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else - { - - /* 20 bits for the fractional part */ - /* shift left by 11 to keep fract in 1.31 format */ - fract = (x & 0x000FFFFF) << 11; - - /* Read two nearest output values from the index in 1.31(q31) format */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract) and y is in 2.30 format */ - y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); - - /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ - y += ((q31_t) (((q63_t) y1 * fract) >> 32)); - - /* Convert y to 1.31 format */ - return (y << 1u); - - } - - } - - /** - * - * @brief Process function for the Q15 Linear Interpolation Function. - * @param[in] *pYData pointer to Q15 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - - - __STATIC_INLINE q15_t arm_linear_interp_q15( - q15_t * pYData, - q31_t x, - uint32_t nValues) - { - q63_t y; /* output */ - q15_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20u); - - /* CHIBIOS FIX BEGIN */ - if(index >= ((int32_t)nValues - 1)) - /* CHIBIOS FIX END */ - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract) and y is in 13.35 format */ - y = ((q63_t) y0 * (0xFFFFF - fract)); - - /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ - y += ((q63_t) y1 * (fract)); - - /* convert y to 1.15 format */ - return (y >> 20); - } - - - } - - /** - * - * @brief Process function for the Q7 Linear Interpolation Function. - * @param[in] *pYData pointer to Q7 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - */ - - - __STATIC_INLINE q7_t arm_linear_interp_q7( - q7_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q7_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20u); - - /* CHIBIOS FIX BEGIN */ - if(index >= ((int32_t)nValues - 1)) - /* CHIBIOS FIX END */ - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else - { - - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index and are in 1.7(q7) format */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ - y = ((y0 * (0xFFFFF - fract))); - - /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ - y += (y1 * fract); - - /* convert y to 1.7(q7) format */ - return (y >> 20u); - - } - - } - /** - * @} end of LinearInterpolate group - */ - - /** - * @brief Fast approximation to the trigonometric sine function for floating-point data. - * @param[in] x input value in radians. - * @return sin(x). - */ - - float32_t arm_sin_f32( - float32_t x); - - /** - * @brief Fast approximation to the trigonometric sine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - - q31_t arm_sin_q31( - q31_t x); - - /** - * @brief Fast approximation to the trigonometric sine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - - q15_t arm_sin_q15( - q15_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for floating-point data. - * @param[in] x input value in radians. - * @return cos(x). - */ - - float32_t arm_cos_f32( - float32_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - - q31_t arm_cos_q31( - q31_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - - q15_t arm_cos_q15( - q15_t x); - - - /** - * @ingroup groupFastMath - */ - - - /** - * @defgroup SQRT Square Root - * - * Computes the square root of a number. - * There are separate functions for Q15, Q31, and floating-point data types. - * The square root function is computed using the Newton-Raphson algorithm. - * This is an iterative algorithm of the form: - * 
-   *      x1 = x0 - f(x0)/f'(x0)
-   *
- * where x1 is the current estimate, - * x0 is the previous estimate and - * f'(x0) is the derivative of f() evaluated at x0. - * For the square root function, the algorithm reduces to: - * 
-   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   *
- */ - - - /** - * @addtogroup SQRT - * @{ - */ - - /** - * @brief Floating-point square root function. - * @param[in] in input value. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - - __STATIC_INLINE arm_status arm_sqrt_f32( - float32_t in, - float32_t * pOut) - { - if(in > 0) - { - -// #if __FPU_USED - #if (__FPU_USED == 1) && defined ( __CC_ARM ) - *pOut = __sqrtf(in); - #elif (__FPU_USED == 1) && defined ( __TMS_740 ) - *pOut = __builtin_sqrtf(in); - #else - *pOut = sqrtf(in); - #endif - - return (ARM_MATH_SUCCESS); - } - else - { - *pOut = 0.0f; - return (ARM_MATH_ARGUMENT_ERROR); - } - - } - - - /** - * @brief Q31 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q31( - q31_t in, - q31_t * pOut); - - /** - * @brief Q15 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q15( - q15_t in, - q15_t * pOut); - - /** - * @} end of SQRT group - */ - - - - - - - /** - * @brief floating-point Circular write function. - */ - - __STATIC_INLINE void arm_circularWrite_f32( - int32_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const int32_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief floating-point Circular Read function. - */ - __STATIC_INLINE void arm_circularRead_f32( - int32_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - int32_t * dst, - int32_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (int32_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - /** - * @brief Q15 Circular write function. - */ - - __STATIC_INLINE void arm_circularWrite_q15( - q15_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q15_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief Q15 Circular Read function. - */ - __STATIC_INLINE void arm_circularRead_q15( - q15_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q15_t * dst, - q15_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q15_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update wOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q7 Circular write function. - */ - - __STATIC_INLINE void arm_circularWrite_q7( - q7_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q7_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief Q7 Circular Read function. - */ - __STATIC_INLINE void arm_circularRead_q7( - q7_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q7_t * dst, - q7_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q7_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Sum of the squares of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Sum of the squares of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Sum of the squares of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q15( - q15_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Sum of the squares of the elements of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q7( - q7_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Mean value of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_mean_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult); - - /** - * @brief Mean value of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Mean value of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Mean value of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Variance of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Variance of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Variance of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_q15( - q15_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Root Mean Square of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Root Mean Square of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Root Mean Square of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Standard deviation of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Standard deviation of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Standard deviation of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Floating-point complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t numSamples, - q31_t * realResult, - q31_t * imagResult); - - /** - * @brief Q31 complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t numSamples, - q63_t * realResult, - q63_t * imagResult); - - /** - * @brief Floating-point complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t numSamples, - float32_t * realResult, - float32_t * imagResult); - - /** - * @brief Q15 complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_q15( - q15_t * pSrcCmplx, - q15_t * pSrcReal, - q15_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Q31 complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_q31( - q31_t * pSrcCmplx, - q31_t * pSrcReal, - q31_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Floating-point complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_f32( - float32_t * pSrcCmplx, - float32_t * pSrcReal, - float32_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Minimum value of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *result is output pointer - * @param[in] index is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * result, - uint32_t * index); - - /** - * @brief Minimum value of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[in] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - /** - * @brief Minimum value of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[out] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - void arm_min_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - /** - * @brief Minimum value of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[out] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q7 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q15 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q31 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a floating-point vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - /** - * @brief Q15 complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Floating-point complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Converts the elements of the floating-point vector to Q31 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q31 output vector - * @param[in] blockSize length of the input vector - * @return none. - */ - void arm_float_to_q31( - float32_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the floating-point vector to Q15 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q15 output vector - * @param[in] blockSize length of the input vector - * @return none - */ - void arm_float_to_q15( - float32_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the floating-point vector to Q7 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q7 output vector - * @param[in] blockSize length of the input vector - * @return none - */ - void arm_float_to_q7( - float32_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q15 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_q15( - q31_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the Q31 vector to Q7 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_q7( - q31_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the Q15 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_float( - q15_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q31 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_q31( - q15_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q7 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_q7( - q15_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup BilinearInterpolate Bilinear Interpolation - * - * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. - * The underlying function f(x, y) is sampled on a regular grid and the interpolation process - * determines values between the grid points. - * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. - * Bilinear interpolation is often used in image processing to rescale images. - * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. - * - * Algorithm - * \par - * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. - * For floating-point, the instance structure is defined as: - * 
-   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   *
- * - * \par - * where numRows specifies the number of rows in the table; - * numCols specifies the number of columns in the table; - * and pData points to an array of size numRows*numCols values. - * The data table pTable is organized in row order and the supplied data values fall on integer indexes. - * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. - * - * \par - * Let (x, y) specify the desired interpolation point. Then define: - * 
-   *     XF = floor(x)
-   *     YF = floor(y)
-   *
- * \par - * The interpolated output point is computed as: - * 
-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   *
- * Note that the coordinates (x, y) contain integer and fractional components. - * The integer components specify which portion of the table to use while the - * fractional components control the interpolation processor. - * - * \par - * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. - */ - - /** - * @addtogroup BilinearInterpolate - * @{ - */ - - /** - * - * @brief Floating-point bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate. - * @param[in] Y interpolation coordinate. - * @return out interpolated value. - */ - - - __STATIC_INLINE float32_t arm_bilinear_interp_f32( - const arm_bilinear_interp_instance_f32 * S, - float32_t X, - float32_t Y) - { - float32_t out; - float32_t f00, f01, f10, f11; - float32_t *pData = S->pData; - int32_t xIndex, yIndex, index; - float32_t xdiff, ydiff; - float32_t b1, b2, b3, b4; - - xIndex = (int32_t) X; - yIndex = (int32_t) Y; - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 - || yIndex > (S->numCols - 1)) - { - return (0); - } - - /* Calculation of index for two nearest points in X-direction */ - index = (xIndex - 1) + (yIndex - 1) * S->numCols; - - - /* Read two nearest points in X-direction */ - f00 = pData[index]; - f01 = pData[index + 1]; - - /* Calculation of index for two nearest points in Y-direction */ - index = (xIndex - 1) + (yIndex) * S->numCols; - - - /* Read two nearest points in Y-direction */ - f10 = pData[index]; - f11 = pData[index + 1]; - - /* Calculation of intermediate values */ - b1 = f00; - b2 = f01 - f00; - b3 = f10 - f00; - b4 = f00 - f01 - f10 + f11; - - /* Calculation of fractional part in X */ - xdiff = X - xIndex; - - /* Calculation of fractional part in Y */ - ydiff = Y - yIndex; - - /* Calculation of bi-linear interpolated output */ - out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; - - /* return to application */ - return (out); - - } - - /** - * - * @brief Q31 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - __STATIC_INLINE q31_t arm_bilinear_interp_q31( - arm_bilinear_interp_instance_q31 * S, - q31_t X, - q31_t Y) - { - q31_t out; /* Temporary output */ - q31_t acc = 0; /* output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q31_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q31_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20u); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20u); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* shift left xfract by 11 to keep 1.31 format */ - xfract = (X & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - /* 20 bits for the fractional part */ - /* shift left yfract by 11 to keep 1.31 format */ - yfract = (Y & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ - out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); - acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); - - /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); - - /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* Convert acc to 1.31(q31) format */ - return (acc << 2u); - - } - - /** - * @brief Q15 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - __STATIC_INLINE q15_t arm_bilinear_interp_q15( - arm_bilinear_interp_instance_q15 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q15_t x1, x2, y1, y2; /* Nearest output values */ - q31_t xfract, yfract; /* X, Y fractional parts */ - int32_t rI, cI; /* Row and column indices */ - q15_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ - - /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ - /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ - out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); - acc = ((q63_t) out * (0xFFFFF - yfract)); - - /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); - acc += ((q63_t) out * (xfract)); - - /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* acc is in 13.51 format and down shift acc by 36 times */ - /* Convert out to 1.15 format */ - return (acc >> 36); - - } - - /** - * @brief Q7 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - __STATIC_INLINE q7_t arm_bilinear_interp_q7( - arm_bilinear_interp_instance_q7 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q7_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q7_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ - out = ((x1 * (0xFFFFF - xfract))); - acc = (((q63_t) out * (0xFFFFF - yfract))); - - /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ - out = ((x2 * (0xFFFFF - yfract))); - acc += (((q63_t) out * (xfract))); - - /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y1 * (0xFFFFF - xfract))); - acc += (((q63_t) out * (yfract))); - - /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y2 * (yfract))); - acc += (((q63_t) out * (xfract))); - - /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ - return (acc >> 40); - - } - - /** - * @} end of BilinearInterpolate group - */ - - - - - - -#ifdef __cplusplus -} -#endif - - -#endif /* _ARM_MATH_H */ - - -/** - * - * End of file. - */ diff --git a/firmware/chibios/os/ports/common/ARMCMx/CMSIS/include/core_cm0.h b/firmware/chibios/os/ports/common/ARMCMx/CMSIS/include/core_cm0.h deleted file mode 100644 index 19bad5ebeb..0000000000 --- a/firmware/chibios/os/ports/common/ARMCMx/CMSIS/include/core_cm0.h +++ /dev/null @@ -1,667 +0,0 @@ -/**************************************************************************//** - * @file core_cm0.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V3.01 - * @date 13. March 2012 - * - * @note - * Copyright (C) 2009-2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM0_H_GENERIC -#define __CORE_CM0_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M0 - @{ - */ - -/* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ - __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#endif /* __CORE_CM0_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0_H_DEPENDANT -#define __CORE_CM0_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0_REV - #define __CM0_REV 0x0000 - #warning "__CM0_REV not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M0 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) - are only accessible over DAP and not via processor. Therefore - they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } - else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ - else { - return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#endif /* __CORE_CM0_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/firmware/chibios/os/ports/common/ARMCMx/CMSIS/include/core_cm0plus.h b/firmware/chibios/os/ports/common/ARMCMx/CMSIS/include/core_cm0plus.h deleted file mode 100644 index aa20e6879f..0000000000 --- a/firmware/chibios/os/ports/common/ARMCMx/CMSIS/include/core_cm0plus.h +++ /dev/null @@ -1,778 +0,0 @@ -/**************************************************************************//** - * @file core_cm0plus.h - * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File - * @version V3.01 - * @date 22. March 2012 - * - * @note - * Copyright (C) 2009-2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM0PLUS_H_GENERIC -#define __CORE_CM0PLUS_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex-M0+ - @{ - */ - -/* CMSIS CM0P definitions */ -#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM0PLUS_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ - __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#endif /* __CORE_CM0PLUS_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0PLUS_H_DEPENDANT -#define __CORE_CM0PLUS_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0PLUS_REV - #define __CM0PLUS_REV 0x0000 - #warning "__CM0PLUS_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0 - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex-M0+ */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if (__VTOR_PRESENT == 1) - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if (__VTOR_PRESENT == 1) -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) - are only accessible over DAP and not via processor. Therefore - they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0+ Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } - else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0+ system interrupts */ - else { - return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#endif /* __CORE_CM0PLUS_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/firmware/chibios/os/ports/common/ARMCMx/CMSIS/include/core_cm3.h b/firmware/chibios/os/ports/common/ARMCMx/CMSIS/include/core_cm3.h deleted file mode 100644 index 0173893fbd..0000000000 --- a/firmware/chibios/os/ports/common/ARMCMx/CMSIS/include/core_cm3.h +++ /dev/null @@ -1,1612 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V3.01 - * @date 22. March 2012 - * - * @note - * Copyright (C) 2009-2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M3 - @{ - */ - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI__VFP_SUPPORT____ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200 - #warning "__CM3_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M3 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#if (__CM3_REV < 0x0201) /* core r2p1 */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#else -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/firmware/chibios/os/ports/common/ARMCMx/CMSIS/include/core_cm4.h b/firmware/chibios/os/ports/common/ARMCMx/CMSIS/include/core_cm4.h deleted file mode 100644 index a965537402..0000000000 --- a/firmware/chibios/os/ports/common/ARMCMx/CMSIS/include/core_cm4.h +++ /dev/null @@ -1,1757 +0,0 @@ -/**************************************************************************//** - * @file core_cm4.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V3.01 - * @date 22. March 2012 - * - * @note - * Copyright (C) 2009-2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM4_H_GENERIC -#define __CORE_CM4_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M4 - @{ - */ - -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ - __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x04) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ -#include /* Compiler specific SIMD Intrinsics */ - -#endif /* __CORE_CM4_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM4_H_DEPENDANT -#define __CORE_CM4_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM4_REV - #define __CM4_REV 0x0000 - #warning "__CM4_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0 - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M4 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register */ -#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register */ -#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register */ -#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ -/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ - NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_CM4_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/firmware/chibios/os/ports/common/ARMCMx/CMSIS/include/core_cm4_simd.h b/firmware/chibios/os/ports/common/ARMCMx/CMSIS/include/core_cm4_simd.h deleted file mode 100644 index 3bc7906152..0000000000 --- a/firmware/chibios/os/ports/common/ARMCMx/CMSIS/include/core_cm4_simd.h +++ /dev/null @@ -1,649 +0,0 @@ -/**************************************************************************//** - * @file core_cm4_simd.h - * @brief CMSIS Cortex-M4 SIMD Header File - * @version V3.01 - * @date 06. March 2012 - * - * @note - * Copyright (C) 2010-2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM4_SIMD_H -#define __CORE_CM4_SIMD_H - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -#include - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -#include - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SMLALD(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -#define __SMLALDX(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SMLSLD(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -#define __SMLSLDX(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -/* not yet supported */ -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - -#endif - -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CORE_CM4_SIMD_H */ - -#ifdef __cplusplus -} -#endif diff --git a/firmware/chibios/os/ports/common/ARMCMx/CMSIS/include/core_cmFunc.h b/firmware/chibios/os/ports/common/ARMCMx/CMSIS/include/core_cmFunc.h deleted file mode 100644 index 31f35f001d..0000000000 --- a/firmware/chibios/os/ports/common/ARMCMx/CMSIS/include/core_cmFunc.h +++ /dev/null @@ -1,620 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V3.01 - * @date 06. March 2012 - * - * @note - * Copyright (C) 2009-2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief Enable IRQ Interrupts - - This function enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i"); -} - - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i"); -} - - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) ); -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f"); -} - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f"); -} - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) ); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); -/* CHIBIOS FIX BEGIN */ -#else - (void)fpscr; -/* CHIBIOS FIX END */ -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -#endif /* __CORE_CMFUNC_H */ diff --git a/firmware/chibios/os/ports/common/ARMCMx/CMSIS/include/core_cmInstr.h b/firmware/chibios/os/ports/common/ARMCMx/CMSIS/include/core_cmInstr.h deleted file mode 100644 index 597e64df04..0000000000 --- a/firmware/chibios/os/ports/common/ARMCMx/CMSIS/include/core_cmInstr.h +++ /dev/null @@ -1,618 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V3.01 - * @date 06. March 2012 - * - * @note - * Copyright (C) 2009-2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __rbit - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#define __CLREX __clrex - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - -#endif /* (__CORTEX_M >= 0x03) */ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ - uint32_t result; - - __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - - __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) ); - return(op1); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint8_t result; - - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint16_t result; - - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) -{ - uint8_t result; - - __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/firmware/chibios/os/ports/common/ARMCMx/CMSIS/readme.txt b/firmware/chibios/os/ports/common/ARMCMx/CMSIS/readme.txt deleted file mode 100644 index 06ab1ae1a8..0000000000 --- a/firmware/chibios/os/ports/common/ARMCMx/CMSIS/readme.txt +++ /dev/null @@ -1,6 +0,0 @@ -CMSIS is Copyright (C) 2011 ARM Limited. All rights reserved. - -This directory contains only part of the CMSIS package. If you need the whole -package please download it from: - -http://www.onarm.com diff --git a/firmware/chibios/os/ports/common/ARMCMx/nvic.c b/firmware/chibios/os/ports/common/ARMCMx/nvic.c deleted file mode 100644 index 15ef4a03ab..0000000000 --- a/firmware/chibios/os/ports/common/ARMCMx/nvic.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file common/ARMCMx/nvic.c - * @brief Cortex-Mx NVIC support code. - * - * @addtogroup COMMON_ARMCMx_NVIC - * @{ - */ - -#include "ch.h" -#include "nvic.h" - -/** - * @brief Sets the priority of an interrupt handler and enables it. - * @note The parameters are not tested for correctness. - * - * @param[in] n the interrupt number - * @param[in] prio the interrupt priority mask - */ -void nvicEnableVector(uint32_t n, uint32_t prio) { - unsigned sh = (n & 3) << 3; - - NVIC_IPR(n >> 2) = (NVIC_IPR(n >> 2) & ~(0xFF << sh)) | (prio << sh); - NVIC_ICPR(n >> 5) = 1 << (n & 0x1F); - NVIC_ISER(n >> 5) = 1 << (n & 0x1F); -} - -/** - * @brief Disables an interrupt handler. - * @note The parameters are not tested for correctness. - * - * @param[in] n the interrupt number - */ -void nvicDisableVector(uint32_t n) { - unsigned sh = (n & 3) << 3; - - NVIC_ICER(n >> 5) = 1 << (n & 0x1F); - NVIC_IPR(n >> 2) = NVIC_IPR(n >> 2) & ~(0xFF << sh); -} - -/** - * @brief Changes the priority of a system handler. - * @note The parameters are not tested for correctness. - * - * @param[in] handler the system handler number - * @param[in] prio the system handler priority mask - */ -void nvicSetSystemHandlerPriority(uint32_t handler, uint32_t prio) { - unsigned sh = (handler & 3) * 8; - - SCB_SHPR(handler >> 2) = (SCB_SHPR(handler >> 2) & - ~(0xFF << sh)) | (prio << sh); -} - -/** @} */ diff --git a/firmware/chibios/os/ports/common/ARMCMx/nvic.h b/firmware/chibios/os/ports/common/ARMCMx/nvic.h deleted file mode 100644 index 3419bc457b..0000000000 --- a/firmware/chibios/os/ports/common/ARMCMx/nvic.h +++ /dev/null @@ -1,300 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file common/ARMCMx/nvic.h - * @brief Cortex-Mx NVIC support macros and structures. - * - * @addtogroup COMMON_ARMCMx_NVIC - * @{ - */ - -#ifndef _NVIC_H_ -#define _NVIC_H_ - -/** - * @name System vector numbers - * @{ - */ -#define HANDLER_MEM_MANAGE 0 /**< MEM MANAGE vector id. */ -#define HANDLER_BUS_FAULT 1 /**< BUS FAULT vector id. */ -#define HANDLER_USAGE_FAULT 2 /**< USAGE FAULT vector id. */ -#define HANDLER_RESERVED_3 3 -#define HANDLER_RESERVED_4 4 -#define HANDLER_RESERVED_5 5 -#define HANDLER_RESERVED_6 6 -#define HANDLER_SVCALL 7 /**< SVCALL vector id. */ -#define HANDLER_DEBUG_MONITOR 8 /**< DEBUG MONITOR vector id. */ -#define HANDLER_RESERVED_9 9 -#define HANDLER_PENDSV 10 /**< PENDSV vector id. */ -#define HANDLER_SYSTICK 11 /**< SYS TCK vector id. */ -/** @} */ - -typedef volatile uint8_t IOREG8; /**< 8 bits I/O register type. */ -typedef volatile uint32_t IOREG32; /**< 32 bits I/O register type. */ - -/** - * @brief NVIC ITCR register. - */ -#define NVIC_ITCR (*((IOREG32 *)0xE000E004U)) - -/** - * @brief Structure representing the SYSTICK I/O space. - */ -typedef struct { - IOREG32 CSR; - IOREG32 RVR; - IOREG32 CVR; - IOREG32 CBVR; -} CMx_ST; - -/** - * @brief SYSTICK peripheral base address. - */ -#define STBase ((CMx_ST *)0xE000E010U) -#define ST_CSR (STBase->CSR) -#define ST_RVR (STBase->RVR) -#define ST_CVR (STBase->CVR) -#define ST_CBVR (STBase->CBVR) - -#define CSR_ENABLE_MASK (0x1U << 0) -#define ENABLE_OFF_BITS (0U << 0) -#define ENABLE_ON_BITS (1U << 0) -#define CSR_TICKINT_MASK (0x1U << 1) -#define TICKINT_DISABLED_BITS (0U << 1) -#define TICKINT_ENABLED_BITS (1U << 1) -#define CSR_CLKSOURCE_MASK (0x1U << 2) -#define CLKSOURCE_EXT_BITS (0U << 2) -#define CLKSOURCE_CORE_BITS (1U << 2) -#define CSR_COUNTFLAG_MASK (0x1U << 16) - -#define RVR_RELOAD_MASK (0xFFFFFFU << 0) - -#define CVR_CURRENT_MASK (0xFFFFFFU << 0) - -#define CBVR_TENMS_MASK (0xFFFFFFU << 0) -#define CBVR_SKEW_MASK (0x1U << 30) -#define CBVR_NOREF_MASK (0x1U << 31) - -/** - * @brief Structure representing the NVIC I/O space. - */ -typedef struct { - IOREG32 ISER[8]; - IOREG32 unused1[24]; - IOREG32 ICER[8]; - IOREG32 unused2[24]; - IOREG32 ISPR[8]; - IOREG32 unused3[24]; - IOREG32 ICPR[8]; - IOREG32 unused4[24]; - IOREG32 IABR[8]; - IOREG32 unused5[56]; - IOREG32 IPR[60]; - IOREG32 unused6[644]; - IOREG32 STIR; -} CMx_NVIC; - -/** - * @brief NVIC peripheral base address. - */ -#define NVICBase ((CMx_NVIC *)0xE000E100U) -#define NVIC_ISER(n) (NVICBase->ISER[n]) -#define NVIC_ICER(n) (NVICBase->ICER[n]) -#define NVIC_ISPR(n) (NVICBase->ISPR[n]) -#define NVIC_ICPR(n) (NVICBase->ICPR[n]) -#define NVIC_IABR(n) (NVICBase->IABR[n]) -#define NVIC_IPR(n) (NVICBase->IPR[n]) -#define NVIC_STIR (NVICBase->STIR) - -/** - * @brief Structure representing the System Control Block I/O space. - */ -typedef struct { - IOREG32 CPUID; - IOREG32 ICSR; - IOREG32 VTOR; - IOREG32 AIRCR; - IOREG32 SCR; - IOREG32 CCR; - IOREG32 SHPR[3]; - IOREG32 SHCSR; - IOREG32 CFSR; - IOREG32 HFSR; - IOREG32 DFSR; - IOREG32 MMFAR; - IOREG32 BFAR; - IOREG32 AFSR; - IOREG32 PFR[2]; - IOREG32 DFR; - IOREG32 ADR; - IOREG32 MMFR[4]; - IOREG32 SAR[5]; - IOREG32 unused1[5]; - IOREG32 CPACR; -} CMx_SCB; - -/** - * @brief SCB peripheral base address. - */ -#define SCBBase ((CMx_SCB *)0xE000ED00U) -#define SCB_CPUID (SCBBase->CPUID) -#define SCB_ICSR (SCBBase->ICSR) -#define SCB_VTOR (SCBBase->VTOR) -#define SCB_AIRCR (SCBBase->AIRCR) -#define SCB_SCR (SCBBase->SCR) -#define SCB_CCR (SCBBase->CCR) -#define SCB_SHPR(n) (SCBBase->SHPR[n]) -#define SCB_SHCSR (SCBBase->SHCSR) -#define SCB_CFSR (SCBBase->CFSR) -#define SCB_HFSR (SCBBase->HFSR) -#define SCB_DFSR (SCBBase->DFSR) -#define SCB_MMFAR (SCBBase->MMFAR) -#define SCB_BFAR (SCBBase->BFAR) -#define SCB_AFSR (SCBBase->AFSR) -#define SCB_PFR(n) (SCBBase->PFR[n]) -#define SCB_DFR (SCBBase->DFR) -#define SCB_ADR (SCBBase->ADR) -#define SCB_MMFR(n) (SCBBase->MMFR[n]) -#define SCB_SAR(n) (SCBBase->SAR[n]) -#define SCB_CPACR (SCBBase->CPACR) - -#define ICSR_VECTACTIVE_MASK (0x1FFU << 0) -#define ICSR_RETTOBASE (0x1U << 11) -#define ICSR_VECTPENDING_MASK (0x1FFU << 12) -#define ICSR_ISRPENDING (0x1U << 22) -#define ICSR_ISRPREEMPT (0x1U << 23) -#define ICSR_PENDSTCLR (0x1U << 25) -#define ICSR_PENDSTSET (0x1U << 26) -#define ICSR_PENDSVCLR (0x1U << 27) -#define ICSR_PENDSVSET (0x1U << 28) -#define ICSR_NMIPENDSET (0x1U << 31) - -#define AIRCR_VECTKEY 0x05FA0000U -#define AIRCR_PRIGROUP_MASK (0x7U << 8) -#define AIRCR_PRIGROUP(n) ((n) << 8) - -/** - * @brief Structure representing the FPU I/O space. - */ -typedef struct { - IOREG32 unused1[1]; - IOREG32 FPCCR; - IOREG32 FPCAR; - IOREG32 FPDSCR; - IOREG32 MVFR0; - IOREG32 MVFR1; -} CMx_FPU; - -/** - * @brief FPU peripheral base address. - */ -#define FPUBase ((CMx_FPU *)0xE000EF30U) -#define SCB_FPCCR (FPUBase->FPCCR) -#define SCB_FPCAR (FPUBase->FPCAR) -#define SCB_FPDSCR (FPUBase->FPDSCR) -#define SCB_MVFR0 (FPUBase->MVFR0) -#define SCB_MVFR1 (FPUBase->MVFR1) - -#define FPCCR_ASPEN (0x1U << 31) -#define FPCCR_LSPEN (0x1U << 30) -#define FPCCR_MONRDY (0x1U << 8) -#define FPCCR_BFRDY (0x1U << 6) -#define FPCCR_MMRDY (0x1U << 5) -#define FPCCR_HFRDY (0x1U << 4) -#define FPCCR_THREAD (0x1U << 3) -#define FPCCR_USER (0x1U << 1) -#define FPCCR_LSPACT (0x1U << 0) - -#define FPDSCR_AHP (0x1U << 26) -#define FPDSCR_DN (0x1U << 25) -#define FPDSCR_FZ (0x1U << 24) -#define FPDSCR_RMODE(n) ((n##U) << 22) - -/** - * @brief Structure representing the SCS I/O space. - */ -typedef struct { - IOREG32 DHCSR; - IOREG32 DCRSR; - IOREG32 DCRDR; - IOREG32 DEMCR; -} CMx_SCS; - -/** - * @brief SCS peripheral base address. - */ -#define SCSBase ((CMx_SCS *)0xE000EDF0U) -#define SCS_DHCSR (SCSBase->DHCSR) -#define SCS_DCRSR (SCSBase->DCRSR) -#define SCS_DCRDR (SCSBase->DCRDR) -#define SCS_DEMCR (SCSBase->DEMCR) - -#define SCS_DEMCR_TRCENA (0x1U << 24) - -/** - * @brief Structure representing the DWT I/O space. - */ -typedef struct { - IOREG32 CTRL; - IOREG32 CYCCNT; - IOREG32 CPICNT; - IOREG32 EXCCNT; - IOREG32 SLEEPCNT; - IOREG32 LSUCNT; - IOREG32 FOLDCNT; - IOREG32 PCSR; -} CMx_DWT; - -/** - * @brief DWT peripheral base address. - */ -#define DWTBase ((CMx_DWT *)0xE0001000U) -#define DWT_CTRL (DWTBase->CTRL) -#define DWT_CYCCNT (DWTBase->CYCCNT) -#define DWT_CPICNT (DWTBase->CPICNT) -#define DWT_EXCCNT (DWTBase->EXCCNT) -#define DWT_SLEEPCNT (DWTBase->SLEEPCNT) -#define DWT_LSUCNT (DWTBase->LSUCNT) -#define DWT_FOLDCNT (DWTBase->FOLDCNT) -#define DWT_PCSR (DWTBase->PCSR) - -#define DWT_CTRL_CYCCNTENA (0x1U << 0) - -#ifdef __cplusplus -extern "C" { -#endif - void nvicEnableVector(uint32_t n, uint32_t prio); - void nvicDisableVector(uint32_t n); - void nvicSetSystemHandlerPriority(uint32_t handler, uint32_t prio); -#ifdef __cplusplus -} -#endif - -#endif /* _NVIC_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/various/chprintf.c b/firmware/chibios/os/various/chprintf.c deleted file mode 100644 index af19e6da74..0000000000 --- a/firmware/chibios/os/various/chprintf.c +++ /dev/null @@ -1,286 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - Concepts and parts of this file have been contributed by Fabio Utzig, - chvprintf() added by Brent Roman. - */ - -/** - * @file chprintf.c - * @brief Mini printf-like functionality. - * - * @addtogroup chprintf - * @{ - */ - -#include "ch.h" -#include "chprintf.h" - -#define MAX_FILLER 11 -/** - * That's out default %f precision here. Two digits should be fine? - * That's important on the lcd screen - */ -#define FLOAT_PRECISION 100 -static char *long_to_string_with_divisor(char *p, - long num, - unsigned radix, - long divisor) { - int i; - char *q; - long l, ll; - - l = num; - if (divisor == 0) { - ll = num; - } else { - ll = divisor; - } - - q = p + MAX_FILLER; - do { - i = (int)(l % radix); - i += '0'; - if (i > '9') - i += 'A' - '0' - 10; - *--q = i; - l /= radix; - } while ((ll /= radix) != 0); - - i = (int)(p + MAX_FILLER - q); - do - *p++ = *q++; - while (--i); - - return p; -} - -static char *ltoa(char *p, long num, unsigned radix) { - - return long_to_string_with_divisor(p, num, radix, 0); -} - -#if CHPRINTF_USE_FLOAT -char *ftoa(char *p, double num, unsigned long precision) { - if (num < 0) { - *p++ = '-'; - return ftoa(p, -num, precision); - } - long l; - if (isnan(num)) { - *p++ = 'N'; - *p++ = 'a'; - *p++ = 'N'; - return p; - } - - if (precision == 0) - precision = FLOAT_PRECISION; - - l = (long)num; - p = long_to_string_with_divisor(p, l, 10, 0); - *p++ = '.'; - l = (long)((num - l) * precision); - return long_to_string_with_divisor(p, l, 10, precision / 10); -} -#endif - -#include "error_handling.h" -int getRemainingStack(Thread *otp); - -/** - * @brief System formatted output function. - * @details This function implements a minimal @p vprintf()-like functionality - * with output on a @p BaseSequentialStream. - * The general parameters format is: %[-][width|*][.precision|*][l|L]p. - * The following parameter types (p) are supported: - * - x hexadecimal integer. - * - X hexadecimal long. - * - o octal integer. - * - O octal long. - * - d decimal signed integer. - * - D decimal signed long. - * - u decimal unsigned integer. - * - U decimal unsigned long. - * - c character. - * - s string. - * . - * - * @param[in] chp pointer to a @p BaseSequentialStream implementing object - * @param[in] fmt formatting string - * @param[in] ap list of parameters - * - * @api - */ -void chvprintf(BaseSequentialStream *chp, const char *fmt, va_list ap) { - char *p, *s, c, filler; - int i, precision, width; - bool_t is_long, left_align; - long l; -#if CHPRINTF_USE_FLOAT - float f; - char tmpbuf[2*MAX_FILLER + 1]; -#else - char tmpbuf[MAX_FILLER + 1]; -#endif - - efiAssertVoid(getRemainingStack(chThdSelf()) > 64, "lowstck#1c"); - - - while (TRUE) { - c = *fmt++; - if (c == 0) - return; - if (c != '%') { - chSequentialStreamPut(chp, (uint8_t)c); - continue; - } - // we are here if c == '%' meaning we have a control sequence - p = tmpbuf; - s = tmpbuf; - left_align = FALSE; - if (*fmt == '-') { - fmt++; - left_align = TRUE; - } - filler = ' '; - if ((*fmt == '.') || (*fmt == '0')) { - fmt++; - filler = '0'; - } - width = 0; - while (TRUE) { - c = *fmt++; - if (c >= '0' && c <= '9') - c -= '0'; - else if (c == '*') - c = va_arg(ap, int); - else - break; - width = width * 10 + c; - } - precision = 0; - if (c == '.') { - while (TRUE) { - c = *fmt++; - if (c >= '0' && c <= '9') - c -= '0'; - else if (c == '*') - c = va_arg(ap, int); - else - break; - precision *= 10; - precision += c; - } - } - /* Long modifier.*/ - if (c == 'l' || c == 'L') { - is_long = TRUE; - if (*fmt) - c = *fmt++; - } - else - is_long = (c >= 'A') && (c <= 'Z'); - - /* Command decoding.*/ - switch (c) { - case 'c': - filler = ' '; - *p++ = va_arg(ap, int); - break; - case 's': - filler = ' '; - if ((s = va_arg(ap, char *)) == 0) - s = "(null)"; - if (precision == 0) - precision = 32767; - for (p = s; *p && (--precision >= 0); p++) - ; - break; - case 'D': - case 'd': - case 'I': - case 'i': - if (is_long) - l = va_arg(ap, long); - else - l = va_arg(ap, int); - if (l < 0) { - *p++ = '-'; - l = -l; - } - p = ltoa(p, l, 10); - break; -#if CHPRINTF_USE_FLOAT - case 'f': - f = (float) va_arg(ap, double); - if (f < 0) { - *p++ = '-'; - f = -f; - } - p = ftoa(p, f, precision); - break; -#endif - case 'X': - case 'x': - c = 16; - goto unsigned_common; - case 'U': - case 'u': - c = 10; - goto unsigned_common; - case 'O': - case 'o': - c = 8; -unsigned_common: - if (is_long) - l = va_arg(ap, unsigned long); - else - l = va_arg(ap, unsigned int); - p = ltoa(p, l, c); - break; - default: - *p++ = c; - break; - } - i = (int)(p - s); - if ((width -= i) < 0) - width = 0; - if (left_align == FALSE) - width = -width; - if (width < 0) { - if (*s == '-' && filler == '0') { - chSequentialStreamPut(chp, (uint8_t)*s++); - i--; - } - do { - chSequentialStreamPut(chp, (uint8_t)filler); - } while (++width != 0); - } - if (i > 0) { - chSequentialStreamWrite(chp, (uint8_t*)s, i); - } - s += i; - - while (width) { - chSequentialStreamPut(chp, (uint8_t)filler); - width--; - } - } -} - -/** @} */ diff --git a/firmware/chibios/os/various/chprintf.h b/firmware/chibios/os/various/chprintf.h deleted file mode 100644 index 050616eff3..0000000000 --- a/firmware/chibios/os/various/chprintf.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file chprintf.h - * @brief Mini printf-like functionality. - * - * @addtogroup chprintf - * @{ - */ - -#ifndef _CHPRINTF_H_ -#define _CHPRINTF_H_ - -#include -#include - -/** - * @brief Float type support. - */ -#if !defined(CHPRINTF_USE_FLOAT) || defined(__DOXYGEN__) -#define CHPRINTF_USE_FLOAT FALSE -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void chvprintf(BaseSequentialStream *chp, const char *fmt, va_list ap); - char *ftoa(char *p, double num, unsigned long precision); -#ifdef __cplusplus -} -#endif - -/** - * @brief System formatted output function. - * @details This function implements a minimal @p printf() like functionality - * with output on a @p BaseSequentialStream. - * The general parameters format is: %[-][width|*][.precision|*][l|L]p. - * The following parameter types (p) are supported: - * - x hexadecimal integer. - * - X hexadecimal long. - * - o octal integer. - * - O octal long. - * - d decimal signed integer. - * - D decimal signed long. - * - u decimal unsigned integer. - * - U decimal unsigned long. - * - c character. - * - s string. - * . - * - * @param[in] chp pointer to a @p BaseSequentialStream implementing object - * @param[in] fmt formatting string - * - * @api - */ -static inline void chprintf(BaseSequentialStream *chp, const char *fmt, ...) { - va_list ap; - - va_start(ap, fmt); - chvprintf(chp, fmt, ap); - va_end(ap); -} - -#endif /* _CHPRINTF_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/various/chrtclib.c b/firmware/chibios/os/various/chrtclib.c deleted file mode 100644 index b374847156..0000000000 --- a/firmware/chibios/os/various/chrtclib.c +++ /dev/null @@ -1,376 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Concepts and parts of this file have been contributed by Uladzimir Pylinsky - aka barthess. - */ - -/** - * @file chrtclib.c - * @brief RTC time conversion utilities code. - * - * @addtogroup chrtclib - * @{ - */ - -#include - -#include "ch.h" -#include "hal.h" - -#include "chrtclib.h" - -#if HAL_USE_RTC || defined(__DOXYGEN__) - -#if (defined(STM32F4XX) || defined(STM32F2XX) || defined(STM32L1XX) || \ - defined(STM32F30X) || defined(STM32F37X) || \ - defined(STM32F1XX) || defined(STM32F10X_MD) || defined(STM32F10X_LD) || \ - defined(STM32F10X_HD) || defined(STM32F10X_CL) || defined(STM32F0XX) || \ - defined(LPC122X) || defined(__DOXYGEN__)) -#if STM32_RTC_IS_CALENDAR -/** - * @brief Converts from STM32 BCD to canonicalized time format. - * - * @param[out] timp pointer to a @p tm structure as defined in time.h - * @param[in] timespec pointer to a @p RTCTime structure - * - * @notapi - */ -static void stm32_rtc_bcd2tm(struct tm *timp, RTCTime *timespec) { - uint32_t tv_time = timespec->tv_time; - uint32_t tv_date = timespec->tv_date; - -#if CH_DBG_ENABLE_CHECKS - timp->tm_isdst = 0; - timp->tm_wday = 0; - timp->tm_mday = 0; - timp->tm_yday = 0; - timp->tm_mon = 0; - timp->tm_year = 0; - timp->tm_sec = 0; - timp->tm_min = 0; - timp->tm_hour = 0; -#endif - - timp->tm_isdst = -1; - - timp->tm_wday = (tv_date & RTC_DR_WDU) >> RTC_DR_WDU_OFFSET; - if (timp->tm_wday == 7) - timp->tm_wday = 0; - - timp->tm_mday = (tv_date & RTC_DR_DU) >> RTC_DR_DU_OFFSET; - timp->tm_mday += ((tv_date & RTC_DR_DT) >> RTC_DR_DT_OFFSET) * 10; - - timp->tm_mon = (tv_date & RTC_DR_MU) >> RTC_DR_MU_OFFSET; - timp->tm_mon += ((tv_date & RTC_DR_MT) >> RTC_DR_MT_OFFSET) * 10; - timp->tm_mon -= 1; - - timp->tm_year = (tv_date & RTC_DR_YU) >> RTC_DR_YU_OFFSET; - timp->tm_year += ((tv_date & RTC_DR_YT) >> RTC_DR_YT_OFFSET) * 10; - timp->tm_year += 2000 - 1900; - - timp->tm_sec = (tv_time & RTC_TR_SU) >> RTC_TR_SU_OFFSET; - timp->tm_sec += ((tv_time & RTC_TR_ST) >> RTC_TR_ST_OFFSET) * 10; - - timp->tm_min = (tv_time & RTC_TR_MNU) >> RTC_TR_MNU_OFFSET; - timp->tm_min += ((tv_time & RTC_TR_MNT) >> RTC_TR_MNT_OFFSET) * 10; - - timp->tm_hour = (tv_time & RTC_TR_HU) >> RTC_TR_HU_OFFSET; - timp->tm_hour += ((tv_time & RTC_TR_HT) >> RTC_TR_HT_OFFSET) * 10; - timp->tm_hour += 12 * ((tv_time & RTC_TR_PM) >> RTC_TR_PM_OFFSET); -} - -/** - * @brief Converts from canonicalized to STM32 BCD time format. - * - * @param[in] timp pointer to a @p tm structure as defined in time.h - * @param[out] timespec pointer to a @p RTCTime structure - * - * @notapi - */ -static void stm32_rtc_tm2bcd(struct tm *timp, RTCTime *timespec) { - uint32_t v = 0; - - timespec->tv_date = 0; - timespec->tv_time = 0; - - v = timp->tm_year - 100; - timespec->tv_date |= ((v / 10) << RTC_DR_YT_OFFSET) & RTC_DR_YT; - timespec->tv_date |= (v % 10) << RTC_DR_YU_OFFSET; - - if (timp->tm_wday == 0) - v = 7; - else - v = timp->tm_wday; - timespec->tv_date |= (v << RTC_DR_WDU_OFFSET) & RTC_DR_WDU; - - v = timp->tm_mon + 1; - timespec->tv_date |= ((v / 10) << RTC_DR_MT_OFFSET) & RTC_DR_MT; - timespec->tv_date |= (v % 10) << RTC_DR_MU_OFFSET; - - v = timp->tm_mday; - timespec->tv_date |= ((v / 10) << RTC_DR_DT_OFFSET) & RTC_DR_DT; - timespec->tv_date |= (v % 10) << RTC_DR_DU_OFFSET; - - v = timp->tm_hour; - timespec->tv_time |= ((v / 10) << RTC_TR_HT_OFFSET) & RTC_TR_HT; - timespec->tv_time |= (v % 10) << RTC_TR_HU_OFFSET; - - v = timp->tm_min; - timespec->tv_time |= ((v / 10) << RTC_TR_MNT_OFFSET) & RTC_TR_MNT; - timespec->tv_time |= (v % 10) << RTC_TR_MNU_OFFSET; - - v = timp->tm_sec; - timespec->tv_time |= ((v / 10) << RTC_TR_ST_OFFSET) & RTC_TR_ST; - timespec->tv_time |= (v % 10) << RTC_TR_SU_OFFSET; -} - -/** - * @brief Gets raw time from RTC and converts it to canonicalized format. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[out] timp pointer to a @p tm structure as defined in time.h - * - * @api - */ -void rtcGetTimeTm(RTCDriver *rtcp, struct tm *timp) { -#if STM32_RTC_HAS_SUBSECONDS - RTCTime timespec = {0,0,FALSE,0}; -#else - RTCTime timespec = {0,0,FALSE}; -#endif - - rtcGetTime(rtcp, ×pec); - stm32_rtc_bcd2tm(timp, ×pec); -} - -/** - * @brief Sets RTC time. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[out] timp pointer to a @p tm structure as defined in time.h - * - * @api - */ -void rtcSetTimeTm(RTCDriver *rtcp, struct tm *timp) { -#if STM32_RTC_HAS_SUBSECONDS - RTCTime timespec = {0,0,FALSE,0}; -#else - RTCTime timespec = {0,0,FALSE}; -#endif - - stm32_rtc_tm2bcd(timp, ×pec); - rtcSetTime(rtcp, ×pec); -} - -/** - * @brief Gets raw time from RTC and converts it to unix format. - * - * @param[in] rtcp pointer to RTC driver structure - * @return Unix time value in seconds. - * - * @api - */ -time_t rtcGetTimeUnixSec(RTCDriver *rtcp) { -#if STM32_RTC_HAS_SUBSECONDS - RTCTime timespec = {0,0,FALSE,0}; -#else - RTCTime timespec = {0,0,FALSE}; -#endif - struct tm timp; - - rtcGetTime(rtcp, ×pec); - stm32_rtc_bcd2tm(&timp, ×pec); - - return mktime(&timp); -} - -/** - * @brief Sets RTC time. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[in] tv_sec time specification - * @return Unix time value in seconds. - * - * @api - */ -void rtcSetTimeUnixSec(RTCDriver *rtcp, time_t tv_sec) { -#if STM32_RTC_HAS_SUBSECONDS - RTCTime timespec = {0,0,FALSE,0}; -#else - RTCTime timespec = {0,0,FALSE}; -#endif - struct tm timp; - -#if defined __GNUC__ - localtime_r(&tv_sec, &timp); -#else - struct tm *t = localtime(&tv_sec); - memcpy(&timp, t, sizeof(struct tm)); -#endif - stm32_rtc_tm2bcd(&timp, ×pec); - rtcSetTime(rtcp, ×pec); -} - -/** - * @brief Gets raw time from RTC and converts it to unix format. - * - * @param[in] rtcp pointer to RTC driver structure - * @return Unix time value in microseconds. - * - * @api - */ -uint64_t rtcGetTimeUnixUsec(RTCDriver *rtcp) { -#if STM32_RTC_HAS_SUBSECONDS - uint64_t result = 0; - RTCTime timespec = {0,0,FALSE,0}; - struct tm timp; - - rtcGetTime(rtcp, ×pec); - stm32_rtc_bcd2tm(&timp, ×pec); - - result = (uint64_t)mktime(&timp) * 1000000; - return result + timespec.tv_msec * 1000; -#else - return (uint64_t)rtcGetTimeUnixSec(rtcp) * 1000000; -#endif -} - -#else /* STM32_RTC_IS_CALENDAR */ -/** - * @brief Gets raw time from RTC and converts it to canonicalized format. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[out] timp pointer to a @p tm structure as defined in time.h - * - * @api - */ -void rtcGetTimeTm(RTCDriver *rtcp, struct tm *timp) { - RTCTime timespec = {0}; - - rtcGetTime(rtcp, ×pec); -#if defined __GNUC__ - localtime_r((time_t *)&(timespec.tv_sec), timp); -#else - { - struct tm *t = localtime((time_t *)&(timespec.tv_sec)); - memcpy(&timp, t, sizeof(struct tm)); - } -#endif -} - -/** - * @brief Sets RTC time. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[out] timp pointer to a @p tm structure as defined in time.h - * - * @api - */ -void rtcSetTimeTm(RTCDriver *rtcp, struct tm *timp) { - RTCTime timespec = {0}; - - timespec.tv_sec = mktime(timp); -#if !defined(LPC122X) - timespec.tv_msec = 0; -#endif - rtcSetTime(rtcp, ×pec); -} - -/** - * @brief Gets raw time from RTC and converts it to unix format. - * - * @param[in] rtcp pointer to RTC driver structure - * @return Unix time value in seconds. - * - * @api - */ -time_t rtcGetTimeUnixSec(RTCDriver *rtcp) { - RTCTime timespec = {0}; - - rtcGetTime(rtcp, ×pec); - return timespec.tv_sec; -} - -/** - * @brief Sets RTC time. - * - * @param[in] rtcp pointer to RTC driver structure - * @param[in] tv_sec time specification - * @return Unix time value in seconds. - * - * @api - */ -void rtcSetTimeUnixSec(RTCDriver *rtcp, time_t tv_sec) { - RTCTime timespec = {0}; - - timespec.tv_sec = tv_sec; -#if !defined(LPC122X) - timespec.tv_msec = 0; -#endif - rtcSetTime(rtcp, ×pec); -} - -/** - * @brief Gets raw time from RTC and converts it to unix format. - * - * @param[in] rtcp pointer to RTC driver structure - * @return Unix time value in microseconds. - * - * @api - */ -uint64_t rtcGetTimeUnixUsec(RTCDriver *rtcp) { -#if STM32_RTC_HAS_SUBSECONDS - uint64_t result = 0; - RTCTime timespec = {0,0}; - - rtcGetTime(rtcp, ×pec); - result = (uint64_t)timespec.tv_sec * 1000000; - return result + timespec.tv_msec * 1000; -#else - return (uint64_t)rtcGetTimeUnixSec(rtcp) * 1000000; -#endif -} - -/** - * @brief Get current time in format suitable for usage in FatFS. - * - * @param[in] rtcp pointer to RTC driver structure - * @return FAT time value. - * - * @api - */ -uint32_t rtcGetTimeFatFromCounter(RTCDriver *rtcp) { - uint32_t fattime; - struct tm timp; - - rtcGetTimeTm(rtcp, &timp); - - fattime = (timp.tm_sec) >> 1; - fattime |= (timp.tm_min) << 5; - fattime |= (timp.tm_hour) << 11; - fattime |= (timp.tm_mday) << 16; - fattime |= (timp.tm_mon + 1) << 21; - fattime |= (timp.tm_year - 80) << 25; - - return fattime; -} -#endif /* STM32_RTC_IS_CALENDAR */ -#endif /* (defined(STM32F4XX) || defined(STM32F2XX) || defined(STM32L1XX) || defined(STM32F1XX)) */ - -#endif /* HAL_USE_RTC */ - -/** @} */ diff --git a/firmware/chibios/os/various/chrtclib.h b/firmware/chibios/os/various/chrtclib.h deleted file mode 100644 index 7761110416..0000000000 --- a/firmware/chibios/os/various/chrtclib.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Concepts and parts of this file have been contributed by Uladzimir Pylinsky - aka barthess. - */ - -/** - * @file chrtclib.h - * @brief RTC time conversion utilities header. - * - * @addtogroup chrtclib - * @{ - */ - -#ifndef CHRTCLIB_H_ -#define CHRTCLIB_H_ - -#include - -#if HAL_USE_RTC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif -#if !STM32_RTC_IS_CALENDAR - uint32_t rtcGetTimeFat(RTCDriver *rtcp); -#endif - void rtcGetTimeTm(RTCDriver *rtcp, struct tm *timp); - void rtcSetTimeTm(RTCDriver *rtcp, struct tm *timp); - time_t rtcGetTimeUnixSec(RTCDriver *rtcp); - uint64_t rtcGetTimeUnixUsec(RTCDriver *rtcp); - void rtcSetTimeUnixSec(RTCDriver *rtcp, time_t tv_sec); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_RTC */ - -#endif /* CHRTCLIB_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/various/cpp_wrappers/ch.cpp b/firmware/chibios/os/various/cpp_wrappers/ch.cpp deleted file mode 100644 index 56e1b49d1d..0000000000 --- a/firmware/chibios/os/various/cpp_wrappers/ch.cpp +++ /dev/null @@ -1,866 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/** - * @file ch.cpp - * @brief C++ wrapper code. - * - * @addtogroup cpp_library - * @{ - */ - -#include "ch.hpp" - -namespace chibios_rt { - - /*------------------------------------------------------------------------* - * chibios_rt::System * - *------------------------------------------------------------------------*/ - void System::init(void) { - - chSysInit(); - } - - void System::lock(void) { - - chSysLock(); - } - - void System::unlock(void) { - - chSysUnlock(); - } - - void System::lockFromIsr(void) { - - chSysLockFromIsr(); - } - - void System::unlockFromIsr(void) { - - chSysUnlockFromIsr(); - } - - systime_t System::getTime(void) { - - return chTimeNow(); - } - - bool System::isTimeWithin(systime_t start, systime_t end) { - - return (bool)chTimeIsWithin(start, end); - } - - /*------------------------------------------------------------------------* - * chibios_rt::Core * - *------------------------------------------------------------------------*/ - void *Core::alloc(size_t size) { - - return chCoreAlloc(size); - } - - void *Core::allocI(size_t size) { - - return chCoreAllocI(size); - } - - size_t Core::getStatus(void) { - - return chCoreStatus(); - } - - /*------------------------------------------------------------------------* - * chibios_rt::Timer * - *------------------------------------------------------------------------*/ - void Timer::setI(systime_t time, vtfunc_t vtfunc, void *par) { - - chVTSetI(&timer_ref, time, vtfunc, par); - } - - void Timer::resetI() { - - if (chVTIsArmedI(&timer_ref)) - chVTResetI(&timer_ref); - } - - bool Timer::isArmedI(void) { - - return (bool)chVTIsArmedI(&timer_ref); - } - - /*------------------------------------------------------------------------* - * chibios_rt::ThreadReference * - *------------------------------------------------------------------------*/ - - void ThreadReference::stop(void) { - - chDbgPanic("invoked unimplemented method stop()"); - } - - msg_t ThreadReference::suspend(void) { - msg_t msg; - - chSysLock(); - - chDbgAssert(thread_ref != NULL, - "ThreadReference, #1", - "already referenced"); - - thread_ref = chThdSelf(); - chSchGoSleepS(THD_STATE_SUSPENDED); - msg = thread_ref->p_u.rdymsg; - - chSysUnlock(); - return msg; - } - - msg_t ThreadReference::suspendS(void) { - - chDbgAssert(thread_ref == NULL, - "ThreadReference, #2", - "already referenced"); - - thread_ref = chThdSelf(); - chSchGoSleepS(THD_STATE_SUSPENDED); - return thread_ref->p_u.rdymsg; - } - - void ThreadReference::resume(msg_t msg) { - - chSysLock() - - chDbgAssert(thread_ref != NULL, - "ThreadReference, #3", - "not referenced"); - - if (thread_ref) { - Thread *tp = thread_ref; - thread_ref = NULL; - chSchWakeupS(tp, msg); - } - - chSysUnlock(); - } - - void ThreadReference::resumeI(msg_t msg) { - - chDbgAssert(thread_ref != NULL, - "ThreadReference, #4", - "not referenced"); - - if (thread_ref) { - Thread *tp = thread_ref; - thread_ref = NULL; - tp->p_msg = msg; - chSchReadyI(tp); - } - } - - void ThreadReference::requestTerminate(void) { - - chDbgAssert(thread_ref != NULL, - "ThreadReference, #5", - "not referenced"); - - chThdTerminate(thread_ref); - } - -#if CH_USE_WAITEXIT - msg_t ThreadReference::wait(void) { - - chDbgAssert(thread_ref != NULL, - "ThreadReference, #6", - "not referenced"); - - msg_t msg = chThdWait(thread_ref); - thread_ref = NULL; - return msg; - } -#endif /* CH_USE_WAITEXIT */ - -#if CH_USE_MESSAGES - msg_t ThreadReference::sendMessage(msg_t msg) { - - chDbgAssert(thread_ref != NULL, - "ThreadReference, #7", - "not referenced"); - - return chMsgSend(thread_ref, msg); - } - - bool ThreadReference::isPendingMessage(void) { - - chDbgAssert(thread_ref != NULL, - "ThreadReference, #7", - "not referenced"); - - return (bool)chMsgIsPendingI(thread_ref); - } - - msg_t ThreadReference::getMessage(void) { - - chDbgAssert(thread_ref != NULL, - "ThreadReference, #8", - "not referenced"); - - return chMsgGet(thread_ref); - } - - void ThreadReference::releaseMessage(msg_t msg) { - - chDbgAssert(thread_ref != NULL, - "ThreadReference, #9", - "not referenced"); - - chMsgRelease(thread_ref, msg); - } -#endif /* CH_USE_MESSAGES */ - -#if CH_USE_EVENTS - void ThreadReference::signalEvents(eventmask_t mask) { - - chDbgAssert(thread_ref != NULL, - "ThreadReference, #10", - "not referenced"); - - chEvtSignal(thread_ref, mask); - } - - void ThreadReference::signalEventsI(eventmask_t mask) { - - chDbgAssert(thread_ref != NULL, - "ThreadReference, #11", - "not referenced"); - - chEvtSignalI(thread_ref, mask); - } -#endif /* CH_USE_EVENTS */ - -#if CH_USE_DYNAMIC -#endif /* CH_USE_DYNAMIC */ - - /*------------------------------------------------------------------------* - * chibios_rt::BaseThread * - *------------------------------------------------------------------------*/ - BaseThread::BaseThread() : ThreadReference(NULL) { - - } - - msg_t BaseThread::main(void) { - - return 0; - } - - ThreadReference BaseThread::start(tprio_t prio) { - - (void)prio; - - return *this; - }; - - msg_t _thd_start(void *arg) { - - return ((BaseThread *)arg)->main(); - } - - void BaseThread::setName(const char *tname) { - - chRegSetThreadName(tname); - } - - tprio_t BaseThread::setPriority(tprio_t newprio) { - - return chThdSetPriority(newprio); - } - - void BaseThread::exit(msg_t msg) { - - chThdExit(msg); - } - - void BaseThread::exitS(msg_t msg) { - - chThdExitS(msg); - } - - bool BaseThread::shouldTerminate(void) { - - return (bool)chThdShouldTerminate(); - } - - void BaseThread::sleep(systime_t interval){ - - chThdSleep(interval); - } - - void BaseThread::sleepUntil(systime_t time) { - - chThdSleepUntil(time); - } - - void BaseThread::yield(void) { - - chThdYield(); - } - -#if CH_USE_MESSAGES - ThreadReference BaseThread::waitMessage(void) { - - ThreadReference tr(chMsgWait()); - return tr; - } -#endif /* CH_USE_MESSAGES */ - -#if CH_USE_EVENTS - eventmask_t BaseThread::getAndClearEvents(eventmask_t mask) { - - return chEvtGetAndClearEvents(mask); - } - - eventmask_t BaseThread::addEvents(eventmask_t mask) { - - return chEvtAddEvents(mask); - } - - eventmask_t BaseThread::waitOneEvent(eventmask_t ewmask) { - - return chEvtWaitOne(ewmask); - } - - eventmask_t BaseThread::waitAnyEvent(eventmask_t ewmask) { - - return chEvtWaitAny(ewmask); - } - - eventmask_t BaseThread::waitAllEvents(eventmask_t ewmask) { - - return chEvtWaitAll(ewmask); - } - -#if CH_USE_EVENTS_TIMEOUT - eventmask_t BaseThread::waitOneEventTimeout(eventmask_t ewmask, - systime_t time) { - - return chEvtWaitOneTimeout(ewmask, time); - } - - eventmask_t BaseThread::waitAnyEventTimeout(eventmask_t ewmask, - systime_t time) { - - return chEvtWaitAnyTimeout(ewmask, time); - } - - eventmask_t BaseThread::waitAllEventsTimeout(eventmask_t ewmask, - systime_t time) { - - return chEvtWaitAllTimeout(ewmask, time); - } -#endif /* CH_USE_EVENTS_TIMEOUT */ - - void BaseThread::dispatchEvents(const evhandler_t handlers[], - eventmask_t mask) { - - chEvtDispatch(handlers, mask); - } -#endif /* CH_USE_EVENTS */ - -#if CH_USE_MUTEXES - void BaseThread::unlockMutex(void) { - - chMtxUnlock(); - } - - void BaseThread::unlockMutexS(void) { - - chMtxUnlockS(); - } - - void BaseThread::unlockAllMutexes(void) { - - chMtxUnlockAll(); - } -#endif /* CH_USE_MUTEXES */ - -#if CH_USE_SEMAPHORES - /*------------------------------------------------------------------------* - * chibios_rt::CounterSemaphore * - *------------------------------------------------------------------------*/ - CounterSemaphore::CounterSemaphore(cnt_t n) { - - chSemInit(&sem, n); - } - - void CounterSemaphore::reset(cnt_t n) { - - chSemReset(&sem, n); - } - - void CounterSemaphore::resetI(cnt_t n) { - - chSemResetI(&sem, n); - } - - msg_t CounterSemaphore::wait(void) { - - return chSemWait(&sem); - } - - msg_t CounterSemaphore::waitS(void) { - - return chSemWaitS(&sem); - } - - msg_t CounterSemaphore::waitTimeout(systime_t time) { - - return chSemWaitTimeout(&sem, time); - } - - msg_t CounterSemaphore::waitTimeoutS(systime_t time) { - - return chSemWaitTimeoutS(&sem, time); - } - - void CounterSemaphore::signal(void) { - - chSemSignal(&sem); - } - - void CounterSemaphore::signalI(void) { - - chSemSignalI(&sem); - } - - void CounterSemaphore::addCounterI(cnt_t n) { - - chSemAddCounterI(&sem, n); - } - - cnt_t CounterSemaphore::getCounterI(void) { - - return chSemGetCounterI(&sem); - } - -#if CH_USE_SEMSW - msg_t CounterSemaphore::signalWait(CounterSemaphore *ssem, - CounterSemaphore *wsem) { - - return chSemSignalWait(&ssem->sem, &wsem->sem); - } -#endif /* CH_USE_SEMSW */ - - /*------------------------------------------------------------------------* - * chibios_rt::BinarySemaphore * - *------------------------------------------------------------------------*/ - BinarySemaphore::BinarySemaphore(bool taken) { - - chBSemInit(&bsem, (bool_t)taken); - } - - msg_t BinarySemaphore::wait(void) { - - return chBSemWait(&bsem); - } - - msg_t BinarySemaphore::waitS(void) { - - return chBSemWaitS(&bsem); - } - - msg_t BinarySemaphore::waitTimeout(systime_t time) { - - return chBSemWaitTimeout(&bsem, time); - } - - msg_t BinarySemaphore::waitTimeoutS(systime_t time) { - - return chBSemWaitTimeoutS(&bsem, time); - } - - void BinarySemaphore::reset(bool taken) { - - chBSemReset(&bsem, (bool_t)taken); - } - - void BinarySemaphore::resetI(bool taken) { - - chBSemResetI(&bsem, (bool_t)taken); - } - - void BinarySemaphore::signal(void) { - - chBSemSignal(&bsem); - } - - void BinarySemaphore::signalI(void) { - - chBSemSignalI(&bsem); - } - - bool BinarySemaphore::getStateI(void) { - - return (bool)chBSemGetStateI(&bsem); - } -#endif /* CH_USE_SEMAPHORES */ - -#if CH_USE_MUTEXES - /*------------------------------------------------------------------------* - * chibios_rt::Mutex * - *------------------------------------------------------------------------*/ - Mutex::Mutex(void) { - - chMtxInit(&mutex); - } - - bool Mutex::tryLock(void) { - - return chMtxTryLock(&mutex); - } - - bool Mutex::tryLockS(void) { - - return chMtxTryLockS(&mutex); - } - - void Mutex::lock(void) { - - chMtxLock(&mutex); - } - - void Mutex::lockS(void) { - - chMtxLockS(&mutex); - } - -#if CH_USE_CONDVARS - /*------------------------------------------------------------------------* - * chibios_rt::CondVar * - *------------------------------------------------------------------------*/ - CondVar::CondVar(void) { - - chCondInit(&condvar); - } - - void CondVar::signal(void) { - - chCondSignal(&condvar); - } - - void CondVar::signalI(void) { - - chCondSignalI(&condvar); - } - - void CondVar::broadcast(void) { - - chCondBroadcast(&condvar); - } - - void CondVar::broadcastI(void) { - - chCondBroadcastI(&condvar); - } - - msg_t CondVar::wait(void) { - - return chCondWait(&condvar); - } - - msg_t CondVar::waitS(void) { - - return chCondWaitS(&condvar); - } - -#if CH_USE_CONDVARS_TIMEOUT - msg_t CondVar::waitTimeout(systime_t time) { - - return chCondWaitTimeout(&condvar, time); - } -#endif /* CH_USE_CONDVARS_TIMEOUT */ -#endif /* CH_USE_CONDVARS */ -#endif /* CH_USE_MUTEXES */ - -#if CH_USE_EVENTS - /*------------------------------------------------------------------------* - * chibios_rt::EvtListener * - *------------------------------------------------------------------------*/ - flagsmask_t EvtListener::getAndClearFlags(void) { - - return chEvtGetAndClearFlags(&ev_listener); - } - - flagsmask_t EvtListener::getAndClearFlagsI(void) { - - return chEvtGetAndClearFlagsI(&ev_listener); - } - - /*------------------------------------------------------------------------* - * chibios_rt::EvtSource * - *------------------------------------------------------------------------*/ - EvtSource::EvtSource(void) { - - chEvtInit(&ev_source); - } - - void EvtSource::registerOne(chibios_rt::EvtListener *elp, - eventid_t eid) { - - chEvtRegister(&ev_source, &elp->ev_listener, eid); - } - - void EvtSource::registerMask(chibios_rt::EvtListener *elp, - eventmask_t emask) { - - chEvtRegisterMask(&ev_source, &elp->ev_listener, emask); - } - - void EvtSource::unregister(chibios_rt::EvtListener *elp) { - - chEvtUnregister(&ev_source, &elp->ev_listener); - } - - void EvtSource::broadcastFlags(flagsmask_t flags) { - - chEvtBroadcastFlags(&ev_source, flags); - } - - void EvtSource::broadcastFlagsI(flagsmask_t flags) { - - chEvtBroadcastFlagsI(&ev_source, flags); - } -#endif /* CH_USE_EVENTS */ - -#if CH_USE_QUEUES - /*------------------------------------------------------------------------* - * chibios_rt::InQueue * - *------------------------------------------------------------------------*/ - InQueue::InQueue(uint8_t *bp, size_t size, qnotify_t infy, void *link) { - - chIQInit(&iq, bp, size, infy, link); - } - - size_t InQueue::getFullI(void) { - - return chIQGetFullI(&iq); - } - - size_t InQueue::getEmptyI(void) { - - return chIQGetEmptyI(&iq); - } - - bool InQueue::isEmptyI(void) { - - return (bool)chIQIsEmptyI(&iq); - } - - bool InQueue::isFullI(void) { - - return (bool)chIQIsFullI(&iq); - } - - void InQueue::resetI(void) { - - chIQResetI(&iq); - } - - msg_t InQueue::putI(uint8_t b) { - - return chIQPutI(&iq, b); - } - - msg_t InQueue::get() { - - return chIQGet(&iq); - } - - msg_t InQueue::getTimeout(systime_t time) { - - return chIQGetTimeout(&iq, time); - } - - size_t InQueue::readTimeout(uint8_t *bp, size_t n, systime_t time) { - - return chIQReadTimeout(&iq, bp, n, time); - } - - /*------------------------------------------------------------------------* - * chibios_rt::OutQueue * - *------------------------------------------------------------------------*/ - OutQueue::OutQueue(uint8_t *bp, size_t size, qnotify_t onfy, void *link) { - - chOQInit(&oq, bp, size, onfy, link); - } - - size_t OutQueue::getFullI(void) { - - return chOQGetFullI(&oq); - } - - size_t OutQueue::getEmptyI(void) { - - return chOQGetEmptyI(&oq); - } - - bool OutQueue::isEmptyI(void) { - - return (bool)chOQIsEmptyI(&oq); - } - - bool OutQueue::isFullI(void) { - - return (bool)chOQIsFullI(&oq); - } - - void OutQueue::resetI(void) { - - chOQResetI(&oq); - } - - msg_t OutQueue::put(uint8_t b) { - - return chOQPut(&oq, b); - } - - msg_t OutQueue::putTimeout(uint8_t b, systime_t time) { - - return chOQPutTimeout(&oq, b, time); - } - - msg_t OutQueue::getI(void) { - - return chOQGetI(&oq); - } - - size_t OutQueue::writeTimeout(const uint8_t *bp, size_t n, - systime_t time) { - - return chOQWriteTimeout(&oq, bp, n, time); - } -#endif /* CH_USE_QUEUES */ - -#if CH_USE_MAILBOXES - /*------------------------------------------------------------------------* - * chibios_rt::Mailbox * - *------------------------------------------------------------------------*/ - Mailbox::Mailbox(msg_t *buf, cnt_t n) { - - chMBInit(&mb, buf, n); - } - - void Mailbox::reset(void) { - - chMBReset(&mb); - } - - msg_t Mailbox::post(msg_t msg, systime_t time) { - - return chMBPost(&mb, msg, time); - } - - msg_t Mailbox::postS(msg_t msg, systime_t time) { - - return chMBPostS(&mb, msg, time); - } - - msg_t Mailbox::postI(msg_t msg) { - - return chMBPostI(&mb, msg); - } - - msg_t Mailbox::postAhead(msg_t msg, systime_t time) { - - return chMBPostAhead(&mb, msg, time); - } - - msg_t Mailbox::postAheadS(msg_t msg, systime_t time) { - - return chMBPostAheadS(&mb, msg, time); - } - - msg_t Mailbox::postAheadI(msg_t msg) { - - return chMBPostAheadI(&mb, msg); - } - - msg_t Mailbox::fetch(msg_t *msgp, systime_t time) { - - return chMBFetch(&mb, msgp, time); - } - - msg_t Mailbox::fetchS(msg_t *msgp, systime_t time) { - - return chMBFetchS(&mb, msgp, time); - } - - msg_t Mailbox::fetchI(msg_t *msgp) { - - return chMBFetchI(&mb, msgp); - } - - cnt_t Mailbox::getFreeCountI(void) { - - return chMBGetFreeCountI(&mb); - } - - cnt_t Mailbox::getUsedCountI(void) { - - return chMBGetUsedCountI(&mb); - } -#endif /* CH_USE_MAILBOXES */ - -#if CH_USE_MEMPOOLS - /*------------------------------------------------------------------------* - * chibios_rt::MemoryPool * - *------------------------------------------------------------------------*/ - MemoryPool::MemoryPool(size_t size, memgetfunc_t provider) { - - chPoolInit(&pool, size, provider); - } - - MemoryPool::MemoryPool(size_t size, memgetfunc_t provider, void* p, size_t n) { - - chPoolInit(&pool, size, provider); - chPoolLoadArray(&pool, p, n); - } - - - void MemoryPool::loadArray(void *p, size_t n) { - - chPoolLoadArray(&pool, p, n); - } - - void *MemoryPool::allocI(void) { - - return chPoolAllocI(&pool); - } - - void *MemoryPool::alloc(void) { - - return chPoolAlloc(&pool); - } - - void MemoryPool::free(void *objp) { - - chPoolFree(&pool, objp); - } - - void MemoryPool::freeI(void *objp) { - - chPoolFreeI(&pool, objp); - } -#endif /* CH_USE_MEMPOOLS */ -} - -/** @} */ diff --git a/firmware/chibios/os/various/cpp_wrappers/ch.hpp b/firmware/chibios/os/various/cpp_wrappers/ch.hpp deleted file mode 100644 index df4a802e34..0000000000 --- a/firmware/chibios/os/various/cpp_wrappers/ch.hpp +++ /dev/null @@ -1,2282 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file ch.hpp - * @brief C++ wrapper classes and definitions. - * - * @addtogroup cpp_library - * @{ - */ - -#include - -#ifndef _CH_HPP_ -#define _CH_HPP_ - -/** - * @brief ChibiOS kernel-related classes and interfaces. - */ -namespace chibios_rt { - - /*------------------------------------------------------------------------* - * chibios_rt::System * - *------------------------------------------------------------------------*/ - /** - * @brief Class encapsulating the base system functionalities. - */ - class System { - public: - /** - * @brief ChibiOS/RT initialization. - * @details After executing this function the current instructions stream - * becomes the main thread. - * @pre Interrupts must be still disabled when @p chSysInit() is invoked - * and are internally enabled. - * @post The main thread is created with priority @p NORMALPRIO. - * @note This function has special, architecture-dependent, requirements, - * see the notes into the various port reference manuals. - * - * @special - */ - static void init(void); - - /** - * @brief Enters the kernel lock mode. - * - * @special - */ - static void lock(void); - - /** - * @brief Leaves the kernel lock mode. - * - * @special - */ - static void unlock(void); - - /** - * @brief Enters the kernel lock mode from within an interrupt handler. - * @note This API may do nothing on some architectures, it is required - * because on ports that support preemptable interrupt handlers - * it is required to raise the interrupt mask to the same level of - * the system mutual exclusion zone.
- * It is good practice to invoke this API before invoking any I-class - * syscall from an interrupt handler. - * @note This API must be invoked exclusively from interrupt handlers. - * - * @special - */ - static void lockFromIsr(void); - - /** - * @brief Leaves the kernel lock mode from within an interrupt handler. - * - * @note This API may do nothing on some architectures, it is required - * because on ports that support preemptable interrupt handlers - * it is required to raise the interrupt mask to the same level of - * the system mutual exclusion zone.
- * It is good practice to invoke this API after invoking any I-class - * syscall from an interrupt handler. - * @note This API must be invoked exclusively from interrupt handlers. - * - * @special - */ - static void unlockFromIsr(void); - - - /** - * @brief Returns the system time as system ticks. - * @note The system tick time interval is implementation dependent. - * - * @return The system time. - * - * @api - */ - static systime_t getTime(void); - - /** - * @brief Checks if the current system time is within the specified time - * window. - * @note When start==end then the function returns always true because the - * whole time range is specified. - * - * @param[in] start the start of the time window (inclusive) - * @param[in] end the end of the time window (non inclusive) - * @retval true current time within the specified time window. - * @retval false current time not within the specified time window. - * - * @api - */ - static bool isTimeWithin(systime_t start, systime_t end); - }; - - /*------------------------------------------------------------------------* - * chibios_rt::System * - *------------------------------------------------------------------------*/ - /** - * @brief Class encapsulating the base system functionalities. - */ - class Core { - public: - - /** - * @brief Allocates a memory block. - * @details The size of the returned block is aligned to the alignment - * type so it is not possible to allocate less - * than MEM_ALIGN_SIZE. - * - * @param[in] size the size of the block to be allocated - * @return A pointer to the allocated memory block. - * @retval NULL allocation failed, core memory exhausted. - * - * @api - */ - static void *alloc(size_t size); - - /** - * @brief Allocates a memory block. - * @details The size of the returned block is aligned to the alignment - * type so it is not possible to allocate less than - * MEM_ALIGN_SIZE. - * - * @param[in] size the size of the block to be allocated. - * @return A pointer to the allocated memory block. - * @retval NULL allocation failed, core memory exhausted. - * - * @iclass - */ - static void *allocI(size_t size); - - /** - * @brief Core memory status. - * - * @return The size, in bytes, of the free core memory. - * - * @api - */ - static size_t getStatus(void); - }; - - /*------------------------------------------------------------------------* - * chibios_rt::Timer * - *------------------------------------------------------------------------*/ - /** - * @brief Timer class. - */ - class Timer { - public: - /** - * @brief Embedded @p VirtualTimer structure. - */ - ::VirtualTimer timer_ref; - - /** - * @brief Enables a virtual timer. - * @note The associated function is invoked from interrupt context. - * - * @param[in] time the number of ticks before the operation timeouts, - * the special values are handled as follow: - * - @a TIME_INFINITE is allowed but interpreted as a - * normal time specification. - * - @a TIME_IMMEDIATE this value is not allowed. - * . - * @param[in] vtfunc the timer callback function. After invoking the - * callback the timer is disabled and the structure - * can be disposed or reused. - * @param[in] par a parameter that will be passed to the callback - * function - * - * @iclass - */ - void setI(systime_t time, vtfunc_t vtfunc, void *par); - - /** - * @brief Resets the timer, if armed. - * - * @iclass - */ - void resetI(); - - /** - * @brief Returns the timer status. - * - * @retval TRUE The timer is armed. - * @retval FALSE The timer already fired its callback. - * - * @iclass - */ - bool isArmedI(void); - }; - - /*------------------------------------------------------------------------* - * chibios_rt::ThreadReference * - *------------------------------------------------------------------------*/ - /** - * @brief Thread reference class. - * @details This class encapsulates a reference to a system thread. All - * operations involving another thread are performed through - * an object of this type. - */ - class ThreadReference { - public: - /** - * @brief Pointer to the system thread. - */ - ::Thread *thread_ref; - - /** - * @brief Thread reference constructor. - * - * @param[in] tp the target thread. This parameter can be - * @p NULL if the thread is not known at - * creation time. - * - * @init - */ - ThreadReference(Thread *tp) : thread_ref(tp) { - - }; - - /** - * @brief Stops the thread. - * @note The implementation is left to descendant classes and is - * optional. - */ - virtual void stop(void); - - /** - * @brief Suspends the current thread on the reference. - * @details The suspended thread becomes the referenced thread. It is - * possible to use this method only if the thread reference - * was set to @p NULL. - * - * @return The incoming message. - * - * @api - */ - msg_t suspend(void); - - /** - * @brief Suspends the current thread on the reference. - * @details The suspended thread becomes the referenced thread. It is - * possible to use this method only if the thread reference - * was set to @p NULL. - * - * @return The incoming message. - * - * @sclass - */ - msg_t suspendS(void); - - /** - * @brief Resumes the currently referenced thread, if any. - * - * @param[in] msg the wakeup message - * - * @api - */ - void resume(msg_t msg); - - /** - * @brief Resumes the currently referenced thread, if any. - * - * @param[in] msg the wakeup message - * - * @iclass - */ - void resumeI(msg_t msg); - - /** - * @brief Requests a thread termination. - * @pre The target thread must be written to invoke periodically - * @p chThdShouldTerminate() and terminate cleanly if it returns - * @p TRUE. - * @post The specified thread will terminate after detecting the - * termination condition. - * - * @api - */ - void requestTerminate(void); - -#if CH_USE_WAITEXIT || defined(__DOXYGEN__) - /** - * @brief Blocks the execution of the invoking thread until the specified - * thread terminates then the exit code is returned. - * @details This function waits for the specified thread to terminate then - * decrements its reference counter, if the counter reaches zero - * then the thread working area is returned to the proper - * allocator.
- * The memory used by the exited thread is handled in different - * ways depending on the API that spawned the thread: - * - If the thread was spawned by @p chThdCreateStatic() or by - * @p chThdCreateI() then nothing happens and the thread working - * area is not released or modified in any way. This is the - * default, totally static, behavior. - * - If the thread was spawned by @p chThdCreateFromHeap() then - * the working area is returned to the system heap. - * - If the thread was spawned by @p chThdCreateFromMemoryPool() - * then the working area is returned to the owning memory pool. - * . - * @pre The configuration option @p CH_USE_WAITEXIT must be enabled in - * order to use this function. - * @post Enabling @p chThdWait() requires 2-4 (depending on the - * architecture) extra bytes in the @p Thread structure. - * @post After invoking @p chThdWait() the thread pointer becomes - * invalid and must not be used as parameter for further system - * calls. - * @note If @p CH_USE_DYNAMIC is not specified this function just waits - * for the thread termination, no memory allocators are involved. - * - * @return The exit code from the terminated thread. - * - * @api - */ - msg_t wait(void); -#endif /* CH_USE_WAITEXIT */ - -#if CH_USE_MESSAGES || defined(__DOXYGEN__) - /** - * @brief Sends a message to the thread and returns the answer. - * - * @param[in] msg the sent message - * @return The returned message. - * - * @api - */ - msg_t sendMessage(msg_t msg); - - /** - * @brief Returns true if there is at least one message in queue. - * - * @retval true A message is waiting in queue. - * @retval false A message is not waiting in queue. - * - * @api - */ - bool isPendingMessage(void); - - /** - * @brief Returns an enqueued message or @p NULL. - * - * @return The incoming message. - * - * @api - */ - msg_t getMessage(void); - - /** - * @brief Releases the next message in queue with a reply. - * - * @param[in] msg the answer message - * - * @api - */ - void releaseMessage(msg_t msg); -#endif /* CH_USE_MESSAGES */ - -#if CH_USE_EVENTS || defined(__DOXYGEN__) - /** - * @brief Adds a set of event flags directly to specified @p Thread. - * - * @param[in] mask the event flags set to be ORed - * - * @api - */ - void signalEvents(eventmask_t mask); - - /** - * @brief Adds a set of event flags directly to specified @p Thread. - * - * @param[in] mask the event flags set to be ORed - * - * @iclass - */ - void signalEventsI(eventmask_t mask); -#endif /* CH_USE_EVENTS */ - -#if CH_USE_DYNAMIC || defined(__DOXYGEN__) -#endif /* CH_USE_DYNAMIC */ - }; - - /*------------------------------------------------------------------------* - * chibios_rt::BaseThread * - *------------------------------------------------------------------------*/ - /** - * @brief Abstract base class for a ChibiOS/RT thread. - * @details The thread body is the virtual function @p Main(). - */ - class BaseThread : public ThreadReference { - public: - /** - * @brief BaseThread constructor. - * - * @init - */ - BaseThread(void); - - /** - * @brief Thread body function. - * - * @return The exit message. - * - * @api - */ - virtual msg_t main(void); - - /** - * @brief Creates and starts a system thread. - * - * @param[in] prio thread priority - * @return A reference to the created thread with - * reference counter set to one. - * - * @api - */ - virtual ThreadReference start(tprio_t prio); - - /** - * @brief Sets the current thread name. - * @pre This function only stores the pointer to the name if the option - * @p CH_USE_REGISTRY is enabled else no action is performed. - * - * @param[in] tname thread name as a zero terminated string - * - * @api - */ - static void setName(const char *tname); - - /** - * @brief Changes the running thread priority level then reschedules if - * necessary. - * @note The function returns the real thread priority regardless of the - * current priority that could be higher than the real priority - * because the priority inheritance mechanism. - * - * @param[in] newprio the new priority level of the running thread - * @return The old priority level. - * - * @api - */ - static tprio_t setPriority(tprio_t newprio); - - /** - * @brief Terminates the current thread. - * @details The thread goes in the @p THD_STATE_FINAL state holding the - * specified exit status code, other threads can retrieve the - * exit status code by invoking the function @p chThdWait(). - * @post Eventual code after this function will never be executed, - * this function never returns. The compiler has no way to - * know this so do not assume that the compiler would remove - * the dead code. - * - * @param[in] msg thread exit code - * - * @api - */ - static void exit(msg_t msg); - - /** - * @brief Terminates the current thread. - * @details The thread goes in the @p THD_STATE_FINAL state holding the - * specified exit status code, other threads can retrieve the - * exit status code by invoking the function @p chThdWait(). - * @post Eventual code after this function will never be executed, - * this function never returns. The compiler has no way to - * know this so do not assume that the compiler would remove - * the dead code. - * - * @param[in] msg thread exit code - * - * @sclass - */ - static void exitS(msg_t msg); - - /** - * @brief Verifies if the current thread has a termination request - * pending. - * @note Can be invoked in any context. - * - * @retval TRUE termination request pending. - * @retval FALSE termination request not pending. - * - * @special - */ - static bool shouldTerminate(void); - - /** - * @brief Suspends the invoking thread for the specified time. - * - * @param[in] interval the delay in system ticks, the special values are - * handled as follow: - * - @a TIME_INFINITE the thread enters an infinite - * sleep state. - * - @a TIME_IMMEDIATE this value is not allowed. - * . - * - * @api - */ - static void sleep(systime_t interval); - - /** - * @brief Suspends the invoking thread until the system time arrives to - * the specified value. - * - * @param[in] time absolute system time - * - * @api - */ - static void sleepUntil(systime_t time); - - /** - * @brief Yields the time slot. - * @details Yields the CPU control to the next thread in the ready list - * with equal priority, if any. - * - * @api - */ - static void yield(void); - -#if CH_USE_MESSAGES || defined(__DOXYGEN__) - /** - * @brief Waits for a message. - * - * @return The sender thread. - * - * @api - */ - static ThreadReference waitMessage(void); -#endif /* CH_USE_MESSAGES */ - -#if CH_USE_EVENTS || defined(__DOXYGEN__) - /** - * @brief Clears the pending events specified in the mask. - * - * @param[in] mask the events to be cleared - * @return The pending events that were cleared. - * - * @api - */ - static eventmask_t getAndClearEvents(eventmask_t mask); - - /** - * @brief Adds (OR) a set of event flags on the current thread, this is - * @b much faster than using @p chEvtBroadcast() or - * @p chEvtSignal(). - * - * @param[in] mask the event flags to be added - * @return The current pending events mask. - * - * @api - */ - static eventmask_t addEvents(eventmask_t mask); - - /** - * @brief Waits for a single event. - * @details A pending event among those specified in @p ewmask is selected, - * cleared and its mask returned. - * @note One and only one event is served in the function, the one with - * the lowest event id. The function is meant to be invoked into - * a loop in order to serve all the pending events.
- * This means that Event Listeners with a lower event identifier - * have an higher priority. - * - * @param[in] ewmask mask of the events that the function should - * wait for, @p ALL_EVENTS enables all the events - * @return The mask of the lowest id served and cleared - * event. - * - * @api - */ - static eventmask_t waitOneEvent(eventmask_t ewmask); - - /** - * @brief Waits for any of the specified events. - * @details The function waits for any event among those specified in - * @p ewmask to become pending then the events are cleared and - * returned. - * - * @param[in] ewmask mask of the events that the function should - * wait for, @p ALL_EVENTS enables all the events - * @return The mask of the served and cleared events. - * - * @api - */ - static eventmask_t waitAnyEvent(eventmask_t ewmask); - - /** - * @brief Waits for all the specified event flags then clears them. - * @details The function waits for all the events specified in @p ewmask - * to become pending then the events are cleared and returned. - * - * @param[in] ewmask mask of the event ids that the function should - * wait for - * @return The mask of the served and cleared events. - * - * @api - */ - static eventmask_t waitAllEvents(eventmask_t ewmask); - -#if CH_USE_EVENTS_TIMEOUT || defined(__DOXYGEN__) - /** - * @brief Waits for a single event. - * @details A pending event among those specified in @p ewmask is selected, - * cleared and its mask returned. - * @note One and only one event is served in the function, the one with - * the lowest event id. The function is meant to be invoked into - * a loop in order to serve all the pending events.
- * This means that Event Listeners with a lower event identifier - * have an higher priority. - * - * @param[in] ewmask mask of the events that the function should - * wait for, @p ALL_EVENTS enables all the events - * - * @param[in] time the number of ticks before the operation - * timouts - * @return The mask of the lowest id served and cleared - * event. - * @retval 0 if the specified timeout expired. - * - * @api - */ - static eventmask_t waitOneEventTimeout(eventmask_t ewmask, - systime_t time); - - /** - * @brief Waits for any of the specified events. - * @details The function waits for any event among those specified in - * @p ewmask to become pending then the events are cleared and - * returned. - * - * @param[in] ewmask mask of the events that the function should - * wait for, @p ALL_EVENTS enables all the events - * @param[in] time the number of ticks before the operation - * timouts - * @return The mask of the served and cleared events. - * @retval 0 if the specified timeout expired. - * - * @api - */ - static eventmask_t waitAnyEventTimeout(eventmask_t ewmask, - systime_t time); - - /** - * @brief Waits for all the specified event flags then clears them. - * @details The function waits for all the events specified in @p ewmask - * to become pending then the events are cleared and returned. - * - * @param[in] ewmask mask of the event ids that the function should - * wait for - * @param[in] time the number of ticks before the operation - * timouts - * @return The mask of the served and cleared events. - * @retval 0 if the specified timeout expired. - * - * @api - */ - static eventmask_t waitAllEventsTimeout(eventmask_t ewmask, - systime_t time); -#endif /* CH_USE_EVENTS_TIMEOUT */ - - /** - * @brief Invokes the event handlers associated to an event flags mask. - * - * @param[in] mask mask of the event flags to be dispatched - * @param[in] handlers an array of @p evhandler_t. The array must have - * size equal to the number of bits in eventmask_t. - * - * @api - */ - static void dispatchEvents(const evhandler_t handlers[], - eventmask_t mask); -#endif /* CH_USE_EVENTS */ - -#if CH_USE_MUTEXES || defined(__DOXYGEN__) - /** - * @brief Unlocks the next owned mutex in reverse lock order. - * @pre The invoking thread must have at least one owned mutex. - * @post The mutex is unlocked and removed from the per-thread stack of - * owned mutexes. - * - * @return A pointer to the unlocked mutex. - * - * @api - */ - static void unlockMutex(void); - - /** - * @brief Unlocks the next owned mutex in reverse lock order. - * @pre The invoking thread must have at least one owned mutex. - * @post The mutex is unlocked and removed from the per-thread stack of - * owned mutexes. - * @post This function does not reschedule so a call to a rescheduling - * function must be performed before unlocking the kernel. - * - * @return A pointer to the unlocked mutex. - * - * @sclass - */ - static void unlockMutexS(void); - - /** - * @brief Unlocks all the mutexes owned by the invoking thread. - * @post The stack of owned mutexes is emptied and all the found - * mutexes are unlocked. - * @note This function is MUCH MORE efficient than releasing the - * mutexes one by one and not just because the call overhead, - * this function does not have any overhead related to the - * priority inheritance mechanism. - * - * @api - */ - static void unlockAllMutexes(void); -#endif /* CH_USE_MUTEXES */ - }; - - /*------------------------------------------------------------------------* - * chibios_rt::BaseStaticThread * - *------------------------------------------------------------------------*/ - /** - * @brief Static threads template class. - * @details This class introduces static working area allocation. - * - * @param N the working area size for the thread class - */ - template - class BaseStaticThread : public BaseThread { - protected: - WORKING_AREA(wa, N); - - public: - /** - * @brief Thread constructor. - * @details The thread object is initialized but the thread is not - * started here. - * - * @init - */ - BaseStaticThread(void) : BaseThread() { - - } - - /** - * @brief Creates and starts a system thread. - * - * @param[in] prio thread priority - * @return A reference to the created thread with - * reference counter set to one. - * - * @api - */ - virtual ThreadReference start(tprio_t prio) { - msg_t _thd_start(void *arg); - - thread_ref = chThdCreateStatic(wa, sizeof(wa), prio, _thd_start, this); - return *this; - } - }; - -#if CH_USE_SEMAPHORES || defined(__DOXYGEN__) - /*------------------------------------------------------------------------* - * chibios_rt::CounterSemaphore * - *------------------------------------------------------------------------*/ - /** - * @brief Class encapsulating a semaphore. - */ - class CounterSemaphore { - public: - /** - * @brief Embedded @p ::Semaphore structure. - */ - ::Semaphore sem; - - /** - * @brief CounterSemaphore constructor. - * @details The embedded @p ::Semaphore structure is initialized. - * - * @param[in] n the semaphore counter value, must be greater - * or equal to zero - * - * @init - */ - CounterSemaphore(cnt_t n); - - /** - * @brief Performs a reset operation on the semaphore. - * @post After invoking this function all the threads waiting on the - * semaphore, if any, are released and the semaphore counter is - * set to the specified, non negative, value. - * @note The released threads can recognize they were waked up by a - * reset rather than a signal because the @p chSemWait() will - * return @p RDY_RESET instead of @p RDY_OK. - * - * @param[in] n the new value of the semaphore counter. The value - * must be non-negative. - * - * @api - */ - void reset(cnt_t n); - - /** - * @brief Performs a reset operation on the semaphore. - * @post After invoking this function all the threads waiting on the - * semaphore, if any, are released and the semaphore counter is - * set to the specified, non negative, value. - * @post This function does not reschedule so a call to a rescheduling - * function must be performed before unlocking the kernel. Note - * that interrupt handlers always reschedule on exit so an - * explicit reschedule must not be performed in ISRs. - * @note The released threads can recognize they were waked up by a - * reset rather than a signal because the @p chSemWait() will - * return @p RDY_RESET instead of @p RDY_OK. - * - * @param[in] n the new value of the semaphore counter. The value - * must be non-negative. - * - * @iclass - */ - void resetI(cnt_t n); - - /** - * @brief Performs a wait operation on a semaphore. - * - * @return A message specifying how the invoking thread has - * been released from the semaphore. - * @retval RDY_OK if the thread has not stopped on the semaphore or - * the semaphore has been signaled. - * @retval RDY_RESET if the semaphore has been reset using - * @p chSemReset(). - * - * @api - */ - msg_t wait(void); - - /** - * @brief Performs a wait operation on a semaphore. - * - * @return A message specifying how the invoking thread has - * been released from the semaphore. - * @retval RDY_OK if the thread has not stopped on the semaphore or - * the semaphore has been signaled. - * @retval RDY_RESET if the semaphore has been reset using - * @p chSemReset(). - * - * @sclass - */ - msg_t waitS(void); - - /** - * @brief Performs a wait operation on a semaphore with timeout - * specification. - * - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return A message specifying how the invoking thread has - * been released from the semaphore. - * @retval RDY_OK if the thread has not stopped on the semaphore or - * the semaphore has been signaled. - * @retval RDY_RESET if the semaphore has been reset using - * @p chSemReset(). - * @retval RDY_TIMEOUT if the semaphore has not been signaled or reset - * within the specified timeout. - * - * @api - */ - msg_t waitTimeout(systime_t time); - - /** - * @brief Performs a wait operation on a semaphore with timeout - * specification. - * - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return A message specifying how the invoking thread has - * been released from the semaphore. - * @retval RDY_OK if the thread has not stopped on the semaphore or - * the semaphore has been signaled. - * @retval RDY_RESET if the semaphore has been reset using - * @p chSemReset(). - * @retval RDY_TIMEOUT if the semaphore has not been signaled or reset - * within the specified timeout. - * - * @sclass - */ - msg_t waitTimeoutS(systime_t time); - - /** - * @brief Performs a signal operation on a semaphore. - * - * @api - */ - void signal(void); - - /** - * @brief Performs a signal operation on a semaphore. - * @post This function does not reschedule so a call to a rescheduling - * function must be performed before unlocking the kernel. Note - * that interrupt handlers always reschedule on exit so an - * explicit reschedule must not be performed in ISRs. - * - * @iclass - */ - void signalI(void); - - /** - * @brief Adds the specified value to the semaphore counter. - * @post This function does not reschedule so a call to a rescheduling - * function must be performed before unlocking the kernel. Note - * that interrupt handlers always reschedule on exit so an explicit - * reschedule must not be performed in ISRs. - * - * @param[in] n value to be added to the semaphore counter. The - * value must be positive. - * - * @iclass - */ - void addCounterI(cnt_t n); - - /** - * @brief Returns the semaphore counter value. - * - * @return The semaphore counter value. - * - * @iclass - */ - cnt_t getCounterI(void); - -#if CH_USE_SEMSW || defined(__DOXYGEN__) - /** - * @brief Atomic signal and wait operations. - * - * @param[in] ssem @p Semaphore object to be signaled - * @param[in] wsem @p Semaphore object to wait on - * @return A message specifying how the invoking thread - * has been released from the semaphore. - * @retval RDY_OK if the thread has not stopped on the semaphore - * or the semaphore has been signaled. - * @retval RDY_RESET if the semaphore has been reset using - * @p chSemReset(). - * - * @api - */ - static msg_t signalWait(CounterSemaphore *ssem, - CounterSemaphore *wsem); -#endif /* CH_USE_SEMSW */ - }; - /*------------------------------------------------------------------------* - * chibios_rt::BinarySemaphore * - *------------------------------------------------------------------------*/ - /** - * @brief Class encapsulating a binary semaphore. - */ - class BinarySemaphore { - public: - /** - * @brief Embedded @p ::Semaphore structure. - */ - ::BinarySemaphore bsem; - - /** - * @brief BinarySemaphore constructor. - * @details The embedded @p ::BinarySemaphore structure is initialized. - * - * @param[in] taken initial state of the binary semaphore: - * - @a false, the initial state is not taken. - * - @a true, the initial state is taken. - * . - * - * @init - */ - BinarySemaphore(bool taken); - - /** - * @brief Wait operation on the binary semaphore. - * - * @return A message specifying how the invoking thread has - * been released from the semaphore. - * @retval RDY_OK if the binary semaphore has been successfully - * taken. - * @retval RDY_RESET if the binary semaphore has been reset using - * @p bsemReset(). - * - * @api - */ - msg_t wait(void); - - /** - * @brief Wait operation on the binary semaphore. - * - * @return A message specifying how the invoking thread has - * been released from the semaphore. - * @retval RDY_OK if the binary semaphore has been successfully - * taken. - * @retval RDY_RESET if the binary semaphore has been reset using - * @p bsemReset(). - * - * @sclass - */ - msg_t waitS(void); - - /** - * @brief Wait operation on the binary semaphore. - * - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return A message specifying how the invoking thread has - * been released from the semaphore. - * @retval RDY_OK if the binary semaphore has been successfully - * taken. - * @retval RDY_RESET if the binary semaphore has been reset using - * @p bsemReset(). - * @retval RDY_TIMEOUT if the binary semaphore has not been signaled - * or reset within the specified timeout. - * - * @api - */ - msg_t waitTimeout(systime_t time); - - /** - * @brief Wait operation on the binary semaphore. - * - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return A message specifying how the invoking thread has - * been released from the semaphore. - * @retval RDY_OK if the binary semaphore has been successfully - * taken. - * @retval RDY_RESET if the binary semaphore has been reset using - * @p bsemReset(). - * @retval RDY_TIMEOUT if the binary semaphore has not been signaled - * or reset within the specified timeout. - * - * @sclass - */ - msg_t waitTimeoutS(systime_t time); - - /** - * @brief Reset operation on the binary semaphore. - * @note The released threads can recognize they were waked up by a - * reset rather than a signal because the @p bsemWait() will - * return @p RDY_RESET instead of @p RDY_OK. - * - * @param[in] taken new state of the binary semaphore - * - @a FALSE, the new state is not taken. - * - @a TRUE, the new state is taken. - * . - * - * @api - */ - void reset(bool taken); - - /** - * @brief Reset operation on the binary semaphore. - * @note The released threads can recognize they were waked up by a - * reset rather than a signal because the @p bsemWait() will - * return @p RDY_RESET instead of @p RDY_OK. - * @note This function does not reschedule. - * - * @param[in] taken new state of the binary semaphore - * - @a FALSE, the new state is not taken. - * - @a TRUE, the new state is taken. - * . - * - * @iclass - */ - void resetI(bool taken); - - /** - * @brief Performs a signal operation on a binary semaphore. - * - * @api - */ - void signal(void); - - /** - * @brief Performs a signal operation on a binary semaphore. - * @note This function does not reschedule. - * - * @iclass - */ - void signalI(void); - - /** - * @brief Returns the binary semaphore current state. - * - * @return The binary semaphore current state. - * @retval false if the binary semaphore is not taken. - * @retval true if the binary semaphore is taken. - * - * @iclass - */ - bool getStateI(void); -}; -#endif /* CH_USE_SEMAPHORES */ - -#if CH_USE_MUTEXES || defined(__DOXYGEN__) - /*------------------------------------------------------------------------* - * chibios_rt::Mutex * - *------------------------------------------------------------------------*/ - /** - * @brief Class encapsulating a mutex. - */ - class Mutex { - public: - /** - * @brief Embedded @p ::Mutex structure. - */ - ::Mutex mutex; - - /** - * @brief Mutex object constructor. - * @details The embedded @p ::Mutex structure is initialized. - * - * @init - */ - Mutex(void); - - /** - * @brief Tries to lock a mutex. - * @details This function attempts to lock a mutex, if the mutex is already - * locked by another thread then the function exits without - * waiting. - * @post The mutex is locked and inserted in the per-thread stack of - * owned mutexes. - * @note This function does not have any overhead related to the - * priority inheritance mechanism because it does not try to - * enter a sleep state. - * - * @return The operation status. - * @retval TRUE if the mutex has been successfully acquired - * @retval FALSE if the lock attempt failed. - * - * @api - */ - bool tryLock(void); - - /** - * @brief Tries to lock a mutex. - * @details This function attempts to lock a mutex, if the mutex is already - * taken by another thread then the function exits without - * waiting. - * @post The mutex is locked and inserted in the per-thread stack of - * owned mutexes. - * @note This function does not have any overhead related to the - * priority inheritance mechanism because it does not try to - * enter a sleep state. - * - * @return The operation status. - * @retval TRUE if the mutex has been successfully acquired - * @retval FALSE if the lock attempt failed. - * - * @sclass - */ - bool tryLockS(void); - - /** - * @brief Locks the specified mutex. - * @post The mutex is locked and inserted in the per-thread stack of - * owned mutexes. - * - * @api - */ - void lock(void); - - /** - * @brief Locks the specified mutex. - * @post The mutex is locked and inserted in the per-thread stack of - * owned mutexes. - * - * @sclass - */ - void lockS(void); - }; - -#if CH_USE_CONDVARS || defined(__DOXYGEN__) - /*------------------------------------------------------------------------* - * chibios_rt::CondVar * - *------------------------------------------------------------------------*/ - /** - * @brief Class encapsulating a conditional variable. - */ - class CondVar { - public: - /** - * @brief Embedded @p ::CondVar structure. - */ - ::CondVar condvar; - - /** - * @brief CondVar object constructor. - * @details The embedded @p ::CondVar structure is initialized. - * - * @init - */ - CondVar(void); - - /** - * @brief Signals one thread that is waiting on the condition variable. - * - * @api - */ - void signal(void); - - /** - * @brief Signals one thread that is waiting on the condition variable. - * @post This function does not reschedule so a call to a rescheduling - * function must be performed before unlocking the kernel. Note - * that interrupt handlers always reschedule on exit so an - * explicit reschedule must not be performed in ISRs. - * - * @iclass - */ - void signalI(void); - - /** - * @brief Signals all threads that are waiting on the condition variable. - * - * @api - */ - void broadcast(void); - - /** - * @brief Signals all threads that are waiting on the condition variable. - * @post This function does not reschedule so a call to a rescheduling - * function must be performed before unlocking the kernel. Note - * that interrupt handlers always reschedule on exit so an - * explicit reschedule must not be performed in ISRs. - * - * @iclass - */ - void broadcastI(void); - - /** - * @brief Waits on the condition variable releasing the mutex lock. - * @details Releases the currently owned mutex, waits on the condition - * variable, and finally acquires the mutex again. All the - * sequence is performed atomically. - * @pre The invoking thread must have at least one owned mutex. - * - * @return A message specifying how the invoking thread has - * been released from the condition variable. - * @retval RDY_OK if the condvar has been signaled using - * @p chCondSignal(). - * @retval RDY_RESET if the condvar has been signaled using - * @p chCondBroadcast(). - * - * @api - */ - msg_t wait(void); - - /** - * @brief Waits on the condition variable releasing the mutex lock. - * @details Releases the currently owned mutex, waits on the condition - * variable, and finally acquires the mutex again. All the - * sequence is performed atomically. - * @pre The invoking thread must have at least one owned mutex. - * - * @return A message specifying how the invoking thread has - * been released from the condition variable. - * @retval RDY_OK if the condvar has been signaled using - * @p chCondSignal(). - * @retval RDY_RESET if the condvar has been signaled using - * @p chCondBroadcast(). - * - * @sclass - */ - msg_t waitS(void); - -#if CH_USE_CONDVARS_TIMEOUT || defined(__DOXYGEN__) - /** - * @brief Waits on the CondVar while releasing the controlling mutex. - * - * @param[in] time the number of ticks before the operation fails - * @return The wakep mode. - * @retval RDY_OK if the condvar was signaled using - * @p chCondSignal(). - * @retval RDY_RESET if the condvar was signaled using - * @p chCondBroadcast(). - * @retval RDY_TIMEOUT if the condvar was not signaled within the - * specified timeout. - * - * @api - */ - msg_t waitTimeout(systime_t time); -#endif /* CH_USE_CONDVARS_TIMEOUT */ - }; -#endif /* CH_USE_CONDVARS */ -#endif /* CH_USE_MUTEXES */ - -#if CH_USE_EVENTS || defined(__DOXYGEN__) - /*------------------------------------------------------------------------* - * chibios_rt::EvtListener * - *------------------------------------------------------------------------*/ - /** - * @brief Class encapsulating an event listener. - */ - class EvtListener { - public: - /** - * @brief Embedded @p ::EventListener structure. - */ - struct ::EventListener ev_listener; - - /** - * @brief Returns the pending flags from the listener and clears them. - * - * @return The flags added to the listener by the - * associated event source. - * - * @api - */ - flagsmask_t getAndClearFlags(void); - - /** - * @brief Returns the flags associated to an @p EventListener. - * @details The flags are returned and the @p EventListener flags mask is - * cleared. - * - * @return The flags added to the listener by the associated - * event source. - * - * @iclass - */ - flagsmask_t getAndClearFlagsI(void); - }; - - /*------------------------------------------------------------------------* - * chibios_rt::EvtSource * - *------------------------------------------------------------------------*/ - /** - * @brief Class encapsulating an event source. - */ - class EvtSource { - public: - /** - * @brief Embedded @p ::EventSource structure. - */ - struct ::EventSource ev_source; - - /** - * @brief EvtSource object constructor. - * @details The embedded @p ::EventSource structure is initialized. - * - * @init - */ - EvtSource(void); - - /** - * @brief Registers a listener on the event source. - * - * @param[in] elp pointer to the @p EvtListener object - * @param[in] eid numeric identifier assigned to the Event - * Listener - * - * @api - */ - void registerOne(chibios_rt::EvtListener *elp, eventid_t eid); - - /** - * @brief Registers an Event Listener on an Event Source. - * @note Multiple Event Listeners can specify the same bits to be added. - * - * @param[in] elp pointer to the @p EvtListener object - * @param[in] emask the mask of event flags to be pended to the - * thread when the event source is broadcasted - * - * @api - */ - void registerMask(chibios_rt::EvtListener *elp, eventmask_t emask); - - /** - * @brief Unregisters a listener. - * @details The specified listeners is no more signaled by the event - * source. - * - * @param[in] elp the listener to be unregistered - * - * @api - */ - void unregister(chibios_rt::EvtListener *elp); - - /** - * @brief Broadcasts on an event source. - * @details All the listeners registered on the event source are signaled - * and the flags are added to the listener's flags mask. - * - * @param[in] flags the flags set to be added to the listener - * flags mask - * - * @api - */ - void broadcastFlags(flagsmask_t flags); - - /** - * @brief Broadcasts on an event source. - * @details All the listeners registered on the event source are signaled - * and the flags are added to the listener's flags mask. - * - * @param[in] flags the flags set to be added to the listener - * flags mask - * - * @iclass - */ - void broadcastFlagsI(flagsmask_t flags); - }; -#endif /* CH_USE_EVENTS */ - -#if CH_USE_QUEUES || defined(__DOXYGEN__) - /*------------------------------------------------------------------------* - * chibios_rt::InQueue * - *------------------------------------------------------------------------*/ - /** - * @brief Class encapsulating an input queue. - */ - class InQueue { - private: - /** - * @brief Embedded @p ::InputQueue structure. - */ - ::InputQueue iq; - - public: - /** - * @brief InQueue constructor. - * - * @param[in] bp pointer to a memory area allocated as queue buffer - * @param[in] size size of the queue buffer - * @param[in] infy pointer to a callback function that is invoked when - * data is read from the queue. The value can be - * @p NULL. - * @param[in] link application defined pointer - * - * @init - */ - InQueue(uint8_t *bp, size_t size, qnotify_t infy, void *link); - - /** - * @brief Returns the filled space into an input queue. - * - * @return The number of full bytes in the queue. - * @retval 0 if the queue is empty. - * - * @iclass - */ - size_t getFullI(void); - - /** - * @brief Returns the empty space into an input queue. - * - * @return The number of empty bytes in the queue. - * @retval 0 if the queue is full. - * - * @iclass - */ - size_t getEmptyI(void); - - /** - * @brief Evaluates to @p TRUE if the specified input queue is empty. - * - * @return The queue status. - * @retval false if the queue is not empty. - * @retval true if the queue is empty. - * - * @iclass - */ - bool isEmptyI(void); - - /** - * @brief Evaluates to @p TRUE if the specified input queue is full. - * - * @return The queue status. - * @retval FALSE if the queue is not full. - * @retval TRUE if the queue is full. - * - * @iclass - */ - bool isFullI(void); - - /** - * @brief Resets an input queue. - * @details All the data in the input queue is erased and lost, any waiting - * thread is resumed with status @p Q_RESET. - * @note A reset operation can be used by a low level driver in order to - * obtain immediate attention from the high level layers. - * @iclass - */ - void resetI(void); - - /** - * @brief Input queue write. - * @details A byte value is written into the low end of an input queue. - * - * @param[in] b the byte value to be written in the queue - * @return The operation status. - * @retval Q_OK if the operation has been completed with success. - * @retval Q_FULL if the queue is full and the operation cannot be - * completed. - * - * @iclass - */ - msg_t putI(uint8_t b); - - /** - * @brief Input queue read. - * @details This function reads a byte value from an input queue. If the - * queue is empty then the calling thread is suspended until a - * byte arrives in the queue. - * - * @return A byte value from the queue. - * @retval Q_RESET if the queue has been reset. - * - * @api - */ - msg_t get(); - - /** - * @brief Input queue read with timeout. - * @details This function reads a byte value from an input queue. If the - * queue is empty then the calling thread is suspended until a - * byte arrives in the queue or a timeout occurs. - * @note The callback is invoked before reading the character from the - * buffer or before entering the state @p THD_STATE_WTQUEUE. - * - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return A byte value from the queue. - * @retval Q_TIMEOUT if the specified time expired. - * @retval Q_RESET if the queue has been reset. - * - * @api - */ - msg_t getTimeout(systime_t time); - - /** - * @brief Input queue read with timeout. - * @details The function reads data from an input queue into a buffer. The - * operation completes when the specified amount of data has been - * transferred or after the specified timeout or if the queue has - * been reset. - * @note The function is not atomic, if you need atomicity it is - * suggested to use a semaphore or a mutex for mutual exclusion. - * @note The callback is invoked before reading each character from the - * buffer or before entering the state @p THD_STATE_WTQUEUE. - * - * @param[out] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred, the - * value 0 is reserved - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The number of bytes effectively transferred. - * - * @api - */ - size_t readTimeout(uint8_t *bp, size_t n, systime_t time); - }; - - /*------------------------------------------------------------------------* - * chibios_rt::InQueueBuffer * - *------------------------------------------------------------------------*/ - /** - * @brief Template class encapsulating an input queue and its buffer. - * - * @param N size of the input queue - */ - template - class InQueueBuffer : public InQueue { - private: - uint8_t iq_buf[N]; - - public: - /** - * @brief InQueueBuffer constructor. - * - * @param[in] infy input notify callback function - * @param[in] link parameter to be passed to the callback - * - * @init - */ - InQueueBuffer(qnotify_t infy, void *link) : InQueue(iq_buf, N, - infy, link) { - } - }; - - /*------------------------------------------------------------------------* - * chibios_rt::OutQueue * - *------------------------------------------------------------------------*/ - /** - * @brief Class encapsulating an output queue. - */ - class OutQueue { - private: - /** - * @brief Embedded @p ::OutputQueue structure. - */ - ::OutputQueue oq; - - public: - /** - * @brief OutQueue constructor. - * - * @param[in] bp pointer to a memory area allocated as queue buffer - * @param[in] size size of the queue buffer - * @param[in] onfy pointer to a callback function that is invoked when - * data is written to the queue. The value can be - * @p NULL. - * @param[in] link application defined pointer - * - * @init - */ - OutQueue(uint8_t *bp, size_t size, qnotify_t onfy, void *link); - - /** - * @brief Returns the filled space into an output queue. - * - * @return The number of full bytes in the queue. - * @retval 0 if the queue is empty. - * - * @iclass - */ - size_t getFullI(void); - - /** - * @brief Returns the empty space into an output queue. - * - * @return The number of empty bytes in the queue. - * @retval 0 if the queue is full. - * - * @iclass - */ - size_t getEmptyI(void); - - /** - * @brief Evaluates to @p TRUE if the specified output queue is empty. - * - * @return The queue status. - * @retval false if the queue is not empty. - * @retval true if the queue is empty. - * - * @iclass - */ - bool isEmptyI(void); - - /** - * @brief Evaluates to @p TRUE if the specified output queue is full. - * - * @return The queue status. - * @retval FALSE if the queue is not full. - * @retval TRUE if the queue is full. - * - * @iclass - */ - bool isFullI(void); - - /** - * @brief Resets an output queue. - * @details All the data in the output queue is erased and lost, any - * waiting thread is resumed with status @p Q_RESET. - * @note A reset operation can be used by a low level driver in order - * to obtain immediate attention from the high level layers. - * - * @iclass - */ - void resetI(void); - - /** - * @brief Output queue write. - * @details This function writes a byte value to an output queue. If the - * queue is full then the calling thread is suspended until there - * is space in the queue. - * - * @param[in] b the byte value to be written in the queue - * @return The operation status. - * @retval Q_OK if the operation succeeded. - * @retval Q_RESET if the queue has been reset. - * - * @api - */ - msg_t put(uint8_t b); - - /** - * @brief Output queue write with timeout. - * @details This function writes a byte value to an output queue. If the - * queue is full then the calling thread is suspended until there - * is space in the queue or a timeout occurs. - * @note The callback is invoked after writing the character into the - * buffer. - * - * @param[in] b the byte value to be written in the queue - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval Q_OK if the operation succeeded. - * @retval Q_TIMEOUT if the specified time expired. - * @retval Q_RESET if the queue has been reset. - * - * @api - */ - msg_t putTimeout(uint8_t b, systime_t time); - - /** - * @brief Output queue read. - * @details A byte value is read from the low end of an output queue. - * - * @return The byte value from the queue. - * @retval Q_EMPTY if the queue is empty. - * - * @iclass - */ - msg_t getI(void); - - /** - * @brief Output queue write with timeout. - * @details The function writes data from a buffer to an output queue. The - * operation completes when the specified amount of data has been - * transferred or after the specified timeout or if the queue has - * been reset. - * @note The function is not atomic, if you need atomicity it is - * suggested to use a semaphore or a mutex for mutual exclusion. - * @note The callback is invoked after writing each character into the - * buffer. - * - * @param[out] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred, the - * value 0 is reserved - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The number of bytes effectively transferred. - * - * @api - */ - size_t writeTimeout(const uint8_t *bp, size_t n, systime_t time); -}; - - /*------------------------------------------------------------------------* - * chibios_rt::OutQueueBuffer * - *------------------------------------------------------------------------*/ - /** - * @brief Template class encapsulating an output queue and its buffer. - * - * @param N size of the output queue - */ - template - class OutQueueBuffer : public OutQueue { - private: - uint8_t oq_buf[N]; - - public: - /** - * @brief OutQueueBuffer constructor. - * - * @param[in] onfy output notify callback function - * @param[in] link parameter to be passed to the callback - * - * @init - */ - OutQueueBuffer(qnotify_t onfy, void *link) : OutQueue(oq_buf, N, - onfy, link) { - } - }; -#endif /* CH_USE_QUEUES */ - -#if CH_USE_MAILBOXES || defined(__DOXYGEN__) - /*------------------------------------------------------------------------* - * chibios_rt::Mailbox * - *------------------------------------------------------------------------*/ - /** - * @brief Class encapsulating a mailbox. - */ - class Mailbox { - public: - /** - * @brief Embedded @p ::Mailbox structure. - */ - ::Mailbox mb; - - /** - * @brief Mailbox constructor. - * @details The embedded @p ::Mailbox structure is initialized. - * - * @param[in] buf pointer to the messages buffer as an array of - * @p msg_t - * @param[in] n number of elements in the buffer array - * - * @init - */ - Mailbox(msg_t *buf, cnt_t n); - - /** - * @brief Resets a Mailbox object. - * @details All the waiting threads are resumed with status @p RDY_RESET - * and the queued messages are lost. - * - * @api - */ - void reset(void); - - /** - * @brief Posts a message into a mailbox. - * @details The invoking thread waits until a empty slot in the mailbox - * becomes available or the specified time runs out. - * - * @param[in] msg the message to be posted on the mailbox - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval RDY_OK if a message has been correctly posted. - * @retval RDY_RESET if the mailbox has been reset while waiting. - * @retval RDY_TIMEOUT if the operation has timed out. - * - * @api - */ - msg_t post(msg_t msg, systime_t time); - - /** - * @brief Posts a message into a mailbox. - * @details The invoking thread waits until a empty slot in the mailbox - * becomes available or the specified time runs out. - * - * @param[in] msg the message to be posted on the mailbox - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval RDY_OK if a message has been correctly posted. - * @retval RDY_RESET if the mailbox has been reset while waiting. - * @retval RDY_TIMEOUT if the operation has timed out. - * - * @sclass - */ - msg_t postS(msg_t msg, systime_t time); - - /** - * @brief Posts a message into a mailbox. - * @details This variant is non-blocking, the function returns a timeout - * condition if the queue is full. - * - * @param[in] msg the message to be posted on the mailbox - * @return The operation status. - * @retval RDY_OK if a message has been correctly posted. - * @retval RDY_TIMEOUT if the mailbox is full and the message cannot be - * posted. - * - * @iclass - */ - msg_t postI(msg_t msg); - - /** - * @brief Posts an high priority message into a mailbox. - * @details The invoking thread waits until a empty slot in the mailbox - * becomes available or the specified time runs out. - * - * @param[in] msg the message to be posted on the mailbox - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval RDY_OK if a message has been correctly posted. - * @retval RDY_RESET if the mailbox has been reset while waiting. - * @retval RDY_TIMEOUT if the operation has timed out. - * - * @api - */ - msg_t postAhead(msg_t msg, systime_t time); - - /** - * @brief Posts an high priority message into a mailbox. - * @details The invoking thread waits until a empty slot in the mailbox - * becomes available or the specified time runs out. - * - * @param[in] msg the message to be posted on the mailbox - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval RDY_OK if a message has been correctly posted. - * @retval RDY_RESET if the mailbox has been reset while waiting. - * @retval RDY_TIMEOUT if the operation has timed out. - * - * @sclass - */ - msg_t postAheadS(msg_t msg, systime_t time); - - /** - * @brief Posts an high priority message into a mailbox. - * @details This variant is non-blocking, the function returns a timeout - * condition if the queue is full. - * - * @param[in] msg the message to be posted on the mailbox - * @return The operation status. - * @retval RDY_OK if a message has been correctly posted. - * @retval RDY_TIMEOUT if the mailbox is full and the message cannot be - * posted. - * - * @iclass - */ - msg_t postAheadI(msg_t msg); - - /** - * @brief Retrieves a message from a mailbox. - * @details The invoking thread waits until a message is posted in the - * mailbox or the specified time runs out. - * - * @param[out] msgp pointer to a message variable for the received - * @param[in] time message the number of ticks before the operation - * timeouts, the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval RDY_OK if a message has been correctly fetched. - * @retval RDY_RESET if the mailbox has been reset while waiting. - * @retval RDY_TIMEOUT if the operation has timed out. - * - * @api - */ - msg_t fetch(msg_t *msgp, systime_t time); - - /** - * @brief Retrieves a message from a mailbox. - * @details The invoking thread waits until a message is posted in the - * mailbox or the specified time runs out. - * - * @param[out] msgp pointer to a message variable for the received - * @param[in] time message the number of ticks before the operation - * timeouts, the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval RDY_OK if a message has been correctly fetched. - * @retval RDY_RESET if the mailbox has been reset while waiting. - * @retval RDY_TIMEOUT if the operation has timed out. - * - * @sclass - */ - msg_t fetchS(msg_t *msgp, systime_t time); - - /** - * @brief Retrieves a message from a mailbox. - * @details This variant is non-blocking, the function returns a timeout - * condition if the queue is empty. - * - * @param[out] msgp pointer to a message variable for the received - * message - * @return The operation status. - * @retval RDY_OK if a message has been correctly fetched. - * @retval RDY_TIMEOUT if the mailbox is empty and a message cannot be - * fetched. - * - * @iclass - */ - msg_t fetchI(msg_t *msgp); - - /** - * @brief Returns the number of free message slots into a mailbox. - * @note Can be invoked in any system state but if invoked out of a - * locked state then the returned value may change after reading. - * @note The returned value can be less than zero when there are waiting - * threads on the internal semaphore. - * - * @return The number of empty message slots. - * - * @iclass - */ - cnt_t getFreeCountI(void); - - /** - * @brief Returns the number of used message slots into a mailbox. - * @note Can be invoked in any system state but if invoked out of a - * locked state then the returned value may change after reading. - * @note The returned value can be less than zero when there are waiting - * threads on the internal semaphore. - * - * @return The number of queued messages. - * - * @iclass - */ - cnt_t getUsedCountI(void); - }; - - /*------------------------------------------------------------------------* - * chibios_rt::MailboxBuffer * - *------------------------------------------------------------------------*/ - /** - * @brief Template class encapsulating a mailbox and its messages buffer. - * - * @param N size of the mailbox - */ - template - class MailboxBuffer : public Mailbox { - private: - msg_t mb_buf[N]; - - public: - /** - * @brief BufferMailbox constructor. - * - * @init - */ - MailboxBuffer(void) : Mailbox(mb_buf, - (cnt_t)(sizeof mb_buf / sizeof (msg_t))) { - } - }; -#endif /* CH_USE_MAILBOXES */ - -#if CH_USE_MEMPOOLS || defined(__DOXYGEN__) - /*------------------------------------------------------------------------* - * chibios_rt::MemoryPool * - *------------------------------------------------------------------------*/ - /** - * @brief Class encapsulating a mailbox. - */ - class MemoryPool { - public: - /** - * @brief Embedded @p ::MemoryPool structure. - */ - ::MemoryPool pool; - - /** - * @brief MemoryPool constructor. - * - * @param[in] size the size of the objects contained in this memory - * pool, the minimum accepted size is the size of - * a pointer to void. - * @param[in] provider memory provider function for the memory pool or - * @p NULL if the pool is not allowed to grow - * automatically - * - * @init - */ - MemoryPool(size_t size, memgetfunc_t provider); - - /** - * @brief MemoryPool constructor. - * - * @param[in] size the size of the objects contained in this memory - * pool, the minimum accepted size is the size of - * a pointer to void. - * @param[in] provider memory provider function for the memory pool or - * @p NULL if the pool is not allowed to grow - * automatically - * @param[in] p pointer to the array first element - * @param[in] n number of elements in the array - * - * @init - */ - MemoryPool(size_t size, memgetfunc_t provider, void* p, size_t n); - - /** - * @brief Loads a memory pool with an array of static objects. - * @pre The memory pool must be already been initialized. - * @pre The array elements must be of the right size for the specified - * memory pool. - * @post The memory pool contains the elements of the input array. - * - * @param[in] p pointer to the array first element - * @param[in] n number of elements in the array - * - * @api - */ - void loadArray(void *p, size_t n); - - /** - * @brief Allocates an object from a memory pool. - * @pre The memory pool must be already been initialized. - * - * @return The pointer to the allocated object. - * @retval NULL if pool is empty. - * - * @iclass - */ - void *allocI(void); - - /** - * @brief Allocates an object from a memory pool. - * @pre The memory pool must be already been initialized. - * - * @return The pointer to the allocated object. - * @retval NULL if pool is empty. - * - * @api - */ - void *alloc(void); - - /** - * @brief Releases an object into a memory pool. - * @pre The memory pool must be already been initialized. - * @pre The freed object must be of the right size for the specified - * memory pool. - * @pre The object must be properly aligned to contain a pointer to - * void. - * - * @param[in] objp the pointer to the object to be released - * - * @iclass - */ - void free(void *objp); - - /** - * @brief Adds an object to a memory pool. - * @pre The memory pool must be already been initialized. - * @pre The added object must be of the right size for the specified - * memory pool. - * @pre The added object must be memory aligned to the size of - * @p stkalign_t type. - * @note This function is just an alias for @p chPoolFree() and has been - * added for clarity. - * - * @param[in] objp the pointer to the object to be added - * - * @iclass - */ - void freeI(void *objp); - }; - - /*------------------------------------------------------------------------* - * chibios_rt::ObjectsPool * - *------------------------------------------------------------------------*/ - /** - * @brief Template class encapsulating a memory pool and its elements. - */ - template - class ObjectsPool : public MemoryPool { - private: - /* The buffer is declared as an array of pointers to void for two - reasons: - 1) The objects must be properly aligned to hold a pointer as - first field. - 2) There is no need to invoke constructors for object that are - into the pool.*/ - void *pool_buf[(N * sizeof (T)) / sizeof (void *)]; - - public: - /** - * @brief ObjectsPool constructor. - * - * @init - */ - ObjectsPool(void) : MemoryPool(sizeof (T), NULL) { - - loadArray(pool_buf, N); - } - }; -#endif /* CH_USE_MEMPOOLS */ - - /*------------------------------------------------------------------------* - * chibios_rt::BaseSequentialStreamInterface * - *------------------------------------------------------------------------*/ - /** - * @brief Interface of a ::BaseSequentialStream. - * @note You can cast a ::BaseSequentialStream to this interface and use - * it, the memory layout is the same. - */ - class BaseSequentialStreamInterface { - public: - /** - * @brief Sequential Stream write. - * @details The function writes data from a buffer to a stream. - * - * @param[in] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred - * @return The number of bytes transferred. The return value - * can be less than the specified number of bytes if - * an end-of-file condition has been met. - * - * @api - */ - virtual size_t write(const uint8_t *bp, size_t n) = 0; - - /** - * @brief Sequential Stream read. - * @details The function reads data from a stream into a buffer. - * - * @param[out] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred - * @return The number of bytes transferred. The return value - * can be less than the specified number of bytes if - * an end-of-file condition has been met. - * - * @api - */ - virtual size_t read(uint8_t *bp, size_t n) = 0; - - /** - * @brief Sequential Stream blocking byte write. - * @details This function writes a byte value to a channel. If the channel - * is not ready to accept data then the calling thread is - * suspended. - * - * @param[in] b the byte value to be written to the channel - * - * @return The operation status. - * @retval Q_OK if the operation succeeded. - * @retval Q_RESET if an end-of-file condition has been met. - * - * @api - */ - virtual msg_t put(uint8_t b) = 0; - - /** - * @brief Sequential Stream blocking byte read. - * @details This function reads a byte value from a channel. If the data - * is not available then the calling thread is suspended. - * - * @return A byte value from the queue. - * @retval Q_RESET if an end-of-file condition has been met. - * - * @api - */ - virtual msg_t get(void) = 0; - }; -} - -#endif /* _CH_HPP_ */ - -/** @} */ diff --git a/firmware/chibios/os/various/cpp_wrappers/kernel.mk b/firmware/chibios/os/various/cpp_wrappers/kernel.mk deleted file mode 100644 index 049da2d371..0000000000 --- a/firmware/chibios/os/various/cpp_wrappers/kernel.mk +++ /dev/null @@ -1,4 +0,0 @@ -# C++ wrapper files. -CHCPPSRC = ${CHIBIOS}/os/various/cpp_wrappers/ch.cpp - -CHCPPINC = ${CHIBIOS}/os/various/cpp_wrappers diff --git a/firmware/chibios/os/various/devices_lib/accel/lis302dl.c b/firmware/chibios/os/various/devices_lib/accel/lis302dl.c deleted file mode 100644 index 0e7f6eecc1..0000000000 --- a/firmware/chibios/os/various/devices_lib/accel/lis302dl.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file lis302dl.c - * @brief LIS302DL MEMS interface module through SPI code. - * - * @addtogroup lis302dl - * @{ - */ - -#include "ch.h" -#include "hal.h" -#include "lis302dl.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -static uint8_t txbuf[2]; -static uint8_t rxbuf[2]; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Reads a register value. - * @pre The SPI interface must be initialized and the driver started. - * - * @param[in] spip pointer to the SPI initerface - * @param[in] reg register number - * @return The register value. - */ -uint8_t lis302dlReadRegister(SPIDriver *spip, uint8_t reg) { - - spiSelect(spip); - txbuf[0] = 0x80 | reg; - txbuf[1] = 0xff; - spiExchange(spip, 2, txbuf, rxbuf); - spiUnselect(spip); - return rxbuf[1]; -} - -/** - * @brief Writes a value into a register. - * @pre The SPI interface must be initialized and the driver started. - * - * @param[in] spip pointer to the SPI initerface - * @param[in] reg register number - * @param[in] value the value to be written - */ -void lis302dlWriteRegister(SPIDriver *spip, uint8_t reg, uint8_t value) { - - switch (reg) { - default: - /* Reserved register must not be written, according to the datasheet - this could permanently damage the device.*/ - chDbgAssert(FALSE, "lis302dlWriteRegister(), #1", "reserved register"); - case LIS302DL_WHO_AM_I: - case LIS302DL_HP_FILTER_RESET: - case LIS302DL_STATUS_REG: - case LIS302DL_OUTX: - case LIS302DL_OUTY: - case LIS302DL_OUTZ: - case LIS302DL_FF_WU_SRC1: - case LIS302DL_FF_WU_SRC2: - case LIS302DL_CLICK_SRC: - /* Read only registers cannot be written, the command is ignored.*/ - return; - case LIS302DL_CTRL_REG1: - case LIS302DL_CTRL_REG2: - case LIS302DL_CTRL_REG3: - case LIS302DL_FF_WU_CFG1: - case LIS302DL_FF_WU_THS1: - case LIS302DL_FF_WU_DURATION1: - case LIS302DL_FF_WU_CFG2: - case LIS302DL_FF_WU_THS2: - case LIS302DL_FF_WU_DURATION2: - case LIS302DL_CLICK_CFG: - case LIS302DL_CLICK_THSY_X: - case LIS302DL_CLICK_THSZ: - case LIS302DL_CLICK_TIMELIMIT: - case LIS302DL_CLICK_LATENCY: - case LIS302DL_CLICK_WINDOW: - spiSelect(spip); - txbuf[0] = reg; - txbuf[1] = value; - spiSend(spip, 2, txbuf); - spiUnselect(spip); - } -} - -/** @} */ diff --git a/firmware/chibios/os/various/devices_lib/accel/lis302dl.h b/firmware/chibios/os/various/devices_lib/accel/lis302dl.h deleted file mode 100644 index efa11f549a..0000000000 --- a/firmware/chibios/os/various/devices_lib/accel/lis302dl.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file lis302dl.h - * @brief LIS302DL MEMS interface module through SPI header. - * - * @addtogroup lis302dl - * @{ - */ - -#ifndef _LIS302DL_H_ -#define _LIS302DL_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name LIS302DL register names - * @{ - */ -#define LIS302DL_WHO_AM_I 0x0F -#define LIS302DL_CTRL_REG1 0x20 -#define LIS302DL_CTRL_REG2 0x21 -#define LIS302DL_CTRL_REG3 0x22 -#define LIS302DL_HP_FILTER_RESET 0x23 -#define LIS302DL_STATUS_REG 0x27 -#define LIS302DL_OUTX 0x29 -#define LIS302DL_OUTY 0x2B -#define LIS302DL_OUTZ 0x2D -#define LIS302DL_FF_WU_CFG1 0x30 -#define LIS302DL_FF_WU_SRC1 0x31 -#define LIS302DL_FF_WU_THS1 0x32 -#define LIS302DL_FF_WU_DURATION1 0x33 -#define LIS302DL_FF_WU_CFG2 0x34 -#define LIS302DL_FF_WU_SRC2 0x35 -#define LIS302DL_FF_WU_THS2 0x36 -#define LIS302DL_FF_WU_DURATION2 0x37 -#define LIS302DL_CLICK_CFG 0x38 -#define LIS302DL_CLICK_SRC 0x39 -#define LIS302DL_CLICK_THSY_X 0x3B -#define LIS302DL_CLICK_THSZ 0x3C -#define LIS302DL_CLICK_TIMELIMIT 0x3D -#define LIS302DL_CLICK_LATENCY 0x3E -#define LIS302DL_CLICK_WINDOW 0x3F -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - uint8_t lis302dlReadRegister(SPIDriver *spip, uint8_t reg); - void lis302dlWriteRegister(SPIDriver *spip, uint8_t reg, uint8_t value); -#ifdef __cplusplus -} -#endif - -#endif /* _LIS302DL_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/various/fatfs_bindings/fatfs.mk b/firmware/chibios/os/various/fatfs_bindings/fatfs.mk deleted file mode 100644 index b703dd2689..0000000000 --- a/firmware/chibios/os/various/fatfs_bindings/fatfs.mk +++ /dev/null @@ -1,7 +0,0 @@ -# FATFS files. -FATFSSRC = ${CHIBIOS}/os/various/fatfs_bindings/fatfs_diskio.c \ - ${CHIBIOS}/os/various/fatfs_bindings/fatfs_syscall.c \ - ${CHIBIOS}/ext/fatfs/src/ff.c \ - ${CHIBIOS}/ext/fatfs/src/option/ccsbcs.c - -FATFSINC = ${CHIBIOS}/ext/fatfs/src diff --git a/firmware/chibios/os/various/fatfs_bindings/fatfs_diskio.c b/firmware/chibios/os/various/fatfs_bindings/fatfs_diskio.c deleted file mode 100644 index 5021ae6100..0000000000 --- a/firmware/chibios/os/various/fatfs_bindings/fatfs_diskio.c +++ /dev/null @@ -1,255 +0,0 @@ -/*-----------------------------------------------------------------------*/ -/* Low level disk I/O module skeleton for FatFs (C)ChaN, 2007 */ -/*-----------------------------------------------------------------------*/ -/* This is a stub disk I/O module that acts as front end of the existing */ -/* disk I/O modules and attach it to FatFs module with common interface. */ -/*-----------------------------------------------------------------------*/ - -#include "main.h" -#include "ffconf.h" -#include "diskio.h" - -#if EFI_FILE_LOGGING || defined(__DOXYGEN__) - -#if HAL_USE_MMC_SPI && HAL_USE_SDC -#error "cannot specify both MMC_SPI and SDC drivers" -#endif - -#if HAL_USE_MMC_SPI -extern MMCDriver MMCD1; -#elif HAL_USE_SDC -extern SDCDriver SDCD1; -#else -#error "MMC_SPI or SDC driver must be specified" -#endif - -#if HAL_USE_RTC -#include "chrtclib.h" -extern RTCDriver RTCD1; -#endif - -/*-----------------------------------------------------------------------*/ -/* Correspondence between physical drive number and physical drive. */ - -#define MMC 0 -#define SDC 0 - - - -/*-----------------------------------------------------------------------*/ -/* Inidialize a Drive */ - -DSTATUS disk_initialize ( - BYTE drv /* Physical drive nmuber (0..) */ -) -{ - DSTATUS stat; - - switch (drv) { -#if HAL_USE_MMC_SPI - case MMC: - stat = 0; - /* It is initialized externally, just reads the status.*/ - if (blkGetDriverState(&MMCD1) != BLK_READY) - stat |= STA_NOINIT; - if (mmcIsWriteProtected(&MMCD1)) - stat |= STA_PROTECT; - return stat; -#else - case SDC: - stat = 0; - /* It is initialized externally, just reads the status.*/ - if (blkGetDriverState(&SDCD1) != BLK_READY) - stat |= STA_NOINIT; - if (sdcIsWriteProtected(&SDCD1)) - stat |= STA_PROTECT; - return stat; -#endif - } - return STA_NODISK; -} - - - -/*-----------------------------------------------------------------------*/ -/* Return Disk Status */ - -DSTATUS disk_status ( - BYTE drv /* Physical drive nmuber (0..) */ -) -{ - DSTATUS stat; - - switch (drv) { -#if HAL_USE_MMC_SPI - case MMC: - stat = 0; - /* It is initialized externally, just reads the status.*/ - if (blkGetDriverState(&MMCD1) != BLK_READY) - stat |= STA_NOINIT; - if (mmcIsWriteProtected(&MMCD1)) - stat |= STA_PROTECT; - return stat; -#else - case SDC: - stat = 0; - /* It is initialized externally, just reads the status.*/ - if (blkGetDriverState(&SDCD1) != BLK_READY) - stat |= STA_NOINIT; - if (sdcIsWriteProtected(&SDCD1)) - stat |= STA_PROTECT; - return stat; -#endif - } - return STA_NODISK; -} - - - -/*-----------------------------------------------------------------------*/ -/* Read Sector(s) */ - -DRESULT disk_read ( - BYTE drv, /* Physical drive nmuber (0..) */ - BYTE *buff, /* Data buffer to store read data */ - DWORD sector, /* Sector address (LBA) */ - BYTE count /* Number of sectors to read (1..255) */ -) -{ - switch (drv) { -#if HAL_USE_MMC_SPI - case MMC: - if (blkGetDriverState(&MMCD1) != BLK_READY) - return RES_NOTRDY; - if (mmcStartSequentialRead(&MMCD1, sector)) - return RES_ERROR; - while (count > 0) { - if (mmcSequentialRead(&MMCD1, buff)) - return RES_ERROR; - buff += MMCSD_BLOCK_SIZE; - count--; - } - if (mmcStopSequentialRead(&MMCD1)) - return RES_ERROR; - return RES_OK; -#else - case SDC: - if (blkGetDriverState(&SDCD1) != BLK_READY) - return RES_NOTRDY; - if (sdcRead(&SDCD1, sector, buff, count)) - return RES_ERROR; - return RES_OK; -#endif - } - return RES_PARERR; -} - - - -/*-----------------------------------------------------------------------*/ -/* Write Sector(s) */ - -#if _READONLY == 0 -DRESULT disk_write ( - BYTE drv, /* Physical drive nmuber (0..) */ - const BYTE *buff, /* Data to be written */ - DWORD sector, /* Sector address (LBA) */ - BYTE count /* Number of sectors to write (1..255) */ -) -{ - switch (drv) { -#if HAL_USE_MMC_SPI - case MMC: - if (blkGetDriverState(&MMCD1) != BLK_READY) - return RES_NOTRDY; - if (mmcIsWriteProtected(&MMCD1)) - return RES_WRPRT; - if (mmcStartSequentialWrite(&MMCD1, sector)) - return RES_ERROR; - while (count > 0) { - if (mmcSequentialWrite(&MMCD1, buff)) - return RES_ERROR; - buff += MMCSD_BLOCK_SIZE; - count--; - } - if (mmcStopSequentialWrite(&MMCD1)) - return RES_ERROR; - return RES_OK; -#else - case SDC: - if (blkGetDriverState(&SDCD1) != BLK_READY) - return RES_NOTRDY; - if (sdcWrite(&SDCD1, sector, buff, count)) - return RES_ERROR; - return RES_OK; -#endif - } - return RES_PARERR; -} -#endif /* _READONLY */ - - - -/*-----------------------------------------------------------------------*/ -/* Miscellaneous Functions */ - -DRESULT disk_ioctl ( - BYTE drv, /* Physical drive nmuber (0..) */ - BYTE ctrl, /* Control code */ - void *buff /* Buffer to send/receive control data */ -) -{ - switch (drv) { -#if HAL_USE_MMC_SPI - case MMC: - switch (ctrl) { - case CTRL_SYNC: - return RES_OK; - case GET_SECTOR_SIZE: - *((WORD *)buff) = MMCSD_BLOCK_SIZE; - return RES_OK; -#if _USE_ERASE - case CTRL_ERASE_SECTOR: - mmcErase(&MMCD1, *((DWORD *)buff), *((DWORD *)buff + 1)); - return RES_OK; -#endif - default: - return RES_PARERR; - } -#else - case SDC: - switch (ctrl) { - case CTRL_SYNC: - return RES_OK; - case GET_SECTOR_COUNT: - *((DWORD *)buff) = mmcsdGetCardCapacity(&SDCD1); - return RES_OK; - case GET_SECTOR_SIZE: - *((WORD *)buff) = MMCSD_BLOCK_SIZE; - return RES_OK; - case GET_BLOCK_SIZE: - *((DWORD *)buff) = 256; /* 512b blocks in one erase block */ - return RES_OK; -#if _USE_ERASE - case CTRL_ERASE_SECTOR: - sdcErase(&SDCD1, *((DWORD *)buff), *((DWORD *)buff + 1)); - return RES_OK; -#endif - default: - return RES_PARERR; - } -#endif - } - return RES_PARERR; -} - -DWORD get_fattime(void) { -#if HAL_USE_RTC - return rtcGetTimeFat(&RTCD1); -#else - return ((uint32_t)0 | (1 << 16)) | (1 << 21); /* wrong but valid time */ -#endif -} - -#endif - diff --git a/firmware/chibios/os/various/fatfs_bindings/fatfs_syscall.c b/firmware/chibios/os/various/fatfs_bindings/fatfs_syscall.c deleted file mode 100644 index c4e35bf0ae..0000000000 --- a/firmware/chibios/os/various/fatfs_bindings/fatfs_syscall.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/*------------------------------------------------------------------------*/ -/* Sample code of OS dependent controls for FatFs R0.08b */ -/* (C)ChaN, 2011 */ -/*------------------------------------------------------------------------*/ - -#include "ch.h" -#include "ff.h" - -#if _FS_REENTRANT -/*------------------------------------------------------------------------*/ -/* Static array of Synchronization Objects */ -/*------------------------------------------------------------------------*/ -static Semaphore ff_sem[_VOLUMES]; - -/*------------------------------------------------------------------------*/ -/* Create a Synchronization Object */ -/*------------------------------------------------------------------------*/ -int ff_cre_syncobj(BYTE vol, _SYNC_t *sobj) { - - *sobj = &ff_sem[vol]; - chSemInit(*sobj, 1); - return TRUE; -} - -/*------------------------------------------------------------------------*/ -/* Delete a Synchronization Object */ -/*------------------------------------------------------------------------*/ -int ff_del_syncobj(_SYNC_t sobj) { - - chSemReset(sobj, 0); - return TRUE; -} - -/*------------------------------------------------------------------------*/ -/* Request Grant to Access the Volume */ -/*------------------------------------------------------------------------*/ -int ff_req_grant(_SYNC_t sobj) { - - msg_t msg = chSemWaitTimeout(sobj, (systime_t)_FS_TIMEOUT); - return msg == RDY_OK; -} - -/*------------------------------------------------------------------------*/ -/* Release Grant to Access the Volume */ -/*------------------------------------------------------------------------*/ -void ff_rel_grant(_SYNC_t sobj) { - - chSemSignal(sobj); -} -#endif /* _FS_REENTRANT */ - -#if _USE_LFN == 3 /* LFN with a working buffer on the heap */ -/*------------------------------------------------------------------------*/ -/* Allocate a memory block */ -/*------------------------------------------------------------------------*/ -void *ff_memalloc(UINT size) { - - return chHeapAlloc(NULL, size); -} - -/*------------------------------------------------------------------------*/ -/* Free a memory block */ -/*------------------------------------------------------------------------*/ -void ff_memfree(void *mblock) { - - chHeapFree(mblock); -} -#endif /* _USE_LFN == 3 */ diff --git a/firmware/chibios/os/various/memstreams.c b/firmware/chibios/os/various/memstreams.c deleted file mode 100644 index 095c65e0f5..0000000000 --- a/firmware/chibios/os/various/memstreams.c +++ /dev/null @@ -1,113 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file memstreams.c - * @brief Memory streams code. - * - * @addtogroup memory_streams - * @{ - */ - -#include - -#include "ch.h" -#include "memstreams.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static size_t writes(void *ip, const uint8_t *bp, size_t n) { - MemoryStream *msp = ip; - - if (msp->size - msp->eos < n) - n = msp->size - msp->eos; - memcpy(msp->buffer + msp->eos, bp, n); - msp->eos += n; - return n; -} - -static size_t reads(void *ip, uint8_t *bp, size_t n) { - MemoryStream *msp = ip; - - if (msp->eos - msp->offset < n) - n = msp->eos - msp->offset; - memcpy(bp, msp->buffer + msp->offset, n); - msp->offset += n; - return n; -} - -static msg_t put(void *ip, uint8_t b) { - MemoryStream *msp = ip; - - if (msp->size - msp->eos <= 0) - return RDY_RESET; - *(msp->buffer + msp->eos) = b; - msp->eos += 1; - return RDY_OK; -} - -static msg_t get(void *ip) { - uint8_t b; - MemoryStream *msp = ip; - - if (msp->eos - msp->offset <= 0) - return RDY_RESET; - b = *(msp->buffer + msp->offset); - msp->offset += 1; - return b; -} - -static const struct MemStreamVMT vmt = {writes, reads, put, get}; - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Memory stream object initialization. - * - * @param[out] msp pointer to the @p MemoryStream object to be initialized - * @param[in] buffer pointer to the memory buffer for the memory stream - * @param[in] size total size of the memory stream buffer - * @param[in] eos initial End Of Stream offset. Normally you need to - * put this to zero for RAM buffers or equal to @p size - * for ROM streams. - */ -void msObjectInit(MemoryStream *msp, uint8_t *buffer, - size_t size, size_t eos) { - - msp->vmt = &vmt; - msp->buffer = buffer; - msp->size = size; - msp->eos = eos; - msp->offset = 0; -} - -/** @} */ diff --git a/firmware/chibios/os/various/memstreams.h b/firmware/chibios/os/various/memstreams.h deleted file mode 100644 index 9a1da6c585..0000000000 --- a/firmware/chibios/os/various/memstreams.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file memstreams.h - * @brief Memory streams structures and macros. - - * @addtogroup memory_streams - * @{ - */ - -#ifndef _MEMSTREAMS_H_ -#define _MEMSTREAMS_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief @p RamStream specific data. - */ -#define _memory_stream_data \ - _base_sequential_stream_data \ - /* Pointer to the stream buffer.*/ \ - uint8_t *buffer; \ - /* Size of the stream.*/ \ - size_t size; \ - /* Current end of stream.*/ \ - size_t eos; \ - /* Current read offset.*/ \ - size_t offset; - -/** - * @brief @p MemStream virtual methods table. - */ -struct MemStreamVMT { - _base_sequential_stream_methods -}; - -/** - * @extends BaseSequentialStream - * - * @brief Memory stream object. - */ -typedef struct { - /** @brief Virtual Methods Table.*/ - const struct MemStreamVMT *vmt; - _memory_stream_data -} MemoryStream; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void msObjectInit(MemoryStream *msp, uint8_t *buffer, - size_t size, size_t eos); -#ifdef __cplusplus -} -#endif - -#endif /* _MEMSTREAMS_H_ */ - -/** @} */ diff --git a/firmware/chibios/os/various/syscalls.c b/firmware/chibios/os/various/syscalls.c deleted file mode 100644 index 4c337c339a..0000000000 --- a/firmware/chibios/os/various/syscalls.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* -* **** This file incorporates work covered by the following copyright and **** -* **** permission notice: **** -* -* Copyright (c) 2009 by Michael Fischer. All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* 1. Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* 3. Neither the name of the author nor the names of its contributors may -* be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL -* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -* SUCH DAMAGE. -* -**************************************************************************** -* History: -* -* 28.03.09 mifi First Version, based on the original syscall.c from -* newlib version 1.17.0 -* 17.08.09 gdisirio Modified the file for use under ChibiOS/RT -* 15.11.09 gdisirio Added read and write handling -****************************************************************************/ - -#include -#include -#include -#include -#include - -#include "ch.h" -#if defined(STDOUT_SD) || defined(STDIN_SD) -#include "hal.h" -#endif - -#ifndef __errno_r -#include -#define __errno_r(reent) reent->_errno -#endif - -/***************************************************************************/ - -int _read_r(struct _reent *r, int file, char * ptr, int len) -{ - (void)r; -#if defined(STDIN_SD) - if (!len || (file != 0)) { - __errno_r(r) = EINVAL; - return -1; - } - len = sdRead(&STDIN_SD, (uint8_t *)ptr, (size_t)len); - return len; -#else - (void)file; - (void)ptr; - (void)len; - __errno_r(r) = EINVAL; - return -1; -#endif -} - -/***************************************************************************/ - -int _lseek_r(struct _reent *r, int file, int ptr, int dir) -{ - (void)r; - (void)file; - (void)ptr; - (void)dir; - - return 0; -} - -/***************************************************************************/ - -int _write_r(struct _reent *r, int file, char * ptr, int len) -{ - (void)r; - (void)file; - (void)ptr; -#if defined(STDOUT_SD) - if (file != 1) { - __errno_r(r) = EINVAL; - return -1; - } - sdWrite(&STDOUT_SD, (uint8_t *)ptr, (size_t)len); -#endif - return len; -} - -/***************************************************************************/ - -int _close_r(struct _reent *r, int file) -{ - (void)r; - (void)file; - - return 0; -} - -/***************************************************************************/ - -caddr_t _sbrk_r(struct _reent *r, int incr) -{ -#if CH_USE_MEMCORE - void *p; - - chDbgCheck(incr > 0, "_sbrk_r"); - - p = chCoreAlloc((size_t)incr); - if (p == NULL) { - __errno_r(r) = ENOMEM; - return (caddr_t)-1; - } - return (caddr_t)p; -#else - (void)incr; - __errno_r(r) = ENOMEM; - return (caddr_t)-1; -#endif -} - -/***************************************************************************/ - -int _fstat_r(struct _reent *r, int file, struct stat * st) -{ - (void)r; - (void)file; - - memset(st, 0, sizeof(*st)); - st->st_mode = S_IFCHR; - return 0; -} - -/***************************************************************************/ - -int _isatty_r(struct _reent *r, int fd) -{ - (void)r; - (void)fd; - - return 1; -} - -/*** EOF ***/ diff --git a/firmware/chibios/readme.txt b/firmware/chibios/readme.txt deleted file mode 100644 index 31f7aca3e4..0000000000 --- a/firmware/chibios/readme.txt +++ /dev/null @@ -1,5 +0,0 @@ - -In this folder we have ChibiOS 2.6.7 with rusefi_chibios.patch applied. -http://chibios.org/ - -rusefi_chibios.patch is only about minor improvements to fatal error message - like __FILE__ info and maybe better messages. \ No newline at end of file diff --git a/firmware/chibios/rusefi_chibios.patch b/firmware/chibios/rusefi_chibios.patch deleted file mode 100644 index 2237a8ca7a..0000000000 --- a/firmware/chibios/rusefi_chibios.patch +++ /dev/null @@ -1,111 +0,0 @@ -Index: boards/ST_STM32F4_DISCOVERY/board.h -=================================================================== ---- boards/ST_STM32F4_DISCOVERY/board.h (revision 2723) -+++ boards/ST_STM32F4_DISCOVERY/board.h (working copy) -@@ -27,6 +27,7 @@ - #define BOARD_ST_STM32F4_DISCOVERY - #define BOARD_NAME "STMicroelectronics STM32F4-Discovery" - -+#define STM32_LSECLK 32768 - - /* - * Board oscillators-related settings. -Index: os/kernel/src/chdebug.c -=================================================================== ---- os/kernel/src/chdebug.c (revision 2723) -+++ os/kernel/src/chdebug.c (working copy) -@@ -114,7 +114,7 @@ - void dbg_check_lock(void) { - - if ((dbg_isr_cnt != 0) || (dbg_lock_cnt != 0)) -- chDbgPanic("SV#4"); -+ chDbgPanic("SV#4 misplaced chSysLock()"); - dbg_enter_lock(); - } - -@@ -138,7 +138,7 @@ - void dbg_check_lock_from_isr(void) { - - if ((dbg_isr_cnt <= 0) || (dbg_lock_cnt != 0)) -- chDbgPanic("SV#6"); -+ chDbgPanic("SV#6 misplaced chSysLockFromIsr"); - dbg_enter_lock(); - } - -@@ -193,7 +193,7 @@ - void chDbgCheckClassI(void) { - - if ((dbg_isr_cnt < 0) || (dbg_lock_cnt <= 0)) -- chDbgPanic("SV#10"); -+ chDbgPanic("SV#10 misplaced I-class function"); - } - - /** -@@ -268,10 +268,11 @@ - * - * @param[in] msg the pointer to the panic message string - */ -+ -+void chDbgPanic3(const char *msg, char * file, int line); -+ - void chDbgPanic(const char *msg) { -- -- dbg_panic_msg = msg; -- chSysHalt(); -+ chDbgPanic3(msg, __FILE__, __LINE__); - } - #endif /* CH_DBG_ENABLED */ - -Index: os/ports/GCC/ARMCMx/chcore_v7m.h -=================================================================== ---- os/ports/GCC/ARMCMx/chcore_v7m.h (revision 2723) -+++ os/ports/GCC/ARMCMx/chcore_v7m.h (working copy) -@@ -36,6 +36,8 @@ - #ifndef _CHCORE_V7M_H_ - #define _CHCORE_V7M_H_ - -+#include "chdebug.h" -+ - /*===========================================================================*/ - /* Port constants. */ - /*===========================================================================*/ -@@ -486,6 +488,8 @@ - #define port_wait_for_interrupt() - #endif - -+void chDbgStackOverflowPanic(Thread *otp); -+ - /** - * @brief Performs a context switch between two threads. - * @details This is the most critical code in any port, this function -@@ -502,7 +506,7 @@ - #define port_switch(ntp, otp) { \ - register struct intctx *r13 asm ("r13"); \ - if ((stkalign_t *)(r13 - 1) < otp->p_stklimit) \ -- chDbgPanic("stack overflow"); \ -+ chDbgStackOverflowPanic(otp); \ - _port_switch(ntp, otp); \ - } - #endif -Index: os/ports/GCC/ARMCMx/rules.mk -=================================================================== ---- os/ports/GCC/ARMCMx/rules.mk (revision 2723) -+++ os/ports/GCC/ARMCMx/rules.mk (working copy) -@@ -60,7 +60,7 @@ - ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS) - ASXFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS) - CFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS) --CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS) -+CPPFLAGS = $(MCFLAGS) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS) - ifeq ($(USE_LINK_GC),yes) - LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LLIBDIR) - else -@@ -113,7 +113,7 @@ - $(BUILDDIR) $(OBJDIR) $(LSTDIR): - ifneq ($(USE_VERBOSE_COMPILE),yes) - @echo Compiler Options -- @echo $(CC) -c $(CFLAGS) -I. $(IINCDIR) main.c -o main.o -+ @echo $(CPPC) -c $(CPPFLAGS) -I. $(IINCDIR) main.cpp -o main.o -llibstd++ - @echo - endif - mkdir -p $(OBJDIR) From 1eb330c6002885607f9225ce3868fa86cd73432d Mon Sep 17 00:00:00 2001 From: Fabien Poussin Date: Tue, 21 Mar 2017 19:58:14 +0100 Subject: [PATCH 02/74] ChibiOS 16.x update. --- .gitmodules | 7 +- firmware/ChibiOS | 1 + firmware/Makefile.old | 340 +++++++++++++++ firmware/config/stm32f4ems/STM32F407xG_CCM.ld | 201 ++------- firmware/config/stm32f4ems/chconf.h | 391 +++++++----------- firmware/config/stm32f4ems/halconf.h | 156 ++++--- firmware/config/stm32f4ems/mcuconf.h | 159 ++++--- firmware/console/binary/tunerstudio_io.cpp | 2 +- firmware/console/eficonsole.cpp | 2 +- firmware/controllers/algo/error_handling.h | 2 +- firmware/controllers/algo/obd_error_codes.h | 4 +- firmware/controllers/engine_controller.cpp | 8 +- firmware/controllers/error_handling.cpp | 4 +- firmware/controllers/lcd_controller.cpp | 8 +- .../controllers/trigger/rpm_calculator.cpp | 2 +- .../controllers/trigger/trigger_central.cpp | 2 +- .../controllers/trigger/trigger_decoder.cpp | 4 +- .../controllers/trigger/trigger_structure.cpp | 2 +- firmware/ext/diskio.h | 42 +- firmware/ext/ff.h | 153 +++---- firmware/ext/ffconf.h | 207 ++++++---- firmware/ext/ffconf_old.h | 193 +++++++++ firmware/ext/readme.txt | 159 ++++++- firmware/global.h | 36 +- firmware/hw_layer/HIP9011.cpp | 2 +- firmware/hw_layer/can_hw.cpp | 4 +- firmware/hw_layer/digital_input_hw.cpp | 4 +- firmware/hw_layer/hardware.cpp | 14 +- firmware/hw_layer/mass_storage/usb_msd.c | 124 +++--- firmware/hw_layer/mass_storage/usb_msd.h | 51 ++- firmware/hw_layer/mass_storage/usb_msd_cfg.c | 4 +- firmware/hw_layer/mmc_card.cpp | 6 +- firmware/hw_layer/rtc_helper.cpp | 47 ++- firmware/hw_layer/serial_over_usb/usbcfg.c | 6 +- firmware/hw_layer/stm32f4/mpu_util.cpp | 13 +- firmware/hw_layer/trigger_input.cpp | 4 +- firmware/util/datalogging.cpp | 8 +- firmware/util/efilib2.h | 2 +- firmware/util/rfiutil.c | 2 + firmware/util/rfiutil.h | 2 + 40 files changed, 1489 insertions(+), 889 deletions(-) create mode 160000 firmware/ChibiOS create mode 100644 firmware/Makefile.old create mode 100644 firmware/ext/ffconf_old.h diff --git a/.gitmodules b/.gitmodules index de894b04fc..a971b630ef 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,4 @@ -[submodule "firmware/ChibiOS-Contrib"] - path = firmware/ChibiOS-Contrib - url = https://github.com/ChibiOS/ChibiOS-Contrib.git +[submodule "firmware/ChibiOS"] + path = firmware/ChibiOS + url = https://github.com/ChibiOS/ChibiOS.git + branch = stable_16.1.x diff --git a/firmware/ChibiOS b/firmware/ChibiOS new file mode 160000 index 0000000000..7cac0e4b08 --- /dev/null +++ b/firmware/ChibiOS @@ -0,0 +1 @@ +Subproject commit 7cac0e4b0889b9f22fb998e48ac2a5e3f06e0b93 diff --git a/firmware/Makefile.old b/firmware/Makefile.old new file mode 100644 index 0000000000..e3e2dbc155 --- /dev/null +++ b/firmware/Makefile.old @@ -0,0 +1,340 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +PROJECT_DIR = . + +# by default EXTRA_PARAMS is empty and we create 'debug' version of the firmware with additional assertions and statistics +# for 'release' options see 'clean_compile_two_versions.bat' file + + +# Compiler options here. +ifeq ($(USE_OPT),) + #USE_OPT = $(EXTRA_PARAMS) $(RFLAGS) -Os -fomit-frame-pointer -falign-functions=16 -Werror-implicit-function-declaration -Werror -Wno-error=pointer-sign -Wno-error=unused-function -Wno-error=unused-variable -Wno-error=sign-compare -Wno-error=unused-parameter -Wno-error=missing-field-initializers -Werror=type-limits -Wno-error=strict-aliasing -Wno-error=attributes + USE_OPT = -Os -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = -fgnu89-inline -std=gnu99 +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -std=c++11 -fno-rtti -fno-exceptions -fno-use-cxa-atexit -Werror=write-strings -Werror=type-limits +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = -Os -flto=5 +endif + +# Enable this if you want link time optimizations (LTO) +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x0600 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x1000 +endif + +# Enables the use of FPU on Cortex-M4 (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = hard +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = rusefi + +# Imported source files and paths +CHIBIOS = ChibiOS + +#PROJECT_BOARD = OLIMEX_STM32_E407 +ifneq ($(PROJECT_BOARD),OLIMEX_STM32_E407) + PROJECT_BOARD = ST_STM32F4_DISCOVERY +endif +DDEFS += -D$(PROJECT_BOARD) + +# Startup files. +include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/platform.mk +include $(CHIBIOS)/os/hal/boards/$(PROJECT_BOARD)/board.mk +include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk + +include $(CHIBIOS)/os/various/fatfs_bindings/fatfs.mk +include console/binary/tunerstudio.mk +include ext/ext.mk +include $(PROJECT_DIR)/hw_layer/hw_layer.mk +include $(PROJECT_DIR)/hw_layer/sensors/sensors.mk +include $(PROJECT_DIR)/hw_layer/mass_storage/mass_storage.mk +include development/development.mk +include controllers/controllers.mk + +include $(PROJECT_DIR)/util/util.mk +include $(PROJECT_DIR)/config/engines/engines.mk +include $(PROJECT_DIR)/controllers/algo/algo.mk +include $(PROJECT_DIR)/controllers/core/core.mk +include $(PROJECT_DIR)/controllers/math/math.mk +include $(PROJECT_DIR)/controllers/sensors/sensors.mk +include $(PROJECT_DIR)/controllers/system/system.mk +include $(PROJECT_DIR)/controllers/trigger/trigger.mk +include $(PROJECT_DIR)/console/console.mk + + +# Define linker script file here +LDSCRIPT= config/stm32f4ems/STM32F407xG_CCM.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(STARTUPSRC) \ + $(KERNSRC) \ + $(PORTSRC) \ + $(OSALSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/syscalls.c \ + $(CHIBIOS)/os/hal/lib/streams/memstreams.c \ + $(CHIBIOS)/os/hal/lib/streams/chprintf.c \ + $(CHIBIOS)/os/various/shell.c \ + ${HW_MASS_STORAGE_SRC_C} \ + $(UTILSRC) \ + $(ENGINES_SRC) \ + $(CONSOLESRC) \ + $(DEV_SRC) \ + $(HW_LAYER_EMS) \ + $(CONTROLLERSSRC) \ + $(CONTROLLERS_ALGO_SRC) \ + $(CONTROLLERS_CORE_SRC) \ + $(CONTROLLERS_SENSORS_SRC) \ + $(FATFSSRC) \ + $(SYSTEMSRC) + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(CHCPPSRC) \ + $(TRIGGER_SRC_CPP) \ + $(TRIGGER_DECODERS_SRC_CPP) \ + $(DEV_SRC_CPP) \ + $(CONTROLLERS_ALGO_SRC_CPP) \ + $(SYSTEMSRC_CPP) \ + $(ENGINES_SRC_CPP) \ + $(HW_LAYER_EMS_CPP) \ + $(HW_SENSORS_SRC) \ + $(TUNERSTUDIO_SRC_CPP) \ + $(CONSOLE_SRC_CPP) \ + $(CONTROLLERS_SENSORS_SRC_CPP) \ + $(CONTROLLERS_SRC_CPP) \ + $(UTILSRC_CPP) \ + $(CONTROLLERS_CORE_SRC_CPP) \ + $(CONTROLLERS_MATH_SRC_CPP) \ + rusefi.cpp \ + main.cpp + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) + +INCDIR = $(PORTINC) \ + $(OSALINC) \ + $(KERNINC) \ + $(TESTINC) \ + $(STARTUPINC) \ + $(HALINC) \ + $(PLATFORMINC) \ + $(BOARDINC) \ + $(CHCPPINC) \ + $(CHIBIOS)/os/hal/lib/streams \ + $(CHIBIOS)/os/various \ + $(CHIBIOS)/os/various/devices_lib/accel \ + config/stm32f4ems \ + config/engines \ + config \ + chibios/os/various \ + ext \ + ext_algo \ + util \ + console_util \ + console \ + $(PROJECT_DIR)/console/binary \ + $(PROJECT_DIR)/console/fl_binary \ + $(PROJECT_DIR)/hw_layer \ + $(PROJECT_DIR)/mass_storage \ + hw_layer/serial_over_usb \ + hw_layer/algo \ + hw_layer/lcd \ + hw_layer/sensors \ + hw_layer/mass_storage \ + hw_layer/stm32f4 \ + development \ + development/hw_layer \ + development/test \ + controllers \ + controllers/sensors \ + controllers/system \ + controllers/algo \ + controllers/core \ + controllers/math \ + controllers/trigger/decoders \ + controllers/trigger + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +SZ = $(TRGT)size +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = -lm + +# +# End of user defines +############################################################################## + +RULESPATH = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC +include $(RULESPATH)/rules.mk diff --git a/firmware/config/stm32f4ems/STM32F407xG_CCM.ld b/firmware/config/stm32f4ems/STM32F407xG_CCM.ld index 1dbaf479a9..d1a5fc1ffa 100644 --- a/firmware/config/stm32f4ems/STM32F407xG_CCM.ld +++ b/firmware/config/stm32f4ems/STM32F407xG_CCM.ld @@ -1,186 +1,51 @@ /* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - This file is part of ChibiOS/RT. + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. + http://www.apache.org/licenses/LICENSE-2.0 - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. */ /* - * ST32F407xG memory setup. + * STM32F407xG memory setup. + * Note: Use of ram1 and ram2 is mutually exclusive with use of ram0. */ -__main_stack_size__ = 0x1000; -__process_stack_size__ = 0x0600; - MEMORY { flash : org = 0x08000000, len = 896k - ram : org = 0x20000000, len = 112k - ethram : org = 0x2001C000, len = 16k - ccmram : org = 0x10000000, len = 64k + ram0 : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */ + ram1 : org = 0x20000000, len = 112k /* SRAM1 */ + ram2 : org = 0x2001C000, len = 16k /* SRAM2 */ + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x10000000, len = 64k /* CCM SRAM */ + ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 } -__ram_start__ = ORIGIN(ram); -__ram_size__ = LENGTH(ram); -__ram_end__ = __ram_start__ + __ram_size__; +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); -ENTRY(ResetHandler) +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); -SECTIONS -{ - . = 0; - _text = .; +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); - startup : ALIGN(16) SUBALIGN(16) - { - KEEP(*(vectors)) - } > flash +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); - constructors : ALIGN(4) SUBALIGN(4) - { - PROVIDE(__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - } > flash +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); - destructors : ALIGN(4) SUBALIGN(4) - { - PROVIDE(__fini_array_start = .); - KEEP(*(.fini_array)) - KEEP(*(SORT(.fini_array.*))) - PROVIDE(__fini_array_end = .); - } > flash - - .text : ALIGN(16) SUBALIGN(16) - { - *(.text.startup.*) - *(.text) - *(.text.*) - *(.rodata) - *(.rodata.*) - *(.glue_7t) - *(.glue_7) - *(.gcc*) - } > flash - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > flash - - .ARM.exidx : { - PROVIDE(__exidx_start = .); - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - PROVIDE(__exidx_end = .); - } > flash - - .eh_frame_hdr : - { - *(.eh_frame_hdr) - } > flash - - .eh_frame : ONLY_IF_RO - { - *(.eh_frame) - } > flash - - .textalign : ONLY_IF_RO - { - . = ALIGN(8); - } > flash - - _etext = .; - _textdata = _etext; - - .stacks : - { - . = ALIGN(8); - __main_stack_base__ = .; - . += __main_stack_size__; - . = ALIGN(8); - __main_stack_end__ = .; - __process_stack_base__ = .; - __main_thread_stack_base__ = .; - . += __process_stack_size__; - . = ALIGN(8); - __process_stack_end__ = .; - __main_thread_stack_end__ = .; - } > ram - - .ccm (NOLOAD) : - { - PROVIDE(_cmm_start = .); - . = ALIGN(4); - *(.bss.mainthread.*) - . = ALIGN(4); - *(.bss._idle_thread_wa) - . = ALIGN(4); - *(.bss.rlist) - . = ALIGN(4); - *(.bss.vtlist) - . = ALIGN(4); - *(.bss.endmem) - . = ALIGN(4); - *(.bss.nextmem) - . = ALIGN(4); - *(.bss.default_heap) - . = ALIGN(4); - *(.ccm) - . = ALIGN(4); - *(.ccm.*) - . = ALIGN(4); - PROVIDE(_cmm_end = .); - } > ccmram - - .data : - { - . = ALIGN(4); - PROVIDE(_data = .); - *(.data) - . = ALIGN(4); - *(.data.*) - . = ALIGN(4); - *(.ramtext) - . = ALIGN(4); - PROVIDE(_edata = .); - } > ram AT > flash - - .bss : - { - . = ALIGN(4); - PROVIDE(_bss_start = .); - *(.bss) - . = ALIGN(4); - *(.bss.*) - . = ALIGN(4); - *(COMMON) - . = ALIGN(4); - PROVIDE(_bss_end = .); - } > ram -} - -PROVIDE(end = .); -_end = .; - -__heap_base__ = _end; -__heap_end__ = __ram_end__; +INCLUDE rules.ld diff --git a/firmware/config/stm32f4ems/chconf.h b/firmware/config/stm32f4ems/chconf.h index f9c1374828..9422affdf4 100644 --- a/firmware/config/stm32f4ems/chconf.h +++ b/firmware/config/stm32f4ems/chconf.h @@ -1,28 +1,17 @@ /* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012 Giovanni Di Sirio. + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - This file is part of ChibiOS/RT. + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. + http://www.apache.org/licenses/LICENSE-2.0 - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. */ /** @@ -39,46 +28,37 @@ #ifndef _CHCONF_H_ #define _CHCONF_H_ -#define chDbgCheck(c, func) { \ - if (!(c)) \ - chDbgPanic3(__QUOTE_THIS(func)"()", __FILE__, __LINE__); \ -} - -#define CORTEX_PRIORITY_SYSTICK 6 - -#define PORT_IDLE_THREAD_STACK_SIZE 1024 - -#define CHPRINTF_USE_FLOAT TRUE - -#define EFI_CLOCK_LOCKS FALSE - - -#if EFI_CLOCK_LOCKS -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - void onLockHook(void); - void onUnlockHook(void); -#ifdef __cplusplus -} -#endif /* __cplusplus */ - #define ON_LOCK_HOOK onLockHook() - #define ON_UNLOCK_HOOK onUnlockHook() -#else /* EFI_CLOCK_LOCKS */ - #define ON_LOCK_HOOK - #define ON_UNLOCK_HOOK -#endif /* EFI_CLOCK_LOCKS */ - +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ /** - * number of ticks per second - * - * 8000 rpm equals 133Hz of crankshaft - * that's 266Hz camshaft - * for timing measures we need 95760 Hz precision + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. */ -#define CH_FREQUENCY 1000 +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 1000 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 0 + +/** @} */ /*===========================================================================*/ /** @@ -87,15 +67,6 @@ extern "C" */ /*===========================================================================*/ -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) -#define CH_FREQUENCY 1000 -#endif - /** * @brief Round robin interval. * @details This constant is the number of system ticks allowed for the @@ -103,13 +74,12 @@ extern "C" * disables the preemption for threads with equal priority and the * round robin becomes cooperative. Note that higher priority * threads can still preempt, the kernel is always preemptive. - * * @note Disabling the round robin preemption makes the kernel more compact * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. */ -#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) -#define CH_TIME_QUANTUM 20 -#endif +#define CH_CFG_TIME_QUANTUM 0 /** * @brief Managed RAM size. @@ -120,29 +90,18 @@ extern "C" * * @note In order to let the OS manage the whole RAM the linker script must * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_MEMCORE. + * @note Requires @p CH_CFG_USE_MEMCORE. */ -#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) -// memory pool is used by ff.c which is used for file logging -#define CH_MEMCORE_SIZE 2048 -#endif +#define CH_CFG_MEMCORE_SIZE 0 /** * @brief Idle thread automatic spawn suppression. * @details When this option is activated the function @p chSysInit() - * does not spawn the idle thread automatically. The application has - * then the responsibility to do one of the following: - * - Spawn a custom idle thread at priority @p IDLEPRIO. - * - Change the main() thread priority to @p IDLEPRIO then enter - * an endless loop. In this scenario the @p main() thread acts as - * the idle thread. - * . - * @note Unless an idle thread is spawned the @p main() thread must not - * enter a sleep state. + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. */ -#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) -#define CH_NO_IDLE_THREAD FALSE -#endif +#define CH_CFG_NO_IDLE_THREAD FALSE /** @} */ @@ -161,9 +120,7 @@ extern "C" * @note This is not related to the compiler optimization options. * @note The default is @p TRUE. */ -#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) -#define CH_OPTIMIZE_SPEED TRUE -#endif +#define CH_CFG_OPTIMIZE_SPEED TRUE /** @} */ @@ -174,15 +131,22 @@ extern "C" */ /*===========================================================================*/ +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM TRUE + /** * @brief Threads registry APIs. * @details If enabled then the registry APIs are included in the kernel. * * @note The default is @p TRUE. */ -#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) -#define CH_USE_REGISTRY TRUE -#endif +#define CH_CFG_USE_REGISTRY TRUE /** * @brief Threads synchronization APIs. @@ -191,9 +155,7 @@ extern "C" * * @note The default is @p TRUE. */ -#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) -#define CH_USE_WAITEXIT FALSE -#endif +#define CH_CFG_USE_WAITEXIT TRUE /** * @brief Semaphores APIs. @@ -201,33 +163,18 @@ extern "C" * * @note The default is @p TRUE. */ -#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES TRUE -#endif +#define CH_CFG_USE_SEMAPHORES TRUE /** * @brief Semaphores queuing mode. * @details If enabled then the threads are enqueued on semaphores by * priority rather than in FIFO order. * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. */ -#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemSignalWait() API - * is included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) -#define CH_USE_SEMSW FALSE -#endif +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE /** * @brief Mutexes APIs. @@ -235,9 +182,17 @@ extern "C" * * @note The default is @p TRUE. */ -#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) -#define CH_USE_MUTEXES TRUE -#endif +#define CH_CFG_USE_MUTEXES TRUE + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE /** * @brief Conditional Variables APIs. @@ -245,11 +200,9 @@ extern "C" * in the kernel. * * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. + * @note Requires @p CH_CFG_USE_MUTEXES. */ -#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS FALSE -#endif +#define CH_CFG_USE_CONDVARS TRUE /** * @brief Conditional Variables APIs with timeout. @@ -257,11 +210,9 @@ extern "C" * specification are included in the kernel. * * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. + * @note Requires @p CH_CFG_USE_CONDVARS. */ -#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS_TIMEOUT FALSE -#endif +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE /** * @brief Events Flags APIs. @@ -269,9 +220,7 @@ extern "C" * * @note The default is @p TRUE. */ -#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) -#define CH_USE_EVENTS TRUE -#endif +#define CH_CFG_USE_EVENTS TRUE /** * @brief Events Flags APIs with timeout. @@ -279,11 +228,9 @@ extern "C" * are included in the kernel. * * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. + * @note Requires @p CH_CFG_USE_EVENTS. */ -#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_EVENTS_TIMEOUT TRUE -#endif +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE /** * @brief Synchronous Messages APIs. @@ -292,21 +239,18 @@ extern "C" * * @note The default is @p TRUE. */ -#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES TRUE -#endif +#define CH_CFG_USE_MESSAGES TRUE /** * @brief Synchronous Messages queuing mode. * @details If enabled then messages are served by priority rather than in * FIFO order. * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. */ -#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_PRIORITY FALSE -#endif +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE /** * @brief Mailboxes APIs. @@ -314,11 +258,9 @@ extern "C" * included in the kernel. * * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note Requires @p CH_CFG_USE_SEMAPHORES. */ -#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXES TRUE -#endif +#define CH_CFG_USE_MAILBOXES TRUE /** * @brief I/O Queues APIs. @@ -326,9 +268,7 @@ extern "C" * * @note The default is @p TRUE. */ -#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) -#define CH_USE_QUEUES TRUE -#endif +#define CH_CFG_USE_QUEUES TRUE /** * @brief Core Memory Manager APIs. @@ -337,9 +277,7 @@ extern "C" * * @note The default is @p TRUE. */ -#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) -#define CH_USE_MEMCORE TRUE -#endif +#define CH_CFG_USE_MEMCORE TRUE /** * @brief Heap Allocator APIs. @@ -347,27 +285,11 @@ extern "C" * in the kernel. * * @note The default is @p TRUE. - * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. * @note Mutexes are recommended. */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) -#define CH_USE_HEAP TRUE -#endif - -/** - * @brief C-runtime allocator. - * @details If enabled the the heap allocator APIs just wrap the C-runtime - * @p malloc() and @p free() functions. - * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the - * appropriate documentation. - */ -#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) -#define CH_USE_MALLOC_HEAP FALSE -#endif +#define CH_CFG_USE_HEAP TRUE /** * @brief Memory Pools Allocator APIs. @@ -376,9 +298,7 @@ extern "C" * * @note The default is @p TRUE. */ -#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) -#define CH_USE_MEMPOOLS TRUE -#endif +#define CH_CFG_USE_MEMPOOLS TRUE /** * @brief Dynamic Threads APIs. @@ -386,12 +306,10 @@ extern "C" * in the kernel. * * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. - * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. */ -#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) -#define CH_USE_DYNAMIC FALSE -#endif +#define CH_CFG_USE_DYNAMIC TRUE /** @} */ @@ -402,6 +320,13 @@ extern "C" */ /*===========================================================================*/ +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS TRUE + /** * @brief Debug option, system state check. * @details If enabled the correct call protocol for system APIs is checked @@ -409,9 +334,7 @@ extern "C" * * @note The default is @p FALSE. */ -#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_SYSTEM_STATE_CHECK TRUE -#endif +#define CH_DBG_SYSTEM_STATE_CHECK TRUE /** * @brief Debug option, parameters checks. @@ -420,9 +343,7 @@ extern "C" * * @note The default is @p FALSE. */ -#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS TRUE -#endif +#define CH_DBG_ENABLE_CHECKS TRUE /** * @brief Debug option, consistency checks. @@ -432,9 +353,7 @@ extern "C" * * @note The default is @p FALSE. */ -#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS TRUE -#endif +#define CH_DBG_ENABLE_ASSERTS TRUE /** * @brief Debug option, trace buffer. @@ -443,9 +362,7 @@ extern "C" * * @note The default is @p FALSE. */ -#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE TRUE -#endif +#define CH_DBG_ENABLE_TRACE TRUE /** * @brief Debug option, stack checks. @@ -457,9 +374,7 @@ extern "C" * @note The default failure mode is to halt the system with the global * @p panic_msg variable set to @p NULL. */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK TRUE -#endif +#define CH_DBG_ENABLE_STACK_CHECK TRUE /** * @brief Debug option, stacks initialization. @@ -469,22 +384,18 @@ extern "C" * * @note The default is @p FALSE. */ -#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS TRUE -#endif +#define CH_DBG_FILL_THREADS TRUE /** * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p Thread structure that + * @details If enabled then a field is added to the @p thread_t structure that * counts the system ticks occurred while executing the thread. * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. */ -#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING TRUE -#endif +#define CH_DBG_THREADS_PROFILING FALSE /** @} */ @@ -497,14 +408,12 @@ extern "C" /** * @brief Threads descriptor structure extension. - * @details User fields added to the end of the @p Thread structure. + * @details User fields added to the end of the @p thread_t structure. */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ - void *activeStack; \ - int remainingStack; \ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + void *activeStack; \ + int remainingStack; \ /* Add threads custom fields here.*/ -#endif /** * @brief Threads initialization hook. @@ -513,11 +422,9 @@ extern "C" * @note It is invoked from within @p chThdInit() and implicitly from all * the threads creation APIs. */ -#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT_HOOK(tp) { \ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ /* Add threads initialization code here.*/ \ } -#endif /** * @brief Threads finalization hook. @@ -527,61 +434,61 @@ extern "C" * @note It is also invoked when the threads simply return in order to * terminate. */ -#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT_HOOK(tp) { \ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ /* Add threads finalization code here.*/ \ } -#endif /** * @brief Context switch hook. * @details This hook is invoked just before switching between threads. */ -#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) -#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ - /* System halt code here.*/ \ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ } -#endif /** * @brief Idle Loop hook. * @details This hook is continuously invoked by the idle thread loop. */ -#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ +#define CH_CFG_IDLE_LOOP_HOOK() { \ /* Idle loop code here.*/ \ } -#endif /** * @brief System tick event hook. * @details This hook is invoked in the system tick handler immediately * after processing the virtual timers queue. */ -#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) -#define SYSTEM_TICK_EVENT_HOOK() { \ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ /* System tick event code here.*/ \ } -#endif /** * @brief System halt hook. * @details This hook is invoked in case to a system halting error before * the system is halted. */ -#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) -#if CH_DBG_ENABLED - -#define SYSTEM_HALT_HOOK() { \ - print("FATAL %s\r\n", dbg_panic_msg); \ - chThdSleepMilliseconds(100); \ -/* System halt code here.*/ \ - +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ } -#endif - -#endif - /** @} */ @@ -589,7 +496,11 @@ extern "C" /* Port-specific settings (override port settings defaulted in chcore.h). */ /*===========================================================================*/ -#define CORTEX_USE_FPU TRUE +#if !CH_DBG_SYSTEM_STATE_CHECK +extern cnt_t dbg_lock_cnt; +#define dbg_enter_lock() {dbg_lock_cnt = 1;ON_LOCK_HOOK;} +#define dbg_leave_lock() {ON_UNLOCK_HOOK;dbg_lock_cnt = 0;} +#endif #endif /* _CHCONF_H_ */ diff --git a/firmware/config/stm32f4ems/halconf.h b/firmware/config/stm32f4ems/halconf.h index 97e7abd8a8..219171e449 100644 --- a/firmware/config/stm32f4ems/halconf.h +++ b/firmware/config/stm32f4ems/halconf.h @@ -1,28 +1,17 @@ /* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012 Giovanni Di Sirio. + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - This file is part of ChibiOS/RT. + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. + http://www.apache.org/licenses/LICENSE-2.0 - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. */ /** @@ -41,13 +30,6 @@ #include "mcuconf.h" -/** - * @brief Enables the TM subsystem. - */ -#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) -#define HAL_USE_TM FALSE -#endif - /** * @brief Enables the PAL subsystem. */ @@ -69,6 +51,13 @@ #define HAL_USE_CAN TRUE #endif +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + /** * @brief Enables the EXT subsystem. */ @@ -90,6 +79,13 @@ #define HAL_USE_I2C TRUE #endif +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + /** * @brief Enables the ICU subsystem. */ @@ -167,6 +163,13 @@ #define HAL_USE_USB TRUE #endif +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + /*===========================================================================*/ /* ADC driver related settings. */ /*===========================================================================*/ @@ -213,6 +216,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + /** * @brief Enables an event sources for incoming packets. */ @@ -224,13 +234,6 @@ /* MMC_SPI driver related settings. */ /*===========================================================================*/ -/** - * @brief Block size for MMC transfers. - */ -#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) -#define MMC_SECTOR_SIZE 512 -#endif - /** * @brief Delays insertions. * @details If enabled this options inserts delays into the MMC waiting @@ -243,32 +246,6 @@ #define MMC_NICE_WAITING TRUE #endif -/** - * @brief Number of positive insertion queries before generating the - * insertion event. - */ -#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) -#define MMC_POLLING_INTERVAL 10 -#endif - -/** - * @brief Interval, in milliseconds, between insertion queries. - */ -#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) -#define MMC_POLLING_DELAY 10 -#endif - -/** - * @brief Uses the SPI polled API for small data transfers. - * @details Polled transfers usually improve performance because it - * saves two context switches and interrupt servicing. Note - * that this option has no effect on large transfers which - * are always performed using DMAs/IRQs. - */ -#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) -#define MMC_USE_SPI_POLLING TRUE -#endif - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ @@ -317,13 +294,36 @@ * @brief Serial buffers size. * @details Configuration parameter, you can change the depth of the queue * buffers depending on the requirements of your application. - * @note The default is 64 bytes for both the transmission and receive + * @note The default is 16 bytes for both the transmission and receive * buffers. */ #if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) #define SERIAL_BUFFERS_SIZE 16 #endif +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + /*===========================================================================*/ /* SPI driver related settings. */ /*===========================================================================*/ @@ -344,6 +344,38 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/firmware/config/stm32f4ems/mcuconf.h b/firmware/config/stm32f4ems/mcuconf.h index 5202f4266b..f62e82893a 100644 --- a/firmware/config/stm32f4ems/mcuconf.h +++ b/firmware/config/stm32f4ems/mcuconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -14,6 +14,16 @@ limitations under the License. */ +#ifndef _MCUCONF_H_ +#define _MCUCONF_H_ + +#include "efifeatures.h" +#include "rusefi_enums.h" + +#define SCHEDULING_TIMER_PRIORITY 4 + +#define ICU_PRIORITY 3 + /* * STM32F4xx drivers configuration. * The following settings override the default settings present in @@ -30,13 +40,6 @@ #define STM32F4xx_MCUCONF -#include "efifeatures.h" -#include "rusefi_enums.h" - -#define SCHEDULING_TIMER_PRIORITY 4 - -#define ICU_PRIORITY 3 - /* * HAL driver system settings. */ @@ -44,29 +47,18 @@ #define STM32_HSI_ENABLED TRUE #define STM32_LSI_ENABLED TRUE #define STM32_HSE_ENABLED TRUE - -// change this 'FALSE to TRUE if you have the LSE 32768 quarts -#define STM32_LSE_ENABLED TRUE - +#define STM32_LSE_ENABLED FALSE #define STM32_CLOCK48_REQUIRED TRUE #define STM32_SW STM32_SW_PLL #define STM32_PLLSRC STM32_PLLSRC_HSE -#ifdef OLIMEX_STM32_E407 -#define STM32_PLLM_VALUE 12 -#else #define STM32_PLLM_VALUE 8 -#endif #define STM32_PLLN_VALUE 336 #define STM32_PLLP_VALUE 2 #define STM32_PLLQ_VALUE 7 #define STM32_HPRE STM32_HPRE_DIV1 #define STM32_PPRE1 STM32_PPRE1_DIV4 #define STM32_PPRE2 STM32_PPRE2_DIV2 -#if STM32_LSE_ENABLED - #define STM32_RTCSEL STM32_RTCSEL_LSE -#else - #define STM32_RTCSEL STM32_RTCSEL_LSI -#endif +#define STM32_RTCSEL STM32_RTCSEL_LSI #define STM32_RTCPRE_VALUE 8 #define STM32_MCO1SEL STM32_MCO1SEL_HSI #define STM32_MCO1PRE STM32_MCO1PRE_DIV1 @@ -75,16 +67,16 @@ #define STM32_I2SSRC STM32_I2SSRC_CKIN #define STM32_PLLI2SN_VALUE 192 #define STM32_PLLI2SR_VALUE 5 -//#define STM32_VOS STM32_VOS_HIGH #define STM32_PVD_ENABLE FALSE #define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE /* * ADC driver system settings. */ #define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 -#define STM32_ADC_USE_ADC1 TRUE // slow ADC -#define STM32_ADC_USE_ADC2 TRUE // fast ADC +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_ADC2 TRUE #define STM32_ADC_USE_ADC3 FALSE #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) #define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) @@ -105,6 +97,19 @@ #define STM32_CAN_CAN1_IRQ_PRIORITY 11 #define STM32_CAN_CAN2_IRQ_PRIORITY 11 +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + /* * EXT driver system settings. */ @@ -142,7 +147,7 @@ #define STM32_GPT_TIM2_IRQ_PRIORITY 7 #define STM32_GPT_TIM3_IRQ_PRIORITY 7 #define STM32_GPT_TIM4_IRQ_PRIORITY 7 -#define STM32_GPT_TIM5_IRQ_PRIORITY SCHEDULING_TIMER_PRIORITY +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 #define STM32_GPT_TIM6_IRQ_PRIORITY 7 #define STM32_GPT_TIM7_IRQ_PRIORITY 7 #define STM32_GPT_TIM8_IRQ_PRIORITY 7 @@ -157,7 +162,8 @@ #define STM32_I2C_USE_I2C1 TRUE #define STM32_I2C_USE_I2C2 FALSE #define STM32_I2C_USE_I2C3 FALSE -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) @@ -169,28 +175,40 @@ #define STM32_I2C_I2C1_DMA_PRIORITY 3 #define STM32_I2C_I2C2_DMA_PRIORITY 3 #define STM32_I2C_I2C3_DMA_PRIORITY 3 -#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() -#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() -#define STM32_I2C_I2C3_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * I2S driver system settings. + */ +#define STM32_I2S_USE_SPI2 FALSE +#define STM32_I2S_USE_SPI3 FALSE +#define STM32_I2S_SPI2_IRQ_PRIORITY 10 +#define STM32_I2S_SPI3_IRQ_PRIORITY 10 +#define STM32_I2S_SPI2_DMA_PRIORITY 1 +#define STM32_I2S_SPI3_DMA_PRIORITY 1 +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") /* * ICU driver system settings. */ -#define STM32_ICU_USE_TIM1 TRUE // wave input -#define STM32_ICU_USE_TIM2 TRUE // primary position sensor -#define STM32_ICU_USE_TIM3 TRUE // secondary position sensor +#define STM32_ICU_USE_TIM1 TRUE +#define STM32_ICU_USE_TIM2 TRUE +#define STM32_ICU_USE_TIM3 TRUE #define STM32_ICU_USE_TIM4 FALSE #define STM32_ICU_USE_TIM5 FALSE #define STM32_ICU_USE_TIM8 FALSE -#define STM32_ICU_USE_TIM9 TRUE // wave input - -#define STM32_ICU_TIM1_IRQ_PRIORITY ICU_PRIORITY -#define STM32_ICU_TIM2_IRQ_PRIORITY ICU_PRIORITY -#define STM32_ICU_TIM3_IRQ_PRIORITY ICU_PRIORITY -#define STM32_ICU_TIM4_IRQ_PRIORITY ICU_PRIORITY -#define STM32_ICU_TIM5_IRQ_PRIORITY ICU_PRIORITY -#define STM32_ICU_TIM8_IRQ_PRIORITY ICU_PRIORITY -#define STM32_ICU_TIM9_IRQ_PRIORITY ICU_PRIORITY +#define STM32_ICU_USE_TIM9 TRUE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 /* * MAC driver system settings. @@ -203,18 +221,17 @@ #define STM32_MAC_ETH1_IRQ_PRIORITY 13 #define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 -#define STM32_PWM_USE_TIM1 FALSE -#define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_USE_TIM4 TRUE // fast adc -#define STM32_PWM_USE_TIM5 FALSE -#define STM32_PWM_USE_TIM8 TRUE // slow adc -#define STM32_PWM_USE_TIM9 FALSE - /* * PWM driver system settings. */ #define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 TRUE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 TRUE +#define STM32_PWM_USE_TIM9 FALSE #define STM32_PWM_TIM1_IRQ_PRIORITY 7 #define STM32_PWM_TIM2_IRQ_PRIORITY 7 #define STM32_PWM_TIM3_IRQ_PRIORITY 7 @@ -223,6 +240,17 @@ #define STM32_PWM_TIM8_IRQ_PRIORITY 7 #define STM32_PWM_TIM9_IRQ_PRIORITY 7 +/* + * SDC driver system settings. + */ +#define STM32_SDC_SDIO_DMA_PRIORITY 3 +#define STM32_SDC_SDIO_IRQ_PRIORITY 9 +#define STM32_SDC_WRITE_TIMEOUT_MS 250 +#define STM32_SDC_READ_TIMEOUT_MS 25 +#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 +#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) + /* * SERIAL driver system settings. */ @@ -243,8 +271,8 @@ * SPI driver system settings. */ #define STM32_SPI_USE_SPI1 TRUE -#define STM32_SPI_USE_SPI2 TRUE // external ADC -#define STM32_SPI_USE_SPI3 TRUE // potentiometer +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 TRUE #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) @@ -257,7 +285,13 @@ #define STM32_SPI_SPI1_IRQ_PRIORITY 10 #define STM32_SPI_SPI2_IRQ_PRIORITY 10 #define STM32_SPI_SPI3_IRQ_PRIORITY 10 -#define STM32_SPI_DMA_ERROR_HOOK(spip) chDbgCheck(TRUE, "STM32_SPI_DMA_ERROR_HOOK") +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 /* * UART driver system settings. @@ -265,6 +299,8 @@ #define STM32_UART_USE_USART1 FALSE #define STM32_UART_USE_USART2 FALSE #define STM32_UART_USE_USART3 TRUE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE #define STM32_UART_USE_USART6 FALSE #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) @@ -272,17 +308,25 @@ #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART1_IRQ_PRIORITY 12 #define STM32_UART_USART2_IRQ_PRIORITY 12 #define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 #define STM32_UART_USART6_IRQ_PRIORITY 12 #define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0 #define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 #define STM32_UART_USART6_DMA_PRIORITY 0 -#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") /* * USB driver system settings. @@ -294,5 +338,12 @@ #define STM32_USB_OTG1_RX_FIFO_SIZE 512 #define STM32_USB_OTG2_RX_FIFO_SIZE 1024 #define STM32_USB_OTG_THREAD_PRIO LOWPRIO -#define STM32_USB_OTG_THREAD_STACK_SIZE 1024 +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 #define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +#endif /* _MCUCONF_H_ */ diff --git a/firmware/console/binary/tunerstudio_io.cpp b/firmware/console/binary/tunerstudio_io.cpp index 29b0aff381..380305f87a 100644 --- a/firmware/console/binary/tunerstudio_io.cpp +++ b/firmware/console/binary/tunerstudio_io.cpp @@ -68,7 +68,7 @@ BaseChannel * getTsSerialDevice(void) { } void tunerStudioWriteData(ts_channel_s *tsChannel, const uint8_t * buffer, int size) { - efiAssertVoid(getRemainingStack(chThdSelf()) > 64, "tunerStudioWriteData"); + efiAssertVoid(getRemainingStack(chThdGetSelfX()) > 64, "tunerStudioWriteData"); #if EFI_SIMULATOR || defined(__DOXYGEN__) logMsg("chSequentialStreamWrite [%d]\r\n", size); #endif diff --git a/firmware/console/eficonsole.cpp b/firmware/console/eficonsole.cpp index 2cfcf79029..a7bf1a4c0b 100644 --- a/firmware/console/eficonsole.cpp +++ b/firmware/console/eficonsole.cpp @@ -32,7 +32,7 @@ static LoggingWithStorage logger("console"); static void myfatal(void) { - chDbgCheck(0, "my fatal"); + chDbgCheck(0); } static void myerror(void) { diff --git a/firmware/controllers/algo/error_handling.h b/firmware/controllers/algo/error_handling.h index 3f566b2c64..001c3c8f70 100644 --- a/firmware/controllers/algo/error_handling.h +++ b/firmware/controllers/algo/error_handling.h @@ -45,7 +45,7 @@ char *getFirmwareError(void); * so that it would not crash the error handler in case of stack issues */ #if CH_DBG_SYSTEM_STATE_CHECK -#define hasFatalError() (dbg_panic_msg != NULL) +#define hasFatalError() (ch.dbg.panic_msg != NULL) #else #define hasFatalError() (FALSE) #endif diff --git a/firmware/controllers/algo/obd_error_codes.h b/firmware/controllers/algo/obd_error_codes.h index 7b42fd465c..ac9cc8ecf7 100644 --- a/firmware/controllers/algo/obd_error_codes.h +++ b/firmware/controllers/algo/obd_error_codes.h @@ -1698,8 +1698,8 @@ typedef enum { CUSTOM_OBD_INJECTION_NO_PIN_ASSIGNED = 6020, CUSTOM_OBD_UNEXPECTED_INJECTION_MODE = 6021, CUSTOM_OBD_ANGLE_CONSTRAINT_VIOLATION = 6022, - CUSTOM_OBD_UNKNOWN_FIRING_ORDER = 6023, - CUSTOM_OBD_WRONG_FIRING_ORDER = 6024, + CUSTOM_OBD_23 = 6023, + CUSTOM_OBD_24 = 6024, CUSTOM_OBD_25 = 6025, CUSTOM_OBD_26 = 6026, CUSTOM_UNEXPECTED_ENGINE_TYPE = 6027, diff --git a/firmware/controllers/engine_controller.cpp b/firmware/controllers/engine_controller.cpp index a548b135a3..480b9d9ca6 100644 --- a/firmware/controllers/engine_controller.cpp +++ b/firmware/controllers/engine_controller.cpp @@ -149,13 +149,13 @@ efitick_t getTimeNowNt(void) { /** * number of SysClock ticks in one ms */ -#define TICKS_IN_MS (CH_FREQUENCY / 1000) +#define TICKS_IN_MS (CH_CFG_ST_FREQUENCY / 1000) // todo: this overflows pretty fast! efitimems_t currentTimeMillis(void) { // todo: migrate to getTimeNowUs? or not? - return chTimeNow() / TICKS_IN_MS; + return chVTGetSystemTimeX() / TICKS_IN_MS; } // todo: this overflows pretty fast! @@ -205,13 +205,13 @@ static void resetAccel(void) { } static void periodicSlowCallback(Engine *engine) { - efiAssertVoid(getRemainingStack(chThdSelf()) > 64, "lowStckOnEv"); + efiAssertVoid(getRemainingStack(chThdGetSelfX()) > 64, "lowStckOnEv"); #if EFI_PROD_CODE /** * We need to push current value into the 64 bit counter often enough so that we do not miss an overflow */ bool alreadyLocked = lockAnyContext(); - updateAndSet(&halTime.state, hal_lld_get_counter_value()); + updateAndSet(&halTime.state, port_rt_get_counter_value()); if (!alreadyLocked) { unlockAnyContext(); } diff --git a/firmware/controllers/error_handling.cpp b/firmware/controllers/error_handling.cpp index e2f32ff744..b58ed065a6 100644 --- a/firmware/controllers/error_handling.cpp +++ b/firmware/controllers/error_handling.cpp @@ -54,7 +54,7 @@ void chDbgPanic3(const char *msg, const char * file, int line) { dbg_panic_file = file; dbg_panic_line = line; #if CH_DBG_SYSTEM_STATE_CHECK || defined(__DOXYGEN__) - dbg_panic_msg = msg; + ch.dbg.panic_msg = msg; #endif /* CH_DBG_SYSTEM_STATE_CHECK */ #if EFI_PROD_CODE || defined(__DOXYGEN__) @@ -71,7 +71,7 @@ void chDbgPanic3(const char *msg, const char * file, int line) { if (!main_loop_started) { print("fatal %s %s:%d\r\n", msg, file, line); chThdSleepSeconds(1); - chSysHalt(); + chSysHalt("Main loop did not start"); } } diff --git a/firmware/controllers/lcd_controller.cpp b/firmware/controllers/lcd_controller.cpp index 7007d2f367..d786ef1395 100644 --- a/firmware/controllers/lcd_controller.cpp +++ b/firmware/controllers/lcd_controller.cpp @@ -117,13 +117,7 @@ void initLcdController(void) { } static char * prepareVBattMapLine(engine_configuration_s *engineConfiguration, char *buffer) { - char *ptr = buffer; - *ptr++ = 'V'; - ptr = ftoa(ptr, getVBatt(PASS_ENGINE_PARAMETER_F), 10.0f); - - ptr = appendStr(ptr, " M"); - ptr = ftoa(ptr, getRawMap(), 10.0f); - return ptr; + return buffer + chsnprintf(buffer, 23,"V%10.0f M%10.0f", getVBatt(PASS_ENGINE_PARAMETER_F), getRawMap()); } static char * prepareCltIatTpsLine(Engine *engine, char *buffer) { diff --git a/firmware/controllers/trigger/rpm_calculator.cpp b/firmware/controllers/trigger/rpm_calculator.cpp index 90f5af3bb9..c32033d94e 100644 --- a/firmware/controllers/trigger/rpm_calculator.cpp +++ b/firmware/controllers/trigger/rpm_calculator.cpp @@ -181,7 +181,7 @@ void rpmShaftPositionCallback(trigger_event_e ckpSignalType, efitick_t nowNt = getTimeNowNt(); engine->m.beforeRpmCb = GET_TIMESTAMP(); #if EFI_PROD_CODE - efiAssertVoid(getRemainingStack(chThdSelf()) > 256, "lowstck#2z"); + efiAssertVoid(getRemainingStack(chThdGetSelfX()) > 256, "lowstck#2z"); #endif #if EFI_SENSOR_CHART || defined(__DOXYGEN__) diff --git a/firmware/controllers/trigger/trigger_central.cpp b/firmware/controllers/trigger/trigger_central.cpp index 486d5cfc97..534a9229cb 100644 --- a/firmware/controllers/trigger/trigger_central.cpp +++ b/firmware/controllers/trigger/trigger_central.cpp @@ -170,7 +170,7 @@ void hwHandleShaftSignal(trigger_event_e signal) { if (triggerReentraint > maxTriggerReentraint) maxTriggerReentraint = triggerReentraint; triggerReentraint++; - efiAssertVoid(getRemainingStack(chThdSelf()) > 128, "lowstck#8"); + efiAssertVoid(getRemainingStack(chThdGetSelfX()) > 128, "lowstck#8"); engine->triggerCentral.handleShaftSignal(signal PASS_ENGINE_PARAMETER); triggerReentraint--; triggerDuration = GET_TIMESTAMP() - triggerHanlderEntryTime; diff --git a/firmware/controllers/trigger/trigger_decoder.cpp b/firmware/controllers/trigger/trigger_decoder.cpp index 95497836c3..2ffe65fe14 100644 --- a/firmware/controllers/trigger/trigger_decoder.cpp +++ b/firmware/controllers/trigger/trigger_decoder.cpp @@ -483,7 +483,7 @@ static TriggerState initState CCM_OPTIONAL; void TriggerShape::initializeTriggerShape(Logging *logger DECLARE_ENGINE_PARAMETER_S) { const trigger_config_s *triggerConfig = &engineConfiguration->trigger; #if EFI_PROD_CODE || defined(__DOXYGEN__) - efiAssertVoid(getRemainingStack(chThdSelf()) > 256, "init t"); + efiAssertVoid(getRemainingStack(chThdGetSelfX()) > 256, "init t"); scheduleMsg(logger, "initializeTriggerShape(%s/%d)", getTrigger_type_e(triggerConfig->type), (int) triggerConfig->type); #endif @@ -676,7 +676,7 @@ static void onFindIndex(TriggerState *state) { uint32_t findTriggerZeroEventIndex(TriggerState *state, TriggerShape * shape, trigger_config_s const*triggerConfig DECLARE_ENGINE_PARAMETER_S) { #if EFI_PROD_CODE || defined(__DOXYGEN__) - efiAssert(getRemainingStack(chThdSelf()) > 128, "findPos", -1); + efiAssert(getRemainingStack(chThdGetSelfX()) > 128, "findPos", -1); #endif isInitializingTrigger = true; errorDetection.clear(); diff --git a/firmware/controllers/trigger/trigger_structure.cpp b/firmware/controllers/trigger/trigger_structure.cpp index 28045d2667..fa8a4aacf2 100644 --- a/firmware/controllers/trigger/trigger_structure.cpp +++ b/firmware/controllers/trigger/trigger_structure.cpp @@ -44,7 +44,7 @@ TriggerShape::TriggerShape() : void TriggerShape::calculateTriggerSynchPoint(TriggerState *state DECLARE_ENGINE_PARAMETER_S) { #if EFI_PROD_CODE || defined(__DOXYGEN__) - efiAssertVoid(getRemainingStack(chThdSelf()) > 256, "calc s"); + efiAssertVoid(getRemainingStack(chThdGetSelfX()) > 256, "calc s"); #endif trigger_config_s const*triggerConfig = &engineConfiguration->trigger; diff --git a/firmware/ext/diskio.h b/firmware/ext/diskio.h index 9573e6ecc7..4d72b910a8 100644 --- a/firmware/ext/diskio.h +++ b/firmware/ext/diskio.h @@ -1,11 +1,16 @@ -/*----------------------------------------------------------------------- -/ Low level disk interface modlue include file +/*-----------------------------------------------------------------------/ +/ Low level disk interface modlue include file (C)ChaN, 2013 / /-----------------------------------------------------------------------*/ -#ifndef _DISKIO +#ifndef _DISKIO_DEFINED +#define _DISKIO_DEFINED -#define _READONLY 0 /* 1: Remove write functions */ -#define _USE_IOCTL 1 /* 1: Use disk_ioctl fucntion */ +#ifdef __cplusplus +extern "C" { +#endif + +#define _USE_WRITE 1 /* 1: Enable disk_write function */ +#define _USE_IOCTL 1 /* 1: Enable disk_ioctl fucntion */ #include "integer.h" @@ -26,15 +31,12 @@ typedef enum { /*---------------------------------------*/ /* Prototypes for disk control functions */ -int assign_drives (int, int); -DSTATUS disk_initialize (BYTE); -DSTATUS disk_status (BYTE); -DRESULT disk_read (BYTE, BYTE*, DWORD, BYTE); -#if _READONLY == 0 -DRESULT disk_write (BYTE, const BYTE*, DWORD, BYTE); -#endif -DRESULT disk_ioctl (BYTE, BYTE, void*); +DSTATUS disk_initialize (BYTE pdrv); +DSTATUS disk_status (BYTE pdrv); +DRESULT disk_read (BYTE pdrv, BYTE* buff, DWORD sector, UINT count); +DRESULT disk_write (BYTE pdrv, const BYTE* buff, DWORD sector, UINT count); +DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff); /* Disk Status Bits (DSTATUS) */ @@ -46,17 +48,18 @@ DRESULT disk_ioctl (BYTE, BYTE, void*); /* Command code for disk_ioctrl fucntion */ -/* Generic command (defined for FatFs) */ +/* Generic command (used by FatFs) */ #define CTRL_SYNC 0 /* Flush disk cache (for write functions) */ #define GET_SECTOR_COUNT 1 /* Get media size (for only f_mkfs()) */ #define GET_SECTOR_SIZE 2 /* Get sector size (for multiple sector size (_MAX_SS >= 1024)) */ #define GET_BLOCK_SIZE 3 /* Get erase block size (for only f_mkfs()) */ #define CTRL_ERASE_SECTOR 4 /* Force erased a block of sectors (for only _USE_ERASE) */ -/* Generic command */ +/* Generic command (not used by FatFs) */ #define CTRL_POWER 5 /* Get/Set power status */ #define CTRL_LOCK 6 /* Lock/Unlock media removal */ #define CTRL_EJECT 7 /* Eject media */ +#define CTRL_FORMAT 8 /* Create physical format on the media */ /* MMC/SDC specific ioctl command */ #define MMC_GET_TYPE 10 /* Get card type */ @@ -70,9 +73,8 @@ DRESULT disk_ioctl (BYTE, BYTE, void*); #define ATA_GET_MODEL 21 /* Get model name */ #define ATA_GET_SN 22 /* Get serial number */ -/* NAND specific ioctl command */ -#define NAND_FORMAT 30 /* Create physical format */ - - -#define _DISKIO +#ifdef __cplusplus +} +#endif + #endif diff --git a/firmware/ext/ff.h b/firmware/ext/ff.h index b1ff46527c..a93d9a2d4a 100644 --- a/firmware/ext/ff.h +++ b/firmware/ext/ff.h @@ -1,11 +1,11 @@ /*---------------------------------------------------------------------------/ -/ FatFs - FAT file system module include file R0.09 (C)ChaN, 2011 +/ FatFs - FAT file system module include file R0.10b (C)ChaN, 2014 /----------------------------------------------------------------------------/ / FatFs module is a generic FAT file system module for small embedded systems. / This is a free software that opened for education, research and commercial -/ developments under license policy of following trems. +/ developments under license policy of following terms. / -/ Copyright (C) 2011, ChaN, all right reserved. +/ Copyright (C) 2014, ChaN, all right reserved. / / * The FatFs module is a free software and there is NO WARRANTY. / * No restriction on use. You can use, modify and redistribute it for @@ -15,7 +15,7 @@ /----------------------------------------------------------------------------*/ #ifndef _FATFS -#define _FATFS 6502 /* Revision ID */ +#define _FATFS 8051 /* Revision ID */ #ifdef __cplusplus extern "C" { @@ -41,9 +41,9 @@ extern PARTITION VolToPart[]; /* Volume - Partition resolution table */ #define LD2PD(vol) (VolToPart[vol].pd) /* Get physical drive number */ #define LD2PT(vol) (VolToPart[vol].pt) /* Get partition index */ -#else /* Single partition configuration */ -#define LD2PD(vol) (vol) /* Each logical drive is bound to the same physical drive number */ -#define LD2PT(vol) 0 /* Always mounts the 1st partition or in SFD */ +#else /* Single partition configuration */ +#define LD2PD(vol) (BYTE)(vol) /* Each logical drive is bound to the same physical drive number */ +#define LD2PT(vol) 0 /* Find first valid partition or in SFD */ #endif @@ -53,7 +53,7 @@ extern PARTITION VolToPart[]; /* Volume - Partition resolution table */ #if _LFN_UNICODE /* Unicode string */ #if !_USE_LFN -#error _LFN_UNICODE must be 0 in non-LFN cfg. +#error _LFN_UNICODE must be 0 at non-LFN cfg. #endif #ifndef _INC_TCHAR typedef WCHAR TCHAR; @@ -78,12 +78,12 @@ typedef struct { BYTE fs_type; /* FAT sub-type (0:Not mounted) */ BYTE drv; /* Physical drive number */ BYTE csize; /* Sectors per cluster (1,2,4...128) */ - BYTE n_fats; /* Number of FAT copies (1,2) */ - BYTE wflag; /* win[] dirty flag (1:must be written back) */ - BYTE fsi_flag; /* fsinfo dirty flag (1:must be written back) */ + BYTE n_fats; /* Number of FAT copies (1 or 2) */ + BYTE wflag; /* win[] flag (b0:dirty) */ + BYTE fsi_flag; /* FSINFO flags (b7:disabled, b0:dirty) */ WORD id; /* File system mount ID */ WORD n_rootdir; /* Number of root directory entries (FAT12/16) */ -#if _MAX_SS != 512 +#if _MAX_SS != _MIN_SS WORD ssize; /* Bytes per sector (512, 1024, 2048 or 4096) */ #endif #if _FS_REENTRANT @@ -92,18 +92,18 @@ typedef struct { #if !_FS_READONLY DWORD last_clust; /* Last allocated cluster */ DWORD free_clust; /* Number of free clusters */ - DWORD fsi_sector; /* fsinfo sector (FAT32) */ #endif #if _FS_RPATH DWORD cdir; /* Current directory start cluster (0:root) */ #endif - DWORD n_fatent; /* Number of FAT entries (= number of clusters + 2) */ + DWORD n_fatent; /* Number of FAT entries, = number of clusters + 2 */ DWORD fsize; /* Sectors per FAT */ + DWORD volbase; /* Volume start sector */ DWORD fatbase; /* FAT start sector */ DWORD dirbase; /* Root directory start sector (FAT32:Cluster#) */ DWORD database; /* Data start sector */ DWORD winsect; /* Current sector appearing in the win[] */ - BYTE win[_MAX_SS]; /* Disk access window for Directory, FAT (and Data on tiny cfg) */ + BYTE win[_MAX_SS]; /* Disk access window for Directory, FAT (and file data at tiny cfg) */ } FATFS; @@ -111,27 +111,27 @@ typedef struct { /* File object structure (FIL) */ typedef struct { - FATFS* fs; /* Pointer to the owner file system object */ - WORD id; /* Owner file system mount ID */ - BYTE flag; /* File status flags */ - BYTE pad1; - DWORD fptr; /* File read/write pointer (0 on file open) */ + FATFS* fs; /* Pointer to the related file system object (**do not change order**) */ + WORD id; /* Owner file system mount ID (**do not change order**) */ + BYTE flag; /* Status flags */ + BYTE err; /* Abort flag (error code) */ + DWORD fptr; /* File read/write pointer (Zeroed on file open) */ DWORD fsize; /* File size */ - DWORD sclust; /* File start cluster (0 when fsize==0) */ - DWORD clust; /* Current cluster */ - DWORD dsect; /* Current data sector */ + DWORD sclust; /* File start cluster (0:no cluster chain, always 0 when fsize is 0) */ + DWORD clust; /* Current cluster of fpter (not valid when fprt is 0) */ + DWORD dsect; /* Sector number appearing in buf[] (0:invalid) */ #if !_FS_READONLY - DWORD dir_sect; /* Sector containing the directory entry */ - BYTE* dir_ptr; /* Ponter to the directory entry in the window */ + DWORD dir_sect; /* Sector number containing the directory entry */ + BYTE* dir_ptr; /* Pointer to the directory entry in the win[] */ #endif #if _USE_FASTSEEK - DWORD* cltbl; /* Pointer to the cluster link map table (null on file open) */ + DWORD* cltbl; /* Pointer to the cluster link map table (Nulled on file open) */ #endif -#if _FS_SHARE - UINT lockid; /* File lock ID (index of file semaphore table) */ +#if _FS_LOCK + UINT lockid; /* File lock ID origin from 1 (index of file semaphore table Files[]) */ #endif #if !_FS_TINY - BYTE buf[_MAX_SS]; /* File data read/write buffer */ + BYTE buf[_MAX_SS]; /* File private data read/write window */ #endif } FIL; @@ -140,14 +140,17 @@ typedef struct { /* Directory object structure (DIR) */ typedef struct { - FATFS* fs; /* Pointer to the owner file system object */ - WORD id; /* Owner file system mount ID */ + FATFS* fs; /* Pointer to the owner file system object (**do not change order**) */ + WORD id; /* Owner file system mount ID (**do not change order**) */ WORD index; /* Current read/write index number */ DWORD sclust; /* Table start cluster (0:Root dir) */ DWORD clust; /* Current cluster */ DWORD sect; /* Current sector */ BYTE* dir; /* Pointer to the current SFN entry in the win[] */ BYTE* fn; /* Pointer to the SFN (in/out) {file[8],ext[3],status[1]} */ +#if _FS_LOCK + UINT lockid; /* File lock ID (index of file semaphore table Files[]) */ +#endif #if _USE_LFN WCHAR* lfn; /* Pointer to the LFN working buffer */ WORD lfn_idx; /* Last matched LFN index number (0xFFFF:No LFN) */ @@ -176,14 +179,14 @@ typedef struct { typedef enum { FR_OK = 0, /* (0) Succeeded */ - FR_DISK_ERR, /* (1) A hard error occured in the low level disk I/O layer */ + FR_DISK_ERR, /* (1) A hard error occurred in the low level disk I/O layer */ FR_INT_ERR, /* (2) Assertion failed */ FR_NOT_READY, /* (3) The physical drive cannot work */ FR_NO_FILE, /* (4) Could not find the file */ FR_NO_PATH, /* (5) Could not find the path */ FR_INVALID_NAME, /* (6) The path name format is invalid */ - FR_DENIED, /* (7) Acces denied due to prohibited access or directory full */ - FR_EXIST, /* (8) Acces denied due to prohibited access */ + FR_DENIED, /* (7) Access denied due to prohibited access or directory full */ + FR_EXIST, /* (8) Access denied due to prohibited access */ FR_INVALID_OBJECT, /* (9) The file/directory object is invalid */ FR_WRITE_PROTECTED, /* (10) The physical drive is write protected */ FR_INVALID_DRIVE, /* (11) The logical drive number is invalid */ @@ -191,7 +194,7 @@ typedef enum { FR_NO_FILESYSTEM, /* (13) There is no valid FAT volume */ FR_MKFS_ABORTED, /* (14) The f_mkfs() aborted due to any parameter error */ FR_TIMEOUT, /* (15) Could not get a grant to access the volume within defined period */ - FR_LOCKED, /* (16) The operation is rejected according to the file shareing policy */ + FR_LOCKED, /* (16) The operation is rejected according to the file sharing policy */ FR_NOT_ENOUGH_CORE, /* (17) LFN working buffer could not be allocated */ FR_TOO_MANY_OPEN_FILES, /* (18) Number of open files > _FS_SHARE */ FR_INVALID_PARAMETER /* (19) Given parameter is invalid */ @@ -202,36 +205,39 @@ typedef enum { /*--------------------------------------------------------------*/ /* FatFs module application interface */ -FRESULT f_mount (BYTE, FATFS*); /* Mount/Unmount a logical drive */ -FRESULT f_open (FIL*, const TCHAR*, BYTE); /* Open or create a file */ -FRESULT f_read (FIL*, void*, UINT, UINT*); /* Read data from a file */ -FRESULT f_lseek (FIL*, DWORD); /* Move file pointer of a file object */ -FRESULT f_close (FIL*); /* Close an open file object */ -FRESULT f_opendir (DIR*, const TCHAR*); /* Open an existing directory */ -FRESULT f_readdir (DIR*, FILINFO*); /* Read a directory item */ -FRESULT f_stat (const TCHAR*, FILINFO*); /* Get file status */ -FRESULT f_write (FIL*, const void*, UINT, UINT*); /* Write data to a file */ -FRESULT f_getfree (const TCHAR*, DWORD*, FATFS**); /* Get number of free clusters on the drive */ -FRESULT f_truncate (FIL*); /* Truncate file */ -FRESULT f_sync (FIL*); /* Flush cached data of a writing file */ -FRESULT f_unlink (const TCHAR*); /* Delete an existing file or directory */ -FRESULT f_mkdir (const TCHAR*); /* Create a new directory */ -FRESULT f_chmod (const TCHAR*, BYTE, BYTE); /* Change attriburte of the file/dir */ -FRESULT f_utime (const TCHAR*, const FILINFO*); /* Change timestamp of the file/dir */ -FRESULT f_rename (const TCHAR*, const TCHAR*); /* Rename/Move a file or directory */ -FRESULT f_chdrive (BYTE); /* Change current drive */ -FRESULT f_chdir (const TCHAR*); /* Change current directory */ -FRESULT f_getcwd (TCHAR*, UINT); /* Get current directory */ -FRESULT f_forward (FIL*, UINT(*)(const BYTE*,UINT), UINT, UINT*); /* Forward data to the stream */ -FRESULT f_mkfs (BYTE, BYTE, UINT); /* Create a file system on the drive */ -FRESULT f_fdisk (BYTE, const DWORD[], void*); /* Divide a physical drive into some partitions */ -int f_putc (TCHAR, FIL*); /* Put a character to the file */ -int f_puts (const TCHAR*, FIL*); /* Put a string to the file */ -int f_printf (FIL*, const TCHAR*, ...); /* Put a formatted string to the file */ -TCHAR* f_gets (TCHAR*, int, FIL*); /* Get a string from the file */ +FRESULT f_open (FIL* fp, const TCHAR* path, BYTE mode); /* Open or create a file */ +FRESULT f_close (FIL* fp); /* Close an open file object */ +FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br); /* Read data from a file */ +FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw); /* Write data to a file */ +FRESULT f_forward (FIL* fp, UINT(*func)(const BYTE*,UINT), UINT btf, UINT* bf); /* Forward data to the stream */ +FRESULT f_lseek (FIL* fp, DWORD ofs); /* Move file pointer of a file object */ +FRESULT f_truncate (FIL* fp); /* Truncate file */ +FRESULT f_sync (FIL* fp); /* Flush cached data of a writing file */ +FRESULT f_opendir (DIR* dp, const TCHAR* path); /* Open a directory */ +FRESULT f_closedir (DIR* dp); /* Close an open directory */ +FRESULT f_readdir (DIR* dp, FILINFO* fno); /* Read a directory item */ +FRESULT f_mkdir (const TCHAR* path); /* Create a sub directory */ +FRESULT f_unlink (const TCHAR* path); /* Delete an existing file or directory */ +FRESULT f_rename (const TCHAR* path_old, const TCHAR* path_new); /* Rename/Move a file or directory */ +FRESULT f_stat (const TCHAR* path, FILINFO* fno); /* Get file status */ +FRESULT f_chmod (const TCHAR* path, BYTE value, BYTE mask); /* Change attribute of the file/dir */ +FRESULT f_utime (const TCHAR* path, const FILINFO* fno); /* Change times-tamp of the file/dir */ +FRESULT f_chdir (const TCHAR* path); /* Change current directory */ +FRESULT f_chdrive (const TCHAR* path); /* Change current drive */ +FRESULT f_getcwd (TCHAR* buff, UINT len); /* Get current directory */ +FRESULT f_getfree (const TCHAR* path, DWORD* nclst, FATFS** fatfs); /* Get number of free clusters on the drive */ +FRESULT f_getlabel (const TCHAR* path, TCHAR* label, DWORD* vsn); /* Get volume label */ +FRESULT f_setlabel (const TCHAR* label); /* Set volume label */ +FRESULT f_mount (FATFS* fs, const TCHAR* path, BYTE opt); /* Mount/Unmount a logical drive */ +FRESULT f_mkfs (const TCHAR* path, BYTE sfd, UINT au); /* Create a file system on the volume */ +FRESULT f_fdisk (BYTE pdrv, const DWORD szt[], void* work); /* Divide a physical drive into some partitions */ +int f_putc (TCHAR c, FIL* fp); /* Put a character to the file */ +int f_puts (const TCHAR* str, FIL* cp); /* Put a string to the file */ +int f_printf (FIL* fp, const TCHAR* str, ...); /* Put a formatted string to the file */ +TCHAR* f_gets (TCHAR* buff, int len, FIL* fp); /* Get a string from the file */ #define f_eof(fp) (((fp)->fptr == (fp)->fsize) ? 1 : 0) -#define f_error(fp) (((fp)->flag & FA__ERROR) ? 1 : 0) +#define f_error(fp) ((fp)->err) #define f_tell(fp) ((fp)->fptr) #define f_size(fp) ((fp)->fsize) @@ -251,21 +257,21 @@ DWORD get_fattime (void); #endif /* Unicode support functions */ -#if _USE_LFN /* Unicode - OEM code conversion */ -WCHAR ff_convert (WCHAR, UINT); /* OEM-Unicode bidirectional conversion */ -WCHAR ff_wtoupper (WCHAR); /* Unicode upper-case conversion */ -#if _USE_LFN == 3 /* Memory functions */ -void* ff_memalloc (UINT); /* Allocate memory block */ -void ff_memfree (void*); /* Free memory block */ +#if _USE_LFN /* Unicode - OEM code conversion */ +WCHAR ff_convert (WCHAR chr, UINT dir); /* OEM-Unicode bidirectional conversion */ +WCHAR ff_wtoupper (WCHAR chr); /* Unicode upper-case conversion */ +#if _USE_LFN == 3 /* Memory functions */ +void* ff_memalloc (UINT msize); /* Allocate memory block */ +void ff_memfree (void* mblock); /* Free memory block */ #endif #endif /* Sync functions */ #if _FS_REENTRANT -int ff_cre_syncobj (BYTE, _SYNC_t*);/* Create a sync object */ -int ff_req_grant (_SYNC_t); /* Lock sync object */ -void ff_rel_grant (_SYNC_t); /* Unlock sync object */ -int ff_del_syncobj (_SYNC_t); /* Delete a sync object */ +int ff_cre_syncobj (BYTE vol, _SYNC_t* sobj); /* Create a sync object */ +int ff_req_grant (_SYNC_t sobj); /* Lock sync object */ +void ff_rel_grant (_SYNC_t sobj); /* Unlock sync object */ +int ff_del_syncobj (_SYNC_t sobj); /* Delete a sync object */ #endif @@ -279,7 +285,6 @@ int ff_del_syncobj (_SYNC_t); /* Delete a sync object */ #define FA_READ 0x01 #define FA_OPEN_EXISTING 0x00 -#define FA__ERROR 0x80 #if !_FS_READONLY #define FA_WRITE 0x02 diff --git a/firmware/ext/ffconf.h b/firmware/ext/ffconf.h index 0ba6d6ddf2..0f13b23297 100644 --- a/firmware/ext/ffconf.h +++ b/firmware/ext/ffconf.h @@ -2,41 +2,38 @@ #include "ch.h" /*---------------------------------------------------------------------------/ -/ FatFs - FAT file system module configuration file R0.09 (C)ChaN, 2011 -/----------------------------------------------------------------------------/ -/ -/ CAUTION! Do not forget to make clean the project after any changes to -/ the configuration options. -/ -/----------------------------------------------------------------------------*/ +/ FatFs - FAT file system module configuration file R0.10b (C)ChaN, 2014 +/---------------------------------------------------------------------------*/ + #ifndef _FFCONF -#define _FFCONF 6502 /* Revision ID */ +#define _FFCONF 8051 /* Revision ID */ /*---------------------------------------------------------------------------/ / Functions and Buffer Configurations -/----------------------------------------------------------------------------*/ +/---------------------------------------------------------------------------*/ #define _FS_TINY 0 /* 0:Normal or 1:Tiny */ -/* When _FS_TINY is set to 1, FatFs uses the sector buffer in the file system -/ object instead of the sector buffer in the individual file object for file -/ data transfer. This reduces memory consumption 512 bytes each file object. */ +/* When _FS_TINY is set to 1, it reduces memory consumption _MAX_SS bytes each +/ file object. For file data transfer, FatFs uses the common sector buffer in +/ the file system object (FATFS) instead of private sector buffer eliminated +/ from the file object (FIL). */ #define _FS_READONLY 0 /* 0:Read/Write or 1:Read only */ /* Setting _FS_READONLY to 1 defines read only configuration. This removes -/ writing functions, f_write, f_sync, f_unlink, f_mkdir, f_chmod, f_rename, -/ f_truncate and useless f_getfree. */ +/ writing functions, f_write(), f_sync(), f_unlink(), f_mkdir(), f_chmod(), +/ f_rename(), f_truncate() and useless f_getfree(). */ #define _FS_MINIMIZE 0 /* 0 to 3 */ -/* The _FS_MINIMIZE option defines minimization level to remove some functions. +/* The _FS_MINIMIZE option defines minimization level to remove API functions. / -/ 0: Full function. -/ 1: f_stat, f_getfree, f_unlink, f_mkdir, f_chmod, f_truncate and f_rename -/ are removed. -/ 2: f_opendir and f_readdir are removed in addition to 1. -/ 3: f_lseek is removed in addition to 2. */ +/ 0: All basic functions are enabled. +/ 1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_chmod(), f_utime(), +/ f_truncate() and f_rename() function are removed. +/ 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1. +/ 3: f_lseek() function is removed in addition to 2. */ #define _USE_STRFUNC 0 /* 0:Disable or 1-2:Enable */ @@ -44,27 +41,30 @@ #define _USE_MKFS 0 /* 0:Disable or 1:Enable */ -/* To enable f_mkfs function, set _USE_MKFS to 1 and set _FS_READONLY to 0 */ - - -#define _USE_FORWARD 1 /* 0:Disable or 1:Enable */ -/* To enable f_forward function, set _USE_FORWARD to 1 and set _FS_TINY to 1. */ +/* To enable f_mkfs() function, set _USE_MKFS to 1 and set _FS_READONLY to 0 */ #define _USE_FASTSEEK 0 /* 0:Disable or 1:Enable */ /* To enable fast seek feature, set _USE_FASTSEEK to 1. */ +#define _USE_LABEL 0 /* 0:Disable or 1:Enable */ +/* To enable volume label functions, set _USE_LAVEL to 1 */ + + +#define _USE_FORWARD 0 /* 0:Disable or 1:Enable */ +/* To enable f_forward() function, set _USE_FORWARD to 1 and set _FS_TINY to 1. */ + /*---------------------------------------------------------------------------/ / Locale and Namespace Configurations -/----------------------------------------------------------------------------*/ +/---------------------------------------------------------------------------*/ #define _CODE_PAGE 1251 /* The _CODE_PAGE specifies the OEM code page to be used on the target system. / Incorrect setting of the code page can cause a file open failure. / -/ 932 - Japanese Shift-JIS (DBCS, OEM, Windows) +/ 932 - Japanese Shift_JIS (DBCS, OEM, Windows) / 936 - Simplified Chinese GBK (DBCS, OEM, Windows) / 949 - Korean (DBCS, OEM, Windows) / 950 - Traditional Chinese Big5 (DBCS, OEM, Windows) @@ -89,105 +89,142 @@ / 857 - Turkish (OEM) / 862 - Hebrew (OEM) / 874 - Thai (OEM, Windows) -/ 1 - ASCII only (Valid for non LFN cfg.) -*/ +/ 1 - ASCII (Valid for only non-LFN configuration) */ #define _USE_LFN 3 /* 0 to 3 */ #define _MAX_LFN 255 /* Maximum LFN length to handle (12 to 255) */ -/* The _USE_LFN option switches the LFN support. +/* The _USE_LFN option switches the LFN feature. / -/ 0: Disable LFN feature. _MAX_LFN and _LFN_UNICODE have no effect. -/ 1: Enable LFN with static working buffer on the BSS. Always NOT reentrant. +/ 0: Disable LFN feature. _MAX_LFN has no effect. +/ 1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe. / 2: Enable LFN with dynamic working buffer on the STACK. / 3: Enable LFN with dynamic working buffer on the HEAP. / -/ The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes. To enable LFN, -/ Unicode handling functions ff_convert() and ff_wtoupper() must be added -/ to the project. When enable to use heap, memory control functions -/ ff_memalloc() and ff_memfree() must be added to the project. */ +/ When enable LFN feature, Unicode handling functions ff_convert() and ff_wtoupper() +/ function must be added to the project. +/ The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes. When use stack for the +/ working buffer, take care on stack overflow. When use heap memory for the working +/ buffer, memory management functions, ff_memalloc() and ff_memfree(), must be added +/ to the project. */ #define _LFN_UNICODE 0 /* 0:ANSI/OEM or 1:Unicode */ -/* To switch the character code set on FatFs API to Unicode, -/ enable LFN feature and set _LFN_UNICODE to 1. */ +/* To switch the character encoding on the FatFs API (TCHAR) to Unicode, enable LFN +/ feature and set _LFN_UNICODE to 1. This option affects behavior of string I/O +/ functions. This option must be 0 when LFN feature is not enabled. */ + + +#define _STRF_ENCODE 3 /* 0:ANSI/OEM, 1:UTF-16LE, 2:UTF-16BE, 3:UTF-8 */ +/* When Unicode API is enabled by _LFN_UNICODE option, this option selects the character +/ encoding on the file to be read/written via string I/O functions, f_gets(), f_putc(), +/ f_puts and f_printf(). This option has no effect when Unicode API is not enabled. */ #define _FS_RPATH 0 /* 0 to 2 */ /* The _FS_RPATH option configures relative path feature. / / 0: Disable relative path feature and remove related functions. -/ 1: Enable relative path. f_chdrive() and f_chdir() are available. -/ 2: f_getcwd() is available in addition to 1. +/ 1: Enable relative path. f_chdrive() and f_chdir() function are available. +/ 2: f_getcwd() function is available in addition to 1. / -/ Note that output of the f_readdir fnction is affected by this option. */ - +/ Note that output of the f_readdir() fnction is affected by this option. */ /*---------------------------------------------------------------------------/ -/ Physical Drive Configurations -/----------------------------------------------------------------------------*/ +/ Drive/Volume Configurations +/---------------------------------------------------------------------------*/ #define _VOLUMES 1 /* Number of volumes (logical drives) to be used. */ -#define _MAX_SS 512 /* 512, 1024, 2048 or 4096 */ -/* Maximum sector size to be handled. -/ Always set 512 for memory card and hard disk but a larger value may be -/ required for on-board flash memory, floppy disk and optical disk. -/ When _MAX_SS is larger than 512, it configures FatFs to variable sector size -/ and GET_SECTOR_SIZE command must be implememted to the disk_ioctl function. */ +#define _STR_VOLUME_ID 0 /* 0:Use only 0-9 for drive ID, 1:Use strings for drive ID */ +#define _VOLUME_STRS "RAM","NAND","CF","SD1","SD2","USB1","USB2","USB3" +/* When _STR_VOLUME_ID is set to 1, also pre-defined strings can be used as drive +/ number in the path name. _VOLUME_STRS defines the drive ID strings for each logical +/ drives. Number of items must be equal to _VOLUMES. Valid characters for the drive ID +/ strings are: 0-9 and A-Z. */ -#define _MULTI_PARTITION 0 /* 0:Single partition, 1/2:Enable multiple partition */ -/* When set to 0, each volume is bound to the same physical drive number and -/ it can mount only first primaly partition. When it is set to 1, each volume -/ is tied to the partitions listed in VolToPart[]. */ +#define _MULTI_PARTITION 0 /* 0:Single partition, 1:Enable multiple partition */ +/* By default(0), each logical drive number is bound to the same physical drive number +/ and only a FAT volume found on the physical drive is mounted. When it is set to 1, +/ each logical drive number is bound to arbitrary drive/partition listed in VolToPart[]. +*/ + + +#define _MIN_SS 512 +#define _MAX_SS 512 +/* These options configure the range of sector size to be supported. (512, 1024, 2048 or +/ 4096) Always set both 512 for most systems, all memory card and harddisk. But a larger +/ value may be required for on-board flash memory and some type of optical media. +/ When _MAX_SS is larger than _MIN_SS, FatFs is configured to variable sector size and +/ GET_SECTOR_SIZE command must be implemented to the disk_ioctl() function. */ #define _USE_ERASE 0 /* 0:Disable or 1:Enable */ -/* To enable sector erase feature, set _USE_ERASE to 1. CTRL_ERASE_SECTOR command -/ should be added to the disk_ioctl functio. */ +/* To enable sector erase feature, set _USE_ERASE to 1. Also CTRL_ERASE_SECTOR command +/ should be added to the disk_ioctl() function. */ + + +#define _FS_NOFSINFO 0 /* 0 to 3 */ +/* If you need to know correct free space on the FAT32 volume, set bit 0 of this option +/ and f_getfree() function at first time after volume mount will force a full FAT scan. +/ Bit 1 controls the last allocated cluster number as bit 0. +/ +/ bit0=0: Use free cluster count in the FSINFO if available. +/ bit0=1: Do not trust free cluster count in the FSINFO. +/ bit1=0: Use last allocated cluster number in the FSINFO if available. +/ bit1=1: Do not trust last allocated cluster number in the FSINFO. +*/ /*---------------------------------------------------------------------------/ / System Configurations -/----------------------------------------------------------------------------*/ +/---------------------------------------------------------------------------*/ -#define _WORD_ACCESS 0 /* 0 or 1 */ -/* Set 0 first and it is always compatible with all platforms. The _WORD_ACCESS -/ option defines which access method is used to the word data on the FAT volume. +#define _FS_LOCK 0 /* 0:Disable or >=1:Enable */ +/* To enable file lock control feature, set _FS_LOCK to non-zero value. +/ The value defines how many files/sub-directories can be opened simultaneously +/ with file lock control. This feature uses bss _FS_LOCK * 12 bytes. */ + + +#define _FS_REENTRANT 0 /* 0:Disable or 1:Enable */ +#define _FS_TIMEOUT MS2ST(1000) /* Timeout period in unit of time tick */ +#define _SYNC_t semaphore_t* /* O/S dependent sync object type. e.g. HANDLE, OS_EVENT*, ID, SemaphoreHandle_t and etc.. */ +/* The _FS_REENTRANT option switches the re-entrancy (thread safe) of the FatFs module. / -/ 0: Byte-by-byte access. -/ 1: Word access. Do not choose this unless following condition is met. -/ -/ When the byte order on the memory is big-endian or address miss-aligned word -/ access results incorrect behavior, the _WORD_ACCESS must be set to 0. -/ If it is not the case, the value can also be set to 1 to improve the -/ performance and code size. +/ 0: Disable re-entrancy. _FS_TIMEOUT and _SYNC_t have no effect. +/ 1: Enable re-entrancy. Also user provided synchronization handlers, +/ ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj() +/ function must be added to the project. */ -/* A header file that defines sync object types on the O/S, such as -/ windows.h, ucos_ii.h and semphr.h, must be included prior to ff.h. */ - -#define _FS_REENTRANT 0 /* 0:Disable or 1:Enable */ -#define _FS_TIMEOUT 1000 /* Timeout period in unit of time ticks */ -#define _SYNC_t Semaphore * /* O/S dependent type of sync object. e.g. HANDLE, OS_EVENT*, ID and etc.. */ - -/* The _FS_REENTRANT option switches the reentrancy (thread safe) of the FatFs module. +#define _WORD_ACCESS 0 /* 0 or 1 */ +/* The _WORD_ACCESS option is an only platform dependent option. It defines +/ which access method is used to the word data on the FAT volume. / -/ 0: Disable reentrancy. _SYNC_t and _FS_TIMEOUT have no effect. -/ 1: Enable reentrancy. Also user provided synchronization handlers, -/ ff_req_grant, ff_rel_grant, ff_del_syncobj and ff_cre_syncobj -/ function must be added to the project. */ +/ 0: Byte-by-byte access. Always compatible with all platforms. +/ 1: Word access. Do not choose this unless under both the following conditions. +/ +/ * Address misaligned memory access is always allowed for ALL instructions. +/ * Byte order on the memory is little-endian. +/ +/ If it is the case, _WORD_ACCESS can also be set to 1 to improve performance and +/ reduce code size. Following table shows an example of some processor types. +/ +/ ARM7TDMI 0 ColdFire 0 V850E2 0 +/ Cortex-M3 0 Z80 0/1 V850ES 0/1 +/ Cortex-M0 0 RX600(LE) 0/1 TLCS-870 0/1 +/ AVR 0/1 RX600(BE) 0 TLCS-900 0/1 +/ AVR32 0 RL78 0 R32C 0 +/ PIC18 0/1 SH-2 0 M16C 0/1 +/ PIC24 0 H8S 0 MSP430 0 +/ PIC32 0 H8/300H 0 x86 0/1 +*/ -#define _FS_SHARE 0 /* 0:Disable or >=1:Enable */ -/* To enable file shareing feature, set _FS_SHARE to 1 or greater. The value - defines how many files can be opened simultaneously. */ - - -#endif /* _FFCONFIG */ +#endif /* _FFCONF */ diff --git a/firmware/ext/ffconf_old.h b/firmware/ext/ffconf_old.h new file mode 100644 index 0000000000..0ba6d6ddf2 --- /dev/null +++ b/firmware/ext/ffconf_old.h @@ -0,0 +1,193 @@ +/* CHIBIOS FIX */ +#include "ch.h" + +/*---------------------------------------------------------------------------/ +/ FatFs - FAT file system module configuration file R0.09 (C)ChaN, 2011 +/----------------------------------------------------------------------------/ +/ +/ CAUTION! Do not forget to make clean the project after any changes to +/ the configuration options. +/ +/----------------------------------------------------------------------------*/ +#ifndef _FFCONF +#define _FFCONF 6502 /* Revision ID */ + + +/*---------------------------------------------------------------------------/ +/ Functions and Buffer Configurations +/----------------------------------------------------------------------------*/ + +#define _FS_TINY 0 /* 0:Normal or 1:Tiny */ +/* When _FS_TINY is set to 1, FatFs uses the sector buffer in the file system +/ object instead of the sector buffer in the individual file object for file +/ data transfer. This reduces memory consumption 512 bytes each file object. */ + + +#define _FS_READONLY 0 /* 0:Read/Write or 1:Read only */ +/* Setting _FS_READONLY to 1 defines read only configuration. This removes +/ writing functions, f_write, f_sync, f_unlink, f_mkdir, f_chmod, f_rename, +/ f_truncate and useless f_getfree. */ + + +#define _FS_MINIMIZE 0 /* 0 to 3 */ +/* The _FS_MINIMIZE option defines minimization level to remove some functions. +/ +/ 0: Full function. +/ 1: f_stat, f_getfree, f_unlink, f_mkdir, f_chmod, f_truncate and f_rename +/ are removed. +/ 2: f_opendir and f_readdir are removed in addition to 1. +/ 3: f_lseek is removed in addition to 2. */ + + +#define _USE_STRFUNC 0 /* 0:Disable or 1-2:Enable */ +/* To enable string functions, set _USE_STRFUNC to 1 or 2. */ + + +#define _USE_MKFS 0 /* 0:Disable or 1:Enable */ +/* To enable f_mkfs function, set _USE_MKFS to 1 and set _FS_READONLY to 0 */ + + +#define _USE_FORWARD 1 /* 0:Disable or 1:Enable */ +/* To enable f_forward function, set _USE_FORWARD to 1 and set _FS_TINY to 1. */ + + +#define _USE_FASTSEEK 0 /* 0:Disable or 1:Enable */ +/* To enable fast seek feature, set _USE_FASTSEEK to 1. */ + + + +/*---------------------------------------------------------------------------/ +/ Locale and Namespace Configurations +/----------------------------------------------------------------------------*/ + +#define _CODE_PAGE 1251 +/* The _CODE_PAGE specifies the OEM code page to be used on the target system. +/ Incorrect setting of the code page can cause a file open failure. +/ +/ 932 - Japanese Shift-JIS (DBCS, OEM, Windows) +/ 936 - Simplified Chinese GBK (DBCS, OEM, Windows) +/ 949 - Korean (DBCS, OEM, Windows) +/ 950 - Traditional Chinese Big5 (DBCS, OEM, Windows) +/ 1250 - Central Europe (Windows) +/ 1251 - Cyrillic (Windows) +/ 1252 - Latin 1 (Windows) +/ 1253 - Greek (Windows) +/ 1254 - Turkish (Windows) +/ 1255 - Hebrew (Windows) +/ 1256 - Arabic (Windows) +/ 1257 - Baltic (Windows) +/ 1258 - Vietnam (OEM, Windows) +/ 437 - U.S. (OEM) +/ 720 - Arabic (OEM) +/ 737 - Greek (OEM) +/ 775 - Baltic (OEM) +/ 850 - Multilingual Latin 1 (OEM) +/ 858 - Multilingual Latin 1 + Euro (OEM) +/ 852 - Latin 2 (OEM) +/ 855 - Cyrillic (OEM) +/ 866 - Russian (OEM) +/ 857 - Turkish (OEM) +/ 862 - Hebrew (OEM) +/ 874 - Thai (OEM, Windows) +/ 1 - ASCII only (Valid for non LFN cfg.) +*/ + + +#define _USE_LFN 3 /* 0 to 3 */ +#define _MAX_LFN 255 /* Maximum LFN length to handle (12 to 255) */ +/* The _USE_LFN option switches the LFN support. +/ +/ 0: Disable LFN feature. _MAX_LFN and _LFN_UNICODE have no effect. +/ 1: Enable LFN with static working buffer on the BSS. Always NOT reentrant. +/ 2: Enable LFN with dynamic working buffer on the STACK. +/ 3: Enable LFN with dynamic working buffer on the HEAP. +/ +/ The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes. To enable LFN, +/ Unicode handling functions ff_convert() and ff_wtoupper() must be added +/ to the project. When enable to use heap, memory control functions +/ ff_memalloc() and ff_memfree() must be added to the project. */ + + +#define _LFN_UNICODE 0 /* 0:ANSI/OEM or 1:Unicode */ +/* To switch the character code set on FatFs API to Unicode, +/ enable LFN feature and set _LFN_UNICODE to 1. */ + + +#define _FS_RPATH 0 /* 0 to 2 */ +/* The _FS_RPATH option configures relative path feature. +/ +/ 0: Disable relative path feature and remove related functions. +/ 1: Enable relative path. f_chdrive() and f_chdir() are available. +/ 2: f_getcwd() is available in addition to 1. +/ +/ Note that output of the f_readdir fnction is affected by this option. */ + + + +/*---------------------------------------------------------------------------/ +/ Physical Drive Configurations +/----------------------------------------------------------------------------*/ + +#define _VOLUMES 1 +/* Number of volumes (logical drives) to be used. */ + + +#define _MAX_SS 512 /* 512, 1024, 2048 or 4096 */ +/* Maximum sector size to be handled. +/ Always set 512 for memory card and hard disk but a larger value may be +/ required for on-board flash memory, floppy disk and optical disk. +/ When _MAX_SS is larger than 512, it configures FatFs to variable sector size +/ and GET_SECTOR_SIZE command must be implememted to the disk_ioctl function. */ + + +#define _MULTI_PARTITION 0 /* 0:Single partition, 1/2:Enable multiple partition */ +/* When set to 0, each volume is bound to the same physical drive number and +/ it can mount only first primaly partition. When it is set to 1, each volume +/ is tied to the partitions listed in VolToPart[]. */ + + +#define _USE_ERASE 0 /* 0:Disable or 1:Enable */ +/* To enable sector erase feature, set _USE_ERASE to 1. CTRL_ERASE_SECTOR command +/ should be added to the disk_ioctl functio. */ + + + +/*---------------------------------------------------------------------------/ +/ System Configurations +/----------------------------------------------------------------------------*/ + +#define _WORD_ACCESS 0 /* 0 or 1 */ +/* Set 0 first and it is always compatible with all platforms. The _WORD_ACCESS +/ option defines which access method is used to the word data on the FAT volume. +/ +/ 0: Byte-by-byte access. +/ 1: Word access. Do not choose this unless following condition is met. +/ +/ When the byte order on the memory is big-endian or address miss-aligned word +/ access results incorrect behavior, the _WORD_ACCESS must be set to 0. +/ If it is not the case, the value can also be set to 1 to improve the +/ performance and code size. +*/ + + +/* A header file that defines sync object types on the O/S, such as +/ windows.h, ucos_ii.h and semphr.h, must be included prior to ff.h. */ + +#define _FS_REENTRANT 0 /* 0:Disable or 1:Enable */ +#define _FS_TIMEOUT 1000 /* Timeout period in unit of time ticks */ +#define _SYNC_t Semaphore * /* O/S dependent type of sync object. e.g. HANDLE, OS_EVENT*, ID and etc.. */ + +/* The _FS_REENTRANT option switches the reentrancy (thread safe) of the FatFs module. +/ +/ 0: Disable reentrancy. _SYNC_t and _FS_TIMEOUT have no effect. +/ 1: Enable reentrancy. Also user provided synchronization handlers, +/ ff_req_grant, ff_rel_grant, ff_del_syncobj and ff_cre_syncobj +/ function must be added to the project. */ + + +#define _FS_SHARE 0 /* 0:Disable or >=1:Enable */ +/* To enable file shareing feature, set _FS_SHARE to 1 or greater. The value + defines how many files can be opened simultaneously. */ + + +#endif /* _FFCONFIG */ diff --git a/firmware/ext/readme.txt b/firmware/ext/readme.txt index fa761829a5..e76920959f 100644 --- a/firmware/ext/readme.txt +++ b/firmware/ext/readme.txt @@ -1 +1,158 @@ -In this folder we have 3rd party code \ No newline at end of file +FatFs Module Source Files R0.10b (C)ChaN, 2014 + + +FILES + + ffconf.h Configuration file for FatFs module. + ff.h Common include file for FatFs and application module. + ff.c FatFs module. + diskio.h Common include file for FatFs and disk I/O module. + diskio.c An example of glue function to attach existing disk I/O module to FatFs. + integer.h Integer type definitions for FatFs. + option Optional external functions. + + Low level disk I/O module is not included in this archive because the FatFs + module is only a generic file system layer and not depend on any specific + storage device. You have to provide a low level disk I/O module that written + to control your storage device. + + + +AGREEMENTS + + FatFs module is an open source software to implement FAT file system to + small embedded systems. This is a free software and is opened for education, + research and commercial developments under license policy of following trems. + + Copyright (C) 2014, ChaN, all right reserved. + + * The FatFs module is a free software and there is NO WARRANTY. + * No restriction on use. You can use, modify and redistribute it for + personal, non-profit or commercial product UNDER YOUR RESPONSIBILITY. + * Redistributions of source code must retain the above copyright notice. + + + +REVISION HISTORY + + Feb 26, 2006 R0.00 Prototype + + Apr 29, 2006 R0.01 First release. + + Jun 01, 2006 R0.02 Added FAT12. + Removed unbuffered mode. + Fixed a problem on small (<32M) patition. + + Jun 10, 2006 R0.02a Added a configuration option _FS_MINIMUM. + + Sep 22, 2006 R0.03 Added f_rename. + Changed option _FS_MINIMUM to _FS_MINIMIZE. + + Dec 11, 2006 R0.03a Improved cluster scan algolithm to write files fast. + Fixed f_mkdir creates incorrect directory on FAT32. + + Feb 04, 2007 R0.04 Supported multiple drive system. (FatFs) + Changed some APIs for multiple drive system. + Added f_mkfs. (FatFs) + Added _USE_FAT32 option. (Tiny-FatFs) + + Apr 01, 2007 R0.04a Supported multiple partitions on a plysical drive. (FatFs) + Fixed an endian sensitive code in f_mkfs. (FatFs) + Added a capability of extending the file size to f_lseek. + Added minimization level 3. + Fixed a problem that can collapse a sector when recreate an + existing file in any sub-directory at non FAT32 cfg. (Tiny-FatFs) + + May 05, 2007 R0.04b Added _USE_NTFLAG option. + Added FSInfo support. + Fixed some problems corresponds to FAT32. (Tiny-FatFs) + Fixed DBCS name can result FR_INVALID_NAME. + Fixed short seek (0 < ofs <= csize) collapses the file object. + + Aug 25, 2007 R0.05 Changed arguments of f_read, f_write. + Changed arguments of f_mkfs. (FatFs) + Fixed f_mkfs on FAT32 creates incorrect FSInfo. (FatFs) + Fixed f_mkdir on FAT32 creates incorrect directory. (FatFs) + + Feb 03, 2008 R0.05a Added f_truncate(). + Added f_utime(). + Fixed off by one error at FAT sub-type determination. + Fixed btr in f_read() can be mistruncated. + Fixed cached sector is not flushed when create and close without write. + + Apr 01, 2008 R0.06 Added f_forward(). (Tiny-FatFs) + Added string functions: fputc(), fputs(), fprintf() and fgets(). + Improved performance of f_lseek() on move to the same or following cluster. + + Apr 01, 2009, R0.07 Merged Tiny-FatFs as a buffer configuration option. + Added long file name support. + Added multiple code page support. + Added re-entrancy for multitask operation. + Added auto cluster size selection to f_mkfs(). + Added rewind option to f_readdir(). + Changed result code of critical errors. + Renamed string functions to avoid name collision. + + Apr 14, 2009, R0.07a Separated out OS dependent code on reentrant cfg. + Added multiple sector size support. + + Jun 21, 2009, R0.07c Fixed f_unlink() may return FR_OK on error. + Fixed wrong cache control in f_lseek(). + Added relative path feature. + Added f_chdir(). + Added f_chdrive(). + Added proper case conversion for extended characters. + + Nov 03, 2009 R0.07e Separated out configuration options from ff.h to ffconf.h. + Added a configuration option, _LFN_UNICODE. + Fixed f_unlink() fails to remove a sub-dir on _FS_RPATH. + Fixed name matching error on the 13 char boundary. + Changed f_readdir() to return the SFN with always upper case on non-LFN cfg. + + May 15, 2010, R0.08 Added a memory configuration option. (_USE_LFN) + Added file lock feature. (_FS_SHARE) + Added fast seek feature. (_USE_FASTSEEK) + Changed some types on the API, XCHAR->TCHAR. + Changed fname member in the FILINFO structure on Unicode cfg. + String functions support UTF-8 encoding files on Unicode cfg. + + Aug 16,'10 R0.08a Added f_getcwd(). (_FS_RPATH = 2) + Added sector erase feature. (_USE_ERASE) + Moved file lock semaphore table from fs object to the bss. + Fixed a wrong directory entry is created on non-LFN cfg when the given name contains ';'. + Fixed f_mkfs() creates wrong FAT32 volume. + + Jan 15,'11 R0.08b Fast seek feature is also applied to f_read() and f_write(). + f_lseek() reports required table size on creating CLMP. + Extended format syntax of f_printf function. + Ignores duplicated directory separators in given path names. + + Sep 06,'11 R0.09 f_mkfs() supports multiple partition to finish the multiple partition feature. + Added f_fdisk(). (_MULTI_PARTITION = 2) + + Aug 27,'12 R0.09a Fixed assertion failure due to OS/2 EA on FAT12/16. + Changed f_open() and f_opendir() reject null object pointer to avoid crash. + Changed option name _FS_SHARE to _FS_LOCK. + + Jan 23,'13 R0.09b Added f_getlabel() and f_setlabel(). (_USE_LABEL) + + Oct 02,'13 R0.10 Added selection of character encoding on the file. (_STRF_ENCODE) + Added f_closedir(). + Added forced full FAT scan for f_getfree(). (_FS_NOFSINFO) + Added forced mount feature with changes of f_mount(). + Improved behavior of volume auto detection. + Improved write throughput of f_puts() and f_printf(). + Changed argument of f_chdrive(), f_mkfs(), disk_read() and disk_write(). + Fixed f_write() can be truncated when the file size is close to 4GB. + Fixed f_open(), f_mkdir() and f_setlabel() can return incorrect error code. + + Jan 15,'14 R0.10a Added arbitrary strings as drive number in the path name. (_STR_VOLUME_ID) + Added a configuration option of minimum sector size. (_MIN_SS) + 2nd argument of f_rename() can have a drive number and it will be ignored. + Fixed f_mount() with forced mount fails when drive number is >= 1. + Fixed f_close() invalidates the file object without volume lock. + Fixed f_closedir() returns but the volume lock is left acquired. + Fixed creation of an entry with LFN fails on too many SFN collisions. + + Mar 19,'14 R0.10b Fixed a hard error in the disk I/O layer can collapse the directory entry. + Fixed LFN entry is not deleted on delete/rename an object with lossy converted SFN. diff --git a/firmware/global.h b/firmware/global.h index 5f8a0715a1..132fbe1d60 100644 --- a/firmware/global.h +++ b/firmware/global.h @@ -8,8 +8,18 @@ #ifndef GLOBAL_H_ #define GLOBAL_H_ +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + #include #include + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + #include #define DEFAULT_ENGINE_TYPE CUSTOM_ENGINE @@ -48,31 +58,13 @@ typedef unsigned int time_t; #define EFI_ERROR_CODE 0xffffffff #if EFI_USE_CCM && defined __GNUC__ -#define CCM_OPTIONAL __attribute__((section(".ccm"))) +#define CCM_OPTIONAL __attribute__((section(".ram4"))) #elif defined __GNUC__ #define CCM_OPTIONAL #else -#define CCM_OPTIONAL @ ".ccm" +#define CCM_OPTIONAL @ ".ram4" #endif -// this stuff is about ChibiOS 2.6 > Migration -typedef VirtualTimer virtual_timer_t; -typedef EventListener event_listener_t; -typedef Thread thread_t; -typedef EventListener event_listener_t; -typedef EventSource event_source_t; -typedef VTList virtual_timers_list_t; -typedef VirtualTimer virtual_timer_t; -#define chSysLockFromISR chSysLockFromIsr -#define chSysUnlockFromISR chSysUnlockFromIsr -#define chThdGetSelfX chThdSelf - -#define HAL_SUCCESS CH_SUCCESS -#define HAL_FAILED CH_FAILED - -#define THD_WORKING_AREA WORKING_AREA -#define THD_FUNCTION(tname, arg) void tname(void *arg) - #if EFI_PROD_CODE || defined(__DOXYGEN__) /** @@ -128,5 +120,9 @@ typedef VirtualTimer virtual_timer_t; turnAllPinsOff(); \ enginePins.communicationPin.setValue(1); +/* + * Stack debugging + */ +int getRemainingStack(thread_t *otp); #endif /* GLOBAL_H_ */ diff --git a/firmware/hw_layer/HIP9011.cpp b/firmware/hw_layer/HIP9011.cpp index 45564009cf..b302ee10f7 100644 --- a/firmware/hw_layer/HIP9011.cpp +++ b/firmware/hw_layer/HIP9011.cpp @@ -194,7 +194,7 @@ void setHip9011FrankensoPinout(void) { // todo: convert this to rusEfi, hardware-independent enum engineConfiguration->spi2SckMode = PAL_STM32_OTYPE_OPENDRAIN; // 4 engineConfiguration->spi2MosiMode = PAL_STM32_OTYPE_OPENDRAIN; // 4 - engineConfiguration->spi2MisoMode = PAL_STM32_PUDR_PULLUP; // 32 + engineConfiguration->spi2MisoMode = PAL_STM32_PUPDR_PULLUP; // 32 boardConfiguration->hip9011Gain = 1; engineConfiguration->knockVThreshold = 4; diff --git a/firmware/hw_layer/can_hw.cpp b/firmware/hw_layer/can_hw.cpp index fa8c419ca6..b7f9607190 100644 --- a/firmware/hw_layer/can_hw.cpp +++ b/firmware/hw_layer/can_hw.cpp @@ -94,7 +94,7 @@ void sendMessage2(int size) { txmsg.DLC = size; // 1 second timeout msg_t result = canTransmit(&EFI_CAN_DEVICE, CAN_ANY_MAILBOX, &txmsg, MS2ST(1000)); - if (result == RDY_OK) { + if (result == MSG_OK) { canWriteOk++; } else { canWriteNotOk++; @@ -201,7 +201,7 @@ static void canInfoNBCBroadcast(can_nbc_e typeOfNBC) { static void canRead(void) { // scheduleMsg(&logger, "Waiting for CAN"); msg_t result = canReceive(&EFI_CAN_DEVICE, CAN_ANY_MAILBOX, &rxBuffer, MS2ST(1000)); - if (result == RDY_TIMEOUT) { + if (result == MSG_TIMEOUT) { return; } diff --git a/firmware/hw_layer/digital_input_hw.cpp b/firmware/hw_layer/digital_input_hw.cpp index 428f90b226..1b349a58ab 100644 --- a/firmware/hw_layer/digital_input_hw.cpp +++ b/firmware/hw_layer/digital_input_hw.cpp @@ -197,12 +197,12 @@ void startInputDriver(digital_input_s *hw, bool isActiveHigh) { if (driver != NULL) { if (hw->started) { - icuDisable(driver); + icuDisableNotificationsI(driver); icuStop(driver); } wave_icucfg.channel = getInputCaptureChannel(hw->brainPin); efiIcuStart(driver, &wave_icucfg); - icuEnable(driver); + icuEnableNotifications(driver); } hw->started = true; } diff --git a/firmware/hw_layer/hardware.cpp b/firmware/hw_layer/hardware.cpp index 4f020ae5e0..3563ca419b 100644 --- a/firmware/hw_layer/hardware.cpp +++ b/firmware/hw_layer/hardware.cpp @@ -54,7 +54,7 @@ EXTERN_ENGINE ; extern bool hasFirmwareErrorFlag; -static Mutex spiMtx; +static mutex_t spiMtx; int maxNesting = 0; @@ -70,13 +70,13 @@ bool rtcWorks = true; * Only one consumer can use SPI bus at a given time */ void lockSpi(spi_device_e device) { - efiAssertVoid(getRemainingStack(chThdSelf()) > 128, "lockSpi"); + efiAssertVoid(getRemainingStack(chThdGetSelfX()) > 128, "lockSpi"); // todo: different locks for different SPI devices! chMtxLock(&spiMtx); } void unlockSpi(void) { - chMtxUnlock(); + chMtxUnlock(&spiMtx); } static void initSpiModules(board_configuration_s *boardConfiguration) { @@ -155,7 +155,7 @@ extern int tpsFastAdc; * This method is not in the adc* lower-level file because it is more business logic then hardware. */ void adc_callback_fast(ADCDriver *adcp, adcsample_t *buffer, size_t n) { - efiAssertVoid(getRemainingStack(chThdSelf()) > 64, "lowstck12a"); + efiAssertVoid(getRemainingStack(chThdGetSelfX()) > 64, "lowstck12a"); (void) buffer; (void) n; @@ -167,7 +167,7 @@ void adc_callback_fast(ADCDriver *adcp, adcsample_t *buffer, size_t n) { /** * this callback is executed 10 000 times a second, it needs to be as fast as possible */ - efiAssertVoid(getRemainingStack(chThdSelf()) > 128, "lowstck#9b"); + efiAssertVoid(getRemainingStack(chThdGetSelfX()) > 128, "lowstck#9b"); #if EFI_MAP_AVERAGING mapAveragingCallback(fastAdc.samples[fastMapSampleIndex]); @@ -303,7 +303,7 @@ void showBor(void) { } void initHardware(Logging *l) { - efiAssertVoid(getRemainingStack(chThdSelf()) > 256, "init h"); + efiAssertVoid(getRemainingStack(chThdGetSelfX()) > 256, "init h"); sharedLogger = l; engine_configuration_s *engineConfiguration = engine->engineConfiguration; efiAssertVoid(engineConfiguration!=NULL, "engineConfiguration"); @@ -314,7 +314,7 @@ void initHardware(Logging *l) { // 10 extra seconds to re-flash the chip //flashProtect(); - chMtxInit(&spiMtx); + chMtxObjectInit(&spiMtx); #if EFI_HISTOGRAMS /** diff --git a/firmware/hw_layer/mass_storage/usb_msd.c b/firmware/hw_layer/mass_storage/usb_msd.c index 026fc77421..50ff41d560 100644 --- a/firmware/hw_layer/mass_storage/usb_msd.c +++ b/firmware/hw_layer/mass_storage/usb_msd.c @@ -31,8 +31,8 @@ #include "ch.h" #include "hal.h" #include "usb_msd.h" -#include "chprintf.h" #include "string.h" +#include "chprintf.h" #if HAL_USE_MASS_STORAGE_USB || defined(__DOXYGEN__) @@ -92,33 +92,21 @@ -static msg_t MassStorageUSBTransferThd(void *arg); -static msg_t MassStorageThd(void *arg); +static THD_FUNCTION(MassStorageUSBTransferThd, arg); +static THD_FUNCTION(MassStorageThd, arg); -static Thread *msdThd = NULL; -static Thread *msdUSBTransferThd = NULL; +static thread_t *msdThd = NULL; +static thread_t *msdUSBTransferThd = NULL; #define WAIT_ISR_SUCCESS 0 #define WAIT_ISR_BUSS_RESET_OR_RECONNECT 1 -static uint8_t msdWaitForISR(USBMassStorageDriver *msdp, const bool_t check_reset, const msd_wait_mode_t wait_mode); +static uint8_t msdWaitForISR(USBMassStorageDriver *msdp, const bool check_reset, const msd_wait_mode_t wait_mode); static void msdSetDefaultSenseKey(USBMassStorageDriver *msdp); #define BLOCK_SIZE_INCREMENT 512 #define BLOCK_WRITE_ITTERATION_COUNT 16 -#define MSD_START_TRANSMIT(msdp) \ - chSysLock(); \ - msdp->bulk_in_interupt_flag = false; \ - usbStartTransmitI(msdp->usbp, msdp->ms_ep_number); \ - chSysUnlock(); - - -#define MSD_START_RECEIVED(msdp) \ - chSysLock(); \ - msdp->bulk_out_interupt_flag = false; \ - usbStartReceiveI(msdp->usbp, msdp->ms_ep_number); \ - chSysUnlock(); typedef enum { MSD_USB_TRANSFER_STATUS_RUNNING = 0, @@ -176,13 +164,13 @@ void msdBulkInCallbackComplete(USBDriver *usbp, usbep_t ep) { if (ep > 0 && usbp->in_params[ep - 1] != NULL) { USBMassStorageDriver *msdp = (USBMassStorageDriver *)usbp->in_params[ep - 1]; - chSysLockFromIsr(); + chSysLockFromISR(); chBSemSignalI(&(msdp->bsem)); msdp->bulk_in_interupt_flag = true; - chSysUnlockFromIsr(); + chSysUnlockFromISR(); } } @@ -201,12 +189,12 @@ void msdBulkOutCallbackComplete(USBDriver *usbp, usbep_t ep) { if (ep > 0 && usbp->in_params[ep - 1] != NULL) { USBMassStorageDriver *msdp = (USBMassStorageDriver *)usbp->in_params[ep - 1]; - chSysLockFromIsr(); + chSysLockFromISR(); chBSemSignalI(&(msdp->bsem)); msdp->bulk_out_interupt_flag = true; - chSysUnlockFromIsr(); + chSysUnlockFromISR(); } } @@ -243,15 +231,15 @@ usb_msd_driver_state_t msdInit(USBDriver *usbp, BaseBlockDevice *bbdp, USBMassSt msdp->enable_media_removial = true; msdp->block_dev_info_valid_flag = false; - chEvtInit(&msdp->evt_connected); - chEvtInit(&msdp->evt_ejected); + chEvtObjectInit(&msdp->evt_connected); + chEvtObjectInit(&msdp->evt_ejected); /* Initialize binary semaphore as taken, will cause the thread to initially * wait on the */ - chBSemInit(&msdp->bsem, TRUE); + chBSemObjectInit(&msdp->bsem, TRUE); /* Initialize binary semaphore as NOT taken */ - chBSemInit(&msdp->usb_transfer_thread_bsem, FALSE); - chBSemInit(&msdp->mass_sorage_thd_bsem, FALSE); + chBSemObjectInit(&msdp->usb_transfer_thread_bsem, FALSE); + chBSemObjectInit(&msdp->mass_sorage_thd_bsem, FALSE); /* Initialize sense structure to zero */ memset(&msdp->sense, 0, sizeof(msdp->sense)); @@ -312,11 +300,11 @@ usb_msd_driver_state_t msdStop(USBMassStorageDriver *msdp) { if (msdThd != NULL) { chThdTerminate(msdThd); int i; - for(i = 0; i < 20 && msdThd->p_state != THD_STATE_FINAL; i++ ) { + for(i = 0; i < 20 && msdThd->p_state != CH_STATE_FINAL; i++ ) { chThdSleepMilliseconds(20); } - if( msdThd->p_state == THD_STATE_FINAL ) { + if( msdThd->p_state == CH_STATE_FINAL ) { final_state = USB_MSD_DRIVER_ERROR; } msdThd = NULL; @@ -326,11 +314,11 @@ usb_msd_driver_state_t msdStop(USBMassStorageDriver *msdp) { if (msdUSBTransferThd == NULL) { chThdTerminate(msdUSBTransferThd); int i; - for(i = 0; i < 20 && msdUSBTransferThd->p_state != THD_STATE_FINAL; i++ ) { + for(i = 0; i < 20 && msdUSBTransferThd->p_state != CH_STATE_FINAL; i++ ) { chThdSleepMilliseconds(20); } - if( msdUSBTransferThd->p_state == THD_STATE_FINAL ) { + if( msdUSBTransferThd->p_state == CH_STATE_FINAL ) { final_state = USB_MSD_DRIVER_ERROR; } msdUSBTransferThd = NULL; @@ -352,7 +340,7 @@ usb_msd_driver_state_t msdStop(USBMassStorageDriver *msdp) { * * @api */ -bool_t msdRequestsHook(USBDriver *usbp) { +bool msdRequestsHook(USBDriver *usbp) { return(msdRequestsHook2(usbp, NULL)); } @@ -367,7 +355,7 @@ bool_t msdRequestsHook(USBDriver *usbp) { * * @api */ -bool_t msdRequestsHook2(USBDriver *usbp, USBMassStorageDriver *msdp) { +bool msdRequestsHook2(USBDriver *usbp, USBMassStorageDriver *msdp) { if (((usbp->setup[0] & USB_RTYPE_TYPE_MASK) == USB_RTYPE_TYPE_CLASS) && ((usbp->setup[0] & USB_RTYPE_RECIPIENT_MASK) == USB_RTYPE_RECIPIENT_INTERFACE)) { @@ -439,14 +427,14 @@ const char* usb_msd_driver_state_t_to_str(const usb_msd_driver_state_t driver_st /* Event Flow Functions */ -static uint8_t msdWaitForISR(USBMassStorageDriver *msdp, const bool_t check_reset, const msd_wait_mode_t wait_mode) { +static uint8_t msdWaitForISR(USBMassStorageDriver *msdp, const bool check_reset, const msd_wait_mode_t wait_mode) { uint8_t ret = WAIT_ISR_SUCCESS; /* sleep until the ISR completes */ chSysLock(); msd_debug_print(msdp->chp, "WaitISR(mode=%d)\r\n", wait_mode); for (;;) { const msg_t m = chBSemWaitTimeoutS(&msdp->bsem, 1); - if (m == RDY_OK && wait_mode == MSD_WAIT_MODE_NONE ) { + if (m == MSG_OK && wait_mode == MSD_WAIT_MODE_NONE ) { break; } @@ -461,7 +449,7 @@ static uint8_t msdWaitForISR(USBMassStorageDriver *msdp, const bool_t check_rese break; } - if( chThdShouldTerminate() ) { + if( chThdShouldTerminateX() ) { break; } } @@ -546,23 +534,18 @@ static msd_wait_mode_t SCSICommandInquiry(USBMassStorageDriver *msdp) { msdp->command_succeeded_flag = false; } - usbPrepareTransmit(msdp->usbp, msdp->ms_ep_number, (uint8_t *)&msdp->data.scsi_inquiry_response, + usbStartTransmitI(msdp->usbp, msdp->ms_ep_number, (uint8_t *)&msdp->data.scsi_inquiry_response, sizeof(scsi_inquiry_response_t)); - - MSD_START_TRANSMIT(msdp); - /* wait for ISR */ return MSD_WAIT_MODE_BULK_IN; } static msd_wait_mode_t SCSICommandRequestSense(USBMassStorageDriver *msdp) { //This command should not affect the sense key - usbPrepareTransmit(msdp->usbp, msdp->ms_ep_number, (uint8_t *)&msdp->sense, + usbStartTransmitI(msdp->usbp, msdp->ms_ep_number, (uint8_t *)&msdp->sense, sizeof(scsi_sense_response_t)); - MSD_START_TRANSMIT(msdp); - /* wait for ISR */ return MSD_WAIT_MODE_BULK_IN; } @@ -576,11 +559,9 @@ static msd_wait_mode_t SCSICommandReadFormatCapacity(USBMassStorageDriver *msdp) msdp->data.format_capacity_response.last_block_addr = swap_uint32(msdp->block_dev_info.blk_num - 1); msdp->data.format_capacity_response.block_size = swap_uint32(msdp->block_dev_info.blk_size) | formated_capactiy_descriptor_code; - usbPrepareTransmit(msdp->usbp, msdp->ms_ep_number, (uint8_t *)&msdp->data.format_capacity_response, + usbStartTransmitI(msdp->usbp, msdp->ms_ep_number, (uint8_t *)&msdp->data.format_capacity_response, sizeof(msdp->data.format_capacity_response)); - MSD_START_TRANSMIT(msdp); - /* wait for ISR */ return MSD_WAIT_MODE_BULK_IN; } @@ -591,11 +572,9 @@ static msd_wait_mode_t SCSICommandReadCapacity10(USBMassStorageDriver *msdp) { msdp->data.read_capacity10_response.block_size = swap_uint32(msdp->block_dev_info.blk_size); msdp->data.read_capacity10_response.last_block_addr = swap_uint32(msdp->block_dev_info.blk_num - 1); - usbPrepareTransmit(msdp->usbp, msdp->ms_ep_number, (uint8_t *)&msdp->data.read_capacity10_response, + usbStartTransmitI(msdp->usbp, msdp->ms_ep_number, (uint8_t *)&msdp->data.read_capacity10_response, sizeof(msdp->data.read_capacity10_response)); - MSD_START_TRANSMIT(msdp); - /* wait for ISR */ return MSD_WAIT_MODE_BULK_IN; } @@ -634,12 +613,11 @@ static void SCSIWriteTransferPingPong(USBMassStorageDriver *msdp, && cnt < dest_buffer->max_blocks_to_read; cnt++) { msdp->transfer_thread_state = "RX-Prep"; - usbPrepareReceive(msdp->usbp, msdp->ms_ep_number, + usbStartReceiveI(msdp->usbp, msdp->ms_ep_number, (uint8_t*)&dest_buffer->buf[cnt * BLOCK_SIZE_INCREMENT], (msdp->block_dev_info.blk_size)); msdp->transfer_thread_state = "RX"; - MSD_START_RECEIVED(msdp); msdp->transfer_thread_state = "RX-Wait"; msdWaitForISR(msdp, FALSE, MSD_WAIT_MODE_BULK_OUT); @@ -727,8 +705,8 @@ static msd_wait_mode_t SCSICommandStartReadWrite10(USBMassStorageDriver *msdp) { const int empty_buffer_index = ((ping_pong_buffer_index + 1) % 2); /*initiate another transfer in the other ping pong buffer*/ - //const bool_t queue_another_transfer = ((i + BLOCK_WRITE_ITTERATION_COUNT) < total_blocks); - const bool_t queue_another_transfer = ((i + rw_ping_pong_buffer[done_buffer_index].num_blocks_to_write) < total_blocks); + //const bool queue_another_transfer = ((i + BLOCK_WRITE_ITTERATION_COUNT) < total_blocks); + const bool queue_another_transfer = ((i + rw_ping_pong_buffer[done_buffer_index].num_blocks_to_write) < total_blocks); msd_debug_nest_print(msdp->chp, "D"); if (queue_another_transfer) { @@ -754,7 +732,7 @@ static msd_wait_mode_t SCSICommandStartReadWrite10(USBMassStorageDriver *msdp) { msd_debug_err_print( msdp->chp, "\r\nCant write 0 blocks, this should not happen, halting\r\n"); chThdSleepMilliseconds(50); - chSysHalt(); + chSysHalt("MSD: Cant write 0 blocks"); } /* now write the block to the block device */ @@ -763,7 +741,7 @@ static msd_wait_mode_t SCSICommandStartReadWrite10(USBMassStorageDriver *msdp) { if (blkWrite(msdp->bbdp, rw_block_address, (uint8_t*)rw_ping_pong_buffer[done_buffer_index].buf, rw_ping_pong_buffer[done_buffer_index].num_blocks_to_write) - == CH_FAILED) { + == HAL_FAILED) { msd_debug_err_print(msdp->chp, "\r\nSD Block Write Error\r\n"); chThdSleepMilliseconds(50); msdp->write_error_count++; @@ -833,7 +811,7 @@ static msd_wait_mode_t SCSICommandStartReadWrite10(USBMassStorageDriver *msdp) { read_success = FALSE; for (retry_count = 0; retry_count < 3; retry_count++) { if (blkRead(msdp->bbdp, rw_block_address, read_buffer[i % 2], 1) - == CH_FAILED) { + == HAL_FAILED) { msd_debug_err_print(msdp->chp, "\r\nSD Block Read Error: block # %u\r\n", rw_block_address); msdp->read_error_count++; } else { @@ -875,11 +853,9 @@ static msd_wait_mode_t SCSICommandStartReadWrite10(USBMassStorageDriver *msdp) { //while (usbGetTransmitStatusI(msdp->usbp, msdp->ms_ep_number)) { //wait for the prior transmit to complete //} - usbPrepareTransmit(msdp->usbp, msdp->ms_ep_number, read_buffer[i % 2], + usbStartTransmitI(msdp->usbp, msdp->ms_ep_number, read_buffer[i % 2], msdp->block_dev_info.blk_size); - MSD_START_TRANSMIT(msdp); - if (i < (total_blocks - 1)) { /* there is at least one more block to be read from device */ /* so read that while the USB transfer takes place */ @@ -887,7 +863,7 @@ static msd_wait_mode_t SCSICommandStartReadWrite10(USBMassStorageDriver *msdp) { MSD_R_LED_ON(); for (retry_count = 0; retry_count < 3; retry_count++) { if (blkRead(msdp->bbdp, rw_block_address, read_buffer[(i+1) % 2], 1) - == CH_FAILED) { + == HAL_FAILED) { msd_debug_err_print(msdp->chp, "\r\nSD Block Read Error 2: block # %u\r\n", rw_block_address); msdp->read_error_count++; @@ -984,20 +960,16 @@ static msd_wait_mode_t SCSICommandModeSense6(USBMassStorageDriver *msdp) { msdp->data.mode_sense6_response.device_specifc_paramters |= (1<<7); } - usbPrepareTransmit(msdp->usbp, msdp->ms_ep_number, (uint8_t*)&msdp->data.mode_sense6_response, 4); - - MSD_START_TRANSMIT(msdp); + usbStartTransmitI(msdp->usbp, msdp->ms_ep_number, (uint8_t*)&msdp->data.mode_sense6_response, 4); /* wait for ISR */ return MSD_WAIT_MODE_BULK_IN; } static msd_wait_mode_t msdWaitForCommandBlock(USBMassStorageDriver *msdp) { - usbPrepareReceive(msdp->usbp, msdp->ms_ep_number, (uint8_t *)&msdp->cbw, + usbStartReceiveI(msdp->usbp, msdp->ms_ep_number, (uint8_t *)&msdp->cbw, sizeof(msd_cbw_t)); - MSD_START_RECEIVED(msdp); - msdp->state = MSD_STATE_READ_CMD_BLOCK; return(MSD_WAIT_MODE_BULK_OUT);/* wait for ISR */ @@ -1220,7 +1192,7 @@ static msd_wait_mode_t msdProcessCommandBlock(USBMassStorageDriver *msdp) { msdp->scsi_command_state = "TX"; msd_debug_nest_print(msdp->chp, "I"); - usbPrepareTransmit(msdp->usbp, msdp->ms_ep_number, (uint8_t *)csw, + usbStartTransmitI(msdp->usbp, msdp->ms_ep_number, (uint8_t *)csw, sizeof(msd_csw_t)); chSysLock(); @@ -1228,7 +1200,6 @@ static msd_wait_mode_t msdProcessCommandBlock(USBMassStorageDriver *msdp) { msdWaitForCommandBlock(msdp); msdp->bulk_in_interupt_flag = false; - usbStartTransmitI(msdp->usbp, msdp->ms_ep_number); chSysUnlock(); msd_debug_nest_print(msdp->chp, "i"); @@ -1259,16 +1230,16 @@ static msd_wait_mode_t msdProcessCommandBlock(USBMassStorageDriver *msdp) { * * @special */ -static msg_t MassStorageUSBTransferThd(void *arg) { +THD_FUNCTION(MassStorageUSBTransferThd, arg) { USBMassStorageDriver *msdp = (USBMassStorageDriver *)arg; chRegSetThreadName("MSD-Transfer"); - while ( !chThdShouldTerminate() ) { + while ( !chThdShouldTerminateX() ) { if (msdp->suspend_threads_callback != NULL && msdp->suspend_threads_callback()) { /* Suspend the thread for power savings mode */ chSysLock(); - chSchGoSleepS(THD_STATE_SUSPENDED); + chSchGoSleepS(CH_STATE_SUSPENDED); chSysUnlock(); } @@ -1284,12 +1255,11 @@ static msg_t MassStorageUSBTransferThd(void *arg) { chBSemWaitTimeout(&msdp->usb_transfer_thread_bsem, MS2ST(1)); } - return (0); } -static msg_t MassStorageThd(void *arg) { +THD_FUNCTION(MassStorageThd, arg) { USBMassStorageDriver *msdp = (USBMassStorageDriver *)arg; chRegSetThreadName("MSD"); @@ -1300,13 +1270,13 @@ static msg_t MassStorageThd(void *arg) { msdWaitForISR(msdp, FALSE, MSD_WAIT_MODE_NONE); msd_debug_print(msdp->chp, "y"); - while ( !chThdShouldTerminate() ) { + while ( !chThdShouldTerminateX() ) { #if 0 if( msdp->suspend_threads_callback != NULL && msdp->suspend_threads_callback() ) { /* Suspend the thread for power savings mode */ chSysLock(); - chSchGoSleepS(THD_STATE_SUSPENDED); + chSchGoSleepS(CH_STATE_SUSPENDED); chSysUnlock(); } #endif @@ -1323,7 +1293,7 @@ static msg_t MassStorageThd(void *arg) { msdSetDefaultSenseKey(msdp); } - bool_t enable_msd = true; + bool enable_msd = true; if (msdp->enable_msd_callback != NULL) { enable_msd = msdp->enable_msd_callback(); } @@ -1367,7 +1337,6 @@ static msg_t MassStorageThd(void *arg) { usbStop(msdp->usbp); chThdExit(0); } - return 0; } } @@ -1402,7 +1371,6 @@ static msg_t MassStorageThd(void *arg) { } } - return 0; } diff --git a/firmware/hw_layer/mass_storage/usb_msd.h b/firmware/hw_layer/mass_storage/usb_msd.h index d4466b0842..049391fd9e 100644 --- a/firmware/hw_layer/mass_storage/usb_msd.h +++ b/firmware/hw_layer/mass_storage/usb_msd.h @@ -30,6 +30,17 @@ #if HAL_USE_MASS_STORAGE_USB || defined(__DOXYGEN__) +#ifndef PACK_STRUCT_BEGIN +#define PACK_STRUCT_BEGIN +#endif + +#ifndef PACK_STRUCT_STRUCT +#define PACK_STRUCT_STRUCT +#endif + +#ifndef PACK_STRUCT_END +#define PACK_STRUCT_END +#endif #if 0 #define MSD_RW_LED_ON() palSetPad(GPIOI, GPIOI_TRI_LED_BLUE) @@ -216,29 +227,29 @@ struct USBMassStorageDriver { /* Driver Setup Data */ USBDriver *usbp; BaseBlockDevice *bbdp; - EventSource evt_connected; - EventSource evt_ejected; + event_source_t evt_connected; + event_source_t evt_ejected; BlockDeviceInfo block_dev_info; bool block_dev_info_valid_flag; usb_msd_driver_state_t driver_state; usbep_t ms_ep_number; uint16_t msd_interface_number; - bool_t (*enable_msd_callback)(void); - bool_t (*suspend_threads_callback)(void); + bool (*enable_msd_callback)(void); + bool (*suspend_threads_callback)(void); /* Externally modifiable settings */ - bool_t enable_media_removial; - bool_t disable_usb_bus_disconnect_on_eject; + bool enable_media_removial; + bool disable_usb_bus_disconnect_on_eject; BaseSequentialStream *chp; /*For debug logging*/ /*Internal data for operation of the driver */ - BinarySemaphore bsem; - BinarySemaphore usb_transfer_thread_bsem; - BinarySemaphore mass_sorage_thd_bsem; + binary_semaphore_t bsem; + binary_semaphore_t usb_transfer_thread_bsem; + binary_semaphore_t mass_sorage_thd_bsem; volatile uint32_t trigger_transfer_index; - volatile bool_t bulk_in_interupt_flag; - volatile bool_t bulk_out_interupt_flag; + volatile bool bulk_in_interupt_flag; + volatile bool bulk_out_interupt_flag; struct { scsi_read_format_capacity_response_t format_capacity_response; @@ -253,11 +264,11 @@ struct USBMassStorageDriver { msd_csw_t csw; scsi_sense_response_t sense; - volatile bool_t reconfigured_or_reset_event; + volatile bool reconfigured_or_reset_event; - bool_t command_succeeded_flag; - bool_t stall_in_endpoint; - bool_t stall_out_endpoint; + bool command_succeeded_flag; + bool stall_in_endpoint; + bool stall_out_endpoint; /*Debugging Information*/ @@ -271,11 +282,11 @@ struct USBMassStorageDriver { volatile uint8_t last_bad_scsi_command; /* Externally readable values */ - volatile bool_t debug_enable_msd; + volatile bool debug_enable_msd; volatile msd_wait_mode_t debug_wait_for_isr; - WORKING_AREA(waMassStorage, MSD_THREAD_STACK_SIZE); - WORKING_AREA(waMassStorageUSBTransfer, MSD_THREAD_STACK_SIZE); + THD_WORKING_AREA(waMassStorage, MSD_THREAD_STACK_SIZE); + THD_WORKING_AREA(waMassStorageUSBTransfer, MSD_THREAD_STACK_SIZE); }; @@ -287,8 +298,8 @@ usb_msd_driver_state_t msdStart(USBMassStorageDriver *msdp); usb_msd_driver_state_t msdStop(USBMassStorageDriver *msdp); void msdBulkInCallbackComplete(USBDriver *usbp, usbep_t ep); void msdBulkOutCallbackComplete(USBDriver *usbp, usbep_t ep); -bool_t msdRequestsHook(USBDriver *usbp); -bool_t msdRequestsHook2(USBDriver *usbp, USBMassStorageDriver *msdp); +bool msdRequestsHook(USBDriver *usbp); +bool msdRequestsHook2(USBDriver *usbp, USBMassStorageDriver *msdp); const char* usb_msd_driver_state_t_to_str(const usb_msd_driver_state_t driver_state); #ifdef __cplusplus } diff --git a/firmware/hw_layer/mass_storage/usb_msd_cfg.c b/firmware/hw_layer/mass_storage/usb_msd_cfg.c index 56b76ff278..d5927a546c 100644 --- a/firmware/hw_layer/mass_storage/usb_msd_cfg.c +++ b/firmware/hw_layer/mass_storage/usb_msd_cfg.c @@ -201,7 +201,7 @@ static void usb_event(USBDriver *usbp, usbevent_t event) { case USB_EVENT_ADDRESS: return; case USB_EVENT_CONFIGURED: - chSysLockFromIsr(); + chSysLockFromISR(); msdp->reconfigured_or_reset_event = TRUE; usbInitEndpointI(usbp, msdp->ms_ep_number, &epDataConfig); /* Kick-start the thread */ @@ -209,7 +209,7 @@ static void usb_event(USBDriver *usbp, usbevent_t event) { /* signal that the device is connected */ chEvtBroadcastI(&msdp->evt_connected); - chSysUnlockFromIsr(); + chSysUnlockFromISR(); return; case USB_EVENT_SUSPEND: diff --git a/firmware/hw_layer/mmc_card.cpp b/firmware/hw_layer/mmc_card.cpp index d40e2f3ffb..2f164ee193 100644 --- a/firmware/hw_layer/mmc_card.cpp +++ b/firmware/hw_layer/mmc_card.cpp @@ -328,7 +328,7 @@ static void MMCumount(void) { f_sync(&FDLogFile); // sync ALL mmcDisconnect(&MMCD1); // Brings the driver in a state safe for card removal. mmcStop(&MMCD1); // Disables the MMC peripheral. - f_mount(0, NULL); // FATFS: Unregister work area prior to discard it + f_mount(NULL, 0, 0); // FATFS: Unregister work area prior to discard it memset(&FDLogFile, 0, sizeof(FIL)); // clear FDLogFile fs_ready = false; // status = false scheduleMsg(&logger, "MMC/SD card removed"); @@ -350,7 +350,7 @@ static void MMCmount(void) { // Performs the initialization procedure on the inserted card. lockSpi(SPI_NONE); sdStatus = SD_STATE_CONNECTING; - if (mmcConnect(&MMCD1) != CH_SUCCESS) { + if (mmcConnect(&MMCD1) != HAL_SUCCESS) { sdStatus = SD_STATE_NOT_CONNECTED; warning(CUSTOM_OBD_MMC_ERROR, "Can't connect or mount MMC/SD"); unlockSpi(); @@ -379,7 +379,7 @@ static void MMCmount(void) { unlockSpi(); // if Ok - mount FS now memset(&MMC_FS, 0, sizeof(FATFS)); - if (f_mount(0, &MMC_FS) == FR_OK) { + if (f_mount(&MMC_FS, 0, 0) == FR_OK) { sdStatus = SD_STATE_MOUNTED; incLogFileName(); createLogFile(); diff --git a/firmware/hw_layer/rtc_helper.cpp b/firmware/hw_layer/rtc_helper.cpp index ac694c1db1..8e0d94f1ef 100644 --- a/firmware/hw_layer/rtc_helper.cpp +++ b/firmware/hw_layer/rtc_helper.cpp @@ -13,25 +13,52 @@ #include "rtc_helper.h" #if EFI_RTC || defined(__DOXYGEN__) -#include "chrtclib.h" +#include "rtc.h" static LoggingWithStorage logger("RTC"); +static RTCDateTime timespec; #endif /* EFI_RTC */ void date_set_tm(struct tm *timp) { (void)timp; #if EFI_RTC || defined(__DOXYGEN__) - rtcSetTimeTm(&RTCD1, timp); + rtcConvertStructTmToDateTime(timp, 0, ×pec); + rtcSetTime(&RTCD1, ×pec); #endif /* EFI_RTC */ } void date_get_tm(struct tm *timp) { - (void)timp; #if EFI_RTC || defined(__DOXYGEN__) - rtcGetTimeTm(&RTCD1, timp); + rtcGetTime(&RTCD1, ×pec); + rtcConvertDateTimeToStructTm(×pec, timp, NULL); #endif /* EFI_RTC */ } +static time_t GetTimeUnixSec(void) { +#if EFI_RTC || defined(__DOXYGEN__) + struct tm tim; + + rtcGetTime(&RTCD1, ×pec); + rtcConvertDateTimeToStructTm(×pec, &tim, NULL); + return mktime(&tim); +#endif +} + +static void SetTimeUnixSec(time_t unix_time) { +#if EFI_RTC || defined(__DOXYGEN__) + struct tm tim; + struct tm *canary; + + /* If the conversion is successful the function returns a pointer + to the object the result was written into.*/ + canary = localtime_r(&unix_time, &tim); + osalDbgCheck(&tim == canary); + + rtcConvertStructTmToDateTime(&tim, 0, ×pec); + rtcSetTime(&RTCD1, ×pec); +#endif +} + static void put2(int offset, char *lcd_str, int value) { static char buff[_MAX_FILLER]; efiAssertVoid(value >=0 && value <100, "value"); @@ -49,7 +76,7 @@ bool dateToStringShort(char *lcd_str) { #if EFI_RTC || defined(__DOXYGEN__) strcpy(lcd_str, "0000_000000\0"); struct tm timp; - rtcGetTimeTm(&RTCD1, &timp); + date_get_tm(&timp); if (timp.tm_year < 116 || timp.tm_year > 130) { // 2016 to 2030 is the valid range lcd_str[0] = 0; @@ -77,7 +104,7 @@ void dateToString(char *lcd_str) { strcpy(lcd_str, "00/00 00:00:00\0"); struct tm timp; - rtcGetTimeTm(&RTCD1, &timp); // get RTC date/time + date_get_tm(&timp); // get RTC date/time put2(0, lcd_str, timp.tm_mon + 1); put2(3, lcd_str, timp.tm_mday); @@ -95,12 +122,12 @@ void printDateTime(void) { static time_t unix_time; struct tm timp; - unix_time = rtcGetTimeUnixSec(&RTCD1); + unix_time = GetTimeUnixSec(); if (unix_time == -1) { scheduleMsg(&logger, "incorrect time in RTC cell"); } else { scheduleMsg(&logger, "%D - unix time", unix_time); - rtcGetTimeTm(&RTCD1, &timp); + date_get_tm(&timp); appendMsgPrefix(&logger); appendPrintf(&logger, "Current RTC time in GMT is: %04u-%02u-%02u %02u:%02u:%02u", timp.tm_year + 1900, timp.tm_mon + 1, timp.tm_mday, timp.tm_hour, @@ -114,7 +141,7 @@ void setDateTime(const char *strDate) { if (strlen(strDate) > 0) { time_t unix_time = atoi(strDate); if (unix_time > 0) { - rtcSetTimeUnixSec(&RTCD1, unix_time); + SetTimeUnixSec(unix_time); printDateTime(); return; } @@ -125,7 +152,7 @@ void setDateTime(const char *strDate) { void initRtc(void) { #if EFI_RTC || defined(__DOXYGEN__) - rtcGetTimeUnixSec(&RTCD1); // this would test RTC, see 'rtcWorks' variable, see #311 + GetTimeUnixSec(); // this would test RTC, see 'rtcWorks' variable, see #311 printMsg(&logger, "initRtc()"); #endif /* EFI_RTC */ } diff --git a/firmware/hw_layer/serial_over_usb/usbcfg.c b/firmware/hw_layer/serial_over_usb/usbcfg.c index b13196f2c6..c712b0bce5 100644 --- a/firmware/hw_layer/serial_over_usb/usbcfg.c +++ b/firmware/hw_layer/serial_over_usb/usbcfg.c @@ -271,7 +271,7 @@ static void usb_event(USBDriver *usbp, usbevent_t event) { case USB_EVENT_ADDRESS: return; case USB_EVENT_CONFIGURED: - chSysLockFromIsr(); + chSysLockFromISR(); /* Enables the endpoints specified into the configuration. Note, this callback is invoked from an ISR so I-Class functions @@ -282,7 +282,9 @@ static void usb_event(USBDriver *usbp, usbevent_t event) { /* Resetting the state of the CDC subsystem.*/ sduConfigureHookI(&SDU1); - chSysUnlockFromIsr(); + chSysUnlockFromISR(); + return; + case USB_EVENT_UNCONFIGURED: return; case USB_EVENT_SUSPEND: return; diff --git a/firmware/hw_layer/stm32f4/mpu_util.cpp b/firmware/hw_layer/stm32f4/mpu_util.cpp index eca12acc1f..b9600512cb 100644 --- a/firmware/hw_layer/stm32f4/mpu_util.cpp +++ b/firmware/hw_layer/stm32f4/mpu_util.cpp @@ -11,11 +11,12 @@ #include "engine.h" #include "pin_repository.h" #include "stm32f4xx_hal_flash.h" +#include "rfiutil.h" EXTERN_ENGINE; extern "C" { -int getRemainingStack(thread_t *otp); +//int getRemainingStack(thread_t *otp); void prvGetRegistersFromStack(uint32_t *pulFaultStackAddress); } @@ -26,12 +27,14 @@ extern uint32_t __main_stack_base__; #if defined __GNUC__ // GCC version +typedef struct port_intctx intctx_t; + int getRemainingStack(thread_t *otp) { #if CH_DBG_ENABLE_STACK_CHECK // this would dismiss coverity warning - see http://rusefi.com/forum/viewtopic.php?f=5&t=655 // coverity[uninit_use] - register struct intctx *r13 asm ("r13"); + register intctx_t *r13 asm ("r13"); otp->activeStack = r13; int remainingStack; @@ -57,9 +60,9 @@ int getRemainingStack(Thread *otp) { #if CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__) int remainingStack; if (dbg_isr_cnt > 0) { - remainingStack = (__get_SP() - sizeof(struct intctx)) - (int)&IRQSTACK$$Base; + remainingStack = (__get_SP() - sizeof(intctx_t)) - (int)&IRQSTACK$$Base; } else { - remainingStack = (__get_SP() - sizeof(struct intctx)) - (int)otp->p_stklimit; + remainingStack = (__get_SP() - sizeof(intctx_t)) - (int)otp->p_stklimit; } otp->remainingStack = remainingStack; return remainingStack; @@ -74,7 +77,7 @@ int getRemainingStack(Thread *otp) { void baseHardwareInit(void) { // looks like this holds a random value on start? Let's set a nice clean zero - DWT_CYCCNT = 0; + DWT->CYCCNT = 0; BOR_Set(BOR_Level_1); // one step above default value } diff --git a/firmware/hw_layer/trigger_input.cpp b/firmware/hw_layer/trigger_input.cpp index 305fd9175c..47b53b49d8 100644 --- a/firmware/hw_layer/trigger_input.cpp +++ b/firmware/hw_layer/trigger_input.cpp @@ -111,7 +111,7 @@ static ICUDriver *turnOnTriggerInputPin(const char *msg, brain_pin_e hwPin, ICUC efiIcuStart(driver, icucfg); if (driver->state == ICU_READY) { - icuEnable(driver); + icuEnableNotifications(driver); } else { // we would be here for example if same pin is used for multiple input capture purposes firmwareError(CUSTOM_ERR_ICU_STATE, "ICU unexpected state [%s]", hwPortname(hwPin)); @@ -123,7 +123,7 @@ static ICUDriver *turnOnTriggerInputPin(const char *msg, brain_pin_e hwPin, ICUC static void turnOffTriggerInputPin(brain_pin_e hwPin) { ICUDriver *driver = getInputCaptureDriver("trigger_off", hwPin); if (driver != NULL) { - icuDisable(driver); + icuDisableNotificationsI(driver); icuStop(driver); scheduleMsg(logger, "turnOffTriggerInputPin %s", hwPortname(hwPin)); unmarkPin(hwPin); diff --git a/firmware/util/datalogging.cpp b/firmware/util/datalogging.cpp index 08e856daa7..ecc2a84ced 100644 --- a/firmware/util/datalogging.cpp +++ b/firmware/util/datalogging.cpp @@ -105,7 +105,7 @@ void appendFast(Logging *logging, const char *text) { // todo: look into chsnprintf once on Chibios 3 static void vappendPrintfI(Logging *logging, const char *fmt, va_list arg) { intermediateLoggingBuffer.eos = 0; // reset - efiAssertVoid(getRemainingStack(chThdSelf()) > 128, "lowstck#1b"); + efiAssertVoid(getRemainingStack(chThdGetSelfX()) > 128, "lowstck#1b"); chvprintf((BaseSequentialStream *) &intermediateLoggingBuffer, fmt, arg); intermediateLoggingBuffer.buffer[intermediateLoggingBuffer.eos] = 0; // need to terminate explicitly append(logging, (char *) intermediateLoggingBufferData); @@ -115,7 +115,7 @@ static void vappendPrintfI(Logging *logging, const char *fmt, va_list arg) { * this method acquires system lock to guard the shared intermediateLoggingBuffer memory stream */ void vappendPrintf(Logging *logging, const char *fmt, va_list arg) { - efiAssertVoid(getRemainingStack(chThdSelf()) > 128, "lowstck#5b"); + efiAssertVoid(getRemainingStack(chThdGetSelfX()) > 128, "lowstck#5b"); if (!intermediateLoggingBufferInited) { firmwareError(CUSTOM_ERR_6532, "intermediateLoggingBufferInited not inited!"); return; @@ -128,7 +128,7 @@ void vappendPrintf(Logging *logging, const char *fmt, va_list arg) { } void appendPrintf(Logging *logging, const char *fmt, ...) { - efiAssertVoid(getRemainingStack(chThdSelf()) > 128, "lowstck#4"); + efiAssertVoid(getRemainingStack(chThdGetSelfX()) > 128, "lowstck#4"); va_list ap; va_start(ap, fmt); vappendPrintf(logging, fmt, ap); @@ -253,7 +253,7 @@ void resetLogging(Logging *logging) { * This method should only be invoked on main thread because only the main thread can write to the console */ void printMsg(Logging *logger, const char *fmt, ...) { - efiAssertVoid(getRemainingStack(chThdSelf()) > 128, "lowstck#5o"); + efiAssertVoid(getRemainingStack(chThdGetSelfX()) > 128, "lowstck#5o"); // resetLogging(logging); // I guess 'reset' is not needed here? appendMsgPrefix(logger); diff --git a/firmware/util/efilib2.h b/firmware/util/efilib2.h index 19cd344a1e..566f191fb9 100644 --- a/firmware/util/efilib2.h +++ b/firmware/util/efilib2.h @@ -34,7 +34,7 @@ class Overflow64Counter #include "main.h" #if (EFI_PROD_CODE || EFI_SIMULATOR) - #define GET_TIMESTAMP() hal_lld_get_counter_value() + #define GET_TIMESTAMP() port_rt_get_counter_value() #else #define GET_TIMESTAMP() 0 #endif diff --git a/firmware/util/rfiutil.c b/firmware/util/rfiutil.c index f6e725592b..cae4d239d6 100644 --- a/firmware/util/rfiutil.c +++ b/firmware/util/rfiutil.c @@ -76,3 +76,5 @@ void chVTSetAny(virtual_timer_t *vtp, systime_t time, vtfunc_t vtfunc, void *par #endif +cnt_t dbg_lock_cnt; +cnt_t dbg_isr_cnt; \ No newline at end of file diff --git a/firmware/util/rfiutil.h b/firmware/util/rfiutil.h index 8f5ee56f12..4b8eaf98ea 100644 --- a/firmware/util/rfiutil.h +++ b/firmware/util/rfiutil.h @@ -15,6 +15,8 @@ #include "histogram.h" +extern cnt_t dbg_lock_cnt; +extern cnt_t dbg_isr_cnt; #define isLocked() (dbg_lock_cnt > 0) /** From 3b851fb3f37b4ff07be9f4acde77d51e14675f86 Mon Sep 17 00:00:00 2001 From: Fabien Poussin Date: Wed, 22 Mar 2017 12:08:20 +0100 Subject: [PATCH 03/74] Disabling smart build and verbose compile. --- firmware/Makefile | 124 +++++++++++++++++++++++----------------------- 1 file changed, 61 insertions(+), 63 deletions(-) diff --git a/firmware/Makefile b/firmware/Makefile index 43bb59c408..84ad0fe28c 100644 --- a/firmware/Makefile +++ b/firmware/Makefile @@ -3,17 +3,9 @@ # NOTE: Can be overridden externally. # -PROJECT_DIR = . - -# by default EXTRA_PARAMS is empty and we create 'debug' version of the firmware with additional assertions and statistics -# for 'release' options see 'clean_compile_two_versions.bat' file - - # Compiler options here. ifeq ($(USE_OPT),) -# USE_OPT = -O2 -ggdb -std=gnu99 -fomit-frame-pointer -falign-functions=16 -# USE_OPT = $(RFLAGS) -O1 -fgnu89-inline -ggdb -fomit-frame-pointer -falign-functions=16 -std=gnu99 -Werror-implicit-function-declaration -Werror -Wno-error=pointer-sign -Wno-error=unused-function -Wno-error=unused-variable -Wno-error=sign-compare -Wno-error=unused-parameter -Wno-error=missing-field-initializers - USE_OPT = $(EXTRA_PARAMS) $(RFLAGS) -O2 -fomit-frame-pointer -falign-functions=16 -Werror-implicit-function-declaration -Werror -Wno-error=pointer-sign -Wno-error=unused-function -Wno-error=unused-variable -Wno-error=sign-compare -Wno-error=unused-parameter -Wno-error=missing-field-initializers -Werror=type-limits -Wno-error=strict-aliasing -Wno-error=attributes + USE_OPT = $(EXTRA_PARAMS) $(RFLAGS) -Os -ggdb -fomit-frame-pointer -falign-functions=16 endif # C specific options here (added to USE_OPT). @@ -33,12 +25,12 @@ endif # Linker extra options here. ifeq ($(USE_LDOPT),) - USE_LDOPT = + USE_LDOPT = -flto=4 endif # Enable this if you want link time optimizations (LTO) ifeq ($(USE_LTO),) - USE_LTO = no + USE_LTO = yes endif # If enabled, this option allows to compile the application in THUMB mode. @@ -51,6 +43,12 @@ ifeq ($(USE_VERBOSE_COMPILE),) USE_VERBOSE_COMPILE = no endif +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = no +endif + # # Build global options ############################################################################## @@ -59,11 +57,21 @@ endif # Architecture or project specific options # -USE_FPU = hard +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x0600 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x1000 +endif # Enables the use of FPU on Cortex-M4 (no, softfp, hard). ifeq ($(USE_FPU),) - USE_FPU = no + USE_FPU = hard endif # @@ -76,26 +84,30 @@ endif # Define project name here PROJECT = rusefi +PROJECT_DIR = . # Imported source files and paths -CHIBIOS = chibios -#include $(CHIBIOS)/test/test.mk +CHIBIOS = ChibiOS -#PROJECT_BOARD = OLIMEX_STM32_E407 ifneq ($(PROJECT_BOARD),OLIMEX_STM32_E407) - PROJECT_BOARD = ST_STM32F4 + PROJECT_BOARD = ST_STM32F4_DISCOVERY endif DDEFS += -D$(PROJECT_BOARD) - -# Imported source files and paths -include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk +# Startup files. +include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk +# HAL-OSAL files (optional). include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk -include $(CHIBIOS)/os/kernel/kernel.mk -#include $(CHIBIOS)/os/various/cpp_wrappers/kernel.mk +include $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/platform.mk +include $(CHIBIOS)/os/hal/boards/$(PROJECT_BOARD)/board.mk +include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk include $(CHIBIOS)/os/various/fatfs_bindings/fatfs.mk +include $(CHIBIOS)/os/various/cpp_wrappers/chcpp.mk + include console/binary/tunerstudio.mk include ext/ext.mk include $(PROJECT_DIR)/hw_layer/hw_layer.mk @@ -105,7 +117,6 @@ include development/development.mk include controllers/controllers.mk include $(PROJECT_DIR)/util/util.mk -include $(PROJECT_DIR)/config/boards/$(PROJECT_BOARD)/board.mk include $(PROJECT_DIR)/config/engines/engines.mk include $(PROJECT_DIR)/controllers/algo/algo.mk include $(PROJECT_DIR)/controllers/core/core.mk @@ -115,31 +126,32 @@ include $(PROJECT_DIR)/controllers/system/system.mk include $(PROJECT_DIR)/controllers/trigger/trigger.mk include $(PROJECT_DIR)/console/console.mk - # Define linker script file here LDSCRIPT= config/stm32f4ems/STM32F407xG_CCM.ld # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. -CSRC = $(PORTSRC) \ +CSRC = $(STARTUPSRC) \ $(KERNSRC) \ - chibios/os/various/syscalls.c \ - chibios/os/various/chprintf.c \ - chibios/os/various/memstreams.c \ - chibios/os/various/chrtclib.c \ + $(PORTSRC) \ + $(OSALSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/syscalls.c \ + $(CHIBIOS)/os/hal/lib/streams/memstreams.c \ + $(CHIBIOS)/os/hal/lib/streams/chprintf.c \ + $(CHIBIOS)/os/various/shell.c \ ${HW_MASS_STORAGE_SRC_C} \ $(UTILSRC) \ $(ENGINES_SRC) \ $(CONSOLESRC) \ - $(HALSRC) \ $(DEV_SRC) \ $(HW_LAYER_EMS) \ $(CONTROLLERSSRC) \ $(CONTROLLERS_ALGO_SRC) \ $(CONTROLLERS_CORE_SRC) \ $(CONTROLLERS_SENSORS_SRC) \ - $(PLATFORMSRC) \ - $(BOARDSRC) \ $(FATFSSRC) \ $(SYSTEMSRC) @@ -185,13 +197,21 @@ TCSRC = TCPPSRC = # List ASM source files here -ASMSRC = $(PORTASM) +# List ASM source files here +ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(PLATFORMINC) $(BOARDINC) \ - $(CHCPPINC) \ - $(CHIBIOS)/os/various \ - $(CHIBIOS)/os/various/devices_lib/accel \ +INCDIR = $(PORTINC) \ + $(OSALINC) \ + $(KERNINC) \ + $(TESTINC) \ + $(STARTUPINC) \ + $(HALINC) \ + $(PLATFORMINC) \ + $(BOARDINC) \ + $(CHCPPINC) \ + $(CHIBIOS)/os/hal/lib/streams \ + $(CHIBIOS)/os/various \ + $(CHIBIOS)/os/various/devices_lib/accel \ config/stm32f4ems \ config/engines \ config \ @@ -244,6 +264,7 @@ LD = $(TRGT)gcc #LD = $(TRGT)g++ CP = $(TRGT)objcopy AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar OD = $(TRGT)objdump SZ = $(TRGT)size HEX = $(CP) -O ihex @@ -265,29 +286,6 @@ CPPWARN = -Wall -Wextra # Compiler settings ############################################################################## -############################################################################## -# Start of default section -# - -# List all default C defines here, like -D_DEBUG=1 -DDEFS = - -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS = - -# List all default directories to look for include files here -DINCDIR = - -# List the default directory to look for the libraries here -DLIBDIR = - -# List all default libraries here -DLIBS = - -# -# End of default section -############################################################################## - ############################################################################## # Start of user section # @@ -311,5 +309,5 @@ ULIBS = -lm # End of user defines ############################################################################## -RULESPATH = $(CHIBIOS)/os/ports/GCC/ARMCMx +RULESPATH = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC include $(RULESPATH)/rules.mk From bac75b2e3eb8a8798295e5852c21035807956aad Mon Sep 17 00:00:00 2001 From: Fabien Poussin Date: Wed, 22 Mar 2017 17:53:09 +0100 Subject: [PATCH 04/74] Changing ChibiOS repo to rusefi, updating code accordingly. --- .gitmodules | 4 +- firmware/ChibiOS | 2 +- firmware/Makefile | 2 +- firmware/config/stm32f4ems/chconf.h | 44 ++++++++++++++++++++-- firmware/config/stm32f4ems/mcuconf.h | 31 ++++++++------- firmware/controllers/algo/error_handling.h | 12 ------ firmware/global.h | 8 ++-- firmware/hw_layer/stm32f4/mpu_util.cpp | 2 +- 8 files changed, 67 insertions(+), 38 deletions(-) diff --git a/.gitmodules b/.gitmodules index a971b630ef..7d5afcc689 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,4 +1,4 @@ [submodule "firmware/ChibiOS"] path = firmware/ChibiOS - url = https://github.com/ChibiOS/ChibiOS.git - branch = stable_16.1.x + url = https://github.com/rusefi/ChibiOS.git + branch = stable_rusefi diff --git a/firmware/ChibiOS b/firmware/ChibiOS index 7cac0e4b08..3f25f7b5e9 160000 --- a/firmware/ChibiOS +++ b/firmware/ChibiOS @@ -1 +1 @@ -Subproject commit 7cac0e4b0889b9f22fb998e48ac2a5e3f06e0b93 +Subproject commit 3f25f7b5e9e81dd6135c7df7c82782a685acf648 diff --git a/firmware/Makefile b/firmware/Makefile index 84ad0fe28c..2afb7330fb 100644 --- a/firmware/Makefile +++ b/firmware/Makefile @@ -99,7 +99,6 @@ include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk # HAL-OSAL files (optional). include $(CHIBIOS)/os/hal/hal.mk include $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/platform.mk -include $(CHIBIOS)/os/hal/boards/$(PROJECT_BOARD)/board.mk include $(CHIBIOS)/os/hal/osal/rt/osal.mk # RTOS files (optional). include $(CHIBIOS)/os/rt/rt.mk @@ -110,6 +109,7 @@ include $(CHIBIOS)/os/various/cpp_wrappers/chcpp.mk include console/binary/tunerstudio.mk include ext/ext.mk +include $(PROJECT_DIR)/boards/$(PROJECT_BOARD)/board.mk include $(PROJECT_DIR)/hw_layer/hw_layer.mk include $(PROJECT_DIR)/hw_layer/sensors/sensors.mk include $(PROJECT_DIR)/hw_layer/mass_storage/mass_storage.mk diff --git a/firmware/config/stm32f4ems/chconf.h b/firmware/config/stm32f4ems/chconf.h index 9422affdf4..454e1e807a 100644 --- a/firmware/config/stm32f4ems/chconf.h +++ b/firmware/config/stm32f4ems/chconf.h @@ -28,6 +28,29 @@ #ifndef _CHCONF_H_ #define _CHCONF_H_ +#define COMMON_IRQ_PRIORITY 6 +#define CORTEX_PRIORITY_SYSTICK COMMON_IRQ_PRIORITY +#define PORT_IDLE_THREAD_STACK_SIZE 1024 +#define PORT_INT_REQUIRED_STACK 768 +#define CHPRINTF_USE_FLOAT TRUE + +#if EFI_CLOCK_LOCKS +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + void onLockHook(void); + void onUnlockHook(void); +#ifdef __cplusplus +} +#endif /* __cplusplus */ + #define ON_LOCK_HOOK onLockHook() + #define ON_UNLOCK_HOOK onUnlockHook() +#else /* EFI_CLOCK_LOCKS */ + #define ON_LOCK_HOOK + #define ON_UNLOCK_HOOK +#endif /* EFI_CLOCK_LOCKS */ + /*===========================================================================*/ /** * @name System timers settings @@ -79,7 +102,7 @@ * @note The round robin preemption is not supported in tickless mode and * must be set to zero in that case. */ -#define CH_CFG_TIME_QUANTUM 0 +#define CH_CFG_TIME_QUANTUM 20 /** * @brief Managed RAM size. @@ -92,7 +115,7 @@ * provide the @p __heap_base__ and @p __heap_end__ symbols. * @note Requires @p CH_CFG_USE_MEMCORE. */ -#define CH_CFG_MEMCORE_SIZE 0 +#define CH_CFG_MEMCORE_SIZE 2048 /** * @brief Idle thread automatic spawn suppression. @@ -309,7 +332,7 @@ * @note Requires @p CH_CFG_USE_WAITEXIT. * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. */ -#define CH_CFG_USE_DYNAMIC TRUE +#define CH_CFG_USE_DYNAMIC FALSE /** @} */ @@ -488,6 +511,7 @@ */ #define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ /* System halt code here.*/ \ + chDbgPanic3(reason, __FILE__, __LINE__); \ } /** @} */ @@ -496,12 +520,26 @@ /* Port-specific settings (override port settings defaulted in chcore.h). */ /*===========================================================================*/ +#ifndef __ASSEMBLER__ #if !CH_DBG_SYSTEM_STATE_CHECK extern cnt_t dbg_lock_cnt; #define dbg_enter_lock() {dbg_lock_cnt = 1;ON_LOCK_HOOK;} #define dbg_leave_lock() {ON_UNLOCK_HOOK;dbg_lock_cnt = 0;} #endif +void chDbgPanic3(const char *msg, const char * file, int line); +#endif + +/** + * declared as a macro so that this code does not use stack + * so that it would not crash the error handler in case of stack issues + */ +#if CH_DBG_SYSTEM_STATE_CHECK +#define hasFatalError() (ch.dbg.panic_msg != NULL) +#else +#define hasFatalError() (FALSE) +#endif + #endif /* _CHCONF_H_ */ /** @} */ diff --git a/firmware/config/stm32f4ems/mcuconf.h b/firmware/config/stm32f4ems/mcuconf.h index f62e82893a..3ef5b00faf 100644 --- a/firmware/config/stm32f4ems/mcuconf.h +++ b/firmware/config/stm32f4ems/mcuconf.h @@ -21,7 +21,6 @@ #include "rusefi_enums.h" #define SCHEDULING_TIMER_PRIORITY 4 - #define ICU_PRIORITY 3 /* @@ -47,7 +46,7 @@ #define STM32_HSI_ENABLED TRUE #define STM32_LSI_ENABLED TRUE #define STM32_HSE_ENABLED TRUE -#define STM32_LSE_ENABLED FALSE +#define STM32_LSE_ENABLED TRUE #define STM32_CLOCK48_REQUIRED TRUE #define STM32_SW STM32_SW_PLL #define STM32_PLLSRC STM32_PLLSRC_HSE @@ -58,7 +57,11 @@ #define STM32_HPRE STM32_HPRE_DIV1 #define STM32_PPRE1 STM32_PPRE1_DIV4 #define STM32_PPRE2 STM32_PPRE2_DIV2 -#define STM32_RTCSEL STM32_RTCSEL_LSI +#if STM32_LSE_ENABLED + #define STM32_RTCSEL STM32_RTCSEL_LSE +#else + #define STM32_RTCSEL STM32_RTCSEL_LSI +#endif #define STM32_RTCPRE_VALUE 8 #define STM32_MCO1SEL STM32_MCO1SEL_HSI #define STM32_MCO1PRE STM32_MCO1PRE_DIV1 @@ -147,7 +150,7 @@ #define STM32_GPT_TIM2_IRQ_PRIORITY 7 #define STM32_GPT_TIM3_IRQ_PRIORITY 7 #define STM32_GPT_TIM4_IRQ_PRIORITY 7 -#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY SCHEDULING_TIMER_PRIORITY #define STM32_GPT_TIM6_IRQ_PRIORITY 7 #define STM32_GPT_TIM7_IRQ_PRIORITY 7 #define STM32_GPT_TIM8_IRQ_PRIORITY 7 @@ -202,13 +205,13 @@ #define STM32_ICU_USE_TIM5 FALSE #define STM32_ICU_USE_TIM8 FALSE #define STM32_ICU_USE_TIM9 TRUE -#define STM32_ICU_TIM1_IRQ_PRIORITY 7 -#define STM32_ICU_TIM2_IRQ_PRIORITY 7 -#define STM32_ICU_TIM3_IRQ_PRIORITY 7 -#define STM32_ICU_TIM4_IRQ_PRIORITY 7 -#define STM32_ICU_TIM5_IRQ_PRIORITY 7 -#define STM32_ICU_TIM8_IRQ_PRIORITY 7 -#define STM32_ICU_TIM9_IRQ_PRIORITY 7 +#define STM32_ICU_TIM1_IRQ_PRIORITY ICU_PRIORITY +#define STM32_ICU_TIM2_IRQ_PRIORITY ICU_PRIORITY +#define STM32_ICU_TIM3_IRQ_PRIORITY ICU_PRIORITY +#define STM32_ICU_TIM4_IRQ_PRIORITY ICU_PRIORITY +#define STM32_ICU_TIM5_IRQ_PRIORITY ICU_PRIORITY +#define STM32_ICU_TIM8_IRQ_PRIORITY ICU_PRIORITY +#define STM32_ICU_TIM9_IRQ_PRIORITY ICU_PRIORITY /* * MAC driver system settings. @@ -285,7 +288,7 @@ #define STM32_SPI_SPI1_IRQ_PRIORITY 10 #define STM32_SPI_SPI2_IRQ_PRIORITY 10 #define STM32_SPI_SPI3_IRQ_PRIORITY 10 -#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("STM32_SPI_DMA_ERROR_HOOK") /* * ST driver system settings. @@ -326,7 +329,7 @@ #define STM32_UART_UART4_DMA_PRIORITY 0 #define STM32_UART_UART5_DMA_PRIORITY 0 #define STM32_UART_USART6_DMA_PRIORITY 0 -#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("STM32_UART_DMA_ERROR_HOOK") /* * USB driver system settings. @@ -338,7 +341,7 @@ #define STM32_USB_OTG1_RX_FIFO_SIZE 512 #define STM32_USB_OTG2_RX_FIFO_SIZE 1024 #define STM32_USB_OTG_THREAD_PRIO LOWPRIO -#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTG_THREAD_STACK_SIZE 1024 #define STM32_USB_OTGFIFO_FILL_BASEPRI 0 /* diff --git a/firmware/controllers/algo/error_handling.h b/firmware/controllers/algo/error_handling.h index 001c3c8f70..6821b7d212 100644 --- a/firmware/controllers/algo/error_handling.h +++ b/firmware/controllers/algo/error_handling.h @@ -40,18 +40,6 @@ void firmwareError(obd_code_e code, const char *fmt, ...); char *getFirmwareError(void); -/** - * declared as a macro so that this code does not use stack - * so that it would not crash the error handler in case of stack issues - */ -#if CH_DBG_SYSTEM_STATE_CHECK -#define hasFatalError() (ch.dbg.panic_msg != NULL) -#else -#define hasFatalError() (FALSE) -#endif - -void chDbgPanic3(const char *msg, const char * file, int line); - void initErrorHandling(void); char *getWarning(void); diff --git a/firmware/global.h b/firmware/global.h index 132fbe1d60..3bb60a41a1 100644 --- a/firmware/global.h +++ b/firmware/global.h @@ -16,10 +16,6 @@ extern "C" #include #include -#ifdef __cplusplus -} -#endif /* __cplusplus */ - #include #define DEFAULT_ENGINE_TYPE CUSTOM_ENGINE @@ -125,4 +121,8 @@ typedef unsigned int time_t; */ int getRemainingStack(thread_t *otp); +#ifdef __cplusplus +} +#endif /* __cplusplus */ + #endif /* GLOBAL_H_ */ diff --git a/firmware/hw_layer/stm32f4/mpu_util.cpp b/firmware/hw_layer/stm32f4/mpu_util.cpp index b9600512cb..41d492708c 100644 --- a/firmware/hw_layer/stm32f4/mpu_util.cpp +++ b/firmware/hw_layer/stm32f4/mpu_util.cpp @@ -16,7 +16,7 @@ EXTERN_ENGINE; extern "C" { -//int getRemainingStack(thread_t *otp); +int getRemainingStack(thread_t *otp); void prvGetRegistersFromStack(uint32_t *pulFaultStackAddress); } From e4952250d172745eee845b7889a0d3b66ec92e44 Mon Sep 17 00:00:00 2001 From: Fabien Poussin Date: Wed, 22 Mar 2017 19:42:36 +0100 Subject: [PATCH 05/74] Adding ChibiOS Contrib module for a proper mass storage driver. Adding missing board files. --- .gitmodules | 3 + firmware/Makefile | 6 +- firmware/boards/ST_STM32F4_DISCOVERY/board.c | 129 ++ firmware/boards/ST_STM32F4_DISCOVERY/board.h | 1343 ++++++++++++++++ firmware/boards/ST_STM32F4_DISCOVERY/board.mk | 5 + firmware/config/stm32f4ems/halconf.h | 4 +- .../config/stm32f4ems/halconf_community.h | 159 ++ .../hw_layer/mass_storage/mass_storage.mk | 2 +- firmware/hw_layer/mass_storage/usb_msd.c | 1380 ----------------- firmware/hw_layer/mass_storage/usb_msd.h | 311 ---- firmware/hw_layer/mass_storage/usb_msd_cfg.c | 165 +- firmware/hw_layer/mass_storage/usb_msd_cfg.h | 5 +- firmware/hw_layer/mmc_card.cpp | 4 +- 13 files changed, 1734 insertions(+), 1782 deletions(-) create mode 100644 firmware/boards/ST_STM32F4_DISCOVERY/board.c create mode 100644 firmware/boards/ST_STM32F4_DISCOVERY/board.h create mode 100644 firmware/boards/ST_STM32F4_DISCOVERY/board.mk create mode 100644 firmware/config/stm32f4ems/halconf_community.h delete mode 100644 firmware/hw_layer/mass_storage/usb_msd.c delete mode 100644 firmware/hw_layer/mass_storage/usb_msd.h diff --git a/.gitmodules b/.gitmodules index 7d5afcc689..2699bb63c0 100644 --- a/.gitmodules +++ b/.gitmodules @@ -2,3 +2,6 @@ path = firmware/ChibiOS url = https://github.com/rusefi/ChibiOS.git branch = stable_rusefi +[submodule "firmware/ChibiOS-Contrib"] + path = firmware/ChibiOS-Contrib + url = https://github.com/ChibiOS/ChibiOS-Contrib.git diff --git a/firmware/Makefile b/firmware/Makefile index 2afb7330fb..feaf57c22f 100644 --- a/firmware/Makefile +++ b/firmware/Makefile @@ -88,6 +88,7 @@ PROJECT_DIR = . # Imported source files and paths CHIBIOS = ChibiOS +CHIBIOS_CONTRIB = ChibiOS-Contrib ifneq ($(PROJECT_BOARD),OLIMEX_STM32_E407) PROJECT_BOARD = ST_STM32F4_DISCOVERY @@ -97,8 +98,8 @@ DDEFS += -D$(PROJECT_BOARD) # Startup files. include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk # HAL-OSAL files (optional). -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/STM32/STM32F4xx/platform.mk include $(CHIBIOS)/os/hal/osal/rt/osal.mk # RTOS files (optional). include $(CHIBIOS)/os/rt/rt.mk @@ -212,6 +213,7 @@ INCDIR = $(PORTINC) \ $(CHIBIOS)/os/hal/lib/streams \ $(CHIBIOS)/os/various \ $(CHIBIOS)/os/various/devices_lib/accel \ + $(CHIBIOS_CONTRIB)/os/various \ config/stm32f4ems \ config/engines \ config \ diff --git a/firmware/boards/ST_STM32F4_DISCOVERY/board.c b/firmware/boards/ST_STM32F4_DISCOVERY/board.c new file mode 100644 index 0000000000..4b26d39f8a --- /dev/null +++ b/firmware/boards/ST_STM32F4_DISCOVERY/board.c @@ -0,0 +1,129 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +const PALConfig pal_default_config = { +#if STM32_HAS_GPIOA + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, +#endif +#if STM32_HAS_GPIOB + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, +#endif +#if STM32_HAS_GPIOC + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, +#endif +#if STM32_HAS_GPIOD + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, +#endif +#if STM32_HAS_GPIOE + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, +#endif +#if STM32_HAS_GPIOF + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, +#endif +#if STM32_HAS_GPIOG + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, + VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, +#endif +#if STM32_HAS_GPIOH + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, + VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, +#endif +#if STM32_HAS_GPIOI + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH} +#endif +}; +#endif + +/** + * @brief Early initialization code. + * @details This initialization must be performed just after stack setup + * and before any other initialization. + */ +void __early_init(void) { + + stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return true; +} + +/** + * @brief SDC card write protection detection. + */ +bool sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return true; +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) { +} diff --git a/firmware/boards/ST_STM32F4_DISCOVERY/board.h b/firmware/boards/ST_STM32F4_DISCOVERY/board.h new file mode 100644 index 0000000000..3fe30786b5 --- /dev/null +++ b/firmware/boards/ST_STM32F4_DISCOVERY/board.h @@ -0,0 +1,1343 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#ifndef BOARD_H +#define BOARD_H + +/* + * Setup for STMicroelectronics STM32F4-Discovery board. + */ + +/* + * Board identifier. + */ +#define BOARD_ST_STM32F4_DISCOVERY +#define BOARD_NAME "STM32F4-Discovery for RusEFI" + +/* + * Board oscillators-related settings. + * NOTE: LSE not fitted. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 32768U +#endif + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 8000000U +#endif + +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 300U + +/* + * MCU type as defined in the ST header. + */ +#define STM32F407xx + +/* + * IO pins assignments. + */ +#define GPIOA_BUTTON 0 +#define GPIOA_PIN1 1 +#define GPIOA_PIN2 2 +#define GPIOA_PIN3 3 +#define GPIOA_LRCK 4 +#define GPIOA_SPC 5 +#define GPIOA_SDO 6 +#define GPIOA_SDI 7 +#define GPIOA_PIN8 8 +#define GPIOA_VBUS_FS 9 +#define GPIOA_OTG_FS_ID 10 +#define GPIOA_OTG_FS_DM 11 +#define GPIOA_OTG_FS_DP 12 +#define GPIOA_SWDIO 13 +#define GPIOA_SWCLK 14 +#define GPIOA_PIN15 15 + +#define GPIOB_PIN0 0 +#define GPIOB_PIN1 1 +#define GPIOB_PIN2 2 +#define GPIOB_SWO 3 +#define GPIOB_PIN4 4 +#define GPIOB_PIN5 5 +#define GPIOB_SCL 6 +#define GPIOB_PIN7 7 +#define GPIOB_PIN8 8 +#define GPIOB_PIN9 9 +#define GPIOB_PIN10 10 +#define GPIOB_PIN11 11 +#define GPIOB_PIN12 12 +#define GPIOB_PIN13 13 +#define GPIOB_PIN14 14 +#define GPIOB_PIN15 15 + +#define GPIOC_OTG_FS_POWER_ON 0 +#define GPIOC_PIN1 1 +#define GPIOC_PIN2 2 +#define GPIOC_PIN3 3 +#define GPIOC_PIN4 4 +#define GPIOC_PIN5 5 +#define GPIOC_PIN6 6 +#define GPIOC_PIN7 7 +#define GPIOC_PIN8 8 +#define GPIOC_PIN9 9 +#define GPIOC_PIN10 10 +#define GPIOC_PIN11 11 +#define GPIOC_PIN12 12 +#define GPIOC_PIN13 13 +#define GPIOC_PIN14 14 +#define GPIOC_PIN15 15 + +#define GPIOD_PIN0 0 +#define GPIOD_PIN1 1 +#define GPIOD_PIN2 2 +#define GPIOD_PIN3 3 +#define GPIOD_RESET 4 +#define GPIOD_OVER_CURRENT 5 +#define GPIOD_PIN6 6 +#define GPIOD_PIN7 7 +#define GPIOD_PIN8 8 +#define GPIOD_PIN9 9 +#define GPIOD_PIN10 10 +#define GPIOD_PIN11 11 +#define GPIOD_LED4 12 +#define GPIOD_LED3 13 +#define GPIOD_LED5 14 +#define GPIOD_LED6 15 + +#define GPIOE_PIN0 0 +#define GPIOE_PIN1 1 +#define GPIOE_PIN2 2 +#define GPIOE_PIN3 3 +#define GPIOE_PIN4 4 +#define GPIOE_PIN5 5 +#define GPIOE_PIN6 6 +#define GPIOE_PIN7 7 +#define GPIOE_PIN8 8 +#define GPIOE_PIN9 9 +#define GPIOE_PIN10 10 +#define GPIOE_PIN11 11 +#define GPIOE_PIN12 12 +#define GPIOE_PIN13 13 +#define GPIOE_PIN14 14 +#define GPIOE_PIN15 15 + +#define GPIOF_PIN0 0 +#define GPIOF_PIN1 1 +#define GPIOF_PIN2 2 +#define GPIOF_PIN3 3 +#define GPIOF_PIN4 4 +#define GPIOF_PIN5 5 +#define GPIOF_PIN6 6 +#define GPIOF_PIN7 7 +#define GPIOF_PIN8 8 +#define GPIOF_PIN9 9 +#define GPIOF_PIN10 10 +#define GPIOF_PIN11 11 +#define GPIOF_PIN12 12 +#define GPIOF_PIN13 13 +#define GPIOF_PIN14 14 +#define GPIOF_PIN15 15 + +#define GPIOG_PIN0 0 +#define GPIOG_PIN1 1 +#define GPIOG_PIN2 2 +#define GPIOG_PIN3 3 +#define GPIOG_PIN4 4 +#define GPIOG_PIN5 5 +#define GPIOG_PIN6 6 +#define GPIOG_PIN7 7 +#define GPIOG_PIN8 8 +#define GPIOG_PIN9 9 +#define GPIOG_PIN10 10 +#define GPIOG_PIN11 11 +#define GPIOG_PIN12 12 +#define GPIOG_PIN13 13 +#define GPIOG_PIN14 14 +#define GPIOG_PIN15 15 + +#define GPIOH_OSC_IN 0 +#define GPIOH_OSC_OUT 1 +#define GPIOH_PIN2 2 +#define GPIOH_PIN3 3 +#define GPIOH_PIN4 4 +#define GPIOH_PIN5 5 +#define GPIOH_PIN6 6 +#define GPIOH_PIN7 7 +#define GPIOH_PIN8 8 +#define GPIOH_PIN9 9 +#define GPIOH_PIN10 10 +#define GPIOH_PIN11 11 +#define GPIOH_PIN12 12 +#define GPIOH_PIN13 13 +#define GPIOH_PIN14 14 +#define GPIOH_PIN15 15 + +#define GPIOI_PIN0 0 +#define GPIOI_PIN1 1 +#define GPIOI_PIN2 2 +#define GPIOI_PIN3 3 +#define GPIOI_PIN4 4 +#define GPIOI_PIN5 5 +#define GPIOI_PIN6 6 +#define GPIOI_PIN7 7 +#define GPIOI_PIN8 8 +#define GPIOI_PIN9 9 +#define GPIOI_PIN10 10 +#define GPIOI_PIN11 11 +#define GPIOI_PIN12 12 +#define GPIOI_PIN13 13 +#define GPIOI_PIN14 14 +#define GPIOI_PIN15 15 + +/* + * IO lines assignments. + */ +#define LINE_BUTTON PAL_LINE(GPIOA, 0U) +#define LINE_LRCK PAL_LINE(GPIOA, 4U) +#define LINE_SPC PAL_LINE(GPIOA, 5U) +#define LINE_SDO PAL_LINE(GPIOA, 6U) +#define LINE_SDI PAL_LINE(GPIOA, 7U) +#define LINE_VBUS_FS PAL_LINE(GPIOA, 9U) +#define LINE_OTG_FS_ID PAL_LINE(GPIOA, 10U) +#define LINE_OTG_FS_DM PAL_LINE(GPIOA, 11U) +#define LINE_OTG_FS_DP PAL_LINE(GPIOA, 12U) +#define LINE_SWDIO PAL_LINE(GPIOA, 13U) +#define LINE_SWCLK PAL_LINE(GPIOA, 14U) + +#define LINE_SWO PAL_LINE(GPIOB, 3U) +#define LINE_SCL PAL_LINE(GPIOB, 6U) +#define LINE_SDA PAL_LINE(GPIOB, 9U) +#define LINE_CLK_IN PAL_LINE(GPIOB, 10U) + +#define LINE_OTG_FS_POWER_ON PAL_LINE(GPIOC, 0U) +#define LINE_PDM_OUT PAL_LINE(GPIOC, 3U) +#define LINE_MCLK PAL_LINE(GPIOC, 7U) +#define LINE_SCLK PAL_LINE(GPIOC, 10U) +#define LINE_SDIN PAL_LINE(GPIOC, 12U) + +#define LINE_RESET PAL_LINE(GPIOD, 4U) +#define LINE_OVER_CURRENT PAL_LINE(GPIOD, 5U) +#define LINE_LED4 PAL_LINE(GPIOD, 12U) +#define LINE_LED3 PAL_LINE(GPIOD, 13U) +#define LINE_LED5 PAL_LINE(GPIOD, 14U) +#define LINE_LED6 PAL_LINE(GPIOD, 15U) + +#define LINE_INT1 PAL_LINE(GPIOE, 0U) +#define LINE_INT2 PAL_LINE(GPIOE, 1U) +#define LINE_CS_SPI PAL_LINE(GPIOE, 3U) + + + +#define LINE_OSC_IN PAL_LINE(GPIOH, 0U) +#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U) + + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) +#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) +#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) +#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) +#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) + +/* + * GPIOA setup: + * + * PA0 - BUTTON (input floating). + * PA1 - PIN1 (input pullup). + * PA2 - PIN2 (input pullup). + * PA3 - PIN3 (input pullup). + * PA4 - LRCK (alternate 6). + * PA5 - SPC (alternate 5). + * PA6 - SDO (alternate 5). + * PA7 - SDI (alternate 5). + * PA8 - PIN8 (input pullup). + * PA9 - VBUS_FS (input floating). + * PA10 - OTG_FS_ID (alternate 10). + * PA11 - OTG_FS_DM (alternate 10). + * PA12 - OTG_FS_DP (alternate 10). + * PA13 - SWDIO (alternate 0). + * PA14 - SWCLK (alternate 0). + * PA15 - PIN15 (input pullup). + */ +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON) | \ + PIN_MODE_INPUT(GPIOA_PIN1) | \ + PIN_MODE_INPUT(GPIOA_PIN2) | \ + PIN_MODE_INPUT(GPIOA_PIN3) | \ + PIN_MODE_ALTERNATE(GPIOA_LRCK) | \ + PIN_MODE_ALTERNATE(GPIOA_SPC) | \ + PIN_MODE_ALTERNATE(GPIOA_SDO) | \ + PIN_MODE_ALTERNATE(GPIOA_SDI) | \ + PIN_MODE_INPUT(GPIOA_PIN8) | \ + PIN_MODE_INPUT(GPIOA_VBUS_FS) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_ID) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \ + PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ + PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ + PIN_MODE_INPUT(GPIOA_PIN15)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOA_LRCK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SPC) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SDO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SDI) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOA_VBUS_FS) | \ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_ID) | \ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_BUTTON) | \ + PIN_OSPEED_HIGH(GPIOA_PIN1) | \ + PIN_OSPEED_HIGH(GPIOA_PIN2) | \ + PIN_OSPEED_HIGH(GPIOA_PIN3) | \ + PIN_OSPEED_HIGH(GPIOA_LRCK) | \ + PIN_OSPEED_MEDIUM(GPIOA_SPC) | \ + PIN_OSPEED_MEDIUM(GPIOA_SDO) | \ + PIN_OSPEED_MEDIUM(GPIOA_SDI) | \ + PIN_OSPEED_HIGH(GPIOA_PIN8) | \ + PIN_OSPEED_HIGH(GPIOA_VBUS_FS) | \ + PIN_OSPEED_HIGH(GPIOA_OTG_FS_ID) | \ + PIN_OSPEED_HIGH(GPIOA_OTG_FS_DM) | \ + PIN_OSPEED_HIGH(GPIOA_OTG_FS_DP) | \ + PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ + PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ + PIN_OSPEED_HIGH(GPIOA_PIN15)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_BUTTON) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOA_LRCK) | \ + PIN_PUPDR_FLOATING(GPIOA_SPC) | \ + PIN_PUPDR_FLOATING(GPIOA_SDO) | \ + PIN_PUPDR_FLOATING(GPIOA_SDI) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOA_VBUS_FS) | \ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_ID) | \ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \ + PIN_PUPDR_FLOATING(GPIOA_SWDIO) | \ + PIN_PUPDR_FLOATING(GPIOA_SWCLK) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN15)) +#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_BUTTON) | \ + PIN_ODR_HIGH(GPIOA_PIN1) | \ + PIN_ODR_HIGH(GPIOA_PIN2) | \ + PIN_ODR_HIGH(GPIOA_PIN3) | \ + PIN_ODR_HIGH(GPIOA_LRCK) | \ + PIN_ODR_HIGH(GPIOA_SPC) | \ + PIN_ODR_HIGH(GPIOA_SDO) | \ + PIN_ODR_HIGH(GPIOA_SDI) | \ + PIN_ODR_HIGH(GPIOA_PIN8) | \ + PIN_ODR_HIGH(GPIOA_VBUS_FS) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_ID) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \ + PIN_ODR_HIGH(GPIOA_SWDIO) | \ + PIN_ODR_HIGH(GPIOA_SWCLK) | \ + PIN_ODR_HIGH(GPIOA_PIN15)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOA_LRCK, 6U) | \ + PIN_AFIO_AF(GPIOA_SPC, 5U) | \ + PIN_AFIO_AF(GPIOA_SDO, 5U) | \ + PIN_AFIO_AF(GPIOA_SDI, 5U)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOA_VBUS_FS, 0U) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_ID, 10U) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10U) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10U) | \ + PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ + PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN15, 0U)) + +/* + * GPIOB setup: + * + * PB0 - PIN0 (input pullup). + * PB1 - PIN1 (input pullup). + * PB2 - PIN2 (input pullup). + * PB3 - SWO (alternate 0). + * PB4 - PIN4 (input pullup). + * PB5 - PIN5 (input pullup). + * PB6 - SCL (alternate 4). + * PB7 - PIN7 (input pullup). + * PB8 - PIN8 (input pullup). + * PB9 - SDA (alternate 4). + * PB10 - CLK_IN (input pullup). + * PB11 - PIN11 (input pullup). + * PB12 - PIN12 (input pullup). + * PB13 - PIN13 (input pullup). + * PB14 - PIN14 (input pullup). + * PB15 - PIN15 (input pullup). + */ +#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \ + PIN_MODE_INPUT(GPIOB_PIN1) | \ + PIN_MODE_INPUT(GPIOB_PIN2) | \ + PIN_MODE_ALTERNATE(GPIOB_SWO) | \ + PIN_MODE_INPUT(GPIOB_PIN4) | \ + PIN_MODE_INPUT(GPIOB_PIN5) | \ + PIN_MODE_ALTERNATE(GPIOB_SCL) | \ + PIN_MODE_INPUT(GPIOB_PIN7) | \ + PIN_MODE_INPUT(GPIOB_PIN8) | \ + PIN_MODE_INPUT(GPIOB_PIN9) | \ + PIN_MODE_INPUT(GPIOB_PIN10) | \ + PIN_MODE_INPUT(GPIOB_PIN11) | \ + PIN_MODE_INPUT(GPIOB_PIN12) | \ + PIN_MODE_INPUT(GPIOB_PIN13) | \ + PIN_MODE_INPUT(GPIOB_PIN14) | \ + PIN_MODE_INPUT(GPIOB_PIN15)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_SCL) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_PIN0) | \ + PIN_OSPEED_HIGH(GPIOB_PIN1) | \ + PIN_OSPEED_HIGH(GPIOB_PIN2) | \ + PIN_OSPEED_HIGH(GPIOB_SWO) | \ + PIN_OSPEED_HIGH(GPIOB_PIN4) | \ + PIN_OSPEED_HIGH(GPIOB_PIN5) | \ + PIN_OSPEED_HIGH(GPIOB_SCL) | \ + PIN_OSPEED_HIGH(GPIOB_PIN7) | \ + PIN_OSPEED_HIGH(GPIOB_PIN8) | \ + PIN_OSPEED_HIGH(GPIOB_PIN9) | \ + PIN_OSPEED_HIGH(GPIOB_PIN10) | \ + PIN_OSPEED_HIGH(GPIOB_PIN11) | \ + PIN_OSPEED_HIGH(GPIOB_PIN12) | \ + PIN_OSPEED_HIGH(GPIOB_PIN13) | \ + PIN_OSPEED_HIGH(GPIOB_PIN14) | \ + PIN_OSPEED_HIGH(GPIOB_PIN15)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOB_SWO) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOB_SCL) | \ + PIN_PUPDR_PULLDOWN(GPIOB_PIN7) | \ + PIN_PUPDR_PULLDOWN(GPIOB_PIN8) | \ + PIN_PUPDR_PULLDOWN(GPIOB_PIN9) | \ + PIN_PUPDR_PULLDOWN(GPIOB_PIN10) | \ + PIN_PUPDR_PULLDOWN(GPIOB_PIN11) | \ + PIN_PUPDR_PULLDOWN(GPIOB_PIN12) | \ + PIN_PUPDR_PULLDOWN(GPIOB_PIN13) | \ + PIN_PUPDR_PULLDOWN(GPIOB_PIN14) | \ + PIN_PUPDR_PULLDOWN(GPIOB_PIN15)) +#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \ + PIN_ODR_HIGH(GPIOB_PIN1) | \ + PIN_ODR_HIGH(GPIOB_PIN2) | \ + PIN_ODR_HIGH(GPIOB_SWO) | \ + PIN_ODR_HIGH(GPIOB_PIN4) | \ + PIN_ODR_HIGH(GPIOB_PIN5) | \ + PIN_ODR_HIGH(GPIOB_SCL) | \ + PIN_ODR_HIGH(GPIOB_PIN7) | \ + PIN_ODR_HIGH(GPIOB_PIN8) | \ + PIN_ODR_HIGH(GPIOB_PIN9) | \ + PIN_ODR_HIGH(GPIOB_PIN10) | \ + PIN_ODR_HIGH(GPIOB_PIN11) | \ + PIN_ODR_HIGH(GPIOB_PIN12) | \ + PIN_ODR_HIGH(GPIOB_PIN13) | \ + PIN_ODR_HIGH(GPIOB_PIN14) | \ + PIN_ODR_HIGH(GPIOB_PIN15)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOB_SWO, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOB_SCL, 4U) | \ + PIN_AFIO_AF(GPIOB_PIN7, 0U)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN15, 0U)) + +/* + * GPIOC setup: + * + * PC0 - OTG_FS_POWER_ON (output pushpull maximum). + * PC1 - PIN1 (input pullup). + * PC2 - PIN2 (input pullup). + * PC3 - PDM_OUT (input pullup). + * PC4 - PIN4 (input pullup). + * PC5 - PIN5 (input pullup). + * PC6 - PIN6 (input pullup). + * PC7 - MCLK (alternate 6). + * PC8 - PIN8 (input pullup). + * PC9 - PIN9 (input pullup). + * PC10 - SCLK (alternate 6). + * PC11 - PIN11 (input pullup). + * PC12 - SDIN (alternate 6). + * PC13 - PIN13 (input pullup). + * PC14 - PIN14 (input pullup). + * PC15 - PIN15 (input pullup). + */ +#define VAL_GPIOC_MODER (PIN_MODE_OUTPUT(GPIOC_OTG_FS_POWER_ON) |\ + PIN_MODE_INPUT(GPIOC_PIN1) | \ + PIN_MODE_INPUT(GPIOC_PIN2) | \ + PIN_MODE_INPUT(GPIOC_PIN3) | \ + PIN_MODE_INPUT(GPIOC_PIN4) | \ + PIN_MODE_INPUT(GPIOC_PIN5) | \ + PIN_MODE_INPUT(GPIOC_PIN6) | \ + PIN_MODE_INPUT(GPIOC_PIN7) | \ + PIN_MODE_INPUT(GPIOC_PIN8) | \ + PIN_MODE_INPUT(GPIOC_PIN9) | \ + PIN_MODE_INPUT(GPIOC_PIN10) | \ + PIN_MODE_INPUT(GPIOC_PIN11) | \ + PIN_MODE_INPUT(GPIOC_PIN12) | \ + PIN_MODE_INPUT(GPIOC_PIN13) | \ + PIN_MODE_INPUT(GPIOC_PIN14) | \ + PIN_MODE_INPUT(GPIOC_PIN15)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_OTG_FS_POWER_ON) |\ + PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN15)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_OTG_FS_POWER_ON) |\ + PIN_OSPEED_HIGH(GPIOC_PIN1) | \ + PIN_OSPEED_HIGH(GPIOC_PIN2) | \ + PIN_OSPEED_HIGH(GPIOC_PIN3) | \ + PIN_OSPEED_HIGH(GPIOC_PIN4) | \ + PIN_OSPEED_HIGH(GPIOC_PIN5) | \ + PIN_OSPEED_HIGH(GPIOC_PIN6) | \ + PIN_OSPEED_HIGH(GPIOC_PIN7) | \ + PIN_OSPEED_HIGH(GPIOC_PIN8) | \ + PIN_OSPEED_HIGH(GPIOC_PIN9) | \ + PIN_OSPEED_HIGH(GPIOC_PIN10) | \ + PIN_OSPEED_HIGH(GPIOC_PIN11) | \ + PIN_OSPEED_HIGH(GPIOC_PIN12) | \ + PIN_OSPEED_HIGH(GPIOC_PIN13) | \ + PIN_OSPEED_HIGH(GPIOC_PIN14) | \ + PIN_OSPEED_HIGH(GPIOC_PIN15)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_OTG_FS_POWER_ON) |\ + PIN_PUPDR_PULLDOWN(GPIOC_PIN1) | \ + PIN_PUPDR_PULLDOWN(GPIOC_PIN2) | \ + PIN_PUPDR_PULLDOWN(GPIOC_PIN3) | \ + PIN_PUPDR_PULLDOWN(GPIOC_PIN4) | \ + PIN_PUPDR_PULLDOWN(GPIOC_PIN5) | \ + PIN_PUPDR_PULLDOWN(GPIOC_PIN6) | \ + PIN_PUPDR_PULLDOWN(GPIOC_PIN7) | \ + PIN_PUPDR_PULLDOWN(GPIOC_PIN8) | \ + PIN_PUPDR_PULLDOWN(GPIOC_PIN9) | \ + PIN_PUPDR_PULLDOWN(GPIOC_PIN10) | \ + PIN_PUPDR_PULLDOWN(GPIOC_PIN11) | \ + PIN_PUPDR_PULLDOWN(GPIOC_PIN12) | \ + PIN_PUPDR_PULLDOWN(GPIOC_PIN13) | \ + PIN_PUPDR_PULLDOWN(GPIOC_PIN14) | \ + PIN_PUPDR_PULLDOWN(GPIOC_PIN15)) +#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_OTG_FS_POWER_ON) | \ + PIN_ODR_HIGH(GPIOC_PIN1) | \ + PIN_ODR_HIGH(GPIOC_PIN2) | \ + PIN_ODR_HIGH(GPIOC_PIN3) | \ + PIN_ODR_HIGH(GPIOC_PIN4) | \ + PIN_ODR_HIGH(GPIOC_PIN5) | \ + PIN_ODR_HIGH(GPIOC_PIN6) | \ + PIN_ODR_HIGH(GPIOC_PIN7) | \ + PIN_ODR_HIGH(GPIOC_PIN8) | \ + PIN_ODR_HIGH(GPIOC_PIN9) | \ + PIN_ODR_HIGH(GPIOC_PIN10) | \ + PIN_ODR_HIGH(GPIOC_PIN11) | \ + PIN_ODR_HIGH(GPIOC_PIN12) | \ + PIN_ODR_HIGH(GPIOC_PIN13) | \ + PIN_ODR_HIGH(GPIOC_PIN14) | \ + PIN_ODR_HIGH(GPIOC_PIN15)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_OTG_FS_POWER_ON, 0U) |\ + PIN_AFIO_AF(GPIOC_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN7, 0U)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN15, 0U)) + +/* + * GPIOD setup: + * + * PD0 - PIN0 (input pullup). + * PD1 - PIN1 (input pullup). + * PD2 - PIN2 (input pullup). + * PD3 - PIN3 (input pullup). + * PD4 - RESET (output pushpull maximum). + * PD5 - OVER_CURRENT (input floating). + * PD6 - PIN6 (input pullup). + * PD7 - PIN7 (input pullup). + * PD8 - PIN8 (input pullup). + * PD9 - PIN9 (input pullup). + * PD10 - PIN10 (input pullup). + * PD11 - PIN11 (input pullup). + * PD12 - LED4 (output pushpull maximum). + * PD13 - LED3 (output pushpull maximum). + * PD14 - LED5 (output pushpull maximum). + * PD15 - LED6 (output pushpull maximum). + */ +#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \ + PIN_MODE_INPUT(GPIOD_PIN1) | \ + PIN_MODE_INPUT(GPIOD_PIN2) | \ + PIN_MODE_INPUT(GPIOD_PIN3) | \ + PIN_MODE_OUTPUT(GPIOD_RESET) | \ + PIN_MODE_INPUT(GPIOD_OVER_CURRENT) | \ + PIN_MODE_INPUT(GPIOD_PIN6) | \ + PIN_MODE_INPUT(GPIOD_PIN7) | \ + PIN_MODE_INPUT(GPIOD_PIN8) | \ + PIN_MODE_INPUT(GPIOD_PIN9) | \ + PIN_MODE_INPUT(GPIOD_PIN10) | \ + PIN_MODE_INPUT(GPIOD_PIN11) | \ + PIN_MODE_OUTPUT(GPIOD_LED4) | \ + PIN_MODE_OUTPUT(GPIOD_LED3) | \ + PIN_MODE_OUTPUT(GPIOD_LED5) | \ + PIN_MODE_OUTPUT(GPIOD_LED6)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_RESET) | \ + PIN_OTYPE_PUSHPULL(GPIOD_OVER_CURRENT) |\ + PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LED4) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LED3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LED5) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LED6)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \ + PIN_OSPEED_HIGH(GPIOD_PIN1) | \ + PIN_OSPEED_HIGH(GPIOD_PIN2) | \ + PIN_OSPEED_HIGH(GPIOD_PIN3) | \ + PIN_OSPEED_HIGH(GPIOD_RESET) | \ + PIN_OSPEED_HIGH(GPIOD_OVER_CURRENT) | \ + PIN_OSPEED_HIGH(GPIOD_PIN6) | \ + PIN_OSPEED_HIGH(GPIOD_PIN7) | \ + PIN_OSPEED_HIGH(GPIOD_PIN8) | \ + PIN_OSPEED_HIGH(GPIOD_PIN9) | \ + PIN_OSPEED_HIGH(GPIOD_PIN10) | \ + PIN_OSPEED_HIGH(GPIOD_PIN11) | \ + PIN_OSPEED_HIGH(GPIOD_LED4) | \ + PIN_OSPEED_HIGH(GPIOD_LED3) | \ + PIN_OSPEED_HIGH(GPIOD_LED5) | \ + PIN_OSPEED_HIGH(GPIOD_LED6)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOD_RESET) | \ + PIN_PUPDR_FLOATING(GPIOD_OVER_CURRENT) |\ + PIN_PUPDR_PULLUP(GPIOD_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOD_LED4) | \ + PIN_PUPDR_FLOATING(GPIOD_LED3) | \ + PIN_PUPDR_FLOATING(GPIOD_LED5) | \ + PIN_PUPDR_FLOATING(GPIOD_LED6)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ + PIN_ODR_HIGH(GPIOD_PIN1) | \ + PIN_ODR_HIGH(GPIOD_PIN2) | \ + PIN_ODR_HIGH(GPIOD_PIN3) | \ + PIN_ODR_HIGH(GPIOD_RESET) | \ + PIN_ODR_HIGH(GPIOD_OVER_CURRENT) | \ + PIN_ODR_HIGH(GPIOD_PIN6) | \ + PIN_ODR_HIGH(GPIOD_PIN7) | \ + PIN_ODR_HIGH(GPIOD_PIN8) | \ + PIN_ODR_HIGH(GPIOD_PIN9) | \ + PIN_ODR_HIGH(GPIOD_PIN10) | \ + PIN_ODR_HIGH(GPIOD_PIN11) | \ + PIN_ODR_LOW(GPIOD_LED4) | \ + PIN_ODR_LOW(GPIOD_LED3) | \ + PIN_ODR_LOW(GPIOD_LED5) | \ + PIN_ODR_LOW(GPIOD_LED6)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOD_RESET, 0U) | \ + PIN_AFIO_AF(GPIOD_OVER_CURRENT, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN7, 0U)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOD_LED4, 0U) | \ + PIN_AFIO_AF(GPIOD_LED3, 0U) | \ + PIN_AFIO_AF(GPIOD_LED5, 0U) | \ + PIN_AFIO_AF(GPIOD_LED6, 0U)) + +/* + * GPIOE setup: + * + * PE0 - INT1 (input floating). + * PE1 - INT2 (input floating). + * PE2 - PIN2 (input floating). + * PE3 - CS_SPI (output pushpull maximum). + * PE4 - PIN4 (input floating). + * PE5 - PIN5 (input floating). + * PE6 - PIN6 (input floating). + * PE7 - PIN7 (input floating). + * PE8 - PIN8 (input floating). + * PE9 - PIN9 (input floating). + * PE10 - PIN10 (input floating). + * PE11 - PIN11 (input floating). + * PE12 - PIN12 (input floating). + * PE13 - PIN13 (input floating). + * PE14 - PIN14 (input floating). + * PE15 - PIN15 (input floating). + */ +#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \ + PIN_MODE_INPUT(GPIOE_PIN1) | \ + PIN_MODE_INPUT(GPIOE_PIN2) | \ + PIN_MODE_INPUT(GPIOE_PIN3) | \ + PIN_MODE_INPUT(GPIOE_PIN4) | \ + PIN_MODE_INPUT(GPIOE_PIN5) | \ + PIN_MODE_INPUT(GPIOE_PIN6) | \ + PIN_MODE_INPUT(GPIOE_PIN7) | \ + PIN_MODE_INPUT(GPIOE_PIN8) | \ + PIN_MODE_INPUT(GPIOE_PIN9) | \ + PIN_MODE_INPUT(GPIOE_PIN10) | \ + PIN_MODE_INPUT(GPIOE_PIN11) | \ + PIN_MODE_INPUT(GPIOE_PIN12) | \ + PIN_MODE_INPUT(GPIOE_PIN13) | \ + PIN_MODE_INPUT(GPIOE_PIN14) | \ + PIN_MODE_INPUT(GPIOE_PIN15)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \ + PIN_OSPEED_HIGH(GPIOE_PIN1) | \ + PIN_OSPEED_HIGH(GPIOE_PIN2) | \ + PIN_OSPEED_HIGH(GPIOE_PIN3) | \ + PIN_OSPEED_HIGH(GPIOE_PIN4) | \ + PIN_OSPEED_HIGH(GPIOE_PIN5) | \ + PIN_OSPEED_HIGH(GPIOE_PIN6) | \ + PIN_OSPEED_HIGH(GPIOE_PIN7) | \ + PIN_OSPEED_HIGH(GPIOE_PIN8) | \ + PIN_OSPEED_HIGH(GPIOE_PIN9) | \ + PIN_OSPEED_HIGH(GPIOE_PIN10) | \ + PIN_OSPEED_HIGH(GPIOE_PIN11) | \ + PIN_OSPEED_HIGH(GPIOE_PIN12) | \ + PIN_OSPEED_HIGH(GPIOE_PIN13) | \ + PIN_OSPEED_HIGH(GPIOE_PIN14) | \ + PIN_OSPEED_HIGH(GPIOE_PIN15)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN15)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ + PIN_ODR_HIGH(GPIOE_PIN1) | \ + PIN_ODR_HIGH(GPIOE_PIN2) | \ + PIN_ODR_HIGH(GPIOE_PIN3) | \ + PIN_ODR_HIGH(GPIOE_PIN4) | \ + PIN_ODR_HIGH(GPIOE_PIN5) | \ + PIN_ODR_HIGH(GPIOE_PIN6) | \ + PIN_ODR_HIGH(GPIOE_PIN7) | \ + PIN_ODR_HIGH(GPIOE_PIN8) | \ + PIN_ODR_HIGH(GPIOE_PIN9) | \ + PIN_ODR_HIGH(GPIOE_PIN10) | \ + PIN_ODR_HIGH(GPIOE_PIN11) | \ + PIN_ODR_HIGH(GPIOE_PIN12) | \ + PIN_ODR_HIGH(GPIOE_PIN13) | \ + PIN_ODR_HIGH(GPIOE_PIN14) | \ + PIN_ODR_HIGH(GPIOE_PIN15)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN7, 0U)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN15, 0U)) + +/* + * GPIOF setup: + * + * PF0 - PIN0 (input floating). + * PF1 - PIN1 (input floating). + * PF2 - PIN2 (input floating). + * PF3 - PIN3 (input floating). + * PF4 - PIN4 (input floating). + * PF5 - PIN5 (input floating). + * PF6 - PIN6 (input floating). + * PF7 - PIN7 (input floating). + * PF8 - PIN8 (input floating). + * PF9 - PIN9 (input floating). + * PF10 - PIN10 (input floating). + * PF11 - PIN11 (input floating). + * PF12 - PIN12 (input floating). + * PF13 - PIN13 (input floating). + * PF14 - PIN14 (input floating). + * PF15 - PIN15 (input floating). + */ +#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \ + PIN_MODE_INPUT(GPIOF_PIN1) | \ + PIN_MODE_INPUT(GPIOF_PIN2) | \ + PIN_MODE_INPUT(GPIOF_PIN3) | \ + PIN_MODE_INPUT(GPIOF_PIN4) | \ + PIN_MODE_INPUT(GPIOF_PIN5) | \ + PIN_MODE_INPUT(GPIOF_PIN6) | \ + PIN_MODE_INPUT(GPIOF_PIN7) | \ + PIN_MODE_INPUT(GPIOF_PIN8) | \ + PIN_MODE_INPUT(GPIOF_PIN9) | \ + PIN_MODE_INPUT(GPIOF_PIN10) | \ + PIN_MODE_INPUT(GPIOF_PIN11) | \ + PIN_MODE_INPUT(GPIOF_PIN12) | \ + PIN_MODE_INPUT(GPIOF_PIN13) | \ + PIN_MODE_INPUT(GPIOF_PIN14) | \ + PIN_MODE_INPUT(GPIOF_PIN15)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_PIN0) | \ + PIN_OSPEED_HIGH(GPIOF_PIN1) | \ + PIN_OSPEED_HIGH(GPIOF_PIN2) | \ + PIN_OSPEED_HIGH(GPIOF_PIN3) | \ + PIN_OSPEED_HIGH(GPIOF_PIN4) | \ + PIN_OSPEED_HIGH(GPIOF_PIN5) | \ + PIN_OSPEED_HIGH(GPIOF_PIN6) | \ + PIN_OSPEED_HIGH(GPIOF_PIN7) | \ + PIN_OSPEED_HIGH(GPIOF_PIN8) | \ + PIN_OSPEED_HIGH(GPIOF_PIN9) | \ + PIN_OSPEED_HIGH(GPIOF_PIN10) | \ + PIN_OSPEED_HIGH(GPIOF_PIN11) | \ + PIN_OSPEED_HIGH(GPIOF_PIN12) | \ + PIN_OSPEED_HIGH(GPIOF_PIN13) | \ + PIN_OSPEED_HIGH(GPIOF_PIN14) | \ + PIN_OSPEED_HIGH(GPIOF_PIN15)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN15)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \ + PIN_ODR_HIGH(GPIOF_PIN1) | \ + PIN_ODR_HIGH(GPIOF_PIN2) | \ + PIN_ODR_HIGH(GPIOF_PIN3) | \ + PIN_ODR_HIGH(GPIOF_PIN4) | \ + PIN_ODR_HIGH(GPIOF_PIN5) | \ + PIN_ODR_HIGH(GPIOF_PIN6) | \ + PIN_ODR_HIGH(GPIOF_PIN7) | \ + PIN_ODR_HIGH(GPIOF_PIN8) | \ + PIN_ODR_HIGH(GPIOF_PIN9) | \ + PIN_ODR_HIGH(GPIOF_PIN10) | \ + PIN_ODR_HIGH(GPIOF_PIN11) | \ + PIN_ODR_HIGH(GPIOF_PIN12) | \ + PIN_ODR_HIGH(GPIOF_PIN13) | \ + PIN_ODR_HIGH(GPIOF_PIN14) | \ + PIN_ODR_HIGH(GPIOF_PIN15)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN7, 0U)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN15, 0U)) + +/* + * GPIOG setup: + * + * PG0 - PIN0 (input floating). + * PG1 - PIN1 (input floating). + * PG2 - PIN2 (input floating). + * PG3 - PIN3 (input floating). + * PG4 - PIN4 (input floating). + * PG5 - PIN5 (input floating). + * PG6 - PIN6 (input floating). + * PG7 - PIN7 (input floating). + * PG8 - PIN8 (input floating). + * PG9 - PIN9 (input floating). + * PG10 - PIN10 (input floating). + * PG11 - PIN11 (input floating). + * PG12 - PIN12 (input floating). + * PG13 - PIN13 (input floating). + * PG14 - PIN14 (input floating). + * PG15 - PIN15 (input floating). + */ +#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | \ + PIN_MODE_INPUT(GPIOG_PIN1) | \ + PIN_MODE_INPUT(GPIOG_PIN2) | \ + PIN_MODE_INPUT(GPIOG_PIN3) | \ + PIN_MODE_INPUT(GPIOG_PIN4) | \ + PIN_MODE_INPUT(GPIOG_PIN5) | \ + PIN_MODE_INPUT(GPIOG_PIN6) | \ + PIN_MODE_INPUT(GPIOG_PIN7) | \ + PIN_MODE_INPUT(GPIOG_PIN8) | \ + PIN_MODE_INPUT(GPIOG_PIN9) | \ + PIN_MODE_INPUT(GPIOG_PIN10) | \ + PIN_MODE_INPUT(GPIOG_PIN11) | \ + PIN_MODE_INPUT(GPIOG_PIN12) | \ + PIN_MODE_INPUT(GPIOG_PIN13) | \ + PIN_MODE_INPUT(GPIOG_PIN14) | \ + PIN_MODE_INPUT(GPIOG_PIN15)) +#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN15)) +#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_HIGH(GPIOG_PIN0) | \ + PIN_OSPEED_HIGH(GPIOG_PIN1) | \ + PIN_OSPEED_HIGH(GPIOG_PIN2) | \ + PIN_OSPEED_HIGH(GPIOG_PIN3) | \ + PIN_OSPEED_HIGH(GPIOG_PIN4) | \ + PIN_OSPEED_HIGH(GPIOG_PIN5) | \ + PIN_OSPEED_HIGH(GPIOG_PIN6) | \ + PIN_OSPEED_HIGH(GPIOG_PIN7) | \ + PIN_OSPEED_HIGH(GPIOG_PIN8) | \ + PIN_OSPEED_HIGH(GPIOG_PIN9) | \ + PIN_OSPEED_HIGH(GPIOG_PIN10) | \ + PIN_OSPEED_HIGH(GPIOG_PIN11) | \ + PIN_OSPEED_HIGH(GPIOG_PIN12) | \ + PIN_OSPEED_HIGH(GPIOG_PIN13) | \ + PIN_OSPEED_HIGH(GPIOG_PIN14) | \ + PIN_OSPEED_HIGH(GPIOG_PIN15)) +#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN15)) +#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \ + PIN_ODR_HIGH(GPIOG_PIN1) | \ + PIN_ODR_HIGH(GPIOG_PIN2) | \ + PIN_ODR_HIGH(GPIOG_PIN3) | \ + PIN_ODR_HIGH(GPIOG_PIN4) | \ + PIN_ODR_HIGH(GPIOG_PIN5) | \ + PIN_ODR_HIGH(GPIOG_PIN6) | \ + PIN_ODR_HIGH(GPIOG_PIN7) | \ + PIN_ODR_HIGH(GPIOG_PIN8) | \ + PIN_ODR_HIGH(GPIOG_PIN9) | \ + PIN_ODR_HIGH(GPIOG_PIN10) | \ + PIN_ODR_HIGH(GPIOG_PIN11) | \ + PIN_ODR_HIGH(GPIOG_PIN12) | \ + PIN_ODR_HIGH(GPIOG_PIN13) | \ + PIN_ODR_HIGH(GPIOG_PIN14) | \ + PIN_ODR_HIGH(GPIOG_PIN15)) +#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN7, 0U)) +#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN15, 0U)) + +/* + * GPIOH setup: + * + * PH0 - OSC_IN (input floating). + * PH1 - OSC_OUT (input floating). + * PH2 - PIN2 (input floating). + * PH3 - PIN3 (input floating). + * PH4 - PIN4 (input floating). + * PH5 - PIN5 (input floating). + * PH6 - PIN6 (input floating). + * PH7 - PIN7 (input floating). + * PH8 - PIN8 (input floating). + * PH9 - PIN9 (input floating). + * PH10 - PIN10 (input floating). + * PH11 - PIN11 (input floating). + * PH12 - PIN12 (input floating). + * PH13 - PIN13 (input floating). + * PH14 - PIN14 (input floating). + * PH15 - PIN15 (input floating). + */ +#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ + PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ + PIN_MODE_INPUT(GPIOH_PIN2) | \ + PIN_MODE_INPUT(GPIOH_PIN3) | \ + PIN_MODE_INPUT(GPIOH_PIN4) | \ + PIN_MODE_INPUT(GPIOH_PIN5) | \ + PIN_MODE_INPUT(GPIOH_PIN6) | \ + PIN_MODE_INPUT(GPIOH_PIN7) | \ + PIN_MODE_INPUT(GPIOH_PIN8) | \ + PIN_MODE_INPUT(GPIOH_PIN9) | \ + PIN_MODE_INPUT(GPIOH_PIN10) | \ + PIN_MODE_INPUT(GPIOH_PIN11) | \ + PIN_MODE_INPUT(GPIOH_PIN12) | \ + PIN_MODE_INPUT(GPIOH_PIN13) | \ + PIN_MODE_INPUT(GPIOH_PIN14) | \ + PIN_MODE_INPUT(GPIOH_PIN15)) +#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \ + PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \ + PIN_OSPEED_HIGH(GPIOH_PIN2) | \ + PIN_OSPEED_HIGH(GPIOH_PIN3) | \ + PIN_OSPEED_HIGH(GPIOH_PIN4) | \ + PIN_OSPEED_HIGH(GPIOH_PIN5) | \ + PIN_OSPEED_HIGH(GPIOH_PIN6) | \ + PIN_OSPEED_HIGH(GPIOH_PIN7) | \ + PIN_OSPEED_HIGH(GPIOH_PIN8) | \ + PIN_OSPEED_HIGH(GPIOH_PIN9) | \ + PIN_OSPEED_HIGH(GPIOH_PIN10) | \ + PIN_OSPEED_HIGH(GPIOH_PIN11) | \ + PIN_OSPEED_HIGH(GPIOH_PIN12) | \ + PIN_OSPEED_HIGH(GPIOH_PIN13) | \ + PIN_OSPEED_HIGH(GPIOH_PIN14) | \ + PIN_OSPEED_HIGH(GPIOH_PIN15)) +#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ + PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN15)) +#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ + PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ + PIN_ODR_HIGH(GPIOH_PIN2) | \ + PIN_ODR_HIGH(GPIOH_PIN3) | \ + PIN_ODR_HIGH(GPIOH_PIN4) | \ + PIN_ODR_HIGH(GPIOH_PIN5) | \ + PIN_ODR_HIGH(GPIOH_PIN6) | \ + PIN_ODR_HIGH(GPIOH_PIN7) | \ + PIN_ODR_HIGH(GPIOH_PIN8) | \ + PIN_ODR_HIGH(GPIOH_PIN9) | \ + PIN_ODR_HIGH(GPIOH_PIN10) | \ + PIN_ODR_HIGH(GPIOH_PIN11) | \ + PIN_ODR_HIGH(GPIOH_PIN12) | \ + PIN_ODR_HIGH(GPIOH_PIN13) | \ + PIN_ODR_HIGH(GPIOH_PIN14) | \ + PIN_ODR_HIGH(GPIOH_PIN15)) +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \ + PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN7, 0U)) +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN15, 0U)) + +/* + * GPIOI setup: + * + * PI0 - PIN0 (input floating). + * PI1 - PIN1 (input floating). + * PI2 - PIN2 (input floating). + * PI3 - PIN3 (input floating). + * PI4 - PIN4 (input floating). + * PI5 - PIN5 (input floating). + * PI6 - PIN6 (input floating). + * PI7 - PIN7 (input floating). + * PI8 - PIN8 (input floating). + * PI9 - PIN9 (input floating). + * PI10 - PIN10 (input floating). + * PI11 - PIN11 (input floating). + * PI12 - PIN12 (input floating). + * PI13 - PIN13 (input floating). + * PI14 - PIN14 (input floating). + * PI15 - PIN15 (input floating). + */ +#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \ + PIN_MODE_INPUT(GPIOI_PIN1) | \ + PIN_MODE_INPUT(GPIOI_PIN2) | \ + PIN_MODE_INPUT(GPIOI_PIN3) | \ + PIN_MODE_INPUT(GPIOI_PIN4) | \ + PIN_MODE_INPUT(GPIOI_PIN5) | \ + PIN_MODE_INPUT(GPIOI_PIN6) | \ + PIN_MODE_INPUT(GPIOI_PIN7) | \ + PIN_MODE_INPUT(GPIOI_PIN8) | \ + PIN_MODE_INPUT(GPIOI_PIN9) | \ + PIN_MODE_INPUT(GPIOI_PIN10) | \ + PIN_MODE_INPUT(GPIOI_PIN11) | \ + PIN_MODE_INPUT(GPIOI_PIN12) | \ + PIN_MODE_INPUT(GPIOI_PIN13) | \ + PIN_MODE_INPUT(GPIOI_PIN14) | \ + PIN_MODE_INPUT(GPIOI_PIN15)) +#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN15)) +#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_HIGH(GPIOI_PIN0) | \ + PIN_OSPEED_HIGH(GPIOI_PIN1) | \ + PIN_OSPEED_HIGH(GPIOI_PIN2) | \ + PIN_OSPEED_HIGH(GPIOI_PIN3) | \ + PIN_OSPEED_HIGH(GPIOI_PIN4) | \ + PIN_OSPEED_HIGH(GPIOI_PIN5) | \ + PIN_OSPEED_HIGH(GPIOI_PIN6) | \ + PIN_OSPEED_HIGH(GPIOI_PIN7) | \ + PIN_OSPEED_HIGH(GPIOI_PIN8) | \ + PIN_OSPEED_HIGH(GPIOI_PIN9) | \ + PIN_OSPEED_HIGH(GPIOI_PIN10) | \ + PIN_OSPEED_HIGH(GPIOI_PIN11) | \ + PIN_OSPEED_HIGH(GPIOI_PIN12) | \ + PIN_OSPEED_HIGH(GPIOI_PIN13) | \ + PIN_OSPEED_HIGH(GPIOI_PIN14) | \ + PIN_OSPEED_HIGH(GPIOI_PIN15)) +#define VAL_GPIOI_PUPDR (PIN_PUPDR_FLOATING(GPIOI_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN15)) +#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \ + PIN_ODR_HIGH(GPIOI_PIN1) | \ + PIN_ODR_HIGH(GPIOI_PIN2) | \ + PIN_ODR_HIGH(GPIOI_PIN3) | \ + PIN_ODR_HIGH(GPIOI_PIN4) | \ + PIN_ODR_HIGH(GPIOI_PIN5) | \ + PIN_ODR_HIGH(GPIOI_PIN6) | \ + PIN_ODR_HIGH(GPIOI_PIN7) | \ + PIN_ODR_HIGH(GPIOI_PIN8) | \ + PIN_ODR_HIGH(GPIOI_PIN9) | \ + PIN_ODR_HIGH(GPIOI_PIN10) | \ + PIN_ODR_HIGH(GPIOI_PIN11) | \ + PIN_ODR_HIGH(GPIOI_PIN12) | \ + PIN_ODR_HIGH(GPIOI_PIN13) | \ + PIN_ODR_HIGH(GPIOI_PIN14) | \ + PIN_ODR_HIGH(GPIOI_PIN15)) +#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN7, 0U)) +#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN15, 0U)) + + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* BOARD_H */ diff --git a/firmware/boards/ST_STM32F4_DISCOVERY/board.mk b/firmware/boards/ST_STM32F4_DISCOVERY/board.mk new file mode 100644 index 0000000000..1c69b8726f --- /dev/null +++ b/firmware/boards/ST_STM32F4_DISCOVERY/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = $(PROJECT_DIR)/boards/ST_STM32F4_DISCOVERY/board.c + +# Required include directories +BOARDINC = $(PROJECT_DIR)/boards/ST_STM32F4_DISCOVERY diff --git a/firmware/config/stm32f4ems/halconf.h b/firmware/config/stm32f4ems/halconf.h index 219171e449..5cd540aff1 100644 --- a/firmware/config/stm32f4ems/halconf.h +++ b/firmware/config/stm32f4ems/halconf.h @@ -373,9 +373,11 @@ * @note Disabling this option saves both code and data space. */ #if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) -#define USB_USE_WAIT FALSE +#define USB_USE_WAIT TRUE #endif +#include "halconf_community.h" + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/firmware/config/stm32f4ems/halconf_community.h b/firmware/config/stm32f4ems/halconf_community.h new file mode 100644 index 0000000000..723221ac20 --- /dev/null +++ b/firmware/config/stm32f4ems/halconf_community.h @@ -0,0 +1,159 @@ +/* + ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _HALCONF_COMMUNITY_H_ +#define _HALCONF_COMMUNITY_H_ + +/** + * @brief Enables the community overlay. + */ +#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) +#define HAL_USE_COMMUNITY TRUE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC FALSE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif + +/** + * @brief Enables the 1-wire subsystem. + */ +#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) +#define HAL_USE_ONEWIRE FALSE +#endif + +/** + * @brief Enables the EICU subsystem. + */ +#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__) +#define HAL_USE_EICU FALSE +#endif + +/** + * @brief Enables the CRC subsystem. + */ +#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__) +#define HAL_USE_CRC FALSE +#endif + +/** + * @brief Enables the USBH subsystem. + */ +#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__) +#define HAL_USE_USBH FALSE +#endif + +/** + * @brief Enables the EEPROM subsystem. + */ +#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__) +#define HAL_USE_EEPROM FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__) +#define HAL_USE_TIMCAP FALSE +#endif + +/** + * @brief Enables the RNG subsystem. + */ +#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__) +#define HAL_USE_RNG FALSE +#endif + +/** + * @brief Enables the USB_MSD subsystem. + */ +#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__) +#define HAL_USE_USB_MSD TRUE +#endif + +/*===========================================================================*/ +/* FSMCNAND driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define NAND_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* 1-wire driver related settings. */ +/*===========================================================================*/ +/** + * @brief Enables strong pull up feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_STRONG_PULLUP FALSE + +/** + * @brief Enables search ROM feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_SEARCH_ROM FALSE + + +/*===========================================================================*/ +/* EEProm driver related settings. */ +/*===========================================================================*/ + +#define EEPROM_USE_EE24XX FALSE +#define EEPROM_USE_EE25XX TRUE + + +#define rccEnableCRC(lp) rccEnableAHB(RCC_AHBENR_CRCEN, lp) +#define rccDisableCRC(lp) rccDisableAHB(RCC_AHBENR_CRCEN, lp) + +/*===========================================================================*/ +/* CRC driver settings. */ +/*===========================================================================*/ + +/** + * @brief Enables DMA engine when performing CRC transactions. + * @note Enabling this option also enables asynchronous API. + */ +#if !defined(CRC_USE_DMA) || defined(__DOXYGEN__) +#define CRC_USE_DMA FALSE +#endif + +/** + * @brief Enables the @p crcAcquireUnit() and @p crcReleaseUnit() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(CRC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define CRC_USE_MUTUAL_EXCLUSION TRUE +#endif + + +#endif /* _HALCONF_COMMUNITY_H_ */ + +/** @} */ diff --git a/firmware/hw_layer/mass_storage/mass_storage.mk b/firmware/hw_layer/mass_storage/mass_storage.mk index f03524cc56..cfebe5a517 100644 --- a/firmware/hw_layer/mass_storage/mass_storage.mk +++ b/firmware/hw_layer/mass_storage/mass_storage.mk @@ -1,2 +1,2 @@ -HW_MASS_STORAGE_SRC_C = $(PROJECT_DIR)/hw_layer/mass_storage/usb_msd.c \ No newline at end of file +HW_MASS_STORAGE_SRC_C = $(PROJECT_DIR)/hw_layer/mass_storage/usb_msd_cfg.c diff --git a/firmware/hw_layer/mass_storage/usb_msd.c b/firmware/hw_layer/mass_storage/usb_msd.c deleted file mode 100644 index 50ff41d560..0000000000 --- a/firmware/hw_layer/mass_storage/usb_msd.c +++ /dev/null @@ -1,1380 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file usb_msd.c - * @brief USB Mass Storage Driver code. - * - * @addtogroup MSD_USB - * @{ - */ - -#define HAL_USE_MASS_STORAGE_USB true - -#include "ch.h" -#include "hal.h" -#include "usb_msd.h" -#include "string.h" -#include "chprintf.h" - - -#if HAL_USE_MASS_STORAGE_USB || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define MSD_ENABLE_PERF_DEBUG_GPIOS FALSE -#define MSD_DEBUG_NESTING FALSE -#define MSD_DEBUG FALSE -//#define MSD_DEBUG (palReadPad(GPIOI, GPIOI_PIN4)) - -#define msd_debug_print(chp_arg, args ...) if (MSD_DEBUG && chp_arg != NULL ) { chprintf(chp_arg, args); } -#define msd_debug_nest_print(chp_arg, args ...) if ( MSD_DEBUG_NESTING && chp_arg != NULL ) { chprintf(chp_arg, args); } -#define msd_debug_err_print(chp_arg, args ...) if ( chp_arg != NULL ) { chprintf(chp_arg, args); } - - - - - -//#define MSD_DEBUG_SCSI_COMMAND_STATE_STRING(description) g_debug_info.msd.scsi_command_state = description; - -#if !defined(MSD_RW_LED_ON) -#define MSD_RW_LED_ON() -#endif - -#if !defined(MSD_RW_LED_OFF) -#define MSD_RW_LED_OFF() -#endif - -#if !defined(MSD_R_LED_ON) -#define MSD_R_LED_ON() -#endif - -#if !defined(MSD_R_LED_OFF) -#define MSD_R_LED_OFF() -#endif - -#if !defined(MSD_W_LED_ON) -#define MSD_W_LED_ON() -#endif - -#if !defined(MSD_W_LED_OFF) -#define MSD_W_LED_OFF() -#endif - - - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - - - -static THD_FUNCTION(MassStorageUSBTransferThd, arg); -static THD_FUNCTION(MassStorageThd, arg); - -static thread_t *msdThd = NULL; -static thread_t *msdUSBTransferThd = NULL; - -#define WAIT_ISR_SUCCESS 0 -#define WAIT_ISR_BUSS_RESET_OR_RECONNECT 1 - -static uint8_t msdWaitForISR(USBMassStorageDriver *msdp, const bool check_reset, const msd_wait_mode_t wait_mode); -static void msdSetDefaultSenseKey(USBMassStorageDriver *msdp); - -#define BLOCK_SIZE_INCREMENT 512 -#define BLOCK_WRITE_ITTERATION_COUNT 16 - - -typedef enum { - MSD_USB_TRANSFER_STATUS_RUNNING = 0, - MSD_USB_TRANSFER_STATUS_DONE_SUCCESSFUL, - MSD_USB_TRANSFER_STATUS_DONE_FAILED, -} msd_usb_transfer_status_t; - -typedef struct { - //uint8_t is_transfer_done; - msd_usb_transfer_status_t transfer_status; - /*Number of blocks actually read from USB IN endpoint that should be written to SD card*/ - int num_blocks_to_write; - /*Number of blocks to read from USB IN endpoint*/ - int max_blocks_to_read; - uint8_t buf[(BLOCK_SIZE_INCREMENT * BLOCK_WRITE_ITTERATION_COUNT)]; -} rw_usb_sd_buffer_t; - -static volatile rw_usb_sd_buffer_t rw_ping_pong_buffer[2]; -static uint8_t read_buffer[2][BLOCK_SIZE_INCREMENT]; - - -inline uint32_t swap_uint32( uint32_t val ) { - val = ((val << 8) & 0xFF00FF00 ) | ((val >> 8) & 0xFF00FF ); - return ((val << 16) & 0xFFFF0000) | ((val >> 16) & 0x0000FFFF); -} - -#define swap_uint16(x) ((((x) >> 8) & 0xff) | (((x) & 0xff) << 8)) - -inline uint32_t swap_4byte_buffer(uint8_t *buff) { - //Note: this is specifically to avoid pointer aliasing and de-referencing words on non-word boundaries - uint32_t temp = 0; - memcpy(&temp, buff, sizeof(temp)); - return(swap_uint32(temp)); -} - -inline uint16_t swap_2byte_buffer(uint8_t *buff) { - //Note: this is specifically to avoid pointer aliasing and de-referencing words on non-half-word boundaries - uint16_t temp = 0; - memcpy(&temp, buff, sizeof(temp)); - return(swap_uint16(temp)); -} - -/** - * @brief USB Event handler calback - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep USB Endpoint Number - * - * @api - */ -void msdBulkInCallbackComplete(USBDriver *usbp, usbep_t ep) { - (void)usbp; - (void)ep; - - if (ep > 0 && usbp->in_params[ep - 1] != NULL) { - USBMassStorageDriver *msdp = (USBMassStorageDriver *)usbp->in_params[ep - 1]; - - chSysLockFromISR(); - chBSemSignalI(&(msdp->bsem)); - - msdp->bulk_in_interupt_flag = true; - - - chSysUnlockFromISR(); - } -} - -/** - * @brief USB Event handler calback - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep USB Endpoint Number - * - * @api - */ -void msdBulkOutCallbackComplete(USBDriver *usbp, usbep_t ep) { - (void)usbp; - (void)ep; - - if (ep > 0 && usbp->in_params[ep - 1] != NULL) { - USBMassStorageDriver *msdp = (USBMassStorageDriver *)usbp->in_params[ep - 1]; - - chSysLockFromISR(); - chBSemSignalI(&(msdp->bsem)); - - msdp->bulk_out_interupt_flag = true; - - chSysUnlockFromISR(); - } -} - - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - - -/** - * @brief This function will initialize a USBMassStorageDriver structure. - * - * @pre Upon entry, the BlockDevice state should be BLK_READY. If it's not BLK_READY, then this will - * wait untile it becomes BLK_READY. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] bbdp pointer to the @p BaseBlockDevice object, such as an SDCDriver object - * @param[in] msdp pointer to the @p USBMassStorageDriver object - * @param[in] ms_ep_number USB Endpoint Number to be used by the mass storage endpoint - * - * @init - */ -usb_msd_driver_state_t msdInit(USBDriver *usbp, BaseBlockDevice *bbdp, USBMassStorageDriver *msdp, - const usbep_t ms_ep_number, const uint16_t msd_interface_number) { - - msdp->usbp = usbp; - msdp->driver_state = USB_MSD_DRIVER_OK; - msdp->state = MSD_STATE_IDLE; - msdp->trigger_transfer_index = UINT32_MAX; - msdp->bbdp = bbdp; - msdp->ms_ep_number = ms_ep_number; - msdp->msd_interface_number = msd_interface_number; - msdp->chp = NULL; - msdp->enable_media_removial = true; - msdp->block_dev_info_valid_flag = false; - - chEvtObjectInit(&msdp->evt_connected); - chEvtObjectInit(&msdp->evt_ejected); - - /* Initialize binary semaphore as taken, will cause the thread to initially - * wait on the */ - chBSemObjectInit(&msdp->bsem, TRUE); - /* Initialize binary semaphore as NOT taken */ - chBSemObjectInit(&msdp->usb_transfer_thread_bsem, FALSE); - chBSemObjectInit(&msdp->mass_sorage_thd_bsem, FALSE); - - /* Initialize sense structure to zero */ - memset(&msdp->sense, 0, sizeof(msdp->sense)); - - /* Response code = 0x70, additional sense length = 0x0A */ - msdp->sense.byte[0] = 0x70;//FIXME use #define, what is this??? - msdp->sense.byte[7] = 0x0A;//FIXME use #define, what is this??? - - /* make sure block device is working and get info */ - msdSetDefaultSenseKey(msdp); - - const uint32_t sleep_ms = 50; - uint32_t t; - for(t = 0; t <= 250 && (blkGetDriverState(bbdp) != BLK_READY); t += sleep_ms ) { - chThdSleepMilliseconds(sleep_ms); - } - - if( blkGetDriverState(bbdp) == BLK_READY ) { - blkGetInfo(bbdp, &msdp->block_dev_info); - msdp->block_dev_info_valid_flag = true; - } else { - //msdp->driver_state = USB_MSD_DRIVER_ERROR_BLK_DEV_NOT_READY; - } - - usbp->in_params[ms_ep_number - 1] = (void *)msdp; - - return(msdp->driver_state); -} - -/** - * @brief Starts data handling threads for USB mass storage driver - * - * @param[in] msdp pointer to the @p USBMassStorageDriver object - * - * @api - */ -usb_msd_driver_state_t msdStart(USBMassStorageDriver *msdp) { - /*upon entry, USB bus should be disconnected*/ - - if (msdThd == NULL ) { - msdThd = chThdCreateStatic(msdp->waMassStorage, sizeof(msdp->waMassStorage), NORMALPRIO, - MassStorageThd, msdp); - } - - if (msdUSBTransferThd == NULL ) { - msdUSBTransferThd = chThdCreateStatic(msdp->waMassStorageUSBTransfer, - sizeof(msdp->waMassStorageUSBTransfer), - NORMALPRIO, MassStorageUSBTransferThd, - msdp); - } - - return(msdp->driver_state); -} - -usb_msd_driver_state_t msdStop(USBMassStorageDriver *msdp) { - usb_msd_driver_state_t final_state = USB_MSD_DRIVER_STOPPED; - - if (msdThd != NULL) { - chThdTerminate(msdThd); - int i; - for(i = 0; i < 20 && msdThd->p_state != CH_STATE_FINAL; i++ ) { - chThdSleepMilliseconds(20); - } - - if( msdThd->p_state == CH_STATE_FINAL ) { - final_state = USB_MSD_DRIVER_ERROR; - } - msdThd = NULL; - } - - - if (msdUSBTransferThd == NULL) { - chThdTerminate(msdUSBTransferThd); - int i; - for(i = 0; i < 20 && msdUSBTransferThd->p_state != CH_STATE_FINAL; i++ ) { - chThdSleepMilliseconds(20); - } - - if( msdUSBTransferThd->p_state == CH_STATE_FINAL ) { - final_state = USB_MSD_DRIVER_ERROR; - } - msdUSBTransferThd = NULL; - } - - - msdp->driver_state = final_state; - return(msdp->driver_state); -} - - -/** - * @brief Default requests hook. - * - * @param[in] usbp pointer to the @p USBDriver object - * @return The hook status. - * @retval TRUE Message handled internally. - * @retval FALSE Message not handled. - * - * @api - */ -bool msdRequestsHook(USBDriver *usbp) { - return(msdRequestsHook2(usbp, NULL)); -} - -/** - * @brief Alternate request hook, useful for USB composite devices - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] msdp pointer to the @p USBMassStorageDriver object - * @return The hook status. - * @retval TRUE Message handled internally. - * @retval FALSE Message not handled. - * - * @api - */ -bool msdRequestsHook2(USBDriver *usbp, USBMassStorageDriver *msdp) { - if (((usbp->setup[0] & USB_RTYPE_TYPE_MASK) == USB_RTYPE_TYPE_CLASS) - && ((usbp->setup[0] & USB_RTYPE_RECIPIENT_MASK) - == USB_RTYPE_RECIPIENT_INTERFACE)) { - /* check that the request is for the MSD interface number.*/ - if( msdp != NULL ) { - if (MSD_SETUP_INDEX(usbp->setup) != msdp->msd_interface_number) - return FALSE; - } else if (MSD_SETUP_INDEX(usbp->setup) != 0 ) { - return FALSE; - } - - /* act depending on bRequest = setup[1] */ - switch (usbp->setup[1]) { - case MSD_REQ_RESET: - /* check that it is a HOST2DEV request */ - if (((usbp->setup[0] & USB_RTYPE_DIR_MASK) != USB_RTYPE_DIR_HOST2DEV) - || (MSD_SETUP_LENGTH(usbp->setup) != 0) - || (MSD_SETUP_VALUE(usbp->setup) != 0)) - return FALSE; - - /* reset all endpoints */ - /* TODO!*/ - /* The device shall NAK the status stage of the device request until - * the Bulk-Only Mass Storage Reset is complete. - */ - return TRUE; - case MSD_GET_MAX_LUN: - /* check that it is a DEV2HOST request */ - if (((usbp->setup[0] & USB_RTYPE_DIR_MASK) != USB_RTYPE_DIR_DEV2HOST) - || (MSD_SETUP_LENGTH(usbp->setup) != 1) - || (MSD_SETUP_VALUE(usbp->setup) != 0)) - return FALSE; - - //static uint8_t len_buf[1] = {0}; - msdp->data.max_lun_len_buf[0] = 0; - usbSetupTransfer(usbp, msdp->data.max_lun_len_buf, 1, NULL); - return TRUE; - default: - return FALSE; - break; - } - } - return FALSE; -} - - -const char* usb_msd_driver_state_t_to_str(const usb_msd_driver_state_t driver_state) { - switch (driver_state) { - case USB_MSD_DRIVER_UNINITIALIZED: - return ("USB_MSD_DRIVER_UNINITIALIZED"); - case USB_MSD_DRIVER_ERROR: - return ("USB_MSD_DRIVER_ERROR"); - case USB_MSD_DRIVER_OK: - return ("USB_MSD_DRIVER_OK"); - case USB_MSD_DRIVER_STOPPED: - return("USB_MSD_DRIVER_STOPPED"); - case USB_MSD_DRIVER_ERROR_BLK_DEV_NOT_READY: - return ("USB_MSD_DRIVER_ERROR_BLK_DEV_NOT_READY"); - } - return ("USB_MSD_DRIVER_UNKNOWN"); -} - - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - - -/* Event Flow Functions */ - - -static uint8_t msdWaitForISR(USBMassStorageDriver *msdp, const bool check_reset, const msd_wait_mode_t wait_mode) { - uint8_t ret = WAIT_ISR_SUCCESS; - /* sleep until the ISR completes */ - chSysLock(); - msd_debug_print(msdp->chp, "WaitISR(mode=%d)\r\n", wait_mode); - for (;;) { - const msg_t m = chBSemWaitTimeoutS(&msdp->bsem, 1); - if (m == MSG_OK && wait_mode == MSD_WAIT_MODE_NONE ) { - break; - } - - if( wait_mode == MSD_WAIT_MODE_BULK_IN && msdp->bulk_in_interupt_flag ) { - break; - } else if( wait_mode == MSD_WAIT_MODE_BULK_OUT && msdp->bulk_out_interupt_flag ) { - break; - } - - if (check_reset && msdp->reconfigured_or_reset_event) { - ret = WAIT_ISR_BUSS_RESET_OR_RECONNECT; - break; - } - - if( chThdShouldTerminateX() ) { - break; - } - } - chSysUnlock(); - return (ret); -} - - -static void WaitForUSBTransferComplete(USBMassStorageDriver *msdp, - const int ping_pong_buffer_index) { - msd_debug_nest_print(msdp->chp, "A"); - while (TRUE) { - chBSemWaitTimeout(&msdp->mass_sorage_thd_bsem, MS2ST(1)); - - if (rw_ping_pong_buffer[ping_pong_buffer_index].transfer_status != MSD_USB_TRANSFER_STATUS_RUNNING) { - break; - } else { - //chThdSleepMilliseconds(1); - } - } - msd_debug_nest_print(msdp->chp, "a"); -} - - - -/* SCSI Functions */ - -static inline void SCSISetSense(USBMassStorageDriver *msdp, uint8_t key, - uint8_t acode, uint8_t aqual) { - msdp->sense.byte[2] = key; - msdp->sense.byte[12] = acode; - msdp->sense.byte[13] = aqual; -} - - -static void msdSetDefaultSenseKey(USBMassStorageDriver *msdp) { - SCSISetSense(msdp, SCSI_SENSE_KEY_GOOD, - SCSI_ASENSE_NO_ADDITIONAL_INFORMATION, - SCSI_ASENSEQ_NO_QUALIFIER); -} - - -#ifndef USB_MASS_STORAGE_INQUIRY_RESPONSE_STRING_0 -# define USB_MASS_STORAGE_INQUIRY_RESPONSE_STRING_0 "Chibios" -#endif - -#ifndef USB_MASS_STORAGE_INQUIRY_RESPONSE_STRING_1 -# define USB_MASS_STORAGE_INQUIRY_RESPONSE_STRING_1 "Mass Storage" -#endif - -#ifndef USB_MASS_STORAGE_INQUIRY_RESPONSE_STRING_2 -# define USB_MASS_STORAGE_INQUIRY_RESPONSE_STRING_2 {'v', CH_KERNEL_MAJOR + '0', '.', CH_KERNEL_MINOR + '0'} -#endif - -static const scsi_inquiry_response_t default_scsi_inquiry_response = - {0x00, /* peripheral, direct access block device */ - 0x80, /* removable */ - 0x04, /* version, SPC-2 */ - 0x02, /* response data format */ - 0x20, /* additional_length, response has 0x20 + 4 bytes */ - 0x00, /* sccstp*/ - 0x00, /* bqueetc*/ - 0x00, /* cmdqueue*/ - USB_MASS_STORAGE_INQUIRY_RESPONSE_STRING_0, - USB_MASS_STORAGE_INQUIRY_RESPONSE_STRING_1, - USB_MASS_STORAGE_INQUIRY_RESPONSE_STRING_2, - }; - - -static msd_wait_mode_t SCSICommandInquiry(USBMassStorageDriver *msdp) { - msd_cbw_t *cbw = &(msdp->cbw); - msdp->data.scsi_inquiry_response = default_scsi_inquiry_response; - - if ((cbw->scsi_cmd_data[1] & ((1 << 0) | (1 << 1))) || cbw->scsi_cmd_data[2]) { - /* Optional but unsupported bits set - update the SENSE key and fail - * the request */ - msd_debug_err_print(msdp->chp, " INQ ERR 0x%X 0x%X\r\n", cbw->scsi_cmd_data[1], cbw->scsi_cmd_data[2]); - SCSISetSense(msdp, SCSI_SENSE_KEY_ILLEGAL_REQUEST, - SCSI_ASENSE_INVALID_FIELD_IN_CDB, SCSI_ASENSEQ_NO_QUALIFIER); - - //we should indicate that the command failed to the host, but still return data - msdp->command_succeeded_flag = false; - } - - usbStartTransmitI(msdp->usbp, msdp->ms_ep_number, (uint8_t *)&msdp->data.scsi_inquiry_response, - sizeof(scsi_inquiry_response_t)); - - /* wait for ISR */ - return MSD_WAIT_MODE_BULK_IN; -} - -static msd_wait_mode_t SCSICommandRequestSense(USBMassStorageDriver *msdp) { - //This command should not affect the sense key - usbStartTransmitI(msdp->usbp, msdp->ms_ep_number, (uint8_t *)&msdp->sense, - sizeof(scsi_sense_response_t)); - - /* wait for ISR */ - return MSD_WAIT_MODE_BULK_IN; -} - -static msd_wait_mode_t SCSICommandReadFormatCapacity(USBMassStorageDriver *msdp) { - msdSetDefaultSenseKey(msdp); - - const uint32_t formated_capactiy_descriptor_code = 0x02;//see usbmass-ufi10.doc for codes - - msdp->data.format_capacity_response.payload_byte_length[3] = 8; - msdp->data.format_capacity_response.last_block_addr = swap_uint32(msdp->block_dev_info.blk_num - 1); - msdp->data.format_capacity_response.block_size = swap_uint32(msdp->block_dev_info.blk_size) | formated_capactiy_descriptor_code; - - usbStartTransmitI(msdp->usbp, msdp->ms_ep_number, (uint8_t *)&msdp->data.format_capacity_response, - sizeof(msdp->data.format_capacity_response)); - - /* wait for ISR */ - return MSD_WAIT_MODE_BULK_IN; -} - -static msd_wait_mode_t SCSICommandReadCapacity10(USBMassStorageDriver *msdp) { - msdSetDefaultSenseKey(msdp); - - msdp->data.read_capacity10_response.block_size = swap_uint32(msdp->block_dev_info.blk_size); - msdp->data.read_capacity10_response.last_block_addr = swap_uint32(msdp->block_dev_info.blk_num - 1); - - usbStartTransmitI(msdp->usbp, msdp->ms_ep_number, (uint8_t *)&msdp->data.read_capacity10_response, - sizeof(msdp->data.read_capacity10_response)); - - /* wait for ISR */ - return MSD_WAIT_MODE_BULK_IN; -} - -static msd_wait_mode_t SCSICommandSendDiagnostic(USBMassStorageDriver *msdp) { - msd_cbw_t *cbw = &(msdp->cbw); - - if ((!cbw->scsi_cmd_data[1]) & (1 << 2)) { - /* Only self-test supported - update SENSE key and fail the command */ - SCSISetSense(msdp, SCSI_SENSE_KEY_ILLEGAL_REQUEST, - SCSI_ASENSE_INVALID_FIELD_IN_CDB, SCSI_ASENSEQ_NO_QUALIFIER); - - msdp->command_succeeded_flag = false; - return MSD_WAIT_MODE_NONE; - } - - /* TODO: actually perform the test */ - - /* don't wait for ISR */ - return MSD_WAIT_MODE_NONE; -} - -static void SCSIWriteTransferPingPong(USBMassStorageDriver *msdp, - volatile rw_usb_sd_buffer_t *dest_buffer) { - msd_debug_nest_print(msdp->chp, "B"); - int cnt; - dest_buffer->transfer_status = MSD_USB_TRANSFER_STATUS_RUNNING; - dest_buffer->num_blocks_to_write = 0; - -#if MSD_ENABLE_PERF_DEBUG_GPIOS - palSetPad(GPIOH, GPIOH_LED2); -#endif - - for (cnt = 0; - cnt < BLOCK_WRITE_ITTERATION_COUNT - && cnt < dest_buffer->max_blocks_to_read; cnt++) { - - msdp->transfer_thread_state = "RX-Prep"; - usbStartReceiveI(msdp->usbp, msdp->ms_ep_number, - (uint8_t*)&dest_buffer->buf[cnt * BLOCK_SIZE_INCREMENT], - (msdp->block_dev_info.blk_size)); - - msdp->transfer_thread_state = "RX"; - - msdp->transfer_thread_state = "RX-Wait"; - msdWaitForISR(msdp, FALSE, MSD_WAIT_MODE_BULK_OUT); - - dest_buffer->num_blocks_to_write++; - } - dest_buffer->transfer_status = MSD_USB_TRANSFER_STATUS_DONE_SUCCESSFUL; - msdp->transfer_thread_state = "RX-Done"; - //FIXME we need to handle setting the status to error if something failed, like a usb reset or something - -#if MSD_ENABLE_PERF_DEBUG_GPIOS - palClearPad(GPIOH, GPIOH_LED2); -#endif - - msd_debug_nest_print(msdp->chp, "b"); -} - - -static msd_wait_mode_t SCSICommandStartReadWrite10(USBMassStorageDriver *msdp) { - msd_cbw_t *cbw = &(msdp->cbw); - int read_success; - int retry_count; - - msdSetDefaultSenseKey(msdp); - - if ((cbw->scsi_cmd_data[0] == SCSI_CMD_WRITE_10) && blkIsWriteProtected(msdp->bbdp)) { - msd_debug_err_print(msdp->chp, "\r\nWrite Protected!\r\n"); - /* device is write protected and a write has been issued */ - /* Block address is invalid, update SENSE key and return command fail */ - SCSISetSense(msdp, SCSI_SENSE_KEY_NOT_READY, SCSI_ASENSE_WRITE_PROTECTED, - SCSI_ASENSEQ_NO_QUALIFIER); - - msdp->command_succeeded_flag = false; - msdp->stall_in_endpoint = true; - return MSD_WAIT_MODE_NONE; - } - - //FIXME, which of these? - //uint32_t rw_block_address = swap_4byte_buffer(&cbw->scsi_cmd_data[2]); - //const uint16_t total_blocks = swap_2byte_buffer(&cbw->scsi_cmd_data[7]); - uint32_t rw_block_address = swap_uint32(*(uint32_t *)&cbw->scsi_cmd_data[2]); - const uint16_t total_blocks = swap_uint16(*(uint16_t *)&cbw->scsi_cmd_data[7]); - const uint32_t rw_block_address_origional = rw_block_address; - uint16_t i = 0; - - if (rw_block_address >= msdp->block_dev_info.blk_num) { - msd_debug_err_print(msdp->chp, "\r\nBlock Address too large %u > %u\r\n", rw_block_address, msdp->block_dev_info.blk_num); - /* Block address is invalid, update SENSE key and return command fail */ - SCSISetSense(msdp, SCSI_SENSE_KEY_ILLEGAL_REQUEST, SCSI_ASENSE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, - SCSI_ASENSEQ_NO_QUALIFIER); - - msdp->command_succeeded_flag = false; - msdp->stall_in_endpoint = true; - - /* don't wait for ISR */ - return MSD_WAIT_MODE_NONE; - } - - /*initialized ping pong buffer*/ - for (i = 0; i < 2; i++) { - rw_ping_pong_buffer[i].max_blocks_to_read = 0; - rw_ping_pong_buffer[i].num_blocks_to_write = 0; - rw_ping_pong_buffer[i].transfer_status = MSD_USB_TRANSFER_STATUS_RUNNING; - } - - msd_debug_nest_print(msdp->chp, "\r\nG"); - if (cbw->scsi_cmd_data[0] == SCSI_CMD_WRITE_10) { - /* loop over each block */ - - uint32_t ping_pong_buffer_index = 0; - /*initiate a transfer*/ - rw_ping_pong_buffer[ping_pong_buffer_index].transfer_status = MSD_USB_TRANSFER_STATUS_RUNNING; - rw_ping_pong_buffer[ping_pong_buffer_index].max_blocks_to_read = total_blocks; - - /*Trigger the transfer in the other thread*/ - msdp->trigger_transfer_index = ping_pong_buffer_index; - - /*wake other thread on semaphore to trigger the transfer*/ - chBSemSignal(&msdp->usb_transfer_thread_bsem); - - WaitForUSBTransferComplete(msdp, ping_pong_buffer_index); - - for (i = 0; i < total_blocks;) { - const int done_buffer_index = ping_pong_buffer_index; - const int empty_buffer_index = ((ping_pong_buffer_index + 1) % 2); - - /*initiate another transfer in the other ping pong buffer*/ - //const bool queue_another_transfer = ((i + BLOCK_WRITE_ITTERATION_COUNT) < total_blocks); - const bool queue_another_transfer = ((i + rw_ping_pong_buffer[done_buffer_index].num_blocks_to_write) < total_blocks); - - msd_debug_nest_print(msdp->chp, "D"); - if (queue_another_transfer) { - while (TRUE) { - if (msdp->trigger_transfer_index == UINT32_MAX) { - rw_ping_pong_buffer[empty_buffer_index].max_blocks_to_read = - total_blocks - i - rw_ping_pong_buffer[done_buffer_index].num_blocks_to_write; - - msdp->trigger_transfer_index = empty_buffer_index; - - /*wake other thread on semaphore to trigger the transfer*/ - chBSemSignal(&msdp->usb_transfer_thread_bsem); - break; - } else { - chThdSleepMilliseconds(1); - } - } - } - msd_debug_nest_print(msdp->chp, "d"); - - if (rw_ping_pong_buffer[done_buffer_index].num_blocks_to_write <= 0) { - /*This should never happen!!! Something is seriously wrong!*/ - msd_debug_err_print( - msdp->chp, "\r\nCant write 0 blocks, this should not happen, halting\r\n"); - chThdSleepMilliseconds(50); - chSysHalt("MSD: Cant write 0 blocks"); - } - - /* now write the block to the block device */ - MSD_W_LED_ON(); - msd_debug_nest_print(msdp->chp, "E"); - if (blkWrite(msdp->bbdp, rw_block_address, - (uint8_t*)rw_ping_pong_buffer[done_buffer_index].buf, - rw_ping_pong_buffer[done_buffer_index].num_blocks_to_write) - == HAL_FAILED) { - msd_debug_err_print(msdp->chp, "\r\nSD Block Write Error\r\n"); - chThdSleepMilliseconds(50); - msdp->write_error_count++; - - msdp->command_succeeded_flag = false; - - SCSISetSense(msdp, SCSI_SENSE_KEY_MEDIUM_ERROR, - SCSI_ASENSE_PEREPHERIAL_DEVICE_WRITE_FAULT, - SCSI_ASENSEQ_PEREPHERIAL_DEVICE_WRITE_FAULT); - - -#define OLD_WRITE_ERROR_HANDLING FALSE -#if OLD_WRITE_ERROR_HANDLING - /* - * I think that this mode of error handling is incorrect, and was causing ACM0 usb device resets in the event of EMMC write errors. - * I confirmed using the Beagle USB 480 analyzer that the host gets a failed staus, and retries the write to the given error block, at which point the block write succeeds for thist test case. - * This code should be purged at some point - */ - msdp->stall_out_endpoint = true; - - if (queue_another_transfer) { - /*Let the previous queued transfer finish and ignore it.*/ - WaitForUSBTransferComplete(msdp, empty_buffer_index); - } - - MSD_W_LED_OFF(); - return (MSD_WAIT_MODE_NONE); -#endif - } else { - msdp->write_success_count++; - } - msd_debug_nest_print(msdp->chp, "e"); - MSD_W_LED_OFF(); - - rw_block_address += rw_ping_pong_buffer[done_buffer_index].num_blocks_to_write; - i += rw_ping_pong_buffer[done_buffer_index].num_blocks_to_write; - rw_ping_pong_buffer[done_buffer_index].transfer_status = MSD_USB_TRANSFER_STATUS_RUNNING; - rw_ping_pong_buffer[done_buffer_index].num_blocks_to_write = 0; - - msd_debug_nest_print(msdp->chp, "F"); - if (queue_another_transfer) { - if( !( i< total_blocks) ) { - msd_debug_err_print(msdp->chp, "\r\nERROR: Queued another transfer but not going to rx the data\r\n"); - } - WaitForUSBTransferComplete(msdp, empty_buffer_index); - } - msd_debug_nest_print(msdp->chp, "f"); - - /*Swap the ping pong buffers*/ - ping_pong_buffer_index = empty_buffer_index; - } - - if( i != total_blocks ) { - msd_debug_err_print(msdp->chp, "\r\ni!=total_blocks, %u, %u\r\n", i, total_blocks); - } - - msd_debug_nest_print(msdp->chp, "(%u,%u,%u)", rw_block_address_origional, total_blocks, i); - - } else { - /* FIXME: For some reason, when doing a blkRead on a SanDisk 8g sd card, it takes 2.5ms to read a block, limiting - * max read performance to about 200k/s. However, when using an 8g transcend SD card, we can get up to 2.0 megabytes/sec - * read through put. What's the difference? configuration for the SD driver? - */ - - i = 0; - /* read the first block from block device */ - read_success = FALSE; - for (retry_count = 0; retry_count < 3; retry_count++) { - if (blkRead(msdp->bbdp, rw_block_address, read_buffer[i % 2], 1) - == HAL_FAILED) { - msd_debug_err_print(msdp->chp, "\r\nSD Block Read Error: block # %u\r\n", rw_block_address); - msdp->read_error_count++; - } else { - msdp->read_success_count++; - if( retry_count > 0 ) { - msd_debug_err_print(msdp->chp, "Successful Block Read Retry\r\n"); - } - read_success = TRUE; - break; - } - } - - - if ((!read_success) ) { - msd_debug_err_print(msdp->chp, "\r\nSD Block Read Error 1, breaking read sequence, block # %u\r\n", rw_block_address); - - /*wait for printing to finish*/ - chThdSleepMilliseconds(10); - - msdp->command_succeeded_flag = false; - msdp->stall_in_endpoint = true; - - msd_debug_err_print( - msdp->chp, "\r\nSetting sense code %u\r\n", SCSI_SENSE_KEY_MEDIUM_ERROR); - - SCSISetSense(msdp, SCSI_SENSE_KEY_MEDIUM_ERROR, - SCSI_ASENSE_UNRECOVERED_READ_ERROR, - SCSI_ASENSEQ_NO_QUALIFIER); - - return MSD_WAIT_MODE_NONE; - } - - rw_block_address++; - - /* loop over each block */ - for (i = 0; i < total_blocks; i++) { - - /* transmit the block */ - //while (usbGetTransmitStatusI(msdp->usbp, msdp->ms_ep_number)) { - //wait for the prior transmit to complete - //} - usbStartTransmitI(msdp->usbp, msdp->ms_ep_number, read_buffer[i % 2], - msdp->block_dev_info.blk_size); - - if (i < (total_blocks - 1)) { - /* there is at least one more block to be read from device */ - /* so read that while the USB transfer takes place */ - read_success = FALSE; - MSD_R_LED_ON(); - for (retry_count = 0; retry_count < 3; retry_count++) { - if (blkRead(msdp->bbdp, rw_block_address, read_buffer[(i+1) % 2], 1) - == HAL_FAILED) { - msd_debug_err_print(msdp->chp, "\r\nSD Block Read Error 2: block # %u\r\n", rw_block_address); - - msdp->read_error_count++; - } else { - if( retry_count > 0 ) { - msd_debug_err_print(msdp->chp, "Successful Block Read Retry: block # %u\r\n", rw_block_address); - } - read_success = TRUE; - msdp->read_success_count++; - break; - } - } - MSD_R_LED_OFF(); - - if( !read_success ) { - msd_debug_err_print( - msdp->chp, "\r\nSD Block Read Error 22, addr=%d, halting\r\n", rw_block_address); - - /*wait for printing to finish*/ - chThdSleepMilliseconds(70); - - msdp->command_succeeded_flag = false; - msdp->stall_in_endpoint = true; - - msd_debug_err_print( - msdp->chp, "\r\nSetting sense code %u\r\n", SCSI_SENSE_KEY_MEDIUM_ERROR); - - SCSISetSense(msdp, SCSI_SENSE_KEY_MEDIUM_ERROR, - SCSI_ASENSE_UNRECOVERED_READ_ERROR, - SCSI_ASENSEQ_NO_QUALIFIER); - return MSD_WAIT_MODE_NONE; - } - - rw_block_address++; - } - - /*FIXME In the event that the USB connection is unplugged while we're waiting for a bulk - * endpoint ISR, this will never return, and when re-plugged into the host, the drive will - * not show back up on the host. We need a way to break out of this loop when disconnected from the bus. - */ - - if (msdWaitForISR(msdp, TRUE, MSD_WAIT_MODE_BULK_IN) == WAIT_ISR_BUSS_RESET_OR_RECONNECT) { - //fixme are we handling the reset case properly - return MSD_WAIT_MODE_NONE; - } - } - } - msd_debug_nest_print(msdp->chp, "g"); - - /* don't wait for ISR */ - return MSD_WAIT_MODE_NONE; -} - -static msd_wait_mode_t SCSICommandStartStopUnit(USBMassStorageDriver *msdp) { - scsi_start_stop_unit_request_t *ssu = - (scsi_start_stop_unit_request_t *)&(msdp->cbw.scsi_cmd_data); - - if ((ssu->loej_start & 0x3) == 2) { - /* device has been ejected */ - if (!msdp->disable_usb_bus_disconnect_on_eject) { - chEvtBroadcast(&msdp->evt_ejected); - msdp->state = MSD_STATE_EJECTED; - } - } - - /* don't wait for ISR */ - return MSD_WAIT_MODE_NONE; -} - -static msd_wait_mode_t SCSICommandPreventAllowMediumRemovial(USBMassStorageDriver *msdp) { - msd_cbw_t *cbw = &(msdp->cbw); - - if( (cbw->scsi_cmd_data[4] & 0x01) ) { - //prohibit media removal - if( msdp->enable_media_removial ) { - //this can have positive performance - msdp->command_succeeded_flag = false; - SCSISetSense(msdp, SCSI_SENSE_KEY_ILLEGAL_REQUEST, - SCSI_ASENSE_INVALID_COMMAND, SCSI_ASENSEQ_NO_QUALIFIER); - } - } - - /* don't wait for ISR */ - return MSD_WAIT_MODE_NONE; -} - - - -static msd_wait_mode_t SCSICommandModeSense6(USBMassStorageDriver *msdp) { - //FIXME check for unsupported mode page set sense code, see page 161(144) of USB Mass storage book - memset(&msdp->data.mode_sense6_response, 0, sizeof(msdp->data.mode_sense6_response)); - msdp->data.mode_sense6_response.mode_data_length = 3; - if( blkIsWriteProtected(msdp->bbdp) ) { - msdp->data.mode_sense6_response.device_specifc_paramters |= (1<<7); - } - - usbStartTransmitI(msdp->usbp, msdp->ms_ep_number, (uint8_t*)&msdp->data.mode_sense6_response, 4); - - /* wait for ISR */ - return MSD_WAIT_MODE_BULK_IN; -} - -static msd_wait_mode_t msdWaitForCommandBlock(USBMassStorageDriver *msdp) { - usbStartReceiveI(msdp->usbp, msdp->ms_ep_number, (uint8_t *)&msdp->cbw, - sizeof(msd_cbw_t)); - - msdp->state = MSD_STATE_READ_CMD_BLOCK; - - return(MSD_WAIT_MODE_BULK_OUT);/* wait for ISR */ -} - -/* */ -/** - * @brief A command block has been received - - * - * @param[in] p1 description of parameter one - * @param[out] p2 description of parameter two - * @param[in,out] p3 description of parameter three - * @return Description of the returned value, must be omitted if - * a function returns void. - * @retval TRUE On success - * @retval FALSE On failure - * - */ -static msd_wait_mode_t msdProcessCommandBlock(USBMassStorageDriver *msdp) { - msd_cbw_t *cbw = &(msdp->cbw); - - /* by default transition back to the idle state */ - msdp->state = MSD_STATE_IDLE; - - msd_debug_print(msdp->chp, " CMD 0x%X\r\n", cbw->scsi_cmd_data[0]); - msdp->command_succeeded_flag = true; - msdp->stall_in_endpoint = false; - msdp->stall_out_endpoint = false; - msd_wait_mode_t wait_mode = MSD_WAIT_MODE_NONE; - - - /* check the command */ - if ((cbw->signature != MSD_CBW_SIGNATURE) || (cbw->lun > 0) - || ((cbw->data_len > 0) && (cbw->flags & 0x1F)) - || (cbw->scsi_cmd_len == 0) || (cbw->scsi_cmd_len > 16)) - { - - msdp->scsi_command_state = "Bad CBW"; - msd_debug_err_print(msdp->chp, "Bad CBW, sig=0x%X, lun=0x%X, data_len=0x%X, flags=0x%X, scsi_cmd_len=0x%X\r\n", cbw->signature, cbw->lun, cbw->data_len, cbw->flags, cbw->scsi_cmd_len); - /* stall both IN and OUT endpoints */ - msdp->stall_out_endpoint = true; - msdp->stall_in_endpoint = true; - msdp->command_succeeded_flag = false; - SCSISetSense(msdp, SCSI_SENSE_KEY_ILLEGAL_REQUEST, - SCSI_ASENSE_INVALID_FIELD_IN_CDB, SCSI_ASENSEQ_NO_QUALIFIER); - -#if 0 - chSysLock(); - msdp->bulk_out_interupt_flag = false; - usbStallReceiveI(msdp->usbp, msdp->ms_ep_number); - //usbStallTransmitI(msdp->usbp, msdp->ms_ep_number); - chSysUnlock(); - - //wait for the host to clear the stall - msdWaitForISR(msdp, TRUE, MSD_WAIT_MODE_BULK_OUT); - - /* don't wait for ISR */ - return MSD_WAIT_MODE_NONE; -#endif - } - - - if( msdp->command_succeeded_flag ) { - switch ( (msd_scsi_command_t) cbw->scsi_cmd_data[0] ) { - case SCSI_CMD_INQUIRY: - msdp->scsi_command_state = "CMD_INQ"; - msd_debug_print(msdp->chp, "CMD_INQ\r\n"); - wait_mode = SCSICommandInquiry(msdp); - msdp->scsi_command_state = "CMD_INQ-Done"; - break; - case SCSI_CMD_REQUEST_SENSE_6: - msdp->scsi_command_state = "CMD_RS"; - msd_debug_print(msdp->chp, "\r\nCMD_RS\r\n"); - wait_mode = SCSICommandRequestSense(msdp); - msdp->scsi_command_state = "CMD_RS-Done"; - break; - case SCSI_CMD_READ_FORMAT_CAPACITY: - msdp->scsi_command_state = "CMD_RFC"; - msd_debug_print(msdp->chp, "CMD_RFC\r\n"); - wait_mode = SCSICommandReadFormatCapacity(msdp); - msdp->scsi_command_state = "CMD_RFC-Done"; - break; - case SCSI_CMD_READ_CAPACITY_10: - msdp->scsi_command_state = "CMD_RC10"; - msd_debug_print(msdp->chp, "CMD_RC10\r\n"); - wait_mode = SCSICommandReadCapacity10(msdp); - msdp->scsi_command_state = "CMD_RC10-Done"; - break; - case SCSI_CMD_READ_10: - case SCSI_CMD_WRITE_10: - msdp->scsi_command_state = "CMD_RW"; - msd_debug_print(msdp->chp, "CMD_RW\r\n"); - MSD_RW_LED_ON(); - wait_mode = SCSICommandStartReadWrite10(msdp); - MSD_RW_LED_OFF(); - msdp->scsi_command_state = "CMD_RW-Done"; - break; - case SCSI_CMD_SEND_DIAGNOSTIC: - msdp->scsi_command_state = "CMD_DIA"; - msd_debug_print(msdp->chp, "CMD_DIA\r\n"); - wait_mode = SCSICommandSendDiagnostic(msdp); - msdp->scsi_command_state = "CMD_DIA-Done"; - break; - case SCSI_CMD_PREVENT_ALLOW_MEDIUM_REMOVAL: - msdp->scsi_command_state = "CMD_PAMR"; - msd_debug_print(msdp->chp, "CMD_PAMR\r\n"); - wait_mode = SCSICommandPreventAllowMediumRemovial(msdp); - msdp->scsi_command_state = "CMD_PAMR-Done"; - break; - case SCSI_CMD_TEST_UNIT_READY: - case SCSI_CMD_VERIFY_10: - msdp->scsi_command_state = "CMD_00_1E_2F"; - msd_debug_print(msdp->chp, "CMD_00_1E_2F\r\n"); - msdp->scsi_command_state = "CMD_00_1E_2F-Done"; - /* don't handle */ - break; - case SCSI_CMD_MODE_SENSE_6: - msdp->scsi_command_state = "CMD_S6"; - msd_debug_print(msdp->chp, "\r\nCMD_S6\r\n"); - wait_mode = SCSICommandModeSense6(msdp); - msdp->scsi_command_state = "CMD_S6-Done"; - break; - case SCSI_CMD_START_STOP_UNIT: - msdp->scsi_command_state = "CMD_STOP"; - msd_debug_print(msdp->chp, "CMD_STOP\r\n"); - wait_mode = SCSICommandStartStopUnit(msdp); - msdp->scsi_command_state = "CMD_STOP-Done"; - break; - case SCSI_CMD_SYNCHRONIZE_CACHE_10: - msdp->scsi_command_state = "SYNC_10"; - msd_debug_print(msdp->chp, "SYNC_10\r\n"); - //FIXME impliment this and flush data to the MMC card, Linux sends this command. We are implicitly synchronized - //in our writes since we never leave data in RAM - - SCSISetSense(msdp, SCSI_SENSE_KEY_GOOD, - SCSI_ASENSE_NO_ADDITIONAL_INFORMATION, SCSI_ASENSEQ_NO_QUALIFIER); - wait_mode = MSD_WAIT_MODE_NONE; - - msdp->scsi_command_state = "SYNC_10-Done"; - break; - default: - msdp->last_bad_scsi_command = cbw->scsi_cmd_data[0]; - - msdp->scsi_command_state = "CMD_Def"; - msd_debug_err_print(msdp->chp, "CMD Unknown: 0x%X, using default CMD handler\r\n", cbw->scsi_cmd_data[0]); - msdp->command_succeeded_flag = false; - SCSISetSense(msdp, SCSI_SENSE_KEY_ILLEGAL_REQUEST, - SCSI_ASENSE_INVALID_COMMAND, SCSI_ASENSEQ_NO_QUALIFIER); - -#if 0 - /* stall IN endpoint */ - chSysLock() - msdp->bulk_in_interupt_flag = false; - usbStallTransmitI(msdp->usbp, msdp->ms_ep_number); - chSysUnlock() - - msdWaitForISR(msdp, TRUE, MSD_WAIT_MODE_BULK_IN); -#else - //msdp->stall_out_endpoint = true; - //msdp->stall_in_endpoint = true; -#endif - - msdp->scsi_command_state = "CMD_Def-Done"; - cbw->data_len = 0; -#if 0 - return MSD_WAIT_MODE_NONE; -#endif - } - } - - cbw->data_len = 0; - - - if( msdp->stall_in_endpoint || msdp->stall_out_endpoint ) { - msdp->scsi_command_state = "Stall"; - /* stall IN endpoint */ - chSysLock(); - if( msdp->stall_in_endpoint ) { - msd_debug_err_print(msdp->chp, "stalling IN endpoint\r\n"); - msdp->bulk_in_interupt_flag = false; - usbStallTransmitI(msdp->usbp, msdp->ms_ep_number); - } - if( msdp->stall_out_endpoint ) { - msd_debug_err_print(msdp->chp, "stalling OUT endpoint\r\n"); - msdp->bulk_out_interupt_flag = false; - usbStallReceiveI(msdp->usbp, msdp->ms_ep_number); - } - chSysUnlock(); - - if( msdp->stall_in_endpoint ) { - msdWaitForISR(msdp, TRUE, MSD_WAIT_MODE_BULK_IN); - } - - if( msdp->stall_out_endpoint ) { - msdWaitForISR(msdp, TRUE, MSD_WAIT_MODE_BULK_OUT); - } - } - - msdp->scsi_command_state = "Wait"; - - if (wait_mode != MSD_WAIT_MODE_NONE ) { - msd_debug_nest_print(msdp->chp, "H"); - if (msdWaitForISR(msdp, TRUE, wait_mode) == WAIT_ISR_BUSS_RESET_OR_RECONNECT) { - msd_debug_nest_print(msdp->chp, "h"); - return (MSD_WAIT_MODE_NONE); - } - msd_debug_nest_print(msdp->chp, "h"); - } - - msdp->scsi_command_state = "Wait-Done"; - - msd_csw_t *csw = &(msdp->csw); - - - csw->status = (msdp->command_succeeded_flag) ? MSD_COMMAND_PASSED : MSD_COMMAND_FAILED; - csw->signature = MSD_CSW_SIGNATURE; - csw->data_residue = cbw->data_len; - csw->tag = cbw->tag; - - msdp->scsi_command_state = "TX"; - msd_debug_nest_print(msdp->chp, "I"); - usbStartTransmitI(msdp->usbp, msdp->ms_ep_number, (uint8_t *)csw, - sizeof(msd_csw_t)); - - chSysLock(); - msdp->bulk_out_interupt_flag = false; - msdWaitForCommandBlock(msdp); - - msdp->bulk_in_interupt_flag = false; - chSysUnlock(); - msd_debug_nest_print(msdp->chp, "i"); - - msdWaitForISR(msdp, TRUE, MSD_WAIT_MODE_BULK_IN);//wait for our status to be sent back - - msdp->scsi_command_state = "Done All"; - - /* wait on ISR */ - //return MSD_WAIT_MODE_BULK_IN; - return MSD_WAIT_MODE_BULK_OUT; -} - - - - - -/*===========================================================================*/ -/* Threads */ -/*===========================================================================*/ - -/** - * @brief This thread is responsible for triggering a USB write of date - * from the MCU to the host. It is run as a separate thread to allow - * for concurrent RXing of data and writing of data to the SD card to - * thus significantly improve performance. - * - * @param[in] arg pointer to the @p USBMassStorageDriver object - * - * @special - */ -THD_FUNCTION(MassStorageUSBTransferThd, arg) { - USBMassStorageDriver *msdp = (USBMassStorageDriver *)arg; - - chRegSetThreadName("MSD-Transfer"); - - while ( !chThdShouldTerminateX() ) { - if (msdp->suspend_threads_callback != NULL && msdp->suspend_threads_callback()) { - /* Suspend the thread for power savings mode */ - chSysLock(); - chSchGoSleepS(CH_STATE_SUSPENDED); - chSysUnlock(); - } - - if (msdp->trigger_transfer_index != UINT32_MAX) { - msdp->transfer_thread_state = "PP"; - SCSIWriteTransferPingPong( - msdp, &rw_ping_pong_buffer[msdp->trigger_transfer_index]); - msdp->trigger_transfer_index = UINT32_MAX; - /*notify other thread*/ - chBSemSignal(&msdp->mass_sorage_thd_bsem); - } - - chBSemWaitTimeout(&msdp->usb_transfer_thread_bsem, MS2ST(1)); - } - -} - - - -THD_FUNCTION(MassStorageThd, arg) { - USBMassStorageDriver *msdp = (USBMassStorageDriver *)arg; - chRegSetThreadName("MSD"); - - msd_wait_mode_t wait_for_isr = MSD_WAIT_MODE_NONE; - - /* wait for the usb to be initialized */ - msd_debug_print(msdp->chp, "Y"); - msdWaitForISR(msdp, FALSE, MSD_WAIT_MODE_NONE); - msd_debug_print(msdp->chp, "y"); - - while ( !chThdShouldTerminateX() ) { - -#if 0 - if( msdp->suspend_threads_callback != NULL && msdp->suspend_threads_callback() ) { - /* Suspend the thread for power savings mode */ - chSysLock(); - chSchGoSleepS(CH_STATE_SUSPENDED); - chSysUnlock(); - } -#endif - - - wait_for_isr = MSD_WAIT_MODE_NONE; - - if (msdp->reconfigured_or_reset_event) { - /*If the devices is unplugged and re-plugged but did not have a CPU reset, - * we must set the state back to idle.*/ - msdp->reconfigured_or_reset_event = FALSE; - msdp->state = MSD_STATE_IDLE; - - msdSetDefaultSenseKey(msdp); - } - - bool enable_msd = true; - if (msdp->enable_msd_callback != NULL) { - enable_msd = msdp->enable_msd_callback(); - } - - if( msdp->driver_state != USB_MSD_DRIVER_OK ) { - enable_msd = false; - } - msdp->debug_enable_msd = enable_msd; - - if ( enable_msd ) { - - if( ! msdp->block_dev_info_valid_flag ) { - if( blkGetDriverState(msdp->bbdp) == BLK_READY ) { - blkGetInfo(msdp->bbdp, &msdp->block_dev_info); - msdp->block_dev_info_valid_flag = true; - } - } - - msd_debug_print(msdp->chp, "state=%d\r\n", msdp->state); - /* wait on data depending on the current state */ - switch (msdp->state) { - case MSD_STATE_IDLE: - msdp->msd_thread_state = "IDL"; - msd_debug_print(msdp->chp, "IDL"); - wait_for_isr = msdWaitForCommandBlock(msdp); - msd_debug_print(msdp->chp, "x\r\n"); - break; - case MSD_STATE_READ_CMD_BLOCK: - msdp->msd_thread_state = "RCB"; - msd_debug_print(msdp->chp, "RCB"); - wait_for_isr = msdProcessCommandBlock(msdp); - msd_debug_print(msdp->chp, "x\r\n"); - break; - case MSD_STATE_EJECTED: - /* disconnect usb device */ - msd_debug_print(msdp->chp, "ejected\r\n"); - if (!msdp->disable_usb_bus_disconnect_on_eject) { - msdp->msd_thread_state = "Ejected"; - chThdSleepMilliseconds(70); - usbDisconnectBus(msdp->usbp); - usbStop(msdp->usbp); - chThdExit(0); - } - } - } - - msdp->debug_wait_for_isr = wait_for_isr; - - if( enable_msd ) { - msd_debug_nest_print(msdp->chp, "L"); - } else { - msd_debug_nest_print(msdp->chp, "M"); - } - - if (wait_for_isr) { - msd_debug_nest_print(msdp->chp, "J"); - } else { - msd_debug_nest_print(msdp->chp, "K"); - } - - if (wait_for_isr && (!msdp->reconfigured_or_reset_event)) { - /* wait until the ISR wakes thread */ - msd_debug_print(msdp->chp, "W%d,%d", wait_for_isr, msdp->state); - msdWaitForISR(msdp, TRUE, wait_for_isr); - msd_debug_print(msdp->chp, "w\r\n"); - } else if( ! enable_msd ) { - chThdSleepMilliseconds(5); - } - - - if (wait_for_isr) { - msd_debug_nest_print(msdp->chp, "j"); - } else { - msd_debug_nest_print(msdp->chp, "k"); - } - } - -} - - - - - -#endif /* HAL_USE_MASS_STORAGE_USB */ diff --git a/firmware/hw_layer/mass_storage/usb_msd.h b/firmware/hw_layer/mass_storage/usb_msd.h deleted file mode 100644 index 049391fd9e..0000000000 --- a/firmware/hw_layer/mass_storage/usb_msd.h +++ /dev/null @@ -1,311 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#ifndef _USB_MSD_H_ -#define _USB_MSD_H_ - -#include "hal.h" - -/* Default to disabled for USB Mass Storage */ -#if !defined(HAL_USE_MASS_STORAGE_USB) -# define HAL_USE_MASS_STORAGE_USB TRUE -#endif - -#if HAL_USE_MASS_STORAGE_USB || defined(__DOXYGEN__) - -#ifndef PACK_STRUCT_BEGIN -#define PACK_STRUCT_BEGIN -#endif - -#ifndef PACK_STRUCT_STRUCT -#define PACK_STRUCT_STRUCT -#endif - -#ifndef PACK_STRUCT_END -#define PACK_STRUCT_END -#endif - -#if 0 -#define MSD_RW_LED_ON() palSetPad(GPIOI, GPIOI_TRI_LED_BLUE) -#define MSD_RW_LED_OFF() palClearPad(GPIOI, GPIOI_TRI_LED_BLUE) -#define MSD_R_LED_ON() palSetPad(GPIOI, GPIOI_TRI_LED_BLUE) -#define MSD_R_LED_OFF() palClearPad(GPIOI, GPIOI_TRI_LED_BLUE) -#define MSD_W_LED_ON() palSetPad(GPIOH, GPIOI_TRI_LED_BLUE) -#define MSD_W_LED_OFF() palClearPad(GPIOH, GPIOI_TRI_LED_BLUE) -#else -#define MSD_RW_LED_ON() -#define MSD_RW_LED_OFF() -#define MSD_R_LED_ON() -#define MSD_R_LED_OFF() -#define MSD_W_LED_ON() -#define MSD_W_LED_OFF() -#endif - - -#if STM32_USB_USE_OTG2 && STM32_USE_USB_OTG2_HS -# define USB_MS_EP_SIZE 512 -#else -# define USB_MS_EP_SIZE 64 -#endif - -#define MSD_THREAD_STACK_SIZE 1024 - -#define MSD_REQ_RESET 0xFF -#define MSD_GET_MAX_LUN 0xFE -#define MSD_CBW_SIGNATURE 0x43425355 -#define MSD_CSW_SIGNATURE 0x53425355 -#define MSD_COMMAND_DIR_DATA_OUT (0 << 7) -#define MSD_COMMAND_DIR_DATA_IN (1 << 7) - -#define MSD_SETUP_WORD(setup, index) (uint16_t)(((uint16_t)setup[index+1] << 8) | (setup[index] & 0x00FF)) - -#define MSD_SETUP_VALUE(setup) MSD_SETUP_WORD(setup, 2) -#define MSD_SETUP_INDEX(setup) MSD_SETUP_WORD(setup, 4) -#define MSD_SETUP_LENGTH(setup) MSD_SETUP_WORD(setup, 6) - -typedef enum { - SCSI_CMD_TEST_UNIT_READY = 0x00, - SCSI_CMD_REQUEST_SENSE_6 = 0x03, - SCSI_CMD_INQUIRY = 0x12, - SCSI_CMD_MODE_SENSE_6 = 0x1A, - SCSI_CMD_START_STOP_UNIT = 0x1B, - SCSI_CMD_SEND_DIAGNOSTIC = 0x1D, - SCSI_CMD_PREVENT_ALLOW_MEDIUM_REMOVAL = 0x1E, - SCSI_CMD_READ_FORMAT_CAPACITY = 0x23, - SCSI_CMD_READ_CAPACITY_10 = 0x25, - SCSI_CMD_READ_10 = 0x28, - SCSI_CMD_WRITE_10 = 0x2A, - SCSI_CMD_VERIFY_10 = 0x2F, - SCSI_CMD_SYNCHRONIZE_CACHE_10 = 0x35, -} msd_scsi_command_t; - - - -#define MSD_COMMAND_PASSED 0x00 -#define MSD_COMMAND_FAILED 0x01 -#define MSD_COMMAND_PHASE_ERROR 0x02 - -#define SCSI_SENSE_KEY_GOOD 0x00 -#define SCSI_SENSE_KEY_RECOVERED_ERROR 0x01 -#define SCSI_SENSE_KEY_NOT_READY 0x02 -#define SCSI_SENSE_KEY_MEDIUM_ERROR 0x03 -#define SCSI_SENSE_KEY_HARDWARE_ERROR 0x04 -#define SCSI_SENSE_KEY_ILLEGAL_REQUEST 0x05 -#define SCSI_SENSE_KEY_UNIT_ATTENTION 0x06 -#define SCSI_SENSE_KEY_DATA_PROTECT 0x07 -#define SCSI_SENSE_KEY_BLANK_CHECK 0x08 -#define SCSI_SENSE_KEY_VENDOR_SPECIFIC 0x09 -#define SCSI_SENSE_KEY_COPY_ABORTED 0x0A -#define SCSI_SENSE_KEY_ABORTED_COMMAND 0x0B -#define SCSI_SENSE_KEY_VOLUME_OVERFLOW 0x0D -#define SCSI_SENSE_KEY_MISCOMPARE 0x0E - -#define SCSI_ASENSE_NO_ADDITIONAL_INFORMATION 0x00 -#define SCSI_ASENSE_PEREPHERIAL_DEVICE_WRITE_FAULT 0x03 -#define SCSI_ASENSE_LOGICAL_UNIT_NOT_READY 0x04 -#define SCSI_ASENSE_UNRECOVERED_READ_ERROR 0x11 -#define SCSI_ASENSE_INVALID_COMMAND 0x20 -#define SCSI_ASENSE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE 0x21 -#define SCSI_ASENSE_INVALID_FIELD_IN_CDB 0x24 -#define SCSI_ASENSE_WRITE_PROTECTED 0x27 -#define SCSI_ASENSE_NOT_READY_TO_READY_CHANGE 0x28 -#define SCSI_ASENSE_FORMAT_ERROR 0x31 -#define SCSI_ASENSE_MEDIUM_NOT_PRESENT 0x3A - -#define SCSI_ASENSEQ_NO_QUALIFIER 0x00 -#define SCSI_ASENSEQ_PEREPHERIAL_DEVICE_WRITE_FAULT 0x00 -#define SCSI_ASENSEQ_FORMAT_COMMAND_FAILED 0x01 -#define SCSI_ASENSEQ_INITIALIZING_COMMAND_REQUIRED 0x02 -#define SCSI_ASENSEQ_OPERATION_IN_PROGRESS 0x07 - - -PACK_STRUCT_BEGIN typedef struct { - uint32_t signature; - uint32_t tag; - uint32_t data_len; - uint8_t flags; - uint8_t lun; - uint8_t scsi_cmd_len; - uint8_t scsi_cmd_data[16]; -} PACK_STRUCT_STRUCT msd_cbw_t PACK_STRUCT_END; - -PACK_STRUCT_BEGIN typedef struct { - uint32_t signature; - uint32_t tag; - uint32_t data_residue; - uint8_t status; -} PACK_STRUCT_STRUCT msd_csw_t PACK_STRUCT_END; - -typedef struct { - uint8_t byte[18]; -} PACK_STRUCT_STRUCT scsi_sense_response_t; - -typedef struct { - uint8_t mode_data_length; //Number of bytes that follow - uint8_t medium_type; //0x00 for SBC devices - uint8_t device_specifc_paramters; //bit 7 is the write protect bit - uint8_t block_descriptor_length; //Length in bytes of all block descriptors in the mode parameter list. -} PACK_STRUCT_STRUCT scsi_mode_sense6_response_t; - -PACK_STRUCT_BEGIN typedef struct -{ - uint8_t peripheral; - uint8_t removable; - uint8_t version; - uint8_t response_data_format; - uint8_t additional_length; - uint8_t sccstp; - uint8_t bqueetc; - uint8_t cmdque; - uint8_t vendorID[8]; - uint8_t productID[16]; - uint8_t productRev[4]; -} PACK_STRUCT_STRUCT scsi_inquiry_response_t PACK_STRUCT_END; - -PACK_STRUCT_BEGIN typedef struct { - uint8_t payload_byte_length[4]; - uint32_t last_block_addr; - uint32_t block_size; -} PACK_STRUCT_STRUCT scsi_read_format_capacity_response_t PACK_STRUCT_END; - -PACK_STRUCT_BEGIN typedef struct { - uint32_t last_block_addr; - uint32_t block_size; -} PACK_STRUCT_STRUCT scsi_read_capacity10_response_t PACK_STRUCT_END; - -PACK_STRUCT_BEGIN typedef struct { - uint8_t op_code; - uint8_t lun_immed; - uint8_t res1; - uint8_t res2; - uint8_t loej_start; - uint8_t control; -} PACK_STRUCT_STRUCT scsi_start_stop_unit_request_t; - - - -typedef enum { - MSD_WAIT_MODE_NONE = 0, - MSD_WAIT_MODE_BULK_IN, - MSD_WAIT_MODE_BULK_OUT -} msd_wait_mode_t; - -typedef enum { - MSD_STATE_IDLE = 0, - MSD_STATE_READ_CMD_BLOCK, - MSD_STATE_EJECTED -} msd_state_t; - -typedef enum { - USB_MSD_DRIVER_UNINITIALIZED = 0, - USB_MSD_DRIVER_ERROR, - USB_MSD_DRIVER_OK, - USB_MSD_DRIVER_STOPPED, - USB_MSD_DRIVER_ERROR_BLK_DEV_NOT_READY, -} usb_msd_driver_state_t; - -typedef struct USBMassStorageDriver USBMassStorageDriver; - -struct USBMassStorageDriver { - /* Driver Setup Data */ - USBDriver *usbp; - BaseBlockDevice *bbdp; - event_source_t evt_connected; - event_source_t evt_ejected; - BlockDeviceInfo block_dev_info; - bool block_dev_info_valid_flag; - usb_msd_driver_state_t driver_state; - usbep_t ms_ep_number; - uint16_t msd_interface_number; - bool (*enable_msd_callback)(void); - bool (*suspend_threads_callback)(void); - - /* Externally modifiable settings */ - bool enable_media_removial; - bool disable_usb_bus_disconnect_on_eject; - BaseSequentialStream *chp; /*For debug logging*/ - - /*Internal data for operation of the driver */ - binary_semaphore_t bsem; - binary_semaphore_t usb_transfer_thread_bsem; - binary_semaphore_t mass_sorage_thd_bsem; - volatile uint32_t trigger_transfer_index; - - volatile bool bulk_in_interupt_flag; - volatile bool bulk_out_interupt_flag; - - struct { - scsi_read_format_capacity_response_t format_capacity_response; - scsi_read_capacity10_response_t read_capacity10_response; - scsi_mode_sense6_response_t mode_sense6_response; - uint8_t max_lun_len_buf[1]; - scsi_inquiry_response_t scsi_inquiry_response; - } data; - - msd_state_t state; - msd_cbw_t cbw; - msd_csw_t csw; - scsi_sense_response_t sense; - - volatile bool reconfigured_or_reset_event; - - bool command_succeeded_flag; - bool stall_in_endpoint; - bool stall_out_endpoint; - - - /*Debugging Information*/ - volatile uint32_t read_error_count; - volatile uint32_t write_error_count; - volatile uint32_t read_success_count; - volatile uint32_t write_success_count; - char *msd_thread_state; - char *transfer_thread_state; - char *scsi_command_state; - volatile uint8_t last_bad_scsi_command; - - /* Externally readable values */ - volatile bool debug_enable_msd; - volatile msd_wait_mode_t debug_wait_for_isr; - - THD_WORKING_AREA(waMassStorage, MSD_THREAD_STACK_SIZE); - THD_WORKING_AREA(waMassStorageUSBTransfer, MSD_THREAD_STACK_SIZE); -}; - - -#ifdef __cplusplus -extern "C" { -#endif -usb_msd_driver_state_t msdInit(USBDriver *usbp, BaseBlockDevice *bbdp, USBMassStorageDriver *msdp, const usbep_t ms_ep_number, const uint16_t msd_interface_number); -usb_msd_driver_state_t msdStart(USBMassStorageDriver *msdp); -usb_msd_driver_state_t msdStop(USBMassStorageDriver *msdp); -void msdBulkInCallbackComplete(USBDriver *usbp, usbep_t ep); -void msdBulkOutCallbackComplete(USBDriver *usbp, usbep_t ep); -bool msdRequestsHook(USBDriver *usbp); -bool msdRequestsHook2(USBDriver *usbp, USBMassStorageDriver *msdp); -const char* usb_msd_driver_state_t_to_str(const usb_msd_driver_state_t driver_state); -#ifdef __cplusplus -} -#endif - - -#endif /* HAL_USE_MASS_STORAGE_USB */ - -#endif /* _USB_MSD_H_ */ diff --git a/firmware/hw_layer/mass_storage/usb_msd_cfg.c b/firmware/hw_layer/mass_storage/usb_msd_cfg.c index d5927a546c..6421ce7ace 100644 --- a/firmware/hw_layer/mass_storage/usb_msd_cfg.c +++ b/firmware/hw_layer/mass_storage/usb_msd_cfg.c @@ -1,43 +1,41 @@ /* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - This file is part of ChibiOS/RT. + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. + http://www.apache.org/licenses/LICENSE-2.0 - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. */ -#include "ch.h" #include "hal.h" + +#include "hal_usb_msd.h" #include "usb_msd_cfg.h" -#include "usb_msd.h" - - +/* + * must be 64 for full speed and 512 for high speed + */ +#define USB_MSD_EP_SIZE 64U /* * USB Device Descriptor. */ static const uint8_t msd_device_descriptor_data[18] = { USB_DESC_DEVICE (0x0200, /* bcdUSB (2.0). */ - 0x00, /* bDeviceClass (None). */ + 0x02, /* bDeviceClass (CDC). */ 0x00, /* bDeviceSubClass. */ 0x00, /* bDeviceProtocol. */ - 0x40, /* Control Endpoint Size. */ + 0x40, /* bMaxPacketSize. */ 0x0483, /* idVendor (ST). */ 0x5742, /* idProduct. */ - 0x0100, /* bcdDevice. */ + 0x0200, /* bcdDevice. */ 1, /* iManufacturer. */ 2, /* iProduct. */ 3, /* iSerialNumber. */ @@ -52,34 +50,34 @@ static const USBDescriptor msd_device_descriptor = { msd_device_descriptor_data }; -/* Configuration Descriptor tree*/ -static const uint8_t msd_configuration_descriptor_data[] = { - /* Configuration Descriptor.*/ - USB_DESC_CONFIGURATION(0x0020, /* wTotalLength. */ - 0x01, /* bNumInterfaces. */ - 0x01, /* bConfigurationValue. */ - 0, /* iConfiguration. */ - 0xC0, /* bmAttributes (self powered). */ - 0x32), /* bMaxPower (100mA). */ - /* Interface Descriptor.*/ - USB_DESC_INTERFACE (USB_MSD_INTERFACE_NUMBER, /* bInterfaceNumber. */ - 0x00, /* bAlternateSetting. */ - 0x02, /* bNumEndpoints. */ - 0x08, /* bInterfaceClass (Mass Storage) */ - 0x06, /* bInterfaceSubClass (SCSI - Transparent storage class) */ - 0x50, /* bInterfaceProtocol (Bulk Only) */ - 0), /* iInterface. (none) */ - /* Mass Storage Data In Endpoint Descriptor.*/ - USB_DESC_ENDPOINT (USB_MS_DATA_EP|0x80, - 0x02, /* bmAttributes (Bulk). */ - USB_MS_EP_SIZE,/* wMaxPacketSize. */ - 0x05), /* bInterval. 1ms */ - /* Mass Storage Data In Endpoint Descriptor.*/ - USB_DESC_ENDPOINT (USB_MS_DATA_EP, - 0x02, /* bmAttributes (Bulk). */ - USB_MS_EP_SIZE,/* wMaxPacketSize. */ - 0x05) /* bInterval. 1ms */ +/* Configuration Descriptor tree for a CDC.*/ +static const uint8_t msd_configuration_descriptor_data[67] = { + /* Configuration Descriptor.*/ + USB_DESC_CONFIGURATION(0x0020, /* wTotalLength. */ + 0x01, /* bNumInterfaces. */ + 0x01, /* bConfigurationValue. */ + 0, /* iConfiguration. */ + 0xC0, /* bmAttributes (self powered). */ + 0x32), /* bMaxPower (100mA). */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x00, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x02, /* bNumEndpoints. */ + 0x08, /* bInterfaceClass (Mass Storage) */ + 0x06, /* bInterfaceSubClass (SCSI + Transparent storage class) */ + 0x50, /* bInterfaceProtocol (Bulk Only) */ + 0), /* iInterface. (none) */ + /* Mass Storage Data In Endpoint Descriptor.*/ + USB_DESC_ENDPOINT (USB_MSD_DATA_EP | 0x80, + 0x02, /* bmAttributes (Bulk). */ + USB_MSD_EP_SIZE, /* wMaxPacketSize. */ + 0x00), /* bInterval. 1ms */ + /* Mass Storage Data Out Endpoint Descriptor.*/ + USB_DESC_ENDPOINT (USB_MSD_DATA_EP, + 0x02, /* bmAttributes (Bulk). */ + USB_MSD_EP_SIZE, /* wMaxPacketSize. */ + 0x00) /* bInterval. 1ms */ }; /* @@ -114,17 +112,17 @@ static const uint8_t msd_string1[] = { * Device Description string. */ static const uint8_t msd_string2[] = { - USB_DESC_BYTE(58), /* bLength. */ + USB_DESC_BYTE(62), /* bLength. */ USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ - 'r', 0, 'u', 0, 's', 0, 'E', 0, 'f', 0, 'i', 0, - ' ', 0, 'M', 0, 'a', 0, 's', 0, 's', 0, ' ', 0, + 'C', 0, 'h', 0, 'i', 0, 'b', 0, 'i', 0, 'O', 0, 'S', 0, '/', 0, + 'R', 0, 'T', 0, ' ', 0, 'M', 0, 'a', 0, 's', 0, 's', 0, ' ', 0, 'S', 0, 't', 0, 'o', 0, 'r', 0, 'a', 0, 'g', 0, 'e', 0, ' ', 0, 'D', 0, 'e', 0, 'v', 0, 'i', 0, 'c', 0, 'e', 0 }; static const uint8_t msd_string3[] = { - USB_DESC_BYTE(26), /* bLength. */ - USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + USB_DESC_BYTE(26), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ 'A', 0, 'E', 0, 'C', 0, 'C', 0, 'E', 0, 'C', 0, 'C', 0, 'C', 0, 'C', 0, '0' + CH_KERNEL_MAJOR, 0, '0' + CH_KERNEL_MINOR, 0, @@ -164,53 +162,51 @@ static const USBDescriptor *get_descriptor(USBDriver *usbp, return NULL; } - - /** * @brief IN EP1 state. */ -static USBInEndpointState ep1InState; -static USBOutEndpointState ep1OutState; +static USBInEndpointState ep1instate; /** - * @brief EP1 initialization structure (IN only). + * @brief OUT EP1 state. */ -static const USBEndpointConfig epDataConfig = { +static USBOutEndpointState ep1outstate; + +/** + * @brief EP1 initialization structure (both IN and OUT). + */ +static const USBEndpointConfig ep1config = { USB_EP_MODE_TYPE_BULK, NULL, - msdBulkInCallbackComplete, - msdBulkOutCallbackComplete, - USB_MS_EP_SIZE, - USB_MS_EP_SIZE, - &ep1InState, - &ep1OutState, - 1, + NULL, + NULL, + USB_MSD_EP_SIZE, + USB_MSD_EP_SIZE, + &ep1instate, + &ep1outstate, + 4, NULL }; - /* * Handles the USB driver global events. */ static void usb_event(USBDriver *usbp, usbevent_t event) { - USBMassStorageDriver *msdp = (USBMassStorageDriver *)usbp->in_params[USB_MS_DATA_EP - 1]; + switch (event) { case USB_EVENT_RESET: - msdp->reconfigured_or_reset_event = TRUE; return; case USB_EVENT_ADDRESS: return; case USB_EVENT_CONFIGURED: chSysLockFromISR(); - msdp->reconfigured_or_reset_event = TRUE; - usbInitEndpointI(usbp, msdp->ms_ep_number, &epDataConfig); - /* Kick-start the thread */ - chBSemSignalI(&msdp->bsem); - - /* signal that the device is connected */ - chEvtBroadcastI(&msdp->evt_connected); + /* Enables the endpoints specified into the configuration. + Note, this callback is invoked from an ISR so I-Class functions + must be used.*/ + usbInitEndpointI(usbp, USBD1_DATA_REQUEST_EP, &ep1config); chSysUnlockFromISR(); - + return; + case USB_EVENT_UNCONFIGURED: return; case USB_EVENT_SUSPEND: return; @@ -222,10 +218,13 @@ static void usb_event(USBDriver *usbp, usbevent_t event) { return; } -const USBConfig msd_usb_config = { - usb_event, - get_descriptor, - msdRequestsHook, - NULL +/* + * USB driver configuration. + */ +const USBConfig msdusbcfg = { + usb_event, + get_descriptor, + msd_request_hook, + NULL }; diff --git a/firmware/hw_layer/mass_storage/usb_msd_cfg.h b/firmware/hw_layer/mass_storage/usb_msd_cfg.h index 55e91230bc..2904c0e2c0 100644 --- a/firmware/hw_layer/mass_storage/usb_msd_cfg.h +++ b/firmware/hw_layer/mass_storage/usb_msd_cfg.h @@ -22,8 +22,9 @@ #define USB_MSD_CFG_H_ -#define USB_MS_DATA_EP 1 -#define USB_MSD_INTERFACE_NUMBER 0x00 +#define USBD1_DATA_REQUEST_EP 1 +#define USBD1_DATA_AVAILABLE_EP 1 +#define USBD1_INTERRUPT_REQUEST_EP 2 #endif /* USB_MSD_CFG_H_ */ diff --git a/firmware/hw_layer/mmc_card.cpp b/firmware/hw_layer/mmc_card.cpp index 2f164ee193..f49a0a2dc3 100644 --- a/firmware/hw_layer/mmc_card.cpp +++ b/firmware/hw_layer/mmc_card.cpp @@ -24,7 +24,7 @@ #include "hardware.h" #include "engine_configuration.h" #include "status_loop.h" -#include "usb_msd.h" +#include "hal_usb_msd.h" #include "usb_msd_cfg.h" #include "rtc_helper.h" @@ -56,7 +56,7 @@ extern board_configuration_s *boardConfiguration; //static USBDriver *ms_usb_driver = &USBD1; //static USBMassStorageDriver UMSD1; -//extern const USBConfig msd_usb_config; +extern const USBConfig msdusbcfg; From 1885da1ab9f1b9057e6e9ca920337f563ecf7531 Mon Sep 17 00:00:00 2001 From: Fabien Poussin Date: Wed, 22 Mar 2017 19:45:11 +0100 Subject: [PATCH 06/74] Moving boards to config folder. --- firmware/Makefile | 3 ++- firmware/boards/ST_STM32F4_DISCOVERY/board.mk | 5 ----- firmware/{ => config}/boards/ST_STM32F4_DISCOVERY/board.c | 0 firmware/{ => config}/boards/ST_STM32F4_DISCOVERY/board.h | 0 firmware/config/boards/ST_STM32F4_DISCOVERY/board.mk | 5 +++++ 5 files changed, 7 insertions(+), 6 deletions(-) delete mode 100644 firmware/boards/ST_STM32F4_DISCOVERY/board.mk rename firmware/{ => config}/boards/ST_STM32F4_DISCOVERY/board.c (100%) rename firmware/{ => config}/boards/ST_STM32F4_DISCOVERY/board.h (100%) create mode 100644 firmware/config/boards/ST_STM32F4_DISCOVERY/board.mk diff --git a/firmware/Makefile b/firmware/Makefile index feaf57c22f..ba89cd40a7 100644 --- a/firmware/Makefile +++ b/firmware/Makefile @@ -110,7 +110,7 @@ include $(CHIBIOS)/os/various/cpp_wrappers/chcpp.mk include console/binary/tunerstudio.mk include ext/ext.mk -include $(PROJECT_DIR)/boards/$(PROJECT_BOARD)/board.mk + include $(PROJECT_DIR)/hw_layer/hw_layer.mk include $(PROJECT_DIR)/hw_layer/sensors/sensors.mk include $(PROJECT_DIR)/hw_layer/mass_storage/mass_storage.mk @@ -118,6 +118,7 @@ include development/development.mk include controllers/controllers.mk include $(PROJECT_DIR)/util/util.mk +include $(PROJECT_DIR)/config/boards/$(PROJECT_BOARD)/board.mk include $(PROJECT_DIR)/config/engines/engines.mk include $(PROJECT_DIR)/controllers/algo/algo.mk include $(PROJECT_DIR)/controllers/core/core.mk diff --git a/firmware/boards/ST_STM32F4_DISCOVERY/board.mk b/firmware/boards/ST_STM32F4_DISCOVERY/board.mk deleted file mode 100644 index 1c69b8726f..0000000000 --- a/firmware/boards/ST_STM32F4_DISCOVERY/board.mk +++ /dev/null @@ -1,5 +0,0 @@ -# List of all the board related files. -BOARDSRC = $(PROJECT_DIR)/boards/ST_STM32F4_DISCOVERY/board.c - -# Required include directories -BOARDINC = $(PROJECT_DIR)/boards/ST_STM32F4_DISCOVERY diff --git a/firmware/boards/ST_STM32F4_DISCOVERY/board.c b/firmware/config/boards/ST_STM32F4_DISCOVERY/board.c similarity index 100% rename from firmware/boards/ST_STM32F4_DISCOVERY/board.c rename to firmware/config/boards/ST_STM32F4_DISCOVERY/board.c diff --git a/firmware/boards/ST_STM32F4_DISCOVERY/board.h b/firmware/config/boards/ST_STM32F4_DISCOVERY/board.h similarity index 100% rename from firmware/boards/ST_STM32F4_DISCOVERY/board.h rename to firmware/config/boards/ST_STM32F4_DISCOVERY/board.h diff --git a/firmware/config/boards/ST_STM32F4_DISCOVERY/board.mk b/firmware/config/boards/ST_STM32F4_DISCOVERY/board.mk new file mode 100644 index 0000000000..162ec1fc16 --- /dev/null +++ b/firmware/config/boards/ST_STM32F4_DISCOVERY/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = $(PROJECT_DIR)/config/boards/ST_STM32F4_DISCOVERY/board.c + +# Required include directories +BOARDINC = $(PROJECT_DIR)/config/boards/ST_STM32F4_DISCOVERY From 8835ebee435738fcb232d7f0c8bca315a6a6f2a8 Mon Sep 17 00:00:00 2001 From: Fabien Poussin Date: Thu, 23 Mar 2017 00:16:45 +0100 Subject: [PATCH 07/74] Fixes to make the firmware run. --- firmware/Makefile | 4 +-- firmware/config/stm32f4ems/mcuconf.h | 2 +- firmware/controllers/error_handling.cpp | 2 +- firmware/hw_layer/can_hw.cpp | 4 +-- firmware/hw_layer/serial_over_usb/usbcfg.c | 31 ++++++++++++++++------ firmware/hw_layer/stm32f4/mpu_util.cpp | 2 +- firmware/hw_layer/trigger_input.cpp | 4 +-- firmware/util/rfiutil.h | 6 ++--- 8 files changed, 34 insertions(+), 21 deletions(-) diff --git a/firmware/Makefile b/firmware/Makefile index ba89cd40a7..a7b3d1f320 100644 --- a/firmware/Makefile +++ b/firmware/Makefile @@ -25,12 +25,12 @@ endif # Linker extra options here. ifeq ($(USE_LDOPT),) - USE_LDOPT = -flto=4 + USE_LDOPT = endif # Enable this if you want link time optimizations (LTO) ifeq ($(USE_LTO),) - USE_LTO = yes + USE_LTO = no endif # If enabled, this option allows to compile the application in THUMB mode. diff --git a/firmware/config/stm32f4ems/mcuconf.h b/firmware/config/stm32f4ems/mcuconf.h index 3ef5b00faf..300751e786 100644 --- a/firmware/config/stm32f4ems/mcuconf.h +++ b/firmware/config/stm32f4ems/mcuconf.h @@ -46,7 +46,7 @@ #define STM32_HSI_ENABLED TRUE #define STM32_LSI_ENABLED TRUE #define STM32_HSE_ENABLED TRUE -#define STM32_LSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE #define STM32_CLOCK48_REQUIRED TRUE #define STM32_SW STM32_SW_PLL #define STM32_PLLSRC STM32_PLLSRC_HSE diff --git a/firmware/controllers/error_handling.cpp b/firmware/controllers/error_handling.cpp index b58ed065a6..3bac9a451b 100644 --- a/firmware/controllers/error_handling.cpp +++ b/firmware/controllers/error_handling.cpp @@ -70,7 +70,7 @@ void chDbgPanic3(const char *msg, const char * file, int line) { if (!main_loop_started) { print("fatal %s %s:%d\r\n", msg, file, line); - chThdSleepSeconds(1); +// chThdSleepSeconds(1); chSysHalt("Main loop did not start"); } } diff --git a/firmware/hw_layer/can_hw.cpp b/firmware/hw_layer/can_hw.cpp index b7f9607190..4bef1731d4 100644 --- a/firmware/hw_layer/can_hw.cpp +++ b/firmware/hw_layer/can_hw.cpp @@ -304,8 +304,8 @@ void initCan(void) { #else canStart(&CAND1, &canConfig); #endif - - canStart(&EFI_CAN_DEVICE, &canConfig); + // FIXME: Can't start a driver twice. + //canStart(&EFI_CAN_DEVICE, &canConfig); #if EFI_PROD_CODE || defined(__DOXYGEN__) chThdCreateStatic(canTreadStack, sizeof(canTreadStack), NORMALPRIO, (tfunc_t) canThread, NULL); diff --git a/firmware/hw_layer/serial_over_usb/usbcfg.c b/firmware/hw_layer/serial_over_usb/usbcfg.c index c712b0bce5..262f3f6f2b 100644 --- a/firmware/hw_layer/serial_over_usb/usbcfg.c +++ b/firmware/hw_layer/serial_over_usb/usbcfg.c @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -14,9 +14,10 @@ limitations under the License. */ -#include "main.h" +#include "hal.h" -#if HAL_USE_SERIAL_USB || defined(__DOXYGEN__) +/* Virtual serial port over USB.*/ +SerialUSBDriver SDU1; /* * Endpoints to be used for USBD1. @@ -287,6 +288,12 @@ static void usb_event(USBDriver *usbp, usbevent_t event) { case USB_EVENT_UNCONFIGURED: return; case USB_EVENT_SUSPEND: + chSysLockFromISR(); + + /* Disconnection event on suspend.*/ + sduDisconnectI(&SDU1); + + chSysUnlockFromISR(); return; case USB_EVENT_WAKEUP: return; @@ -296,6 +303,18 @@ static void usb_event(USBDriver *usbp, usbevent_t event) { return; } +/* + * Handles the USB driver global events. + */ +static void sof_handler(USBDriver *usbp) { + + (void)usbp; + + osalSysLockFromISR(); + sduSOFHookI(&SDU1); + osalSysUnlockFromISR(); +} + /* * USB driver configuration. */ @@ -303,7 +322,7 @@ const USBConfig usbcfg = { usb_event, get_descriptor, sduRequestsHook, - NULL + sof_handler }; /* @@ -315,7 +334,3 @@ const SerialUSBConfig serusbcfg = { USBD1_DATA_AVAILABLE_EP, USBD1_INTERRUPT_REQUEST_EP }; - -/* Virtual serial port over USB.*/ -SerialUSBDriver SDU1; -#endif diff --git a/firmware/hw_layer/stm32f4/mpu_util.cpp b/firmware/hw_layer/stm32f4/mpu_util.cpp index 41d492708c..5e6ab5bd1a 100644 --- a/firmware/hw_layer/stm32f4/mpu_util.cpp +++ b/firmware/hw_layer/stm32f4/mpu_util.cpp @@ -38,7 +38,7 @@ int getRemainingStack(thread_t *otp) { otp->activeStack = r13; int remainingStack; - if (dbg_isr_cnt > 0) { + if (ch.dbg.isr_cnt > 0) { // ISR context remainingStack = (int)(r13 - 1) - (int)&__main_stack_base__; } else { diff --git a/firmware/hw_layer/trigger_input.cpp b/firmware/hw_layer/trigger_input.cpp index 47b53b49d8..b9c5842eac 100644 --- a/firmware/hw_layer/trigger_input.cpp +++ b/firmware/hw_layer/trigger_input.cpp @@ -111,7 +111,7 @@ static ICUDriver *turnOnTriggerInputPin(const char *msg, brain_pin_e hwPin, ICUC efiIcuStart(driver, icucfg); if (driver->state == ICU_READY) { - icuEnableNotifications(driver); + icuStartCapture(driver); } else { // we would be here for example if same pin is used for multiple input capture purposes firmwareError(CUSTOM_ERR_ICU_STATE, "ICU unexpected state [%s]", hwPortname(hwPin)); @@ -123,7 +123,7 @@ static ICUDriver *turnOnTriggerInputPin(const char *msg, brain_pin_e hwPin, ICUC static void turnOffTriggerInputPin(brain_pin_e hwPin) { ICUDriver *driver = getInputCaptureDriver("trigger_off", hwPin); if (driver != NULL) { - icuDisableNotificationsI(driver); + icuStopCapture(driver); icuStop(driver); scheduleMsg(logger, "turnOffTriggerInputPin %s", hwPortname(hwPin)); unmarkPin(hwPin); diff --git a/firmware/util/rfiutil.h b/firmware/util/rfiutil.h index 4b8eaf98ea..f9770f792d 100644 --- a/firmware/util/rfiutil.h +++ b/firmware/util/rfiutil.h @@ -15,16 +15,14 @@ #include "histogram.h" -extern cnt_t dbg_lock_cnt; -extern cnt_t dbg_isr_cnt; -#define isLocked() (dbg_lock_cnt > 0) +#define isLocked() (ch.dbg.lock_cnt > 0) /** * Unfortunately ChibiOS has two versions of methods for different * contexts. */ -#define isIsrContext() (dbg_isr_cnt > 0) +#define isIsrContext() (ch.dbg.isr_cnt > 0) #ifdef __cplusplus extern "C" From f5d2eab8b5189b45c5e66ef945617366856580f3 Mon Sep 17 00:00:00 2001 From: Fabien Poussin Date: Thu, 23 Mar 2017 00:46:05 +0100 Subject: [PATCH 08/74] Fixed ICU. --- firmware/hw_layer/microsecond_timer.cpp | 2 +- firmware/hw_layer/trigger_input.cpp | 22 ++++++++++++++++++---- 2 files changed, 19 insertions(+), 5 deletions(-) diff --git a/firmware/hw_layer/microsecond_timer.cpp b/firmware/hw_layer/microsecond_timer.cpp index 5198d575a5..dc0c504507 100644 --- a/firmware/hw_layer/microsecond_timer.cpp +++ b/firmware/hw_layer/microsecond_timer.cpp @@ -127,7 +127,7 @@ static msg_t mwThread(int param) { static const GPTConfig gpt5cfg = { 1000000, /* 1 MHz timer clock.*/ callback, /* Timer callback.*/ -0 }; +0, 0 }; void initMicrosecondTimer(void) { diff --git a/firmware/hw_layer/trigger_input.cpp b/firmware/hw_layer/trigger_input.cpp index b9c5842eac..a3c2d78150 100644 --- a/firmware/hw_layer/trigger_input.cpp +++ b/firmware/hw_layer/trigger_input.cpp @@ -31,11 +31,13 @@ int vvtEventRiseCounter = 0; int vvtEventFallCounter = 0; static void cam_icu_width_callback(ICUDriver *icup) { + (void)icup; vvtEventRiseCounter++; hwHandleVvtCamSignal(TV_RISE); } static void cam_icu_period_callback(ICUDriver *icup) { + (void)icup; vvtEventFallCounter++; hwHandleVvtCamSignal(TV_FALL); } @@ -80,14 +82,24 @@ static void shaft_icu_period_callback(ICUDriver *icup) { /** * the main purpose of this configuration structure is to specify the input interrupt callbacks */ -static ICUConfig shaft_icucfg = { ICU_INPUT_ACTIVE_LOW, 100000, /* 100kHz ICU clock frequency. */ -shaft_icu_width_callback, shaft_icu_period_callback }; +static ICUConfig shaft_icucfg = { ICU_INPUT_ACTIVE_LOW, + 100000, /* 100kHz ICU clock frequency. */ + shaft_icu_width_callback, + shaft_icu_period_callback, + NULL, + ICU_CHANNEL_1, + 0}; /** * this is about VTTi and stuff kind of cam sensor */ -static ICUConfig cam_icucfg = { ICU_INPUT_ACTIVE_LOW, 100000, /* 100kHz ICU clock frequency. */ -cam_icu_width_callback, cam_icu_period_callback }; +static ICUConfig cam_icucfg = { ICU_INPUT_ACTIVE_LOW, + 100000, /* 100kHz ICU clock frequency. */ + cam_icu_width_callback, + cam_icu_period_callback, + NULL, + ICU_CHANNEL_1, + 0}; static ICUDriver *turnOnTriggerInputPin(const char *msg, brain_pin_e hwPin, ICUConfig *icucfg) { @@ -112,6 +124,7 @@ static ICUDriver *turnOnTriggerInputPin(const char *msg, brain_pin_e hwPin, ICUC efiIcuStart(driver, icucfg); if (driver->state == ICU_READY) { icuStartCapture(driver); + icuEnableNotifications(driver); } else { // we would be here for example if same pin is used for multiple input capture purposes firmwareError(CUSTOM_ERR_ICU_STATE, "ICU unexpected state [%s]", hwPortname(hwPin)); @@ -123,6 +136,7 @@ static ICUDriver *turnOnTriggerInputPin(const char *msg, brain_pin_e hwPin, ICUC static void turnOffTriggerInputPin(brain_pin_e hwPin) { ICUDriver *driver = getInputCaptureDriver("trigger_off", hwPin); if (driver != NULL) { + icuDisableNotifications(driver); icuStopCapture(driver); icuStop(driver); scheduleMsg(logger, "turnOffTriggerInputPin %s", hwPortname(hwPin)); From 63e4a3dea1fd9efde2015e277e99cb2824b4f943 Mon Sep 17 00:00:00 2001 From: Fabien Poussin Date: Fri, 24 Mar 2017 01:59:14 +0100 Subject: [PATCH 09/74] Fixed simulator. Needs testing. --- .gitignore | 3 +- firmware/console/eficonsole.cpp | 4 +- firmware/util/rfiutil.h | 15 +- win32_functional_tests/Makefile | 196 +++++------ win32_functional_tests/chconf.h | 309 ++++++++---------- win32_functional_tests/halconf.h | 57 +++- win32_functional_tests/main.c | 13 +- win32_functional_tests/rules.mk | 152 +++++---- .../simulator/framework.cpp | 6 +- win32_functional_tests/simulator/global.h | 15 +- 10 files changed, 369 insertions(+), 401 deletions(-) diff --git a/.gitignore b/.gitignore index e16d067fd0..5c807052b5 100644 --- a/.gitignore +++ b/.gitignore @@ -1,7 +1,8 @@ .svn* .dep* *.o.d +*.o build/ Debug_EMS/ Release_EMS/ -Debug/ \ No newline at end of file +Debug/ diff --git a/firmware/console/eficonsole.cpp b/firmware/console/eficonsole.cpp index a7bf1a4c0b..17922b9324 100644 --- a/firmware/console/eficonsole.cpp +++ b/firmware/console/eficonsole.cpp @@ -121,8 +121,8 @@ static void sayHello(void) { */ static void cmd_threads(void) { #if CH_DBG_THREADS_PROFILING || defined(__DOXYGEN__) - static const char *states[] = { THD_STATE_NAMES }; - Thread *tp; + static const char *states[] = { CH_STATE_NAMES }; + thread_t *tp; scheduleMsg(&logger, " addr stack prio refs state time"); tp = chRegFirstThread(); diff --git a/firmware/util/rfiutil.h b/firmware/util/rfiutil.h index f9770f792d..b0a79076c9 100644 --- a/firmware/util/rfiutil.h +++ b/firmware/util/rfiutil.h @@ -15,14 +15,17 @@ #include "histogram.h" +/** + * Unfortunately ChibiOS has two versions of methods for different + * contexts. + */ +#ifndef SIMULATOR #define isLocked() (ch.dbg.lock_cnt > 0) - - /** - * Unfortunately ChibiOS has two versions of methods for different - * contexts. - */ - #define isIsrContext() (ch.dbg.isr_cnt > 0) +#else +#define isLocked() (0) +#define isIsrContext() (0) +#endif #ifdef __cplusplus extern "C" diff --git a/win32_functional_tests/Makefile b/win32_functional_tests/Makefile index a7e566fed0..7786105a2d 100644 --- a/win32_functional_tests/Makefile +++ b/win32_functional_tests/Makefile @@ -3,60 +3,47 @@ # NOTE: Can be overridden externally. # -PROJECT_DIR = ../firmware -#CHIBIOS = $(PROJECT_DIR)/chibios - # Compiler options here. ifeq ($(USE_OPT),) # this config if debugging is needed, but the binary is about 50M # USE_OPT = -c -Wall -O0 -ggdb -g3 -Werror-implicit-function-declaration -Werror -Wno-error=pointer-sign -Wno-error=unused-function -Wno-error=unused-variable -Wno-error=sign-compare -Wno-error=unused-parameter -Wno-error=missing-field-initializers -Wno-error=write-strings # this config producec a smaller binary file - USE_OPT = -c -Wall -O2 -Werror-implicit-function-declaration -Wno-error=pointer-sign -Wno-error=unused-function -Wno-error=unused-variable -Wno-error=sign-compare -Wno-error=unused-parameter -Wno-error=missing-field-initializers -Wno-error=write-strings -Wno-error=strict-aliasing - - ifeq ($(OS),Windows_NT) - else - USE_OPT += -m32 - endif +USE_OPT = -Os +endif +ifeq ($(OS),Windows_NT) +else +USE_OPT += -m32 endif # C specific options here (added to USE_OPT). ifeq ($(USE_COPT),) - USE_COPT = -std=gnu99 -fgnu89-inline - - ifeq ($(OS),Windows_NT) - else - USE_COPT += -Wno-error=attributes -Wno-error=implicit-function-declaration -include stdio.h - endif +USE_COPT = -std=gnu99 -fgnu89-inline +endif +ifeq ($(OS),Windows_NT) +else +USE_COPT += -Wno-error=attributes -Wno-error=implicit-function-declaration -include stdio.h endif # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -std=c++11 -fno-rtti -fpermissive -fno-exceptions -fno-use-cxa-atexit - - - ifeq ($(OS),Windows_NT) - else - USE_CPPOPT += -include cstring -include cstdio -include cstdlib - endif - +USE_CPPOPT = -std=c++11 -fno-rtti -fpermissive -fno-exceptions -fno-use-cxa-atexit endif +ifeq ($(OS),Windows_NT) +else +USE_CPPOPT += -include cstring -include cstdio -include cstdlib +endif # Enable this if you want the linker to remove unused code and data ifeq ($(USE_LINK_GC),) USE_LINK_GC = yes endif -# If enabled, this option allows to compile the application in THUMB mode. -ifeq ($(USE_THUMB),) - USE_THUMB = no -endif - # Enable this if you want to see the full log while compiling. ifeq ($(USE_VERBOSE_COMPILE),) - USE_VERBOSE_COMPILE = no + USE_VERBOSE_COMPILE = yes endif # @@ -78,18 +65,24 @@ DDEFS = ############################################################################## # Project, sources and paths # - - # Define project name here +# Define project name here PROJECT = rusefi_simulator +PROJECT_DIR = ../firmware +CHIBIOS = ../firmware/ChibiOS -#PROJECT_BOARD = OLIMEX_STM32_E407 -#ifneq ($(PROJECT_BOARD),OLIMEX_STM32_E407) -# PROJECT_BOARD = ST_STM32F4_DISCOVERY -#endif -#DDEFS += -D$(PROJECT_BOARD) - -CHIBIOS = ../firmware/chibios # Imported source files and paths +include $(CHIBIOS)/os/hal/boards/simulator/board.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/hal/osal/rt/osal.mk +include $(CHIBIOS)/os/rt/ports/SIMIA32/compilers/GCC/port.mk +include $(CHIBIOS)/os/rt/rt.mk + +ifeq ($(OS),Windows_NT) + include ${CHIBIOS}/os/hal/ports/simulator/win32/platform.mk +else + include ${CHIBIOS}/os/hal/ports/simulator/Posix/platform.mk +endif + include $(PROJECT_DIR)/util/util.mk include $(PROJECT_DIR)/config/engines/engines.mk include $(PROJECT_DIR)/controllers/algo/algo.mk @@ -102,48 +95,36 @@ include $(PROJECT_DIR)/console/console.mk include $(PROJECT_DIR)/console/binary/tunerstudio.mk include $(PROJECT_DIR)/development/development.mk -include $(CHIBIOS)/boards/simulator/board.mk -include ${CHIBIOS}/os/hal/hal.mk - -ifeq ($(OS),Windows_NT) - include ${CHIBIOS}/os/hal/platforms/Win32/platform.mk -else - include ${CHIBIOS}/os/hal/platforms/Posix/platform.mk -endif - -include ${CHIBIOS}/os/ports/GCC/SIMIA32/port.mk -include ${CHIBIOS}/os/kernel/kernel.mk - # Define linker script file here #LDSCRIPT= config/system/STM32F407xG.ld #LDSCRIPT= $(PORTLD)/STM32F407xG_CCM.ld # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. -CSRC = ${PORTSRC} \ - ${KERNSRC} \ - ${TESTSRC} \ - ${HALSRC} \ - ${PLATFORMSRC} \ - $(SYSTEMSRC) \ - $(CONSOLESRC) \ - $(CONTROLLERS_ALGO_SRC) \ - $(CONTROLLERS_CORE_SRC) \ - $(CONTROLLERS_SENSORS_SRC) \ - $(ENGINES_SRC) \ - $(BOARDSRC) \ - ${CHIBIOS}/os/various/chprintf.c \ - ${CHIBIOS}/os/various/memstreams.c \ - $(UTILSRC) \ - main.c +CSRC = ${PORTSRC} \ + ${KERNSRC} \ + ${HALSRC} \ + ${PLATFORMSRC} \ + $(SYSTEMSRC) \ + $(CONSOLESRC) \ + $(CONTROLLERS_ALGO_SRC) \ + $(CONTROLLERS_CORE_SRC) \ + $(CONTROLLERS_SENSORS_SRC) \ + $(ENGINES_SRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/hal/lib/streams/memstreams.c \ + $(CHIBIOS)/os/hal/lib/streams/chprintf.c \ + $(CHIBIOS)/os/various/shell.c \ + $(UTILSRC) \ + main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global # setting. CPPSRC = $(UTILSRC_CPP) \ $(CONTROLLERS_ALGO_SRC_CPP) \ $(PROJECT_DIR)/controllers/settings.cpp \ - $(PROJECT_DIR)/controllers/engine_controller.cpp \ - $(PROJECT_DIR)/controllers/error_handling.cpp \ + $(PROJECT_DIR)/controllers/engine_controller.cpp \ + $(PROJECT_DIR)/controllers/error_handling.cpp \ $(PROJECT_DIR)/development/sensor_chart.cpp \ $(TRIGGER_SRC_CPP) \ $(TRIGGER_DECODERS_SRC_CPP) \ @@ -155,57 +136,43 @@ CPPSRC = $(UTILSRC_CPP) \ $(CONTROLLERS_MATH_SRC_CPP) \ $(DEV_SIMULATOR_SRC_CPP) \ $(ENGINES_SRC_CPP) \ - $(PROJECT_DIR)/simulator/rusEfiFunctionalTest.cpp \ - $(PROJECT_DIR)/simulator/framework.cpp \ + simulator/rusEfiFunctionalTest.cpp \ + simulator/framework.cpp \ + simulator/boards.cpp \ $(PROJECT_DIR)/controllers/map_averaging.cpp \ $(PROJECT_DIR)/development/trigger_emulator.cpp \ - simulator/boards.cpp \ $(TEST_SRC_CPP) -# C sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACSRC = -# C++ sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACPPSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) INCDIR = . \ -$(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(PLATFORMINC) $(BOARDINC) \ - $(PROJECT_DIR)/util \ - $(PROJECT_DIR)/console \ - $(PROJECT_DIR)/console/binary \ - $(PROJECT_DIR)/console/fl_binary \ - $(PROJECT_DIR)/config/engines \ - $(PROJECT_DIR)/ext_algo \ - $(PROJECT_DIR)/controllers \ - $(PROJECT_DIR)/hw_layer/algo \ - $(PROJECT_DIR)/development \ - $(PROJECT_DIR)/controllers/algo \ - $(PROJECT_DIR)/controllers/core \ - $(PROJECT_DIR)/controllers/math \ - $(PROJECT_DIR)/controllers/sensors \ - $(PROJECT_DIR)/controllers/system \ - $(PROJECT_DIR)/controllers/trigger \ - $(PROJECT_DIR)/controllers/trigger/decoders \ - ${CHIBIOS}/os/various \ - simulator - + $(PORTINC) \ + $(KERNINC) \ + $(OSALINC) \ + $(HALINC) \ + $(PLATFORMINC) \ + $(BOARDINC) \ + $(PROJECT_DIR)/util \ + $(PROJECT_DIR)/console \ + $(PROJECT_DIR)/console/binary \ + $(PROJECT_DIR)/console/fl_binary \ + $(PROJECT_DIR)/config/engines \ + $(PROJECT_DIR)/ext_algo \ + $(PROJECT_DIR)/controllers \ + $(PROJECT_DIR)/hw_layer/algo \ + $(PROJECT_DIR)/development \ + $(PROJECT_DIR)/controllers/algo \ + $(PROJECT_DIR)/controllers/core \ + $(PROJECT_DIR)/controllers/math \ + $(PROJECT_DIR)/controllers/sensors \ + $(PROJECT_DIR)/controllers/system \ + $(PROJECT_DIR)/controllers/trigger \ + $(PROJECT_DIR)/controllers/trigger/decoders \ + ${CHIBIOS}/os/various \ + $(CHIBIOS)/os/hal/lib/streams \ + simulator # # Project, sources and paths @@ -221,6 +188,7 @@ $(PORTINC) $(KERNINC) $(TESTINC) \ ifeq ($(OS),Windows_NT) #Cygwin64 is used with mingw64 32-bit version + #TRGT = i686-w64-mingw32- TRGT = i686-w64-mingw32- else TRGT = @@ -239,12 +207,6 @@ OD = $(TRGT)objdump HEX = $(CP) -O ihex BIN = $(CP) -O binary -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -DTHUMB - # Define C warning options here CWARN = -Wall -Wextra -Wstrict-prototypes @@ -285,7 +247,7 @@ endif # # List all user C define here, like -D_DEBUG=1 -UDEFS = +UDEFS = -DSIMULATOR # Define ASM defines here UADEFS = diff --git a/win32_functional_tests/chconf.h b/win32_functional_tests/chconf.h index be1cee9d80..2f29bf9e75 100644 --- a/win32_functional_tests/chconf.h +++ b/win32_functional_tests/chconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -28,11 +28,37 @@ #ifndef _CHCONF_H_ #define _CHCONF_H_ -#define CHPRINTF_USE_FLOAT TRUE +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ - #define ON_LOCK_HOOK - #define ON_UNLOCK_HOOK +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 100000 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 0 + +/** @} */ /*===========================================================================*/ /** @@ -41,15 +67,6 @@ */ /*===========================================================================*/ -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) -#define CH_FREQUENCY 100000 -#endif - /** * @brief Round robin interval. * @details This constant is the number of system ticks allowed for the @@ -57,13 +74,12 @@ * disables the preemption for threads with equal priority and the * round robin becomes cooperative. Note that higher priority * threads can still preempt, the kernel is always preemptive. - * * @note Disabling the round robin preemption makes the kernel more compact * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. */ -#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) -#define CH_TIME_QUANTUM 20 -#endif +#define CH_CFG_TIME_QUANTUM 20 /** * @brief Managed RAM size. @@ -74,28 +90,18 @@ * * @note In order to let the OS manage the whole RAM the linker script must * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_MEMCORE. + * @note Requires @p CH_CFG_USE_MEMCORE. */ -#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) -#define CH_MEMCORE_SIZE 0x20000 -#endif +#define CH_CFG_MEMCORE_SIZE 0x20000 /** * @brief Idle thread automatic spawn suppression. * @details When this option is activated the function @p chSysInit() - * does not spawn the idle thread automatically. The application has - * then the responsibility to do one of the following: - * - Spawn a custom idle thread at priority @p IDLEPRIO. - * - Change the main() thread priority to @p IDLEPRIO then enter - * an endless loop. In this scenario the @p main() thread acts as - * the idle thread. - * . - * @note Unless an idle thread is spawned the @p main() thread must not - * enter a sleep state. + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. */ -#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) -#define CH_NO_IDLE_THREAD FALSE -#endif +#define CH_CFG_NO_IDLE_THREAD FALSE /** @} */ @@ -114,9 +120,7 @@ * @note This is not related to the compiler optimization options. * @note The default is @p TRUE. */ -#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) -#define CH_OPTIMIZE_SPEED TRUE -#endif +#define CH_CFG_OPTIMIZE_SPEED TRUE /** @} */ @@ -127,15 +131,22 @@ */ /*===========================================================================*/ +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM FALSE + /** * @brief Threads registry APIs. * @details If enabled then the registry APIs are included in the kernel. * * @note The default is @p TRUE. */ -#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) -#define CH_USE_REGISTRY TRUE -#endif +#define CH_CFG_USE_REGISTRY TRUE /** * @brief Threads synchronization APIs. @@ -144,9 +155,7 @@ * * @note The default is @p TRUE. */ -#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) -#define CH_USE_WAITEXIT TRUE -#endif +#define CH_CFG_USE_WAITEXIT TRUE /** * @brief Semaphores APIs. @@ -154,33 +163,18 @@ * * @note The default is @p TRUE. */ -#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES TRUE -#endif +#define CH_CFG_USE_SEMAPHORES TRUE /** * @brief Semaphores queuing mode. * @details If enabled then the threads are enqueued on semaphores by * priority rather than in FIFO order. * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. */ -#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemSignalWait() API - * is included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) -#define CH_USE_SEMSW TRUE -#endif +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE /** * @brief Mutexes APIs. @@ -188,9 +182,17 @@ * * @note The default is @p TRUE. */ -#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) -#define CH_USE_MUTEXES TRUE -#endif +#define CH_CFG_USE_MUTEXES TRUE + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE /** * @brief Conditional Variables APIs. @@ -198,11 +200,9 @@ * in the kernel. * * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. + * @note Requires @p CH_CFG_USE_MUTEXES. */ -#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS TRUE -#endif +#define CH_CFG_USE_CONDVARS TRUE /** * @brief Conditional Variables APIs with timeout. @@ -210,11 +210,9 @@ * specification are included in the kernel. * * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. + * @note Requires @p CH_CFG_USE_CONDVARS. */ -#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS_TIMEOUT TRUE -#endif +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE /** * @brief Events Flags APIs. @@ -222,9 +220,7 @@ * * @note The default is @p TRUE. */ -#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) -#define CH_USE_EVENTS TRUE -#endif +#define CH_CFG_USE_EVENTS TRUE /** * @brief Events Flags APIs with timeout. @@ -232,11 +228,9 @@ * are included in the kernel. * * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. + * @note Requires @p CH_CFG_USE_EVENTS. */ -#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_EVENTS_TIMEOUT TRUE -#endif +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE /** * @brief Synchronous Messages APIs. @@ -245,21 +239,18 @@ * * @note The default is @p TRUE. */ -#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES TRUE -#endif +#define CH_CFG_USE_MESSAGES TRUE /** * @brief Synchronous Messages queuing mode. * @details If enabled then messages are served by priority rather than in * FIFO order. * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. */ -#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_PRIORITY FALSE -#endif +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE /** * @brief Mailboxes APIs. @@ -267,11 +258,9 @@ * included in the kernel. * * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note Requires @p CH_CFG_USE_SEMAPHORES. */ -#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXES TRUE -#endif +#define CH_CFG_USE_MAILBOXES TRUE /** * @brief I/O Queues APIs. @@ -279,9 +268,7 @@ * * @note The default is @p TRUE. */ -#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) -#define CH_USE_QUEUES TRUE -#endif +#define CH_CFG_USE_QUEUES TRUE /** * @brief Core Memory Manager APIs. @@ -290,9 +277,7 @@ * * @note The default is @p TRUE. */ -#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) -#define CH_USE_MEMCORE TRUE -#endif +#define CH_CFG_USE_MEMCORE TRUE /** * @brief Heap Allocator APIs. @@ -300,27 +285,11 @@ * in the kernel. * * @note The default is @p TRUE. - * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. * @note Mutexes are recommended. */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) -#define CH_USE_HEAP TRUE -#endif - -/** - * @brief C-runtime allocator. - * @details If enabled the the heap allocator APIs just wrap the C-runtime - * @p malloc() and @p free() functions. - * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the - * appropriate documentation. - */ -#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) -#define CH_USE_MALLOC_HEAP FALSE -#endif +#define CH_CFG_USE_HEAP TRUE /** * @brief Memory Pools Allocator APIs. @@ -329,9 +298,7 @@ * * @note The default is @p TRUE. */ -#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) -#define CH_USE_MEMPOOLS TRUE -#endif +#define CH_CFG_USE_MEMPOOLS TRUE /** * @brief Dynamic Threads APIs. @@ -339,12 +306,10 @@ * in the kernel. * * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. - * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. */ -#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) -#define CH_USE_DYNAMIC TRUE -#endif +#define CH_CFG_USE_DYNAMIC TRUE /** @} */ @@ -355,6 +320,13 @@ */ /*===========================================================================*/ +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + /** * @brief Debug option, system state check. * @details If enabled the correct call protocol for system APIs is checked @@ -362,9 +334,7 @@ * * @note The default is @p FALSE. */ -#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_SYSTEM_STATE_CHECK TRUE -#endif +#define CH_DBG_SYSTEM_STATE_CHECK FALSE /** * @brief Debug option, parameters checks. @@ -373,9 +343,7 @@ * * @note The default is @p FALSE. */ -#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS TRUE -#endif +#define CH_DBG_ENABLE_CHECKS FALSE /** * @brief Debug option, consistency checks. @@ -385,9 +353,7 @@ * * @note The default is @p FALSE. */ -#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS TRUE -#endif +#define CH_DBG_ENABLE_ASSERTS FALSE /** * @brief Debug option, trace buffer. @@ -396,9 +362,7 @@ * * @note The default is @p FALSE. */ -#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE FALSE -#endif +#define CH_DBG_ENABLE_TRACE FALSE /** * @brief Debug option, stack checks. @@ -410,9 +374,7 @@ * @note The default failure mode is to halt the system with the global * @p panic_msg variable set to @p NULL. */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK FALSE -#endif +#define CH_DBG_ENABLE_STACK_CHECK FALSE /** * @brief Debug option, stacks initialization. @@ -422,22 +384,18 @@ * * @note The default is @p FALSE. */ -#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS FALSE -#endif +#define CH_DBG_FILL_THREADS FALSE /** * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p Thread structure that + * @details If enabled then a field is added to the @p thread_t structure that * counts the system ticks occurred while executing the thread. * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. */ -#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING TRUE -#endif +#define CH_DBG_THREADS_PROFILING TRUE /** @} */ @@ -450,12 +408,10 @@ /** * @brief Threads descriptor structure extension. - * @details User fields added to the end of the @p Thread structure. + * @details User fields added to the end of the @p thread_t structure. */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ +#define CH_CFG_THREAD_EXTRA_FIELDS \ /* Add threads custom fields here.*/ -#endif /** * @brief Threads initialization hook. @@ -464,11 +420,9 @@ * @note It is invoked from within @p chThdInit() and implicitly from all * the threads creation APIs. */ -#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT_HOOK(tp) { \ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ /* Add threads initialization code here.*/ \ } -#endif /** * @brief Threads finalization hook. @@ -478,54 +432,61 @@ * @note It is also invoked when the threads simply return in order to * terminate. */ -#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT_HOOK(tp) { \ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ /* Add threads finalization code here.*/ \ } -#endif /** * @brief Context switch hook. * @details This hook is invoked just before switching between threads. */ -#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) -#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ - /* System halt code here.*/ \ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ } -#endif /** * @brief Idle Loop hook. * @details This hook is continuously invoked by the idle thread loop. */ -#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ +#define CH_CFG_IDLE_LOOP_HOOK() { \ /* Idle loop code here.*/ \ } -#endif /** * @brief System tick event hook. * @details This hook is invoked in the system tick handler immediately * after processing the virtual timers queue. */ -#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) -#define SYSTEM_TICK_EVENT_HOOK() { \ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ /* System tick event code here.*/ \ } -#endif - /** * @brief System halt hook. * @details This hook is invoked in case to a system halting error before * the system is halted. */ -#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) -#define SYSTEM_HALT_HOOK() { \ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ /* System halt code here.*/ \ } -#endif /** @} */ diff --git a/win32_functional_tests/halconf.h b/win32_functional_tests/halconf.h index 37c0489640..07718cf692 100644 --- a/win32_functional_tests/halconf.h +++ b/win32_functional_tests/halconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -58,6 +58,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + /** * @brief Enables the EXT subsystem. */ @@ -79,6 +86,13 @@ #define HAL_USE_I2C FALSE #endif +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + /** * @brief Enables the ICU subsystem. */ @@ -156,6 +170,13 @@ #define HAL_USE_USB FALSE #endif +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + /*===========================================================================*/ /* ADC driver related settings. */ /*===========================================================================*/ @@ -280,7 +301,7 @@ * @brief Serial buffers size. * @details Configuration parameter, you can change the depth of the queue * buffers depending on the requirements of your application. - * @note The default is 64 bytes for both the transmission and receive + * @note The default is 16 bytes for both the transmission and receive * buffers. */ #if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) @@ -307,6 +328,38 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/win32_functional_tests/main.c b/win32_functional_tests/main.c index 3b790a5fd3..61de2528c0 100644 --- a/win32_functional_tests/main.c +++ b/win32_functional_tests/main.c @@ -19,13 +19,13 @@ #include "rusEfiFunctionalTest.h" #include "framework.h" -#define CONSOLE_WA_SIZE THD_WA_SIZE(4096) +#define CONSOLE_WA_SIZE THD_WORKING_AREA_SIZE(4096) bool main_loop_started = false; static thread_t *cdtp; -//static Thread *shelltp1; -//static Thread *shelltp2; +//static thread_t *shelltp1; +//static thread_t *shelltp2; #define cputs(msg) chMsgSend(cdtp, (msg_t)msg) @@ -40,16 +40,15 @@ TestStream testStream; * to the C printf() thread safe and the print operation atomic among threads. * In this example the message is the zero terminated string itself. */ -static msg_t console_thread(void *arg) { +THD_FUNCTION(console_thread, arg) { (void) arg; - while (!chThdShouldTerminate()) { + while (!chThdShouldTerminateX()) { thread_t *tp = chMsgWait(); puts((char *) chMsgGet(tp)); fflush(stdout); chMsgRelease(tp, MSG_OK); } - return 0; } extern int isSerialOverTcpReady; @@ -172,7 +171,7 @@ int main(void) { /* * Events servicing loop. */ - while (!chThdShouldTerminate()) { + while (!chThdShouldTerminateX()) { chEvtDispatch(fhandlers, chEvtWaitOne(ALL_EVENTS)); printPendingMessages(); chThdSleepMilliseconds(100); diff --git a/win32_functional_tests/rules.mk b/win32_functional_tests/rules.mk index 5e93b3e311..b23473b182 100644 --- a/win32_functional_tests/rules.mk +++ b/win32_functional_tests/rules.mk @@ -1,72 +1,84 @@ # ARM Cortex-Mx common makefile scripts and rules. -# Output directory and files -ifeq ($(BUILDDIR),) - BUILDDIR = build -endif -ifeq ($(BUILDDIR),.) - BUILDDIR = build -endif -OUTFILES = $(BUILDDIR)/$(PROJECT) +############################################################################## +# Processing options coming from the upper Makefile. +# -# Automatic compiler options -OPT = $(USE_OPT) -COPT = $(USE_COPT) -CPPOPT = $(USE_CPPOPT) +# Compiler options +OPT := $(USE_OPT) +COPT := $(USE_COPT) +CPPOPT := $(USE_CPPOPT) + +# Garbage collection ifeq ($(USE_LINK_GC),yes) - OPT += -ffunction-sections -fdata-sections -fno-common + OPT += -ffunction-sections -fdata-sections -fno-common + LDOPT := ,--gc-sections +else + LDOPT := endif -# Source files groups and paths -ifeq ($(USE_THUMB),yes) - TCSRC += $(CSRC) - TCPPSRC += $(CPPSRC) -else - ACSRC += $(CSRC) - ACPPSRC += $(CPPSRC) +# Linker extra options +ifneq ($(USE_LDOPT),) + LDOPT := $(LDOPT),$(USE_LDOPT) endif -ASRC = $(ACSRC)$(ACPPSRC) -TSRC = $(TCSRC)$(TCPPSRC) -SRCPATHS = $(sort $(dir $(ASMXSRC)) $(dir $(ASMSRC)) $(dir $(ASRC)) $(dir $(TSRC))) + +# Link time optimizations +ifeq ($(USE_LTO),yes) + OPT += -flto +endif + +# Process stack size +ifeq ($(USE_PROCESS_STACKSIZE),) + LDOPT := $(LDOPT),--defsym=__process_stack_size__=0x400 +else + LDOPT := $(LDOPT),--defsym=__process_stack_size__=$(USE_PROCESS_STACKSIZE) +endif + +# Exceptions stack size +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + LDOPT := $(LDOPT),--defsym=__main_stack_size__=0x400 +else + LDOPT := $(LDOPT),--defsym=__main_stack_size__=$(USE_EXCEPTIONS_STACKSIZE) +endif + +BUILDDIR = build +OUTFILES := $(BUILDDIR)/$(PROJECT).exe +SRCPATHS := $(sort $(dir $(ASMXSRC)) $(dir $(ASMSRC)) $(dir $(CSRC)) $(dir $(CPPSRC))) # Various directories -OBJDIR = $(BUILDDIR)/obj -LSTDIR = $(BUILDDIR)/lst +OBJDIR := $(BUILDDIR)/obj +LSTDIR := $(BUILDDIR)/lst # Object files groups -ACOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ACSRC:.c=.o))) -ACPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ACPPSRC:.cpp=.o))) -TCOBJS = $(addprefix $(OBJDIR)/, $(notdir $(TCSRC:.c=.o))) -TCPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(TCPPSRC:.cpp=.o))) -ASMOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMSRC:.s=.o))) -ASMXOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMXSRC:.S=.o))) -OBJS = $(ASMXOBJS) $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS) +COBJS := $(addprefix $(OBJDIR)/, $(notdir $(CSRC:.c=.o))) +CPPOBJS := $(addprefix $(OBJDIR)/, $(notdir $(CPPSRC:.cpp=.o))) +ASMOBJS := $(addprefix $(OBJDIR)/, $(notdir $(ASMSRC:.s=.o))) +ASMXOBJS := $(addprefix $(OBJDIR)/, $(notdir $(ASMXSRC:.S=.o))) +OBJS := $(ASMXOBJS) $(ASMOBJS) $(COBJS) $(CPPOBJS) # Paths -IINCDIR = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR)) -LLIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) +IINCDIR := $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR)) +LLIBDIR := $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) # Macros -DEFS = $(DDEFS) $(UDEFS) -ADEFS = $(DADEFS) $(UADEFS) +DEFS := $(DDEFS) $(UDEFS) +ADEFS := $(DADEFS) $(UADEFS) # Libs -LIBS = $(DLIBS) $(ULIBS) +LIBS := $(DLIBS) $(ULIBS) # Various settings -#MCFLAGS = -mcpu=$(MCU) +MCFLAGS = ODFLAGS = -x --syms ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS) ASXFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS) CFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS) CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS) -ifeq ($(USE_LINK_GC),yes) - LDFLAGS = $(MCFLAGS) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LLIBDIR) -else - LDFLAGS = $(MCFLAGS) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch $(LLIBDIR) -endif +LDFLAGS = $(MCFLAGS) $(OPT) $(LLIBDIR) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--library-path=$(RULESPATH),$(LDOPT) # Generate dependency information +ASFLAGS += -MD -MP -MF .dep/$(@F).d +ASXFLAGS += -MD -MP -MF .dep/$(@F).d CFLAGS += -MD -MP -MF .dep/$(@F).d CPPFLAGS += -MD -MP -MF .dep/$(@F).d @@ -77,55 +89,40 @@ VPATH = $(SRCPATHS) # Makefile rules # -all: $(OBJS) $(OUTFILES) MAKE_ALL_RULE_HOOK +all: $(OBJS) $(OUTFILES) -MAKE_ALL_RULE_HOOK: +$(OBJS): $(BUILDDIR) $(OBJDIR) $(LSTDIR) -$(OBJS): | $(BUILDDIR) - -$(BUILDDIR) $(OBJDIR) $(LSTDIR): +$(BUILDDIR): ifneq ($(USE_VERBOSE_COMPILE),yes) @echo Compiler Options - @echo $(CPPC) -c $(CPPFLAGS) -I. $(IINCDIR) main.cpp -o main.o + @echo $(CC) -c $(CFLAGS) -I. $(IINCDIR) main.c -o main.o @echo endif - mkdir -p $(OBJDIR) - mkdir -p $(LSTDIR) + @mkdir -p $(BUILDDIR) -$(ACPPOBJS) : $(OBJDIR)/%.o : %.cpp Makefile +$(OBJDIR): + @mkdir -p $(OBJDIR) + +$(LSTDIR): + @mkdir -p $(LSTDIR) + +$(CPPOBJS) : $(OBJDIR)/%.o : %.cpp Makefile ifeq ($(USE_VERBOSE_COMPILE),yes) @echo - $(CPPC) -c $(CPPFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@ + $(CPPC) -c $(CPPFLAGS) $(OPT) -I. $(IINCDIR) $< -o $@ else @echo Compiling $( Migration -typedef VirtualTimer virtual_timer_t; -typedef EventListener event_listener_t; -typedef Thread thread_t; -#define THD_WORKING_AREA WORKING_AREA -#define THD_FUNCTION(tname, arg) void tname(void *arg) -#define MSG_OK RDY_OK -#define eventflags_t flagsmask_t -#define chSysLockFromISR chSysLockFromIsr -#define chSysUnlockFromISR chSysUnlockFromIsr -#define chThdGetSelfX chThdSelf +#define EFI_UNIT_TEST FALSE +#define hasFatalError() (FALSE) #define US_TO_NT_MULTIPLIER 100 -#define ALWAYS_INLINE INLINE +#define ALWAYS_INLINE #define US2NT(x) (US_TO_NT_MULTIPLIER * (x)) From 0babb9d5b842e2532c11a5d56404d1117bd0b337 Mon Sep 17 00:00:00 2001 From: Fabien Poussin Date: Fri, 24 Mar 2017 13:55:32 +0100 Subject: [PATCH 10/74] Fixed FatFS library compilation. --- firmware/Makefile | 2 +- firmware/ext/fatfs.mk | 7 +++++++ 2 files changed, 8 insertions(+), 1 deletion(-) create mode 100644 firmware/ext/fatfs.mk diff --git a/firmware/Makefile b/firmware/Makefile index a7b3d1f320..4eb63f0c7c 100644 --- a/firmware/Makefile +++ b/firmware/Makefile @@ -109,7 +109,7 @@ include $(CHIBIOS)/os/various/fatfs_bindings/fatfs.mk include $(CHIBIOS)/os/various/cpp_wrappers/chcpp.mk include console/binary/tunerstudio.mk -include ext/ext.mk +include $(PROJECT_DIR)/ext/fatfs.mk include $(PROJECT_DIR)/hw_layer/hw_layer.mk include $(PROJECT_DIR)/hw_layer/sensors/sensors.mk diff --git a/firmware/ext/fatfs.mk b/firmware/ext/fatfs.mk new file mode 100644 index 0000000000..c7f4fc2c58 --- /dev/null +++ b/firmware/ext/fatfs.mk @@ -0,0 +1,7 @@ +# FATFS files. +FATFSSRC = ${CHIBIOS}/os/various/fatfs_bindings/fatfs_diskio.c \ + ${CHIBIOS}/os/various/fatfs_bindings/fatfs_syscall.c \ + ${PROJECT_DIR}/ext/ff.c \ + ${PROJECT_DIR}/ext/option/unicode.c + +FATFSINC = ${PROJECT_DIR}/ext From c49b5392dda2b94cbcc0884910bea26a948250c5 Mon Sep 17 00:00:00 2001 From: Fabien Poussin Date: Sun, 26 Mar 2017 14:25:23 +0200 Subject: [PATCH 11/74] Removing empty linker flag --- win32_functional_tests/rules.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/win32_functional_tests/rules.mk b/win32_functional_tests/rules.mk index b23473b182..0e7132a118 100644 --- a/win32_functional_tests/rules.mk +++ b/win32_functional_tests/rules.mk @@ -74,7 +74,7 @@ ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS) ASXFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS) CFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS) CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS) -LDFLAGS = $(MCFLAGS) $(OPT) $(LLIBDIR) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--library-path=$(RULESPATH),$(LDOPT) +LDFLAGS = $(MCFLAGS) $(OPT) $(LLIBDIR) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,$(LDOPT) # Generate dependency information ASFLAGS += -MD -MP -MF .dep/$(@F).d From 77d7221843bc580255155635c2b0bfe8ba7a2d89 Mon Sep 17 00:00:00 2001 From: Fabien Poussin Date: Tue, 28 Mar 2017 00:04:53 +0200 Subject: [PATCH 12/74] Missing CHPRINTF_USE_FLOAT in simulator's chconf.h --- win32_functional_tests/chconf.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/win32_functional_tests/chconf.h b/win32_functional_tests/chconf.h index 2f29bf9e75..76ab9217a0 100644 --- a/win32_functional_tests/chconf.h +++ b/win32_functional_tests/chconf.h @@ -28,6 +28,8 @@ #ifndef _CHCONF_H_ #define _CHCONF_H_ +#define CHPRINTF_USE_FLOAT TRUE + /*===========================================================================*/ /** * @name System timers settings From 1fcafe9c5da4b5a8fb64370921104ca93ed1ab7c Mon Sep 17 00:00:00 2001 From: Fabien Poussin Date: Wed, 29 Mar 2017 17:00:36 +0200 Subject: [PATCH 13/74] Adding missing ff.c --- firmware/ext/ff.c | 4588 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 4588 insertions(+) create mode 100644 firmware/ext/ff.c diff --git a/firmware/ext/ff.c b/firmware/ext/ff.c new file mode 100644 index 0000000000..d7d690c70e --- /dev/null +++ b/firmware/ext/ff.c @@ -0,0 +1,4588 @@ +/*----------------------------------------------------------------------------/ +/ FatFs - FAT file system module R0.10b (C)ChaN, 2014 +/-----------------------------------------------------------------------------/ +/ FatFs module is a generic FAT file system module for small embedded systems. +/ This is a free software that opened for education, research and commercial +/ developments under license policy of following terms. +/ +/ Copyright (C) 2014, ChaN, all right reserved. +/ +/ * The FatFs module is a free software and there is NO WARRANTY. +/ * No restriction on use. You can use, modify and redistribute it for +/ personal, non-profit or commercial products UNDER YOUR RESPONSIBILITY. +/ * Redistributions of source code must retain the above copyright notice. +/ +/-----------------------------------------------------------------------------/ +/ Feb 26,'06 R0.00 Prototype. +/ +/ Apr 29,'06 R0.01 First stable version. +/ +/ Jun 01,'06 R0.02 Added FAT12 support. +/ Removed unbuffered mode. +/ Fixed a problem on small (<32M) partition. +/ Jun 10,'06 R0.02a Added a configuration option (_FS_MINIMUM). +/ +/ Sep 22,'06 R0.03 Added f_rename(). +/ Changed option _FS_MINIMUM to _FS_MINIMIZE. +/ Dec 11,'06 R0.03a Improved cluster scan algorithm to write files fast. +/ Fixed f_mkdir() creates incorrect directory on FAT32. +/ +/ Feb 04,'07 R0.04 Supported multiple drive system. +/ Changed some interfaces for multiple drive system. +/ Changed f_mountdrv() to f_mount(). +/ Added f_mkfs(). +/ Apr 01,'07 R0.04a Supported multiple partitions on a physical drive. +/ Added a capability of extending file size to f_lseek(). +/ Added minimization level 3. +/ Fixed an endian sensitive code in f_mkfs(). +/ May 05,'07 R0.04b Added a configuration option _USE_NTFLAG. +/ Added FSINFO support. +/ Fixed DBCS name can result FR_INVALID_NAME. +/ Fixed short seek (<= csize) collapses the file object. +/ +/ Aug 25,'07 R0.05 Changed arguments of f_read(), f_write() and f_mkfs(). +/ Fixed f_mkfs() on FAT32 creates incorrect FSINFO. +/ Fixed f_mkdir() on FAT32 creates incorrect directory. +/ Feb 03,'08 R0.05a Added f_truncate() and f_utime(). +/ Fixed off by one error at FAT sub-type determination. +/ Fixed btr in f_read() can be mistruncated. +/ Fixed cached sector is not flushed when create and close without write. +/ +/ Apr 01,'08 R0.06 Added fputc(), fputs(), fprintf() and fgets(). +/ Improved performance of f_lseek() on moving to the same or following cluster. +/ +/ Apr 01,'09 R0.07 Merged Tiny-FatFs as a configuration option. (_FS_TINY) +/ Added long file name feature. +/ Added multiple code page feature. +/ Added re-entrancy for multitask operation. +/ Added auto cluster size selection to f_mkfs(). +/ Added rewind option to f_readdir(). +/ Changed result code of critical errors. +/ Renamed string functions to avoid name collision. +/ Apr 14,'09 R0.07a Separated out OS dependent code on reentrant cfg. +/ Added multiple sector size feature. +/ Jun 21,'09 R0.07c Fixed f_unlink() can return FR_OK on error. +/ Fixed wrong cache control in f_lseek(). +/ Added relative path feature. +/ Added f_chdir() and f_chdrive(). +/ Added proper case conversion to extended character. +/ Nov 03,'09 R0.07e Separated out configuration options from ff.h to ffconf.h. +/ Fixed f_unlink() fails to remove a sub-directory on _FS_RPATH. +/ Fixed name matching error on the 13 character boundary. +/ Added a configuration option, _LFN_UNICODE. +/ Changed f_readdir() to return the SFN with always upper case on non-LFN cfg. +/ +/ May 15,'10 R0.08 Added a memory configuration option. (_USE_LFN = 3) +/ Added file lock feature. (_FS_SHARE) +/ Added fast seek feature. (_USE_FASTSEEK) +/ Changed some types on the API, XCHAR->TCHAR. +/ Changed .fname in the FILINFO structure on Unicode cfg. +/ String functions support UTF-8 encoding files on Unicode cfg. +/ Aug 16,'10 R0.08a Added f_getcwd(). +/ Added sector erase feature. (_USE_ERASE) +/ Moved file lock semaphore table from fs object to the bss. +/ Fixed a wrong directory entry is created on non-LFN cfg when the given name contains ';'. +/ Fixed f_mkfs() creates wrong FAT32 volume. +/ Jan 15,'11 R0.08b Fast seek feature is also applied to f_read() and f_write(). +/ f_lseek() reports required table size on creating CLMP. +/ Extended format syntax of f_printf(). +/ Ignores duplicated directory separators in given path name. +/ +/ Sep 06,'11 R0.09 f_mkfs() supports multiple partition to complete the multiple partition feature. +/ Added f_fdisk(). +/ Aug 27,'12 R0.09a Changed f_open() and f_opendir() reject null object pointer to avoid crash. +/ Changed option name _FS_SHARE to _FS_LOCK. +/ Fixed assertion failure due to OS/2 EA on FAT12/16 volume. +/ Jan 24,'13 R0.09b Added f_setlabel() and f_getlabel(). +/ +/ Oct 02,'13 R0.10 Added selection of character encoding on the file. (_STRF_ENCODE) +/ Added f_closedir(). +/ Added forced full FAT scan for f_getfree(). (_FS_NOFSINFO) +/ Added forced mount feature with changes of f_mount(). +/ Improved behavior of volume auto detection. +/ Improved write throughput of f_puts() and f_printf(). +/ Changed argument of f_chdrive(), f_mkfs(), disk_read() and disk_write(). +/ Fixed f_write() can be truncated when the file size is close to 4GB. +/ Fixed f_open(), f_mkdir() and f_setlabel() can return incorrect error code. +/ Jan 15,'14 R0.10a Added arbitrary strings as drive number in the path name. (_STR_VOLUME_ID) +/ Added a configuration option of minimum sector size. (_MIN_SS) +/ 2nd argument of f_rename() can have a drive number and it will be ignored. +/ Fixed f_mount() with forced mount fails when drive number is >= 1. +/ Fixed f_close() invalidates the file object without volume lock. +/ Fixed f_closedir() returns but the volume lock is left acquired. +/ Fixed creation of an entry with LFN fails on too many SFN collisions. +/ May 19,'14 R0.10b Fixed a hard error in the disk I/O layer can collapse the directory entry. +/ Fixed LFN entry is not deleted on delete/rename an object with lossy converted SFN. +/---------------------------------------------------------------------------*/ + +#include "ff.h" /* Declarations of FatFs API */ +#include "diskio.h" /* Declarations of disk I/O functions */ + + + + +/*-------------------------------------------------------------------------- + + Module Private Definitions + +---------------------------------------------------------------------------*/ + +#if _FATFS != 8051 /* Revision ID */ +#error Wrong include file (ff.h). +#endif + + +/* Reentrancy related */ +#if _FS_REENTRANT +#if _USE_LFN == 1 +#error Static LFN work area cannot be used at thread-safe configuration. +#endif +#define ENTER_FF(fs) { if (!lock_fs(fs)) return FR_TIMEOUT; } +#define LEAVE_FF(fs, res) { unlock_fs(fs, res); return res; } +#else +#define ENTER_FF(fs) +#define LEAVE_FF(fs, res) return res +#endif + +#define ABORT(fs, res) { fp->err = (BYTE)(res); LEAVE_FF(fs, res); } + + +/* Definitions of sector size */ +#if (_MAX_SS < _MIN_SS) || (_MAX_SS != 512 && _MAX_SS != 1024 && _MAX_SS != 2048 && _MAX_SS != 4096) || (_MIN_SS != 512 && _MIN_SS != 1024 && _MIN_SS != 2048 && _MIN_SS != 4096) +#error Wrong sector size configuration. +#endif +#if _MAX_SS == _MIN_SS +#define SS(fs) ((UINT)_MAX_SS) /* Fixed sector size */ +#else +#define SS(fs) ((fs)->ssize) /* Variable sector size */ +#endif + + +/* File access control feature */ +#if _FS_LOCK +#if _FS_READONLY +#error _FS_LOCK must be 0 at read-only cfg. +#endif +typedef struct { + FATFS *fs; /* Object ID 1, volume (NULL:blank entry) */ + DWORD clu; /* Object ID 2, directory (0:root) */ + WORD idx; /* Object ID 3, directory index */ + WORD ctr; /* Object open counter, 0:none, 0x01..0xFF:read mode open count, 0x100:write mode */ +} FILESEM; +#endif + + + +/* DBCS code ranges and SBCS extend character conversion table */ + +#if _CODE_PAGE == 932 /* Japanese Shift-JIS */ +#define _DF1S 0x81 /* DBC 1st byte range 1 start */ +#define _DF1E 0x9F /* DBC 1st byte range 1 end */ +#define _DF2S 0xE0 /* DBC 1st byte range 2 start */ +#define _DF2E 0xFC /* DBC 1st byte range 2 end */ +#define _DS1S 0x40 /* DBC 2nd byte range 1 start */ +#define _DS1E 0x7E /* DBC 2nd byte range 1 end */ +#define _DS2S 0x80 /* DBC 2nd byte range 2 start */ +#define _DS2E 0xFC /* DBC 2nd byte range 2 end */ + +#elif _CODE_PAGE == 936 /* Simplified Chinese GBK */ +#define _DF1S 0x81 +#define _DF1E 0xFE +#define _DS1S 0x40 +#define _DS1E 0x7E +#define _DS2S 0x80 +#define _DS2E 0xFE + +#elif _CODE_PAGE == 949 /* Korean */ +#define _DF1S 0x81 +#define _DF1E 0xFE +#define _DS1S 0x41 +#define _DS1E 0x5A +#define _DS2S 0x61 +#define _DS2E 0x7A +#define _DS3S 0x81 +#define _DS3E 0xFE + +#elif _CODE_PAGE == 950 /* Traditional Chinese Big5 */ +#define _DF1S 0x81 +#define _DF1E 0xFE +#define _DS1S 0x40 +#define _DS1E 0x7E +#define _DS2S 0xA1 +#define _DS2E 0xFE + +#elif _CODE_PAGE == 437 /* U.S. (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F,0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 720 /* Arabic (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x45,0x41,0x84,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x49,0x49,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 737 /* Greek (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \ + 0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xE7,0xE8,0xF1,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 775 /* Baltic (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 850 /* Multilingual Latin 1 (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ + 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 852 /* Latin 2 (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F,0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0x9F, \ + 0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF} + +#elif _CODE_PAGE == 855 /* Cyrillic (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F,0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \ + 0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \ + 0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 857 /* Turkish (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x98,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \ + 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0x59,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 858 /* Multilingual Latin 1 + Euro (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ + 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 862 /* Hebrew (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 866 /* Russian (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0x90,0x91,0x92,0x93,0x9d,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F,0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 874 /* Thai (OEM, Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 1250 /* Central Europe (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xA3,0xB4,0xB5,0xB6,0xB7,0xB8,0xA5,0xAA,0xBB,0xBC,0xBD,0xBC,0xAF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF} + +#elif _CODE_PAGE == 1251 /* Cyrillic (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x82,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x80,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \ + 0xA0,0xA2,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB2,0xA5,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xA3,0xBD,0xBD,0xAF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF} + +#elif _CODE_PAGE == 1252 /* Latin 1 (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0xAd,0x9B,0x8C,0x9D,0xAE,0x9F, \ + 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F} + +#elif _CODE_PAGE == 1253 /* Greek (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xA2,0xB8,0xB9,0xBA, \ + 0xE0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xFB,0xBC,0xFD,0xBF,0xFF} + +#elif _CODE_PAGE == 1254 /* Turkish (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x9D,0x9E,0x9F, \ + 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F} + +#elif _CODE_PAGE == 1255 /* Hebrew (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 1256 /* Arabic (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x8C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0x41,0xE1,0x41,0xE3,0xE4,0xE5,0xE6,0x43,0x45,0x45,0x45,0x45,0xEC,0xED,0x49,0x49,0xF0,0xF1,0xF2,0xF3,0x4F,0xF5,0xF6,0xF7,0xF8,0x55,0xFA,0x55,0x55,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 1257 /* Baltic (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xBC,0xBD,0xBE,0xAF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF} + +#elif _CODE_PAGE == 1258 /* Vietnam (OEM, Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0xAC,0x9D,0x9E,0x9F, \ + 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xEC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xFE,0x9F} + +#elif _CODE_PAGE == 1 /* ASCII (for only non-LFN cfg) */ +#if _USE_LFN +#error Cannot use LFN feature without valid code page. +#endif +#define _DF1S 0 + +#else +#error Unknown code page + +#endif + + +/* Character code support macros */ +#define IsUpper(c) (((c)>='A')&&((c)<='Z')) +#define IsLower(c) (((c)>='a')&&((c)<='z')) +#define IsDigit(c) (((c)>='0')&&((c)<='9')) + +#if _DF1S /* Code page is DBCS */ + +#ifdef _DF2S /* Two 1st byte areas */ +#define IsDBCS1(c) (((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) || ((BYTE)(c) >= _DF2S && (BYTE)(c) <= _DF2E)) +#else /* One 1st byte area */ +#define IsDBCS1(c) ((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) +#endif + +#ifdef _DS3S /* Three 2nd byte areas */ +#define IsDBCS2(c) (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E) || ((BYTE)(c) >= _DS3S && (BYTE)(c) <= _DS3E)) +#else /* Two 2nd byte areas */ +#define IsDBCS2(c) (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E)) +#endif + +#else /* Code page is SBCS */ + +#define IsDBCS1(c) 0 +#define IsDBCS2(c) 0 + +#endif /* _DF1S */ + + +/* Name status flags */ +#define NS 11 /* Index of name status byte in fn[] */ +#define NS_LOSS 0x01 /* Out of 8.3 format */ +#define NS_LFN 0x02 /* Force to create LFN entry */ +#define NS_LAST 0x04 /* Last segment */ +#define NS_BODY 0x08 /* Lower case flag (body) */ +#define NS_EXT 0x10 /* Lower case flag (ext) */ +#define NS_DOT 0x20 /* Dot entry */ + + +/* FAT sub-type boundaries */ +#define MIN_FAT16 4086U /* Minimum number of clusters for FAT16 */ +#define MIN_FAT32 65526U /* Minimum number of clusters for FAT32 */ + + +/* FatFs refers the members in the FAT structures as byte array instead of +/ structure member because the structure is not binary compatible between +/ different platforms */ + +#define BS_jmpBoot 0 /* Jump instruction (3) */ +#define BS_OEMName 3 /* OEM name (8) */ +#define BPB_BytsPerSec 11 /* Sector size [byte] (2) */ +#define BPB_SecPerClus 13 /* Cluster size [sector] (1) */ +#define BPB_RsvdSecCnt 14 /* Size of reserved area [sector] (2) */ +#define BPB_NumFATs 16 /* Number of FAT copies (1) */ +#define BPB_RootEntCnt 17 /* Number of root directory entries for FAT12/16 (2) */ +#define BPB_TotSec16 19 /* Volume size [sector] (2) */ +#define BPB_Media 21 /* Media descriptor (1) */ +#define BPB_FATSz16 22 /* FAT size [sector] (2) */ +#define BPB_SecPerTrk 24 /* Track size [sector] (2) */ +#define BPB_NumHeads 26 /* Number of heads (2) */ +#define BPB_HiddSec 28 /* Number of special hidden sectors (4) */ +#define BPB_TotSec32 32 /* Volume size [sector] (4) */ +#define BS_DrvNum 36 /* Physical drive number (2) */ +#define BS_BootSig 38 /* Extended boot signature (1) */ +#define BS_VolID 39 /* Volume serial number (4) */ +#define BS_VolLab 43 /* Volume label (8) */ +#define BS_FilSysType 54 /* File system type (1) */ +#define BPB_FATSz32 36 /* FAT size [sector] (4) */ +#define BPB_ExtFlags 40 /* Extended flags (2) */ +#define BPB_FSVer 42 /* File system version (2) */ +#define BPB_RootClus 44 /* Root directory first cluster (4) */ +#define BPB_FSInfo 48 /* Offset of FSINFO sector (2) */ +#define BPB_BkBootSec 50 /* Offset of backup boot sector (2) */ +#define BS_DrvNum32 64 /* Physical drive number (2) */ +#define BS_BootSig32 66 /* Extended boot signature (1) */ +#define BS_VolID32 67 /* Volume serial number (4) */ +#define BS_VolLab32 71 /* Volume label (8) */ +#define BS_FilSysType32 82 /* File system type (1) */ +#define FSI_LeadSig 0 /* FSI: Leading signature (4) */ +#define FSI_StrucSig 484 /* FSI: Structure signature (4) */ +#define FSI_Free_Count 488 /* FSI: Number of free clusters (4) */ +#define FSI_Nxt_Free 492 /* FSI: Last allocated cluster (4) */ +#define MBR_Table 446 /* MBR: Partition table offset (2) */ +#define SZ_PTE 16 /* MBR: Size of a partition table entry */ +#define BS_55AA 510 /* Signature word (2) */ + +#define DIR_Name 0 /* Short file name (11) */ +#define DIR_Attr 11 /* Attribute (1) */ +#define DIR_NTres 12 /* NT flag (1) */ +#define DIR_CrtTimeTenth 13 /* Created time sub-second (1) */ +#define DIR_CrtTime 14 /* Created time (2) */ +#define DIR_CrtDate 16 /* Created date (2) */ +#define DIR_LstAccDate 18 /* Last accessed date (2) */ +#define DIR_FstClusHI 20 /* Higher 16-bit of first cluster (2) */ +#define DIR_WrtTime 22 /* Modified time (2) */ +#define DIR_WrtDate 24 /* Modified date (2) */ +#define DIR_FstClusLO 26 /* Lower 16-bit of first cluster (2) */ +#define DIR_FileSize 28 /* File size (4) */ +#define LDIR_Ord 0 /* LFN entry order and LLE flag (1) */ +#define LDIR_Attr 11 /* LFN attribute (1) */ +#define LDIR_Type 12 /* LFN type (1) */ +#define LDIR_Chksum 13 /* Sum of corresponding SFN entry */ +#define LDIR_FstClusLO 26 /* Filled by zero (0) */ +#define SZ_DIR 32 /* Size of a directory entry */ +#define LLE 0x40 /* Last long entry flag in LDIR_Ord */ +#define DDE 0xE5 /* Deleted directory entry mark in DIR_Name[0] */ +#define NDDE 0x05 /* Replacement of the character collides with DDE */ + + + + +/*------------------------------------------------------------*/ +/* Module private work area */ +/*------------------------------------------------------------*/ +/* Note that uninitialized variables with static duration are +/ guaranteed zero/null as initial value. If not, either the +/ linker or start-up routine is out of ANSI-C standard. +*/ + +#if _VOLUMES >= 1 || _VOLUMES <= 10 +static +FATFS *FatFs[_VOLUMES]; /* Pointer to the file system objects (logical drives) */ +#else +#error Number of volumes must be 1 to 10. +#endif + +static +WORD Fsid; /* File system mount ID */ + +#if _FS_RPATH && _VOLUMES >= 2 +static +BYTE CurrVol; /* Current drive */ +#endif + +#if _FS_LOCK +static +FILESEM Files[_FS_LOCK]; /* Open object lock semaphores */ +#endif + +#if _USE_LFN == 0 /* No LFN feature */ +#define DEF_NAMEBUF BYTE sfn[12] +#define INIT_BUF(dobj) (dobj).fn = sfn +#define FREE_BUF() + +#elif _USE_LFN == 1 /* LFN feature with static working buffer */ +static +WCHAR LfnBuf[_MAX_LFN+1]; +#define DEF_NAMEBUF BYTE sfn[12] +#define INIT_BUF(dobj) { (dobj).fn = sfn; (dobj).lfn = LfnBuf; } +#define FREE_BUF() + +#elif _USE_LFN == 2 /* LFN feature with dynamic working buffer on the stack */ +#define DEF_NAMEBUF BYTE sfn[12]; WCHAR lbuf[_MAX_LFN+1] +#define INIT_BUF(dobj) { (dobj).fn = sfn; (dobj).lfn = lbuf; } +#define FREE_BUF() + +#elif _USE_LFN == 3 /* LFN feature with dynamic working buffer on the heap */ +#define DEF_NAMEBUF BYTE sfn[12]; WCHAR *lfn +#define INIT_BUF(dobj) { lfn = ff_memalloc((_MAX_LFN + 1) * 2); \ + if (!lfn) LEAVE_FF((dobj).fs, FR_NOT_ENOUGH_CORE); \ + (dobj).lfn = lfn; (dobj).fn = sfn; } +#define FREE_BUF() ff_memfree(lfn) + +#else +#error Wrong LFN configuration. +#endif + + +#ifdef _EXCVT +static +const BYTE ExCvt[] = _EXCVT; /* Upper conversion table for extended characters */ +#endif + + + + + + +/*-------------------------------------------------------------------------- + + Module Private Functions + +---------------------------------------------------------------------------*/ + + +/*-----------------------------------------------------------------------*/ +/* String functions */ +/*-----------------------------------------------------------------------*/ + +/* Copy memory to memory */ +static +void mem_cpy (void* dst, const void* src, UINT cnt) { + BYTE *d = (BYTE*)dst; + const BYTE *s = (const BYTE*)src; + +#if _WORD_ACCESS == 1 + while (cnt >= sizeof (int)) { + *(int*)d = *(int*)s; + d += sizeof (int); s += sizeof (int); + cnt -= sizeof (int); + } +#endif + while (cnt--) + *d++ = *s++; +} + +/* Fill memory */ +static +void mem_set (void* dst, int val, UINT cnt) { + BYTE *d = (BYTE*)dst; + + while (cnt--) + *d++ = (BYTE)val; +} + +/* Compare memory to memory */ +static +int mem_cmp (const void* dst, const void* src, UINT cnt) { + const BYTE *d = (const BYTE *)dst, *s = (const BYTE *)src; + int r = 0; + + while (cnt-- && (r = *d++ - *s++) == 0) ; + return r; +} + +/* Check if chr is contained in the string */ +static +int chk_chr (const char* str, int chr) { + while (*str && *str != chr) str++; + return *str; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Request/Release grant to access the volume */ +/*-----------------------------------------------------------------------*/ +#if _FS_REENTRANT +static +int lock_fs ( + FATFS* fs /* File system object */ +) +{ + return ff_req_grant(fs->sobj); +} + + +static +void unlock_fs ( + FATFS* fs, /* File system object */ + FRESULT res /* Result code to be returned */ +) +{ + if (fs && + res != FR_NOT_ENABLED && + res != FR_INVALID_DRIVE && + res != FR_INVALID_OBJECT && + res != FR_TIMEOUT) { + ff_rel_grant(fs->sobj); + } +} +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* File lock control functions */ +/*-----------------------------------------------------------------------*/ +#if _FS_LOCK + +static +FRESULT chk_lock ( /* Check if the file can be accessed */ + DIR* dp, /* Directory object pointing the file to be checked */ + int acc /* Desired access type (0:Read, 1:Write, 2:Delete/Rename) */ +) +{ + UINT i, be; + + /* Search file semaphore table */ + for (i = be = 0; i < _FS_LOCK; i++) { + if (Files[i].fs) { /* Existing entry */ + if (Files[i].fs == dp->fs && /* Check if the object matched with an open object */ + Files[i].clu == dp->sclust && + Files[i].idx == dp->index) break; + } else { /* Blank entry */ + be = 1; + } + } + if (i == _FS_LOCK) /* The object is not opened */ + return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES; /* Is there a blank entry for new object? */ + + /* The object has been opened. Reject any open against writing file and all write mode open */ + return (acc || Files[i].ctr == 0x100) ? FR_LOCKED : FR_OK; +} + + +static +int enq_lock (void) /* Check if an entry is available for a new object */ +{ + UINT i; + + for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ; + return (i == _FS_LOCK) ? 0 : 1; +} + + +static +UINT inc_lock ( /* Increment object open counter and returns its index (0:Internal error) */ + DIR* dp, /* Directory object pointing the file to register or increment */ + int acc /* Desired access (0:Read, 1:Write, 2:Delete/Rename) */ +) +{ + UINT i; + + + for (i = 0; i < _FS_LOCK; i++) { /* Find the object */ + if (Files[i].fs == dp->fs && + Files[i].clu == dp->sclust && + Files[i].idx == dp->index) break; + } + + if (i == _FS_LOCK) { /* Not opened. Register it as new. */ + for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ; + if (i == _FS_LOCK) return 0; /* No free entry to register (int err) */ + Files[i].fs = dp->fs; + Files[i].clu = dp->sclust; + Files[i].idx = dp->index; + Files[i].ctr = 0; + } + + if (acc && Files[i].ctr) return 0; /* Access violation (int err) */ + + Files[i].ctr = acc ? 0x100 : Files[i].ctr + 1; /* Set semaphore value */ + + return i + 1; +} + + +static +FRESULT dec_lock ( /* Decrement object open counter */ + UINT i /* Semaphore index (1..) */ +) +{ + WORD n; + FRESULT res; + + + if (--i < _FS_LOCK) { /* Shift index number origin from 0 */ + n = Files[i].ctr; + if (n == 0x100) n = 0; /* If write mode open, delete the entry */ + if (n) n--; /* Decrement read mode open count */ + Files[i].ctr = n; + if (!n) Files[i].fs = 0; /* Delete the entry if open count gets zero */ + res = FR_OK; + } else { + res = FR_INT_ERR; /* Invalid index nunber */ + } + return res; +} + + +static +void clear_lock ( /* Clear lock entries of the volume */ + FATFS *fs +) +{ + UINT i; + + for (i = 0; i < _FS_LOCK; i++) { + if (Files[i].fs == fs) Files[i].fs = 0; + } +} +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* Move/Flush disk access window in the file system object */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY +static +FRESULT sync_window ( + FATFS* fs /* File system object */ +) +{ + DWORD wsect; + UINT nf; + + + if (fs->wflag) { /* Write back the sector if it is dirty */ + wsect = fs->winsect; /* Current sector number */ + if (disk_write(fs->drv, fs->win, wsect, 1)) + return FR_DISK_ERR; + fs->wflag = 0; + if (wsect - fs->fatbase < fs->fsize) { /* Is it in the FAT area? */ + for (nf = fs->n_fats; nf >= 2; nf--) { /* Reflect the change to all FAT copies */ + wsect += fs->fsize; + disk_write(fs->drv, fs->win, wsect, 1); + } + } + } + return FR_OK; +} +#endif + + +static +FRESULT move_window ( + FATFS* fs, /* File system object */ + DWORD sector /* Sector number to make appearance in the fs->win[] */ +) +{ + if (sector != fs->winsect) { /* Changed current window */ +#if !_FS_READONLY + if (sync_window(fs) != FR_OK) + return FR_DISK_ERR; +#endif + if (disk_read(fs->drv, fs->win, sector, 1)) + return FR_DISK_ERR; + fs->winsect = sector; + } + + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Synchronize file system and strage device */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY +static +FRESULT sync_fs ( /* FR_OK: successful, FR_DISK_ERR: failed */ + FATFS* fs /* File system object */ +) +{ + FRESULT res; + + + res = sync_window(fs); + if (res == FR_OK) { + /* Update FSINFO sector if needed */ + if (fs->fs_type == FS_FAT32 && fs->fsi_flag == 1) { + /* Create FSINFO structure */ + mem_set(fs->win, 0, SS(fs)); + ST_WORD(fs->win+BS_55AA, 0xAA55); + ST_DWORD(fs->win+FSI_LeadSig, 0x41615252); + ST_DWORD(fs->win+FSI_StrucSig, 0x61417272); + ST_DWORD(fs->win+FSI_Free_Count, fs->free_clust); + ST_DWORD(fs->win+FSI_Nxt_Free, fs->last_clust); + /* Write it into the FSINFO sector */ + fs->winsect = fs->volbase + 1; + disk_write(fs->drv, fs->win, fs->winsect, 1); + fs->fsi_flag = 0; + } + /* Make sure that no pending write process in the physical drive */ + if (disk_ioctl(fs->drv, CTRL_SYNC, 0) != RES_OK) + res = FR_DISK_ERR; + } + + return res; +} +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* Get sector# from cluster# */ +/*-----------------------------------------------------------------------*/ + + +DWORD clust2sect ( /* !=0: Sector number, 0: Failed - invalid cluster# */ + FATFS* fs, /* File system object */ + DWORD clst /* Cluster# to be converted */ +) +{ + clst -= 2; + if (clst >= (fs->n_fatent - 2)) return 0; /* Invalid cluster# */ + return clst * fs->csize + fs->database; +} + + + + +/*-----------------------------------------------------------------------*/ +/* FAT access - Read value of a FAT entry */ +/*-----------------------------------------------------------------------*/ + + +DWORD get_fat ( /* 0xFFFFFFFF:Disk error, 1:Internal error, Else:Cluster status */ + FATFS* fs, /* File system object */ + DWORD clst /* Cluster# to get the link information */ +) +{ + UINT wc, bc; + BYTE *p; + + + if (clst < 2 || clst >= fs->n_fatent) /* Check range */ + return 1; + + switch (fs->fs_type) { + case FS_FAT12 : + bc = (UINT)clst; bc += bc / 2; + if (move_window(fs, fs->fatbase + (bc / SS(fs)))) break; + wc = fs->win[bc % SS(fs)]; bc++; + if (move_window(fs, fs->fatbase + (bc / SS(fs)))) break; + wc |= fs->win[bc % SS(fs)] << 8; + return clst & 1 ? wc >> 4 : (wc & 0xFFF); + + case FS_FAT16 : + if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 2)))) break; + p = &fs->win[clst * 2 % SS(fs)]; + return LD_WORD(p); + + case FS_FAT32 : + if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4)))) break; + p = &fs->win[clst * 4 % SS(fs)]; + return LD_DWORD(p) & 0x0FFFFFFF; + + default: + return 1; + } + + return 0xFFFFFFFF; /* An error occurred at the disk I/O layer */ +} + + + + +/*-----------------------------------------------------------------------*/ +/* FAT access - Change value of a FAT entry */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY + +FRESULT put_fat ( + FATFS* fs, /* File system object */ + DWORD clst, /* Cluster# to be changed in range of 2 to fs->n_fatent - 1 */ + DWORD val /* New value to mark the cluster */ +) +{ + UINT bc; + BYTE *p; + FRESULT res; + + + if (clst < 2 || clst >= fs->n_fatent) { /* Check range */ + res = FR_INT_ERR; + + } else { + switch (fs->fs_type) { + case FS_FAT12 : + bc = (UINT)clst; bc += bc / 2; + res = move_window(fs, fs->fatbase + (bc / SS(fs))); + if (res != FR_OK) break; + p = &fs->win[bc % SS(fs)]; + *p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val; + bc++; + fs->wflag = 1; + res = move_window(fs, fs->fatbase + (bc / SS(fs))); + if (res != FR_OK) break; + p = &fs->win[bc % SS(fs)]; + *p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F)); + break; + + case FS_FAT16 : + res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))); + if (res != FR_OK) break; + p = &fs->win[clst * 2 % SS(fs)]; + ST_WORD(p, (WORD)val); + break; + + case FS_FAT32 : + res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))); + if (res != FR_OK) break; + p = &fs->win[clst * 4 % SS(fs)]; + val |= LD_DWORD(p) & 0xF0000000; + ST_DWORD(p, val); + break; + + default : + res = FR_INT_ERR; + } + fs->wflag = 1; + } + + return res; +} +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* FAT handling - Remove a cluster chain */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY +static +FRESULT remove_chain ( + FATFS* fs, /* File system object */ + DWORD clst /* Cluster# to remove a chain from */ +) +{ + FRESULT res; + DWORD nxt; +#if _USE_ERASE + DWORD scl = clst, ecl = clst, rt[2]; +#endif + + if (clst < 2 || clst >= fs->n_fatent) { /* Check range */ + res = FR_INT_ERR; + + } else { + res = FR_OK; + while (clst < fs->n_fatent) { /* Not a last link? */ + nxt = get_fat(fs, clst); /* Get cluster status */ + if (nxt == 0) break; /* Empty cluster? */ + if (nxt == 1) { res = FR_INT_ERR; break; } /* Internal error? */ + if (nxt == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } /* Disk error? */ + res = put_fat(fs, clst, 0); /* Mark the cluster "empty" */ + if (res != FR_OK) break; + if (fs->free_clust != 0xFFFFFFFF) { /* Update FSINFO */ + fs->free_clust++; + fs->fsi_flag |= 1; + } +#if _USE_ERASE + if (ecl + 1 == nxt) { /* Is next cluster contiguous? */ + ecl = nxt; + } else { /* End of contiguous clusters */ + rt[0] = clust2sect(fs, scl); /* Start sector */ + rt[1] = clust2sect(fs, ecl) + fs->csize - 1; /* End sector */ + disk_ioctl(fs->drv, CTRL_ERASE_SECTOR, rt); /* Erase the block */ + scl = ecl = nxt; + } +#endif + clst = nxt; /* Next cluster */ + } + } + + return res; +} +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* FAT handling - Stretch or Create a cluster chain */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY +static +DWORD create_chain ( /* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:Disk error, >=2:New cluster# */ + FATFS* fs, /* File system object */ + DWORD clst /* Cluster# to stretch. 0 means create a new chain. */ +) +{ + DWORD cs, ncl, scl; + FRESULT res; + + + if (clst == 0) { /* Create a new chain */ + scl = fs->last_clust; /* Get suggested start point */ + if (!scl || scl >= fs->n_fatent) scl = 1; + } + else { /* Stretch the current chain */ + cs = get_fat(fs, clst); /* Check the cluster status */ + if (cs < 2) return 1; /* Invalid value */ + if (cs == 0xFFFFFFFF) return cs; /* A disk error occurred */ + if (cs < fs->n_fatent) return cs; /* It is already followed by next cluster */ + scl = clst; + } + + ncl = scl; /* Start cluster */ + for (;;) { + ncl++; /* Next cluster */ + if (ncl >= fs->n_fatent) { /* Check wrap around */ + ncl = 2; + if (ncl > scl) return 0; /* No free cluster */ + } + cs = get_fat(fs, ncl); /* Get the cluster status */ + if (cs == 0) break; /* Found a free cluster */ + if (cs == 0xFFFFFFFF || cs == 1)/* An error occurred */ + return cs; + if (ncl == scl) return 0; /* No free cluster */ + } + + res = put_fat(fs, ncl, 0x0FFFFFFF); /* Mark the new cluster "last link" */ + if (res == FR_OK && clst != 0) { + res = put_fat(fs, clst, ncl); /* Link it to the previous one if needed */ + } + if (res == FR_OK) { + fs->last_clust = ncl; /* Update FSINFO */ + if (fs->free_clust != 0xFFFFFFFF) { + fs->free_clust--; + fs->fsi_flag |= 1; + } + } else { + ncl = (res == FR_DISK_ERR) ? 0xFFFFFFFF : 1; + } + + return ncl; /* Return new cluster number or error code */ +} +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* FAT handling - Convert offset into cluster with link map table */ +/*-----------------------------------------------------------------------*/ + +#if _USE_FASTSEEK +static +DWORD clmt_clust ( /* <2:Error, >=2:Cluster number */ + FIL* fp, /* Pointer to the file object */ + DWORD ofs /* File offset to be converted to cluster# */ +) +{ + DWORD cl, ncl, *tbl; + + + tbl = fp->cltbl + 1; /* Top of CLMT */ + cl = ofs / SS(fp->fs) / fp->fs->csize; /* Cluster order from top of the file */ + for (;;) { + ncl = *tbl++; /* Number of cluters in the fragment */ + if (!ncl) return 0; /* End of table? (error) */ + if (cl < ncl) break; /* In this fragment? */ + cl -= ncl; tbl++; /* Next fragment */ + } + return cl + *tbl; /* Return the cluster number */ +} +#endif /* _USE_FASTSEEK */ + + + + +/*-----------------------------------------------------------------------*/ +/* Directory handling - Set directory index */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT dir_sdi ( + DIR* dp, /* Pointer to directory object */ + UINT idx /* Index of directory table */ +) +{ + DWORD clst, sect; + UINT ic; + + + dp->index = (WORD)idx; /* Current index */ + clst = dp->sclust; /* Table start cluster (0:root) */ + if (clst == 1 || clst >= dp->fs->n_fatent) /* Check start cluster range */ + return FR_INT_ERR; + if (!clst && dp->fs->fs_type == FS_FAT32) /* Replace cluster# 0 with root cluster# if in FAT32 */ + clst = dp->fs->dirbase; + + if (clst == 0) { /* Static table (root-directory in FAT12/16) */ + if (idx >= dp->fs->n_rootdir) /* Is index out of range? */ + return FR_INT_ERR; + sect = dp->fs->dirbase; + } + else { /* Dynamic table (root-directory in FAT32 or sub-directory) */ + ic = SS(dp->fs) / SZ_DIR * dp->fs->csize; /* Entries per cluster */ + while (idx >= ic) { /* Follow cluster chain */ + clst = get_fat(dp->fs, clst); /* Get next cluster */ + if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ + if (clst < 2 || clst >= dp->fs->n_fatent) /* Reached to end of table or internal error */ + return FR_INT_ERR; + idx -= ic; + } + sect = clust2sect(dp->fs, clst); + } + dp->clust = clst; /* Current cluster# */ + if (!sect) return FR_INT_ERR; + dp->sect = sect + idx / (SS(dp->fs) / SZ_DIR); /* Sector# of the directory entry */ + dp->dir = dp->fs->win + (idx % (SS(dp->fs) / SZ_DIR)) * SZ_DIR; /* Ptr to the entry in the sector */ + + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Directory handling - Move directory table index next */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT dir_next ( /* FR_OK:Succeeded, FR_NO_FILE:End of table, FR_DENIED:Could not stretch */ + DIR* dp, /* Pointer to the directory object */ + int stretch /* 0: Do not stretch table, 1: Stretch table if needed */ +) +{ + DWORD clst; + UINT i; + + + i = dp->index + 1; + if (!(i & 0xFFFF) || !dp->sect) /* Report EOT when index has reached 65535 */ + return FR_NO_FILE; + + if (!(i % (SS(dp->fs) / SZ_DIR))) { /* Sector changed? */ + dp->sect++; /* Next sector */ + + if (!dp->clust) { /* Static table */ + if (i >= dp->fs->n_rootdir) /* Report EOT if it reached end of static table */ + return FR_NO_FILE; + } + else { /* Dynamic table */ + if (((i / (SS(dp->fs) / SZ_DIR)) & (dp->fs->csize - 1)) == 0) { /* Cluster changed? */ + clst = get_fat(dp->fs, dp->clust); /* Get next cluster */ + if (clst <= 1) return FR_INT_ERR; + if (clst == 0xFFFFFFFF) return FR_DISK_ERR; + if (clst >= dp->fs->n_fatent) { /* If it reached end of dynamic table, */ +#if !_FS_READONLY + UINT c; + if (!stretch) return FR_NO_FILE; /* If do not stretch, report EOT */ + clst = create_chain(dp->fs, dp->clust); /* Stretch cluster chain */ + if (clst == 0) return FR_DENIED; /* No free cluster */ + if (clst == 1) return FR_INT_ERR; + if (clst == 0xFFFFFFFF) return FR_DISK_ERR; + /* Clean-up stretched table */ + if (sync_window(dp->fs)) return FR_DISK_ERR;/* Flush disk access window */ + mem_set(dp->fs->win, 0, SS(dp->fs)); /* Clear window buffer */ + dp->fs->winsect = clust2sect(dp->fs, clst); /* Cluster start sector */ + for (c = 0; c < dp->fs->csize; c++) { /* Fill the new cluster with 0 */ + dp->fs->wflag = 1; + if (sync_window(dp->fs)) return FR_DISK_ERR; + dp->fs->winsect++; + } + dp->fs->winsect -= c; /* Rewind window offset */ +#else + if (!stretch) return FR_NO_FILE; /* If do not stretch, report EOT (this is to suppress warning) */ + return FR_NO_FILE; /* Report EOT */ +#endif + } + dp->clust = clst; /* Initialize data for new cluster */ + dp->sect = clust2sect(dp->fs, clst); + } + } + } + + dp->index = (WORD)i; /* Current index */ + dp->dir = dp->fs->win + (i % (SS(dp->fs) / SZ_DIR)) * SZ_DIR; /* Current entry in the window */ + + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Directory handling - Reserve directory entry */ +/*-----------------------------------------------------------------------*/ + +#if !_FS_READONLY +static +FRESULT dir_alloc ( + DIR* dp, /* Pointer to the directory object */ + UINT nent /* Number of contiguous entries to allocate (1-21) */ +) +{ + FRESULT res; + UINT n; + + + res = dir_sdi(dp, 0); + if (res == FR_OK) { + n = 0; + do { + res = move_window(dp->fs, dp->sect); + if (res != FR_OK) break; + if (dp->dir[0] == DDE || dp->dir[0] == 0) { /* Is it a blank entry? */ + if (++n == nent) break; /* A block of contiguous entries is found */ + } else { + n = 0; /* Not a blank entry. Restart to search */ + } + res = dir_next(dp, 1); /* Next entry with table stretch enabled */ + } while (res == FR_OK); + } + if (res == FR_NO_FILE) res = FR_DENIED; /* No directory entry to allocate */ + return res; +} +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* Directory handling - Load/Store start cluster number */ +/*-----------------------------------------------------------------------*/ + +static +DWORD ld_clust ( + FATFS* fs, /* Pointer to the fs object */ + BYTE* dir /* Pointer to the directory entry */ +) +{ + DWORD cl; + + cl = LD_WORD(dir+DIR_FstClusLO); + if (fs->fs_type == FS_FAT32) + cl |= (DWORD)LD_WORD(dir+DIR_FstClusHI) << 16; + + return cl; +} + + +#if !_FS_READONLY +static +void st_clust ( + BYTE* dir, /* Pointer to the directory entry */ + DWORD cl /* Value to be set */ +) +{ + ST_WORD(dir+DIR_FstClusLO, cl); + ST_WORD(dir+DIR_FstClusHI, cl >> 16); +} +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* LFN handling - Test/Pick/Fit an LFN segment from/to directory entry */ +/*-----------------------------------------------------------------------*/ +#if _USE_LFN +static +const BYTE LfnOfs[] = {1,3,5,7,9,14,16,18,20,22,24,28,30}; /* Offset of LFN characters in the directory entry */ + + +static +int cmp_lfn ( /* 1:Matched, 0:Not matched */ + WCHAR* lfnbuf, /* Pointer to the LFN to be compared */ + BYTE* dir /* Pointer to the directory entry containing a part of LFN */ +) +{ + UINT i, s; + WCHAR wc, uc; + + + i = ((dir[LDIR_Ord] & ~LLE) - 1) * 13; /* Get offset in the LFN buffer */ + s = 0; wc = 1; + do { + uc = LD_WORD(dir+LfnOfs[s]); /* Pick an LFN character from the entry */ + if (wc) { /* Last character has not been processed */ + wc = ff_wtoupper(uc); /* Convert it to upper case */ + if (i >= _MAX_LFN || wc != ff_wtoupper(lfnbuf[i++])) /* Compare it */ + return 0; /* Not matched */ + } else { + if (uc != 0xFFFF) return 0; /* Check filler */ + } + } while (++s < 13); /* Repeat until all characters in the entry are checked */ + + if ((dir[LDIR_Ord] & LLE) && wc && lfnbuf[i]) /* Last segment matched but different length */ + return 0; + + return 1; /* The part of LFN matched */ +} + + + +static +int pick_lfn ( /* 1:Succeeded, 0:Buffer overflow */ + WCHAR* lfnbuf, /* Pointer to the Unicode-LFN buffer */ + BYTE* dir /* Pointer to the directory entry */ +) +{ + UINT i, s; + WCHAR wc, uc; + + + i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13; /* Offset in the LFN buffer */ + + s = 0; wc = 1; + do { + uc = LD_WORD(dir+LfnOfs[s]); /* Pick an LFN character from the entry */ + if (wc) { /* Last character has not been processed */ + if (i >= _MAX_LFN) return 0; /* Buffer overflow? */ + lfnbuf[i++] = wc = uc; /* Store it */ + } else { + if (uc != 0xFFFF) return 0; /* Check filler */ + } + } while (++s < 13); /* Read all character in the entry */ + + if (dir[LDIR_Ord] & LLE) { /* Put terminator if it is the last LFN part */ + if (i >= _MAX_LFN) return 0; /* Buffer overflow? */ + lfnbuf[i] = 0; + } + + return 1; +} + + +#if !_FS_READONLY +static +void fit_lfn ( + const WCHAR* lfnbuf, /* Pointer to the LFN buffer */ + BYTE* dir, /* Pointer to the directory entry */ + BYTE ord, /* LFN order (1-20) */ + BYTE sum /* SFN sum */ +) +{ + UINT i, s; + WCHAR wc; + + + dir[LDIR_Chksum] = sum; /* Set check sum */ + dir[LDIR_Attr] = AM_LFN; /* Set attribute. LFN entry */ + dir[LDIR_Type] = 0; + ST_WORD(dir+LDIR_FstClusLO, 0); + + i = (ord - 1) * 13; /* Get offset in the LFN buffer */ + s = wc = 0; + do { + if (wc != 0xFFFF) wc = lfnbuf[i++]; /* Get an effective character */ + ST_WORD(dir+LfnOfs[s], wc); /* Put it */ + if (!wc) wc = 0xFFFF; /* Padding characters following last character */ + } while (++s < 13); + if (wc == 0xFFFF || !lfnbuf[i]) ord |= LLE; /* Bottom LFN part is the start of LFN sequence */ + dir[LDIR_Ord] = ord; /* Set the LFN order */ +} + +#endif +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* Create numbered name */ +/*-----------------------------------------------------------------------*/ +#if _USE_LFN +static +void gen_numname ( + BYTE* dst, /* Pointer to the buffer to store numbered SFN */ + const BYTE* src, /* Pointer to SFN */ + const WCHAR* lfn, /* Pointer to LFN */ + UINT seq /* Sequence number */ +) +{ + BYTE ns[8], c; + UINT i, j; + + + mem_cpy(dst, src, 11); + + if (seq > 5) { /* On many collisions, generate a hash number instead of sequential number */ + WCHAR wc; + DWORD sr = seq; + + while (*lfn) { /* Create a CRC */ + wc = *lfn++; + for (i = 0; i < 16; i++) { + sr = (sr << 1) + (wc & 1); + wc >>= 1; + if (sr & 0x10000) sr ^= 0x11021; + } + } + seq = (UINT)sr; + } + + /* itoa (hexdecimal) */ + i = 7; + do { + c = (seq % 16) + '0'; + if (c > '9') c += 7; + ns[i--] = c; + seq /= 16; + } while (seq); + ns[i] = '~'; + + /* Append the number */ + for (j = 0; j < i && dst[j] != ' '; j++) { + if (IsDBCS1(dst[j])) { + if (j == i - 1) break; + j++; + } + } + do { + dst[j++] = (i < 8) ? ns[i++] : ' '; + } while (j < 8); +} +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* Calculate sum of an SFN */ +/*-----------------------------------------------------------------------*/ +#if _USE_LFN +static +BYTE sum_sfn ( + const BYTE* dir /* Pointer to the SFN entry */ +) +{ + BYTE sum = 0; + UINT n = 11; + + do sum = (sum >> 1) + (sum << 7) + *dir++; while (--n); + return sum; +} +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* Directory handling - Find an object in the directory */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT dir_find ( + DIR* dp /* Pointer to the directory object linked to the file name */ +) +{ + FRESULT res; + BYTE c, *dir; +#if _USE_LFN + BYTE a, ord, sum; +#endif + + res = dir_sdi(dp, 0); /* Rewind directory object */ + if (res != FR_OK) return res; + +#if _USE_LFN + ord = sum = 0xFF; dp->lfn_idx = 0xFFFF; /* Reset LFN sequence */ +#endif + do { + res = move_window(dp->fs, dp->sect); + if (res != FR_OK) break; + dir = dp->dir; /* Ptr to the directory entry of current index */ + c = dir[DIR_Name]; + if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */ +#if _USE_LFN /* LFN configuration */ + a = dir[DIR_Attr] & AM_MASK; + if (c == DDE || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */ + ord = 0xFF; dp->lfn_idx = 0xFFFF; /* Reset LFN sequence */ + } else { + if (a == AM_LFN) { /* An LFN entry is found */ + if (dp->lfn) { + if (c & LLE) { /* Is it start of LFN sequence? */ + sum = dir[LDIR_Chksum]; + c &= ~LLE; ord = c; /* LFN start order */ + dp->lfn_idx = dp->index; /* Start index of LFN */ + } + /* Check validity of the LFN entry and compare it with given name */ + ord = (c == ord && sum == dir[LDIR_Chksum] && cmp_lfn(dp->lfn, dir)) ? ord - 1 : 0xFF; + } + } else { /* An SFN entry is found */ + if (!ord && sum == sum_sfn(dir)) break; /* LFN matched? */ + if (!(dp->fn[NS] & NS_LOSS) && !mem_cmp(dir, dp->fn, 11)) break; /* SFN matched? */ + ord = 0xFF; dp->lfn_idx = 0xFFFF; /* Reset LFN sequence */ + } + } +#else /* Non LFN configuration */ + if (!(dir[DIR_Attr] & AM_VOL) && !mem_cmp(dir, dp->fn, 11)) /* Is it a valid entry? */ + break; +#endif + res = dir_next(dp, 0); /* Next entry */ + } while (res == FR_OK); + + return res; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Read an object from the directory */ +/*-----------------------------------------------------------------------*/ +#if _FS_MINIMIZE <= 1 || _USE_LABEL || _FS_RPATH >= 2 +static +FRESULT dir_read ( + DIR* dp, /* Pointer to the directory object */ + int vol /* Filtered by 0:file/directory or 1:volume label */ +) +{ + FRESULT res; + BYTE a, c, *dir; +#if _USE_LFN + BYTE ord = 0xFF, sum = 0xFF; +#endif + + res = FR_NO_FILE; + while (dp->sect) { + res = move_window(dp->fs, dp->sect); + if (res != FR_OK) break; + dir = dp->dir; /* Ptr to the directory entry of current index */ + c = dir[DIR_Name]; + if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */ + a = dir[DIR_Attr] & AM_MASK; +#if _USE_LFN /* LFN configuration */ + if (c == DDE || (!_FS_RPATH && c == '.') || (int)(a == AM_VOL) != vol) { /* An entry without valid data */ + ord = 0xFF; + } else { + if (a == AM_LFN) { /* An LFN entry is found */ + if (c & LLE) { /* Is it start of LFN sequence? */ + sum = dir[LDIR_Chksum]; + c &= ~LLE; ord = c; + dp->lfn_idx = dp->index; + } + /* Check LFN validity and capture it */ + ord = (c == ord && sum == dir[LDIR_Chksum] && pick_lfn(dp->lfn, dir)) ? ord - 1 : 0xFF; + } else { /* An SFN entry is found */ + if (ord || sum != sum_sfn(dir)) /* Is there a valid LFN? */ + dp->lfn_idx = 0xFFFF; /* It has no LFN. */ + break; + } + } +#else /* Non LFN configuration */ + if (c != DDE && (_FS_RPATH || c != '.') && a != AM_LFN && (int)(a == AM_VOL) == vol) /* Is it a valid entry? */ + break; +#endif + res = dir_next(dp, 0); /* Next entry */ + if (res != FR_OK) break; + } + + if (res != FR_OK) dp->sect = 0; + + return res; +} +#endif /* _FS_MINIMIZE <= 1 || _USE_LABEL || _FS_RPATH >= 2 */ + + + + +/*-----------------------------------------------------------------------*/ +/* Register an object to the directory */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY +static +FRESULT dir_register ( /* FR_OK:Successful, FR_DENIED:No free entry or too many SFN collision, FR_DISK_ERR:Disk error */ + DIR* dp /* Target directory with object name to be created */ +) +{ + FRESULT res; +#if _USE_LFN /* LFN configuration */ + UINT n, nent; + BYTE sn[12], *fn, sum; + WCHAR *lfn; + + + fn = dp->fn; lfn = dp->lfn; + mem_cpy(sn, fn, 12); + + if (_FS_RPATH && (sn[NS] & NS_DOT)) /* Cannot create dot entry */ + return FR_INVALID_NAME; + + if (sn[NS] & NS_LOSS) { /* When LFN is out of 8.3 format, generate a numbered name */ + fn[NS] = 0; dp->lfn = 0; /* Find only SFN */ + for (n = 1; n < 100; n++) { + gen_numname(fn, sn, lfn, n); /* Generate a numbered name */ + res = dir_find(dp); /* Check if the name collides with existing SFN */ + if (res != FR_OK) break; + } + if (n == 100) return FR_DENIED; /* Abort if too many collisions */ + if (res != FR_NO_FILE) return res; /* Abort if the result is other than 'not collided' */ + fn[NS] = sn[NS]; dp->lfn = lfn; + } + + if (sn[NS] & NS_LFN) { /* When LFN is to be created, allocate entries for an SFN + LFNs. */ + for (n = 0; lfn[n]; n++) ; + nent = (n + 25) / 13; + } else { /* Otherwise allocate an entry for an SFN */ + nent = 1; + } + res = dir_alloc(dp, nent); /* Allocate entries */ + + if (res == FR_OK && --nent) { /* Set LFN entry if needed */ + res = dir_sdi(dp, dp->index - nent); + if (res == FR_OK) { + sum = sum_sfn(dp->fn); /* Sum value of the SFN tied to the LFN */ + do { /* Store LFN entries in bottom first */ + res = move_window(dp->fs, dp->sect); + if (res != FR_OK) break; + fit_lfn(dp->lfn, dp->dir, (BYTE)nent, sum); + dp->fs->wflag = 1; + res = dir_next(dp, 0); /* Next entry */ + } while (res == FR_OK && --nent); + } + } +#else /* Non LFN configuration */ + res = dir_alloc(dp, 1); /* Allocate an entry for SFN */ +#endif + + if (res == FR_OK) { /* Set SFN entry */ + res = move_window(dp->fs, dp->sect); + if (res == FR_OK) { + mem_set(dp->dir, 0, SZ_DIR); /* Clean the entry */ + mem_cpy(dp->dir, dp->fn, 11); /* Put SFN */ +#if _USE_LFN + dp->dir[DIR_NTres] = dp->fn[NS] & (NS_BODY | NS_EXT); /* Put NT flag */ +#endif + dp->fs->wflag = 1; + } + } + + return res; +} +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* Remove an object from the directory */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY && !_FS_MINIMIZE +static +FRESULT dir_remove ( /* FR_OK: Successful, FR_DISK_ERR: A disk error */ + DIR* dp /* Directory object pointing the entry to be removed */ +) +{ + FRESULT res; +#if _USE_LFN /* LFN configuration */ + UINT i; + + i = dp->index; /* SFN index */ + res = dir_sdi(dp, (dp->lfn_idx == 0xFFFF) ? i : dp->lfn_idx); /* Goto the SFN or top of the LFN entries */ + if (res == FR_OK) { + do { + res = move_window(dp->fs, dp->sect); + if (res != FR_OK) break; + mem_set(dp->dir, 0, SZ_DIR); /* Clear and mark the entry "deleted" */ + *dp->dir = DDE; + dp->fs->wflag = 1; + if (dp->index >= i) break; /* When reached SFN, all entries of the object has been deleted. */ + res = dir_next(dp, 0); /* Next entry */ + } while (res == FR_OK); + if (res == FR_NO_FILE) res = FR_INT_ERR; + } + +#else /* Non LFN configuration */ + res = dir_sdi(dp, dp->index); + if (res == FR_OK) { + res = move_window(dp->fs, dp->sect); + if (res == FR_OK) { + mem_set(dp->dir, 0, SZ_DIR); /* Clear and mark the entry "deleted" */ + *dp->dir = DDE; + dp->fs->wflag = 1; + } + } +#endif + + return res; +} +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* Get file information from directory entry */ +/*-----------------------------------------------------------------------*/ +#if _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 +static +void get_fileinfo ( /* No return code */ + DIR* dp, /* Pointer to the directory object */ + FILINFO* fno /* Pointer to the file information to be filled */ +) +{ + UINT i; + TCHAR *p, c; + + + p = fno->fname; + if (dp->sect) { /* Get SFN */ + BYTE *dir = dp->dir; + + i = 0; + while (i < 11) { /* Copy name body and extension */ + c = (TCHAR)dir[i++]; + if (c == ' ') continue; /* Skip padding spaces */ + if (c == NDDE) c = (TCHAR)DDE; /* Restore replaced DDE character */ + if (i == 9) *p++ = '.'; /* Insert a . if extension is exist */ +#if _USE_LFN + if (IsUpper(c) && (dir[DIR_NTres] & (i >= 9 ? NS_EXT : NS_BODY))) + c += 0x20; /* To lower */ +#if _LFN_UNICODE + if (IsDBCS1(c) && i != 8 && i != 11 && IsDBCS2(dir[i])) + c = c << 8 | dir[i++]; + c = ff_convert(c, 1); /* OEM -> Unicode */ + if (!c) c = '?'; +#endif +#endif + *p++ = c; + } + fno->fattrib = dir[DIR_Attr]; /* Attribute */ + fno->fsize = LD_DWORD(dir+DIR_FileSize); /* Size */ + fno->fdate = LD_WORD(dir+DIR_WrtDate); /* Date */ + fno->ftime = LD_WORD(dir+DIR_WrtTime); /* Time */ + } + *p = 0; /* Terminate SFN string by a \0 */ + +#if _USE_LFN + if (fno->lfname) { + WCHAR w, *lfn; + + i = 0; p = fno->lfname; + if (dp->sect && fno->lfsize && dp->lfn_idx != 0xFFFF) { /* Get LFN if available */ + lfn = dp->lfn; + while ((w = *lfn++) != 0) { /* Get an LFN character */ +#if !_LFN_UNICODE + w = ff_convert(w, 0); /* Unicode -> OEM */ + if (!w) { i = 0; break; } /* No LFN if it could not be converted */ + if (_DF1S && w >= 0x100) /* Put 1st byte if it is a DBC (always false on SBCS cfg) */ + p[i++] = (TCHAR)(w >> 8); +#endif + if (i >= fno->lfsize - 1) { i = 0; break; } /* No LFN if buffer overflow */ + p[i++] = (TCHAR)w; + } + } + p[i] = 0; /* Terminate LFN string by a \0 */ + } +#endif +} +#endif /* _FS_MINIMIZE <= 1 || _FS_RPATH >= 2*/ + + + + +/*-----------------------------------------------------------------------*/ +/* Pick a segment and create the object name in directory form */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT create_name ( + DIR* dp, /* Pointer to the directory object */ + const TCHAR** path /* Pointer to pointer to the segment in the path string */ +) +{ +#if _USE_LFN /* LFN configuration */ + BYTE b, cf; + WCHAR w, *lfn; + UINT i, ni, si, di; + const TCHAR *p; + + /* Create LFN in Unicode */ + for (p = *path; *p == '/' || *p == '\\'; p++) ; /* Strip duplicated separator */ + lfn = dp->lfn; + si = di = 0; + for (;;) { + w = p[si++]; /* Get a character */ + if (w < ' ' || w == '/' || w == '\\') break; /* Break on end of segment */ + if (di >= _MAX_LFN) /* Reject too long name */ + return FR_INVALID_NAME; +#if !_LFN_UNICODE + w &= 0xFF; + if (IsDBCS1(w)) { /* Check if it is a DBC 1st byte (always false on SBCS cfg) */ + b = (BYTE)p[si++]; /* Get 2nd byte */ + if (!IsDBCS2(b)) + return FR_INVALID_NAME; /* Reject invalid sequence */ + w = (w << 8) + b; /* Create a DBC */ + } + w = ff_convert(w, 1); /* Convert ANSI/OEM to Unicode */ + if (!w) return FR_INVALID_NAME; /* Reject invalid code */ +#endif + if (w < 0x80 && chk_chr("\"*:<>\?|\x7F", w)) /* Reject illegal characters for LFN */ + return FR_INVALID_NAME; + lfn[di++] = w; /* Store the Unicode character */ + } + *path = &p[si]; /* Return pointer to the next segment */ + cf = (w < ' ') ? NS_LAST : 0; /* Set last segment flag if end of path */ +#if _FS_RPATH + if ((di == 1 && lfn[di-1] == '.') || /* Is this a dot entry? */ + (di == 2 && lfn[di-1] == '.' && lfn[di-2] == '.')) { + lfn[di] = 0; + for (i = 0; i < 11; i++) + dp->fn[i] = (i < di) ? '.' : ' '; + dp->fn[i] = cf | NS_DOT; /* This is a dot entry */ + return FR_OK; + } +#endif + while (di) { /* Strip trailing spaces and dots */ + w = lfn[di-1]; + if (w != ' ' && w != '.') break; + di--; + } + if (!di) return FR_INVALID_NAME; /* Reject nul string */ + + lfn[di] = 0; /* LFN is created */ + + /* Create SFN in directory form */ + mem_set(dp->fn, ' ', 11); + for (si = 0; lfn[si] == ' ' || lfn[si] == '.'; si++) ; /* Strip leading spaces and dots */ + if (si) cf |= NS_LOSS | NS_LFN; + while (di && lfn[di - 1] != '.') di--; /* Find extension (di<=si: no extension) */ + + b = i = 0; ni = 8; + for (;;) { + w = lfn[si++]; /* Get an LFN character */ + if (!w) break; /* Break on end of the LFN */ + if (w == ' ' || (w == '.' && si != di)) { /* Remove spaces and dots */ + cf |= NS_LOSS | NS_LFN; continue; + } + + if (i >= ni || si == di) { /* Extension or end of SFN */ + if (ni == 11) { /* Long extension */ + cf |= NS_LOSS | NS_LFN; break; + } + if (si != di) cf |= NS_LOSS | NS_LFN; /* Out of 8.3 format */ + if (si > di) break; /* No extension */ + si = di; i = 8; ni = 11; /* Enter extension section */ + b <<= 2; continue; + } + + if (w >= 0x80) { /* Non ASCII character */ +#ifdef _EXCVT + w = ff_convert(w, 0); /* Unicode -> OEM code */ + if (w) w = ExCvt[w - 0x80]; /* Convert extended character to upper (SBCS) */ +#else + w = ff_convert(ff_wtoupper(w), 0); /* Upper converted Unicode -> OEM code */ +#endif + cf |= NS_LFN; /* Force create LFN entry */ + } + + if (_DF1S && w >= 0x100) { /* Double byte character (always false on SBCS cfg) */ + if (i >= ni - 1) { + cf |= NS_LOSS | NS_LFN; i = ni; continue; + } + dp->fn[i++] = (BYTE)(w >> 8); + } else { /* Single byte character */ + if (!w || chk_chr("+,;=[]", w)) { /* Replace illegal characters for SFN */ + w = '_'; cf |= NS_LOSS | NS_LFN;/* Lossy conversion */ + } else { + if (IsUpper(w)) { /* ASCII large capital */ + b |= 2; + } else { + if (IsLower(w)) { /* ASCII small capital */ + b |= 1; w -= 0x20; + } + } + } + } + dp->fn[i++] = (BYTE)w; + } + + if (dp->fn[0] == DDE) dp->fn[0] = NDDE; /* If the first character collides with deleted mark, replace it with 0x05 */ + + if (ni == 8) b <<= 2; + if ((b & 0x0C) == 0x0C || (b & 0x03) == 0x03) /* Create LFN entry when there are composite capitals */ + cf |= NS_LFN; + if (!(cf & NS_LFN)) { /* When LFN is in 8.3 format without extended character, NT flags are created */ + if ((b & 0x03) == 0x01) cf |= NS_EXT; /* NT flag (Extension has only small capital) */ + if ((b & 0x0C) == 0x04) cf |= NS_BODY; /* NT flag (Filename has only small capital) */ + } + + dp->fn[NS] = cf; /* SFN is created */ + + return FR_OK; + + +#else /* Non-LFN configuration */ + BYTE b, c, d, *sfn; + UINT ni, si, i; + const char *p; + + /* Create file name in directory form */ + for (p = *path; *p == '/' || *p == '\\'; p++) ; /* Strip duplicated separator */ + sfn = dp->fn; + mem_set(sfn, ' ', 11); + si = i = b = 0; ni = 8; +#if _FS_RPATH + if (p[si] == '.') { /* Is this a dot entry? */ + for (;;) { + c = (BYTE)p[si++]; + if (c != '.' || si >= 3) break; + sfn[i++] = c; + } + if (c != '/' && c != '\\' && c > ' ') return FR_INVALID_NAME; + *path = &p[si]; /* Return pointer to the next segment */ + sfn[NS] = (c <= ' ') ? NS_LAST | NS_DOT : NS_DOT; /* Set last segment flag if end of path */ + return FR_OK; + } +#endif + for (;;) { + c = (BYTE)p[si++]; + if (c <= ' ' || c == '/' || c == '\\') break; /* Break on end of segment */ + if (c == '.' || i >= ni) { + if (ni != 8 || c != '.') return FR_INVALID_NAME; + i = 8; ni = 11; + b <<= 2; continue; + } + if (c >= 0x80) { /* Extended character? */ + b |= 3; /* Eliminate NT flag */ +#ifdef _EXCVT + c = ExCvt[c - 0x80]; /* To upper extended characters (SBCS cfg) */ +#else +#if !_DF1S + return FR_INVALID_NAME; /* Reject extended characters (ASCII cfg) */ +#endif +#endif + } + if (IsDBCS1(c)) { /* Check if it is a DBC 1st byte (always false on SBCS cfg) */ + d = (BYTE)p[si++]; /* Get 2nd byte */ + if (!IsDBCS2(d) || i >= ni - 1) /* Reject invalid DBC */ + return FR_INVALID_NAME; + sfn[i++] = c; + sfn[i++] = d; + } else { /* Single byte code */ + if (chk_chr("\"*+,:;<=>\?[]|\x7F", c)) /* Reject illegal chrs for SFN */ + return FR_INVALID_NAME; + if (IsUpper(c)) { /* ASCII large capital? */ + b |= 2; + } else { + if (IsLower(c)) { /* ASCII small capital? */ + b |= 1; c -= 0x20; + } + } + sfn[i++] = c; + } + } + *path = &p[si]; /* Return pointer to the next segment */ + c = (c <= ' ') ? NS_LAST : 0; /* Set last segment flag if end of path */ + + if (!i) return FR_INVALID_NAME; /* Reject nul string */ + if (sfn[0] == DDE) sfn[0] = NDDE; /* When first character collides with DDE, replace it with 0x05 */ + + if (ni == 8) b <<= 2; + if ((b & 0x03) == 0x01) c |= NS_EXT; /* NT flag (Name extension has only small capital) */ + if ((b & 0x0C) == 0x04) c |= NS_BODY; /* NT flag (Name body has only small capital) */ + + sfn[NS] = c; /* Store NT flag, File name is created */ + + return FR_OK; +#endif +} + + + + +/*-----------------------------------------------------------------------*/ +/* Follow a file path */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT follow_path ( /* FR_OK(0): successful, !=0: error code */ + DIR* dp, /* Directory object to return last directory and found object */ + const TCHAR* path /* Full-path string to find a file or directory */ +) +{ + FRESULT res; + BYTE *dir, ns; + + +#if _FS_RPATH + if (*path == '/' || *path == '\\') { /* There is a heading separator */ + path++; dp->sclust = 0; /* Strip it and start from the root directory */ + } else { /* No heading separator */ + dp->sclust = dp->fs->cdir; /* Start from the current directory */ + } +#else + if (*path == '/' || *path == '\\') /* Strip heading separator if exist */ + path++; + dp->sclust = 0; /* Always start from the root directory */ +#endif + + if ((UINT)*path < ' ') { /* Null path name is the origin directory itself */ + res = dir_sdi(dp, 0); + dp->dir = 0; + } else { /* Follow path */ + for (;;) { + res = create_name(dp, &path); /* Get a segment name of the path */ + if (res != FR_OK) break; + res = dir_find(dp); /* Find an object with the sagment name */ + ns = dp->fn[NS]; + if (res != FR_OK) { /* Failed to find the object */ + if (res == FR_NO_FILE) { /* Object is not found */ + if (_FS_RPATH && (ns & NS_DOT)) { /* If dot entry is not exist, */ + dp->sclust = 0; dp->dir = 0; /* it is the root directory and stay there */ + if (!(ns & NS_LAST)) continue; /* Continue to follow if not last segment */ + res = FR_OK; /* Ended at the root directroy. Function completed. */ + } else { /* Could not find the object */ + if (!(ns & NS_LAST)) res = FR_NO_PATH; /* Adjust error code if not last segment */ + } + } + break; + } + if (ns & NS_LAST) break; /* Last segment matched. Function completed. */ + dir = dp->dir; /* Follow the sub-directory */ + if (!(dir[DIR_Attr] & AM_DIR)) { /* It is not a sub-directory and cannot follow */ + res = FR_NO_PATH; break; + } + dp->sclust = ld_clust(dp->fs, dir); + } + } + + return res; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Get logical drive number from path name */ +/*-----------------------------------------------------------------------*/ + +static +int get_ldnumber ( /* Returns logical drive number (-1:invalid drive) */ + const TCHAR** path /* Pointer to pointer to the path name */ +) +{ + const TCHAR *tp, *tt; + UINT i; + int vol = -1; + + + if (*path) { /* If the pointer is not a null */ + for (tt = *path; (UINT)*tt >= (_USE_LFN ? ' ' : '!') && *tt != ':'; tt++) ; /* Find ':' in the path */ + if (*tt == ':') { /* If a ':' is exist in the path name */ + tp = *path; + i = *tp++ - '0'; + if (i < 10 && tp == tt) { /* Is there a numeric drive id? */ + if (i < _VOLUMES) { /* If a drive id is found, get the value and strip it */ + vol = (int)i; + *path = ++tt; + } + } else { /* No numeric drive number */ +#if _STR_VOLUME_ID /* Find string drive id */ + static const char* const str[] = {_VOLUME_STRS}; + const char *sp; + char c; + TCHAR tc; + + i = 0; tt++; + do { + sp = str[i]; tp = *path; + do { /* Compare a string drive id with path name */ + c = *sp++; tc = *tp++; + if (IsLower(tc)) tc -= 0x20; + } while (c && (TCHAR)c == tc); + } while ((c || tp != tt) && ++i < _VOLUMES); /* Repeat for each id until pattern match */ + if (i < _VOLUMES) { /* If a drive id is found, get the value and strip it */ + vol = (int)i; + *path = tt; + } +#endif + } + return vol; + } +#if _FS_RPATH && _VOLUMES >= 2 + vol = CurrVol; /* Current drive */ +#else + vol = 0; /* Drive 0 */ +#endif + } + return vol; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Load a sector and check if it is an FAT boot sector */ +/*-----------------------------------------------------------------------*/ + +static +BYTE check_fs ( /* 0:FAT boor sector, 1:Valid boor sector but not FAT, 2:Not a boot sector, 3:Disk error */ + FATFS* fs, /* File system object */ + DWORD sect /* Sector# (lba) to check if it is an FAT boot record or not */ +) +{ + fs->wflag = 0; fs->winsect = 0xFFFFFFFF; /* Invaidate window */ + if (move_window(fs, sect) != FR_OK) /* Load boot record */ + return 3; + + if (LD_WORD(&fs->win[BS_55AA]) != 0xAA55) /* Check boot record signature (always placed at offset 510 even if the sector size is >512) */ + return 2; + + if ((LD_DWORD(&fs->win[BS_FilSysType]) & 0xFFFFFF) == 0x544146) /* Check "FAT" string */ + return 0; + if ((LD_DWORD(&fs->win[BS_FilSysType32]) & 0xFFFFFF) == 0x544146) /* Check "FAT" string */ + return 0; + + return 1; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Find logical drive and check if the volume is mounted */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT find_volume ( /* FR_OK(0): successful, !=0: any error occurred */ + FATFS** rfs, /* Pointer to pointer to the found file system object */ + const TCHAR** path, /* Pointer to pointer to the path name (drive number) */ + BYTE wmode /* !=0: Check write protection for write access */ +) +{ + BYTE fmt; + int vol; + DSTATUS stat; + DWORD bsect, fasize, tsect, sysect, nclst, szbfat; + WORD nrsv; + FATFS *fs; + + + /* Get logical drive number from the path name */ + *rfs = 0; + vol = get_ldnumber(path); + if (vol < 0) return FR_INVALID_DRIVE; + + /* Check if the file system object is valid or not */ + fs = FatFs[vol]; /* Get pointer to the file system object */ + if (!fs) return FR_NOT_ENABLED; /* Is the file system object available? */ + + ENTER_FF(fs); /* Lock the volume */ + *rfs = fs; /* Return pointer to the file system object */ + + if (fs->fs_type) { /* If the volume has been mounted */ + stat = disk_status(fs->drv); + if (!(stat & STA_NOINIT)) { /* and the physical drive is kept initialized */ + if (!_FS_READONLY && wmode && (stat & STA_PROTECT)) /* Check write protection if needed */ + return FR_WRITE_PROTECTED; + return FR_OK; /* The file system object is valid */ + } + } + + /* The file system object is not valid. */ + /* Following code attempts to mount the volume. (analyze BPB and initialize the fs object) */ + + fs->fs_type = 0; /* Clear the file system object */ + fs->drv = LD2PD(vol); /* Bind the logical drive and a physical drive */ + stat = disk_initialize(fs->drv); /* Initialize the physical drive */ + if (stat & STA_NOINIT) /* Check if the initialization succeeded */ + return FR_NOT_READY; /* Failed to initialize due to no medium or hard error */ + if (!_FS_READONLY && wmode && (stat & STA_PROTECT)) /* Check disk write protection if needed */ + return FR_WRITE_PROTECTED; +#if _MAX_SS != _MIN_SS /* Get sector size (multiple sector size cfg only) */ + if (disk_ioctl(fs->drv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK + || SS(fs) < _MIN_SS || SS(fs) > _MAX_SS) return FR_DISK_ERR; +#endif + /* Find an FAT partition on the drive. Supports only generic partitioning, FDISK and SFD. */ + bsect = 0; + fmt = check_fs(fs, bsect); /* Load sector 0 and check if it is an FAT boot sector as SFD */ + if (fmt == 1 || (!fmt && (LD2PT(vol)))) { /* Not an FAT boot sector or forced partition number */ + UINT i; + DWORD br[4]; + + for (i = 0; i < 4; i++) { /* Get partition offset */ + BYTE *pt = fs->win+MBR_Table + i * SZ_PTE; + br[i] = pt[4] ? LD_DWORD(&pt[8]) : 0; + } + i = LD2PT(vol); /* Partition number: 0:auto, 1-4:forced */ + if (i) i--; + do { /* Find an FAT volume */ + bsect = br[i]; + fmt = bsect ? check_fs(fs, bsect) : 2; /* Check the partition */ + } while (!LD2PT(vol) && fmt && ++i < 4); + } + if (fmt == 3) return FR_DISK_ERR; /* An error occured in the disk I/O layer */ + if (fmt) return FR_NO_FILESYSTEM; /* No FAT volume is found */ + + /* An FAT volume is found. Following code initializes the file system object */ + + if (LD_WORD(fs->win+BPB_BytsPerSec) != SS(fs)) /* (BPB_BytsPerSec must be equal to the physical sector size) */ + return FR_NO_FILESYSTEM; + + fasize = LD_WORD(fs->win+BPB_FATSz16); /* Number of sectors per FAT */ + if (!fasize) fasize = LD_DWORD(fs->win+BPB_FATSz32); + fs->fsize = fasize; + + fs->n_fats = fs->win[BPB_NumFATs]; /* Number of FAT copies */ + if (fs->n_fats != 1 && fs->n_fats != 2) /* (Must be 1 or 2) */ + return FR_NO_FILESYSTEM; + fasize *= fs->n_fats; /* Number of sectors for FAT area */ + + fs->csize = fs->win[BPB_SecPerClus]; /* Number of sectors per cluster */ + if (!fs->csize || (fs->csize & (fs->csize - 1))) /* (Must be power of 2) */ + return FR_NO_FILESYSTEM; + + fs->n_rootdir = LD_WORD(fs->win+BPB_RootEntCnt); /* Number of root directory entries */ + if (fs->n_rootdir % (SS(fs) / SZ_DIR)) /* (Must be sector aligned) */ + return FR_NO_FILESYSTEM; + + tsect = LD_WORD(fs->win+BPB_TotSec16); /* Number of sectors on the volume */ + if (!tsect) tsect = LD_DWORD(fs->win+BPB_TotSec32); + + nrsv = LD_WORD(fs->win+BPB_RsvdSecCnt); /* Number of reserved sectors */ + if (!nrsv) return FR_NO_FILESYSTEM; /* (Must not be 0) */ + + /* Determine the FAT sub type */ + sysect = nrsv + fasize + fs->n_rootdir / (SS(fs) / SZ_DIR); /* RSV+FAT+DIR */ + if (tsect < sysect) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ + nclst = (tsect - sysect) / fs->csize; /* Number of clusters */ + if (!nclst) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ + fmt = FS_FAT12; + if (nclst >= MIN_FAT16) fmt = FS_FAT16; + if (nclst >= MIN_FAT32) fmt = FS_FAT32; + + /* Boundaries and Limits */ + fs->n_fatent = nclst + 2; /* Number of FAT entries */ + fs->volbase = bsect; /* Volume start sector */ + fs->fatbase = bsect + nrsv; /* FAT start sector */ + fs->database = bsect + sysect; /* Data start sector */ + if (fmt == FS_FAT32) { + if (fs->n_rootdir) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be 0) */ + fs->dirbase = LD_DWORD(fs->win+BPB_RootClus); /* Root directory start cluster */ + szbfat = fs->n_fatent * 4; /* (Needed FAT size) */ + } else { + if (!fs->n_rootdir) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must not be 0) */ + fs->dirbase = fs->fatbase + fasize; /* Root directory start sector */ + szbfat = (fmt == FS_FAT16) ? /* (Needed FAT size) */ + fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1); + } + if (fs->fsize < (szbfat + (SS(fs) - 1)) / SS(fs)) /* (BPB_FATSz must not be less than needed) */ + return FR_NO_FILESYSTEM; + +#if !_FS_READONLY + /* Initialize cluster allocation information */ + fs->last_clust = fs->free_clust = 0xFFFFFFFF; + + /* Get fsinfo if available */ + fs->fsi_flag = 0x80; +#if (_FS_NOFSINFO & 3) != 3 + if (fmt == FS_FAT32 /* Enable FSINFO only if FAT32 and BPB_FSInfo is 1 */ + && LD_WORD(fs->win+BPB_FSInfo) == 1 + && move_window(fs, bsect + 1) == FR_OK) + { + fs->fsi_flag = 0; + if (LD_WORD(fs->win+BS_55AA) == 0xAA55 /* Load FSINFO data if available */ + && LD_DWORD(fs->win+FSI_LeadSig) == 0x41615252 + && LD_DWORD(fs->win+FSI_StrucSig) == 0x61417272) + { +#if (_FS_NOFSINFO & 1) == 0 + fs->free_clust = LD_DWORD(fs->win+FSI_Free_Count); +#endif +#if (_FS_NOFSINFO & 2) == 0 + fs->last_clust = LD_DWORD(fs->win+FSI_Nxt_Free); +#endif + } + } +#endif +#endif + fs->fs_type = fmt; /* FAT sub-type */ + fs->id = ++Fsid; /* File system mount ID */ +#if _FS_RPATH + fs->cdir = 0; /* Set current directory to root */ +#endif +#if _FS_LOCK /* Clear file lock semaphores */ + clear_lock(fs); +#endif + + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Check if the file/directory object is valid or not */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT validate ( /* FR_OK(0): The object is valid, !=0: Invalid */ + void* obj /* Pointer to the object FIL/DIR to check validity */ +) +{ + FIL *fil = (FIL*)obj; /* Assuming offset of .fs and .id in the FIL/DIR structure is identical */ + + + if (!fil || !fil->fs || !fil->fs->fs_type || fil->fs->id != fil->id) + return FR_INVALID_OBJECT; + + ENTER_FF(fil->fs); /* Lock file system */ + + if (disk_status(fil->fs->drv) & STA_NOINIT) + return FR_NOT_READY; + + return FR_OK; +} + + + + +/*-------------------------------------------------------------------------- + + Public Functions + +--------------------------------------------------------------------------*/ + + + +/*-----------------------------------------------------------------------*/ +/* Mount/Unmount a Logical Drive */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_mount ( + FATFS* fs, /* Pointer to the file system object (NULL:unmount)*/ + const TCHAR* path, /* Logical drive number to be mounted/unmounted */ + BYTE opt /* 0:Do not mount (delayed mount), 1:Mount immediately */ +) +{ + FATFS *cfs; + int vol; + FRESULT res; + const TCHAR *rp = path; + + + vol = get_ldnumber(&rp); + if (vol < 0) return FR_INVALID_DRIVE; + cfs = FatFs[vol]; /* Pointer to fs object */ + + if (cfs) { +#if _FS_LOCK + clear_lock(cfs); +#endif +#if _FS_REENTRANT /* Discard sync object of the current volume */ + if (!ff_del_syncobj(cfs->sobj)) return FR_INT_ERR; +#endif + cfs->fs_type = 0; /* Clear old fs object */ + } + + if (fs) { + fs->fs_type = 0; /* Clear new fs object */ +#if _FS_REENTRANT /* Create sync object for the new volume */ + if (!ff_cre_syncobj((BYTE)vol, &fs->sobj)) return FR_INT_ERR; +#endif + } + FatFs[vol] = fs; /* Register new fs object */ + + if (!fs || opt != 1) return FR_OK; /* Do not mount now, it will be mounted later */ + + res = find_volume(&fs, &path, 0); /* Force mounted the volume */ + LEAVE_FF(fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Open or Create a File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_open ( + FIL* fp, /* Pointer to the blank file object */ + const TCHAR* path, /* Pointer to the file name */ + BYTE mode /* Access mode and file open mode flags */ +) +{ + FRESULT res; + DIR dj; + BYTE *dir; + DEF_NAMEBUF; + + + if (!fp) return FR_INVALID_OBJECT; + fp->fs = 0; /* Clear file object */ + + /* Get logical drive number */ +#if !_FS_READONLY + mode &= FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW; + res = find_volume(&dj.fs, &path, (BYTE)(mode & ~FA_READ)); +#else + mode &= FA_READ; + res = find_volume(&dj.fs, &path, 0); +#endif + if (res == FR_OK) { + INIT_BUF(dj); + res = follow_path(&dj, path); /* Follow the file path */ + dir = dj.dir; +#if !_FS_READONLY /* R/W configuration */ + if (res == FR_OK) { + if (!dir) /* Default directory itself */ + res = FR_INVALID_NAME; +#if _FS_LOCK + else + res = chk_lock(&dj, (mode & ~FA_READ) ? 1 : 0); +#endif + } + /* Create or Open a file */ + if (mode & (FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW)) { + DWORD dw, cl; + + if (res != FR_OK) { /* No file, create new */ + if (res == FR_NO_FILE) /* There is no file to open, create a new entry */ +#if _FS_LOCK + res = enq_lock() ? dir_register(&dj) : FR_TOO_MANY_OPEN_FILES; +#else + res = dir_register(&dj); +#endif + mode |= FA_CREATE_ALWAYS; /* File is created */ + dir = dj.dir; /* New entry */ + } + else { /* Any object is already existing */ + if (dir[DIR_Attr] & (AM_RDO | AM_DIR)) { /* Cannot overwrite it (R/O or DIR) */ + res = FR_DENIED; + } else { + if (mode & FA_CREATE_NEW) /* Cannot create as new file */ + res = FR_EXIST; + } + } + if (res == FR_OK && (mode & FA_CREATE_ALWAYS)) { /* Truncate it if overwrite mode */ + dw = get_fattime(); /* Created time */ + ST_DWORD(dir+DIR_CrtTime, dw); + dir[DIR_Attr] = 0; /* Reset attribute */ + ST_DWORD(dir+DIR_FileSize, 0); /* size = 0 */ + cl = ld_clust(dj.fs, dir); /* Get start cluster */ + st_clust(dir, 0); /* cluster = 0 */ + dj.fs->wflag = 1; + if (cl) { /* Remove the cluster chain if exist */ + dw = dj.fs->winsect; + res = remove_chain(dj.fs, cl); + if (res == FR_OK) { + dj.fs->last_clust = cl - 1; /* Reuse the cluster hole */ + res = move_window(dj.fs, dw); + } + } + } + } + else { /* Open an existing file */ + if (res == FR_OK) { /* Follow succeeded */ + if (dir[DIR_Attr] & AM_DIR) { /* It is a directory */ + res = FR_NO_FILE; + } else { + if ((mode & FA_WRITE) && (dir[DIR_Attr] & AM_RDO)) /* R/O violation */ + res = FR_DENIED; + } + } + } + if (res == FR_OK) { + if (mode & FA_CREATE_ALWAYS) /* Set file change flag if created or overwritten */ + mode |= FA__WRITTEN; + fp->dir_sect = dj.fs->winsect; /* Pointer to the directory entry */ + fp->dir_ptr = dir; +#if _FS_LOCK + fp->lockid = inc_lock(&dj, (mode & ~FA_READ) ? 1 : 0); + if (!fp->lockid) res = FR_INT_ERR; +#endif + } + +#else /* R/O configuration */ + if (res == FR_OK) { /* Follow succeeded */ + dir = dj.dir; + if (!dir) { /* Current directory itself */ + res = FR_INVALID_NAME; + } else { + if (dir[DIR_Attr] & AM_DIR) /* It is a directory */ + res = FR_NO_FILE; + } + } +#endif + FREE_BUF(); + + if (res == FR_OK) { + fp->flag = mode; /* File access mode */ + fp->err = 0; /* Clear error flag */ + fp->sclust = ld_clust(dj.fs, dir); /* File start cluster */ + fp->fsize = LD_DWORD(dir+DIR_FileSize); /* File size */ + fp->fptr = 0; /* File pointer */ + fp->dsect = 0; +#if _USE_FASTSEEK + fp->cltbl = 0; /* Normal seek mode */ +#endif + fp->fs = dj.fs; /* Validate file object */ + fp->id = fp->fs->id; + } + } + + LEAVE_FF(dj.fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Read File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_read ( + FIL* fp, /* Pointer to the file object */ + void* buff, /* Pointer to data buffer */ + UINT btr, /* Number of bytes to read */ + UINT* br /* Pointer to number of bytes read */ +) +{ + FRESULT res; + DWORD clst, sect, remain; + UINT rcnt, cc; + BYTE csect, *rbuff = (BYTE*)buff; + + + *br = 0; /* Clear read byte counter */ + + res = validate(fp); /* Check validity */ + if (res != FR_OK) LEAVE_FF(fp->fs, res); + if (fp->err) /* Check error */ + LEAVE_FF(fp->fs, (FRESULT)fp->err); + if (!(fp->flag & FA_READ)) /* Check access mode */ + LEAVE_FF(fp->fs, FR_DENIED); + remain = fp->fsize - fp->fptr; + if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */ + + for ( ; btr; /* Repeat until all data read */ + rbuff += rcnt, fp->fptr += rcnt, *br += rcnt, btr -= rcnt) { + if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ + csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */ + if (!csect) { /* On the cluster boundary? */ + if (fp->fptr == 0) { /* On the top of the file? */ + clst = fp->sclust; /* Follow from the origin */ + } else { /* Middle or end of the file */ +#if _USE_FASTSEEK + if (fp->cltbl) + clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */ + else +#endif + clst = get_fat(fp->fs, fp->clust); /* Follow cluster chain on the FAT */ + } + if (clst < 2) ABORT(fp->fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); + fp->clust = clst; /* Update current cluster */ + } + sect = clust2sect(fp->fs, fp->clust); /* Get current sector */ + if (!sect) ABORT(fp->fs, FR_INT_ERR); + sect += csect; + cc = btr / SS(fp->fs); /* When remaining bytes >= sector size, */ + if (cc) { /* Read maximum contiguous sectors directly */ + if (csect + cc > fp->fs->csize) /* Clip at cluster boundary */ + cc = fp->fs->csize - csect; + if (disk_read(fp->fs->drv, rbuff, sect, cc)) + ABORT(fp->fs, FR_DISK_ERR); +#if !_FS_READONLY && _FS_MINIMIZE <= 2 /* Replace one of the read sectors with cached data if it contains a dirty sector */ +#if _FS_TINY + if (fp->fs->wflag && fp->fs->winsect - sect < cc) + mem_cpy(rbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), fp->fs->win, SS(fp->fs)); +#else + if ((fp->flag & FA__DIRTY) && fp->dsect - sect < cc) + mem_cpy(rbuff + ((fp->dsect - sect) * SS(fp->fs)), fp->buf, SS(fp->fs)); +#endif +#endif + rcnt = SS(fp->fs) * cc; /* Number of bytes transferred */ + continue; + } +#if !_FS_TINY + if (fp->dsect != sect) { /* Load data sector if not in cache */ +#if !_FS_READONLY + if (fp->flag & FA__DIRTY) { /* Write-back dirty sector cache */ + if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1)) + ABORT(fp->fs, FR_DISK_ERR); + fp->flag &= ~FA__DIRTY; + } +#endif + if (disk_read(fp->fs->drv, fp->buf, sect, 1)) /* Fill sector cache */ + ABORT(fp->fs, FR_DISK_ERR); + } +#endif + fp->dsect = sect; + } + rcnt = SS(fp->fs) - ((UINT)fp->fptr % SS(fp->fs)); /* Get partial sector data from sector buffer */ + if (rcnt > btr) rcnt = btr; +#if _FS_TINY + if (move_window(fp->fs, fp->dsect)) /* Move sector window */ + ABORT(fp->fs, FR_DISK_ERR); + mem_cpy(rbuff, &fp->fs->win[fp->fptr % SS(fp->fs)], rcnt); /* Pick partial sector */ +#else + mem_cpy(rbuff, &fp->buf[fp->fptr % SS(fp->fs)], rcnt); /* Pick partial sector */ +#endif + } + + LEAVE_FF(fp->fs, FR_OK); +} + + + + +#if !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Write File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_write ( + FIL* fp, /* Pointer to the file object */ + const void *buff, /* Pointer to the data to be written */ + UINT btw, /* Number of bytes to write */ + UINT* bw /* Pointer to number of bytes written */ +) +{ + FRESULT res; + DWORD clst, sect; + UINT wcnt, cc; + const BYTE *wbuff = (const BYTE*)buff; + BYTE csect; + + + *bw = 0; /* Clear write byte counter */ + + res = validate(fp); /* Check validity */ + if (res != FR_OK) LEAVE_FF(fp->fs, res); + if (fp->err) /* Check error */ + LEAVE_FF(fp->fs, (FRESULT)fp->err); + if (!(fp->flag & FA_WRITE)) /* Check access mode */ + LEAVE_FF(fp->fs, FR_DENIED); + if (fp->fptr + btw < fp->fptr) btw = 0; /* File size cannot reach 4GB */ + + for ( ; btw; /* Repeat until all data written */ + wbuff += wcnt, fp->fptr += wcnt, *bw += wcnt, btw -= wcnt) { + if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ + csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */ + if (!csect) { /* On the cluster boundary? */ + if (fp->fptr == 0) { /* On the top of the file? */ + clst = fp->sclust; /* Follow from the origin */ + if (clst == 0) /* When no cluster is allocated, */ + clst = create_chain(fp->fs, 0); /* Create a new cluster chain */ + } else { /* Middle or end of the file */ +#if _USE_FASTSEEK + if (fp->cltbl) + clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */ + else +#endif + clst = create_chain(fp->fs, fp->clust); /* Follow or stretch cluster chain on the FAT */ + } + if (clst == 0) break; /* Could not allocate a new cluster (disk full) */ + if (clst == 1) ABORT(fp->fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); + fp->clust = clst; /* Update current cluster */ + if (fp->sclust == 0) fp->sclust = clst; /* Set start cluster if the first write */ + } +#if _FS_TINY + if (fp->fs->winsect == fp->dsect && sync_window(fp->fs)) /* Write-back sector cache */ + ABORT(fp->fs, FR_DISK_ERR); +#else + if (fp->flag & FA__DIRTY) { /* Write-back sector cache */ + if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1)) + ABORT(fp->fs, FR_DISK_ERR); + fp->flag &= ~FA__DIRTY; + } +#endif + sect = clust2sect(fp->fs, fp->clust); /* Get current sector */ + if (!sect) ABORT(fp->fs, FR_INT_ERR); + sect += csect; + cc = btw / SS(fp->fs); /* When remaining bytes >= sector size, */ + if (cc) { /* Write maximum contiguous sectors directly */ + if (csect + cc > fp->fs->csize) /* Clip at cluster boundary */ + cc = fp->fs->csize - csect; + if (disk_write(fp->fs->drv, wbuff, sect, cc)) + ABORT(fp->fs, FR_DISK_ERR); +#if _FS_MINIMIZE <= 2 +#if _FS_TINY + if (fp->fs->winsect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */ + mem_cpy(fp->fs->win, wbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), SS(fp->fs)); + fp->fs->wflag = 0; + } +#else + if (fp->dsect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */ + mem_cpy(fp->buf, wbuff + ((fp->dsect - sect) * SS(fp->fs)), SS(fp->fs)); + fp->flag &= ~FA__DIRTY; + } +#endif +#endif + wcnt = SS(fp->fs) * cc; /* Number of bytes transferred */ + continue; + } +#if _FS_TINY + if (fp->fptr >= fp->fsize) { /* Avoid silly cache filling at growing edge */ + if (sync_window(fp->fs)) ABORT(fp->fs, FR_DISK_ERR); + fp->fs->winsect = sect; + } +#else + if (fp->dsect != sect) { /* Fill sector cache with file data */ + if (fp->fptr < fp->fsize && + disk_read(fp->fs->drv, fp->buf, sect, 1)) + ABORT(fp->fs, FR_DISK_ERR); + } +#endif + fp->dsect = sect; + } + wcnt = SS(fp->fs) - ((UINT)fp->fptr % SS(fp->fs));/* Put partial sector into file I/O buffer */ + if (wcnt > btw) wcnt = btw; +#if _FS_TINY + if (move_window(fp->fs, fp->dsect)) /* Move sector window */ + ABORT(fp->fs, FR_DISK_ERR); + mem_cpy(&fp->fs->win[fp->fptr % SS(fp->fs)], wbuff, wcnt); /* Fit partial sector */ + fp->fs->wflag = 1; +#else + mem_cpy(&fp->buf[fp->fptr % SS(fp->fs)], wbuff, wcnt); /* Fit partial sector */ + fp->flag |= FA__DIRTY; +#endif + } + + if (fp->fptr > fp->fsize) fp->fsize = fp->fptr; /* Update file size if needed */ + fp->flag |= FA__WRITTEN; /* Set file change flag */ + + LEAVE_FF(fp->fs, FR_OK); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Synchronize the File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_sync ( + FIL* fp /* Pointer to the file object */ +) +{ + FRESULT res; + DWORD tm; + BYTE *dir; + + + res = validate(fp); /* Check validity of the object */ + if (res == FR_OK) { + if (fp->flag & FA__WRITTEN) { /* Has the file been written? */ + /* Write-back dirty buffer */ +#if !_FS_TINY + if (fp->flag & FA__DIRTY) { + if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1)) + LEAVE_FF(fp->fs, FR_DISK_ERR); + fp->flag &= ~FA__DIRTY; + } +#endif + /* Update the directory entry */ + res = move_window(fp->fs, fp->dir_sect); + if (res == FR_OK) { + dir = fp->dir_ptr; + dir[DIR_Attr] |= AM_ARC; /* Set archive bit */ + ST_DWORD(dir+DIR_FileSize, fp->fsize); /* Update file size */ + st_clust(dir, fp->sclust); /* Update start cluster */ + tm = get_fattime(); /* Update updated time */ + ST_DWORD(dir+DIR_WrtTime, tm); + ST_WORD(dir+DIR_LstAccDate, 0); + fp->flag &= ~FA__WRITTEN; + fp->fs->wflag = 1; + res = sync_fs(fp->fs); + } + } + } + + LEAVE_FF(fp->fs, res); +} + +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* Close File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_close ( + FIL *fp /* Pointer to the file object to be closed */ +) +{ + FRESULT res; + + +#if !_FS_READONLY + res = f_sync(fp); /* Flush cached data */ + if (res == FR_OK) +#endif + { + res = validate(fp); /* Lock volume */ + if (res == FR_OK) { +#if _FS_REENTRANT + FATFS *fs = fp->fs; +#endif +#if _FS_LOCK + res = dec_lock(fp->lockid); /* Decrement file open counter */ + if (res == FR_OK) +#endif + fp->fs = 0; /* Invalidate file object */ +#if _FS_REENTRANT + unlock_fs(fs, FR_OK); /* Unlock volume */ +#endif + } + } + return res; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Change Current Directory or Current Drive, Get Current Directory */ +/*-----------------------------------------------------------------------*/ + +#if _FS_RPATH >= 1 +#if _VOLUMES >= 2 +FRESULT f_chdrive ( + const TCHAR* path /* Drive number */ +) +{ + int vol; + + + vol = get_ldnumber(&path); + if (vol < 0) return FR_INVALID_DRIVE; + + CurrVol = (BYTE)vol; + + return FR_OK; +} +#endif + + +FRESULT f_chdir ( + const TCHAR* path /* Pointer to the directory path */ +) +{ + FRESULT res; + DIR dj; + DEF_NAMEBUF; + + + /* Get logical drive number */ + res = find_volume(&dj.fs, &path, 0); + if (res == FR_OK) { + INIT_BUF(dj); + res = follow_path(&dj, path); /* Follow the path */ + FREE_BUF(); + if (res == FR_OK) { /* Follow completed */ + if (!dj.dir) { + dj.fs->cdir = dj.sclust; /* Start directory itself */ + } else { + if (dj.dir[DIR_Attr] & AM_DIR) /* Reached to the directory */ + dj.fs->cdir = ld_clust(dj.fs, dj.dir); + else + res = FR_NO_PATH; /* Reached but a file */ + } + } + if (res == FR_NO_FILE) res = FR_NO_PATH; + } + + LEAVE_FF(dj.fs, res); +} + + +#if _FS_RPATH >= 2 +FRESULT f_getcwd ( + TCHAR* buff, /* Pointer to the directory path */ + UINT len /* Size of path */ +) +{ + FRESULT res; + DIR dj; + UINT i, n; + DWORD ccl; + TCHAR *tp; + FILINFO fno; + DEF_NAMEBUF; + + + *buff = 0; + /* Get logical drive number */ + res = find_volume(&dj.fs, (const TCHAR**)&buff, 0); /* Get current volume */ + if (res == FR_OK) { + INIT_BUF(dj); + i = len; /* Bottom of buffer (directory stack base) */ + dj.sclust = dj.fs->cdir; /* Start to follow upper directory from current directory */ + while ((ccl = dj.sclust) != 0) { /* Repeat while current directory is a sub-directory */ + res = dir_sdi(&dj, 1); /* Get parent directory */ + if (res != FR_OK) break; + res = dir_read(&dj, 0); + if (res != FR_OK) break; + dj.sclust = ld_clust(dj.fs, dj.dir); /* Goto parent directory */ + res = dir_sdi(&dj, 0); + if (res != FR_OK) break; + do { /* Find the entry links to the child directory */ + res = dir_read(&dj, 0); + if (res != FR_OK) break; + if (ccl == ld_clust(dj.fs, dj.dir)) break; /* Found the entry */ + res = dir_next(&dj, 0); + } while (res == FR_OK); + if (res == FR_NO_FILE) res = FR_INT_ERR;/* It cannot be 'not found'. */ + if (res != FR_OK) break; +#if _USE_LFN + fno.lfname = buff; + fno.lfsize = i; +#endif + get_fileinfo(&dj, &fno); /* Get the directory name and push it to the buffer */ + tp = fno.fname; +#if _USE_LFN + if (*buff) tp = buff; +#endif + for (n = 0; tp[n]; n++) ; + if (i < n + 3) { + res = FR_NOT_ENOUGH_CORE; break; + } + while (n) buff[--i] = tp[--n]; + buff[--i] = '/'; + } + tp = buff; + if (res == FR_OK) { +#if _VOLUMES >= 2 + *tp++ = '0' + CurrVol; /* Put drive number */ + *tp++ = ':'; +#endif + if (i == len) { /* Root-directory */ + *tp++ = '/'; + } else { /* Sub-directroy */ + do /* Add stacked path str */ + *tp++ = buff[i++]; + while (i < len); + } + } + *tp = 0; + FREE_BUF(); + } + + LEAVE_FF(dj.fs, res); +} +#endif /* _FS_RPATH >= 2 */ +#endif /* _FS_RPATH >= 1 */ + + + +#if _FS_MINIMIZE <= 2 +/*-----------------------------------------------------------------------*/ +/* Seek File R/W Pointer */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_lseek ( + FIL* fp, /* Pointer to the file object */ + DWORD ofs /* File pointer from top of file */ +) +{ + FRESULT res; + + + res = validate(fp); /* Check validity of the object */ + if (res != FR_OK) LEAVE_FF(fp->fs, res); + if (fp->err) /* Check error */ + LEAVE_FF(fp->fs, (FRESULT)fp->err); + +#if _USE_FASTSEEK + if (fp->cltbl) { /* Fast seek */ + DWORD cl, pcl, ncl, tcl, dsc, tlen, ulen, *tbl; + + if (ofs == CREATE_LINKMAP) { /* Create CLMT */ + tbl = fp->cltbl; + tlen = *tbl++; ulen = 2; /* Given table size and required table size */ + cl = fp->sclust; /* Top of the chain */ + if (cl) { + do { + /* Get a fragment */ + tcl = cl; ncl = 0; ulen += 2; /* Top, length and used items */ + do { + pcl = cl; ncl++; + cl = get_fat(fp->fs, cl); + if (cl <= 1) ABORT(fp->fs, FR_INT_ERR); + if (cl == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); + } while (cl == pcl + 1); + if (ulen <= tlen) { /* Store the length and top of the fragment */ + *tbl++ = ncl; *tbl++ = tcl; + } + } while (cl < fp->fs->n_fatent); /* Repeat until end of chain */ + } + *fp->cltbl = ulen; /* Number of items used */ + if (ulen <= tlen) + *tbl = 0; /* Terminate table */ + else + res = FR_NOT_ENOUGH_CORE; /* Given table size is smaller than required */ + + } else { /* Fast seek */ + if (ofs > fp->fsize) /* Clip offset at the file size */ + ofs = fp->fsize; + fp->fptr = ofs; /* Set file pointer */ + if (ofs) { + fp->clust = clmt_clust(fp, ofs - 1); + dsc = clust2sect(fp->fs, fp->clust); + if (!dsc) ABORT(fp->fs, FR_INT_ERR); + dsc += (ofs - 1) / SS(fp->fs) & (fp->fs->csize - 1); + if (fp->fptr % SS(fp->fs) && dsc != fp->dsect) { /* Refill sector cache if needed */ +#if !_FS_TINY +#if !_FS_READONLY + if (fp->flag & FA__DIRTY) { /* Write-back dirty sector cache */ + if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1)) + ABORT(fp->fs, FR_DISK_ERR); + fp->flag &= ~FA__DIRTY; + } +#endif + if (disk_read(fp->fs->drv, fp->buf, dsc, 1)) /* Load current sector */ + ABORT(fp->fs, FR_DISK_ERR); +#endif + fp->dsect = dsc; + } + } + } + } else +#endif + + /* Normal Seek */ + { + DWORD clst, bcs, nsect, ifptr; + + if (ofs > fp->fsize /* In read-only mode, clip offset with the file size */ +#if !_FS_READONLY + && !(fp->flag & FA_WRITE) +#endif + ) ofs = fp->fsize; + + ifptr = fp->fptr; + fp->fptr = nsect = 0; + if (ofs) { + bcs = (DWORD)fp->fs->csize * SS(fp->fs); /* Cluster size (byte) */ + if (ifptr > 0 && + (ofs - 1) / bcs >= (ifptr - 1) / bcs) { /* When seek to same or following cluster, */ + fp->fptr = (ifptr - 1) & ~(bcs - 1); /* start from the current cluster */ + ofs -= fp->fptr; + clst = fp->clust; + } else { /* When seek to back cluster, */ + clst = fp->sclust; /* start from the first cluster */ +#if !_FS_READONLY + if (clst == 0) { /* If no cluster chain, create a new chain */ + clst = create_chain(fp->fs, 0); + if (clst == 1) ABORT(fp->fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); + fp->sclust = clst; + } +#endif + fp->clust = clst; + } + if (clst != 0) { + while (ofs > bcs) { /* Cluster following loop */ +#if !_FS_READONLY + if (fp->flag & FA_WRITE) { /* Check if in write mode or not */ + clst = create_chain(fp->fs, clst); /* Force stretch if in write mode */ + if (clst == 0) { /* When disk gets full, clip file size */ + ofs = bcs; break; + } + } else +#endif + clst = get_fat(fp->fs, clst); /* Follow cluster chain if not in write mode */ + if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); + if (clst <= 1 || clst >= fp->fs->n_fatent) ABORT(fp->fs, FR_INT_ERR); + fp->clust = clst; + fp->fptr += bcs; + ofs -= bcs; + } + fp->fptr += ofs; + if (ofs % SS(fp->fs)) { + nsect = clust2sect(fp->fs, clst); /* Current sector */ + if (!nsect) ABORT(fp->fs, FR_INT_ERR); + nsect += ofs / SS(fp->fs); + } + } + } + if (fp->fptr % SS(fp->fs) && nsect != fp->dsect) { /* Fill sector cache if needed */ +#if !_FS_TINY +#if !_FS_READONLY + if (fp->flag & FA__DIRTY) { /* Write-back dirty sector cache */ + if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1)) + ABORT(fp->fs, FR_DISK_ERR); + fp->flag &= ~FA__DIRTY; + } +#endif + if (disk_read(fp->fs->drv, fp->buf, nsect, 1)) /* Fill sector cache */ + ABORT(fp->fs, FR_DISK_ERR); +#endif + fp->dsect = nsect; + } +#if !_FS_READONLY + if (fp->fptr > fp->fsize) { /* Set file change flag if the file size is extended */ + fp->fsize = fp->fptr; + fp->flag |= FA__WRITTEN; + } +#endif + } + + LEAVE_FF(fp->fs, res); +} + + + +#if _FS_MINIMIZE <= 1 +/*-----------------------------------------------------------------------*/ +/* Create a Directory Object */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_opendir ( + DIR* dp, /* Pointer to directory object to create */ + const TCHAR* path /* Pointer to the directory path */ +) +{ + FRESULT res; + FATFS* fs; + DEF_NAMEBUF; + + + if (!dp) return FR_INVALID_OBJECT; + + /* Get logical drive number */ + res = find_volume(&fs, &path, 0); + if (res == FR_OK) { + dp->fs = fs; + INIT_BUF(*dp); + res = follow_path(dp, path); /* Follow the path to the directory */ + FREE_BUF(); + if (res == FR_OK) { /* Follow completed */ + if (dp->dir) { /* It is not the origin directory itself */ + if (dp->dir[DIR_Attr] & AM_DIR) /* The object is a sub directory */ + dp->sclust = ld_clust(fs, dp->dir); + else /* The object is a file */ + res = FR_NO_PATH; + } + if (res == FR_OK) { + dp->id = fs->id; + res = dir_sdi(dp, 0); /* Rewind directory */ +#if _FS_LOCK + if (res == FR_OK) { + if (dp->sclust) { + dp->lockid = inc_lock(dp, 0); /* Lock the sub directory */ + if (!dp->lockid) + res = FR_TOO_MANY_OPEN_FILES; + } else { + dp->lockid = 0; /* Root directory need not to be locked */ + } + } +#endif + } + } + if (res == FR_NO_FILE) res = FR_NO_PATH; + } + if (res != FR_OK) dp->fs = 0; /* Invalidate the directory object if function faild */ + + LEAVE_FF(fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Close Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_closedir ( + DIR *dp /* Pointer to the directory object to be closed */ +) +{ + FRESULT res; + + + res = validate(dp); + if (res == FR_OK) { +#if _FS_REENTRANT + FATFS *fs = dp->fs; +#endif +#if _FS_LOCK + if (dp->lockid) /* Decrement sub-directory open counter */ + res = dec_lock(dp->lockid); + if (res == FR_OK) +#endif + dp->fs = 0; /* Invalidate directory object */ +#if _FS_REENTRANT + unlock_fs(fs, FR_OK); /* Unlock volume */ +#endif + } + return res; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Read Directory Entries in Sequence */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_readdir ( + DIR* dp, /* Pointer to the open directory object */ + FILINFO* fno /* Pointer to file information to return */ +) +{ + FRESULT res; + DEF_NAMEBUF; + + + res = validate(dp); /* Check validity of the object */ + if (res == FR_OK) { + if (!fno) { + res = dir_sdi(dp, 0); /* Rewind the directory object */ + } else { + INIT_BUF(*dp); + res = dir_read(dp, 0); /* Read an item */ + if (res == FR_NO_FILE) { /* Reached end of directory */ + dp->sect = 0; + res = FR_OK; + } + if (res == FR_OK) { /* A valid entry is found */ + get_fileinfo(dp, fno); /* Get the object information */ + res = dir_next(dp, 0); /* Increment index for next */ + if (res == FR_NO_FILE) { + dp->sect = 0; + res = FR_OK; + } + } + FREE_BUF(); + } + } + + LEAVE_FF(dp->fs, res); +} + + + +#if _FS_MINIMIZE == 0 +/*-----------------------------------------------------------------------*/ +/* Get File Status */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_stat ( + const TCHAR* path, /* Pointer to the file path */ + FILINFO* fno /* Pointer to file information to return */ +) +{ + FRESULT res; + DIR dj; + DEF_NAMEBUF; + + + /* Get logical drive number */ + res = find_volume(&dj.fs, &path, 0); + if (res == FR_OK) { + INIT_BUF(dj); + res = follow_path(&dj, path); /* Follow the file path */ + if (res == FR_OK) { /* Follow completed */ + if (dj.dir) { /* Found an object */ + if (fno) get_fileinfo(&dj, fno); + } else { /* It is root directory */ + res = FR_INVALID_NAME; + } + } + FREE_BUF(); + } + + LEAVE_FF(dj.fs, res); +} + + + +#if !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Get Number of Free Clusters */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_getfree ( + const TCHAR* path, /* Path name of the logical drive number */ + DWORD* nclst, /* Pointer to a variable to return number of free clusters */ + FATFS** fatfs /* Pointer to return pointer to corresponding file system object */ +) +{ + FRESULT res; + FATFS *fs; + DWORD n, clst, sect, stat; + UINT i; + BYTE fat, *p; + + + /* Get logical drive number */ + res = find_volume(fatfs, &path, 0); + fs = *fatfs; + if (res == FR_OK) { + /* If free_clust is valid, return it without full cluster scan */ + if (fs->free_clust <= fs->n_fatent - 2) { + *nclst = fs->free_clust; + } else { + /* Get number of free clusters */ + fat = fs->fs_type; + n = 0; + if (fat == FS_FAT12) { + clst = 2; + do { + stat = get_fat(fs, clst); + if (stat == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } + if (stat == 1) { res = FR_INT_ERR; break; } + if (stat == 0) n++; + } while (++clst < fs->n_fatent); + } else { + clst = fs->n_fatent; + sect = fs->fatbase; + i = 0; p = 0; + do { + if (!i) { + res = move_window(fs, sect++); + if (res != FR_OK) break; + p = fs->win; + i = SS(fs); + } + if (fat == FS_FAT16) { + if (LD_WORD(p) == 0) n++; + p += 2; i -= 2; + } else { + if ((LD_DWORD(p) & 0x0FFFFFFF) == 0) n++; + p += 4; i -= 4; + } + } while (--clst); + } + fs->free_clust = n; + fs->fsi_flag |= 1; + *nclst = n; + } + } + LEAVE_FF(fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Truncate File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_truncate ( + FIL* fp /* Pointer to the file object */ +) +{ + FRESULT res; + DWORD ncl; + + + res = validate(fp); /* Check validity of the object */ + if (res == FR_OK) { + if (fp->err) { /* Check error */ + res = (FRESULT)fp->err; + } else { + if (!(fp->flag & FA_WRITE)) /* Check access mode */ + res = FR_DENIED; + } + } + if (res == FR_OK) { + if (fp->fsize > fp->fptr) { + fp->fsize = fp->fptr; /* Set file size to current R/W point */ + fp->flag |= FA__WRITTEN; + if (fp->fptr == 0) { /* When set file size to zero, remove entire cluster chain */ + res = remove_chain(fp->fs, fp->sclust); + fp->sclust = 0; + } else { /* When truncate a part of the file, remove remaining clusters */ + ncl = get_fat(fp->fs, fp->clust); + res = FR_OK; + if (ncl == 0xFFFFFFFF) res = FR_DISK_ERR; + if (ncl == 1) res = FR_INT_ERR; + if (res == FR_OK && ncl < fp->fs->n_fatent) { + res = put_fat(fp->fs, fp->clust, 0x0FFFFFFF); + if (res == FR_OK) res = remove_chain(fp->fs, ncl); + } + } +#if !_FS_TINY + if (res == FR_OK && (fp->flag & FA__DIRTY)) { + if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1)) + res = FR_DISK_ERR; + else + fp->flag &= ~FA__DIRTY; + } +#endif + } + if (res != FR_OK) fp->err = (FRESULT)res; + } + + LEAVE_FF(fp->fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Delete a File or Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_unlink ( + const TCHAR* path /* Pointer to the file or directory path */ +) +{ + FRESULT res; + DIR dj, sdj; + BYTE *dir; + DWORD dclst; + DEF_NAMEBUF; + + + /* Get logical drive number */ + res = find_volume(&dj.fs, &path, 1); + if (res == FR_OK) { + INIT_BUF(dj); + res = follow_path(&dj, path); /* Follow the file path */ + if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT)) + res = FR_INVALID_NAME; /* Cannot remove dot entry */ +#if _FS_LOCK + if (res == FR_OK) res = chk_lock(&dj, 2); /* Cannot remove open file */ +#endif + if (res == FR_OK) { /* The object is accessible */ + dir = dj.dir; + if (!dir) { + res = FR_INVALID_NAME; /* Cannot remove the start directory */ + } else { + if (dir[DIR_Attr] & AM_RDO) + res = FR_DENIED; /* Cannot remove R/O object */ + } + dclst = ld_clust(dj.fs, dir); + if (res == FR_OK && (dir[DIR_Attr] & AM_DIR)) { /* Is it a sub-dir? */ + if (dclst < 2) { + res = FR_INT_ERR; + } else { + mem_cpy(&sdj, &dj, sizeof (DIR)); /* Check if the sub-directory is empty or not */ + sdj.sclust = dclst; + res = dir_sdi(&sdj, 2); /* Exclude dot entries */ + if (res == FR_OK) { + res = dir_read(&sdj, 0); /* Read an item */ + if (res == FR_OK /* Not empty directory */ +#if _FS_RPATH + || dclst == dj.fs->cdir /* Current directory */ +#endif + ) res = FR_DENIED; + if (res == FR_NO_FILE) res = FR_OK; /* Empty */ + } + } + } + if (res == FR_OK) { + res = dir_remove(&dj); /* Remove the directory entry */ + if (res == FR_OK) { + if (dclst) /* Remove the cluster chain if exist */ + res = remove_chain(dj.fs, dclst); + if (res == FR_OK) res = sync_fs(dj.fs); + } + } + } + FREE_BUF(); + } + + LEAVE_FF(dj.fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Create a Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_mkdir ( + const TCHAR* path /* Pointer to the directory path */ +) +{ + FRESULT res; + DIR dj; + BYTE *dir, n; + DWORD dsc, dcl, pcl, tm = get_fattime(); + DEF_NAMEBUF; + + + /* Get logical drive number */ + res = find_volume(&dj.fs, &path, 1); + if (res == FR_OK) { + INIT_BUF(dj); + res = follow_path(&dj, path); /* Follow the file path */ + if (res == FR_OK) res = FR_EXIST; /* Any object with same name is already existing */ + if (_FS_RPATH && res == FR_NO_FILE && (dj.fn[NS] & NS_DOT)) + res = FR_INVALID_NAME; + if (res == FR_NO_FILE) { /* Can create a new directory */ + dcl = create_chain(dj.fs, 0); /* Allocate a cluster for the new directory table */ + res = FR_OK; + if (dcl == 0) res = FR_DENIED; /* No space to allocate a new cluster */ + if (dcl == 1) res = FR_INT_ERR; + if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR; + if (res == FR_OK) /* Flush FAT */ + res = sync_window(dj.fs); + if (res == FR_OK) { /* Initialize the new directory table */ + dsc = clust2sect(dj.fs, dcl); + dir = dj.fs->win; + mem_set(dir, 0, SS(dj.fs)); + mem_set(dir+DIR_Name, ' ', 11); /* Create "." entry */ + dir[DIR_Name] = '.'; + dir[DIR_Attr] = AM_DIR; + ST_DWORD(dir+DIR_WrtTime, tm); + st_clust(dir, dcl); + mem_cpy(dir+SZ_DIR, dir, SZ_DIR); /* Create ".." entry */ + dir[SZ_DIR+1] = '.'; pcl = dj.sclust; + if (dj.fs->fs_type == FS_FAT32 && pcl == dj.fs->dirbase) + pcl = 0; + st_clust(dir+SZ_DIR, pcl); + for (n = dj.fs->csize; n; n--) { /* Write dot entries and clear following sectors */ + dj.fs->winsect = dsc++; + dj.fs->wflag = 1; + res = sync_window(dj.fs); + if (res != FR_OK) break; + mem_set(dir, 0, SS(dj.fs)); + } + } + if (res == FR_OK) res = dir_register(&dj); /* Register the object to the directoy */ + if (res != FR_OK) { + remove_chain(dj.fs, dcl); /* Could not register, remove cluster chain */ + } else { + dir = dj.dir; + dir[DIR_Attr] = AM_DIR; /* Attribute */ + ST_DWORD(dir+DIR_WrtTime, tm); /* Created time */ + st_clust(dir, dcl); /* Table start cluster */ + dj.fs->wflag = 1; + res = sync_fs(dj.fs); + } + } + FREE_BUF(); + } + + LEAVE_FF(dj.fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Change Attribute */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_chmod ( + const TCHAR* path, /* Pointer to the file path */ + BYTE value, /* Attribute bits */ + BYTE mask /* Attribute mask to change */ +) +{ + FRESULT res; + DIR dj; + BYTE *dir; + DEF_NAMEBUF; + + + /* Get logical drive number */ + res = find_volume(&dj.fs, &path, 1); + if (res == FR_OK) { + INIT_BUF(dj); + res = follow_path(&dj, path); /* Follow the file path */ + FREE_BUF(); + if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT)) + res = FR_INVALID_NAME; + if (res == FR_OK) { + dir = dj.dir; + if (!dir) { /* Is it a root directory? */ + res = FR_INVALID_NAME; + } else { /* File or sub directory */ + mask &= AM_RDO|AM_HID|AM_SYS|AM_ARC; /* Valid attribute mask */ + dir[DIR_Attr] = (value & mask) | (dir[DIR_Attr] & (BYTE)~mask); /* Apply attribute change */ + dj.fs->wflag = 1; + res = sync_fs(dj.fs); + } + } + } + + LEAVE_FF(dj.fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Change Timestamp */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_utime ( + const TCHAR* path, /* Pointer to the file/directory name */ + const FILINFO* fno /* Pointer to the time stamp to be set */ +) +{ + FRESULT res; + DIR dj; + BYTE *dir; + DEF_NAMEBUF; + + + /* Get logical drive number */ + res = find_volume(&dj.fs, &path, 1); + if (res == FR_OK) { + INIT_BUF(dj); + res = follow_path(&dj, path); /* Follow the file path */ + FREE_BUF(); + if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT)) + res = FR_INVALID_NAME; + if (res == FR_OK) { + dir = dj.dir; + if (!dir) { /* Root directory */ + res = FR_INVALID_NAME; + } else { /* File or sub-directory */ + ST_WORD(dir+DIR_WrtTime, fno->ftime); + ST_WORD(dir+DIR_WrtDate, fno->fdate); + dj.fs->wflag = 1; + res = sync_fs(dj.fs); + } + } + } + + LEAVE_FF(dj.fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Rename File/Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_rename ( + const TCHAR* path_old, /* Pointer to the object to be renamed */ + const TCHAR* path_new /* Pointer to the new name */ +) +{ + FRESULT res; + DIR djo, djn; + BYTE buf[21], *dir; + DWORD dw; + DEF_NAMEBUF; + + + /* Get logical drive number of the source object */ + res = find_volume(&djo.fs, &path_old, 1); + if (res == FR_OK) { + djn.fs = djo.fs; + INIT_BUF(djo); + res = follow_path(&djo, path_old); /* Check old object */ + if (_FS_RPATH && res == FR_OK && (djo.fn[NS] & NS_DOT)) + res = FR_INVALID_NAME; +#if _FS_LOCK + if (res == FR_OK) res = chk_lock(&djo, 2); +#endif + if (res == FR_OK) { /* Old object is found */ + if (!djo.dir) { /* Is root dir? */ + res = FR_NO_FILE; + } else { + mem_cpy(buf, djo.dir+DIR_Attr, 21); /* Save the object information except name */ + mem_cpy(&djn, &djo, sizeof (DIR)); /* Duplicate the directory object */ + if (get_ldnumber(&path_new) >= 0) /* Snip drive number off and ignore it */ + res = follow_path(&djn, path_new); /* and check if new object is exist */ + else + res = FR_INVALID_DRIVE; + if (res == FR_OK) res = FR_EXIST; /* The new object name is already existing */ + if (res == FR_NO_FILE) { /* Is it a valid path and no name collision? */ +/* Start critical section that any interruption can cause a cross-link */ + res = dir_register(&djn); /* Register the new entry */ + if (res == FR_OK) { + dir = djn.dir; /* Copy object information except name */ + mem_cpy(dir+13, buf+2, 19); + dir[DIR_Attr] = buf[0] | AM_ARC; + djo.fs->wflag = 1; + if (djo.sclust != djn.sclust && (dir[DIR_Attr] & AM_DIR)) { /* Update .. entry in the directory if needed */ + dw = clust2sect(djo.fs, ld_clust(djo.fs, dir)); + if (!dw) { + res = FR_INT_ERR; + } else { + res = move_window(djo.fs, dw); + dir = djo.fs->win+SZ_DIR; /* .. entry */ + if (res == FR_OK && dir[1] == '.') { + dw = (djo.fs->fs_type == FS_FAT32 && djn.sclust == djo.fs->dirbase) ? 0 : djn.sclust; + st_clust(dir, dw); + djo.fs->wflag = 1; + } + } + } + if (res == FR_OK) { + res = dir_remove(&djo); /* Remove old entry */ + if (res == FR_OK) + res = sync_fs(djo.fs); + } + } +/* End critical section */ + } + } + } + FREE_BUF(); + } + + LEAVE_FF(djo.fs, res); +} + +#endif /* !_FS_READONLY */ +#endif /* _FS_MINIMIZE == 0 */ +#endif /* _FS_MINIMIZE <= 1 */ +#endif /* _FS_MINIMIZE <= 2 */ + + + +#if _USE_LABEL +/*-----------------------------------------------------------------------*/ +/* Get volume label */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_getlabel ( + const TCHAR* path, /* Path name of the logical drive number */ + TCHAR* label, /* Pointer to a buffer to return the volume label */ + DWORD* vsn /* Pointer to a variable to return the volume serial number */ +) +{ + FRESULT res; + DIR dj; + UINT i, j; + + + /* Get logical drive number */ + res = find_volume(&dj.fs, &path, 0); + + /* Get volume label */ + if (res == FR_OK && label) { + dj.sclust = 0; /* Open root directory */ + res = dir_sdi(&dj, 0); + if (res == FR_OK) { + res = dir_read(&dj, 1); /* Get an entry with AM_VOL */ + if (res == FR_OK) { /* A volume label is exist */ +#if _USE_LFN && _LFN_UNICODE + WCHAR w; + i = j = 0; + do { + w = (i < 11) ? dj.dir[i++] : ' '; + if (IsDBCS1(w) && i < 11 && IsDBCS2(dj.dir[i])) + w = w << 8 | dj.dir[i++]; + label[j++] = ff_convert(w, 1); /* OEM -> Unicode */ + } while (j < 11); +#else + mem_cpy(label, dj.dir, 11); +#endif + j = 11; + do { + label[j] = 0; + if (!j) break; + } while (label[--j] == ' '); + } + if (res == FR_NO_FILE) { /* No label, return nul string */ + label[0] = 0; + res = FR_OK; + } + } + } + + /* Get volume serial number */ + if (res == FR_OK && vsn) { + res = move_window(dj.fs, dj.fs->volbase); + if (res == FR_OK) { + i = dj.fs->fs_type == FS_FAT32 ? BS_VolID32 : BS_VolID; + *vsn = LD_DWORD(&dj.fs->win[i]); + } + } + + LEAVE_FF(dj.fs, res); +} + + + +#if !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Set volume label */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_setlabel ( + const TCHAR* label /* Pointer to the volume label to set */ +) +{ + FRESULT res; + DIR dj; + BYTE vn[11]; + UINT i, j, sl; + WCHAR w; + DWORD tm; + + + /* Get logical drive number */ + res = find_volume(&dj.fs, &label, 1); + if (res) LEAVE_FF(dj.fs, res); + + /* Create a volume label in directory form */ + vn[0] = 0; + for (sl = 0; label[sl]; sl++) ; /* Get name length */ + for ( ; sl && label[sl-1] == ' '; sl--) ; /* Remove trailing spaces */ + if (sl) { /* Create volume label in directory form */ + i = j = 0; + do { +#if _USE_LFN && _LFN_UNICODE + w = ff_convert(ff_wtoupper(label[i++]), 0); +#else + w = (BYTE)label[i++]; + if (IsDBCS1(w)) + w = (j < 10 && i < sl && IsDBCS2(label[i])) ? w << 8 | (BYTE)label[i++] : 0; +#if _USE_LFN + w = ff_convert(ff_wtoupper(ff_convert(w, 1)), 0); +#else + if (IsLower(w)) w -= 0x20; /* To upper ASCII characters */ +#ifdef _EXCVT + if (w >= 0x80) w = ExCvt[w - 0x80]; /* To upper extended characters (SBCS cfg) */ +#else + if (!_DF1S && w >= 0x80) w = 0; /* Reject extended characters (ASCII cfg) */ +#endif +#endif +#endif + if (!w || chk_chr("\"*+,.:;<=>\?[]|\x7F", w) || j >= (UINT)((w >= 0x100) ? 10 : 11)) /* Reject invalid characters for volume label */ + LEAVE_FF(dj.fs, FR_INVALID_NAME); + if (w >= 0x100) vn[j++] = (BYTE)(w >> 8); + vn[j++] = (BYTE)w; + } while (i < sl); + while (j < 11) vn[j++] = ' '; + } + + /* Set volume label */ + dj.sclust = 0; /* Open root directory */ + res = dir_sdi(&dj, 0); + if (res == FR_OK) { + res = dir_read(&dj, 1); /* Get an entry with AM_VOL */ + if (res == FR_OK) { /* A volume label is found */ + if (vn[0]) { + mem_cpy(dj.dir, vn, 11); /* Change the volume label name */ + tm = get_fattime(); + ST_DWORD(dj.dir+DIR_WrtTime, tm); + } else { + dj.dir[0] = DDE; /* Remove the volume label */ + } + dj.fs->wflag = 1; + res = sync_fs(dj.fs); + } else { /* No volume label is found or error */ + if (res == FR_NO_FILE) { + res = FR_OK; + if (vn[0]) { /* Create volume label as new */ + res = dir_alloc(&dj, 1); /* Allocate an entry for volume label */ + if (res == FR_OK) { + mem_set(dj.dir, 0, SZ_DIR); /* Set volume label */ + mem_cpy(dj.dir, vn, 11); + dj.dir[DIR_Attr] = AM_VOL; + tm = get_fattime(); + ST_DWORD(dj.dir+DIR_WrtTime, tm); + dj.fs->wflag = 1; + res = sync_fs(dj.fs); + } + } + } + } + } + + LEAVE_FF(dj.fs, res); +} + +#endif /* !_FS_READONLY */ +#endif /* _USE_LABEL */ + + + +/*-----------------------------------------------------------------------*/ +/* Forward data to the stream directly (available on only tiny cfg) */ +/*-----------------------------------------------------------------------*/ +#if _USE_FORWARD && _FS_TINY + +FRESULT f_forward ( + FIL* fp, /* Pointer to the file object */ + UINT (*func)(const BYTE*,UINT), /* Pointer to the streaming function */ + UINT btf, /* Number of bytes to forward */ + UINT* bf /* Pointer to number of bytes forwarded */ +) +{ + FRESULT res; + DWORD remain, clst, sect; + UINT rcnt; + BYTE csect; + + + *bf = 0; /* Clear transfer byte counter */ + + res = validate(fp); /* Check validity of the object */ + if (res != FR_OK) LEAVE_FF(fp->fs, res); + if (fp->err) /* Check error */ + LEAVE_FF(fp->fs, (FRESULT)fp->err); + if (!(fp->flag & FA_READ)) /* Check access mode */ + LEAVE_FF(fp->fs, FR_DENIED); + + remain = fp->fsize - fp->fptr; + if (btf > remain) btf = (UINT)remain; /* Truncate btf by remaining bytes */ + + for ( ; btf && (*func)(0, 0); /* Repeat until all data transferred or stream becomes busy */ + fp->fptr += rcnt, *bf += rcnt, btf -= rcnt) { + csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */ + if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ + if (!csect) { /* On the cluster boundary? */ + clst = (fp->fptr == 0) ? /* On the top of the file? */ + fp->sclust : get_fat(fp->fs, fp->clust); + if (clst <= 1) ABORT(fp->fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); + fp->clust = clst; /* Update current cluster */ + } + } + sect = clust2sect(fp->fs, fp->clust); /* Get current data sector */ + if (!sect) ABORT(fp->fs, FR_INT_ERR); + sect += csect; + if (move_window(fp->fs, sect)) /* Move sector window */ + ABORT(fp->fs, FR_DISK_ERR); + fp->dsect = sect; + rcnt = SS(fp->fs) - (WORD)(fp->fptr % SS(fp->fs)); /* Forward data from sector window */ + if (rcnt > btf) rcnt = btf; + rcnt = (*func)(&fp->fs->win[(WORD)fp->fptr % SS(fp->fs)], rcnt); + if (!rcnt) ABORT(fp->fs, FR_INT_ERR); + } + + LEAVE_FF(fp->fs, FR_OK); +} +#endif /* _USE_FORWARD */ + + + +#if _USE_MKFS && !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Create File System on the Drive */ +/*-----------------------------------------------------------------------*/ +#define N_ROOTDIR 512 /* Number of root directory entries for FAT12/16 */ +#define N_FATS 1 /* Number of FAT copies (1 or 2) */ + + +FRESULT f_mkfs ( + const TCHAR* path, /* Logical drive number */ + BYTE sfd, /* Partitioning rule 0:FDISK, 1:SFD */ + UINT au /* Allocation unit [bytes] */ +) +{ + static const WORD vst[] = { 1024, 512, 256, 128, 64, 32, 16, 8, 4, 2, 0}; + static const WORD cst[] = {32768, 16384, 8192, 4096, 2048, 16384, 8192, 4096, 2048, 1024, 512}; + int vol; + BYTE fmt, md, sys, *tbl, pdrv, part; + DWORD n_clst, vs, n, wsect; + UINT i; + DWORD b_vol, b_fat, b_dir, b_data; /* LBA */ + DWORD n_vol, n_rsv, n_fat, n_dir; /* Size */ + FATFS *fs; + DSTATUS stat; + + + /* Check mounted drive and clear work area */ + vol = get_ldnumber(&path); + if (vol < 0) return FR_INVALID_DRIVE; + if (sfd > 1) return FR_INVALID_PARAMETER; + if (au & (au - 1)) return FR_INVALID_PARAMETER; + fs = FatFs[vol]; + if (!fs) return FR_NOT_ENABLED; + fs->fs_type = 0; + pdrv = LD2PD(vol); /* Physical drive */ + part = LD2PT(vol); /* Partition (0:auto detect, 1-4:get from partition table)*/ + + /* Get disk statics */ + stat = disk_initialize(pdrv); + if (stat & STA_NOINIT) return FR_NOT_READY; + if (stat & STA_PROTECT) return FR_WRITE_PROTECTED; +#if _MAX_SS != _MIN_SS /* Get disk sector size */ + if (disk_ioctl(pdrv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK || SS(fs) > _MAX_SS || SS(fs) < _MIN_SS) + return FR_DISK_ERR; +#endif + if (_MULTI_PARTITION && part) { + /* Get partition information from partition table in the MBR */ + if (disk_read(pdrv, fs->win, 0, 1)) return FR_DISK_ERR; + if (LD_WORD(fs->win+BS_55AA) != 0xAA55) return FR_MKFS_ABORTED; + tbl = &fs->win[MBR_Table + (part - 1) * SZ_PTE]; + if (!tbl[4]) return FR_MKFS_ABORTED; /* No partition? */ + b_vol = LD_DWORD(tbl+8); /* Volume start sector */ + n_vol = LD_DWORD(tbl+12); /* Volume size */ + } else { + /* Create a partition in this function */ + if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &n_vol) != RES_OK || n_vol < 128) + return FR_DISK_ERR; + b_vol = (sfd) ? 0 : 63; /* Volume start sector */ + n_vol -= b_vol; /* Volume size */ + } + + if (!au) { /* AU auto selection */ + vs = n_vol / (2000 / (SS(fs) / 512)); + for (i = 0; vs < vst[i]; i++) ; + au = cst[i]; + } + au /= SS(fs); /* Number of sectors per cluster */ + if (au == 0) au = 1; + if (au > 128) au = 128; + + /* Pre-compute number of clusters and FAT sub-type */ + n_clst = n_vol / au; + fmt = FS_FAT12; + if (n_clst >= MIN_FAT16) fmt = FS_FAT16; + if (n_clst >= MIN_FAT32) fmt = FS_FAT32; + + /* Determine offset and size of FAT structure */ + if (fmt == FS_FAT32) { + n_fat = ((n_clst * 4) + 8 + SS(fs) - 1) / SS(fs); + n_rsv = 32; + n_dir = 0; + } else { + n_fat = (fmt == FS_FAT12) ? (n_clst * 3 + 1) / 2 + 3 : (n_clst * 2) + 4; + n_fat = (n_fat + SS(fs) - 1) / SS(fs); + n_rsv = 1; + n_dir = (DWORD)N_ROOTDIR * SZ_DIR / SS(fs); + } + b_fat = b_vol + n_rsv; /* FAT area start sector */ + b_dir = b_fat + n_fat * N_FATS; /* Directory area start sector */ + b_data = b_dir + n_dir; /* Data area start sector */ + if (n_vol < b_data + au - b_vol) return FR_MKFS_ABORTED; /* Too small volume */ + + /* Align data start sector to erase block boundary (for flash memory media) */ + if (disk_ioctl(pdrv, GET_BLOCK_SIZE, &n) != RES_OK || !n || n > 32768) n = 1; + n = (b_data + n - 1) & ~(n - 1); /* Next nearest erase block from current data start */ + n = (n - b_data) / N_FATS; + if (fmt == FS_FAT32) { /* FAT32: Move FAT offset */ + n_rsv += n; + b_fat += n; + } else { /* FAT12/16: Expand FAT size */ + n_fat += n; + } + + /* Determine number of clusters and final check of validity of the FAT sub-type */ + n_clst = (n_vol - n_rsv - n_fat * N_FATS - n_dir) / au; + if ( (fmt == FS_FAT16 && n_clst < MIN_FAT16) + || (fmt == FS_FAT32 && n_clst < MIN_FAT32)) + return FR_MKFS_ABORTED; + + /* Determine system ID in the partition table */ + if (fmt == FS_FAT32) { + sys = 0x0C; /* FAT32X */ + } else { + if (fmt == FS_FAT12 && n_vol < 0x10000) { + sys = 0x01; /* FAT12(<65536) */ + } else { + sys = (n_vol < 0x10000) ? 0x04 : 0x06; /* FAT16(<65536) : FAT12/16(>=65536) */ + } + } + + if (_MULTI_PARTITION && part) { + /* Update system ID in the partition table */ + tbl = &fs->win[MBR_Table + (part - 1) * SZ_PTE]; + tbl[4] = sys; + if (disk_write(pdrv, fs->win, 0, 1)) /* Write it to teh MBR */ + return FR_DISK_ERR; + md = 0xF8; + } else { + if (sfd) { /* No partition table (SFD) */ + md = 0xF0; + } else { /* Create partition table (FDISK) */ + mem_set(fs->win, 0, SS(fs)); + tbl = fs->win+MBR_Table; /* Create partition table for single partition in the drive */ + tbl[1] = 1; /* Partition start head */ + tbl[2] = 1; /* Partition start sector */ + tbl[3] = 0; /* Partition start cylinder */ + tbl[4] = sys; /* System type */ + tbl[5] = 254; /* Partition end head */ + n = (b_vol + n_vol) / 63 / 255; + tbl[6] = (BYTE)(n >> 2 | 63); /* Partition end sector */ + tbl[7] = (BYTE)n; /* End cylinder */ + ST_DWORD(tbl+8, 63); /* Partition start in LBA */ + ST_DWORD(tbl+12, n_vol); /* Partition size in LBA */ + ST_WORD(fs->win+BS_55AA, 0xAA55); /* MBR signature */ + if (disk_write(pdrv, fs->win, 0, 1)) /* Write it to the MBR */ + return FR_DISK_ERR; + md = 0xF8; + } + } + + /* Create BPB in the VBR */ + tbl = fs->win; /* Clear sector */ + mem_set(tbl, 0, SS(fs)); + mem_cpy(tbl, "\xEB\xFE\x90" "MSDOS5.0", 11);/* Boot jump code, OEM name */ + i = SS(fs); /* Sector size */ + ST_WORD(tbl+BPB_BytsPerSec, i); + tbl[BPB_SecPerClus] = (BYTE)au; /* Sectors per cluster */ + ST_WORD(tbl+BPB_RsvdSecCnt, n_rsv); /* Reserved sectors */ + tbl[BPB_NumFATs] = N_FATS; /* Number of FATs */ + i = (fmt == FS_FAT32) ? 0 : N_ROOTDIR; /* Number of root directory entries */ + ST_WORD(tbl+BPB_RootEntCnt, i); + if (n_vol < 0x10000) { /* Number of total sectors */ + ST_WORD(tbl+BPB_TotSec16, n_vol); + } else { + ST_DWORD(tbl+BPB_TotSec32, n_vol); + } + tbl[BPB_Media] = md; /* Media descriptor */ + ST_WORD(tbl+BPB_SecPerTrk, 63); /* Number of sectors per track */ + ST_WORD(tbl+BPB_NumHeads, 255); /* Number of heads */ + ST_DWORD(tbl+BPB_HiddSec, b_vol); /* Hidden sectors */ + n = get_fattime(); /* Use current time as VSN */ + if (fmt == FS_FAT32) { + ST_DWORD(tbl+BS_VolID32, n); /* VSN */ + ST_DWORD(tbl+BPB_FATSz32, n_fat); /* Number of sectors per FAT */ + ST_DWORD(tbl+BPB_RootClus, 2); /* Root directory start cluster (2) */ + ST_WORD(tbl+BPB_FSInfo, 1); /* FSINFO record offset (VBR+1) */ + ST_WORD(tbl+BPB_BkBootSec, 6); /* Backup boot record offset (VBR+6) */ + tbl[BS_DrvNum32] = 0x80; /* Drive number */ + tbl[BS_BootSig32] = 0x29; /* Extended boot signature */ + mem_cpy(tbl+BS_VolLab32, "NO NAME " "FAT32 ", 19); /* Volume label, FAT signature */ + } else { + ST_DWORD(tbl+BS_VolID, n); /* VSN */ + ST_WORD(tbl+BPB_FATSz16, n_fat); /* Number of sectors per FAT */ + tbl[BS_DrvNum] = 0x80; /* Drive number */ + tbl[BS_BootSig] = 0x29; /* Extended boot signature */ + mem_cpy(tbl+BS_VolLab, "NO NAME " "FAT ", 19); /* Volume label, FAT signature */ + } + ST_WORD(tbl+BS_55AA, 0xAA55); /* Signature (Offset is fixed here regardless of sector size) */ + if (disk_write(pdrv, tbl, b_vol, 1)) /* Write it to the VBR sector */ + return FR_DISK_ERR; + if (fmt == FS_FAT32) /* Write backup VBR if needed (VBR+6) */ + disk_write(pdrv, tbl, b_vol + 6, 1); + + /* Initialize FAT area */ + wsect = b_fat; + for (i = 0; i < N_FATS; i++) { /* Initialize each FAT copy */ + mem_set(tbl, 0, SS(fs)); /* 1st sector of the FAT */ + n = md; /* Media descriptor byte */ + if (fmt != FS_FAT32) { + n |= (fmt == FS_FAT12) ? 0x00FFFF00 : 0xFFFFFF00; + ST_DWORD(tbl+0, n); /* Reserve cluster #0-1 (FAT12/16) */ + } else { + n |= 0xFFFFFF00; + ST_DWORD(tbl+0, n); /* Reserve cluster #0-1 (FAT32) */ + ST_DWORD(tbl+4, 0xFFFFFFFF); + ST_DWORD(tbl+8, 0x0FFFFFFF); /* Reserve cluster #2 for root directory */ + } + if (disk_write(pdrv, tbl, wsect++, 1)) + return FR_DISK_ERR; + mem_set(tbl, 0, SS(fs)); /* Fill following FAT entries with zero */ + for (n = 1; n < n_fat; n++) { /* This loop may take a time on FAT32 volume due to many single sector writes */ + if (disk_write(pdrv, tbl, wsect++, 1)) + return FR_DISK_ERR; + } + } + + /* Initialize root directory */ + i = (fmt == FS_FAT32) ? au : (UINT)n_dir; + do { + if (disk_write(pdrv, tbl, wsect++, 1)) + return FR_DISK_ERR; + } while (--i); + +#if _USE_ERASE /* Erase data area if needed */ + { + DWORD eb[2]; + + eb[0] = wsect; eb[1] = wsect + (n_clst - ((fmt == FS_FAT32) ? 1 : 0)) * au - 1; + disk_ioctl(pdrv, CTRL_ERASE_SECTOR, eb); + } +#endif + + /* Create FSINFO if needed */ + if (fmt == FS_FAT32) { + ST_DWORD(tbl+FSI_LeadSig, 0x41615252); + ST_DWORD(tbl+FSI_StrucSig, 0x61417272); + ST_DWORD(tbl+FSI_Free_Count, n_clst - 1); /* Number of free clusters */ + ST_DWORD(tbl+FSI_Nxt_Free, 2); /* Last allocated cluster# */ + ST_WORD(tbl+BS_55AA, 0xAA55); + disk_write(pdrv, tbl, b_vol + 1, 1); /* Write original (VBR+1) */ + disk_write(pdrv, tbl, b_vol + 7, 1); /* Write backup (VBR+7) */ + } + + return (disk_ioctl(pdrv, CTRL_SYNC, 0) == RES_OK) ? FR_OK : FR_DISK_ERR; +} + + + +#if _MULTI_PARTITION +/*-----------------------------------------------------------------------*/ +/* Divide Physical Drive */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_fdisk ( + BYTE pdrv, /* Physical drive number */ + const DWORD szt[], /* Pointer to the size table for each partitions */ + void* work /* Pointer to the working buffer */ +) +{ + UINT i, n, sz_cyl, tot_cyl, b_cyl, e_cyl, p_cyl; + BYTE s_hd, e_hd, *p, *buf = (BYTE*)work; + DSTATUS stat; + DWORD sz_disk, sz_part, s_part; + + + stat = disk_initialize(pdrv); + if (stat & STA_NOINIT) return FR_NOT_READY; + if (stat & STA_PROTECT) return FR_WRITE_PROTECTED; + if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_disk)) return FR_DISK_ERR; + + /* Determine CHS in the table regardless of the drive geometry */ + for (n = 16; n < 256 && sz_disk / n / 63 > 1024; n *= 2) ; + if (n == 256) n--; + e_hd = n - 1; + sz_cyl = 63 * n; + tot_cyl = sz_disk / sz_cyl; + + /* Create partition table */ + mem_set(buf, 0, _MAX_SS); + p = buf + MBR_Table; b_cyl = 0; + for (i = 0; i < 4; i++, p += SZ_PTE) { + p_cyl = (szt[i] <= 100U) ? (DWORD)tot_cyl * szt[i] / 100 : szt[i] / sz_cyl; + if (!p_cyl) continue; + s_part = (DWORD)sz_cyl * b_cyl; + sz_part = (DWORD)sz_cyl * p_cyl; + if (i == 0) { /* Exclude first track of cylinder 0 */ + s_hd = 1; + s_part += 63; sz_part -= 63; + } else { + s_hd = 0; + } + e_cyl = b_cyl + p_cyl - 1; + if (e_cyl >= tot_cyl) return FR_INVALID_PARAMETER; + + /* Set partition table */ + p[1] = s_hd; /* Start head */ + p[2] = (BYTE)((b_cyl >> 2) + 1); /* Start sector */ + p[3] = (BYTE)b_cyl; /* Start cylinder */ + p[4] = 0x06; /* System type (temporary setting) */ + p[5] = e_hd; /* End head */ + p[6] = (BYTE)((e_cyl >> 2) + 63); /* End sector */ + p[7] = (BYTE)e_cyl; /* End cylinder */ + ST_DWORD(p + 8, s_part); /* Start sector in LBA */ + ST_DWORD(p + 12, sz_part); /* Partition size */ + + /* Next partition */ + b_cyl += p_cyl; + } + ST_WORD(p, 0xAA55); + + /* Write it to the MBR */ + return (disk_write(pdrv, buf, 0, 1) || disk_ioctl(pdrv, CTRL_SYNC, 0)) ? FR_DISK_ERR : FR_OK; +} + + +#endif /* _MULTI_PARTITION */ +#endif /* _USE_MKFS && !_FS_READONLY */ + + + + +#if _USE_STRFUNC +/*-----------------------------------------------------------------------*/ +/* Get a string from the file */ +/*-----------------------------------------------------------------------*/ + +TCHAR* f_gets ( + TCHAR* buff, /* Pointer to the string buffer to read */ + int len, /* Size of string buffer (characters) */ + FIL* fp /* Pointer to the file object */ +) +{ + int n = 0; + TCHAR c, *p = buff; + BYTE s[2]; + UINT rc; + + + while (n < len - 1) { /* Read characters until buffer gets filled */ +#if _USE_LFN && _LFN_UNICODE +#if _STRF_ENCODE == 3 /* Read a character in UTF-8 */ + f_read(fp, s, 1, &rc); + if (rc != 1) break; + c = s[0]; + if (c >= 0x80) { + if (c < 0xC0) continue; /* Skip stray trailer */ + if (c < 0xE0) { /* Two-byte sequence */ + f_read(fp, s, 1, &rc); + if (rc != 1) break; + c = (c & 0x1F) << 6 | (s[0] & 0x3F); + if (c < 0x80) c = '?'; + } else { + if (c < 0xF0) { /* Three-byte sequence */ + f_read(fp, s, 2, &rc); + if (rc != 2) break; + c = c << 12 | (s[0] & 0x3F) << 6 | (s[1] & 0x3F); + if (c < 0x800) c = '?'; + } else { /* Reject four-byte sequence */ + c = '?'; + } + } + } +#elif _STRF_ENCODE == 2 /* Read a character in UTF-16BE */ + f_read(fp, s, 2, &rc); + if (rc != 2) break; + c = s[1] + (s[0] << 8); +#elif _STRF_ENCODE == 1 /* Read a character in UTF-16LE */ + f_read(fp, s, 2, &rc); + if (rc != 2) break; + c = s[0] + (s[1] << 8); +#else /* Read a character in ANSI/OEM */ + f_read(fp, s, 1, &rc); + if (rc != 1) break; + c = s[0]; + if (IsDBCS1(c)) { + f_read(fp, s, 1, &rc); + if (rc != 1) break; + c = (c << 8) + s[0]; + } + c = ff_convert(c, 1); /* OEM -> Unicode */ + if (!c) c = '?'; +#endif +#else /* Read a character without conversion */ + f_read(fp, s, 1, &rc); + if (rc != 1) break; + c = s[0]; +#endif + if (_USE_STRFUNC == 2 && c == '\r') continue; /* Strip '\r' */ + *p++ = c; + n++; + if (c == '\n') break; /* Break on EOL */ + } + *p = 0; + return n ? buff : 0; /* When no data read (eof or error), return with error. */ +} + + + +#if !_FS_READONLY +#include +/*-----------------------------------------------------------------------*/ +/* Put a character to the file */ +/*-----------------------------------------------------------------------*/ + +typedef struct { + FIL* fp; + int idx, nchr; + BYTE buf[64]; +} putbuff; + + +static +void putc_bfd ( + putbuff* pb, + TCHAR c +) +{ + UINT bw; + int i; + + + if (_USE_STRFUNC == 2 && c == '\n') /* LF -> CRLF conversion */ + putc_bfd(pb, '\r'); + + i = pb->idx; /* Buffer write index (-1:error) */ + if (i < 0) return; + +#if _USE_LFN && _LFN_UNICODE +#if _STRF_ENCODE == 3 /* Write a character in UTF-8 */ + if (c < 0x80) { /* 7-bit */ + pb->buf[i++] = (BYTE)c; + } else { + if (c < 0x800) { /* 11-bit */ + pb->buf[i++] = (BYTE)(0xC0 | c >> 6); + } else { /* 16-bit */ + pb->buf[i++] = (BYTE)(0xE0 | c >> 12); + pb->buf[i++] = (BYTE)(0x80 | (c >> 6 & 0x3F)); + } + pb->buf[i++] = (BYTE)(0x80 | (c & 0x3F)); + } +#elif _STRF_ENCODE == 2 /* Write a character in UTF-16BE */ + pb->buf[i++] = (BYTE)(c >> 8); + pb->buf[i++] = (BYTE)c; +#elif _STRF_ENCODE == 1 /* Write a character in UTF-16LE */ + pb->buf[i++] = (BYTE)c; + pb->buf[i++] = (BYTE)(c >> 8); +#else /* Write a character in ANSI/OEM */ + c = ff_convert(c, 0); /* Unicode -> OEM */ + if (!c) c = '?'; + if (c >= 0x100) + pb->buf[i++] = (BYTE)(c >> 8); + pb->buf[i++] = (BYTE)c; +#endif +#else /* Write a character without conversion */ + pb->buf[i++] = (BYTE)c; +#endif + + if (i >= (int)(sizeof pb->buf) - 3) { /* Write buffered characters to the file */ + f_write(pb->fp, pb->buf, (UINT)i, &bw); + i = (bw == (UINT)i) ? 0 : -1; + } + pb->idx = i; + pb->nchr++; +} + + + +int f_putc ( + TCHAR c, /* A character to be output */ + FIL* fp /* Pointer to the file object */ +) +{ + putbuff pb; + UINT nw; + + + pb.fp = fp; /* Initialize output buffer */ + pb.nchr = pb.idx = 0; + + putc_bfd(&pb, c); /* Put a character */ + + if ( pb.idx >= 0 /* Flush buffered characters to the file */ + && f_write(pb.fp, pb.buf, (UINT)pb.idx, &nw) == FR_OK + && (UINT)pb.idx == nw) return pb.nchr; + return EOF; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Put a string to the file */ +/*-----------------------------------------------------------------------*/ + +int f_puts ( + const TCHAR* str, /* Pointer to the string to be output */ + FIL* fp /* Pointer to the file object */ +) +{ + putbuff pb; + UINT nw; + + + pb.fp = fp; /* Initialize output buffer */ + pb.nchr = pb.idx = 0; + + while (*str) /* Put the string */ + putc_bfd(&pb, *str++); + + if ( pb.idx >= 0 /* Flush buffered characters to the file */ + && f_write(pb.fp, pb.buf, (UINT)pb.idx, &nw) == FR_OK + && (UINT)pb.idx == nw) return pb.nchr; + return EOF; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Put a formatted string to the file */ +/*-----------------------------------------------------------------------*/ + +int f_printf ( + FIL* fp, /* Pointer to the file object */ + const TCHAR* fmt, /* Pointer to the format string */ + ... /* Optional arguments... */ +) +{ + va_list arp; + BYTE f, r; + UINT nw, i, j, w; + DWORD v; + TCHAR c, d, s[16], *p; + putbuff pb; + + + pb.fp = fp; /* Initialize output buffer */ + pb.nchr = pb.idx = 0; + + va_start(arp, fmt); + + for (;;) { + c = *fmt++; + if (c == 0) break; /* End of string */ + if (c != '%') { /* Non escape character */ + putc_bfd(&pb, c); + continue; + } + w = f = 0; + c = *fmt++; + if (c == '0') { /* Flag: '0' padding */ + f = 1; c = *fmt++; + } else { + if (c == '-') { /* Flag: left justified */ + f = 2; c = *fmt++; + } + } + while (IsDigit(c)) { /* Precision */ + w = w * 10 + c - '0'; + c = *fmt++; + } + if (c == 'l' || c == 'L') { /* Prefix: Size is long int */ + f |= 4; c = *fmt++; + } + if (!c) break; + d = c; + if (IsLower(d)) d -= 0x20; + switch (d) { /* Type is... */ + case 'S' : /* String */ + p = va_arg(arp, TCHAR*); + for (j = 0; p[j]; j++) ; + if (!(f & 2)) { + while (j++ < w) putc_bfd(&pb, ' '); + } + while (*p) putc_bfd(&pb, *p++); + while (j++ < w) putc_bfd(&pb, ' '); + continue; + case 'C' : /* Character */ + putc_bfd(&pb, (TCHAR)va_arg(arp, int)); continue; + case 'B' : /* Binary */ + r = 2; break; + case 'O' : /* Octal */ + r = 8; break; + case 'D' : /* Signed decimal */ + case 'U' : /* Unsigned decimal */ + r = 10; break; + case 'X' : /* Hexdecimal */ + r = 16; break; + default: /* Unknown type (pass-through) */ + putc_bfd(&pb, c); continue; + } + + /* Get an argument and put it in numeral */ + v = (f & 4) ? (DWORD)va_arg(arp, long) : ((d == 'D') ? (DWORD)(long)va_arg(arp, int) : (DWORD)va_arg(arp, unsigned int)); + if (d == 'D' && (v & 0x80000000)) { + v = 0 - v; + f |= 8; + } + i = 0; + do { + d = (TCHAR)(v % r); v /= r; + if (d > 9) d += (c == 'x') ? 0x27 : 0x07; + s[i++] = d + '0'; + } while (v && i < sizeof s / sizeof s[0]); + if (f & 8) s[i++] = '-'; + j = i; d = (f & 1) ? '0' : ' '; + while (!(f & 2) && j++ < w) putc_bfd(&pb, d); + do putc_bfd(&pb, s[--i]); while (i); + while (j++ < w) putc_bfd(&pb, d); + } + + va_end(arp); + + if ( pb.idx >= 0 /* Flush buffered characters to the file */ + && f_write(pb.fp, pb.buf, (UINT)pb.idx, &nw) == FR_OK + && (UINT)pb.idx == nw) return pb.nchr; + return EOF; +} + +#endif /* !_FS_READONLY */ +#endif /* _USE_STRFUNC */ From 4b6d378e818b11d695a60d32a05ac4acd61bff0e Mon Sep 17 00:00:00 2001 From: Fabien Poussin Date: Wed, 29 Mar 2017 17:58:36 +0200 Subject: [PATCH 14/74] Missing fatfs file --- firmware/ext/option/ccsbcs.c | 540 +++++++++++++++++++++++++++++++++++ 1 file changed, 540 insertions(+) create mode 100644 firmware/ext/option/ccsbcs.c diff --git a/firmware/ext/option/ccsbcs.c b/firmware/ext/option/ccsbcs.c new file mode 100644 index 0000000000..8aa71b29f0 --- /dev/null +++ b/firmware/ext/option/ccsbcs.c @@ -0,0 +1,540 @@ +/*------------------------------------------------------------------------*/ +/* Unicode - Local code bidirectional converter (C)ChaN, 2012 */ +/* (SBCS code pages) */ +/*------------------------------------------------------------------------*/ +/* 437 U.S. (OEM) +/ 720 Arabic (OEM) +/ 1256 Arabic (Windows) +/ 737 Greek (OEM) +/ 1253 Greek (Windows) +/ 1250 Central Europe (Windows) +/ 775 Baltic (OEM) +/ 1257 Baltic (Windows) +/ 850 Multilingual Latin 1 (OEM) +/ 852 Latin 2 (OEM) +/ 1252 Latin 1 (Windows) +/ 855 Cyrillic (OEM) +/ 1251 Cyrillic (Windows) +/ 866 Russian (OEM) +/ 857 Turkish (OEM) +/ 1254 Turkish (Windows) +/ 858 Multilingual Latin 1 + Euro (OEM) +/ 862 Hebrew (OEM) +/ 1255 Hebrew (Windows) +/ 874 Thai (OEM, Windows) +/ 1258 Vietnam (OEM, Windows) +*/ + +#include "../ff.h" + + +#if _CODE_PAGE == 437 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP437(0x80-0xFF) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, + 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, + 0x00FF, 0x00D6, 0x00DC, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, + 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, + 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, + 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, + 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, + 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, + 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 720 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP720(0x80-0xFF) to Unicode conversion table */ + 0x0000, 0x0000, 0x00E9, 0x00E2, 0x0000, 0x00E0, 0x0000, 0x00E7, + 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0651, 0x0652, 0x00F4, 0x00A4, 0x0640, 0x00FB, 0x00F9, + 0x0621, 0x0622, 0x0623, 0x0624, 0x00A3, 0x0625, 0x0626, 0x0627, + 0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F, + 0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, + 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, + 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x0636, 0x0637, 0x0638, 0x0639, 0x063A, 0x0641, 0x00B5, 0x0642, + 0x0643, 0x0644, 0x0645, 0x0646, 0x0647, 0x0648, 0x0649, 0x064A, + 0x2261, 0x064B, 0x064C, 0x064D, 0x064E, 0x064F, 0x0650, 0x2248, + 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 737 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP737(0x80-0xFF) to Unicode conversion table */ + 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x0398, + 0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F, 0x03A0, + 0x03A1, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7, 0x03A8, 0x03A9, + 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7, 0x03B8, + 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, 0x03C0, + 0x03C1, 0x03C3, 0x03C2, 0x03C4, 0x03C5, 0x03C6, 0x03C7, 0x03C8, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, + 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, + 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03C9, 0x03AC, 0x03AD, 0x03AE, 0x03CA, 0x03AF, 0x03CC, 0x03CD, + 0x03CB, 0x03CE, 0x0386, 0x0388, 0x0389, 0x038A, 0x038C, 0x038E, + 0x038F, 0x00B1, 0x2265, 0x2264, 0x03AA, 0x03AB, 0x00F7, 0x2248, + 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 775 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP775(0x80-0xFF) to Unicode conversion table */ + 0x0106, 0x00FC, 0x00E9, 0x0101, 0x00E4, 0x0123, 0x00E5, 0x0107, + 0x0142, 0x0113, 0x0156, 0x0157, 0x012B, 0x0179, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x014D, 0x00F6, 0x0122, 0x00A2, 0x015A, + 0x015B, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x00A4, + 0x0100, 0x012A, 0x00F3, 0x017B, 0x017C, 0x017A, 0x201D, 0x00A6, + 0x00A9, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x0141, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0104, 0x010C, 0x0118, + 0x0116, 0x2563, 0x2551, 0x2557, 0x255D, 0x012E, 0x0160, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0172, 0x016A, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x017D, + 0x0105, 0x010D, 0x0119, 0x0117, 0x012F, 0x0161, 0x0173, 0x016B, + 0x017E, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x00D3, 0x00DF, 0x014C, 0x0143, 0x00F5, 0x00D5, 0x00B5, 0x0144, + 0x0136, 0x0137, 0x013B, 0x013C, 0x0146, 0x0112, 0x0145, 0x2019, + 0x00AD, 0x00B1, 0x201C, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x201E, + 0x00B0, 0x2219, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 850 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP850(0x80-0xFF) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, + 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, + 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, + 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, + 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x0131, 0x00CD, 0x00CE, + 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580, + 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE, + 0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4, + 0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, + 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 852 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP852(0x80-0xFF) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x016F, 0x0107, 0x00E7, + 0x0142, 0x00EB, 0x0150, 0x0151, 0x00EE, 0x0179, 0x00C4, 0x0106, + 0x00C9, 0x0139, 0x013A, 0x00F4, 0x00F6, 0x013D, 0x013E, 0x015A, + 0x015B, 0x00D6, 0x00DC, 0x0164, 0x0165, 0x0141, 0x00D7, 0x010D, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x0104, 0x0105, 0x017D, 0x017E, + 0x0118, 0x0119, 0x00AC, 0x017A, 0x010C, 0x015F, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x011A, + 0x015E, 0x2563, 0x2551, 0x2557, 0x255D, 0x017B, 0x017C, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0102, 0x0103, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x0111, 0x0110, 0x010E, 0x00CB, 0x010F, 0x0147, 0x00CD, 0x00CE, + 0x011B, 0x2518, 0x250C, 0x2588, 0x2584, 0x0162, 0x016E, 0x2580, + 0x00D3, 0x00DF, 0x00D4, 0x0143, 0x0144, 0x0148, 0x0160, 0x0161, + 0x0154, 0x00DA, 0x0155, 0x0170, 0x00FD, 0x00DD, 0x0163, 0x00B4, + 0x00AD, 0x02DD, 0x02DB, 0x02C7, 0x02D8, 0x00A7, 0x00F7, 0x00B8, + 0x00B0, 0x00A8, 0x02D9, 0x0171, 0x0158, 0x0159, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 855 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP855(0x80-0xFF) to Unicode conversion table */ + 0x0452, 0x0402, 0x0453, 0x0403, 0x0451, 0x0401, 0x0454, 0x0404, + 0x0455, 0x0405, 0x0456, 0x0406, 0x0457, 0x0407, 0x0458, 0x0408, + 0x0459, 0x0409, 0x045A, 0x040A, 0x045B, 0x040B, 0x045C, 0x040C, + 0x045E, 0x040E, 0x045F, 0x040F, 0x044E, 0x042E, 0x044A, 0x042A, + 0x0430, 0x0410, 0x0431, 0x0411, 0x0446, 0x0426, 0x0434, 0x0414, + 0x0435, 0x0415, 0x0444, 0x0424, 0x0433, 0x0413, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0445, 0x0425, 0x0438, + 0x0418, 0x2563, 0x2551, 0x2557, 0x255D, 0x0439, 0x0419, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x043A, 0x041A, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x043B, 0x041B, 0x043C, 0x041C, 0x043D, 0x041D, 0x043E, 0x041E, + 0x043F, 0x2518, 0x250C, 0x2588, 0x2584, 0x041F, 0x044F, 0x2580, + 0x042F, 0x0440, 0x0420, 0x0441, 0x0421, 0x0442, 0x0422, 0x0443, + 0x0423, 0x0436, 0x0416, 0x0432, 0x0412, 0x044C, 0x042C, 0x2116, + 0x00AD, 0x044B, 0x042B, 0x0437, 0x0417, 0x0448, 0x0428, 0x044D, + 0x042D, 0x0449, 0x0429, 0x0447, 0x0427, 0x00A7, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 857 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP857(0x80-0xFF) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, + 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0131, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, + 0x0130, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x015E, 0x015F, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x011E, 0x011F, + 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, + 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x00BA, 0x00AA, 0x00CA, 0x00CB, 0x00C8, 0x0000, 0x00CD, 0x00CE, + 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580, + 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x0000, + 0x00D7, 0x00DA, 0x00DB, 0x00D9, 0x00EC, 0x00FF, 0x00AF, 0x00B4, + 0x00AD, 0x00B1, 0x0000, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, + 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 858 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP858(0x80-0xFF) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, + 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, + 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, + 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, + 0x00A9, 0x2563, 0x2551, 0x2557, 0x2550, 0x00A2, 0x00A5, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x20AC, 0x00CD, 0x00CE, + 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00C6, 0x00CC, 0x2580, + 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE, + 0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4, + 0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, + 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 862 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP862(0x80-0xFF) to Unicode conversion table */ + 0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7, + 0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF, + 0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7, + 0x05E8, 0x05E9, 0x05EA, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, + 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, + 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, + 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, + 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, + 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, + 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 866 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP866(0x80-0xFF) to Unicode conversion table */ + 0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, + 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F, + 0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, + 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F, + 0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, + 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, + 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, + 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, + 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F, + 0x0401, 0x0451, 0x0404, 0x0454, 0x0407, 0x0457, 0x040E, 0x045E, + 0x00B0, 0x2219, 0x00B7, 0x221A, 0x2116, 0x00A4, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 874 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP874(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x0000, 0x0000, 0x0000, 0x2026, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x00A0, 0x0E01, 0x0E02, 0x0E03, 0x0E04, 0x0E05, 0x0E06, 0x0E07, + 0x0E08, 0x0E09, 0x0E0A, 0x0E0B, 0x0E0C, 0x0E0D, 0x0E0E, 0x0E0F, + 0x0E10, 0x0E11, 0x0E12, 0x0E13, 0x0E14, 0x0E15, 0x0E16, 0x0E17, + 0x0E18, 0x0E19, 0x0E1A, 0x0E1B, 0x0E1C, 0x0E1D, 0x0E1E, 0x0E1F, + 0x0E20, 0x0E21, 0x0E22, 0x0E23, 0x0E24, 0x0E25, 0x0E26, 0x0E27, + 0x0E28, 0x0E29, 0x0E2A, 0x0E2B, 0x0E2C, 0x0E2D, 0x0E2E, 0x0E2F, + 0x0E30, 0x0E31, 0x0E32, 0x0E33, 0x0E34, 0x0E35, 0x0E36, 0x0E37, + 0x0E38, 0x0E39, 0x0E3A, 0x0000, 0x0000, 0x0000, 0x0000, 0x0E3F, + 0x0E40, 0x0E41, 0x0E42, 0x0E43, 0x0E44, 0x0E45, 0x0E46, 0x0E47, + 0x0E48, 0x0E49, 0x0E4A, 0x0E4B, 0x0E4C, 0x0E4D, 0x0E4E, 0x0E4F, + 0x0E50, 0x0E51, 0x0E52, 0x0E53, 0x0E54, 0x0E55, 0x0E56, 0x0E57, + 0x0E58, 0x0E59, 0x0E5A, 0x0E5B, 0x0000, 0x0000, 0x0000, 0x0000 +}; + +#elif _CODE_PAGE == 1250 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1250(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x201A, 0x0000, 0x201E, 0x2026, 0x2020, 0x2021, + 0x0000, 0x2030, 0x0160, 0x2039, 0x015A, 0x0164, 0x017D, 0x0179, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x0000, 0x2122, 0x0161, 0x203A, 0x015B, 0x0165, 0x017E, 0x017A, + 0x00A0, 0x02C7, 0x02D8, 0x0141, 0x00A4, 0x0104, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x015E, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x017B, + 0x00B0, 0x00B1, 0x02DB, 0x0142, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x0105, 0x015F, 0x00BB, 0x013D, 0x02DD, 0x013E, 0x017C, + 0x0154, 0x00C1, 0x00C2, 0x0102, 0x00C4, 0x0139, 0x0106, 0x00C7, + 0x010C, 0x00C9, 0x0118, 0x00CB, 0x011A, 0x00CD, 0x00CE, 0x010E, + 0x0110, 0x0143, 0x0147, 0x00D3, 0x00D4, 0x0150, 0x00D6, 0x00D7, + 0x0158, 0x016E, 0x00DA, 0x0170, 0x00DC, 0x00DD, 0x0162, 0x00DF, + 0x0155, 0x00E1, 0x00E2, 0x0103, 0x00E4, 0x013A, 0x0107, 0x00E7, + 0x010D, 0x00E9, 0x0119, 0x00EB, 0x011B, 0x00ED, 0x00EE, 0x010F, + 0x0111, 0x0144, 0x0148, 0x00F3, 0x00F4, 0x0151, 0x00F6, 0x00F7, + 0x0159, 0x016F, 0x00FA, 0x0171, 0x00FC, 0x00FD, 0x0163, 0x02D9 +}; + +#elif _CODE_PAGE == 1251 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1251(0x80-0xFF) to Unicode conversion table */ + 0x0402, 0x0403, 0x201A, 0x0453, 0x201E, 0x2026, 0x2020, 0x2021, + 0x20AC, 0x2030, 0x0409, 0x2039, 0x040A, 0x040C, 0x040B, 0x040F, + 0x0452, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x0000, 0x2111, 0x0459, 0x203A, 0x045A, 0x045C, 0x045B, 0x045F, + 0x00A0, 0x040E, 0x045E, 0x0408, 0x00A4, 0x0490, 0x00A6, 0x00A7, + 0x0401, 0x00A9, 0x0404, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x0407, + 0x00B0, 0x00B1, 0x0406, 0x0456, 0x0491, 0x00B5, 0x00B6, 0x00B7, + 0x0451, 0x2116, 0x0454, 0x00BB, 0x0458, 0x0405, 0x0455, 0x0457, + 0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, + 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F, + 0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, + 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F, + 0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, + 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F, + 0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, + 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F +}; + +#elif _CODE_PAGE == 1252 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1252(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, + 0x02C6, 0x2030, 0x0160, 0x2039, 0x0152, 0x0000, 0x017D, 0x0000, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x02DC, 0x2122, 0x0161, 0x203A, 0x0153, 0x0000, 0x017E, 0x0178, + 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, + 0x00C0, 0x00C1, 0x00C2, 0x00C3, 0x00C4, 0x00C5, 0x00C6, 0x00C7, + 0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x00CC, 0x00CD, 0x00CE, 0x00CF, + 0x00D0, 0x00D1, 0x00D2, 0x00D3, 0x00D4, 0x00D5, 0x00D6, 0x00D7, + 0x00D8, 0x00D9, 0x00DA, 0x00DB, 0x00DC, 0x00DD, 0x00DE, 0x00DF, + 0x00E0, 0x00E1, 0x00E2, 0x00E3, 0x00E4, 0x00E5, 0x00E6, 0x00E7, + 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x00EC, 0x00ED, 0x00EE, 0x00EF, + 0x00F0, 0x00F1, 0x00F2, 0x00F3, 0x00F4, 0x00F5, 0x00F6, 0x00F7, + 0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x00FD, 0x00FE, 0x00FF +}; + +#elif _CODE_PAGE == 1253 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1253(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, + 0x0000, 0x2030, 0x0000, 0x2039, 0x000C, 0x0000, 0x0000, 0x0000, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x0000, 0x2122, 0x0000, 0x203A, 0x0000, 0x0000, 0x0000, 0x0000, + 0x00A0, 0x0385, 0x0386, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x0000, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x2015, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x0384, 0x00B5, 0x00B6, 0x00B7, + 0x0388, 0x0389, 0x038A, 0x00BB, 0x038C, 0x00BD, 0x038E, 0x038F, + 0x0390, 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, + 0x0398, 0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F, + 0x03A0, 0x03A1, 0x0000, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7, + 0x03A8, 0x03A9, 0x03AA, 0x03AD, 0x03AC, 0x03AD, 0x03AE, 0x03AF, + 0x03B0, 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7, + 0x03B8, 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, + 0x03C0, 0x03C1, 0x03C2, 0x03C3, 0x03C4, 0x03C5, 0x03C6, 0x03C7, + 0x03C8, 0x03C9, 0x03CA, 0x03CB, 0x03CC, 0x03CD, 0x03CE, 0x0000 +}; + +#elif _CODE_PAGE == 1254 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1254(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x210A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, + 0x02C6, 0x2030, 0x0160, 0x2039, 0x0152, 0x0000, 0x0000, 0x0000, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x02DC, 0x2122, 0x0161, 0x203A, 0x0153, 0x0000, 0x0000, 0x0178, + 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, + 0x00C0, 0x00C1, 0x00C2, 0x00C3, 0x00C4, 0x00C5, 0x00C6, 0x00C7, + 0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x00CC, 0x00CD, 0x00CE, 0x00CF, + 0x011E, 0x00D1, 0x00D2, 0x00D3, 0x00D4, 0x00D5, 0x00D6, 0x00D7, + 0x00D8, 0x00D9, 0x00DA, 0x00BD, 0x00DC, 0x0130, 0x015E, 0x00DF, + 0x00E0, 0x00E1, 0x00E2, 0x00E3, 0x00E4, 0x00E5, 0x00E6, 0x00E7, + 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x00EC, 0x00ED, 0x00EE, 0x00EF, + 0x011F, 0x00F1, 0x00F2, 0x00F3, 0x00F4, 0x00F5, 0x00F6, 0x00F7, + 0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x0131, 0x015F, 0x00FF +}; + +#elif _CODE_PAGE == 1255 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1255(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, + 0x02C6, 0x2030, 0x0000, 0x2039, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x02DC, 0x2122, 0x0000, 0x203A, 0x0000, 0x0000, 0x0000, 0x0000, + 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x00D7, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x00B9, 0x00F7, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, + 0x05B0, 0x05B1, 0x05B2, 0x05B3, 0x05B4, 0x05B5, 0x05B6, 0x05B7, + 0x05B8, 0x05B9, 0x0000, 0x05BB, 0x05BC, 0x05BD, 0x05BE, 0x05BF, + 0x05C0, 0x05C1, 0x05C2, 0x05C3, 0x05F0, 0x05F1, 0x05F2, 0x05F3, + 0x05F4, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7, + 0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF, + 0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7, + 0x05E8, 0x05E9, 0x05EA, 0x0000, 0x0000, 0x200E, 0x200F, 0x0000 +}; + +#elif _CODE_PAGE == 1256 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1256(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x067E, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, + 0x02C6, 0x2030, 0x0679, 0x2039, 0x0152, 0x0686, 0x0698, 0x0688, + 0x06AF, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x06A9, 0x2122, 0x0691, 0x203A, 0x0153, 0x200C, 0x200D, 0x06BA, + 0x00A0, 0x060C, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x06BE, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x00B9, 0x061B, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x061F, + 0x06C1, 0x0621, 0x0622, 0x0623, 0x0624, 0x0625, 0x0626, 0x0627, + 0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F, + 0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x0636, 0x00D7, + 0x0637, 0x0638, 0x0639, 0x063A, 0x0640, 0x0640, 0x0642, 0x0643, + 0x00E0, 0x0644, 0x00E2, 0x0645, 0x0646, 0x0647, 0x0648, 0x00E7, + 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x0649, 0x064A, 0x00EE, 0x00EF, + 0x064B, 0x064C, 0x064D, 0x064E, 0x00F4, 0x064F, 0x0650, 0x00F7, + 0x0651, 0x00F9, 0x0652, 0x00FB, 0x00FC, 0x200E, 0x200F, 0x06D2 +} + +#elif _CODE_PAGE == 1257 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1257(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x201A, 0x0000, 0x201E, 0x2026, 0x2020, 0x2021, + 0x0000, 0x2030, 0x0000, 0x2039, 0x0000, 0x00A8, 0x02C7, 0x00B8, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x0000, 0x2122, 0x0000, 0x203A, 0x0000, 0x00AF, 0x02DB, 0x0000, + 0x00A0, 0x0000, 0x00A2, 0x00A3, 0x00A4, 0x0000, 0x00A6, 0x00A7, + 0x00D8, 0x00A9, 0x0156, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x00B9, 0x0157, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00E6, + 0x0104, 0x012E, 0x0100, 0x0106, 0x00C4, 0x00C5, 0x0118, 0x0112, + 0x010C, 0x00C9, 0x0179, 0x0116, 0x0122, 0x0136, 0x012A, 0x013B, + 0x0160, 0x0143, 0x0145, 0x00D3, 0x014C, 0x00D5, 0x00D6, 0x00D7, + 0x0172, 0x0141, 0x015A, 0x016A, 0x00DC, 0x017B, 0x017D, 0x00DF, + 0x0105, 0x012F, 0x0101, 0x0107, 0x00E4, 0x00E5, 0x0119, 0x0113, + 0x010D, 0x00E9, 0x017A, 0x0117, 0x0123, 0x0137, 0x012B, 0x013C, + 0x0161, 0x0144, 0x0146, 0x00F3, 0x014D, 0x00F5, 0x00F6, 0x00F7, + 0x0173, 0x014E, 0x015B, 0x016B, 0x00FC, 0x017C, 0x017E, 0x02D9 +}; + +#elif _CODE_PAGE == 1258 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1258(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, + 0x02C6, 0x2030, 0x0000, 0x2039, 0x0152, 0x0000, 0x0000, 0x0000, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x02DC, 0x2122, 0x0000, 0x203A, 0x0153, 0x0000, 0x0000, 0x0178, + 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, + 0x00C0, 0x00C1, 0x00C2, 0x0102, 0x00C4, 0x00C5, 0x00C6, 0x00C7, + 0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x0300, 0x00CD, 0x00CE, 0x00CF, + 0x0110, 0x00D1, 0x0309, 0x00D3, 0x00D4, 0x01A0, 0x00D6, 0x00D7, + 0x00D8, 0x00D9, 0x00DA, 0x00DB, 0x00DC, 0x01AF, 0x0303, 0x00DF, + 0x00E0, 0x00E1, 0x00E2, 0x0103, 0x00E4, 0x00E5, 0x00E6, 0x00E7, + 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x0301, 0x00ED, 0x00EE, 0x00EF, + 0x0111, 0x00F1, 0x0323, 0x00F3, 0x00F4, 0x01A1, 0x00F6, 0x00F7, + 0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x01B0, 0x20AB, 0x00FF +}; + +#endif + + +#if !_TBLDEF || !_USE_LFN +#error This file is not needed in current configuration. Remove from the project. +#endif + + +WCHAR ff_convert ( /* Converted character, Returns zero on error */ + WCHAR chr, /* Character code to be converted */ + UINT dir /* 0: Unicode to OEMCP, 1: OEMCP to Unicode */ +) +{ + WCHAR c; + + + if (chr < 0x80) { /* ASCII */ + c = chr; + + } else { + if (dir) { /* OEMCP to Unicode */ + c = (chr >= 0x100) ? 0 : Tbl[chr - 0x80]; + + } else { /* Unicode to OEMCP */ + for (c = 0; c < 0x80; c++) { + if (chr == Tbl[c]) break; + } + c = (c + 0x80) & 0xFF; + } + } + + return c; +} + + +WCHAR ff_wtoupper ( /* Upper converted character */ + WCHAR chr /* Input character */ +) +{ + static const WCHAR tbl_lower[] = { 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0xA1, 0x00A2, 0x00A3, 0x00A5, 0x00AC, 0x00AF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0x0FF, 0x101, 0x103, 0x105, 0x107, 0x109, 0x10B, 0x10D, 0x10F, 0x111, 0x113, 0x115, 0x117, 0x119, 0x11B, 0x11D, 0x11F, 0x121, 0x123, 0x125, 0x127, 0x129, 0x12B, 0x12D, 0x12F, 0x131, 0x133, 0x135, 0x137, 0x13A, 0x13C, 0x13E, 0x140, 0x142, 0x144, 0x146, 0x148, 0x14B, 0x14D, 0x14F, 0x151, 0x153, 0x155, 0x157, 0x159, 0x15B, 0x15D, 0x15F, 0x161, 0x163, 0x165, 0x167, 0x169, 0x16B, 0x16D, 0x16F, 0x171, 0x173, 0x175, 0x177, 0x17A, 0x17C, 0x17E, 0x192, 0x3B1, 0x3B2, 0x3B3, 0x3B4, 0x3B5, 0x3B6, 0x3B7, 0x3B8, 0x3B9, 0x3BA, 0x3BB, 0x3BC, 0x3BD, 0x3BE, 0x3BF, 0x3C0, 0x3C1, 0x3C3, 0x3C4, 0x3C5, 0x3C6, 0x3C7, 0x3C8, 0x3C9, 0x3CA, 0x430, 0x431, 0x432, 0x433, 0x434, 0x435, 0x436, 0x437, 0x438, 0x439, 0x43A, 0x43B, 0x43C, 0x43D, 0x43E, 0x43F, 0x440, 0x441, 0x442, 0x443, 0x444, 0x445, 0x446, 0x447, 0x448, 0x449, 0x44A, 0x44B, 0x44C, 0x44D, 0x44E, 0x44F, 0x451, 0x452, 0x453, 0x454, 0x455, 0x456, 0x457, 0x458, 0x459, 0x45A, 0x45B, 0x45C, 0x45E, 0x45F, 0x2170, 0x2171, 0x2172, 0x2173, 0x2174, 0x2175, 0x2176, 0x2177, 0x2178, 0x2179, 0x217A, 0x217B, 0x217C, 0x217D, 0x217E, 0x217F, 0xFF41, 0xFF42, 0xFF43, 0xFF44, 0xFF45, 0xFF46, 0xFF47, 0xFF48, 0xFF49, 0xFF4A, 0xFF4B, 0xFF4C, 0xFF4D, 0xFF4E, 0xFF4F, 0xFF50, 0xFF51, 0xFF52, 0xFF53, 0xFF54, 0xFF55, 0xFF56, 0xFF57, 0xFF58, 0xFF59, 0xFF5A, 0 }; + static const WCHAR tbl_upper[] = { 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x21, 0xFFE0, 0xFFE1, 0xFFE5, 0xFFE2, 0xFFE3, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0x178, 0x100, 0x102, 0x104, 0x106, 0x108, 0x10A, 0x10C, 0x10E, 0x110, 0x112, 0x114, 0x116, 0x118, 0x11A, 0x11C, 0x11E, 0x120, 0x122, 0x124, 0x126, 0x128, 0x12A, 0x12C, 0x12E, 0x130, 0x132, 0x134, 0x136, 0x139, 0x13B, 0x13D, 0x13F, 0x141, 0x143, 0x145, 0x147, 0x14A, 0x14C, 0x14E, 0x150, 0x152, 0x154, 0x156, 0x158, 0x15A, 0x15C, 0x15E, 0x160, 0x162, 0x164, 0x166, 0x168, 0x16A, 0x16C, 0x16E, 0x170, 0x172, 0x174, 0x176, 0x179, 0x17B, 0x17D, 0x191, 0x391, 0x392, 0x393, 0x394, 0x395, 0x396, 0x397, 0x398, 0x399, 0x39A, 0x39B, 0x39C, 0x39D, 0x39E, 0x39F, 0x3A0, 0x3A1, 0x3A3, 0x3A4, 0x3A5, 0x3A6, 0x3A7, 0x3A8, 0x3A9, 0x3AA, 0x410, 0x411, 0x412, 0x413, 0x414, 0x415, 0x416, 0x417, 0x418, 0x419, 0x41A, 0x41B, 0x41C, 0x41D, 0x41E, 0x41F, 0x420, 0x421, 0x422, 0x423, 0x424, 0x425, 0x426, 0x427, 0x428, 0x429, 0x42A, 0x42B, 0x42C, 0x42D, 0x42E, 0x42F, 0x401, 0x402, 0x403, 0x404, 0x405, 0x406, 0x407, 0x408, 0x409, 0x40A, 0x40B, 0x40C, 0x40E, 0x40F, 0x2160, 0x2161, 0x2162, 0x2163, 0x2164, 0x2165, 0x2166, 0x2167, 0x2168, 0x2169, 0x216A, 0x216B, 0x216C, 0x216D, 0x216E, 0x216F, 0xFF21, 0xFF22, 0xFF23, 0xFF24, 0xFF25, 0xFF26, 0xFF27, 0xFF28, 0xFF29, 0xFF2A, 0xFF2B, 0xFF2C, 0xFF2D, 0xFF2E, 0xFF2F, 0xFF30, 0xFF31, 0xFF32, 0xFF33, 0xFF34, 0xFF35, 0xFF36, 0xFF37, 0xFF38, 0xFF39, 0xFF3A, 0 }; + int i; + + + for (i = 0; tbl_lower[i] && chr != tbl_lower[i]; i++) ; + + return tbl_lower[i] ? tbl_upper[i] : chr; +} From 9f75cd5c75f7132cf04c20ededb70acdf915886b Mon Sep 17 00:00:00 2001 From: Fabien Poussin Date: Wed, 29 Mar 2017 18:03:37 +0200 Subject: [PATCH 15/74] Various ChibiOS compatibility fixes and a missing OBD define --- firmware/controllers/algo/obd_error_codes.h | 4 ++-- firmware/hw_layer/adc_inputs.cpp | 18 +++++++++--------- firmware/hw_layer/microsecond_timer.cpp | 4 ++-- firmware/rusefi.cpp | 6 +++--- 4 files changed, 16 insertions(+), 16 deletions(-) diff --git a/firmware/controllers/algo/obd_error_codes.h b/firmware/controllers/algo/obd_error_codes.h index ac9cc8ecf7..7b42fd465c 100644 --- a/firmware/controllers/algo/obd_error_codes.h +++ b/firmware/controllers/algo/obd_error_codes.h @@ -1698,8 +1698,8 @@ typedef enum { CUSTOM_OBD_INJECTION_NO_PIN_ASSIGNED = 6020, CUSTOM_OBD_UNEXPECTED_INJECTION_MODE = 6021, CUSTOM_OBD_ANGLE_CONSTRAINT_VIOLATION = 6022, - CUSTOM_OBD_23 = 6023, - CUSTOM_OBD_24 = 6024, + CUSTOM_OBD_UNKNOWN_FIRING_ORDER = 6023, + CUSTOM_OBD_WRONG_FIRING_ORDER = 6024, CUSTOM_OBD_25 = 6025, CUSTOM_OBD_26 = 6026, CUSTOM_UNEXPECTED_ENGINE_TYPE = 6027, diff --git a/firmware/hw_layer/adc_inputs.cpp b/firmware/hw_layer/adc_inputs.cpp index 117dada0e5..a05d626bec 100644 --- a/firmware/hw_layer/adc_inputs.cpp +++ b/firmware/hw_layer/adc_inputs.cpp @@ -148,7 +148,7 @@ AdcDevice fastAdc(&adcgrpcfg_fast); void doSlowAdc(void) { - efiAssertVoid(getRemainingStack(chThdSelf())> 32, "lwStAdcSlow"); + efiAssertVoid(getRemainingStack(chThdGetSelfX())> 32, "lwStAdcSlow"); #if EFI_INTERNAL_ADC @@ -156,19 +156,19 @@ void doSlowAdc(void) { will be executed in parallel to the current PWM cycle and will terminate before the next PWM cycle.*/ slowAdc.conversionCount++; - chSysLockFromIsr() + chSysLockFromISR() ; if (ADC_SLOW_DEVICE.state != ADC_READY && ADC_SLOW_DEVICE.state != ADC_COMPLETE && ADC_SLOW_DEVICE.state != ADC_ERROR) { // todo: why and when does this happen? firmwareError(OBD_PCM_Processor_Fault, "ADC slow not ready?"); slowAdc.errorsCount++; - chSysUnlockFromIsr() + chSysUnlockFromISR() ; return; } adcStartConversionI(&ADC_SLOW_DEVICE, &adcgrpcfgSlow, slowAdc.samples, ADC_BUF_DEPTH_SLOW); - chSysUnlockFromIsr() + chSysUnlockFromISR() ; #endif } @@ -179,7 +179,7 @@ static void pwmpcb_slow(PWMDriver *pwmp) { } static void pwmpcb_fast(PWMDriver *pwmp) { - efiAssertVoid(getRemainingStack(chThdSelf())> 32, "lwStAdcFast"); + efiAssertVoid(getRemainingStack(chThdGetSelfX())> 32, "lwStAdcFast"); #if EFI_INTERNAL_ADC (void) pwmp; @@ -188,19 +188,19 @@ static void pwmpcb_fast(PWMDriver *pwmp) { * will be executed in parallel to the current PWM cycle and will * terminate before the next PWM cycle. */ - chSysLockFromIsr() + chSysLockFromISR() ; if (ADC_FAST_DEVICE.state != ADC_READY && ADC_FAST_DEVICE.state != ADC_COMPLETE && ADC_FAST_DEVICE.state != ADC_ERROR) { fastAdc.errorsCount++; // todo: when? why? firmwareError(OBD_PCM_Processor_Fault, "ADC fast not ready?"); - chSysUnlockFromIsr() + chSysUnlockFromISR() ; return; } adcStartConversionI(&ADC_FAST_DEVICE, &adcgrpcfg_fast, fastAdc.samples, ADC_BUF_DEPTH_FAST); - chSysUnlockFromIsr() + chSysUnlockFromISR() ; fastAdc.conversionCount++; #endif @@ -483,7 +483,7 @@ static void setAdcDebugReporting(int value) { static void adc_callback_slow(ADCDriver *adcp, adcsample_t *buffer, size_t n) { (void) buffer; (void) n; - efiAssertVoid(getRemainingStack(chThdSelf()) > 128, "lowstck#9c"); + efiAssertVoid(getRemainingStack(chThdGetSelfX()) > 128, "lowstck#9c"); /* Note, only in the ADC_COMPLETE state because the ADC driver fires * an intermediate callback when the buffer is half full. */ if (adcp->state == ADC_COMPLETE) { diff --git a/firmware/hw_layer/microsecond_timer.cpp b/firmware/hw_layer/microsecond_timer.cpp index dc0c504507..54e4197ab8 100644 --- a/firmware/hw_layer/microsecond_timer.cpp +++ b/firmware/hw_layer/microsecond_timer.cpp @@ -87,10 +87,10 @@ static void callback(GPTDriver *gptp) { // // test code // setOutputPinValue(LED_CRANKING, timerCallbackCounter % 2); // int mod = timerCallbackCounter % 400; -// chSysLockFromIsr() +// chSysLockFromISR() // ; // setHardwareUsTimer(400 - mod); -// chSysUnlockFromIsr() +// chSysUnlockFromISR() // ; globalTimerCallback(NULL); diff --git a/firmware/rusefi.cpp b/firmware/rusefi.cpp index f4bdedc98d..913222b023 100644 --- a/firmware/rusefi.cpp +++ b/firmware/rusefi.cpp @@ -150,7 +150,7 @@ static void scheduleReboot(void) { } void runRusEfi(void) { - efiAssertVoid(getRemainingStack(chThdSelf()) > 512, "init s"); + efiAssertVoid(getRemainingStack(chThdGetSelfX()) > 512, "init s"); assertEngineReference(PASS_ENGINE_PARAMETER_F); initIntermediateLoggingBuffer(); initErrorHandling(); @@ -220,7 +220,7 @@ void runRusEfi(void) { * control is around main_trigger_callback */ while (true) { - efiAssertVoid(getRemainingStack(chThdSelf()) > 128, "stack#1"); + efiAssertVoid(getRemainingStack(chThdGetSelfX()) > 128, "stack#1"); #if (EFI_CLI_SUPPORT && !EFI_UART_ECHO_TEST_MODE) || defined(__DOXYGEN__) // sensor state + all pending messages for our own dev console @@ -231,7 +231,7 @@ void runRusEfi(void) { } } -void chDbgStackOverflowPanic(Thread *otp) { +void chDbgStackOverflowPanic(thread_t *otp) { strcpy(panicMessage, "stack overflow: "); #if defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) int p_name_len = strlen(otp->p_name); From a7cf2d82efedde9cccfa7ebb1ee2006b8d2ccd99 Mon Sep 17 00:00:00 2001 From: Fabien Poussin Date: Wed, 29 Mar 2017 18:15:10 +0200 Subject: [PATCH 16/74] Fix old lock_cnt and isr_cnt --- firmware/config/stm32f4ems/chconf.h | 5 ++--- firmware/hw_layer/stm32f4/mpu_util.cpp | 2 +- firmware/util/rfiutil.c | 3 --- 3 files changed, 3 insertions(+), 7 deletions(-) diff --git a/firmware/config/stm32f4ems/chconf.h b/firmware/config/stm32f4ems/chconf.h index 454e1e807a..d608f3345a 100644 --- a/firmware/config/stm32f4ems/chconf.h +++ b/firmware/config/stm32f4ems/chconf.h @@ -522,9 +522,8 @@ extern "C" #ifndef __ASSEMBLER__ #if !CH_DBG_SYSTEM_STATE_CHECK -extern cnt_t dbg_lock_cnt; -#define dbg_enter_lock() {dbg_lock_cnt = 1;ON_LOCK_HOOK;} -#define dbg_leave_lock() {ON_UNLOCK_HOOK;dbg_lock_cnt = 0;} +#define dbg_enter_lock() {ch.dbg.lock_cnt = 1;ON_LOCK_HOOK;} +#define dbg_leave_lock() {ON_UNLOCK_HOOK;ch.dbg.lock_cnt = 0;} #endif void chDbgPanic3(const char *msg, const char * file, int line); diff --git a/firmware/hw_layer/stm32f4/mpu_util.cpp b/firmware/hw_layer/stm32f4/mpu_util.cpp index 5e6ab5bd1a..72a8941565 100644 --- a/firmware/hw_layer/stm32f4/mpu_util.cpp +++ b/firmware/hw_layer/stm32f4/mpu_util.cpp @@ -59,7 +59,7 @@ extern uint32_t IRQSTACK$$Base; /* symbol created by the IAR linker */ int getRemainingStack(Thread *otp) { #if CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__) int remainingStack; - if (dbg_isr_cnt > 0) { + if (ch.dbg.isr_cnt > 0) { remainingStack = (__get_SP() - sizeof(intctx_t)) - (int)&IRQSTACK$$Base; } else { remainingStack = (__get_SP() - sizeof(intctx_t)) - (int)otp->p_stklimit; diff --git a/firmware/util/rfiutil.c b/firmware/util/rfiutil.c index cae4d239d6..bdad4981aa 100644 --- a/firmware/util/rfiutil.c +++ b/firmware/util/rfiutil.c @@ -75,6 +75,3 @@ void chVTSetAny(virtual_timer_t *vtp, systime_t time, vtfunc_t vtfunc, void *par } #endif - -cnt_t dbg_lock_cnt; -cnt_t dbg_isr_cnt; \ No newline at end of file From 33d78215ce390e0c477fe3b6afbbdb97dfb191cf Mon Sep 17 00:00:00 2001 From: rusefi Date: Wed, 29 Mar 2017 13:48:17 -0400 Subject: [PATCH 17/74] fixing simulator build script --- README.md | 8 ++++++++ win32_functional_tests/rules.mk | 2 +- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index ab3b905732..be5b629c9b 100644 --- a/README.md +++ b/README.md @@ -1,6 +1,7 @@ current binaries are always available at http://rusefi.com/build_server/ + #Releases | Release date | Revision | Details | @@ -53,3 +54,10 @@ General source code Q&A is at http://rusefi.com/forum/viewtopic.php?f=5&t=10 Facebook https://www.facebook.com/rusEfiECU youtube https://www.youtube.com/user/rusefi + + += How to build the code? = + +We now use submodules: + +git submodule update --init diff --git a/win32_functional_tests/rules.mk b/win32_functional_tests/rules.mk index 0e7132a118..dffded6894 100644 --- a/win32_functional_tests/rules.mk +++ b/win32_functional_tests/rules.mk @@ -74,7 +74,7 @@ ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS) ASXFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS) CFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS) CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS) -LDFLAGS = $(MCFLAGS) $(OPT) $(LLIBDIR) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,$(LDOPT) +LDFLAGS = $(MCFLAGS) $(OPT) $(LLIBDIR) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch$(LDOPT) # Generate dependency information ASFLAGS += -MD -MP -MF .dep/$(@F).d From 12b6ba655f13e2c6787e93e5173cc9f1cc5bc66f Mon Sep 17 00:00:00 2001 From: rusefi Date: Wed, 29 Mar 2017 16:58:49 -0400 Subject: [PATCH 18/74] taking fresh chibios --- firmware/ChibiOS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/firmware/ChibiOS b/firmware/ChibiOS index 3f25f7b5e9..820840273b 160000 --- a/firmware/ChibiOS +++ b/firmware/ChibiOS @@ -1 +1 @@ -Subproject commit 3f25f7b5e9e81dd6135c7df7c82782a685acf648 +Subproject commit 820840273b7f870dae339c53d9ad8a5591cdd061 From 084c3dc01f325200d73b47de073d72f3b6714024 Mon Sep 17 00:00:00 2001 From: rusefi Date: Wed, 29 Mar 2017 17:06:40 -0400 Subject: [PATCH 19/74] working on a better Makefile - incremental and contained to one folder --- firmware/compile_and_program.bat | 2 + win32_functional_tests/Makefile.inc | 248 ++++++++++++++++++++++++++++ 2 files changed, 250 insertions(+) create mode 100644 win32_functional_tests/Makefile.inc diff --git a/firmware/compile_and_program.bat b/firmware/compile_and_program.bat index 414e59871e..475ffc3af0 100644 --- a/firmware/compile_and_program.bat +++ b/firmware/compile_and_program.bat @@ -7,6 +7,8 @@ rm -rf build\rusefi.bin rem todo add rem git submodule update --init +rem PS: +rem git submodule update --recursive --remote rem magic once needed call update_version.bat diff --git a/win32_functional_tests/Makefile.inc b/win32_functional_tests/Makefile.inc new file mode 100644 index 0000000000..49450126ba --- /dev/null +++ b/win32_functional_tests/Makefile.inc @@ -0,0 +1,248 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO) +ifeq ($(USE_LTO),) + USE_LTO = no +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = rusefi_simulator +PROJECT_DIR = ../firmware +CHIBIOS = ../firmware/ChibiOS + + +# Imported source files and paths +CHIBIOS = ../firmware/ChibiOS + +# Startup files. +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/hal/boards/simulator/board.mk +include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/rt/ports/SIMIA32/compilers/GCC/port.mk +# Other files (optional). +include $(CHIBIOS)/os/hal/lib/streams/streams.mk +include $(CHIBIOS)/os/various/shell/shell.mk + +ifeq ($(OS),Windows_NT) + include ${CHIBIOS}/os/hal/ports/simulator/win32/platform.mk +else + include ${CHIBIOS}/os/hal/ports/simulator/Posix/platform.mk +endif + +include $(PROJECT_DIR)/util/util.mk +include $(PROJECT_DIR)/config/engines/engines.mk +include $(PROJECT_DIR)/controllers/algo/algo.mk +include $(PROJECT_DIR)/controllers/core/core.mk +include $(PROJECT_DIR)/controllers/math/math.mk +include $(PROJECT_DIR)/controllers/sensors/sensors.mk +include $(PROJECT_DIR)/controllers/trigger/trigger.mk +include $(PROJECT_DIR)/controllers/system/system.mk +include $(PROJECT_DIR)/console/console.mk +include $(PROJECT_DIR)/console/binary/tunerstudio.mk +include $(PROJECT_DIR)/development/development.mk + + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = ${PORTSRC} \ + ${KERNSRC} \ + ${HALSRC} \ + ${PLATFORMSRC} \ + $(SYSTEMSRC) \ + $(CONSOLESRC) \ + $(CONTROLLERS_ALGO_SRC) \ + $(CONTROLLERS_CORE_SRC) \ + $(CONTROLLERS_SENSORS_SRC) \ + $(ENGINES_SRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/hal/lib/streams/memstreams.c \ + $(CHIBIOS)/os/hal/lib/streams/chprintf.c \ + $(CHIBIOS)/os/various/shell.c \ + $(UTILSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(UTILSRC_CPP) \ + $(CONTROLLERS_ALGO_SRC_CPP) \ + $(PROJECT_DIR)/controllers/settings.cpp \ + $(PROJECT_DIR)/controllers/engine_controller.cpp \ + $(PROJECT_DIR)/controllers/error_handling.cpp \ + $(PROJECT_DIR)/development/sensor_chart.cpp \ + $(TRIGGER_SRC_CPP) \ + $(TRIGGER_DECODERS_SRC_CPP) \ + $(SYSTEMSRC_CPP) \ + $(TUNERSTUDIO_SRC_CPP) \ + $(CONSOLE_SRC_CPP) \ + $(CONTROLLERS_SENSORS_SRC_CPP) \ + $(CONTROLLERS_CORE_SRC_CPP) \ + $(CONTROLLERS_MATH_SRC_CPP) \ + $(DEV_SIMULATOR_SRC_CPP) \ + $(ENGINES_SRC_CPP) \ + simulator/rusEfiFunctionalTest.cpp \ + simulator/framework.cpp \ + simulator/boards.cpp \ + $(PROJECT_DIR)/controllers/map_averaging.cpp \ + $(PROJECT_DIR)/development/trigger_emulator.cpp \ + $(TEST_SRC_CPP) + + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = . \ + $(PORTINC) \ + $(KERNINC) \ + $(OSALINC) \ + $(HALINC) \ + $(PLATFORMINC) \ + $(BOARDINC) \ + $(PROJECT_DIR)/util \ + $(PROJECT_DIR)/console \ + $(PROJECT_DIR)/console/binary \ + $(PROJECT_DIR)/console/fl_binary \ + $(PROJECT_DIR)/config/engines \ + $(PROJECT_DIR)/ext_algo \ + $(PROJECT_DIR)/controllers \ + $(PROJECT_DIR)/hw_layer/algo \ + $(PROJECT_DIR)/development \ + $(PROJECT_DIR)/controllers/algo \ + $(PROJECT_DIR)/controllers/core \ + $(PROJECT_DIR)/controllers/math \ + $(PROJECT_DIR)/controllers/sensors \ + $(PROJECT_DIR)/controllers/system \ + $(PROJECT_DIR)/controllers/trigger \ + $(PROJECT_DIR)/controllers/trigger/decoders \ + ${CHIBIOS}/os/various \ + $(CHIBIOS)/os/hal/lib/streams \ + simulator + +# List ASM source files here +ASMSRC = +ASMXSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +ifeq ($(OS),Windows_NT) + #Cygwin64 is used with mingw64 32-bit version + + #TRGT = i686-w64-mingw32- + TRGT = i686-w64-mingw32- +else + TRGT = +endif + +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar +OD = $(TRGT)objdump +SZ = $(TRGT)size +BIN = $(CP) -O binary +COV = gcov + +# Define C warning options here +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra -Wundef + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = -DSIMULATOR + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = -lws2_32 + +# +# End of user defines +############################################################################## + +RULESPATH = $(CHIBIOS)/os/common/startup/SIMIA32/compilers/GCC +include $(RULESPATH)/rules.mk From e98dbc1218911ff059a363861820b72b08d615e1 Mon Sep 17 00:00:00 2001 From: rusefi Date: Wed, 29 Mar 2017 17:17:39 -0400 Subject: [PATCH 20/74] working on a better Makefile - incremental and contained to one folder --- win32_functional_tests/Makefile | 114 ++++++------- win32_functional_tests/Makefile.inc | 248 ---------------------------- 2 files changed, 47 insertions(+), 315 deletions(-) delete mode 100644 win32_functional_tests/Makefile.inc diff --git a/win32_functional_tests/Makefile b/win32_functional_tests/Makefile index 7786105a2d..49450126ba 100644 --- a/win32_functional_tests/Makefile +++ b/win32_functional_tests/Makefile @@ -5,45 +5,43 @@ # Compiler options here. ifeq ($(USE_OPT),) -# this config if debugging is needed, but the binary is about 50M -# USE_OPT = -c -Wall -O0 -ggdb -g3 -Werror-implicit-function-declaration -Werror -Wno-error=pointer-sign -Wno-error=unused-function -Wno-error=unused-variable -Wno-error=sign-compare -Wno-error=unused-parameter -Wno-error=missing-field-initializers -Wno-error=write-strings -# this config producec a smaller binary file -USE_OPT = -Os -endif - -ifeq ($(OS),Windows_NT) -else -USE_OPT += -m32 + USE_OPT = -O2 -ggdb endif # C specific options here (added to USE_OPT). ifeq ($(USE_COPT),) -USE_COPT = -std=gnu99 -fgnu89-inline -endif - -ifeq ($(OS),Windows_NT) -else -USE_COPT += -Wno-error=attributes -Wno-error=implicit-function-declaration -include stdio.h + USE_COPT = endif # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) -USE_CPPOPT = -std=c++11 -fno-rtti -fpermissive -fno-exceptions -fno-use-cxa-atexit + USE_CPPOPT = -fno-rtti endif -ifeq ($(OS),Windows_NT) -else -USE_CPPOPT += -include cstring -include cstdio -include cstdlib -endif - -# Enable this if you want the linker to remove unused code and data +# Enable this if you want the linker to remove unused code and data. ifeq ($(USE_LINK_GC),) USE_LINK_GC = yes endif +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO) +ifeq ($(USE_LTO),) + USE_LTO = no +endif + # Enable this if you want to see the full log while compiling. ifeq ($(USE_VERBOSE_COMPILE),) - USE_VERBOSE_COMPILE = yes + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes endif # @@ -54,10 +52,6 @@ endif # Architecture or project specific options # - -# List all default C defines here, like -D_DEBUG=1 -DDEFS = - # # Architecture or project specific options ############################################################################## @@ -65,17 +59,27 @@ DDEFS = ############################################################################## # Project, sources and paths # + # Define project name here PROJECT = rusefi_simulator PROJECT_DIR = ../firmware CHIBIOS = ../firmware/ChibiOS + # Imported source files and paths -include $(CHIBIOS)/os/hal/boards/simulator/board.mk +CHIBIOS = ../firmware/ChibiOS + +# Startup files. +# HAL-OSAL files (optional). include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/hal/boards/simulator/board.mk include $(CHIBIOS)/os/hal/osal/rt/osal.mk -include $(CHIBIOS)/os/rt/ports/SIMIA32/compilers/GCC/port.mk +# RTOS files (optional). include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/rt/ports/SIMIA32/compilers/GCC/port.mk +# Other files (optional). +include $(CHIBIOS)/os/hal/lib/streams/streams.mk +include $(CHIBIOS)/os/various/shell/shell.mk ifeq ($(OS),Windows_NT) include ${CHIBIOS}/os/hal/ports/simulator/win32/platform.mk @@ -95,9 +99,6 @@ include $(PROJECT_DIR)/console/console.mk include $(PROJECT_DIR)/console/binary/tunerstudio.mk include $(PROJECT_DIR)/development/development.mk -# Define linker script file here -#LDSCRIPT= config/system/STM32F407xG.ld -#LDSCRIPT= $(PORTLD)/STM32F407xG_CCM.ld # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. @@ -174,6 +175,10 @@ INCDIR = . \ $(CHIBIOS)/os/hal/lib/streams \ simulator +# List ASM source files here +ASMSRC = +ASMXSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) + # # Project, sources and paths ############################################################################## @@ -182,9 +187,6 @@ INCDIR = . \ # Compiler settings # -#MCU = cortex-m4 - - ifeq ($(OS),Windows_NT) #Cygwin64 is used with mingw64 32-bit version @@ -199,49 +201,26 @@ CPPC = $(TRGT)g++ # Enable loading with g++ only if you need C++ runtime support. # NOTE: You can use C++ even without C++ support if you are careful. C++ # runtime support makes code size explode. -#LD = $(TRGT)gcc -LD = $(TRGT)g++ +LD = $(TRGT)gcc +#LD = $(TRGT)g++ CP = $(TRGT)objcopy AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar OD = $(TRGT)objdump -HEX = $(CP) -O ihex +SZ = $(TRGT)size BIN = $(CP) -O binary +COV = gcov # Define C warning options here -CWARN = -Wall -Wextra -Wstrict-prototypes +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes # Define C++ warning options here -CPPWARN = -Wall -Wextra +CPPWARN = -Wall -Wextra -Wundef # # Compiler settings ############################################################################## -############################################################################## -# Start of default section -# - -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS = - -# List all default directories to look for include files here -DINCDIR = - -# List the default directory to look for the libraries here -DLIBDIR = - -# List all default libraries here -ifeq ($(OS),Windows_NT) - DLIBS = -static-libgcc -static-libstdc++ -lws2_32 -else - DLIBS = -static-libgcc -lgcc -static-libstdc++ -m32 -endif - - -# -# End of default section -############################################################################## - ############################################################################## # Start of user section # @@ -259,10 +238,11 @@ UINCDIR = ULIBDIR = # List all user libraries here -ULIBS = -lm +ULIBS = -lws2_32 # # End of user defines ############################################################################## -include rules.mk +RULESPATH = $(CHIBIOS)/os/common/startup/SIMIA32/compilers/GCC +include $(RULESPATH)/rules.mk diff --git a/win32_functional_tests/Makefile.inc b/win32_functional_tests/Makefile.inc deleted file mode 100644 index 49450126ba..0000000000 --- a/win32_functional_tests/Makefile.inc +++ /dev/null @@ -1,248 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -O2 -ggdb -endif - -# C specific options here (added to USE_OPT). -ifeq ($(USE_COPT),) - USE_COPT = -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data. -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# Linker extra options here. -ifeq ($(USE_LDOPT),) - USE_LDOPT = -endif - -# Enable this if you want link time optimizations (LTO) -ifeq ($(USE_LTO),) - USE_LTO = no -endif - -# Enable this if you want to see the full log while compiling. -ifeq ($(USE_VERBOSE_COMPILE),) - USE_VERBOSE_COMPILE = no -endif - -# If enabled, this option makes the build process faster by not compiling -# modules not used in the current configuration. -ifeq ($(USE_SMART_BUILD),) - USE_SMART_BUILD = yes -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Architecture or project specific options -# - -# -# Architecture or project specific options -############################################################################## - -############################################################################## -# Project, sources and paths -# - -# Define project name here -PROJECT = rusefi_simulator -PROJECT_DIR = ../firmware -CHIBIOS = ../firmware/ChibiOS - - -# Imported source files and paths -CHIBIOS = ../firmware/ChibiOS - -# Startup files. -# HAL-OSAL files (optional). -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/hal/boards/simulator/board.mk -include $(CHIBIOS)/os/hal/osal/rt/osal.mk -# RTOS files (optional). -include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/os/rt/ports/SIMIA32/compilers/GCC/port.mk -# Other files (optional). -include $(CHIBIOS)/os/hal/lib/streams/streams.mk -include $(CHIBIOS)/os/various/shell/shell.mk - -ifeq ($(OS),Windows_NT) - include ${CHIBIOS}/os/hal/ports/simulator/win32/platform.mk -else - include ${CHIBIOS}/os/hal/ports/simulator/Posix/platform.mk -endif - -include $(PROJECT_DIR)/util/util.mk -include $(PROJECT_DIR)/config/engines/engines.mk -include $(PROJECT_DIR)/controllers/algo/algo.mk -include $(PROJECT_DIR)/controllers/core/core.mk -include $(PROJECT_DIR)/controllers/math/math.mk -include $(PROJECT_DIR)/controllers/sensors/sensors.mk -include $(PROJECT_DIR)/controllers/trigger/trigger.mk -include $(PROJECT_DIR)/controllers/system/system.mk -include $(PROJECT_DIR)/console/console.mk -include $(PROJECT_DIR)/console/binary/tunerstudio.mk -include $(PROJECT_DIR)/development/development.mk - - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = ${PORTSRC} \ - ${KERNSRC} \ - ${HALSRC} \ - ${PLATFORMSRC} \ - $(SYSTEMSRC) \ - $(CONSOLESRC) \ - $(CONTROLLERS_ALGO_SRC) \ - $(CONTROLLERS_CORE_SRC) \ - $(CONTROLLERS_SENSORS_SRC) \ - $(ENGINES_SRC) \ - $(BOARDSRC) \ - $(CHIBIOS)/os/hal/lib/streams/memstreams.c \ - $(CHIBIOS)/os/hal/lib/streams/chprintf.c \ - $(CHIBIOS)/os/various/shell.c \ - $(UTILSRC) \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = $(UTILSRC_CPP) \ - $(CONTROLLERS_ALGO_SRC_CPP) \ - $(PROJECT_DIR)/controllers/settings.cpp \ - $(PROJECT_DIR)/controllers/engine_controller.cpp \ - $(PROJECT_DIR)/controllers/error_handling.cpp \ - $(PROJECT_DIR)/development/sensor_chart.cpp \ - $(TRIGGER_SRC_CPP) \ - $(TRIGGER_DECODERS_SRC_CPP) \ - $(SYSTEMSRC_CPP) \ - $(TUNERSTUDIO_SRC_CPP) \ - $(CONSOLE_SRC_CPP) \ - $(CONTROLLERS_SENSORS_SRC_CPP) \ - $(CONTROLLERS_CORE_SRC_CPP) \ - $(CONTROLLERS_MATH_SRC_CPP) \ - $(DEV_SIMULATOR_SRC_CPP) \ - $(ENGINES_SRC_CPP) \ - simulator/rusEfiFunctionalTest.cpp \ - simulator/framework.cpp \ - simulator/boards.cpp \ - $(PROJECT_DIR)/controllers/map_averaging.cpp \ - $(PROJECT_DIR)/development/trigger_emulator.cpp \ - $(TEST_SRC_CPP) - - -# List ASM source files here -ASMSRC = $(PORTASM) - -INCDIR = . \ - $(PORTINC) \ - $(KERNINC) \ - $(OSALINC) \ - $(HALINC) \ - $(PLATFORMINC) \ - $(BOARDINC) \ - $(PROJECT_DIR)/util \ - $(PROJECT_DIR)/console \ - $(PROJECT_DIR)/console/binary \ - $(PROJECT_DIR)/console/fl_binary \ - $(PROJECT_DIR)/config/engines \ - $(PROJECT_DIR)/ext_algo \ - $(PROJECT_DIR)/controllers \ - $(PROJECT_DIR)/hw_layer/algo \ - $(PROJECT_DIR)/development \ - $(PROJECT_DIR)/controllers/algo \ - $(PROJECT_DIR)/controllers/core \ - $(PROJECT_DIR)/controllers/math \ - $(PROJECT_DIR)/controllers/sensors \ - $(PROJECT_DIR)/controllers/system \ - $(PROJECT_DIR)/controllers/trigger \ - $(PROJECT_DIR)/controllers/trigger/decoders \ - ${CHIBIOS}/os/various \ - $(CHIBIOS)/os/hal/lib/streams \ - simulator - -# List ASM source files here -ASMSRC = -ASMXSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) - -# -# Project, sources and paths -############################################################################## - -############################################################################## -# Compiler settings -# - -ifeq ($(OS),Windows_NT) - #Cygwin64 is used with mingw64 32-bit version - - #TRGT = i686-w64-mingw32- - TRGT = i686-w64-mingw32- -else - TRGT = -endif - -CC = $(TRGT)gcc -CPPC = $(TRGT)g++ -# Enable loading with g++ only if you need C++ runtime support. -# NOTE: You can use C++ even without C++ support if you are careful. C++ -# runtime support makes code size explode. -LD = $(TRGT)gcc -#LD = $(TRGT)g++ -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -AR = $(TRGT)ar -OD = $(TRGT)objdump -SZ = $(TRGT)size -BIN = $(CP) -O binary -COV = gcov - -# Define C warning options here -CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes - -# Define C++ warning options here -CPPWARN = -Wall -Wextra -Wundef - -# -# Compiler settings -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = -DSIMULATOR - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = - -# List the user directory to look for the libraries here -ULIBDIR = - -# List all user libraries here -ULIBS = -lws2_32 - -# -# End of user defines -############################################################################## - -RULESPATH = $(CHIBIOS)/os/common/startup/SIMIA32/compilers/GCC -include $(RULESPATH)/rules.mk From 1bd29111ad170e96601a41cac1f032a669c50735 Mon Sep 17 00:00:00 2001 From: rusefi Date: Wed, 29 Mar 2017 18:29:36 -0400 Subject: [PATCH 21/74] gdb option --- win32_functional_tests/Makefile | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/win32_functional_tests/Makefile b/win32_functional_tests/Makefile index 49450126ba..89b611ccae 100644 --- a/win32_functional_tests/Makefile +++ b/win32_functional_tests/Makefile @@ -5,7 +5,15 @@ # Compiler options here. ifeq ($(USE_OPT),) - USE_OPT = -O2 -ggdb +# this config if debugging is needed, but the binary is about 50M +# USE_OPT = -c -Wall -O0 -ggdb -g3 -Werror-implicit-function-declaration -Werror -Wno-error=pointer-sign -Wno-error=unused-function -Wno-error=unused-variable -Wno-error=sign-compare -Wno-error=unused-parameter -Wno-error=missing-field-initializers -Wno-error=write-strings +# this config producec a smaller binary file + USE_OPT = -c -Wall -O2 -Werror-implicit-function-declaration -Wno-error=pointer-sign -Wno-error=unused-function -Wno-error=unused-variable -Wno-error=sign-compare -Wno-error=unused-parameter -Wno-error=missing-field-initializers -Wno-error=write-strings -Wno-error=strict-aliasing + + ifeq ($(OS),Windows_NT) + else + USE_OPT += -m32 + endif endif # C specific options here (added to USE_OPT). From 89a0d7ce1e135fb6bb2dd18f7c8eb726d5c530ab Mon Sep 17 00:00:00 2001 From: rusefi Date: Wed, 29 Mar 2017 18:55:38 -0400 Subject: [PATCH 22/74] making USB serial conditional --- firmware/hw_layer/serial_over_usb/usbcfg.c | 6 +++++- firmware/hw_layer/serial_over_usb/usbconsole.c | 2 +- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/firmware/hw_layer/serial_over_usb/usbcfg.c b/firmware/hw_layer/serial_over_usb/usbcfg.c index 262f3f6f2b..ee8e1c8f17 100644 --- a/firmware/hw_layer/serial_over_usb/usbcfg.c +++ b/firmware/hw_layer/serial_over_usb/usbcfg.c @@ -14,7 +14,9 @@ limitations under the License. */ -#include "hal.h" +#include "main.h" + +#if HAL_USE_SERIAL_USB || defined(__DOXYGEN__) /* Virtual serial port over USB.*/ SerialUSBDriver SDU1; @@ -334,3 +336,5 @@ const SerialUSBConfig serusbcfg = { USBD1_DATA_AVAILABLE_EP, USBD1_INTERRUPT_REQUEST_EP }; + +#endif /* EFI_USB_SERIAL */ diff --git a/firmware/hw_layer/serial_over_usb/usbconsole.c b/firmware/hw_layer/serial_over_usb/usbconsole.c index 29746e12a6..57547131ce 100644 --- a/firmware/hw_layer/serial_over_usb/usbconsole.c +++ b/firmware/hw_layer/serial_over_usb/usbconsole.c @@ -46,4 +46,4 @@ bool is_usb_serial_ready(void) { return false; } -#endif +#endif /* EFI_USB_SERIAL */ From 4776e72123a0554a7ff113978dbe773708fefa85 Mon Sep 17 00:00:00 2001 From: rusefi Date: Wed, 29 Mar 2017 18:56:03 -0400 Subject: [PATCH 23/74] will deal with this later --- firmware/hw_layer/accelerometer.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/firmware/hw_layer/accelerometer.cpp b/firmware/hw_layer/accelerometer.cpp index 9b9c36a453..828a2b00d4 100644 --- a/firmware/hw_layer/accelerometer.cpp +++ b/firmware/hw_layer/accelerometer.cpp @@ -6,7 +6,7 @@ */ #include "main.h" -#include "lis302dl.h" +//#include "lis302dl.h" void initAccelerometer(DECLARE_ENGINE_PARAMETER_F) { From 86d19d0ccc71b9585e24a6f5a5af2f1e21791067 Mon Sep 17 00:00:00 2001 From: rusefi Date: Wed, 29 Mar 2017 19:17:12 -0400 Subject: [PATCH 24/74] stricter def requirments --- firmware/config/engines/audi_aan.h | 1 + firmware/config/engines/snow_blower.h | 2 ++ 2 files changed, 3 insertions(+) diff --git a/firmware/config/engines/audi_aan.h b/firmware/config/engines/audi_aan.h index 5e1edb7c94..28ba423dc9 100644 --- a/firmware/config/engines/audi_aan.h +++ b/firmware/config/engines/audi_aan.h @@ -9,6 +9,7 @@ #ifndef AUDI_AAN_H_ #define AUDI_AAN_H_ +#include "global.h" #if EFI_ENGINE_AUDI_AAN #endif /* EFI_ENGINE_AUDI_AAN */ diff --git a/firmware/config/engines/snow_blower.h b/firmware/config/engines/snow_blower.h index f33e2e468e..16242dfbcb 100644 --- a/firmware/config/engines/snow_blower.h +++ b/firmware/config/engines/snow_blower.h @@ -9,6 +9,8 @@ #ifndef SNOW_BLOWER_H_ #define SNOW_BLOWER_H_ +#include "global.h" + #if EFI_ENGINE_SNOW_BLOWER #endif /* EFI_ENGINE_SNOW_BLOWER */ From b904710b12efcff55dca97b559b2d626b57e532c Mon Sep 17 00:00:00 2001 From: rusefi Date: Wed, 29 Mar 2017 19:17:48 -0400 Subject: [PATCH 25/74] stricted def requirments --- firmware/controllers/algo/error_handling.h | 1 + 1 file changed, 1 insertion(+) diff --git a/firmware/controllers/algo/error_handling.h b/firmware/controllers/algo/error_handling.h index 6821b7d212..6adc656ff7 100644 --- a/firmware/controllers/algo/error_handling.h +++ b/firmware/controllers/algo/error_handling.h @@ -13,6 +13,7 @@ extern "C" { #endif /* __cplusplus */ +#include "global.h" #include "obd_error_codes.h" #include "efifeatures.h" #include "stdbool.h" From 8a5f3eb38c976eebe859f2e2a978540666bd60cd Mon Sep 17 00:00:00 2001 From: rusefi Date: Wed, 29 Mar 2017 19:18:27 -0400 Subject: [PATCH 26/74] stricter def requirments --- firmware/util/listener_array.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/firmware/util/listener_array.cpp b/firmware/util/listener_array.cpp index 18fa87b7ea..f6390dce16 100644 --- a/firmware/util/listener_array.cpp +++ b/firmware/util/listener_array.cpp @@ -5,6 +5,6 @@ * @author Andrey Belomutskiy, (c) 2012-2017 */ -#include "listener_array.h" #include "main.h" +#include "listener_array.h" From d99c529f91897b519fbbe6ca283c7f94dd2bcd98 Mon Sep 17 00:00:00 2001 From: rusefi Date: Wed, 29 Mar 2017 19:48:16 -0400 Subject: [PATCH 27/74] tagging success --- firmware/svnversion.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/firmware/svnversion.h b/firmware/svnversion.h index 5e45f8ef55..8ba459ecd2 100644 --- a/firmware/svnversion.h +++ b/firmware/svnversion.h @@ -1,5 +1,5 @@ // This file was generated by Version2Header -// Mon Mar 20 18:51:25 EDT 2017 +// Wed Mar 29 19:43:20 EDT 2017 #ifndef VCS_VERSION -#define VCS_VERSION "13225" +#define VCS_VERSION "13395" #endif From eda9751bbd22a7ce8702854e2df7763084414123 Mon Sep 17 00:00:00 2001 From: rusefi Date: Wed, 29 Mar 2017 20:19:40 -0400 Subject: [PATCH 28/74] moving from discovery to brain board --- firmware/Makefile | 2 +- firmware/config/boards/ST_STM32F4/board.c | 45 +- firmware/config/boards/ST_STM32F4/board.h | 742 ++++----- .../boards/ST_STM32F4_DISCOVERY/board.c | 129 -- .../boards/ST_STM32F4_DISCOVERY/board.h | 1343 ----------------- .../boards/ST_STM32F4_DISCOVERY/board.mk | 5 - 6 files changed, 428 insertions(+), 1838 deletions(-) delete mode 100644 firmware/config/boards/ST_STM32F4_DISCOVERY/board.c delete mode 100644 firmware/config/boards/ST_STM32F4_DISCOVERY/board.h delete mode 100644 firmware/config/boards/ST_STM32F4_DISCOVERY/board.mk diff --git a/firmware/Makefile b/firmware/Makefile index 4eb63f0c7c..55f41243e0 100644 --- a/firmware/Makefile +++ b/firmware/Makefile @@ -91,7 +91,7 @@ CHIBIOS = ChibiOS CHIBIOS_CONTRIB = ChibiOS-Contrib ifneq ($(PROJECT_BOARD),OLIMEX_STM32_E407) - PROJECT_BOARD = ST_STM32F4_DISCOVERY + PROJECT_BOARD = ST_STM32F4 endif DDEFS += -D$(PROJECT_BOARD) diff --git a/firmware/config/boards/ST_STM32F4/board.c b/firmware/config/boards/ST_STM32F4/board.c index 087ff3f6a2..4b26d39f8a 100644 --- a/firmware/config/boards/ST_STM32F4/board.c +++ b/firmware/config/boards/ST_STM32F4/board.c @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -14,7 +14,11 @@ limitations under the License. */ -#include "ch.h" +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + #include "hal.h" #if HAL_USE_PAL || defined(__DOXYGEN__) @@ -23,26 +27,43 @@ * @details Digital I/O ports static configuration as defined in @p board.h. * This variable is used by the HAL when initializing the PAL driver. */ -const PALConfig pal_default_config = -{ +const PALConfig pal_default_config = { +#if STM32_HAS_GPIOA {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, +#endif +#if STM32_HAS_GPIOB {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, +#endif +#if STM32_HAS_GPIOC {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, +#endif +#if STM32_HAS_GPIOD {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, +#endif +#if STM32_HAS_GPIOE {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, +#endif +#if STM32_HAS_GPIOF {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, +#endif +#if STM32_HAS_GPIOG {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, +#endif +#if STM32_HAS_GPIOH {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, +#endif +#if STM32_HAS_GPIOI {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH} +#endif }; #endif @@ -60,21 +81,21 @@ void __early_init(void) { /** * @brief SDC card detection. */ -bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) { +bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { (void)sdcp; /* TODO: Fill the implementation.*/ - return TRUE; + return true; } /** * @brief SDC card write protection detection. */ -bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) { +bool sdc_lld_is_write_protected(SDCDriver *sdcp) { (void)sdcp; /* TODO: Fill the implementation.*/ - return FALSE; + return false; } #endif /* HAL_USE_SDC */ @@ -82,21 +103,21 @@ bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) { /** * @brief MMC_SPI card detection. */ -bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) { +bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { (void)mmcp; /* TODO: Fill the implementation.*/ - return TRUE; + return true; } /** * @brief MMC_SPI card write protection detection. */ -bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) { +bool mmc_lld_is_write_protected(MMCDriver *mmcp) { (void)mmcp; /* TODO: Fill the implementation.*/ - return FALSE; + return false; } #endif diff --git a/firmware/config/boards/ST_STM32F4/board.h b/firmware/config/boards/ST_STM32F4/board.h index c56d40a7dd..3fe30786b5 100644 --- a/firmware/config/boards/ST_STM32F4/board.h +++ b/firmware/config/boards/ST_STM32F4/board.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -14,8 +14,13 @@ limitations under the License. */ -#ifndef _BOARD_H_ -#define _BOARD_H_ +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#ifndef BOARD_H +#define BOARD_H /* * Setup for STMicroelectronics STM32F4-Discovery board. @@ -25,32 +30,30 @@ * Board identifier. */ #define BOARD_ST_STM32F4_DISCOVERY -#define BOARD_NAME "STMicroelectronics STM32F4-Discovery" - -#define STM32_LSECLK 32768 +#define BOARD_NAME "STM32F4-Discovery for RusEFI" /* * Board oscillators-related settings. * NOTE: LSE not fitted. */ #if !defined(STM32_LSECLK) -#define STM32_LSECLK 0 +#define STM32_LSECLK 32768U #endif #if !defined(STM32_HSECLK) -#define STM32_HSECLK 8000000 +#define STM32_HSECLK 8000000U #endif /* * Board voltages. * Required for performance limits calculation. */ -#define STM32_VDD 300 +#define STM32_VDD 300U /* * MCU type as defined in the ST header. */ -#define STM32F40_41xxx +#define STM32F407xx /* * IO pins assignments. @@ -208,27 +211,70 @@ #define GPIOI_PIN14 14 #define GPIOI_PIN15 15 +/* + * IO lines assignments. + */ +#define LINE_BUTTON PAL_LINE(GPIOA, 0U) +#define LINE_LRCK PAL_LINE(GPIOA, 4U) +#define LINE_SPC PAL_LINE(GPIOA, 5U) +#define LINE_SDO PAL_LINE(GPIOA, 6U) +#define LINE_SDI PAL_LINE(GPIOA, 7U) +#define LINE_VBUS_FS PAL_LINE(GPIOA, 9U) +#define LINE_OTG_FS_ID PAL_LINE(GPIOA, 10U) +#define LINE_OTG_FS_DM PAL_LINE(GPIOA, 11U) +#define LINE_OTG_FS_DP PAL_LINE(GPIOA, 12U) +#define LINE_SWDIO PAL_LINE(GPIOA, 13U) +#define LINE_SWCLK PAL_LINE(GPIOA, 14U) + +#define LINE_SWO PAL_LINE(GPIOB, 3U) +#define LINE_SCL PAL_LINE(GPIOB, 6U) +#define LINE_SDA PAL_LINE(GPIOB, 9U) +#define LINE_CLK_IN PAL_LINE(GPIOB, 10U) + +#define LINE_OTG_FS_POWER_ON PAL_LINE(GPIOC, 0U) +#define LINE_PDM_OUT PAL_LINE(GPIOC, 3U) +#define LINE_MCLK PAL_LINE(GPIOC, 7U) +#define LINE_SCLK PAL_LINE(GPIOC, 10U) +#define LINE_SDIN PAL_LINE(GPIOC, 12U) + +#define LINE_RESET PAL_LINE(GPIOD, 4U) +#define LINE_OVER_CURRENT PAL_LINE(GPIOD, 5U) +#define LINE_LED4 PAL_LINE(GPIOD, 12U) +#define LINE_LED3 PAL_LINE(GPIOD, 13U) +#define LINE_LED5 PAL_LINE(GPIOD, 14U) +#define LINE_LED6 PAL_LINE(GPIOD, 15U) + +#define LINE_INT1 PAL_LINE(GPIOE, 0U) +#define LINE_INT2 PAL_LINE(GPIOE, 1U) +#define LINE_CS_SPI PAL_LINE(GPIOE, 3U) + + + +#define LINE_OSC_IN PAL_LINE(GPIOH, 0U) +#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U) + + /* * I/O ports initial setup, this configuration is established soon after reset * in the initialization code. * Please refer to the STM32 Reference Manual for details. */ -#define PIN_MODE_INPUT(n) (0U << ((n) * 2)) -#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2)) -#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2)) -#define PIN_MODE_ANALOG(n) (3U << ((n) * 2)) +#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) #define PIN_ODR_LOW(n) (0U << (n)) #define PIN_ODR_HIGH(n) (1U << (n)) #define PIN_OTYPE_PUSHPULL(n) (0U << (n)) #define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) -#define PIN_OSPEED_2M(n) (0U << ((n) * 2)) -#define PIN_OSPEED_25M(n) (1U << ((n) * 2)) -#define PIN_OSPEED_50M(n) (2U << ((n) * 2)) -#define PIN_OSPEED_100M(n) (3U << ((n) * 2)) -#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2)) -#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2)) -#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2)) -#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4)) +#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) +#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) +#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) +#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) +#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) /* * GPIOA setup: @@ -282,22 +328,22 @@ PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) -#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_100M(GPIOA_BUTTON) | \ - PIN_OSPEED_100M(GPIOA_PIN1) | \ - PIN_OSPEED_100M(GPIOA_PIN2) | \ - PIN_OSPEED_100M(GPIOA_PIN3) | \ - PIN_OSPEED_100M(GPIOA_LRCK) | \ - PIN_OSPEED_50M(GPIOA_SPC) | \ - PIN_OSPEED_50M(GPIOA_SDO) | \ - PIN_OSPEED_50M(GPIOA_SDI) | \ - PIN_OSPEED_100M(GPIOA_PIN8) | \ - PIN_OSPEED_100M(GPIOA_VBUS_FS) | \ - PIN_OSPEED_100M(GPIOA_OTG_FS_ID) | \ - PIN_OSPEED_100M(GPIOA_OTG_FS_DM) | \ - PIN_OSPEED_100M(GPIOA_OTG_FS_DP) | \ - PIN_OSPEED_100M(GPIOA_SWDIO) | \ - PIN_OSPEED_100M(GPIOA_SWCLK) | \ - PIN_OSPEED_100M(GPIOA_PIN15)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_BUTTON) | \ + PIN_OSPEED_HIGH(GPIOA_PIN1) | \ + PIN_OSPEED_HIGH(GPIOA_PIN2) | \ + PIN_OSPEED_HIGH(GPIOA_PIN3) | \ + PIN_OSPEED_HIGH(GPIOA_LRCK) | \ + PIN_OSPEED_MEDIUM(GPIOA_SPC) | \ + PIN_OSPEED_MEDIUM(GPIOA_SDO) | \ + PIN_OSPEED_MEDIUM(GPIOA_SDI) | \ + PIN_OSPEED_HIGH(GPIOA_PIN8) | \ + PIN_OSPEED_HIGH(GPIOA_VBUS_FS) | \ + PIN_OSPEED_HIGH(GPIOA_OTG_FS_ID) | \ + PIN_OSPEED_HIGH(GPIOA_OTG_FS_DM) | \ + PIN_OSPEED_HIGH(GPIOA_OTG_FS_DP) | \ + PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ + PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ + PIN_OSPEED_HIGH(GPIOA_PIN15)) #define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_BUTTON) | \ PIN_PUPDR_PULLUP(GPIOA_PIN1) | \ PIN_PUPDR_PULLUP(GPIOA_PIN2) | \ @@ -330,22 +376,22 @@ PIN_ODR_HIGH(GPIOA_SWDIO) | \ PIN_ODR_HIGH(GPIOA_SWCLK) | \ PIN_ODR_HIGH(GPIOA_PIN15)) -#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON, 0) | \ - PIN_AFIO_AF(GPIOA_PIN1, 0) | \ - PIN_AFIO_AF(GPIOA_PIN2, 0) | \ - PIN_AFIO_AF(GPIOA_PIN3, 0) | \ - PIN_AFIO_AF(GPIOA_LRCK, 6) | \ - PIN_AFIO_AF(GPIOA_SPC, 5) | \ - PIN_AFIO_AF(GPIOA_SDO, 5) | \ - PIN_AFIO_AF(GPIOA_SDI, 5)) -#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0) | \ - PIN_AFIO_AF(GPIOA_VBUS_FS, 0) | \ - PIN_AFIO_AF(GPIOA_OTG_FS_ID, 10) | \ - PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) | \ - PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) | \ - PIN_AFIO_AF(GPIOA_SWDIO, 0) | \ - PIN_AFIO_AF(GPIOA_SWCLK, 0) | \ - PIN_AFIO_AF(GPIOA_PIN15, 0)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOA_LRCK, 6U) | \ + PIN_AFIO_AF(GPIOA_SPC, 5U) | \ + PIN_AFIO_AF(GPIOA_SDO, 5U) | \ + PIN_AFIO_AF(GPIOA_SDI, 5U)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOA_VBUS_FS, 0U) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_ID, 10U) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10U) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10U) | \ + PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ + PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN15, 0U)) /* * GPIOB setup: @@ -376,8 +422,8 @@ PIN_MODE_ALTERNATE(GPIOB_SCL) | \ PIN_MODE_INPUT(GPIOB_PIN7) | \ PIN_MODE_INPUT(GPIOB_PIN8) | \ - PIN_MODE_INPUT(GPIOB_PIN9) | \ - PIN_MODE_INPUT(GPIOB_PIN10) | \ + PIN_MODE_INPUT(GPIOB_PIN9) | \ + PIN_MODE_INPUT(GPIOB_PIN10) | \ PIN_MODE_INPUT(GPIOB_PIN11) | \ PIN_MODE_INPUT(GPIOB_PIN12) | \ PIN_MODE_INPUT(GPIOB_PIN13) | \ @@ -389,7 +435,7 @@ PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \ PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \ PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOB_SCL) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_SCL) | \ PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \ PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \ PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \ @@ -399,28 +445,28 @@ PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \ PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) -#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_100M(GPIOB_PIN0) | \ - PIN_OSPEED_100M(GPIOB_PIN1) | \ - PIN_OSPEED_100M(GPIOB_PIN2) | \ - PIN_OSPEED_100M(GPIOB_SWO) | \ - PIN_OSPEED_100M(GPIOB_PIN4) | \ - PIN_OSPEED_100M(GPIOB_PIN5) | \ - PIN_OSPEED_100M(GPIOB_SCL) | \ - PIN_OSPEED_100M(GPIOB_PIN7) | \ - PIN_OSPEED_100M(GPIOB_PIN8) | \ - PIN_OSPEED_100M(GPIOB_PIN9) | \ - PIN_OSPEED_100M(GPIOB_PIN10) | \ - PIN_OSPEED_100M(GPIOB_PIN11) | \ - PIN_OSPEED_100M(GPIOB_PIN12) | \ - PIN_OSPEED_100M(GPIOB_PIN13) | \ - PIN_OSPEED_100M(GPIOB_PIN14) | \ - PIN_OSPEED_100M(GPIOB_PIN15)) -#define VAL_GPIOB_PUPDR (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_PIN0) | \ + PIN_OSPEED_HIGH(GPIOB_PIN1) | \ + PIN_OSPEED_HIGH(GPIOB_PIN2) | \ + PIN_OSPEED_HIGH(GPIOB_SWO) | \ + PIN_OSPEED_HIGH(GPIOB_PIN4) | \ + PIN_OSPEED_HIGH(GPIOB_PIN5) | \ + PIN_OSPEED_HIGH(GPIOB_SCL) | \ + PIN_OSPEED_HIGH(GPIOB_PIN7) | \ + PIN_OSPEED_HIGH(GPIOB_PIN8) | \ + PIN_OSPEED_HIGH(GPIOB_PIN9) | \ + PIN_OSPEED_HIGH(GPIOB_PIN10) | \ + PIN_OSPEED_HIGH(GPIOB_PIN11) | \ + PIN_OSPEED_HIGH(GPIOB_PIN12) | \ + PIN_OSPEED_HIGH(GPIOB_PIN13) | \ + PIN_OSPEED_HIGH(GPIOB_PIN14) | \ + PIN_OSPEED_HIGH(GPIOB_PIN15)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN2) | \ PIN_PUPDR_FLOATING(GPIOB_SWO) | \ - PIN_PUPDR_PULLDOWN(GPIOB_PIN4) | \ - PIN_PUPDR_PULLDOWN(GPIOB_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN5) | \ PIN_PUPDR_FLOATING(GPIOB_SCL) | \ PIN_PUPDR_PULLDOWN(GPIOB_PIN7) | \ PIN_PUPDR_PULLDOWN(GPIOB_PIN8) | \ @@ -447,22 +493,22 @@ PIN_ODR_HIGH(GPIOB_PIN13) | \ PIN_ODR_HIGH(GPIOB_PIN14) | \ PIN_ODR_HIGH(GPIOB_PIN15)) -#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0) | \ - PIN_AFIO_AF(GPIOB_PIN1, 0) | \ - PIN_AFIO_AF(GPIOB_PIN2, 0) | \ - PIN_AFIO_AF(GPIOB_SWO, 0) | \ - PIN_AFIO_AF(GPIOB_PIN4, 0) | \ - PIN_AFIO_AF(GPIOB_PIN5, 0) | \ - PIN_AFIO_AF(GPIOB_SCL, 4) | \ - PIN_AFIO_AF(GPIOB_PIN7, 0)) -#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0) | \ - PIN_AFIO_AF(GPIOB_PIN9, 4) | \ - PIN_AFIO_AF(GPIOB_PIN10, 0) | \ - PIN_AFIO_AF(GPIOB_PIN11, 0) | \ - PIN_AFIO_AF(GPIOB_PIN12, 0) | \ - PIN_AFIO_AF(GPIOB_PIN13, 0) | \ - PIN_AFIO_AF(GPIOB_PIN14, 0) | \ - PIN_AFIO_AF(GPIOB_PIN15, 0)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOB_SWO, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOB_SCL, 4U) | \ + PIN_AFIO_AF(GPIOB_PIN7, 0U)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN15, 0U)) /* * GPIOC setup: @@ -512,26 +558,26 @@ PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \ PIN_OTYPE_PUSHPULL(GPIOC_PIN15)) -#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_100M(GPIOC_OTG_FS_POWER_ON) |\ - PIN_OSPEED_100M(GPIOC_PIN1) | \ - PIN_OSPEED_100M(GPIOC_PIN2) | \ - PIN_OSPEED_100M(GPIOC_PIN3) | \ - PIN_OSPEED_100M(GPIOC_PIN4) | \ - PIN_OSPEED_100M(GPIOC_PIN5) | \ - PIN_OSPEED_100M(GPIOC_PIN6) | \ - PIN_OSPEED_100M(GPIOC_PIN7) | \ - PIN_OSPEED_100M(GPIOC_PIN8) | \ - PIN_OSPEED_100M(GPIOC_PIN9) | \ - PIN_OSPEED_100M(GPIOC_PIN10) | \ - PIN_OSPEED_100M(GPIOC_PIN11) | \ - PIN_OSPEED_100M(GPIOC_PIN12) | \ - PIN_OSPEED_100M(GPIOC_PIN13) | \ - PIN_OSPEED_100M(GPIOC_PIN14) | \ - PIN_OSPEED_100M(GPIOC_PIN15)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_OTG_FS_POWER_ON) |\ + PIN_OSPEED_HIGH(GPIOC_PIN1) | \ + PIN_OSPEED_HIGH(GPIOC_PIN2) | \ + PIN_OSPEED_HIGH(GPIOC_PIN3) | \ + PIN_OSPEED_HIGH(GPIOC_PIN4) | \ + PIN_OSPEED_HIGH(GPIOC_PIN5) | \ + PIN_OSPEED_HIGH(GPIOC_PIN6) | \ + PIN_OSPEED_HIGH(GPIOC_PIN7) | \ + PIN_OSPEED_HIGH(GPIOC_PIN8) | \ + PIN_OSPEED_HIGH(GPIOC_PIN9) | \ + PIN_OSPEED_HIGH(GPIOC_PIN10) | \ + PIN_OSPEED_HIGH(GPIOC_PIN11) | \ + PIN_OSPEED_HIGH(GPIOC_PIN12) | \ + PIN_OSPEED_HIGH(GPIOC_PIN13) | \ + PIN_OSPEED_HIGH(GPIOC_PIN14) | \ + PIN_OSPEED_HIGH(GPIOC_PIN15)) #define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_OTG_FS_POWER_ON) |\ PIN_PUPDR_PULLDOWN(GPIOC_PIN1) | \ PIN_PUPDR_PULLDOWN(GPIOC_PIN2) | \ @@ -564,22 +610,22 @@ PIN_ODR_HIGH(GPIOC_PIN13) | \ PIN_ODR_HIGH(GPIOC_PIN14) | \ PIN_ODR_HIGH(GPIOC_PIN15)) -#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_OTG_FS_POWER_ON, 0) |\ - PIN_AFIO_AF(GPIOC_PIN1, 0) | \ - PIN_AFIO_AF(GPIOC_PIN2, 0) | \ - PIN_AFIO_AF(GPIOC_PIN3, 0) | \ - PIN_AFIO_AF(GPIOC_PIN4, 0) | \ - PIN_AFIO_AF(GPIOC_PIN5, 0) | \ - PIN_AFIO_AF(GPIOC_PIN6, 0) | \ - PIN_AFIO_AF(GPIOC_PIN7, 6)) -#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0) | \ - PIN_AFIO_AF(GPIOC_PIN9, 0) | \ - PIN_AFIO_AF(GPIOC_PIN10, 6) | \ - PIN_AFIO_AF(GPIOC_PIN11, 0) | \ - PIN_AFIO_AF(GPIOC_PIN12, 6) | \ - PIN_AFIO_AF(GPIOC_PIN13, 0) | \ - PIN_AFIO_AF(GPIOC_PIN14, 0) | \ - PIN_AFIO_AF(GPIOC_PIN15, 0)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_OTG_FS_POWER_ON, 0U) |\ + PIN_AFIO_AF(GPIOC_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN7, 0U)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN15, 0U)) /* * GPIOD setup: @@ -633,32 +679,32 @@ PIN_OTYPE_PUSHPULL(GPIOD_LED3) | \ PIN_OTYPE_PUSHPULL(GPIOD_LED5) | \ PIN_OTYPE_PUSHPULL(GPIOD_LED6)) -#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_100M(GPIOD_PIN0) | \ - PIN_OSPEED_100M(GPIOD_PIN1) | \ - PIN_OSPEED_100M(GPIOD_PIN2) | \ - PIN_OSPEED_100M(GPIOD_PIN3) | \ - PIN_OSPEED_100M(GPIOD_RESET) | \ - PIN_OSPEED_100M(GPIOD_OVER_CURRENT) | \ - PIN_OSPEED_100M(GPIOD_PIN6) | \ - PIN_OSPEED_100M(GPIOD_PIN7) | \ - PIN_OSPEED_100M(GPIOD_PIN8) | \ - PIN_OSPEED_100M(GPIOD_PIN9) | \ - PIN_OSPEED_100M(GPIOD_PIN10) | \ - PIN_OSPEED_100M(GPIOD_PIN11) | \ - PIN_OSPEED_100M(GPIOD_LED4) | \ - PIN_OSPEED_100M(GPIOD_LED3) | \ - PIN_OSPEED_100M(GPIOD_LED5) | \ - PIN_OSPEED_100M(GPIOD_LED6)) -#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLDOWN(GPIOD_PIN0) | \ - PIN_PUPDR_PULLDOWN(GPIOD_PIN1) | \ - PIN_PUPDR_PULLDOWN(GPIOD_PIN2) | \ - PIN_PUPDR_PULLDOWN(GPIOD_PIN3) | \ +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \ + PIN_OSPEED_HIGH(GPIOD_PIN1) | \ + PIN_OSPEED_HIGH(GPIOD_PIN2) | \ + PIN_OSPEED_HIGH(GPIOD_PIN3) | \ + PIN_OSPEED_HIGH(GPIOD_RESET) | \ + PIN_OSPEED_HIGH(GPIOD_OVER_CURRENT) | \ + PIN_OSPEED_HIGH(GPIOD_PIN6) | \ + PIN_OSPEED_HIGH(GPIOD_PIN7) | \ + PIN_OSPEED_HIGH(GPIOD_PIN8) | \ + PIN_OSPEED_HIGH(GPIOD_PIN9) | \ + PIN_OSPEED_HIGH(GPIOD_PIN10) | \ + PIN_OSPEED_HIGH(GPIOD_PIN11) | \ + PIN_OSPEED_HIGH(GPIOD_LED4) | \ + PIN_OSPEED_HIGH(GPIOD_LED3) | \ + PIN_OSPEED_HIGH(GPIOD_LED5) | \ + PIN_OSPEED_HIGH(GPIOD_LED6)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN3) | \ PIN_PUPDR_FLOATING(GPIOD_RESET) | \ PIN_PUPDR_FLOATING(GPIOD_OVER_CURRENT) |\ - PIN_PUPDR_PULLDOWN(GPIOD_PIN6) | \ - PIN_PUPDR_PULLDOWN(GPIOD_PIN7) | \ - PIN_PUPDR_PULLDOWN(GPIOD_PIN8) | \ - PIN_PUPDR_PULLDOWN(GPIOD_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN9) | \ PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ PIN_PUPDR_PULLUP(GPIOD_PIN11) | \ PIN_PUPDR_FLOATING(GPIOD_LED4) | \ @@ -681,30 +727,30 @@ PIN_ODR_LOW(GPIOD_LED3) | \ PIN_ODR_LOW(GPIOD_LED5) | \ PIN_ODR_LOW(GPIOD_LED6)) -#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0) | \ - PIN_AFIO_AF(GPIOD_PIN1, 0) | \ - PIN_AFIO_AF(GPIOD_PIN2, 0) | \ - PIN_AFIO_AF(GPIOD_PIN3, 0) | \ - PIN_AFIO_AF(GPIOD_RESET, 0) | \ - PIN_AFIO_AF(GPIOD_OVER_CURRENT, 0) | \ - PIN_AFIO_AF(GPIOD_PIN6, 0) | \ - PIN_AFIO_AF(GPIOD_PIN7, 0)) -#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0) | \ - PIN_AFIO_AF(GPIOD_PIN9, 0) | \ - PIN_AFIO_AF(GPIOD_PIN10, 0) | \ - PIN_AFIO_AF(GPIOD_PIN11, 0) | \ - PIN_AFIO_AF(GPIOD_LED4, 0) | \ - PIN_AFIO_AF(GPIOD_LED3, 0) | \ - PIN_AFIO_AF(GPIOD_LED5, 0) | \ - PIN_AFIO_AF(GPIOD_LED6, 0)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOD_RESET, 0U) | \ + PIN_AFIO_AF(GPIOD_OVER_CURRENT, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN7, 0U)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOD_LED4, 0U) | \ + PIN_AFIO_AF(GPIOD_LED3, 0U) | \ + PIN_AFIO_AF(GPIOD_LED5, 0U) | \ + PIN_AFIO_AF(GPIOD_LED6, 0U)) /* * GPIOE setup: * - * PE0 - PIN0 (input floating). - * PE1 - PIN1 (input floating). + * PE0 - INT1 (input floating). + * PE1 - INT2 (input floating). * PE2 - PIN2 (input floating). - * PE3 - PIN3 (input floating). + * PE3 - CS_SPI (output pushpull maximum). * PE4 - PIN4 (input floating). * PE5 - PIN5 (input floating). * PE6 - PIN6 (input floating). @@ -721,7 +767,7 @@ #define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \ PIN_MODE_INPUT(GPIOE_PIN1) | \ PIN_MODE_INPUT(GPIOE_PIN2) | \ - PIN_MODE_OUTPUT(GPIOE_PIN3) | \ + PIN_MODE_INPUT(GPIOE_PIN3) | \ PIN_MODE_INPUT(GPIOE_PIN4) | \ PIN_MODE_INPUT(GPIOE_PIN5) | \ PIN_MODE_INPUT(GPIOE_PIN6) | \ @@ -750,38 +796,38 @@ PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) -#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_100M(GPIOE_PIN0) | \ - PIN_OSPEED_100M(GPIOE_PIN1) | \ - PIN_OSPEED_100M(GPIOE_PIN2) | \ - PIN_OSPEED_100M(GPIOE_PIN3) | \ - PIN_OSPEED_100M(GPIOE_PIN4) | \ - PIN_OSPEED_100M(GPIOE_PIN5) | \ - PIN_OSPEED_100M(GPIOE_PIN6) | \ - PIN_OSPEED_100M(GPIOE_PIN7) | \ - PIN_OSPEED_100M(GPIOE_PIN8) | \ - PIN_OSPEED_100M(GPIOE_PIN9) | \ - PIN_OSPEED_100M(GPIOE_PIN10) | \ - PIN_OSPEED_100M(GPIOE_PIN11) | \ - PIN_OSPEED_100M(GPIOE_PIN12) | \ - PIN_OSPEED_100M(GPIOE_PIN13) | \ - PIN_OSPEED_100M(GPIOE_PIN14) | \ - PIN_OSPEED_100M(GPIOE_PIN15)) -#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLDOWN(GPIOE_PIN0) | \ - PIN_PUPDR_PULLDOWN(GPIOE_PIN1) | \ - PIN_PUPDR_PULLDOWN(GPIOE_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN3) | \ - PIN_PUPDR_PULLDOWN(GPIOE_PIN4) | \ - PIN_PUPDR_PULLDOWN(GPIOE_PIN5) | \ - PIN_PUPDR_PULLDOWN(GPIOE_PIN6) | \ - PIN_PUPDR_PULLDOWN(GPIOE_PIN7) | \ - PIN_PUPDR_PULLDOWN(GPIOE_PIN8) | \ - PIN_PUPDR_PULLDOWN(GPIOE_PIN9) | \ - PIN_PUPDR_PULLDOWN(GPIOE_PIN10) | \ - PIN_PUPDR_PULLDOWN(GPIOE_PIN11) | \ - PIN_PUPDR_PULLDOWN(GPIOE_PIN12) | \ - PIN_PUPDR_PULLDOWN(GPIOE_PIN13) | \ - PIN_PUPDR_PULLDOWN(GPIOE_PIN14) | \ - PIN_PUPDR_PULLDOWN(GPIOE_PIN15)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \ + PIN_OSPEED_HIGH(GPIOE_PIN1) | \ + PIN_OSPEED_HIGH(GPIOE_PIN2) | \ + PIN_OSPEED_HIGH(GPIOE_PIN3) | \ + PIN_OSPEED_HIGH(GPIOE_PIN4) | \ + PIN_OSPEED_HIGH(GPIOE_PIN5) | \ + PIN_OSPEED_HIGH(GPIOE_PIN6) | \ + PIN_OSPEED_HIGH(GPIOE_PIN7) | \ + PIN_OSPEED_HIGH(GPIOE_PIN8) | \ + PIN_OSPEED_HIGH(GPIOE_PIN9) | \ + PIN_OSPEED_HIGH(GPIOE_PIN10) | \ + PIN_OSPEED_HIGH(GPIOE_PIN11) | \ + PIN_OSPEED_HIGH(GPIOE_PIN12) | \ + PIN_OSPEED_HIGH(GPIOE_PIN13) | \ + PIN_OSPEED_HIGH(GPIOE_PIN14) | \ + PIN_OSPEED_HIGH(GPIOE_PIN15)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN15)) #define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ PIN_ODR_HIGH(GPIOE_PIN1) | \ PIN_ODR_HIGH(GPIOE_PIN2) | \ @@ -798,22 +844,22 @@ PIN_ODR_HIGH(GPIOE_PIN13) | \ PIN_ODR_HIGH(GPIOE_PIN14) | \ PIN_ODR_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0) | \ - PIN_AFIO_AF(GPIOE_PIN1, 0) | \ - PIN_AFIO_AF(GPIOE_PIN2, 0) | \ - PIN_AFIO_AF(GPIOE_PIN3, 0) | \ - PIN_AFIO_AF(GPIOE_PIN4, 0) | \ - PIN_AFIO_AF(GPIOE_PIN5, 0) | \ - PIN_AFIO_AF(GPIOE_PIN6, 0) | \ - PIN_AFIO_AF(GPIOE_PIN7, 0)) -#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0) | \ - PIN_AFIO_AF(GPIOE_PIN9, 0) | \ - PIN_AFIO_AF(GPIOE_PIN10, 0) | \ - PIN_AFIO_AF(GPIOE_PIN11, 0) | \ - PIN_AFIO_AF(GPIOE_PIN12, 0) | \ - PIN_AFIO_AF(GPIOE_PIN13, 0) | \ - PIN_AFIO_AF(GPIOE_PIN14, 0) | \ - PIN_AFIO_AF(GPIOE_PIN15, 0)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN7, 0U)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN15, 0U)) /* * GPIOF setup: @@ -867,22 +913,22 @@ PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) -#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_100M(GPIOF_PIN0) | \ - PIN_OSPEED_100M(GPIOF_PIN1) | \ - PIN_OSPEED_100M(GPIOF_PIN2) | \ - PIN_OSPEED_100M(GPIOF_PIN3) | \ - PIN_OSPEED_100M(GPIOF_PIN4) | \ - PIN_OSPEED_100M(GPIOF_PIN5) | \ - PIN_OSPEED_100M(GPIOF_PIN6) | \ - PIN_OSPEED_100M(GPIOF_PIN7) | \ - PIN_OSPEED_100M(GPIOF_PIN8) | \ - PIN_OSPEED_100M(GPIOF_PIN9) | \ - PIN_OSPEED_100M(GPIOF_PIN10) | \ - PIN_OSPEED_100M(GPIOF_PIN11) | \ - PIN_OSPEED_100M(GPIOF_PIN12) | \ - PIN_OSPEED_100M(GPIOF_PIN13) | \ - PIN_OSPEED_100M(GPIOF_PIN14) | \ - PIN_OSPEED_100M(GPIOF_PIN15)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_PIN0) | \ + PIN_OSPEED_HIGH(GPIOF_PIN1) | \ + PIN_OSPEED_HIGH(GPIOF_PIN2) | \ + PIN_OSPEED_HIGH(GPIOF_PIN3) | \ + PIN_OSPEED_HIGH(GPIOF_PIN4) | \ + PIN_OSPEED_HIGH(GPIOF_PIN5) | \ + PIN_OSPEED_HIGH(GPIOF_PIN6) | \ + PIN_OSPEED_HIGH(GPIOF_PIN7) | \ + PIN_OSPEED_HIGH(GPIOF_PIN8) | \ + PIN_OSPEED_HIGH(GPIOF_PIN9) | \ + PIN_OSPEED_HIGH(GPIOF_PIN10) | \ + PIN_OSPEED_HIGH(GPIOF_PIN11) | \ + PIN_OSPEED_HIGH(GPIOF_PIN12) | \ + PIN_OSPEED_HIGH(GPIOF_PIN13) | \ + PIN_OSPEED_HIGH(GPIOF_PIN14) | \ + PIN_OSPEED_HIGH(GPIOF_PIN15)) #define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_PIN0) | \ PIN_PUPDR_FLOATING(GPIOF_PIN1) | \ PIN_PUPDR_FLOATING(GPIOF_PIN2) | \ @@ -915,22 +961,22 @@ PIN_ODR_HIGH(GPIOF_PIN13) | \ PIN_ODR_HIGH(GPIOF_PIN14) | \ PIN_ODR_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0) | \ - PIN_AFIO_AF(GPIOF_PIN1, 0) | \ - PIN_AFIO_AF(GPIOF_PIN2, 0) | \ - PIN_AFIO_AF(GPIOF_PIN3, 0) | \ - PIN_AFIO_AF(GPIOF_PIN4, 0) | \ - PIN_AFIO_AF(GPIOF_PIN5, 0) | \ - PIN_AFIO_AF(GPIOF_PIN6, 0) | \ - PIN_AFIO_AF(GPIOF_PIN7, 0)) -#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0) | \ - PIN_AFIO_AF(GPIOF_PIN9, 0) | \ - PIN_AFIO_AF(GPIOF_PIN10, 0) | \ - PIN_AFIO_AF(GPIOF_PIN11, 0) | \ - PIN_AFIO_AF(GPIOF_PIN12, 0) | \ - PIN_AFIO_AF(GPIOF_PIN13, 0) | \ - PIN_AFIO_AF(GPIOF_PIN14, 0) | \ - PIN_AFIO_AF(GPIOF_PIN15, 0)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN7, 0U)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN15, 0U)) /* * GPIOG setup: @@ -984,22 +1030,22 @@ PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \ PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \ PIN_OTYPE_PUSHPULL(GPIOG_PIN15)) -#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_100M(GPIOG_PIN0) | \ - PIN_OSPEED_100M(GPIOG_PIN1) | \ - PIN_OSPEED_100M(GPIOG_PIN2) | \ - PIN_OSPEED_100M(GPIOG_PIN3) | \ - PIN_OSPEED_100M(GPIOG_PIN4) | \ - PIN_OSPEED_100M(GPIOG_PIN5) | \ - PIN_OSPEED_100M(GPIOG_PIN6) | \ - PIN_OSPEED_100M(GPIOG_PIN7) | \ - PIN_OSPEED_100M(GPIOG_PIN8) | \ - PIN_OSPEED_100M(GPIOG_PIN9) | \ - PIN_OSPEED_100M(GPIOG_PIN10) | \ - PIN_OSPEED_100M(GPIOG_PIN11) | \ - PIN_OSPEED_100M(GPIOG_PIN12) | \ - PIN_OSPEED_100M(GPIOG_PIN13) | \ - PIN_OSPEED_100M(GPIOG_PIN14) | \ - PIN_OSPEED_100M(GPIOG_PIN15)) +#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_HIGH(GPIOG_PIN0) | \ + PIN_OSPEED_HIGH(GPIOG_PIN1) | \ + PIN_OSPEED_HIGH(GPIOG_PIN2) | \ + PIN_OSPEED_HIGH(GPIOG_PIN3) | \ + PIN_OSPEED_HIGH(GPIOG_PIN4) | \ + PIN_OSPEED_HIGH(GPIOG_PIN5) | \ + PIN_OSPEED_HIGH(GPIOG_PIN6) | \ + PIN_OSPEED_HIGH(GPIOG_PIN7) | \ + PIN_OSPEED_HIGH(GPIOG_PIN8) | \ + PIN_OSPEED_HIGH(GPIOG_PIN9) | \ + PIN_OSPEED_HIGH(GPIOG_PIN10) | \ + PIN_OSPEED_HIGH(GPIOG_PIN11) | \ + PIN_OSPEED_HIGH(GPIOG_PIN12) | \ + PIN_OSPEED_HIGH(GPIOG_PIN13) | \ + PIN_OSPEED_HIGH(GPIOG_PIN14) | \ + PIN_OSPEED_HIGH(GPIOG_PIN15)) #define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_PIN0) | \ PIN_PUPDR_FLOATING(GPIOG_PIN1) | \ PIN_PUPDR_FLOATING(GPIOG_PIN2) | \ @@ -1032,22 +1078,22 @@ PIN_ODR_HIGH(GPIOG_PIN13) | \ PIN_ODR_HIGH(GPIOG_PIN14) | \ PIN_ODR_HIGH(GPIOG_PIN15)) -#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0) | \ - PIN_AFIO_AF(GPIOG_PIN1, 0) | \ - PIN_AFIO_AF(GPIOG_PIN2, 0) | \ - PIN_AFIO_AF(GPIOG_PIN3, 0) | \ - PIN_AFIO_AF(GPIOG_PIN4, 0) | \ - PIN_AFIO_AF(GPIOG_PIN5, 0) | \ - PIN_AFIO_AF(GPIOG_PIN6, 0) | \ - PIN_AFIO_AF(GPIOG_PIN7, 0)) -#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0) | \ - PIN_AFIO_AF(GPIOG_PIN9, 0) | \ - PIN_AFIO_AF(GPIOG_PIN10, 0) | \ - PIN_AFIO_AF(GPIOG_PIN11, 0) | \ - PIN_AFIO_AF(GPIOG_PIN12, 0) | \ - PIN_AFIO_AF(GPIOG_PIN13, 0) | \ - PIN_AFIO_AF(GPIOG_PIN14, 0) | \ - PIN_AFIO_AF(GPIOG_PIN15, 0)) +#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN7, 0U)) +#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN15, 0U)) /* * GPIOH setup: @@ -1101,22 +1147,22 @@ PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) -#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_100M(GPIOH_OSC_IN) | \ - PIN_OSPEED_100M(GPIOH_OSC_OUT) | \ - PIN_OSPEED_100M(GPIOH_PIN2) | \ - PIN_OSPEED_100M(GPIOH_PIN3) | \ - PIN_OSPEED_100M(GPIOH_PIN4) | \ - PIN_OSPEED_100M(GPIOH_PIN5) | \ - PIN_OSPEED_100M(GPIOH_PIN6) | \ - PIN_OSPEED_100M(GPIOH_PIN7) | \ - PIN_OSPEED_100M(GPIOH_PIN8) | \ - PIN_OSPEED_100M(GPIOH_PIN9) | \ - PIN_OSPEED_100M(GPIOH_PIN10) | \ - PIN_OSPEED_100M(GPIOH_PIN11) | \ - PIN_OSPEED_100M(GPIOH_PIN12) | \ - PIN_OSPEED_100M(GPIOH_PIN13) | \ - PIN_OSPEED_100M(GPIOH_PIN14) | \ - PIN_OSPEED_100M(GPIOH_PIN15)) +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \ + PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \ + PIN_OSPEED_HIGH(GPIOH_PIN2) | \ + PIN_OSPEED_HIGH(GPIOH_PIN3) | \ + PIN_OSPEED_HIGH(GPIOH_PIN4) | \ + PIN_OSPEED_HIGH(GPIOH_PIN5) | \ + PIN_OSPEED_HIGH(GPIOH_PIN6) | \ + PIN_OSPEED_HIGH(GPIOH_PIN7) | \ + PIN_OSPEED_HIGH(GPIOH_PIN8) | \ + PIN_OSPEED_HIGH(GPIOH_PIN9) | \ + PIN_OSPEED_HIGH(GPIOH_PIN10) | \ + PIN_OSPEED_HIGH(GPIOH_PIN11) | \ + PIN_OSPEED_HIGH(GPIOH_PIN12) | \ + PIN_OSPEED_HIGH(GPIOH_PIN13) | \ + PIN_OSPEED_HIGH(GPIOH_PIN14) | \ + PIN_OSPEED_HIGH(GPIOH_PIN15)) #define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ PIN_PUPDR_FLOATING(GPIOH_PIN2) | \ @@ -1149,22 +1195,22 @@ PIN_ODR_HIGH(GPIOH_PIN13) | \ PIN_ODR_HIGH(GPIOH_PIN14) | \ PIN_ODR_HIGH(GPIOH_PIN15)) -#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0) | \ - PIN_AFIO_AF(GPIOH_OSC_OUT, 0) | \ - PIN_AFIO_AF(GPIOH_PIN2, 0) | \ - PIN_AFIO_AF(GPIOH_PIN3, 0) | \ - PIN_AFIO_AF(GPIOH_PIN4, 0) | \ - PIN_AFIO_AF(GPIOH_PIN5, 0) | \ - PIN_AFIO_AF(GPIOH_PIN6, 0) | \ - PIN_AFIO_AF(GPIOH_PIN7, 0)) -#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0) | \ - PIN_AFIO_AF(GPIOH_PIN9, 0) | \ - PIN_AFIO_AF(GPIOH_PIN10, 0) | \ - PIN_AFIO_AF(GPIOH_PIN11, 0) | \ - PIN_AFIO_AF(GPIOH_PIN12, 0) | \ - PIN_AFIO_AF(GPIOH_PIN13, 0) | \ - PIN_AFIO_AF(GPIOH_PIN14, 0) | \ - PIN_AFIO_AF(GPIOH_PIN15, 0)) +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \ + PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN7, 0U)) +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN15, 0U)) /* * GPIOI setup: @@ -1218,22 +1264,22 @@ PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \ PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \ PIN_OTYPE_PUSHPULL(GPIOI_PIN15)) -#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_100M(GPIOI_PIN0) | \ - PIN_OSPEED_100M(GPIOI_PIN1) | \ - PIN_OSPEED_100M(GPIOI_PIN2) | \ - PIN_OSPEED_100M(GPIOI_PIN3) | \ - PIN_OSPEED_100M(GPIOI_PIN4) | \ - PIN_OSPEED_100M(GPIOI_PIN5) | \ - PIN_OSPEED_100M(GPIOI_PIN6) | \ - PIN_OSPEED_100M(GPIOI_PIN7) | \ - PIN_OSPEED_100M(GPIOI_PIN8) | \ - PIN_OSPEED_100M(GPIOI_PIN9) | \ - PIN_OSPEED_100M(GPIOI_PIN10) | \ - PIN_OSPEED_100M(GPIOI_PIN11) | \ - PIN_OSPEED_100M(GPIOI_PIN12) | \ - PIN_OSPEED_100M(GPIOI_PIN13) | \ - PIN_OSPEED_100M(GPIOI_PIN14) | \ - PIN_OSPEED_100M(GPIOI_PIN15)) +#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_HIGH(GPIOI_PIN0) | \ + PIN_OSPEED_HIGH(GPIOI_PIN1) | \ + PIN_OSPEED_HIGH(GPIOI_PIN2) | \ + PIN_OSPEED_HIGH(GPIOI_PIN3) | \ + PIN_OSPEED_HIGH(GPIOI_PIN4) | \ + PIN_OSPEED_HIGH(GPIOI_PIN5) | \ + PIN_OSPEED_HIGH(GPIOI_PIN6) | \ + PIN_OSPEED_HIGH(GPIOI_PIN7) | \ + PIN_OSPEED_HIGH(GPIOI_PIN8) | \ + PIN_OSPEED_HIGH(GPIOI_PIN9) | \ + PIN_OSPEED_HIGH(GPIOI_PIN10) | \ + PIN_OSPEED_HIGH(GPIOI_PIN11) | \ + PIN_OSPEED_HIGH(GPIOI_PIN12) | \ + PIN_OSPEED_HIGH(GPIOI_PIN13) | \ + PIN_OSPEED_HIGH(GPIOI_PIN14) | \ + PIN_OSPEED_HIGH(GPIOI_PIN15)) #define VAL_GPIOI_PUPDR (PIN_PUPDR_FLOATING(GPIOI_PIN0) | \ PIN_PUPDR_FLOATING(GPIOI_PIN1) | \ PIN_PUPDR_FLOATING(GPIOI_PIN2) | \ @@ -1266,22 +1312,22 @@ PIN_ODR_HIGH(GPIOI_PIN13) | \ PIN_ODR_HIGH(GPIOI_PIN14) | \ PIN_ODR_HIGH(GPIOI_PIN15)) -#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0) | \ - PIN_AFIO_AF(GPIOI_PIN1, 0) | \ - PIN_AFIO_AF(GPIOI_PIN2, 0) | \ - PIN_AFIO_AF(GPIOI_PIN3, 0) | \ - PIN_AFIO_AF(GPIOI_PIN4, 0) | \ - PIN_AFIO_AF(GPIOI_PIN5, 0) | \ - PIN_AFIO_AF(GPIOI_PIN6, 0) | \ - PIN_AFIO_AF(GPIOI_PIN7, 0)) -#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0) | \ - PIN_AFIO_AF(GPIOI_PIN9, 0) | \ - PIN_AFIO_AF(GPIOI_PIN10, 0) | \ - PIN_AFIO_AF(GPIOI_PIN11, 0) | \ - PIN_AFIO_AF(GPIOI_PIN12, 0) | \ - PIN_AFIO_AF(GPIOI_PIN13, 0) | \ - PIN_AFIO_AF(GPIOI_PIN14, 0) | \ - PIN_AFIO_AF(GPIOI_PIN15, 0)) +#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN7, 0U)) +#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN15, 0U)) #if !defined(_FROM_ASM_) @@ -1294,4 +1340,4 @@ extern "C" { #endif #endif /* _FROM_ASM_ */ -#endif /* _BOARD_H_ */ +#endif /* BOARD_H */ diff --git a/firmware/config/boards/ST_STM32F4_DISCOVERY/board.c b/firmware/config/boards/ST_STM32F4_DISCOVERY/board.c deleted file mode 100644 index 4b26d39f8a..0000000000 --- a/firmware/config/boards/ST_STM32F4_DISCOVERY/board.c +++ /dev/null @@ -1,129 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#include "hal.h" - -#if HAL_USE_PAL || defined(__DOXYGEN__) -/** - * @brief PAL setup. - * @details Digital I/O ports static configuration as defined in @p board.h. - * This variable is used by the HAL when initializing the PAL driver. - */ -const PALConfig pal_default_config = { -#if STM32_HAS_GPIOA - {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, - VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, -#endif -#if STM32_HAS_GPIOB - {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, - VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, -#endif -#if STM32_HAS_GPIOC - {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, - VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, -#endif -#if STM32_HAS_GPIOD - {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, - VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, -#endif -#if STM32_HAS_GPIOE - {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, - VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, -#endif -#if STM32_HAS_GPIOF - {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, - VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, -#endif -#if STM32_HAS_GPIOG - {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, - VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, -#endif -#if STM32_HAS_GPIOH - {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, - VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, -#endif -#if STM32_HAS_GPIOI - {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, - VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH} -#endif -}; -#endif - -/** - * @brief Early initialization code. - * @details This initialization must be performed just after stack setup - * and before any other initialization. - */ -void __early_init(void) { - - stm32_clock_init(); -} - -#if HAL_USE_SDC || defined(__DOXYGEN__) -/** - * @brief SDC card detection. - */ -bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief SDC card write protection detection. - */ -bool sdc_lld_is_write_protected(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif /* HAL_USE_SDC */ - -#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) -/** - * @brief MMC_SPI card detection. - */ -bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief MMC_SPI card write protection detection. - */ -bool mmc_lld_is_write_protected(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif - -/** - * @brief Board-specific initialization code. - * @todo Add your board-specific code, if any. - */ -void boardInit(void) { -} diff --git a/firmware/config/boards/ST_STM32F4_DISCOVERY/board.h b/firmware/config/boards/ST_STM32F4_DISCOVERY/board.h deleted file mode 100644 index 3fe30786b5..0000000000 --- a/firmware/config/boards/ST_STM32F4_DISCOVERY/board.h +++ /dev/null @@ -1,1343 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#ifndef BOARD_H -#define BOARD_H - -/* - * Setup for STMicroelectronics STM32F4-Discovery board. - */ - -/* - * Board identifier. - */ -#define BOARD_ST_STM32F4_DISCOVERY -#define BOARD_NAME "STM32F4-Discovery for RusEFI" - -/* - * Board oscillators-related settings. - * NOTE: LSE not fitted. - */ -#if !defined(STM32_LSECLK) -#define STM32_LSECLK 32768U -#endif - -#if !defined(STM32_HSECLK) -#define STM32_HSECLK 8000000U -#endif - -/* - * Board voltages. - * Required for performance limits calculation. - */ -#define STM32_VDD 300U - -/* - * MCU type as defined in the ST header. - */ -#define STM32F407xx - -/* - * IO pins assignments. - */ -#define GPIOA_BUTTON 0 -#define GPIOA_PIN1 1 -#define GPIOA_PIN2 2 -#define GPIOA_PIN3 3 -#define GPIOA_LRCK 4 -#define GPIOA_SPC 5 -#define GPIOA_SDO 6 -#define GPIOA_SDI 7 -#define GPIOA_PIN8 8 -#define GPIOA_VBUS_FS 9 -#define GPIOA_OTG_FS_ID 10 -#define GPIOA_OTG_FS_DM 11 -#define GPIOA_OTG_FS_DP 12 -#define GPIOA_SWDIO 13 -#define GPIOA_SWCLK 14 -#define GPIOA_PIN15 15 - -#define GPIOB_PIN0 0 -#define GPIOB_PIN1 1 -#define GPIOB_PIN2 2 -#define GPIOB_SWO 3 -#define GPIOB_PIN4 4 -#define GPIOB_PIN5 5 -#define GPIOB_SCL 6 -#define GPIOB_PIN7 7 -#define GPIOB_PIN8 8 -#define GPIOB_PIN9 9 -#define GPIOB_PIN10 10 -#define GPIOB_PIN11 11 -#define GPIOB_PIN12 12 -#define GPIOB_PIN13 13 -#define GPIOB_PIN14 14 -#define GPIOB_PIN15 15 - -#define GPIOC_OTG_FS_POWER_ON 0 -#define GPIOC_PIN1 1 -#define GPIOC_PIN2 2 -#define GPIOC_PIN3 3 -#define GPIOC_PIN4 4 -#define GPIOC_PIN5 5 -#define GPIOC_PIN6 6 -#define GPIOC_PIN7 7 -#define GPIOC_PIN8 8 -#define GPIOC_PIN9 9 -#define GPIOC_PIN10 10 -#define GPIOC_PIN11 11 -#define GPIOC_PIN12 12 -#define GPIOC_PIN13 13 -#define GPIOC_PIN14 14 -#define GPIOC_PIN15 15 - -#define GPIOD_PIN0 0 -#define GPIOD_PIN1 1 -#define GPIOD_PIN2 2 -#define GPIOD_PIN3 3 -#define GPIOD_RESET 4 -#define GPIOD_OVER_CURRENT 5 -#define GPIOD_PIN6 6 -#define GPIOD_PIN7 7 -#define GPIOD_PIN8 8 -#define GPIOD_PIN9 9 -#define GPIOD_PIN10 10 -#define GPIOD_PIN11 11 -#define GPIOD_LED4 12 -#define GPIOD_LED3 13 -#define GPIOD_LED5 14 -#define GPIOD_LED6 15 - -#define GPIOE_PIN0 0 -#define GPIOE_PIN1 1 -#define GPIOE_PIN2 2 -#define GPIOE_PIN3 3 -#define GPIOE_PIN4 4 -#define GPIOE_PIN5 5 -#define GPIOE_PIN6 6 -#define GPIOE_PIN7 7 -#define GPIOE_PIN8 8 -#define GPIOE_PIN9 9 -#define GPIOE_PIN10 10 -#define GPIOE_PIN11 11 -#define GPIOE_PIN12 12 -#define GPIOE_PIN13 13 -#define GPIOE_PIN14 14 -#define GPIOE_PIN15 15 - -#define GPIOF_PIN0 0 -#define GPIOF_PIN1 1 -#define GPIOF_PIN2 2 -#define GPIOF_PIN3 3 -#define GPIOF_PIN4 4 -#define GPIOF_PIN5 5 -#define GPIOF_PIN6 6 -#define GPIOF_PIN7 7 -#define GPIOF_PIN8 8 -#define GPIOF_PIN9 9 -#define GPIOF_PIN10 10 -#define GPIOF_PIN11 11 -#define GPIOF_PIN12 12 -#define GPIOF_PIN13 13 -#define GPIOF_PIN14 14 -#define GPIOF_PIN15 15 - -#define GPIOG_PIN0 0 -#define GPIOG_PIN1 1 -#define GPIOG_PIN2 2 -#define GPIOG_PIN3 3 -#define GPIOG_PIN4 4 -#define GPIOG_PIN5 5 -#define GPIOG_PIN6 6 -#define GPIOG_PIN7 7 -#define GPIOG_PIN8 8 -#define GPIOG_PIN9 9 -#define GPIOG_PIN10 10 -#define GPIOG_PIN11 11 -#define GPIOG_PIN12 12 -#define GPIOG_PIN13 13 -#define GPIOG_PIN14 14 -#define GPIOG_PIN15 15 - -#define GPIOH_OSC_IN 0 -#define GPIOH_OSC_OUT 1 -#define GPIOH_PIN2 2 -#define GPIOH_PIN3 3 -#define GPIOH_PIN4 4 -#define GPIOH_PIN5 5 -#define GPIOH_PIN6 6 -#define GPIOH_PIN7 7 -#define GPIOH_PIN8 8 -#define GPIOH_PIN9 9 -#define GPIOH_PIN10 10 -#define GPIOH_PIN11 11 -#define GPIOH_PIN12 12 -#define GPIOH_PIN13 13 -#define GPIOH_PIN14 14 -#define GPIOH_PIN15 15 - -#define GPIOI_PIN0 0 -#define GPIOI_PIN1 1 -#define GPIOI_PIN2 2 -#define GPIOI_PIN3 3 -#define GPIOI_PIN4 4 -#define GPIOI_PIN5 5 -#define GPIOI_PIN6 6 -#define GPIOI_PIN7 7 -#define GPIOI_PIN8 8 -#define GPIOI_PIN9 9 -#define GPIOI_PIN10 10 -#define GPIOI_PIN11 11 -#define GPIOI_PIN12 12 -#define GPIOI_PIN13 13 -#define GPIOI_PIN14 14 -#define GPIOI_PIN15 15 - -/* - * IO lines assignments. - */ -#define LINE_BUTTON PAL_LINE(GPIOA, 0U) -#define LINE_LRCK PAL_LINE(GPIOA, 4U) -#define LINE_SPC PAL_LINE(GPIOA, 5U) -#define LINE_SDO PAL_LINE(GPIOA, 6U) -#define LINE_SDI PAL_LINE(GPIOA, 7U) -#define LINE_VBUS_FS PAL_LINE(GPIOA, 9U) -#define LINE_OTG_FS_ID PAL_LINE(GPIOA, 10U) -#define LINE_OTG_FS_DM PAL_LINE(GPIOA, 11U) -#define LINE_OTG_FS_DP PAL_LINE(GPIOA, 12U) -#define LINE_SWDIO PAL_LINE(GPIOA, 13U) -#define LINE_SWCLK PAL_LINE(GPIOA, 14U) - -#define LINE_SWO PAL_LINE(GPIOB, 3U) -#define LINE_SCL PAL_LINE(GPIOB, 6U) -#define LINE_SDA PAL_LINE(GPIOB, 9U) -#define LINE_CLK_IN PAL_LINE(GPIOB, 10U) - -#define LINE_OTG_FS_POWER_ON PAL_LINE(GPIOC, 0U) -#define LINE_PDM_OUT PAL_LINE(GPIOC, 3U) -#define LINE_MCLK PAL_LINE(GPIOC, 7U) -#define LINE_SCLK PAL_LINE(GPIOC, 10U) -#define LINE_SDIN PAL_LINE(GPIOC, 12U) - -#define LINE_RESET PAL_LINE(GPIOD, 4U) -#define LINE_OVER_CURRENT PAL_LINE(GPIOD, 5U) -#define LINE_LED4 PAL_LINE(GPIOD, 12U) -#define LINE_LED3 PAL_LINE(GPIOD, 13U) -#define LINE_LED5 PAL_LINE(GPIOD, 14U) -#define LINE_LED6 PAL_LINE(GPIOD, 15U) - -#define LINE_INT1 PAL_LINE(GPIOE, 0U) -#define LINE_INT2 PAL_LINE(GPIOE, 1U) -#define LINE_CS_SPI PAL_LINE(GPIOE, 3U) - - - -#define LINE_OSC_IN PAL_LINE(GPIOH, 0U) -#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U) - - -/* - * I/O ports initial setup, this configuration is established soon after reset - * in the initialization code. - * Please refer to the STM32 Reference Manual for details. - */ -#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) -#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) -#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) -#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) -#define PIN_ODR_LOW(n) (0U << (n)) -#define PIN_ODR_HIGH(n) (1U << (n)) -#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) -#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) -#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) -#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) -#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) -#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) -#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) -#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) -#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) -#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) - -/* - * GPIOA setup: - * - * PA0 - BUTTON (input floating). - * PA1 - PIN1 (input pullup). - * PA2 - PIN2 (input pullup). - * PA3 - PIN3 (input pullup). - * PA4 - LRCK (alternate 6). - * PA5 - SPC (alternate 5). - * PA6 - SDO (alternate 5). - * PA7 - SDI (alternate 5). - * PA8 - PIN8 (input pullup). - * PA9 - VBUS_FS (input floating). - * PA10 - OTG_FS_ID (alternate 10). - * PA11 - OTG_FS_DM (alternate 10). - * PA12 - OTG_FS_DP (alternate 10). - * PA13 - SWDIO (alternate 0). - * PA14 - SWCLK (alternate 0). - * PA15 - PIN15 (input pullup). - */ -#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON) | \ - PIN_MODE_INPUT(GPIOA_PIN1) | \ - PIN_MODE_INPUT(GPIOA_PIN2) | \ - PIN_MODE_INPUT(GPIOA_PIN3) | \ - PIN_MODE_ALTERNATE(GPIOA_LRCK) | \ - PIN_MODE_ALTERNATE(GPIOA_SPC) | \ - PIN_MODE_ALTERNATE(GPIOA_SDO) | \ - PIN_MODE_ALTERNATE(GPIOA_SDI) | \ - PIN_MODE_INPUT(GPIOA_PIN8) | \ - PIN_MODE_INPUT(GPIOA_VBUS_FS) | \ - PIN_MODE_ALTERNATE(GPIOA_OTG_FS_ID) | \ - PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \ - PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \ - PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ - PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ - PIN_MODE_INPUT(GPIOA_PIN15)) -#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOA_LRCK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SPC) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SDO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SDI) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOA_VBUS_FS) | \ - PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_ID) | \ - PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \ - PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) -#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_BUTTON) | \ - PIN_OSPEED_HIGH(GPIOA_PIN1) | \ - PIN_OSPEED_HIGH(GPIOA_PIN2) | \ - PIN_OSPEED_HIGH(GPIOA_PIN3) | \ - PIN_OSPEED_HIGH(GPIOA_LRCK) | \ - PIN_OSPEED_MEDIUM(GPIOA_SPC) | \ - PIN_OSPEED_MEDIUM(GPIOA_SDO) | \ - PIN_OSPEED_MEDIUM(GPIOA_SDI) | \ - PIN_OSPEED_HIGH(GPIOA_PIN8) | \ - PIN_OSPEED_HIGH(GPIOA_VBUS_FS) | \ - PIN_OSPEED_HIGH(GPIOA_OTG_FS_ID) | \ - PIN_OSPEED_HIGH(GPIOA_OTG_FS_DM) | \ - PIN_OSPEED_HIGH(GPIOA_OTG_FS_DP) | \ - PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ - PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ - PIN_OSPEED_HIGH(GPIOA_PIN15)) -#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_BUTTON) | \ - PIN_PUPDR_PULLUP(GPIOA_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOA_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOA_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOA_LRCK) | \ - PIN_PUPDR_FLOATING(GPIOA_SPC) | \ - PIN_PUPDR_FLOATING(GPIOA_SDO) | \ - PIN_PUPDR_FLOATING(GPIOA_SDI) | \ - PIN_PUPDR_PULLUP(GPIOA_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOA_VBUS_FS) | \ - PIN_PUPDR_FLOATING(GPIOA_OTG_FS_ID) | \ - PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \ - PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \ - PIN_PUPDR_FLOATING(GPIOA_SWDIO) | \ - PIN_PUPDR_FLOATING(GPIOA_SWCLK) | \ - PIN_PUPDR_PULLUP(GPIOA_PIN15)) -#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_BUTTON) | \ - PIN_ODR_HIGH(GPIOA_PIN1) | \ - PIN_ODR_HIGH(GPIOA_PIN2) | \ - PIN_ODR_HIGH(GPIOA_PIN3) | \ - PIN_ODR_HIGH(GPIOA_LRCK) | \ - PIN_ODR_HIGH(GPIOA_SPC) | \ - PIN_ODR_HIGH(GPIOA_SDO) | \ - PIN_ODR_HIGH(GPIOA_SDI) | \ - PIN_ODR_HIGH(GPIOA_PIN8) | \ - PIN_ODR_HIGH(GPIOA_VBUS_FS) | \ - PIN_ODR_HIGH(GPIOA_OTG_FS_ID) | \ - PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \ - PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \ - PIN_ODR_HIGH(GPIOA_SWDIO) | \ - PIN_ODR_HIGH(GPIOA_SWCLK) | \ - PIN_ODR_HIGH(GPIOA_PIN15)) -#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOA_LRCK, 6U) | \ - PIN_AFIO_AF(GPIOA_SPC, 5U) | \ - PIN_AFIO_AF(GPIOA_SDO, 5U) | \ - PIN_AFIO_AF(GPIOA_SDI, 5U)) -#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOA_VBUS_FS, 0U) | \ - PIN_AFIO_AF(GPIOA_OTG_FS_ID, 10U) | \ - PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10U) | \ - PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10U) | \ - PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ - PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN15, 0U)) - -/* - * GPIOB setup: - * - * PB0 - PIN0 (input pullup). - * PB1 - PIN1 (input pullup). - * PB2 - PIN2 (input pullup). - * PB3 - SWO (alternate 0). - * PB4 - PIN4 (input pullup). - * PB5 - PIN5 (input pullup). - * PB6 - SCL (alternate 4). - * PB7 - PIN7 (input pullup). - * PB8 - PIN8 (input pullup). - * PB9 - SDA (alternate 4). - * PB10 - CLK_IN (input pullup). - * PB11 - PIN11 (input pullup). - * PB12 - PIN12 (input pullup). - * PB13 - PIN13 (input pullup). - * PB14 - PIN14 (input pullup). - * PB15 - PIN15 (input pullup). - */ -#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \ - PIN_MODE_INPUT(GPIOB_PIN1) | \ - PIN_MODE_INPUT(GPIOB_PIN2) | \ - PIN_MODE_ALTERNATE(GPIOB_SWO) | \ - PIN_MODE_INPUT(GPIOB_PIN4) | \ - PIN_MODE_INPUT(GPIOB_PIN5) | \ - PIN_MODE_ALTERNATE(GPIOB_SCL) | \ - PIN_MODE_INPUT(GPIOB_PIN7) | \ - PIN_MODE_INPUT(GPIOB_PIN8) | \ - PIN_MODE_INPUT(GPIOB_PIN9) | \ - PIN_MODE_INPUT(GPIOB_PIN10) | \ - PIN_MODE_INPUT(GPIOB_PIN11) | \ - PIN_MODE_INPUT(GPIOB_PIN12) | \ - PIN_MODE_INPUT(GPIOB_PIN13) | \ - PIN_MODE_INPUT(GPIOB_PIN14) | \ - PIN_MODE_INPUT(GPIOB_PIN15)) -#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_SCL) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) -#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_PIN0) | \ - PIN_OSPEED_HIGH(GPIOB_PIN1) | \ - PIN_OSPEED_HIGH(GPIOB_PIN2) | \ - PIN_OSPEED_HIGH(GPIOB_SWO) | \ - PIN_OSPEED_HIGH(GPIOB_PIN4) | \ - PIN_OSPEED_HIGH(GPIOB_PIN5) | \ - PIN_OSPEED_HIGH(GPIOB_SCL) | \ - PIN_OSPEED_HIGH(GPIOB_PIN7) | \ - PIN_OSPEED_HIGH(GPIOB_PIN8) | \ - PIN_OSPEED_HIGH(GPIOB_PIN9) | \ - PIN_OSPEED_HIGH(GPIOB_PIN10) | \ - PIN_OSPEED_HIGH(GPIOB_PIN11) | \ - PIN_OSPEED_HIGH(GPIOB_PIN12) | \ - PIN_OSPEED_HIGH(GPIOB_PIN13) | \ - PIN_OSPEED_HIGH(GPIOB_PIN14) | \ - PIN_OSPEED_HIGH(GPIOB_PIN15)) -#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOB_SWO) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOB_SCL) | \ - PIN_PUPDR_PULLDOWN(GPIOB_PIN7) | \ - PIN_PUPDR_PULLDOWN(GPIOB_PIN8) | \ - PIN_PUPDR_PULLDOWN(GPIOB_PIN9) | \ - PIN_PUPDR_PULLDOWN(GPIOB_PIN10) | \ - PIN_PUPDR_PULLDOWN(GPIOB_PIN11) | \ - PIN_PUPDR_PULLDOWN(GPIOB_PIN12) | \ - PIN_PUPDR_PULLDOWN(GPIOB_PIN13) | \ - PIN_PUPDR_PULLDOWN(GPIOB_PIN14) | \ - PIN_PUPDR_PULLDOWN(GPIOB_PIN15)) -#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \ - PIN_ODR_HIGH(GPIOB_PIN1) | \ - PIN_ODR_HIGH(GPIOB_PIN2) | \ - PIN_ODR_HIGH(GPIOB_SWO) | \ - PIN_ODR_HIGH(GPIOB_PIN4) | \ - PIN_ODR_HIGH(GPIOB_PIN5) | \ - PIN_ODR_HIGH(GPIOB_SCL) | \ - PIN_ODR_HIGH(GPIOB_PIN7) | \ - PIN_ODR_HIGH(GPIOB_PIN8) | \ - PIN_ODR_HIGH(GPIOB_PIN9) | \ - PIN_ODR_HIGH(GPIOB_PIN10) | \ - PIN_ODR_HIGH(GPIOB_PIN11) | \ - PIN_ODR_HIGH(GPIOB_PIN12) | \ - PIN_ODR_HIGH(GPIOB_PIN13) | \ - PIN_ODR_HIGH(GPIOB_PIN14) | \ - PIN_ODR_HIGH(GPIOB_PIN15)) -#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOB_SWO, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOB_SCL, 4U) | \ - PIN_AFIO_AF(GPIOB_PIN7, 0U)) -#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN15, 0U)) - -/* - * GPIOC setup: - * - * PC0 - OTG_FS_POWER_ON (output pushpull maximum). - * PC1 - PIN1 (input pullup). - * PC2 - PIN2 (input pullup). - * PC3 - PDM_OUT (input pullup). - * PC4 - PIN4 (input pullup). - * PC5 - PIN5 (input pullup). - * PC6 - PIN6 (input pullup). - * PC7 - MCLK (alternate 6). - * PC8 - PIN8 (input pullup). - * PC9 - PIN9 (input pullup). - * PC10 - SCLK (alternate 6). - * PC11 - PIN11 (input pullup). - * PC12 - SDIN (alternate 6). - * PC13 - PIN13 (input pullup). - * PC14 - PIN14 (input pullup). - * PC15 - PIN15 (input pullup). - */ -#define VAL_GPIOC_MODER (PIN_MODE_OUTPUT(GPIOC_OTG_FS_POWER_ON) |\ - PIN_MODE_INPUT(GPIOC_PIN1) | \ - PIN_MODE_INPUT(GPIOC_PIN2) | \ - PIN_MODE_INPUT(GPIOC_PIN3) | \ - PIN_MODE_INPUT(GPIOC_PIN4) | \ - PIN_MODE_INPUT(GPIOC_PIN5) | \ - PIN_MODE_INPUT(GPIOC_PIN6) | \ - PIN_MODE_INPUT(GPIOC_PIN7) | \ - PIN_MODE_INPUT(GPIOC_PIN8) | \ - PIN_MODE_INPUT(GPIOC_PIN9) | \ - PIN_MODE_INPUT(GPIOC_PIN10) | \ - PIN_MODE_INPUT(GPIOC_PIN11) | \ - PIN_MODE_INPUT(GPIOC_PIN12) | \ - PIN_MODE_INPUT(GPIOC_PIN13) | \ - PIN_MODE_INPUT(GPIOC_PIN14) | \ - PIN_MODE_INPUT(GPIOC_PIN15)) -#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_OTG_FS_POWER_ON) |\ - PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN15)) -#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_OTG_FS_POWER_ON) |\ - PIN_OSPEED_HIGH(GPIOC_PIN1) | \ - PIN_OSPEED_HIGH(GPIOC_PIN2) | \ - PIN_OSPEED_HIGH(GPIOC_PIN3) | \ - PIN_OSPEED_HIGH(GPIOC_PIN4) | \ - PIN_OSPEED_HIGH(GPIOC_PIN5) | \ - PIN_OSPEED_HIGH(GPIOC_PIN6) | \ - PIN_OSPEED_HIGH(GPIOC_PIN7) | \ - PIN_OSPEED_HIGH(GPIOC_PIN8) | \ - PIN_OSPEED_HIGH(GPIOC_PIN9) | \ - PIN_OSPEED_HIGH(GPIOC_PIN10) | \ - PIN_OSPEED_HIGH(GPIOC_PIN11) | \ - PIN_OSPEED_HIGH(GPIOC_PIN12) | \ - PIN_OSPEED_HIGH(GPIOC_PIN13) | \ - PIN_OSPEED_HIGH(GPIOC_PIN14) | \ - PIN_OSPEED_HIGH(GPIOC_PIN15)) -#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_OTG_FS_POWER_ON) |\ - PIN_PUPDR_PULLDOWN(GPIOC_PIN1) | \ - PIN_PUPDR_PULLDOWN(GPIOC_PIN2) | \ - PIN_PUPDR_PULLDOWN(GPIOC_PIN3) | \ - PIN_PUPDR_PULLDOWN(GPIOC_PIN4) | \ - PIN_PUPDR_PULLDOWN(GPIOC_PIN5) | \ - PIN_PUPDR_PULLDOWN(GPIOC_PIN6) | \ - PIN_PUPDR_PULLDOWN(GPIOC_PIN7) | \ - PIN_PUPDR_PULLDOWN(GPIOC_PIN8) | \ - PIN_PUPDR_PULLDOWN(GPIOC_PIN9) | \ - PIN_PUPDR_PULLDOWN(GPIOC_PIN10) | \ - PIN_PUPDR_PULLDOWN(GPIOC_PIN11) | \ - PIN_PUPDR_PULLDOWN(GPIOC_PIN12) | \ - PIN_PUPDR_PULLDOWN(GPIOC_PIN13) | \ - PIN_PUPDR_PULLDOWN(GPIOC_PIN14) | \ - PIN_PUPDR_PULLDOWN(GPIOC_PIN15)) -#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_OTG_FS_POWER_ON) | \ - PIN_ODR_HIGH(GPIOC_PIN1) | \ - PIN_ODR_HIGH(GPIOC_PIN2) | \ - PIN_ODR_HIGH(GPIOC_PIN3) | \ - PIN_ODR_HIGH(GPIOC_PIN4) | \ - PIN_ODR_HIGH(GPIOC_PIN5) | \ - PIN_ODR_HIGH(GPIOC_PIN6) | \ - PIN_ODR_HIGH(GPIOC_PIN7) | \ - PIN_ODR_HIGH(GPIOC_PIN8) | \ - PIN_ODR_HIGH(GPIOC_PIN9) | \ - PIN_ODR_HIGH(GPIOC_PIN10) | \ - PIN_ODR_HIGH(GPIOC_PIN11) | \ - PIN_ODR_HIGH(GPIOC_PIN12) | \ - PIN_ODR_HIGH(GPIOC_PIN13) | \ - PIN_ODR_HIGH(GPIOC_PIN14) | \ - PIN_ODR_HIGH(GPIOC_PIN15)) -#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_OTG_FS_POWER_ON, 0U) |\ - PIN_AFIO_AF(GPIOC_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN7, 0U)) -#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN15, 0U)) - -/* - * GPIOD setup: - * - * PD0 - PIN0 (input pullup). - * PD1 - PIN1 (input pullup). - * PD2 - PIN2 (input pullup). - * PD3 - PIN3 (input pullup). - * PD4 - RESET (output pushpull maximum). - * PD5 - OVER_CURRENT (input floating). - * PD6 - PIN6 (input pullup). - * PD7 - PIN7 (input pullup). - * PD8 - PIN8 (input pullup). - * PD9 - PIN9 (input pullup). - * PD10 - PIN10 (input pullup). - * PD11 - PIN11 (input pullup). - * PD12 - LED4 (output pushpull maximum). - * PD13 - LED3 (output pushpull maximum). - * PD14 - LED5 (output pushpull maximum). - * PD15 - LED6 (output pushpull maximum). - */ -#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \ - PIN_MODE_INPUT(GPIOD_PIN1) | \ - PIN_MODE_INPUT(GPIOD_PIN2) | \ - PIN_MODE_INPUT(GPIOD_PIN3) | \ - PIN_MODE_OUTPUT(GPIOD_RESET) | \ - PIN_MODE_INPUT(GPIOD_OVER_CURRENT) | \ - PIN_MODE_INPUT(GPIOD_PIN6) | \ - PIN_MODE_INPUT(GPIOD_PIN7) | \ - PIN_MODE_INPUT(GPIOD_PIN8) | \ - PIN_MODE_INPUT(GPIOD_PIN9) | \ - PIN_MODE_INPUT(GPIOD_PIN10) | \ - PIN_MODE_INPUT(GPIOD_PIN11) | \ - PIN_MODE_OUTPUT(GPIOD_LED4) | \ - PIN_MODE_OUTPUT(GPIOD_LED3) | \ - PIN_MODE_OUTPUT(GPIOD_LED5) | \ - PIN_MODE_OUTPUT(GPIOD_LED6)) -#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOD_RESET) | \ - PIN_OTYPE_PUSHPULL(GPIOD_OVER_CURRENT) |\ - PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOD_LED4) | \ - PIN_OTYPE_PUSHPULL(GPIOD_LED3) | \ - PIN_OTYPE_PUSHPULL(GPIOD_LED5) | \ - PIN_OTYPE_PUSHPULL(GPIOD_LED6)) -#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \ - PIN_OSPEED_HIGH(GPIOD_PIN1) | \ - PIN_OSPEED_HIGH(GPIOD_PIN2) | \ - PIN_OSPEED_HIGH(GPIOD_PIN3) | \ - PIN_OSPEED_HIGH(GPIOD_RESET) | \ - PIN_OSPEED_HIGH(GPIOD_OVER_CURRENT) | \ - PIN_OSPEED_HIGH(GPIOD_PIN6) | \ - PIN_OSPEED_HIGH(GPIOD_PIN7) | \ - PIN_OSPEED_HIGH(GPIOD_PIN8) | \ - PIN_OSPEED_HIGH(GPIOD_PIN9) | \ - PIN_OSPEED_HIGH(GPIOD_PIN10) | \ - PIN_OSPEED_HIGH(GPIOD_PIN11) | \ - PIN_OSPEED_HIGH(GPIOD_LED4) | \ - PIN_OSPEED_HIGH(GPIOD_LED3) | \ - PIN_OSPEED_HIGH(GPIOD_LED5) | \ - PIN_OSPEED_HIGH(GPIOD_LED6)) -#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOD_RESET) | \ - PIN_PUPDR_FLOATING(GPIOD_OVER_CURRENT) |\ - PIN_PUPDR_PULLUP(GPIOD_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOD_LED4) | \ - PIN_PUPDR_FLOATING(GPIOD_LED3) | \ - PIN_PUPDR_FLOATING(GPIOD_LED5) | \ - PIN_PUPDR_FLOATING(GPIOD_LED6)) -#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ - PIN_ODR_HIGH(GPIOD_PIN1) | \ - PIN_ODR_HIGH(GPIOD_PIN2) | \ - PIN_ODR_HIGH(GPIOD_PIN3) | \ - PIN_ODR_HIGH(GPIOD_RESET) | \ - PIN_ODR_HIGH(GPIOD_OVER_CURRENT) | \ - PIN_ODR_HIGH(GPIOD_PIN6) | \ - PIN_ODR_HIGH(GPIOD_PIN7) | \ - PIN_ODR_HIGH(GPIOD_PIN8) | \ - PIN_ODR_HIGH(GPIOD_PIN9) | \ - PIN_ODR_HIGH(GPIOD_PIN10) | \ - PIN_ODR_HIGH(GPIOD_PIN11) | \ - PIN_ODR_LOW(GPIOD_LED4) | \ - PIN_ODR_LOW(GPIOD_LED3) | \ - PIN_ODR_LOW(GPIOD_LED5) | \ - PIN_ODR_LOW(GPIOD_LED6)) -#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOD_RESET, 0U) | \ - PIN_AFIO_AF(GPIOD_OVER_CURRENT, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN7, 0U)) -#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOD_LED4, 0U) | \ - PIN_AFIO_AF(GPIOD_LED3, 0U) | \ - PIN_AFIO_AF(GPIOD_LED5, 0U) | \ - PIN_AFIO_AF(GPIOD_LED6, 0U)) - -/* - * GPIOE setup: - * - * PE0 - INT1 (input floating). - * PE1 - INT2 (input floating). - * PE2 - PIN2 (input floating). - * PE3 - CS_SPI (output pushpull maximum). - * PE4 - PIN4 (input floating). - * PE5 - PIN5 (input floating). - * PE6 - PIN6 (input floating). - * PE7 - PIN7 (input floating). - * PE8 - PIN8 (input floating). - * PE9 - PIN9 (input floating). - * PE10 - PIN10 (input floating). - * PE11 - PIN11 (input floating). - * PE12 - PIN12 (input floating). - * PE13 - PIN13 (input floating). - * PE14 - PIN14 (input floating). - * PE15 - PIN15 (input floating). - */ -#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \ - PIN_MODE_INPUT(GPIOE_PIN1) | \ - PIN_MODE_INPUT(GPIOE_PIN2) | \ - PIN_MODE_INPUT(GPIOE_PIN3) | \ - PIN_MODE_INPUT(GPIOE_PIN4) | \ - PIN_MODE_INPUT(GPIOE_PIN5) | \ - PIN_MODE_INPUT(GPIOE_PIN6) | \ - PIN_MODE_INPUT(GPIOE_PIN7) | \ - PIN_MODE_INPUT(GPIOE_PIN8) | \ - PIN_MODE_INPUT(GPIOE_PIN9) | \ - PIN_MODE_INPUT(GPIOE_PIN10) | \ - PIN_MODE_INPUT(GPIOE_PIN11) | \ - PIN_MODE_INPUT(GPIOE_PIN12) | \ - PIN_MODE_INPUT(GPIOE_PIN13) | \ - PIN_MODE_INPUT(GPIOE_PIN14) | \ - PIN_MODE_INPUT(GPIOE_PIN15)) -#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) -#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \ - PIN_OSPEED_HIGH(GPIOE_PIN1) | \ - PIN_OSPEED_HIGH(GPIOE_PIN2) | \ - PIN_OSPEED_HIGH(GPIOE_PIN3) | \ - PIN_OSPEED_HIGH(GPIOE_PIN4) | \ - PIN_OSPEED_HIGH(GPIOE_PIN5) | \ - PIN_OSPEED_HIGH(GPIOE_PIN6) | \ - PIN_OSPEED_HIGH(GPIOE_PIN7) | \ - PIN_OSPEED_HIGH(GPIOE_PIN8) | \ - PIN_OSPEED_HIGH(GPIOE_PIN9) | \ - PIN_OSPEED_HIGH(GPIOE_PIN10) | \ - PIN_OSPEED_HIGH(GPIOE_PIN11) | \ - PIN_OSPEED_HIGH(GPIOE_PIN12) | \ - PIN_OSPEED_HIGH(GPIOE_PIN13) | \ - PIN_OSPEED_HIGH(GPIOE_PIN14) | \ - PIN_OSPEED_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN15)) -#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ - PIN_ODR_HIGH(GPIOE_PIN1) | \ - PIN_ODR_HIGH(GPIOE_PIN2) | \ - PIN_ODR_HIGH(GPIOE_PIN3) | \ - PIN_ODR_HIGH(GPIOE_PIN4) | \ - PIN_ODR_HIGH(GPIOE_PIN5) | \ - PIN_ODR_HIGH(GPIOE_PIN6) | \ - PIN_ODR_HIGH(GPIOE_PIN7) | \ - PIN_ODR_HIGH(GPIOE_PIN8) | \ - PIN_ODR_HIGH(GPIOE_PIN9) | \ - PIN_ODR_HIGH(GPIOE_PIN10) | \ - PIN_ODR_HIGH(GPIOE_PIN11) | \ - PIN_ODR_HIGH(GPIOE_PIN12) | \ - PIN_ODR_HIGH(GPIOE_PIN13) | \ - PIN_ODR_HIGH(GPIOE_PIN14) | \ - PIN_ODR_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN7, 0U)) -#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN15, 0U)) - -/* - * GPIOF setup: - * - * PF0 - PIN0 (input floating). - * PF1 - PIN1 (input floating). - * PF2 - PIN2 (input floating). - * PF3 - PIN3 (input floating). - * PF4 - PIN4 (input floating). - * PF5 - PIN5 (input floating). - * PF6 - PIN6 (input floating). - * PF7 - PIN7 (input floating). - * PF8 - PIN8 (input floating). - * PF9 - PIN9 (input floating). - * PF10 - PIN10 (input floating). - * PF11 - PIN11 (input floating). - * PF12 - PIN12 (input floating). - * PF13 - PIN13 (input floating). - * PF14 - PIN14 (input floating). - * PF15 - PIN15 (input floating). - */ -#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \ - PIN_MODE_INPUT(GPIOF_PIN1) | \ - PIN_MODE_INPUT(GPIOF_PIN2) | \ - PIN_MODE_INPUT(GPIOF_PIN3) | \ - PIN_MODE_INPUT(GPIOF_PIN4) | \ - PIN_MODE_INPUT(GPIOF_PIN5) | \ - PIN_MODE_INPUT(GPIOF_PIN6) | \ - PIN_MODE_INPUT(GPIOF_PIN7) | \ - PIN_MODE_INPUT(GPIOF_PIN8) | \ - PIN_MODE_INPUT(GPIOF_PIN9) | \ - PIN_MODE_INPUT(GPIOF_PIN10) | \ - PIN_MODE_INPUT(GPIOF_PIN11) | \ - PIN_MODE_INPUT(GPIOF_PIN12) | \ - PIN_MODE_INPUT(GPIOF_PIN13) | \ - PIN_MODE_INPUT(GPIOF_PIN14) | \ - PIN_MODE_INPUT(GPIOF_PIN15)) -#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) -#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_PIN0) | \ - PIN_OSPEED_HIGH(GPIOF_PIN1) | \ - PIN_OSPEED_HIGH(GPIOF_PIN2) | \ - PIN_OSPEED_HIGH(GPIOF_PIN3) | \ - PIN_OSPEED_HIGH(GPIOF_PIN4) | \ - PIN_OSPEED_HIGH(GPIOF_PIN5) | \ - PIN_OSPEED_HIGH(GPIOF_PIN6) | \ - PIN_OSPEED_HIGH(GPIOF_PIN7) | \ - PIN_OSPEED_HIGH(GPIOF_PIN8) | \ - PIN_OSPEED_HIGH(GPIOF_PIN9) | \ - PIN_OSPEED_HIGH(GPIOF_PIN10) | \ - PIN_OSPEED_HIGH(GPIOF_PIN11) | \ - PIN_OSPEED_HIGH(GPIOF_PIN12) | \ - PIN_OSPEED_HIGH(GPIOF_PIN13) | \ - PIN_OSPEED_HIGH(GPIOF_PIN14) | \ - PIN_OSPEED_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN15)) -#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \ - PIN_ODR_HIGH(GPIOF_PIN1) | \ - PIN_ODR_HIGH(GPIOF_PIN2) | \ - PIN_ODR_HIGH(GPIOF_PIN3) | \ - PIN_ODR_HIGH(GPIOF_PIN4) | \ - PIN_ODR_HIGH(GPIOF_PIN5) | \ - PIN_ODR_HIGH(GPIOF_PIN6) | \ - PIN_ODR_HIGH(GPIOF_PIN7) | \ - PIN_ODR_HIGH(GPIOF_PIN8) | \ - PIN_ODR_HIGH(GPIOF_PIN9) | \ - PIN_ODR_HIGH(GPIOF_PIN10) | \ - PIN_ODR_HIGH(GPIOF_PIN11) | \ - PIN_ODR_HIGH(GPIOF_PIN12) | \ - PIN_ODR_HIGH(GPIOF_PIN13) | \ - PIN_ODR_HIGH(GPIOF_PIN14) | \ - PIN_ODR_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN7, 0U)) -#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN15, 0U)) - -/* - * GPIOG setup: - * - * PG0 - PIN0 (input floating). - * PG1 - PIN1 (input floating). - * PG2 - PIN2 (input floating). - * PG3 - PIN3 (input floating). - * PG4 - PIN4 (input floating). - * PG5 - PIN5 (input floating). - * PG6 - PIN6 (input floating). - * PG7 - PIN7 (input floating). - * PG8 - PIN8 (input floating). - * PG9 - PIN9 (input floating). - * PG10 - PIN10 (input floating). - * PG11 - PIN11 (input floating). - * PG12 - PIN12 (input floating). - * PG13 - PIN13 (input floating). - * PG14 - PIN14 (input floating). - * PG15 - PIN15 (input floating). - */ -#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | \ - PIN_MODE_INPUT(GPIOG_PIN1) | \ - PIN_MODE_INPUT(GPIOG_PIN2) | \ - PIN_MODE_INPUT(GPIOG_PIN3) | \ - PIN_MODE_INPUT(GPIOG_PIN4) | \ - PIN_MODE_INPUT(GPIOG_PIN5) | \ - PIN_MODE_INPUT(GPIOG_PIN6) | \ - PIN_MODE_INPUT(GPIOG_PIN7) | \ - PIN_MODE_INPUT(GPIOG_PIN8) | \ - PIN_MODE_INPUT(GPIOG_PIN9) | \ - PIN_MODE_INPUT(GPIOG_PIN10) | \ - PIN_MODE_INPUT(GPIOG_PIN11) | \ - PIN_MODE_INPUT(GPIOG_PIN12) | \ - PIN_MODE_INPUT(GPIOG_PIN13) | \ - PIN_MODE_INPUT(GPIOG_PIN14) | \ - PIN_MODE_INPUT(GPIOG_PIN15)) -#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN15)) -#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_HIGH(GPIOG_PIN0) | \ - PIN_OSPEED_HIGH(GPIOG_PIN1) | \ - PIN_OSPEED_HIGH(GPIOG_PIN2) | \ - PIN_OSPEED_HIGH(GPIOG_PIN3) | \ - PIN_OSPEED_HIGH(GPIOG_PIN4) | \ - PIN_OSPEED_HIGH(GPIOG_PIN5) | \ - PIN_OSPEED_HIGH(GPIOG_PIN6) | \ - PIN_OSPEED_HIGH(GPIOG_PIN7) | \ - PIN_OSPEED_HIGH(GPIOG_PIN8) | \ - PIN_OSPEED_HIGH(GPIOG_PIN9) | \ - PIN_OSPEED_HIGH(GPIOG_PIN10) | \ - PIN_OSPEED_HIGH(GPIOG_PIN11) | \ - PIN_OSPEED_HIGH(GPIOG_PIN12) | \ - PIN_OSPEED_HIGH(GPIOG_PIN13) | \ - PIN_OSPEED_HIGH(GPIOG_PIN14) | \ - PIN_OSPEED_HIGH(GPIOG_PIN15)) -#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN15)) -#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \ - PIN_ODR_HIGH(GPIOG_PIN1) | \ - PIN_ODR_HIGH(GPIOG_PIN2) | \ - PIN_ODR_HIGH(GPIOG_PIN3) | \ - PIN_ODR_HIGH(GPIOG_PIN4) | \ - PIN_ODR_HIGH(GPIOG_PIN5) | \ - PIN_ODR_HIGH(GPIOG_PIN6) | \ - PIN_ODR_HIGH(GPIOG_PIN7) | \ - PIN_ODR_HIGH(GPIOG_PIN8) | \ - PIN_ODR_HIGH(GPIOG_PIN9) | \ - PIN_ODR_HIGH(GPIOG_PIN10) | \ - PIN_ODR_HIGH(GPIOG_PIN11) | \ - PIN_ODR_HIGH(GPIOG_PIN12) | \ - PIN_ODR_HIGH(GPIOG_PIN13) | \ - PIN_ODR_HIGH(GPIOG_PIN14) | \ - PIN_ODR_HIGH(GPIOG_PIN15)) -#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN7, 0U)) -#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN15, 0U)) - -/* - * GPIOH setup: - * - * PH0 - OSC_IN (input floating). - * PH1 - OSC_OUT (input floating). - * PH2 - PIN2 (input floating). - * PH3 - PIN3 (input floating). - * PH4 - PIN4 (input floating). - * PH5 - PIN5 (input floating). - * PH6 - PIN6 (input floating). - * PH7 - PIN7 (input floating). - * PH8 - PIN8 (input floating). - * PH9 - PIN9 (input floating). - * PH10 - PIN10 (input floating). - * PH11 - PIN11 (input floating). - * PH12 - PIN12 (input floating). - * PH13 - PIN13 (input floating). - * PH14 - PIN14 (input floating). - * PH15 - PIN15 (input floating). - */ -#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ - PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ - PIN_MODE_INPUT(GPIOH_PIN2) | \ - PIN_MODE_INPUT(GPIOH_PIN3) | \ - PIN_MODE_INPUT(GPIOH_PIN4) | \ - PIN_MODE_INPUT(GPIOH_PIN5) | \ - PIN_MODE_INPUT(GPIOH_PIN6) | \ - PIN_MODE_INPUT(GPIOH_PIN7) | \ - PIN_MODE_INPUT(GPIOH_PIN8) | \ - PIN_MODE_INPUT(GPIOH_PIN9) | \ - PIN_MODE_INPUT(GPIOH_PIN10) | \ - PIN_MODE_INPUT(GPIOH_PIN11) | \ - PIN_MODE_INPUT(GPIOH_PIN12) | \ - PIN_MODE_INPUT(GPIOH_PIN13) | \ - PIN_MODE_INPUT(GPIOH_PIN14) | \ - PIN_MODE_INPUT(GPIOH_PIN15)) -#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) -#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \ - PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \ - PIN_OSPEED_HIGH(GPIOH_PIN2) | \ - PIN_OSPEED_HIGH(GPIOH_PIN3) | \ - PIN_OSPEED_HIGH(GPIOH_PIN4) | \ - PIN_OSPEED_HIGH(GPIOH_PIN5) | \ - PIN_OSPEED_HIGH(GPIOH_PIN6) | \ - PIN_OSPEED_HIGH(GPIOH_PIN7) | \ - PIN_OSPEED_HIGH(GPIOH_PIN8) | \ - PIN_OSPEED_HIGH(GPIOH_PIN9) | \ - PIN_OSPEED_HIGH(GPIOH_PIN10) | \ - PIN_OSPEED_HIGH(GPIOH_PIN11) | \ - PIN_OSPEED_HIGH(GPIOH_PIN12) | \ - PIN_OSPEED_HIGH(GPIOH_PIN13) | \ - PIN_OSPEED_HIGH(GPIOH_PIN14) | \ - PIN_OSPEED_HIGH(GPIOH_PIN15)) -#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ - PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN15)) -#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ - PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ - PIN_ODR_HIGH(GPIOH_PIN2) | \ - PIN_ODR_HIGH(GPIOH_PIN3) | \ - PIN_ODR_HIGH(GPIOH_PIN4) | \ - PIN_ODR_HIGH(GPIOH_PIN5) | \ - PIN_ODR_HIGH(GPIOH_PIN6) | \ - PIN_ODR_HIGH(GPIOH_PIN7) | \ - PIN_ODR_HIGH(GPIOH_PIN8) | \ - PIN_ODR_HIGH(GPIOH_PIN9) | \ - PIN_ODR_HIGH(GPIOH_PIN10) | \ - PIN_ODR_HIGH(GPIOH_PIN11) | \ - PIN_ODR_HIGH(GPIOH_PIN12) | \ - PIN_ODR_HIGH(GPIOH_PIN13) | \ - PIN_ODR_HIGH(GPIOH_PIN14) | \ - PIN_ODR_HIGH(GPIOH_PIN15)) -#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \ - PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN7, 0U)) -#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN15, 0U)) - -/* - * GPIOI setup: - * - * PI0 - PIN0 (input floating). - * PI1 - PIN1 (input floating). - * PI2 - PIN2 (input floating). - * PI3 - PIN3 (input floating). - * PI4 - PIN4 (input floating). - * PI5 - PIN5 (input floating). - * PI6 - PIN6 (input floating). - * PI7 - PIN7 (input floating). - * PI8 - PIN8 (input floating). - * PI9 - PIN9 (input floating). - * PI10 - PIN10 (input floating). - * PI11 - PIN11 (input floating). - * PI12 - PIN12 (input floating). - * PI13 - PIN13 (input floating). - * PI14 - PIN14 (input floating). - * PI15 - PIN15 (input floating). - */ -#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \ - PIN_MODE_INPUT(GPIOI_PIN1) | \ - PIN_MODE_INPUT(GPIOI_PIN2) | \ - PIN_MODE_INPUT(GPIOI_PIN3) | \ - PIN_MODE_INPUT(GPIOI_PIN4) | \ - PIN_MODE_INPUT(GPIOI_PIN5) | \ - PIN_MODE_INPUT(GPIOI_PIN6) | \ - PIN_MODE_INPUT(GPIOI_PIN7) | \ - PIN_MODE_INPUT(GPIOI_PIN8) | \ - PIN_MODE_INPUT(GPIOI_PIN9) | \ - PIN_MODE_INPUT(GPIOI_PIN10) | \ - PIN_MODE_INPUT(GPIOI_PIN11) | \ - PIN_MODE_INPUT(GPIOI_PIN12) | \ - PIN_MODE_INPUT(GPIOI_PIN13) | \ - PIN_MODE_INPUT(GPIOI_PIN14) | \ - PIN_MODE_INPUT(GPIOI_PIN15)) -#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN15)) -#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_HIGH(GPIOI_PIN0) | \ - PIN_OSPEED_HIGH(GPIOI_PIN1) | \ - PIN_OSPEED_HIGH(GPIOI_PIN2) | \ - PIN_OSPEED_HIGH(GPIOI_PIN3) | \ - PIN_OSPEED_HIGH(GPIOI_PIN4) | \ - PIN_OSPEED_HIGH(GPIOI_PIN5) | \ - PIN_OSPEED_HIGH(GPIOI_PIN6) | \ - PIN_OSPEED_HIGH(GPIOI_PIN7) | \ - PIN_OSPEED_HIGH(GPIOI_PIN8) | \ - PIN_OSPEED_HIGH(GPIOI_PIN9) | \ - PIN_OSPEED_HIGH(GPIOI_PIN10) | \ - PIN_OSPEED_HIGH(GPIOI_PIN11) | \ - PIN_OSPEED_HIGH(GPIOI_PIN12) | \ - PIN_OSPEED_HIGH(GPIOI_PIN13) | \ - PIN_OSPEED_HIGH(GPIOI_PIN14) | \ - PIN_OSPEED_HIGH(GPIOI_PIN15)) -#define VAL_GPIOI_PUPDR (PIN_PUPDR_FLOATING(GPIOI_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN15)) -#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \ - PIN_ODR_HIGH(GPIOI_PIN1) | \ - PIN_ODR_HIGH(GPIOI_PIN2) | \ - PIN_ODR_HIGH(GPIOI_PIN3) | \ - PIN_ODR_HIGH(GPIOI_PIN4) | \ - PIN_ODR_HIGH(GPIOI_PIN5) | \ - PIN_ODR_HIGH(GPIOI_PIN6) | \ - PIN_ODR_HIGH(GPIOI_PIN7) | \ - PIN_ODR_HIGH(GPIOI_PIN8) | \ - PIN_ODR_HIGH(GPIOI_PIN9) | \ - PIN_ODR_HIGH(GPIOI_PIN10) | \ - PIN_ODR_HIGH(GPIOI_PIN11) | \ - PIN_ODR_HIGH(GPIOI_PIN12) | \ - PIN_ODR_HIGH(GPIOI_PIN13) | \ - PIN_ODR_HIGH(GPIOI_PIN14) | \ - PIN_ODR_HIGH(GPIOI_PIN15)) -#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN7, 0U)) -#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN15, 0U)) - - -#if !defined(_FROM_ASM_) -#ifdef __cplusplus -extern "C" { -#endif - void boardInit(void); -#ifdef __cplusplus -} -#endif -#endif /* _FROM_ASM_ */ - -#endif /* BOARD_H */ diff --git a/firmware/config/boards/ST_STM32F4_DISCOVERY/board.mk b/firmware/config/boards/ST_STM32F4_DISCOVERY/board.mk deleted file mode 100644 index 162ec1fc16..0000000000 --- a/firmware/config/boards/ST_STM32F4_DISCOVERY/board.mk +++ /dev/null @@ -1,5 +0,0 @@ -# List of all the board related files. -BOARDSRC = $(PROJECT_DIR)/config/boards/ST_STM32F4_DISCOVERY/board.c - -# Required include directories -BOARDINC = $(PROJECT_DIR)/config/boards/ST_STM32F4_DISCOVERY From 0eccf66dba6a70861a146425cb9d346cf21762fa Mon Sep 17 00:00:00 2001 From: rusefi Date: Wed, 29 Mar 2017 20:26:23 -0400 Subject: [PATCH 29/74] smaller snapshot --- firmware/ChibiOS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/firmware/ChibiOS b/firmware/ChibiOS index 820840273b..ef5d8b77ac 160000 --- a/firmware/ChibiOS +++ b/firmware/ChibiOS @@ -1 +1 @@ -Subproject commit 820840273b7f870dae339c53d9ad8a5591cdd061 +Subproject commit ef5d8b77ac35f8a0ec584b16e5dcad32b451315f From e7f1d0a0bbf0a8041cfbb4f8f4349931de191f4f Mon Sep 17 00:00:00 2001 From: rusefi Date: Wed, 29 Mar 2017 20:51:30 -0400 Subject: [PATCH 30/74] explicit defines --- .../simulator/efifeatures.h | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/win32_functional_tests/simulator/efifeatures.h b/win32_functional_tests/simulator/efifeatures.h index c2ab0950e0..5e6bc3e6ab 100644 --- a/win32_functional_tests/simulator/efifeatures.h +++ b/win32_functional_tests/simulator/efifeatures.h @@ -24,6 +24,7 @@ #define EFI_PROD_CODE FALSE #define EFI_MAP_AVERAGING TRUE +#define EFI_ALTERNATOR_CONTROL FALSE #define EFI_SUPPORT_DODGE_NEON TRUE #define EFI_SUPPORT_FORD_ASPIRE TRUE @@ -31,6 +32,9 @@ #define EFI_SUPPORT_NISSAN_PRIMERA TRUE #define EFI_SUPPORT_1995_FORD_INLINE_6 TRUE +#define EFI_ENGINE_AUDI_AAN FALSE +#define EFI_ENGINE_SNOW_BLOWER FALSE + /** * simulator works via self-stimulation which works via trigger emulation */ @@ -42,10 +46,30 @@ #define EFI_SHAFT_POSITION_INPUT TRUE #define EFI_ENGINE_CONTROL TRUE +#define EFI_IDLE_CONTROL FALSE +#define EFI_HIP_9011 FALSE +#define EFI_ELECTRONIC_THROTTLE_BODY FALSE +#define EFI_AUX_PID FALSE +#define EFI_DEFAILED_LOGGING FALSE #define EFI_ENGINE_SNIFFER TRUE +#define FUEL_MATH_EXTREME_LOGGING FALSE #define EFI_ANALOG_SENSORS TRUE +#define EFI_INTERNAL_FLASH FALSE +#define EFI_RTC FALSE +#define EFI_MALFUNCTION_INDICATOR FALSE +#define EFI_HD44780_LCD FALSE +#define EFI_WAVE_ANALYZER FALSE +#define EFI_PWM_TESTER FALSE +#define TRIGGER_EXTREME_LOGGING FALSE +#define SPARK_EXTREME_LOGGING FALSE +#define DEBUG_PWM FALSE +#define EFI_SIGNAL_EXECUTOR_ONE_TIMER FALSE +#define EFI_TUNER_STUDIO_VERBOSE FALSE +#define EFI_FILE_LOGGING FALSE +#define EFI_WARNING_LED FALSE +#define EFI_VEHICLE_SPEED FALSE #define EFI_SENSOR_CHART TRUE #define EFI_HISTOGRAMS FALSE From 947633b0c0407618ec6d64eebd6833a53a526b62 Mon Sep 17 00:00:00 2001 From: rusefi Date: Wed, 29 Mar 2017 20:52:03 -0400 Subject: [PATCH 31/74] progress with Eclipse --- firmware/rusefi.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/firmware/rusefi.cpp b/firmware/rusefi.cpp index 913222b023..1e7dcc0916 100644 --- a/firmware/rusefi.cpp +++ b/firmware/rusefi.cpp @@ -241,7 +241,7 @@ void chDbgStackOverflowPanic(thread_t *otp) { chDbgPanic3(panicMessage, __FILE__, __LINE__); } -static char UNUSED_RAM_SIZE[21100]; +static char UNUSED_RAM_SIZE[20100]; static char UNUSED_CCM_SIZE[9500] CCM_OPTIONAL; From 53794424e19fe25311597f8685b7b4a686938222 Mon Sep 17 00:00:00 2001 From: rusefi Date: Wed, 29 Mar 2017 20:55:20 -0400 Subject: [PATCH 32/74] progress --- win32_functional_tests/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/win32_functional_tests/Makefile b/win32_functional_tests/Makefile index 89b611ccae..e246cfca6e 100644 --- a/win32_functional_tests/Makefile +++ b/win32_functional_tests/Makefile @@ -6,9 +6,9 @@ # Compiler options here. ifeq ($(USE_OPT),) # this config if debugging is needed, but the binary is about 50M -# USE_OPT = -c -Wall -O0 -ggdb -g3 -Werror-implicit-function-declaration -Werror -Wno-error=pointer-sign -Wno-error=unused-function -Wno-error=unused-variable -Wno-error=sign-compare -Wno-error=unused-parameter -Wno-error=missing-field-initializers -Wno-error=write-strings +# USE_OPT = -Wall -O0 -ggdb -g3 -Werror-implicit-function-declaration -Werror -Wno-error=pointer-sign -Wno-error=unused-function -Wno-error=unused-variable -Wno-error=sign-compare -Wno-error=unused-parameter -Wno-error=missing-field-initializers -Wno-error=write-strings # this config producec a smaller binary file - USE_OPT = -c -Wall -O2 -Werror-implicit-function-declaration -Wno-error=pointer-sign -Wno-error=unused-function -Wno-error=unused-variable -Wno-error=sign-compare -Wno-error=unused-parameter -Wno-error=missing-field-initializers -Wno-error=write-strings -Wno-error=strict-aliasing + USE_OPT = -Wall -O2 -Werror-implicit-function-declaration -Wno-error=pointer-sign -Wno-error=unused-function -Wno-error=unused-variable -Wno-error=sign-compare -Wno-error=unused-parameter -Wno-error=missing-field-initializers -Wno-error=write-strings -Wno-error=strict-aliasing ifeq ($(OS),Windows_NT) else From ea4c5ef21c03475fd75372f51e65e6e266700fb0 Mon Sep 17 00:00:00 2001 From: rusefi Date: Wed, 29 Mar 2017 21:07:26 -0400 Subject: [PATCH 33/74] minor linking fix --- firmware/util/efilib.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/firmware/util/efilib.h b/firmware/util/efilib.h index fc201d7456..8f430e235b 100644 --- a/firmware/util/efilib.h +++ b/firmware/util/efilib.h @@ -30,13 +30,13 @@ #define ERROR_CODE 311223344 -const char * boolToString(bool value); - #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ +const char * boolToString(bool value); + char * efiTrim(char *param); uint32_t efiStrlen(const char *param); int efiPow10(int param); From b0cd4a42320e350d3024469c1bb235a8179580d9 Mon Sep 17 00:00:00 2001 From: rusefi Date: Wed, 29 Mar 2017 21:09:04 -0400 Subject: [PATCH 34/74] eclipse project progress --- firmware/.cproject | 117 ++++++++++++++++++++++++++++----------------- 1 file changed, 73 insertions(+), 44 deletions(-) diff --git a/firmware/.cproject b/firmware/.cproject index 1a275983bc..a91aafcf8f 100644 --- a/firmware/.cproject +++ b/firmware/.cproject @@ -47,16 +47,19 @@